diff --git a/bsv/eth/CRT.bsv b/bsv/eth/CRT.bsv new file mode 100644 index 00000000..00324b0a --- /dev/null +++ b/bsv/eth/CRT.bsv @@ -0,0 +1,184 @@ +// CRT.bsv - Command-Response Transaction (CRT) +// Copyright (c) 2012,2013 Atomic Rules LLC - ALL RIGHTS RESERVED + +import ARAXI4L ::*; + +import ClientServer ::*; +import Clocks ::*; +import Connectable ::*; +import FIFO ::*; +import GetPut ::*; +import Vector ::*; + +typedef enum { + NOP = 4'h0, + Write = 4'h1, + Read = 4'h2, + Response = 4'h3 +} CRTMesgType deriving (Bits, Eq); + +typedef enum { + OK = 4'h0, + Timeout = 4'h1, + Error = 4'h2, + RSVD = 4'hF +} CRTRespCode deriving (Bits, Eq); + +typedef struct { + Bool isLast; + Bit#(2) rsvd28; + UInt#(12) adl; + Bit#(8) rsvd8; + Bit#(1) rsvd7; + Bool isDO; + CRTMesgType mesgt; + Bit#(4) tag; +} CRHNOP deriving (Bits, Eq); + +typedef struct { + Bool isLast; + Bit#(2) rsvd28; + UInt#(12) adl; + Bit#(4) lastBE; + Bit#(4) firtBE; + Bit#(1) rsvd7; + Bool isDO; + CRTMesgType mesgt; + Bit#(4) tag; +} CRHWrite deriving (Bits, Eq); + +typedef struct { + Bool isLast; + Bit#(2) rsvd28; + UInt#(12) adl; + Bit#(4) lastBE; + Bit#(4) firtBE; + Bit#(1) rsvd7; + Bool isDO; + CRTMesgType mesgt; + Bit#(4) tag; +} CRHRead deriving (Bits, Eq); + +typedef struct { + Bool isLast; + Bit#(2) rsvd28; + UInt#(12) adl; + Bit#(4) rsvd12; + CRTRespCode mesgt; + Bit#(1) rsvd7; + Bool isDO; + CRTMesgType mesgt; + Bit#(4) tag; +} CRHResp deriving (Bits, Eq); + +typedef union tagged { + CRHNOP NOP; + CRHWrite Write; + CRHRead Read; + CRHResp Response; + void Invalid; +} TagCRH deriving (Bits, Eq); + +interface CRTServToA4LMIfc; + interface Server#(CRTDW,CRTDW) crtS0; + interface A4LMIfx axiM0 +endinterface + +module mkCRTServToA4LM (CRTServToA4LM); + + Integer respBufSize = 64; + + // CRT Command/Response FIFOs... + FIFO#(Bit#(32)) crtCmdF <- mkFIFO; // Inbound CRT Commands + FIFO#(Bit#(32)) crtRespF <- mkFIFO; // Outbound CRT Responses + // The internal state of the CRT module... + Reg#(TagCRH) thisCRH <- mkReg(tagged Invalid); + Reg#(Bool) isCmdCRH <- mkReg(True); + Reg#(Bool) fault <- mkReg(False); + Reg#(Bool) doInFlight <- mkReg(False); // True when a Discovery Operation (DO) is in flight + Reg#(Maybe#(Bit#(8))) lastTag <- mkReg(tagged Invalid); // The last tag captured (valid or not) + UInt#(12) adlRemain <- mkReg(0); + UInt#(12) adlLastResp <- mkReg(0); + FIFO#(Bit#(32)) respBuffer <- mkSizedFIFO(respBufSize/4); + + Bit#(32) targAdvert = respBufSize; + + rule crt_cmd_ingress; + let x = crtCmdF.first; crtCmdF.deq; + if (isCmdCRH) + CRTMesgType cmt = unpack(x[5:4]); + case (cmt) + NOP: thisCRH <= tagged NOP unpack(x); + Write: thisCRH <= tagged Write unpack(x); + Read: thisCRH <= tagged Read unpack(x); + Response: fault <= True; + endcase + end + endrule + +/* + case (x) matches + tagged NOP .n: begin + crtRespF.enq(tagged NOP( CRTResponseNOP{hasDO:n.isDO, targAdvert:targAdvert, tag:n.tag, code:RESP_OK})); // Respond to the NOP + if (!n.isDO) lastTag <= (tagged Invalid); // NOPs Invalidate the lastTag so next command is always accepted + if ( n.isDO) doInFlight <= True; + end + tagged Write .w: begin + if ((isValid(lastTag) && w.tag!=fromMaybe(?,lastTag)) || !isValid(lastTag) || w.isDO) begin // if the lastTag is Valid and the tags dont match OR if the lastTag is Invalid OR a Discovery Op + cpReqF.enq(tagged WriteRequest( CpWriteReq{dwAddr:truncate(w.addr>>2), byteEn:w.be, data:w.data})); // Issue the Write + if (!w.isDO) lastTag <= (tagged Valid w.tag); // Capture the tag into lastTag + if ( w.isDO) doInFlight <= True; + end + crtRespF.enq(tagged Write( CRTResponseWrite{hasDO:w.isDO, tag:w.tag, code:RESP_OK})); // Blind ACK the Write regardless if tag match or not + //TODO: When CP write responses are non-blind (from non-posted requests), make write machine use lastResp like Read + end + tagged Read .r: begin + if ((isValid(lastTag) && r.tag!=fromMaybe(?,lastTag)) || !isValid(lastTag) || r.isDO) begin // if the lastTag is Valid and the tags dont match OR if the lastTag is Invalid OR a Discovery Op + cpReqF.enq(tagged ReadRequest( CpReadReq {dwAddr:truncate(r.addr>>2), byteEn:r.be, tag:r.tag})); // Issue the Read + if (!r.isDO) lastTag <= (tagged Valid r.tag); // Capture the tag into lastTag + if ( r.isDO) doInFlight <= True; + end else crtRespF.enq(lastResp); // Retransmit the lastResp since tags match + end + endcase + endrule + + */ + + /* + rule cp_response; + let y = cpRespF.first; cpRespF.deq; + CRTResponse crtr = (tagged Read( CRTResponseRead{hasDO:doInFlight, data:y.data, tag:y.tag, code:RESP_OK})); + crtRespF.enq(crtr); // Advance the CP Read response + if (!doInFlight) lastResp <= crtr; // Save crtr in lastResponse for possible re-transmission + doInFlight <= False; + endrule + */ + + interface Server server; // Facing the CRT Packet Side + interface request = toPut(crtCmdF); + interface response = toGet(crtRespF); + endinterface + interface A4LMIfc axiM0 = a4l.a4lm; +endmodule + +/* +// This is an easy (lazy) way of doing an asyc CP-side client interface... +// We simply take the lean sync implementation as-is; and attach two async FIFOs to +// the CP-facing side so they can be in their own clock domain. + +module mkCRTAdapterAsync#(Clock cpClock, Reset cpReset) (CRTAdapterIfc); + CRTAdapterIfc crt <- mkCRTAdapterSync; + SyncFIFOIfc#(CpReq) cpReqAF <- mkSyncFIFOFromCC(4, cpClock); + SyncFIFOIfc#(CpReadResp) cpRespAF <- mkSyncFIFOToCC( 4, cpClock, cpReset); + + mkConnection(crt.client.request, toPut(cpReqAF)); + mkConnection(toGet(cpRespAF), crt.client.response); + + interface Server server = crt.server; // Facing the Ethernet L2 directly + + interface Client client; // Facing the Control Plane through Async FIFOs + interface request = toGet(cpReqAF); + interface response = toPut(cpRespAF); + endinterface +endmodule +*/ diff --git a/bsv/inf/CPDefs.bsv b/bsv/inf/CPDefs.bsv index 81c574e0..b2a8a738 100644 --- a/bsv/inf/CPDefs.bsv +++ b/bsv/inf/CPDefs.bsv @@ -1,5 +1,5 @@ -// CPDefs.bsv -the data structures used byu OCCP -// Copyright (c) 2009-2012 Atomic Rules LLC - ALL RIGHTS RESERVED +// CPDefs.bsv -the data structures used by OCCP +// Copyright (c) 2009-2013 Atomic Rules LLC - ALL RIGHTS RESERVED package CPDefs; diff --git a/bsv/inf/TLPSerializer.bsv b/bsv/inf/TLPSerializer.bsv index 9624ae71..dffecb8d 100644 --- a/bsv/inf/TLPSerializer.bsv +++ b/bsv/inf/TLPSerializer.bsv @@ -28,6 +28,7 @@ typedef enum {Idle,RdPush,RdFinal} RdStage deriving (Bits, Eq); // For Reads: Use the firstBE condition for the first DW, then make dwLength DW requests // up until the last, where lastBE is used +(* synthesize *) module mkTLPSerializer#(PciId pciDevice) (TLPSerializerIfc); FIFO#(PTW16) inF <- mkFIFO; // inbound TLPs diff --git a/bsv/utl/CompileTime.bsv b/bsv/utl/CompileTime.bsv index c15f3329..441c6c70 100644 --- a/bsv/utl/CompileTime.bsv +++ b/bsv/utl/CompileTime.bsv @@ -1 +1,5 @@ +<<<<<<< HEAD Bit#(32) compileTime = 1379207501; // Verilog Sat Sep 14 21:11:41 EDT 2013 +======= +Bit#(32) compileTime = 1371848185; // Verilog Fri Jun 21 16:56:25 EDT 2013 +>>>>>>> 652a840fab4fae234140a80489c4f89c78f9245c diff --git a/bsv/wip/OCWci.bsv b/bsv/wip/OCWci.bsv index c0ac4a2d..871071ee 100644 --- a/bsv/wip/OCWci.bsv +++ b/bsv/wip/OCWci.bsv @@ -5,6 +5,8 @@ // It should contain the WCI higher-level attributes; not the protocol-specific bits // It will typically be imported by the protocol-specific packages for its common WCI abstraction +//TODO MAddrSpace and SThreadbusy need to be vectors Check all profiles + package OCWci; import OCWipDefs::*; @@ -552,6 +554,8 @@ interface WciMasterIfc#(numeric type nda, numeric type na); interface Wci_m#(na) mas; endinterface +// TODO: See Jim Email about two databus read codes for conrtol op + module mkWciMaster (WciMasterIfc#(nda,na)) provisos ( Add#(a_,5,nda), // Insist that there are at least 5 address bits in nda to allow control ops Add#(b_,nda,32), // Compiler suggestion diff --git a/bsv/wrk/WSIPatternWorker.bsv b/bsv/wrk/WSIPatternWorker.bsv index 765872f1..cdf2428d 100644 --- a/bsv/wrk/WSIPatternWorker.bsv +++ b/bsv/wrk/WSIPatternWorker.bsv @@ -182,7 +182,8 @@ endfunction let dReq = BRAMRequest { write:False, address:truncate(dataPtr), datain:0, responseOnWrite:False }; dataBramsA[i].request.put(dReq); end - dataPtr <= (bytesRemain==4 && !noRecycleData) ? 0 : dataPtr + 1; + //dataPtr <= (bytesRemain==4 && !noRecycleData) ? 0 : dataPtr + 1; // Original, bug, fails to wrap + dataPtr <= (bytesRemain<=4 && !noRecycleData) ? 0 : dataPtr + 1; // and Suggested Fix bytesRemain <= (bytesRemain<4) ? 0 : bytesRemain - 4; endrule diff --git a/logs/ml605-20130127_1122/fpgaTop-ml605.srp b/logs/ml605-20130127_1122/fpgaTop-ml605.srp new file mode 100644 index 00000000..51b20ce2 --- /dev/null +++ b/logs/ml605-20130127_1122/fpgaTop-ml605.srp @@ -0,0 +1,13814 @@ +Release 14.4 - xst P.49d (lin64) +Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. +--> +Parameter xsthdpini set to ocpihdp_v6.ini + + +Total REAL time to Xst completion: 0.00 secs +Total CPU time to Xst completion: 0.04 secs + +--> + +TABLE OF CONTENTS + 1) Synthesis Options Summary + 2) HDL Parsing + 3) HDL Elaboration + 4) HDL Synthesis + 4.1) HDL Synthesis Report + 5) Advanced HDL Synthesis + 5.1) Advanced HDL Synthesis Report + 6) Low Level Synthesis + 7) Partition Report + 8) Design Summary + 8.1) Primitive and Black Box Usage + 8.2) Device utilization summary + 8.3) Partition Resource Summary + 8.4) Timing Report + 8.4.1) Clock Information + 8.4.2) Asynchronous Control Signals Information + 8.4.3) Timing Summary + 8.4.4) Timing Details + 8.4.5) Cross Clock Domains Report + + +========================================================================= +* Synthesis Options Summary * +========================================================================= +---- Source Parameters +Input File Name : "fpgaTop-ml605.prj" +Input Format : mixed + +---- Target Parameters +Output File Name : "fpgaTop" +Output Format : NGC +Target Device : xc6vlx240t-ff1156-1 + +---- Source Options +Top Module Name : fpgaTop +Automatic FSM Extraction : YES +FSM Encoding Algorithm : Auto +Safe Implementation : No +FSM Style : lut +RAM Extraction : Yes +RAM Style : Auto +ROM Extraction : Yes +Shift Register Extraction : YES +ROM Style : Auto +Resource Sharing : YES +Asynchronous To Synchronous : NO +Use DSP Block : auto +Automatic Register Balancing : NO + +---- Target Options +LUT Combining : off +Reduce Control Sets : off +Add IO Buffers : YES +Global Maximum Fanout : 100000 +Add Generic Clock Buffer(BUFG) : 32 +Register Duplication : YES +Optimize Instantiated Primitives : NO +Use Clock Enable : Auto +Use Synchronous Set : Auto +Use Synchronous Reset : Auto +Pack IO Registers into IOBs : auto +Equivalent register Removal : YES + +---- General Options +Optimization Goal : Speed +Optimization Effort : 2 +Power Reduction : NO +Library Search Order : fpgaTop.lso +Keep Hierarchy : soft +Netlist Hierarchy : rebuilt +RTL Output : Yes +Global Optimization : AllClockNets +Read Cores : optimize +Write Timing Constraints : NO +Cross Clock Analysis : NO +Hierarchy Separator : / +Bus Delimiter : <> +Case Specifier : maintain +Slice Utilization Ratio : 100 +BRAM Utilization Ratio : 100 +DSP48 Utilization Ratio : 100 +Auto BRAM Packing : NO +Slice Utilization Ratio Delta : 5 + +---- Other Options +change_error_to_warning : "HDLCompiler:532 HDLCompiler:597" + +========================================================================= + +INFO:Xst - Changing 'HDLCompiler:532' to warning +INFO:Xst - Changing 'HDLCompiler:597' to warning + +========================================================================= +* HDL Parsing * +========================================================================= +The vhdl library search path for library \"bsv\" is now \"/home/shep/projects/ocpi/lib/hdl/bsv/bsv_v6\" +The veri library search path for library \"bsv\" is now \"/home/shep/projects/ocpi/lib/hdl/bsv/bsv_v6\" +Analyzing Verilog file "/home/shep/projects/ocpi/libsrc/hdl/ocpi/ClockInvToBool.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/libsrc/hdl/ocpi/arSRLFIFO.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/libsrc/hdl/ocpi/arSRLFIFOD.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/libsrc/hdl/ocpi/Ethernet_v6_v1_5.v" into library work +Parsing module . +Parsing module . +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_upconfig_fix_3451_v6.v" into library work +Parsing module . +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_upconfig_fix_3451_v6.v" Line 85. parameter declaration becomes local in pcie_upconfig_fix_3451_v6 with formal parameter declaration list +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_reset_delay_v6.v" into library work +Parsing module . +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_reset_delay_v6.v" Line 76. parameter declaration becomes local in pcie_reset_delay_v6 with formal parameter declaration list +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_brams_v6.v" into library work +Parsing module . +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_brams_v6.v" Line 120. parameter declaration becomes local in pcie_brams_v6 with formal parameter declaration list +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_clocking_v6.v" into library work +Parsing module . +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_clocking_v6.v" Line 86. parameter declaration becomes local in pcie_clocking_v6 with formal parameter declaration list +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_gtx_v6.v" into library work +Parsing module . +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_gtx_v6.v" Line 216. parameter declaration becomes local in pcie_gtx_v6 with formal parameter declaration list +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_pipe_v6.v" into library work +Parsing module . +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_pipe_v6.v" Line 325. parameter declaration becomes local in pcie_pipe_v6 with formal parameter declaration list +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_pipe_lane_v6.v" into library work +Parsing module . +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_pipe_lane_v6.v" Line 103. parameter declaration becomes local in pcie_pipe_lane_v6 with formal parameter declaration list +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_pipe_misc_v6.v" into library work +Parsing module . +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_pipe_misc_v6.v" Line 90. parameter declaration becomes local in pcie_pipe_misc_v6 with formal parameter declaration list +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_2_0_v6.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_bram_v6.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_bram_top_v6.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_rx_valid_filter_v6.v" into library work +Parsing module . +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_rx_valid_filter_v6.v" Line 85. parameter declaration becomes local in GTX_RX_VALID_FILTER_V6 with formal parameter declaration list +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_rx_valid_filter_v6.v" Line 87. parameter declaration becomes local in GTX_RX_VALID_FILTER_V6 with formal parameter declaration list +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_rx_valid_filter_v6.v" Line 88. parameter declaration becomes local in GTX_RX_VALID_FILTER_V6 with formal parameter declaration list +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_rx_valid_filter_v6.v" Line 89. parameter declaration becomes local in GTX_RX_VALID_FILTER_V6 with formal parameter declaration list +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_rx_valid_filter_v6.v" Line 90. parameter declaration becomes local in GTX_RX_VALID_FILTER_V6 with formal parameter declaration list +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_rx_valid_filter_v6.v" Line 91. parameter declaration becomes local in GTX_RX_VALID_FILTER_V6 with formal parameter declaration list +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_rx_valid_filter_v6.v" Line 93. parameter declaration becomes local in GTX_RX_VALID_FILTER_V6 with formal parameter declaration list +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_rx_valid_filter_v6.v" Line 94. parameter declaration becomes local in GTX_RX_VALID_FILTER_V6 with formal parameter declaration list +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_rx_valid_filter_v6.v" Line 95. parameter declaration becomes local in GTX_RX_VALID_FILTER_V6 with formal parameter declaration list +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_rx_valid_filter_v6.v" Line 96. parameter declaration becomes local in GTX_RX_VALID_FILTER_V6 with formal parameter declaration list +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_rx_valid_filter_v6.v" Line 107. parameter declaration becomes local in GTX_RX_VALID_FILTER_V6 with formal parameter declaration list +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_rx_valid_filter_v6.v" Line 108. parameter declaration becomes local in GTX_RX_VALID_FILTER_V6 with formal parameter declaration list +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_rx_valid_filter_v6.v" Line 109. parameter declaration becomes local in GTX_RX_VALID_FILTER_V6 with formal parameter declaration list +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_rx_valid_filter_v6.v" Line 110. parameter declaration becomes local in GTX_RX_VALID_FILTER_V6 with formal parameter declaration list +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_drp_chanalign_fix_3752_v6.v" into library work +Parsing module . +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_drp_chanalign_fix_3752_v6.v" Line 90. parameter declaration becomes local in GTX_DRP_CHANALIGN_FIX_3752_V6 with formal parameter declaration list +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_drp_chanalign_fix_3752_v6.v" Line 91. parameter declaration becomes local in GTX_DRP_CHANALIGN_FIX_3752_V6 with formal parameter declaration list +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_drp_chanalign_fix_3752_v6.v" Line 92. parameter declaration becomes local in GTX_DRP_CHANALIGN_FIX_3752_V6 with formal parameter declaration list +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_drp_chanalign_fix_3752_v6.v" Line 93. parameter declaration becomes local in GTX_DRP_CHANALIGN_FIX_3752_V6 with formal parameter declaration list +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_drp_chanalign_fix_3752_v6.v" Line 94. parameter declaration becomes local in GTX_DRP_CHANALIGN_FIX_3752_V6 with formal parameter declaration list +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_drp_chanalign_fix_3752_v6.v" Line 95. parameter declaration becomes local in GTX_DRP_CHANALIGN_FIX_3752_V6 with formal parameter declaration list +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_drp_chanalign_fix_3752_v6.v" Line 96. parameter declaration becomes local in GTX_DRP_CHANALIGN_FIX_3752_V6 with formal parameter declaration list +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_drp_chanalign_fix_3752_v6.v" Line 97. parameter declaration becomes local in GTX_DRP_CHANALIGN_FIX_3752_V6 with formal parameter declaration list +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_drp_chanalign_fix_3752_v6.v" Line 98. parameter declaration becomes local in GTX_DRP_CHANALIGN_FIX_3752_V6 with formal parameter declaration list +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_drp_chanalign_fix_3752_v6.v" Line 99. parameter declaration becomes local in GTX_DRP_CHANALIGN_FIX_3752_V6 with formal parameter declaration list +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_drp_chanalign_fix_3752_v6.v" Line 100. parameter declaration becomes local in GTX_DRP_CHANALIGN_FIX_3752_V6 with formal parameter declaration list +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_tx_sync_rate_v6.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/libsrc/hdl/ocpi/xilinx_v6_pcie_wrapper.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkSMAdapter4B.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/libsrc/hdl/ocpi/duc_ddc_compiler_v1_0.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkDDCWorker.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkDelayWorker4B.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkDelayWorker16B.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/libsrc/hdl/ocpi/xfft_v7_1.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkPSD.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkBiasWorker4B.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkTimeClient.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkCRC32.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkGMAC.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkICAPWorker.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/arb_mux.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/arb_row_col.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/arb_select.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_cntrl.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_common.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_compare.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_mach.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_queue.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_state.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/col_mach.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/mc.v" into library work +Parsing module . +INFO:HDLCompiler:693 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/mc.v" Line 200. parameter declaration becomes local in mc with formal parameter declaration list +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/rank_cntrl.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/rank_common.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/rank_mach.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/round_robin_arb.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ecc/ecc_buf.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ecc/ecc_dec_fix.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ecc/ecc_gen.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ecc/ecc_merge_enc.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ip_top/clk_ibuf.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ip_top/ddr2_ddr3_chipscope.v" into library work +Parsing module . +Parsing module . +Parsing module . +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ip_top/infrastructure.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ip_top/memc_ui_top.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ip_top/mem_intfc.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/circ_buffer.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_ck_iob.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_clock_io.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_control_io.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_dly_ctrl.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_dm_iob.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_dq_iob.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_dqs_iob.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_init.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_pd_top.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_pd.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdclk_gen.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdctrl_sync.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rddata_sync.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_read.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_top.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_write.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_wrlvl.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/rd_bitslip.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ui/ui_cmd.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ui/ui_rd_data.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ui/ui_top.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ui/ui_wr_data.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/iodelay_ctrl_eco20100428.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/coregen/dram_v6_mig37/v6_mig37_patch20110411.v" into library work +Parsing module . +WARNING:HDLCompiler:751 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/v6_mig37_patch20110411.v" Line 271: Redeclaration of ansi port app_addr is not allowed +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkTLPSM.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkTLPCM.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkPktFork.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkPktMerge.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkUUID.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkOCCP.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkOCDP4B.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkOCInf4B.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkOCInf16B.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkOCApp4B.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkCTop4B.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkCTop16B.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkWciMonitor.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkFMC150.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkLCDController.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" into library work +Parsing module . +Analyzing Verilog file "/home/shep/projects/ocpi/libsrc/hdl/ocpi/fpgaTop_ml605.v" into library work +Parsing module . + +========================================================================= +* HDL Elaboration * +========================================================================= +WARNING:HDLCompiler:1016 - "/home/shep/projects/ocpi/libsrc/hdl/ocpi/fpgaTop_ml605.v" Line 102: Port flash_wp_n is not connected to this instance + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1434: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1466: Assignment to wci_wslv_wciReq$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1467: Assignment to wci_wslv_respF_x_wire$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1474: Assignment to wci_wslv_wEdge$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1475: Assignment to wci_wslv_wEdge$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1476: Assignment to wci_wslv_sFlagReg_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1477: Assignment to wci_wslv_sFlagReg_1$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1478: Assignment to wci_wslv_ctlAckReg_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1482: Assignment to wci_wci_Es_mCmd_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1483: Assignment to wci_wci_Es_mCmd_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1484: Assignment to wci_wci_Es_mAddrSpace_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1485: Assignment to wci_wci_Es_mAddrSpace_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1486: Assignment to wci_wci_Es_mByteEn_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1487: Assignment to wci_wci_Es_mByteEn_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1488: Assignment to wci_wci_Es_mAddr_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1489: Assignment to wci_wci_Es_mAddr_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1490: Assignment to wci_wci_Es_mData_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1491: Assignment to wci_wci_Es_mData_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1500: Assignment to wsiS_wsiReq$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1501: Assignment to wsiS_operateD_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1502: Assignment to wsiS_operateD_1$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1503: Assignment to wsiS_peerIsReady_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1504: Assignment to wsiS_peerIsReady_1$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1508: Assignment to wtiS_wtiReq$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1509: Assignment to wtiS_wtiReq$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1510: Assignment to wtiS_operateD_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1511: Assignment to wtiS_operateD_1$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1513: Assignment to nowW$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1514: Assignment to statusReg_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1515: Assignment to statusReg_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1516: Assignment to dataBram_0_serverAdapterA_outData_enqData$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1523: Assignment to dataBram_0_serverAdapterA_outData_outData$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1527: Assignment to dataBram_0_serverAdapterA_outData_outData$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1531: Assignment to dataBram_0_serverAdapterA_cnt_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1532: Assignment to dataBram_0_serverAdapterA_cnt_1$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1533: Assignment to dataBram_0_serverAdapterA_cnt_2$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1534: Assignment to dataBram_0_serverAdapterA_cnt_2$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1535: Assignment to dataBram_0_serverAdapterA_cnt_3$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1536: Assignment to dataBram_0_serverAdapterA_cnt_3$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1537: Assignment to dataBram_0_serverAdapterA_writeWithResp$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1538: Assignment to dataBram_0_serverAdapterA_writeWithResp$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1540: Assignment to dataBram_0_serverAdapterA_s1_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1541: Assignment to dataBram_0_serverAdapterA_s1_1$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1542: Assignment to dataBram_0_serverAdapterB_outData_enqData$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1549: Assignment to dataBram_0_serverAdapterB_outData_outData$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1554: Assignment to dataBram_0_serverAdapterB_cnt_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1555: Assignment to dataBram_0_serverAdapterB_cnt_1$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1557: Assignment to dataBram_0_serverAdapterB_cnt_2$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1558: Assignment to dataBram_0_serverAdapterB_cnt_2$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1560: Assignment to dataBram_0_serverAdapterB_cnt_3$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1561: Assignment to dataBram_0_serverAdapterB_cnt_3$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1562: Assignment to dataBram_0_serverAdapterB_writeWithResp$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1563: Assignment to dataBram_0_serverAdapterB_writeWithResp$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1565: Assignment to dataBram_0_serverAdapterB_s1_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1566: Assignment to dataBram_0_serverAdapterB_s1_1$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1568: Assignment to metaBram_0_serverAdapterA_outData_enqData$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1575: Assignment to metaBram_0_serverAdapterA_outData_outData$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1579: Assignment to metaBram_0_serverAdapterA_outData_outData$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1583: Assignment to metaBram_0_serverAdapterA_cnt_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1584: Assignment to metaBram_0_serverAdapterA_cnt_1$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1585: Assignment to metaBram_0_serverAdapterA_cnt_2$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1586: Assignment to metaBram_0_serverAdapterA_cnt_2$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1587: Assignment to metaBram_0_serverAdapterA_cnt_3$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1588: Assignment to metaBram_0_serverAdapterA_cnt_3$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1589: Assignment to metaBram_0_serverAdapterA_writeWithResp$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1590: Assignment to metaBram_0_serverAdapterA_writeWithResp$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1592: Assignment to metaBram_0_serverAdapterA_s1_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1593: Assignment to metaBram_0_serverAdapterA_s1_1$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1594: Assignment to metaBram_0_serverAdapterB_outData_enqData$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1601: Assignment to metaBram_0_serverAdapterB_outData_outData$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1606: Assignment to metaBram_0_serverAdapterB_cnt_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1607: Assignment to metaBram_0_serverAdapterB_cnt_1$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1609: Assignment to metaBram_0_serverAdapterB_cnt_2$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1610: Assignment to metaBram_0_serverAdapterB_cnt_2$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1612: Assignment to metaBram_0_serverAdapterB_cnt_3$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1613: Assignment to metaBram_0_serverAdapterB_cnt_3$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1614: Assignment to metaBram_0_serverAdapterB_writeWithResp$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1615: Assignment to metaBram_0_serverAdapterB_writeWithResp$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1617: Assignment to metaBram_0_serverAdapterB_s1_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1618: Assignment to metaBram_0_serverAdapterB_s1_1$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1620: Assignment to metaBram_1_serverAdapterA_outData_enqData$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1627: Assignment to metaBram_1_serverAdapterA_outData_outData$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1631: Assignment to metaBram_1_serverAdapterA_outData_outData$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1635: Assignment to metaBram_1_serverAdapterA_cnt_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1636: Assignment to metaBram_1_serverAdapterA_cnt_1$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1637: Assignment to metaBram_1_serverAdapterA_cnt_2$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1638: Assignment to metaBram_1_serverAdapterA_cnt_2$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1639: Assignment to metaBram_1_serverAdapterA_cnt_3$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1640: Assignment to metaBram_1_serverAdapterA_cnt_3$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1641: Assignment to metaBram_1_serverAdapterA_writeWithResp$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1642: Assignment to metaBram_1_serverAdapterA_writeWithResp$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1644: Assignment to metaBram_1_serverAdapterA_s1_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1645: Assignment to metaBram_1_serverAdapterA_s1_1$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1646: Assignment to metaBram_1_serverAdapterB_outData_enqData$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1653: Assignment to metaBram_1_serverAdapterB_outData_outData$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1658: Assignment to metaBram_1_serverAdapterB_cnt_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1659: Assignment to metaBram_1_serverAdapterB_cnt_1$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1661: Assignment to metaBram_1_serverAdapterB_cnt_2$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1666: Assignment to metaBram_1_serverAdapterB_cnt_3$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1667: Assignment to metaBram_1_serverAdapterB_cnt_3$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1668: Assignment to metaBram_1_serverAdapterB_writeWithResp$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1669: Assignment to metaBram_1_serverAdapterB_writeWithResp$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1671: Assignment to metaBram_1_serverAdapterB_s1_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1672: Assignment to metaBram_1_serverAdapterB_s1_1$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1674: Assignment to metaBram_2_serverAdapterA_outData_enqData$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1681: Assignment to metaBram_2_serverAdapterA_outData_outData$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1685: Assignment to metaBram_2_serverAdapterA_outData_outData$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1689: Assignment to metaBram_2_serverAdapterA_cnt_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1690: Assignment to metaBram_2_serverAdapterA_cnt_1$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1691: Assignment to metaBram_2_serverAdapterA_cnt_2$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1692: Assignment to metaBram_2_serverAdapterA_cnt_2$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1693: Assignment to metaBram_2_serverAdapterA_cnt_3$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1694: Assignment to metaBram_2_serverAdapterA_cnt_3$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1695: Assignment to metaBram_2_serverAdapterA_writeWithResp$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1696: Assignment to metaBram_2_serverAdapterA_writeWithResp$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1698: Assignment to metaBram_2_serverAdapterA_s1_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1699: Assignment to metaBram_2_serverAdapterA_s1_1$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1700: Assignment to metaBram_2_serverAdapterB_outData_enqData$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1707: Assignment to metaBram_2_serverAdapterB_outData_outData$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1712: Assignment to metaBram_2_serverAdapterB_cnt_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1713: Assignment to metaBram_2_serverAdapterB_cnt_1$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1715: Assignment to metaBram_2_serverAdapterB_cnt_2$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1716: Assignment to metaBram_2_serverAdapterB_cnt_2$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1718: Assignment to metaBram_2_serverAdapterB_cnt_3$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1719: Assignment to metaBram_2_serverAdapterB_cnt_3$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1720: Assignment to metaBram_2_serverAdapterB_writeWithResp$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1721: Assignment to metaBram_2_serverAdapterB_writeWithResp$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1723: Assignment to metaBram_2_serverAdapterB_s1_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1724: Assignment to metaBram_2_serverAdapterB_s1_1$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1726: Assignment to metaBram_3_serverAdapterA_outData_enqData$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1733: Assignment to metaBram_3_serverAdapterA_outData_outData$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1737: Assignment to metaBram_3_serverAdapterA_outData_outData$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1741: Assignment to metaBram_3_serverAdapterA_cnt_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1742: Assignment to metaBram_3_serverAdapterA_cnt_1$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1743: Assignment to metaBram_3_serverAdapterA_cnt_2$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1744: Assignment to metaBram_3_serverAdapterA_cnt_2$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1745: Assignment to metaBram_3_serverAdapterA_cnt_3$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1746: Assignment to metaBram_3_serverAdapterA_cnt_3$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1747: Assignment to metaBram_3_serverAdapterA_writeWithResp$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1748: Assignment to metaBram_3_serverAdapterA_writeWithResp$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1750: Assignment to metaBram_3_serverAdapterA_s1_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1751: Assignment to metaBram_3_serverAdapterA_s1_1$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1752: Assignment to metaBram_3_serverAdapterB_outData_enqData$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1759: Assignment to metaBram_3_serverAdapterB_outData_outData$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1764: Assignment to metaBram_3_serverAdapterB_cnt_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1765: Assignment to metaBram_3_serverAdapterB_cnt_1$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1767: Assignment to metaBram_3_serverAdapterB_cnt_2$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1768: Assignment to metaBram_3_serverAdapterB_cnt_2$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1770: Assignment to metaBram_3_serverAdapterB_cnt_3$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1771: Assignment to metaBram_3_serverAdapterB_cnt_3$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1772: Assignment to metaBram_3_serverAdapterB_writeWithResp$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1773: Assignment to metaBram_3_serverAdapterB_writeWithResp$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1775: Assignment to metaBram_3_serverAdapterB_s1_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1776: Assignment to metaBram_3_serverAdapterB_s1_1$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1778: Assignment to wsi_Es_mCmd_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1779: Assignment to wsi_Es_mCmd_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1780: Assignment to wsi_Es_mBurstLength_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1781: Assignment to wsi_Es_mBurstLength_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1782: Assignment to wsi_Es_mData_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1783: Assignment to wsi_Es_mData_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1784: Assignment to wsi_Es_mByteEn_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1785: Assignment to wsi_Es_mByteEn_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1786: Assignment to wsi_Es_mReqInfo_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1787: Assignment to wsi_Es_mReqInfo_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1788: Assignment to wti_Es_mCmd_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1789: Assignment to wti_Es_mCmd_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1790: Assignment to wti_Es_mData_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1791: Assignment to wti_Es_mData_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1792: Assignment to wci_wslv_reqF_r_enq$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1796: Assignment to wci_wslv_reqF_r_clr$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1803: Assignment to wci_wslv_respF_dequeueing$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1804: Assignment to wci_wslv_sThreadBusy_pw$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1814: Assignment to wsiS_reqFifo_r_enq$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1815: Assignment to wsiS_reqFifo_r_deq$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1817: Assignment to wsiS_reqFifo_r_clr$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1818: Assignment to wsiS_reqFifo_doResetEnq$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1819: Assignment to wsiS_reqFifo_doResetDeq$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1821: Assignment to wsiS_reqFifo_doResetClr$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1822: Assignment to dataBram_0_serverAdapterA_outData_deqCalled$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1826: Assignment to metaBram_0_serverAdapterA_outData_deqCalled$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1831: Assignment to metaBram_1_serverAdapterA_outData_deqCalled$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1832: Assignment to metaBram_1_serverAdapterB_outData_deqCalled$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1834: Assignment to metaBram_2_serverAdapterA_outData_deqCalled$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1839: Assignment to metaBram_3_serverAdapterA_outData_deqCalled$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1844: Assignment to wsi_Es_mReqLast_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1845: Assignment to wsi_Es_mBurstPrecise_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 1846: Assignment to wsi_Es_mDataInfo_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 2103: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 2127: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" Line 2687: Assignment to isFirst ignored, since the identifier is never used +WARNING:HDLCompiler:1016 - "/home/shep/projects/ocpi/rtl/mkCTop16B.v" Line 1483: Port EN_uuid is not connected to this instance + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 829: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 883: Assignment to wci_wslv_wciReq$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 884: Assignment to wci_wslv_respF_x_wire$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 888: Assignment to wci_wslv_wEdge$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 889: Assignment to wci_wslv_wEdge$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 890: Assignment to wci_wslv_sFlagReg_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 891: Assignment to wci_wslv_sFlagReg_1$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 892: Assignment to wci_wslv_ctlAckReg_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 896: Assignment to wci_wci_Es_mCmd_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 897: Assignment to wci_wci_Es_mCmd_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 898: Assignment to wci_wci_Es_mAddrSpace_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 899: Assignment to wci_wci_Es_mAddrSpace_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 900: Assignment to wci_wci_Es_mByteEn_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 901: Assignment to wci_wci_Es_mByteEn_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 902: Assignment to wci_wci_Es_mAddr_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 903: Assignment to wci_wci_Es_mAddr_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 904: Assignment to wci_wci_Es_mData_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 905: Assignment to wci_wci_Es_mData_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 906: Assignment to wmemi_reqF_x_wire$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 909: Assignment to wmemi_dhF_x_wire$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 910: Assignment to wmemi_dhF_x_wire$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 913: Assignment to wmemi_wmemiResponse$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 914: Assignment to wmemi_sCmdAccept_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 915: Assignment to wmemi_sCmdAccept_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 916: Assignment to wmemi_sDataAccept_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 917: Assignment to wmemi_sDataAccept_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 918: Assignment to wmemi_operateD_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 919: Assignment to wmemi_operateD_1$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 920: Assignment to wmemi_peerIsReady_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 921: Assignment to wmemi_peerIsReady_1$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 922: Assignment to wmemi_Em_sResp_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 923: Assignment to wmemi_Em_sResp_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 924: Assignment to wmemi_Em_sData_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 925: Assignment to wmemi_Em_sData_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 926: Assignment to wci_wslv_reqF_r_enq$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 930: Assignment to wci_wslv_reqF_r_clr$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 934: Assignment to wci_wslv_respF_dequeueing$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 935: Assignment to wci_wslv_sThreadBusy_pw$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 949: Assignment to wmemi_dhF_enqueueing$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 952: Assignment to wmemi_Em_sRespLast_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 1120: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 1144: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 1217: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 1238: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 1286: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 1307: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" Line 1434: Assignment to respCnt ignored, since the identifier is never used + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1568: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1650: Assignment to wci_wslv_wciReq$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1651: Assignment to wci_wslv_respF_x_wire$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1655: Assignment to wci_wslv_wEdge$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1656: Assignment to wci_wslv_wEdge$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1657: Assignment to wci_wslv_sFlagReg_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1658: Assignment to wci_wslv_sFlagReg_1$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1659: Assignment to wci_wslv_ctlAckReg_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1663: Assignment to wci_wci_Es_mCmd_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1664: Assignment to wci_wci_Es_mCmd_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1665: Assignment to wci_wci_Es_mAddrSpace_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1666: Assignment to wci_wci_Es_mAddrSpace_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1667: Assignment to wci_wci_Es_mByteEn_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1668: Assignment to wci_wci_Es_mByteEn_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1669: Assignment to wci_wci_Es_mAddr_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1670: Assignment to wci_wci_Es_mAddr_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1671: Assignment to wci_wci_Es_mData_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1672: Assignment to wci_wci_Es_mData_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1673: Assignment to wmi_reqF_x_wire$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1677: Assignment to wmi_mFlagF_x_wire$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1678: Assignment to wmi_mFlagF_x_wire$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1679: Assignment to wmi_dhF_x_wire$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1680: Assignment to wmi_dhF_x_wire$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1682: Assignment to wmi_wmiResponse$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1683: Assignment to wmi_sThreadBusy_d_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1684: Assignment to wmi_sThreadBusy_d_1$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1685: Assignment to wmi_sDataThreadBusy_d_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1686: Assignment to wmi_sDataThreadBusy_d_1$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1687: Assignment to wmi_operateD_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1688: Assignment to wmi_operateD_1$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1689: Assignment to wmi_peerIsReady_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1690: Assignment to wmi_peerIsReady_1$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1691: Assignment to wsiM_reqFifo_x_wire$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1692: Assignment to wsiM_reqFifo_x_wire$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1693: Assignment to wsiM_operateD_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1694: Assignment to wsiM_operateD_1$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1695: Assignment to wsiM_peerIsReady_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1696: Assignment to wsiM_peerIsReady_1$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1705: Assignment to wsiS_wsiReq$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1706: Assignment to wsiS_operateD_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1707: Assignment to wsiS_operateD_1$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1708: Assignment to wsiS_peerIsReady_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1709: Assignment to wsiS_peerIsReady_1$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1713: Assignment to fabRespCredit_acc_v1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1714: Assignment to fabRespCredit_acc_v1$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1715: Assignment to fabRespCredit_acc_v2$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1716: Assignment to fabRespCredit_acc_v2$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1717: Assignment to mesgPreRequest_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1718: Assignment to mesgPreRequest_1$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1727: Assignment to respF_wDataIn$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1728: Assignment to respF_wDataOut$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1729: Assignment to respF_wDataOut$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1730: Assignment to wsi_Es_mCmd_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1731: Assignment to wsi_Es_mCmd_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1732: Assignment to wsi_Es_mBurstLength_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1733: Assignment to wsi_Es_mBurstLength_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1734: Assignment to wsi_Es_mData_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1735: Assignment to wsi_Es_mData_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1736: Assignment to wsi_Es_mByteEn_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1737: Assignment to wsi_Es_mByteEn_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1738: Assignment to wsi_Es_mReqInfo_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1739: Assignment to wsi_Es_mReqInfo_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1740: Assignment to wmi_Em_sResp_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1741: Assignment to wmi_Em_sResp_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1742: Assignment to wmi_Em_sData_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1743: Assignment to wmi_Em_sData_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1744: Assignment to wci_wslv_reqF_r_enq$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1748: Assignment to wci_wslv_reqF_r_clr$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1752: Assignment to wci_wslv_respF_dequeueing$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1753: Assignment to wci_wslv_sThreadBusy_pw$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1775: Assignment to wmi_dhF_enqueueing$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1785: Assignment to wsiM_reqFifo_dequeueing$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1786: Assignment to wsiM_sThreadBusy_pw$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1787: Assignment to wsiS_reqFifo_r_enq$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1791: Assignment to wsiS_reqFifo_r_clr$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1792: Assignment to wsiS_reqFifo_doResetEnq$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1793: Assignment to wsiS_reqFifo_doResetDeq$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1794: Assignment to wsiS_reqFifo_doResetClr$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1795: Assignment to respF_pwDequeue$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1797: Assignment to respF_pwClear$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1798: Assignment to wsi_Es_mReqLast_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1799: Assignment to wsi_Es_mBurstPrecise_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1800: Assignment to wsi_Es_mDataInfo_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1871: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1968: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 2074: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 2098: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 2142: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 2163: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 2201: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 2220: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 2256: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 2276: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 2382: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 2406: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 2861: Assignment to firstMsgReq ignored, since the identifier is never used + +Elaborating module . +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 787: Found parallel_case directive in module mkBiasWorker16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 830: Assignment to wci_wslv_wciReq$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 831: Assignment to wci_wslv_respF_x_wire$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 835: Assignment to wci_wslv_wEdge$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 836: Assignment to wci_wslv_wEdge$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 837: Assignment to wci_wslv_sFlagReg_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 838: Assignment to wci_wslv_sFlagReg_1$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 839: Assignment to wci_wslv_ctlAckReg_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 843: Assignment to wci_wci_Es_mCmd_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 844: Assignment to wci_wci_Es_mCmd_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 845: Assignment to wci_wci_Es_mAddrSpace_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 846: Assignment to wci_wci_Es_mAddrSpace_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 847: Assignment to wci_wci_Es_mByteEn_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 848: Assignment to wci_wci_Es_mByteEn_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 849: Assignment to wci_wci_Es_mAddr_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 850: Assignment to wci_wci_Es_mAddr_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 851: Assignment to wci_wci_Es_mData_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 852: Assignment to wci_wci_Es_mData_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 861: Assignment to wsiS_wsiReq$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 862: Assignment to wsiS_operateD_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 863: Assignment to wsiS_operateD_1$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 864: Assignment to wsiS_peerIsReady_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 865: Assignment to wsiS_peerIsReady_1$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 869: Assignment to wsiM_reqFifo_x_wire$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 870: Assignment to wsiM_reqFifo_x_wire$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 872: Assignment to wsiM_operateD_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 873: Assignment to wsiM_operateD_1$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 874: Assignment to wsiM_peerIsReady_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 875: Assignment to wsiM_peerIsReady_1$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 876: Assignment to wsi_Es_mCmd_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 877: Assignment to wsi_Es_mCmd_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 878: Assignment to wsi_Es_mBurstLength_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 879: Assignment to wsi_Es_mBurstLength_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 880: Assignment to wsi_Es_mData_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 881: Assignment to wsi_Es_mData_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 882: Assignment to wsi_Es_mByteEn_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 883: Assignment to wsi_Es_mByteEn_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 884: Assignment to wsi_Es_mReqInfo_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 885: Assignment to wsi_Es_mReqInfo_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 886: Assignment to wci_wslv_reqF_r_enq$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 890: Assignment to wci_wslv_reqF_r_clr$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 894: Assignment to wci_wslv_respF_dequeueing$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 895: Assignment to wci_wslv_sThreadBusy_pw$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 905: Assignment to wsiS_reqFifo_r_enq$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 906: Assignment to wsiS_reqFifo_r_deq$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 908: Assignment to wsiS_reqFifo_r_clr$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 909: Assignment to wsiS_reqFifo_doResetEnq$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 910: Assignment to wsiS_reqFifo_doResetDeq$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 912: Assignment to wsiS_reqFifo_doResetClr$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 913: Assignment to wsiM_reqFifo_enqueueing$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 915: Assignment to wsiM_reqFifo_dequeueing$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 916: Assignment to wsiM_sThreadBusy_pw$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 917: Assignment to wsi_Es_mReqLast_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 918: Assignment to wsi_Es_mBurstPrecise_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 919: Assignment to wsi_Es_mDataInfo_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 1019: Found parallel_case directive in module mkBiasWorker16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 1043: Found parallel_case directive in module mkBiasWorker16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 1128: Found parallel_case directive in module mkBiasWorker16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 1152: Found parallel_case directive in module mkBiasWorker16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" Line 1349: Assignment to wci_wslv_cEdge ignored, since the identifier is never used + +Elaborating module . +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1568: Found parallel_case directive in module mkSMAdapter16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1650: Assignment to wci_wslv_wciReq$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1651: Assignment to wci_wslv_respF_x_wire$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1655: Assignment to wci_wslv_wEdge$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1656: Assignment to wci_wslv_wEdge$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1657: Assignment to wci_wslv_sFlagReg_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1658: Assignment to wci_wslv_sFlagReg_1$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1659: Assignment to wci_wslv_ctlAckReg_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1663: Assignment to wci_wci_Es_mCmd_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1664: Assignment to wci_wci_Es_mCmd_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1665: Assignment to wci_wci_Es_mAddrSpace_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1666: Assignment to wci_wci_Es_mAddrSpace_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1667: Assignment to wci_wci_Es_mByteEn_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1668: Assignment to wci_wci_Es_mByteEn_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1669: Assignment to wci_wci_Es_mAddr_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1670: Assignment to wci_wci_Es_mAddr_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1671: Assignment to wci_wci_Es_mData_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1672: Assignment to wci_wci_Es_mData_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1673: Assignment to wmi_reqF_x_wire$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1677: Assignment to wmi_mFlagF_x_wire$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1678: Assignment to wmi_mFlagF_x_wire$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1679: Assignment to wmi_dhF_x_wire$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1680: Assignment to wmi_dhF_x_wire$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1682: Assignment to wmi_wmiResponse$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1683: Assignment to wmi_sThreadBusy_d_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1684: Assignment to wmi_sThreadBusy_d_1$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1685: Assignment to wmi_sDataThreadBusy_d_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1686: Assignment to wmi_sDataThreadBusy_d_1$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1687: Assignment to wmi_operateD_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1688: Assignment to wmi_operateD_1$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1689: Assignment to wmi_peerIsReady_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1690: Assignment to wmi_peerIsReady_1$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1691: Assignment to wsiM_reqFifo_x_wire$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1692: Assignment to wsiM_reqFifo_x_wire$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1693: Assignment to wsiM_operateD_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1694: Assignment to wsiM_operateD_1$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1695: Assignment to wsiM_peerIsReady_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1696: Assignment to wsiM_peerIsReady_1$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1705: Assignment to wsiS_wsiReq$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1706: Assignment to wsiS_operateD_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1707: Assignment to wsiS_operateD_1$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1708: Assignment to wsiS_peerIsReady_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1709: Assignment to wsiS_peerIsReady_1$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1713: Assignment to fabRespCredit_acc_v1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1714: Assignment to fabRespCredit_acc_v1$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1715: Assignment to fabRespCredit_acc_v2$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1716: Assignment to fabRespCredit_acc_v2$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1717: Assignment to mesgPreRequest_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1718: Assignment to mesgPreRequest_1$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1727: Assignment to respF_wDataIn$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1728: Assignment to respF_wDataOut$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1729: Assignment to respF_wDataOut$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1730: Assignment to wsi_Es_mCmd_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1731: Assignment to wsi_Es_mCmd_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1732: Assignment to wsi_Es_mBurstLength_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1733: Assignment to wsi_Es_mBurstLength_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1734: Assignment to wsi_Es_mData_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1735: Assignment to wsi_Es_mData_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1736: Assignment to wsi_Es_mByteEn_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1737: Assignment to wsi_Es_mByteEn_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1738: Assignment to wsi_Es_mReqInfo_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1739: Assignment to wsi_Es_mReqInfo_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1740: Assignment to wmi_Em_sResp_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1741: Assignment to wmi_Em_sResp_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1742: Assignment to wmi_Em_sData_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1743: Assignment to wmi_Em_sData_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1744: Assignment to wci_wslv_reqF_r_enq$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1748: Assignment to wci_wslv_reqF_r_clr$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1752: Assignment to wci_wslv_respF_dequeueing$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1753: Assignment to wci_wslv_sThreadBusy_pw$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1775: Assignment to wmi_dhF_enqueueing$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1785: Assignment to wsiM_reqFifo_dequeueing$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1786: Assignment to wsiM_sThreadBusy_pw$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1787: Assignment to wsiS_reqFifo_r_enq$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1791: Assignment to wsiS_reqFifo_r_clr$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1792: Assignment to wsiS_reqFifo_doResetEnq$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1793: Assignment to wsiS_reqFifo_doResetDeq$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1794: Assignment to wsiS_reqFifo_doResetClr$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1795: Assignment to respF_pwDequeue$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1797: Assignment to respF_pwClear$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1798: Assignment to wsi_Es_mReqLast_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1799: Assignment to wsi_Es_mBurstPrecise_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1800: Assignment to wsi_Es_mDataInfo_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1871: Found parallel_case directive in module mkSMAdapter16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 1968: Found parallel_case directive in module mkSMAdapter16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 2074: Found parallel_case directive in module mkSMAdapter16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 2098: Found parallel_case directive in module mkSMAdapter16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 2142: Found parallel_case directive in module mkSMAdapter16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 2163: Found parallel_case directive in module mkSMAdapter16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 2201: Found parallel_case directive in module mkSMAdapter16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 2220: Found parallel_case directive in module mkSMAdapter16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 2256: Found parallel_case directive in module mkSMAdapter16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 2276: Found parallel_case directive in module mkSMAdapter16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 2382: Found parallel_case directive in module mkSMAdapter16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 2406: Found parallel_case directive in module mkSMAdapter16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" Line 2861: Assignment to firstMsgReq ignored, since the identifier is never used + +Elaborating module . +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1743: Assignment to tieOff0_wci_Es_mCmd_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1744: Assignment to tieOff0_wci_Es_mCmd_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1745: Assignment to tieOff0_wci_Es_mAddrSpace_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1746: Assignment to tieOff0_wci_Es_mAddrSpace_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1747: Assignment to tieOff0_wci_Es_mByteEn_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1748: Assignment to tieOff0_wci_Es_mByteEn_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1749: Assignment to tieOff0_wci_Es_mAddr_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1750: Assignment to tieOff0_wci_Es_mAddr_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1751: Assignment to tieOff0_wci_Es_mData_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1752: Assignment to tieOff0_wci_Es_mData_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1753: Assignment to tieOff5_wci_Es_mCmd_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1754: Assignment to tieOff5_wci_Es_mCmd_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1755: Assignment to tieOff5_wci_Es_mAddrSpace_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1756: Assignment to tieOff5_wci_Es_mAddrSpace_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1757: Assignment to tieOff5_wci_Es_mByteEn_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1758: Assignment to tieOff5_wci_Es_mByteEn_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1759: Assignment to tieOff5_wci_Es_mAddr_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1760: Assignment to tieOff5_wci_Es_mAddr_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1761: Assignment to tieOff5_wci_Es_mData_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1762: Assignment to tieOff5_wci_Es_mData_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1763: Assignment to tieOff6_wci_Es_mCmd_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1764: Assignment to tieOff6_wci_Es_mCmd_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1765: Assignment to tieOff6_wci_Es_mAddrSpace_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1766: Assignment to tieOff6_wci_Es_mAddrSpace_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1767: Assignment to tieOff6_wci_Es_mByteEn_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1768: Assignment to tieOff6_wci_Es_mByteEn_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1769: Assignment to tieOff6_wci_Es_mAddr_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1770: Assignment to tieOff6_wci_Es_mAddr_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1771: Assignment to tieOff6_wci_Es_mData_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1772: Assignment to tieOff6_wci_Es_mData_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1773: Assignment to tieOff7_wci_Es_mCmd_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1774: Assignment to tieOff7_wci_Es_mCmd_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1775: Assignment to tieOff7_wci_Es_mAddrSpace_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1776: Assignment to tieOff7_wci_Es_mAddrSpace_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1777: Assignment to tieOff7_wci_Es_mByteEn_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1778: Assignment to tieOff7_wci_Es_mByteEn_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1779: Assignment to tieOff7_wci_Es_mAddr_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1780: Assignment to tieOff7_wci_Es_mAddr_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1781: Assignment to tieOff7_wci_Es_mData_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCApp16B.v" Line 1782: Assignment to tieOff7_wci_Es_mData_w$whas ignored, since the identifier is never used + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 9396: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 9471: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 9548: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 9625: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 9702: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 9779: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 9859: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 9935: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10011: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10087: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10163: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10239: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10315: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10391: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10467: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10511: Assignment to warmResetP_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10512: Assignment to warmResetP_1$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10513: Assignment to timeServ_jamFrac_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10516: Assignment to timeServ_jamFracVal_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10517: Assignment to timeServ_jamFracVal_1$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10518: Assignment to deviceDNA$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10519: Assignment to deviceDNA$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10522: Assignment to devDNAV$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10523: Assignment to rom_serverAdapter_outData_enqData$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10537: Assignment to rom_serverAdapter_cnt_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10538: Assignment to rom_serverAdapter_cnt_1$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10540: Assignment to rom_serverAdapter_cnt_2$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10541: Assignment to rom_serverAdapter_cnt_2$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10543: Assignment to rom_serverAdapter_cnt_3$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10544: Assignment to rom_serverAdapter_cnt_3$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10545: Assignment to rom_serverAdapter_writeWithResp$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10546: Assignment to rom_serverAdapter_writeWithResp$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10548: Assignment to rom_serverAdapter_s1_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10549: Assignment to rom_serverAdapter_s1_1$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10551: Assignment to dna_rdReg_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10553: Assignment to dna_shftReg_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10555: Assignment to uuidV$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10556: Assignment to uuidV$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10557: Assignment to wci_0_reqF_x_wire$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10563: Assignment to wci_0_wciResponse$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10564: Assignment to wci_0_sfCapSet_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10565: Assignment to wci_0_sfCapSet_1$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10566: Assignment to wci_0_sfCapClear_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10570: Assignment to wci_1_reqF_x_wire$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10576: Assignment to wci_1_wciResponse$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10577: Assignment to wci_1_sfCapSet_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10578: Assignment to wci_1_sfCapSet_1$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10579: Assignment to wci_1_sfCapClear_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10583: Assignment to wci_2_reqF_x_wire$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10589: Assignment to wci_2_wciResponse$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10590: Assignment to wci_2_sfCapSet_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10591: Assignment to wci_2_sfCapSet_1$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10592: Assignment to wci_2_sfCapClear_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10596: Assignment to wci_3_reqF_x_wire$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10602: Assignment to wci_3_wciResponse$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10603: Assignment to wci_3_sfCapSet_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10604: Assignment to wci_3_sfCapSet_1$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10605: Assignment to wci_3_sfCapClear_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10609: Assignment to wci_4_reqF_x_wire$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10615: Assignment to wci_4_wciResponse$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10616: Assignment to wci_4_sfCapSet_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10617: Assignment to wci_4_sfCapSet_1$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10618: Assignment to wci_4_sfCapClear_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10622: Assignment to wci_5_reqF_x_wire$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10628: Assignment to wci_5_wciResponse$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10629: Assignment to wci_5_sfCapSet_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10630: Assignment to wci_5_sfCapSet_1$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10631: Assignment to wci_5_sfCapClear_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10635: Assignment to wci_6_reqF_x_wire$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10641: Assignment to wci_6_wciResponse$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10642: Assignment to wci_6_sfCapSet_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10643: Assignment to wci_6_sfCapSet_1$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10644: Assignment to wci_6_sfCapClear_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10648: Assignment to wci_7_reqF_x_wire$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10654: Assignment to wci_7_wciResponse$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10655: Assignment to wci_7_sfCapSet_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10656: Assignment to wci_7_sfCapSet_1$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10657: Assignment to wci_7_sfCapClear_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10661: Assignment to wci_8_reqF_x_wire$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10667: Assignment to wci_8_wciResponse$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10668: Assignment to wci_8_sfCapSet_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10669: Assignment to wci_8_sfCapSet_1$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10670: Assignment to wci_8_sfCapClear_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10674: Assignment to wci_9_reqF_x_wire$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10680: Assignment to wci_9_wciResponse$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10681: Assignment to wci_9_sfCapSet_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10682: Assignment to wci_9_sfCapSet_1$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10683: Assignment to wci_9_sfCapClear_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10687: Assignment to wci_10_reqF_x_wire$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10693: Assignment to wci_10_wciResponse$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10694: Assignment to wci_10_sfCapSet_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10695: Assignment to wci_10_sfCapSet_1$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10696: Assignment to wci_10_sfCapClear_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10700: Assignment to wci_11_reqF_x_wire$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10706: Assignment to wci_11_wciResponse$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10707: Assignment to wci_11_sfCapSet_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10708: Assignment to wci_11_sfCapSet_1$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10709: Assignment to wci_11_sfCapClear_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10713: Assignment to wci_12_reqF_x_wire$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10719: Assignment to wci_12_wciResponse$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10720: Assignment to wci_12_sfCapSet_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10721: Assignment to wci_12_sfCapSet_1$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10722: Assignment to wci_12_sfCapClear_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10726: Assignment to wci_13_reqF_x_wire$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10732: Assignment to wci_13_wciResponse$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10733: Assignment to wci_13_sfCapSet_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10734: Assignment to wci_13_sfCapSet_1$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10735: Assignment to wci_13_sfCapClear_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10739: Assignment to wci_14_reqF_x_wire$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10745: Assignment to wci_14_wciResponse$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10746: Assignment to wci_14_sfCapSet_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10747: Assignment to wci_14_sfCapSet_1$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10748: Assignment to wci_14_sfCapClear_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10752: Assignment to wci_Emv_0_resp_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10753: Assignment to wci_Emv_0_resp_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10754: Assignment to wci_Emv_0_respData_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10755: Assignment to wci_Emv_0_respData_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10756: Assignment to wci_Emv_1_resp_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10757: Assignment to wci_Emv_1_resp_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10758: Assignment to wci_Emv_1_respData_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10759: Assignment to wci_Emv_1_respData_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10760: Assignment to wci_Emv_2_resp_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10761: Assignment to wci_Emv_2_resp_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10762: Assignment to wci_Emv_2_respData_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10763: Assignment to wci_Emv_2_respData_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10764: Assignment to wci_Emv_3_resp_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10765: Assignment to wci_Emv_3_resp_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10766: Assignment to wci_Emv_3_respData_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10767: Assignment to wci_Emv_3_respData_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10768: Assignment to wci_Emv_4_resp_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10769: Assignment to wci_Emv_4_resp_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10770: Assignment to wci_Emv_4_respData_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10771: Assignment to wci_Emv_4_respData_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10772: Assignment to wci_Emv_5_resp_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10773: Assignment to wci_Emv_5_resp_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10774: Assignment to wci_Emv_5_respData_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10775: Assignment to wci_Emv_5_respData_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10776: Assignment to wci_Emv_6_resp_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10777: Assignment to wci_Emv_6_resp_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10778: Assignment to wci_Emv_6_respData_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10779: Assignment to wci_Emv_6_respData_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10780: Assignment to wci_Emv_7_resp_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10781: Assignment to wci_Emv_7_resp_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10782: Assignment to wci_Emv_7_respData_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10783: Assignment to wci_Emv_7_respData_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10784: Assignment to wci_Emv_8_resp_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10785: Assignment to wci_Emv_8_resp_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10786: Assignment to wci_Emv_8_respData_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10787: Assignment to wci_Emv_8_respData_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10788: Assignment to wci_Emv_9_resp_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10789: Assignment to wci_Emv_9_resp_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10790: Assignment to wci_Emv_9_respData_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10791: Assignment to wci_Emv_9_respData_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10792: Assignment to wci_Emv_10_resp_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10793: Assignment to wci_Emv_10_resp_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10794: Assignment to wci_Emv_10_respData_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10795: Assignment to wci_Emv_10_respData_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10796: Assignment to wci_Emv_11_resp_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10797: Assignment to wci_Emv_11_resp_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10798: Assignment to wci_Emv_11_respData_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10799: Assignment to wci_Emv_11_respData_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10800: Assignment to wci_Emv_12_resp_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10801: Assignment to wci_Emv_12_resp_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10802: Assignment to wci_Emv_12_respData_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10803: Assignment to wci_Emv_12_respData_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10804: Assignment to wci_Emv_13_resp_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10805: Assignment to wci_Emv_13_resp_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10806: Assignment to wci_Emv_13_respData_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10807: Assignment to wci_Emv_13_respData_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10808: Assignment to wci_Emv_14_resp_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10809: Assignment to wci_Emv_14_resp_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10810: Assignment to wci_Emv_14_respData_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10811: Assignment to wci_Emv_14_respData_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10817: Assignment to wci_0_reqF_enqueueing$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10821: Assignment to wci_0_sThreadBusy_pw$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10822: Assignment to wci_1_reqF_enqueueing$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10826: Assignment to wci_1_sThreadBusy_pw$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10827: Assignment to wci_2_reqF_enqueueing$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10831: Assignment to wci_2_sThreadBusy_pw$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10832: Assignment to wci_3_reqF_enqueueing$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10836: Assignment to wci_3_sThreadBusy_pw$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10837: Assignment to wci_4_reqF_enqueueing$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10841: Assignment to wci_4_sThreadBusy_pw$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10842: Assignment to wci_5_reqF_enqueueing$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10846: Assignment to wci_5_sThreadBusy_pw$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10847: Assignment to wci_6_reqF_enqueueing$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10851: Assignment to wci_6_sThreadBusy_pw$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10852: Assignment to wci_7_reqF_enqueueing$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10856: Assignment to wci_7_sThreadBusy_pw$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10857: Assignment to wci_8_reqF_enqueueing$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10861: Assignment to wci_8_sThreadBusy_pw$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10862: Assignment to wci_9_reqF_enqueueing$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10866: Assignment to wci_9_sThreadBusy_pw$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10867: Assignment to wci_10_reqF_enqueueing$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10872: Assignment to wci_10_sThreadBusy_pw$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10873: Assignment to wci_11_reqF_enqueueing$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10878: Assignment to wci_11_sThreadBusy_pw$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10879: Assignment to wci_12_reqF_enqueueing$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10884: Assignment to wci_12_sThreadBusy_pw$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10885: Assignment to wci_13_reqF_enqueueing$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10890: Assignment to wci_13_sThreadBusy_pw$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10891: Assignment to wci_14_reqF_enqueueing$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 10896: Assignment to wci_14_sThreadBusy_pw$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 12161: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 12183: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 12348: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 12370: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 12536: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 12558: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 12724: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 12746: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 12912: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 12934: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 13100: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 13122: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 13287: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 13309: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 13473: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 13495: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 13659: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 13681: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 13845: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 13867: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 14031: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 14053: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 14217: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 14239: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 14403: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 14425: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 14589: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 14611: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 14775: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 14797: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 14885: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 15195: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 15363: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 15420: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 15478: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 15536: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 15594: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 15652: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 15710: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 15767: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 15824: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 15881: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 15938: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 15995: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 16052: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 16109: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 16166: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 24475: Assignment to warmResetP ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" Line 25618: Assignment to timeServ_ppsExtCapture ignored, since the identifier is never used + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/libsrc/hdl/ocpi/arSRLFIFOD.v" Line 62: Result of 32-bit expression is truncated to fit in 4-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/libsrc/hdl/ocpi/arSRLFIFOD.v" Line 63: Result of 5-bit expression is truncated to fit in 4-bit target. + +Elaborating module . + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3483: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3529: Assignment to bram_0_serverAdapterA_outData_enqData$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3543: Assignment to bram_0_serverAdapterA_cnt_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3550: Assignment to bram_0_serverAdapterA_cnt_2$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3551: Assignment to bram_0_serverAdapterA_cnt_2$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3553: Assignment to bram_0_serverAdapterA_cnt_3$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3554: Assignment to bram_0_serverAdapterA_cnt_3$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3555: Assignment to bram_0_serverAdapterA_writeWithResp$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3563: Assignment to bram_0_serverAdapterA_s1_1$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3565: Assignment to bram_0_serverAdapterB_outData_enqData$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3579: Assignment to bram_0_serverAdapterB_cnt_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3585: Assignment to bram_0_serverAdapterB_cnt_2$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3586: Assignment to bram_0_serverAdapterB_cnt_2$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3588: Assignment to bram_0_serverAdapterB_cnt_3$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3589: Assignment to bram_0_serverAdapterB_cnt_3$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3590: Assignment to bram_0_serverAdapterB_writeWithResp$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3597: Assignment to bram_0_serverAdapterB_s1_1$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3599: Assignment to bram_1_serverAdapterA_outData_enqData$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3613: Assignment to bram_1_serverAdapterA_cnt_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3620: Assignment to bram_1_serverAdapterA_cnt_2$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3621: Assignment to bram_1_serverAdapterA_cnt_2$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3623: Assignment to bram_1_serverAdapterA_cnt_3$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3624: Assignment to bram_1_serverAdapterA_cnt_3$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3625: Assignment to bram_1_serverAdapterA_writeWithResp$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3633: Assignment to bram_1_serverAdapterA_s1_1$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3635: Assignment to bram_1_serverAdapterB_outData_enqData$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3649: Assignment to bram_1_serverAdapterB_cnt_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3655: Assignment to bram_1_serverAdapterB_cnt_2$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3656: Assignment to bram_1_serverAdapterB_cnt_2$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3658: Assignment to bram_1_serverAdapterB_cnt_3$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3659: Assignment to bram_1_serverAdapterB_cnt_3$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3660: Assignment to bram_1_serverAdapterB_writeWithResp$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3661: Assignment to bram_1_serverAdapterB_writeWithResp$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3665: Assignment to bram_1_serverAdapterB_s1_1$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3667: Assignment to bram_2_serverAdapterA_outData_enqData$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3680: Assignment to bram_2_serverAdapterA_cnt_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3687: Assignment to bram_2_serverAdapterA_cnt_2$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3688: Assignment to bram_2_serverAdapterA_cnt_2$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3690: Assignment to bram_2_serverAdapterA_cnt_3$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3691: Assignment to bram_2_serverAdapterA_cnt_3$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3692: Assignment to bram_2_serverAdapterA_writeWithResp$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3700: Assignment to bram_2_serverAdapterA_s1_1$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3702: Assignment to bram_2_serverAdapterB_outData_enqData$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3716: Assignment to bram_2_serverAdapterB_cnt_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3722: Assignment to bram_2_serverAdapterB_cnt_2$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3723: Assignment to bram_2_serverAdapterB_cnt_2$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3725: Assignment to bram_2_serverAdapterB_cnt_3$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3726: Assignment to bram_2_serverAdapterB_cnt_3$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3727: Assignment to bram_2_serverAdapterB_writeWithResp$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3728: Assignment to bram_2_serverAdapterB_writeWithResp$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3732: Assignment to bram_2_serverAdapterB_s1_1$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3734: Assignment to bram_3_serverAdapterA_outData_enqData$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3748: Assignment to bram_3_serverAdapterA_cnt_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3755: Assignment to bram_3_serverAdapterA_cnt_2$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3756: Assignment to bram_3_serverAdapterA_cnt_2$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3758: Assignment to bram_3_serverAdapterA_cnt_3$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3759: Assignment to bram_3_serverAdapterA_cnt_3$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3760: Assignment to bram_3_serverAdapterA_writeWithResp$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3768: Assignment to bram_3_serverAdapterA_s1_1$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3770: Assignment to bram_3_serverAdapterB_outData_enqData$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3784: Assignment to bram_3_serverAdapterB_cnt_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3790: Assignment to bram_3_serverAdapterB_cnt_2$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3791: Assignment to bram_3_serverAdapterB_cnt_2$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3793: Assignment to bram_3_serverAdapterB_cnt_3$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3794: Assignment to bram_3_serverAdapterB_cnt_3$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3795: Assignment to bram_3_serverAdapterB_writeWithResp$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3796: Assignment to bram_3_serverAdapterB_writeWithResp$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3800: Assignment to bram_3_serverAdapterB_s1_1$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3808: Assignment to wci_wciReq$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3809: Assignment to wci_respF_x_wire$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3810: Assignment to wci_respF_x_wire$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3811: Assignment to wci_wEdge$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3812: Assignment to wci_wEdge$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3813: Assignment to wci_sFlagReg_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3814: Assignment to wci_sFlagReg_1$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3815: Assignment to wci_ctlAckReg_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3824: Assignment to wti_wtiReq$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3825: Assignment to wti_wtiReq$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3826: Assignment to wti_operateD_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3827: Assignment to wti_operateD_1$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3828: Assignment to tlp_remStart_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3833: Assignment to tlp_remDone_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3837: Assignment to tlp_nearBufReady_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3840: Assignment to tlp_farBufReady_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3843: Assignment to tlp_creditReady_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3846: Assignment to tlp_dpControl$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3847: Assignment to tlp_dpControl$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3855: Assignment to tlp_nowW$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3856: Assignment to tlp_nowW$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3857: Assignment to tlp_dmaStartMark_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3861: Assignment to tlp_dmaDoneMark_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3862: Assignment to tlp_dmaDoneMark_1$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3870: Assignment to wmi_wmi_wmiReq$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3871: Assignment to wmi_wmi_wmiMFlag$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3872: Assignment to wmi_wmi_wmiMFlag$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3878: Assignment to wmi_wmi_wmiDh$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3879: Assignment to wmi_wmi_respF_x_wire$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3880: Assignment to wmi_wmi_respF_x_wire$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3881: Assignment to wmi_wmi_operateD_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3882: Assignment to wmi_wmi_operateD_1$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3883: Assignment to wmi_wmi_peerIsReady_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3884: Assignment to wmi_wmi_peerIsReady_1$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3894: Assignment to wmi_mesgStart_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3896: Assignment to wmi_mesgDone_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3901: Assignment to wmi_mesgBufReady_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3904: Assignment to wmi_dpControl$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3905: Assignment to wmi_dpControl$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3907: Assignment to wmi_nowW$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3908: Assignment to bml_lclBufStart_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3909: Assignment to bml_lclBufStart_1$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3910: Assignment to bml_lclBufDone_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3911: Assignment to bml_lclBufDone_1$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3912: Assignment to bml_remStart_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3913: Assignment to bml_remStart_1$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3914: Assignment to bml_remDone_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3915: Assignment to bml_remDone_1$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3916: Assignment to bml_fabDone_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3920: Assignment to bml_fabAvail_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3924: Assignment to bml_datumAReg_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3925: Assignment to bml_datumAReg_1$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3926: Assignment to bml_dpControl$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3927: Assignment to bml_dpControl$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3928: Assignment to wci_Es_mCmd_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3929: Assignment to wci_Es_mCmd_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3930: Assignment to wci_Es_mAddrSpace_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3931: Assignment to wci_Es_mAddrSpace_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3932: Assignment to wci_Es_mByteEn_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3933: Assignment to wci_Es_mByteEn_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3934: Assignment to wci_Es_mAddr_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3935: Assignment to wci_Es_mAddr_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3936: Assignment to wci_Es_mData_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3937: Assignment to wci_Es_mData_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3938: Assignment to wmi_Es_mCmd_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3939: Assignment to wmi_Es_mCmd_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3940: Assignment to wmi_Es_mReqInfo_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3941: Assignment to wmi_Es_mReqInfo_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3942: Assignment to wmi_Es_mAddrSpace_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3943: Assignment to wmi_Es_mAddrSpace_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3944: Assignment to wmi_Es_mAddr_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3945: Assignment to wmi_Es_mAddr_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3946: Assignment to wmi_Es_mBurstLength_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3947: Assignment to wmi_Es_mBurstLength_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3948: Assignment to wmi_Es_mData_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3949: Assignment to wmi_Es_mData_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3950: Assignment to wmi_Es_mDataByteEn_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3951: Assignment to wmi_Es_mDataByteEn_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3964: Assignment to bram_1_serverAdapterB_outData_deqCalled$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3971: Assignment to bram_2_serverAdapterB_outData_deqCalled$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3978: Assignment to bram_3_serverAdapterB_outData_deqCalled$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3980: Assignment to wci_reqF_r_enq$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3984: Assignment to wci_reqF_r_clr$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3988: Assignment to wci_respF_dequeueing$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3989: Assignment to wci_sThreadBusy_pw$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4002: Assignment to wmi_wmi_reqF_r_enq$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4004: Assignment to wmi_wmi_reqF_r_deq$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4005: Assignment to wmi_wmi_reqF_r_clr$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4006: Assignment to wmi_wmi_reqF_doResetEnq$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4008: Assignment to wmi_wmi_reqF_doResetDeq$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4009: Assignment to wmi_wmi_reqF_doResetClr$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4010: Assignment to wmi_wmi_mFlagF_r_enq$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4012: Assignment to wmi_wmi_mFlagF_r_deq$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4013: Assignment to wmi_wmi_mFlagF_r_clr$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4014: Assignment to wmi_wmi_mFlagF_doResetEnq$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4016: Assignment to wmi_wmi_mFlagF_doResetDeq$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4017: Assignment to wmi_wmi_mFlagF_doResetClr$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4018: Assignment to wmi_wmi_dhF_r_enq$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4019: Assignment to wmi_wmi_dhF_r_deq$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4020: Assignment to wmi_wmi_dhF_r_clr$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4021: Assignment to wmi_wmi_dhF_doResetEnq$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4023: Assignment to wmi_wmi_dhF_doResetDeq$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4024: Assignment to wmi_wmi_dhF_doResetClr$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4025: Assignment to wmi_wmi_respF_enqueueing$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4026: Assignment to wmi_wmi_respF_dequeueing$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4027: Assignment to bml_lclBuf_incAction$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4028: Assignment to bml_lclBuf_decAction$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4029: Assignment to bml_remBuf_incAction$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4030: Assignment to bml_remBuf_decAction$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4031: Assignment to bml_fabBuf_incAction$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4032: Assignment to bml_fabBuf_decAction$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4033: Assignment to bml_crdBuf_incAction$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4034: Assignment to bml_crdBuf_decAction$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4035: Assignment to wmi_Es_mReqLast_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4036: Assignment to wmi_Es_mDataValid_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4037: Assignment to wmi_Es_mDataLast_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4038: Assignment to wmi_Es_mDataInfo_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4039: Assignment to bml_lclBuf_modulus_bw$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4040: Assignment to bml_remBuf_modulus_bw$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4041: Assignment to bml_fabBuf_modulus_bw$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4042: Assignment to bml_crdBuf_modulus_bw$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4100: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4512: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4581: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4649: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4754: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4779: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4835: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4878: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4914: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5067: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5091: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5220: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5240: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5487: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5511: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5581: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5599: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5616: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5633: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5699: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5717: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5734: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5751: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5817: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5835: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5852: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5869: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5935: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5953: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5970: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5987: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 6072: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 6129: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 7301: Assignment to bml_datumAReg ignored, since the identifier is never used + +Elaborating module . +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3483: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3529: Assignment to bram_0_serverAdapterA_outData_enqData$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3543: Assignment to bram_0_serverAdapterA_cnt_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3550: Assignment to bram_0_serverAdapterA_cnt_2$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3551: Assignment to bram_0_serverAdapterA_cnt_2$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3553: Assignment to bram_0_serverAdapterA_cnt_3$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3554: Assignment to bram_0_serverAdapterA_cnt_3$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3555: Assignment to bram_0_serverAdapterA_writeWithResp$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3563: Assignment to bram_0_serverAdapterA_s1_1$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3565: Assignment to bram_0_serverAdapterB_outData_enqData$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3579: Assignment to bram_0_serverAdapterB_cnt_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3585: Assignment to bram_0_serverAdapterB_cnt_2$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3586: Assignment to bram_0_serverAdapterB_cnt_2$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3588: Assignment to bram_0_serverAdapterB_cnt_3$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3589: Assignment to bram_0_serverAdapterB_cnt_3$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3590: Assignment to bram_0_serverAdapterB_writeWithResp$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3597: Assignment to bram_0_serverAdapterB_s1_1$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3599: Assignment to bram_1_serverAdapterA_outData_enqData$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3613: Assignment to bram_1_serverAdapterA_cnt_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3620: Assignment to bram_1_serverAdapterA_cnt_2$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3621: Assignment to bram_1_serverAdapterA_cnt_2$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3623: Assignment to bram_1_serverAdapterA_cnt_3$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3624: Assignment to bram_1_serverAdapterA_cnt_3$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3625: Assignment to bram_1_serverAdapterA_writeWithResp$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3633: Assignment to bram_1_serverAdapterA_s1_1$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3635: Assignment to bram_1_serverAdapterB_outData_enqData$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3649: Assignment to bram_1_serverAdapterB_cnt_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3655: Assignment to bram_1_serverAdapterB_cnt_2$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3656: Assignment to bram_1_serverAdapterB_cnt_2$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3658: Assignment to bram_1_serverAdapterB_cnt_3$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3659: Assignment to bram_1_serverAdapterB_cnt_3$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3660: Assignment to bram_1_serverAdapterB_writeWithResp$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3661: Assignment to bram_1_serverAdapterB_writeWithResp$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3665: Assignment to bram_1_serverAdapterB_s1_1$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3667: Assignment to bram_2_serverAdapterA_outData_enqData$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3680: Assignment to bram_2_serverAdapterA_cnt_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3687: Assignment to bram_2_serverAdapterA_cnt_2$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3688: Assignment to bram_2_serverAdapterA_cnt_2$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3690: Assignment to bram_2_serverAdapterA_cnt_3$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3691: Assignment to bram_2_serverAdapterA_cnt_3$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3692: Assignment to bram_2_serverAdapterA_writeWithResp$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3700: Assignment to bram_2_serverAdapterA_s1_1$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3702: Assignment to bram_2_serverAdapterB_outData_enqData$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3716: Assignment to bram_2_serverAdapterB_cnt_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3722: Assignment to bram_2_serverAdapterB_cnt_2$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3723: Assignment to bram_2_serverAdapterB_cnt_2$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3725: Assignment to bram_2_serverAdapterB_cnt_3$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3726: Assignment to bram_2_serverAdapterB_cnt_3$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3727: Assignment to bram_2_serverAdapterB_writeWithResp$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3728: Assignment to bram_2_serverAdapterB_writeWithResp$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3732: Assignment to bram_2_serverAdapterB_s1_1$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3734: Assignment to bram_3_serverAdapterA_outData_enqData$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3748: Assignment to bram_3_serverAdapterA_cnt_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3755: Assignment to bram_3_serverAdapterA_cnt_2$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3756: Assignment to bram_3_serverAdapterA_cnt_2$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3758: Assignment to bram_3_serverAdapterA_cnt_3$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3759: Assignment to bram_3_serverAdapterA_cnt_3$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3760: Assignment to bram_3_serverAdapterA_writeWithResp$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3768: Assignment to bram_3_serverAdapterA_s1_1$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3770: Assignment to bram_3_serverAdapterB_outData_enqData$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3784: Assignment to bram_3_serverAdapterB_cnt_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3790: Assignment to bram_3_serverAdapterB_cnt_2$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3791: Assignment to bram_3_serverAdapterB_cnt_2$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3793: Assignment to bram_3_serverAdapterB_cnt_3$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3794: Assignment to bram_3_serverAdapterB_cnt_3$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3795: Assignment to bram_3_serverAdapterB_writeWithResp$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3796: Assignment to bram_3_serverAdapterB_writeWithResp$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3800: Assignment to bram_3_serverAdapterB_s1_1$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3808: Assignment to wci_wciReq$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3809: Assignment to wci_respF_x_wire$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3810: Assignment to wci_respF_x_wire$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3811: Assignment to wci_wEdge$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3812: Assignment to wci_wEdge$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3813: Assignment to wci_sFlagReg_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3814: Assignment to wci_sFlagReg_1$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3815: Assignment to wci_ctlAckReg_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3824: Assignment to wti_wtiReq$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3825: Assignment to wti_wtiReq$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3826: Assignment to wti_operateD_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3827: Assignment to wti_operateD_1$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3828: Assignment to tlp_remStart_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3833: Assignment to tlp_remDone_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3837: Assignment to tlp_nearBufReady_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3840: Assignment to tlp_farBufReady_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3843: Assignment to tlp_creditReady_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3846: Assignment to tlp_dpControl$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3847: Assignment to tlp_dpControl$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3855: Assignment to tlp_nowW$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3856: Assignment to tlp_nowW$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3857: Assignment to tlp_dmaStartMark_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3861: Assignment to tlp_dmaDoneMark_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3862: Assignment to tlp_dmaDoneMark_1$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3870: Assignment to wmi_wmi_wmiReq$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3871: Assignment to wmi_wmi_wmiMFlag$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3872: Assignment to wmi_wmi_wmiMFlag$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3878: Assignment to wmi_wmi_wmiDh$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3879: Assignment to wmi_wmi_respF_x_wire$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3880: Assignment to wmi_wmi_respF_x_wire$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3881: Assignment to wmi_wmi_operateD_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3882: Assignment to wmi_wmi_operateD_1$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3883: Assignment to wmi_wmi_peerIsReady_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3884: Assignment to wmi_wmi_peerIsReady_1$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3894: Assignment to wmi_mesgStart_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3896: Assignment to wmi_mesgDone_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3901: Assignment to wmi_mesgBufReady_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3904: Assignment to wmi_dpControl$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3905: Assignment to wmi_dpControl$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3907: Assignment to wmi_nowW$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3908: Assignment to bml_lclBufStart_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3909: Assignment to bml_lclBufStart_1$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3910: Assignment to bml_lclBufDone_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3911: Assignment to bml_lclBufDone_1$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3912: Assignment to bml_remStart_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3913: Assignment to bml_remStart_1$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3914: Assignment to bml_remDone_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3915: Assignment to bml_remDone_1$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3916: Assignment to bml_fabDone_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3920: Assignment to bml_fabAvail_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3924: Assignment to bml_datumAReg_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3925: Assignment to bml_datumAReg_1$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3926: Assignment to bml_dpControl$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3927: Assignment to bml_dpControl$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3928: Assignment to wci_Es_mCmd_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3929: Assignment to wci_Es_mCmd_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3930: Assignment to wci_Es_mAddrSpace_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3931: Assignment to wci_Es_mAddrSpace_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3932: Assignment to wci_Es_mByteEn_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3933: Assignment to wci_Es_mByteEn_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3934: Assignment to wci_Es_mAddr_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3935: Assignment to wci_Es_mAddr_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3936: Assignment to wci_Es_mData_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3937: Assignment to wci_Es_mData_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3938: Assignment to wmi_Es_mCmd_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3939: Assignment to wmi_Es_mCmd_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3940: Assignment to wmi_Es_mReqInfo_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3941: Assignment to wmi_Es_mReqInfo_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3942: Assignment to wmi_Es_mAddrSpace_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3943: Assignment to wmi_Es_mAddrSpace_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3944: Assignment to wmi_Es_mAddr_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3945: Assignment to wmi_Es_mAddr_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3946: Assignment to wmi_Es_mBurstLength_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3947: Assignment to wmi_Es_mBurstLength_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3948: Assignment to wmi_Es_mData_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3949: Assignment to wmi_Es_mData_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3950: Assignment to wmi_Es_mDataByteEn_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3951: Assignment to wmi_Es_mDataByteEn_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3964: Assignment to bram_1_serverAdapterB_outData_deqCalled$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3971: Assignment to bram_2_serverAdapterB_outData_deqCalled$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3978: Assignment to bram_3_serverAdapterB_outData_deqCalled$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3980: Assignment to wci_reqF_r_enq$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3984: Assignment to wci_reqF_r_clr$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3988: Assignment to wci_respF_dequeueing$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 3989: Assignment to wci_sThreadBusy_pw$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4002: Assignment to wmi_wmi_reqF_r_enq$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4004: Assignment to wmi_wmi_reqF_r_deq$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4005: Assignment to wmi_wmi_reqF_r_clr$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4006: Assignment to wmi_wmi_reqF_doResetEnq$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4008: Assignment to wmi_wmi_reqF_doResetDeq$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4009: Assignment to wmi_wmi_reqF_doResetClr$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4010: Assignment to wmi_wmi_mFlagF_r_enq$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4012: Assignment to wmi_wmi_mFlagF_r_deq$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4013: Assignment to wmi_wmi_mFlagF_r_clr$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4014: Assignment to wmi_wmi_mFlagF_doResetEnq$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4016: Assignment to wmi_wmi_mFlagF_doResetDeq$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4017: Assignment to wmi_wmi_mFlagF_doResetClr$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4018: Assignment to wmi_wmi_dhF_r_enq$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4019: Assignment to wmi_wmi_dhF_r_deq$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4020: Assignment to wmi_wmi_dhF_r_clr$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4021: Assignment to wmi_wmi_dhF_doResetEnq$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4023: Assignment to wmi_wmi_dhF_doResetDeq$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4024: Assignment to wmi_wmi_dhF_doResetClr$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4025: Assignment to wmi_wmi_respF_enqueueing$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4026: Assignment to wmi_wmi_respF_dequeueing$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4027: Assignment to bml_lclBuf_incAction$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4028: Assignment to bml_lclBuf_decAction$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4029: Assignment to bml_remBuf_incAction$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4030: Assignment to bml_remBuf_decAction$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4031: Assignment to bml_fabBuf_incAction$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4032: Assignment to bml_fabBuf_decAction$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4033: Assignment to bml_crdBuf_incAction$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4034: Assignment to bml_crdBuf_decAction$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4035: Assignment to wmi_Es_mReqLast_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4036: Assignment to wmi_Es_mDataValid_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4037: Assignment to wmi_Es_mDataLast_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4038: Assignment to wmi_Es_mDataInfo_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4039: Assignment to bml_lclBuf_modulus_bw$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4040: Assignment to bml_remBuf_modulus_bw$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4041: Assignment to bml_fabBuf_modulus_bw$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4042: Assignment to bml_crdBuf_modulus_bw$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4100: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4512: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4581: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4649: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4754: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4779: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4835: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4878: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 4914: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5067: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5091: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5220: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5240: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5487: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5511: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5581: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5599: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5616: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5633: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5699: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5717: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5734: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5751: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5817: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5835: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5852: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5869: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5935: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5953: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5970: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 5987: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 6072: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 6129: Found parallel_case directive in module mkOCDP16B. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" Line 7301: Assignment to bml_datumAReg ignored, since the identifier is never used + +Elaborating module . +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkTimeClient.v" Line 118: Assignment to wti_peerIsReady_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkTimeClient.v" Line 119: Assignment to wti_peerIsReady_1$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkTimeClient.v" Line 120: Assignment to wti_sThreadBusy_pw$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkTimeClient.v" Line 140: Assignment to wti_peerIsReady ignored, since the identifier is never used + +Elaborating module . + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkPktMerge.v" Line 198: Found parallel_case directive in module mkPktMerge. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkPktMerge.v" Line 240: Found parallel_case directive in module mkPktMerge. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkCTop16B.v" Line 1691: Assignment to wtiM_0_peerIsReady_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkCTop16B.v" Line 1692: Assignment to wtiM_0_peerIsReady_1$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkCTop16B.v" Line 1693: Assignment to wtiM_1_peerIsReady_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkCTop16B.v" Line 1694: Assignment to wtiM_1_peerIsReady_1$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkCTop16B.v" Line 1695: Assignment to wtiM_2_peerIsReady_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkCTop16B.v" Line 1696: Assignment to wtiM_2_peerIsReady_1$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkCTop16B.v" Line 1697: Assignment to wtiM_0_sThreadBusy_pw$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkCTop16B.v" Line 1698: Assignment to wtiM_1_sThreadBusy_pw$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkCTop16B.v" Line 1699: Assignment to wtiM_2_sThreadBusy_pw$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkCTop16B.v" Line 1918: Assignment to wtiM_0_peerIsReady ignored, since the identifier is never used +WARNING:HDLCompiler:552 - "/home/shep/projects/ocpi/rtl/mkCTop16B.v" Line 1483: Input port EN_uuid is not connected on this instance +WARNING:HDLCompiler:1016 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1202: Port sda is not connected to this instance + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:1016 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/v6_mig37_patch20110411.v" Line 376: Port pd_PSEN is not connected to this instance + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/v6_mig37_patch20110411.v" Line 312: Assignment to sys_clk_p ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/v6_mig37_patch20110411.v" Line 313: Assignment to sys_clk_n ignored, since the identifier is never used + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/v6_mig37_patch20110411.v" Line 370: Assignment to ocb_mon_PSDONE ignored, since the identifier is never used +WARNING:HDLCompiler:597 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/v6_mig37_patch20110411.v" Line 392: Module memc_ui_top does not have a parameter named OCB_MONITOR +WARNING:HDLCompiler:597 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/v6_mig37_patch20110411.v" Line 402: Module memc_ui_top does not have a parameter named SIM_CAL_OPTION +WARNING:HDLCompiler:597 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/v6_mig37_patch20110411.v" Line 403: Module memc_ui_top does not have a parameter named SIM_INIT_OPTION + +Elaborating module . + +Elaborating module +. +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ip_top/mem_intfc.v" Line 386: Assignment to dfi_odt_nom0_r3 ignored, since the identifier is never used +WARNING:HDLCompiler:91 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ip_top/mem_intfc.v" Line 432: Signal missing in the sensitivity list is added for synthesis purposes. HDL and post-synthesis simulations may differ as a result. + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/rank_cntrl.v" Line 146: Net does not have a driver. + +Elaborating module . + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/round_robin_arb.v" Line 153: Net does not have a driver. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/mc.v" Line 443: Result of 64-bit expression is truncated to fit in 8-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/mc.v" Line 444: Result of 64-bit expression is truncated to fit in 8-bit target. + +Elaborating module . + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_compare.v" Line 168: Net does not have a driver. +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_compare.v" Line 169: Net does not have a driver. +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_compare.v" Line 201: Net does not have a driver. + +Elaborating module . +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_state.v" Line 293: Net does not have a driver. +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_state.v" Line 294: Net does not have a driver. +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_state.v" Line 297: Net does not have a driver. + +Elaborating module . +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_queue.v" Line 477: Net does not have a driver. + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_state.v" Line 293: Net does not have a driver. +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_state.v" Line 294: Net does not have a driver. +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_state.v" Line 297: Net does not have a driver. + +Elaborating module . +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_queue.v" Line 477: Net does not have a driver. + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_state.v" Line 293: Net does not have a driver. +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_state.v" Line 294: Net does not have a driver. +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_state.v" Line 297: Net does not have a driver. + +Elaborating module . +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_queue.v" Line 477: Net does not have a driver. + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_state.v" Line 293: Net does not have a driver. +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_state.v" Line 294: Net does not have a driver. +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_state.v" Line 297: Net does not have a driver. + +Elaborating module . +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_queue.v" Line 477: Net does not have a driver. + +Elaborating module . +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_common.v" Line 426: Result of 32-bit expression is truncated to fit in 6-bit target. + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/arb_select.v" Line 140: Net does not have a driver. +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/arb_select.v" Line 198: Net does not have a driver. +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/arb_select.v" Line 204: Net does not have a driver. + +Elaborating module . +WARNING:HDLCompiler:532 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/col_mach.v" Line 323: Index <13> is out of range [12:0] for signal . + +Elaborating module . +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/col_mach.v" Line 151: Net does not have a driver. + +Elaborating module . +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_top.v" Line 506: Result of 32-bit expression is truncated to fit in 5-bit target. + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_init.v" Line 764: Result of 32-bit expression is truncated to fit in 5-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_init.v" Line 854: Result of 8-bit expression is truncated to fit in 7-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_init.v" Line 879: Result of 11-bit expression is truncated to fit in 10-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_init.v" Line 888: Result of 10-bit expression is truncated to fit in 9-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_init.v" Line 935: Result of 9-bit expression is truncated to fit in 8-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_init.v" Line 950: Result of 9-bit expression is truncated to fit in 8-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_init.v" Line 966: Result of 9-bit expression is truncated to fit in 8-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_init.v" Line 987: Result of 3-bit expression is truncated to fit in 2-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_init.v" Line 1038: Result of 3-bit expression is truncated to fit in 2-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_init.v" Line 1051: Result of 4-bit expression is truncated to fit in 3-bit target. +WARNING:HDLCompiler:91 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_init.v" Line 1179: Signal missing in the sensitivity list is added for synthesis purposes. HDL and post-synthesis simulations may differ as a result. +WARNING:HDLCompiler:91 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_init.v" Line 1208: Signal missing in the sensitivity list is added for synthesis purposes. HDL and post-synthesis simulations may differ as a result. +WARNING:HDLCompiler:1308 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_init.v" Line 1083: Found full_case directive in module phy_init. Use of full_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_init.v" Line 1561: Result of 3-bit expression is truncated to fit in 2-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_init.v" Line 1573: Result of 3-bit expression is truncated to fit in 2-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_init.v" Line 1657: Result of 3-bit expression is truncated to fit in 2-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_init.v" Line 1735: Result of 5-bit expression is truncated to fit in 4-bit target. +WARNING:HDLCompiler:1308 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_init.v" Line 1745: Found full_case directive in module phy_init. Use of full_case directives may cause differences between RTL and post-synthesis simulation + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" Line 232: Assignment to rst_r ignored, since the identifier is never used + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_dqs_iob.v" Line 152: Assignment to dqs_ibuf_n ignored, since the identifier is never used + +Elaborating module . + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_dqs_iob.v" Line 288: Assignment to dqs_n_tfb ignored, since the identifier is never used + +Elaborating module . + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_dm_iob.v" Line 147: Assignment to mask_data_rise0_r4 ignored, since the identifier is never used + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_dq_iob.v" Line 239: Assignment to wr_data_rise0_r4 ignored, since the identifier is never used + +Elaborating module . +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_dly_ctrl.v" Line 199: Assignment to dqs_oe_r ignored, since the identifier is never used + +Elaborating module . +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_write.v" Line 269: Assignment to wrdata_en_r7 ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_write.v" Line 1549: Assignment to wrlvl_done_r3 ignored, since the identifier is never used +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_write.v" Line 1634: Result of 3-bit expression is truncated to fit in 2-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_write.v" Line 1758: Result of 32-bit expression is truncated to fit in 8-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_write.v" Line 1761: Result of 32-bit expression is truncated to fit in 8-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_write.v" Line 1764: Result of 32-bit expression is truncated to fit in 8-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_write.v" Line 1767: Result of 32-bit expression is truncated to fit in 8-bit target. + +Elaborating module . +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_wrlvl.v" Line 284: Result of 3-bit expression is truncated to fit in 2-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_wrlvl.v" Line 298: Result of 3-bit expression is truncated to fit in 2-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_wrlvl.v" Line 523: Result of 32-bit expression is truncated to fit in 5-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_wrlvl.v" Line 540: Result of 32-bit expression is truncated to fit in 5-bit target. +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_wrlvl.v" Line 453: Assignment to wl_state_r1 ignored, since the identifier is never used + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdclk_gen.v" Line 310: Result of 5-bit expression is truncated to fit in 4-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdclk_gen.v" Line 324: Result of 5-bit expression is truncated to fit in 4-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdclk_gen.v" Line 331: Result of 5-bit expression is truncated to fit in 4-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdclk_gen.v" Line 339: Result of 5-bit expression is truncated to fit in 4-bit target. +WARNING:HDLCompiler:1308 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdclk_gen.v" Line 301: Found full_case directive in module phy_rdclk_gen. Use of full_case directives may cause differences between RTL and post-synthesis simulation + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdclk_gen.v" Line 173: Net does not have a driver. +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdclk_gen.v" Line 180: Net does not have a driver. + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdctrl_sync.v" Line 163: Result of 10-bit expression is truncated to fit in 9-bit target. + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/circ_buffer.v" Line 143: Result of 4-bit expression is truncated to fit in 3-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/circ_buffer.v" Line 170: Result of 4-bit expression is truncated to fit in 3-bit target. + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/circ_buffer.v" Line 143: Result of 4-bit expression is truncated to fit in 3-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/circ_buffer.v" Line 170: Result of 4-bit expression is truncated to fit in 3-bit target. + +Elaborating module . +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 566: Result of 8-bit expression is truncated to fit in 4-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 647: Result of 5-bit expression is truncated to fit in 4-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 707: Result of 5-bit expression is truncated to fit in 4-bit target. +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 878: Assignment to prev_found_edge_valid_r ignored, since the identifier is never used +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 918: Result of 13-bit expression is truncated to fit in 12-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 946: Result of 13-bit expression is truncated to fit in 12-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 1025: Result of 4-bit expression is truncated to fit in 3-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 1046: Result of 6-bit expression is truncated to fit in 5-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 1048: Result of 32-bit expression is truncated to fit in 5-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 1167: Result of 32-bit expression is truncated to fit in 5-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 1179: Result of 32-bit expression is truncated to fit in 5-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 1283: Result of 32-bit expression is truncated to fit in 6-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 1292: Result of 32-bit expression is truncated to fit in 6-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 1296: Result of 32-bit expression is truncated to fit in 6-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 1317: Result of 32-bit expression is truncated to fit in 6-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 1343: Result of 4-bit expression is truncated to fit in 3-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 1356: Result of 6-bit expression is truncated to fit in 5-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 1357: Result of 6-bit expression is truncated to fit in 5-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 1372: Result of 32-bit expression is truncated to fit in 6-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 1395: Result of 32-bit expression is truncated to fit in 5-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 1405: Result of 6-bit expression is truncated to fit in 5-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 1413: Result of 6-bit expression is truncated to fit in 5-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 1479: Result of 6-bit expression is truncated to fit in 5-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 1481: Result of 6-bit expression is truncated to fit in 5-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 1483: Result of 6-bit expression is truncated to fit in 5-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 1497: Result of 32-bit expression is truncated to fit in 5-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 1525: Result of 32-bit expression is truncated to fit in 5-bit target. +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 1073: Assignment to found_two_edge_r ignored, since the identifier is never used +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 1541: Result of 31-bit expression is truncated to fit in 6-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 1650: Result of 4-bit expression is truncated to fit in 3-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 1784: Result of 6-bit expression is truncated to fit in 5-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 1809: Result of 32-bit expression is truncated to fit in 5-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 1880: Result of 4-bit expression is truncated to fit in 3-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 1974: Result of 6-bit expression is truncated to fit in 5-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 1984: Result of 3-bit expression is truncated to fit in 2-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 1995: Result of 3-bit expression is truncated to fit in 2-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 2037: Result of 4-bit expression is truncated to fit in 3-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v" Line 2091: Result of 32-bit expression is truncated to fit in 5-bit target. + +Elaborating module . +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_pd_top.v" Line 275: Result of 32-bit expression is truncated to fit in 4-bit target. + +Elaborating module . +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_pd.v" Line 199: Result of 32-bit expression is truncated to fit in 4-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_pd.v" Line 229: Result of 32-bit expression is truncated to fit in 4-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_pd.v" Line 416: Result of 6-bit expression is truncated to fit in 5-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_pd.v" Line 417: Result of 32-bit expression is truncated to fit in 5-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_pd.v" Line 593: Result of 5-bit expression is truncated to fit in 4-bit target. +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_top.v" Line 977: Net does not have a driver. +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ip_top/memc_ui_top.v" Line 568: Assignment to ecc_single ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ip_top/memc_ui_top.v" Line 570: Assignment to ecc_err_addr ignored, since the identifier is never used + +Elaborating module . + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ui/ui_wr_data.v" Line 232: Result of 5-bit expression is truncated to fit in 4-bit target. + +Elaborating module . +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ui/ui_rd_data.v" Line 199: Net does not have a driver. +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ip_top/memc_ui_top.v" Line 620: Assignment to hi_priority ignored, since the identifier is never used +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ip_top/memc_ui_top.v" Line 377: Net does not have a driver. +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ip_top/memc_ui_top.v" Line 378: Net does not have a driver. +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ip_top/memc_ui_top.v" Line 396: Net does not have a driver. +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/v6_mig37_patch20110411.v" Line 435: Assignment to ddr3_parity ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/v6_mig37_patch20110411.v" Line 442: Assignment to bank_mach_next ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/v6_mig37_patch20110411.v" Line 446: Assignment to app_ecc_multiple_err_i ignored, since the identifier is never used +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/v6_mig37_patch20110411.v" Line 267: Net does not have a driver. +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/v6_mig37_patch20110411.v" Line 268: Net does not have a driver. +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/v6_mig37_patch20110411.v" Line 298: Net does not have a driver. +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/v6_mig37_patch20110411.v" Line 306: Net does not have a driver. +WARNING:HDLCompiler:552 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/v6_mig37_patch20110411.v" Line 422: Input port pd_PSDONE is not connected on this instance +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1205: Size mismatch in connection of port . Formal port size is 27-bit while actual signal size is 33-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1254: Size mismatch in connection of port . Formal port size is 256-bit while actual signal size is 32-bit. + +Elaborating module . +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/libsrc/hdl/ocpi/arSRLFIFOD.v" Line 62: Result of 32-bit expression is truncated to fit in 4-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/libsrc/hdl/ocpi/arSRLFIFOD.v" Line 63: Result of 5-bit expression is truncated to fit in 4-bit target. + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/libsrc/hdl/ocpi/arSRLFIFOD.v" Line 62: Result of 32-bit expression is truncated to fit in 4-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/libsrc/hdl/ocpi/arSRLFIFOD.v" Line 63: Result of 5-bit expression is truncated to fit in 4-bit target. + +Elaborating module . + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1599: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1645: Assignment to wci_wslv_wciReq$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1646: Assignment to wci_wslv_respF_x_wire$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1652: Assignment to wci_wslv_wEdge$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1653: Assignment to wci_wslv_wEdge$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1654: Assignment to wci_wslv_sFlagReg_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1655: Assignment to wci_wslv_sFlagReg_1$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1656: Assignment to wci_wslv_ctlAckReg_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1660: Assignment to wci_wci_Es_mCmd_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1661: Assignment to wci_wci_Es_mCmd_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1662: Assignment to wci_wci_Es_mAddrSpace_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1663: Assignment to wci_wci_Es_mAddrSpace_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1664: Assignment to wci_wci_Es_mByteEn_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1665: Assignment to wci_wci_Es_mByteEn_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1666: Assignment to wci_wci_Es_mAddr_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1667: Assignment to wci_wci_Es_mAddr_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1668: Assignment to wci_wci_Es_mData_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1669: Assignment to wci_wci_Es_mData_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1670: Assignment to memc_wdfWren$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1674: Assignment to memc_wdfEnd$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1675: Assignment to memc_wdfEnd$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1681: Assignment to wmemi_wmemiReq$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1687: Assignment to wmemi_wmemiDh$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1688: Assignment to wmemi_cmdAccept_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1693: Assignment to wmemi_dhAccept_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1698: Assignment to wmemi_respF_x_wire$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1699: Assignment to wmemi_respF_x_wire$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1700: Assignment to wmemi_operateD_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1701: Assignment to wmemi_operateD_1$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1702: Assignment to wmemi_peerIsReady_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1703: Assignment to wmemi_peerIsReady_1$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1704: Assignment to wmemiReadInFlight_acc_v1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1708: Assignment to wmemiReadInFlight_acc_v2$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1709: Assignment to wmemiReadInFlight_acc_v2$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1710: Assignment to wmemi_Es_mCmd_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1711: Assignment to wmemi_Es_mCmd_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1712: Assignment to wmemi_Es_mAddr_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1713: Assignment to wmemi_Es_mAddr_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1714: Assignment to wmemi_Es_mBurstLength_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1715: Assignment to wmemi_Es_mBurstLength_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1716: Assignment to wmemi_Es_mData_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1717: Assignment to wmemi_Es_mData_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1718: Assignment to wmemi_Es_mDataByteEn_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1719: Assignment to wmemi_Es_mDataByteEn_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1720: Assignment to wci_wslv_reqF_r_enq$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1724: Assignment to wci_wslv_reqF_r_clr$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1730: Assignment to wci_wslv_respF_dequeueing$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1731: Assignment to wci_wslv_sThreadBusy_pw$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1745: Assignment to wmemi_respF_dequeueing$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1746: Assignment to wmemi_Es_mReqLast_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1747: Assignment to wmemi_Es_mDataValid_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1748: Assignment to wmemi_Es_mDataLast_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1928: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 1952: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 2053: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 2075: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 2221: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 2669: Assignment to pioReadInFlight ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" Line 2789: Assignment to dbgCtrl ignored, since the identifier is never used + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 915: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 948: Assignment to wci_wslv_wciReq$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 949: Assignment to wci_wslv_respF_x_wire$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 955: Assignment to wci_wslv_wEdge$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 956: Assignment to wci_wslv_wEdge$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 957: Assignment to wci_wslv_sFlagReg_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 958: Assignment to wci_wslv_sFlagReg_1$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 959: Assignment to wci_wslv_ctlAckReg_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 963: Assignment to wci_wci_Es_mCmd_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 964: Assignment to wci_wci_Es_mCmd_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 965: Assignment to wci_wci_Es_mAddrSpace_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 966: Assignment to wci_wci_Es_mAddrSpace_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 967: Assignment to wci_wci_Es_mByteEn_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 968: Assignment to wci_wci_Es_mByteEn_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 969: Assignment to wci_wci_Es_mAddr_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 970: Assignment to wci_wci_Es_mAddr_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 971: Assignment to wci_wci_Es_mData_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 972: Assignment to wci_wci_Es_mData_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 973: Assignment to flashC_rseqFsm_start_wire$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 977: Assignment to flashC_rseqFsm_start_reg_2$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 978: Assignment to flashC_rseqFsm_start_reg_2$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 979: Assignment to flashC_rseqFsm_abort$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 980: Assignment to flashC_rseqFsm_abort$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 981: Assignment to flashC_rseqFsm_state_fired_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 982: Assignment to flashC_rseqFsm_state_fired_1$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 984: Assignment to flashC_wseqFsm_start_wire$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 988: Assignment to flashC_wseqFsm_start_reg_2$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 989: Assignment to flashC_wseqFsm_start_reg_2$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 990: Assignment to flashC_wseqFsm_abort$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 991: Assignment to flashC_wseqFsm_abort$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 992: Assignment to flashC_wseqFsm_state_fired_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 993: Assignment to flashC_wseqFsm_state_fired_1$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 995: Assignment to wci_wslv_reqF_r_enq$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 999: Assignment to wci_wslv_reqF_r_clr$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 1005: Assignment to wci_wslv_respF_dequeueing$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 1006: Assignment to wci_wslv_sThreadBusy_pw$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 1025: Assignment to flashC_rseqFsm_state_overlap_pw$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 1052: Assignment to flashC_wseqFsm_state_overlap_pw$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 1127: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 1268: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 1446: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 1470: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" Line 1586: Assignment to flashC_wdReg ignored, since the identifier is never used + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/libsrc/hdl/bsv/ClockDiv.v" Line 106: Result of 4-bit expression is truncated to fit in 3-bit target. + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/libsrc/hdl/bsv/ClockDiv.v" Line 106: Result of 5-bit expression is truncated to fit in 4-bit target. +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1227: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1264: Assignment to wci_wslv_wciReq$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1265: Assignment to wci_wslv_respF_x_wire$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1273: Assignment to wci_wslv_wEdge$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1274: Assignment to wci_wslv_wEdge$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1275: Assignment to wci_wslv_sFlagReg_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1276: Assignment to wci_wslv_sFlagReg_1$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1277: Assignment to wci_wslv_ctlAckReg_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1281: Assignment to wci_wci_Es_mCmd_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1282: Assignment to wci_wci_Es_mCmd_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1283: Assignment to wci_wci_Es_mAddrSpace_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1284: Assignment to wci_wci_Es_mAddrSpace_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1285: Assignment to wci_wci_Es_mByteEn_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1286: Assignment to wci_wci_Es_mByteEn_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1287: Assignment to wci_wci_Es_mAddr_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1288: Assignment to wci_wci_Es_mAddr_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1289: Assignment to wci_wci_Es_mData_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1290: Assignment to wci_wci_Es_mData_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1297: Assignment to spiCDC_csbR_1$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1298: Assignment to spiCDC_doResp_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1302: Assignment to spiDAC_cGate_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1305: Assignment to spiDAC_csbR_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1306: Assignment to spiDAC_csbR_1$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1314: Assignment to fcCdc_pulseAction_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1315: Assignment to fcCdc_pulseAction_1$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1316: Assignment to wci_wslv_reqF_r_enq$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1320: Assignment to wci_wslv_reqF_r_clr$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1328: Assignment to wci_wslv_respF_dequeueing$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1329: Assignment to wci_wslv_sThreadBusy_pw$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1342: Assignment to spiCDC_reqF_deq_pw$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1343: Assignment to spiCDC_reqF_sClear_pw$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1344: Assignment to spiCDC_reqF_dClear_pw$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1345: Assignment to spiCDC_reqF_deq_happened$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1346: Assignment to spiCDC_respF_enq_pw$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1347: Assignment to spiCDC_respF_deq_pw$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1348: Assignment to spiCDC_respF_sClear_pw$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1349: Assignment to spiCDC_respF_dClear_pw$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1350: Assignment to spiCDC_respF_deq_happened$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1354: Assignment to spiDAC_reqF_deq_pw$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1355: Assignment to spiDAC_reqF_sClear_pw$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1356: Assignment to spiDAC_reqF_dClear_pw$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1357: Assignment to spiDAC_reqF_deq_happened$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1358: Assignment to spiDAC_respF_enq_pw$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1359: Assignment to spiDAC_respF_deq_pw$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1360: Assignment to spiDAC_respF_sClear_pw$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1361: Assignment to spiDAC_respF_dClear_pw$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1362: Assignment to spiDAC_respF_deq_happened$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1363: Assignment to fcCdc_grayCounter_pwIncrement$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1364: Assignment to fcCdc_grayCounter_pwDecrement$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1365: Assignment to oneKHz_incAction$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1366: Assignment to oneKHz_decAction$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1367: Assignment to spiCDC_sdiWs$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1368: Assignment to spiDAC_sdiWs$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1369: Assignment to fcCdc_grayCounter_wdCounterCrossing$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1719: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 1743: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" Line 2023: Assignment to splitReadInFlight ignored, since the identifier is never used + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" Line 614: Assignment to gmii_rx_clk$O ignored, since the identifier is never used + +Elaborating module . +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" Line 622: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" Line 623: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" Line 624: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" Line 625: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" Line 626: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" Line 627: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" Line 628: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" Line 1023: Assignment to rxRS_rxOperateD_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" Line 1024: Assignment to rxRS_rxOperateD_1$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" Line 1025: Assignment to txRS_txOperateD_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" Line 1026: Assignment to txRS_txOperateD_1$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" Line 1035: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" Line 1051: Assignment to txRS_txDV_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" Line 1056: Assignment to txRS_txER_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" Line 1057: Assignment to txRS_txER_1$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" Line 1058: Assignment to txRS_underflow_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" Line 1059: Assignment to txRS_underflow_1$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" Line 1062: Assignment to rxRS_preambleCnt_decAction$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" Line 1065: Assignment to rxRS_crcDbgCnt_decAction$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" Line 1066: Assignment to txRS_preambleCnt_incAction$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" Line 1067: Assignment to txRS_preambleCnt_decAction$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" Line 1068: Assignment to txRS_ifgCnt_incAction$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" Line 1078: Assignment to txRS_lenCnt_decAction$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" Line 1085: Assignment to txRS_crcDbgCnt_decAction$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" Line 1437: Assignment to txRS_underflow ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" Line 1485: Assignment to rxRS_isSOF ignored, since the identifier is never used + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1768: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1802: Assignment to wci_wslv_wciReq$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1803: Assignment to wci_wslv_respF_x_wire$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1809: Assignment to wci_wslv_wEdge$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1810: Assignment to wci_wslv_wEdge$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1811: Assignment to wci_wslv_sFlagReg_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1812: Assignment to wci_wslv_sFlagReg_1$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1813: Assignment to wci_wslv_ctlAckReg_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1817: Assignment to wci_wci_Es_mCmd_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1818: Assignment to wci_wci_Es_mCmd_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1819: Assignment to wci_wci_Es_mAddrSpace_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1820: Assignment to wci_wci_Es_mAddrSpace_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1821: Assignment to wci_wci_Es_mByteEn_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1822: Assignment to wci_wci_Es_mByteEn_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1823: Assignment to wci_wci_Es_mAddr_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1824: Assignment to wci_wci_Es_mAddr_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1825: Assignment to wci_wci_Es_mData_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1826: Assignment to wci_wci_Es_mData_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1827: Assignment to wti_wtiReq$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1828: Assignment to wti_wtiReq$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1829: Assignment to wti_operateD_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1830: Assignment to wti_operateD_1$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1831: Assignment to wsiM_reqFifo_x_wire$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1832: Assignment to wsiM_reqFifo_x_wire$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1833: Assignment to wsiM_operateD_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1836: Assignment to wsiM_peerIsReady_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1837: Assignment to wsiM_peerIsReady_1$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1846: Assignment to wsiS_wsiReq$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1847: Assignment to wsiS_operateD_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1848: Assignment to wsiS_operateD_1$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1849: Assignment to wsiS_peerIsReady_1$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1850: Assignment to wsiS_peerIsReady_1$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1854: Assignment to wsi_Es_mCmd_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1855: Assignment to wsi_Es_mCmd_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1856: Assignment to wsi_Es_mBurstLength_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1857: Assignment to wsi_Es_mBurstLength_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1858: Assignment to wsi_Es_mData_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1859: Assignment to wsi_Es_mData_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1860: Assignment to wsi_Es_mByteEn_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1861: Assignment to wsi_Es_mByteEn_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1862: Assignment to wsi_Es_mReqInfo_w$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1863: Assignment to wsi_Es_mReqInfo_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1864: Assignment to wci_wslv_reqF_r_enq$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1868: Assignment to wci_wslv_reqF_r_clr$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1874: Assignment to wci_wslv_respF_dequeueing$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1875: Assignment to wci_wslv_sThreadBusy_pw$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1885: Assignment to wsiM_reqFifo_enqueueing$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1886: Assignment to wsiM_reqFifo_dequeueing$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1887: Assignment to wsiM_sThreadBusy_pw$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1888: Assignment to wsiS_reqFifo_r_enq$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1889: Assignment to wsiS_reqFifo_r_deq$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1891: Assignment to wsiS_reqFifo_r_clr$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1892: Assignment to wsiS_reqFifo_doResetEnq$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1893: Assignment to wsiS_reqFifo_doResetDeq$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1895: Assignment to wsiS_reqFifo_doResetClr$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1896: Assignment to mdi_pwTick$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1897: Assignment to wsi_Es_mReqLast_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1898: Assignment to wsi_Es_mBurstPrecise_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 1899: Assignment to wsi_Es_mDataInfo_w$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 2341: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1311 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 2365: Found parallel_case directive. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 3497: Assignment to txDBGPos ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" Line 3755: Assignment to wti_nowReq ignored, since the identifier is never used + +Elaborating module . +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkLCDController.v" Line 1806: Found parallel_case directive in module mkLCDController. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkLCDController.v" Line 1877: Found parallel_case directive in module mkLCDController. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkLCDController.v" Line 1923: Found parallel_case directive in module mkLCDController. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkLCDController.v" Line 2064: Found parallel_case directive in module mkLCDController. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkLCDController.v" Line 2278: Found parallel_case directive in module mkLCDController. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkLCDController.v" Line 2746: Found parallel_case directive in module mkLCDController. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation +WARNING:HDLCompiler:1310 - "/home/shep/projects/ocpi/rtl/mkLCDController.v" Line 2822: Found parallel_case directive in module mkLCDController. Use of parallel_case directives may cause differences between RTL and post-synthesis simulation + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" Line 719: Assignment to block_clk ignored, since the identifier is never used + +Elaborating module +. + +Elaborating module +. +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_2_0_v6.v" Line 1166: Assignment to LL2BADDLLPERRN ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_2_0_v6.v" Line 1167: Assignment to LL2BADTLPERRN ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_2_0_v6.v" Line 1168: Assignment to LL2PROTOCOLERRN ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_2_0_v6.v" Line 1169: Assignment to LL2REPLAYROERRN ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_2_0_v6.v" Line 1170: Assignment to LL2REPLAYTOERRN ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_2_0_v6.v" Line 1171: Assignment to LL2SUSPENDOKN ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_2_0_v6.v" Line 1172: Assignment to LL2TFCINIT1SEQN ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_2_0_v6.v" Line 1173: Assignment to LL2TFCINIT2SEQN ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_2_0_v6.v" Line 1252: Assignment to PL2LINKUPN ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_2_0_v6.v" Line 1253: Assignment to PL2RECEIVERERRN ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_2_0_v6.v" Line 1254: Assignment to PL2RECOVERYN ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_2_0_v6.v" Line 1255: Assignment to PL2RXELECIDLE ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_2_0_v6.v" Line 1256: Assignment to PL2SUSPENDOK ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_2_0_v6.v" Line 1259: Assignment to TL2ASPMSUSPENDCREDITCHECKOKN ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_2_0_v6.v" Line 1260: Assignment to TL2ASPMSUSPENDREQN ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_2_0_v6.v" Line 1261: Assignment to TL2PPMSUSPENDOKN ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_2_0_v6.v" Line 1273: Assignment to TRNRDLLPSRCRDYN ignored, since the identifier is never used + +Elaborating module . + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_pipe_v6.v" Line 336: Net does not have a driver. +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_pipe_v6.v" Line 337: Net does not have a driver. +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_pipe_v6.v" Line 338: Net does not have a driver. +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_pipe_v6.v" Line 339: Net does not have a driver. +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_pipe_v6.v" Line 340: Net does not have a driver. +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_pipe_v6.v" Line 341: Net does not have a driver. +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_pipe_v6.v" Line 342: Net does not have a driver. +WARNING:HDLCompiler:634 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_pipe_v6.v" Line 343: Net does not have a driver. + +Elaborating module . + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_drp_chanalign_fix_3752_v6.v" Line 180: Result of 9-bit expression is truncated to fit in 8-bit target. +WARNING:HDLCompiler:413 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_drp_chanalign_fix_3752_v6.v" Line 229: Result of 9-bit expression is truncated to fit in 8-bit target. + +Elaborating module . + +Elaborating module . + +Elaborating module +. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 473: Size mismatch in connection of port . Formal port size is 5-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 487: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 488: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 496: Size mismatch in connection of port . Formal port size is 2-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 497: Size mismatch in connection of port . Formal port size is 2-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 563: Size mismatch in connection of port . Formal port size is 2-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 564: Size mismatch in connection of port . Formal port size is 2-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 587: Size mismatch in connection of port . Formal port size is 3-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 589: Size mismatch in connection of port . Formal port size is 3-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 604: Size mismatch in connection of port . Formal port size is 5-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 606: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 607: Size mismatch in connection of port . Formal port size is 4-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 612: Size mismatch in connection of port . Formal port size is 7-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 613: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 617: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 618: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 619: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 620: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 623: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 473: Size mismatch in connection of port . Formal port size is 5-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 487: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 488: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 496: Size mismatch in connection of port . Formal port size is 2-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 497: Size mismatch in connection of port . Formal port size is 2-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 563: Size mismatch in connection of port . Formal port size is 2-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 564: Size mismatch in connection of port . Formal port size is 2-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 587: Size mismatch in connection of port . Formal port size is 3-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 589: Size mismatch in connection of port . Formal port size is 3-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 604: Size mismatch in connection of port . Formal port size is 5-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 606: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 607: Size mismatch in connection of port . Formal port size is 4-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 612: Size mismatch in connection of port . Formal port size is 7-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 613: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 617: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 618: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 619: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 620: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 623: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 473: Size mismatch in connection of port . Formal port size is 5-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 487: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 488: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 496: Size mismatch in connection of port . Formal port size is 2-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 497: Size mismatch in connection of port . Formal port size is 2-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 563: Size mismatch in connection of port . Formal port size is 2-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 564: Size mismatch in connection of port . Formal port size is 2-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 587: Size mismatch in connection of port . Formal port size is 3-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 589: Size mismatch in connection of port . Formal port size is 3-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 604: Size mismatch in connection of port . Formal port size is 5-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 606: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 607: Size mismatch in connection of port . Formal port size is 4-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 612: Size mismatch in connection of port . Formal port size is 7-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 613: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 617: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 618: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 619: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 620: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 623: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 473: Size mismatch in connection of port . Formal port size is 5-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 487: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 488: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 496: Size mismatch in connection of port . Formal port size is 2-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 497: Size mismatch in connection of port . Formal port size is 2-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 563: Size mismatch in connection of port . Formal port size is 2-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 564: Size mismatch in connection of port . Formal port size is 2-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 587: Size mismatch in connection of port . Formal port size is 3-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 589: Size mismatch in connection of port . Formal port size is 3-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 604: Size mismatch in connection of port . Formal port size is 5-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 606: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 607: Size mismatch in connection of port . Formal port size is 4-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 612: Size mismatch in connection of port . Formal port size is 7-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 613: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 617: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 618: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 619: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 620: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" Line 623: Size mismatch in connection of port . Formal port size is 1-bit while actual signal size is 32-bit. + +Elaborating module . +"/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_bram_top_v6.v" Line 126. $display [ $time ] pcie_bram_top_v6 ROWS_TX 1 COLS_TX 4 +"/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_bram_top_v6.v" Line 127. $display [ $time ] pcie_bram_top_v6 ROWS_RX 1 COLS_RX 4 + +Elaborating module . +WARNING:HDLCompiler:1016 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_bram_v6.v" Line 257: Port DOPB is not connected to this instance + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_2_0_v6.v" Line 1886: Size mismatch in connection of port . Formal port size is 72-bit while actual signal size is 69-bit. +WARNING:HDLCompiler:189 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_2_0_v6.v" Line 1894: Size mismatch in connection of port . Formal port size is 72-bit while actual signal size is 68-bit. + +Elaborating module . +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" Line 986: Assignment to rx_func_level_reset_n ignored, since the identifier is never used + +Elaborating module . + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 1869: Assignment to pciw_pci0_wTrnTxSof_n$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 1870: Assignment to pciw_pci0_wTrnTxSof_n$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 1871: Assignment to pciw_pci0_wTrnTxEof_n$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 1872: Assignment to pciw_pci0_wTrnTxEof_n$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 1873: Assignment to pciw_pci0_wTrnTxDsc_n$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 1874: Assignment to pciw_pci0_wTrnTxDsc_n$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 1875: Assignment to pciw_pci0_wTrnTxRem_n$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 1876: Assignment to pciw_pci0_wTrnTxRem_n$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 1877: Assignment to pciw_pci0_wTrnTxDat$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 1878: Assignment to pciw_pci0_wTrnTxDat$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 1879: Assignment to pciw_pci0_wTrnRxNpOk_n$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 1880: Assignment to pciw_pci0_wTrnRxNpOk_n$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 1881: Assignment to pciw_pci0_wTrnRxCplS_n$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 1882: Assignment to pciw_pci0_wTrnRxCplS_n$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 1883: Assignment to pciw_pcie_irq_wInterruptRdyN$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 1885: Assignment to pciw_pcie_irq_wInterruptRdyN$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 1886: Assignment to pciw_pcie_irq_wInterruptDo$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 1888: Assignment to pciw_pcie_irq_wInterruptDo$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 1901: Assignment to pciw_p2iAF_sClear_pw$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 1902: Assignment to pciw_p2iAF_dClear_pw$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 1903: Assignment to pciw_p2iAF_deq_happened$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 1908: Assignment to pciw_i2pAF_deq_pw$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 1910: Assignment to pciw_i2pAF_sClear_pw$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 1911: Assignment to pciw_i2pAF_dClear_pw$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 1912: Assignment to pciw_i2pAF_deq_happened$whas ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 1913: Assignment to infLed$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 1914: Assignment to blinkLed$wget ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" Line 2297: Assignment to pciw_pcie_irq_rMMEnabled ignored, since the identifier is never used +WARNING:HDLCompiler:552 - "/home/shep/projects/ocpi/libsrc/hdl/ocpi/fpgaTop_ml605.v" Line 102: Input port gmii_col_i is not connected on this instance +WARNING:Xst:2972 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" line 982. All outputs of instance of block are unconnected in block . Underlying logic will be removed. +WARNING:Xst:2972 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" line 1027. All outputs of instance of block are unconnected in block . Underlying logic will be removed. +WARNING:Xst:2972 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" line 1072. All outputs of instance of block are unconnected in block . Underlying logic will be removed. +WARNING:Xst:2972 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" line 1117. All outputs of instance of block are unconnected in block . Underlying logic will be removed. +WARNING:Xst:2972 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" line 1162. All outputs of instance of block are unconnected in block . Underlying logic will be removed. +WARNING:Xst:2972 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" line 988. All outputs of instance of block are unconnected in block . Underlying logic will be removed. +WARNING:Xst:2972 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" line 998. All outputs of instance of block are unconnected in block . Underlying logic will be removed. +WARNING:Xst:2972 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" line 1008. All outputs of instance of block are unconnected in block . Underlying logic will be removed. +WARNING:Xst:2972 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" line 1018. All outputs of instance of block are unconnected in block . Underlying logic will be removed. +WARNING:Xst:2972 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" line 1028. All outputs of instance of block are unconnected in block . Underlying logic will be removed. +WARNING:Xst:2972 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" line 1038. All outputs of instance of block are unconnected in block . Underlying logic will be removed. +WARNING:Xst:2972 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" line 1048. All outputs of instance of block are unconnected in block . Underlying logic will be removed. +WARNING:Xst:2972 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" line 1058. All outputs of instance of block are unconnected in block . Underlying logic will be removed. +WARNING:Xst:2972 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" line 1068. All outputs of instance of block are unconnected in block . Underlying logic will be removed. +WARNING:Xst:2972 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" line 1078. All outputs of instance of block are unconnected in block . Underlying logic will be removed. +WARNING:Xst:2972 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" line 1088. All outputs of instance of block are unconnected in block . Underlying logic will be removed. +WARNING:Xst:2972 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" line 1098. All outputs of instance of block are unconnected in block . Underlying logic will be removed. +WARNING:Xst:2972 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" line 1108. All outputs of instance of block are unconnected in block . Underlying logic will be removed. +WARNING:Xst:2972 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" line 1118. All outputs of instance of block are unconnected in block . Underlying logic will be removed. +WARNING:Xst:2972 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" line 1128. All outputs of instance of block are unconnected in block . Underlying logic will be removed. +WARNING:Xst:2972 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" line 1138. All outputs of instance of block are unconnected in block . Underlying logic will be removed. +WARNING:Xst:2972 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" line 1303. All outputs of instance of block are unconnected in block . Underlying logic will be removed. +WARNING:Xst:2972 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" line 1313. All outputs of instance of block are unconnected in block . Underlying logic will be removed. +WARNING:Xst:2972 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" line 1489. All outputs of instance of block are unconnected in block . Underlying logic will be removed. +WARNING:Xst:2972 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" line 598. All outputs of instance of block are unconnected in block . Underlying logic will be removed. +WARNING:Xst:2972 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" line 606. All outputs of instance of block are unconnected in block . Underlying logic will be removed. + +========================================================================= +* HDL Synthesis * +========================================================================= + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/ocpi/fpgaTop_ml605.v". +WARNING:Xst:2898 - Port 'gmii_col_i', unconnected in block instance 'ftop', is tied to GND. +WARNING:Xst:2898 - Port 'gmii_crs_i', unconnected in block instance 'ftop', is tied to GND. +WARNING:Xst:2898 - Port 'gmii_intr_i', unconnected in block instance 'ftop', is tied to GND. +INFO:Xst:3210 - "/home/shep/projects/ocpi/libsrc/hdl/ocpi/fpgaTop_ml605.v" line 102: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/libsrc/hdl/ocpi/fpgaTop_ml605.v" line 102: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/libsrc/hdl/ocpi/fpgaTop_ml605.v" line 102: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/libsrc/hdl/ocpi/fpgaTop_ml605.v" line 102: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/libsrc/hdl/ocpi/fpgaTop_ml605.v" line 102: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/libsrc/hdl/ocpi/fpgaTop_ml605.v" line 102: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/libsrc/hdl/ocpi/fpgaTop_ml605.v" line 102: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/libsrc/hdl/ocpi/fpgaTop_ml605.v" line 102: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/libsrc/hdl/ocpi/fpgaTop_ml605.v" line 102: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/libsrc/hdl/ocpi/fpgaTop_ml605.v" line 102: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/libsrc/hdl/ocpi/fpgaTop_ml605.v" line 102: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/libsrc/hdl/ocpi/fpgaTop_ml605.v" line 102: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/libsrc/hdl/ocpi/fpgaTop_ml605.v" line 102: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/libsrc/hdl/ocpi/fpgaTop_ml605.v" line 102: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/libsrc/hdl/ocpi/fpgaTop_ml605.v" line 102: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/libsrc/hdl/ocpi/fpgaTop_ml605.v" line 102: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/libsrc/hdl/ocpi/fpgaTop_ml605.v" line 102: Output port of the instance is unconnected or connected to loadless signal. + Summary: + no macro. +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v". +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1200: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1200: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1228: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1228: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1228: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1228: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1228: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1228: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1228: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1228: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1228: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1228: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1228: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1418: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1418: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1418: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1418: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1452: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1452: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1452: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1452: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1608: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1608: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1608: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1608: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1608: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1608: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1608: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1608: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1608: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1608: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1608: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1608: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1608: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1608: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1608: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1608: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1608: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1608: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1608: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1608: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1608: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1608: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1608: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1608: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1608: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1608: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1608: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1608: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1608: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1608: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1608: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1608: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1608: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1608: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1608: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1608: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1608: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1608: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1608: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFTop_ml605.v" line 1729: Output port of the instance is unconnected or connected to loadless signal. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 82-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 8-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 153-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 16-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 153-bit register for signal . + Found 82-bit register for signal . + Found 32-bit adder for signal created at line 1917. + Found 1-bit comparator equal for signal created at line 1819 + Found 1-bit comparator equal for signal created at line 2082 + Summary: + inferred 1 Adder/Subtractor(s). + inferred 538 D-type flip-flop(s). + inferred 2 Comparator(s). + inferred 5 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" line 982: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" line 982: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" line 1027: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" line 1027: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" line 1072: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" line 1072: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" line 1117: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" line 1117: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" line 1162: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" line 1162: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkWSICaptureWorker4B.v" line 1201: Output port of the instance is unconnected or connected to loadless signal. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 2-bit register for signal . + Found 14-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 34-bit register for signal . + Found 34-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 8-bit register for signal . + Found 3-bit register for signal . + Found 2-bit subtractor for signal created at line 2082. + Found 2-bit subtractor for signal created at line 2200. + Found 2-bit subtractor for signal created at line 2532. + Found 32-bit adder for signal created at line 1415. + Found 32-bit adder for signal created at line 1416. + Found 2-bit adder for signal created at line 1422. + Found 2-bit adder for signal created at line 2081. + Found 32-bit adder for signal created at line 2168. + Found 32-bit adder for signal created at line 2187. + Found 2-bit adder for signal created at line 2199. + Found 32-bit adder for signal created at line 2225. + Found 3-bit adder for signal created at line 2469. + Found 3-bit adder for signal created at line 2469. + Found 3-bit adder for signal created at line 2480. + Found 3-bit adder for signal created at line 2480. + Found 3-bit adder for signal created at line 2488. + Found 3-bit adder for signal created at line 2488. + Found 3-bit adder for signal created at line 2494. + Found 3-bit adder for signal created at line 2494. + Found 3-bit adder for signal created at line 2502. + Found 3-bit adder for signal created at line 2502. + Found 14-bit adder for signal created at line 2510. + Found 3-bit adder for signal created at line 2513. + Found 3-bit adder for signal created at line 2533. + Found 3-bit adder for signal created at line 2534. + Found 4x3-bit Read Only RAM for signal <_n1539> + Found 1-bit 4-to-1 multiplexer for signal created at line 2584. + Found 32-bit 4-to-1 multiplexer for signal created at line 2619. + Found 1-bit 4-to-1 multiplexer for signal created at line 2644. + Found 1-bit 4-to-1 multiplexer for signal created at line 2669. + Found 34-bit 8-to-1 multiplexer for signal <_n1602> created at line 866. + Found 2-bit comparator greater for signal created at line 943 + Found 2-bit comparator greater for signal created at line 1505 + Found 1-bit comparator not equal for signal created at line 2084 + Found 1-bit comparator not equal for signal created at line 2202 + Found 3-bit comparator greater for signal created at line 2452 + Found 3-bit comparator greater for signal created at line 2454 + Found 3-bit comparator greater for signal created at line 2455 + Found 3-bit comparator greater for signal created at line 2456 + Found 3-bit comparator greater for signal created at line 2457 + Found 32-bit comparator greater for signal created at line 2476 + Found 32-bit comparator greater for signal created at line 2509 + Found 3-bit comparator greater for signal created at line 2587 + Found 3-bit comparator greater for signal created at line 2590 + Found 3-bit comparator greater for signal created at line 2593 + Found 3-bit comparator greater for signal created at line 2596 + Found 3-bit comparator greater for signal created at line 2608 + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + Summary: + inferred 1 RAM(s). + inferred 23 Adder/Subtractor(s). + inferred 347 D-type flip-flop(s). + inferred 16 Comparator(s). + inferred 22 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/BRAM2.v". + Set property "syn_ramstyle = no_rw_check" for signal . + Found 1024x32-bit dual-port RAM for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Summary: + inferred 1 RAM(s). + inferred 64 D-type flip-flop(s). + inferred 2 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/SizedFIFO.v". + Found 2x32-bit dual-port RAM for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 1-bit adder for signal created at line 81. + Found 1-bit adder for signal created at line 82. + Found 1-bit comparator equal for signal created at line 180 + Found 1-bit comparator not equal for signal created at line 199 + Summary: + inferred 1 RAM(s). + inferred 2 Adder/Subtractor(s). + inferred 37 D-type flip-flop(s). + inferred 2 Comparator(s). + inferred 12 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/FIFO2.v". + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 8 D-type flip-flop(s). + inferred 1 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/SizedFIFO.v". + Found 2x72-bit dual-port RAM for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 72-bit register for signal . + Found 1-bit register for signal . + Found 1-bit adder for signal created at line 81. + Found 1-bit adder for signal created at line 82. + Found 1-bit comparator equal for signal created at line 180 + Found 1-bit comparator not equal for signal created at line 199 + Summary: + inferred 1 RAM(s). + inferred 2 Adder/Subtractor(s). + inferred 77 D-type flip-flop(s). + inferred 2 Comparator(s). + inferred 12 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/SizedFIFO.v". + Found 2x61-bit dual-port RAM for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 61-bit register for signal . + Found 1-bit register for signal . + Found 1-bit adder for signal created at line 81. + Found 1-bit adder for signal created at line 82. + Found 1-bit comparator equal for signal created at line 180 + Found 1-bit comparator not equal for signal created at line 199 + Summary: + inferred 1 RAM(s). + inferred 2 Adder/Subtractor(s). + inferred 66 D-type flip-flop(s). + inferred 2 Comparator(s). + inferred 12 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/rtl/mkCTop16B.v". +WARNING:Xst:2898 - Port 'EN_uuid', unconnected in block instance 'inf', is tied to GND. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkCTop16B.v" line 1297: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkCTop16B.v" line 1297: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkCTop16B.v" line 1297: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkCTop16B.v" line 1297: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkCTop16B.v" line 1297: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkCTop16B.v" line 1297: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkCTop16B.v" line 1297: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkCTop16B.v" line 1297: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkCTop16B.v" line 1297: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkCTop16B.v" line 1297: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkCTop16B.v" line 1297: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkCTop16B.v" line 1297: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkCTop16B.v" line 1297: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkCTop16B.v" line 1483: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkCTop16B.v" line 1483: Output port of the instance is unconnected or connected to loadless signal. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 67-bit register for signal . + Summary: + inferred 70 D-type flip-flop(s). + inferred 3 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/rtl/mkOCApp16B.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + Summary: + no macro. +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkMemiTestWorker.v" line 623: Output port of the instance is unconnected or connected to loadless signal. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 128-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 34-bit register for signal . + Found 34-bit register for signal . + Found 128-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 2-bit register for signal . + Found 146-bit register for signal . + Found 146-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 52-bit register for signal . + Found 52-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 8-bit register for signal . + Found 32-bit register for signal . + Found 32-bit subtractor for signal created at line 813. + Found 32-bit subtractor for signal created at line 997. + Found 2-bit subtractor for signal created at line 1099. + Found 32-bit subtractor for signal created at line 1341. + Found 2-bit subtractor for signal created at line 1403. + Found 2-bit subtractor for signal created at line 1404. + Found 2-bit subtractor for signal created at line 1405. + Found 2-bit adder for signal created at line 819. + Found 2-bit adder for signal created at line 849. + Found 2-bit adder for signal created at line 860. + Found 32-bit adder for signal created at line 955. + Found 32-bit adder for signal created at line 961. + Found 32-bit adder for signal created at line 965. + Found 32-bit adder for signal > created at line 1006. + Found 32-bit adder for signal > created at line 1007. + Found 32-bit adder for signal > created at line 1008. + Found 32-bit adder for signal > created at line 1009. + Found 32-bit adder for signal created at line 1019. + Found 2-bit adder for signal created at line 1098. + Found 32-bit adder for signal > created at line 1171. + Found 32-bit adder for signal > created at line 1172. + Found 32-bit adder for signal > created at line 1173. + Found 32-bit adder for signal > created at line 1174. + Found 32-bit adder for signal created at line 1178. + Found 32-bit adder for signal created at line 1185. + Found 32-bit adder for signal created at line 1192. + Found 4x3-bit Read Only RAM for signal <_n1607> + Found 34-bit 13-to-1 multiplexer for signal <_n1655> created at line 525. + Found 2-bit comparator greater for signal created at line 576 + Found 1-bit comparator not equal for signal created at line 1101 + Found 128-bit comparator not equal for signal created at line 1372 + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + Summary: + inferred 1 RAM(s). + inferred 25 Adder/Subtractor(s). + inferred 1201 D-type flip-flop(s). + inferred 3 Comparator(s). + inferred 10 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/FIFO2.v". + Found 1-bit register for signal . + Found 128-bit register for signal . + Found 128-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 258 D-type flip-flop(s). + inferred 3 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/FIFO2.v". + Found 1-bit register for signal . + Found 131-bit register for signal . + Found 131-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 264 D-type flip-flop(s). + inferred 1 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" line 1194: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" line 1211: Output port of the instance is unconnected or connected to loadless signal. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 12-bit register for signal . + Found 14-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 14-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 9-bit register for signal . + Found 1-bit register for signal . + Found 182-bit register for signal . + Found 12-bit register for signal . + Found 12-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 16-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 34-bit register for signal . + Found 34-bit register for signal . + Found 2-bit register for signal . + Found 146-bit register for signal . + Found 146-bit register for signal . + Found 2-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 169-bit register for signal . + Found 169-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 14-bit register for signal . + Found 14-bit register for signal . + Found 8-bit register for signal . + Found 8-bit register for signal . + Found 32-bit register for signal . + Found 14-bit subtractor for signal created at line 1541. + Found 16-bit subtractor for signal created at line 1552. + Found 2-bit subtractor for signal created at line 1623. + Found 2-bit subtractor for signal created at line 2053. + Found 2-bit subtractor for signal created at line 2499. + Found 12-bit subtractor for signal created at line 2619. + Found 2-bit subtractor for signal created at line 2664. + Found 2-bit subtractor for signal created at line 2665. + Found 2-bit subtractor for signal created at line 2666. + Found 2-bit subtractor for signal created at line 2667. + Found 12-bit adder for signal created at line 1536. + Found 12-bit adder for signal created at line 1536. + Found 32-bit adder for signal created at line 1542. + Found 14-bit adder for signal created at line 1544. + Found 2-bit adder for signal created at line 1558. + Found 2-bit adder for signal created at line 1588. + Found 2-bit adder for signal created at line 1599. + Found 2-bit adder for signal created at line 1606. + Found 2-bit adder for signal created at line 1624. + Found 32-bit adder for signal created at line 1807. + Found 2-bit adder for signal created at line 2052. + Found 32-bit adder for signal created at line 2311. + Found 32-bit adder for signal created at line 2315. + Found 32-bit adder for signal created at line 2319. + Found 32-bit adder for signal created at line 2339. + Found 32-bit adder for signal created at line 2355. + Found 32-bit adder for signal created at line 2441. + Found 32-bit adder for signal created at line 2467. + Found 32-bit adder for signal created at line 2486. + Found 2-bit adder for signal created at line 2498. + Found 32-bit adder for signal created at line 2524. + Found 24-bit adder for signal created at line 2620. + Found 14-bit adder for signal created at line 2628. + Found 5-bit adder for signal created at line 2631. + Found 12-bit adder for signal created at line 2670. + Found 12-bit adder for signal created at line 2677. + Found 12-bit adder for signal created at line 2678. + Found 5-bit adder for signal created at line 2788. + Found 5-bit adder for signal created at line 2789. + Found 5-bit adder for signal created at line 2790. + Found 5-bit adder for signal created at line 2791. + Found 5-bit adder for signal created at line 2792. + Found 5-bit adder for signal created at line 2793. + Found 5-bit adder for signal created at line 2794. + Found 5-bit adder for signal created at line 2795. + Found 5-bit adder for signal created at line 2796. + Found 5-bit adder for signal created at line 2797. + Found 5-bit adder for signal created at line 2798. + Found 5-bit adder for signal created at line 2799. + Found 5-bit adder for signal created at line 2800. + Found 5-bit adder for signal created at line 2801. + Found 4x3-bit Read Only RAM for signal <_n1964> + Found 34-bit 24-to-1 multiplexer for signal <_n2107> created at line 950. + Found 2-bit comparator greater for signal created at line 1107 + Found 12-bit comparator greater for signal created at line 1252 + Found 12-bit comparator not equal for signal created at line 1386 + Found 12-bit comparator equal for signal created at line 1639 + Found 2-bit comparator greater for signal created at line 1710 + Found 14-bit comparator lessequal for signal created at line 1838 + Found 1-bit comparator not equal for signal created at line 2055 + Found 1-bit comparator not equal for signal created at line 2501 + Found 12-bit comparator not equal for signal created at line 2670 + Found 14-bit comparator equal for signal created at line 2680 + Found 4-bit comparator lessequal for signal created at line 2684 + Found 4-bit comparator lessequal for signal created at line 2686 + Found 4-bit comparator lessequal for signal created at line 2688 + Found 4-bit comparator lessequal for signal created at line 2690 + Found 4-bit comparator lessequal for signal created at line 2692 + Found 4-bit comparator lessequal for signal created at line 2694 + Found 4-bit comparator lessequal for signal created at line 2696 + Found 4-bit comparator lessequal for signal created at line 2698 + Found 4-bit comparator lessequal for signal created at line 2700 + Found 4-bit comparator lessequal for signal created at line 2702 + Found 4-bit comparator lessequal for signal created at line 2705 + Found 4-bit comparator lessequal for signal created at line 2708 + Found 4-bit comparator lessequal for signal created at line 2711 + Found 4-bit comparator lessequal for signal created at line 2715 + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + Summary: + inferred 1 RAM(s). + inferred 49 Adder/Subtractor(s). + inferred 1668 D-type flip-flop(s). + inferred 24 Comparator(s). + inferred 48 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/FIFO10.v". + Found 1-bit register for signal . + Summary: + inferred 1 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/BRAM2.v". + Set property "syn_ramstyle = no_rw_check" for signal . + Found 2048x169-bit dual-port RAM for signal . + Found 169-bit register for signal . + Found 169-bit register for signal . + Summary: + inferred 1 RAM(s). + inferred 338 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/FIFO2.v". + Found 1-bit register for signal . + Found 130-bit register for signal . + Found 130-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 262 D-type flip-flop(s). + inferred 3 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/SizedFIFO.v". + Found 2x169-bit dual-port RAM for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 169-bit register for signal . + Found 1-bit register for signal . + Found 1-bit adder for signal created at line 81. + Found 1-bit adder for signal created at line 82. + Found 1-bit comparator equal for signal created at line 180 + Found 1-bit comparator not equal for signal created at line 199 + Summary: + inferred 1 RAM(s). + inferred 2 Adder/Subtractor(s). + inferred 174 D-type flip-flop(s). + inferred 2 Comparator(s). + inferred 9 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkBiasWorker16B.v" line 620: Output port of the instance is unconnected or connected to loadless signal. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 34-bit register for signal . + Found 34-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 169-bit register for signal . + Found 169-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 8-bit register for signal . + Found 8-bit register for signal . + Found 2-bit subtractor for signal created at line 808. + Found 2-bit subtractor for signal created at line 998. + Found 2-bit subtractor for signal created at line 1245. + Found 2-bit subtractor for signal created at line 1318. + Found 2-bit adder for signal created at line 777. + Found 2-bit adder for signal created at line 809. + Found 2-bit adder for signal created at line 997. + Found 32-bit adder for signal created at line 1085. + Found 32-bit adder for signal created at line 1101. + Found 32-bit adder for signal created at line 1187. + Found 32-bit adder for signal created at line 1213. + Found 32-bit adder for signal created at line 1232. + Found 2-bit adder for signal created at line 1244. + Found 32-bit adder for signal created at line 1271. + Found 32-bit adder for signal > created at line 1321. + Found 32-bit adder for signal > created at line 1322. + Found 32-bit adder for signal > created at line 1323. + Found 32-bit adder for signal > created at line 1324. + Found 4x3-bit Read Only RAM for signal <_n0725> + Found 34-bit 15-to-1 multiplexer for signal <_n0763> created at line 537. + Found 2-bit comparator greater for signal created at line 579 + Found 2-bit comparator greater for signal created at line 866 + Found 1-bit comparator not equal for signal created at line 1000 + Found 1-bit comparator not equal for signal created at line 1247 + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + Summary: + inferred 1 RAM(s). + inferred 16 Adder/Subtractor(s). + inferred 710 D-type flip-flop(s). + inferred 4 Comparator(s). + inferred 7 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" line 1194: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkSMAdapter16B.v" line 1211: Output port of the instance is unconnected or connected to loadless signal. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 12-bit register for signal . + Found 14-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 14-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 9-bit register for signal . + Found 1-bit register for signal . + Found 182-bit register for signal . + Found 12-bit register for signal . + Found 12-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 16-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 34-bit register for signal . + Found 34-bit register for signal . + Found 2-bit register for signal . + Found 146-bit register for signal . + Found 146-bit register for signal . + Found 2-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 169-bit register for signal . + Found 169-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 14-bit register for signal . + Found 14-bit register for signal . + Found 8-bit register for signal . + Found 8-bit register for signal . + Found 32-bit register for signal . + Found 14-bit subtractor for signal created at line 1541. + Found 16-bit subtractor for signal created at line 1552. + Found 2-bit subtractor for signal created at line 1623. + Found 2-bit subtractor for signal created at line 2053. + Found 2-bit subtractor for signal created at line 2499. + Found 12-bit subtractor for signal created at line 2619. + Found 2-bit subtractor for signal created at line 2664. + Found 2-bit subtractor for signal created at line 2665. + Found 2-bit subtractor for signal created at line 2666. + Found 2-bit subtractor for signal created at line 2667. + Found 12-bit adder for signal created at line 1536. + Found 12-bit adder for signal created at line 1536. + Found 32-bit adder for signal created at line 1542. + Found 14-bit adder for signal created at line 1544. + Found 2-bit adder for signal created at line 1558. + Found 2-bit adder for signal created at line 1588. + Found 2-bit adder for signal created at line 1599. + Found 2-bit adder for signal created at line 1606. + Found 2-bit adder for signal created at line 1624. + Found 32-bit adder for signal created at line 1807. + Found 2-bit adder for signal created at line 2052. + Found 32-bit adder for signal created at line 2311. + Found 32-bit adder for signal created at line 2315. + Found 32-bit adder for signal created at line 2319. + Found 32-bit adder for signal created at line 2339. + Found 32-bit adder for signal created at line 2355. + Found 32-bit adder for signal created at line 2441. + Found 32-bit adder for signal created at line 2467. + Found 32-bit adder for signal created at line 2486. + Found 2-bit adder for signal created at line 2498. + Found 32-bit adder for signal created at line 2524. + Found 24-bit adder for signal created at line 2620. + Found 14-bit adder for signal created at line 2628. + Found 5-bit adder for signal created at line 2631. + Found 12-bit adder for signal created at line 2670. + Found 12-bit adder for signal created at line 2677. + Found 12-bit adder for signal created at line 2678. + Found 5-bit adder for signal created at line 2788. + Found 5-bit adder for signal created at line 2789. + Found 5-bit adder for signal created at line 2790. + Found 5-bit adder for signal created at line 2791. + Found 5-bit adder for signal created at line 2792. + Found 5-bit adder for signal created at line 2793. + Found 5-bit adder for signal created at line 2794. + Found 5-bit adder for signal created at line 2795. + Found 5-bit adder for signal created at line 2796. + Found 5-bit adder for signal created at line 2797. + Found 5-bit adder for signal created at line 2798. + Found 5-bit adder for signal created at line 2799. + Found 5-bit adder for signal created at line 2800. + Found 5-bit adder for signal created at line 2801. + Found 4x3-bit Read Only RAM for signal <_n1964> + Found 34-bit 24-to-1 multiplexer for signal <_n2114> created at line 950. + Found 2-bit comparator greater for signal created at line 1107 + Found 12-bit comparator greater for signal created at line 1252 + Found 12-bit comparator not equal for signal created at line 1386 + Found 12-bit comparator equal for signal created at line 1639 + Found 2-bit comparator greater for signal created at line 1710 + Found 14-bit comparator lessequal for signal created at line 1838 + Found 1-bit comparator not equal for signal created at line 2055 + Found 1-bit comparator not equal for signal created at line 2501 + Found 12-bit comparator not equal for signal created at line 2670 + Found 14-bit comparator equal for signal created at line 2680 + Found 4-bit comparator lessequal for signal created at line 2684 + Found 4-bit comparator lessequal for signal created at line 2686 + Found 4-bit comparator lessequal for signal created at line 2688 + Found 4-bit comparator lessequal for signal created at line 2690 + Found 4-bit comparator lessequal for signal created at line 2692 + Found 4-bit comparator lessequal for signal created at line 2694 + Found 4-bit comparator lessequal for signal created at line 2696 + Found 4-bit comparator lessequal for signal created at line 2698 + Found 4-bit comparator lessequal for signal created at line 2700 + Found 4-bit comparator lessequal for signal created at line 2702 + Found 4-bit comparator lessequal for signal created at line 2705 + Found 4-bit comparator lessequal for signal created at line 2708 + Found 4-bit comparator lessequal for signal created at line 2711 + Found 4-bit comparator lessequal for signal created at line 2715 + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + Summary: + inferred 1 RAM(s). + inferred 49 Adder/Subtractor(s). + inferred 1668 D-type flip-flop(s). + inferred 24 Comparator(s). + inferred 48 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/rtl/mkUUID.v". + Summary: + no macro. +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/SyncRegister.v". + Found 64-bit register for signal . + Found 64-bit register for signal . + Summary: + inferred 128 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/SyncHandshake.v". + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit comparator not equal for signal created at line 68 + Found 1-bit comparator equal for signal created at line 69 + Summary: + inferred 6 D-type flip-flop(s). + inferred 2 Comparator(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/rtl/mkOCInf16B.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkOCInf16B.v" line 2153: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkOCInf16B.v" line 2634: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkOCInf16B.v" line 2634: Output port of the instance is unconnected or connected to loadless signal. + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 10-bit register for signal . + Found 128-bit register for signal . + Found 32-bit register for signal . + Found 30-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 64-bit register for signal . + Found 10-bit register for signal . + Found 1-bit register for signal . + Found 10-bit subtractor for signal created at line 2720. + Found 10-bit subtractor for signal created at line 2721. + Found 2-bit subtractor for signal created at line 2737. + Found 10-bit subtractor for signal created at line 2738. + Found 12-bit subtractor for signal created at line 3160. + Found 12-bit subtractor for signal created at line 3198. + Found 2-bit adder for signal created at line 2733. + Found 30-bit adder for signal created at line 2736. + Found 2-bit subtractor for signal > created at line 1831. + Found 4x16-bit Read Only RAM for signal + Found 4x2-bit Read Only RAM for signal <_n1229> + Found 4x2-bit Read Only RAM for signal <_n1248> + Found 4x2-bit Read Only RAM for signal <_n1266> + Found 32-bit 4-to-1 multiplexer for signal created at line 3225. + Summary: + inferred 4 RAM(s). + inferred 8 Adder/Subtractor(s). + inferred 283 D-type flip-flop(s). + inferred 18 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/rtl/mkOCCP.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" line 5398: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" line 5417: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" line 5436: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" line 5455: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" line 5474: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" line 5493: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" line 5512: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" line 5531: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" line 5550: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" line 5569: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" line 5588: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" line 5607: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" line 5626: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" line 5645: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkOCCP.v" line 5664: Output port of the instance is unconnected or connected to loadless signal. + Found 65-bit register for signal . + Found 64-bit register for signal . + Found 1-bit register for signal . + Found 7-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 57-bit register for signal . + Found 32-bit register for signal . + Found 4-bit register for signal . + Found 3-bit register for signal . + Found 2-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 33-bit register for signal . + Found 5-bit register for signal . + Found 4-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 12-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 72-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 33-bit register for signal . + Found 5-bit register for signal . + Found 4-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 12-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 72-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 33-bit register for signal . + Found 5-bit register for signal . + Found 4-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 12-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 72-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 33-bit register for signal . + Found 5-bit register for signal . + Found 4-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 12-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 72-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 33-bit register for signal . + Found 5-bit register for signal . + Found 4-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 12-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 72-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 33-bit register for signal . + Found 5-bit register for signal . + Found 4-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 12-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 72-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 33-bit register for signal . + Found 5-bit register for signal . + Found 4-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 12-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 72-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 33-bit register for signal . + Found 5-bit register for signal . + Found 4-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 12-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 72-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 33-bit register for signal . + Found 5-bit register for signal . + Found 4-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 12-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 72-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 33-bit register for signal . + Found 5-bit register for signal . + Found 4-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 12-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 72-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 33-bit register for signal . + Found 5-bit register for signal . + Found 4-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 12-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 72-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 33-bit register for signal . + Found 5-bit register for signal . + Found 4-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 12-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 72-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 33-bit register for signal . + Found 5-bit register for signal . + Found 4-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 12-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 72-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 33-bit register for signal . + Found 5-bit register for signal . + Found 4-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 12-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 72-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 33-bit register for signal . + Found 5-bit register for signal . + Found 4-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 12-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 72-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 4-bit register for signal . + Found 8-bit register for signal . + Found 32-bit register for signal . + Found 2-bit register for signal . + Found 50-bit register for signal . + Found 50-bit register for signal . + Found 50-bit register for signal . + Found 1-bit register for signal . + Found 50-bit register for signal . + Found 50-bit register for signal . + Found 64-bit register for signal . + Found 1-bit register for signal . + Found 8-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 28-bit register for signal . + Found 28-bit register for signal . + Found 28-bit register for signal . + Found 28-bit register for signal . + Found 28-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 28-bit register for signal . + Found 28-bit register for signal . + Found 28-bit register for signal . + Found 28-bit register for signal . + Found 28-bit register for signal . + Found 28-bit register for signal . + Found 28-bit register for signal . + Found 28-bit register for signal . + Found 28-bit register for signal . + Found 28-bit register for signal . + Found 28-bit register for signal . + Found 28-bit register for signal . + Found 28-bit register for signal . + Found 28-bit register for signal . + Found 28-bit register for signal . + Found 64-bit subtractor for signal created at line 10957. + Found 50-bit subtractor for signal created at line 11922. + Found 28-bit subtractor for signal created at line 12027. + Found 50-bit subtractor for signal <_281474976710656_MINUS_timeServ_delSecond__q1> created at line 17283. + Found 4-bit subtractor for signal created at line 17480. + Found 4-bit subtractor for signal created at line 17481. + Found 32-bit adder for signal created at line 9361. + Found 1-bit adder for signal created at line 9383. + Found 1-bit adder for signal created at line 9462. + Found 1-bit adder for signal created at line 9539. + Found 1-bit adder for signal created at line 9616. + Found 1-bit adder for signal created at line 9693. + Found 1-bit adder for signal created at line 9770. + Found 1-bit adder for signal created at line 9846. + Found 1-bit adder for signal created at line 9922. + Found 1-bit adder for signal created at line 9998. + Found 1-bit adder for signal created at line 10074. + Found 1-bit adder for signal created at line 10150. + Found 1-bit adder for signal created at line 10226. + Found 1-bit adder for signal created at line 10302. + Found 1-bit adder for signal created at line 10378. + Found 1-bit adder for signal created at line 10454. + Found 7-bit adder for signal created at line 11846. + Found 50-bit adder for signal created at line 11929. + Found 8-bit adder for signal created at line 11968. + Found 28-bit adder for signal created at line 12015. + Found 28-bit adder for signal created at line 12037. + Found 28-bit adder for signal created at line 12044. + Found 3-bit adder for signal created at line 17325. + Found 3-bit adder for signal created at line 17325. + Found 32-bit adder for signal created at line 17514. + Found 32-bit adder for signal created at line 17515. + Found 32-bit adder for signal created at line 17516. + Found 32-bit adder for signal created at line 17517. + Found 32-bit adder for signal created at line 17518. + Found 32-bit adder for signal created at line 17519. + Found 32-bit adder for signal created at line 17521. + Found 32-bit adder for signal created at line 17522. + Found 50-bit adder for signal created at line 17526. + Found 32-bit adder for signal created at line 17527. + Found 32-bit adder for signal created at line 17528. + Found 32-bit adder for signal created at line 17529. + Found 32-bit adder for signal created at line 17530. + Found 32-bit adder for signal created at line 17531. + Found 32-bit adder for signal created at line 17532. + Found 32-bit adder for signal created at line 17533. + Found 32-bit adder for signal created at line 17534. + Found 32-bit shifter logical left for signal created at line 4556 + Found 32-bit shifter logical left for signal created at line 4557 + Found 32-bit shifter logical left for signal created at line 4558 + Found 32-bit shifter logical left for signal created at line 4559 + Found 32-bit shifter logical left for signal created at line 4560 + Found 32-bit shifter logical left for signal created at line 4561 + Found 32-bit shifter logical left for signal created at line 4562 + Found 32-bit shifter logical left for signal created at line 4563 + Found 32-bit shifter logical left for signal created at line 4564 + Found 32-bit shifter logical left for signal created at line 4565 + Found 32-bit shifter logical left for signal created at line 4566 + Found 32-bit shifter logical left for signal created at line 4567 + Found 32-bit shifter logical left for signal created at line 4568 + Found 32-bit shifter logical left for signal created at line 4569 + Found 32-bit shifter logical left for signal created at line 4570 + Found 32-bit 16-to-1 multiplexer for signal created at line 17629. + Found 1-bit 16-to-1 multiplexer for signal created at line 17666. + Found 1-bit 16-to-1 multiplexer for signal created at line 17735. + Found 1-bit 16-to-1 multiplexer for signal created at line 17815. + Found 1-bit 16-to-1 multiplexer for signal created at line 17883. + Found 1-bit 16-to-1 multiplexer for signal created at line 17952. + Found 1-bit 16-to-1 multiplexer for signal created at line 18020. + Found 1-bit 16-to-1 multiplexer for signal created at line 18089. + Found 1-bit 16-to-1 multiplexer for signal created at line 18157. + Found 1-bit 16-to-1 multiplexer for signal created at line 18226. + Found 1-bit 16-to-1 multiplexer for signal created at line 18294. + Found 1-bit 16-to-1 multiplexer for signal created at line 18363. + Found 1-bit 16-to-1 multiplexer for signal created at line 18431. + Found 1-bit 16-to-1 multiplexer for signal created at line 18500. + Found 1-bit 16-to-1 multiplexer for signal created at line 18568. + Found 1-bit 16-to-1 multiplexer for signal created at line 18637. + Found 1-bit 16-to-1 multiplexer for signal created at line 18705. + Found 1-bit 16-to-1 multiplexer for signal created at line 18774. + Found 1-bit 16-to-1 multiplexer for signal created at line 18843. + Found 1-bit 16-to-1 multiplexer for signal created at line 18911. + Found 1-bit 16-to-1 multiplexer for signal created at line 18979. + Found 1-bit 16-to-1 multiplexer for signal created at line 19048. + Found 1-bit 16-to-1 multiplexer for signal created at line 19116. + Found 1-bit 16-to-1 multiplexer for signal created at line 19185. + Found 1-bit 16-to-1 multiplexer for signal created at line 19253. + Found 1-bit 16-to-1 multiplexer for signal created at line 19322. + Found 1-bit 16-to-1 multiplexer for signal created at line 19390. + Found 1-bit 16-to-1 multiplexer for signal created at line 19459. + Found 1-bit 16-to-1 multiplexer for signal created at line 19527. + Found 1-bit 16-to-1 multiplexer for signal created at line 19596. + Found 1-bit 16-to-1 multiplexer for signal created at line 19663. + Found 1-bit 16-to-1 multiplexer for signal created at line 19730. + Found 1-bit 16-to-1 multiplexer for signal created at line 19843. + Found 1-bit 16-to-1 multiplexer for signal created at line 20093. + Found 1-bit 16-to-1 multiplexer for signal created at line 20162. + Found 1-bit 16-to-1 multiplexer for signal created at line 20242. + Found 1-bit 16-to-1 multiplexer for signal created at line 20447. + Found 1-bit 16-to-1 multiplexer for signal created at line 20516. + Found 1-bit 16-to-1 multiplexer for signal created at line 20721. + Found 1-bit 16-to-1 multiplexer for signal created at line 20790. + Found 1-bit 16-to-1 multiplexer for signal created at line 20995. + Found 1-bit 16-to-1 multiplexer for signal created at line 21064. + Found 1-bit 16-to-1 multiplexer for signal created at line 21269. + Found 1-bit 16-to-1 multiplexer for signal created at line 21338. + Found 1-bit 16-to-1 multiplexer for signal created at line 21543. + Found 1-bit 16-to-1 multiplexer for signal created at line 21612. + Found 1-bit 16-to-1 multiplexer for signal created at line 21817. + Found 1-bit 16-to-1 multiplexer for signal created at line 21886. + Found 1-bit 16-to-1 multiplexer for signal created at line 22091. + Found 1-bit 16-to-1 multiplexer for signal created at line 22160. + Found 1-bit 16-to-1 multiplexer for signal created at line 22365. + Found 1-bit 16-to-1 multiplexer for signal created at line 22434. + Found 1-bit 16-to-1 multiplexer for signal created at line 22639. + Found 1-bit 16-to-1 multiplexer for signal created at line 22708. + Found 1-bit 16-to-1 multiplexer for signal created at line 22913. + Found 1-bit 16-to-1 multiplexer for signal created at line 22982. + Found 1-bit 16-to-1 multiplexer for signal created at line 23187. + Found 1-bit 16-to-1 multiplexer for signal created at line 23256. + Found 1-bit 16-to-1 multiplexer for signal created at line 23461. + Found 1-bit 16-to-1 multiplexer for signal created at line 23530. + Found 1-bit 16-to-1 multiplexer for signal created at line 23735. + Found 1-bit 16-to-1 multiplexer for signal created at line 23804. + Found 1-bit 16-to-1 multiplexer for signal created at line 24005. + Found 1-bit 16-to-1 multiplexer for signal created at line 24072. + Found 1-bit 16-to-1 multiplexer for signal created at line 24169. + Found 1-bit 16-to-1 multiplexer for signal created at line 24265. + Found 32-bit 16-to-1 multiplexer for signal created at line 24421. + Found 3-bit comparator greater for signal created at line 5814 + Found 7-bit comparator lessequal for signal created at line 10554 + Found 7-bit comparator lessequal for signal created at line 10554 + Found 28-bit comparator greater for signal created at line 11964 + Found 2-bit comparator not equal for signal created at line 16408 + Found 8-bit comparator greater for signal created at line 17299 + Found 8-bit comparator greater for signal created at line 17300 + Found 24-bit comparator greater for signal created at line 17302 + Found 24-bit comparator greater for signal created at line 17304 + Found 28-bit comparator greater for signal created at line 17334 + Found 28-bit comparator greater for signal created at line 17342 + Found 28-bit comparator greater for signal created at line 17344 + Found 32-bit comparator greater for signal created at line 17376 + Found 32-bit comparator greater for signal created at line 17383 + Found 32-bit comparator greater for signal created at line 17390 + Found 32-bit comparator greater for signal created at line 17397 + Found 32-bit comparator greater for signal created at line 17404 + Found 32-bit comparator greater for signal created at line 17411 + Found 32-bit comparator greater for signal created at line 17418 + Found 32-bit comparator greater for signal created at line 17425 + Found 32-bit comparator greater for signal created at line 17432 + Found 32-bit comparator greater for signal created at line 17439 + Found 32-bit comparator greater for signal created at line 17446 + Found 32-bit comparator greater for signal created at line 17453 + Found 32-bit comparator greater for signal created at line 17460 + Found 32-bit comparator greater for signal created at line 17467 + Found 32-bit comparator greater for signal created at line 17474 + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + Summary: + inferred 47 Adder/Subtractor(s). + inferred 4100 D-type flip-flop(s). + inferred 27 Comparator(s). + inferred 299 Multiplexer(s). + inferred 15 Combinational logic shifter(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/FIFO1.v". + Found 33-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 34 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/FIFO2.v". + Found 1-bit register for signal . + Found 59-bit register for signal . + Found 59-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 120 D-type flip-flop(s). + inferred 3 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/FIFO2.v". + Found 1-bit register for signal . + Found 40-bit register for signal . + Found 40-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 82 D-type flip-flop(s). + inferred 3 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/BRAM1Load.v". + Found 1024x32-bit single-port RAM for signal . + Found 32-bit register for signal . + Summary: + inferred 1 RAM(s). + inferred 32 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/SyncRegister.v". + Found 1-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 2 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/SyncRegister.v". + Found 2-bit register for signal . + Found 2-bit register for signal . + Summary: + inferred 4 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/SyncRegister.v". + Found 28-bit register for signal . + Found 28-bit register for signal . + Summary: + inferred 56 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/SyncRegister.v". + Found 8-bit register for signal . + Found 8-bit register for signal . + Summary: + inferred 16 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/SyncFIFO.v". + Found 2x64-bit dual-port RAM for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 64-bit register for signal . + Found 2-bit comparator not equal for signal created at line 126 + Found 2-bit comparator not equal for signal created at line 127 + Found 2-bit comparator equal for signal created at line 172 + Summary: + inferred 1 RAM(s). + inferred 86 D-type flip-flop(s). + inferred 3 Comparator(s). + inferred 1 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/MakeResetA.v". + Found 1-bit register for signal . + Summary: + inferred 1 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/SyncResetA.v". + Found 17-bit register for signal . + Summary: + inferred 17 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/FIFO1.v". + Found 34-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 35 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/FIFO2.v". + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 4 D-type flip-flop(s). + inferred 3 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/FIFO2.v". + Found 1-bit register for signal . + Found 56-bit register for signal . + Found 56-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 114 D-type flip-flop(s). + inferred 1 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/FIFO2.v". + Found 1-bit register for signal . + Found 153-bit register for signal . + Found 153-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 308 D-type flip-flop(s). + inferred 3 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/rtl/mkOCDP16B.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" line 2332: Output port of the instance is unconnected or connected to loadless signal. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 16-bit register for signal . + Found 1-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 16-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 1-bit register for signal . + Found 16-bit register for signal . + Found 1-bit register for signal . + Found 16-bit register for signal . + Found 3-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 64-bit register for signal . + Found 64-bit register for signal . + Found 8-bit register for signal . + Found 12-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 4-bit register for signal . + Found 129-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 4-bit register for signal . + Found 13-bit register for signal . + Found 13-bit register for signal . + Found 1-bit register for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 34-bit register for signal . + Found 34-bit register for signal . + Found 2-bit register for signal . + Found 14-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 129-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 16-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 130-bit register for signal . + Found 130-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 16-bit register for signal . + Found 67-bit register for signal . + Found 16-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 10-bit register for signal . + Found 10-bit register for signal . + Found 5-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 17-bit register for signal . + Found 17-bit register for signal . + Found 17-bit register for signal . + Found 10-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 10-bit register for signal . + Found 13-bit register for signal . + Found 10-bit register for signal . + Found 13-bit register for signal . + Found 10-bit register for signal . + Found 14-bit register for signal . + Found 14-bit register for signal . + Found 15-bit register for signal . + Found 15-bit register for signal . + Found 16-bit register for signal . + Found 10-bit subtractor for signal created at line 3265. + Found 10-bit subtractor for signal created at line 3268. + Found 10-bit subtractor for signal created at line 3269. + Found 10-bit subtractor for signal created at line 3271. + Found 10-bit subtractor for signal created at line 3275. + Found 4-bit subtractor for signal created at line 3276. + Found 17-bit subtractor for signal created at line 3306. + Found 10-bit subtractor for signal created at line 3316. + Found 10-bit subtractor for signal created at line 3317. + Found 10-bit subtractor for signal created at line 3319. + Found 4-bit subtractor for signal created at line 3383. + Found 10-bit subtractor for signal created at line 3448. + Found 10-bit subtractor for signal created at line 3450. + Found 10-bit subtractor for signal created at line 3456. + Found 10-bit subtractor for signal created at line 3458. + Found 10-bit subtractor for signal created at line 3464. + Found 10-bit subtractor for signal created at line 3466. + Found 2-bit subtractor for signal created at line 3503. + Found 14-bit subtractor for signal created at line 3504. + Found 14-bit subtractor for signal created at line 3508. + Found 16-bit subtractor for signal created at line 4045. + Found 16-bit subtractor for signal created at line 4066. + Found 2-bit subtractor for signal created at line 5201. + Found 2-bit subtractor for signal created at line 5406. + Found 2-bit subtractor for signal created at line 5458. + Found 2-bit subtractor for signal created at line 6550. + Found 2-bit subtractor for signal created at line 6551. + Found 2-bit subtractor for signal created at line 6552. + Found 2-bit subtractor for signal created at line 6554. + Found 2-bit subtractor for signal created at line 6555. + Found 2-bit subtractor for signal created at line 6556. + Found 13-bit subtractor for signal created at line 6665. + Found 2-bit subtractor for signal created at line 6782. + Found 2-bit subtractor for signal created at line 6796. + Found 12-bit subtractor for signal created at line 6799. + Found 16-bit subtractor for signal created at line 6823. + Found 16-bit subtractor for signal created at line 6825. + Found 16-bit subtractor for signal created at line 6827. + Found 16-bit subtractor for signal created at line 6829. + Found 16-bit adder for signal created at line 3013. + Found 16-bit adder for signal created at line 3017. + Found 32-bit adder for signal created at line 3033. + Found 32-bit adder for signal created at line 3037. + Found 16-bit adder for signal created at line 3041. + Found 16-bit adder for signal created at line 3061. + Found 16-bit adder for signal created at line 3065. + Found 16-bit adder for signal created at line 3069. + Found 16-bit adder for signal created at line 3073. + Found 16-bit adder for signal created at line 3077. + Found 11-bit adder for signal created at line 3128. + Found 32-bit adder for signal created at line 3277. + Found 32-bit adder for signal created at line 3278. + Found 17-bit adder for signal created at line 3296. + Found 17-bit adder for signal created at line 3298. + Found 16-bit adder for signal created at line 3384. + Found 16-bit adder for signal created at line 3385. + Found 13-bit adder for signal created at line 3452. + Found 13-bit adder for signal created at line 3454. + Found 13-bit adder for signal created at line 3460. + Found 13-bit adder for signal created at line 3462. + Found 2-bit adder for signal created at line 3473. + Found 14-bit adder for signal created at line 3502. + Found 32-bit adder for signal created at line 3509. + Found 2-bit adder for signal created at line 3517. + Found 16-bit adder for signal created at line 4236. + Found 16-bit adder for signal created at line 4263. + Found 16-bit adder for signal created at line 4304. + Found 16-bit adder for signal created at line 4330. + Found 12-bit adder for signal created at line 4460. + Found 5-bit adder for signal created at line 4548. + Found 32-bit adder for signal created at line 4640. + Found 2-bit adder for signal created at line 5200. + Found 16-bit adder for signal created at line 5381. + Found 2-bit adder for signal created at line 5405. + Found 2-bit adder for signal created at line 5457. + Found 16-bit adder for signal created at line 5557. + Found 32-bit adder for signal created at line 6384. + Found 3-bit adder for signal created at line 6395. + Found 3-bit adder for signal created at line 6395. + Found 3-bit adder for signal created at line 6407. + Found 3-bit adder for signal created at line 6407. + Found 3-bit adder for signal created at line 6423. + Found 3-bit adder for signal created at line 6423. + Found 3-bit adder for signal created at line 6429. + Found 3-bit adder for signal created at line 6429. + Found 3-bit adder for signal created at line 6443. + Found 3-bit adder for signal created at line 6443. + Found 3-bit adder for signal created at line 6459. + Found 3-bit adder for signal created at line 6459. + Found 3-bit adder for signal created at line 6465. + Found 3-bit adder for signal created at line 6465. + Found 3-bit adder for signal created at line 6471. + Found 3-bit adder for signal created at line 6471. + Found 17-bit adder for signal created at line 6690. + Found 13-bit adder for signal created at line 6704. + Found 13-bit adder for signal created at line 6706. + Found 13-bit adder for signal created at line 6708. + Found 2-bit adder for signal created at line 6712. + Found 13-bit adder for signal created at line 6715. + Found 13-bit adder for signal created at line 6717. + Found 13-bit adder for signal created at line 6719. + Found 16-bit adder for signal created at line 6822. + Found 16-bit adder for signal created at line 6824. + Found 16-bit adder for signal created at line 6826. + Found 16-bit adder for signal created at line 6828. + Found 12-bit subtractor for signal created at line 6167. + Found 2-bit subtractor for signal created at line 1969. + Found 2-bit subtractor for signal created at line 1973. + Found 4x16-bit Read Only RAM for signal + Found 4x2-bit Read Only RAM for signal <_n4203> + Found 4x3-bit Read Only RAM for signal <_n4213> + Found 4x2-bit Read Only RAM for signal <_n4237> + Found 4x2-bit Read Only RAM for signal <_n4265> + Found 11-bit 4-to-1 multiplexer for signal created at line 3084. + Found 11-bit 4-to-1 multiplexer for signal created at line 3103. + Found 11-bit 4-to-1 multiplexer for signal created at line 3135. + Found 11-bit 4-to-1 multiplexer for signal created at line 3154. + Found 11-bit 4-to-1 multiplexer for signal created at line 3179. + Found 11-bit 4-to-1 multiplexer for signal created at line 3198. + Found 11-bit 4-to-1 multiplexer for signal created at line 3223. + Found 11-bit 4-to-1 multiplexer for signal created at line 3242. + Found 1-bit 4-to-1 multiplexer for signal created at line 6974. + Found 1-bit 4-to-1 multiplexer for signal created at line 6995. + Found 1-bit 4-to-1 multiplexer for signal created at line 7016. + Found 1-bit 4-to-1 multiplexer for signal created at line 7037. + Found 1-bit 4-to-1 multiplexer for signal created at line 7058. + Found 32-bit 4-to-1 multiplexer for signal created at line 7075. + Found 32-bit 4-to-1 multiplexer for signal created at line 7092. + Found 32-bit 4-to-1 multiplexer for signal created at line 7109. + Found 32-bit 4-to-1 multiplexer for signal created at line 7126. + Found 1-bit 4-to-1 multiplexer for signal created at line 7147. + Found 1-bit 4-to-1 multiplexer for signal created at line 7237. + Found 32-bit 4-to-1 multiplexer for signal created at line 7262. + Found 1-bit 4-to-1 multiplexer for signal created at line 7283. + Found 34-bit 44-to-1 multiplexer for signal <_n4556> created at line 1684. + Found 2-bit comparator greater for signal created at line 2040 + Found 2-bit comparator greater for signal created at line 3885 + Found 2-bit comparator greater for signal created at line 3890 + Found 1-bit comparator not equal for signal created at line 5203 + Found 1-bit comparator not equal for signal created at line 5408 + Found 1-bit comparator not equal for signal created at line 5460 + Found 10-bit comparator greater for signal created at line 6319 + Found 10-bit comparator greater for signal created at line 6321 + Found 10-bit comparator greater for signal created at line 6323 + Found 16-bit comparator equal for signal created at line 6380 + Found 16-bit comparator equal for signal created at line 6382 + Found 16-bit comparator equal for signal created at line 6391 + Found 16-bit comparator equal for signal created at line 6393 + Found 3-bit comparator greater for signal created at line 6399 + Found 3-bit comparator greater for signal created at line 6416 + Found 3-bit comparator greater for signal created at line 6427 + Found 3-bit comparator greater for signal created at line 6433 + Found 3-bit comparator greater for signal created at line 6447 + Found 3-bit comparator greater for signal created at line 6463 + Found 3-bit comparator greater for signal created at line 6469 + Found 3-bit comparator greater for signal created at line 6475 + Found 8-bit comparator equal for signal created at line 6489 + Found 17-bit comparator lessequal for signal created at line 6519 + Found 13-bit comparator lessequal for signal created at line 6673 + Found 10-bit comparator greater for signal created at line 6677 + Found 10-bit comparator greater for signal created at line 6679 + Found 8-bit comparator equal for signal created at line 6681 + Found 5-bit comparator equal for signal created at line 6682 + Found 3-bit comparator equal for signal created at line 6683 + Found 10-bit comparator lessequal for signal created at line 6693 + Found 10-bit comparator greater for signal created at line 6695 + Found 10-bit comparator lessequal for signal created at line 6702 + Found 10-bit comparator lessequal for signal created at line 6710 + Found 17-bit comparator lessequal for signal created at line 6818 + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 1 in block . + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + Summary: + inferred 5 RAM(s). + inferred 91 Adder/Subtractor(s). + inferred 2516 D-type flip-flop(s). + inferred 34 Comparator(s). + inferred 93 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/BRAM2.v". + Set property "syn_ramstyle = no_rw_check" for signal . + Found 2048x32-bit dual-port RAM for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Summary: + inferred 1 RAM(s). + inferred 64 D-type flip-flop(s). + inferred 2 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/ocpi/arSRLFIFOD.v". + Found 153-bit register for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 2448-bit register for signal . + Found 4-bit adder for signal created at line 63. + Found 4-bit subtractor for signal > created at line 51. + Found 153-bit 16-to-1 multiplexer for signal created at line 51. + Summary: + inferred 2 Adder/Subtractor(s). + inferred 2608 D-type flip-flop(s). + inferred 1 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/FIFO2.v". + Found 1-bit register for signal . + Found 139-bit register for signal . + Found 139-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 280 D-type flip-flop(s). + inferred 3 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/FIFO2.v". + Found 1-bit register for signal . + Found 61-bit register for signal . + Found 61-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 124 D-type flip-flop(s). + inferred 3 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/SizedFIFO.v". + Found 2x146-bit dual-port RAM for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 146-bit register for signal . + Found 1-bit register for signal . + Found 1-bit adder for signal created at line 81. + Found 1-bit adder for signal created at line 82. + Found 1-bit comparator equal for signal created at line 180 + Found 1-bit comparator not equal for signal created at line 199 + Summary: + inferred 1 RAM(s). + inferred 2 Adder/Subtractor(s). + inferred 151 D-type flip-flop(s). + inferred 2 Comparator(s). + inferred 9 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/rtl/mkOCDP16B.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkOCDP16B.v" line 2332: Output port of the instance is unconnected or connected to loadless signal. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 16-bit register for signal . + Found 1-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 16-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 1-bit register for signal . + Found 16-bit register for signal . + Found 1-bit register for signal . + Found 16-bit register for signal . + Found 3-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 64-bit register for signal . + Found 64-bit register for signal . + Found 8-bit register for signal . + Found 12-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 4-bit register for signal . + Found 129-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 4-bit register for signal . + Found 13-bit register for signal . + Found 13-bit register for signal . + Found 1-bit register for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 34-bit register for signal . + Found 34-bit register for signal . + Found 2-bit register for signal . + Found 14-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 129-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 16-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 130-bit register for signal . + Found 130-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 16-bit register for signal . + Found 67-bit register for signal . + Found 16-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 10-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 17-bit register for signal . + Found 17-bit register for signal . + Found 10-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 32-bit register for signal . + Found 10-bit register for signal . + Found 13-bit register for signal . + Found 10-bit register for signal . + Found 13-bit register for signal . + Found 10-bit register for signal . + Found 14-bit register for signal . + Found 14-bit register for signal . + Found 15-bit register for signal . + Found 15-bit register for signal . + Found 16-bit register for signal . + Found 4-bit subtractor for signal created at line 3276. + Found 17-bit subtractor for signal created at line 3314. + Found 10-bit subtractor for signal created at line 3316. + Found 10-bit subtractor for signal created at line 3317. + Found 10-bit subtractor for signal created at line 3319. + Found 4-bit subtractor for signal created at line 3383. + Found 10-bit subtractor for signal created at line 3448. + Found 10-bit subtractor for signal created at line 3450. + Found 10-bit subtractor for signal created at line 3456. + Found 10-bit subtractor for signal created at line 3458. + Found 10-bit subtractor for signal created at line 3464. + Found 10-bit subtractor for signal created at line 3466. + Found 2-bit subtractor for signal created at line 3503. + Found 14-bit subtractor for signal created at line 3504. + Found 14-bit subtractor for signal created at line 3508. + Found 16-bit subtractor for signal created at line 4045. + Found 16-bit subtractor for signal created at line 4066. + Found 2-bit subtractor for signal created at line 5201. + Found 2-bit subtractor for signal created at line 5406. + Found 2-bit subtractor for signal created at line 5458. + Found 2-bit subtractor for signal created at line 6550. + Found 2-bit subtractor for signal created at line 6551. + Found 2-bit subtractor for signal created at line 6552. + Found 2-bit subtractor for signal created at line 6554. + Found 2-bit subtractor for signal created at line 6555. + Found 2-bit subtractor for signal created at line 6556. + Found 13-bit subtractor for signal created at line 6664. + Found 13-bit subtractor for signal created at line 6665. + Found 2-bit subtractor for signal created at line 6782. + Found 2-bit subtractor for signal created at line 6796. + Found 12-bit subtractor for signal created at line 6799. + Found 16-bit subtractor for signal created at line 6823. + Found 16-bit subtractor for signal created at line 6825. + Found 16-bit subtractor for signal created at line 6827. + Found 16-bit subtractor for signal created at line 6829. + Found 16-bit adder for signal created at line 3013. + Found 16-bit adder for signal created at line 3017. + Found 32-bit adder for signal created at line 3033. + Found 32-bit adder for signal created at line 3037. + Found 16-bit adder for signal created at line 3041. + Found 16-bit adder for signal created at line 3061. + Found 16-bit adder for signal created at line 3065. + Found 16-bit adder for signal created at line 3069. + Found 16-bit adder for signal created at line 3073. + Found 16-bit adder for signal created at line 3077. + Found 11-bit adder for signal created at line 3128. + Found 32-bit adder for signal created at line 3277. + Found 32-bit adder for signal created at line 3278. + Found 16-bit adder for signal created at line 3384. + Found 16-bit adder for signal created at line 3385. + Found 32-bit adder for signal created at line 3389. + Found 13-bit adder for signal created at line 3452. + Found 13-bit adder for signal created at line 3454. + Found 13-bit adder for signal created at line 3460. + Found 13-bit adder for signal created at line 3462. + Found 2-bit adder for signal created at line 3473. + Found 14-bit adder for signal created at line 3502. + Found 32-bit adder for signal created at line 3509. + Found 2-bit adder for signal created at line 3517. + Found 16-bit adder for signal created at line 4236. + Found 16-bit adder for signal created at line 4263. + Found 16-bit adder for signal created at line 4304. + Found 16-bit adder for signal created at line 4330. + Found 12-bit adder for signal created at line 4460. + Found 32-bit adder for signal created at line 4640. + Found 2-bit adder for signal created at line 5200. + Found 16-bit adder for signal created at line 5381. + Found 2-bit adder for signal created at line 5405. + Found 2-bit adder for signal created at line 5457. + Found 16-bit adder for signal created at line 5557. + Found 32-bit adder for signal created at line 6384. + Found 3-bit adder for signal created at line 6395. + Found 3-bit adder for signal created at line 6395. + Found 3-bit adder for signal created at line 6407. + Found 3-bit adder for signal created at line 6407. + Found 3-bit adder for signal created at line 6423. + Found 3-bit adder for signal created at line 6423. + Found 3-bit adder for signal created at line 6429. + Found 3-bit adder for signal created at line 6429. + Found 3-bit adder for signal created at line 6443. + Found 3-bit adder for signal created at line 6443. + Found 3-bit adder for signal created at line 6459. + Found 3-bit adder for signal created at line 6459. + Found 3-bit adder for signal created at line 6465. + Found 3-bit adder for signal created at line 6465. + Found 3-bit adder for signal created at line 6471. + Found 3-bit adder for signal created at line 6471. + Found 17-bit adder for signal created at line 6692. + Found 13-bit adder for signal created at line 6704. + Found 13-bit adder for signal created at line 6706. + Found 13-bit adder for signal created at line 6708. + Found 2-bit adder for signal created at line 6712. + Found 13-bit adder for signal created at line 6715. + Found 13-bit adder for signal created at line 6717. + Found 13-bit adder for signal created at line 6719. + Found 16-bit adder for signal created at line 6822. + Found 16-bit adder for signal created at line 6824. + Found 16-bit adder for signal created at line 6826. + Found 16-bit adder for signal created at line 6828. + Found 12-bit subtractor for signal created at line 6167. + Found 2-bit subtractor for signal created at line 1973. + Found 2-bit subtractor for signal created at line 1969. + Found 4x16-bit Read Only RAM for signal + Found 4x3-bit Read Only RAM for signal <_n4119> + Found 4x2-bit Read Only RAM for signal <_n4139> + Found 4x2-bit Read Only RAM for signal <_n4163> + Found 4x2-bit Read Only RAM for signal <_n4194> + Found 11-bit 4-to-1 multiplexer for signal created at line 3084. + Found 11-bit 4-to-1 multiplexer for signal created at line 3103. + Found 11-bit 4-to-1 multiplexer for signal created at line 3135. + Found 11-bit 4-to-1 multiplexer for signal created at line 3154. + Found 11-bit 4-to-1 multiplexer for signal created at line 3179. + Found 11-bit 4-to-1 multiplexer for signal created at line 3198. + Found 11-bit 4-to-1 multiplexer for signal created at line 3223. + Found 11-bit 4-to-1 multiplexer for signal created at line 3242. + Found 1-bit 4-to-1 multiplexer for signal created at line 6974. + Found 1-bit 4-to-1 multiplexer for signal created at line 6995. + Found 1-bit 4-to-1 multiplexer for signal created at line 7016. + Found 1-bit 4-to-1 multiplexer for signal created at line 7037. + Found 1-bit 4-to-1 multiplexer for signal created at line 7058. + Found 32-bit 4-to-1 multiplexer for signal created at line 7075. + Found 32-bit 4-to-1 multiplexer for signal created at line 7092. + Found 32-bit 4-to-1 multiplexer for signal created at line 7109. + Found 32-bit 4-to-1 multiplexer for signal created at line 7126. + Found 1-bit 4-to-1 multiplexer for signal created at line 7147. + Found 1-bit 4-to-1 multiplexer for signal created at line 7237. + Found 32-bit 4-to-1 multiplexer for signal created at line 7262. + Found 1-bit 4-to-1 multiplexer for signal created at line 7283. + Found 34-bit 44-to-1 multiplexer for signal <_n4436> created at line 1684. + Found 2-bit comparator greater for signal created at line 2040 + Found 2-bit comparator greater for signal created at line 3885 + Found 2-bit comparator greater for signal created at line 3890 + Found 1-bit comparator not equal for signal created at line 5203 + Found 1-bit comparator not equal for signal created at line 5408 + Found 1-bit comparator not equal for signal created at line 5460 + Found 10-bit comparator greater for signal created at line 6319 + Found 10-bit comparator greater for signal created at line 6321 + Found 10-bit comparator greater for signal created at line 6323 + Found 16-bit comparator equal for signal created at line 6380 + Found 16-bit comparator equal for signal created at line 6382 + Found 16-bit comparator equal for signal created at line 6391 + Found 16-bit comparator equal for signal created at line 6393 + Found 3-bit comparator greater for signal created at line 6399 + Found 3-bit comparator greater for signal created at line 6416 + Found 3-bit comparator greater for signal created at line 6427 + Found 3-bit comparator greater for signal created at line 6433 + Found 3-bit comparator greater for signal created at line 6447 + Found 3-bit comparator greater for signal created at line 6463 + Found 3-bit comparator greater for signal created at line 6469 + Found 3-bit comparator greater for signal created at line 6475 + Found 17-bit comparator equal for signal created at line 6658 + Found 13-bit comparator lessequal for signal created at line 6669 + Found 10-bit comparator lessequal for signal created at line 6693 + Found 10-bit comparator greater for signal created at line 6695 + Found 10-bit comparator lessequal for signal created at line 6702 + Found 10-bit comparator lessequal for signal created at line 6710 + Found 17-bit comparator lessequal for signal created at line 6808 + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + Summary: + inferred 5 RAM(s). + inferred 87 Adder/Subtractor(s). + inferred 2502 D-type flip-flop(s). + inferred 28 Comparator(s). + inferred 93 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/rtl/mkTimeClient.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + Found 1-bit register for signal . + Found 67-bit register for signal . + Summary: + inferred 68 D-type flip-flop(s). + inferred 1 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/rtl/mkTLPSM.v". + Summary: + inferred 1 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/rtl/mkPktFork.v". + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 7-bit shifter logical left for signal created at line 107 + Found 7-bit shifter logical left for signal created at line 107 + Found 1-bit 4-to-1 multiplexer for signal created at line 247. + Found 3-bit comparator equal for signal created at line 225 + Found 7-bit comparator equal for signal created at line 226 + Found 1-bit comparator equal for signal created at line 226 + Found 4-bit comparator equal for signal created at line 230 + Found 8-bit comparator equal for signal created at line 237 + Found 7-bit comparator equal for signal created at line 250 + Summary: + inferred 2 D-type flip-flop(s). + inferred 6 Comparator(s). + inferred 4 Multiplexer(s). + inferred 2 Combinational logic shifter(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/rtl/mkPktMerge.v". + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 3 D-type flip-flop(s). + inferred 4 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" line 988: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" line 998: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" line 1008: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" line 1018: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" line 1028: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" line 1038: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" line 1048: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" line 1058: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" line 1068: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" line 1078: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" line 1088: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" line 1098: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" line 1108: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" line 1118: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" line 1128: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" line 1138: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" line 1202: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" line 1303: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" line 1313: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkDramServer_v6.v" line 1344: Output port of the instance is unconnected or connected to loadless signal. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 8-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 34-bit register for signal . + Found 34-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 8-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 131-bit register for signal . + Found 131-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 2-bit subtractor for signal created at line 1907. + Found 2-bit subtractor for signal created at line 2471. + Found 2-bit subtractor for signal created at line 2474. + Found 2-bit adder for signal created at line 1587. + Found 8-bit adder for signal created at line 1624. + Found 8-bit adder for signal created at line 1624. + Found 2-bit adder for signal created at line 1627. + Found 8-bit adder for signal created at line 1843. + Found 2-bit adder for signal created at line 1906. + Found 4x3-bit Read Only RAM for signal <_n1504> + Found 34-bit 4-to-1 multiplexer for signal created at line 820. + Found 2-bit comparator greater for signal created at line 922 + Found 1-bit comparator not equal for signal created at line 1909 + Found 8-bit comparator greater for signal created at line 2246 + Found 8-bit comparator greater for signal created at line 2473 + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + Summary: + inferred 1 RAM(s). + inferred 8 Adder/Subtractor(s). + inferred 560 D-type flip-flop(s). + inferred 4 Comparator(s). + inferred 158 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/SyncBit.v". + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 3 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/SyncRegister.v". + Found 16-bit register for signal . + Found 16-bit register for signal . + Summary: + inferred 32 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/SyncFIFO.v". + Found 2x177-bit dual-port RAM for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 177-bit register for signal . + Found 2-bit comparator not equal for signal created at line 126 + Found 2-bit comparator not equal for signal created at line 127 + Found 2-bit comparator equal for signal created at line 172 + Summary: + inferred 1 RAM(s). + inferred 199 D-type flip-flop(s). + inferred 3 Comparator(s). + inferred 1 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/SyncFIFO.v". + Found 2x128-bit dual-port RAM for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 128-bit register for signal . + Found 2-bit comparator not equal for signal created at line 126 + Found 2-bit comparator not equal for signal created at line 127 + Found 2-bit comparator equal for signal created at line 172 + Summary: + inferred 1 RAM(s). + inferred 150 D-type flip-flop(s). + inferred 3 Comparator(s). + inferred 1 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/SyncResetA.v". + Found 16-bit register for signal . + Summary: + inferred 16 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/v6_mig37_patch20110411.v". +WARNING:Xst:2898 - Port 'dbg_wr_dqs_tap_set', unconnected in block instance 'u_memc_ui_top', is tied to GND. +WARNING:Xst:2898 - Port 'dbg_wr_dq_tap_set', unconnected in block instance 'u_memc_ui_top', is tied to GND. +WARNING:Xst:2898 - Port 'pd_PSDONE', unconnected in block instance 'u_memc_ui_top', is tied to GND. +WARNING:Xst:2898 - Port 'dbg_wr_tap_set_en', unconnected in block instance 'u_memc_ui_top', is tied to GND. +WARNING:Xst:2898 - Port 'dbg_inc_rd_fps', unconnected in block instance 'u_memc_ui_top', is tied to GND. +WARNING:Xst:2898 - Port 'dbg_dec_rd_fps', unconnected in block instance 'u_memc_ui_top', is tied to GND. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/v6_mig37_patch20110411.v" line 357: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/v6_mig37_patch20110411.v" line 422: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/v6_mig37_patch20110411.v" line 422: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/v6_mig37_patch20110411.v" line 422: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/v6_mig37_patch20110411.v" line 422: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/v6_mig37_patch20110411.v" line 422: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/v6_mig37_patch20110411.v" line 422: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/v6_mig37_patch20110411.v" line 422: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/v6_mig37_patch20110411.v" line 422: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/v6_mig37_patch20110411.v" line 422: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/v6_mig37_patch20110411.v" line 422: Output port of the instance is unconnected or connected to loadless signal. +WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. +WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. +WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. +WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. +WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. +WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. + Summary: + no macro. +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/iodelay_ctrl_eco20100428.v". + Set property "IODELAY_GROUP = IODELAY_MIG" for instance . + Set property "syn_maxfan = 10" for signal . +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + Found 15-bit register for signal . + Summary: + inferred 15 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ip_top/infrastructure.v". + Set property "syn_maxfan = 10" for signal . + Set property "syn_maxfan = 10" for signal . + Found 8-bit register for signal . + Summary: + inferred 8 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ip_top/memc_ui_top.v". +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ip_top/memc_ui_top.v" line 480: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ip_top/memc_ui_top.v" line 480: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ip_top/memc_ui_top.v" line 480: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ip_top/memc_ui_top.v" line 480: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ip_top/memc_ui_top.v" line 480: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ip_top/memc_ui_top.v" line 480: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ip_top/memc_ui_top.v" line 480: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ip_top/memc_ui_top.v" line 480: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ip_top/memc_ui_top.v" line 480: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ip_top/memc_ui_top.v" line 480: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ip_top/memc_ui_top.v" line 612: Output port of the instance is unconnected or connected to loadless signal. +WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. +WARNING:Xst:653 - Signal > is used but never assigned. This sourceless signal will be automatically connected to value GND. +WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. + Summary: + no macro. +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ip_top/mem_intfc.v". + Summary: + no macro. +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/mc.v". + Set property "MAX_FANOUT = 10" for signal . +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/mc.v" line 628: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/mc.v" line 628: Output port of the instance is unconnected or connected to loadless signal. +WARNING:Xst:2935 - Signal 'dfi_dram_clk_disable', unconnected in block 'mc', is tied to its initial value (0). +WARNING:Xst:2935 - Signal 'dfi_reset_n', unconnected in block 'mc', is tied to its initial value (1). + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 13-bit register for signal . + Found 13-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 8-bit register for signal . + Found 8-bit register for signal . + Found 1-bit register for signal . + Found 8-bit register for signal . + Found 1-bit register for signal . + Found 10-bit register for signal . + Summary: + inferred 84 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/rank_mach.v". + Summary: + no macro. +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/rank_cntrl.v". +WARNING:Xst:2935 - Signal 'add_rrd_inhbt', unconnected in block 'rank_cntrl', is tied to its initial value (0). + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 4-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 3-bit subtractor for signal created at line 206. + Found 3-bit subtractor for signal created at line 267. + Found 4-bit subtractor for signal created at line 326. + Found 3-bit subtractor for signal created at line 385. + Found 3-bit adder for signal created at line 205. + Found 4-bit adder for signal created at line 329. + Found 3-bit comparator lessequal for signal created at line 271 + Summary: + inferred 5 Adder/Subtractor(s). + inferred 17 D-type flip-flop(s). + inferred 1 Comparator(s). + inferred 6 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/rank_common.v". +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/rank_common.v" line 236: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/rank_common.v" line 321: Output port of the instance is unconnected or connected to loadless signal. + Found 1-bit register for signal . + Found 6-bit register for signal . + Found 20-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 6-bit register for signal . + Found 6-bit subtractor for signal created at line 122. + Found 6-bit subtractor for signal created at line 147. + Found 20-bit subtractor for signal created at line 175. + Found 1-bit adder for signal created at line 267. + Found 1-bit adder for signal > created at line 270. + Found 1-bit adder for signal > created at line 270. + Found 1-bit adder for signal > created at line 270. + Found 1-bit adder for signal > created at line 270. + Found 1-bit adder for signal > created at line 270. + Found 1-bit adder for signal > created at line 270. + Found 1-bit adder for signal > created at line 270. + Found 1-bit adder for signal > created at line 270. + Summary: + inferred 12 Adder/Subtractor(s). + inferred 43 D-type flip-flop(s). + inferred 18 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/round_robin_arb.v". + Found 2-bit register for signal . + Found 2-bit register for signal . + Summary: + inferred 4 D-type flip-flop(s). + inferred 2 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/round_robin_arb.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. + Found 1-bit register for signal . + Summary: + inferred 1 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_mach.v". + Summary: + no macro. +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_cntrl.v". + Summary: + no macro. +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_compare.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:2935 - Signal 'req_rank_r_lcl', unconnected in block 'bank_compare', is tied to its initial value (0). +WARNING:Xst:2935 - Signal 'req_rank_ns', unconnected in block 'bank_compare', is tied to its initial value (0). +WARNING:Xst:2935 - Signal 'req_col_r<10>', unconnected in block 'bank_compare', is tied to its initial value (0). + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 13-bit register for signal . + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 8-bit register for signal . + Found 1-bit shifter logical left for signal > created at line 280 + Found 3-bit comparator equal for signal created at line 221 + Found 13-bit comparator equal for signal created at line 230 + Summary: + inferred 44 D-type flip-flop(s). + inferred 2 Comparator(s). + inferred 5 Multiplexer(s). + inferred 1 Combinational logic shifter(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_state.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:2935 - Signal 'rmw_rd_done', unconnected in block 'bank_state_1', is tied to its initial value (0). +WARNING:Xst:2935 - Signal 'rd_half_rmw_lcl', unconnected in block 'bank_state_1', is tied to its initial value (0). +WARNING:Xst:2935 - Signal 'rmw_wait_r', unconnected in block 'bank_state_1', is tied to its initial value (0). + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit subtractor for signal created at line 359. + Found 2-bit subtractor for signal created at line 398. + Found 1-bit adder for signal > created at line 262. + Found 1-bit adder for signal > created at line 488. + Found 2-bit adder for signal created at line 563. + Found 3-bit adder for signal created at line 646. + Found 3-bit comparator lessequal for signal created at line 358 + Found 2-bit comparator equal for signal created at line 736 + Summary: + inferred 6 Adder/Subtractor(s). + inferred 27 D-type flip-flop(s). + inferred 2 Comparator(s). + inferred 13 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_queue.v". +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:2935 - Signal 'rb_hit_busies_r_lcl<7:4>', unconnected in block 'bank_queue_1', is tied to its initial value (0000). +WARNING:Xst:2935 - Signal 'rb_hit_busies_r_lcl<0>', unconnected in block 'bank_queue_1', is tied to its initial value (0). + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 2-bit subtractor for signal created at line 268. + Found 2-bit subtractor for signal created at line 283. + Found 2-bit subtractor for signal created at line 286. + Found 2-bit subtractor for signal created at line 288. + Found 2-bit subtractor for signal created at line 461. + Found 2-bit subtractor for signal created at line 463. + Summary: + inferred 5 Adder/Subtractor(s). + inferred 18 D-type flip-flop(s). + inferred 12 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_cntrl.v". + Summary: + no macro. +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_state.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:2935 - Signal 'rmw_rd_done', unconnected in block 'bank_state_2', is tied to its initial value (0). +WARNING:Xst:2935 - Signal 'rd_half_rmw_lcl', unconnected in block 'bank_state_2', is tied to its initial value (0). +WARNING:Xst:2935 - Signal 'rmw_wait_r', unconnected in block 'bank_state_2', is tied to its initial value (0). + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit subtractor for signal created at line 359. + Found 2-bit subtractor for signal created at line 398. + Found 1-bit adder for signal > created at line 262. + Found 1-bit adder for signal > created at line 488. + Found 2-bit adder for signal created at line 563. + Found 3-bit adder for signal created at line 646. + Found 3-bit comparator lessequal for signal created at line 358 + Found 2-bit comparator equal for signal created at line 736 + Summary: + inferred 6 Adder/Subtractor(s). + inferred 27 D-type flip-flop(s). + inferred 2 Comparator(s). + inferred 13 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_queue.v". +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:2935 - Signal 'rb_hit_busies_r_lcl<7:5>', unconnected in block 'bank_queue_2', is tied to its initial value (000). +WARNING:Xst:2935 - Signal 'rb_hit_busies_r_lcl<1:0>', unconnected in block 'bank_queue_2', is tied to its initial value (00). + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 2-bit subtractor for signal created at line 268. + Found 2-bit subtractor for signal created at line 283. + Found 2-bit subtractor for signal created at line 286. + Found 2-bit subtractor for signal created at line 288. + Found 2-bit subtractor for signal created at line 461. + Found 2-bit subtractor for signal created at line 463. + Found 2-bit adder for signal created at line 267. + Summary: + inferred 6 Adder/Subtractor(s). + inferred 18 D-type flip-flop(s). + inferred 11 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_cntrl.v". + Summary: + no macro. +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_state.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:2935 - Signal 'rmw_rd_done', unconnected in block 'bank_state_3', is tied to its initial value (0). +WARNING:Xst:2935 - Signal 'rd_half_rmw_lcl', unconnected in block 'bank_state_3', is tied to its initial value (0). +WARNING:Xst:2935 - Signal 'rmw_wait_r', unconnected in block 'bank_state_3', is tied to its initial value (0). + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit subtractor for signal created at line 359. + Found 2-bit subtractor for signal created at line 398. + Found 1-bit adder for signal > created at line 262. + Found 1-bit adder for signal > created at line 488. + Found 2-bit adder for signal created at line 563. + Found 3-bit adder for signal created at line 646. + Found 3-bit comparator lessequal for signal created at line 358 + Found 2-bit comparator equal for signal created at line 736 + Summary: + inferred 6 Adder/Subtractor(s). + inferred 27 D-type flip-flop(s). + inferred 2 Comparator(s). + inferred 13 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_queue.v". +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:2935 - Signal 'rb_hit_busies_r_lcl<7:6>', unconnected in block 'bank_queue_3', is tied to its initial value (00). +WARNING:Xst:2935 - Signal 'rb_hit_busies_r_lcl<2:0>', unconnected in block 'bank_queue_3', is tied to its initial value (000). + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 2-bit subtractor for signal created at line 268. + Found 2-bit subtractor for signal created at line 283. + Found 2-bit subtractor for signal created at line 286. + Found 2-bit subtractor for signal created at line 288. + Found 2-bit subtractor for signal created at line 461. + Found 2-bit subtractor for signal created at line 463. + Found 2-bit adder for signal created at line 229. + Found 2-bit adder for signal created at line 267. + Summary: + inferred 7 Adder/Subtractor(s). + inferred 18 D-type flip-flop(s). + inferred 11 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_cntrl.v". + Summary: + no macro. +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_state.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:2935 - Signal 'rmw_rd_done', unconnected in block 'bank_state_4', is tied to its initial value (0). +WARNING:Xst:2935 - Signal 'rd_half_rmw_lcl', unconnected in block 'bank_state_4', is tied to its initial value (0). +WARNING:Xst:2935 - Signal 'rmw_wait_r', unconnected in block 'bank_state_4', is tied to its initial value (0). + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit subtractor for signal created at line 359. + Found 2-bit subtractor for signal created at line 398. + Found 1-bit adder for signal > created at line 262. + Found 1-bit adder for signal > created at line 488. + Found 2-bit adder for signal created at line 563. + Found 3-bit adder for signal created at line 646. + Found 3-bit comparator lessequal for signal created at line 358 + Found 2-bit comparator equal for signal created at line 736 + Summary: + inferred 6 Adder/Subtractor(s). + inferred 27 D-type flip-flop(s). + inferred 2 Comparator(s). + inferred 13 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_queue.v". +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:2935 - Signal 'rb_hit_busies_r_lcl<7>', unconnected in block 'bank_queue_4', is tied to its initial value (0). +WARNING:Xst:2935 - Signal 'rb_hit_busies_r_lcl<3:0>', unconnected in block 'bank_queue_4', is tied to its initial value (0000). + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 2-bit subtractor for signal created at line 268. + Found 2-bit subtractor for signal created at line 283. + Found 2-bit subtractor for signal created at line 286. + Found 2-bit subtractor for signal created at line 288. + Found 2-bit subtractor for signal created at line 461. + Found 2-bit subtractor for signal created at line 463. + Found 2-bit adder for signal created at line 229. + Found 2-bit adder for signal created at line 229. + Found 2-bit adder for signal created at line 267. + Summary: + inferred 8 Adder/Subtractor(s). + inferred 18 D-type flip-flop(s). + inferred 11 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_common.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:2935 - Signal 'low_idle_cnt_r', unconnected in block 'bank_common', is tied to its initial value (0). + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 6-bit register for signal . + Found 1-bit register for signal . + Found 2-bit subtractor for signal created at line 393. + Found 6-bit subtractor for signal created at line 430. + Found 2-bit adder for signal created at line 170. + Found 2-bit adder for signal created at line 170. + Found 2-bit adder for signal created at line 170. + Found 2-bit adder for signal created at line 179. + Found 2-bit adder for signal created at line 179. + Found 2-bit adder for signal created at line 179. + Found 2-bit adder for signal created at line 188. + Found 2-bit adder for signal created at line 188. + Found 2-bit adder for signal created at line 188. + Found 2-bit adder for signal created at line 378. + Found 2-bit adder for signal created at line 378. + Found 2-bit adder for signal created at line 378. + Found 2-bit adder for signal created at line 378. + Found 2-bit adder for signal created at line 378. + Found 2-bit adder for signal created at line 378. + Found 2-bit adder for signal created at line 378. + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + Summary: + inferred 18 Adder/Subtractor(s). + inferred 21 D-type flip-flop(s). + inferred 14 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/arb_mux.v". + Summary: + no macro. +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/arb_row_col.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/arb_row_col.v" line 159: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/arb_row_col.v" line 185: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/arb_row_col.v" line 235: Output port of the instance is unconnected or connected to loadless signal. +WARNING:Xst:2935 - Signal 'send_cmd0_col', unconnected in block 'arb_row_col', is tied to its initial value (0). +WARNING:Xst:2935 - Signal 'send_cmd1_row', unconnected in block 'arb_row_col', is tied to its initial value (0). + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 6 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/round_robin_arb.v". + Found 4-bit register for signal . + Found 4-bit register for signal . + Summary: + inferred 8 D-type flip-flop(s). + inferred 2 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/arb_select.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:2935 - Signal 'row_mux.row_cmd_r', unconnected in block 'arb_select', is tied to its initial value (00000000000000000000). +WARNING:Xst:2935 - Signal 'col_mux.col_cmd_r', unconnected in block 'arb_select', is tied to its initial value (00000000000000000000). +WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 8-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 1-bit shifter logical left for signal > created at line 349 + Found 1-bit shifter logical left for signal > created at line 351 + Found 1-bit shifter logical left for signal created at line 390 + Summary: + inferred 13 D-type flip-flop(s). + inferred 40 Multiplexer(s). + inferred 3 Combinational logic shifter(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/col_mach.v". +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:2935 - Signal 'offset_r<1>', unconnected in block 'col_mach', is tied to its initial value (0). + Found 3-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 5-bit register for signal . + Found 5-bit register for signal . + Found 11-bit register for signal >. + Found 1-bit register for signal >. + Found 11-bit register for signal . + Found 3-bit subtractor for signal created at line 260. + Found 2-bit subtractor for signal created at line 280. + Found 5-bit adder for signal created at line 377. + Found 5-bit adder for signal created at line 386. + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + Summary: + inferred 4 Adder/Subtractor(s). + inferred 45 D-type flip-flop(s). + inferred 10 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_top.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_top.v" line 955: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_top.v" line 955: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_top.v" line 1020: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_top.v" line 1020: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_top.v" line 1020: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_top.v" line 1020: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_top.v" line 1131: Output port of the instance is unconnected or connected to loadless signal. +WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Summary: + inferred 8 D-type flip-flop(s). + inferred 2 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_init.v". +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst - Value "0" of property "syn_replicate" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 7-bit register for signal . + Found 1-bit register for signal . + Found 10-bit register for signal . + Found 1-bit register for signal . + Found 9-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 8-bit register for signal . + Found 1-bit register for signal . + Found 8-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 6-bit register for signal . + Found 6-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 4-bit register for signal . + Found 256-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal <1>>. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 13-bit register for signal . + Found 1-bit register for signal . +INFO:Xst:1799 - State 011110 is never reached in FSM . +INFO:Xst:1799 - State 100101 is never reached in FSM . +INFO:Xst:1799 - State 100100 is never reached in FSM . +INFO:Xst:1799 - State 100111 is never reached in FSM . +INFO:Xst:1799 - State 011101 is never reached in FSM . + Found finite state machine for signal . + ----------------------------------------------------------------------- + | States | 42 | + | Transitions | 86 | + | Inputs | 31 | + | Outputs | 43 | + | Clock | clk (rising_edge) | + | Reset | rst (positive) | + | Reset type | synchronous | + | Reset State | 000000 | + | Encoding | auto | + | Implementation | LUT | + ----------------------------------------------------------------------- + Found 4-bit subtractor for signal created at line 1560. + Found 7-bit adder for signal created at line 854. + Found 10-bit adder for signal created at line 879. + Found 9-bit adder for signal created at line 888. + Found 8-bit adder for signal created at line 935. + Found 8-bit adder for signal created at line 966. + Found 2-bit adder for signal created at line 987. + Found 2-bit adder for signal created at line 1038. + Found 3-bit adder for signal created at line 1051. + Found 2-bit adder for signal created at line 1561. + Found 2-bit adder for signal created at line 1573. + Found 2-bit adder for signal created at line 1657. + Found 4-bit adder for signal created at line 1735. + Found 5-bit subtractor for signal > created at line 764. + Found 16x256-bit Read Only RAM for signal + Found 4x3-bit Read Only RAM for signal + Found 2-bit comparator greater for signal created at line 1208 + Found 32-bit comparator not equal for signal created at line 1560 + Found 2-bit comparator greater for signal created at line 1597 + WARNING:Xst:2404 - FFs/Latches <7:0>> (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches <1:1>> (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches <1:2>> (without init value) have a constant value of 1 in block . + WARNING:Xst:2404 - FFs/Latches <2:10>> (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches <0:0>> (without init value) have a constant value of 1 in block . + WARNING:Xst:2404 - FFs/Latches <0:0>> (without init value) have a constant value of 1 in block . + WARNING:Xst:2404 - FFs/Latches <0><0:0>> (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches <2><0:0>> (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches <0><2:2>> (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches <2><0:0>> (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches <1><2:2>> (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches <0><1:1>> (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches <0><0:0>> (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches <2><0:0>> (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches <1><2:2>> (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches <0><1:1>> (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches <0><0:0>> (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches <2><0:0>> (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches <1><2:2>> (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches <0><1:1>> (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches <1><0:0>> (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches <1><1:1>> (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches <1><1:1>> (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches <1><1:1>> (without init value) have a constant value of 0 in block . + Summary: + inferred 2 RAM(s). + inferred 14 Adder/Subtractor(s). + inferred 468 D-type flip-flop(s). + inferred 3 Comparator(s). + inferred 21 Multiplexer(s). + inferred 1 Finite State Machine(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_control_io.v". + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_keep = 1" for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + Summary: + inferred 5 D-type flip-flop(s). + inferred 17 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_clock_io.v". + Summary: + no macro. +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_ck_iob.v". + Summary: + no macro. +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v". + Set property "syn_maxfan = 1" for signal . + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "syn_maxfan = 1" for signal . +WARNING:Xst - Value "1" of property "syn_preserve" is not applicable. List of valid values is "true, false, yes, no" +WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored. + Set property "MAX_FANOUT = 1" for signal . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v" line 370: Output port of the instance is unconnected or connected to loadless signal. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 80 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_dqs_iob.v". + Set property "IODELAY_GROUP = IODELAY_MIG" for instance . + Found 6-bit register for signal . + Found 6-bit register for signal . + Summary: + inferred 12 D-type flip-flop(s). + inferred 1 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/rd_bitslip.v". + Found 4-bit register for signal . + Found 4-bit register for signal . + Found 4-bit register for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 4-bit 4-to-1 multiplexer for signal created at line 109. + Found 4-bit 4-to-1 multiplexer for signal created at line 133. + Summary: + inferred 17 D-type flip-flop(s). + inferred 2 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_dm_iob.v". + Set property "IODELAY_GROUP = IODELAY_MIG" for instance . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit 8-to-1 multiplexer for signal created at line 189. + Found 1-bit 8-to-1 multiplexer for signal created at line 189. + Found 1-bit 8-to-1 multiplexer for signal created at line 189. + Found 1-bit 8-to-1 multiplexer for signal created at line 189. + Summary: + inferred 14 D-type flip-flop(s). + inferred 4 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_dq_iob.v". + Set property "IODELAY_GROUP = IODELAY_MIG" for instance . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 6-bit register for signal . + Found 6-bit register for signal . + Found 1-bit register for signal . + Found 1-bit 8-to-1 multiplexer for signal created at line 274. + Found 1-bit 8-to-1 multiplexer for signal created at line 274. + Found 1-bit 8-to-1 multiplexer for signal created at line 274. + Found 1-bit 8-to-1 multiplexer for signal created at line 274. + Summary: + inferred 26 D-type flip-flop(s). + inferred 5 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_dly_ctrl.v". +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 8-bit register for signal . + Found 8-bit register for signal . + Found 4-bit register for signal . + Found 4-bit register for signal . + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Summary: + inferred 108 D-type flip-flop(s). + inferred 124 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_write.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + Found 8-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 20-bit register for signal . + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 2-bit adder for signal created at line 1634. + Summary: + inferred 1 Adder/Subtractor(s). + inferred 137 D-type flip-flop(s). + inferred 146 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_wrlvl.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + Found 40-bit register for signal >. + Found 16-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 8-bit register for signal . + Found 8-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 8-bit register for signal . + Found 8-bit register for signal . + Found 40-bit register for signal . + Found 1-bit register for signal . + Found 8-bit register for signal >. + Found 40-bit register for signal >. + Found 1-bit register for signal <4>>. + Found 1-bit register for signal <3>>. + Found 1-bit register for signal <2>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <9>>. + Found 1-bit register for signal <8>>. + Found 1-bit register for signal <7>>. + Found 1-bit register for signal <6>>. + Found 1-bit register for signal <5>>. + Found 1-bit register for signal <14>>. + Found 1-bit register for signal <13>>. + Found 1-bit register for signal <12>>. + Found 1-bit register for signal <11>>. + Found 1-bit register for signal <10>>. + Found 1-bit register for signal <19>>. + Found 1-bit register for signal <18>>. + Found 1-bit register for signal <17>>. + Found 1-bit register for signal <16>>. + Found 1-bit register for signal <15>>. + Found 1-bit register for signal <24>>. + Found 1-bit register for signal <23>>. + Found 1-bit register for signal <22>>. + Found 1-bit register for signal <21>>. + Found 1-bit register for signal <20>>. + Found 1-bit register for signal <29>>. + Found 1-bit register for signal <28>>. + Found 1-bit register for signal <27>>. + Found 1-bit register for signal <26>>. + Found 1-bit register for signal <25>>. + Found 1-bit register for signal <34>>. + Found 1-bit register for signal <33>>. + Found 1-bit register for signal <32>>. + Found 1-bit register for signal <31>>. + Found 1-bit register for signal <30>>. + Found 1-bit register for signal <39>>. + Found 1-bit register for signal <38>>. + Found 1-bit register for signal <37>>. + Found 1-bit register for signal <36>>. + Found 1-bit register for signal <35>>. + Found 40-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 4-bit register for signal . + Found 4-bit register for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 16-bit register for signal . + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 8-bit register for signal >. + Found finite state machine for signal . + ----------------------------------------------------------------------- + | States | 9 | + | Transitions | 23 | + | Inputs | 10 | + | Outputs | 11 | + | Clock | clk (rising_edge) | + | Reset | rst (positive) | + | Reset type | synchronous | + | Reset State | 0000 | + | Encoding | auto | + | Implementation | LUT | + ----------------------------------------------------------------------- + Found 6-bit subtractor for signal created at line 541. + Found 4-bit subtractor for signal created at line 581. + Found 2-bit adder for signal created at line 284. + Found 2-bit adder for signal created at line 298. + Found 5-bit adder for signal created at line 492. + Found 4-bit adder for signal created at line 566. + Found 4-bit adder for signal created at line 567. + Found 4-bit adder for signal created at line 568. + Found 2-bit adder for signal created at line 586. + Found 5-bit adder for signal created at line 641. + Found 3x4-bit multiplier for signal created at line 408. + Found 1-bit 8-to-1 multiplexer for signal created at line 264. + Found 1-bit 8-to-1 multiplexer for signal created at line 285. + Found 1-bit 8-to-1 multiplexer for signal created at line 285. + Found 1-bit 8-to-1 multiplexer for signal created at line 299. + Found 5-bit 8-to-1 multiplexer for signal created at line 341. + Found 1-bit 8-to-1 multiplexer for signal created at line 512. + Found 1-bit 8-to-1 multiplexer for signal created at line 529. + Found 1-bit 16-to-1 multiplexer for signal created at line 640. + Found 1-bit 16-to-1 multiplexer for signal created at line 641. + Found 1-bit 8-to-1 multiplexer for signal created at line 665. + Found 1-bit 8-to-1 multiplexer for signal created at line 668. + Found 2-bit comparator lessequal for signal created at line 230 + Found 5-bit comparator greater for signal created at line 280 + Found 1-bit comparator equal for signal created at line 282 + Found 2-bit comparator greater for signal created at line 283 + Found 1-bit comparator equal for signal created at line 295 + Found 2-bit comparator greater for signal created at line 297 + Found 4-bit comparator lessequal for signal created at line 341 + Found 2-bit comparator lessequal for signal created at line 341 + Found 5-bit comparator greater for signal created at line 530 + Found 5-bit comparator greater for signal created at line 543 + Found 4-bit comparator lessequal for signal created at line 549 + Found 32-bit comparator equal for signal created at line 581 + Found 5-bit comparator lessequal for signal created at line 673 + Summary: + inferred 1 Multiplier(s). + inferred 10 Adder/Subtractor(s). + inferred 351 D-type flip-flop(s). + inferred 13 Comparator(s). + inferred 163 Multiplexer(s). + inferred 1 Finite State Machine(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_read.v". + Summary: + no macro. +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdclk_gen.v". + Set property "IODELAY_GROUP = IODELAY_MIG" for instance . + Set property "IODELAY_GROUP = IODELAY_MIG" for instance . + Set property "IODELAY_GROUP = IODELAY_MIG" for instance . + Set property "IODELAY_GROUP = IODELAY_MIG" for instance . + Set property "IODELAY_GROUP = IODELAY_MIG" for instance . + Set property "IODELAY_GROUP = IODELAY_MIG" for instance . + Set property "IODELAY_GROUP = IODELAY_MIG" for instance . + Set property "IODELAY_GROUP = IODELAY_MIG" for instance . + Set property "IODELAY_GROUP = IODELAY_MIG" for instance . + Set property "IODELAY_GROUP = IODELAY_MIG" for instance . + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "shreg_extract = no" for signal >. + Set property "equivalent_register_removal = no" for signal >. + Set property "shreg_extract = no" for signal >. + Set property "equivalent_register_removal = no" for signal >. + Set property "shreg_extract = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "shreg_extract = no" for signal >. + Set property "equivalent_register_removal = no" for signal >. + Set property "shreg_extract = no" for signal >. + Set property "equivalent_register_removal = no" for signal >. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:653 - Signal > is used but never assigned. This sourceless signal will be automatically connected to value GND. +WARNING:Xst:653 - Signal > is used but never assigned. This sourceless signal will be automatically connected to value GND. +WARNING:Xst:653 - Signal > is used but never assigned. This sourceless signal will be automatically connected to value GND. + Found 4-bit register for signal . + Found 4-bit register for signal . + Found 8-bit register for signal . + Found 8-bit register for signal . + Found 2-bit register for signal >. + Found 2-bit register for signal >. + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 8-bit register for signal . + Found 2-bit register for signal >. + Found 8-bit register for signal . + Found 2-bit register for signal >. + Found 4-bit register for signal . + Found 8-bit register for signal . + Found 9-bit register for signal . + Found 2-bit register for signal . + Found finite state machine for signal . + ----------------------------------------------------------------------- + | States | 7 | + | Transitions | 11 | + | Inputs | 4 | + | Outputs | 27 | + | Clock | clk (rising_edge) | + | Reset | rst_oserdes (positive) | + | Reset type | synchronous | + | Reset State | 000 | + | Encoding | auto | + | Implementation | LUT | + ----------------------------------------------------------------------- + Found 4-bit adder for signal created at line 310. + Found 4-bit adder for signal created at line 324. + Found 4-bit adder for signal created at line 331. + Found 4-bit adder for signal created at line 339. + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + Summary: + inferred 4 Adder/Subtractor(s). + inferred 81 D-type flip-flop(s). + inferred 8 Multiplexer(s). + inferred 1 Finite State Machine(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdctrl_sync.v". + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 8 D-type flip-flop(s). + inferred 1 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rddata_sync.v". +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + Found 32-bit register for signal . + Found 256-bit register for signal . + Summary: + inferred 288 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/circ_buffer.v". + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 3-bit adder for signal created at line 143. + Found 3-bit adder for signal created at line 170. + Summary: + inferred 2 Adder/Subtractor(s). + inferred 12 D-type flip-flop(s). + inferred 2 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/circ_buffer.v". + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 3-bit adder for signal created at line 143. + Found 3-bit adder for signal created at line 170. + Summary: + inferred 2 Adder/Subtractor(s). + inferred 12 D-type flip-flop(s). + inferred 2 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdlvl.v". + Found 1-bit register for signal <3>>. + Found 1-bit register for signal <2>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <4>>. + Found 1-bit register for signal <3>>. + Found 1-bit register for signal <2>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <4>>. + Found 1-bit register for signal <3>>. + Found 1-bit register for signal <2>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <4>>. + Found 1-bit register for signal <3>>. + Found 1-bit register for signal <2>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <4>>. + Found 1-bit register for signal <3>>. + Found 1-bit register for signal <2>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <4>>. + Found 1-bit register for signal <3>>. + Found 1-bit register for signal <2>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <4>>. + Found 1-bit register for signal <3>>. + Found 1-bit register for signal <2>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <4>>. + Found 1-bit register for signal <3>>. + Found 1-bit register for signal <2>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <4>>. + Found 1-bit register for signal <3>>. + Found 1-bit register for signal <2>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <4>>. + Found 1-bit register for signal <3>>. + Found 1-bit register for signal <2>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <4>>. + Found 1-bit register for signal <3>>. + Found 1-bit register for signal <2>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <4>>. + Found 1-bit register for signal <3>>. + Found 1-bit register for signal <2>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <4>>. + Found 1-bit register for signal <3>>. + Found 1-bit register for signal <2>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <4>>. + Found 1-bit register for signal <3>>. + Found 1-bit register for signal <2>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <4>>. + Found 1-bit register for signal <3>>. + Found 1-bit register for signal <2>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <4>>. + Found 1-bit register for signal <3>>. + Found 1-bit register for signal <2>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 5-bit register for signal . + Found 16-bit register for signal . + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 3-bit register for signal . + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 8-bit register for signal . + Found 1-bit register for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 40-bit register for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 12-bit register for signal . + Found 1-bit register for signal . + Found 12-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 6-bit register for signal . + Found 5-bit register for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 5-bit register for signal . + Found 5-bit register for signal . + Found 5-bit register for signal . + Found 6-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 16-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 8-bit register for signal . + Found 5-bit register for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 5-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 16-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 5-bit register for signal . + Found 1-bit register for signal <4>>. + Found 1-bit register for signal <3>>. + Found 1-bit register for signal <2>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal <4>>. + Found 1-bit register for signal <3>>. + Found 1-bit register for signal <2>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal <4>>. + Found 1-bit register for signal <3>>. + Found 1-bit register for signal <2>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal <4>>. + Found 1-bit register for signal <3>>. + Found 1-bit register for signal <2>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal <4>>. + Found 1-bit register for signal <3>>. + Found 1-bit register for signal <2>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal <4>>. + Found 1-bit register for signal <3>>. + Found 1-bit register for signal <2>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal <4>>. + Found 1-bit register for signal <3>>. + Found 1-bit register for signal <2>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal <4>>. + Found 1-bit register for signal <3>>. + Found 1-bit register for signal <2>>. + Found 1-bit register for signal <1>>. + Found 1-bit register for signal <0>>. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal >. + Found 1-bit register for signal <4>>. + Found finite state machine for signal . + ----------------------------------------------------------------------- + | States | 18 | + | Transitions | 42 | + | Inputs | 18 | + | Outputs | 18 | + | Clock | clk (rising_edge) | + | Reset | rst (positive) | + | Reset type | synchronous | + | Reset State | 00000 | + | Encoding | auto | + | Implementation | LUT | + ----------------------------------------------------------------------- + Found finite state machine for signal . + ----------------------------------------------------------------------- + | States | 10 | + | Transitions | 22 | + | Inputs | 10 | + | Outputs | 6 | + | Clock | clk (rising_edge) | + | Reset | rst (positive) | + | Reset type | synchronous | + | Reset State | 0000 | + | Encoding | auto | + | Implementation | LUT | + ----------------------------------------------------------------------- + Found finite state machine for signal . + ----------------------------------------------------------------------- + | States | 6 | + | Transitions | 15 | + | Inputs | 9 | + | Outputs | 5 | + | Clock | clk (rising_edge) | + | Reset | rst (positive) | + | Reset type | synchronous | + | Reset State | 000 | + | Encoding | auto | + | Implementation | LUT | + ----------------------------------------------------------------------- + Found 6-bit subtractor for signal created at line 1284. + Found 6-bit subtractor for signal created at line 1297. + Found 6-bit subtractor for signal created at line 1395. + Found 5-bit subtractor for signal created at line 2100. + Found 5-bit subtractor for signal created at line 2100. + Found 5-bit subtractor for signal created at line 2100. + Found 5-bit subtractor for signal created at line 2100. + Found 5-bit subtractor for signal created at line 2100. + Found 5-bit subtractor for signal created at line 2100. + Found 5-bit subtractor for signal created at line 2100. + Found 5-bit subtractor for signal created at line 2100. + Found 6-bit adder for signal created at line 505. + Found 6-bit adder for signal created at line 505. + Found 6-bit adder for signal created at line 505. + Found 6-bit adder for signal created at line 505. + Found 6-bit adder for signal created at line 505. + Found 6-bit adder for signal created at line 505. + Found 6-bit adder for signal created at line 505. + Found 4-bit adder for signal created at line 647. + Found 4-bit adder for signal created at line 707. + Found 12-bit adder for signal created at line 918. + Found 12-bit adder for signal created at line 946. + Found 3-bit adder for signal created at line 1025. + Found 5-bit adder for signal created at line 1046. + Found 31-bit adder for signal created at line 1284. + Found 6-bit adder for signal created at line 1290. + Found 32-bit adder for signal created at line 1297. + Found 3-bit adder for signal created at line 1343. + Found 5-bit adder for signal created at line 1413. + Found 7-bit adder for signal created at line 1480. + Found 32-bit adder for signal created at line 1541. + Found 6-bit adder for signal created at line 1543. + Found 3-bit adder for signal created at line 1650. + Found 5-bit adder for signal created at line 1784. + Found 3-bit adder for signal created at line 1880. + Found 5-bit adder for signal created at line 1974. + Found 2-bit adder for signal created at line 1984. + Found 3-bit adder for signal created at line 1996. + Found 3-bit adder for signal created at line 2037. + Found 5-bit subtractor for signal > created at line 1048. + Found 6-bit subtractor for signal > created at line 1293. + Found 6-bit subtractor for signal > created at line 1372. + Found 5-bit subtractor for signal > created at line 1479. + Found 5-bit subtractor for signal > created at line 1483. + Found 5-bit subtractor for signal > created at line 1497. + Found 5-bit subtractor for signal > created at line 1525. + Found 5-bit subtractor for signal > created at line 1809. + Found 5-bit subtractor for signal > created at line 2091. + Found 3x3-bit multiplier for signal created at line 599. + Found 30-bit shifter logical right for signal created at line 1996 + Found 3x3-bit multiplier for signal created at line 2021. + Found 3-bit 3-to-1 multiplexer for signal created at line 490. + Found 1-bit 64-to-1 multiplexer for signal created at line 505. + Found 1-bit 64-to-1 multiplexer for signal created at line 507. + Found 1-bit 64-to-1 multiplexer for signal created at line 509. + Found 1-bit 64-to-1 multiplexer for signal created at line 511. + Found 1-bit 64-to-1 multiplexer for signal created at line 505. + Found 1-bit 64-to-1 multiplexer for signal created at line 507. + Found 1-bit 64-to-1 multiplexer for signal created at line 509. + Found 1-bit 64-to-1 multiplexer for signal created at line 511. + Found 1-bit 64-to-1 multiplexer for signal created at line 505. + Found 1-bit 64-to-1 multiplexer for signal created at line 507. + Found 1-bit 64-to-1 multiplexer for signal created at line 509. + Found 1-bit 64-to-1 multiplexer for signal created at line 511. + Found 1-bit 64-to-1 multiplexer for signal created at line 505. + Found 1-bit 64-to-1 multiplexer for signal created at line 507. + Found 1-bit 64-to-1 multiplexer for signal created at line 509. + Found 1-bit 64-to-1 multiplexer for signal created at line 511. + Found 1-bit 64-to-1 multiplexer for signal created at line 505. + Found 1-bit 64-to-1 multiplexer for signal created at line 507. + Found 1-bit 64-to-1 multiplexer for signal created at line 509. + Found 1-bit 64-to-1 multiplexer for signal created at line 511. + Found 1-bit 64-to-1 multiplexer for signal created at line 505. + Found 1-bit 64-to-1 multiplexer for signal created at line 507. + Found 1-bit 64-to-1 multiplexer for signal created at line 509. + Found 1-bit 64-to-1 multiplexer for signal created at line 511. + Found 1-bit 64-to-1 multiplexer for signal created at line 505. + Found 1-bit 64-to-1 multiplexer for signal created at line 507. + Found 1-bit 64-to-1 multiplexer for signal created at line 509. + Found 1-bit 64-to-1 multiplexer for signal created at line 511. + Found 1-bit 64-to-1 multiplexer for signal created at line 505. + Found 1-bit 64-to-1 multiplexer for signal created at line 507. + Found 1-bit 64-to-1 multiplexer for signal created at line 509. + Found 1-bit 64-to-1 multiplexer for signal created at line 511. + Found 2-bit comparator equal for signal created at line 816 + Found 2-bit comparator equal for signal created at line 821 + Found 2-bit comparator equal for signal created at line 826 + Found 2-bit comparator equal for signal created at line 831 + Found 2-bit comparator equal for signal created at line 837 + Found 2-bit comparator equal for signal created at line 842 + Found 2-bit comparator equal for signal created at line 847 + Found 2-bit comparator equal for signal created at line 852 + Found 2-bit comparator equal for signal created at line 816 + Found 2-bit comparator equal for signal created at line 821 + Found 2-bit comparator equal for signal created at line 826 + Found 2-bit comparator equal for signal created at line 831 + Found 2-bit comparator equal for signal created at line 837 + Found 2-bit comparator equal for signal created at line 842 + Found 2-bit comparator equal for signal created at line 847 + Found 2-bit comparator equal for signal created at line 852 + Found 2-bit comparator equal for signal created at line 816 + Found 2-bit comparator equal for signal created at line 821 + Found 2-bit comparator equal for signal created at line 826 + Found 2-bit comparator equal for signal created at line 831 + Found 2-bit comparator equal for signal created at line 837 + Found 2-bit comparator equal for signal created at line 842 + Found 2-bit comparator equal for signal created at line 847 + Found 2-bit comparator equal for signal created at line 852 + Found 2-bit comparator equal for signal created at line 816 + Found 2-bit comparator equal for signal created at line 821 + Found 2-bit comparator equal for signal created at line 826 + Found 2-bit comparator equal for signal created at line 831 + Found 2-bit comparator equal for signal created at line 837 + Found 2-bit comparator equal for signal created at line 842 + Found 2-bit comparator equal for signal created at line 847 + Found 2-bit comparator equal for signal created at line 852 + Found 2-bit comparator equal for signal created at line 816 + Found 2-bit comparator equal for signal created at line 821 + Found 2-bit comparator equal for signal created at line 826 + Found 2-bit comparator equal for signal created at line 831 + Found 2-bit comparator equal for signal created at line 837 + Found 2-bit comparator equal for signal created at line 842 + Found 2-bit comparator equal for signal created at line 847 + Found 2-bit comparator equal for signal created at line 852 + Found 2-bit comparator equal for signal created at line 816 + Found 2-bit comparator equal for signal created at line 821 + Found 2-bit comparator equal for signal created at line 826 + Found 2-bit comparator equal for signal created at line 831 + Found 2-bit comparator equal for signal created at line 837 + Found 2-bit comparator equal for signal created at line 842 + Found 2-bit comparator equal for signal created at line 847 + Found 2-bit comparator equal for signal created at line 852 + Found 2-bit comparator equal for signal created at line 816 + Found 2-bit comparator equal for signal created at line 821 + Found 2-bit comparator equal for signal created at line 826 + Found 2-bit comparator equal for signal created at line 831 + Found 2-bit comparator equal for signal created at line 837 + Found 2-bit comparator equal for signal created at line 842 + Found 2-bit comparator equal for signal created at line 847 + Found 2-bit comparator equal for signal created at line 852 + Found 2-bit comparator equal for signal created at line 816 + Found 2-bit comparator equal for signal created at line 821 + Found 2-bit comparator equal for signal created at line 826 + Found 2-bit comparator equal for signal created at line 831 + Found 2-bit comparator equal for signal created at line 837 + Found 2-bit comparator equal for signal created at line 842 + Found 2-bit comparator equal for signal created at line 847 + Found 2-bit comparator equal for signal created at line 852 + Found 5-bit comparator lessequal for signal created at line 1289 + Found 6-bit comparator greater for signal created at line 1290 + Found 3-bit comparator greater for signal created at line 1336 + Found 6-bit comparator greater for signal created at line 1383 + Found 6-bit comparator lessequal for signal created at line 1478 + Found 7-bit comparator lessequal for signal created at line 1480 + Found 5-bit comparator lessequal for signal created at line 1756 + Found 3-bit comparator greater for signal created at line 1872 + Found 5-bit comparator lessequal for signal created at line 2013 + WARNING:Xst:2404 - FFs/Latches <0:0>> (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches <2:2>> (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches <5:5>> (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches <8:8>> (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches <11:11>> (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches <14:14>> (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches <17:17>> (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches <20:20>> (without init value) have a constant value of 0 in block . + Summary: + inferred 2 Multiplier(s). + inferred 44 Adder/Subtractor(s). + inferred 870 D-type flip-flop(s). + inferred 73 Comparator(s). + inferred 232 Multiplexer(s). + inferred 1 Combinational logic shifter(s). + inferred 3 Finite State Machine(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_pd_top.v". +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + Found 1-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 2 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_pd.v". + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 3-bit register for signal . + Found 6-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 3-bit register for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found finite state machine for signal . + ----------------------------------------------------------------------- + | States | 5 | + | Transitions | 9 | + | Inputs | 4 | + | Outputs | 9 | + | Clock | clk (rising_edge) | + | Reset | reset (positive) | + | Reset type | synchronous | + | Reset State | 000 | + | Encoding | auto | + | Implementation | LUT | + ----------------------------------------------------------------------- + Found 5-bit adder for signal created at line 416. + Found 6-bit adder for signal created at line 502. + Found 16-bit adder for signal created at line 536. + Found 16-bit adder for signal created at line 546. + Found 4-bit adder for signal created at line 593. + Found 4-bit subtractor for signal created at line 184. + Found 5-bit subtractor for signal > created at line 417. + Found 1-bit 16-to-1 multiplexer for signal created at line 203. + Found 1-bit 16-to-1 multiplexer for signal created at line 205. + Found 1-bit 16-to-1 multiplexer for signal created at line 232. + Found 1-bit 16-to-1 multiplexer for signal created at line 233. + Summary: + inferred 6 Adder/Subtractor(s). + inferred 67 D-type flip-flop(s). + inferred 12 Multiplexer(s). + inferred 1 Finite State Machine(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ui/ui_top.v". + Set property "MAX_FANOUT = 10" for signal . +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + Found 1-bit register for signal . + Found 10-bit register for signal . + Summary: + inferred 11 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ui/ui_cmd.v". + Found 1-bit register for signal . + Found 27-bit register for signal . + Found 27-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 68 D-type flip-flop(s). + inferred 1 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ui/ui_wr_data.v". + Set property "equivalent_register_removal = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "equivalent_register_removal = no" for signal . + Set property "equivalent_register_removal = no" for signal . +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 4-bit register for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 16-bit register for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 5-bit register for signal . + Found 256-bit register for signal . + Found 5-bit subtractor for signal created at line 376. + Found 4-bit adder for signal created at line 232. + Found 4-bit adder for signal created at line 252. + Found 4-bit adder for signal created at line 283. + Found 5-bit adder for signal created at line 377. + Summary: + inferred 5 Adder/Subtractor(s). + inferred 339 D-type flip-flop(s). + inferred 5 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/dram_v6_mig37/mig_37/user_design/rtl/ui/ui_rd_data.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:2935 - Signal 'app_ecc_multiple_err_r', unconnected in block 'ui_rd_data', is tied to its initial value (0000). + Found 6-bit register for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 4-bit adder for signal created at line 224. + Found 6-bit adder for signal created at line 183. + Summary: + inferred 2 Adder/Subtractor(s). + inferred 11 D-type flip-flop(s). + inferred 1 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/ocpi/arSRLFIFOD.v". + Found 2-bit register for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 4-bit adder for signal created at line 63. + Found 4-bit subtractor for signal > created at line 51. + Found 2-bit 16-to-1 multiplexer for signal created at line 51. + Summary: + inferred 2 Adder/Subtractor(s). + inferred 41 D-type flip-flop(s). + inferred 1 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/FIFO2.v". + Found 1-bit register for signal . + Found 177-bit register for signal . + Found 177-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 356 D-type flip-flop(s). + inferred 1 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/ocpi/arSRLFIFOD.v". + Found 128-bit register for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 2048-bit register for signal . + Found 4-bit adder for signal created at line 63. + Found 4-bit subtractor for signal > created at line 51. + Found 128-bit 16-to-1 multiplexer for signal created at line 51. + Summary: + inferred 2 Adder/Subtractor(s). + inferred 2183 D-type flip-flop(s). + inferred 1 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/ResetInverter.v". + Summary: + no macro. +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/FIFO2.v". + Found 1-bit register for signal . + Found 146-bit register for signal . + Found 146-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 294 D-type flip-flop(s). + inferred 1 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/FIFO2.v". + Found 1-bit register for signal . + Found 52-bit register for signal . + Found 52-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 106 D-type flip-flop(s). + inferred 1 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/rtl/mkFlashWorker.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFlashWorker.v" line 585: Output port of the instance is unconnected or connected to loadless signal. + Found 1-bit register for signal . + Found 24-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 15-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 4-bit register for signal . + Found 16-bit register for signal . + Found 1-bit register for signal . + Found 16-bit register for signal . + Found 1-bit register for signal . + Found 7-bit register for signal . + Found 7-bit register for signal . + Found 7-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 34-bit register for signal . + Found 34-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found finite state machine for signal . + ----------------------------------------------------------------------- + | States | 9 | + | Transitions | 84 | + | Inputs | 8 | + | Outputs | 8 | + | Clock | wciS0_Clk (rising_edge) | + | Reset | wciS0_MReset_n_GND_179_o_equal_234_o (positive) | + | Reset type | synchronous | + | Reset State | 0000 | + | Encoding | auto | + | Implementation | LUT | + ----------------------------------------------------------------------- + Found finite state machine for signal . + ----------------------------------------------------------------------- + | States | 25 | + | Transitions | 299 | + | Inputs | 11 | + | Outputs | 25 | + | Clock | wciS0_Clk (rising_edge) | + | Reset | wciS0_MReset_n_GND_179_o_equal_234_o (positive) | + | Reset type | synchronous | + | Reset State | 00000 | + | Encoding | auto | + | Implementation | LUT | + ----------------------------------------------------------------------- + Found 2-bit subtractor for signal created at line 1425. + Found 2-bit subtractor for signal created at line 1562. + Found 2-bit adder for signal created at line 903. + Found 2-bit adder for signal created at line 1424. + Found 4x3-bit Read Only RAM for signal <_n0851> + Found 32-bit 7-to-1 multiplexer for signal <_n0843> created at line 507. + Found 2-bit comparator greater for signal created at line 527 + Found 1-bit comparator not equal for signal created at line 1427 + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + Summary: + inferred 1 RAM(s). + inferred 3 Adder/Subtractor(s). + inferred 315 D-type flip-flop(s). + inferred 2 Comparator(s). + inferred 14 Multiplexer(s). + inferred 2 Finite State Machine(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/FIFO2.v". + Found 1-bit register for signal . + Found 41-bit register for signal . + Found 41-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 84 D-type flip-flop(s). + inferred 1 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/FIFO2.v". + Found 1-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 34 D-type flip-flop(s). + inferred 1 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/TriState.v". + Found 1-bit tristate buffer for signal > created at line 50 + Found 1-bit tristate buffer for signal > created at line 50 + Found 1-bit tristate buffer for signal > created at line 50 + Found 1-bit tristate buffer for signal > created at line 50 + Found 1-bit tristate buffer for signal > created at line 50 + Found 1-bit tristate buffer for signal > created at line 50 + Found 1-bit tristate buffer for signal > created at line 50 + Found 1-bit tristate buffer for signal > created at line 50 + Found 1-bit tristate buffer for signal > created at line 50 + Found 1-bit tristate buffer for signal > created at line 50 + Found 1-bit tristate buffer for signal > created at line 50 + Found 1-bit tristate buffer for signal > created at line 50 + Found 1-bit tristate buffer for signal > created at line 50 + Found 1-bit tristate buffer for signal > created at line 50 + Found 1-bit tristate buffer for signal > created at line 50 + Found 1-bit tristate buffer for signal > created at line 50 + Summary: + inferred 16 Tristate(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/SyncResetA.v". + Found 1-bit register for signal . + Summary: + inferred 1 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/rtl/mkFMC150.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" line 820: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" line 891: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkFMC150.v" line 956: Output port of the instance is unconnected or connected to loadless signal. + Found 18-bit register for signal . + Found 18-bit register for signal . + Found 18-bit register for signal . + Found 1-bit register for signal . + Found 18-bit register for signal . + Found 18-bit register for signal . + Found 1-bit register for signal . + Found 18-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 34-bit register for signal . + Found 34-bit register for signal . + Found 33-bit register for signal . + Found 14-bit register for signal . + Found 1-bit register for signal . + Found 28-bit register for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 6-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 28-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 8-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 8-bit register for signal . + Found 1-bit register for signal . + Found 18-bit register for signal . + Found 5-bit subtractor for signal created at line 1185. + Found 6-bit subtractor for signal created at line 1188. + Found 3-bit subtractor for signal created at line 1194. + Found 3-bit subtractor for signal created at line 1196. + Found 18-bit subtractor for signal created at line 1400. + Found 2-bit subtractor for signal created at line 1698. + Found 5-bit subtractor for signal <_31_MINUS_spiCDC_dPos_29___d230> created at line 1855. + Found 2-bit subtractor for signal created at line 1920. + Found 5-bit subtractor for signal created at line 1922. + Found 18-bit adder for signal created at line 1183. + Found 2-bit adder for signal created at line 1213. + Found 2-bit adder for signal created at line 1697. + Found 18-bit shifter logical left for signal created at line 708 + Found 4x3-bit Read Only RAM for signal <_n0979> + Found 1-bit 18-to-1 multiplexer for signal created at line 1179. + Found 1-bit 8-to-1 multiplexer for signal created at line 1207. + Found 1-bit 28-to-1 multiplexer for signal created at line 1921. + Found 1-bit 4-to-1 multiplexer for signal <_n0993> created at line 701. + Found 1-bit 4-to-1 multiplexer for signal <_n1007> created at line 700. + Found 2-bit comparator greater for signal created at line 782 + Found 1-bit comparator equal for signal created at line 969 + Found 1-bit comparator equal for signal created at line 976 + Found 1-bit comparator equal for signal created at line 1056 + Found 1-bit comparator not equal for signal created at line 1700 + Found 1-bit comparator equal for signal created at line 1848 + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + Summary: + inferred 1 RAM(s). + inferred 11 Adder/Subtractor(s). + inferred 367 D-type flip-flop(s). + inferred 6 Comparator(s). + inferred 39 Multiplexer(s). + inferred 1 Combinational logic shifter(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/SyncResetA.v". + Found 2-bit register for signal . + Summary: + inferred 2 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/ClockDiv.v". + Found 3-bit register for signal . + Found 3-bit adder for signal created at line 106. + Found 3-bit comparator greater for signal created at line 105 + Summary: + inferred 1 Adder/Subtractor(s). + inferred 3 D-type flip-flop(s). + inferred 1 Comparator(s). + inferred 1 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/ClockInverter.v". + Summary: + no macro. +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/ResetEither.v". + Summary: + no macro. +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/SyncReset0.v". + Summary: + no macro. +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/ResetToBool.v". + Summary: + no macro. +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/ClockDiv.v". + Found 4-bit register for signal . + Found 4-bit adder for signal created at line 106. + Found 4-bit comparator greater for signal created at line 105 + Summary: + inferred 1 Adder/Subtractor(s). + inferred 4 D-type flip-flop(s). + inferred 1 Comparator(s). + inferred 1 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/rtl/mkGbeWorker.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" line 1363: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" line 1363: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" line 1363: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" line 1363: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" line 1363: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" line 1363: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" line 1363: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" line 1363: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" line 1447: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" line 1459: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" line 1467: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" line 1478: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" line 1478: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" line 1489: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" line 1489: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" line 1489: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" line 1503: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkGbeWorker.v" line 1517: Output port of the instance is unconnected or connected to loadless signal. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 9-bit register for signal . + Found 32-bit register for signal . + Found 48-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 22-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 5-bit register for signal . + Found 8-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 4-bit register for signal . + Found 113-bit register for signal . + Found 4-bit register for signal . + Found 113-bit register for signal . + Found 128-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 5-bit register for signal . + Found 32-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 34-bit register for signal . + Found 34-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 61-bit register for signal . + Found 61-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 45-bit register for signal . + Found 5-bit register for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 16-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 112-bit register for signal . + Found 8-bit register for signal . + Found 8-bit register for signal . + Found 1-bit register for signal . + Found finite state machine for signal . + ----------------------------------------------------------------------- + | States | 3 | + | Transitions | 16 | + | Inputs | 5 | + | Outputs | 3 | + | Clock | wciS0_Clk (rising_edge) | + | Reset | wciS0_MReset_n_GND_214_o_equal_658_o (positive) | + | Reset type | synchronous | + | Reset State | 00 | + | Encoding | auto | + | Implementation | LUT | + ----------------------------------------------------------------------- + Found 2-bit subtractor for signal created at line 1793. + Found 22-bit subtractor for signal created at line 2096. + Found 2-bit subtractor for signal created at line 2320. + Found 2-bit subtractor for signal created at line 2964. + Found 5-bit subtractor for signal created at line 2966. + Found 5-bit subtractor for signal created at line 2967. + Found 5-bit subtractor for signal created at line 2968. + Found 5-bit adder for signal created at line 1745. + Found 4-bit adder for signal created at line 1746. + Found 4-bit adder for signal created at line 1748. + Found 2-bit adder for signal created at line 1756. + Found 32-bit adder for signal created at line 2101. + Found 32-bit adder for signal created at line 2108. + Found 32-bit adder for signal created at line 2141. + Found 32-bit adder for signal created at line 2146. + Found 32-bit adder for signal created at line 2211. + Found 32-bit adder for signal created at line 2225. + Found 32-bit adder for signal created at line 2229. + Found 32-bit adder for signal created at line 2262. + Found 2-bit adder for signal created at line 2319. + Found 32-bit adder for signal created at line 2407. + Found 32-bit adder for signal created at line 2423. + Found 5-bit adder for signal created at line 2957. + Found 32-bit adder for signal created at line 2965. + Found 4x3-bit Read Only RAM for signal <_n2216> + Found 4x10-bit Read Only RAM for signal <_n2472> + Found 256x2-bit Read Only RAM for signal <_n2868> + Found 8-bit 15-to-1 multiplexer for signal created at line 3010. + Found 8-bit 15-to-1 multiplexer for signal created at line 3059. + Found 8-bit 15-to-1 multiplexer for signal <_n2245> created at line 1132. + Found 8-bit 15-to-1 multiplexer for signal <_n2274> created at line 3108. + Found 8-bit 15-to-1 multiplexer for signal <_n2317> created at line 1131. + Found 34-bit 32-to-1 multiplexer for signal <_n2485> created at line 1093. + Found 2-bit comparator greater for signal created at line 1245 + Found 4-bit comparator greater for signal created at line 1748 + Found 22-bit comparator greater for signal created at line 2098 + Found 32-bit comparator greater for signal created at line 2200 + Found 1-bit comparator not equal for signal created at line 2322 + Found 8-bit comparator greater for signal created at line 2782 + Found 8-bit comparator equal for signal created at line 2810 + Found 8-bit comparator equal for signal created at line 2875 + Found 8-bit comparator equal for signal created at line 2877 + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + Summary: + inferred 3 RAM(s). + inferred 23 Adder/Subtractor(s). + inferred 1539 D-type flip-flop(s). + inferred 9 Comparator(s). + inferred 100 Multiplexer(s). + inferred 1 Finite State Machine(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/FIFO2.v". + Found 1-bit register for signal . + Found 45-bit register for signal . + Found 45-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 92 D-type flip-flop(s). + inferred 3 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/FIFO2.v". + Found 1-bit register for signal . + Found 79-bit register for signal . + Found 79-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 160 D-type flip-flop(s). + inferred 1 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/rtl/mkGMAC.v". +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" line 598: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" line 606: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" line 651: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" line 651: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" line 651: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" line 651: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" line 651: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" line 699: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" line 699: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" line 699: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" line 699: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/rtl/mkGMAC.v" line 699: Output port of the instance is unconnected or connected to loadless signal. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 12-bit register for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 8-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 4-bit register for signal . + Found 6-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 8-bit register for signal . + Found 48-bit register for signal . + Found 1-bit register for signal . + Found 5-bit subtractor for signal created at line 995. + Found 3-bit subtractor for signal created at line 1397. + Found 4-bit adder for signal created at line 971. + Found 12-bit adder for signal created at line 999. + Found 5-bit adder for signal created at line 1003. + Found 8-bit 4-to-1 multiplexer for signal <_n0412> created at line 518. + Found 32-bit comparator not equal for signal created at line 975 + Found 4-bit comparator greater for signal created at line 1136 + Found 12-bit comparator greater for signal created at line 1394 + Found 5-bit comparator greater for signal created at line 1396 + WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + Summary: + inferred 5 Adder/Subtractor(s). + inferred 113 D-type flip-flop(s). + inferred 4 Comparator(s). + inferred 16 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/SyncResetA.v". + Found 8-bit register for signal . + Summary: + inferred 8 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/rtl/mkCRC32.v". + Found 32-bit register for signal . + Summary: + inferred 32 D-type flip-flop(s). + inferred 9 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/SyncFIFO.v". + Found 8x10-bit dual-port RAM for signal . + Found 1-bit register for signal . + Found 4-bit register for signal . + Found 4-bit register for signal . + Found 5-bit register for signal . + Found 5-bit register for signal . + Found 4-bit register for signal . + Found 4-bit register for signal . + Found 5-bit register for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 10-bit register for signal . + Found 4-bit comparator not equal for signal created at line 126 + Found 4-bit comparator not equal for signal created at line 127 + Found 4-bit comparator equal for signal created at line 172 + Summary: + inferred 1 RAM(s). + inferred 48 D-type flip-flop(s). + inferred 3 Comparator(s). + inferred 1 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/SyncFIFO.v". + Found 16x10-bit dual-port RAM for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 5-bit register for signal . + Found 6-bit register for signal . + Found 6-bit register for signal . + Found 5-bit register for signal . + Found 5-bit register for signal . + Found 6-bit register for signal . + Found 6-bit register for signal . + Found 1-bit register for signal . + Found 10-bit register for signal . + Found 5-bit comparator not equal for signal created at line 126 + Found 5-bit comparator not equal for signal created at line 127 + Found 5-bit comparator equal for signal created at line 172 + Summary: + inferred 1 RAM(s). + inferred 56 D-type flip-flop(s). + inferred 3 Comparator(s). + inferred 1 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/FIFO2.v". + Found 1-bit register for signal . + Found 27-bit register for signal . + Found 27-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 56 D-type flip-flop(s). + inferred 1 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/FIFO2.v". + Found 1-bit register for signal . + Found 17-bit register for signal . + Found 17-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 36 D-type flip-flop(s). + inferred 1 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/Counter.v". + Found 8-bit register for signal . + Found 8-bit adder for signal created at line 78. + Summary: + inferred 1 Adder/Subtractor(s). + inferred 8 D-type flip-flop(s). + inferred 1 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/Counter.v". + Found 4-bit register for signal . + Found 4-bit adder for signal created at line 78. + Summary: + inferred 1 Adder/Subtractor(s). + inferred 4 D-type flip-flop(s). + inferred 2 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/TriState.v". + Found 1-bit tristate buffer for signal created at line 50 + Summary: + inferred 1 Tristate(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/MakeResetA.v". + Found 1-bit register for signal . + Summary: + inferred 1 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/FIFO2.v". + Found 1-bit register for signal . + Found 112-bit register for signal . + Found 112-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 226 D-type flip-flop(s). + inferred 1 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/FIFO2.v". + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 34 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/rtl/mkLCDController.v". + Found 2-bit register for signal . + Found 24-bit register for signal . + Found 8-bit register for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 8-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 8-bit register for signal . + Found 5-bit register for signal . + Found 128-bit register for signal . + Found 128-bit register for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found finite state machine for signal . + ----------------------------------------------------------------------- + | States | 3 | + | Transitions | 15 | + | Inputs | 12 | + | Outputs | 2 | + | Clock | CLK (rising_edge) | + | Reset | RST_N_GND_237_o_equal_539_o (positive) | + | Reset type | synchronous | + | Reset State | 00 | + | Encoding | auto | + | Implementation | LUT | + ----------------------------------------------------------------------- + Found finite state machine for signal . + ----------------------------------------------------------------------- + | States | 11 | + | Transitions | 61 | + | Inputs | 6 | + | Outputs | 11 | + | Clock | CLK (rising_edge) | + | Reset | RST_N_GND_237_o_equal_539_o (positive) | + | Reset type | synchronous | + | Reset State | 0000 | + | Encoding | auto | + | Implementation | LUT | + ----------------------------------------------------------------------- + Found finite state machine for signal . + ----------------------------------------------------------------------- + | States | 140 | + | Transitions | 4472 | + | Inputs | 18 | + | Outputs | 139 | + | Clock | CLK (rising_edge) | + | Reset | RST_N_GND_237_o_equal_539_o (positive) | + | Reset type | synchronous | + | Reset State | 00000000 | + | Encoding | auto | + | Implementation | LUT | + ----------------------------------------------------------------------- + Found finite state machine for signal . + ----------------------------------------------------------------------- + | States | 11 | + | Transitions | 156 | + | Inputs | 11 | + | Outputs | 10 | + | Clock | CLK (rising_edge) | + | Reset | RST_N_GND_237_o_equal_539_o (positive) | + | Reset type | synchronous | + | Reset State | 0000 | + | Encoding | auto | + | Implementation | LUT | + ----------------------------------------------------------------------- + Found finite state machine for signal . + ----------------------------------------------------------------------- + | States | 11 | + | Transitions | 156 | + | Inputs | 11 | + | Outputs | 10 | + | Clock | CLK (rising_edge) | + | Reset | RST_N_GND_237_o_equal_539_o (positive) | + | Reset type | synchronous | + | Reset State | 0000 | + | Encoding | auto | + | Implementation | LUT | + ----------------------------------------------------------------------- + Found 24-bit subtractor for signal created at line 1550. + Found 8-bit adder for signal created at line 1551. + Found 5-bit adder for signal created at line 1594. + Found 4-bit adder for signal created at line 1595. + Found 8-bit 16-to-1 multiplexer for signal <_n1472> created at line 443. + Found 8-bit 16-to-1 multiplexer for signal <_n1503> created at line 443. + Found 5-bit comparator greater for signal created at line 2925 + Found 4-bit comparator greater for signal created at line 2938 + Summary: + inferred 4 Adder/Subtractor(s). + inferred 330 D-type flip-flop(s). + inferred 2 Comparator(s). + inferred 11 Multiplexer(s). + inferred 5 Finite State Machine(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/SizedFIFO.v". +WARNING:Xst:3035 - Index value(s) does not match array range for signal , simulation mismatch. + Found 3x81-bit dual-port RAM for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 81-bit register for signal . + Found 2-bit register for signal . + Found 2-bit adder for signal created at line 81. + Found 2-bit adder for signal created at line 82. + Found 2-bit comparator equal for signal created at line 180 + Found 2-bit comparator not equal for signal created at line 199 + Summary: + inferred 1 RAM(s). + inferred 2 Adder/Subtractor(s). + inferred 88 D-type flip-flop(s). + inferred 2 Comparator(s). + inferred 14 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/ocpi/xilinx_v6_pcie_wrapper.v". + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Set property "KEEP = TRUE" for signal . + Summary: + no macro. +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v". +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 709: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/v6_pcie_v1_7.v" line 970: Output port of the instance is unconnected or connected to loadless signal. + Found 5-bit register for signal . + Found 3-bit register for signal . + Found 8-bit register for signal . + Summary: + inferred 16 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_reset_delay_v6.v". + Found 8-bit register for signal . + Found 8-bit register for signal . + Found 8-bit register for signal . + Found 8-bit adder for signal created at line 99. + Found 8-bit adder for signal created at line 100. + Found 8-bit adder for signal created at line 101. + Summary: + inferred 3 Adder/Subtractor(s). + inferred 24 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_clocking_v6.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. + Found 2-bit register for signal . + Summary: + inferred 2 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_2_0_v6.v". +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_2_0_v6.v" line 1439: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_2_0_v6.v" line 1439: Output port of the instance is unconnected or connected to loadless signal. + Summary: + inferred 8 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_pipe_v6.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. +WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. +WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. +WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. +WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. +WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. +WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. +WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. + Summary: + no macro. +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_pipe_misc_v6.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + Summary: + no macro. +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_pipe_lane_v6.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + Summary: + no macro. +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_gtx_v6.v". +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_gtx_v6.v" line 254: Output port of the instance is unconnected or connected to loadless signal. + Found 4-bit register for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 6-bit register for signal . + Found 1-bit register for signal . + Found 4-bit subtractor for signal created at line 484. + Found 5-bit adder for signal created at line 464. + Summary: + inferred 2 Adder/Subtractor(s). + inferred 18 D-type flip-flop(s). + inferred 1 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v". +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" line 275: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" line 275: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" line 275: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_wrapper_v6.v" line 275: Output port of the instance is unconnected or connected to loadless signal. +WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND. + Found 4-bit register for signal . + Found 4-bit register for signal . + Summary: + inferred 8 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_drp_chanalign_fix_3752_v6.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 8-bit register for signal . + Found finite state machine for signal . + ----------------------------------------------------------------------- + | States | 7 | + | Transitions | 20 | + | Inputs | 6 | + | Outputs | 11 | + | Clock | drp_clk (rising_edge) | + | Reset | Reset_n (negative) | + | Reset type | synchronous | + | Reset State | 0011 | + | Encoding | auto | + | Implementation | LUT | + ----------------------------------------------------------------------- + Found 8-bit adder for signal created at line 180. + Found 16x32-bit Read Only RAM for signal <_n0098> + Summary: + inferred 1 RAM(s). + inferred 1 Adder/Subtractor(s). + inferred 10 D-type flip-flop(s). + inferred 7 Multiplexer(s). + inferred 1 Finite State Machine(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_rx_valid_filter_v6.v". + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 16-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 4-bit register for signal . + Found 5-bit register for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found finite state machine for signal . + ----------------------------------------------------------------------- + | States | 5 | + | Transitions | 26 | + | Inputs | 8 | + | Outputs | 5 | + | Clock | USER_CLK (rising_edge) | + | Reset | RESET (positive) | + | Reset type | synchronous | + | Reset State | 00001 | + | Encoding | auto | + | Implementation | LUT | + ----------------------------------------------------------------------- + Found finite state machine for signal . + ----------------------------------------------------------------------- + | States | 4 | + | Transitions | 14 | + | Inputs | 7 | + | Outputs | 4 | + | Clock | USER_CLK (rising_edge) | + | Reset | RESET (positive) | + | Reset type | synchronous | + | Reset State | 0001 | + | Encoding | auto | + | Implementation | LUT | + ----------------------------------------------------------------------- + Found 5-bit adder for signal created at line 308. + Found 4-bit adder for signal created at line 328. + Found 4-bit adder for signal created at line 360. + Found 5-bit comparator greater for signal created at line 283 + Found 4-bit comparator lessequal for signal created at line 356 + Summary: + inferred 3 Adder/Subtractor(s). + inferred 44 D-type flip-flop(s). + inferred 2 Comparator(s). + inferred 7 Multiplexer(s). + inferred 2 Finite State Machine(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/gtx_tx_sync_rate_v6.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + Found 8-bit register for signal . + Found 8-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 25-bit register for signal . + Found finite state machine for signal . + ----------------------------------------------------------------------- + | States | 21 | + | Transitions | 40 | + | Inputs | 10 | + | Outputs | 21 | + | Clock | USER_CLK (rising_edge) | + | Reset | RESET (positive) | + | Reset type | synchronous | + | Reset State | 0000000000000100000000000 | + | Encoding | auto | + | Implementation | LUT | + ----------------------------------------------------------------------- + Found 8-bit adder for signal created at line 179. + Found 8-bit adder for signal created at line 180. + Found 1-bit comparator equal for signal created at line 534 + Summary: + inferred 2 Adder/Subtractor(s). + inferred 27 D-type flip-flop(s). + inferred 1 Comparator(s). + inferred 19 Multiplexer(s). + inferred 1 Finite State Machine(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_bram_top_v6.v". + Summary: + no macro. +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_brams_v6.v". + Summary: + no macro. +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_bram_v6.v". +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + Summary: + no macro. +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_upconfig_fix_3451_v6.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + Summary: + no macro. +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/bsv/SyncFIFO.v". + Found 8x8-bit dual-port RAM for signal . + Found 1-bit register for signal . + Found 4-bit register for signal . + Found 4-bit register for signal . + Found 5-bit register for signal . + Found 5-bit register for signal . + Found 4-bit register for signal . + Found 4-bit register for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 8-bit register for signal . + Found 4-bit comparator not equal for signal created at line 126 + Found 4-bit comparator equal for signal created at line 172 + Summary: + inferred 1 RAM(s). + inferred 41 D-type flip-flop(s). + inferred 2 Comparator(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/shep/projects/ocpi/libsrc/hdl/ocpi/ClockInvToBool.v". + Summary: + no macro. +Unit synthesized. + +========================================================================= +HDL Synthesis Report + +Macro Statistics +# RAMs : 99 + 1024x32-bit dual-port RAM : 5 + 1024x32-bit single-port RAM : 1 + 16x10-bit dual-port RAM : 1 + 16x256-bit single-port Read Only RAM : 1 + 16x32-bit single-port Read Only RAM : 4 + 2048x169-bit dual-port RAM : 2 + 2048x32-bit dual-port RAM : 8 + 256x2-bit single-port Read Only RAM : 1 + 2x128-bit dual-port RAM : 1 + 2x146-bit dual-port RAM : 2 + 2x169-bit dual-port RAM : 3 + 2x177-bit dual-port RAM : 1 + 2x32-bit dual-port RAM : 26 + 2x61-bit dual-port RAM : 2 + 2x64-bit dual-port RAM : 1 + 2x72-bit dual-port RAM : 11 + 3x81-bit dual-port RAM : 2 + 4x10-bit single-port Read Only RAM : 1 + 4x16-bit single-port Read Only RAM : 3 + 4x2-bit single-port Read Only RAM : 9 + 4x3-bit single-port Read Only RAM : 12 + 8x10-bit dual-port RAM : 1 + 8x8-bit dual-port RAM : 1 +# Multipliers : 3 + 3x3-bit multiplier : 2 + 4x3-bit multiplier : 1 +# Adders/Subtractors : 804 + 1-bit adder : 120 + 10-bit adder : 1 + 10-bit subtractor : 16 + 11-bit adder : 2 + 12-bit adder : 15 + 12-bit subtractor : 8 + 13-bit adder : 16 + 13-bit subtractor : 2 + 14-bit adder : 7 + 14-bit subtractor : 6 + 16-bit adder : 32 + 16-bit addsub : 8 + 16-bit subtractor : 6 + 17-bit adder : 4 + 17-bit subtractor : 2 + 18-bit adder : 1 + 18-bit subtractor : 1 + 2-bit adder : 43 + 2-bit addsub : 44 + 2-bit subtractor : 72 + 20-bit subtractor : 1 + 22-bit subtractor : 1 + 24-bit adder : 2 + 24-bit subtractor : 1 + 28-bit adder : 3 + 28-bit subtractor : 1 + 3-bit adder : 64 + 3-bit subtractor : 11 + 30-bit adder : 1 + 31-bit adder : 1 + 32-bit adder : 96 + 32-bit subtractor : 3 + 4-bit adder : 29 + 4-bit addsub : 26 + 4-bit subtractor : 35 + 5-bit adder : 46 + 5-bit addsub : 4 + 5-bit subtractor : 21 + 50-bit adder : 2 + 50-bit subtractor : 2 + 6-bit adder : 11 + 6-bit subtractor : 9 + 64-bit subtractor : 1 + 7-bit adder : 3 + 8-bit adder : 23 + 9-bit adder : 1 +# Registers : 5013 + 1-bit register : 3047 + 10-bit register : 17 + 11-bit register : 2 + 112-bit register : 3 + 113-bit register : 2 + 12-bit register : 26 + 128-bit register : 12 + 129-bit register : 4 + 13-bit register : 13 + 130-bit register : 12 + 131-bit register : 4 + 139-bit register : 4 + 14-bit register : 16 + 146-bit register : 10 + 15-bit register : 6 + 153-bit register : 28 + 16-bit register : 93 + 169-bit register : 13 + 17-bit register : 20 + 177-bit register : 3 + 18-bit register : 7 + 182-bit register : 2 + 2-bit register : 290 + 20-bit register : 2 + 2048-bit register : 1 + 22-bit register : 1 + 24-bit register : 2 + 2448-bit register : 22 + 256-bit register : 3 + 27-bit register : 4 + 28-bit register : 24 + 3-bit register : 162 + 30-bit register : 1 + 32-bit register : 233 + 33-bit register : 21 + 34-bit register : 37 + 4-bit register : 391 + 40-bit register : 18 + 41-bit register : 2 + 45-bit register : 5 + 48-bit register : 2 + 5-bit register : 103 + 50-bit register : 5 + 52-bit register : 4 + 56-bit register : 2 + 57-bit register : 1 + 59-bit register : 12 + 6-bit register : 159 + 61-bit register : 8 + 64-bit register : 19 + 65-bit register : 1 + 67-bit register : 6 + 7-bit register : 5 + 72-bit register : 26 + 79-bit register : 2 + 8-bit register : 86 + 81-bit register : 2 + 82-bit register : 2 + 9-bit register : 5 +# Comparators : 462 + 1-bit comparator equal : 72 + 1-bit comparator not equal : 76 + 10-bit comparator greater : 10 + 10-bit comparator lessequal : 6 + 12-bit comparator equal : 2 + 12-bit comparator greater : 3 + 12-bit comparator not equal : 4 + 128-bit comparator not equal : 1 + 13-bit comparator equal : 4 + 13-bit comparator lessequal : 2 + 14-bit comparator equal : 2 + 14-bit comparator lessequal : 2 + 16-bit comparator equal : 8 + 17-bit comparator equal : 1 + 17-bit comparator lessequal : 3 + 2-bit comparator equal : 73 + 2-bit comparator greater : 23 + 2-bit comparator lessequal : 2 + 2-bit comparator not equal : 9 + 22-bit comparator greater : 1 + 24-bit comparator greater : 2 + 28-bit comparator greater : 4 + 3-bit comparator equal : 8 + 3-bit comparator greater : 30 + 3-bit comparator lessequal : 5 + 32-bit comparator equal : 1 + 32-bit comparator greater : 18 + 32-bit comparator not equal : 2 + 4-bit comparator equal : 5 + 4-bit comparator greater : 4 + 4-bit comparator lessequal : 34 + 4-bit comparator not equal : 3 + 5-bit comparator equal : 2 + 5-bit comparator greater : 9 + 5-bit comparator lessequal : 4 + 5-bit comparator not equal : 2 + 6-bit comparator greater : 2 + 6-bit comparator lessequal : 1 + 7-bit comparator equal : 6 + 7-bit comparator lessequal : 3 + 8-bit comparator equal : 8 + 8-bit comparator greater : 5 +# Multiplexers : 3328 + 1-bit 16-to-1 multiplexer : 71 + 1-bit 18-to-1 multiplexer : 1 + 1-bit 2-to-1 multiplexer : 1358 + 1-bit 28-to-1 multiplexer : 1 + 1-bit 4-to-1 multiplexer : 24 + 1-bit 64-to-1 multiplexer : 32 + 1-bit 8-to-1 multiplexer : 297 + 10-bit 2-to-1 multiplexer : 43 + 11-bit 2-to-1 multiplexer : 2 + 11-bit 4-to-1 multiplexer : 16 + 113-bit 2-to-1 multiplexer : 1 + 12-bit 2-to-1 multiplexer : 16 + 128-bit 16-to-1 multiplexer : 1 + 128-bit 2-to-1 multiplexer : 12 + 13-bit 2-to-1 multiplexer : 22 + 14-bit 2-to-1 multiplexer : 16 + 15-bit 2-to-1 multiplexer : 1 + 153-bit 16-to-1 multiplexer : 22 + 16-bit 2-to-1 multiplexer : 54 + 17-bit 2-to-1 multiplexer : 3 + 18-bit 2-to-1 multiplexer : 2 + 2-bit 16-to-1 multiplexer : 2 + 2-bit 2-to-1 multiplexer : 101 + 20-bit 2-to-1 multiplexer : 13 + 22-bit 2-to-1 multiplexer : 1 + 24-bit 2-to-1 multiplexer : 8 + 27-bit 2-to-1 multiplexer : 1 + 3-bit 2-to-1 multiplexer : 131 + 3-bit 3-to-1 multiplexer : 1 + 30-bit 2-to-1 multiplexer : 1 + 32-bit 16-to-1 multiplexer : 2 + 32-bit 2-to-1 multiplexer : 318 + 32-bit 4-to-1 multiplexer : 12 + 32-bit 7-to-1 multiplexer : 1 + 33-bit 2-to-1 multiplexer : 4 + 34-bit 13-to-1 multiplexer : 1 + 34-bit 15-to-1 multiplexer : 1 + 34-bit 2-to-1 multiplexer : 47 + 34-bit 24-to-1 multiplexer : 2 + 34-bit 32-to-1 multiplexer : 1 + 34-bit 4-to-1 multiplexer : 1 + 34-bit 44-to-1 multiplexer : 2 + 34-bit 8-to-1 multiplexer : 1 + 4-bit 2-to-1 multiplexer : 75 + 4-bit 4-to-1 multiplexer : 144 + 40-bit 2-to-1 multiplexer : 2 + 41-bit 2-to-1 multiplexer : 1 + 45-bit 2-to-1 multiplexer : 1 + 5-bit 2-to-1 multiplexer : 146 + 5-bit 8-to-1 multiplexer : 1 + 50-bit 2-to-1 multiplexer : 1 + 52-bit 2-to-1 multiplexer : 3 + 58-bit 2-to-1 multiplexer : 2 + 59-bit 2-to-1 multiplexer : 1 + 6-bit 2-to-1 multiplexer : 86 + 61-bit 2-to-1 multiplexer : 6 + 64-bit 2-to-1 multiplexer : 9 + 65-bit 2-to-1 multiplexer : 3 + 67-bit 2-to-1 multiplexer : 3 + 7-bit 2-to-1 multiplexer : 3 + 72-bit 2-to-1 multiplexer : 48 + 8-bit 15-to-1 multiplexer : 5 + 8-bit 16-to-1 multiplexer : 2 + 8-bit 2-to-1 multiplexer : 127 + 8-bit 4-to-1 multiplexer : 1 + 81-bit 2-to-1 multiplexer : 7 + 82-bit 2-to-1 multiplexer : 2 + 9-bit 2-to-1 multiplexer : 2 +# Logic shifters : 30 + 1-bit shifter logical left : 7 + 18-bit shifter logical left : 1 + 30-bit shifter logical right : 1 + 32-bit shifter logical left : 15 + 7-bit shifter logical left : 6 +# Tristates : 18 + 1-bit tristate buffer : 18 +# FSMs : 31 +# Xors : 77 + 1-bit xor18 : 1 + 1-bit xor2 : 21 + 12-bit xor2 : 2 + 2-bit xor2 : 12 + 22-bit xor2 : 1 + 3-bit xor2 : 27 + 32-bit xor2 : 2 + 4-bit xor2 : 6 + 5-bit xor2 : 4 + 8-bit xor2 : 1 + +========================================================================= +INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing. + +========================================================================= +* Advanced HDL Synthesis * +========================================================================= + +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . +WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . +WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . +WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . +WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + +Synthesizing (advanced) Unit . +INFO:Xst:3226 - The RAM will be implemented as a BLOCK RAM, absorbing the following register(s): + ----------------------------------------------------------------------- + | ram_type | Block | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 1024-word x 32-bit | | + | mode | write-first | | + | clkA | connected to signal | rise | + | enA | connected to signal | high | + | weA | connected to signal | high | + | addrA | connected to signal | | + | diA | connected to signal | | + | doA | connected to signal | | + ----------------------------------------------------------------------- + | optimization | speed | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +INFO:Xst:3226 - The RAM will be implemented as a BLOCK RAM, absorbing the following register(s): + ----------------------------------------------------------------------- + | ram_type | Block | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 1024-word x 32-bit | | + | mode | write-first | | + | clkA | connected to signal | rise | + | enA | connected to signal | high | + | weA | connected to signal | high | + | addrA | connected to signal | | + | diA | connected to signal | | + | doA | connected to signal | | + ----------------------------------------------------------------------- + | optimization | speed | | + ----------------------------------------------------------------------- + | Port B | + | aspect ratio | 1024-word x 32-bit | | + | mode | write-first | | + | clkB | connected to signal | rise | + | enB | connected to signal | high | + | weB | connected to signal | high | + | addrB | connected to signal | | + | diB | connected to signal | | + | doB | connected to signal | | + ----------------------------------------------------------------------- + | optimization | speed | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +INFO:Xst:3226 - The RAM will be implemented as a BLOCK RAM, absorbing the following register(s): + ----------------------------------------------------------------------- + | ram_type | Block | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 2048-word x 169-bit | | + | mode | write-first | | + | clkA | connected to signal | rise | + | enA | connected to signal | high | + | weA | connected to signal | high | + | addrA | connected to signal | | + | diA | connected to signal | | + | doA | connected to signal | | + ----------------------------------------------------------------------- + | optimization | speed | | + ----------------------------------------------------------------------- + | Port B | + | aspect ratio | 2048-word x 169-bit | | + | mode | write-first | | + | clkB | connected to signal | rise | + | enB | connected to signal | high | + | weB | connected to signal | high | + | addrB | connected to signal | | + | diB | connected to signal | | + | doB | connected to signal | | + ----------------------------------------------------------------------- + | optimization | speed | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +INFO:Xst:3226 - The RAM will be implemented as a BLOCK RAM, absorbing the following register(s): + ----------------------------------------------------------------------- + | ram_type | Block | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 2048-word x 32-bit | | + | mode | write-first | | + | clkA | connected to signal | rise | + | enA | connected to signal | high | + | weA | connected to signal | high | + | addrA | connected to signal | | + | diA | connected to signal | | + | doA | connected to signal | | + ----------------------------------------------------------------------- + | optimization | speed | | + ----------------------------------------------------------------------- + | Port B | + | aspect ratio | 2048-word x 32-bit | | + | mode | write-first | | + | clkB | connected to signal | rise | + | enB | connected to signal | high | + | weB | connected to signal | high | + | addrB | connected to signal | | + | diB | connected to signal | | + | doB | connected to signal | | + ----------------------------------------------------------------------- + | optimization | speed | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into accumulator : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +INFO:Xst:3231 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 16-word x 32-bit | | + | weA | connected to signal | high | + | addrA | connected to signal > | | + | diA | connected to signal | | + | doA | connected to internal node | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +INFO:Xst:3218 - HDL ADVISOR - The RAM will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 2-word x 32-bit | | + | clkA | connected to signal | rise | + | weA | connected to internal node | high | + | addrA | connected to signal | | + | diA | connected to signal | | + ----------------------------------------------------------------------- + | Port B | + | aspect ratio | 2-word x 32-bit | | + | addrB | connected to signal | | + | doB | connected to internal node | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +INFO:Xst:3218 - HDL ADVISOR - The RAM will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 2-word x 72-bit | | + | clkA | connected to signal | rise | + | weA | connected to internal node | high | + | addrA | connected to signal | | + | diA | connected to signal | | + ----------------------------------------------------------------------- + | Port B | + | aspect ratio | 2-word x 72-bit | | + | addrB | connected to signal | | + | doB | connected to internal node | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +INFO:Xst:3218 - HDL ADVISOR - The RAM will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 2-word x 61-bit | | + | clkA | connected to signal | rise | + | weA | connected to internal node | high | + | addrA | connected to signal | | + | diA | connected to signal | | + ----------------------------------------------------------------------- + | Port B | + | aspect ratio | 2-word x 61-bit | | + | addrB | connected to signal | | + | doB | connected to internal node | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +INFO:Xst:3218 - HDL ADVISOR - The RAM will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 2-word x 169-bit | | + | clkA | connected to signal | rise | + | weA | connected to internal node | high | + | addrA | connected to signal | | + | diA | connected to signal | | + ----------------------------------------------------------------------- + | Port B | + | aspect ratio | 2-word x 169-bit | | + | addrB | connected to signal | | + | doB | connected to internal node | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +INFO:Xst:3218 - HDL ADVISOR - The RAM will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 2-word x 146-bit | | + | clkA | connected to signal | rise | + | weA | connected to internal node | high | + | addrA | connected to signal | | + | diA | connected to signal | | + ----------------------------------------------------------------------- + | Port B | + | aspect ratio | 2-word x 146-bit | | + | addrB | connected to signal | | + | doB | connected to internal node | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +INFO:Xst:3231 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 3-word x 81-bit | | + | clkA | connected to signal | rise | + | weA | connected to internal node | high | + | addrA | connected to signal | | + | diA | connected to signal | | + ----------------------------------------------------------------------- + | Port B | + | aspect ratio | 3-word x 81-bit | | + | addrB | connected to signal | | + | doB | connected to internal node | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +INFO:Xst:3231 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 2-word x 64-bit | | + | clkA | connected to signal | rise | + | weA | connected to signal | high | + | addrA | connected to signal > | | + | diA | connected to signal | | + ----------------------------------------------------------------------- + | Port B | + | aspect ratio | 2-word x 64-bit | | + | addrB | connected to signal > | | + | doB | connected to internal node | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +INFO:Xst:3231 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 2-word x 177-bit | | + | clkA | connected to signal | rise | + | weA | connected to signal | high | + | addrA | connected to signal > | | + | diA | connected to signal | | + ----------------------------------------------------------------------- + | Port B | + | aspect ratio | 2-word x 177-bit | | + | addrB | connected to signal > | | + | doB | connected to internal node | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +INFO:Xst:3231 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 2-word x 128-bit | | + | clkA | connected to signal | rise | + | weA | connected to signal | high | + | addrA | connected to signal > | | + | diA | connected to signal | | + ----------------------------------------------------------------------- + | Port B | + | aspect ratio | 2-word x 128-bit | | + | addrB | connected to signal > | | + | doB | connected to internal node | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +INFO:Xst:3231 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 8-word x 10-bit | | + | clkA | connected to signal | rise | + | weA | connected to signal | high | + | addrA | connected to signal > | | + | diA | connected to signal | | + ----------------------------------------------------------------------- + | Port B | + | aspect ratio | 8-word x 10-bit | | + | addrB | connected to signal > | | + | doB | connected to internal node | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +INFO:Xst:3231 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 16-word x 10-bit | | + | clkA | connected to signal | rise | + | weA | connected to signal | high | + | addrA | connected to signal > | | + | diA | connected to signal | | + ----------------------------------------------------------------------- + | Port B | + | aspect ratio | 16-word x 10-bit | | + | addrB | connected to signal > | | + | doB | connected to internal node | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +INFO:Xst:3231 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 8-word x 8-bit | | + | clkA | connected to signal | rise | + | weA | connected to signal | high | + | addrA | connected to signal > | | + | diA | connected to signal | | + ----------------------------------------------------------------------- + | Port B | + | aspect ratio | 8-word x 8-bit | | + | addrB | connected to signal > | | + | doB | connected to internal node | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . + The following adders/subtractors are grouped into adder tree : + in block , in block , in block , in block . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +INFO:Xst:3231 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 4-word x 3-bit | | + | weA | connected to signal | high | + | addrA | connected to signal > | | + | diA | connected to signal | | + | doA | connected to internal node | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +INFO:Xst:3231 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 4-word x 3-bit | | + | weA | connected to signal | high | + | addrA | connected to signal > | | + | diA | connected to signal | | + | doA | connected to internal node | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +INFO:Xst:3231 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 4-word x 3-bit | | + | weA | connected to signal | high | + | addrA | connected to signal > | | + | diA | connected to signal | | + | doA | connected to internal node | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +INFO:Xst:3231 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 4-word x 3-bit | | + | weA | connected to signal | high | + | addrA | connected to signal > | | + | diA | connected to signal | | + | doA | connected to internal node | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +INFO:Xst:3231 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 4-word x 10-bit | | + | weA | connected to signal | high | + | addrA | connected to signal > | | + | diA | connected to signal | | + | doA | connected to internal node | | + ----------------------------------------------------------------------- +INFO:Xst:3231 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 4-word x 3-bit | | + | weA | connected to signal | high | + | addrA | connected to signal > | | + | diA | connected to signal | | + | doA | connected to internal node | | + ----------------------------------------------------------------------- +INFO:Xst:3218 - HDL ADVISOR - The RAM will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 256-word x 2-bit | | + | weA | connected to signal | high | + | addrA | connected to signal | | + | diA | connected to signal | | + | doA | connected to internal node | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +INFO:Xst:3231 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 4-word x 3-bit | | + | weA | connected to signal | high | + | addrA | connected to signal > | | + | diA | connected to signal | | + | doA | connected to internal node | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +INFO:Xst:3231 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 4-word x 3-bit | | + | weA | connected to signal | high | + | addrA | connected to signal > | | + | diA | connected to signal | | + | doA | connected to internal node | | + ----------------------------------------------------------------------- +INFO:Xst:3231 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 4-word x 16-bit | | + | weA | connected to signal | high | + | addrA | connected to signal > | | + | diA | connected to signal | | + | doA | connected to signal | | + ----------------------------------------------------------------------- +INFO:Xst:3218 - HDL ADVISOR - The RAM will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 4-word x 2-bit | | + | weA | connected to signal | high | + | addrA | connected to signal > | | + | diA | connected to signal | | + | doA | connected to internal node | | + ----------------------------------------------------------------------- +INFO:Xst:3218 - HDL ADVISOR - The RAM will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 4-word x 2-bit | | + | weA | connected to signal | high | + | addrA | connected to signal > | | + | diA | connected to signal | | + | doA | connected to internal node | | + ----------------------------------------------------------------------- +INFO:Xst:3218 - HDL ADVISOR - The RAM will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 4-word x 2-bit | | + | weA | connected to signal | high | + | addrA | connected to signal > | | + | diA | connected to signal | | + | doA | connected to internal node | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +INFO:Xst:3231 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 4-word x 3-bit | | + | weA | connected to signal | high | + | addrA | connected to signal > | | + | diA | connected to signal | | + | doA | connected to internal node | | + ----------------------------------------------------------------------- +INFO:Xst:3231 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 4-word x 16-bit | | + | weA | connected to signal | high | + | addrA | connected to signal > | | + | diA | connected to signal | | + | doA | connected to signal | | + ----------------------------------------------------------------------- +INFO:Xst:3218 - HDL ADVISOR - The RAM will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 4-word x 2-bit | | + | weA | connected to signal | high | + | addrA | connected to signal > | | + | diA | connected to signal | | + | doA | connected to internal node | | + ----------------------------------------------------------------------- +INFO:Xst:3218 - HDL ADVISOR - The RAM will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 4-word x 2-bit | | + | weA | connected to signal | high | + | addrA | connected to signal > | | + | diA | connected to signal | | + | doA | connected to internal node | | + ----------------------------------------------------------------------- +INFO:Xst:3218 - HDL ADVISOR - The RAM will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 4-word x 2-bit | | + | weA | connected to signal | high | + | addrA | connected to signal > | | + | diA | connected to signal | | + | doA | connected to internal node | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +INFO:Xst:3218 - HDL ADVISOR - The RAM will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 4-word x 16-bit | | + | weA | connected to signal | high | + | addrA | connected to signal | | + | diA | connected to signal | | + | doA | connected to signal | | + ----------------------------------------------------------------------- +INFO:Xst:3218 - HDL ADVISOR - The RAM will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 4-word x 2-bit | | + | weA | connected to signal | high | + | addrA | connected to signal > | | + | diA | connected to signal | | + | doA | connected to internal node | | + ----------------------------------------------------------------------- +INFO:Xst:3218 - HDL ADVISOR - The RAM will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 4-word x 2-bit | | + | weA | connected to signal | high | + | addrA | connected to signal > | | + | diA | connected to signal | | + | doA | connected to internal node | | + ----------------------------------------------------------------------- +INFO:Xst:3218 - HDL ADVISOR - The RAM will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 4-word x 2-bit | | + | weA | connected to signal | high | + | addrA | connected to signal > | | + | diA | connected to signal | | + | doA | connected to internal node | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . + The following adders/subtractors are grouped into adder tree : + in block , in block , in block , in block , in block , in block , in block , in block . +INFO:Xst:3231 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 4-word x 3-bit | | + | weA | connected to signal | high | + | addrA | connected to signal > | | + | diA | connected to signal | | + | doA | connected to internal node | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . + The following adders/subtractors are grouped into adder tree : + in block , in block , in block , in block , in block , in block , in block , in block . +INFO:Xst:3231 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 4-word x 3-bit | | + | weA | connected to signal | high | + | addrA | connected to signal > | | + | diA | connected to signal | | + | doA | connected to internal node | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +INFO:Xst:3231 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 4-word x 3-bit | | + | weA | connected to signal | high | + | addrA | connected to signal > | | + | diA | connected to signal | | + | doA | connected to internal node | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +INFO:Xst:3231 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 16-word x 256-bit | | + | weA | connected to signal | high | + | addrA | connected to signal | | + | diA | connected to signal | | + | doA | connected to internal node | | + ----------------------------------------------------------------------- +INFO:Xst:3218 - HDL ADVISOR - The RAM will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 4-word x 3-bit | | + | weA | connected to signal | high | + | addrA | connected to signal | | + | diA | connected to signal | | + | doA | connected to internal node | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +The following registers are absorbed into counter : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. + Found 16-bit dynamic shift register for signal >. +Unit synthesized (advanced). + +========================================================================= +Advanced HDL Synthesis Report + +Macro Statistics +# RAMs : 99 + 1024x32-bit dual-port block RAM : 5 + 1024x32-bit single-port block RAM : 1 + 16x10-bit dual-port distributed RAM : 1 + 16x256-bit single-port distributed Read Only RAM : 1 + 16x32-bit single-port distributed Read Only RAM : 4 + 2048x169-bit dual-port block RAM : 2 + 2048x32-bit dual-port block RAM : 8 + 256x2-bit single-port distributed Read Only RAM : 1 + 2x128-bit dual-port distributed RAM : 1 + 2x146-bit dual-port distributed RAM : 2 + 2x169-bit dual-port distributed RAM : 3 + 2x177-bit dual-port distributed RAM : 1 + 2x32-bit dual-port distributed RAM : 26 + 2x61-bit dual-port distributed RAM : 2 + 2x64-bit dual-port distributed RAM : 1 + 2x72-bit dual-port distributed RAM : 11 + 3x81-bit dual-port distributed RAM : 2 + 4x10-bit single-port distributed Read Only RAM : 1 + 4x16-bit single-port distributed Read Only RAM : 3 + 4x2-bit single-port distributed Read Only RAM : 9 + 4x3-bit single-port distributed Read Only RAM : 12 + 8x10-bit dual-port distributed RAM : 1 + 8x8-bit dual-port distributed RAM : 1 +# Multipliers : 3 + 3x3-bit multiplier : 2 + 4x3-bit multiplier : 1 +# Adders/Subtractors : 411 + 1-bit adder : 101 + 10-bit subtractor : 15 + 11-bit adder : 2 + 12-bit adder : 4 + 12-bit subtractor : 8 + 13-bit adder : 16 + 13-bit subtractor : 2 + 14-bit adder : 5 + 14-bit subtractor : 4 + 16-bit adder : 12 + 16-bit subtractor : 4 + 17-bit adder : 4 + 17-bit subtractor : 2 + 18-bit subtractor : 1 + 2-bit adder : 20 + 2-bit adder carry in : 1 + 2-bit subtractor : 64 + 24-bit subtractor : 1 + 28-bit subtractor : 1 + 3-bit adder : 3 + 3-bit adder carry in : 1 + 3-bit subtractor : 8 + 32-bit adder : 40 + 32-bit subtractor : 3 + 4-bit adder : 4 + 4-bit subtractor : 30 + 5-bit adder : 4 + 5-bit addsub : 1 + 5-bit subtractor : 17 + 50-bit subtractor : 2 + 6-bit adder : 11 + 6-bit subtractor : 5 + 64-bit subtractor : 1 + 7-bit adder : 2 + 8-bit adder : 12 +# Adder Trees : 3 + 2-bit / 5-inputs adder tree : 1 + 5-bit / 9-inputs adder tree : 2 +# Counters : 383 + 1-bit up counter : 107 + 10-bit down counter : 1 + 10-bit up counter : 1 + 12-bit up counter : 9 + 16-bit down counter : 2 + 16-bit up counter : 20 + 16-bit updown counter : 8 + 18-bit up counter : 1 + 2-bit down counter : 8 + 2-bit up counter : 14 + 2-bit updown counter : 44 + 20-bit down counter : 1 + 22-bit down counter : 1 + 28-bit up counter : 3 + 3-bit down counter : 3 + 3-bit up counter : 15 + 30-bit up counter : 1 + 32-bit up counter : 53 + 4-bit down counter : 5 + 4-bit up counter : 25 + 4-bit updown counter : 26 + 5-bit down counter : 4 + 5-bit up counter : 12 + 5-bit updown counter : 3 + 6-bit down counter : 4 + 6-bit up counter : 1 + 7-bit up counter : 2 + 8-bit up counter : 8 + 9-bit up counter : 1 +# Accumulators : 40 + 12-bit up accumulator cin : 2 + 14-bit down loadable accumulator : 2 + 14-bit up accumulator : 5 + 16-bit up accumulator : 2 + 3-bit up accumulator cin : 22 + 32-bit up loadable accumulator : 1 + 4-bit up loadable accumulator : 1 + 50-bit up accumulator : 1 + 50-bit up loadable accumulator : 1 + 6-bit up accumulator : 1 + 8-bit up accumulator cin : 1 + 8-bit up loadable accumulator : 1 +# Registers : 37377 + Flip-Flops : 37377 +# Shift Registers : 3498 + 16-bit dynamic shift register : 3498 +# Comparators : 462 + 1-bit comparator equal : 72 + 1-bit comparator not equal : 76 + 10-bit comparator greater : 10 + 10-bit comparator lessequal : 6 + 12-bit comparator equal : 2 + 12-bit comparator greater : 3 + 12-bit comparator not equal : 4 + 128-bit comparator not equal : 1 + 13-bit comparator equal : 4 + 13-bit comparator lessequal : 2 + 14-bit comparator equal : 2 + 14-bit comparator lessequal : 2 + 16-bit comparator equal : 8 + 17-bit comparator equal : 1 + 17-bit comparator lessequal : 3 + 2-bit comparator equal : 73 + 2-bit comparator greater : 23 + 2-bit comparator lessequal : 2 + 2-bit comparator not equal : 9 + 22-bit comparator greater : 1 + 24-bit comparator greater : 2 + 28-bit comparator greater : 4 + 3-bit comparator equal : 8 + 3-bit comparator greater : 30 + 3-bit comparator lessequal : 5 + 32-bit comparator equal : 1 + 32-bit comparator greater : 18 + 32-bit comparator not equal : 2 + 4-bit comparator equal : 5 + 4-bit comparator greater : 4 + 4-bit comparator lessequal : 34 + 4-bit comparator not equal : 3 + 5-bit comparator equal : 2 + 5-bit comparator greater : 9 + 5-bit comparator lessequal : 4 + 5-bit comparator not equal : 2 + 6-bit comparator greater : 2 + 6-bit comparator lessequal : 1 + 7-bit comparator equal : 6 + 7-bit comparator lessequal : 3 + 8-bit comparator equal : 8 + 8-bit comparator greater : 5 +# Multiplexers : 4602 + 1-bit 15-to-1 multiplexer : 24 + 1-bit 16-to-1 multiplexer : 87 + 1-bit 18-to-1 multiplexer : 1 + 1-bit 2-to-1 multiplexer : 2609 + 1-bit 28-to-1 multiplexer : 1 + 1-bit 32-to-1 multiplexer : 34 + 1-bit 4-to-1 multiplexer : 312 + 1-bit 64-to-1 multiplexer : 32 + 1-bit 8-to-1 multiplexer : 297 + 10-bit 2-to-1 multiplexer : 38 + 11-bit 2-to-1 multiplexer : 2 + 11-bit 4-to-1 multiplexer : 16 + 113-bit 2-to-1 multiplexer : 1 + 12-bit 2-to-1 multiplexer : 15 + 128-bit 2-to-1 multiplexer : 12 + 13-bit 2-to-1 multiplexer : 22 + 14-bit 2-to-1 multiplexer : 14 + 15-bit 2-to-1 multiplexer : 1 + 16-bit 2-to-1 multiplexer : 38 + 17-bit 2-to-1 multiplexer : 3 + 18-bit 2-to-1 multiplexer : 2 + 2-bit 2-to-1 multiplexer : 89 + 20-bit 2-to-1 multiplexer : 13 + 24-bit 2-to-1 multiplexer : 8 + 27-bit 2-to-1 multiplexer : 1 + 3-bit 2-to-1 multiplexer : 122 + 3-bit 3-to-1 multiplexer : 1 + 32-bit 16-to-1 multiplexer : 2 + 32-bit 2-to-1 multiplexer : 285 + 32-bit 4-to-1 multiplexer : 12 + 32-bit 7-to-1 multiplexer : 1 + 33-bit 2-to-1 multiplexer : 4 + 34-bit 13-to-1 multiplexer : 1 + 34-bit 15-to-1 multiplexer : 1 + 34-bit 2-to-1 multiplexer : 36 + 34-bit 24-to-1 multiplexer : 2 + 34-bit 4-to-1 multiplexer : 1 + 34-bit 44-to-1 multiplexer : 2 + 34-bit 8-to-1 multiplexer : 1 + 4-bit 2-to-1 multiplexer : 56 + 4-bit 4-to-1 multiplexer : 72 + 40-bit 2-to-1 multiplexer : 2 + 41-bit 2-to-1 multiplexer : 1 + 45-bit 2-to-1 multiplexer : 1 + 5-bit 2-to-1 multiplexer : 31 + 5-bit 8-to-1 multiplexer : 1 + 52-bit 2-to-1 multiplexer : 2 + 58-bit 2-to-1 multiplexer : 2 + 59-bit 2-to-1 multiplexer : 1 + 6-bit 2-to-1 multiplexer : 84 + 61-bit 2-to-1 multiplexer : 6 + 64-bit 2-to-1 multiplexer : 9 + 65-bit 2-to-1 multiplexer : 3 + 67-bit 2-to-1 multiplexer : 3 + 7-bit 2-to-1 multiplexer : 3 + 72-bit 2-to-1 multiplexer : 48 + 8-bit 15-to-1 multiplexer : 2 + 8-bit 2-to-1 multiplexer : 121 + 8-bit 4-to-1 multiplexer : 1 + 81-bit 2-to-1 multiplexer : 6 + 82-bit 2-to-1 multiplexer : 2 + 9-bit 2-to-1 multiplexer : 2 +# Logic shifters : 30 + 1-bit shifter logical left : 7 + 18-bit shifter logical left : 1 + 30-bit shifter logical right : 1 + 32-bit shifter logical left : 15 + 7-bit shifter logical left : 6 +# FSMs : 31 +# Xors : 77 + 1-bit xor18 : 1 + 1-bit xor2 : 21 + 12-bit xor2 : 2 + 2-bit xor2 : 12 + 22-bit xor2 : 1 + 3-bit xor2 : 27 + 32-bit xor2 : 2 + 4-bit xor2 : 6 + 5-bit xor2 : 4 + 8-bit xor2 : 1 + +========================================================================= + +========================================================================= +* Low Level Synthesis * +========================================================================= +WARNING:Xst:1989 - Unit : instances , of unit are equivalent, second instance is removed +WARNING:Xst:1989 - Unit : instances , of unit are equivalent, second instance is removed +WARNING:Xst:1989 - Unit : instances , of unit are equivalent, second instance is removed +WARNING:Xst:1989 - Unit : instances , of unit are equivalent, second instance is removed +WARNING:Xst:1989 - Unit : instances , of unit are equivalent, second instance is removed +WARNING:Xst:1989 - Unit : instances , of unit are equivalent, second instance is removed +WARNING:Xst:1989 - Unit : instances , of unit are equivalent, second instance is removed +WARNING:Xst:1989 - Unit : instances , of unit are equivalent, second instance is removed +WARNING:Xst:1989 - Unit : instances , of unit are equivalent, second instance is removed +WARNING:Xst:1989 - Unit : instances , of unit are equivalent, second instance is removed +Analyzing FSM for best encoding. +Optimizing FSM on signal with sequential encoding. +Optimizing FSM on signal with sequential encoding. +Optimizing FSM on signal with sequential encoding. +Optimizing FSM on signal with sequential encoding. +------------------- + State | Encoding +------------------- + 00001 | 000 + 00010 | 001 + 00100 | 010 + 01000 | 011 + 10000 | 100 +------------------- +Analyzing FSM for best encoding. +Optimizing FSM on signal with gray encoding. +Optimizing FSM on signal with gray encoding. +Optimizing FSM on signal with gray encoding. +Optimizing FSM on signal with gray encoding. +------------------- + State | Encoding +------------------- + 0001 | 00 + 0010 | 01 + 0100 | 11 + 1000 | 10 +------------------- +Analyzing FSM for best encoding. +Optimizing FSM on signal with gray encoding. +Optimizing FSM on signal with gray encoding. +Optimizing FSM on signal with gray encoding. +Optimizing FSM on signal with gray encoding. +------------------- + State | Encoding +------------------- + 0011 | 000 + 0110 | 001 + 0111 | 011 + 0001 | 010 + 1000 | 110 + 1001 | 111 + 0010 | 101 +------------------- +Analyzing FSM for best encoding. +Optimizing FSM on signal with one-hot encoding. +Optimizing FSM on signal with one-hot encoding. +Optimizing FSM on signal with one-hot encoding. +Optimizing FSM on signal with one-hot encoding. +---------------------------------------------------- + State | Encoding +---------------------------------------------------- + 0000000000000100000000000 | 000000000000000000001 + 0010000000000000000000000 | 000000000000000000010 + 0000100000000000000000000 | 000000000000000000100 + 0100000000000000000000000 | 000000000000000001000 + 1000000000000000000000000 | 000000000000000010000 + 0000000010000000000000000 | 000000000000000100000 + 0000000100000000000000000 | 000000000000001000000 + 0000000000000000000000010 | 000000000000010000000 + 0000001000000000000000000 | 000000000000100000000 + 0000000000000000000000001 | 000000000001000000000 + 0000000000010000000000000 | 000000000010000000000 + 0000000000000000010000000 | 000000000100000000000 + 0000010000000000000000000 | 000000001000000000000 + 0000000000000000000000100 | 000000010000000000000 + 0000000000000000000001000 | 000000100000000000000 + 0000000000000000001000000 | 000001000000000000000 + 0000000000100000000000000 | 000010000000000000000 + 0001000000000000000000000 | 000100000000000000000 + 0000000000000000100000000 | 001000000000000000000 + 0000000000000001000000000 | 010000000000000000000 + 0000000000000010000000000 | 100000000000000000000 +---------------------------------------------------- +Analyzing FSM for best encoding. +Optimizing FSM on signal with gray encoding. +------------------- + State | Encoding +------------------- + 00 | 00 + 10 | 01 + 01 | 11 +------------------- +INFO:Xst:2146 - In block , Counter are equivalent, XST will keep only . +INFO:Xst:2146 - In block , Accumulator are equivalent, XST will keep only . +INFO:Xst:2146 - In block , Accumulator are equivalent, XST will keep only . +Analyzing FSM for best encoding. +Optimizing FSM on signal with one-hot encoding. +------------------------------------ + State | Encoding +------------------------------------ + 00000 | 0000000000000000000000001 + 11000 | 0000000000000000000000010 + 00001 | 0000000000000000000000100 + 00010 | 0000000000000000000001000 + 00011 | 0000000000000000000010000 + 00100 | 0000000000000000000100000 + 00111 | 0000000000000000001000000 + 01000 | 0000000000000000010000000 + 01001 | 0000000000000000100000000 + 01010 | 0000000000000001000000000 + 01011 | 0000000000000010000000000 + 01100 | 0000000000000100000000000 + 01111 | 0000000000001000000000000 + 10000 | 0000000000010000000000000 + 10001 | 0000000000100000000000000 + 10010 | 0000000001000000000000000 + 10011 | 0000000010000000000000000 + 10100 | 0000000100000000000000000 + 10111 | 0000001000000000000000000 + 00101 | 0000010000000000000000000 + 00110 | 0000100000000000000000000 + 01101 | 0001000000000000000000000 + 01110 | 0010000000000000000000000 + 10101 | 0100000000000000000000000 + 10110 | 1000000000000000000000000 +------------------------------------ +Analyzing FSM for best encoding. +Optimizing FSM on signal with one-hot encoding. +-------------------- + State | Encoding +-------------------- + 0000 | 000000001 + 0111 | 000000010 + 0001 | 000000100 + 0010 | 000001000 + 0101 | 000010000 + 0110 | 000100000 + 0011 | 001000000 + 0100 | 010000000 + 1010 | 100000000 +-------------------- +Analyzing FSM for best encoding. +Optimizing FSM on signal with one-hot encoding. +------------------- + State | Encoding +------------------- + 000 | 0000001 + 001 | 0000010 + 010 | 0000100 + 011 | 0001000 + 100 | 0010000 + 101 | 0100000 + 110 | 1000000 +------------------- +Analyzing FSM for best encoding. +Optimizing FSM on signal with one-hot encoding. +------------------------------------------------- + State | Encoding +------------------------------------------------- + 000000 | 0000000000000000000000000000000000001 + 000001 | 0000000000000000000000000000000000010 + 000010 | 0000000000000000000000000000000000100 + 000011 | 0000000000000000000000000000000001000 + 000100 | 0000000000000000000000000000000010000 + 010110 | 0000000000000000000000000000000100000 + 000101 | 0000000000000000000000000000001000000 + 000110 | 0000000000000000000000000000010000000 + 000111 | 0000000000000000000000000000100000000 + 001000 | 0000000000000000000000000001000000000 + 001001 | 0000000000000000000000000010000000000 + 001010 | 0000000000000000000000000100000000000 + 001011 | 0000000000000000000000001000000000000 + 001100 | 0000000000000000000000010000000000000 + 001101 | 0000000000000000000000100000000000000 + 010101 | 0000000000000000000001000000000000000 + 011010 | 0000000000000000000010000000000000000 + 011001 | 0000000000000000000100000000000000000 + 001111 | 0000000000000000001000000000000000000 + 010010 | 0000000000000000010000000000000000000 + 010100 | 0000000000000000100000000000000000000 + 010011 | 0000000000000001000000000000000000000 + 010111 | 0000000000000010000000000000000000000 + 011111 | 0000000000000100000000000000000000000 + 011000 | 0000000000001000000000000000000000000 + 011011 | 0000000000010000000000000000000000000 + 011100 | 0000000000100000000000000000000000000 + 010001 | 0000000001000000000000000000000000000 + 101000 | 0000000010000000000000000000000000000 + 001110 | 0000000100000000000000000000000000000 + 100011 | 0000001000000000000000000000000000000 + 101010 | 0000010000000000000000000000000000000 + 010000 | 0000100000000000000000000000000000000 + 011110 | unreached + 100000 | 0001000000000000000000000000000000000 + 100001 | 0010000000000000000000000000000000000 + 100010 | 0100000000000000000000000000000000000 + 100101 | unreached + 100100 | unreached + 100111 | unreached + 011101 | unreached + 101001 | 1000000000000000000000000000000000000 +------------------------------------------------- +INFO:Xst:2146 - In block , Counter are equivalent, XST will keep only . +Analyzing FSM for best encoding. +Optimizing FSM on signal with user encoding. +------------------- + State | Encoding +------------------- + 0000 | 0000 + 0001 | 0001 + 0100 | 0100 + 0011 | 0011 + 1000 | 1000 + 0111 | 0111 + 0110 | 0110 + 0101 | 0101 + 0010 | 0010 +------------------- +Analyzing FSM for best encoding. +Optimizing FSM on signal with sequential encoding. +------------------- + State | Encoding +------------------- + 000 | 000 + 001 | 001 + 010 | 010 + 110 | 011 + 100 | 100 + 101 | 101 +------------------- +Analyzing FSM for best encoding. +Optimizing FSM on signal with user encoding. +------------------- + State | Encoding +------------------- + 00000 | 00000 + 00001 | 00001 + 00010 | 00010 + 00011 | 00011 + 01100 | 01100 + 01011 | 01011 + 00100 | 00100 + 00111 | 00111 + 00101 | 00101 + 01101 | 01101 + 00110 | 00110 + 01000 | 01000 + 10010 | 10010 + 01010 | 01010 + 01111 | 01111 + 01110 | 01110 + 10000 | 10000 + 01001 | 01001 +------------------- +Analyzing FSM for best encoding. +Optimizing FSM on signal with user encoding. +------------------- + State | Encoding +------------------- + 0000 | 0000 + 0001 | 0001 + 0010 | 0010 + 0011 | 0011 + 0100 | 0100 + 0110 | 0110 + 0101 | 0101 + 0111 | 0111 + 1000 | 1000 + 1001 | 1001 +------------------- +Analyzing FSM for best encoding. +Optimizing FSM on signal with user encoding. +------------------- + State | Encoding +------------------- + 000 | 000 + 001 | 001 + 010 | 010 + 011 | 011 + 100 | 100 +------------------- +Analyzing FSM for best encoding. +Optimizing FSM on signal with user encoding. +------------------- + State | Encoding +------------------- + 00 | 00 + 01 | 01 + 10 | 10 +------------------- +Analyzing FSM for best encoding. +Optimizing FSM on signal with one-hot encoding. +---------------------- + State | Encoding +---------------------- + 0000 | 00000000001 + 1010 | 00000000010 + 0001 | 00000000100 + 0010 | 00000001000 + 0011 | 00000010000 + 0100 | 00000100000 + 0101 | 00001000000 + 0110 | 00010000000 + 0111 | 00100000000 + 1000 | 01000000000 + 1001 | 10000000000 +---------------------- +Analyzing FSM for best encoding. +Optimizing FSM on signal with one-hot encoding. +---------------------------------------------------------------------------------------------------------------------------------------------------------- + State | Encoding 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00100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + 01000001 | 01000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + 10101010 | 10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +---------------------------------------------------------------------------------------------------------------------------------------------------------- +Analyzing FSM for best encoding. +Optimizing FSM on signal with one-hot encoding. +---------------------- + State | Encoding +---------------------- + 0000 | 00000000001 + 1001 | 00000000010 + 0001 | 00000000100 + 0010 | 00000001000 + 0011 | 00000010000 + 0101 | 00000100000 + 0110 | 00001000000 + 0111 | 00010000000 + 0100 | 00100000000 + 1000 | 01000000000 + 1010 | 10000000000 +---------------------- +Analyzing FSM for best encoding. +Optimizing FSM on signal with one-hot encoding. +---------------------- + State | Encoding +---------------------- + 0000 | 00000000001 + 1001 | 00000000010 + 0001 | 00000000100 + 0010 | 00000001000 + 0011 | 00000010000 + 0101 | 00000100000 + 0110 | 00001000000 + 0111 | 00010000000 + 0100 | 00100000000 + 1000 | 01000000000 + 1010 | 10000000000 +---------------------- +INFO:Xst:1901 - Instance use_ramb36.ramb36 in unit use_ramb36.ramb36 of type RAMB36 has been replaced by RAMB36E1 +INFO:Xst:1901 - Instance GEN2_LINK.pipe_clk_bufgmux in unit pcie_clocking_v6 of type BUFGMUX has been replaced by BUFGCTRL +INFO:Xst:1901 - Instance gmii_rxc_dly in unit mkGMAC of type IODELAY has been replaced by IODELAYE1 +INFO:Xst:1901 - Instance gmii_rx_clk in unit mkGMAC of type BUFIO has been replaced by BUFIODQS +INFO:Xst:1901 - Instance gen_ck_cpt[0].u_bufio_cpt in unit phy_rdclk_gen of type BUFIO has been replaced by BUFIODQS +INFO:Xst:1901 - Instance gen_ck_cpt[1].u_bufio_cpt in unit phy_rdclk_gen of type BUFIO has been replaced by BUFIODQS +INFO:Xst:1901 - Instance gen_ck_cpt[2].u_bufio_cpt in unit phy_rdclk_gen of type BUFIO has been replaced by BUFIODQS +INFO:Xst:1901 - Instance gen_ck_cpt[3].u_bufio_cpt in unit phy_rdclk_gen of type BUFIO has been replaced by BUFIODQS +INFO:Xst:1901 - Instance gen_ck_cpt[4].u_bufio_cpt in unit phy_rdclk_gen of type BUFIO has been replaced by BUFIODQS +INFO:Xst:1901 - Instance gen_ck_cpt[5].u_bufio_cpt in unit phy_rdclk_gen of type BUFIO has been replaced by BUFIODQS +INFO:Xst:1901 - Instance gen_ck_cpt[6].u_bufio_cpt in unit phy_rdclk_gen of type BUFIO has been replaced by BUFIODQS +INFO:Xst:1901 - Instance gen_ck_cpt[7].u_bufio_cpt in unit phy_rdclk_gen of type BUFIO has been replaced by BUFIODQS +WARNING:Xst:1989 - Unit : instances , of unit are equivalent, second instance is removed +WARNING:Xst:1989 - Unit : instances , of unit are equivalent, second instance is removed +WARNING:Xst:1989 - Unit : instances , of unit are equivalent, second instance is removed +WARNING:Xst:1989 - Unit : instances , of unit are equivalent, second instance is removed +WARNING:Xst:1989 - Unit : instances , of unit are equivalent, second instance is removed +WARNING:Xst:1989 - Unit : instances , of unit are equivalent, second instance is removed + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... +WARNING:Xst:638 - in unit mkLCDController Conflict on KEEP property on signal line1_fsm_state_mkFSMstate_FSM_FFd1 and line2_fsm_state_mkFSMstate_FSM_FFd1 line2_fsm_state_mkFSMstate_FSM_FFd1 signal will be lost. +WARNING:Xst:638 - in unit mkLCDController Conflict on KEEP property on signal line1_fsm_state_mkFSMstate_FSM_FFd1 and line2_fsm_state_mkFSMstate_FSM_FFd1 line2_fsm_state_mkFSMstate_FSM_FFd1 signal will be lost. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +INFO:Xst:2399 - RAMs , are equivalent, second RAM is removed +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. + +Mapping all equations... +Building and optimizing final netlist ... +Found area constraint ratio of 100 (+ 5) on block fpgaTop, actual ratio is 2. +FlipFlop ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/rst_final has been replicated 2 time(s) +FlipFlop ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/rst_final has been replicated 2 time(s) +FlipFlop ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_cmd0/app_rdy_r has been replicated 1 time(s) + +Final Macro Processing ... + +Processing Unit : + Found 10-bit shift register for signal . +Unit processed. + +Processing Unit : +INFO:Xst:741 - HDL ADVISOR - A 16-bit shift register was found for signal and currently occupies 16 logic cells (8 slices). Removing the set/reset logic would take advantage of SRL32 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally. +Unit processed. + +Processing Unit : + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . +Unit processed. + +Processing Unit : +INFO:Xst:741 - HDL ADVISOR - A 17-bit shift register was found for signal and currently occupies 17 logic cells (8 slices). Removing the set/reset logic would take advantage of SRL32 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally. +INFO:Xst:741 - HDL ADVISOR - A 17-bit shift register was found for signal and currently occupies 17 logic cells (8 slices). Removing the set/reset logic would take advantage of SRL32 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally. +INFO:Xst:741 - HDL ADVISOR - A 17-bit shift register was found for signal and currently occupies 17 logic cells (8 slices). Removing the set/reset logic would take advantage of SRL32 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally. +INFO:Xst:741 - HDL ADVISOR - A 17-bit shift register was found for signal and currently occupies 17 logic cells (8 slices). Removing the set/reset logic would take advantage of SRL32 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally. +INFO:Xst:741 - HDL ADVISOR - A 17-bit shift register was found for signal and currently occupies 17 logic cells (8 slices). Removing the set/reset logic would take advantage of SRL32 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally. +INFO:Xst:741 - HDL ADVISOR - A 17-bit shift register was found for signal and currently occupies 17 logic cells (8 slices). Removing the set/reset logic would take advantage of SRL32 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally. +INFO:Xst:741 - HDL ADVISOR - A 17-bit shift register was found for signal and currently occupies 17 logic cells (8 slices). Removing the set/reset logic would take advantage of SRL32 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally. +INFO:Xst:741 - HDL ADVISOR - A 17-bit shift register was found for signal and currently occupies 17 logic cells (8 slices). Removing the set/reset logic would take advantage of SRL32 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally. +INFO:Xst:741 - HDL ADVISOR - A 17-bit shift register was found for signal and currently occupies 17 logic cells (8 slices). Removing the set/reset logic would take advantage of SRL32 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally. +INFO:Xst:741 - HDL ADVISOR - A 17-bit shift register was found for signal and currently occupies 17 logic cells (8 slices). Removing the set/reset logic would take advantage of SRL32 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally. +INFO:Xst:741 - HDL ADVISOR - A 17-bit shift register was found for signal and currently occupies 17 logic cells (8 slices). Removing the set/reset logic would take advantage of SRL32 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally. +Unit processed. + +Processing Unit : +INFO:Xst:741 - HDL ADVISOR - A 8-bit shift register was found for signal and currently occupies 8 logic cells (4 slices). Removing the set/reset logic would take advantage of SRL32 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally. +Unit processed. + +Processing Unit : +INFO:Xst:741 - HDL ADVISOR - A 15-bit shift register was found for signal and currently occupies 15 logic cells (7 slices). Removing the set/reset logic would take advantage of SRL32 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally. +Unit processed. + +Processing Unit : + Found 3-bit shift register for signal . +Unit processed. + +Processing Unit : + Found 16-bit shift register for signal . + Found 16-bit shift register for signal . + Found 16-bit shift register for signal . + Found 16-bit shift register for signal . + Found 3-bit shift register for signal . + Found 16-bit shift register for signal . +Unit processed. + +Processing Unit : +INFO:Xst:741 - HDL ADVISOR - A 5-bit shift register was found for signal and currently occupies 5 logic cells (2 slices). Removing the set/reset logic would take advantage of SRL32 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally. +Unit processed. + +Processing Unit : + Found 4-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . +Unit processed. + +Processing Unit : +INFO:Xst:741 - HDL ADVISOR - A 8-bit shift register was found for signal and currently occupies 8 logic cells (4 slices). Removing the set/reset logic would take advantage of SRL32 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally. +Unit processed. + +Processing Unit : + Found 10-bit shift register for signal . +Unit processed. + +========================================================================= +Final Register Report + +Macro Statistics +# Registers : 32751 + Flip-Flops : 32751 +# Shift Registers : 44 + 10-bit shift register : 2 + 16-bit shift register : 5 + 2-bit shift register : 34 + 3-bit shift register : 2 + 4-bit shift register : 1 + +========================================================================= + +========================================================================= +* Partition Report * +========================================================================= + +Partition Implementation Status +------------------------------- + + No Partitions were found in this design. + +------------------------------- + +========================================================================= +* Design Summary * +========================================================================= + +Top Level Output File Name : fpgaTop.ngc + +Primitive and Black Box Usage: +------------------------------ +# BELS : 45668 +# BUF : 94 +# GND : 215 +# INV : 1239 +# LUT1 : 2344 +# LUT2 : 3301 +# LUT3 : 4472 +# LUT4 : 4037 +# LUT5 : 6882 +# LUT6 : 13352 +# MULT_AND : 90 +# MUXCY : 4470 +# MUXF7 : 710 +# MUXF8 : 100 +# VCC : 186 +# XORCY : 4176 +# FlipFlops/Latches : 32811 +# FD : 7159 +# FD_1 : 432 +# FDC : 425 +# FDCE : 619 +# FDE : 10790 +# FDP : 67 +# FDPE : 58 +# FDR : 2098 +# FDRE : 9009 +# FDS : 109 +# FDSE : 2033 +# ODDR : 12 +# RAMS : 826 +# RAM32M : 431 +# RAM32X1D : 66 +# RAM64X1D : 288 +# RAMB18E1 : 3 +# RAMB36E1 : 38 +# Shift Registers : 2977 +# SRL16E : 5 +# SRLC16E : 2970 +# SRLC32E : 2 +# Clock Buffers : 12 +# BUFG : 11 +# BUFGCTRL : 1 +# IO Buffers : 229 +# IBUF : 28 +# IBUFDS : 2 +# IBUFDS_GTXE1 : 2 +# IOBUF : 81 +# IOBUFDS_DIFF_OUT : 8 +# OBUF : 107 +# OBUFDS : 1 +# GigabitIOs : 4 +# GTXE1 : 4 +# Others : 302 +# BUFIODQS : 9 +# BUFR : 3 +# DNA_PORT : 1 +# IDELAYCTRL : 1 +# IODELAYE1 : 91 +# ISERDESE1 : 72 +# MMCM_ADV : 2 +# OSERDESE1 : 122 +# PCIE_2_0 : 1 + +Device utilization summary: +--------------------------- + +Selected Device : 6vlx240tff1156-1 + + +Slice Logic Utilization: + Number of Slice Registers: 32811 out of 301440 10% + Number of Slice LUTs: 41036 out of 150720 27% + Number used as Logic: 35627 out of 150720 23% + Number used as Memory: 5409 out of 58400 9% + Number used as RAM: 2432 + Number used as SRL: 2977 + +Slice Logic Distribution: + Number of LUT Flip Flop pairs used: 55005 + Number with an unused Flip Flop: 22194 out of 55005 40% + Number with an unused LUT: 13969 out of 55005 25% + Number of fully used LUT-FF pairs: 18842 out of 55005 34% + Number of unique control sets: 2121 + +IO Utilization: + Number of IOs: 238 + Number of bonded IOBs: 234 out of 600 39% + +Specific Feature Utilization: + Number of Block RAM/FIFO: 40 out of 416 9% + Number using Block RAM only: 40 + Number of BUFG/BUFGCTRLs: 12 out of 32 37% + +--------------------------- +Partition Resource Summary: +--------------------------- + + No Partitions were found in this design. + +--------------------------- + + +========================================================================= +Timing Report + +NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE. + FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT + GENERATED AFTER PLACE-and-ROUTE. + +Clock Information: +------------------ +--------------------------------------------------------------------------------------------------+--------------------------------------------------------+-------+ +Clock Signal | Clock buffer(FF name) | Load | +--------------------------------------------------------------------------------------------------+--------------------------------------------------------+-------+ +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/TxOutClk | MMCM_ADV:CLKOUT0 | 550 | +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/TxOutClk | MMCM_ADV:CLKOUT1 | 27182 | +ftop/pciw_pci0_pcie_ep/ep/pcie_clocking_i/clk_125 | BUFGCTRL | 418 | +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PCIEDRPDWE | NONE(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i)| 1 | +sys1_clkp | IBUF+IBUFDS_GTXE1+BUFG | 119 | +ftop/gbe0/gmac/gmii_rxc_dly$DATAOUT | BUFR | 134 | +sys0_clkp | MMCM_ADV:CLKOUT1 | 5619 | +flp_cdc_clk_p | IBUFDS+BUFG | 20 | +ftop/fmc150/spiCDC_cd/cntr_2 | BUFG | 76 | +ftop/fmc150/spiDAC_cd/cntr_3 | BUFG | 31 | +ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/rsync_odelay<0>| BUFR | 928 | +ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/rsync_odelay<1>| BUFR | 1542 | +--------------------------------------------------------------------------------------------------+--------------------------------------------------------+-------+ +INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems. + +Asynchronous Control Signals Information: +---------------------------------------- +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------+-------+ +Control Signal | Buffer(FF name) | Load | +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------+-------+ +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[0].ram/use_ramb36.ramb36/N11(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[0].ram/use_ramb36.ramb36/XST_VCC:P)| NONE(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[0].ram/use_ramb36.ramb36/use_ramb36.ramb36)| 62 | +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[1].ram/use_ramb36.ramb36/N11(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[1].ram/use_ramb36.ramb36/XST_VCC:P)| NONE(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[1].ram/use_ramb36.ramb36/use_ramb36.ramb36)| 62 | +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[2].ram/use_ramb36.ramb36/N11(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[2].ram/use_ramb36.ramb36/XST_VCC:P)| NONE(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[2].ram/use_ramb36.ramb36/use_ramb36.ramb36)| 62 | +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[3].ram/use_ramb36.ramb36/N11(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[3].ram/use_ramb36.ramb36/XST_VCC:P)| NONE(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[3].ram/use_ramb36.ramb36/use_ramb36.ramb36)| 62 | +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[0].ram/use_ramb36.ramb36/N11(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[0].ram/use_ramb36.ramb36/XST_VCC:P)| NONE(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[0].ram/use_ramb36.ramb36/use_ramb36.ramb36)| 62 | +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[1].ram/use_ramb36.ramb36/N11(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[1].ram/use_ramb36.ramb36/XST_VCC:P)| NONE(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[1].ram/use_ramb36.ramb36/use_ramb36.ramb36)| 62 | +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[2].ram/use_ramb36.ramb36/N11(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[2].ram/use_ramb36.ramb36/XST_VCC:P)| NONE(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[2].ram/use_ramb36.ramb36/use_ramb36.ramb36)| 62 | +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[3].ram/use_ramb36.ramb36/N11(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[3].ram/use_ramb36.ramb36/XST_VCC:P)| NONE(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[3].ram/use_ramb36.ramb36/use_ramb36.ramb36)| 62 | +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[0].ram/use_ramb36.ramb36/N01(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[0].ram/use_ramb36.ramb36/XST_GND:G)| NONE(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[0].ram/use_ramb36.ramb36/use_ramb36.ramb36)| 36 | +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[1].ram/use_ramb36.ramb36/N01(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[1].ram/use_ramb36.ramb36/XST_GND:G)| NONE(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[1].ram/use_ramb36.ramb36/use_ramb36.ramb36)| 36 | +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[2].ram/use_ramb36.ramb36/N01(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[2].ram/use_ramb36.ramb36/XST_GND:G)| NONE(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[2].ram/use_ramb36.ramb36/use_ramb36.ramb36)| 36 | +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[3].ram/use_ramb36.ramb36/N01(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[3].ram/use_ramb36.ramb36/XST_GND:G)| NONE(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[3].ram/use_ramb36.ramb36/use_ramb36.ramb36)| 36 | +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[0].ram/use_ramb36.ramb36/N01(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[0].ram/use_ramb36.ramb36/XST_GND:G)| NONE(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[0].ram/use_ramb36.ramb36/use_ramb36.ramb36)| 36 | +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[1].ram/use_ramb36.ramb36/N01(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[1].ram/use_ramb36.ramb36/XST_GND:G)| NONE(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[1].ram/use_ramb36.ramb36/use_ramb36.ramb36)| 36 | +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[2].ram/use_ramb36.ramb36/N01(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[2].ram/use_ramb36.ramb36/XST_GND:G)| NONE(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[2].ram/use_ramb36.ramb36/use_ramb36.ramb36)| 36 | +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[3].ram/use_ramb36.ramb36/N01(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[3].ram/use_ramb36.ramb36/XST_GND:G)| NONE(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[3].ram/use_ramb36.ramb36/use_ramb36.ramb36)| 36 | +ftop/ctop/app/appW2/wmiM0_MDataValid(ftop/ctop/app/appW2/XST_GND:G) | NONE(ftop/ctop/app/appW2/respF_memory/Mram_RAM10) | 4 | +ftop/ctop/app/appW4/wmiM0_MAddrSpace(ftop/ctop/app/appW4/XST_GND:G) | NONE(ftop/ctop/app/appW4/respF_memory/Mram_RAM10) | 4 | +ftop/pciw_pci0_pcie_ep/ep/phy_rdy_n_INV_4580_o(ftop/pciw_pci0_pcie_ep/ep/phy_rdy_n_INV_4580_o1_INV_0:O) | NONE(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i) | 3 | +ftop/ctop/app/appW2/respF_pwEnqueue$whas(ftop/ctop/app/appW2/respF_pwEnqueue$whas1:O) | NONE(ftop/ctop/app/appW2/respF_memory/Mram_RAM10) | 2 | +ftop/ctop/app/appW4/respF_pwEnqueue$whas(ftop/ctop/app/appW4/respF_pwEnqueue$whas1:O) | NONE(ftop/ctop/app/appW4/respF_memory/Mram_RAM10) | 2 | +ftop/ctop/inf/cp/rom_memory/DO<16>(ftop/ctop/inf/cp/rom_memory/XST_GND:G) | NONE(ftop/ctop/inf/cp/rom_memory/Mram_RAM1) | 2 | +ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/N0(ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/XST_VCC:P) | NONE(ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_loop_col0.u_bufr_rsync) | 2 | +ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/rst_rsync_0(ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/rst_rsync_0:Q) | NONE(ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_loop_col0.u_bufr_rsync) | 2 | +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[0].ram/N1(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[0].ram/XST_GND:G) | NONE(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[0].ram/use_ramb36.ramb36/use_ramb36.ramb36)| 2 | +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[1].ram/N1(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[1].ram/XST_GND:G) | NONE(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[1].ram/use_ramb36.ramb36/use_ramb36.ramb36)| 2 | +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[2].ram/N1(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[2].ram/XST_GND:G) | NONE(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[2].ram/use_ramb36.ramb36/use_ramb36.ramb36)| 2 | +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[3].ram/N1(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[3].ram/XST_GND:G) | NONE(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[3].ram/use_ramb36.ramb36/use_ramb36.ramb36)| 2 | +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[0].ram/N1(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[0].ram/XST_GND:G) | NONE(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[0].ram/use_ramb36.ramb36/use_ramb36.ramb36)| 2 | +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[1].ram/N1(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[1].ram/XST_GND:G) | NONE(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[1].ram/use_ramb36.ramb36/use_ramb36.ramb36)| 2 | +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[2].ram/N1(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[2].ram/XST_GND:G) | NONE(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[2].ram/use_ramb36.ramb36/use_ramb36.ramb36)| 2 | +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[3].ram/N1(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[3].ram/XST_GND:G) | NONE(ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[3].ram/use_ramb36.ramb36/use_ramb36.ramb36)| 2 | +ftop/gbe0/gmac/CLK_GATE_rxclkBnd(ftop/gbe0/gmac/XST_VCC:P) | NONE(ftop/gbe0/gmac/rxClk_BUFR) | 1 | +ftop/gbe0/gmac/txRS_txER(ftop/gbe0/gmac/XST_GND:G) | NONE(ftop/gbe0/gmac/rxClk_BUFR) | 1 | +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------+-------+ + +Timing Summary: +--------------- +Speed Grade: -1 + + Minimum period: 4.758ns (Maximum Frequency: 210.172MHz) + Minimum input arrival time before clock: 1.793ns + Maximum output required time after clock: 1.923ns + Maximum combinational path delay: 0.538ns + +Timing Details: +--------------- +All values displayed in nanoseconds (ns) + +========================================================================= +Timing constraint: Default period analysis for Clock 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/TxOutClk' + Clock period: 4.074ns (frequency: 245.441MHz) + Total number of paths / destination ports: 10223690 / 77360 +------------------------------------------------------------------------- +Delay: 8.149ns (Levels of Logic = 12) + Source: ftop/ctop/inf/cp/cpReq_26 (FF) + Destination: ftop/ctop/inf/cp/cpReq_0 (FF) + Source Clock: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/TxOutClk rising 0.5X + Destination Clock: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/TxOutClk rising 0.5X + + Data Path: ftop/ctop/inf/cp/cpReq_26 to ftop/ctop/inf/cp/cpReq_0 + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + FDRE:C->Q 29 0.375 0.733 cpReq_26 (cpReq_26) + LUT3:I0->O 65 0.068 0.577 Msub_wn___1__h76499_xor<2>11 (wn___1__h76499<2>) + LUT6:I5->O 64 0.068 0.559 Mmux__theResult_____1__h7572431 (_theResult_____1__h75724<2>) + MUXF7:S->O 1 0.267 0.000 Mmux_CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d2986_4_f7 (Mmux_CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d2986_4_f7) + MUXF8:I0->O 6 0.175 0.450 Mmux_CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d2986_2_f8 (CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d2986) + LUT6:I5->O 29 0.068 0.569 WILL_FIRE_RL_cpDispatch_F_F_T_E0_F_T11 (WILL_FIRE_RL_cpDispatch_F_F_T_E0_F_T1) + LUT5:I4->O 5 0.068 0.665 WILL_FIRE_RL_cpDispatch_F_F_T_E4_F_T1 (WILL_FIRE_RL_cpDispatch_F_F_T_E4_F_T) + LUT6:I2->O 1 0.068 0.417 WILL_FIRE_RL_completeWorkerWrite28 (WILL_FIRE_RL_completeWorkerWrite28) + LUT4:I3->O 1 0.068 0.417 WILL_FIRE_RL_completeWorkerWrite29_SW0 (N590) + LUT6:I5->O 1 0.068 0.417 WILL_FIRE_RL_completeWorkerWrite29 (WILL_FIRE_RL_completeWorkerWrite29) + LUT6:I5->O 1 0.068 0.417 WILL_FIRE_RL_completeWorkerWrite31 (WILL_FIRE_RL_completeWorkerWrite31) + LUT6:I5->O 19 0.068 0.610 WILL_FIRE_RL_completeWorkerWrite32 (WILL_FIRE_RL_completeWorkerWrite) + LUT5:I3->O 64 0.068 0.559 cpReq$EN (cpReq$EN) + FDRE:CE 0.263 cpReq_0 + ---------------------------------------- + Total 8.149ns (1.760ns logic, 6.389ns route) + (21.6% logic, 78.4% route) + +========================================================================= +Timing constraint: Default period analysis for Clock 'ftop/pciw_pci0_pcie_ep/ep/pcie_clocking_i/clk_125' + Clock period: 3.724ns (frequency: 268.528MHz) + Total number of paths / destination ports: 4781 / 823 +------------------------------------------------------------------------- +Delay: 3.724ns (Levels of Logic = 5) + Source: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX_TX_SYNC/state_FSM_FFd5 (FF) + Destination: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX_TX_SYNC/waitcounter_4 (FF) + Source Clock: ftop/pciw_pci0_pcie_ep/ep/pcie_clocking_i/clk_125 rising + Destination Clock: ftop/pciw_pci0_pcie_ep/ep/pcie_clocking_i/clk_125 rising + + Data Path: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX_TX_SYNC/state_FSM_FFd5 to ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX_TX_SYNC/waitcounter_4 + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + FDR:C->Q 4 0.375 0.798 state_FSM_FFd5 (state_FSM_FFd5) + LUT6:I0->O 1 0.068 0.491 nextwaitcounter2<7>112 (nextwaitcounter2<7>112) + LUT6:I4->O 2 0.068 0.423 nextwaitcounter2<7>113 (nextwaitcounter2<7>11) + LUT4:I3->O 2 0.068 0.423 nextwaitcounter2<1>31 (nextwaitcounter2<1>3) + LUT6:I5->O 14 0.068 0.863 nextwaitcounter2<0>11 (nextwaitcounter2<0>1) + LUT6:I0->O 1 0.068 0.000 nextwaitcounter<4>1 (nextwaitcounter<4>) + FDR:D 0.011 waitcounter_4 + ---------------------------------------- + Total 3.724ns (0.726ns logic, 2.998ns route) + (19.5% logic, 80.5% route) + +========================================================================= +Timing constraint: Default period analysis for Clock 'sys1_clkp' + Clock period: 3.851ns (frequency: 259.673MHz) + Total number of paths / destination ports: 7036 / 281 +------------------------------------------------------------------------- +Delay: 3.851ns (Levels of Logic = 6) + Source: ftop/gbe0/gmac/txRS_txF/dNotEmptyReg (FF) + Destination: ftop/gbe0/gmac/txRS_crc/rRemainder_5 (FF) + Source Clock: sys1_clkp rising + Destination Clock: sys1_clkp rising + + Data Path: ftop/gbe0/gmac/txRS_txF/dNotEmptyReg to ftop/gbe0/gmac/txRS_crc/rRemainder_5 + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + FDCE:C->Q 6 0.375 0.808 dNotEmptyReg (dNotEmptyReg) + end scope: 'ftop/gbe0/gmac/txRS_txF:dEMPTY_N' + LUT6:I1->O 21 0.068 0.547 WILL_FIRE_RL_txRS_egress_Body11 (WILL_FIRE_RL_txRS_egress_Body1) + LUT6:I5->O 11 0.068 0.483 MUX_txRS_crc$add_1__SEL_11 (MUX_txRS_crc$add_1__SEL_1) + LUT6:I5->O 15 0.068 0.870 Mmux_txRS_crc$add_data12 (txRS_crc$add_data<0>) + begin scope: 'ftop/gbe0/gmac/txRS_crc:add_data<0>' + LUT6:I0->O 1 0.068 0.417 rRemainder$D_IN<5>1 (rRemainder$D_IN<5>1) + LUT5:I4->O 1 0.068 0.000 rRemainder$D_IN<5>3 (rRemainder$D_IN<5>) + FDSE:D 0.011 rRemainder_5 + ---------------------------------------- + Total 3.851ns (0.726ns logic, 3.125ns route) + (18.9% logic, 81.1% route) + +========================================================================= +Timing constraint: Default period analysis for Clock 'ftop/gbe0/gmac/gmii_rxc_dly$DATAOUT' + Clock period: 3.539ns (frequency: 282.553MHz) + Total number of paths / destination ports: 2257 / 314 +------------------------------------------------------------------------- +Delay: 3.539ns (Levels of Logic = 4) + Source: ftop/gbe0/gmac/rxRS_rxAPipe_3 (FF) + Destination: ftop/gbe0/gmac/rxRS_preambleCnt_value_0 (FF) + Source Clock: ftop/gbe0/gmac/gmii_rxc_dly$DATAOUT rising + Destination Clock: ftop/gbe0/gmac/gmii_rxc_dly$DATAOUT rising + + Data Path: ftop/gbe0/gmac/rxRS_rxAPipe_3 to ftop/gbe0/gmac/rxRS_preambleCnt_value_0 + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + FDRE:C->Q 3 0.375 0.792 rxRS_rxAPipe_3 (rxRS_rxAPipe_3) + LUT6:I0->O 2 0.068 0.423 WILL_FIRE_RL_rxRS_ingress_noadvance_SW0 (N10) + LUT6:I5->O 44 0.068 0.572 WILL_FIRE_RL_rxRS_ingress_noadvance (WILL_FIRE_RL_rxRS_ingress_noadvance) + LUT4:I3->O 2 0.068 0.423 WILL_FIRE_RL_rxRS_end_frame1 (WILL_FIRE_RL_rxRS_end_frame) + LUT5:I4->O 4 0.068 0.419 _n0446_inv1 (_n0446_inv) + FDRE:CE 0.263 rxRS_preambleCnt_value_0 + ---------------------------------------- + Total 3.539ns (0.910ns logic, 2.629ns route) + (25.7% logic, 74.3% route) + +========================================================================= +Timing constraint: Default period analysis for Clock 'sys0_clkp' + Clock period: 4.758ns (frequency: 210.172MHz) + Total number of paths / destination ports: 148877 / 11129 +------------------------------------------------------------------------- +Delay: 4.758ns (Levels of Logic = 13) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/arb_mux0/arb_select0/io_config_r_1 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/arb_mux0/arb_row_col0/io_config_valid_r_lcl (FF) + Source Clock: sys0_clkp rising + Destination Clock: sys0_clkp rising + + Data Path: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/arb_mux0/arb_select0/io_config_r_1 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/arb_mux0/arb_row_col0/io_config_valid_r_lcl + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + FD:C->Q 2 0.375 0.784 io_config_r_1 (io_config_r_1) + LUT6:I0->O 1 0.068 0.417 Mmux_io_config_ns41 (Mmux_io_config_ns4) + LUT6:I5->O 1 0.068 0.417 Mmux_io_config_ns42 (Mmux_io_config_ns41) + LUT5:I4->O 20 0.068 0.542 Mmux_io_config_ns43 (dfi_odt_nom1<0>) + end scope: 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/arb_mux0/arb_select0:io_config<1>' + end scope: 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/arb_mux0:io_config<1>' + end scope: 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0:io_config<1>' + begin scope: 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0:io_config<1>' + LUT4:I3->O 4 0.068 0.511 inhbt_wr_config11 (inhbt_wr_config) + end scope: 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0:inhbt_wr_config' + begin scope: 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0:inhbt_wr_config' + begin scope: 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[2].bank0:inhbt_wr_config' + begin scope: 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[2].bank0/bank_state0:inhbt_wr_config' + LUT6:I4->O 6 0.068 0.808 rtc (rtc) + end scope: 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[2].bank0/bank_state0:rtc' + end scope: 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[2].bank0:rtc' + begin scope: 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/arb_mux0:rtc<2>' + begin scope: 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/arb_mux0/arb_row_col0:rtc<2>' + LUT6:I1->O 1 0.068 0.417 io_config_valid_ns_norst2 (io_config_valid_ns_norst2) + LUT2:I1->O 1 0.068 0.000 io_config_valid_ns_norst3 (io_config_valid_ns_norst) + FDR:D 0.011 io_config_valid_r_lcl + ---------------------------------------- + Total 4.758ns (0.862ns logic, 3.896ns route) + (18.1% logic, 81.9% route) + +========================================================================= +Timing constraint: Default period analysis for Clock 'flp_cdc_clk_p' + Clock period: 4.676ns (frequency: 213.858MHz) + Total number of paths / destination ports: 12407 / 37 +------------------------------------------------------------------------- +Delay: 4.676ns (Levels of Logic = 7) + Source: ftop/fmc150/fcCdc_grayCounter_rsCounter_16 (FF) + Destination: ftop/fmc150/fcCdc_grayCounter_rsCounter_0 (FF) + Source Clock: flp_cdc_clk_p rising + Destination Clock: flp_cdc_clk_p rising + + Data Path: ftop/fmc150/fcCdc_grayCounter_rsCounter_16 to ftop/fmc150/fcCdc_grayCounter_rsCounter_0 + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + FDC:C->Q 5 0.375 0.802 fcCdc_grayCounter_rsCounter_16 (fcCdc_grayCounter_rsCounter_16) + LUT6:I1->O 3 0.068 0.595 Mxor_fcCdc_grayCounter_rsCounter_13_BIT_0_20_XOR_fc_ETC___d454_xo<0>2 (Mxor_fcCdc_grayCounter_rsCounter_13_BIT_0_20_XOR_fc_ETC___d454_xo<0>1) + LUT3:I0->O 14 0.068 0.502 Mxor_fcCdc_grayCounter_rsCounter_13_BIT_0_20_XOR_fc_ETC___d454_xo<0>4 (fcCdc_grayCounter_rsCounter_13_BIT_0_20_XOR_fc_ETC___d454) + LUT6:I5->O 13 0.068 0.571 Mmux_IF_fcCdc_grayCounter_rsCounter_13_BIT_0_20_XOR_ETC___d49014 (IF_fcCdc_grayCounter_rsCounter_13_BIT_0_20_XOR_ETC___d490<0>) + LUT6:I4->O 1 0.068 0.638 Mmux_IF_fcCdc_grayCounter_rsCounter_13_BIT_0_20_XOR_ETC___d490[4]_X_177_o_Mux_53_o_91 (Mmux_IF_fcCdc_grayCounter_rsCounter_13_BIT_0_20_XOR_ETC___d490[4]_X_177_o_Mux_53_o_91) + LUT6:I2->O 1 0.068 0.000 Mmux_IF_fcCdc_grayCounter_rsCounter_13_BIT_0_20_XOR_ETC___d490[4]_X_177_o_Mux_53_o_4 (Mmux_IF_fcCdc_grayCounter_rsCounter_13_BIT_0_20_XOR_ETC___d490[4]_X_177_o_Mux_53_o_4) + MUXF7:I0->O 18 0.245 0.529 Mmux_IF_fcCdc_grayCounter_rsCounter_13_BIT_0_20_XOR_ETC___d490[4]_X_177_o_Mux_53_o_2_f7 (IF_fcCdc_grayCounter_rsCounter_13_BIT_0_20_XOR_ETC___d490[4]_X_177_o_Mux_53_o) + LUT6:I5->O 1 0.068 0.000 Mmux_MUX_fcCdc_grayCounter_rsCounter$write_1__VAL_181 (MUX_fcCdc_grayCounter_rsCounter$write_1__VAL_1<16>) + FDC:D 0.011 fcCdc_grayCounter_rsCounter_16 + ---------------------------------------- + Total 4.676ns (1.039ns logic, 3.637ns route) + (22.2% logic, 77.8% route) + +========================================================================= +Timing constraint: Default period analysis for Clock 'ftop/fmc150/spiCDC_cd/cntr_2' + Clock period: 3.708ns (frequency: 269.687MHz) + Total number of paths / destination ports: 745 / 184 +------------------------------------------------------------------------- +Delay: 3.708ns (Levels of Logic = 7) + Source: ftop/fmc150/spiCDC_slowReset/reset_hold_1 (FF) + Destination: ftop/fmc150/spiCDC_reqF_head_wrapped (FF) + Source Clock: ftop/fmc150/spiCDC_cd/cntr_2 rising + Destination Clock: ftop/fmc150/spiCDC_cd/cntr_2 rising + + Data Path: ftop/fmc150/spiCDC_slowReset/reset_hold_1 to ftop/fmc150/spiCDC_reqF_head_wrapped + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + FDC:C->Q 9 0.375 0.470 reset_hold_1 (reset_hold_1) + end scope: 'ftop/fmc150/spiCDC_slowReset:OUT_RST' + begin scope: 'ftop/fmc150/spiCDC_reqF_dCombinedReset:A_RST' + LUT2:I1->O 2 0.068 0.405 RST_OUT1 (RST_OUT) + end scope: 'ftop/fmc150/spiCDC_reqF_dCombinedReset:RST_OUT' + begin scope: 'ftop/fmc150/spiCDC_reqF_dInReset:RST' + INV:I->O 8 0.086 0.824 VAL1_INV_0 (VAL) + end scope: 'ftop/fmc150/spiCDC_reqF_dInReset:VAL' + LUT6:I0->O 4 0.068 0.511 MUX_spiCDC_rcv_d$write_1__SEL_21 (MUX_spiCDC_rcv_d$write_1__SEL_2) + LUT4:I2->O 1 0.068 0.399 Reset_OR_DriverANDClockEnable91 (Reset_OR_DriverANDClockEnable9) + FDRE:R 0.434 spiCDC_reqF_head_wrapped + ---------------------------------------- + Total 3.708ns (1.099ns logic, 2.609ns route) + (29.6% logic, 70.4% route) + +========================================================================= +Timing constraint: Default period analysis for Clock 'ftop/fmc150/spiDAC_cd/cntr_3' + Clock period: 3.785ns (frequency: 264.201MHz) + Total number of paths / destination ports: 333 / 69 +------------------------------------------------------------------------- +Delay: 3.785ns (Levels of Logic = 8) + Source: ftop/fmc150/spiDAC_slowReset/reset_hold_1 (FF) + Destination: ftop/fmc150/spiDAC_reqF_head_wrapped (FF) + Source Clock: ftop/fmc150/spiDAC_cd/cntr_3 rising + Destination Clock: ftop/fmc150/spiDAC_cd/cntr_3 rising + + Data Path: ftop/fmc150/spiDAC_slowReset/reset_hold_1 to ftop/fmc150/spiDAC_reqF_head_wrapped + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + FDC:C->Q 6 0.375 0.450 reset_hold_1 (reset_hold_1) + end scope: 'ftop/fmc150/spiDAC_slowReset:OUT_RST' + begin scope: 'ftop/fmc150/spiDAC_reqF_dCombinedReset:A_RST' + LUT2:I1->O 2 0.068 0.405 RST_OUT1 (RST_OUT) + end scope: 'ftop/fmc150/spiDAC_reqF_dCombinedReset:RST_OUT' + begin scope: 'ftop/fmc150/spiDAC_reqF_dInReset:RST' + INV:I->O 5 0.086 0.444 VAL1_INV_0 (VAL) + end scope: 'ftop/fmc150/spiDAC_reqF_dInReset:VAL' + LUT6:I5->O 13 0.068 0.497 WILL_FIRE_RL_spiDAC_doxcv_d1 (WILL_FIRE_RL_spiDAC_doxcv_d) + LUT5:I4->O 2 0.068 0.423 spiDAC_reqF_head_wrapped$EN1 (spiDAC_reqF_head_wrapped$EN) + LUT3:I2->O 1 0.068 0.399 Reset_OR_DriverANDClockEnable101 (Reset_OR_DriverANDClockEnable10) + FDRE:R 0.434 spiDAC_reqF_head_wrapped + ---------------------------------------- + Total 3.785ns (1.167ns logic, 2.618ns route) + (30.8% logic, 69.2% route) + +========================================================================= +Timing constraint: Default period analysis for Clock 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/rsync_odelay<0>' + Clock period: 2.088ns (frequency: 478.927MHz) + Total number of paths / destination ports: 2069 / 1093 +------------------------------------------------------------------------- +Delay: 2.088ns (Levels of Logic = 4) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2].u_phy_dqs_iob/iserdes_q_r_2 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2].u_phy_dqs_iob/u_rd_bitslip_early/qout_1 (FF) + Source Clock: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/rsync_odelay<0> rising + Destination Clock: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/rsync_odelay<0> rising + + Data Path: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2].u_phy_dqs_iob/iserdes_q_r_2 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2].u_phy_dqs_iob/u_rd_bitslip_early/qout_1 + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + FD:C->Q 1 0.375 0.417 iserdes_q_r_2 (iserdes_q_r_2) + LUT3:I2->O 4 0.068 0.658 Mmux_iserdes_q_mux31 (iserdes_q_mux<2>) + begin scope: 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2].u_phy_dqs_iob/u_rd_bitslip_early:din<2>' + LUT6:I2->O 2 0.068 0.423 Mmux_slip_out21 (slip_out<1>) + LUT6:I5->O 1 0.068 0.000 mux113 (clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<1>) + FD:D 0.011 qout_1 + ---------------------------------------- + Total 2.088ns (0.590ns logic, 1.498ns route) + (28.3% logic, 71.7% route) + +========================================================================= +Timing constraint: Default period analysis for Clock 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/rsync_odelay<1>' + Clock period: 2.088ns (frequency: 478.927MHz) + Total number of paths / destination ports: 3439 / 1815 +------------------------------------------------------------------------- +Delay: 2.088ns (Levels of Logic = 4) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7].u_phy_dqs_iob/iserdes_q_r_2 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7].u_phy_dqs_iob/u_rd_bitslip_early/qout_1 (FF) + Source Clock: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/rsync_odelay<1> rising + Destination Clock: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/rsync_odelay<1> rising + + Data Path: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7].u_phy_dqs_iob/iserdes_q_r_2 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7].u_phy_dqs_iob/u_rd_bitslip_early/qout_1 + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + FD:C->Q 1 0.375 0.417 iserdes_q_r_2 (iserdes_q_r_2) + LUT3:I2->O 4 0.068 0.658 Mmux_iserdes_q_mux31 (iserdes_q_mux<2>) + begin scope: 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7].u_phy_dqs_iob/u_rd_bitslip_early:din<2>' + LUT6:I2->O 2 0.068 0.423 Mmux_slip_out21 (slip_out<1>) + LUT6:I5->O 1 0.068 0.000 mux113 (clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<1>) + FD:D 0.011 qout_1 + ---------------------------------------- + Total 2.088ns (0.590ns logic, 1.498ns route) + (28.3% logic, 71.7% route) + +========================================================================= +Timing constraint: Default OFFSET IN BEFORE for Clock 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/TxOutClk' + Total number of paths / destination ports: 24 / 24 +------------------------------------------------------------------------- +Offset: 1.457ns (Levels of Logic = 4) + Source: pci0_reset_n (PAD) + Destination: ftop/pciw_pci0_pcie_ep/ep/pcie_reset_delay_i/reg_count_23_16_0 (FF) + Destination Clock: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/TxOutClk rising + + Data Path: pci0_reset_n to ftop/pciw_pci0_pcie_ep/ep/pcie_reset_delay_i/reg_count_23_16_0 + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + IBUF:I->O 1 0.003 0.399 pci0_reset_n_IBUF (pci0_reset_n_IBUF) + begin scope: 'ftop:pci0_rstn' + begin scope: 'ftop/pciw_pci0_pcie_ep:sys_reset_n' + begin scope: 'ftop/pciw_pci0_pcie_ep/ep:sys_reset_n' + begin scope: 'ftop/pciw_pci0_pcie_ep/ep/pcie_reset_delay_i:sys_reset_n' + INV:I->O 22 0.086 0.535 sys_reset_n_inv1_INV_0 (sys_reset_n_inv) + FDCE:CLR 0.434 reg_count_23_16_0 + ---------------------------------------- + Total 1.457ns (0.523ns logic, 0.934ns route) + (35.9% logic, 64.1% route) + +========================================================================= +Timing constraint: Default OFFSET IN BEFORE for Clock 'ftop/gbe0/gmac/gmii_rxc_dly$DATAOUT' + Total number of paths / destination ports: 10 / 10 +------------------------------------------------------------------------- +Offset: 0.413ns (Levels of Logic = 3) + Source: gmii_rxd<0> (PAD) + Destination: ftop/gbe0/gmac/rxRS_rxData_0 (FF) + Destination Clock: ftop/gbe0/gmac/gmii_rxc_dly$DATAOUT rising + + Data Path: gmii_rxd<0> to ftop/gbe0/gmac/rxRS_rxData_0 + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + IBUF:I->O 1 0.003 0.399 gmii_rxd_0_IBUF (gmii_rxd_0_IBUF) + begin scope: 'ftop:gmii_rx_rxd_i<0>' + begin scope: 'ftop/gbe0:gmii_rx_rxd_i<0>' + begin scope: 'ftop/gbe0/gmac:gmii_rx_rxd_i<0>' + FD:D 0.011 rxRS_rxData_0 + ---------------------------------------- + Total 0.413ns (0.014ns logic, 0.399ns route) + (3.4% logic, 96.6% route) + +========================================================================= +Timing constraint: Default OFFSET IN BEFORE for Clock 'sys0_clkp' + Total number of paths / destination ports: 11 / 11 +------------------------------------------------------------------------- +Offset: 0.413ns (Levels of Logic = 3) + Source: ppsExtIn (PAD) + Destination: ftop/ctop/inf/cp/timeServ_ppsExtSync_d1 (FF) + Destination Clock: sys0_clkp rising + + Data Path: ppsExtIn to ftop/ctop/inf/cp/timeServ_ppsExtSync_d1 + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + IBUF:I->O 1 0.003 0.399 ppsExtIn_IBUF (ppsExtIn_IBUF) + begin scope: 'ftop:gps_ppsSyncIn_x' + begin scope: 'ftop/ctop:gps_ppsSyncIn_x' + begin scope: 'ftop/ctop/inf:gps_ppsSyncIn_x' + begin scope: 'ftop/ctop/inf/cp:gps_ppsSyncIn_x' + FDR:D 0.011 timeServ_ppsExtSync_d1 + ---------------------------------------- + Total 0.413ns (0.014ns logic, 0.399ns route) + (3.4% logic, 96.6% route) + +========================================================================= +Timing constraint: Default OFFSET IN BEFORE for Clock 'ftop/fmc150/spiCDC_cd/cntr_2' + Total number of paths / destination ports: 1 / 1 +------------------------------------------------------------------------- +Offset: 0.413ns (Levels of Logic = 2) + Source: flp_cdc_sdi (PAD) + Destination: ftop/fmc150/spiCDC_sdiP (FF) + Destination Clock: ftop/fmc150/spiCDC_cd/cntr_2 falling + + Data Path: flp_cdc_sdi to ftop/fmc150/spiCDC_sdiP + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + IBUF:I->O 1 0.003 0.399 flp_cdc_sdi_IBUF (flp_cdc_sdi_IBUF) + begin scope: 'ftop:flpCDC_sdi_arg' + begin scope: 'ftop/fmc150:padsCDC_sdi_arg' + FD:D 0.011 spiCDC_sdiP + ---------------------------------------- + Total 0.413ns (0.014ns logic, 0.399ns route) + (3.4% logic, 96.6% route) + +========================================================================= +Timing constraint: Default OFFSET IN BEFORE for Clock 'ftop/fmc150/spiDAC_cd/cntr_3' + Total number of paths / destination ports: 1 / 1 +------------------------------------------------------------------------- +Offset: 0.413ns (Levels of Logic = 2) + Source: flp_dac_sdi (PAD) + Destination: ftop/fmc150/spiDAC_sdiP (FF) + Destination Clock: ftop/fmc150/spiDAC_cd/cntr_3 falling + + Data Path: flp_dac_sdi to ftop/fmc150/spiDAC_sdiP + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + IBUF:I->O 1 0.003 0.399 flp_dac_sdi_IBUF (flp_dac_sdi_IBUF) + begin scope: 'ftop:flpDAC_sdi_arg' + begin scope: 'ftop/fmc150:padsDAC_sdi_arg' + FD:D 0.011 spiDAC_sdiP + ---------------------------------------- + Total 0.413ns (0.014ns logic, 0.399ns route) + (3.4% logic, 96.6% route) + +========================================================================= +Timing constraint: Default OFFSET IN BEFORE for Clock 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/rsync_odelay<1>' + Total number of paths / destination ports: 1665 / 675 +------------------------------------------------------------------------- +Offset: 1.793ns (Levels of Logic = 4) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7].u_phy_dqs_iob/u_iserdes_dqs_p:Q3 (PAD) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7].u_phy_dqs_iob/u_rd_bitslip_early/qout_1 (FF) + Destination Clock: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/rsync_odelay<1> rising + + Data Path: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7].u_phy_dqs_iob/u_iserdes_dqs_p:Q3 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7].u_phy_dqs_iob/u_rd_bitslip_early/qout_1 + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + ISERDESE1:Q3 2 0.000 0.497 u_iserdes_dqs_p (iserdes_q<2>) + LUT3:I1->O 4 0.068 0.658 Mmux_iserdes_q_mux31 (iserdes_q_mux<2>) + begin scope: 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7].u_phy_dqs_iob/u_rd_bitslip_early:din<2>' + LUT6:I2->O 2 0.068 0.423 Mmux_slip_out21 (slip_out<1>) + LUT6:I5->O 1 0.068 0.000 mux113 (clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<1>) + FD:D 0.011 qout_1 + ---------------------------------------- + Total 1.793ns (0.215ns logic, 1.578ns route) + (12.0% logic, 88.0% route) + +========================================================================= +Timing constraint: Default OFFSET IN BEFORE for Clock 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/rsync_odelay<0>' + Total number of paths / destination ports: 999 / 405 +------------------------------------------------------------------------- +Offset: 1.793ns (Levels of Logic = 4) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2].u_phy_dqs_iob/u_iserdes_dqs_p:Q3 (PAD) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2].u_phy_dqs_iob/u_rd_bitslip_early/qout_1 (FF) + Destination Clock: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/rsync_odelay<0> rising + + Data Path: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2].u_phy_dqs_iob/u_iserdes_dqs_p:Q3 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2].u_phy_dqs_iob/u_rd_bitslip_early/qout_1 + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + ISERDESE1:Q3 2 0.000 0.497 u_iserdes_dqs_p (iserdes_q<2>) + LUT3:I1->O 4 0.068 0.658 Mmux_iserdes_q_mux31 (iserdes_q_mux<2>) + begin scope: 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2].u_phy_dqs_iob/u_rd_bitslip_early:din<2>' + LUT6:I2->O 2 0.068 0.423 Mmux_slip_out21 (slip_out<1>) + LUT6:I5->O 1 0.068 0.000 mux113 (clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<1>) + FD:D 0.011 qout_1 + ---------------------------------------- + Total 1.793ns (0.215ns logic, 1.578ns route) + (12.0% logic, 88.0% route) + +========================================================================= +Timing constraint: Default OFFSET OUT AFTER for Clock 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/TxOutClk' + Total number of paths / destination ports: 75 / 58 +------------------------------------------------------------------------- +Offset: 1.360ns (Levels of Logic = 4) + Source: ftop/flash0/flashC_tsOE (FF) + Destination: flash_io_dq<15> (PAD) + Source Clock: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/TxOutClk rising 0.5X + + Data Path: ftop/flash0/flashC_tsOE to flash_io_dq<15> + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + FDRE:C->Q 1 0.375 0.399 flashC_tsOE (flashC_tsOE) + begin scope: 'ftop/flash0/flashC_tsd:OE' + INV:I->O 16 0.086 0.497 OE_inv1_INV_0 (OE_inv) + IOBUF:T->IO 0.003 IO_15_IOBUF (IO<15>) + end scope: 'ftop/flash0/flashC_tsd:IO<15>' + end scope: 'ftop/flash0:flash_io_dq<15>' + end scope: 'ftop:flash_io_dq<15>' + ---------------------------------------- + Total 1.360ns (0.464ns logic, 0.896ns route) + (34.1% logic, 65.9% route) + +========================================================================= +Timing constraint: Default OFFSET OUT AFTER for Clock 'sys1_clkp' + Total number of paths / destination ports: 12 / 12 +------------------------------------------------------------------------- +Offset: 1.009ns (Levels of Logic = 3) + Source: ftop/gbe0/gmac/txRS_iobTxData_7 (FF) + Destination: gmii_txd<7> (PAD) + Source Clock: sys1_clkp rising + + Data Path: ftop/gbe0/gmac/txRS_iobTxData_7 to gmii_txd<7> + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + ODDR:C->Q 1 0.607 0.399 txRS_iobTxData_7 (gmii_tx_txd<7>) + end scope: 'ftop/gbe0/gmac:gmii_tx_txd<7>' + end scope: 'ftop/gbe0:gmii_tx_txd<7>' + end scope: 'ftop:gmii_tx_txd<7>' + OBUF:I->O 0.003 gmii_txd_7_OBUF (gmii_txd<7>) + ---------------------------------------- + Total 1.009ns (0.610ns logic, 0.399ns route) + (60.5% logic, 39.5% route) + +========================================================================= +Timing constraint: Default OFFSET OUT AFTER for Clock 'sys0_clkp' + Total number of paths / destination ports: 1228 / 1056 +------------------------------------------------------------------------- +Offset: 1.870ns (Levels of Logic = 5) + Source: ftop/dram0/memc_memc/u_infrastructure/rstdiv0_sync_r_7 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_clock_io/gen_ck[0].u_phy_ck_iob/u_oserdes_ck_p:RST (PAD) + Source Clock: sys0_clkp rising + + Data Path: ftop/dram0/memc_memc/u_infrastructure/rstdiv0_sync_r_7 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_clock_io/gen_ck[0].u_phy_ck_iob/u_oserdes_ck_p:RST + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + FDP:C->Q 3 0.375 0.413 rstdiv0_sync_r_7 (rstdiv0_sync_r_7) + end scope: 'ftop/dram0/memc_memc/u_infrastructure:rstdiv0' + begin scope: 'ftop/dram0/memc_memc/u_memc_ui_top:rst' + BUF:I->O 10 0.086 0.458 rst_1 (rst_1) + begin scope: 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc:rst' + begin scope: 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0:rst' + BUF:I->O 9 0.086 0.452 rst_8 (rst_8) + begin scope: 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_clock_io:rst' + begin scope: 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_clock_io/gen_ck[0].u_phy_ck_iob:rst' + OSERDESE1:RST 0.000 u_oserdes_ck_p + ---------------------------------------- + Total 1.870ns (0.547ns logic, 1.323ns route) + (29.3% logic, 70.7% route) + +========================================================================= +Timing constraint: Default OFFSET OUT AFTER for Clock 'ftop/fmc150/spiCDC_cd/cntr_2' + Total number of paths / destination ports: 5 / 4 +------------------------------------------------------------------------- +Offset: 1.923ns (Levels of Logic = 4) + Source: ftop/fmc150/spiCDC_csbR (FF) + Destination: flp_com_sclk (PAD) + Source Clock: ftop/fmc150/spiCDC_cd/cntr_2 rising + + Data Path: ftop/fmc150/spiCDC_csbR to flp_com_sclk + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + FDS:C->Q 2 0.375 0.405 spiCDC_csbR (spiCDC_csbR) + INV:I->O 2 0.086 0.587 spiCDC_csbR_inv1_INV_0 (padsCDC_sclkgate) + end scope: 'ftop/fmc150:padsCDC_sclkgate' + end scope: 'ftop:flpCDC_sclkgate' + LUT4:I1->O 1 0.068 0.399 flp_com_sdc2m1 (flp_com_sdc2m_OBUF) + OBUF:I->O 0.003 flp_com_sdc2m_OBUF (flp_com_sdc2m) + ---------------------------------------- + Total 1.923ns (0.532ns logic, 1.391ns route) + (27.7% logic, 72.3% route) + +========================================================================= +Timing constraint: Default OFFSET OUT AFTER for Clock 'ftop/fmc150/spiDAC_cd/cntr_3' + Total number of paths / destination ports: 4 / 3 +------------------------------------------------------------------------- +Offset: 1.336ns (Levels of Logic = 3) + Source: ftop/fmc150/spiDAC_sdoR (FF) + Destination: flp_com_sdc2m (PAD) + Source Clock: ftop/fmc150/spiDAC_cd/cntr_3 rising + + Data Path: ftop/fmc150/spiDAC_sdoR to flp_com_sdc2m + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + FDRE:C->Q 1 0.375 0.491 spiDAC_sdoR (spiDAC_sdoR) + end scope: 'ftop/fmc150:padsDAC_sdo' + end scope: 'ftop:flpDAC_sdo' + LUT4:I2->O 1 0.068 0.399 flp_com_sdc2m1 (flp_com_sdc2m_OBUF) + OBUF:I->O 0.003 flp_com_sdc2m_OBUF (flp_com_sdc2m) + ---------------------------------------- + Total 1.336ns (0.446ns logic, 0.890ns route) + (33.4% logic, 66.6% route) + +========================================================================= +Timing constraint: Default OFFSET OUT AFTER for Clock 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/rsync_odelay<1>' + Total number of paths / destination ports: 250 / 250 +------------------------------------------------------------------------- +Offset: 0.827ns (Levels of Logic = 2) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_dly_ctrl/dlyval_dq_39 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_inst.gen_dm[7].u_phy_dm_iob/u_odelay_dm:CNTVALUEIN4 (PAD) + Source Clock: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/rsync_odelay<1> rising + + Data Path: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_dly_ctrl/dlyval_dq_39 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_inst.gen_dm[7].u_phy_dm_iob/u_odelay_dm:CNTVALUEIN4 + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + FD:C->Q 9 0.375 0.452 dlyval_dq_39 (dlyval_dq_39) + end scope: 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_dly_ctrl:dlyval_dq<39>' + begin scope: 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io:dlyval_dq<39>' + begin scope: 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_inst.gen_dm[7].u_phy_dm_iob:dlyval<4>' + IODELAYE1:CNTVALUEIN4 0.000 u_odelay_dm + ---------------------------------------- + Total 0.827ns (0.375ns logic, 0.452ns route) + (45.3% logic, 54.7% route) + +========================================================================= +Timing constraint: Default OFFSET OUT AFTER for Clock 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/rsync_odelay<0>' + Total number of paths / destination ports: 150 / 150 +------------------------------------------------------------------------- +Offset: 0.827ns (Levels of Logic = 2) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_dly_ctrl/dlyval_dq_14 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_inst.gen_dm[2].u_phy_dm_iob/u_odelay_dm:CNTVALUEIN4 (PAD) + Source Clock: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/rsync_odelay<0> rising + + Data Path: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_dly_ctrl/dlyval_dq_14 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_inst.gen_dm[2].u_phy_dm_iob/u_odelay_dm:CNTVALUEIN4 + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + FD:C->Q 9 0.375 0.452 dlyval_dq_14 (dlyval_dq_14) + end scope: 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_dly_ctrl:dlyval_dq<14>' + begin scope: 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io:dlyval_dq<14>' + begin scope: 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_inst.gen_dm[2].u_phy_dm_iob:dlyval<4>' + IODELAYE1:CNTVALUEIN4 0.000 u_odelay_dm + ---------------------------------------- + Total 0.827ns (0.375ns logic, 0.452ns route) + (45.3% logic, 54.7% route) + +========================================================================= +Timing constraint: Default path analysis + Total number of paths / destination ports: 596 / 532 +------------------------------------------------------------------------- +Delay: 0.538ns (Levels of Logic = 3) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[7].u_bufio_cpt:O (PAD) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7].u_phy_dqs_iob/u_iserdes_dqs_p:CLKB (PAD) + + Data Path: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[7].u_bufio_cpt:O to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7].u_phy_dqs_iob/u_iserdes_dqs_p:CLKB + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + BUFIODQS:O 9 0.000 0.000 gen_ck_cpt[7].u_bufio_cpt (clk_cpt<7>) + end scope: 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen:clk_cpt<7>' + end scope: 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read:clk_cpt<7>' + begin scope: 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io:clk_cpt<7>' + begin scope: 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7].u_phy_dqs_iob:clk_cpt' + INV:I->O 0 0.086 0.000 iserdes_clkb1_INV_0 (iserdes_clkb) + ISERDESE1:CLKB 0.000 u_iserdes_dqs_p + ---------------------------------------- + Total 0.538ns (0.538ns logic, 0.000ns route) + (100.0% logic, 0.0% route) + +========================================================================= + +Cross Clock Domains Report: +-------------------------- + +Clock to Setup on destination clock flp_cdc_clk_p +----------------------------------------------------------------+---------+---------+---------+---------+ + | Src:Rise| Src:Fall| Src:Rise| Src:Fall| +Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| +----------------------------------------------------------------+---------+---------+---------+---------+ +flp_cdc_clk_p | 4.676| | | | +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/TxOutClk| 1.824| | | | +----------------------------------------------------------------+---------+---------+---------+---------+ + +Clock to Setup on destination clock ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/rsync_odelay<0> +--------------------------------------------------------------------------------------------------+---------+---------+---------+---------+ + | Src:Rise| Src:Fall| Src:Rise| Src:Fall| +Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| +--------------------------------------------------------------------------------------------------+---------+---------+---------+---------+ +ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/rsync_odelay<0>| 2.088| 0.778| | | +sys0_clkp | 2.410| | | | +--------------------------------------------------------------------------------------------------+---------+---------+---------+---------+ + +Clock to Setup on destination clock ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/rsync_odelay<1> +--------------------------------------------------------------------------------------------------+---------+---------+---------+---------+ + | Src:Rise| Src:Fall| Src:Rise| Src:Fall| +Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| +--------------------------------------------------------------------------------------------------+---------+---------+---------+---------+ +ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/rsync_odelay<1>| 2.088| 0.778| | | +sys0_clkp | 2.410| | | | +--------------------------------------------------------------------------------------------------+---------+---------+---------+---------+ + +Clock to Setup on destination clock ftop/fmc150/spiCDC_cd/cntr_2 +----------------------------------------------------------------+---------+---------+---------+---------+ + | Src:Rise| Src:Fall| Src:Rise| Src:Fall| +Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| +----------------------------------------------------------------+---------+---------+---------+---------+ +ftop/fmc150/spiCDC_cd/cntr_2 | 3.708| 0.791| | | +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/TxOutClk| 3.854| | | | +----------------------------------------------------------------+---------+---------+---------+---------+ + +Clock to Setup on destination clock ftop/fmc150/spiDAC_cd/cntr_3 +----------------------------------------------------------------+---------+---------+---------+---------+ + | Src:Rise| Src:Fall| Src:Rise| Src:Fall| +Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| +----------------------------------------------------------------+---------+---------+---------+---------+ +ftop/fmc150/spiDAC_cd/cntr_3 | 3.785| 0.791| | | +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/TxOutClk| 3.951| | | | +----------------------------------------------------------------+---------+---------+---------+---------+ + +Clock to Setup on destination clock ftop/gbe0/gmac/gmii_rxc_dly$DATAOUT +----------------------------------------------------------------+---------+---------+---------+---------+ + | Src:Rise| Src:Fall| Src:Rise| Src:Fall| +Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| +----------------------------------------------------------------+---------+---------+---------+---------+ +ftop/gbe0/gmac/gmii_rxc_dly$DATAOUT | 3.539| | | | +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/TxOutClk| 1.860| | | | +----------------------------------------------------------------+---------+---------+---------+---------+ + +Clock to Setup on destination clock ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/TxOutClk +----------------------------------------------------------------+---------+---------+---------+---------+ + | Src:Rise| Src:Fall| Src:Rise| Src:Fall| +Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| +----------------------------------------------------------------+---------+---------+---------+---------+ +flp_cdc_clk_p | 0.857| | | | +ftop/fmc150/spiCDC_cd/cntr_2 | 5.230| | | | +ftop/fmc150/spiDAC_cd/cntr_3 | 5.350| | | | +ftop/gbe0/gmac/gmii_rxc_dly$DATAOUT | 2.078| | | | +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/TxOutClk| 8.149| | | | +ftop/pciw_pci0_pcie_ep/ep/pcie_clocking_i/clk_125 | 2.324| | | | +sys0_clkp | 2.654| | | | +sys1_clkp | 1.727| | | | +----------------------------------------------------------------+---------+---------+---------+---------+ + +Clock to Setup on destination clock ftop/pciw_pci0_pcie_ep/ep/pcie_clocking_i/clk_125 +-------------------------------------------------+---------+---------+---------+---------+ + | Src:Rise| Src:Fall| Src:Rise| Src:Fall| +Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| +-------------------------------------------------+---------+---------+---------+---------+ +ftop/pciw_pci0_pcie_ep/ep/pcie_clocking_i/clk_125| 3.724| | | | +-------------------------------------------------+---------+---------+---------+---------+ + +Clock to Setup on destination clock sys0_clkp +--------------------------------------------------------------------------------------------------+---------+---------+---------+---------+ + | Src:Rise| Src:Fall| Src:Rise| Src:Fall| +Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| +--------------------------------------------------------------------------------------------------+---------+---------+---------+---------+ +ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/rsync_odelay<0>| 1.675| | | | +ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/rsync_odelay<1>| 1.675| | | | +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/TxOutClk | 2.368| | | | +sys0_clkp | 4.758| | | | +--------------------------------------------------------------------------------------------------+---------+---------+---------+---------+ + +Clock to Setup on destination clock sys1_clkp +----------------------------------------------------------------+---------+---------+---------+---------+ + | Src:Rise| Src:Fall| Src:Rise| Src:Fall| +Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| +----------------------------------------------------------------+---------+---------+---------+---------+ +ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/TxOutClk| 2.078| | | | +sys1_clkp | 3.851| | | | +----------------------------------------------------------------+---------+---------+---------+---------+ + +========================================================================= + + +Total REAL time to Xst completion: 341.00 secs +Total CPU time to Xst completion: 340.10 secs + +--> + + +Total memory usage is 1406988 kilobytes + +Number of errors : 0 ( 0 filtered) +Number of warnings : 2480 ( 0 filtered) +Number of infos : 422 ( 0 filtered) + diff --git a/logs/ml605-20130127_1122/fpgaTop.bld b/logs/ml605-20130127_1122/fpgaTop.bld new file mode 100644 index 00000000..cf059c52 --- /dev/null +++ b/logs/ml605-20130127_1122/fpgaTop.bld @@ -0,0 +1,5870 @@ +Release 14.4 ngdbuild P.49d (lin64) +Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. + +Command Line: /opt/Xilinx/14.4/ISE_DS/ISE/bin/lin64/unwrapped/ngdbuild -sd +../../coregen/pcie_4243_trn_v6_gtx_x4_250 -sd ../../coregen/fft_v5_4k_strm_nat +-sd ../../coregen/ddc_4243_4ch_v5 -aul -aut -uc ml605.ucf -p xc6vlx240t-ff1156-1 +fpgaTop_csi.ngc fpgaTop.ngd + +Reading NGO file "/home/shep/projects/ocpi/build/tmp-ml605/fpgaTop_csi.ngc" ... +Gathering constraint information from source properties... +Done. + +Annotating constraints to design from ucf file "ml605.ucf" ... +WARNING:NgdBuild - The value of SIM_DEVICE on instance + 'ftop/gbe0/gmac/rxClk_BUFR' of type BUFR has been changed from 'VIRTEX4' to + 'VIRTEX6' to correct post-ngdbuild and timing simulation for this primitive. + In order for functional simulation to be correct, the value of SIM_DEVICE + should be changed in this same manner in the source netlist or constraint + file. +Resolving constraint associations... +Checking Constraint Associations... +WARNING:ConstraintSystem - Constraint + [ml605.ucf(45)] was not distributed to the output pin TXOUTCLK of block + GTXD[0].GTX because the signal path to this output pin depends upon block + attribute settings. Constraint distribution does not support attribute + dependent distribution. + +INFO:ConstraintSystem:59 - Constraint + [ml605.ucf(106)]: NET "gmii_tx_clk" not found. Please verify that: + 1. The specified design element actually exists in the original design. + 2. The specified object is spelled correctly in the constraint source file. + +WARNING:ConstraintSystem - A target design object for the Locate constraint + ' [ml605.ucf(106)]' could not be found + and so the Locate constraint will be removed. + +INFO:ConstraintSystem:59 - Constraint [ml605.ucf(106)]: + NET "gmii_tx_clk" not found. Please verify that: + 1. The specified design element actually exists in the original design. + 2. The specified object is spelled correctly in the constraint source file. + +INFO:ConstraintSystem:59 - Constraint + [ml605.ucf(118)]: NET "gmii_COL" not found. Please verify that: + 1. The specified design element actually exists in the original design. + 2. The specified object is spelled correctly in the constraint source file. + +WARNING:ConstraintSystem - A target design object for the Locate constraint + ' [ml605.ucf(118)]' could not be found + and so the Locate constraint will be removed. + +INFO:ConstraintSystem:59 - Constraint [ml605.ucf(118)]: + NET "gmii_COL" not found. Please verify that: + 1. The specified design element actually exists in the original design. + 2. The specified object is spelled correctly in the constraint source file. + +INFO:ConstraintSystem:59 - Constraint + [ml605.ucf(119)]: NET "gmii_CRS" not found. Please verify that: + 1. The specified design element actually exists in the original design. + 2. The specified object is spelled correctly in the constraint source file. + +WARNING:ConstraintSystem - A target design object for the Locate constraint + ' [ml605.ucf(119)]' could not be found + and so the Locate constraint will be removed. + +INFO:ConstraintSystem:59 - Constraint [ml605.ucf(119)]: + NET "gmii_CRS" not found. Please verify that: + 1. The specified design element actually exists in the original design. + 2. The specified object is spelled correctly in the constraint source file. + +INFO:ConstraintSystem:59 - Constraint + [ml605.ucf(120)]: NET "gmii_INT" not found. Please verify that: + 1. The specified design element actually exists in the original design. + 2. The specified object is spelled correctly in the constraint source file. + +WARNING:ConstraintSystem - A target design object for the Locate constraint + ' [ml605.ucf(120)]' could not be found + and so the Locate constraint will be removed. + +INFO:ConstraintSystem:59 - Constraint [ml605.ucf(120)]: + NET "gmii_INT" not found. Please verify that: + 1. The specified design element actually exists in the original design. + 2. The specified object is spelled correctly in the constraint source file. + +INFO:ConstraintSystem:59 - Constraint + [ml605.ucf(274)]: NET "flp_cdc_pllstat" not found. Please verify that: + 1. The specified design element actually exists in the original design. + 2. The specified object is spelled correctly in the constraint source file. + +WARNING:ConstraintSystem - A target design object for the Locate constraint + ' [ml605.ucf(274)]' could not be found + and so the Locate constraint will be removed. + +INFO:ConstraintSystem:59 - Constraint + [ml605.ucf(274)]: NET "flp_cdc_pllstat" not found. Please verify that: + 1. The specified design element actually exists in the original design. + 2. The specified object is spelled correctly in the constraint source file. + +INFO:ConstraintSystem:59 - Constraint + [ml605.ucf(279)]: NET "flp_mon_rstn" not found. Please verify that: + 1. The specified design element actually exists in the original design. + 2. The specified object is spelled correctly in the constraint source file. + +WARNING:ConstraintSystem - A target design object for the Locate constraint + ' [ml605.ucf(279)]' could not be found + and so the Locate constraint will be removed. + +INFO:ConstraintSystem:59 - Constraint + [ml605.ucf(279)]: NET "flp_mon_rstn" not found. Please verify that: + 1. The specified design element actually exists in the original design. + 2. The specified object is spelled correctly in the constraint source file. + +INFO:ConstraintSystem:59 - Constraint + [ml605.ucf(280)]: NET "flp_mon_intn" not found. Please verify that: + 1. The specified design element actually exists in the original design. + 2. The specified object is spelled correctly in the constraint source file. + +WARNING:ConstraintSystem - A target design object for the Locate constraint + ' [ml605.ucf(280)]' could not be found + and so the Locate constraint will be removed. + +INFO:ConstraintSystem:59 - Constraint + [ml605.ucf(280)]: NET "flp_mon_intn" not found. Please verify that: + 1. The specified design element actually exists in the original design. + 2. The specified object is spelled correctly in the constraint source file. + +INFO:ConstraintSystem:59 - Constraint + [ml605.ucf(287)]: NET "flp_adc_rstn" not found. Please verify that: + 1. The specified design element actually exists in the original design. + 2. The specified object is spelled correctly in the constraint source file. + +WARNING:ConstraintSystem - A target design object for the Locate constraint + ' [ml605.ucf(287)]' could not be found + and so the Locate constraint will be removed. + +INFO:ConstraintSystem:59 - Constraint + [ml605.ucf(287)]: NET "flp_adc_rstn" not found. Please verify that: + 1. The specified design element actually exists in the original design. + 2. The specified object is spelled correctly in the constraint source file. + +INFO:ConstraintSystem:58 - Constraint [ml605.ucf(754)]: INST + "*/gen_enable_ocb_mon.u_phy_ocb_mon_top/u_oserdes_ocb_mon" does not match any + design objects. + +WARNING:ConstraintSystem - A target design object for the Locate constraint + ' [ml605.ucf(754)]' could not be found and so the Locate + constraint will be removed. + +INFO:ConstraintSystem:59 - Constraint + [ml605.ucf(761)]: INST "ftop/dram0/memc/u_infrastructure/u_mmcm_adv" not + found. Please verify that: + 1. The specified design element actually exists in the original design. + 2. The specified object is spelled correctly in the constraint source file. + +WARNING:ConstraintSystem - A target design object for the Locate constraint + ' [ml605.ucf(761)]' could not be found and so the Locate + constraint will be removed. + +INFO:ConstraintSystem:59 - Constraint [ml605.ucf(762)]: INST + "ftop/dram0/memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_ge + n/u_mmcm_clk_base" not found. Please verify that: + 1. The specified design element actually exists in the original design. + 2. The specified object is spelled correctly in the constraint source file. + +WARNING:ConstraintSystem - A target design object for the Locate constraint + ' [ml605.ucf(762)]' could not be + found and so the Locate constraint will be removed. + +INFO:ConstraintSystem:178 - TNM 'SYS0CLK', used in period specification + 'TS_SYS0CLK', was traced into MMCM_ADV instance u_mmcm_adv. The following new + TNM groups and period specifications were generated at the MMCM_ADV + output(s): + CLKOUT1: + +INFO:ConstraintSystem:178 - TNM 'SYS0CLK', used in period specification + 'TS_SYS0CLK', was traced into MMCM_ADV instance u_mmcm_adv. The following new + TNM groups and period specifications were generated at the MMCM_ADV + output(s): + CLKOUT0: + +INFO:ConstraintSystem:178 - TNM 'SYS0CLK', used in period specification + 'TS_SYS0CLK', was traced into MMCM_ADV instance u_mmcm_adv. The following new + TNM groups and period specifications were generated at the MMCM_ADV + output(s): + CLKOUT2: + +Done... + +Checking expanded design ... +WARNING:NgdBuild:452 - logical net 'N100' has no driver +WARNING:NgdBuild:452 - logical net 'N101' has no driver +WARNING:NgdBuild:452 - logical net 'N102' has no driver +WARNING:NgdBuild:452 - logical net 'N103' has no driver +WARNING:NgdBuild:452 - logical net 'N104' has no driver +WARNING:NgdBuild:452 - logical net 'N105' has no driver +WARNING:NgdBuild:452 - logical net 'N106' has no driver +WARNING:NgdBuild:452 - logical net 'N107' has no driver +WARNING:NgdBuild:452 - logical net 'N108' has no driver +WARNING:NgdBuild:452 - logical net 'N109' has no driver +WARNING:NgdBuild:452 - logical net 'N110' has no driver +WARNING:NgdBuild:452 - logical net 'N111' has no driver +WARNING:NgdBuild:452 - logical net 'N112' has no driver +WARNING:NgdBuild:452 - logical net 'N113' has no driver +WARNING:NgdBuild:452 - logical net 'N114' has no driver +WARNING:NgdBuild:452 - logical net 'N115' has no driver +WARNING:NgdBuild:452 - logical net 'N116' has no driver +WARNING:NgdBuild:452 - logical net 'N117' has no driver +WARNING:NgdBuild:452 - logical net 'N118' has no driver +WARNING:NgdBuild:452 - logical net 'N119' has no driver +WARNING:NgdBuild:452 - logical net 'N120' has no driver +WARNING:NgdBuild:452 - logical net 'N121' has no driver +WARNING:NgdBuild:452 - logical net 'N122' has no driver +WARNING:NgdBuild:452 - logical net 'N123' has no driver +WARNING:NgdBuild:452 - logical net 'N124' has no driver +WARNING:NgdBuild:452 - logical net 'N125' has no driver +WARNING:NgdBuild:452 - logical net 'N126' has no driver +WARNING:NgdBuild:452 - logical net 'N127' has no driver +WARNING:NgdBuild:452 - logical net 'N128' has no driver +WARNING:NgdBuild:452 - logical net 'N129' has no driver +WARNING:NgdBuild:452 - logical net 'N130' has no driver +WARNING:NgdBuild:452 - logical net 'N131' has no driver +WARNING:NgdBuild:452 - logical net 'N132' has no driver +WARNING:NgdBuild:452 - logical net 'N133' has no driver +WARNING:NgdBuild:452 - logical net 'N134' has no driver +WARNING:NgdBuild:452 - logical net 'N135' has no driver +WARNING:NgdBuild:452 - logical net 'N136' has no driver +WARNING:NgdBuild:452 - logical net 'N137' has no driver +WARNING:NgdBuild:452 - logical net 'N138' has no driver +WARNING:NgdBuild:452 - logical net 'N139' has no driver +WARNING:NgdBuild:452 - logical net 'N140' has no driver +WARNING:NgdBuild:452 - logical net 'N141' has no driver +WARNING:NgdBuild:452 - logical net 'N142' has no driver +WARNING:NgdBuild:452 - logical net 'N143' has no driver +WARNING:NgdBuild:452 - logical net 'N144' has no driver +WARNING:NgdBuild:452 - logical net 'N145' has no driver +WARNING:NgdBuild:452 - logical net 'N146' has no driver +WARNING:NgdBuild:452 - logical net 'N147' has no driver +WARNING:NgdBuild:452 - logical net 'N148' has no driver +WARNING:NgdBuild:452 - logical net 'N149' has no driver +WARNING:NgdBuild:452 - logical net 'N150' has no driver +WARNING:NgdBuild:452 - logical net 'N151' has no driver +WARNING:NgdBuild:452 - logical net 'N152' has no driver +WARNING:NgdBuild:452 - logical net 'N153' has no driver +WARNING:NgdBuild:452 - logical net 'N154' has no driver +WARNING:NgdBuild:452 - logical net 'N155' has no driver +WARNING:NgdBuild:452 - logical net 'N156' has no driver +WARNING:NgdBuild:452 - logical net 'N157' has no driver +WARNING:NgdBuild:452 - logical net 'N158' has no driver +WARNING:NgdBuild:452 - logical net 'N159' has no driver +WARNING:NgdBuild:452 - logical net 'N160' has no driver +WARNING:NgdBuild:452 - logical net 'N161' has no driver +WARNING:NgdBuild:452 - logical net 'N162' has no driver +WARNING:NgdBuild:452 - logical net 'N163' has no driver +WARNING:NgdBuild:452 - logical net 'N164' has no driver +WARNING:NgdBuild:452 - logical net 'N165' has no driver +WARNING:NgdBuild:452 - logical net 'N166' has no driver +WARNING:NgdBuild:452 - logical net 'N167' has no driver +WARNING:NgdBuild:452 - logical net 'N168' has no driver +WARNING:NgdBuild:452 - logical net 'N169' has no driver +WARNING:NgdBuild:452 - logical net 'N170' has no driver +WARNING:NgdBuild:452 - logical net 'N171' has no driver +WARNING:NgdBuild:452 - logical net 'N172' has no driver +WARNING:NgdBuild:452 - logical net 'N173' has no driver +WARNING:NgdBuild:452 - logical net 'N174' has no driver +WARNING:NgdBuild:452 - logical net 'N175' has no driver +WARNING:NgdBuild:452 - logical net 'N176' has no driver +WARNING:NgdBuild:452 - logical net 'N177' has no driver +WARNING:NgdBuild:452 - logical net 'N178' has no driver +WARNING:NgdBuild:452 - logical net 'N179' has no driver +WARNING:NgdBuild:452 - logical net 'N180' has no driver +WARNING:NgdBuild:452 - logical net 'N181' has no driver +WARNING:NgdBuild:452 - logical net 'N182' has no driver +WARNING:NgdBuild:452 - logical net 'N183' has no driver +WARNING:NgdBuild:452 - logical net 'N184' has no driver +WARNING:NgdBuild:452 - logical net 'N185' has no driver +WARNING:NgdBuild:452 - logical net 'N186' has no driver +WARNING:NgdBuild:452 - logical net 'N187' has no driver +WARNING:NgdBuild:452 - logical net 'N188' has no driver +WARNING:NgdBuild:452 - logical net 'N189' has no driver +WARNING:NgdBuild:452 - logical net 'N190' has no driver +WARNING:NgdBuild:452 - logical net 'N191' has no driver +WARNING:NgdBuild:452 - logical net 'N192' has no driver +WARNING:NgdBuild:452 - logical net 'N193' has no driver +WARNING:NgdBuild:452 - logical net 'N194' has no driver +WARNING:NgdBuild:452 - logical net 'N195' has no driver +WARNING:NgdBuild:452 - logical net 'N196' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/gmii_led' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop$wci_m_0_MByteEn<1>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop$wci_m_0_MByteEn<0>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop$wci_m_0_MAddr<31>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop$wci_m_0_MAddr<30>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop$wci_m_0_MAddr<29>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop$wci_m_0_MAddr<28>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop$wci_m_0_MAddr<27>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop$wci_m_0_MAddr<26>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop$wci_m_0_MAddr<25>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop$wci_m_0_MAddr<24>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop$wci_m_0_MAddr<23>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop$wci_m_0_MAddr<22>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop$wci_m_0_MAddr<21>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop$wci_m_0_MAddr<20>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop$wci_m_0_MAddr<19>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop$wci_m_0_MAddr<18>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop$wci_m_0_MAddr<17>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop$wci_m_0_MAddr<16>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop$wci_m_1_MByteEn<1>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop$wci_m_1_MByteEn<0>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop$wci_m_1_MAddr<31>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop$wci_m_1_MAddr<30>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop$wci_m_1_MAddr<29>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop$wci_m_1_MAddr<28>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop$wci_m_1_MAddr<27>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop$wci_m_1_MAddr<26>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop$wci_m_1_MAddr<25>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop$wci_m_1_MAddr<24>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop$wci_m_1_MAddr<23>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop$wci_m_1_MAddr<22>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop$wci_m_2_MByteEn<1>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop$wci_m_2_MByteEn<0>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop$wci_m_2_MAddr<31>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop$wci_m_2_MAddr<30>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop$wci_m_2_MAddr<29>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop$wci_m_2_MAddr<28>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop$wci_m_2_MAddr<27>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop$wci_m_2_MAddr<26>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop$wci_m_2_MAddr<25>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop$wci_m_2_MAddr<24>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop$wci_m_2_MAddr<23>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop$wci_m_2_MAddr<22>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop$wci_m_2_MAddr<21>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop$wci_m_2_MAddr<20>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop$wci_m_2_MAddr<19>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop$wci_m_2_MAddr<18>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop$wci_m_2_MAddr<17>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop$wci_m_2_MAddr<16>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop$wci_m_2_MAddr<15>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop$wci_m_2_MAddr<14>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop$wci_m_2_MAddr<13>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop$wci_m_2_MAddr<12>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop$wci_m_2_MAddr<11>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop$wci_m_2_MAddr<10>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop$wci_m_4_MByteEn<1>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop$wci_m_4_MByteEn<0>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop$wci_m_4_MAddr<31>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop$wci_m_4_MAddr<30>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop$wci_m_4_MAddr<29>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop$wci_m_4_MAddr<28>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop$wci_m_4_MAddr<27>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop$wci_m_4_MAddr<26>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop$wci_m_4_MAddr<25>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop$wci_m_4_MAddr<24>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop$wci_m_4_MAddr<23>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop$wci_m_4_MAddr<22>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop$wmemiM0_MAddr<35>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop$wmemiM0_MAddr<34>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop$wmemiM0_MAddr<33>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop$wmemiM0_MAddr<32>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop$wmemiM0_MAddr<31>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/ctop$wmemiM0_MAddr<30>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/dram0$wmemiS0_SRespLast' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_status<15>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_status<14>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_status<13>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_status<12>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_status<11>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_status<10>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_status<9>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_status<8>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_status<7>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_status<6>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_status<5>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_status<4>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_status<3>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_status<2>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_status<1>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_status<0>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_command<15>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_command<14>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_command<13>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_command<12>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_command<11>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_command<9>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_command<7>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_command<6>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_command<5>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_command<4>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_command<3>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_dstatus<15>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_dstatus<14>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_dstatus<13>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_dstatus<12>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_dstatus<11>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_dstatus<10>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_dstatus<9>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_dstatus<8>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_dstatus<7>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_dstatus<6>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_dstatus<5>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_dstatus<4>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_dcommand<15>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_lstatus<12>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_lstatus<10>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_lstatus<9>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_lstatus<8>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_lstatus<3>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_lstatus<2>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_lcommand<15>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_lcommand<14>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_lcommand<13>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_lcommand<12>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_lcommand<2>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_dcommand2<15>' + has no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_dcommand2<14>' + has no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_dcommand2<13>' + has no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_dcommand2<12>' + has no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_dcommand2<11>' + has no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_dcommand2<10>' + has no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_dcommand2<9>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_dcommand2<8>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_dcommand2<7>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_dcommand2<6>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_dcommand2<5>' has + no driver +WARNING:NgdBuild:452 - logical net 'ftop/pciw_pci0_pcie_ep/cfg_to_turnoff_n' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX4CHARISKGT<1>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX4CHARISKGT<0>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX4DATAGT<15>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX4DATAGT<14>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX4DATAGT<13>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX4DATAGT<12>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX4DATAGT<11>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX4DATAGT<10>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX4DATAGT<9>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX4DATAGT<8>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX4DATAGT<7>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX4DATAGT<6>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX4DATAGT<5>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX4DATAGT<4>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX4DATAGT<3>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX4DATAGT<2>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX4DATAGT<1>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX4DATAGT<0>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX4STATUSGT<2>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX4STATUSGT<1>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX4STATUSGT<0>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX5CHARISKGT<1>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX5CHARISKGT<0>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX5DATAGT<15>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX5DATAGT<14>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX5DATAGT<13>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX5DATAGT<12>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX5DATAGT<11>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX5DATAGT<10>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX5DATAGT<9>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX5DATAGT<8>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX5DATAGT<7>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX5DATAGT<6>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX5DATAGT<5>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX5DATAGT<4>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX5DATAGT<3>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX5DATAGT<2>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX5DATAGT<1>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX5DATAGT<0>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX5STATUSGT<2>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX5STATUSGT<1>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX5STATUSGT<0>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX6CHARISKGT<1>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX6CHARISKGT<0>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX6DATAGT<15>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX6DATAGT<14>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX6DATAGT<13>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX6DATAGT<12>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX6DATAGT<11>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX6DATAGT<10>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX6DATAGT<9>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX6DATAGT<8>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX6DATAGT<7>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX6DATAGT<6>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX6DATAGT<5>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX6DATAGT<4>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX6DATAGT<3>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX6DATAGT<2>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX6DATAGT<1>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX6DATAGT<0>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX6STATUSGT<2>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX6STATUSGT<1>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX6STATUSGT<0>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX7CHARISKGT<1>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX7CHARISKGT<0>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX7DATAGT<15>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX7DATAGT<14>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX7DATAGT<13>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX7DATAGT<12>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX7DATAGT<11>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX7DATAGT<10>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX7DATAGT<9>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX7DATAGT<8>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX7DATAGT<7>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX7DATAGT<6>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX7DATAGT<5>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX7DATAGT<4>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX7DATAGT<3>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX7DATAGT<2>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX7DATAGT<1>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX7DATAGT<0>' has no driver +WARNING:NgdBuild:452 - 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logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/rd_data_addr<0>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/bank_mach_next<1>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/bank_mach_next<0>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/ecc_multiple<3>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/ecc_multiple<2>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/ecc_multiple<1>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/ecc_multiple<0>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/dram0/memc_memc/u_memc_ui_top/pd_PSEN' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/pd_PSINCDEC' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/dbg_wrlvl_err' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/rd_buf_full' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/hi_priority' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/data_buf_addr<7>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/data_buf_addr<6>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/data_buf_addr<5>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/data_buf_addr<4>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/io_config<0>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dfi_address1<11>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/wr_data_addr<7>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/wr_data_addr<6>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/wr_data_addr<5>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/wr_data_addr<4>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/rd_data_addr<7>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/rd_data_addr<6>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/rd_data_addr<5>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/rd_data_addr<4>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/ecc_single<3>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/ecc_single<2>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/ecc_single<1>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/ecc_single<0>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dfi_dram_clk_disable' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dfi_reset_n' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dfi_cas_n1' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<255>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<254>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<253>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<252>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<251>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<250>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<249>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<248>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<247>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<246>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<245>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<244>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<243>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<242>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<241>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<240>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<239>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<238>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<237>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<236>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<235>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<234>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<233>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<232>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<231>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<230>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<229>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<228>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<227>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<226>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<225>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<224>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<223>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<222>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<221>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<220>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<219>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<218>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<217>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<216>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<215>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<214>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<213>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<212>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<211>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<210>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<209>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<208>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<207>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<206>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<205>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<204>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<203>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<202>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<201>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<200>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<199>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<198>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<197>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<196>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<195>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<194>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<193>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<192>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<191>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<190>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<189>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<188>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<187>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<186>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<185>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<184>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<183>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<182>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<181>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<180>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<179>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<178>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<177>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<176>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<175>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<174>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<173>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<172>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<171>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<170>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<169>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<168>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<167>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<166>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<165>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<164>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<163>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<162>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<161>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<160>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<159>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<158>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<157>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<156>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<155>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<154>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<153>' has no + driver +WARNING:NgdBuild:452 - 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logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<143>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<142>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<141>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<140>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<139>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<138>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<137>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<136>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<135>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<134>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<133>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<132>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<131>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<130>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<129>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<128>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<127>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<126>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<125>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<124>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<123>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<122>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<121>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<120>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<119>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<118>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<117>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<116>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<115>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<114>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<113>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<112>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<111>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<110>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<109>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<108>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<107>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<103>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<101>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<21>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<20>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<19>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<18>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<13>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<9>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<4>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<255>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<254>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<253>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<252>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<251>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<250>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<249>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<248>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<247>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<246>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<245>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<244>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<243>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<242>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<241>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<240>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<239>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<238>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<237>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<236>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<235>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<234>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<233>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<232>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<231>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<230>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<229>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<228>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<227>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<226>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<225>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<224>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<223>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<222>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<221>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<220>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<219>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<218>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<217>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<216>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<215>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<214>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<213>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<212>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<211>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<210>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<209>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<208>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<207>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<206>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<205>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<204>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<203>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<202>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<201>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<200>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<199>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<198>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<197>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<196>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<195>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<194>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<193>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<192>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<191>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<190>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<189>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<188>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<187>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<186>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<185>' has no + driver +WARNING:NgdBuild:452 - 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logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<175>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<174>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<173>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<172>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<171>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<170>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<169>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<168>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<167>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<166>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<165>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<164>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<163>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<162>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<161>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<160>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<159>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<158>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<157>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<156>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<155>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<154>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<153>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<152>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<151>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<150>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<149>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<148>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<147>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<146>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<145>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<144>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<143>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<142>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<141>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<140>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<139>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<138>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<137>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<136>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<135>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<134>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<133>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<132>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<131>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<130>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<129>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<128>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<127>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<126>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<125>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<124>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<123>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<122>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<121>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<120>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<119>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<118>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<117>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<116>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<115>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<114>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<113>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<112>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<111>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<110>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<109>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<108>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<107>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<106>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<105>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<104>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<103>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<102>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<101>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<100>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<99>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<98>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<97>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<96>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<95>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<94>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<93>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<92>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<91>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<90>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<89>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<88>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<87>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<86>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<85>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<84>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<83>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<82>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<81>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<80>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<79>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<78>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<77>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<76>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<75>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<74>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<73>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<72>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<71>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<70>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<69>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<68>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<67>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<66>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<65>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<64>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<63>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<62>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<61>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<60>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<59>' has no + driver +WARNING:NgdBuild:452 - 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logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<31>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<30>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<29>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<28>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<27>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<26>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<25>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<24>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<23>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<22>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<21>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<20>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<19>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<18>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<17>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<16>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<15>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<14>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<13>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<12>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<11>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<10>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<9>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<8>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<7>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<6>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<5>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<4>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<3>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<2>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<1>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_read<0>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_rdlvl<73>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_rdlvl<6>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_rdlvl<4>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<255>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<254>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<253>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<252>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<251>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<250>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<249>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<248>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<247>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<246>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<245>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<244>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<243>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<242>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<241>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<240>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<239>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<238>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<237>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<236>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<235>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<234>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<233>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<232>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<231>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<230>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<229>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<228>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<227>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<226>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<225>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<224>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<223>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<222>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<221>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<220>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<219>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<218>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<217>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<216>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<215>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<214>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<213>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<212>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<211>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<210>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<209>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<208>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<207>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<206>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<205>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<204>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<203>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<202>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<201>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<200>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<199>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<198>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<197>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<196>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<195>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<194>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<193>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<192>' has no + driver +WARNING:NgdBuild:452 - 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logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<146>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<145>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<144>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<143>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<142>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<141>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<140>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<139>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<138>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<137>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<136>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<135>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<134>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<133>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<132>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<131>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<130>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<129>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<128>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<127>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<126>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<125>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<124>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<123>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<122>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<121>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<120>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<119>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<118>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<117>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<116>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<115>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<114>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<113>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<112>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<111>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<110>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<109>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<108>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<107>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<106>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<105>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<104>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<103>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<102>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<101>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<100>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<99>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<98>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<97>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<96>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<95>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<94>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<93>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<92>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<91>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<90>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<89>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<88>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<87>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<86>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<85>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<84>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<83>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<82>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<81>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<80>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<79>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<78>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<77>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<76>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<75>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<74>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<73>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<72>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<71>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<70>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<69>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<68>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<67>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<66>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<65>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<64>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<63>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<62>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<61>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<60>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<59>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<58>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<57>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<56>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<55>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<54>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<53>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<52>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<51>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<50>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<49>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<48>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<47>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<46>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<45>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<44>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<43>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<42>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<41>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<40>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<39>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<38>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<37>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<36>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<35>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<34>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<33>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<32>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<31>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<30>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<29>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<28>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<27>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<26>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<25>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<24>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<23>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<22>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<21>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<20>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<19>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<18>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<17>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<16>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<15>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<14>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<13>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<12>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<11>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<10>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<9>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<8>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<7>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<6>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<5>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<4>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<3>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<2>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<1>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_top<0>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/slot_1_present<7>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/slot_1_present<6>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/slot_1_present<5>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/slot_1_present<4>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/slot_1_present<3>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/slot_1_present<2>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/slot_1_present<1>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/slot_1_present<0>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/slot_0_present<7>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/slot_0_present<6>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/slot_0_present<5>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/slot_0_present<4>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/slot_0_present<3>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/slot_0_present<2>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/slot_0_present<1>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/slot_0_present<0>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_wr_data_buf_addr<7>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_wr_data_buf_addr<6>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_wr_data_buf_addr<5>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_wr_data_buf_addr<4>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_row<12>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_row<11>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_row<10>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_row<9>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_row<8>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_row<7>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_row<6>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_row<5>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_row<4>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_row<3>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_row<2>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_row<1>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_row<0>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_ra' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_a<11>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/io_config_ns<0>' has no + driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_rmw' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/rank_mach0/rank_common0/m + aintenance_request.maint_grant_r<0>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/start_pre_wait + <0>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/op_exit_req<0> + ' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/end_rtp<0>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/demand_act_pri + ority<0>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/col_rdy_wr<0>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/start_pre_wait + <1>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/op_exit_req<1> + ' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/end_rtp<1>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/demand_act_pri + ority<1>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/col_rdy_wr<1>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/start_pre_wait + <2>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/op_exit_req<2> + ' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/end_rtp<2>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/demand_act_pri + ority<2>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/col_rdy_wr<2>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/start_pre_wait + <3>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/op_exit_req<3> + ' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/end_rtp<3>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/demand_act_pri + ority<3>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/col_rdy_wr<3>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/op_exit_grant< + 0>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/op_exit_grant< + 1>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/op_exit_grant< + 2>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/op_exit_grant< + 3>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/low_idle_cnt_r + ' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/was_priority' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[0]. + bank0/rd_half_rmw' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[0]. + bank0/rb_hit_busies_r<7>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[0]. + bank0/rb_hit_busies_r<6>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[0]. + bank0/rb_hit_busies_r<5>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[0]. + bank0/rb_hit_busies_r<4>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[0]. + bank0/rb_hit_busies_r<0>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[0]. + bank0/q_has_priority' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[1]. + bank0/rd_half_rmw' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[1]. + bank0/rb_hit_busies_r<7>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[1]. + bank0/rb_hit_busies_r<6>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[1]. + bank0/rb_hit_busies_r<5>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[1]. + bank0/rb_hit_busies_r<1>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[1]. + bank0/rb_hit_busies_r<0>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[1]. + bank0/q_has_priority' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[2]. + bank0/rd_half_rmw' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[2]. + bank0/rb_hit_busies_r<7>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[2]. + bank0/rb_hit_busies_r<6>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[2]. + bank0/rb_hit_busies_r<2>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[2]. + bank0/rb_hit_busies_r<1>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[2]. + bank0/rb_hit_busies_r<0>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[2]. + bank0/q_has_priority' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[3]. + bank0/rd_half_rmw' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[3]. + bank0/rb_hit_busies_r<7>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[3]. + bank0/rb_hit_busies_r<3>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[3]. + bank0/rb_hit_busies_r<2>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[3]. + bank0/rb_hit_busies_r<1>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[3]. + bank0/rb_hit_busies_r<0>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[3]. + bank0/q_has_priority' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/arb_mux0/grant + _col_wr<3>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/arb_mux0/grant + _col_wr<2>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/arb_mux0/grant + _col_wr<1>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/arb_mux0/grant + _col_wr<0>' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/arb_mux0/send_ + cmd0_col' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/arb_mux0/send_ + cmd1_row' has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyce_rsync<3>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyce_rsync<2>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dfi_rd_dqs<7>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dfi_rd_dqs<6>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dfi_rd_dqs<5>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dfi_rd_dqs<4>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dfi_rd_dqs<3>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dfi_rd_dqs<2>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dfi_rd_dqs<1>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dfi_rd_dqs<15>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dfi_rd_dqs<14>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dfi_rd_dqs<13>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dfi_rd_dqs<12>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dfi_rd_dqs<11>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dfi_rd_dqs<10>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dfi_rd_dqs<9>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dfi_rd_dqs<23>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dfi_rd_dqs<22>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dfi_rd_dqs<21>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dfi_rd_dqs<20>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dfi_rd_dqs<19>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dfi_rd_dqs<18>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dfi_rd_dqs<17>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dfi_rd_dqs<31>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dfi_rd_dqs<30>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dfi_rd_dqs<29>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dfi_rd_dqs<28>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dfi_rd_dqs<27>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dfi_rd_dqs<26>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dfi_rd_dqs<25>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyce_pd_cpt<7>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyce_pd_cpt<6>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyce_pd_cpt<5>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyce_pd_cpt<4>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyce_pd_cpt<3>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyce_pd_cpt<2>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyce_pd_cpt<1>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyce_pd_cpt<0>' has + no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyinc_pd_cpt<7>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyinc_pd_cpt<6>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyinc_pd_cpt<5>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyinc_pd_cpt<4>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyinc_pd_cpt<3>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyinc_pd_cpt<2>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyinc_pd_cpt<1>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<39>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<38>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<37>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<36>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<35>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<34>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<33>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<32>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<31>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<30>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<29>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<28>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<27>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<26>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<25>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<24>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<23>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<22>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<21>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<20>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<19>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<18>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<17>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<16>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<15>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<14>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<13>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<12>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<11>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<10>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<9>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<8>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<7>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<6>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dlyval_pd_dqs<5>' + has no driver +WARNING:NgdBuild:452 - logical net + 'ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/pd_prech_req' has no + driver + +Partition Implementation Status +------------------------------- + + No Partitions were found in this design. + +------------------------------- + +NGDBUILD Design Results Summary: + Number of errors: 0 + Number of warnings: 2523 + +Total memory usage is 820892 kilobytes + +Writing NGD file "fpgaTop.ngd" ... +Total REAL time to NGDBUILD completion: 45 sec +Total CPU time to NGDBUILD completion: 45 sec + +Writing NGDBUILD log file "fpgaTop.bld"... diff --git a/logs/ml605-20130127_1122/fpgaTop.par b/logs/ml605-20130127_1122/fpgaTop.par new file mode 100644 index 00000000..8b79a524 --- /dev/null +++ b/logs/ml605-20130127_1122/fpgaTop.par @@ -0,0 +1,1214 @@ +Release 14.4 par P.49d (lin64) +Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. + +ar-cms520:: Sun Jan 27 11:07:36 2013 + +par -w -xe n fpgaTop_map.ncd fpgaTop.ncd fpgaTop.pcf + + +Constraints file: fpgaTop.pcf. +Loading device for application Rf_Device from file '6vlx240t.nph' in environment /opt/Xilinx/14.4/ISE_DS/ISE/. + "fpgaTop" is an NCD, version 3.2, device xc6vlx240t, package ff1156, speed -1 + +Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius) +Initializing voltage to 0.950 Volts. (default - Range: 0.950 to 1.050 Volts) + + +Device speed data version: "PRODUCTION 1.17 2012-12-04". + + + +Device Utilization Summary: + +Slice Logic Utilization: + Number of Slice Registers: 32,742 out of 301,440 10% + Number used as Flip Flops: 32,735 + Number used as Latches: 2 + Number used as Latch-thrus: 0 + Number used as AND/OR logics: 5 + Number of Slice LUTs: 41,259 out of 150,720 27% + Number used as logic: 35,513 out of 150,720 23% + Number using O6 output only: 32,112 + Number using O5 output only: 2,230 + Number using O5 and O6: 1,171 + Number used as ROM: 0 + Number used as Memory: 5,075 out of 58,400 8% + Number used as Dual Port RAM: 2,098 + Number using O6 output only: 106 + Number using O5 output only: 53 + Number using O5 and O6: 1,939 + Number used as Single Port RAM: 0 + Number used as Shift Register: 2,977 + Number using O6 output only: 2,977 + Number using O5 output only: 0 + Number using O5 and O6: 0 + Number used exclusively as route-thrus: 671 + Number with same-slice register load: 547 + Number with same-slice carry load: 122 + Number with other load: 2 + +Slice Logic Distribution: + Number of occupied Slices: 16,343 out of 37,680 43% + Number of LUT Flip Flop pairs used: 48,814 + Number with an unused Flip Flop: 16,997 out of 48,814 34% + Number with an unused LUT: 7,555 out of 48,814 15% + Number of fully used LUT-FF pairs: 24,262 out of 48,814 49% + Number of slice register sites lost + to control set restrictions: 0 out of 301,440 0% + + A LUT Flip Flop pair for this architecture represents one LUT paired with + one Flip Flop within a slice. A control set is a unique combination of + clock, reset, set, and enable signals for a registered element. + The Slice Logic Distribution report is not meaningful if the design is + over-mapped for a non-slice resource or if Placement fails. + OVERMAPPING of BRAM resources should be ignored if the design is + over-mapped for a non-BRAM resource or if placement fails. + +IO Utilization: + Number of bonded IOBs: 218 out of 600 36% + Number of LOCed IOBs: 218 out of 218 100% + IOB Flip Flops: 12 + IOB Master Pads: 9 + IOB Slave Pads: 9 + Number of bonded IPADs: 12 + Number of LOCed IPADs: 4 out of 12 33% + Number of bonded OPADs: 8 + +Specific Feature Utilization: + Number of RAMB36E1/FIFO36E1s: 38 out of 416 9% + Number using RAMB36E1 only: 38 + Number using FIFO36E1 only: 0 + Number of RAMB18E1/FIFO18E1s: 3 out of 832 1% + Number using RAMB18E1 only: 3 + Number using FIFO18E1 only: 0 + Number of BUFG/BUFGCTRLs: 12 out of 32 37% + Number used as BUFGs: 11 + Number used as BUFGCTRLs: 1 + Number of ILOGICE1/ISERDESE1s: 65 out of 720 9% + Number used as ILOGICE1s: 0 + Number used as ISERDESE1s: 65 + Number of OLOGICE1/OSERDESE1s: 138 out of 720 19% + Number used as OLOGICE1s: 17 + Number used as OSERDESE1s: 121 + Number of BSCANs: 0 out of 4 0% + Number of BUFHCEs: 0 out of 144 0% + Number of BUFIODQSs: 8 out of 72 11% + Number of BUFRs: 3 out of 36 8% + Number of LOCed BUFRs: 2 out of 3 66% + Number of CAPTUREs: 0 out of 1 0% + Number of DSP48E1s: 0 out of 768 0% + Number of EFUSE_USRs: 0 out of 1 0% + Number of FRAME_ECCs: 0 out of 1 0% + Number of GTXE1s: 4 out of 20 20% + Number of LOCed GTXE1s: 4 out of 4 100% + Number of IBUFDS_GTXE1s: 2 out of 12 16% + Number of LOCed IBUFDS_GTXE1s: 1 out of 2 50% + Number of ICAPs: 0 out of 2 0% + Number of IDELAYCTRLs: 4 out of 18 22% + Number of IODELAYE1s: 91 out of 720 12% + Number of LOCed IODELAYE1s: 10 out of 91 10% + Number of MMCM_ADVs: 2 out of 12 16% + Number of PCIE_2_0s: 1 out of 2 50% + Number of LOCed PCIE_2_0s: 1 out of 1 100% + Number of STARTUPs: 1 out of 1 100% + Number of SYSMONs: 0 out of 1 0% + Number of TEMAC_SINGLEs: 0 out of 4 0% + + +Overall effort level (-ol): Standard +Router effort level (-rl): High + +WARNING:Timing:3175 - gmii_gtx_clk does not clock data to gmii_txd<7> +WARNING:Timing:3225 - Timing constraint COMP "gmii_txd<7>" OFFSET = OUT 6 ns AFTER COMP "gmii_gtx_clk"; ignored during timing analysis +WARNING:Timing:3175 - gmii_gtx_clk does not clock data to gmii_txd<6> +WARNING:Timing:3225 - Timing constraint COMP "gmii_txd<6>" OFFSET = OUT 6 ns AFTER COMP "gmii_gtx_clk"; ignored during timing analysis +WARNING:Timing:3175 - gmii_gtx_clk does not clock data to gmii_txd<5> +WARNING:Timing:3225 - Timing constraint COMP "gmii_txd<5>" OFFSET = OUT 6 ns AFTER COMP "gmii_gtx_clk"; ignored during timing analysis +WARNING:Timing:3175 - gmii_gtx_clk does not clock data to gmii_txd<4> +WARNING:Timing:3225 - Timing constraint COMP "gmii_txd<4>" OFFSET = OUT 6 ns AFTER COMP "gmii_gtx_clk"; ignored during timing analysis +WARNING:Timing:3175 - gmii_gtx_clk does not clock data to gmii_txd<3> +WARNING:Timing:3225 - Timing constraint COMP "gmii_txd<3>" OFFSET = OUT 6 ns AFTER COMP "gmii_gtx_clk"; ignored during timing analysis +WARNING:Timing:3175 - gmii_gtx_clk does not clock data to gmii_txd<2> +WARNING:Timing:3225 - Timing constraint COMP "gmii_txd<2>" OFFSET = OUT 6 ns AFTER COMP "gmii_gtx_clk"; ignored during timing analysis +WARNING:Timing:3175 - gmii_gtx_clk does not clock data to gmii_txd<1> +WARNING:Timing:3225 - Timing constraint COMP "gmii_txd<1>" OFFSET = OUT 6 ns AFTER COMP "gmii_gtx_clk"; ignored during timing analysis +WARNING:Timing:3175 - gmii_gtx_clk does not clock data to gmii_txd<0> +WARNING:Timing:3225 - Timing constraint COMP "gmii_txd<0>" OFFSET = OUT 6 ns AFTER COMP "gmii_gtx_clk"; ignored during timing analysis +WARNING:Timing:3175 - gmii_gtx_clk does not clock data to gmii_tx_en +WARNING:Timing:3225 - Timing constraint COMP "gmii_tx_en" OFFSET = OUT 6 ns AFTER COMP "gmii_gtx_clk"; ignored during timing analysis +WARNING:Timing:3175 - gmii_gtx_clk does not clock data to gmii_tx_er +WARNING:Timing:3225 - Timing constraint COMP "gmii_tx_er" OFFSET = OUT 6 ns AFTER COMP "gmii_gtx_clk"; ignored during timing analysis +Starting initial Timing Analysis. REAL time: 39 secs +Finished initial Timing Analysis. REAL time: 40 secs + +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/bram_1_memory$DOB<11> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/bram_1_memory$DOB<9> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[0].u_phy_dqs_iob/u_iobuf_dqs/OB + has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1].u_phy_dqs_iob/u_iobuf_dqs/OB + has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2].u_phy_dqs_iob/u_iobuf_dqs/OB + has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3].u_phy_dqs_iob/u_iobuf_dqs/OB + has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4].u_phy_dqs_iob/u_iobuf_dqs/OB + has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5].u_phy_dqs_iob/u_iobuf_dqs/OB + has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6].u_phy_dqs_iob/u_iobuf_dqs/OB + has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7].u_phy_dqs_iob/u_iobuf_dqs/OB + has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/wmi_wmi_reqF/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/wmi_wmi_reqF/Mram_arr3_RAMA_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/wmi_wmi_reqF/Mram_arr3_RAMB_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/wmi_wmi_reqF/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_1_serverAdapterB_outDataCore/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_1_serverAdapterA_outDataCore/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_1_serverAdapterA_outDataCore/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_1_serverAdapterA_outDataCore/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_1_serverAdapterA_outDataCore/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_0_serverAdapterA_outDataCore/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/cp/timeServ_setRefF/Mram_fifoMem1_RAMD_D1_O has no load. PAR will not attempt to route this + signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/wmi_wmi_reqF/Mram_arr2_RAMC_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/wmi_wmi_reqF/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/wmi_wmi_reqF/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/wmi_wmi_reqF/Mram_arr5_RAMB_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/wmi_wmi_reqF/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_1_serverAdapterB_outDataCore/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_1_serverAdapterB_outDataCore/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_1_serverAdapterB_outDataCore/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/wmi_wmi_mFlagF/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/wmi_wmi_mFlagF/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_1_serverAdapterA_outDataCore/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_0_serverAdapterA_outDataCore/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_0_serverAdapterA_outDataCore/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_0_serverAdapterA_outDataCore/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_0_serverAdapterA_outDataCore/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_1_serverAdapterB_outDataCore/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/wmi_wmi_mFlagF/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/wmi_wmi_mFlagF/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/wmi_wmi_mFlagF/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_3_serverAdapterA_outDataCore/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_3_serverAdapterA_outDataCore/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_3_serverAdapterA_outDataCore/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_3_serverAdapterB_outDataCore/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_3_serverAdapterA_outDataCore/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_3_serverAdapterA_outDataCore/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_0_serverAdapterB_outDataCore/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_3_serverAdapterB_outDataCore/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_3_serverAdapterB_outDataCore/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wsiS_reqFifo/Mram_arr10_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wsiS_reqFifo/Mram_arr11_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_3_serverAdapterB_outDataCore/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_3_serverAdapterB_outDataCore/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_0_serverAdapterB_outDataCore/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_2_serverAdapterA_outDataCore/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_2_serverAdapterA_outDataCore/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_2_serverAdapterA_outDataCore/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_0_serverAdapterB_outDataCore/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_2_serverAdapterA_outDataCore/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_2_serverAdapterA_outDataCore/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wsiS_reqFifo/Mram_arr9_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wsiS_reqFifo/Mram_arr13_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wsiS_reqFifo/Mram_arr12_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wsiS_reqFifo/Mram_arr14_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/cp/timeServ_setRefF/Mram_fifoMem2_RAMD_D1_O has no load. PAR will not attempt to route this + signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_0_serverAdapterB_outDataCore/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_0_serverAdapterB_outDataCore/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/cp/timeServ_setRefF/Mram_fifoMem3_RAMD_D1_O has no load. PAR will not attempt to route this + signal. +WARNING:Par:288 - The signal ftop/ctop/inf/cp/timeServ_setRefF/Mram_fifoMem4_RAMD_D1_O has no load. PAR will not attempt to route this + signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wsiS_reqFifo/Mram_arr21_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wsiS_reqFifo/Mram_arr22_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_2_serverAdapterB_outDataCore/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wsiS_reqFifo/Mram_arr8_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wsiS_reqFifo/Mram_arr24_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wsiS_reqFifo/Mram_arr23_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_2_serverAdapterB_outDataCore/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_2_serverAdapterB_outDataCore/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_2_serverAdapterB_outDataCore/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/bram_2_serverAdapterB_outDataCore/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wsiS_reqFifo/Mram_arr26_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wsiS_reqFifo/Mram_arr7_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wsiS_reqFifo/Mram_arr17_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wsiS_reqFifo/Mram_arr15_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wsiS_reqFifo/Mram_arr16_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wsiS_reqFifo/Mram_arr20_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/cp/timeServ_setRefF/Mram_fifoMem5_RAMD_D1_O has no load. PAR will not attempt to route this + signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_dhF/Mram_arr19_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_dhF/Mram_arr20_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_dhF/Mram_arr14_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wsiS_reqFifo/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wsiS_reqFifo/Mram_arr25_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_dhF/Mram_arr16_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3$wsiM0_MBurstLength<3> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3$wsiM0_MBurstLength<1> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wsiS_reqFifo/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wsiS_reqFifo/Mram_arr18_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wsiS_reqFifo/Mram_arr19_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wsiS_reqFifo/Mram_arr28_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/wci_reqF/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/wci_reqF/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wsiS_reqFifo/Mram_arr20_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wsiS_reqFifo/Mram_arr11_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wsiS_reqFifo/Mram_arr14_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3$wsiM0_MBurstLength<11> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wsiS_reqFifo/Mram_arr6_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wsiS_reqFifo/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/wci_reqF/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/wci_reqF/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wsiS_reqFifo/Mram_arr22_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/wci_reqF/Mram_arr6_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wsiS_reqFifo/Mram_arr21_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wsiS_reqFifo/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wsiS_reqFifo/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/wci_reqF/Mram_arr7_RAMC_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/wci_reqF/Mram_arr7_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/wci_reqF/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wsiS_reqFifo/Mram_arr10_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wsiS_reqFifo/Mram_arr16_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wsiS_reqFifo/Mram_arr12_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wsiS_reqFifo/Mram_arr15_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_dhF/Mram_arr21_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_dhF/Mram_arr15_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/cp/timeServ_setRefF/Mram_fifoMem6_RAMD_D1_O has no load. PAR will not attempt to route this + signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wsiS_reqFifo/Mram_arr7_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wsiS_reqFifo/Mram_arr6_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wsiS_reqFifo/Mram_arr17_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wsiS_reqFifo/Mram_arr26_RAMB_D1_DPO has no load. PAR will not attempt to route this + signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wsiS_reqFifo/Mram_arr26_RAMC_D1_DPO has no load. PAR will not attempt to route this + signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wsiS_reqFifo/Mram_arr26_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wsiS_reqFifo/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wsiS_reqFifo/Mram_arr19_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wsiS_reqFifo/Mram_arr13_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wsiS_reqFifo/Mram_arr24_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wsiS_reqFifo/Mram_arr23_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_dhF/Mram_arr22_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/bram_2_serverAdapterA_outDataCore/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/bram_2_serverAdapterA_outDataCore/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wci_wslv_reqF/Mram_arr6_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/cp/timeServ_setRefF/Mram_fifoMem10_RAMD_D1_O has no load. PAR will not attempt to route this + signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/wci_reqF/Mram_arr12_RAMA_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp0/wci_reqF/Mram_arr12_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wsiS_reqFifo/Mram_arr8_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wsiS_reqFifo/Mram_arr9_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wsiS_reqFifo/Mram_arr18_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wsiS_reqFifo/Mram_arr25_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_dhF/Mram_arr17_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/bram_2_serverAdapterA_outDataCore/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/cp$wci_Vm_13_MAddr<9> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wci_reqF/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_dhF/Mram_arr18_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/bram_2_serverAdapterA_outDataCore/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW2/wci_wslv_reqF/Mram_arr7_RAMC_D1_DPO has no load. PAR will not attempt to route this + signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW2/wci_wslv_reqF/Mram_arr7_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW2/wci_wslv_reqF/Mram_arr12_RAMA_D1_DPO has no load. PAR will not attempt to route this + signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW2/wci_wslv_reqF/Mram_arr12_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW2/wci_wslv_reqF/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wci_wslv_reqF/Mram_arr7_RAMC_D1_DPO has no load. PAR will not attempt to route this + signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wci_wslv_reqF/Mram_arr7_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wci_wslv_reqF/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wci_wslv_reqF/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/cp/timeServ_setRefF/Mram_fifoMem7_RAMD_D1_O has no load. PAR will not attempt to route this + signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wci_reqF/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wci_reqF/Mram_arr7_RAMC_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wci_reqF/Mram_arr7_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/bram_2_serverAdapterA_outDataCore/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW2/wci_wslv_reqF/Mram_arr6_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW2/wci_wslv_reqF/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW2/wci_wslv_reqF/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/fmc150/wci_wslv_reqF/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/fmc150/wci_wslv_reqF/Mram_arr12_RAMA_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/fmc150/wci_wslv_reqF/Mram_arr12_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wci_wslv_reqF/Mram_arr12_RAMA_D1_DPO has no load. PAR will not attempt to route this + signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wci_wslv_reqF/Mram_arr12_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wci_wslv_reqF/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wci_wslv_reqF/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW1/wci_wslv_reqF/Mram_arr10_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW1/wci_wslv_reqF/Mram_arr9_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW1/wci_wslv_reqF/Mram_arr8_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/cp/timeServ_setRefF/Mram_fifoMem8_RAMD_D1_O has no load. PAR will not attempt to route this + signal. +WARNING:Par:288 - The signal ftop/ctop/inf/cp/timeServ_setRefF/Mram_fifoMem9_RAMD_D1_O has no load. PAR will not attempt to route this + signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wsiS_reqFifo/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wsiS_reqFifo/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wsiS_reqFifo/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lrespF/Mram_fifoMem6_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wsiS_reqFifo/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wci_reqF/Mram_arr6_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_dhF/Mram_arr13_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_dhF/Mram_arr10_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_dhF/Mram_arr11_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/bram_3_serverAdapterA_outDataCore/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW2/wci_wslv_reqF/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW2/wci_wslv_reqF/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/fmc150/wci_wslv_reqF/Mram_arr6_RAMA_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/fmc150/wci_wslv_reqF/Mram_arr6_RAMB_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/fmc150/wci_wslv_reqF/Mram_arr6_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/fmc150/wci_wslv_reqF/Mram_arr7_RAMC_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/fmc150/wci_wslv_reqF/Mram_arr7_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/fmc150/wci_wslv_reqF/Mram_arr8_RAMB_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/fmc150/wci_wslv_reqF/Mram_arr8_RAMC_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/fmc150/wci_wslv_reqF/Mram_arr8_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW3/wci_wslv_reqF/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW1/wci_wslv_reqF/Mram_arr7_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW1/wci_wslv_reqF/Mram_arr6_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lrespF/Mram_fifoMem21_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lrespF/Mram_fifoMem11_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lrespF/Mram_fifoMem5_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lrespF/Mram_fifoMem19_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lrespF/Mram_fifoMem18_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lrespF/Mram_fifoMem17_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wci_reqF/Mram_arr12_RAMA_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wci_reqF/Mram_arr12_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wci_reqF/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_dhF/Mram_arr3_RAMA_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_dhF/Mram_arr3_RAMB_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_dhF/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_dhF/Mram_arr23_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_dhF/Mram_arr9_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/bram_3_serverAdapterA_outDataCore/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/bram_3_serverAdapterA_outDataCore/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/app$wmiM1_MDataByteEn<13> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app$wmiM1_MDataByteEn<15> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/fmc150/wci_wslv_reqF/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/fmc150/wci_wslv_reqF/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/fmc150/wci_wslv_reqF/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/fmc150/wci_wslv_reqF/Mram_arr5_RAMC_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/fmc150/wci_wslv_reqF/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf$wci_m_3_MAddr<9> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW1/wci_wslv_reqF/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lrespF/Mram_fifoMem15_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lrespF/Mram_fifoMem14_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lrespF/Mram_fifoMem10_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wsiS_reqFifo/Mram_arr28_RAMA_D1_DPO has no load. PAR will not attempt to route this + signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wsiS_reqFifo/Mram_arr28_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lrespF/Mram_fifoMem16_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lrespF/Mram_fifoMem9_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lrespF/Mram_fifoMem20_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lrespF/Mram_fifoMem8_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wci_reqF/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_dhF/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_dhF/Mram_arr6_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_dhF/Mram_arr24_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/bram_3_serverAdapterA_outDataCore/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/bram_1_serverAdapterA_outDataCore/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW1/wci_wslv_reqF/Mram_arr11_RAMC_D1_DPO has no load. PAR will not attempt to route this + signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW1/wci_wslv_reqF/Mram_arr11_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW1/wci_wslv_reqF/Mram_arr12_RAMA_D1_DPO has no load. PAR will not attempt to route this + signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW1/wci_wslv_reqF/Mram_arr12_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW1/wci_wslv_reqF/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW1/wci_wslv_reqF/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lrespF/Mram_fifoMem12_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lrespF/Mram_fifoMem4_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lrespF/Mram_fifoMem3_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lrespF/Mram_fifoMem7_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wci_reqF/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_dhF/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/bram_3_serverAdapterA_outDataCore/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop$wci_m_0_MAddr<1> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/cp$wci_Vm_14_MAddr<9> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/cp$wci_Vm_14_MByteEn<3> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop$wci_m_0_MData<29> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop$wci_m_0_MData<31> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf$wci_m_3_MByteEn<3> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop$wci_m_0_MAddr<13> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop$wci_m_0_MAddr<7> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop$wci_m_0_MAddr<9> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf$wci_m_2_MAddr<9> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/cp$wci_Vm_13_MByteEn<3> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop$wci_m_0_MByteEn<3> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW1/wci_wslv_reqF/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW1/wci_wslv_reqF/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF/Mram_fifoMem10_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lrespF/Mram_fifoMem1_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lrespF/Mram_fifoMem13_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lrespF/Mram_fifoMem2_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[40].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[29].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[7].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_mFlagF/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_dhF/Mram_arr12_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_reqF/Mram_arr3_RAMA_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_reqF/Mram_arr3_RAMB_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_reqF/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_reqF/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_reqF/Mram_arr5_RAMB_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_reqF/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/bram_1_serverAdapterA_outDataCore/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/bram_1_serverAdapterA_outDataCore/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/bram_1_serverAdapterA_outDataCore/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/bram_1_serverAdapterA_outDataCore/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf$wci_m_1_MByteEn<1> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop$wci_m_0_MAddr<15> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/flash0/wci_wslv_reqF/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF/Mram_fifoMem19_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF/Mram_fifoMem9_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF/Mram_fifoMem20_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF/Mram_fifoMem21_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF/Mram_fifoMem15_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF/Mram_fifoMem16_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[41].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[30].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[19].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[9].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[8].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[18].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[39].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[28].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[6].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[26].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_dhF/Mram_arr8_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_mFlagF/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_mFlagF/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_mFlagF/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_reqF/Mram_arr2_RAMC_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_reqF/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/bram_0_serverAdapterA_outDataCore/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/flash0/wci_wslv_reqF/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/flash0/wci_wslv_reqF/Mram_arr6_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/flash0/wci_wslv_reqF/Mram_arr12_RAMA_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/flash0/wci_wslv_reqF/Mram_arr12_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF/Mram_fifoMem18_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF/Mram_fifoMem17_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF/Mram_fifoMem5_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[20].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[17].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[38].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[36].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[37].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[15].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[5].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_reqF/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/bram_0_serverAdapterA_outDataCore/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/bram_0_serverAdapterA_outDataCore/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/bram_0_serverAdapterA_outDataCore/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf$wci_m_2_MByteEn<3> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf$wci_m_1_MByteEn<3> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/wci_wslv_reqF/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF/Mram_fifoMem29_RAMC_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF/Mram_fifoMem29_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF/Mram_fifoMem28_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF/Mram_fifoMem11_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF/Mram_fifoMem22_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[31].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[42].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[4].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app$wmiM1_MAddr<1> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[27].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[16].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_dhF/Mram_arr7_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/wmi_wmi_mFlagF/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/bram_0_serverAdapterA_outDataCore/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/app$wmiM1_MAddr<3> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/flash0/wci_wslv_reqF/Mram_arr7_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/flash0/wci_wslv_reqF/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop$wci_m_1_MAddr<21> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/wci_wslv_reqF/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF$sD_IN<173> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF/Mram_fifoMem8_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF/Mram_fifoMem1_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF/Mram_fifoMem7_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF/Mram_fifoMem6_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/cap0/dataBram_0_serverAdapterB_outDataCore/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to route + this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[10].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[45].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[46].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[44].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[47].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[43].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/read_fifo.fifo_ram[1].RAM32M0_RAMB_D1_DPO has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/read_fifo.fifo_ram[1].RAM32M0_RAMC_D1_DPO has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/read_fifo.fifo_ram[1].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/flash0/wci_wslv_reqF/Mram_arr9_RAMC_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/flash0/wci_wslv_reqF/Mram_arr9_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/wci_wslv_reqF/Mram_arr6_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/cap0/dataBram_0_serverAdapterB_outDataCore/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to route + this signal. +WARNING:Par:288 - The signal ftop/flash0/wci_wslv_reqF/Mram_arr8_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/wci_wslv_reqF/Mram_arr12_RAMA_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/wci_wslv_reqF/Mram_arr12_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/cap0/metaBram_1_serverAdapterB_outDataCore/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to route + this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/bram_0_serverAdapterB_outDataCore/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/bram_0_serverAdapterB_outDataCore/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/bram_1_serverAdapterB_outDataCore/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/bram_1_serverAdapterB_outDataCore/Mram_arr2_RAMB_D1_DPO has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/bram_1_serverAdapterB_outDataCore/Mram_arr2_RAMC_D1_DPO has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/bram_1_serverAdapterB_outDataCore/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop$wci_m_1_MByteEn<3> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop$wci_m_4_MAddr<21> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/flash0/wci_wslv_reqF/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop$wci_m_4_MByteEn<3> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/wci_wslv_reqF/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF/Mram_fifoMem24_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF/Mram_fifoMem23_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF/Mram_fifoMem25_RAMA_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF/Mram_fifoMem25_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF/Mram_fifoMem13_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF/Mram_fifoMem2_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF/Mram_fifoMem14_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF/Mram_fifoMem4_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/cap0/metaBram_1_serverAdapterB_outDataCore/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to route + this signal. +WARNING:Par:288 - The signal ftop/cap0/metaBram_0_serverAdapterB_outDataCore/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to route + this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/bram_0_serverAdapterB_outDataCore/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/flash0/wci_wslv_reqF/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/cp/rom_serverAdapter_outDataCore/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to route + this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/cp/rom_serverAdapter_outDataCore/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to route + this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/cp/rom_serverAdapter_outDataCore/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to route + this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF/Mram_fifoMem12_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF/Mram_fifoMem3_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/cap0/metaBram_3_serverAdapterB_outDataCore/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to route + this signal. +WARNING:Par:288 - The signal ftop/cap0/metaBram_0_serverAdapterB_outDataCore/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to route + this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/dp1/bram_0_serverAdapterB_outDataCore/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to + route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/cp/rom_serverAdapter_outDataCore/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to route + this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF/Mram_fifoMem26_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF/Mram_fifoMem27_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/cap0/metaBram_1_serverAdapterB_outDataCore/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to route + this signal. +WARNING:Par:288 - The signal ftop/cap0/dataBram_0_serverAdapterB_outDataCore/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to route + this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[21].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[0].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[32].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[11].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[14].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[25].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop$wci_m_2_MByteEn<3> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/lreqF$sD_IN<145> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/wci_wslv_reqF/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/wci_wslv_reqF/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/cap0/metaBram_1_serverAdapterB_outDataCore/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to route + this signal. +WARNING:Par:288 - The signal ftop/cap0/metaBram_3_serverAdapterB_outDataCore/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to route + this signal. +WARNING:Par:288 - The signal ftop/cap0/dataBram_0_serverAdapterB_outDataCore/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to route + this signal. +WARNING:Par:288 - The signal ftop/cap0/metaBram_0_serverAdapterB_outDataCore/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to route + this signal. +WARNING:Par:288 - The signal ftop/cap0/metaBram_0_serverAdapterB_outDataCore/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to route + this signal. +WARNING:Par:288 - The signal ftop/cap0/metaBram_2_serverAdapterB_outDataCore/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to route + this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[33].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[3].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf/cp/rom_serverAdapter_outDataCore/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to route + this signal. +WARNING:Par:288 - The signal ftop/cap0/dataBram_0_serverAdapterB_outDataCore/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to route + this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[22].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/cap0/metaBram_2_serverAdapterB_outDataCore/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to route + this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[35].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/wci_wslv_reqF/Mram_arr7_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/cap0/metaBram_1_serverAdapterB_outDataCore/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to route + this signal. +WARNING:Par:288 - The signal ftop/cap0/metaBram_3_serverAdapterB_outDataCore/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to route + this signal. +WARNING:Par:288 - The signal ftop/cap0/metaBram_0_serverAdapterB_outDataCore/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to route + this signal. +WARNING:Par:288 - The signal ftop/cap0/metaBram_2_serverAdapterB_outDataCore/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to route + this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[1].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[24].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop$wci_m_3_MByteEn<1> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/wci_wslv_reqF/Mram_arr9_RAMC_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/wci_wslv_reqF/Mram_arr9_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/cap0/metaBram_3_serverAdapterB_outDataCore/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to route + this signal. +WARNING:Par:288 - The signal ftop/cap0/metaBram_3_serverAdapterB_outDataCore/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to route + this signal. +WARNING:Par:288 - The signal ftop/cap0/metaBram_2_serverAdapterB_outDataCore/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to route + this signal. +WARNING:Par:288 - The signal ftop/ctop/inf$wci_m_4_MAddr<9> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/wci_wslv_reqF/Mram_arr8_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/cap0/metaBram_2_serverAdapterB_outDataCore/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to route + this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[13].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[34].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[12].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[2].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[23].RAM32M0_RAMD_D1_O has no + load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wci_wslv_reqF/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wci_wslv_reqF/Mram_arr12_RAMA_D1_DPO has no load. PAR will not attempt to route this + signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wci_wslv_reqF/Mram_arr12_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wci_wslv_reqF/Mram_arr7_RAMC_D1_DPO has no load. PAR will not attempt to route this + signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wci_wslv_reqF/Mram_arr7_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/gbe0/wci_wslv_reqF/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wci_wslv_reqF/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wci_wslv_reqF/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wci_wslv_reqF/Mram_arr6_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/cap0/wci_wslv_reqF/Mram_arr8_RAMC_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/cap0/wci_wslv_reqF/Mram_arr8_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/inf$wci_m_4_MByteEn<3> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop$wci_m_2_MAddr<9> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop$wci_m_3_MAddr<17> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop$wci_m_3_MAddr<19> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wci_wslv_reqF/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop/app/appW4/wci_wslv_reqF/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop$wci_m_3_MAddr<15> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/cap0/wci_wslv_reqF/Mram_arr7_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/pointer_ram.rams[0].RAM32M0_RAMA_D1_DPO has no load. + PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/pointer_ram.rams[0].RAM32M0_RAMD_D1_O has no load. PAR + will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem1_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/gbe0/wci_wslv_reqF/Mram_arr12_RAMA_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/gbe0/wci_wslv_reqF/Mram_arr12_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/gbe0/wci_wslv_reqF/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/gbe0/wci_wslv_reqF/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/cap0/wci_wslv_reqF/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/cap0/wci_wslv_reqF/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/pointer_ram.rams[1].RAM32M0_RAMA_D1_DPO has no load. + PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/pointer_ram.rams[1].RAM32M0_RAMD_D1_O has no load. PAR + will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/gbe0/wci_wslv_reqF/Mram_arr7_RAMC_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/gbe0/wci_wslv_reqF/Mram_arr7_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/gbe0/wci_wslv_reqF/Mram_arr6_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/gbe0/wci_wslv_reqF/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/ctop$wci_m_3_MByteEn<3> has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/cap0/wci_wslv_reqF/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/gbe0/wci_wslv_reqF/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/cap0/wci_wslv_reqF/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/cap0/wci_wslv_reqF/Mram_arr11_RAMC_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/cap0/wci_wslv_reqF/Mram_arr11_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/cap0/wci_wslv_reqF/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/cap0/wci_wslv_reqF/Mram_arr12_RAMA_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/cap0/wci_wslv_reqF/Mram_arr12_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/gbe0/gmac/txRS_txF/Mram_fifoMem1_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/cap0/wci_wslv_reqF/Mram_arr9_RAMA_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/cap0/wci_wslv_reqF/Mram_arr9_RAMB_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/cap0/wci_wslv_reqF/Mram_arr9_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/cap0/wci_wslv_reqF/Mram_arr6_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/cap0/wci_wslv_reqF/Mram_arr10_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/pciw_fI2P/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/pciw_fP2I/Mram_arr11_RAMC_D1_DPO has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/pciw_fP2I/Mram_arr11_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/pciw_fP2I/Mram_arr9_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/pciw_fP2I/Mram_arr13_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/pciw_fP2I/Mram_arr6_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/pciw_fI2P/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/pciw_fI2P/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/pciw_fI2P/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/pciw_fI2P/Mram_arr12_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/pciw_fP2I/Mram_arr1_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/pciw_fP2I/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/pciw_fP2I/Mram_arr3_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/pciw_fP2I/Mram_arr4_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/pciw_fP2I/Mram_arr7_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/pciw_fP2I/Mram_arr5_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/pciw_fI2P/Mram_arr7_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/pciw_fI2P/Mram_arr2_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/pciw_fI2P/Mram_arr6_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/pciw_fI2P/Mram_arr8_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/pciw_fI2P/Mram_arr9_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/pciw_fI2P/Mram_arr11_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/pciw_fI2P/Mram_arr10_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/pciw_fP2I/Mram_arr8_RAMD_D1_O has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal ftop/pciw_fP2I/Mram_arr10_RAMD_D1_O has no load. PAR will not attempt to route this signal. +Starting Router + + +Phase 1 : 249882 unrouted; REAL time: 46 secs + +Phase 2 : 213693 unrouted; REAL time: 1 mins 1 secs + +Phase 3 : 68586 unrouted; REAL time: 1 mins 54 secs + +Phase 4 : 69479 unrouted; (Setup:177118, Hold:26573, Component Switching Limit:0) REAL time: 2 mins 13 secs + +Updating file: fpgaTop.ncd with current fully routed design. + +Phase 5 : 0 unrouted; (Setup:407716, Hold:24568, Component Switching Limit:0) REAL time: 4 mins 9 secs + +Phase 6 : 0 unrouted; (Setup:407716, Hold:24568, Component Switching Limit:0) REAL time: 5 mins 22 secs + +Phase 7 : 0 unrouted; (Setup:407716, Hold:24568, Component Switching Limit:0) REAL time: 11 mins 7 secs + +Phase 8 : 0 unrouted; (Setup:407716, Hold:24568, Component Switching Limit:0) REAL time: 11 mins 7 secs + +Phase 9 : 0 unrouted; (Setup:407716, Hold:24568, Component Switching Limit:0) REAL time: 11 mins 7 secs + +Phase 10 : 0 unrouted; (Setup:407716, Hold:0, Component Switching Limit:0) REAL time: 11 mins 13 secs + +Phase 11 : 0 unrouted; (Setup:393240, Hold:0, Component Switching Limit:0) REAL time: 11 mins 25 secs +Total REAL time to Router completion: 11 mins 25 secs +Total CPU time to Router completion: 11 mins 56 secs + +Partition Implementation Status +------------------------------- + + No Partitions were found in this design. + +------------------------------- + +Generating "PAR" statistics. + +************************** +Generating Clock Report +************************** + ++---------------------+--------------+------+------+------------+-------------+ +| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)| ++---------------------+--------------+------+------+------------+-------------+ +| ftop/p125clk |BUFGCTRL_X0Y29| No | 7742 | 0.462 | 2.046 | ++---------------------+--------------+------+------+------------+-------------+ +|ftop/dram0/memc_memc | | | | | | +| $tb_clk |BUFGCTRL_X0Y25| No | 1982 | 0.298 | 1.915 | ++---------------------+--------------+------+------+------------+-------------+ +|ftop/dram0/memc_memc | | | | | | +| /clk_mem |BUFGCTRL_X0Y26| No | 186 | 0.164 | 1.901 | ++---------------------+--------------+------+------+------------+-------------+ +|ftop/sys0_clk$O_BUFG | | | | | | +| | BUFGCTRL_X0Y1| No | 232 | 0.292 | 1.880 | ++---------------------+--------------+------+------+------------+-------------+ +|ftop/pciw_pci0_pcie_ | | | | | | +| ep/ep/pipe_clk |BUFGCTRL_X0Y30| No | 182 | 0.413 | 2.046 | ++---------------------+--------------+------+------+------------+-------------+ +|ftop/dram0/memc_memc | | | | | | +|/u_memc_ui_top/u_mem | | | | | | +|_intfc/phy_top0/clk_ | | | | | | +| rsync<1> | Regional Clk|Yes | 430 | 0.193 | 1.036 | ++---------------------+--------------+------+------+------------+-------------+ +|ftop/dram0/memc_memc | | | | | | +|/u_memc_ui_top/u_mem | | | | | | +|_intfc/phy_top0/clk_ | | | | | | +| rsync<0> | Regional Clk|Yes | 292 | 0.245 | 1.083 | ++---------------------+--------------+------+------+------------+-------------+ +| ftop/rxclkBnd | Regional Clk| No | 47 | 0.225 | 1.083 | ++---------------------+--------------+------+------+------------+-------------+ +|ftop/pciw_pci0_pcie_ | | | | | | +| ep$trn_clk |BUFGCTRL_X0Y28| No | 236 | 0.183 | 1.787 | ++---------------------+--------------+------+------+------------+-------------+ +| ftop/flp_clk$O_BUFG | BUFGCTRL_X0Y0| No | 9 | 0.047 | 1.881 | ++---------------------+--------------+------+------+------------+-------------+ +| ftop/sys1_clk$O |BUFGCTRL_X0Y24| No | 57 | 0.080 | 1.937 | ++---------------------+--------------+------+------+------------+-------------+ +| ftop/flpCDC_sclk | BUFGCTRL_X0Y2| No | 29 | 0.318 | 1.920 | ++---------------------+--------------+------+------+------------+-------------+ +| ftop/flpDAC_sclk | BUFGCTRL_X0Y3| No | 16 | 0.278 | 1.891 | ++---------------------+--------------+------+------+------------+-------------+ +|ftop/pciw_pci0_pcie_ | | | | | | +| ep/ep/TxOutClk_bufg |BUFGCTRL_X0Y31| No | 6 | 0.013 | 1.636 | ++---------------------+--------------+------+------+------------+-------------+ +|ftop/dram0/memc_memc | | | | | | +|/u_memc_ui_top/u_mem | | | | | | +|_intfc/phy_top0/clk_ | | | | | | +| cpt<5> | Local| | 16 | 0.011 | 1.310 | ++---------------------+--------------+------+------+------------+-------------+ +|MMCM_PHASE_CALIBRATI | | | | | | +|ON_ML_LUT2_301_ML_NE | | | | | | +| W_CLK | Local| | 3 | 0.016 | 0.489 | ++---------------------+--------------+------+------+------------+-------------+ +|MMCM_PHASE_CALIBRATI | | | | | | +|ON_ML_LUT2_309_ML_NE | | | | | | +| W_CLK | Local| | 3 | 0.134 | 0.496 | ++---------------------+--------------+------+------+------------+-------------+ +|ftop/pciw_pci0_pcie_ | | | | | | +|ep/ep/pcie_clocking_ | | | | | | +|i/mmcm_adv_i_ML_NEW_ | | | | | | +| OUT | Local| | 2 | 0.000 | 0.541 | ++---------------------+--------------+------+------+------------+-------------+ +|ftop/dram0/memc_memc | | | | | | +|/u_infrastructure/u_ | | | | | | +| mmcm_adv_ML_NEW_OUT | Local| | 2 | 0.000 | 0.358 | ++---------------------+--------------+------+------+------------+-------------+ +|ftop/pciw_pci0_pcie_ | | | | | | +|ep/ep/pcie_clocking_ | | | | | | +|i/mmcm_adv_i_ML_NEW_ | | | | | | +| I1 | Local| | 3 | 0.000 | 2.253 | ++---------------------+--------------+------+------+------------+-------------+ +|ftop/dram0/memc_memc | | | | | | +|/u_infrastructure/u_ | | | | | | +| mmcm_adv_ML_NEW_I1 | Local| | 3 | 0.000 | 1.184 | ++---------------------+--------------+------+------+------------+-------------+ +|ftop/ctop/inf/cp/dna | | | | | | +| _cnt<0> | Local| | 11 | 0.000 | 2.766 | ++---------------------+--------------+------+------+------------+-------------+ +|ftop/dram0/memc_memc | | | | | | +|/u_memc_ui_top/u_mem | | | | | | +|_intfc/phy_top0/clk_ | | | | | | +| cpt<7> | Local| | 16 | 0.011 | 1.310 | ++---------------------+--------------+------+------+------------+-------------+ +|ftop/dram0/memc_memc | | | | | | +| /clk_wr_i | Local| | 10 | 0.402 | 1.403 | ++---------------------+--------------+------+------+------------+-------------+ +|ftop/dram0/memc_memc | | | | | | +|/u_memc_ui_top/u_mem | | | | | | +|_intfc/phy_top0/clk_ | | | | | | +| cpt<6> | Local| | 16 | 0.000 | 1.288 | ++---------------------+--------------+------+------+------------+-------------+ +|ftop/dram0/memc_memc | | | | | | +|/u_memc_ui_top/u_mem | | | | | | +|_intfc/phy_top0/clk_ | | | | | | +| cpt<2> | Local| | 16 | 0.011 | 1.310 | ++---------------------+--------------+------+------+------------+-------------+ +|ftop/dram0/memc_memc | | | | | | +|/u_memc_ui_top/u_mem | | | | | | +|_intfc/phy_top0/clk_ | | | | | | +| cpt<3> | Local| | 16 | 0.000 | 1.288 | ++---------------------+--------------+------+------+------------+-------------+ +|ftop/dram0/memc_memc | | | | | | +|/u_memc_ui_top/u_mem | | | | | | +|_intfc/phy_top0/clk_ | | | | | | +| cpt<4> | Local| | 16 | 0.011 | 1.310 | ++---------------------+--------------+------+------+------------+-------------+ +|ftop/dram0/memc_memc | | | | | | +|/u_memc_ui_top/u_mem | | | | | | +|_intfc/phy_top0/clk_ | | | | | | +| cpt<0> | Local| | 18 | 0.011 | 1.310 | ++---------------------+--------------+------+------+------------+-------------+ +|ftop/pciw_pci0_clk$O | | | | | | +| | Local| | 8 | 0.000 | 2.396 | ++---------------------+--------------+------+------+------------+-------------+ +|ftop/dram0/memc_memc | | | | | | +|/u_memc_ui_top/u_mem | | | | | | +|_intfc/phy_top0/clk_ | | | | | | +| cpt<1> | Local| | 16 | 0.000 | 1.288 | ++---------------------+--------------+------+------+------------+-------------+ + +* Net Skew is the difference between the minimum and maximum routing +only delays for the net. Note this is different from Clock Skew which +is reported in TRCE timing report. Clock Skew is the difference between +the minimum and maximum path delays which includes logic delays. + +* The fanout is the number of component pins not the individual BEL loads, +for example SLICE loads not FF loads. + +Timing Score: 393240 (Setup: 393240, Hold: 0, Component Switching Limit: 0) + +WARNING:Par:468 - Your design did not meet timing. The following are some suggestions to assist you to meet timing in your design. + + Review the timing report using Timing Analyzer (In ISE select "Post-Place & + Route Static Timing Report"). Go to the failing constraint(s) and evaluate the failing paths for each constraint. + + Try the Design Goal and Strategies for Timing Performance(In ISE select Project -> Design Goals & Strategies) to ensure the best options + are set in the tools for timing closure. + + Increase the PAR Effort Level setting to "high" + + Use the Xilinx "SmartXplorer" script to try special combinations of + options known to produce very good results. + + Visit the Xilinx technical support web at http://support.xilinx.com and go to + either "Troubleshoot->Tech Tips->Timing & Constraints" or " + TechXclusives->Timing Closure" for tips and suggestions for meeting timing + in your design. + +Number of Timing Constraints that were not applied: 13 + +Asterisk (*) preceding a constraint indicates it was not met. + This may be due to a setup or hold violation. + +---------------------------------------------------------------------------------------------------------- + Constraint | Check | Worst Case | Best Case | Timing | Timing + | | Slack | Achievable | Errors | Score +---------------------------------------------------------------------------------------------------------- +* TS_CLK_125 = PERIOD TIMEGRP "CLK_125" TS_ | SETUP | -2.171ns| 10.171ns| 380| 392584 + PCICLK / 2 HIGH 50% PRIORITY 100 | HOLD | 0.001ns| | 0| 0 +---------------------------------------------------------------------------------------------------------- +* TS_ftop_dram0_memc_memc_u_infrastructure_ | SETUP | -0.170ns| 5.170ns| 5| 392 + clk_pll = PERIOD TIMEGRP "ftop_dr | HOLD | 0.040ns| | 0| 0 + am0_memc_memc_u_infrastructure_clk_pll" T | | | | | + S_SYS0CLK HIGH 50% | | | | | +---------------------------------------------------------------------------------------------------------- +* TS_CLK_250 = PERIOD TIMEGRP "CLK_250" TS_ | SETUP | -0.033ns| 4.033ns| 8| 264 + PCICLK HIGH 50% PRIORITY 1 | HOLD | 0.002ns| | 0| 0 + | MINPERIOD | 0.000ns| 4.000ns| 0| 0 +---------------------------------------------------------------------------------------------------------- + Pin to Pin Skew Constraint | MAXDELAY | 0.108ns| 0.450ns| 0| 0 +---------------------------------------------------------------------------------------------------------- + TS_SYS0CLK = PERIOD TIMEGRP "SYS0CLK" 200 | SETUP | 0.111ns| 4.889ns| 0| 0 + MHz HIGH 50% | HOLD | 0.048ns| | 0| 0 +---------------------------------------------------------------------------------------------------------- + COMP "gmii_rxd<1>" OFFSET = IN 0.5 ns VAL | SETUP | 0.224ns| 0.276ns| 0| 0 + ID 3 ns BEFORE COMP "gmii_rx_clk" | HOLD | 2.070ns| | 0| 0 +---------------------------------------------------------------------------------------------------------- + COMP "gmii_rxd<3>" OFFSET = IN 0.5 ns VAL | SETUP | 0.565ns| -0.065ns| 0| 0 + ID 3 ns BEFORE COMP "gmii_rx_clk" | HOLD | 1.692ns| | 0| 0 +---------------------------------------------------------------------------------------------------------- + COMP "gmii_rx_dv" OFFSET = IN 0.5 ns VALI | SETUP | 0.569ns| -0.069ns| 0| 0 + D 3 ns BEFORE COMP "gmii_rx_clk" | HOLD | 1.676ns| | 0| 0 +---------------------------------------------------------------------------------------------------------- + COMP "gmii_rxd<0>" OFFSET = IN 0.5 ns VAL | SETUP | 0.637ns| -0.137ns| 0| 0 + ID 3 ns BEFORE COMP "gmii_rx_clk" | HOLD | 1.577ns| | 0| 0 +---------------------------------------------------------------------------------------------------------- + COMP "gmii_rxd<2>" OFFSET = IN 0.5 ns VAL | SETUP | 0.641ns| -0.141ns| 0| 0 + ID 3 ns BEFORE COMP "gmii_rx_clk" | HOLD | 1.653ns| | 0| 0 +---------------------------------------------------------------------------------------------------------- + COMP "gmii_rxd<6>" OFFSET = IN 0.5 ns VAL | SETUP | 0.663ns| -0.163ns| 0| 0 + ID 3 ns BEFORE COMP "gmii_rx_clk" | HOLD | 1.666ns| | 0| 0 +---------------------------------------------------------------------------------------------------------- + COMP "gmii_rxd<7>" OFFSET = IN 0.5 ns VAL | SETUP | 0.667ns| -0.167ns| 0| 0 + ID 3 ns BEFORE COMP "gmii_rx_clk" | HOLD | 1.655ns| | 0| 0 +---------------------------------------------------------------------------------------------------------- + COMP "gmii_rxd<5>" OFFSET = IN 0.5 ns VAL | SETUP | 0.712ns| -0.212ns| 0| 0 + ID 3 ns BEFORE COMP "gmii_rx_clk" | HOLD | 1.614ns| | 0| 0 +---------------------------------------------------------------------------------------------------------- + COMP "gmii_rxd<4>" OFFSET = IN 0.5 ns VAL | SETUP | 0.816ns| -0.316ns| 0| 0 + ID 3 ns BEFORE COMP "gmii_rx_clk" | HOLD | 1.417ns| | 0| 0 +---------------------------------------------------------------------------------------------------------- + COMP "gmii_rx_er" OFFSET = IN 0.5 ns VALI | SETUP | 1.037ns| -0.537ns| 0| 0 + D 3 ns BEFORE COMP "gmii_rx_clk" | HOLD | 1.069ns| | 0| 0 +---------------------------------------------------------------------------------------------------------- + TS_ftop_dram0_memc_memc_u_infrastructure_ | MINPERIOD | 1.071ns| 1.429ns| 0| 0 + clk_mem_pll = PERIOD TIMEGRP "fto | | | | | + p_dram0_memc_memc_u_infrastructure_clk_me | | | | | + m_pll" TS_SYS0CLK * 2 HIGH 50% | | | | | +---------------------------------------------------------------------------------------------------------- + TS_GMII_GTX_CLK = PERIOD TIMEGRP "GMII_GT | SETUP | 2.200ns| 5.800ns| 0| 0 + X_CLK" 125 MHz HIGH 50% | HOLD | 0.072ns| | 0| 0 +---------------------------------------------------------------------------------------------------------- + TS_PCICLK = PERIOD TIMEGRP "PCICLK" 250 M | MINPERIOD | 2.462ns| 1.538ns| 0| 0 + Hz HIGH 50% | | | | | +---------------------------------------------------------------------------------------------------------- + TS_GMII_RX_CLK = PERIOD TIMEGRP "GMII_RX_ | SETUP | 2.533ns| 5.467ns| 0| 0 + CLK" 125 MHz HIGH 50% | HOLD | 0.055ns| | 0| 0 +---------------------------------------------------------------------------------------------------------- + COMP "gmii_tx_er" OFFSET = OUT 6 ns AFTER | N/A | N/A| N/A| N/A| N/A + COMP "gmii_gtx_clk" | | | | | +---------------------------------------------------------------------------------------------------------- + COMP "gmii_tx_en" OFFSET = OUT 6 ns AFTER | N/A | N/A| N/A| N/A| N/A + COMP "gmii_gtx_clk" | | | | | +---------------------------------------------------------------------------------------------------------- + COMP "gmii_txd<0>" OFFSET = OUT 6 ns AFTE | N/A | N/A| N/A| N/A| N/A + R COMP "gmii_gtx_clk" | | | | | +---------------------------------------------------------------------------------------------------------- + COMP "gmii_txd<1>" OFFSET = OUT 6 ns AFTE | N/A | N/A| N/A| N/A| N/A + R COMP "gmii_gtx_clk" | | | | | +---------------------------------------------------------------------------------------------------------- + COMP "gmii_txd<2>" OFFSET = OUT 6 ns AFTE | N/A | N/A| N/A| N/A| N/A + R COMP "gmii_gtx_clk" | | | | | +---------------------------------------------------------------------------------------------------------- + COMP "gmii_txd<3>" OFFSET = OUT 6 ns AFTE | N/A | N/A| N/A| N/A| N/A + R COMP "gmii_gtx_clk" | | | | | +---------------------------------------------------------------------------------------------------------- + COMP "gmii_txd<4>" OFFSET = OUT 6 ns AFTE | N/A | N/A| N/A| N/A| N/A + R COMP "gmii_gtx_clk" | | | | | +---------------------------------------------------------------------------------------------------------- + COMP "gmii_txd<5>" OFFSET = OUT 6 ns AFTE | N/A | N/A| N/A| N/A| N/A + R COMP "gmii_gtx_clk" | | | | | +---------------------------------------------------------------------------------------------------------- + COMP "gmii_txd<6>" OFFSET = OUT 6 ns AFTE | N/A | N/A| N/A| N/A| N/A + R COMP "gmii_gtx_clk" | | | | | +---------------------------------------------------------------------------------------------------------- + COMP "gmii_txd<7>" OFFSET = OUT 6 ns AFTE | N/A | N/A| N/A| N/A| N/A + R COMP "gmii_gtx_clk" | | | | | +---------------------------------------------------------------------------------------------------------- + TS_ftop_dram0_memc_memc_clk_wr_i = PERIOD | N/A | N/A| N/A| N/A| N/A + TIMEGRP "ftop_dram0_memc_memc_cl | | | | | + k_wr_i" TS_SYS0CLK * 2 HIGH 50% | | | | | +---------------------------------------------------------------------------------------------------------- + + +Derived Constraint Report +Review Timing Report for more details on the following derived constraints. +To create a Timing Report, run "trce -v 12 -fastpaths -o design_timing_report design.ncd design.pcf" +or "Run Timing Analysis" from Timing Analyzer (timingan). +Derived Constraints for TS_SYS0CLK ++-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ +| | Period | Actual Period | Timing Errors | Paths Analyzed | +| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------| +| | | Direct | Derivative | Direct | Derivative | Direct | Derivative | ++-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ +|TS_SYS0CLK | 5.000ns| 4.889ns| 5.170ns| 0| 5| 91979| 58635| +| TS_ftop_dram0_memc_memc_u_infr| 5.000ns| 5.170ns| N/A| 5| 0| 58635| 0| +| astructure_clk_pll | | | | | | | | +| TS_ftop_dram0_memc_memc_u_infr| 2.500ns| 1.429ns| N/A| 0| 0| 0| 0| +| astructure_clk_mem_pll | | | | | | | | +| TS_ftop_dram0_memc_memc_clk_wr| 2.500ns| N/A| N/A| 0| 0| 0| 0| +| _i | | | | | | | | ++-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ + +Derived Constraints for TS_PCICLK ++-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ +| | Period | Actual Period | Timing Errors | Paths Analyzed | +| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------| +| | | Direct | Derivative | Direct | Derivative | Direct | Derivative | ++-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ +|TS_PCICLK | 4.000ns| 1.538ns| 5.085ns| 0| 388| 0| 13963164| +| TS_CLK_125 | 8.000ns| 10.171ns| N/A| 380| 0| 13943867| 0| +| TS_CLK_250 | 4.000ns| 4.033ns| N/A| 8| 0| 19297| 0| ++-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ + +3 constraints not met. +INFO:Timing:2761 - N/A entries in the Constraints List may indicate that the + constraint is not analyzed due to the following: No paths covered by this + constraint; Other constraints intersect with this constraint; or This + constraint was disabled by a Path Tracing Control. Please run the Timespec + Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI. + + +Generating Pad Report. + +All signals are completely routed. + +WARNING:Par:283 - There are 532 loadless signals in this design. This design will cause Bitgen to issue DRC warnings. + +Total REAL time to PAR completion: 11 mins 42 secs +Total CPU time to PAR completion: 12 mins 13 secs + +Peak Memory Usage: 2196 MB + +Placer: Placement generated during map. +Routing: Completed - No errors found. +Timing: Completed - 393 errors found. + +Number of error messages: 0 +Number of warning messages: 555 +Number of info messages: 0 + +Writing design to file fpgaTop.ncd + + + +PAR done! diff --git a/logs/ml605-20130127_1122/fpgaTop.twr b/logs/ml605-20130127_1122/fpgaTop.twr new file mode 100644 index 00000000..c5f94d15 --- /dev/null +++ b/logs/ml605-20130127_1122/fpgaTop.twr @@ -0,0 +1,10813 @@ +-------------------------------------------------------------------------------- +Release 14.4 Trace (lin64) +Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. + +/opt/Xilinx/14.4/ISE_DS/ISE/bin/lin64/unwrapped/trce -v 20 -fastpaths -xml +fpgaTop.twx fpgaTop.ncd -o fpgaTop.twr fpgaTop.pcf + +Design file: fpgaTop.ncd +Physical constraint file: fpgaTop.pcf +Device,package,speed: xc6vlx240t,ff1156,C,-1 (PRODUCTION 1.17 2012-12-04, STEPPING level 0) +Report level: verbose report, limited to 20 items per constraint + +Environment Variable Effect +-------------------- ------ +NONE No environment variables were set +-------------------------------------------------------------------------------- + +WARNING:Timing:3175 - gmii_gtx_clk does not clock data to gmii_txd<7> +WARNING:Timing:3225 - Timing constraint COMP "gmii_txd<7>" OFFSET = OUT 6 ns + AFTER COMP "gmii_gtx_clk"; ignored during timing analysis +WARNING:Timing:3175 - gmii_gtx_clk does not clock data to gmii_txd<6> +WARNING:Timing:3225 - Timing constraint COMP "gmii_txd<6>" OFFSET = OUT 6 ns + AFTER COMP "gmii_gtx_clk"; ignored during timing analysis +WARNING:Timing:3175 - gmii_gtx_clk does not clock data to gmii_txd<5> +WARNING:Timing:3225 - Timing constraint COMP "gmii_txd<5>" OFFSET = OUT 6 ns + AFTER COMP "gmii_gtx_clk"; ignored during timing analysis +WARNING:Timing:3175 - gmii_gtx_clk does not clock data to gmii_txd<4> +WARNING:Timing:3225 - Timing constraint COMP "gmii_txd<4>" OFFSET = OUT 6 ns + AFTER COMP "gmii_gtx_clk"; ignored during timing analysis +WARNING:Timing:3175 - gmii_gtx_clk does not clock data to gmii_txd<3> +WARNING:Timing:3225 - Timing constraint COMP "gmii_txd<3>" OFFSET = OUT 6 ns + AFTER COMP "gmii_gtx_clk"; ignored during timing analysis +WARNING:Timing:3175 - gmii_gtx_clk does not clock data to gmii_txd<2> +WARNING:Timing:3225 - Timing constraint COMP "gmii_txd<2>" OFFSET = OUT 6 ns + AFTER COMP "gmii_gtx_clk"; ignored during timing analysis +WARNING:Timing:3175 - gmii_gtx_clk does not clock data to gmii_txd<1> +WARNING:Timing:3225 - Timing constraint COMP "gmii_txd<1>" OFFSET = OUT 6 ns + AFTER COMP "gmii_gtx_clk"; ignored during timing analysis +WARNING:Timing:3175 - gmii_gtx_clk does not clock data to gmii_txd<0> +WARNING:Timing:3225 - Timing constraint COMP "gmii_txd<0>" OFFSET = OUT 6 ns + AFTER COMP "gmii_gtx_clk"; ignored during timing analysis +WARNING:Timing:3175 - gmii_gtx_clk does not clock data to gmii_tx_en +WARNING:Timing:3225 - Timing constraint COMP "gmii_tx_en" OFFSET = OUT 6 ns + AFTER COMP "gmii_gtx_clk"; ignored during timing analysis +WARNING:Timing:3175 - gmii_gtx_clk does not clock data to gmii_tx_er +WARNING:Timing:3225 - Timing constraint COMP "gmii_tx_er" OFFSET = OUT 6 ns + AFTER COMP "gmii_gtx_clk"; ignored during timing analysis +INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612). +INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths + option. All paths that are not constrained will be reported in the + unconstrained paths section(s) of the report. +INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on + a 50 Ohm transmission line loading model. For the details of this model, + and for more information on accounting for different loading conditions, + please see the device datasheet. + +================================================================================ +Timing constraint: TS_SYS0CLK = PERIOD TIMEGRP "SYS0CLK" 200 MHz HIGH 50%; +For more information, see Period Analysis in the Timing Closure User Guide (UG612). + + 91979 paths analyzed, 3670 endpoints analyzed, 0 failing endpoints + 0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors) + Minimum period is 4.889ns. +-------------------------------------------------------------------------------- +Slack (setup path): 0.111ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/timeServ_setRefF/dNotEmptyReg (FF) + Destination: ftop/ctop/inf/cp/timeServ_jamFracVal_42 (FF) + Requirement: 5.000ns + Data Path Delay: 4.638ns (Levels of Logic = 1) + Clock Path Skew: -0.216ns (1.470 - 1.686) + Source Clock: ftop/sys0_clk$O_BUFG rising at 0.000ns + Destination Clock: ftop/sys0_clk$O_BUFG rising at 5.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/timeServ_setRefF/dNotEmptyReg to ftop/ctop/inf/cp/timeServ_jamFracVal_42 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X44Y79.AQ Tcko 0.381 ftop/ctop/inf/cp/timeServ_setRefF$dEMPTY_N + ftop/ctop/inf/cp/timeServ_setRefF/dNotEmptyReg + SLICE_X5Y82.B5 net (fanout=37) 2.314 ftop/ctop/inf/cp/timeServ_setRefF$dEMPTY_N + SLICE_X5Y82.B Tilo 0.068 ftop/ctop/app/appW2/wmi_peerIsReady + ftop/ctop/inf/cp/timeServ_jamFrac_1$whas_inv_01 + SLICE_X19Y89.SR net (fanout=8) 1.362 ftop/ctop/inf/cp/timeServ_jamFrac_1$whas_inv_0 + SLICE_X19Y89.CLK Tsrck 0.513 ftop/ctop/inf/cp/timeServ_jamFracVal<43> + ftop/ctop/inf/cp/timeServ_jamFracVal_42 + ------------------------------------------------- --------------------------- + Total 4.638ns (0.962ns logic, 3.676ns route) + (20.7% logic, 79.3% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.111ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/timeServ_setRefF/dNotEmptyReg (FF) + Destination: ftop/ctop/inf/cp/timeServ_jamFracVal_43 (FF) + Requirement: 5.000ns + Data Path Delay: 4.638ns (Levels of Logic = 1) + Clock Path Skew: -0.216ns (1.470 - 1.686) + Source Clock: ftop/sys0_clk$O_BUFG rising at 0.000ns + Destination Clock: ftop/sys0_clk$O_BUFG rising at 5.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/timeServ_setRefF/dNotEmptyReg to ftop/ctop/inf/cp/timeServ_jamFracVal_43 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X44Y79.AQ Tcko 0.381 ftop/ctop/inf/cp/timeServ_setRefF$dEMPTY_N + ftop/ctop/inf/cp/timeServ_setRefF/dNotEmptyReg + SLICE_X5Y82.B5 net (fanout=37) 2.314 ftop/ctop/inf/cp/timeServ_setRefF$dEMPTY_N + SLICE_X5Y82.B Tilo 0.068 ftop/ctop/app/appW2/wmi_peerIsReady + ftop/ctop/inf/cp/timeServ_jamFrac_1$whas_inv_01 + SLICE_X19Y89.SR net (fanout=8) 1.362 ftop/ctop/inf/cp/timeServ_jamFrac_1$whas_inv_0 + SLICE_X19Y89.CLK Tsrck 0.513 ftop/ctop/inf/cp/timeServ_jamFracVal<43> + ftop/ctop/inf/cp/timeServ_jamFracVal_43 + ------------------------------------------------- --------------------------- + Total 4.638ns (0.962ns logic, 3.676ns route) + (20.7% logic, 79.3% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.111ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/timeServ_setRefF/dNotEmptyReg (FF) + Destination: ftop/ctop/inf/cp/timeServ_jamFracVal_40 (FF) + Requirement: 5.000ns + Data Path Delay: 4.638ns (Levels of Logic = 1) + Clock Path Skew: -0.216ns (1.470 - 1.686) + Source Clock: ftop/sys0_clk$O_BUFG rising at 0.000ns + Destination Clock: ftop/sys0_clk$O_BUFG rising at 5.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/timeServ_setRefF/dNotEmptyReg to ftop/ctop/inf/cp/timeServ_jamFracVal_40 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X44Y79.AQ Tcko 0.381 ftop/ctop/inf/cp/timeServ_setRefF$dEMPTY_N + ftop/ctop/inf/cp/timeServ_setRefF/dNotEmptyReg + SLICE_X5Y82.B5 net (fanout=37) 2.314 ftop/ctop/inf/cp/timeServ_setRefF$dEMPTY_N + SLICE_X5Y82.B Tilo 0.068 ftop/ctop/app/appW2/wmi_peerIsReady + ftop/ctop/inf/cp/timeServ_jamFrac_1$whas_inv_01 + SLICE_X19Y89.SR net (fanout=8) 1.362 ftop/ctop/inf/cp/timeServ_jamFrac_1$whas_inv_0 + SLICE_X19Y89.CLK Tsrck 0.513 ftop/ctop/inf/cp/timeServ_jamFracVal<43> + ftop/ctop/inf/cp/timeServ_jamFracVal_40 + ------------------------------------------------- --------------------------- + Total 4.638ns (0.962ns logic, 3.676ns route) + (20.7% logic, 79.3% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.111ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/timeServ_setRefF/dNotEmptyReg (FF) + Destination: ftop/ctop/inf/cp/timeServ_jamFracVal_41 (FF) + Requirement: 5.000ns + Data Path Delay: 4.638ns (Levels of Logic = 1) + Clock Path Skew: -0.216ns (1.470 - 1.686) + Source Clock: ftop/sys0_clk$O_BUFG rising at 0.000ns + Destination Clock: ftop/sys0_clk$O_BUFG rising at 5.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/timeServ_setRefF/dNotEmptyReg to ftop/ctop/inf/cp/timeServ_jamFracVal_41 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X44Y79.AQ Tcko 0.381 ftop/ctop/inf/cp/timeServ_setRefF$dEMPTY_N + ftop/ctop/inf/cp/timeServ_setRefF/dNotEmptyReg + SLICE_X5Y82.B5 net (fanout=37) 2.314 ftop/ctop/inf/cp/timeServ_setRefF$dEMPTY_N + SLICE_X5Y82.B Tilo 0.068 ftop/ctop/app/appW2/wmi_peerIsReady + ftop/ctop/inf/cp/timeServ_jamFrac_1$whas_inv_01 + SLICE_X19Y89.SR net (fanout=8) 1.362 ftop/ctop/inf/cp/timeServ_jamFrac_1$whas_inv_0 + SLICE_X19Y89.CLK Tsrck 0.513 ftop/ctop/inf/cp/timeServ_jamFracVal<43> + ftop/ctop/inf/cp/timeServ_jamFracVal_41 + ------------------------------------------------- --------------------------- + Total 4.638ns (0.962ns logic, 3.676ns route) + (20.7% logic, 79.3% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.134ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/timeServ_refFromRise_9 (FF) + Destination: ftop/ctop/inf/cp/timeServ_delSecond_49 (FF) + Requirement: 5.000ns + Data Path Delay: 4.609ns (Levels of Logic = 3) + Clock Path Skew: -0.222ns (1.482 - 1.704) + Source Clock: ftop/sys0_clk$O_BUFG rising at 0.000ns + Destination Clock: ftop/sys0_clk$O_BUFG rising at 5.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/timeServ_refFromRise_9 to ftop/ctop/inf/cp/timeServ_delSecond_49 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X0Y76.BQ Tcko 0.381 ftop/ctop/inf/cp/timeServ_refFromRise<11> + ftop/ctop/inf/cp/timeServ_refFromRise_9 + SLICE_X3Y77.A2 net (fanout=4) 0.844 ftop/ctop/inf/cp/timeServ_refFromRise<9> + SLICE_X3Y77.COUT Topcya 0.409 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<3> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_lut<0> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<3> + SLICE_X3Y78.CIN net (fanout=1) 0.000 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<3> + SLICE_X3Y78.AMUX Tcina 0.248 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<4> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<4> + SLICE_X19Y76.B5 net (fanout=4) 0.849 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<4> + SLICE_X19Y76.B Tilo 0.068 ftop/ctop/app/appW2/wmi_respF/data1_reg<123> + ftop/ctop/inf/cp/timeServ_ppsExtSync_d2_2_AND_NOT_timeServ_ppsE_ETC___d7011 + SLICE_X9Y91.CE net (fanout=34) 1.492 ftop/ctop/inf/cp/timeServ_delSecond$EN + SLICE_X9Y91.CLK Tceck 0.318 ftop/ctop/inf/cp/timeServ_delSecond<49> + ftop/ctop/inf/cp/timeServ_delSecond_49 + ------------------------------------------------- --------------------------- + Total 4.609ns (1.424ns logic, 3.185ns route) + (30.9% logic, 69.1% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.134ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/timeServ_refFromRise_9 (FF) + Destination: ftop/ctop/inf/cp/timeServ_delSecond_48 (FF) + Requirement: 5.000ns + Data Path Delay: 4.609ns (Levels of Logic = 3) + Clock Path Skew: -0.222ns (1.482 - 1.704) + Source Clock: ftop/sys0_clk$O_BUFG rising at 0.000ns + Destination Clock: ftop/sys0_clk$O_BUFG rising at 5.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/timeServ_refFromRise_9 to ftop/ctop/inf/cp/timeServ_delSecond_48 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X0Y76.BQ Tcko 0.381 ftop/ctop/inf/cp/timeServ_refFromRise<11> + ftop/ctop/inf/cp/timeServ_refFromRise_9 + SLICE_X3Y77.A2 net (fanout=4) 0.844 ftop/ctop/inf/cp/timeServ_refFromRise<9> + SLICE_X3Y77.COUT Topcya 0.409 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<3> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_lut<0> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<3> + SLICE_X3Y78.CIN net (fanout=1) 0.000 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<3> + SLICE_X3Y78.AMUX Tcina 0.248 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<4> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<4> + SLICE_X19Y76.B5 net (fanout=4) 0.849 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<4> + SLICE_X19Y76.B Tilo 0.068 ftop/ctop/app/appW2/wmi_respF/data1_reg<123> + ftop/ctop/inf/cp/timeServ_ppsExtSync_d2_2_AND_NOT_timeServ_ppsE_ETC___d7011 + SLICE_X9Y91.CE net (fanout=34) 1.492 ftop/ctop/inf/cp/timeServ_delSecond$EN + SLICE_X9Y91.CLK Tceck 0.318 ftop/ctop/inf/cp/timeServ_delSecond<49> + ftop/ctop/inf/cp/timeServ_delSecond_48 + ------------------------------------------------- --------------------------- + Total 4.609ns (1.424ns logic, 3.185ns route) + (30.9% logic, 69.1% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.162ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/timeServ_refFromRise_9 (FF) + Destination: ftop/ctop/inf/cp/timeServ_delSecond_49 (FF) + Requirement: 5.000ns + Data Path Delay: 4.581ns (Levels of Logic = 3) + Clock Path Skew: -0.222ns (1.482 - 1.704) + Source Clock: ftop/sys0_clk$O_BUFG rising at 0.000ns + Destination Clock: ftop/sys0_clk$O_BUFG rising at 5.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/timeServ_refFromRise_9 to ftop/ctop/inf/cp/timeServ_delSecond_49 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X0Y76.BQ Tcko 0.381 ftop/ctop/inf/cp/timeServ_refFromRise<11> + ftop/ctop/inf/cp/timeServ_refFromRise_9 + SLICE_X3Y77.A2 net (fanout=4) 0.844 ftop/ctop/inf/cp/timeServ_refFromRise<9> + SLICE_X3Y77.COUT Topcya 0.381 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<3> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_lutdi + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<3> + SLICE_X3Y78.CIN net (fanout=1) 0.000 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<3> + SLICE_X3Y78.AMUX Tcina 0.248 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<4> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<4> + SLICE_X19Y76.B5 net (fanout=4) 0.849 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<4> + SLICE_X19Y76.B Tilo 0.068 ftop/ctop/app/appW2/wmi_respF/data1_reg<123> + ftop/ctop/inf/cp/timeServ_ppsExtSync_d2_2_AND_NOT_timeServ_ppsE_ETC___d7011 + SLICE_X9Y91.CE net (fanout=34) 1.492 ftop/ctop/inf/cp/timeServ_delSecond$EN + SLICE_X9Y91.CLK Tceck 0.318 ftop/ctop/inf/cp/timeServ_delSecond<49> + ftop/ctop/inf/cp/timeServ_delSecond_49 + ------------------------------------------------- --------------------------- + Total 4.581ns (1.396ns logic, 3.185ns route) + (30.5% logic, 69.5% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.162ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/timeServ_refFromRise_9 (FF) + Destination: ftop/ctop/inf/cp/timeServ_delSecond_48 (FF) + Requirement: 5.000ns + Data Path Delay: 4.581ns (Levels of Logic = 3) + Clock Path Skew: -0.222ns (1.482 - 1.704) + Source Clock: ftop/sys0_clk$O_BUFG rising at 0.000ns + Destination Clock: ftop/sys0_clk$O_BUFG rising at 5.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/timeServ_refFromRise_9 to ftop/ctop/inf/cp/timeServ_delSecond_48 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X0Y76.BQ Tcko 0.381 ftop/ctop/inf/cp/timeServ_refFromRise<11> + ftop/ctop/inf/cp/timeServ_refFromRise_9 + SLICE_X3Y77.A2 net (fanout=4) 0.844 ftop/ctop/inf/cp/timeServ_refFromRise<9> + SLICE_X3Y77.COUT Topcya 0.381 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<3> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_lutdi + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<3> + SLICE_X3Y78.CIN net (fanout=1) 0.000 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<3> + SLICE_X3Y78.AMUX Tcina 0.248 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<4> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<4> + SLICE_X19Y76.B5 net (fanout=4) 0.849 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<4> + SLICE_X19Y76.B Tilo 0.068 ftop/ctop/app/appW2/wmi_respF/data1_reg<123> + ftop/ctop/inf/cp/timeServ_ppsExtSync_d2_2_AND_NOT_timeServ_ppsE_ETC___d7011 + SLICE_X9Y91.CE net (fanout=34) 1.492 ftop/ctop/inf/cp/timeServ_delSecond$EN + SLICE_X9Y91.CLK Tceck 0.318 ftop/ctop/inf/cp/timeServ_delSecond<49> + ftop/ctop/inf/cp/timeServ_delSecond_48 + ------------------------------------------------- --------------------------- + Total 4.581ns (1.396ns logic, 3.185ns route) + (30.5% logic, 69.5% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.169ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/timeServ_setRefF/dNotEmptyReg (FF) + Destination: ftop/ctop/inf/cp/timeServ_jamFracVal_36 (FF) + Requirement: 5.000ns + Data Path Delay: 4.580ns (Levels of Logic = 1) + Clock Path Skew: -0.216ns (1.470 - 1.686) + Source Clock: ftop/sys0_clk$O_BUFG rising at 0.000ns + Destination Clock: ftop/sys0_clk$O_BUFG rising at 5.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/timeServ_setRefF/dNotEmptyReg to ftop/ctop/inf/cp/timeServ_jamFracVal_36 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X44Y79.AQ Tcko 0.381 ftop/ctop/inf/cp/timeServ_setRefF$dEMPTY_N + ftop/ctop/inf/cp/timeServ_setRefF/dNotEmptyReg + SLICE_X5Y82.B5 net (fanout=37) 2.314 ftop/ctop/inf/cp/timeServ_setRefF$dEMPTY_N + SLICE_X5Y82.B Tilo 0.068 ftop/ctop/app/appW2/wmi_peerIsReady + ftop/ctop/inf/cp/timeServ_jamFrac_1$whas_inv_01 + SLICE_X18Y89.SR net (fanout=8) 1.362 ftop/ctop/inf/cp/timeServ_jamFrac_1$whas_inv_0 + SLICE_X18Y89.CLK Tsrck 0.455 ftop/ctop/inf/cp/timeServ_jamFracVal<39> + ftop/ctop/inf/cp/timeServ_jamFracVal_36 + ------------------------------------------------- --------------------------- + Total 4.580ns (0.904ns logic, 3.676ns route) + (19.7% logic, 80.3% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.169ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/timeServ_setRefF/dNotEmptyReg (FF) + Destination: ftop/ctop/inf/cp/timeServ_jamFracVal_37 (FF) + Requirement: 5.000ns + Data Path Delay: 4.580ns (Levels of Logic = 1) + Clock Path Skew: -0.216ns (1.470 - 1.686) + Source Clock: ftop/sys0_clk$O_BUFG rising at 0.000ns + Destination Clock: ftop/sys0_clk$O_BUFG rising at 5.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/timeServ_setRefF/dNotEmptyReg to ftop/ctop/inf/cp/timeServ_jamFracVal_37 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X44Y79.AQ Tcko 0.381 ftop/ctop/inf/cp/timeServ_setRefF$dEMPTY_N + ftop/ctop/inf/cp/timeServ_setRefF/dNotEmptyReg + SLICE_X5Y82.B5 net (fanout=37) 2.314 ftop/ctop/inf/cp/timeServ_setRefF$dEMPTY_N + SLICE_X5Y82.B Tilo 0.068 ftop/ctop/app/appW2/wmi_peerIsReady + ftop/ctop/inf/cp/timeServ_jamFrac_1$whas_inv_01 + SLICE_X18Y89.SR net (fanout=8) 1.362 ftop/ctop/inf/cp/timeServ_jamFrac_1$whas_inv_0 + SLICE_X18Y89.CLK Tsrck 0.455 ftop/ctop/inf/cp/timeServ_jamFracVal<39> + ftop/ctop/inf/cp/timeServ_jamFracVal_37 + ------------------------------------------------- --------------------------- + Total 4.580ns (0.904ns logic, 3.676ns route) + (19.7% logic, 80.3% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.169ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/timeServ_setRefF/dNotEmptyReg (FF) + Destination: ftop/ctop/inf/cp/timeServ_jamFracVal_39 (FF) + Requirement: 5.000ns + Data Path Delay: 4.580ns (Levels of Logic = 1) + Clock Path Skew: -0.216ns (1.470 - 1.686) + Source Clock: ftop/sys0_clk$O_BUFG rising at 0.000ns + Destination Clock: ftop/sys0_clk$O_BUFG rising at 5.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/timeServ_setRefF/dNotEmptyReg to ftop/ctop/inf/cp/timeServ_jamFracVal_39 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X44Y79.AQ Tcko 0.381 ftop/ctop/inf/cp/timeServ_setRefF$dEMPTY_N + ftop/ctop/inf/cp/timeServ_setRefF/dNotEmptyReg + SLICE_X5Y82.B5 net (fanout=37) 2.314 ftop/ctop/inf/cp/timeServ_setRefF$dEMPTY_N + SLICE_X5Y82.B Tilo 0.068 ftop/ctop/app/appW2/wmi_peerIsReady + ftop/ctop/inf/cp/timeServ_jamFrac_1$whas_inv_01 + SLICE_X18Y89.SR net (fanout=8) 1.362 ftop/ctop/inf/cp/timeServ_jamFrac_1$whas_inv_0 + SLICE_X18Y89.CLK Tsrck 0.455 ftop/ctop/inf/cp/timeServ_jamFracVal<39> + ftop/ctop/inf/cp/timeServ_jamFracVal_39 + ------------------------------------------------- --------------------------- + Total 4.580ns (0.904ns logic, 3.676ns route) + (19.7% logic, 80.3% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.169ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/timeServ_setRefF/dNotEmptyReg (FF) + Destination: ftop/ctop/inf/cp/timeServ_jamFracVal_38 (FF) + Requirement: 5.000ns + Data Path Delay: 4.580ns (Levels of Logic = 1) + Clock Path Skew: -0.216ns (1.470 - 1.686) + Source Clock: ftop/sys0_clk$O_BUFG rising at 0.000ns + Destination Clock: ftop/sys0_clk$O_BUFG rising at 5.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/timeServ_setRefF/dNotEmptyReg to ftop/ctop/inf/cp/timeServ_jamFracVal_38 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X44Y79.AQ Tcko 0.381 ftop/ctop/inf/cp/timeServ_setRefF$dEMPTY_N + ftop/ctop/inf/cp/timeServ_setRefF/dNotEmptyReg + SLICE_X5Y82.B5 net (fanout=37) 2.314 ftop/ctop/inf/cp/timeServ_setRefF$dEMPTY_N + SLICE_X5Y82.B Tilo 0.068 ftop/ctop/app/appW2/wmi_peerIsReady + ftop/ctop/inf/cp/timeServ_jamFrac_1$whas_inv_01 + SLICE_X18Y89.SR net (fanout=8) 1.362 ftop/ctop/inf/cp/timeServ_jamFrac_1$whas_inv_0 + SLICE_X18Y89.CLK Tsrck 0.455 ftop/ctop/inf/cp/timeServ_jamFracVal<39> + ftop/ctop/inf/cp/timeServ_jamFracVal_38 + ------------------------------------------------- --------------------------- + Total 4.580ns (0.904ns logic, 3.676ns route) + (19.7% logic, 80.3% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.209ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/timeServ_refFromRise_10 (FF) + Destination: ftop/ctop/inf/cp/timeServ_delSecond_49 (FF) + Requirement: 5.000ns + Data Path Delay: 4.534ns (Levels of Logic = 3) + Clock Path Skew: -0.222ns (1.482 - 1.704) + Source Clock: ftop/sys0_clk$O_BUFG rising at 0.000ns + Destination Clock: ftop/sys0_clk$O_BUFG rising at 5.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/timeServ_refFromRise_10 to ftop/ctop/inf/cp/timeServ_delSecond_49 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X0Y76.CQ Tcko 0.381 ftop/ctop/inf/cp/timeServ_refFromRise<11> + ftop/ctop/inf/cp/timeServ_refFromRise_10 + SLICE_X3Y77.A1 net (fanout=4) 0.769 ftop/ctop/inf/cp/timeServ_refFromRise<10> + SLICE_X3Y77.COUT Topcya 0.409 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<3> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_lut<0> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<3> + SLICE_X3Y78.CIN net (fanout=1) 0.000 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<3> + SLICE_X3Y78.AMUX Tcina 0.248 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<4> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<4> + SLICE_X19Y76.B5 net (fanout=4) 0.849 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<4> + SLICE_X19Y76.B Tilo 0.068 ftop/ctop/app/appW2/wmi_respF/data1_reg<123> + ftop/ctop/inf/cp/timeServ_ppsExtSync_d2_2_AND_NOT_timeServ_ppsE_ETC___d7011 + SLICE_X9Y91.CE net (fanout=34) 1.492 ftop/ctop/inf/cp/timeServ_delSecond$EN + SLICE_X9Y91.CLK Tceck 0.318 ftop/ctop/inf/cp/timeServ_delSecond<49> + ftop/ctop/inf/cp/timeServ_delSecond_49 + ------------------------------------------------- --------------------------- + Total 4.534ns (1.424ns logic, 3.110ns route) + (31.4% logic, 68.6% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.209ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/timeServ_refFromRise_10 (FF) + Destination: ftop/ctop/inf/cp/timeServ_delSecond_48 (FF) + Requirement: 5.000ns + Data Path Delay: 4.534ns (Levels of Logic = 3) + Clock Path Skew: -0.222ns (1.482 - 1.704) + Source Clock: ftop/sys0_clk$O_BUFG rising at 0.000ns + Destination Clock: ftop/sys0_clk$O_BUFG rising at 5.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/timeServ_refFromRise_10 to ftop/ctop/inf/cp/timeServ_delSecond_48 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X0Y76.CQ Tcko 0.381 ftop/ctop/inf/cp/timeServ_refFromRise<11> + ftop/ctop/inf/cp/timeServ_refFromRise_10 + SLICE_X3Y77.A1 net (fanout=4) 0.769 ftop/ctop/inf/cp/timeServ_refFromRise<10> + SLICE_X3Y77.COUT Topcya 0.409 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<3> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_lut<0> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<3> + SLICE_X3Y78.CIN net (fanout=1) 0.000 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<3> + SLICE_X3Y78.AMUX Tcina 0.248 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<4> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<4> + SLICE_X19Y76.B5 net (fanout=4) 0.849 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<4> + SLICE_X19Y76.B Tilo 0.068 ftop/ctop/app/appW2/wmi_respF/data1_reg<123> + ftop/ctop/inf/cp/timeServ_ppsExtSync_d2_2_AND_NOT_timeServ_ppsE_ETC___d7011 + SLICE_X9Y91.CE net (fanout=34) 1.492 ftop/ctop/inf/cp/timeServ_delSecond$EN + SLICE_X9Y91.CLK Tceck 0.318 ftop/ctop/inf/cp/timeServ_delSecond<49> + ftop/ctop/inf/cp/timeServ_delSecond_48 + ------------------------------------------------- --------------------------- + Total 4.534ns (1.424ns logic, 3.110ns route) + (31.4% logic, 68.6% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.237ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/timeServ_refFromRise_10 (FF) + Destination: ftop/ctop/inf/cp/timeServ_delSecond_49 (FF) + Requirement: 5.000ns + Data Path Delay: 4.506ns (Levels of Logic = 3) + Clock Path Skew: -0.222ns (1.482 - 1.704) + Source Clock: ftop/sys0_clk$O_BUFG rising at 0.000ns + Destination Clock: ftop/sys0_clk$O_BUFG rising at 5.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/timeServ_refFromRise_10 to ftop/ctop/inf/cp/timeServ_delSecond_49 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X0Y76.CQ Tcko 0.381 ftop/ctop/inf/cp/timeServ_refFromRise<11> + ftop/ctop/inf/cp/timeServ_refFromRise_10 + SLICE_X3Y77.A1 net (fanout=4) 0.769 ftop/ctop/inf/cp/timeServ_refFromRise<10> + SLICE_X3Y77.COUT Topcya 0.381 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<3> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_lutdi + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<3> + SLICE_X3Y78.CIN net (fanout=1) 0.000 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<3> + SLICE_X3Y78.AMUX Tcina 0.248 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<4> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<4> + SLICE_X19Y76.B5 net (fanout=4) 0.849 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<4> + SLICE_X19Y76.B Tilo 0.068 ftop/ctop/app/appW2/wmi_respF/data1_reg<123> + ftop/ctop/inf/cp/timeServ_ppsExtSync_d2_2_AND_NOT_timeServ_ppsE_ETC___d7011 + SLICE_X9Y91.CE net (fanout=34) 1.492 ftop/ctop/inf/cp/timeServ_delSecond$EN + SLICE_X9Y91.CLK Tceck 0.318 ftop/ctop/inf/cp/timeServ_delSecond<49> + ftop/ctop/inf/cp/timeServ_delSecond_49 + ------------------------------------------------- --------------------------- + Total 4.506ns (1.396ns logic, 3.110ns route) + (31.0% logic, 69.0% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.237ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/timeServ_refFromRise_10 (FF) + Destination: ftop/ctop/inf/cp/timeServ_delSecond_48 (FF) + Requirement: 5.000ns + Data Path Delay: 4.506ns (Levels of Logic = 3) + Clock Path Skew: -0.222ns (1.482 - 1.704) + Source Clock: ftop/sys0_clk$O_BUFG rising at 0.000ns + Destination Clock: ftop/sys0_clk$O_BUFG rising at 5.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/timeServ_refFromRise_10 to ftop/ctop/inf/cp/timeServ_delSecond_48 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X0Y76.CQ Tcko 0.381 ftop/ctop/inf/cp/timeServ_refFromRise<11> + ftop/ctop/inf/cp/timeServ_refFromRise_10 + SLICE_X3Y77.A1 net (fanout=4) 0.769 ftop/ctop/inf/cp/timeServ_refFromRise<10> + SLICE_X3Y77.COUT Topcya 0.381 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<3> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_lutdi + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<3> + SLICE_X3Y78.CIN net (fanout=1) 0.000 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<3> + SLICE_X3Y78.AMUX Tcina 0.248 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<4> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<4> + SLICE_X19Y76.B5 net (fanout=4) 0.849 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<4> + SLICE_X19Y76.B Tilo 0.068 ftop/ctop/app/appW2/wmi_respF/data1_reg<123> + ftop/ctop/inf/cp/timeServ_ppsExtSync_d2_2_AND_NOT_timeServ_ppsE_ETC___d7011 + SLICE_X9Y91.CE net (fanout=34) 1.492 ftop/ctop/inf/cp/timeServ_delSecond$EN + SLICE_X9Y91.CLK Tceck 0.318 ftop/ctop/inf/cp/timeServ_delSecond<49> + ftop/ctop/inf/cp/timeServ_delSecond_48 + ------------------------------------------------- --------------------------- + Total 4.506ns (1.396ns logic, 3.110ns route) + (31.0% logic, 69.0% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.245ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/timeServ_refFromRise_23 (FF) + Destination: ftop/ctop/inf/cp/timeServ_delSecond_49 (FF) + Requirement: 5.000ns + Data Path Delay: 4.497ns (Levels of Logic = 3) + Clock Path Skew: -0.223ns (1.482 - 1.705) + Source Clock: ftop/sys0_clk$O_BUFG rising at 0.000ns + Destination Clock: ftop/sys0_clk$O_BUFG rising at 5.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/timeServ_refFromRise_23 to ftop/ctop/inf/cp/timeServ_delSecond_49 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X0Y79.DQ Tcko 0.381 ftop/ctop/inf/cp/timeServ_refFromRise<23> + ftop/ctop/inf/cp/timeServ_refFromRise_23 + SLICE_X3Y77.D1 net (fanout=4) 0.822 ftop/ctop/inf/cp/timeServ_refFromRise<23> + SLICE_X3Y77.COUT Topcyd 0.319 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<3> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_lut<3> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<3> + SLICE_X3Y78.CIN net (fanout=1) 0.000 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<3> + SLICE_X3Y78.AMUX Tcina 0.248 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<4> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<4> + SLICE_X19Y76.B5 net (fanout=4) 0.849 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<4> + SLICE_X19Y76.B Tilo 0.068 ftop/ctop/app/appW2/wmi_respF/data1_reg<123> + ftop/ctop/inf/cp/timeServ_ppsExtSync_d2_2_AND_NOT_timeServ_ppsE_ETC___d7011 + SLICE_X9Y91.CE net (fanout=34) 1.492 ftop/ctop/inf/cp/timeServ_delSecond$EN + SLICE_X9Y91.CLK Tceck 0.318 ftop/ctop/inf/cp/timeServ_delSecond<49> + ftop/ctop/inf/cp/timeServ_delSecond_49 + ------------------------------------------------- --------------------------- + Total 4.497ns (1.334ns logic, 3.163ns route) + (29.7% logic, 70.3% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.245ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/timeServ_refFromRise_23 (FF) + Destination: ftop/ctop/inf/cp/timeServ_delSecond_48 (FF) + Requirement: 5.000ns + Data Path Delay: 4.497ns (Levels of Logic = 3) + Clock Path Skew: -0.223ns (1.482 - 1.705) + Source Clock: ftop/sys0_clk$O_BUFG rising at 0.000ns + Destination Clock: ftop/sys0_clk$O_BUFG rising at 5.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/timeServ_refFromRise_23 to ftop/ctop/inf/cp/timeServ_delSecond_48 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X0Y79.DQ Tcko 0.381 ftop/ctop/inf/cp/timeServ_refFromRise<23> + ftop/ctop/inf/cp/timeServ_refFromRise_23 + SLICE_X3Y77.D1 net (fanout=4) 0.822 ftop/ctop/inf/cp/timeServ_refFromRise<23> + SLICE_X3Y77.COUT Topcyd 0.319 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<3> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_lut<3> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<3> + SLICE_X3Y78.CIN net (fanout=1) 0.000 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<3> + SLICE_X3Y78.AMUX Tcina 0.248 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<4> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<4> + SLICE_X19Y76.B5 net (fanout=4) 0.849 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<4> + SLICE_X19Y76.B Tilo 0.068 ftop/ctop/app/appW2/wmi_respF/data1_reg<123> + ftop/ctop/inf/cp/timeServ_ppsExtSync_d2_2_AND_NOT_timeServ_ppsE_ETC___d7011 + SLICE_X9Y91.CE net (fanout=34) 1.492 ftop/ctop/inf/cp/timeServ_delSecond$EN + SLICE_X9Y91.CLK Tceck 0.318 ftop/ctop/inf/cp/timeServ_delSecond<49> + ftop/ctop/inf/cp/timeServ_delSecond_48 + ------------------------------------------------- --------------------------- + Total 4.497ns (1.334ns logic, 3.163ns route) + (29.7% logic, 70.3% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.247ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/timeServ_refFromRise_6 (FF) + Destination: ftop/ctop/inf/cp/timeServ_delSecond_48 (FF) + Requirement: 5.000ns + Data Path Delay: 4.496ns (Levels of Logic = 3) + Clock Path Skew: -0.222ns (1.482 - 1.704) + Source Clock: ftop/sys0_clk$O_BUFG rising at 0.000ns + Destination Clock: ftop/sys0_clk$O_BUFG rising at 5.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/timeServ_refFromRise_6 to ftop/ctop/inf/cp/timeServ_delSecond_48 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X0Y75.CQ Tcko 0.381 ftop/ctop/inf/cp/timeServ_refFromRise<7> + ftop/ctop/inf/cp/timeServ_refFromRise_6 + SLICE_X3Y77.A3 net (fanout=4) 0.731 ftop/ctop/inf/cp/timeServ_refFromRise<6> + SLICE_X3Y77.COUT Topcya 0.409 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<3> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_lut<0> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<3> + SLICE_X3Y78.CIN net (fanout=1) 0.000 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<3> + SLICE_X3Y78.AMUX Tcina 0.248 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<4> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<4> + SLICE_X19Y76.B5 net (fanout=4) 0.849 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<4> + SLICE_X19Y76.B Tilo 0.068 ftop/ctop/app/appW2/wmi_respF/data1_reg<123> + ftop/ctop/inf/cp/timeServ_ppsExtSync_d2_2_AND_NOT_timeServ_ppsE_ETC___d7011 + SLICE_X9Y91.CE net (fanout=34) 1.492 ftop/ctop/inf/cp/timeServ_delSecond$EN + SLICE_X9Y91.CLK Tceck 0.318 ftop/ctop/inf/cp/timeServ_delSecond<49> + ftop/ctop/inf/cp/timeServ_delSecond_48 + ------------------------------------------------- --------------------------- + Total 4.496ns (1.424ns logic, 3.072ns route) + (31.7% logic, 68.3% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.247ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/timeServ_refFromRise_6 (FF) + Destination: ftop/ctop/inf/cp/timeServ_delSecond_49 (FF) + Requirement: 5.000ns + Data Path Delay: 4.496ns (Levels of Logic = 3) + Clock Path Skew: -0.222ns (1.482 - 1.704) + Source Clock: ftop/sys0_clk$O_BUFG rising at 0.000ns + Destination Clock: ftop/sys0_clk$O_BUFG rising at 5.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/timeServ_refFromRise_6 to ftop/ctop/inf/cp/timeServ_delSecond_49 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X0Y75.CQ Tcko 0.381 ftop/ctop/inf/cp/timeServ_refFromRise<7> + ftop/ctop/inf/cp/timeServ_refFromRise_6 + SLICE_X3Y77.A3 net (fanout=4) 0.731 ftop/ctop/inf/cp/timeServ_refFromRise<6> + SLICE_X3Y77.COUT Topcya 0.409 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<3> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_lut<0> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<3> + SLICE_X3Y78.CIN net (fanout=1) 0.000 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<3> + SLICE_X3Y78.AMUX Tcina 0.248 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<4> + ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<4> + SLICE_X19Y76.B5 net (fanout=4) 0.849 ftop/ctop/inf/cp/Mcompar_timeServ_refFromRise_3_ULT_200200000___d50_cy<4> + SLICE_X19Y76.B Tilo 0.068 ftop/ctop/app/appW2/wmi_respF/data1_reg<123> + ftop/ctop/inf/cp/timeServ_ppsExtSync_d2_2_AND_NOT_timeServ_ppsE_ETC___d7011 + SLICE_X9Y91.CE net (fanout=34) 1.492 ftop/ctop/inf/cp/timeServ_delSecond$EN + SLICE_X9Y91.CLK Tceck 0.318 ftop/ctop/inf/cp/timeServ_delSecond<49> + ftop/ctop/inf/cp/timeServ_delSecond_49 + ------------------------------------------------- --------------------------- + Total 4.496ns (1.424ns logic, 3.072ns route) + (31.7% logic, 68.3% route) + +-------------------------------------------------------------------------------- + +Hold Paths: TS_SYS0CLK = PERIOD TIMEGRP "SYS0CLK" 200 MHz HIGH 50%; +-------------------------------------------------------------------------------- +Slack (hold path): 0.048ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/ctop/inf/cp/timeServ_fracSeconds_1 (FF) + Destination: ftop/ctop/inf/cp/timeServ_lastSecond_1 (FF) + Requirement: 0.000ns + Data Path Delay: 0.155ns (Levels of Logic = 1) + Clock Path Skew: 0.107ns (0.766 - 0.659) + Source Clock: ftop/sys0_clk$O_BUFG rising at 5.000ns + Destination Clock: ftop/sys0_clk$O_BUFG rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/ctop/inf/cp/timeServ_fracSeconds_1 to ftop/ctop/inf/cp/timeServ_lastSecond_1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X8Y81.BQ Tcko 0.115 ftop/ctop/inf/cp/timeServ_fracSeconds<3> + ftop/ctop/inf/cp/timeServ_fracSeconds_1 + SLICE_X9Y79.C5 net (fanout=4) 0.122 ftop/ctop/inf/cp/timeServ_fracSeconds<1> + SLICE_X9Y79.CLK Tah (-Th) 0.082 ftop/ctop/inf/cp/timeServ_delSecond<3> + ftop/ctop/inf/cp/timeServ_fracSeconds<1>_rt + ftop/ctop/inf/cp/timeServ_lastSecond_1 + ------------------------------------------------- --------------------------- + Total 0.155ns (0.033ns logic, 0.122ns route) + (21.3% logic, 78.7% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.077ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/ctop/inf/cp/timeServ_fracSeconds_0 (FF) + Destination: ftop/ctop/inf/cp/timeServ_delSecond_1 (FF) + Requirement: 0.000ns + Data Path Delay: 0.184ns (Levels of Logic = 1) + Clock Path Skew: 0.107ns (0.766 - 0.659) + Source Clock: ftop/sys0_clk$O_BUFG rising at 5.000ns + Destination Clock: ftop/sys0_clk$O_BUFG rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/ctop/inf/cp/timeServ_fracSeconds_0 to ftop/ctop/inf/cp/timeServ_delSecond_1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X8Y81.AQ Tcko 0.115 ftop/ctop/inf/cp/timeServ_fracSeconds<3> + ftop/ctop/inf/cp/timeServ_fracSeconds_0 + SLICE_X9Y79.AX net (fanout=4) 0.102 ftop/ctop/inf/cp/timeServ_fracSeconds<0> + SLICE_X9Y79.CLK Tckdi (-Th) 0.033 ftop/ctop/inf/cp/timeServ_delSecond<3> + ftop/ctop/inf/cp/Msub_timeServ_delSecond$D_IN_cy<3> + ftop/ctop/inf/cp/timeServ_delSecond_1 + ------------------------------------------------- --------------------------- + Total 0.184ns (0.082ns logic, 0.102ns route) + (44.6% logic, 55.4% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.082ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/ctop/inf/cp/timeServ_fracSeconds_3 (FF) + Destination: ftop/ctop/inf/cp/timeServ_lastSecond_3 (FF) + Requirement: 0.000ns + Data Path Delay: 0.189ns (Levels of Logic = 1) + Clock Path Skew: 0.107ns (0.766 - 0.659) + Source Clock: ftop/sys0_clk$O_BUFG rising at 5.000ns + Destination Clock: ftop/sys0_clk$O_BUFG rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/ctop/inf/cp/timeServ_fracSeconds_3 to ftop/ctop/inf/cp/timeServ_lastSecond_3 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X8Y81.DQ Tcko 0.115 ftop/ctop/inf/cp/timeServ_fracSeconds<3> + ftop/ctop/inf/cp/timeServ_fracSeconds_3 + SLICE_X9Y79.A4 net (fanout=4) 0.156 ftop/ctop/inf/cp/timeServ_fracSeconds<3> + SLICE_X9Y79.CLK Tah (-Th) 0.082 ftop/ctop/inf/cp/timeServ_delSecond<3> + ftop/ctop/inf/cp/timeServ_fracSeconds<3>_rt + ftop/ctop/inf/cp/timeServ_lastSecond_3 + ------------------------------------------------- --------------------------- + Total 0.189ns (0.033ns logic, 0.156ns route) + (17.5% logic, 82.5% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.086ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/ctop/inf/cp/timeServ_fracSeconds_2 (FF) + Destination: ftop/ctop/inf/cp/timeServ_delSecond_3 (FF) + Requirement: 0.000ns + Data Path Delay: 0.193ns (Levels of Logic = 1) + Clock Path Skew: 0.107ns (0.766 - 0.659) + Source Clock: ftop/sys0_clk$O_BUFG rising at 5.000ns + Destination Clock: ftop/sys0_clk$O_BUFG rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/ctop/inf/cp/timeServ_fracSeconds_2 to ftop/ctop/inf/cp/timeServ_delSecond_3 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X8Y81.CQ Tcko 0.115 ftop/ctop/inf/cp/timeServ_fracSeconds<3> + ftop/ctop/inf/cp/timeServ_fracSeconds_2 + SLICE_X9Y79.CX net (fanout=4) 0.107 ftop/ctop/inf/cp/timeServ_fracSeconds<2> + SLICE_X9Y79.CLK Tckdi (-Th) 0.029 ftop/ctop/inf/cp/timeServ_delSecond<3> + ftop/ctop/inf/cp/Msub_timeServ_delSecond$D_IN_cy<3> + ftop/ctop/inf/cp/timeServ_delSecond_3 + ------------------------------------------------- --------------------------- + Total 0.193ns (0.086ns logic, 0.107ns route) + (44.6% logic, 55.4% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.091ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/dram0/memc_mem_rst_p/reset_hold_3 (FF) + Destination: ftop/dram0/memc_mem_rst_p/reset_hold_4 (FF) + Requirement: 0.000ns + Data Path Delay: 0.103ns (Levels of Logic = 0) + Clock Path Skew: 0.012ns (0.066 - 0.054) + Source Clock: ftop/sys0_clk$O_BUFG rising at 5.000ns + Destination Clock: ftop/sys0_clk$O_BUFG rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/dram0/memc_mem_rst_p/reset_hold_3 to ftop/dram0/memc_mem_rst_p/reset_hold_4 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X143Y78.DQ Tcko 0.098 ftop/dram0/memc_mem_rst_p/reset_hold<3> + ftop/dram0/memc_mem_rst_p/reset_hold_3 + SLICE_X142Y78.AX net (fanout=1) 0.094 ftop/dram0/memc_mem_rst_p/reset_hold<3> + SLICE_X142Y78.CLK Tckdi (-Th) 0.089 ftop/dram0/memc_mem_rst_p/reset_hold<7> + ftop/dram0/memc_mem_rst_p/reset_hold_4 + ------------------------------------------------- --------------------------- + Total 0.103ns (0.009ns logic, 0.094ns route) + (8.7% logic, 91.3% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.092ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/dram0/memc_memc/u_iodelay_ctrl/rst_ref_sync_r_3 (FF) + Destination: ftop/dram0/memc_memc/u_iodelay_ctrl/rst_ref_sync_r_4 (FF) + Requirement: 0.000ns + Data Path Delay: 0.103ns (Levels of Logic = 0) + Clock Path Skew: 0.011ns (0.060 - 0.049) + Source Clock: ftop/sys0_clk$O_BUFG rising at 5.000ns + Destination Clock: ftop/sys0_clk$O_BUFG rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/dram0/memc_memc/u_iodelay_ctrl/rst_ref_sync_r_3 to ftop/dram0/memc_memc/u_iodelay_ctrl/rst_ref_sync_r_4 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X117Y107.DQ Tcko 0.098 ftop/dram0/memc_memc/u_iodelay_ctrl/rst_ref_sync_r<3> + ftop/dram0/memc_memc/u_iodelay_ctrl/rst_ref_sync_r_3 + SLICE_X116Y107.AX net (fanout=1) 0.094 ftop/dram0/memc_memc/u_iodelay_ctrl/rst_ref_sync_r<3> + SLICE_X116Y107.CLK Tckdi (-Th) 0.089 ftop/dram0/memc_memc/u_iodelay_ctrl/rst_ref_sync_r<7> + ftop/dram0/memc_memc/u_iodelay_ctrl/rst_ref_sync_r_4 + ------------------------------------------------- --------------------------- + Total 0.103ns (0.009ns logic, 0.094ns route) + (8.7% logic, 91.3% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.092ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/dram0/memc_memc/u_iodelay_ctrl/rst_ref_sync_r_11 (FF) + Destination: ftop/dram0/memc_memc/u_iodelay_ctrl/rst_ref_sync_r_12 (FF) + Requirement: 0.000ns + Data Path Delay: 0.103ns (Levels of Logic = 0) + Clock Path Skew: 0.011ns (0.064 - 0.053) + Source Clock: ftop/sys0_clk$O_BUFG rising at 5.000ns + Destination Clock: ftop/sys0_clk$O_BUFG rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/dram0/memc_memc/u_iodelay_ctrl/rst_ref_sync_r_11 to ftop/dram0/memc_memc/u_iodelay_ctrl/rst_ref_sync_r_12 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X111Y111.DQ Tcko 0.098 ftop/dram0/memc_memc/u_iodelay_ctrl/rst_ref_sync_r<11> + ftop/dram0/memc_memc/u_iodelay_ctrl/rst_ref_sync_r_11 + SLICE_X110Y111.AX net (fanout=1) 0.094 ftop/dram0/memc_memc/u_iodelay_ctrl/rst_ref_sync_r<11> + SLICE_X110Y111.CLK Tckdi (-Th) 0.089 ftop/dram0/memc_memc/u_iodelay_ctrl/rst_ref_sync_r<14> + ftop/dram0/memc_memc/u_iodelay_ctrl/rst_ref_sync_r_12 + ------------------------------------------------- --------------------------- + Total 0.103ns (0.009ns logic, 0.094ns route) + (8.7% logic, 91.3% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.095ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/ctop/inf/cp/timeServ_setRefF/dDoutReg_7 (FF) + Destination: ftop/ctop/inf/cp/timeServ_jamFracVal_23 (FF) + Requirement: 0.000ns + Data Path Delay: 0.107ns (Levels of Logic = 0) + Clock Path Skew: 0.012ns (0.066 - 0.054) + Source Clock: ftop/sys0_clk$O_BUFG rising at 5.000ns + Destination Clock: ftop/sys0_clk$O_BUFG rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/ctop/inf/cp/timeServ_setRefF/dDoutReg_7 to ftop/ctop/inf/cp/timeServ_jamFracVal_23 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X5Y81.DQ Tcko 0.098 ftop/ctop/inf/cp/timeServ_setRefF$dD_OUT<7> + ftop/ctop/inf/cp/timeServ_setRefF/dDoutReg_7 + SLICE_X4Y83.DX net (fanout=1) 0.098 ftop/ctop/inf/cp/timeServ_setRefF$dD_OUT<7> + SLICE_X4Y83.CLK Tckdi (-Th) 0.089 ftop/ctop/inf/cp/timeServ_jamFracVal<23> + ftop/ctop/inf/cp/timeServ_jamFracVal_23 + ------------------------------------------------- --------------------------- + Total 0.107ns (0.009ns logic, 0.098ns route) + (8.4% logic, 91.6% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.095ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/ctop/inf/cp/timeServ_setRefF/dDoutReg_5 (FF) + Destination: ftop/ctop/inf/cp/timeServ_jamFracVal_21 (FF) + Requirement: 0.000ns + Data Path Delay: 0.107ns (Levels of Logic = 0) + Clock Path Skew: 0.012ns (0.066 - 0.054) + Source Clock: ftop/sys0_clk$O_BUFG rising at 5.000ns + Destination Clock: ftop/sys0_clk$O_BUFG rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/ctop/inf/cp/timeServ_setRefF/dDoutReg_5 to ftop/ctop/inf/cp/timeServ_jamFracVal_21 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X5Y81.BQ Tcko 0.098 ftop/ctop/inf/cp/timeServ_setRefF$dD_OUT<7> + ftop/ctop/inf/cp/timeServ_setRefF/dDoutReg_5 + SLICE_X4Y83.BX net (fanout=1) 0.098 ftop/ctop/inf/cp/timeServ_setRefF$dD_OUT<5> + SLICE_X4Y83.CLK Tckdi (-Th) 0.089 ftop/ctop/inf/cp/timeServ_jamFracVal<23> + ftop/ctop/inf/cp/timeServ_jamFracVal_21 + ------------------------------------------------- --------------------------- + Total 0.107ns (0.009ns logic, 0.098ns route) + (8.4% logic, 91.6% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.105ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/ctop/inf/cp/timeServ_fracSeconds_1 (FF) + Destination: ftop/ctop/inf/cp/timeServ_delSecond_2 (FF) + Requirement: 0.000ns + Data Path Delay: 0.212ns (Levels of Logic = 1) + Clock Path Skew: 0.107ns (0.766 - 0.659) + Source Clock: ftop/sys0_clk$O_BUFG rising at 5.000ns + Destination Clock: ftop/sys0_clk$O_BUFG rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/ctop/inf/cp/timeServ_fracSeconds_1 to ftop/ctop/inf/cp/timeServ_delSecond_2 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X8Y81.BQ Tcko 0.115 ftop/ctop/inf/cp/timeServ_fracSeconds<3> + ftop/ctop/inf/cp/timeServ_fracSeconds_1 + SLICE_X9Y79.BX net (fanout=4) 0.109 ftop/ctop/inf/cp/timeServ_fracSeconds<1> + SLICE_X9Y79.CLK Tckdi (-Th) 0.012 ftop/ctop/inf/cp/timeServ_delSecond<3> + ftop/ctop/inf/cp/Msub_timeServ_delSecond$D_IN_cy<3> + ftop/ctop/inf/cp/timeServ_delSecond_2 + ------------------------------------------------- --------------------------- + Total 0.212ns (0.103ns logic, 0.109ns route) + (48.6% logic, 51.4% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.109ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/ctop/inf/cp/timeServ_rollingPPSIn/sync/sToggleReg (FF) + Destination: ftop/ctop/inf/cp/timeServ_rollingPPSIn/sync/sToggleReg (FF) + Requirement: 0.000ns + Data Path Delay: 0.109ns (Levels of Logic = 1) + Clock Path Skew: 0.000ns + Source Clock: ftop/sys0_clk$O_BUFG rising at 5.000ns + Destination Clock: ftop/sys0_clk$O_BUFG rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/ctop/inf/cp/timeServ_rollingPPSIn/sync/sToggleReg to ftop/ctop/inf/cp/timeServ_rollingPPSIn/sync/sToggleReg + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X45Y33.AQ Tcko 0.098 ftop/ctop/inf/cp/timeServ_rollingPPSIn/sync/sToggleReg + ftop/ctop/inf/cp/timeServ_rollingPPSIn/sync/sToggleReg + SLICE_X45Y33.A5 net (fanout=3) 0.066 ftop/ctop/inf/cp/timeServ_rollingPPSIn/sync/sToggleReg + SLICE_X45Y33.CLK Tah (-Th) 0.055 ftop/ctop/inf/cp/timeServ_rollingPPSIn/sync/sToggleReg + ftop/ctop/inf/cp/timeServ_rollingPPSIn/sync/sToggleReg_INV_408_o1_INV_0 + ftop/ctop/inf/cp/timeServ_rollingPPSIn/sync/sToggleReg + ------------------------------------------------- --------------------------- + Total 0.109ns (0.043ns logic, 0.066ns route) + (39.4% logic, 60.6% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.111ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/ctop/inf/cp/timeServ_setRefF/dGDeqPtr1_2 (FF) + Destination: ftop/ctop/inf/cp/timeServ_setRefF/dGDeqPtr1_2 (FF) + Requirement: 0.000ns + Data Path Delay: 0.111ns (Levels of Logic = 1) + Clock Path Skew: 0.000ns + Source Clock: ftop/sys0_clk$O_BUFG rising at 5.000ns + Destination Clock: ftop/sys0_clk$O_BUFG rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/ctop/inf/cp/timeServ_setRefF/dGDeqPtr1_2 to ftop/ctop/inf/cp/timeServ_setRefF/dGDeqPtr1_2 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X44Y77.CQ Tcko 0.115 ftop/ctop/inf/cp/timeServ_setRefF/dGDeqPtr1<2> + ftop/ctop/inf/cp/timeServ_setRefF/dGDeqPtr1_2 + SLICE_X44Y77.C5 net (fanout=2) 0.072 ftop/ctop/inf/cp/timeServ_setRefF/dGDeqPtr1<2> + SLICE_X44Y77.CLK Tah (-Th) 0.076 ftop/ctop/inf/cp/timeServ_setRefF/dGDeqPtr1<2> + ftop/ctop/inf/cp/timeServ_setRefF/Mxor_dGDeqPtr1[0]_dGDeqPtr1[2]_xor_20_OUT_1_xo<0>1 + ftop/ctop/inf/cp/timeServ_setRefF/dGDeqPtr1_2 + ------------------------------------------------- --------------------------- + Total 0.111ns (0.039ns logic, 0.072ns route) + (35.1% logic, 64.9% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.113ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/ctop/inf/cp/timeServ_ppsEdgeCount_2 (FF) + Destination: ftop/ctop/inf/cp/timeServ_rollingPPSIn/sDataSyncIn_2 (FF) + Requirement: 0.000ns + Data Path Delay: 0.125ns (Levels of Logic = 0) + Clock Path Skew: 0.012ns (0.066 - 0.054) + Source Clock: ftop/sys0_clk$O_BUFG rising at 5.000ns + Destination Clock: ftop/sys0_clk$O_BUFG rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/ctop/inf/cp/timeServ_ppsEdgeCount_2 to ftop/ctop/inf/cp/timeServ_rollingPPSIn/sDataSyncIn_2 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X41Y37.CQ Tcko 0.098 ftop/ctop/inf/cp/timeServ_ppsEdgeCount<3> + ftop/ctop/inf/cp/timeServ_ppsEdgeCount_2 + SLICE_X41Y39.CX net (fanout=2) 0.103 ftop/ctop/inf/cp/timeServ_ppsEdgeCount<2> + SLICE_X41Y39.CLK Tckdi (-Th) 0.076 ftop/ctop/inf/cp/timeServ_rollingPPSIn/sDataSyncIn<3> + ftop/ctop/inf/cp/timeServ_rollingPPSIn/sDataSyncIn_2 + ------------------------------------------------- --------------------------- + Total 0.125ns (0.022ns logic, 0.103ns route) + (17.6% logic, 82.4% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.113ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/ctop/inf/cp/timeServ_ppsEdgeCount_0 (FF) + Destination: ftop/ctop/inf/cp/timeServ_rollingPPSIn/sDataSyncIn_0 (FF) + Requirement: 0.000ns + Data Path Delay: 0.125ns (Levels of Logic = 0) + Clock Path Skew: 0.012ns (0.066 - 0.054) + Source Clock: ftop/sys0_clk$O_BUFG rising at 5.000ns + Destination Clock: ftop/sys0_clk$O_BUFG rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/ctop/inf/cp/timeServ_ppsEdgeCount_0 to ftop/ctop/inf/cp/timeServ_rollingPPSIn/sDataSyncIn_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X41Y37.AQ Tcko 0.098 ftop/ctop/inf/cp/timeServ_ppsEdgeCount<3> + ftop/ctop/inf/cp/timeServ_ppsEdgeCount_0 + SLICE_X41Y39.AX net (fanout=2) 0.103 ftop/ctop/inf/cp/timeServ_ppsEdgeCount<0> + SLICE_X41Y39.CLK Tckdi (-Th) 0.076 ftop/ctop/inf/cp/timeServ_rollingPPSIn/sDataSyncIn<3> + ftop/ctop/inf/cp/timeServ_rollingPPSIn/sDataSyncIn_0 + ------------------------------------------------- --------------------------- + Total 0.125ns (0.022ns logic, 0.103ns route) + (17.6% logic, 82.4% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.114ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/ctop/inf/cp/timeServ_setRefF/dGDeqPtr1_1 (FF) + Destination: ftop/ctop/inf/cp/timeServ_setRefF/dGDeqPtr_1 (FF) + Requirement: 0.000ns + Data Path Delay: 0.126ns (Levels of Logic = 0) + Clock Path Skew: 0.012ns (0.066 - 0.054) + Source Clock: ftop/sys0_clk$O_BUFG rising at 5.000ns + Destination Clock: ftop/sys0_clk$O_BUFG rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/ctop/inf/cp/timeServ_setRefF/dGDeqPtr1_1 to ftop/ctop/inf/cp/timeServ_setRefF/dGDeqPtr_1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X44Y77.BQ Tcko 0.115 ftop/ctop/inf/cp/timeServ_setRefF/dGDeqPtr1<2> + ftop/ctop/inf/cp/timeServ_setRefF/dGDeqPtr1_1 + SLICE_X44Y78.BX net (fanout=2) 0.100 ftop/ctop/inf/cp/timeServ_setRefF/dGDeqPtr1<1> + SLICE_X44Y78.CLK Tckdi (-Th) 0.089 ftop/ctop/inf/cp/timeServ_setRefF/dGDeqPtr<2> + ftop/ctop/inf/cp/timeServ_setRefF/dGDeqPtr_1 + ------------------------------------------------- --------------------------- + Total 0.126ns (0.026ns logic, 0.100ns route) + (20.6% logic, 79.4% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.114ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/ctop/inf/cp/timeServ_setRefF/dGDeqPtr1_2 (FF) + Destination: ftop/ctop/inf/cp/timeServ_setRefF/dGDeqPtr_2 (FF) + Requirement: 0.000ns + Data Path Delay: 0.126ns (Levels of Logic = 0) + Clock Path Skew: 0.012ns (0.066 - 0.054) + Source Clock: ftop/sys0_clk$O_BUFG rising at 5.000ns + Destination Clock: ftop/sys0_clk$O_BUFG rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/ctop/inf/cp/timeServ_setRefF/dGDeqPtr1_2 to ftop/ctop/inf/cp/timeServ_setRefF/dGDeqPtr_2 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X44Y77.CQ Tcko 0.115 ftop/ctop/inf/cp/timeServ_setRefF/dGDeqPtr1<2> + ftop/ctop/inf/cp/timeServ_setRefF/dGDeqPtr1_2 + SLICE_X44Y78.CX net (fanout=2) 0.100 ftop/ctop/inf/cp/timeServ_setRefF/dGDeqPtr1<2> + SLICE_X44Y78.CLK Tckdi (-Th) 0.089 ftop/ctop/inf/cp/timeServ_setRefF/dGDeqPtr<2> + ftop/ctop/inf/cp/timeServ_setRefF/dGDeqPtr_2 + ------------------------------------------------- --------------------------- + Total 0.126ns (0.026ns logic, 0.100ns route) + (20.6% logic, 79.4% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.114ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/ctop/inf/cp/timeServ_fracSeconds_1 (FF) + Destination: ftop/ctop/inf/cp/timeServ_delSecond_1 (FF) + Requirement: 0.000ns + Data Path Delay: 0.221ns (Levels of Logic = 1) + Clock Path Skew: 0.107ns (0.766 - 0.659) + Source Clock: ftop/sys0_clk$O_BUFG rising at 5.000ns + Destination Clock: ftop/sys0_clk$O_BUFG rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/ctop/inf/cp/timeServ_fracSeconds_1 to ftop/ctop/inf/cp/timeServ_delSecond_1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X8Y81.BQ Tcko 0.115 ftop/ctop/inf/cp/timeServ_fracSeconds<3> + ftop/ctop/inf/cp/timeServ_fracSeconds_1 + SLICE_X9Y79.B5 net (fanout=4) 0.124 ftop/ctop/inf/cp/timeServ_fracSeconds<1> + SLICE_X9Y79.CLK Tah (-Th) 0.018 ftop/ctop/inf/cp/timeServ_delSecond<3> + ftop/ctop/inf/cp/Msub_timeServ_delSecond$D_IN_lut<1> + ftop/ctop/inf/cp/Msub_timeServ_delSecond$D_IN_cy<3> + ftop/ctop/inf/cp/timeServ_delSecond_1 + ------------------------------------------------- --------------------------- + Total 0.221ns (0.097ns logic, 0.124ns route) + (43.9% logic, 56.1% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.114ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/ctop/inf/cp/timeServ_nowInCC/sync/sToggleReg (FF) + Destination: ftop/ctop/inf/cp/timeServ_nowInCC/sync/sToggleReg (FF) + Requirement: 0.000ns + Data Path Delay: 0.114ns (Levels of Logic = 1) + Clock Path Skew: 0.000ns + Source Clock: ftop/sys0_clk$O_BUFG rising at 5.000ns + Destination Clock: ftop/sys0_clk$O_BUFG rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/ctop/inf/cp/timeServ_nowInCC/sync/sToggleReg to ftop/ctop/inf/cp/timeServ_nowInCC/sync/sToggleReg + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X41Y82.AQ Tcko 0.098 ftop/ctop/inf/cp/timeServ_nowInCC/sync/sToggleReg + ftop/ctop/inf/cp/timeServ_nowInCC/sync/sToggleReg + SLICE_X41Y82.A5 net (fanout=3) 0.071 ftop/ctop/inf/cp/timeServ_nowInCC/sync/sToggleReg + SLICE_X41Y82.CLK Tah (-Th) 0.055 ftop/ctop/inf/cp/timeServ_nowInCC/sync/sToggleReg + ftop/ctop/inf/cp/timeServ_nowInCC/sync/sToggleReg_INV_408_o1_INV_0 + ftop/ctop/inf/cp/timeServ_nowInCC/sync/sToggleReg + ------------------------------------------------- --------------------------- + Total 0.114ns (0.043ns logic, 0.071ns route) + (37.7% logic, 62.3% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.115ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/ctop/inf/cp/timeServ_ppsEdgeCount_4 (FF) + Destination: ftop/ctop/inf/cp/timeServ_rollingPPSIn/sDataSyncIn_4 (FF) + Requirement: 0.000ns + Data Path Delay: 0.127ns (Levels of Logic = 1) + Clock Path Skew: 0.012ns (0.066 - 0.054) + Source Clock: ftop/sys0_clk$O_BUFG rising at 5.000ns + Destination Clock: ftop/sys0_clk$O_BUFG rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/ctop/inf/cp/timeServ_ppsEdgeCount_4 to ftop/ctop/inf/cp/timeServ_rollingPPSIn/sDataSyncIn_4 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X41Y38.AQ Tcko 0.098 ftop/ctop/inf/cp/timeServ_ppsEdgeCount<7> + ftop/ctop/inf/cp/timeServ_ppsEdgeCount_4 + SLICE_X41Y39.A5 net (fanout=2) 0.111 ftop/ctop/inf/cp/timeServ_ppsEdgeCount<4> + SLICE_X41Y39.CLK Tah (-Th) 0.082 ftop/ctop/inf/cp/timeServ_rollingPPSIn/sDataSyncIn<3> + ftop/ctop/inf/cp/timeServ_ppsEdgeCount<4>_rt + ftop/ctop/inf/cp/timeServ_rollingPPSIn/sDataSyncIn_4 + ------------------------------------------------- --------------------------- + Total 0.127ns (0.016ns logic, 0.111ns route) + (12.6% logic, 87.4% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.115ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/ctop/inf/cp/timeServ_fracSeconds_0 (FF) + Destination: ftop/ctop/inf/cp/timeServ_delSecond_2 (FF) + Requirement: 0.000ns + Data Path Delay: 0.222ns (Levels of Logic = 1) + Clock Path Skew: 0.107ns (0.766 - 0.659) + Source Clock: ftop/sys0_clk$O_BUFG rising at 5.000ns + Destination Clock: ftop/sys0_clk$O_BUFG rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/ctop/inf/cp/timeServ_fracSeconds_0 to ftop/ctop/inf/cp/timeServ_delSecond_2 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X8Y81.AQ Tcko 0.115 ftop/ctop/inf/cp/timeServ_fracSeconds<3> + ftop/ctop/inf/cp/timeServ_fracSeconds_0 + SLICE_X9Y79.AX net (fanout=4) 0.102 ftop/ctop/inf/cp/timeServ_fracSeconds<0> + SLICE_X9Y79.CLK Tckdi (-Th) -0.005 ftop/ctop/inf/cp/timeServ_delSecond<3> + ftop/ctop/inf/cp/Msub_timeServ_delSecond$D_IN_cy<3> + ftop/ctop/inf/cp/timeServ_delSecond_2 + ------------------------------------------------- --------------------------- + Total 0.222ns (0.120ns logic, 0.102ns route) + (54.1% logic, 45.9% route) + +-------------------------------------------------------------------------------- + +Component Switching Limit Checks: TS_SYS0CLK = PERIOD TIMEGRP "SYS0CLK" 200 MHz HIGH 50%; +-------------------------------------------------------------------------------- +Slack: 0.239ns (period - min period limit) + Period: 5.000ns + Min period limit: 4.761ns (210.040MHz) (Tdlycper_REFCLK) + Physical resource: ftop/dram0/memc_memc/u_iodelay_ctrl/u_idelayctrl_MapLib_replicate1/REFCLK + Logical resource: ftop/dram0/memc_memc/u_iodelay_ctrl/u_idelayctrl_MapLib_replicate1/REFCLK + Location pin: IDELAYCTRL_X1Y3.REFCLK + Clock network: ftop/sys0_clk$O_BUFG +-------------------------------------------------------------------------------- +Slack: 0.239ns (period - min period limit) + Period: 5.000ns + Min period limit: 4.761ns (210.040MHz) (Tdlycper_REFCLK) + Physical resource: ftop/dram0/memc_memc/u_iodelay_ctrl/u_idelayctrl_MapLib_replicate2/REFCLK + Logical resource: ftop/dram0/memc_memc/u_iodelay_ctrl/u_idelayctrl_MapLib_replicate2/REFCLK + Location pin: IDELAYCTRL_X1Y4.REFCLK + Clock network: ftop/sys0_clk$O_BUFG +-------------------------------------------------------------------------------- +Slack: 0.239ns (period - min period limit) + Period: 5.000ns + Min period limit: 4.761ns (210.040MHz) (Tdlycper_REFCLK) + Physical resource: ftop/dram0/memc_memc/u_iodelay_ctrl/u_idelayctrl_MapLib_replicate5/REFCLK + Logical resource: ftop/dram0/memc_memc/u_iodelay_ctrl/u_idelayctrl_MapLib_replicate5/REFCLK + Location pin: IDELAYCTRL_X2Y1.REFCLK + Clock network: ftop/sys0_clk$O_BUFG +-------------------------------------------------------------------------------- +Slack: 0.239ns (period - min period limit) + Period: 5.000ns + Min period limit: 4.761ns (210.040MHz) (Tdlycper_REFCLK) + Physical resource: ftop/dram0/memc_memc/u_iodelay_ctrl/u_idelayctrl_MapLib_replicate7/REFCLK + Logical resource: ftop/dram0/memc_memc/u_iodelay_ctrl/u_idelayctrl_MapLib_replicate7/REFCLK + Location pin: IDELAYCTRL_X2Y3.REFCLK + Clock network: ftop/sys0_clk$O_BUFG +-------------------------------------------------------------------------------- +Slack: 1.072ns (period - min period limit) + Period: 2.500ns + Min period limit: 1.428ns (700.280MHz) (Tmmcmper_CLKOUT(Foutmax)) + Physical resource: ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv/CLKOUT0 + Logical resource: ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv/CLKOUT0 + Location pin: MMCM_ADV_X0Y6.CLKOUT0 + Clock network: ftop/dram0/memc_memc/u_infrastructure/clk_mem_pll +-------------------------------------------------------------------------------- +Slack: 1.072ns (period - min period limit) + Period: 2.500ns + Min period limit: 1.428ns (700.280MHz) (Tmmcmper_CLKOUT(Foutmax)) + Physical resource: ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv/CLKOUT2 + Logical resource: ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv/CLKOUT2 + Location pin: MMCM_ADV_X0Y6.CLKOUT2 + Clock network: ftop/dram0/memc_memc/clk_wr_i +-------------------------------------------------------------------------------- +Slack: 2.200ns (period - (min low pulse limit / (low pulse / period))) + Period: 5.000ns + Low pulse: 2.500ns + Low pulse limit: 1.400ns (Tdcmpw_CLKIN_200_250) + Physical resource: ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv/CLKIN1 + Logical resource: ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv/CLKIN1 + Location pin: MMCM_ADV_X0Y6.CLKIN1 + Clock network: ftop/sys0_clk$O_BUFG +-------------------------------------------------------------------------------- +Slack: 2.200ns (period - (min high pulse limit / (high pulse / period))) + Period: 5.000ns + High pulse: 2.500ns + High pulse limit: 1.400ns (Tdcmpw_CLKIN_200_250) + Physical resource: ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv/CLKIN1 + Logical resource: ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv/CLKIN1 + Location pin: MMCM_ADV_X0Y6.CLKIN1 + Clock network: ftop/sys0_clk$O_BUFG +-------------------------------------------------------------------------------- +Slack: 3.571ns (period - min period limit) + Period: 5.000ns + Min period limit: 1.429ns (699.790MHz) (Tbcper_I) + Physical resource: ftop/sys0_clk$O_BUFG/I0 + Logical resource: ftop/sys0_clk$O_BUFG/I0 + Location pin: BUFGCTRL_X0Y1.I0 + Clock network: ftop/sys0_clk$O +-------------------------------------------------------------------------------- +Slack: 3.572ns (period - min period limit) + Period: 5.000ns + Min period limit: 1.428ns (700.280MHz) (Tmmcmper_CLKIN(Finmax)) + Physical resource: ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv/CLKIN1 + Logical resource: ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv/CLKIN1 + Location pin: MMCM_ADV_X0Y6.CLKIN1 + Clock network: ftop/sys0_clk$O_BUFG +-------------------------------------------------------------------------------- +Slack: 3.572ns (period - min period limit) + Period: 5.000ns + Min period limit: 1.428ns (700.280MHz) (Tmmcmper_CLKFBOUT(Foutmax)) + Physical resource: ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv/CLKFBOUT + Logical resource: ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv/CLKFBOUT + Location pin: MMCM_ADV_X0Y6.CLKFBOUT + Clock network: ftop/dram0/memc_memc/u_infrastructure/clkfbout_pll +-------------------------------------------------------------------------------- +Slack: 3.572ns (period - min period limit) + Period: 5.000ns + Min period limit: 1.428ns (700.280MHz) (Tmmcmper_CLKOUT(Foutmax)) + Physical resource: ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv/CLKOUT1 + Logical resource: ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv/CLKOUT1 + Location pin: MMCM_ADV_X0Y6.CLKOUT1 + Clock network: ftop/dram0/memc_memc/u_infrastructure/clk_pll +-------------------------------------------------------------------------------- +Slack: 4.168ns (period - (min high pulse limit / (high pulse / period))) + Period: 5.000ns + High pulse: 2.500ns + High pulse limit: 0.416ns (Trpw) + Physical resource: ftop/ctop/inf/cp/timeServ_ppsOKCC/sync/sSyncReg2/SR + Logical resource: ftop/ctop/inf/cp/timeServ_ppsOKCC/sync/sSyncReg1/SR + Location pin: SLICE_X0Y68.SR + Clock network: ftop/ctop/inf/cp/timeServ_ppsOKCC/sync/sRST_inv +-------------------------------------------------------------------------------- +Slack: 4.168ns (period - (min high pulse limit / (high pulse / period))) + Period: 5.000ns + High pulse: 2.500ns + High pulse limit: 0.416ns (Trpw) + Physical resource: ftop/ctop/inf/cp/timeServ_ppsOKCC/sync/sSyncReg2/SR + Logical resource: ftop/ctop/inf/cp/timeServ_ppsOKCC/sync/sSyncReg2/SR + Location pin: SLICE_X0Y68.SR + Clock network: ftop/ctop/inf/cp/timeServ_ppsOKCC/sync/sRST_inv +-------------------------------------------------------------------------------- +Slack: 4.168ns (period - (min high pulse limit / (high pulse / period))) + Period: 5.000ns + High pulse: 2.500ns + High pulse limit: 0.416ns (Trpw) + Physical resource: ftop/ctop/inf/cp/timeServ_ppsOKCC/sync/sToggleReg/SR + Logical resource: ftop/ctop/inf/cp/timeServ_ppsOKCC/sync/sToggleReg/SR + Location pin: SLICE_X0Y69.SR + Clock network: ftop/ctop/inf/cp/timeServ_ppsOKCC/sync/sRST_inv +-------------------------------------------------------------------------------- +Slack: 4.168ns (period - (min high pulse limit / (high pulse / period))) + Period: 5.000ns + High pulse: 2.500ns + High pulse limit: 0.416ns (Trpw) + Physical resource: ftop/ctop/inf/cp/timeServ_disableServo/sync/dLastState/SR + Logical resource: ftop/ctop/inf/cp/timeServ_disableServo/sync/dLastState/SR + Location pin: SLICE_X8Y53.SR + Clock network: ftop/ctop/inf/cp/timeServ_disableServo/sync/sRST_inv +-------------------------------------------------------------------------------- +Slack: 4.168ns (period - (min high pulse limit / (high pulse / period))) + Period: 5.000ns + High pulse: 2.500ns + High pulse limit: 0.416ns (Trpw) + Physical resource: ftop/ctop/inf/cp/timeServ_ppsOKCC/sDataSyncIn_0/SR + Logical resource: ftop/ctop/inf/cp/timeServ_ppsOKCC/sDataSyncIn_0/SR + Location pin: SLICE_X8Y67.SR + Clock network: ftop/ctop/inf/cp/timeServ_ppsOKCC/sRST_inv +-------------------------------------------------------------------------------- +Slack: 4.168ns (period - (min high pulse limit / (high pulse / period))) + Period: 5.000ns + High pulse: 2.500ns + High pulse limit: 0.416ns (Trpw) + Physical resource: ftop/ctop/inf/cp/timeServ_ppsLostCC/sync/sSyncReg2/SR + Logical resource: ftop/ctop/inf/cp/timeServ_ppsLostCC/sync/sSyncReg1/SR + Location pin: SLICE_X9Y58.SR + Clock network: ftop/ctop/inf/cp/timeServ_ppsLostCC/sync/sRST_inv +-------------------------------------------------------------------------------- +Slack: 4.168ns (period - (min high pulse limit / (high pulse / period))) + Period: 5.000ns + High pulse: 2.500ns + High pulse limit: 0.416ns (Trpw) + Physical resource: ftop/ctop/inf/cp/timeServ_ppsLostCC/sync/sSyncReg2/SR + Logical resource: ftop/ctop/inf/cp/timeServ_ppsLostCC/sync/sSyncReg2/SR + Location pin: SLICE_X9Y58.SR + Clock network: ftop/ctop/inf/cp/timeServ_ppsLostCC/sync/sRST_inv +-------------------------------------------------------------------------------- +Slack: 4.168ns (period - (min high pulse limit / (high pulse / period))) + Period: 5.000ns + High pulse: 2.500ns + High pulse limit: 0.416ns (Trpw) + Physical resource: ftop/ctop/inf/cp/timeServ_ppsLostCC/sync/sToggleReg/SR + Logical resource: ftop/ctop/inf/cp/timeServ_ppsLostCC/sync/sToggleReg/SR + Location pin: SLICE_X9Y59.SR + Clock network: ftop/ctop/inf/cp/timeServ_ppsLostCC/sync/sRST_inv +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: TS_PCICLK = PERIOD TIMEGRP "PCICLK" 250 MHz HIGH 50%; +For more information, see Period Analysis in the Timing Closure User Guide (UG612). + + 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints + 0 timing errors detected. (0 component switching limit errors) + Minimum period is 1.538ns. +-------------------------------------------------------------------------------- + +Component Switching Limit Checks: TS_PCICLK = PERIOD TIMEGRP "PCICLK" 250 MHz HIGH 50%; +-------------------------------------------------------------------------------- +Slack: 2.462ns (period - min period limit) + Period: 4.000ns + Min period limit: 1.538ns (650.195MHz) (Tgtxper_REFCLK(Fgclk)) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[0].GTX/MGTREFCLKRX0 + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[0].GTX/MGTREFCLKRX0 + Location pin: GTXE1_X0Y15.NORTHREFCLKRX0 + Clock network: ftop/pciw_pci0_clk$O +-------------------------------------------------------------------------------- +Slack: 2.462ns (period - min period limit) + Period: 4.000ns + Min period limit: 1.538ns (650.195MHz) (Tgtxper_REFCLK(Fgclk)) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[0].GTX/MGTREFCLKTX0 + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[0].GTX/MGTREFCLKTX0 + Location pin: GTXE1_X0Y15.NORTHREFCLKTX0 + Clock network: ftop/pciw_pci0_clk$O +-------------------------------------------------------------------------------- +Slack: 2.462ns (period - min period limit) + Period: 4.000ns + Min period limit: 1.538ns (650.195MHz) (Tgtxper_REFCLK(Fgclk)) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[1].GTX/MGTREFCLKRX0 + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[1].GTX/MGTREFCLKRX0 + Location pin: GTXE1_X0Y14.NORTHREFCLKRX0 + Clock network: ftop/pciw_pci0_clk$O +-------------------------------------------------------------------------------- +Slack: 2.462ns (period - min period limit) + Period: 4.000ns + Min period limit: 1.538ns (650.195MHz) (Tgtxper_REFCLK(Fgclk)) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[1].GTX/MGTREFCLKTX0 + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[1].GTX/MGTREFCLKTX0 + Location pin: GTXE1_X0Y14.NORTHREFCLKTX0 + Clock network: ftop/pciw_pci0_clk$O +-------------------------------------------------------------------------------- +Slack: 2.462ns (period - min period limit) + Period: 4.000ns + Min period limit: 1.538ns (650.195MHz) (Tgtxper_REFCLK(Fgclk)) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX/MGTREFCLKRX0 + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX/MGTREFCLKRX0 + Location pin: GTXE1_X0Y13.NORTHREFCLKRX0 + Clock network: ftop/pciw_pci0_clk$O +-------------------------------------------------------------------------------- +Slack: 2.462ns (period - min period limit) + Period: 4.000ns + Min period limit: 1.538ns (650.195MHz) (Tgtxper_REFCLK(Fgclk)) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX/MGTREFCLKTX0 + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX/MGTREFCLKTX0 + Location pin: GTXE1_X0Y13.NORTHREFCLKTX0 + Clock network: ftop/pciw_pci0_clk$O +-------------------------------------------------------------------------------- +Slack: 2.462ns (period - min period limit) + Period: 4.000ns + Min period limit: 1.538ns (650.195MHz) (Tgtxper_REFCLK(Fgclk)) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX/MGTREFCLKRX0 + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX/MGTREFCLKRX0 + Location pin: GTXE1_X0Y12.NORTHREFCLKRX0 + Clock network: ftop/pciw_pci0_clk$O +-------------------------------------------------------------------------------- +Slack: 2.462ns (period - min period limit) + Period: 4.000ns + Min period limit: 1.538ns (650.195MHz) (Tgtxper_REFCLK(Fgclk)) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX/MGTREFCLKTX0 + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX/MGTREFCLKTX0 + Location pin: GTXE1_X0Y12.NORTHREFCLKTX0 + Clock network: ftop/pciw_pci0_clk$O +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: TS_CLK_125 = PERIOD TIMEGRP "CLK_125" TS_PCICLK / 2 HIGH 50% +PRIORITY 100; +For more information, see Period Analysis in the Timing Closure User Guide (UG612). + + 13943867 paths analyzed, 134790 endpoints analyzed, 380 failing endpoints + 380 timing errors detected. (380 setup errors, 0 hold errors, 0 component switching limit errors) + Minimum period is 10.171ns. +-------------------------------------------------------------------------------- +Slack (setup path): -2.171ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/cpReq_24 (FF) + Destination: ftop/ctop/inf/cp/cpReq<21>_REPLICA_174 (FF) + Requirement: 8.000ns + Data Path Delay: 10.055ns (Levels of Logic = 10) + Clock Path Skew: -0.047ns (1.011 - 1.058) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.069ns + + Clock Uncertainty: 0.069ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/cpReq_24 to ftop/ctop/inf/cp/cpReq<21>_REPLICA_174 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X108Y47.AQ Tcko 0.381 ftop/ctop/inf/cp/cpReq<27> + ftop/ctop/inf/cp/cpReq_24 + SLICE_X109Y47.D3 net (fanout=72) 0.503 ftop/ctop/inf/cp/cpReq<24> + SLICE_X109Y47.D Tilo 0.068 ftop/ctop/inf/cp/wci_6_wReset_n + ftop/ctop/inf/cp/Msub_wn___1__h76499_xor<2>11 + SLICE_X106Y46.D2 net (fanout=50) 0.779 ftop/ctop/inf/cp/wn___1__h76499<2> + SLICE_X106Y46.D Tilo 0.068 ftop/ctop/inf/cp/wci_6_respF$EMPTY_N + ftop/ctop/inf/cp/Mmux__theResult_____1__h7573931 + SLICE_X106Y47.CX net (fanout=37) 0.535 ftop/ctop/inf/cp/_theResult_____1__h75739<2> + SLICE_X106Y47.BMUX Tcxb 0.331 ftop/ctop/inf/cp/CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793_4_f7 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793_2_f8 + SLICE_X100Y55.B6 net (fanout=10) 0.722 ftop/ctop/inf/cp/CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793 + SLICE_X100Y55.B Tilo 0.068 ftop/ctop/inf/cp/wci_0_respF$D_OUT<22> + ftop/ctop/inf/cp/_n13764<34>21 + SLICE_X96Y54.A6 net (fanout=76) 0.516 ftop/ctop/inf/cp/_n13764<34>2 + SLICE_X96Y54.A Tilo 0.068 ftop/ctop/inf/cp/wci_7_respF$D_OUT<21> + ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_F_T1 + SLICE_X97Y52.B2 net (fanout=13) 0.723 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_F_T + SLICE_X97Y52.B Tilo 0.068 ftop/ctop/inf/cp/cpReq<8>_REPLICA_52 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead24 + SLICE_X101Y51.B1 net (fanout=1) 0.866 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead24 + SLICE_X101Y51.B Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_T_F + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead26 + SLICE_X101Y51.A2 net (fanout=1) 0.465 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead26 + SLICE_X101Y51.A Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_T_F + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead32 + SLICE_X124Y42.B6 net (fanout=21) 1.308 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead + SLICE_X124Y42.B Tilo 0.068 ftop/ctop/inf/cp/cpRespF/d0h + ftop/ctop/inf/cp/cpRespF$ENQ + SLICE_X104Y55.C6 net (fanout=32) 1.399 ftop/ctop/inf/cp/cpRespF$ENQ + SLICE_X104Y55.C Tilo 0.068 ftop/ctop/inf/cp/wci_0_lastConfigAddr<12> + ftop/ctop/inf/cp/cpReq$EN_REPLICA_439 + SLICE_X98Y56.CE net (fanout=1) 0.597 ftop/ctop/inf/cp/cpReq$EN_REPLICA_439 + SLICE_X98Y56.CLK Tceck 0.318 ftop/ctop/inf/cp/cpReq<21>_REPLICA_174 + ftop/ctop/inf/cp/cpReq<21>_REPLICA_174 + ------------------------------------------------- --------------------------- + Total 10.055ns (1.642ns logic, 8.413ns route) + (16.3% logic, 83.7% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -2.171ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/cpReq_24 (FF) + Destination: ftop/ctop/inf/cp/cpReq<6>_REPLICA_36 (FF) + Requirement: 8.000ns + Data Path Delay: 10.055ns (Levels of Logic = 10) + Clock Path Skew: -0.047ns (1.011 - 1.058) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.069ns + + Clock Uncertainty: 0.069ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/cpReq_24 to ftop/ctop/inf/cp/cpReq<6>_REPLICA_36 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X108Y47.AQ Tcko 0.381 ftop/ctop/inf/cp/cpReq<27> + ftop/ctop/inf/cp/cpReq_24 + SLICE_X109Y47.D3 net (fanout=72) 0.503 ftop/ctop/inf/cp/cpReq<24> + SLICE_X109Y47.D Tilo 0.068 ftop/ctop/inf/cp/wci_6_wReset_n + ftop/ctop/inf/cp/Msub_wn___1__h76499_xor<2>11 + SLICE_X106Y46.D2 net (fanout=50) 0.779 ftop/ctop/inf/cp/wn___1__h76499<2> + SLICE_X106Y46.D Tilo 0.068 ftop/ctop/inf/cp/wci_6_respF$EMPTY_N + ftop/ctop/inf/cp/Mmux__theResult_____1__h7573931 + SLICE_X106Y47.CX net (fanout=37) 0.535 ftop/ctop/inf/cp/_theResult_____1__h75739<2> + SLICE_X106Y47.BMUX Tcxb 0.331 ftop/ctop/inf/cp/CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793_4_f7 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793_2_f8 + SLICE_X100Y55.B6 net (fanout=10) 0.722 ftop/ctop/inf/cp/CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793 + SLICE_X100Y55.B Tilo 0.068 ftop/ctop/inf/cp/wci_0_respF$D_OUT<22> + ftop/ctop/inf/cp/_n13764<34>21 + SLICE_X96Y54.A6 net (fanout=76) 0.516 ftop/ctop/inf/cp/_n13764<34>2 + SLICE_X96Y54.A Tilo 0.068 ftop/ctop/inf/cp/wci_7_respF$D_OUT<21> + ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_F_T1 + SLICE_X97Y52.B2 net (fanout=13) 0.723 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_F_T + SLICE_X97Y52.B Tilo 0.068 ftop/ctop/inf/cp/cpReq<8>_REPLICA_52 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead24 + SLICE_X101Y51.B1 net (fanout=1) 0.866 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead24 + SLICE_X101Y51.B Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_T_F + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead26 + SLICE_X101Y51.A2 net (fanout=1) 0.465 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead26 + SLICE_X101Y51.A Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_T_F + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead32 + SLICE_X124Y42.B6 net (fanout=21) 1.308 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead + SLICE_X124Y42.B Tilo 0.068 ftop/ctop/inf/cp/cpRespF/d0h + ftop/ctop/inf/cp/cpRespF$ENQ + SLICE_X104Y55.C6 net (fanout=32) 1.399 ftop/ctop/inf/cp/cpRespF$ENQ + SLICE_X104Y55.C Tilo 0.068 ftop/ctop/inf/cp/wci_0_lastConfigAddr<12> + ftop/ctop/inf/cp/cpReq$EN_REPLICA_439 + SLICE_X98Y56.CE net (fanout=1) 0.597 ftop/ctop/inf/cp/cpReq$EN_REPLICA_439 + SLICE_X98Y56.CLK Tceck 0.318 ftop/ctop/inf/cp/cpReq<21>_REPLICA_174 + ftop/ctop/inf/cp/cpReq<6>_REPLICA_36 + ------------------------------------------------- --------------------------- + Total 10.055ns (1.642ns logic, 8.413ns route) + (16.3% logic, 83.7% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -2.171ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/cpReq_24 (FF) + Destination: ftop/ctop/inf/cp/cpReq<8>_REPLICA_54 (FF) + Requirement: 8.000ns + Data Path Delay: 10.055ns (Levels of Logic = 10) + Clock Path Skew: -0.047ns (1.011 - 1.058) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.069ns + + Clock Uncertainty: 0.069ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/cpReq_24 to ftop/ctop/inf/cp/cpReq<8>_REPLICA_54 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X108Y47.AQ Tcko 0.381 ftop/ctop/inf/cp/cpReq<27> + ftop/ctop/inf/cp/cpReq_24 + SLICE_X109Y47.D3 net (fanout=72) 0.503 ftop/ctop/inf/cp/cpReq<24> + SLICE_X109Y47.D Tilo 0.068 ftop/ctop/inf/cp/wci_6_wReset_n + ftop/ctop/inf/cp/Msub_wn___1__h76499_xor<2>11 + SLICE_X106Y46.D2 net (fanout=50) 0.779 ftop/ctop/inf/cp/wn___1__h76499<2> + SLICE_X106Y46.D Tilo 0.068 ftop/ctop/inf/cp/wci_6_respF$EMPTY_N + ftop/ctop/inf/cp/Mmux__theResult_____1__h7573931 + SLICE_X106Y47.CX net (fanout=37) 0.535 ftop/ctop/inf/cp/_theResult_____1__h75739<2> + SLICE_X106Y47.BMUX Tcxb 0.331 ftop/ctop/inf/cp/CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793_4_f7 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793_2_f8 + SLICE_X100Y55.B6 net (fanout=10) 0.722 ftop/ctop/inf/cp/CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793 + SLICE_X100Y55.B Tilo 0.068 ftop/ctop/inf/cp/wci_0_respF$D_OUT<22> + ftop/ctop/inf/cp/_n13764<34>21 + SLICE_X96Y54.A6 net (fanout=76) 0.516 ftop/ctop/inf/cp/_n13764<34>2 + SLICE_X96Y54.A Tilo 0.068 ftop/ctop/inf/cp/wci_7_respF$D_OUT<21> + ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_F_T1 + SLICE_X97Y52.B2 net (fanout=13) 0.723 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_F_T + SLICE_X97Y52.B Tilo 0.068 ftop/ctop/inf/cp/cpReq<8>_REPLICA_52 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead24 + SLICE_X101Y51.B1 net (fanout=1) 0.866 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead24 + SLICE_X101Y51.B Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_T_F + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead26 + SLICE_X101Y51.A2 net (fanout=1) 0.465 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead26 + SLICE_X101Y51.A Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_T_F + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead32 + SLICE_X124Y42.B6 net (fanout=21) 1.308 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead + SLICE_X124Y42.B Tilo 0.068 ftop/ctop/inf/cp/cpRespF/d0h + ftop/ctop/inf/cp/cpRespF$ENQ + SLICE_X104Y55.C6 net (fanout=32) 1.399 ftop/ctop/inf/cp/cpRespF$ENQ + SLICE_X104Y55.C Tilo 0.068 ftop/ctop/inf/cp/wci_0_lastConfigAddr<12> + ftop/ctop/inf/cp/cpReq$EN_REPLICA_439 + SLICE_X98Y56.CE net (fanout=1) 0.597 ftop/ctop/inf/cp/cpReq$EN_REPLICA_439 + SLICE_X98Y56.CLK Tceck 0.318 ftop/ctop/inf/cp/cpReq<21>_REPLICA_174 + ftop/ctop/inf/cp/cpReq<8>_REPLICA_54 + ------------------------------------------------- --------------------------- + Total 10.055ns (1.642ns logic, 8.413ns route) + (16.3% logic, 83.7% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -2.167ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/cpReq_24 (FF) + Destination: ftop/ctop/inf/cp/cpReq<8>_REPLICA_54 (FF) + Requirement: 8.000ns + Data Path Delay: 10.051ns (Levels of Logic = 10) + Clock Path Skew: -0.047ns (1.011 - 1.058) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.069ns + + Clock Uncertainty: 0.069ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/cpReq_24 to ftop/ctop/inf/cp/cpReq<8>_REPLICA_54 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X108Y47.AQ Tcko 0.381 ftop/ctop/inf/cp/cpReq<27> + ftop/ctop/inf/cp/cpReq_24 + SLICE_X109Y47.D3 net (fanout=72) 0.503 ftop/ctop/inf/cp/cpReq<24> + SLICE_X109Y47.D Tilo 0.068 ftop/ctop/inf/cp/wci_6_wReset_n + ftop/ctop/inf/cp/Msub_wn___1__h76499_xor<2>11 + SLICE_X106Y46.D2 net (fanout=50) 0.779 ftop/ctop/inf/cp/wn___1__h76499<2> + SLICE_X106Y46.D Tilo 0.068 ftop/ctop/inf/cp/wci_6_respF$EMPTY_N + ftop/ctop/inf/cp/Mmux__theResult_____1__h7573931 + SLICE_X106Y47.AX net (fanout=37) 0.537 ftop/ctop/inf/cp/_theResult_____1__h75739<2> + SLICE_X106Y47.BMUX Taxb 0.325 ftop/ctop/inf/cp/CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793_3_f7 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793_2_f8 + SLICE_X100Y55.B6 net (fanout=10) 0.722 ftop/ctop/inf/cp/CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793 + SLICE_X100Y55.B Tilo 0.068 ftop/ctop/inf/cp/wci_0_respF$D_OUT<22> + ftop/ctop/inf/cp/_n13764<34>21 + SLICE_X96Y54.A6 net (fanout=76) 0.516 ftop/ctop/inf/cp/_n13764<34>2 + SLICE_X96Y54.A Tilo 0.068 ftop/ctop/inf/cp/wci_7_respF$D_OUT<21> + ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_F_T1 + SLICE_X97Y52.B2 net (fanout=13) 0.723 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_F_T + SLICE_X97Y52.B Tilo 0.068 ftop/ctop/inf/cp/cpReq<8>_REPLICA_52 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead24 + SLICE_X101Y51.B1 net (fanout=1) 0.866 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead24 + SLICE_X101Y51.B Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_T_F + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead26 + SLICE_X101Y51.A2 net (fanout=1) 0.465 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead26 + SLICE_X101Y51.A Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_T_F + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead32 + SLICE_X124Y42.B6 net (fanout=21) 1.308 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead + SLICE_X124Y42.B Tilo 0.068 ftop/ctop/inf/cp/cpRespF/d0h + ftop/ctop/inf/cp/cpRespF$ENQ + SLICE_X104Y55.C6 net (fanout=32) 1.399 ftop/ctop/inf/cp/cpRespF$ENQ + SLICE_X104Y55.C Tilo 0.068 ftop/ctop/inf/cp/wci_0_lastConfigAddr<12> + ftop/ctop/inf/cp/cpReq$EN_REPLICA_439 + SLICE_X98Y56.CE net (fanout=1) 0.597 ftop/ctop/inf/cp/cpReq$EN_REPLICA_439 + SLICE_X98Y56.CLK Tceck 0.318 ftop/ctop/inf/cp/cpReq<21>_REPLICA_174 + ftop/ctop/inf/cp/cpReq<8>_REPLICA_54 + ------------------------------------------------- --------------------------- + Total 10.051ns (1.636ns logic, 8.415ns route) + (16.3% logic, 83.7% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -2.167ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/cpReq_24 (FF) + Destination: ftop/ctop/inf/cp/cpReq<21>_REPLICA_174 (FF) + Requirement: 8.000ns + Data Path Delay: 10.051ns (Levels of Logic = 10) + Clock Path Skew: -0.047ns (1.011 - 1.058) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.069ns + + Clock Uncertainty: 0.069ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/cpReq_24 to ftop/ctop/inf/cp/cpReq<21>_REPLICA_174 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X108Y47.AQ Tcko 0.381 ftop/ctop/inf/cp/cpReq<27> + ftop/ctop/inf/cp/cpReq_24 + SLICE_X109Y47.D3 net (fanout=72) 0.503 ftop/ctop/inf/cp/cpReq<24> + SLICE_X109Y47.D Tilo 0.068 ftop/ctop/inf/cp/wci_6_wReset_n + ftop/ctop/inf/cp/Msub_wn___1__h76499_xor<2>11 + SLICE_X106Y46.D2 net (fanout=50) 0.779 ftop/ctop/inf/cp/wn___1__h76499<2> + SLICE_X106Y46.D Tilo 0.068 ftop/ctop/inf/cp/wci_6_respF$EMPTY_N + ftop/ctop/inf/cp/Mmux__theResult_____1__h7573931 + SLICE_X106Y47.AX net (fanout=37) 0.537 ftop/ctop/inf/cp/_theResult_____1__h75739<2> + SLICE_X106Y47.BMUX Taxb 0.325 ftop/ctop/inf/cp/CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793_3_f7 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793_2_f8 + SLICE_X100Y55.B6 net (fanout=10) 0.722 ftop/ctop/inf/cp/CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793 + SLICE_X100Y55.B Tilo 0.068 ftop/ctop/inf/cp/wci_0_respF$D_OUT<22> + ftop/ctop/inf/cp/_n13764<34>21 + SLICE_X96Y54.A6 net (fanout=76) 0.516 ftop/ctop/inf/cp/_n13764<34>2 + SLICE_X96Y54.A Tilo 0.068 ftop/ctop/inf/cp/wci_7_respF$D_OUT<21> + ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_F_T1 + SLICE_X97Y52.B2 net (fanout=13) 0.723 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_F_T + SLICE_X97Y52.B Tilo 0.068 ftop/ctop/inf/cp/cpReq<8>_REPLICA_52 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead24 + SLICE_X101Y51.B1 net (fanout=1) 0.866 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead24 + SLICE_X101Y51.B Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_T_F + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead26 + SLICE_X101Y51.A2 net (fanout=1) 0.465 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead26 + SLICE_X101Y51.A Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_T_F + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead32 + SLICE_X124Y42.B6 net (fanout=21) 1.308 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead + SLICE_X124Y42.B Tilo 0.068 ftop/ctop/inf/cp/cpRespF/d0h + ftop/ctop/inf/cp/cpRespF$ENQ + SLICE_X104Y55.C6 net (fanout=32) 1.399 ftop/ctop/inf/cp/cpRespF$ENQ + SLICE_X104Y55.C Tilo 0.068 ftop/ctop/inf/cp/wci_0_lastConfigAddr<12> + ftop/ctop/inf/cp/cpReq$EN_REPLICA_439 + SLICE_X98Y56.CE net (fanout=1) 0.597 ftop/ctop/inf/cp/cpReq$EN_REPLICA_439 + SLICE_X98Y56.CLK Tceck 0.318 ftop/ctop/inf/cp/cpReq<21>_REPLICA_174 + ftop/ctop/inf/cp/cpReq<21>_REPLICA_174 + ------------------------------------------------- --------------------------- + Total 10.051ns (1.636ns logic, 8.415ns route) + (16.3% logic, 83.7% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -2.167ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/cpReq_24 (FF) + Destination: ftop/ctop/inf/cp/cpReq<6>_REPLICA_36 (FF) + Requirement: 8.000ns + Data Path Delay: 10.051ns (Levels of Logic = 10) + Clock Path Skew: -0.047ns (1.011 - 1.058) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.069ns + + Clock Uncertainty: 0.069ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/cpReq_24 to ftop/ctop/inf/cp/cpReq<6>_REPLICA_36 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X108Y47.AQ Tcko 0.381 ftop/ctop/inf/cp/cpReq<27> + ftop/ctop/inf/cp/cpReq_24 + SLICE_X109Y47.D3 net (fanout=72) 0.503 ftop/ctop/inf/cp/cpReq<24> + SLICE_X109Y47.D Tilo 0.068 ftop/ctop/inf/cp/wci_6_wReset_n + ftop/ctop/inf/cp/Msub_wn___1__h76499_xor<2>11 + SLICE_X106Y46.D2 net (fanout=50) 0.779 ftop/ctop/inf/cp/wn___1__h76499<2> + SLICE_X106Y46.D Tilo 0.068 ftop/ctop/inf/cp/wci_6_respF$EMPTY_N + ftop/ctop/inf/cp/Mmux__theResult_____1__h7573931 + SLICE_X106Y47.AX net (fanout=37) 0.537 ftop/ctop/inf/cp/_theResult_____1__h75739<2> + SLICE_X106Y47.BMUX Taxb 0.325 ftop/ctop/inf/cp/CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793_3_f7 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793_2_f8 + SLICE_X100Y55.B6 net (fanout=10) 0.722 ftop/ctop/inf/cp/CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793 + SLICE_X100Y55.B Tilo 0.068 ftop/ctop/inf/cp/wci_0_respF$D_OUT<22> + ftop/ctop/inf/cp/_n13764<34>21 + SLICE_X96Y54.A6 net (fanout=76) 0.516 ftop/ctop/inf/cp/_n13764<34>2 + SLICE_X96Y54.A Tilo 0.068 ftop/ctop/inf/cp/wci_7_respF$D_OUT<21> + ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_F_T1 + SLICE_X97Y52.B2 net (fanout=13) 0.723 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_F_T + SLICE_X97Y52.B Tilo 0.068 ftop/ctop/inf/cp/cpReq<8>_REPLICA_52 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead24 + SLICE_X101Y51.B1 net (fanout=1) 0.866 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead24 + SLICE_X101Y51.B Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_T_F + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead26 + SLICE_X101Y51.A2 net (fanout=1) 0.465 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead26 + SLICE_X101Y51.A Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_T_F + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead32 + SLICE_X124Y42.B6 net (fanout=21) 1.308 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead + SLICE_X124Y42.B Tilo 0.068 ftop/ctop/inf/cp/cpRespF/d0h + ftop/ctop/inf/cp/cpRespF$ENQ + SLICE_X104Y55.C6 net (fanout=32) 1.399 ftop/ctop/inf/cp/cpRespF$ENQ + SLICE_X104Y55.C Tilo 0.068 ftop/ctop/inf/cp/wci_0_lastConfigAddr<12> + ftop/ctop/inf/cp/cpReq$EN_REPLICA_439 + SLICE_X98Y56.CE net (fanout=1) 0.597 ftop/ctop/inf/cp/cpReq$EN_REPLICA_439 + SLICE_X98Y56.CLK Tceck 0.318 ftop/ctop/inf/cp/cpReq<21>_REPLICA_174 + ftop/ctop/inf/cp/cpReq<6>_REPLICA_36 + ------------------------------------------------- --------------------------- + Total 10.051ns (1.636ns logic, 8.415ns route) + (16.3% logic, 83.7% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -2.155ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/cpReq_24 (FF) + Destination: ftop/ctop/inf/cp/cpReq<6>_REPLICA_33 (FF) + Requirement: 8.000ns + Data Path Delay: 10.043ns (Levels of Logic = 10) + Clock Path Skew: -0.043ns (1.015 - 1.058) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.069ns + + Clock Uncertainty: 0.069ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/cpReq_24 to ftop/ctop/inf/cp/cpReq<6>_REPLICA_33 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X108Y47.AQ Tcko 0.381 ftop/ctop/inf/cp/cpReq<27> + ftop/ctop/inf/cp/cpReq_24 + SLICE_X109Y47.D3 net (fanout=72) 0.503 ftop/ctop/inf/cp/cpReq<24> + SLICE_X109Y47.D Tilo 0.068 ftop/ctop/inf/cp/wci_6_wReset_n + ftop/ctop/inf/cp/Msub_wn___1__h76499_xor<2>11 + SLICE_X106Y46.D2 net (fanout=50) 0.779 ftop/ctop/inf/cp/wn___1__h76499<2> + SLICE_X106Y46.D Tilo 0.068 ftop/ctop/inf/cp/wci_6_respF$EMPTY_N + ftop/ctop/inf/cp/Mmux__theResult_____1__h7573931 + SLICE_X106Y47.CX net (fanout=37) 0.535 ftop/ctop/inf/cp/_theResult_____1__h75739<2> + SLICE_X106Y47.BMUX Tcxb 0.331 ftop/ctop/inf/cp/CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793_4_f7 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793_2_f8 + SLICE_X100Y55.B6 net (fanout=10) 0.722 ftop/ctop/inf/cp/CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793 + SLICE_X100Y55.B Tilo 0.068 ftop/ctop/inf/cp/wci_0_respF$D_OUT<22> + ftop/ctop/inf/cp/_n13764<34>21 + SLICE_X96Y54.A6 net (fanout=76) 0.516 ftop/ctop/inf/cp/_n13764<34>2 + SLICE_X96Y54.A Tilo 0.068 ftop/ctop/inf/cp/wci_7_respF$D_OUT<21> + ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_F_T1 + SLICE_X97Y52.B2 net (fanout=13) 0.723 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_F_T + SLICE_X97Y52.B Tilo 0.068 ftop/ctop/inf/cp/cpReq<8>_REPLICA_52 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead24 + SLICE_X101Y51.B1 net (fanout=1) 0.866 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead24 + SLICE_X101Y51.B Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_T_F + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead26 + SLICE_X101Y51.A2 net (fanout=1) 0.465 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead26 + SLICE_X101Y51.A Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_T_F + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead32 + SLICE_X124Y42.B6 net (fanout=21) 1.308 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead + SLICE_X124Y42.B Tilo 0.068 ftop/ctop/inf/cp/cpRespF/d0h + ftop/ctop/inf/cp/cpRespF$ENQ + SLICE_X107Y55.C6 net (fanout=32) 1.264 ftop/ctop/inf/cp/cpRespF$ENQ + SLICE_X107Y55.C Tilo 0.068 ftop/ctop/inf/cp/wci_0_pageWindow<11> + ftop/ctop/inf/cp/cpReq$EN_REPLICA_426 + SLICE_X97Y54.CE net (fanout=2) 0.720 ftop/ctop/inf/cp/cpReq$EN_REPLICA_426 + SLICE_X97Y54.CLK Tceck 0.318 ftop/ctop/inf/cp/cpReq<6>_REPLICA_33 + ftop/ctop/inf/cp/cpReq<6>_REPLICA_33 + ------------------------------------------------- --------------------------- + Total 10.043ns (1.642ns logic, 8.401ns route) + (16.3% logic, 83.7% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -2.155ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/cpReq_24 (FF) + Destination: ftop/ctop/inf/cp/cpReq<20>_REPLICA_86 (FF) + Requirement: 8.000ns + Data Path Delay: 10.043ns (Levels of Logic = 10) + Clock Path Skew: -0.043ns (1.015 - 1.058) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.069ns + + Clock Uncertainty: 0.069ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/cpReq_24 to ftop/ctop/inf/cp/cpReq<20>_REPLICA_86 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X108Y47.AQ Tcko 0.381 ftop/ctop/inf/cp/cpReq<27> + ftop/ctop/inf/cp/cpReq_24 + SLICE_X109Y47.D3 net (fanout=72) 0.503 ftop/ctop/inf/cp/cpReq<24> + SLICE_X109Y47.D Tilo 0.068 ftop/ctop/inf/cp/wci_6_wReset_n + ftop/ctop/inf/cp/Msub_wn___1__h76499_xor<2>11 + SLICE_X106Y46.D2 net (fanout=50) 0.779 ftop/ctop/inf/cp/wn___1__h76499<2> + SLICE_X106Y46.D Tilo 0.068 ftop/ctop/inf/cp/wci_6_respF$EMPTY_N + ftop/ctop/inf/cp/Mmux__theResult_____1__h7573931 + SLICE_X106Y47.CX net (fanout=37) 0.535 ftop/ctop/inf/cp/_theResult_____1__h75739<2> + SLICE_X106Y47.BMUX Tcxb 0.331 ftop/ctop/inf/cp/CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793_4_f7 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793_2_f8 + SLICE_X100Y55.B6 net (fanout=10) 0.722 ftop/ctop/inf/cp/CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793 + SLICE_X100Y55.B Tilo 0.068 ftop/ctop/inf/cp/wci_0_respF$D_OUT<22> + ftop/ctop/inf/cp/_n13764<34>21 + SLICE_X96Y54.A6 net (fanout=76) 0.516 ftop/ctop/inf/cp/_n13764<34>2 + SLICE_X96Y54.A Tilo 0.068 ftop/ctop/inf/cp/wci_7_respF$D_OUT<21> + ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_F_T1 + SLICE_X97Y52.B2 net (fanout=13) 0.723 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_F_T + SLICE_X97Y52.B Tilo 0.068 ftop/ctop/inf/cp/cpReq<8>_REPLICA_52 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead24 + SLICE_X101Y51.B1 net (fanout=1) 0.866 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead24 + SLICE_X101Y51.B Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_T_F + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead26 + SLICE_X101Y51.A2 net (fanout=1) 0.465 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead26 + SLICE_X101Y51.A Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_T_F + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead32 + SLICE_X124Y42.B6 net (fanout=21) 1.308 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead + SLICE_X124Y42.B Tilo 0.068 ftop/ctop/inf/cp/cpRespF/d0h + ftop/ctop/inf/cp/cpRespF$ENQ + SLICE_X107Y55.C6 net (fanout=32) 1.264 ftop/ctop/inf/cp/cpRespF$ENQ + SLICE_X107Y55.C Tilo 0.068 ftop/ctop/inf/cp/wci_0_pageWindow<11> + ftop/ctop/inf/cp/cpReq$EN_REPLICA_426 + SLICE_X97Y54.CE net (fanout=2) 0.720 ftop/ctop/inf/cp/cpReq$EN_REPLICA_426 + SLICE_X97Y54.CLK Tceck 0.318 ftop/ctop/inf/cp/cpReq<6>_REPLICA_33 + ftop/ctop/inf/cp/cpReq<20>_REPLICA_86 + ------------------------------------------------- --------------------------- + Total 10.043ns (1.642ns logic, 8.401ns route) + (16.3% logic, 83.7% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -2.151ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/cpReq_24 (FF) + Destination: ftop/ctop/inf/cp/cpReq<6>_REPLICA_33 (FF) + Requirement: 8.000ns + Data Path Delay: 10.039ns (Levels of Logic = 10) + Clock Path Skew: -0.043ns (1.015 - 1.058) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.069ns + + Clock Uncertainty: 0.069ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/cpReq_24 to ftop/ctop/inf/cp/cpReq<6>_REPLICA_33 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X108Y47.AQ Tcko 0.381 ftop/ctop/inf/cp/cpReq<27> + ftop/ctop/inf/cp/cpReq_24 + SLICE_X109Y47.D3 net (fanout=72) 0.503 ftop/ctop/inf/cp/cpReq<24> + SLICE_X109Y47.D Tilo 0.068 ftop/ctop/inf/cp/wci_6_wReset_n + ftop/ctop/inf/cp/Msub_wn___1__h76499_xor<2>11 + SLICE_X106Y46.D2 net (fanout=50) 0.779 ftop/ctop/inf/cp/wn___1__h76499<2> + SLICE_X106Y46.D Tilo 0.068 ftop/ctop/inf/cp/wci_6_respF$EMPTY_N + ftop/ctop/inf/cp/Mmux__theResult_____1__h7573931 + SLICE_X106Y47.AX net (fanout=37) 0.537 ftop/ctop/inf/cp/_theResult_____1__h75739<2> + SLICE_X106Y47.BMUX Taxb 0.325 ftop/ctop/inf/cp/CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793_3_f7 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793_2_f8 + SLICE_X100Y55.B6 net (fanout=10) 0.722 ftop/ctop/inf/cp/CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793 + SLICE_X100Y55.B Tilo 0.068 ftop/ctop/inf/cp/wci_0_respF$D_OUT<22> + ftop/ctop/inf/cp/_n13764<34>21 + SLICE_X96Y54.A6 net (fanout=76) 0.516 ftop/ctop/inf/cp/_n13764<34>2 + SLICE_X96Y54.A Tilo 0.068 ftop/ctop/inf/cp/wci_7_respF$D_OUT<21> + ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_F_T1 + SLICE_X97Y52.B2 net (fanout=13) 0.723 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_F_T + SLICE_X97Y52.B Tilo 0.068 ftop/ctop/inf/cp/cpReq<8>_REPLICA_52 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead24 + SLICE_X101Y51.B1 net (fanout=1) 0.866 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead24 + SLICE_X101Y51.B Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_T_F + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead26 + SLICE_X101Y51.A2 net (fanout=1) 0.465 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead26 + SLICE_X101Y51.A Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_T_F + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead32 + SLICE_X124Y42.B6 net (fanout=21) 1.308 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead + SLICE_X124Y42.B Tilo 0.068 ftop/ctop/inf/cp/cpRespF/d0h + ftop/ctop/inf/cp/cpRespF$ENQ + SLICE_X107Y55.C6 net (fanout=32) 1.264 ftop/ctop/inf/cp/cpRespF$ENQ + SLICE_X107Y55.C Tilo 0.068 ftop/ctop/inf/cp/wci_0_pageWindow<11> + ftop/ctop/inf/cp/cpReq$EN_REPLICA_426 + SLICE_X97Y54.CE net (fanout=2) 0.720 ftop/ctop/inf/cp/cpReq$EN_REPLICA_426 + SLICE_X97Y54.CLK Tceck 0.318 ftop/ctop/inf/cp/cpReq<6>_REPLICA_33 + ftop/ctop/inf/cp/cpReq<6>_REPLICA_33 + ------------------------------------------------- --------------------------- + Total 10.039ns (1.636ns logic, 8.403ns route) + (16.3% logic, 83.7% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -2.151ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/cpReq_24 (FF) + Destination: ftop/ctop/inf/cp/cpReq<20>_REPLICA_86 (FF) + Requirement: 8.000ns + Data Path Delay: 10.039ns (Levels of Logic = 10) + Clock Path Skew: -0.043ns (1.015 - 1.058) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.069ns + + Clock Uncertainty: 0.069ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/cpReq_24 to ftop/ctop/inf/cp/cpReq<20>_REPLICA_86 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X108Y47.AQ Tcko 0.381 ftop/ctop/inf/cp/cpReq<27> + ftop/ctop/inf/cp/cpReq_24 + SLICE_X109Y47.D3 net (fanout=72) 0.503 ftop/ctop/inf/cp/cpReq<24> + SLICE_X109Y47.D Tilo 0.068 ftop/ctop/inf/cp/wci_6_wReset_n + ftop/ctop/inf/cp/Msub_wn___1__h76499_xor<2>11 + SLICE_X106Y46.D2 net (fanout=50) 0.779 ftop/ctop/inf/cp/wn___1__h76499<2> + SLICE_X106Y46.D Tilo 0.068 ftop/ctop/inf/cp/wci_6_respF$EMPTY_N + ftop/ctop/inf/cp/Mmux__theResult_____1__h7573931 + SLICE_X106Y47.AX net (fanout=37) 0.537 ftop/ctop/inf/cp/_theResult_____1__h75739<2> + SLICE_X106Y47.BMUX Taxb 0.325 ftop/ctop/inf/cp/CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793_3_f7 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793_2_f8 + SLICE_X100Y55.B6 net (fanout=10) 0.722 ftop/ctop/inf/cp/CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793 + SLICE_X100Y55.B Tilo 0.068 ftop/ctop/inf/cp/wci_0_respF$D_OUT<22> + ftop/ctop/inf/cp/_n13764<34>21 + SLICE_X96Y54.A6 net (fanout=76) 0.516 ftop/ctop/inf/cp/_n13764<34>2 + SLICE_X96Y54.A Tilo 0.068 ftop/ctop/inf/cp/wci_7_respF$D_OUT<21> + ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_F_T1 + SLICE_X97Y52.B2 net (fanout=13) 0.723 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_F_T + SLICE_X97Y52.B Tilo 0.068 ftop/ctop/inf/cp/cpReq<8>_REPLICA_52 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead24 + SLICE_X101Y51.B1 net (fanout=1) 0.866 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead24 + SLICE_X101Y51.B Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_T_F + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead26 + SLICE_X101Y51.A2 net (fanout=1) 0.465 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead26 + SLICE_X101Y51.A Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_T_F + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead32 + SLICE_X124Y42.B6 net (fanout=21) 1.308 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead + SLICE_X124Y42.B Tilo 0.068 ftop/ctop/inf/cp/cpRespF/d0h + ftop/ctop/inf/cp/cpRespF$ENQ + SLICE_X107Y55.C6 net (fanout=32) 1.264 ftop/ctop/inf/cp/cpRespF$ENQ + SLICE_X107Y55.C Tilo 0.068 ftop/ctop/inf/cp/wci_0_pageWindow<11> + ftop/ctop/inf/cp/cpReq$EN_REPLICA_426 + SLICE_X97Y54.CE net (fanout=2) 0.720 ftop/ctop/inf/cp/cpReq$EN_REPLICA_426 + SLICE_X97Y54.CLK Tceck 0.318 ftop/ctop/inf/cp/cpReq<6>_REPLICA_33 + ftop/ctop/inf/cp/cpReq<20>_REPLICA_86 + ------------------------------------------------- --------------------------- + Total 10.039ns (1.636ns logic, 8.403ns route) + (16.3% logic, 83.7% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -2.150ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/wci_14_respF/empty_reg (FF) + Destination: ftop/ctop/inf/cp/cpReq<8>_REPLICA_54 (FF) + Requirement: 8.000ns + Data Path Delay: 10.021ns (Levels of Logic = 9) + Clock Path Skew: -0.060ns (1.011 - 1.071) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.069ns + + Clock Uncertainty: 0.069ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/wci_14_respF/empty_reg to ftop/ctop/inf/cp/cpReq<8>_REPLICA_54 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X102Y46.CQ Tcko 0.381 ftop/ctop/inf/cp/wci_14_respF$EMPTY_N + ftop/ctop/inf/cp/wci_14_respF/empty_reg + SLICE_X119Y44.A3 net (fanout=43) 1.190 ftop/ctop/inf/cp/wci_14_respF$EMPTY_N + SLICE_X119Y44.A Tilo 0.068 ftop/ctop/inf/cp/NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942_REPLICA_705 + ftop/ctop/inf/cp/NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942_REPLICA_705 + SLICE_X109Y44.A1 net (fanout=5) 0.949 ftop/ctop/inf/cp/NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942_REPLICA_705 + SLICE_X109Y44.BMUX Topab 0.395 ftop/ctop/inf/cp/CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4551 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4551_3_f71 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4551_3_f7 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4551_2_f8 + SLICE_X114Y47.D6 net (fanout=4) 0.561 ftop/ctop/inf/cp/CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4551 + SLICE_X114Y47.D Tilo 0.068 ftop/ctop/inf/cp/wci_10_respF$EMPTY_N + ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_T_T1 + SLICE_X103Y50.D2 net (fanout=39) 1.075 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_T_T + SLICE_X103Y50.D Tilo 0.068 ftop/ctop/inf/cp/cpReq<21>_REPLICA_178 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead16 + SLICE_X103Y50.C2 net (fanout=1) 0.463 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead16 + SLICE_X103Y50.C Tilo 0.068 ftop/ctop/inf/cp/cpReq<21>_REPLICA_178 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead17 + SLICE_X101Y51.B6 net (fanout=1) 0.376 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead17 + SLICE_X101Y51.B Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_T_F + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead26 + SLICE_X101Y51.A2 net (fanout=1) 0.465 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead26 + SLICE_X101Y51.A Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_T_F + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead32 + SLICE_X124Y42.B6 net (fanout=21) 1.308 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead + SLICE_X124Y42.B Tilo 0.068 ftop/ctop/inf/cp/cpRespF/d0h + ftop/ctop/inf/cp/cpRespF$ENQ + SLICE_X104Y55.C6 net (fanout=32) 1.399 ftop/ctop/inf/cp/cpRespF$ENQ + SLICE_X104Y55.C Tilo 0.068 ftop/ctop/inf/cp/wci_0_lastConfigAddr<12> + ftop/ctop/inf/cp/cpReq$EN_REPLICA_439 + SLICE_X98Y56.CE net (fanout=1) 0.597 ftop/ctop/inf/cp/cpReq$EN_REPLICA_439 + SLICE_X98Y56.CLK Tceck 0.318 ftop/ctop/inf/cp/cpReq<21>_REPLICA_174 + ftop/ctop/inf/cp/cpReq<8>_REPLICA_54 + ------------------------------------------------- --------------------------- + Total 10.021ns (1.638ns logic, 8.383ns route) + (16.3% logic, 83.7% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -2.150ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/wci_14_respF/empty_reg (FF) + Destination: ftop/ctop/inf/cp/cpReq<21>_REPLICA_174 (FF) + Requirement: 8.000ns + Data Path Delay: 10.021ns (Levels of Logic = 9) + Clock Path Skew: -0.060ns (1.011 - 1.071) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.069ns + + Clock Uncertainty: 0.069ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/wci_14_respF/empty_reg to ftop/ctop/inf/cp/cpReq<21>_REPLICA_174 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X102Y46.CQ Tcko 0.381 ftop/ctop/inf/cp/wci_14_respF$EMPTY_N + ftop/ctop/inf/cp/wci_14_respF/empty_reg + SLICE_X119Y44.A3 net (fanout=43) 1.190 ftop/ctop/inf/cp/wci_14_respF$EMPTY_N + SLICE_X119Y44.A Tilo 0.068 ftop/ctop/inf/cp/NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942_REPLICA_705 + ftop/ctop/inf/cp/NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942_REPLICA_705 + SLICE_X109Y44.A1 net (fanout=5) 0.949 ftop/ctop/inf/cp/NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942_REPLICA_705 + SLICE_X109Y44.BMUX Topab 0.395 ftop/ctop/inf/cp/CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4551 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4551_3_f71 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4551_3_f7 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4551_2_f8 + SLICE_X114Y47.D6 net (fanout=4) 0.561 ftop/ctop/inf/cp/CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4551 + SLICE_X114Y47.D Tilo 0.068 ftop/ctop/inf/cp/wci_10_respF$EMPTY_N + ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_T_T1 + SLICE_X103Y50.D2 net (fanout=39) 1.075 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_T_T + SLICE_X103Y50.D Tilo 0.068 ftop/ctop/inf/cp/cpReq<21>_REPLICA_178 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead16 + SLICE_X103Y50.C2 net (fanout=1) 0.463 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead16 + SLICE_X103Y50.C Tilo 0.068 ftop/ctop/inf/cp/cpReq<21>_REPLICA_178 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead17 + SLICE_X101Y51.B6 net (fanout=1) 0.376 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead17 + SLICE_X101Y51.B Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_T_F + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead26 + SLICE_X101Y51.A2 net (fanout=1) 0.465 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead26 + SLICE_X101Y51.A Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_T_F + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead32 + SLICE_X124Y42.B6 net (fanout=21) 1.308 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead + SLICE_X124Y42.B Tilo 0.068 ftop/ctop/inf/cp/cpRespF/d0h + ftop/ctop/inf/cp/cpRespF$ENQ + SLICE_X104Y55.C6 net (fanout=32) 1.399 ftop/ctop/inf/cp/cpRespF$ENQ + SLICE_X104Y55.C Tilo 0.068 ftop/ctop/inf/cp/wci_0_lastConfigAddr<12> + ftop/ctop/inf/cp/cpReq$EN_REPLICA_439 + SLICE_X98Y56.CE net (fanout=1) 0.597 ftop/ctop/inf/cp/cpReq$EN_REPLICA_439 + SLICE_X98Y56.CLK Tceck 0.318 ftop/ctop/inf/cp/cpReq<21>_REPLICA_174 + ftop/ctop/inf/cp/cpReq<21>_REPLICA_174 + ------------------------------------------------- --------------------------- + Total 10.021ns (1.638ns logic, 8.383ns route) + (16.3% logic, 83.7% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -2.150ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/wci_14_respF/empty_reg (FF) + Destination: ftop/ctop/inf/cp/cpReq<6>_REPLICA_36 (FF) + Requirement: 8.000ns + Data Path Delay: 10.021ns (Levels of Logic = 9) + Clock Path Skew: -0.060ns (1.011 - 1.071) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.069ns + + Clock Uncertainty: 0.069ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/wci_14_respF/empty_reg to ftop/ctop/inf/cp/cpReq<6>_REPLICA_36 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X102Y46.CQ Tcko 0.381 ftop/ctop/inf/cp/wci_14_respF$EMPTY_N + ftop/ctop/inf/cp/wci_14_respF/empty_reg + SLICE_X119Y44.A3 net (fanout=43) 1.190 ftop/ctop/inf/cp/wci_14_respF$EMPTY_N + SLICE_X119Y44.A Tilo 0.068 ftop/ctop/inf/cp/NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942_REPLICA_705 + ftop/ctop/inf/cp/NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942_REPLICA_705 + SLICE_X109Y44.A1 net (fanout=5) 0.949 ftop/ctop/inf/cp/NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942_REPLICA_705 + SLICE_X109Y44.BMUX Topab 0.395 ftop/ctop/inf/cp/CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4551 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4551_3_f71 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4551_3_f7 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4551_2_f8 + SLICE_X114Y47.D6 net (fanout=4) 0.561 ftop/ctop/inf/cp/CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4551 + SLICE_X114Y47.D Tilo 0.068 ftop/ctop/inf/cp/wci_10_respF$EMPTY_N + ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_T_T1 + SLICE_X103Y50.D2 net (fanout=39) 1.075 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_T_T + SLICE_X103Y50.D Tilo 0.068 ftop/ctop/inf/cp/cpReq<21>_REPLICA_178 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead16 + SLICE_X103Y50.C2 net (fanout=1) 0.463 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead16 + SLICE_X103Y50.C Tilo 0.068 ftop/ctop/inf/cp/cpReq<21>_REPLICA_178 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead17 + SLICE_X101Y51.B6 net (fanout=1) 0.376 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead17 + SLICE_X101Y51.B Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_T_F + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead26 + SLICE_X101Y51.A2 net (fanout=1) 0.465 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead26 + SLICE_X101Y51.A Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_T_F + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead32 + SLICE_X124Y42.B6 net (fanout=21) 1.308 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead + SLICE_X124Y42.B Tilo 0.068 ftop/ctop/inf/cp/cpRespF/d0h + ftop/ctop/inf/cp/cpRespF$ENQ + SLICE_X104Y55.C6 net (fanout=32) 1.399 ftop/ctop/inf/cp/cpRespF$ENQ + SLICE_X104Y55.C Tilo 0.068 ftop/ctop/inf/cp/wci_0_lastConfigAddr<12> + ftop/ctop/inf/cp/cpReq$EN_REPLICA_439 + SLICE_X98Y56.CE net (fanout=1) 0.597 ftop/ctop/inf/cp/cpReq$EN_REPLICA_439 + SLICE_X98Y56.CLK Tceck 0.318 ftop/ctop/inf/cp/cpReq<21>_REPLICA_174 + ftop/ctop/inf/cp/cpReq<6>_REPLICA_36 + ------------------------------------------------- --------------------------- + Total 10.021ns (1.638ns logic, 8.383ns route) + (16.3% logic, 83.7% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -2.134ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/wci_14_respF/empty_reg (FF) + Destination: ftop/ctop/inf/cp/cpReq<6>_REPLICA_33 (FF) + Requirement: 8.000ns + Data Path Delay: 10.009ns (Levels of Logic = 9) + Clock Path Skew: -0.056ns (1.015 - 1.071) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.069ns + + Clock Uncertainty: 0.069ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/wci_14_respF/empty_reg to ftop/ctop/inf/cp/cpReq<6>_REPLICA_33 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X102Y46.CQ Tcko 0.381 ftop/ctop/inf/cp/wci_14_respF$EMPTY_N + ftop/ctop/inf/cp/wci_14_respF/empty_reg + SLICE_X119Y44.A3 net (fanout=43) 1.190 ftop/ctop/inf/cp/wci_14_respF$EMPTY_N + SLICE_X119Y44.A Tilo 0.068 ftop/ctop/inf/cp/NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942_REPLICA_705 + ftop/ctop/inf/cp/NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942_REPLICA_705 + SLICE_X109Y44.A1 net (fanout=5) 0.949 ftop/ctop/inf/cp/NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942_REPLICA_705 + SLICE_X109Y44.BMUX Topab 0.395 ftop/ctop/inf/cp/CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4551 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4551_3_f71 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4551_3_f7 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4551_2_f8 + SLICE_X114Y47.D6 net (fanout=4) 0.561 ftop/ctop/inf/cp/CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4551 + SLICE_X114Y47.D Tilo 0.068 ftop/ctop/inf/cp/wci_10_respF$EMPTY_N + ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_T_T1 + SLICE_X103Y50.D2 net (fanout=39) 1.075 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_T_T + SLICE_X103Y50.D Tilo 0.068 ftop/ctop/inf/cp/cpReq<21>_REPLICA_178 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead16 + SLICE_X103Y50.C2 net (fanout=1) 0.463 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead16 + SLICE_X103Y50.C Tilo 0.068 ftop/ctop/inf/cp/cpReq<21>_REPLICA_178 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead17 + SLICE_X101Y51.B6 net (fanout=1) 0.376 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead17 + SLICE_X101Y51.B Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_T_F + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead26 + SLICE_X101Y51.A2 net (fanout=1) 0.465 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead26 + SLICE_X101Y51.A Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_T_F + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead32 + SLICE_X124Y42.B6 net (fanout=21) 1.308 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead + SLICE_X124Y42.B Tilo 0.068 ftop/ctop/inf/cp/cpRespF/d0h + ftop/ctop/inf/cp/cpRespF$ENQ + SLICE_X107Y55.C6 net (fanout=32) 1.264 ftop/ctop/inf/cp/cpRespF$ENQ + SLICE_X107Y55.C Tilo 0.068 ftop/ctop/inf/cp/wci_0_pageWindow<11> + ftop/ctop/inf/cp/cpReq$EN_REPLICA_426 + SLICE_X97Y54.CE net (fanout=2) 0.720 ftop/ctop/inf/cp/cpReq$EN_REPLICA_426 + SLICE_X97Y54.CLK Tceck 0.318 ftop/ctop/inf/cp/cpReq<6>_REPLICA_33 + ftop/ctop/inf/cp/cpReq<6>_REPLICA_33 + ------------------------------------------------- --------------------------- + Total 10.009ns (1.638ns logic, 8.371ns route) + (16.4% logic, 83.6% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -2.134ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/wci_14_respF/empty_reg (FF) + Destination: ftop/ctop/inf/cp/cpReq<20>_REPLICA_86 (FF) + Requirement: 8.000ns + Data Path Delay: 10.009ns (Levels of Logic = 9) + Clock Path Skew: -0.056ns (1.015 - 1.071) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.069ns + + Clock Uncertainty: 0.069ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/wci_14_respF/empty_reg to ftop/ctop/inf/cp/cpReq<20>_REPLICA_86 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X102Y46.CQ Tcko 0.381 ftop/ctop/inf/cp/wci_14_respF$EMPTY_N + ftop/ctop/inf/cp/wci_14_respF/empty_reg + SLICE_X119Y44.A3 net (fanout=43) 1.190 ftop/ctop/inf/cp/wci_14_respF$EMPTY_N + SLICE_X119Y44.A Tilo 0.068 ftop/ctop/inf/cp/NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942_REPLICA_705 + ftop/ctop/inf/cp/NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942_REPLICA_705 + SLICE_X109Y44.A1 net (fanout=5) 0.949 ftop/ctop/inf/cp/NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942_REPLICA_705 + SLICE_X109Y44.BMUX Topab 0.395 ftop/ctop/inf/cp/CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4551 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4551_3_f71 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4551_3_f7 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4551_2_f8 + SLICE_X114Y47.D6 net (fanout=4) 0.561 ftop/ctop/inf/cp/CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4551 + SLICE_X114Y47.D Tilo 0.068 ftop/ctop/inf/cp/wci_10_respF$EMPTY_N + ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_T_T1 + SLICE_X103Y50.D2 net (fanout=39) 1.075 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_T_T + SLICE_X103Y50.D Tilo 0.068 ftop/ctop/inf/cp/cpReq<21>_REPLICA_178 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead16 + SLICE_X103Y50.C2 net (fanout=1) 0.463 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead16 + SLICE_X103Y50.C Tilo 0.068 ftop/ctop/inf/cp/cpReq<21>_REPLICA_178 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead17 + SLICE_X101Y51.B6 net (fanout=1) 0.376 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead17 + SLICE_X101Y51.B Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_T_F + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead26 + SLICE_X101Y51.A2 net (fanout=1) 0.465 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead26 + SLICE_X101Y51.A Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_T_F + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead32 + SLICE_X124Y42.B6 net (fanout=21) 1.308 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead + SLICE_X124Y42.B Tilo 0.068 ftop/ctop/inf/cp/cpRespF/d0h + ftop/ctop/inf/cp/cpRespF$ENQ + SLICE_X107Y55.C6 net (fanout=32) 1.264 ftop/ctop/inf/cp/cpRespF$ENQ + SLICE_X107Y55.C Tilo 0.068 ftop/ctop/inf/cp/wci_0_pageWindow<11> + ftop/ctop/inf/cp/cpReq$EN_REPLICA_426 + SLICE_X97Y54.CE net (fanout=2) 0.720 ftop/ctop/inf/cp/cpReq$EN_REPLICA_426 + SLICE_X97Y54.CLK Tceck 0.318 ftop/ctop/inf/cp/cpReq<6>_REPLICA_33 + ftop/ctop/inf/cp/cpReq<20>_REPLICA_86 + ------------------------------------------------- --------------------------- + Total 10.009ns (1.638ns logic, 8.371ns route) + (16.4% logic, 83.6% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -2.115ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/cpReq_24 (FF) + Destination: ftop/ctop/inf/cp/cpReq<23>_REPLICA_339 (FF) + Requirement: 8.000ns + Data Path Delay: 9.982ns (Levels of Logic = 10) + Clock Path Skew: -0.064ns (0.994 - 1.058) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.069ns + + Clock Uncertainty: 0.069ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/cpReq_24 to ftop/ctop/inf/cp/cpReq<23>_REPLICA_339 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X108Y47.AQ Tcko 0.381 ftop/ctop/inf/cp/cpReq<27> + ftop/ctop/inf/cp/cpReq_24 + SLICE_X109Y47.D3 net (fanout=72) 0.503 ftop/ctop/inf/cp/cpReq<24> + SLICE_X109Y47.D Tilo 0.068 ftop/ctop/inf/cp/wci_6_wReset_n + ftop/ctop/inf/cp/Msub_wn___1__h76499_xor<2>11 + SLICE_X106Y46.D2 net (fanout=50) 0.779 ftop/ctop/inf/cp/wn___1__h76499<2> + SLICE_X106Y46.D Tilo 0.068 ftop/ctop/inf/cp/wci_6_respF$EMPTY_N + ftop/ctop/inf/cp/Mmux__theResult_____1__h7573931 + SLICE_X106Y47.CX net (fanout=37) 0.535 ftop/ctop/inf/cp/_theResult_____1__h75739<2> + SLICE_X106Y47.BMUX Tcxb 0.331 ftop/ctop/inf/cp/CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793_4_f7 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793_2_f8 + SLICE_X100Y55.B6 net (fanout=10) 0.722 ftop/ctop/inf/cp/CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793 + SLICE_X100Y55.B Tilo 0.068 ftop/ctop/inf/cp/wci_0_respF$D_OUT<22> + ftop/ctop/inf/cp/_n13764<34>21 + SLICE_X96Y54.A6 net (fanout=76) 0.516 ftop/ctop/inf/cp/_n13764<34>2 + SLICE_X96Y54.A Tilo 0.068 ftop/ctop/inf/cp/wci_7_respF$D_OUT<21> + ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_F_T1 + SLICE_X97Y52.B2 net (fanout=13) 0.723 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_F_T + SLICE_X97Y52.B Tilo 0.068 ftop/ctop/inf/cp/cpReq<8>_REPLICA_52 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead24 + SLICE_X101Y51.B1 net (fanout=1) 0.866 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead24 + SLICE_X101Y51.B Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_T_F + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead26 + SLICE_X101Y51.A2 net (fanout=1) 0.465 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead26 + SLICE_X101Y51.A Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_T_F + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead32 + SLICE_X124Y42.B6 net (fanout=21) 1.308 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead + SLICE_X124Y42.B Tilo 0.068 ftop/ctop/inf/cp/cpRespF/d0h + ftop/ctop/inf/cp/cpRespF$ENQ + SLICE_X105Y57.C5 net (fanout=32) 1.452 ftop/ctop/inf/cp/cpRespF$ENQ + SLICE_X105Y57.C Tilo 0.068 ftop/ctop/inf/cp/wci_12_reqF_q_0<53> + ftop/ctop/inf/cp/cpReq$EN_REPLICA_443 + SLICE_X102Y59.CE net (fanout=2) 0.505 ftop/ctop/inf/cp/cpReq$EN_REPLICA_443 + SLICE_X102Y59.CLK Tceck 0.284 ftop/ctop/inf/cp/cpReq<23>_REPLICA_339 + ftop/ctop/inf/cp/cpReq<23>_REPLICA_339 + ------------------------------------------------- --------------------------- + Total 9.982ns (1.608ns logic, 8.374ns route) + (16.1% logic, 83.9% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -2.115ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/cpReq_24 (FF) + Destination: ftop/ctop/inf/cp/cpReq<7>_REPLICA_44 (FF) + Requirement: 8.000ns + Data Path Delay: 10.003ns (Levels of Logic = 10) + Clock Path Skew: -0.043ns (1.015 - 1.058) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.069ns + + Clock Uncertainty: 0.069ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/cpReq_24 to ftop/ctop/inf/cp/cpReq<7>_REPLICA_44 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X108Y47.AQ Tcko 0.381 ftop/ctop/inf/cp/cpReq<27> + ftop/ctop/inf/cp/cpReq_24 + SLICE_X109Y47.D3 net (fanout=72) 0.503 ftop/ctop/inf/cp/cpReq<24> + SLICE_X109Y47.D Tilo 0.068 ftop/ctop/inf/cp/wci_6_wReset_n + ftop/ctop/inf/cp/Msub_wn___1__h76499_xor<2>11 + SLICE_X106Y46.D2 net (fanout=50) 0.779 ftop/ctop/inf/cp/wn___1__h76499<2> + SLICE_X106Y46.D Tilo 0.068 ftop/ctop/inf/cp/wci_6_respF$EMPTY_N + ftop/ctop/inf/cp/Mmux__theResult_____1__h7573931 + SLICE_X106Y47.CX net (fanout=37) 0.535 ftop/ctop/inf/cp/_theResult_____1__h75739<2> + SLICE_X106Y47.BMUX Tcxb 0.331 ftop/ctop/inf/cp/CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793_4_f7 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793_2_f8 + SLICE_X100Y55.B6 net (fanout=10) 0.722 ftop/ctop/inf/cp/CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793 + SLICE_X100Y55.B Tilo 0.068 ftop/ctop/inf/cp/wci_0_respF$D_OUT<22> + ftop/ctop/inf/cp/_n13764<34>21 + SLICE_X96Y54.A6 net (fanout=76) 0.516 ftop/ctop/inf/cp/_n13764<34>2 + SLICE_X96Y54.A Tilo 0.068 ftop/ctop/inf/cp/wci_7_respF$D_OUT<21> + ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_F_T1 + SLICE_X97Y52.B2 net (fanout=13) 0.723 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_F_T + SLICE_X97Y52.B Tilo 0.068 ftop/ctop/inf/cp/cpReq<8>_REPLICA_52 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead24 + SLICE_X101Y51.B1 net (fanout=1) 0.866 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead24 + SLICE_X101Y51.B Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_T_F + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead26 + SLICE_X101Y51.A2 net (fanout=1) 0.465 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead26 + SLICE_X101Y51.A Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_T_F + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead32 + SLICE_X124Y42.B6 net (fanout=21) 1.308 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead + SLICE_X124Y42.B Tilo 0.068 ftop/ctop/inf/cp/cpRespF/d0h + ftop/ctop/inf/cp/cpRespF$ENQ + SLICE_X107Y55.C6 net (fanout=32) 1.264 ftop/ctop/inf/cp/cpRespF$ENQ + SLICE_X107Y55.C Tilo 0.068 ftop/ctop/inf/cp/wci_0_pageWindow<11> + ftop/ctop/inf/cp/cpReq$EN_REPLICA_426 + SLICE_X97Y54.CE net (fanout=2) 0.720 ftop/ctop/inf/cp/cpReq$EN_REPLICA_426 + SLICE_X97Y54.CLK Tceck 0.278 ftop/ctop/inf/cp/cpReq<6>_REPLICA_33 + ftop/ctop/inf/cp/cpReq<7>_REPLICA_44 + ------------------------------------------------- --------------------------- + Total 10.003ns (1.602ns logic, 8.401ns route) + (16.0% logic, 84.0% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -2.111ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/cpReq_24 (FF) + Destination: ftop/ctop/inf/cp/cpReq<7>_REPLICA_44 (FF) + Requirement: 8.000ns + Data Path Delay: 9.999ns (Levels of Logic = 10) + Clock Path Skew: -0.043ns (1.015 - 1.058) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.069ns + + Clock Uncertainty: 0.069ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/cpReq_24 to ftop/ctop/inf/cp/cpReq<7>_REPLICA_44 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X108Y47.AQ Tcko 0.381 ftop/ctop/inf/cp/cpReq<27> + ftop/ctop/inf/cp/cpReq_24 + SLICE_X109Y47.D3 net (fanout=72) 0.503 ftop/ctop/inf/cp/cpReq<24> + SLICE_X109Y47.D Tilo 0.068 ftop/ctop/inf/cp/wci_6_wReset_n + ftop/ctop/inf/cp/Msub_wn___1__h76499_xor<2>11 + SLICE_X106Y46.D2 net (fanout=50) 0.779 ftop/ctop/inf/cp/wn___1__h76499<2> + SLICE_X106Y46.D Tilo 0.068 ftop/ctop/inf/cp/wci_6_respF$EMPTY_N + ftop/ctop/inf/cp/Mmux__theResult_____1__h7573931 + SLICE_X106Y47.AX net (fanout=37) 0.537 ftop/ctop/inf/cp/_theResult_____1__h75739<2> + SLICE_X106Y47.BMUX Taxb 0.325 ftop/ctop/inf/cp/CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793_3_f7 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793_2_f8 + SLICE_X100Y55.B6 net (fanout=10) 0.722 ftop/ctop/inf/cp/CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793 + SLICE_X100Y55.B Tilo 0.068 ftop/ctop/inf/cp/wci_0_respF$D_OUT<22> + ftop/ctop/inf/cp/_n13764<34>21 + SLICE_X96Y54.A6 net (fanout=76) 0.516 ftop/ctop/inf/cp/_n13764<34>2 + SLICE_X96Y54.A Tilo 0.068 ftop/ctop/inf/cp/wci_7_respF$D_OUT<21> + ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_F_T1 + SLICE_X97Y52.B2 net (fanout=13) 0.723 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_F_T + SLICE_X97Y52.B Tilo 0.068 ftop/ctop/inf/cp/cpReq<8>_REPLICA_52 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead24 + SLICE_X101Y51.B1 net (fanout=1) 0.866 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead24 + SLICE_X101Y51.B Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_T_F + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead26 + SLICE_X101Y51.A2 net (fanout=1) 0.465 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead26 + SLICE_X101Y51.A Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_T_F + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead32 + SLICE_X124Y42.B6 net (fanout=21) 1.308 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead + SLICE_X124Y42.B Tilo 0.068 ftop/ctop/inf/cp/cpRespF/d0h + ftop/ctop/inf/cp/cpRespF$ENQ + SLICE_X107Y55.C6 net (fanout=32) 1.264 ftop/ctop/inf/cp/cpRespF$ENQ + SLICE_X107Y55.C Tilo 0.068 ftop/ctop/inf/cp/wci_0_pageWindow<11> + ftop/ctop/inf/cp/cpReq$EN_REPLICA_426 + SLICE_X97Y54.CE net (fanout=2) 0.720 ftop/ctop/inf/cp/cpReq$EN_REPLICA_426 + SLICE_X97Y54.CLK Tceck 0.278 ftop/ctop/inf/cp/cpReq<6>_REPLICA_33 + ftop/ctop/inf/cp/cpReq<7>_REPLICA_44 + ------------------------------------------------- --------------------------- + Total 9.999ns (1.596ns logic, 8.403ns route) + (16.0% logic, 84.0% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -2.111ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/cpReq_24 (FF) + Destination: ftop/ctop/inf/cp/cpReq<23>_REPLICA_339 (FF) + Requirement: 8.000ns + Data Path Delay: 9.978ns (Levels of Logic = 10) + Clock Path Skew: -0.064ns (0.994 - 1.058) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.069ns + + Clock Uncertainty: 0.069ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/cpReq_24 to ftop/ctop/inf/cp/cpReq<23>_REPLICA_339 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X108Y47.AQ Tcko 0.381 ftop/ctop/inf/cp/cpReq<27> + ftop/ctop/inf/cp/cpReq_24 + SLICE_X109Y47.D3 net (fanout=72) 0.503 ftop/ctop/inf/cp/cpReq<24> + SLICE_X109Y47.D Tilo 0.068 ftop/ctop/inf/cp/wci_6_wReset_n + ftop/ctop/inf/cp/Msub_wn___1__h76499_xor<2>11 + SLICE_X106Y46.D2 net (fanout=50) 0.779 ftop/ctop/inf/cp/wn___1__h76499<2> + SLICE_X106Y46.D Tilo 0.068 ftop/ctop/inf/cp/wci_6_respF$EMPTY_N + ftop/ctop/inf/cp/Mmux__theResult_____1__h7573931 + SLICE_X106Y47.AX net (fanout=37) 0.537 ftop/ctop/inf/cp/_theResult_____1__h75739<2> + SLICE_X106Y47.BMUX Taxb 0.325 ftop/ctop/inf/cp/CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793_3_f7 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793_2_f8 + SLICE_X100Y55.B6 net (fanout=10) 0.722 ftop/ctop/inf/cp/CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793 + SLICE_X100Y55.B Tilo 0.068 ftop/ctop/inf/cp/wci_0_respF$D_OUT<22> + ftop/ctop/inf/cp/_n13764<34>21 + SLICE_X96Y54.A6 net (fanout=76) 0.516 ftop/ctop/inf/cp/_n13764<34>2 + SLICE_X96Y54.A Tilo 0.068 ftop/ctop/inf/cp/wci_7_respF$D_OUT<21> + ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_F_T1 + SLICE_X97Y52.B2 net (fanout=13) 0.723 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_F_T + SLICE_X97Y52.B Tilo 0.068 ftop/ctop/inf/cp/cpReq<8>_REPLICA_52 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead24 + SLICE_X101Y51.B1 net (fanout=1) 0.866 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead24 + SLICE_X101Y51.B Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_T_F + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead26 + SLICE_X101Y51.A2 net (fanout=1) 0.465 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead26 + SLICE_X101Y51.A Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_T_F + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead32 + SLICE_X124Y42.B6 net (fanout=21) 1.308 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead + SLICE_X124Y42.B Tilo 0.068 ftop/ctop/inf/cp/cpRespF/d0h + ftop/ctop/inf/cp/cpRespF$ENQ + SLICE_X105Y57.C5 net (fanout=32) 1.452 ftop/ctop/inf/cp/cpRespF$ENQ + SLICE_X105Y57.C Tilo 0.068 ftop/ctop/inf/cp/wci_12_reqF_q_0<53> + ftop/ctop/inf/cp/cpReq$EN_REPLICA_443 + SLICE_X102Y59.CE net (fanout=2) 0.505 ftop/ctop/inf/cp/cpReq$EN_REPLICA_443 + SLICE_X102Y59.CLK Tceck 0.284 ftop/ctop/inf/cp/cpReq<23>_REPLICA_339 + ftop/ctop/inf/cp/cpReq<23>_REPLICA_339 + ------------------------------------------------- --------------------------- + Total 9.978ns (1.602ns logic, 8.376ns route) + (16.1% logic, 83.9% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -2.109ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/ctop/inf/cp/cpReq_24 (FF) + Destination: ftop/ctop/inf/cp/cpReq<21>_REPLICA_174 (FF) + Requirement: 8.000ns + Data Path Delay: 9.993ns (Levels of Logic = 10) + Clock Path Skew: -0.047ns (1.011 - 1.058) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.069ns + + Clock Uncertainty: 0.069ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/ctop/inf/cp/cpReq_24 to ftop/ctop/inf/cp/cpReq<21>_REPLICA_174 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X108Y47.AQ Tcko 0.381 ftop/ctop/inf/cp/cpReq<27> + ftop/ctop/inf/cp/cpReq_24 + SLICE_X109Y47.D3 net (fanout=72) 0.503 ftop/ctop/inf/cp/cpReq<24> + SLICE_X109Y47.D Tilo 0.068 ftop/ctop/inf/cp/wci_6_wReset_n + ftop/ctop/inf/cp/Msub_wn___1__h76499_xor<2>11 + SLICE_X106Y46.D2 net (fanout=50) 0.779 ftop/ctop/inf/cp/wn___1__h76499<2> + SLICE_X106Y46.D Tilo 0.068 ftop/ctop/inf/cp/wci_6_respF$EMPTY_N + ftop/ctop/inf/cp/Mmux__theResult_____1__h7573931 + SLICE_X106Y47.CX net (fanout=37) 0.535 ftop/ctop/inf/cp/_theResult_____1__h75739<2> + SLICE_X106Y47.BMUX Tcxb 0.331 ftop/ctop/inf/cp/CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793_4_f7 + ftop/ctop/inf/cp/Mmux_CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793_2_f8 + SLICE_X101Y52.D5 net (fanout=10) 0.637 ftop/ctop/inf/cp/CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793 + SLICE_X101Y52.D Tilo 0.068 ftop/ctop/inf/cp/cpReq<37>_REPLICA_374 + ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_F_F_F_F_F2 + SLICE_X97Y60.A6 net (fanout=18) 0.814 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_F_F_F_F_F2 + SLICE_X97Y60.A Tilo 0.068 flash_addr_11_OBUF + ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_F_F_F_F_F_F1 + SLICE_X101Y49.C3 net (fanout=2) 1.004 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_F_F_F_F_F_F + SLICE_X101Y49.C Tilo 0.068 ftop/ctop/inf/cp/N466 + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead21 + SLICE_X101Y51.B5 net (fanout=1) 0.310 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead21 + SLICE_X101Y51.B Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_T_F + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead26 + SLICE_X101Y51.A2 net (fanout=1) 0.465 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead26 + SLICE_X101Y51.A Tilo 0.068 ftop/ctop/inf/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_T_F + ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead32 + SLICE_X124Y42.B6 net (fanout=21) 1.308 ftop/ctop/inf/cp/WILL_FIRE_RL_completeWorkerRead + SLICE_X124Y42.B Tilo 0.068 ftop/ctop/inf/cp/cpRespF/d0h + ftop/ctop/inf/cp/cpRespF$ENQ + SLICE_X104Y55.C6 net (fanout=32) 1.399 ftop/ctop/inf/cp/cpRespF$ENQ + SLICE_X104Y55.C Tilo 0.068 ftop/ctop/inf/cp/wci_0_lastConfigAddr<12> + ftop/ctop/inf/cp/cpReq$EN_REPLICA_439 + SLICE_X98Y56.CE net (fanout=1) 0.597 ftop/ctop/inf/cp/cpReq$EN_REPLICA_439 + SLICE_X98Y56.CLK Tceck 0.318 ftop/ctop/inf/cp/cpReq<21>_REPLICA_174 + ftop/ctop/inf/cp/cpReq<21>_REPLICA_174 + ------------------------------------------------- --------------------------- + Total 9.993ns (1.642ns logic, 8.351ns route) + (16.4% logic, 83.6% route) + +-------------------------------------------------------------------------------- + +Hold Paths: TS_CLK_125 = PERIOD TIMEGRP "CLK_125" TS_PCICLK / 2 HIGH 50% PRIORITY 100; +-------------------------------------------------------------------------------- +Slack (hold path): 0.001ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_p2iS_26 (FF) + Destination: ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_52_o_dat[15][152]_wide_mux_5_OUT_26_0 (FF) + Requirement: 0.000ns + Data Path Delay: 0.265ns (Levels of Logic = 0) + Clock Path Skew: 0.075ns (1.219 - 1.144) + Source Clock: ftop/pciw_pci0_pcie_ep$trn_clk rising at 8.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.189ns + + Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.120ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_p2iS_26 to ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_52_o_dat[15][152]_wide_mux_5_OUT_26_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X153Y172.CQ Tcko 0.098 ftop/pciw_p2iS<27> + ftop/pciw_p2iS_26 + SLICE_X152Y175.CX net (fanout=1) 0.197 ftop/pciw_p2iS<26> + SLICE_X152Y175.CLK Tdh (-Th) 0.030 ftop/ctop/inf/noc_sm0/pktFork/fi$D_OUT<27> + ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_52_o_dat[15][152]_wide_mux_5_OUT_26_0 + ------------------------------------------------- --------------------------- + Total 0.265ns (0.068ns logic, 0.197ns route) + (25.7% logic, 74.3% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.002ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_p2iS_5 (FF) + Destination: ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_52_o_dat[15][152]_wide_mux_5_OUT_5_0 (FF) + Requirement: 0.000ns + Data Path Delay: 0.270ns (Levels of Logic = 0) + Clock Path Skew: 0.079ns (1.227 - 1.148) + Source Clock: ftop/pciw_pci0_pcie_ep$trn_clk rising at 8.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.189ns + + Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.120ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_p2iS_5 to ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_52_o_dat[15][152]_wide_mux_5_OUT_5_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X153Y167.BQ Tcko 0.098 ftop/pciw_p2iS<7> + ftop/pciw_p2iS_5 + SLICE_X152Y167.BX net (fanout=1) 0.199 ftop/pciw_p2iS<5> + SLICE_X152Y167.CLK Tdh (-Th) 0.027 ftop/ctop/inf/noc_sm0/pktFork/fi$D_OUT<7> + ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_52_o_dat[15][152]_wide_mux_5_OUT_5_0 + ------------------------------------------------- --------------------------- + Total 0.270ns (0.071ns logic, 0.199ns route) + (26.3% logic, 73.7% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.003ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_p2iS_8 (FF) + Destination: ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_52_o_dat[15][152]_wide_mux_5_OUT_8_0 (FF) + Requirement: 0.000ns + Data Path Delay: 0.268ns (Levels of Logic = 0) + Clock Path Skew: 0.076ns (1.224 - 1.148) + Source Clock: ftop/pciw_pci0_pcie_ep$trn_clk rising at 8.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.189ns + + Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.120ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_p2iS_8 to ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_52_o_dat[15][152]_wide_mux_5_OUT_8_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X154Y167.AQ Tcko 0.098 ftop/pciw_p2iS<11> + ftop/pciw_p2iS_8 + SLICE_X158Y172.AX net (fanout=1) 0.206 ftop/pciw_p2iS<8> + SLICE_X158Y172.CLK Tdh (-Th) 0.036 ftop/ctop/inf/noc_sm0/pktFork/fi$D_OUT<11> + ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_52_o_dat[15][152]_wide_mux_5_OUT_8_0 + ------------------------------------------------- --------------------------- + Total 0.268ns (0.062ns logic, 0.206ns route) + (23.1% logic, 76.9% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.005ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_p2iS_11 (FF) + Destination: ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_52_o_dat[15][152]_wide_mux_5_OUT_11_0 (FF) + Requirement: 0.000ns + Data Path Delay: 0.270ns (Levels of Logic = 0) + Clock Path Skew: 0.076ns (1.224 - 1.148) + Source Clock: ftop/pciw_pci0_pcie_ep$trn_clk rising at 8.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.189ns + + Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.120ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_p2iS_11 to ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_52_o_dat[15][152]_wide_mux_5_OUT_11_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X154Y167.DQ Tcko 0.098 ftop/pciw_p2iS<11> + ftop/pciw_p2iS_11 + SLICE_X158Y172.DX net (fanout=1) 0.210 ftop/pciw_p2iS<11> + SLICE_X158Y172.CLK Tdh (-Th) 0.038 ftop/ctop/inf/noc_sm0/pktFork/fi$D_OUT<11> + ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_52_o_dat[15][152]_wide_mux_5_OUT_11_0 + ------------------------------------------------- --------------------------- + Total 0.270ns (0.060ns logic, 0.210ns route) + (22.2% logic, 77.8% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.008ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_p2iS_30 (FF) + Destination: ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_52_o_dat[15][152]_wide_mux_5_OUT_30_0 (FF) + Requirement: 0.000ns + Data Path Delay: 0.269ns (Levels of Logic = 0) + Clock Path Skew: 0.072ns (1.218 - 1.146) + Source Clock: ftop/pciw_pci0_pcie_ep$trn_clk rising at 8.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.189ns + + Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.120ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_p2iS_30 to ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_52_o_dat[15][152]_wide_mux_5_OUT_30_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X153Y170.CQ Tcko 0.098 ftop/pciw_p2iS<31> + ftop/pciw_p2iS_30 + SLICE_X152Y176.CX net (fanout=1) 0.201 ftop/pciw_p2iS<30> + SLICE_X152Y176.CLK Tdh (-Th) 0.030 ftop/ctop/inf/noc_sm0/pktFork/fi$D_OUT<31> + ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_52_o_dat[15][152]_wide_mux_5_OUT_30_0 + ------------------------------------------------- --------------------------- + Total 0.269ns (0.068ns logic, 0.201ns route) + (25.3% logic, 74.7% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.010ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_p2iS_10 (FF) + Destination: ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_52_o_dat[15][152]_wide_mux_5_OUT_10_0 (FF) + Requirement: 0.000ns + Data Path Delay: 0.275ns (Levels of Logic = 0) + Clock Path Skew: 0.076ns (1.224 - 1.148) + Source Clock: ftop/pciw_pci0_pcie_ep$trn_clk rising at 8.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.189ns + + Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.120ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_p2iS_10 to ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_52_o_dat[15][152]_wide_mux_5_OUT_10_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X154Y167.CQ Tcko 0.098 ftop/pciw_p2iS<11> + ftop/pciw_p2iS_10 + SLICE_X158Y172.CX net (fanout=1) 0.207 ftop/pciw_p2iS<10> + SLICE_X158Y172.CLK Tdh (-Th) 0.030 ftop/ctop/inf/noc_sm0/pktFork/fi$D_OUT<11> + ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_52_o_dat[15][152]_wide_mux_5_OUT_10_0 + ------------------------------------------------- --------------------------- + Total 0.275ns (0.068ns logic, 0.207ns route) + (24.7% logic, 75.3% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.012ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_p2iS_32 (FF) + Destination: ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_52_o_dat[15][152]_wide_mux_5_OUT_32_0 (FF) + Requirement: 0.000ns + Data Path Delay: 0.272ns (Levels of Logic = 0) + Clock Path Skew: 0.071ns (1.213 - 1.142) + Source Clock: ftop/pciw_pci0_pcie_ep$trn_clk rising at 8.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.189ns + + Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.120ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_p2iS_32 to ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_52_o_dat[15][152]_wide_mux_5_OUT_32_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X145Y168.AQ Tcko 0.098 ftop/pciw_p2iS<35> + ftop/pciw_p2iS_32 + SLICE_X136Y167.AX net (fanout=1) 0.210 ftop/pciw_p2iS<32> + SLICE_X136Y167.CLK Tdh (-Th) 0.036 ftop/ctop/inf/noc_sm0/pktFork/fi$D_OUT<35> + ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_52_o_dat[15][152]_wide_mux_5_OUT_32_0 + ------------------------------------------------- --------------------------- + Total 0.272ns (0.062ns logic, 0.210ns route) + (22.8% logic, 77.2% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.016ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_p2iS_9 (FF) + Destination: ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_52_o_dat[15][152]_wide_mux_5_OUT_9_0 (FF) + Requirement: 0.000ns + Data Path Delay: 0.281ns (Levels of Logic = 0) + Clock Path Skew: 0.076ns (1.224 - 1.148) + Source Clock: ftop/pciw_pci0_pcie_ep$trn_clk rising at 8.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.189ns + + Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.120ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_p2iS_9 to ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_52_o_dat[15][152]_wide_mux_5_OUT_9_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X154Y167.BQ Tcko 0.098 ftop/pciw_p2iS<11> + ftop/pciw_p2iS_9 + SLICE_X158Y172.BX net (fanout=1) 0.210 ftop/pciw_p2iS<9> + SLICE_X158Y172.CLK Tdh (-Th) 0.027 ftop/ctop/inf/noc_sm0/pktFork/fi$D_OUT<11> + ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_52_o_dat[15][152]_wide_mux_5_OUT_9_0 + ------------------------------------------------- --------------------------- + Total 0.281ns (0.071ns logic, 0.210ns route) + (25.3% logic, 74.7% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.017ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_p2iS_47 (FF) + Destination: ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_52_o_dat[15][152]_wide_mux_5_OUT_47_0 (FF) + Requirement: 0.000ns + Data Path Delay: 0.279ns (Levels of Logic = 0) + Clock Path Skew: 0.073ns (1.222 - 1.149) + Source Clock: ftop/pciw_pci0_pcie_ep$trn_clk rising at 8.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.189ns + + Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.120ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_p2iS_47 to ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_52_o_dat[15][152]_wide_mux_5_OUT_47_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X158Y166.DQ Tcko 0.115 ftop/pciw_p2iS<47> + ftop/pciw_p2iS_47 + SLICE_X158Y173.DX net (fanout=1) 0.202 ftop/pciw_p2iS<47> + SLICE_X158Y173.CLK Tdh (-Th) 0.038 ftop/ctop/inf/noc_sm0/pktFork/fi$D_OUT<47> + ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_52_o_dat[15][152]_wide_mux_5_OUT_47_0 + ------------------------------------------------- --------------------------- + Total 0.279ns (0.077ns logic, 0.202ns route) + (27.6% logic, 72.4% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.017ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/ctop/app/appW4/wmi_reqF_q_1_19 (FF) + Destination: ftop/ctop/app/appW4/wmi_reqF_q_0_19 (FF) + Requirement: 0.000ns + Data Path Delay: 0.125ns (Levels of Logic = 1) + Clock Path Skew: 0.108ns (0.797 - 0.689) + Source Clock: ftop/p125clk rising at 8.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/ctop/app/appW4/wmi_reqF_q_1_19 to ftop/ctop/app/appW4/wmi_reqF_q_0_19 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X98Y159.CQ Tcko 0.098 ftop/ctop/app/appW4/wmi_reqF_q_1<20> + ftop/ctop/app/appW4/wmi_reqF_q_1_19 + SLICE_X99Y160.D6 net (fanout=1) 0.084 ftop/ctop/app/appW4/wmi_reqF_q_1<19> + SLICE_X99Y160.CLK Tah (-Th) 0.057 ftop/ctop/app/appW4/wmi_reqF_q_0<19> + ftop/ctop/app/appW4/wmi_reqF_q_0$D_IN<19> + ftop/ctop/app/appW4/wmi_reqF_q_0_19 + ------------------------------------------------- --------------------------- + Total 0.125ns (0.041ns logic, 0.084ns route) + (32.8% logic, 67.2% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.018ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_p2iS_34 (FF) + Destination: ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_52_o_dat[15][152]_wide_mux_5_OUT_34_0 (FF) + Requirement: 0.000ns + Data Path Delay: 0.278ns (Levels of Logic = 0) + Clock Path Skew: 0.071ns (1.213 - 1.142) + Source Clock: ftop/pciw_pci0_pcie_ep$trn_clk rising at 8.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.189ns + + Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.120ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_p2iS_34 to ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_52_o_dat[15][152]_wide_mux_5_OUT_34_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X145Y168.CQ Tcko 0.098 ftop/pciw_p2iS<35> + ftop/pciw_p2iS_34 + SLICE_X136Y167.CX net (fanout=1) 0.210 ftop/pciw_p2iS<34> + SLICE_X136Y167.CLK Tdh (-Th) 0.030 ftop/ctop/inf/noc_sm0/pktFork/fi$D_OUT<35> + ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_52_o_dat[15][152]_wide_mux_5_OUT_34_0 + ------------------------------------------------- --------------------------- + Total 0.278ns (0.068ns logic, 0.210ns route) + (24.5% logic, 75.5% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.019ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_p2iS_80 (FF) + Destination: ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_52_o_dat[15][152]_wide_mux_5_OUT_80_0 (FF) + Requirement: 0.000ns + Data Path Delay: 0.282ns (Levels of Logic = 0) + Clock Path Skew: 0.074ns (1.222 - 1.148) + Source Clock: ftop/pciw_pci0_pcie_ep$trn_clk rising at 8.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.189ns + + Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.120ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_p2iS_80 to ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_52_o_dat[15][152]_wide_mux_5_OUT_80_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X153Y165.AQ Tcko 0.098 ftop/pciw_p2iS<83> + ftop/pciw_p2iS_80 + SLICE_X144Y165.AX net (fanout=1) 0.220 ftop/pciw_p2iS<80> + SLICE_X144Y165.CLK Tdh (-Th) 0.036 ftop/ctop/inf/noc_sm0/pktFork/fi$D_OUT<83> + ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_52_o_dat[15][152]_wide_mux_5_OUT_80_0 + ------------------------------------------------- --------------------------- + Total 0.282ns (0.062ns logic, 0.220ns route) + (22.0% logic, 78.0% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.020ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_i2pAF_head_wrapped (FF) + Destination: ftop/pciw_i2pAF_tail_wrapped (FF) + Requirement: 0.000ns + Data Path Delay: 0.282ns (Levels of Logic = 1) + Clock Path Skew: 0.073ns (1.167 - 1.094) + Source Clock: ftop/pciw_pci0_pcie_ep$trn_clk rising at 8.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.189ns + + Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.120ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_i2pAF_head_wrapped to ftop/pciw_i2pAF_tail_wrapped + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X149Y120.CQ Tcko 0.098 ftop/pciw_i2pAF_head_wrapped + ftop/pciw_i2pAF_head_wrapped + SLICE_X147Y121.A6 net (fanout=7) 0.239 ftop/pciw_i2pAF_head_wrapped + SLICE_X147Y121.CLK Tah (-Th) 0.055 ftop/pciw_i2pAF_tail_wrapped + ftop/WILL_FIRE_RL_pciw_i2pAF_enq_update_tail11 + ftop/pciw_i2pAF_tail_wrapped + ------------------------------------------------- --------------------------- + Total 0.282ns (0.043ns logic, 0.239ns route) + (15.2% logic, 84.8% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.022ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_p2iS_39 (FF) + Destination: ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_52_o_dat[15][152]_wide_mux_5_OUT_39_0 (FF) + Requirement: 0.000ns + Data Path Delay: 0.286ns (Levels of Logic = 0) + Clock Path Skew: 0.075ns (1.220 - 1.145) + Source Clock: ftop/pciw_pci0_pcie_ep$trn_clk rising at 8.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.189ns + + Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.120ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_p2iS_39 to ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_52_o_dat[15][152]_wide_mux_5_OUT_39_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X151Y170.DQ Tcko 0.098 ftop/pciw_p2iS<39> + ftop/pciw_p2iS_39 + SLICE_X146Y170.DX net (fanout=1) 0.226 ftop/pciw_p2iS<39> + SLICE_X146Y170.CLK Tdh (-Th) 0.038 ftop/ctop/inf/noc_sm0/pktFork/fi$D_OUT<39> + ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_52_o_dat[15][152]_wide_mux_5_OUT_39_0 + ------------------------------------------------- --------------------------- + Total 0.286ns (0.060ns logic, 0.226ns route) + (21.0% logic, 79.0% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.022ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_p2iS_36 (FF) + Destination: ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_52_o_dat[15][152]_wide_mux_5_OUT_36_0 (FF) + Requirement: 0.000ns + Data Path Delay: 0.286ns (Levels of Logic = 0) + Clock Path Skew: 0.075ns (1.220 - 1.145) + Source Clock: ftop/pciw_pci0_pcie_ep$trn_clk rising at 8.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.189ns + + Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.120ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_p2iS_36 to ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_52_o_dat[15][152]_wide_mux_5_OUT_36_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X151Y170.AQ Tcko 0.098 ftop/pciw_p2iS<39> + ftop/pciw_p2iS_36 + SLICE_X146Y170.AX net (fanout=1) 0.224 ftop/pciw_p2iS<36> + SLICE_X146Y170.CLK Tdh (-Th) 0.036 ftop/ctop/inf/noc_sm0/pktFork/fi$D_OUT<39> + ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_52_o_dat[15][152]_wide_mux_5_OUT_36_0 + ------------------------------------------------- --------------------------- + Total 0.286ns (0.062ns logic, 0.224ns route) + (21.7% logic, 78.3% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.023ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_p2iS_19 (FF) + Destination: ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_52_o_dat[15][152]_wide_mux_5_OUT_19_0 (FF) + Requirement: 0.000ns + Data Path Delay: 0.285ns (Levels of Logic = 0) + Clock Path Skew: 0.073ns (1.221 - 1.148) + Source Clock: ftop/pciw_pci0_pcie_ep$trn_clk rising at 8.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.189ns + + Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.120ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_p2iS_19 to ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_52_o_dat[15][152]_wide_mux_5_OUT_19_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X153Y166.DQ Tcko 0.098 ftop/pciw_p2iS<19> + ftop/pciw_p2iS_19 + SLICE_X144Y167.DX net (fanout=1) 0.225 ftop/pciw_p2iS<19> + SLICE_X144Y167.CLK Tdh (-Th) 0.038 ftop/ctop/inf/noc_sm0/pktFork/fi$D_OUT<19> + ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_52_o_dat[15][152]_wide_mux_5_OUT_19_0 + ------------------------------------------------- --------------------------- + Total 0.285ns (0.060ns logic, 0.225ns route) + (21.1% logic, 78.9% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.025ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_p2iAF_tail_wrapped (FF) + Destination: ftop/pciw_p2iAF_head_wrapped (FF) + Requirement: 0.000ns + Data Path Delay: 0.287ns (Levels of Logic = 1) + Clock Path Skew: 0.073ns (1.167 - 1.094) + Source Clock: ftop/pciw_pci0_pcie_ep$trn_clk rising at 8.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.189ns + + Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.120ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_p2iAF_tail_wrapped to ftop/pciw_p2iAF_head_wrapped + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X150Y155.AQ Tcko 0.098 ftop/pciw_p2iAF_tail_wrapped + ftop/pciw_p2iAF_tail_wrapped + SLICE_X147Y158.A5 net (fanout=7) 0.244 ftop/pciw_p2iAF_tail_wrapped + SLICE_X147Y158.CLK Tah (-Th) 0.055 ftop/pciw_p2iAF_head_wrapped + ftop/WILL_FIRE_RL_pciw_p2iAF_deq_update_head11 + ftop/pciw_p2iAF_head_wrapped + ------------------------------------------------- --------------------------- + Total 0.287ns (0.043ns logic, 0.244ns route) + (15.0% logic, 85.0% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.026ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_p2iS_82 (FF) + Destination: ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_52_o_dat[15][152]_wide_mux_5_OUT_82_0 (FF) + Requirement: 0.000ns + Data Path Delay: 0.289ns (Levels of Logic = 0) + Clock Path Skew: 0.074ns (1.222 - 1.148) + Source Clock: ftop/pciw_pci0_pcie_ep$trn_clk rising at 8.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.189ns + + Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.120ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_p2iS_82 to ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_52_o_dat[15][152]_wide_mux_5_OUT_82_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X153Y165.CQ Tcko 0.098 ftop/pciw_p2iS<83> + ftop/pciw_p2iS_82 + SLICE_X144Y165.CX net (fanout=1) 0.221 ftop/pciw_p2iS<82> + SLICE_X144Y165.CLK Tdh (-Th) 0.030 ftop/ctop/inf/noc_sm0/pktFork/fi$D_OUT<83> + ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_52_o_dat[15][152]_wide_mux_5_OUT_82_0 + ------------------------------------------------- --------------------------- + Total 0.289ns (0.068ns logic, 0.221ns route) + (23.5% logic, 76.5% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.027ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_p2iS_46 (FF) + Destination: ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_52_o_dat[15][152]_wide_mux_5_OUT_46_0 (FF) + Requirement: 0.000ns + Data Path Delay: 0.289ns (Levels of Logic = 0) + Clock Path Skew: 0.073ns (1.222 - 1.149) + Source Clock: ftop/pciw_pci0_pcie_ep$trn_clk rising at 8.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.189ns + + Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.120ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_p2iS_46 to ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_52_o_dat[15][152]_wide_mux_5_OUT_46_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X158Y166.CQ Tcko 0.115 ftop/pciw_p2iS<47> + ftop/pciw_p2iS_46 + SLICE_X158Y173.CX net (fanout=1) 0.204 ftop/pciw_p2iS<46> + SLICE_X158Y173.CLK Tdh (-Th) 0.030 ftop/ctop/inf/noc_sm0/pktFork/fi$D_OUT<47> + ftop/ctop/inf/noc_sm0/pktFork/fi/Mshreg_GND_52_o_dat[15][152]_wide_mux_5_OUT_46_0 + ------------------------------------------------- --------------------------- + Total 0.289ns (0.085ns logic, 0.204ns route) + (29.4% logic, 70.6% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.028ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/ctop/inf/dp0/bram_0_serverAdapterA_outDataCore/tail_0_0 (FF) + Destination: ftop/ctop/inf/dp0/bram_0_serverAdapterA_outDataCore/Mram_arr2_RAMA (RAM) + Requirement: 0.000ns + Data Path Delay: 0.063ns (Levels of Logic = 0) + Clock Path Skew: 0.035ns (0.497 - 0.462) + Source Clock: ftop/p125clk rising at 8.000ns + Destination Clock: ftop/p125clk rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/ctop/inf/dp0/bram_0_serverAdapterA_outDataCore/tail_0_0 to ftop/ctop/inf/dp0/bram_0_serverAdapterA_outDataCore/Mram_arr2_RAMA + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X2Y148.AQ Tcko 0.098 ftop/ctop/inf/dp0/bram_0_serverAdapterA_outDataCore/tail_0_0 + ftop/ctop/inf/dp0/bram_0_serverAdapterA_outDataCore/tail_0_0 + SLICE_X4Y147.D1 net (fanout=10) 0.244 ftop/ctop/inf/dp0/bram_0_serverAdapterA_outDataCore/tail_0_0 + SLICE_X4Y147.CLK Tah (-Th) 0.279 ftop/ctop/inf/dp0/bram_0_serverAdapterA_outDataCore/_n0101<11> + ftop/ctop/inf/dp0/bram_0_serverAdapterA_outDataCore/Mram_arr2_RAMA + ------------------------------------------------- --------------------------- + Total 0.063ns (-0.181ns logic, 0.244ns route) + (-287.3% logic, 387.3% route) + +-------------------------------------------------------------------------------- + +Component Switching Limit Checks: TS_CLK_125 = PERIOD TIMEGRP "CLK_125" TS_PCICLK / 2 HIGH 50% PRIORITY 100; +-------------------------------------------------------------------------------- +Slack: 0.308ns (period - min period limit) + Period: 8.000ns + Min period limit: 7.692ns (130.005MHz) (Tgtxper_DCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[0].GTX/DCLK + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[0].GTX/DCLK + Location pin: GTXE1_X0Y15.DCLK + Clock network: ftop/p125clk +-------------------------------------------------------------------------------- +Slack: 0.308ns (period - min period limit) + Period: 8.000ns + Min period limit: 7.692ns (130.005MHz) (Tgtxper_DCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[1].GTX/DCLK + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[1].GTX/DCLK + Location pin: GTXE1_X0Y14.DCLK + Clock network: ftop/p125clk +-------------------------------------------------------------------------------- +Slack: 0.308ns (period - min period limit) + Period: 8.000ns + Min period limit: 7.692ns (130.005MHz) (Tgtxper_DCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX/DCLK + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX/DCLK + Location pin: GTXE1_X0Y13.DCLK + Clock network: ftop/p125clk +-------------------------------------------------------------------------------- +Slack: 0.308ns (period - min period limit) + Period: 8.000ns + Min period limit: 7.692ns (130.005MHz) (Tgtxper_DCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX/DCLK + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX/DCLK + Location pin: GTXE1_X0Y12.DCLK + Clock network: ftop/p125clk +-------------------------------------------------------------------------------- +Slack: 4.000ns (period - min period limit) + Period: 8.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[0].GTX/RXUSRCLK + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[0].GTX/RXUSRCLK + Location pin: GTXE1_X0Y15.RXUSRCLK + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 4.000ns (period - min period limit) + Period: 8.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[0].GTX/RXUSRCLK2 + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[0].GTX/RXUSRCLK2 + Location pin: GTXE1_X0Y15.RXUSRCLK2 + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 4.000ns (period - min period limit) + Period: 8.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[0].GTX/TXUSRCLK + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[0].GTX/TXUSRCLK + Location pin: GTXE1_X0Y15.TXUSRCLK + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 4.000ns (period - min period limit) + Period: 8.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[0].GTX/TXUSRCLK2 + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[0].GTX/TXUSRCLK2 + Location pin: GTXE1_X0Y15.TXUSRCLK2 + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 4.000ns (period - min period limit) + Period: 8.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[1].GTX/RXUSRCLK + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[1].GTX/RXUSRCLK + Location pin: GTXE1_X0Y14.RXUSRCLK + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 4.000ns (period - min period limit) + Period: 8.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[1].GTX/RXUSRCLK2 + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[1].GTX/RXUSRCLK2 + Location pin: GTXE1_X0Y14.RXUSRCLK2 + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 4.000ns (period - min period limit) + Period: 8.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[1].GTX/TXUSRCLK + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[1].GTX/TXUSRCLK + Location pin: GTXE1_X0Y14.TXUSRCLK + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 4.000ns (period - min period limit) + Period: 8.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[1].GTX/TXUSRCLK2 + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[1].GTX/TXUSRCLK2 + Location pin: GTXE1_X0Y14.TXUSRCLK2 + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 4.000ns (period - min period limit) + Period: 8.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX/RXUSRCLK + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX/RXUSRCLK + Location pin: GTXE1_X0Y13.RXUSRCLK + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 4.000ns (period - min period limit) + Period: 8.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX/RXUSRCLK2 + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX/RXUSRCLK2 + Location pin: GTXE1_X0Y13.RXUSRCLK2 + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 4.000ns (period - min period limit) + Period: 8.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX/TXUSRCLK + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX/TXUSRCLK + Location pin: GTXE1_X0Y13.TXUSRCLK + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 4.000ns (period - min period limit) + Period: 8.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX/TXUSRCLK2 + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX/TXUSRCLK2 + Location pin: GTXE1_X0Y13.TXUSRCLK2 + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 4.000ns (period - min period limit) + Period: 8.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX/RXUSRCLK + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX/RXUSRCLK + Location pin: GTXE1_X0Y12.RXUSRCLK + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 4.000ns (period - min period limit) + Period: 8.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX/RXUSRCLK2 + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX/RXUSRCLK2 + Location pin: GTXE1_X0Y12.RXUSRCLK2 + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 4.000ns (period - min period limit) + Period: 8.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX/TXUSRCLK + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX/TXUSRCLK + Location pin: GTXE1_X0Y12.TXUSRCLK + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 4.000ns (period - min period limit) + Period: 8.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX/TXUSRCLK2 + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX/TXUSRCLK2 + Location pin: GTXE1_X0Y12.TXUSRCLK2 + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: TS_CLK_250 = PERIOD TIMEGRP "CLK_250" TS_PCICLK HIGH 50% +PRIORITY 1; +For more information, see Period Analysis in the Timing Closure User Guide (UG612). + + 19297 paths analyzed, 6214 endpoints analyzed, 8 failing endpoints + 8 timing errors detected. (8 setup errors, 0 hold errors, 0 component switching limit errors) + Minimum period is 4.033ns. +-------------------------------------------------------------------------------- +Slack (setup path): -0.033ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/pciw_p2iAF_sInReset_isInReset (FF) + Destination: ftop/pciw_fP2I/Mram_arr10_RAMA (RAM) + Requirement: 4.000ns + Data Path Delay: 3.908ns (Levels of Logic = 3) + Clock Path Skew: -0.062ns (0.985 - 1.047) + Source Clock: ftop/pciw_pci0_pcie_ep$trn_clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep$trn_clk rising at 4.000ns + Clock Uncertainty: 0.063ns + + Clock Uncertainty: 0.063ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.103ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/pciw_p2iAF_sInReset_isInReset to ftop/pciw_fP2I/Mram_arr10_RAMA + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X150Y125.AQ Tcko 0.337 ftop/pciw_p2iAF_sInReset_isInReset + ftop/pciw_p2iAF_sInReset_isInReset + SLICE_X150Y158.D6 net (fanout=10) 1.497 ftop/pciw_p2iAF_sInReset_isInReset + SLICE_X150Y158.D Tilo 0.068 ftop/MUX_pciw_p2iS$write_1__SEL_11 + ftop/MUX_pciw_p2iS$write_1__SEL_111 + SLICE_X150Y158.C6 net (fanout=150) 0.132 ftop/MUX_pciw_p2iS$write_1__SEL_11 + SLICE_X150Y158.C Tilo 0.068 ftop/MUX_pciw_p2iS$write_1__SEL_11 + ftop/pciw_fP2I$DEQ1 + SLICE_X151Y153.A6 net (fanout=89) 0.672 ftop/pciw_fP2I$DEQ + SLICE_X151Y153.A Tilo 0.068 ftop/pciw_fP2I/_n0153_inv_REPLICA_387 + ftop/pciw_fP2I/Mmux_BUS_000311 + SLICE_X158Y153.CE net (fanout=13) 0.658 ftop/pciw_fP2I/BUS_0003 + SLICE_X158Y153.CLK Tceck 0.408 ftop/pciw_fP2I/_n0117<59> + ftop/pciw_fP2I/Mram_arr10_RAMA + ------------------------------------------------- --------------------------- + Total 3.908ns (0.949ns logic, 2.959ns route) + (24.3% logic, 75.7% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -0.033ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/pciw_p2iAF_sInReset_isInReset (FF) + Destination: ftop/pciw_fP2I/Mram_arr10_RAMD (RAM) + Requirement: 4.000ns + Data Path Delay: 3.908ns (Levels of Logic = 3) + Clock Path Skew: -0.062ns (0.985 - 1.047) + Source Clock: ftop/pciw_pci0_pcie_ep$trn_clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep$trn_clk rising at 4.000ns + Clock Uncertainty: 0.063ns + + Clock Uncertainty: 0.063ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.103ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/pciw_p2iAF_sInReset_isInReset to ftop/pciw_fP2I/Mram_arr10_RAMD + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X150Y125.AQ Tcko 0.337 ftop/pciw_p2iAF_sInReset_isInReset + ftop/pciw_p2iAF_sInReset_isInReset + SLICE_X150Y158.D6 net (fanout=10) 1.497 ftop/pciw_p2iAF_sInReset_isInReset + SLICE_X150Y158.D Tilo 0.068 ftop/MUX_pciw_p2iS$write_1__SEL_11 + ftop/MUX_pciw_p2iS$write_1__SEL_111 + SLICE_X150Y158.C6 net (fanout=150) 0.132 ftop/MUX_pciw_p2iS$write_1__SEL_11 + SLICE_X150Y158.C Tilo 0.068 ftop/MUX_pciw_p2iS$write_1__SEL_11 + ftop/pciw_fP2I$DEQ1 + SLICE_X151Y153.A6 net (fanout=89) 0.672 ftop/pciw_fP2I$DEQ + SLICE_X151Y153.A Tilo 0.068 ftop/pciw_fP2I/_n0153_inv_REPLICA_387 + ftop/pciw_fP2I/Mmux_BUS_000311 + SLICE_X158Y153.CE net (fanout=13) 0.658 ftop/pciw_fP2I/BUS_0003 + SLICE_X158Y153.CLK Tceck 0.408 ftop/pciw_fP2I/_n0117<59> + ftop/pciw_fP2I/Mram_arr10_RAMD + ------------------------------------------------- --------------------------- + Total 3.908ns (0.949ns logic, 2.959ns route) + (24.3% logic, 75.7% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -0.033ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/pciw_p2iAF_sInReset_isInReset (FF) + Destination: ftop/pciw_fP2I/Mram_arr10_RAMC_D1 (RAM) + Requirement: 4.000ns + Data Path Delay: 3.908ns (Levels of Logic = 3) + Clock Path Skew: -0.062ns (0.985 - 1.047) + Source Clock: ftop/pciw_pci0_pcie_ep$trn_clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep$trn_clk rising at 4.000ns + Clock Uncertainty: 0.063ns + + Clock Uncertainty: 0.063ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.103ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/pciw_p2iAF_sInReset_isInReset to ftop/pciw_fP2I/Mram_arr10_RAMC_D1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X150Y125.AQ Tcko 0.337 ftop/pciw_p2iAF_sInReset_isInReset + ftop/pciw_p2iAF_sInReset_isInReset + SLICE_X150Y158.D6 net (fanout=10) 1.497 ftop/pciw_p2iAF_sInReset_isInReset + SLICE_X150Y158.D Tilo 0.068 ftop/MUX_pciw_p2iS$write_1__SEL_11 + ftop/MUX_pciw_p2iS$write_1__SEL_111 + SLICE_X150Y158.C6 net (fanout=150) 0.132 ftop/MUX_pciw_p2iS$write_1__SEL_11 + SLICE_X150Y158.C Tilo 0.068 ftop/MUX_pciw_p2iS$write_1__SEL_11 + ftop/pciw_fP2I$DEQ1 + SLICE_X151Y153.A6 net (fanout=89) 0.672 ftop/pciw_fP2I$DEQ + SLICE_X151Y153.A Tilo 0.068 ftop/pciw_fP2I/_n0153_inv_REPLICA_387 + ftop/pciw_fP2I/Mmux_BUS_000311 + SLICE_X158Y153.CE net (fanout=13) 0.658 ftop/pciw_fP2I/BUS_0003 + SLICE_X158Y153.CLK Tceck 0.408 ftop/pciw_fP2I/_n0117<59> + ftop/pciw_fP2I/Mram_arr10_RAMC_D1 + ------------------------------------------------- --------------------------- + Total 3.908ns (0.949ns logic, 2.959ns route) + (24.3% logic, 75.7% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -0.033ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/pciw_p2iAF_sInReset_isInReset (FF) + Destination: ftop/pciw_fP2I/Mram_arr10_RAMC (RAM) + Requirement: 4.000ns + Data Path Delay: 3.908ns (Levels of Logic = 3) + Clock Path Skew: -0.062ns (0.985 - 1.047) + Source Clock: ftop/pciw_pci0_pcie_ep$trn_clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep$trn_clk rising at 4.000ns + Clock Uncertainty: 0.063ns + + Clock Uncertainty: 0.063ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.103ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/pciw_p2iAF_sInReset_isInReset to ftop/pciw_fP2I/Mram_arr10_RAMC + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X150Y125.AQ Tcko 0.337 ftop/pciw_p2iAF_sInReset_isInReset + ftop/pciw_p2iAF_sInReset_isInReset + SLICE_X150Y158.D6 net (fanout=10) 1.497 ftop/pciw_p2iAF_sInReset_isInReset + SLICE_X150Y158.D Tilo 0.068 ftop/MUX_pciw_p2iS$write_1__SEL_11 + ftop/MUX_pciw_p2iS$write_1__SEL_111 + SLICE_X150Y158.C6 net (fanout=150) 0.132 ftop/MUX_pciw_p2iS$write_1__SEL_11 + SLICE_X150Y158.C Tilo 0.068 ftop/MUX_pciw_p2iS$write_1__SEL_11 + ftop/pciw_fP2I$DEQ1 + SLICE_X151Y153.A6 net (fanout=89) 0.672 ftop/pciw_fP2I$DEQ + SLICE_X151Y153.A Tilo 0.068 ftop/pciw_fP2I/_n0153_inv_REPLICA_387 + ftop/pciw_fP2I/Mmux_BUS_000311 + SLICE_X158Y153.CE net (fanout=13) 0.658 ftop/pciw_fP2I/BUS_0003 + SLICE_X158Y153.CLK Tceck 0.408 ftop/pciw_fP2I/_n0117<59> + ftop/pciw_fP2I/Mram_arr10_RAMC + ------------------------------------------------- --------------------------- + Total 3.908ns (0.949ns logic, 2.959ns route) + (24.3% logic, 75.7% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -0.033ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/pciw_p2iAF_sInReset_isInReset (FF) + Destination: ftop/pciw_fP2I/Mram_arr10_RAMD_D1 (RAM) + Requirement: 4.000ns + Data Path Delay: 3.908ns (Levels of Logic = 3) + Clock Path Skew: -0.062ns (0.985 - 1.047) + Source Clock: ftop/pciw_pci0_pcie_ep$trn_clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep$trn_clk rising at 4.000ns + Clock Uncertainty: 0.063ns + + Clock Uncertainty: 0.063ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.103ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/pciw_p2iAF_sInReset_isInReset to ftop/pciw_fP2I/Mram_arr10_RAMD_D1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X150Y125.AQ Tcko 0.337 ftop/pciw_p2iAF_sInReset_isInReset + ftop/pciw_p2iAF_sInReset_isInReset + SLICE_X150Y158.D6 net (fanout=10) 1.497 ftop/pciw_p2iAF_sInReset_isInReset + SLICE_X150Y158.D Tilo 0.068 ftop/MUX_pciw_p2iS$write_1__SEL_11 + ftop/MUX_pciw_p2iS$write_1__SEL_111 + SLICE_X150Y158.C6 net (fanout=150) 0.132 ftop/MUX_pciw_p2iS$write_1__SEL_11 + SLICE_X150Y158.C Tilo 0.068 ftop/MUX_pciw_p2iS$write_1__SEL_11 + ftop/pciw_fP2I$DEQ1 + SLICE_X151Y153.A6 net (fanout=89) 0.672 ftop/pciw_fP2I$DEQ + SLICE_X151Y153.A Tilo 0.068 ftop/pciw_fP2I/_n0153_inv_REPLICA_387 + ftop/pciw_fP2I/Mmux_BUS_000311 + SLICE_X158Y153.CE net (fanout=13) 0.658 ftop/pciw_fP2I/BUS_0003 + SLICE_X158Y153.CLK Tceck 0.408 ftop/pciw_fP2I/_n0117<59> + ftop/pciw_fP2I/Mram_arr10_RAMD_D1 + ------------------------------------------------- --------------------------- + Total 3.908ns (0.949ns logic, 2.959ns route) + (24.3% logic, 75.7% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -0.033ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/pciw_p2iAF_sInReset_isInReset (FF) + Destination: ftop/pciw_fP2I/Mram_arr10_RAMB (RAM) + Requirement: 4.000ns + Data Path Delay: 3.908ns (Levels of Logic = 3) + Clock Path Skew: -0.062ns (0.985 - 1.047) + Source Clock: ftop/pciw_pci0_pcie_ep$trn_clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep$trn_clk rising at 4.000ns + Clock Uncertainty: 0.063ns + + Clock Uncertainty: 0.063ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.103ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/pciw_p2iAF_sInReset_isInReset to ftop/pciw_fP2I/Mram_arr10_RAMB + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X150Y125.AQ Tcko 0.337 ftop/pciw_p2iAF_sInReset_isInReset + ftop/pciw_p2iAF_sInReset_isInReset + SLICE_X150Y158.D6 net (fanout=10) 1.497 ftop/pciw_p2iAF_sInReset_isInReset + SLICE_X150Y158.D Tilo 0.068 ftop/MUX_pciw_p2iS$write_1__SEL_11 + ftop/MUX_pciw_p2iS$write_1__SEL_111 + SLICE_X150Y158.C6 net (fanout=150) 0.132 ftop/MUX_pciw_p2iS$write_1__SEL_11 + SLICE_X150Y158.C Tilo 0.068 ftop/MUX_pciw_p2iS$write_1__SEL_11 + ftop/pciw_fP2I$DEQ1 + SLICE_X151Y153.A6 net (fanout=89) 0.672 ftop/pciw_fP2I$DEQ + SLICE_X151Y153.A Tilo 0.068 ftop/pciw_fP2I/_n0153_inv_REPLICA_387 + ftop/pciw_fP2I/Mmux_BUS_000311 + SLICE_X158Y153.CE net (fanout=13) 0.658 ftop/pciw_fP2I/BUS_0003 + SLICE_X158Y153.CLK Tceck 0.408 ftop/pciw_fP2I/_n0117<59> + ftop/pciw_fP2I/Mram_arr10_RAMB + ------------------------------------------------- --------------------------- + Total 3.908ns (0.949ns logic, 2.959ns route) + (24.3% logic, 75.7% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -0.033ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/pciw_p2iAF_sInReset_isInReset (FF) + Destination: ftop/pciw_fP2I/Mram_arr10_RAMA_D1 (RAM) + Requirement: 4.000ns + Data Path Delay: 3.908ns (Levels of Logic = 3) + Clock Path Skew: -0.062ns (0.985 - 1.047) + Source Clock: ftop/pciw_pci0_pcie_ep$trn_clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep$trn_clk rising at 4.000ns + Clock Uncertainty: 0.063ns + + Clock Uncertainty: 0.063ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.103ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/pciw_p2iAF_sInReset_isInReset to ftop/pciw_fP2I/Mram_arr10_RAMA_D1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X150Y125.AQ Tcko 0.337 ftop/pciw_p2iAF_sInReset_isInReset + ftop/pciw_p2iAF_sInReset_isInReset + SLICE_X150Y158.D6 net (fanout=10) 1.497 ftop/pciw_p2iAF_sInReset_isInReset + SLICE_X150Y158.D Tilo 0.068 ftop/MUX_pciw_p2iS$write_1__SEL_11 + ftop/MUX_pciw_p2iS$write_1__SEL_111 + SLICE_X150Y158.C6 net (fanout=150) 0.132 ftop/MUX_pciw_p2iS$write_1__SEL_11 + SLICE_X150Y158.C Tilo 0.068 ftop/MUX_pciw_p2iS$write_1__SEL_11 + ftop/pciw_fP2I$DEQ1 + SLICE_X151Y153.A6 net (fanout=89) 0.672 ftop/pciw_fP2I$DEQ + SLICE_X151Y153.A Tilo 0.068 ftop/pciw_fP2I/_n0153_inv_REPLICA_387 + ftop/pciw_fP2I/Mmux_BUS_000311 + SLICE_X158Y153.CE net (fanout=13) 0.658 ftop/pciw_fP2I/BUS_0003 + SLICE_X158Y153.CLK Tceck 0.408 ftop/pciw_fP2I/_n0117<59> + ftop/pciw_fP2I/Mram_arr10_RAMA_D1 + ------------------------------------------------- --------------------------- + Total 3.908ns (0.949ns logic, 2.959ns route) + (24.3% logic, 75.7% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -0.033ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/pciw_p2iAF_sInReset_isInReset (FF) + Destination: ftop/pciw_fP2I/Mram_arr10_RAMB_D1 (RAM) + Requirement: 4.000ns + Data Path Delay: 3.908ns (Levels of Logic = 3) + Clock Path Skew: -0.062ns (0.985 - 1.047) + Source Clock: ftop/pciw_pci0_pcie_ep$trn_clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep$trn_clk rising at 4.000ns + Clock Uncertainty: 0.063ns + + Clock Uncertainty: 0.063ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.103ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/pciw_p2iAF_sInReset_isInReset to ftop/pciw_fP2I/Mram_arr10_RAMB_D1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X150Y125.AQ Tcko 0.337 ftop/pciw_p2iAF_sInReset_isInReset + ftop/pciw_p2iAF_sInReset_isInReset + SLICE_X150Y158.D6 net (fanout=10) 1.497 ftop/pciw_p2iAF_sInReset_isInReset + SLICE_X150Y158.D Tilo 0.068 ftop/MUX_pciw_p2iS$write_1__SEL_11 + ftop/MUX_pciw_p2iS$write_1__SEL_111 + SLICE_X150Y158.C6 net (fanout=150) 0.132 ftop/MUX_pciw_p2iS$write_1__SEL_11 + SLICE_X150Y158.C Tilo 0.068 ftop/MUX_pciw_p2iS$write_1__SEL_11 + ftop/pciw_fP2I$DEQ1 + SLICE_X151Y153.A6 net (fanout=89) 0.672 ftop/pciw_fP2I$DEQ + SLICE_X151Y153.A Tilo 0.068 ftop/pciw_fP2I/_n0153_inv_REPLICA_387 + ftop/pciw_fP2I/Mmux_BUS_000311 + SLICE_X158Y153.CE net (fanout=13) 0.658 ftop/pciw_fP2I/BUS_0003 + SLICE_X158Y153.CLK Tceck 0.408 ftop/pciw_fP2I/_n0117<59> + ftop/pciw_fP2I/Mram_arr10_RAMB_D1 + ------------------------------------------------- --------------------------- + Total 3.908ns (0.949ns logic, 2.959ns route) + (24.3% logic, 75.7% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.019ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/pciw_preEdge/FRDSE_inst (FF) + Destination: ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_81 (FF) + Requirement: 4.000ns + Data Path Delay: 3.829ns (Levels of Logic = 2) + Clock Path Skew: -0.089ns (1.494 - 1.583) + Source Clock: ftop/pciw_pci0_pcie_ep$trn_clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep$trn_clk rising at 4.000ns + Clock Uncertainty: 0.063ns + + Clock Uncertainty: 0.063ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.103ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/pciw_preEdge/FRDSE_inst to ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_81 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X150Y133.DQ Tcko 0.337 ftop/pciw_preEdge$CLK_VAL + ftop/pciw_preEdge/FRDSE_inst + SLICE_X149Y120.C1 net (fanout=7) 1.174 ftop/pciw_preEdge$CLK_VAL + SLICE_X149Y120.C Tilo 0.068 ftop/pciw_i2pAF_head_wrapped + ftop/WILL_FIRE_RL_pciw_i2pAF_deq_update_head1 + SLICE_X149Y107.A4 net (fanout=75) 1.091 ftop/MUX_pciw_Prelude_inst_changeSpecialWires_2_rg$write_1__SEL_11 + SLICE_X149Y107.A Tilo 0.068 ftop/pciw_i2pS<83> + ftop/pciw_Prelude_inst_changeSpecialWires_2_rg$EN1 + SLICE_X149Y112.CE net (fanout=19) 0.773 ftop/pciw_Prelude_inst_changeSpecialWires_2_rg$EN + SLICE_X149Y112.CLK Tceck 0.318 ftop/pciw_Prelude_inst_changeSpecialWires_2_rg<81> + ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_81 + ------------------------------------------------- --------------------------- + Total 3.829ns (0.791ns logic, 3.038ns route) + (20.7% logic, 79.3% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.019ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/pciw_preEdge/FRDSE_inst (FF) + Destination: ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_79 (FF) + Requirement: 4.000ns + Data Path Delay: 3.829ns (Levels of Logic = 2) + Clock Path Skew: -0.089ns (1.494 - 1.583) + Source Clock: ftop/pciw_pci0_pcie_ep$trn_clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep$trn_clk rising at 4.000ns + Clock Uncertainty: 0.063ns + + Clock Uncertainty: 0.063ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.103ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/pciw_preEdge/FRDSE_inst to ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_79 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X150Y133.DQ Tcko 0.337 ftop/pciw_preEdge$CLK_VAL + ftop/pciw_preEdge/FRDSE_inst + SLICE_X149Y120.C1 net (fanout=7) 1.174 ftop/pciw_preEdge$CLK_VAL + SLICE_X149Y120.C Tilo 0.068 ftop/pciw_i2pAF_head_wrapped + ftop/WILL_FIRE_RL_pciw_i2pAF_deq_update_head1 + SLICE_X149Y107.A4 net (fanout=75) 1.091 ftop/MUX_pciw_Prelude_inst_changeSpecialWires_2_rg$write_1__SEL_11 + SLICE_X149Y107.A Tilo 0.068 ftop/pciw_i2pS<83> + ftop/pciw_Prelude_inst_changeSpecialWires_2_rg$EN1 + SLICE_X149Y112.CE net (fanout=19) 0.773 ftop/pciw_Prelude_inst_changeSpecialWires_2_rg$EN + SLICE_X149Y112.CLK Tceck 0.318 ftop/pciw_Prelude_inst_changeSpecialWires_2_rg<81> + ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_79 + ------------------------------------------------- --------------------------- + Total 3.829ns (0.791ns logic, 3.038ns route) + (20.7% logic, 79.3% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.049ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/pciw_p2iAF_sInReset_isInReset (FF) + Destination: ftop/pciw_fP2I/Mram_arr1_RAMA (RAM) + Requirement: 4.000ns + Data Path Delay: 3.819ns (Levels of Logic = 3) + Clock Path Skew: -0.069ns (0.978 - 1.047) + Source Clock: ftop/pciw_pci0_pcie_ep$trn_clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep$trn_clk rising at 4.000ns + Clock Uncertainty: 0.063ns + + Clock Uncertainty: 0.063ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.103ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/pciw_p2iAF_sInReset_isInReset to ftop/pciw_fP2I/Mram_arr1_RAMA + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X150Y125.AQ Tcko 0.337 ftop/pciw_p2iAF_sInReset_isInReset + ftop/pciw_p2iAF_sInReset_isInReset + SLICE_X150Y158.D6 net (fanout=10) 1.497 ftop/pciw_p2iAF_sInReset_isInReset + SLICE_X150Y158.D Tilo 0.068 ftop/MUX_pciw_p2iS$write_1__SEL_11 + ftop/MUX_pciw_p2iS$write_1__SEL_111 + SLICE_X150Y158.C6 net (fanout=150) 0.132 ftop/MUX_pciw_p2iS$write_1__SEL_11 + SLICE_X150Y158.C Tilo 0.068 ftop/MUX_pciw_p2iS$write_1__SEL_11 + ftop/pciw_fP2I$DEQ1 + SLICE_X151Y153.A6 net (fanout=89) 0.672 ftop/pciw_fP2I$DEQ + SLICE_X151Y153.A Tilo 0.068 ftop/pciw_fP2I/_n0153_inv_REPLICA_387 + ftop/pciw_fP2I/Mmux_BUS_000311 + SLICE_X152Y147.CE net (fanout=13) 0.569 ftop/pciw_fP2I/BUS_0003 + SLICE_X152Y147.CLK Tceck 0.408 ftop/pciw_fP2I/_n0117<5> + ftop/pciw_fP2I/Mram_arr1_RAMA + ------------------------------------------------- --------------------------- + Total 3.819ns (0.949ns logic, 2.870ns route) + (24.8% logic, 75.2% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.049ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/pciw_p2iAF_sInReset_isInReset (FF) + Destination: ftop/pciw_fP2I/Mram_arr1_RAMD (RAM) + Requirement: 4.000ns + Data Path Delay: 3.819ns (Levels of Logic = 3) + Clock Path Skew: -0.069ns (0.978 - 1.047) + Source Clock: ftop/pciw_pci0_pcie_ep$trn_clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep$trn_clk rising at 4.000ns + Clock Uncertainty: 0.063ns + + Clock Uncertainty: 0.063ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.103ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/pciw_p2iAF_sInReset_isInReset to ftop/pciw_fP2I/Mram_arr1_RAMD + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X150Y125.AQ Tcko 0.337 ftop/pciw_p2iAF_sInReset_isInReset + ftop/pciw_p2iAF_sInReset_isInReset + SLICE_X150Y158.D6 net (fanout=10) 1.497 ftop/pciw_p2iAF_sInReset_isInReset + SLICE_X150Y158.D Tilo 0.068 ftop/MUX_pciw_p2iS$write_1__SEL_11 + ftop/MUX_pciw_p2iS$write_1__SEL_111 + SLICE_X150Y158.C6 net (fanout=150) 0.132 ftop/MUX_pciw_p2iS$write_1__SEL_11 + SLICE_X150Y158.C Tilo 0.068 ftop/MUX_pciw_p2iS$write_1__SEL_11 + ftop/pciw_fP2I$DEQ1 + SLICE_X151Y153.A6 net (fanout=89) 0.672 ftop/pciw_fP2I$DEQ + SLICE_X151Y153.A Tilo 0.068 ftop/pciw_fP2I/_n0153_inv_REPLICA_387 + ftop/pciw_fP2I/Mmux_BUS_000311 + SLICE_X152Y147.CE net (fanout=13) 0.569 ftop/pciw_fP2I/BUS_0003 + SLICE_X152Y147.CLK Tceck 0.408 ftop/pciw_fP2I/_n0117<5> + ftop/pciw_fP2I/Mram_arr1_RAMD + ------------------------------------------------- --------------------------- + Total 3.819ns (0.949ns logic, 2.870ns route) + (24.8% logic, 75.2% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.049ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/pciw_p2iAF_sInReset_isInReset (FF) + Destination: ftop/pciw_fP2I/Mram_arr1_RAMC_D1 (RAM) + Requirement: 4.000ns + Data Path Delay: 3.819ns (Levels of Logic = 3) + Clock Path Skew: -0.069ns (0.978 - 1.047) + Source Clock: ftop/pciw_pci0_pcie_ep$trn_clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep$trn_clk rising at 4.000ns + Clock Uncertainty: 0.063ns + + Clock Uncertainty: 0.063ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.103ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/pciw_p2iAF_sInReset_isInReset to ftop/pciw_fP2I/Mram_arr1_RAMC_D1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X150Y125.AQ Tcko 0.337 ftop/pciw_p2iAF_sInReset_isInReset + ftop/pciw_p2iAF_sInReset_isInReset + SLICE_X150Y158.D6 net (fanout=10) 1.497 ftop/pciw_p2iAF_sInReset_isInReset + SLICE_X150Y158.D Tilo 0.068 ftop/MUX_pciw_p2iS$write_1__SEL_11 + ftop/MUX_pciw_p2iS$write_1__SEL_111 + SLICE_X150Y158.C6 net (fanout=150) 0.132 ftop/MUX_pciw_p2iS$write_1__SEL_11 + SLICE_X150Y158.C Tilo 0.068 ftop/MUX_pciw_p2iS$write_1__SEL_11 + ftop/pciw_fP2I$DEQ1 + SLICE_X151Y153.A6 net (fanout=89) 0.672 ftop/pciw_fP2I$DEQ + SLICE_X151Y153.A Tilo 0.068 ftop/pciw_fP2I/_n0153_inv_REPLICA_387 + ftop/pciw_fP2I/Mmux_BUS_000311 + SLICE_X152Y147.CE net (fanout=13) 0.569 ftop/pciw_fP2I/BUS_0003 + SLICE_X152Y147.CLK Tceck 0.408 ftop/pciw_fP2I/_n0117<5> + ftop/pciw_fP2I/Mram_arr1_RAMC_D1 + ------------------------------------------------- --------------------------- + Total 3.819ns (0.949ns logic, 2.870ns route) + (24.8% logic, 75.2% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.049ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/pciw_p2iAF_sInReset_isInReset (FF) + Destination: ftop/pciw_fP2I/Mram_arr1_RAMC (RAM) + Requirement: 4.000ns + Data Path Delay: 3.819ns (Levels of Logic = 3) + Clock Path Skew: -0.069ns (0.978 - 1.047) + Source Clock: ftop/pciw_pci0_pcie_ep$trn_clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep$trn_clk rising at 4.000ns + Clock Uncertainty: 0.063ns + + Clock Uncertainty: 0.063ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.103ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/pciw_p2iAF_sInReset_isInReset to ftop/pciw_fP2I/Mram_arr1_RAMC + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X150Y125.AQ Tcko 0.337 ftop/pciw_p2iAF_sInReset_isInReset + ftop/pciw_p2iAF_sInReset_isInReset + SLICE_X150Y158.D6 net (fanout=10) 1.497 ftop/pciw_p2iAF_sInReset_isInReset + SLICE_X150Y158.D Tilo 0.068 ftop/MUX_pciw_p2iS$write_1__SEL_11 + ftop/MUX_pciw_p2iS$write_1__SEL_111 + SLICE_X150Y158.C6 net (fanout=150) 0.132 ftop/MUX_pciw_p2iS$write_1__SEL_11 + SLICE_X150Y158.C Tilo 0.068 ftop/MUX_pciw_p2iS$write_1__SEL_11 + ftop/pciw_fP2I$DEQ1 + SLICE_X151Y153.A6 net (fanout=89) 0.672 ftop/pciw_fP2I$DEQ + SLICE_X151Y153.A Tilo 0.068 ftop/pciw_fP2I/_n0153_inv_REPLICA_387 + ftop/pciw_fP2I/Mmux_BUS_000311 + SLICE_X152Y147.CE net (fanout=13) 0.569 ftop/pciw_fP2I/BUS_0003 + SLICE_X152Y147.CLK Tceck 0.408 ftop/pciw_fP2I/_n0117<5> + ftop/pciw_fP2I/Mram_arr1_RAMC + ------------------------------------------------- --------------------------- + Total 3.819ns (0.949ns logic, 2.870ns route) + (24.8% logic, 75.2% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.049ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/pciw_p2iAF_sInReset_isInReset (FF) + Destination: ftop/pciw_fP2I/Mram_arr1_RAMD_D1 (RAM) + Requirement: 4.000ns + Data Path Delay: 3.819ns (Levels of Logic = 3) + Clock Path Skew: -0.069ns (0.978 - 1.047) + Source Clock: ftop/pciw_pci0_pcie_ep$trn_clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep$trn_clk rising at 4.000ns + Clock Uncertainty: 0.063ns + + Clock Uncertainty: 0.063ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.103ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/pciw_p2iAF_sInReset_isInReset to ftop/pciw_fP2I/Mram_arr1_RAMD_D1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X150Y125.AQ Tcko 0.337 ftop/pciw_p2iAF_sInReset_isInReset + ftop/pciw_p2iAF_sInReset_isInReset + SLICE_X150Y158.D6 net (fanout=10) 1.497 ftop/pciw_p2iAF_sInReset_isInReset + SLICE_X150Y158.D Tilo 0.068 ftop/MUX_pciw_p2iS$write_1__SEL_11 + ftop/MUX_pciw_p2iS$write_1__SEL_111 + SLICE_X150Y158.C6 net (fanout=150) 0.132 ftop/MUX_pciw_p2iS$write_1__SEL_11 + SLICE_X150Y158.C Tilo 0.068 ftop/MUX_pciw_p2iS$write_1__SEL_11 + ftop/pciw_fP2I$DEQ1 + SLICE_X151Y153.A6 net (fanout=89) 0.672 ftop/pciw_fP2I$DEQ + SLICE_X151Y153.A Tilo 0.068 ftop/pciw_fP2I/_n0153_inv_REPLICA_387 + ftop/pciw_fP2I/Mmux_BUS_000311 + SLICE_X152Y147.CE net (fanout=13) 0.569 ftop/pciw_fP2I/BUS_0003 + SLICE_X152Y147.CLK Tceck 0.408 ftop/pciw_fP2I/_n0117<5> + ftop/pciw_fP2I/Mram_arr1_RAMD_D1 + ------------------------------------------------- --------------------------- + Total 3.819ns (0.949ns logic, 2.870ns route) + (24.8% logic, 75.2% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.049ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/pciw_p2iAF_sInReset_isInReset (FF) + Destination: ftop/pciw_fP2I/Mram_arr1_RAMB (RAM) + Requirement: 4.000ns + Data Path Delay: 3.819ns (Levels of Logic = 3) + Clock Path Skew: -0.069ns (0.978 - 1.047) + Source Clock: ftop/pciw_pci0_pcie_ep$trn_clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep$trn_clk rising at 4.000ns + Clock Uncertainty: 0.063ns + + Clock Uncertainty: 0.063ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.103ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/pciw_p2iAF_sInReset_isInReset to ftop/pciw_fP2I/Mram_arr1_RAMB + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X150Y125.AQ Tcko 0.337 ftop/pciw_p2iAF_sInReset_isInReset + ftop/pciw_p2iAF_sInReset_isInReset + SLICE_X150Y158.D6 net (fanout=10) 1.497 ftop/pciw_p2iAF_sInReset_isInReset + SLICE_X150Y158.D Tilo 0.068 ftop/MUX_pciw_p2iS$write_1__SEL_11 + ftop/MUX_pciw_p2iS$write_1__SEL_111 + SLICE_X150Y158.C6 net (fanout=150) 0.132 ftop/MUX_pciw_p2iS$write_1__SEL_11 + SLICE_X150Y158.C Tilo 0.068 ftop/MUX_pciw_p2iS$write_1__SEL_11 + ftop/pciw_fP2I$DEQ1 + SLICE_X151Y153.A6 net (fanout=89) 0.672 ftop/pciw_fP2I$DEQ + SLICE_X151Y153.A Tilo 0.068 ftop/pciw_fP2I/_n0153_inv_REPLICA_387 + ftop/pciw_fP2I/Mmux_BUS_000311 + SLICE_X152Y147.CE net (fanout=13) 0.569 ftop/pciw_fP2I/BUS_0003 + SLICE_X152Y147.CLK Tceck 0.408 ftop/pciw_fP2I/_n0117<5> + ftop/pciw_fP2I/Mram_arr1_RAMB + ------------------------------------------------- --------------------------- + Total 3.819ns (0.949ns logic, 2.870ns route) + (24.8% logic, 75.2% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.049ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/pciw_p2iAF_sInReset_isInReset (FF) + Destination: ftop/pciw_fP2I/Mram_arr1_RAMA_D1 (RAM) + Requirement: 4.000ns + Data Path Delay: 3.819ns (Levels of Logic = 3) + Clock Path Skew: -0.069ns (0.978 - 1.047) + Source Clock: ftop/pciw_pci0_pcie_ep$trn_clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep$trn_clk rising at 4.000ns + Clock Uncertainty: 0.063ns + + Clock Uncertainty: 0.063ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.103ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/pciw_p2iAF_sInReset_isInReset to ftop/pciw_fP2I/Mram_arr1_RAMA_D1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X150Y125.AQ Tcko 0.337 ftop/pciw_p2iAF_sInReset_isInReset + ftop/pciw_p2iAF_sInReset_isInReset + SLICE_X150Y158.D6 net (fanout=10) 1.497 ftop/pciw_p2iAF_sInReset_isInReset + SLICE_X150Y158.D Tilo 0.068 ftop/MUX_pciw_p2iS$write_1__SEL_11 + ftop/MUX_pciw_p2iS$write_1__SEL_111 + SLICE_X150Y158.C6 net (fanout=150) 0.132 ftop/MUX_pciw_p2iS$write_1__SEL_11 + SLICE_X150Y158.C Tilo 0.068 ftop/MUX_pciw_p2iS$write_1__SEL_11 + ftop/pciw_fP2I$DEQ1 + SLICE_X151Y153.A6 net (fanout=89) 0.672 ftop/pciw_fP2I$DEQ + SLICE_X151Y153.A Tilo 0.068 ftop/pciw_fP2I/_n0153_inv_REPLICA_387 + ftop/pciw_fP2I/Mmux_BUS_000311 + SLICE_X152Y147.CE net (fanout=13) 0.569 ftop/pciw_fP2I/BUS_0003 + SLICE_X152Y147.CLK Tceck 0.408 ftop/pciw_fP2I/_n0117<5> + ftop/pciw_fP2I/Mram_arr1_RAMA_D1 + ------------------------------------------------- --------------------------- + Total 3.819ns (0.949ns logic, 2.870ns route) + (24.8% logic, 75.2% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.049ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/pciw_p2iAF_sInReset_isInReset (FF) + Destination: ftop/pciw_fP2I/Mram_arr1_RAMB_D1 (RAM) + Requirement: 4.000ns + Data Path Delay: 3.819ns (Levels of Logic = 3) + Clock Path Skew: -0.069ns (0.978 - 1.047) + Source Clock: ftop/pciw_pci0_pcie_ep$trn_clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep$trn_clk rising at 4.000ns + Clock Uncertainty: 0.063ns + + Clock Uncertainty: 0.063ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.103ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/pciw_p2iAF_sInReset_isInReset to ftop/pciw_fP2I/Mram_arr1_RAMB_D1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X150Y125.AQ Tcko 0.337 ftop/pciw_p2iAF_sInReset_isInReset + ftop/pciw_p2iAF_sInReset_isInReset + SLICE_X150Y158.D6 net (fanout=10) 1.497 ftop/pciw_p2iAF_sInReset_isInReset + SLICE_X150Y158.D Tilo 0.068 ftop/MUX_pciw_p2iS$write_1__SEL_11 + ftop/MUX_pciw_p2iS$write_1__SEL_111 + SLICE_X150Y158.C6 net (fanout=150) 0.132 ftop/MUX_pciw_p2iS$write_1__SEL_11 + SLICE_X150Y158.C Tilo 0.068 ftop/MUX_pciw_p2iS$write_1__SEL_11 + ftop/pciw_fP2I$DEQ1 + SLICE_X151Y153.A6 net (fanout=89) 0.672 ftop/pciw_fP2I$DEQ + SLICE_X151Y153.A Tilo 0.068 ftop/pciw_fP2I/_n0153_inv_REPLICA_387 + ftop/pciw_fP2I/Mmux_BUS_000311 + SLICE_X152Y147.CE net (fanout=13) 0.569 ftop/pciw_fP2I/BUS_0003 + SLICE_X152Y147.CLK Tceck 0.408 ftop/pciw_fP2I/_n0117<5> + ftop/pciw_fP2I/Mram_arr1_RAMB_D1 + ------------------------------------------------- --------------------------- + Total 3.819ns (0.949ns logic, 2.870ns route) + (24.8% logic, 75.2% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.052ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i (CPU) + Destination: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX (HSIO) + Requirement: 4.000ns + Data Path Delay: 4.020ns (Levels of Logic = 0) + Clock Path Skew: 0.261ns (1.351 - 1.090) + Source Clock: ftop/pciw_pci0_pcie_ep/ep/pipe_clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep/ep/pipe_clk rising at 4.000ns + Clock Uncertainty: 0.189ns + + Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.120ns + + Maximum Data Path at Slow Process Corner: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i to ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + --------------------------------------------------- ------------------- + PCIE_X0Y1.PIPETX2DATA0 Tpcicko_MGT2 0.557 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + GTXE1_X0Y13.TXDATA0 net (fanout=1) 3.139 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX2DATA<0> + GTXE1_X0Y13.TXUSRCLK2 Tgtxcck_TXDATA 0.324 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX + --------------------------------------------------- --------------------------- + Total 4.020ns (0.881ns logic, 3.139ns route) + (21.9% logic, 78.1% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.059ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/pciw_p2iAF_sInReset_isInReset (FF) + Destination: ftop/pciw_fP2I/Mram_arr2_RAMA (RAM) + Requirement: 4.000ns + Data Path Delay: 3.810ns (Levels of Logic = 3) + Clock Path Skew: -0.068ns (0.979 - 1.047) + Source Clock: ftop/pciw_pci0_pcie_ep$trn_clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep$trn_clk rising at 4.000ns + Clock Uncertainty: 0.063ns + + Clock Uncertainty: 0.063ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.103ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/pciw_p2iAF_sInReset_isInReset to ftop/pciw_fP2I/Mram_arr2_RAMA + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X150Y125.AQ Tcko 0.337 ftop/pciw_p2iAF_sInReset_isInReset + ftop/pciw_p2iAF_sInReset_isInReset + SLICE_X150Y158.D6 net (fanout=10) 1.497 ftop/pciw_p2iAF_sInReset_isInReset + SLICE_X150Y158.D Tilo 0.068 ftop/MUX_pciw_p2iS$write_1__SEL_11 + ftop/MUX_pciw_p2iS$write_1__SEL_111 + SLICE_X150Y158.C6 net (fanout=150) 0.132 ftop/MUX_pciw_p2iS$write_1__SEL_11 + SLICE_X150Y158.C Tilo 0.068 ftop/MUX_pciw_p2iS$write_1__SEL_11 + ftop/pciw_fP2I$DEQ1 + SLICE_X151Y153.A6 net (fanout=89) 0.672 ftop/pciw_fP2I$DEQ + SLICE_X151Y153.A Tilo 0.068 ftop/pciw_fP2I/_n0153_inv_REPLICA_387 + ftop/pciw_fP2I/Mmux_BUS_000311 + SLICE_X152Y148.CE net (fanout=13) 0.560 ftop/pciw_fP2I/BUS_0003 + SLICE_X152Y148.CLK Tceck 0.408 ftop/pciw_fP2I/_n0117<11> + ftop/pciw_fP2I/Mram_arr2_RAMA + ------------------------------------------------- --------------------------- + Total 3.810ns (0.949ns logic, 2.861ns route) + (24.9% logic, 75.1% route) + +-------------------------------------------------------------------------------- + +Hold Paths: TS_CLK_250 = PERIOD TIMEGRP "CLK_250" TS_PCICLK HIGH 50% PRIORITY 1; +-------------------------------------------------------------------------------- +Slack (hold path): 0.002ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_i2pS_8 (FF) + Destination: ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_8 (FF) + Requirement: 0.000ns + Data Path Delay: 0.274ns (Levels of Logic = 1) + Clock Path Skew: 0.083ns (1.160 - 1.077) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep$trn_clk rising at 0.000ns + Clock Uncertainty: 0.189ns + + Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.120ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_i2pS_8 to ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_8 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X141Y103.AQ Tcko 0.098 ftop/pciw_i2pS<11> + ftop/pciw_i2pS_8 + SLICE_X149Y103.A5 net (fanout=1) 0.231 ftop/pciw_i2pS<8> + SLICE_X149Y103.CLK Tah (-Th) 0.055 ftop/pciw_Prelude_inst_changeSpecialWires_2_rg<11> + ftop/Mmux_pciw_Prelude_inst_changeSpecialWires_2_rg$D_IN801 + ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_8 + ------------------------------------------------- --------------------------- + Total 0.274ns (0.043ns logic, 0.231ns route) + (15.7% logic, 84.3% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.010ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_i2pS_40 (FF) + Destination: ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_40 (FF) + Requirement: 0.000ns + Data Path Delay: 0.268ns (Levels of Logic = 1) + Clock Path Skew: 0.069ns (1.164 - 1.095) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep$trn_clk rising at 0.000ns + Clock Uncertainty: 0.189ns + + Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.120ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_i2pS_40 to ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_40 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X153Y112.AQ Tcko 0.098 ftop/pciw_i2pS<43> + ftop/pciw_i2pS_40 + SLICE_X152Y106.A5 net (fanout=1) 0.246 ftop/pciw_i2pS<40> + SLICE_X152Y106.CLK Tah (-Th) 0.076 ftop/pciw_Prelude_inst_changeSpecialWires_2_rg<43> + ftop/Mmux_pciw_Prelude_inst_changeSpecialWires_2_rg$D_IN351 + ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_40 + ------------------------------------------------- --------------------------- + Total 0.268ns (0.022ns logic, 0.246ns route) + (8.2% logic, 91.8% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.021ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX_RX_VALID_FILTER/gt_rxdata_q_2 (FF) + Destination: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i (CPU) + Requirement: 0.000ns + Data Path Delay: 0.101ns (Levels of Logic = 1) + Clock Path Skew: 0.080ns (0.533 - 0.453) + Source Clock: ftop/pciw_pci0_pcie_ep/ep/pipe_clk rising at 4.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep/ep/pipe_clk rising at 4.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX_RX_VALID_FILTER/gt_rxdata_q_2 to ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + --------------------------------------------------- ------------------- + SLICE_X151Y122.CQ Tcko 0.098 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX_RX_VALID_FILTER/gt_rxdata_q<3> + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX_RX_VALID_FILTER/gt_rxdata_q_2 + SLICE_X151Y120.A3 net (fanout=2) 0.170 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX_RX_VALID_FILTER/gt_rxdata_q<2> + SLICE_X151Y120.A Tilo 0.034 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX3DATA<1> + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX_RX_VALID_FILTER/Mmux_USER_RXDATA<7:0>31 + PCIE_X0Y1.PIPERX3DATA2 net (fanout=1) 0.230 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX3DATA<2> + PCIE_X0Y1.PIPECLK Tpcickc_MGT3(-Th) 0.431 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + --------------------------------------------------- --------------------------- + Total 0.101ns (-0.299ns logic, 0.400ns route) + (-296.0% logic, 396.0% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.022ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_i2pS_38 (FF) + Destination: ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_38 (FF) + Requirement: 0.000ns + Data Path Delay: 0.283ns (Levels of Logic = 1) + Clock Path Skew: 0.072ns (1.155 - 1.083) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep$trn_clk rising at 0.000ns + Clock Uncertainty: 0.189ns + + Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.120ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_i2pS_38 to ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_38 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X153Y100.CQ Tcko 0.098 ftop/pciw_i2pS<39> + ftop/pciw_i2pS_38 + SLICE_X148Y100.C2 net (fanout=1) 0.261 ftop/pciw_i2pS<38> + SLICE_X148Y100.CLK Tah (-Th) 0.076 ftop/pciw_Prelude_inst_changeSpecialWires_2_rg<39> + ftop/Mmux_pciw_Prelude_inst_changeSpecialWires_2_rg$D_IN321 + ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_38 + ------------------------------------------------- --------------------------- + Total 0.283ns (0.022ns logic, 0.261ns route) + (7.8% logic, 92.2% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.025ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX_RX_VALID_FILTER/gt_rx_is_skp0_q (FF) + Destination: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i (CPU) + Requirement: 0.000ns + Data Path Delay: 0.106ns (Levels of Logic = 1) + Clock Path Skew: 0.081ns (0.533 - 0.452) + Source Clock: ftop/pciw_pci0_pcie_ep/ep/pipe_clk rising at 4.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep/ep/pipe_clk rising at 4.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX_RX_VALID_FILTER/gt_rx_is_skp0_q to ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + --------------------------------------------------- ------------------- + SLICE_X153Y129.AQ Tcko 0.098 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX_RX_VALID_FILTER/gt_rx_is_skp0_q + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX_RX_VALID_FILTER/gt_rx_is_skp0_q + SLICE_X151Y128.B1 net (fanout=8) 0.225 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX_RX_VALID_FILTER/gt_rx_is_skp0_q + SLICE_X151Y128.B Tilo 0.034 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX2DATA<0> + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX_RX_VALID_FILTER/Mmux_USER_RXDATA<7:0>51 + PCIE_X0Y1.PIPERX2DATA4 net (fanout=1) 0.232 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX2DATA<4> + PCIE_X0Y1.PIPECLK Tpcickc_MGT2(-Th) 0.483 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + --------------------------------------------------- --------------------------- + Total 0.106ns (-0.351ns logic, 0.457ns route) + (-331.1% logic, 431.1% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.028ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_i2pS_9 (FF) + Destination: ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_9 (FF) + Requirement: 0.000ns + Data Path Delay: 0.300ns (Levels of Logic = 1) + Clock Path Skew: 0.083ns (1.160 - 1.077) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep$trn_clk rising at 0.000ns + Clock Uncertainty: 0.189ns + + Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.120ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_i2pS_9 to ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_9 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X141Y103.BQ Tcko 0.098 ftop/pciw_i2pS<11> + ftop/pciw_i2pS_9 + SLICE_X149Y103.B6 net (fanout=1) 0.259 ftop/pciw_i2pS<9> + SLICE_X149Y103.CLK Tah (-Th) 0.057 ftop/pciw_Prelude_inst_changeSpecialWires_2_rg<11> + ftop/Mmux_pciw_Prelude_inst_changeSpecialWires_2_rg$D_IN811 + ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_9 + ------------------------------------------------- --------------------------- + Total 0.300ns (0.041ns logic, 0.259ns route) + (13.7% logic, 86.3% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.029ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX_RX_VALID_FILTER/gt_rx_is_skp1_q (FF) + Destination: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i (CPU) + Requirement: 0.000ns + Data Path Delay: 0.113ns (Levels of Logic = 1) + Clock Path Skew: 0.084ns (0.533 - 0.449) + Source Clock: ftop/pciw_pci0_pcie_ep/ep/pipe_clk rising at 4.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep/ep/pipe_clk rising at 4.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX_RX_VALID_FILTER/gt_rx_is_skp1_q to ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ---------------------------------------------------- ------------------- + SLICE_X150Y131.AQ Tcko 0.098 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX_RX_VALID_FILTER/gt_rx_is_skp1_q + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX_RX_VALID_FILTER/gt_rx_is_skp1_q + SLICE_X150Y131.D5 net (fanout=8) 0.091 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX_RX_VALID_FILTER/gt_rx_is_skp1_q + SLICE_X150Y131.D Tilo 0.034 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX_RX_VALID_FILTER/gt_rx_is_skp1_q + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX_RX_VALID_FILTER/Mmux_USER_RXDATA<15:8>21 + PCIE_X0Y1.PIPERX2DATA11 net (fanout=1) 0.383 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX2DATA<11> + PCIE_X0Y1.PIPECLK Tpcickc_MGT2(-Th) 0.493 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + ---------------------------------------------------- --------------------------- + Total 0.113ns (-0.361ns logic, 0.474ns route) + (-319.5% logic, 419.5% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.031ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX_RX_VALID_FILTER/gt_rxdata_q_4 (FF) + Destination: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i (CPU) + Requirement: 0.000ns + Data Path Delay: 0.111ns (Levels of Logic = 1) + Clock Path Skew: 0.080ns (0.533 - 0.453) + Source Clock: ftop/pciw_pci0_pcie_ep/ep/pipe_clk rising at 4.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep/ep/pipe_clk rising at 4.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX_RX_VALID_FILTER/gt_rxdata_q_4 to ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + --------------------------------------------------- ------------------- + SLICE_X152Y128.AQ Tcko 0.115 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX_RX_VALID_FILTER/gt_rxdata_q<7> + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX_RX_VALID_FILTER/gt_rxdata_q_4 + SLICE_X151Y128.B3 net (fanout=2) 0.213 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX_RX_VALID_FILTER/gt_rxdata_q<4> + SLICE_X151Y128.B Tilo 0.034 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX2DATA<0> + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX_RX_VALID_FILTER/Mmux_USER_RXDATA<7:0>51 + PCIE_X0Y1.PIPERX2DATA4 net (fanout=1) 0.232 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX2DATA<4> + PCIE_X0Y1.PIPECLK Tpcickc_MGT2(-Th) 0.483 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + --------------------------------------------------- --------------------------- + Total 0.111ns (-0.334ns logic, 0.445ns route) + (-300.9% logic, 400.9% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.031ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX_RX_VALID_FILTER/awake_in_progress_q (FF) + Destination: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i (CPU) + Requirement: 0.000ns + Data Path Delay: 0.116ns (Levels of Logic = 1) + Clock Path Skew: 0.085ns (0.533 - 0.448) + Source Clock: ftop/pciw_pci0_pcie_ep/ep/pipe_clk rising at 4.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep/ep/pipe_clk rising at 4.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX_RX_VALID_FILTER/awake_in_progress_q to ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + --------------------------------------------------- ------------------- + SLICE_X145Y123.CQ Tcko 0.098 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX_RX_VALID_FILTER/awake_in_progress_q + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX_RX_VALID_FILTER/awake_in_progress_q + SLICE_X146Y124.A6 net (fanout=5) 0.110 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX_RX_VALID_FILTER/awake_in_progress_q + SLICE_X146Y124.A Tilo 0.034 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX3VALID + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX_RX_VALID_FILTER/USER_RXVALID1 + PCIE_X0Y1.PIPERX3VALID net (fanout=1) 0.312 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX3VALID + PCIE_X0Y1.PIPECLK Tpcickc_MGT3(-Th) 0.438 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + --------------------------------------------------- --------------------------- + Total 0.116ns (-0.306ns logic, 0.422ns route) + (-263.8% logic, 363.8% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.032ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_i2pS_35 (FF) + Destination: ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_35 (FF) + Requirement: 0.000ns + Data Path Delay: 0.291ns (Levels of Logic = 1) + Clock Path Skew: 0.070ns (1.164 - 1.094) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep$trn_clk rising at 0.000ns + Clock Uncertainty: 0.189ns + + Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.120ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_i2pS_35 to ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_35 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X150Y111.DQ Tcko 0.098 ftop/pciw_i2pS<35> + ftop/pciw_i2pS_35 + SLICE_X153Y106.D6 net (fanout=1) 0.250 ftop/pciw_i2pS<35> + SLICE_X153Y106.CLK Tah (-Th) 0.057 ftop/pciw_Prelude_inst_changeSpecialWires_2_rg<35> + ftop/Mmux_pciw_Prelude_inst_changeSpecialWires_2_rg$D_IN291 + ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_35 + ------------------------------------------------- --------------------------- + Total 0.291ns (0.041ns logic, 0.250ns route) + (14.1% logic, 85.9% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.033ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_i2pS_39 (FF) + Destination: ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_39 (FF) + Requirement: 0.000ns + Data Path Delay: 0.294ns (Levels of Logic = 1) + Clock Path Skew: 0.072ns (1.155 - 1.083) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep$trn_clk rising at 0.000ns + Clock Uncertainty: 0.189ns + + Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.120ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_i2pS_39 to ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_39 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X153Y100.DQ Tcko 0.098 ftop/pciw_i2pS<39> + ftop/pciw_i2pS_39 + SLICE_X148Y100.D2 net (fanout=1) 0.273 ftop/pciw_i2pS<39> + SLICE_X148Y100.CLK Tah (-Th) 0.077 ftop/pciw_Prelude_inst_changeSpecialWires_2_rg<39> + ftop/Mmux_pciw_Prelude_inst_changeSpecialWires_2_rg$D_IN331 + ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_39 + ------------------------------------------------- --------------------------- + Total 0.294ns (0.021ns logic, 0.273ns route) + (7.1% logic, 92.9% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.033ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i (CPU) + Destination: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[0].ram/use_ramb36.ramb36 (RAM) + Requirement: 0.000ns + Data Path Delay: 0.156ns (Levels of Logic = 0) + Clock Path Skew: 0.123ns (0.836 - 0.713) + Source Clock: ftop/pciw_pci0_pcie_ep$trn_clk rising at 4.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep$trn_clk rising at 4.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i to ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[0].ram/use_ramb36.ramb36 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ---------------------------------------------------- ------------------- + PCIE_X0Y1.MIMRXWDATA14 Tpcicko_RXRAM 0.013 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + RAMB36_X8Y23.DIADI14 net (fanout=1) 0.341 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/MIMRXWDATA<14> + RAMB36_X8Y23.CLKARDCLKL Trckd_DIA (-Th) 0.198 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[0].ram/use_ramb36.ramb36 + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[0].ram/use_ramb36.ramb36 + ---------------------------------------------------- --------------------------- + Total 0.156ns (-0.185ns logic, 0.341ns route) + (-118.6% logic, 218.6% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.034ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[0].GTX_RX_VALID_FILTER/gt_rx_status_q_1 (FF) + Destination: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i (CPU) + Requirement: 0.000ns + Data Path Delay: 0.121ns (Levels of Logic = 1) + Clock Path Skew: 0.087ns (0.533 - 0.446) + Source Clock: ftop/pciw_pci0_pcie_ep/ep/pipe_clk rising at 4.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep/ep/pipe_clk rising at 4.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[0].GTX_RX_VALID_FILTER/gt_rx_status_q_1 to ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ----------------------------------------------------- ------------------- + SLICE_X151Y144.BQ Tcko 0.098 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[0].GTX_RX_VALID_FILTER/gt_rx_status_q<2> + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[0].GTX_RX_VALID_FILTER/gt_rx_status_q_1 + SLICE_X151Y139.B4 net (fanout=1) 0.219 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[0].GTX_RX_VALID_FILTER/gt_rx_status_q<1> + SLICE_X151Y139.B Tilo 0.034 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[0].GTX_RX_VALID_FILTER/awake_see_com_q + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[0].GTX_RX_VALID_FILTER/Mmux_USER_RX_STATUS21 + PCIE_X0Y1.PIPERX0STATUS1 net (fanout=1) 0.260 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX0STATUS<1> + PCIE_X0Y1.PIPECLK Tpcickc_MGT0(-Th) 0.490 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + ----------------------------------------------------- --------------------------- + Total 0.121ns (-0.358ns logic, 0.479ns route) + (-295.9% logic, 395.9% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.034ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/phy_rdy_n (FF) + Destination: ftop/pciw_pci0_pcie_ep/ep/trn_reset_n_i (FF) + Requirement: 0.000ns + Data Path Delay: 0.304ns (Levels of Logic = 1) + Clock Path Skew: 0.081ns (1.169 - 1.088) + Source Clock: ftop/pciw_pci0_pcie_ep/ep/pipe_clk rising at 4.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep$trn_clk rising at 4.000ns + Clock Uncertainty: 0.189ns + + Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.120ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/phy_rdy_n to ftop/pciw_pci0_pcie_ep/ep/trn_reset_n_i + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X150Y134.AQ Tcko 0.098 ftop/pciw_pci0_pcie_ep/ep/phy_rdy_n + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/phy_rdy_n + SLICE_X149Y127.D4 net (fanout=5) 0.263 ftop/pciw_pci0_pcie_ep/ep/phy_rdy_n + SLICE_X149Y127.CLK Tah (-Th) 0.057 ftop/pciw_pci0_pcie_ep$trn_reset_n + ftop/pciw_pci0_pcie_ep/ep/trn_reset_n_int1_phy_rdy_n_AND_10071_o1 + ftop/pciw_pci0_pcie_ep/ep/trn_reset_n_i + ------------------------------------------------- --------------------------- + Total 0.304ns (0.041ns logic, 0.263ns route) + (13.5% logic, 86.5% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.035ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX_RX_VALID_FILTER/gt_rxdata_q_8 (FF) + Destination: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i (CPU) + Requirement: 0.000ns + Data Path Delay: 0.115ns (Levels of Logic = 1) + Clock Path Skew: 0.080ns (0.533 - 0.453) + Source Clock: ftop/pciw_pci0_pcie_ep/ep/pipe_clk rising at 4.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep/ep/pipe_clk rising at 4.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX_RX_VALID_FILTER/gt_rxdata_q_8 to ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + --------------------------------------------------- ------------------- + SLICE_X151Y122.AMUX Tshcko 0.130 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX_RX_VALID_FILTER/gt_rxdata_q<3> + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX_RX_VALID_FILTER/gt_rxdata_q_8 + SLICE_X150Y122.D1 net (fanout=2) 0.166 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX_RX_VALID_FILTER/gt_rxdata_q<8> + SLICE_X150Y122.D Tilo 0.034 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX_RX_VALID_FILTER/reg_symbol_after_eios + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX_RX_VALID_FILTER/Mmux_USER_RXDATA<15:8>71 + PCIE_X0Y1.PIPERX3DATA8 net (fanout=1) 0.234 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX3DATA<8> + PCIE_X0Y1.PIPECLK Tpcickc_MGT3(-Th) 0.449 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + --------------------------------------------------- --------------------------- + Total 0.115ns (-0.285ns logic, 0.400ns route) + (-247.8% logic, 347.8% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.036ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_i2pS_34 (FF) + Destination: ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_34 (FF) + Requirement: 0.000ns + Data Path Delay: 0.295ns (Levels of Logic = 1) + Clock Path Skew: 0.070ns (1.164 - 1.094) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep$trn_clk rising at 0.000ns + Clock Uncertainty: 0.189ns + + Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.120ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_i2pS_34 to ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_34 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X150Y111.CQ Tcko 0.098 ftop/pciw_i2pS<35> + ftop/pciw_i2pS_34 + SLICE_X153Y106.C5 net (fanout=1) 0.253 ftop/pciw_i2pS<34> + SLICE_X153Y106.CLK Tah (-Th) 0.056 ftop/pciw_Prelude_inst_changeSpecialWires_2_rg<35> + ftop/Mmux_pciw_Prelude_inst_changeSpecialWires_2_rg$D_IN281 + ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_34 + ------------------------------------------------- --------------------------- + Total 0.295ns (0.042ns logic, 0.253ns route) + (14.2% logic, 85.8% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.040ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_i2pS_151 (FF) + Destination: ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_79 (FF) + Requirement: 0.000ns + Data Path Delay: 0.313ns (Levels of Logic = 1) + Clock Path Skew: 0.084ns (1.169 - 1.085) + Source Clock: ftop/p125clk rising at 0.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep$trn_clk rising at 0.000ns + Clock Uncertainty: 0.189ns + + Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.118ns + Phase Error (PE): 0.120ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_i2pS_151 to ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_79 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X141Y116.BQ Tcko 0.098 ftop/pciw_i2pS<152> + ftop/pciw_i2pS_151 + SLICE_X149Y112.A6 net (fanout=2) 0.270 ftop/pciw_i2pS<151> + SLICE_X149Y112.CLK Tah (-Th) 0.055 ftop/pciw_Prelude_inst_changeSpecialWires_2_rg<81> + ftop/Mmux_pciw_Prelude_inst_changeSpecialWires_2_rg$D_IN771 + ftop/pciw_Prelude_inst_changeSpecialWires_2_rg_79 + ------------------------------------------------- --------------------------- + Total 0.313ns (0.043ns logic, 0.270ns route) + (13.7% logic, 86.3% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.041ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX_RX_VALID_FILTER/gt_rxdata_q_15 (FF) + Destination: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i (CPU) + Requirement: 0.000ns + Data Path Delay: 0.120ns (Levels of Logic = 1) + Clock Path Skew: 0.079ns (0.533 - 0.454) + Source Clock: ftop/pciw_pci0_pcie_ep/ep/pipe_clk rising at 4.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep/ep/pipe_clk rising at 4.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX_RX_VALID_FILTER/gt_rxdata_q_15 to ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ---------------------------------------------------- ------------------- + SLICE_X152Y122.DQ Tcko 0.115 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX_RX_VALID_FILTER/gt_rxdata_q<15> + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX_RX_VALID_FILTER/gt_rxdata_q_15 + SLICE_X148Y122.D5 net (fanout=5) 0.181 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX_RX_VALID_FILTER/gt_rxdata_q<15> + SLICE_X148Y122.D Tilo 0.034 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX_RX_VALID_FILTER/gt_rxdata_q<7> + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX_RX_VALID_FILTER/Mmux_USER_RXDATA<15:8>61 + PCIE_X0Y1.PIPERX3DATA15 net (fanout=1) 0.237 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX3DATA<15> + PCIE_X0Y1.PIPECLK Tpcickc_MGT3(-Th) 0.447 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + ---------------------------------------------------- --------------------------- + Total 0.120ns (-0.298ns logic, 0.418ns route) + (-248.3% logic, 348.3% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.044ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i (CPU) + Destination: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[1].GTX (HSIO) + Requirement: 0.000ns + Data Path Delay: 0.433ns (Levels of Logic = 0) + Clock Path Skew: 0.389ns (1.416 - 1.027) + Source Clock: ftop/pciw_pci0_pcie_ep/ep/pipe_clk rising at 4.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep/ep/pipe_clk rising at 4.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Slow Process Corner: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i to ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[1].GTX + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ---------------------------------------------------- ------------------- + PCIE_X0Y1.PIPETXRCVRDET Tpcicko_MGT 0.062 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + GTXE1_X0Y14.TXDETECTRX net (fanout=4) 1.236 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETXRCVRDET + GTXE1_X0Y14.TXUSRCLK2 Tgtxckc_PCI (-Th) 0.865 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[1].GTX + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[1].GTX + ---------------------------------------------------- --------------------------- + Total 0.433ns (-0.803ns logic, 1.236ns route) + (-185.5% logic, 285.5% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.045ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX_RX_VALID_FILTER/gt_rxdata_q_13 (FF) + Destination: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i (CPU) + Requirement: 0.000ns + Data Path Delay: 0.124ns (Levels of Logic = 1) + Clock Path Skew: 0.079ns (0.533 - 0.454) + Source Clock: ftop/pciw_pci0_pcie_ep/ep/pipe_clk rising at 4.000ns + Destination Clock: ftop/pciw_pci0_pcie_ep/ep/pipe_clk rising at 4.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX_RX_VALID_FILTER/gt_rxdata_q_13 to ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ---------------------------------------------------- ------------------- + SLICE_X152Y122.BQ Tcko 0.115 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX_RX_VALID_FILTER/gt_rxdata_q<15> + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX_RX_VALID_FILTER/gt_rxdata_q_13 + SLICE_X148Y121.B5 net (fanout=2) 0.174 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX_RX_VALID_FILTER/gt_rxdata_q<13> + SLICE_X148Y121.B Tilo 0.034 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX3DATA<9> + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX_RX_VALID_FILTER/Mmux_USER_RXDATA<15:8>41 + PCIE_X0Y1.PIPERX3DATA13 net (fanout=1) 0.252 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX3DATA<13> + PCIE_X0Y1.PIPECLK Tpcickc_MGT3(-Th) 0.451 ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i + ---------------------------------------------------- --------------------------- + Total 0.124ns (-0.302ns logic, 0.426ns route) + (-243.5% logic, 343.5% route) + +-------------------------------------------------------------------------------- + +Component Switching Limit Checks: TS_CLK_250 = PERIOD TIMEGRP "CLK_250" TS_PCICLK HIGH 50% PRIORITY 1; +-------------------------------------------------------------------------------- +Slack: 0.000ns (period - min period limit) + Period: 4.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[0].GTX/RXUSRCLK + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[0].GTX/RXUSRCLK + Location pin: GTXE1_X0Y15.RXUSRCLK + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 0.000ns (period - min period limit) + Period: 4.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[0].GTX/RXUSRCLK2 + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[0].GTX/RXUSRCLK2 + Location pin: GTXE1_X0Y15.RXUSRCLK2 + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 0.000ns (period - min period limit) + Period: 4.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[0].GTX/TXUSRCLK + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[0].GTX/TXUSRCLK + Location pin: GTXE1_X0Y15.TXUSRCLK + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 0.000ns (period - min period limit) + Period: 4.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[0].GTX/TXUSRCLK2 + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[0].GTX/TXUSRCLK2 + Location pin: GTXE1_X0Y15.TXUSRCLK2 + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 0.000ns (period - min period limit) + Period: 4.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[1].GTX/RXUSRCLK + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[1].GTX/RXUSRCLK + Location pin: GTXE1_X0Y14.RXUSRCLK + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 0.000ns (period - min period limit) + Period: 4.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[1].GTX/RXUSRCLK2 + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[1].GTX/RXUSRCLK2 + Location pin: GTXE1_X0Y14.RXUSRCLK2 + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 0.000ns (period - min period limit) + Period: 4.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[1].GTX/TXUSRCLK + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[1].GTX/TXUSRCLK + Location pin: GTXE1_X0Y14.TXUSRCLK + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 0.000ns (period - min period limit) + Period: 4.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[1].GTX/TXUSRCLK2 + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[1].GTX/TXUSRCLK2 + Location pin: GTXE1_X0Y14.TXUSRCLK2 + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 0.000ns (period - min period limit) + Period: 4.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX/RXUSRCLK + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX/RXUSRCLK + Location pin: GTXE1_X0Y13.RXUSRCLK + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 0.000ns (period - min period limit) + Period: 4.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX/RXUSRCLK2 + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX/RXUSRCLK2 + Location pin: GTXE1_X0Y13.RXUSRCLK2 + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 0.000ns (period - min period limit) + Period: 4.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX/TXUSRCLK + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX/TXUSRCLK + Location pin: GTXE1_X0Y13.TXUSRCLK + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 0.000ns (period - min period limit) + Period: 4.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX/TXUSRCLK2 + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX/TXUSRCLK2 + Location pin: GTXE1_X0Y13.TXUSRCLK2 + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 0.000ns (period - min period limit) + Period: 4.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX/RXUSRCLK + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX/RXUSRCLK + Location pin: GTXE1_X0Y12.RXUSRCLK + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 0.000ns (period - min period limit) + Period: 4.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX/RXUSRCLK2 + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX/RXUSRCLK2 + Location pin: GTXE1_X0Y12.RXUSRCLK2 + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 0.000ns (period - min period limit) + Period: 4.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX/TXUSRCLK + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX/TXUSRCLK + Location pin: GTXE1_X0Y12.TXUSRCLK + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 0.000ns (period - min period limit) + Period: 4.000ns + Min period limit: 4.000ns (250.000MHz) (Tgtxper_USRCLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX/TXUSRCLK2 + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX/TXUSRCLK2 + Location pin: GTXE1_X0Y12.TXUSRCLK2 + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 0.000ns (period - min period limit) + Period: 4.000ns + Min period limit: 4.000ns (250.000MHz) (Tpciper_PIPECLK) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i/PIPECLK + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i/PIPECLK + Location pin: PCIE_X0Y1.PIPECLK + Clock network: ftop/pciw_pci0_pcie_ep/ep/pipe_clk +-------------------------------------------------------------------------------- +Slack: 1.778ns (period - min period limit) + Period: 4.000ns + Min period limit: 2.222ns (450.045MHz) (Trper_CLKA) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[3].ram/use_ramb36.ramb36/CLKARDCLKL + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[3].ram/use_ramb36.ramb36/CLKARDCLKL + Location pin: RAMB36_X7Y26.CLKARDCLKL + Clock network: ftop/pciw_pci0_pcie_ep$trn_clk +-------------------------------------------------------------------------------- +Slack: 1.778ns (period - min period limit) + Period: 4.000ns + Min period limit: 2.222ns (450.045MHz) (Trper_CLKB) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[3].ram/use_ramb36.ramb36/CLKBWRCLKL + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[3].ram/use_ramb36.ramb36/CLKBWRCLKL + Location pin: RAMB36_X7Y26.CLKBWRCLKL + Clock network: ftop/pciw_pci0_pcie_ep$trn_clk +-------------------------------------------------------------------------------- +Slack: 1.778ns (period - min period limit) + Period: 4.000ns + Min period limit: 2.222ns (450.045MHz) (Trper_CLKA) + Physical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[3].ram/use_ramb36.ramb36/CLKARDCLKL + Logical resource: ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[3].ram/use_ramb36.ramb36/CLKARDCLKL + Location pin: RAMB36_X6Y26.CLKARDCLKL + Clock network: ftop/pciw_pci0_pcie_ep$trn_clk +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: TS_GMII_RX_CLK = PERIOD TIMEGRP "GMII_RX_CLK" 125 MHz HIGH +50%; +For more information, see Period Analysis in the Timing Closure User Guide (UG612). + + 2549 paths analyzed, 537 endpoints analyzed, 0 failing endpoints + 0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors) + Minimum period is 5.467ns. +-------------------------------------------------------------------------------- +Slack (setup path): 2.533ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/rxRS_rxER (FF) + Destination: ftop/gbe0/gmac/rxRS_rxActive (FF) + Requirement: 8.000ns + Data Path Delay: 5.523ns (Levels of Logic = 3) + Clock Path Skew: 0.091ns (0.949 - 0.858) + Source Clock: ftop/rxclkBnd rising at 0.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/rxRS_rxER to ftop/gbe0/gmac/rxRS_rxActive + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X90Y45.DQ Tcko 0.337 ftop/gbe0/gmac/rxRS_rxER + ftop/gbe0/gmac/rxRS_rxER + SLICE_X111Y15.D5 net (fanout=14) 2.238 ftop/gbe0/gmac/rxRS_rxER + SLICE_X111Y15.D Tilo 0.068 ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_advance + ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_advance1 + SLICE_X102Y22.C4 net (fanout=10) 1.040 ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_advance + SLICE_X102Y22.C Tilo 0.068 ftop/gbe0/gmac/N8 + ftop/gbe0/gmac/rxRS_rxActive$EN1 + SLICE_X107Y22.D4 net (fanout=2) 0.538 ftop/gbe0/gmac/rxRS_rxActive$EN1 + SLICE_X107Y22.D Tilo 0.068 ftop/gbe0/gmac/rxRS_rxActive$EN + ftop/gbe0/gmac/rxRS_rxActive$EN2 + SLICE_X113Y14.CE net (fanout=1) 0.848 ftop/gbe0/gmac/rxRS_rxActive$EN + SLICE_X113Y14.CLK Tceck 0.318 ftop/gbe0/gmac/rxRS_rxActive + ftop/gbe0/gmac/rxRS_rxActive + ------------------------------------------------- --------------------------- + Total 5.523ns (0.859ns logic, 4.664ns route) + (15.6% logic, 84.4% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 3.076ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/rxRS_rxDV (FF) + Destination: ftop/gbe0/gmac/rxRS_rxActive (FF) + Requirement: 8.000ns + Data Path Delay: 4.905ns (Levels of Logic = 3) + Clock Path Skew: 0.016ns (0.730 - 0.714) + Source Clock: ftop/rxclkBnd rising at 0.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/rxRS_rxDV to ftop/gbe0/gmac/rxRS_rxActive + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X97Y31.DQ Tcko 0.337 ftop/gbe0/gmac/rxRS_rxDV + ftop/gbe0/gmac/rxRS_rxDV + SLICE_X111Y15.D1 net (fanout=4) 1.620 ftop/gbe0/gmac/rxRS_rxDV + SLICE_X111Y15.D Tilo 0.068 ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_advance + ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_advance1 + SLICE_X102Y22.C4 net (fanout=10) 1.040 ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_advance + SLICE_X102Y22.C Tilo 0.068 ftop/gbe0/gmac/N8 + ftop/gbe0/gmac/rxRS_rxActive$EN1 + SLICE_X107Y22.D4 net (fanout=2) 0.538 ftop/gbe0/gmac/rxRS_rxActive$EN1 + SLICE_X107Y22.D Tilo 0.068 ftop/gbe0/gmac/rxRS_rxActive$EN + ftop/gbe0/gmac/rxRS_rxActive$EN2 + SLICE_X113Y14.CE net (fanout=1) 0.848 ftop/gbe0/gmac/rxRS_rxActive$EN + SLICE_X113Y14.CLK Tceck 0.318 ftop/gbe0/gmac/rxRS_rxActive + ftop/gbe0/gmac/rxRS_rxActive + ------------------------------------------------- --------------------------- + Total 4.905ns (0.859ns logic, 4.046ns route) + (17.5% logic, 82.5% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 3.083ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/rxRS_rxER (FF) + Destination: ftop/gbe0/gmac/rxRS_preambleCnt_value_2 (FF) + Requirement: 8.000ns + Data Path Delay: 4.949ns (Levels of Logic = 3) + Clock Path Skew: 0.067ns (0.925 - 0.858) + Source Clock: ftop/rxclkBnd rising at 0.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/rxRS_rxER to ftop/gbe0/gmac/rxRS_preambleCnt_value_2 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X90Y45.DQ Tcko 0.337 ftop/gbe0/gmac/rxRS_rxER + ftop/gbe0/gmac/rxRS_rxER + SLICE_X111Y15.D5 net (fanout=14) 2.238 ftop/gbe0/gmac/rxRS_rxER + SLICE_X111Y15.D Tilo 0.068 ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_advance + ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_advance1 + SLICE_X102Y22.C4 net (fanout=10) 1.040 ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_advance + SLICE_X102Y22.C Tilo 0.068 ftop/gbe0/gmac/N8 + ftop/gbe0/gmac/rxRS_rxActive$EN1 + SLICE_X106Y22.A4 net (fanout=2) 0.559 ftop/gbe0/gmac/rxRS_rxActive$EN1 + SLICE_X106Y22.A Tilo 0.068 ftop/gbe0/gmac/_n0446_inv + ftop/gbe0/gmac/_n0446_inv1 + SLICE_X109Y22.CE net (fanout=1) 0.253 ftop/gbe0/gmac/_n0446_inv + SLICE_X109Y22.CLK Tceck 0.318 ftop/gbe0/gmac/rxRS_preambleCnt_value<3> + ftop/gbe0/gmac/rxRS_preambleCnt_value_2 + ------------------------------------------------- --------------------------- + Total 4.949ns (0.859ns logic, 4.090ns route) + (17.4% logic, 82.6% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 3.083ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/rxRS_rxER (FF) + Destination: ftop/gbe0/gmac/rxRS_preambleCnt_value_0 (FF) + Requirement: 8.000ns + Data Path Delay: 4.949ns (Levels of Logic = 3) + Clock Path Skew: 0.067ns (0.925 - 0.858) + Source Clock: ftop/rxclkBnd rising at 0.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/rxRS_rxER to ftop/gbe0/gmac/rxRS_preambleCnt_value_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X90Y45.DQ Tcko 0.337 ftop/gbe0/gmac/rxRS_rxER + ftop/gbe0/gmac/rxRS_rxER + SLICE_X111Y15.D5 net (fanout=14) 2.238 ftop/gbe0/gmac/rxRS_rxER + SLICE_X111Y15.D Tilo 0.068 ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_advance + ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_advance1 + SLICE_X102Y22.C4 net (fanout=10) 1.040 ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_advance + SLICE_X102Y22.C Tilo 0.068 ftop/gbe0/gmac/N8 + ftop/gbe0/gmac/rxRS_rxActive$EN1 + SLICE_X106Y22.A4 net (fanout=2) 0.559 ftop/gbe0/gmac/rxRS_rxActive$EN1 + SLICE_X106Y22.A Tilo 0.068 ftop/gbe0/gmac/_n0446_inv + ftop/gbe0/gmac/_n0446_inv1 + SLICE_X109Y22.CE net (fanout=1) 0.253 ftop/gbe0/gmac/_n0446_inv + SLICE_X109Y22.CLK Tceck 0.318 ftop/gbe0/gmac/rxRS_preambleCnt_value<3> + ftop/gbe0/gmac/rxRS_preambleCnt_value_0 + ------------------------------------------------- --------------------------- + Total 4.949ns (0.859ns logic, 4.090ns route) + (17.4% logic, 82.6% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 3.083ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/rxRS_rxER (FF) + Destination: ftop/gbe0/gmac/rxRS_preambleCnt_value_3 (FF) + Requirement: 8.000ns + Data Path Delay: 4.949ns (Levels of Logic = 3) + Clock Path Skew: 0.067ns (0.925 - 0.858) + Source Clock: ftop/rxclkBnd rising at 0.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/rxRS_rxER to ftop/gbe0/gmac/rxRS_preambleCnt_value_3 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X90Y45.DQ Tcko 0.337 ftop/gbe0/gmac/rxRS_rxER + ftop/gbe0/gmac/rxRS_rxER + SLICE_X111Y15.D5 net (fanout=14) 2.238 ftop/gbe0/gmac/rxRS_rxER + SLICE_X111Y15.D Tilo 0.068 ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_advance + ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_advance1 + SLICE_X102Y22.C4 net (fanout=10) 1.040 ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_advance + SLICE_X102Y22.C Tilo 0.068 ftop/gbe0/gmac/N8 + ftop/gbe0/gmac/rxRS_rxActive$EN1 + SLICE_X106Y22.A4 net (fanout=2) 0.559 ftop/gbe0/gmac/rxRS_rxActive$EN1 + SLICE_X106Y22.A Tilo 0.068 ftop/gbe0/gmac/_n0446_inv + ftop/gbe0/gmac/_n0446_inv1 + SLICE_X109Y22.CE net (fanout=1) 0.253 ftop/gbe0/gmac/_n0446_inv + SLICE_X109Y22.CLK Tceck 0.318 ftop/gbe0/gmac/rxRS_preambleCnt_value<3> + ftop/gbe0/gmac/rxRS_preambleCnt_value_3 + ------------------------------------------------- --------------------------- + Total 4.949ns (0.859ns logic, 4.090ns route) + (17.4% logic, 82.6% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 3.083ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/rxRS_rxER (FF) + Destination: ftop/gbe0/gmac/rxRS_preambleCnt_value_1 (FF) + Requirement: 8.000ns + Data Path Delay: 4.949ns (Levels of Logic = 3) + Clock Path Skew: 0.067ns (0.925 - 0.858) + Source Clock: ftop/rxclkBnd rising at 0.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/rxRS_rxER to ftop/gbe0/gmac/rxRS_preambleCnt_value_1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X90Y45.DQ Tcko 0.337 ftop/gbe0/gmac/rxRS_rxER + ftop/gbe0/gmac/rxRS_rxER + SLICE_X111Y15.D5 net (fanout=14) 2.238 ftop/gbe0/gmac/rxRS_rxER + SLICE_X111Y15.D Tilo 0.068 ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_advance + ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_advance1 + SLICE_X102Y22.C4 net (fanout=10) 1.040 ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_advance + SLICE_X102Y22.C Tilo 0.068 ftop/gbe0/gmac/N8 + ftop/gbe0/gmac/rxRS_rxActive$EN1 + SLICE_X106Y22.A4 net (fanout=2) 0.559 ftop/gbe0/gmac/rxRS_rxActive$EN1 + SLICE_X106Y22.A Tilo 0.068 ftop/gbe0/gmac/_n0446_inv + ftop/gbe0/gmac/_n0446_inv1 + SLICE_X109Y22.CE net (fanout=1) 0.253 ftop/gbe0/gmac/_n0446_inv + SLICE_X109Y22.CLK Tceck 0.318 ftop/gbe0/gmac/rxRS_preambleCnt_value<3> + ftop/gbe0/gmac/rxRS_preambleCnt_value_1 + ------------------------------------------------- --------------------------- + Total 4.949ns (0.859ns logic, 4.090ns route) + (17.4% logic, 82.6% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 3.348ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/rxRS_rxRst/reset_hold_1 (FF) + Destination: ftop/gbe0/gmac/rxRS_rxER (FF) + Requirement: 8.000ns + Data Path Delay: 4.320ns (Levels of Logic = 1) + Clock Path Skew: -0.297ns (0.777 - 1.074) + Source Clock: ftop/rxclkBnd rising at 0.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/rxRS_rxRst/reset_hold_1 to ftop/gbe0/gmac/rxRS_rxER + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X121Y7.DQ Tcko 0.337 ftop/gbe0/gmac/rxRS_rxRst$OUT_RST + ftop/gbe0/gmac/rxRS_rxRst/reset_hold_1 + SLICE_X120Y13.A4 net (fanout=7) 0.592 ftop/gbe0/gmac/rxRS_rxRst$OUT_RST + SLICE_X120Y13.A Tilo 0.068 ftop/gbe0/gmac/rxRS_rxRst$OUT_RST_inv + ftop/gbe0/gmac/rxRS_rxRst$OUT_RST_inv1_INV_0 + SLICE_X90Y45.SR net (fanout=7) 2.810 ftop/gbe0/gmac/rxRS_rxRst$OUT_RST_inv + SLICE_X90Y45.CLK Tsrck 0.513 ftop/gbe0/gmac/rxRS_rxER + ftop/gbe0/gmac/rxRS_rxER + ------------------------------------------------- --------------------------- + Total 4.320ns (0.918ns logic, 3.402ns route) + (21.2% logic, 78.8% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 3.514ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 (FF) + Destination: ftop/gbe0/gmac/rxRS_rxActive (FF) + Requirement: 8.000ns + Data Path Delay: 4.362ns (Levels of Logic = 3) + Clock Path Skew: -0.089ns (0.730 - 0.819) + Source Clock: ftop/rxclkBnd rising at 0.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 to ftop/gbe0/gmac/rxRS_rxActive + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X120Y17.DQ Tcko 0.381 ftop/gbe0/gmac/rxRS_rxOperateS$dD_OUT + ftop/gbe0/gmac/rxRS_rxOperateS/dSyncReg2 + SLICE_X111Y15.D3 net (fanout=19) 1.033 ftop/gbe0/gmac/rxRS_rxOperateS$dD_OUT + SLICE_X111Y15.D Tilo 0.068 ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_advance + ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_advance1 + SLICE_X102Y22.C4 net (fanout=10) 1.040 ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_advance + SLICE_X102Y22.C Tilo 0.068 ftop/gbe0/gmac/N8 + ftop/gbe0/gmac/rxRS_rxActive$EN1 + SLICE_X107Y22.D4 net (fanout=2) 0.538 ftop/gbe0/gmac/rxRS_rxActive$EN1 + SLICE_X107Y22.D Tilo 0.068 ftop/gbe0/gmac/rxRS_rxActive$EN + ftop/gbe0/gmac/rxRS_rxActive$EN2 + SLICE_X113Y14.CE net (fanout=1) 0.848 ftop/gbe0/gmac/rxRS_rxActive$EN + SLICE_X113Y14.CLK Tceck 0.318 ftop/gbe0/gmac/rxRS_rxActive + ftop/gbe0/gmac/rxRS_rxActive + ------------------------------------------------- --------------------------- + Total 4.362ns (0.903ns logic, 3.459ns route) + (20.7% logic, 79.3% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 3.562ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/rxRS_rxAPipe_0 (FF) + Destination: ftop/gbe0/gmac/rxRS_rxActive (FF) + Requirement: 8.000ns + Data Path Delay: 4.312ns (Levels of Logic = 4) + Clock Path Skew: -0.091ns (0.730 - 0.821) + Source Clock: ftop/rxclkBnd rising at 0.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/rxRS_rxAPipe_0 to ftop/gbe0/gmac/rxRS_rxActive + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X117Y10.AQ Tcko 0.337 ftop/gbe0/gmac/rxRS_rxAPipe<3> + ftop/gbe0/gmac/rxRS_rxAPipe_0 + SLICE_X119Y11.B2 net (fanout=2) 0.727 ftop/gbe0/gmac/rxRS_rxAPipe<0> + SLICE_X119Y11.B Tilo 0.068 ftop/gbe0/mdi_fRequest/data1_reg<19> + ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_noadvance_SW0 + SLICE_X119Y11.A6 net (fanout=2) 0.115 ftop/gbe0/gmac/N10 + SLICE_X119Y11.A Tilo 0.068 ftop/gbe0/mdi_fRequest/data1_reg<19> + ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_noadvance + SLICE_X107Y22.C4 net (fanout=44) 1.356 ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_noadvance + SLICE_X107Y22.C Tilo 0.068 ftop/gbe0/gmac/rxRS_rxActive$EN + ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_end_frame1 + SLICE_X107Y22.D3 net (fanout=2) 0.339 ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_end_frame + SLICE_X107Y22.D Tilo 0.068 ftop/gbe0/gmac/rxRS_rxActive$EN + ftop/gbe0/gmac/rxRS_rxActive$EN2 + SLICE_X113Y14.CE net (fanout=1) 0.848 ftop/gbe0/gmac/rxRS_rxActive$EN + SLICE_X113Y14.CLK Tceck 0.318 ftop/gbe0/gmac/rxRS_rxActive + ftop/gbe0/gmac/rxRS_rxActive + ------------------------------------------------- --------------------------- + Total 4.312ns (0.927ns logic, 3.385ns route) + (21.5% logic, 78.5% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 3.573ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/rxRS_rxPipe_1 (FF) + Destination: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem24/SP (RAM) + Requirement: 8.000ns + Data Path Delay: 4.428ns (Levels of Logic = 2) + Clock Path Skew: 0.036ns (0.773 - 0.737) + Source Clock: ftop/rxclkBnd rising at 0.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/rxRS_rxPipe_1 to ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem24/SP + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X102Y20.BQ Tcko 0.381 ftop/gbe0/gmac/rxRS_rxPipe<3> + ftop/gbe0/gmac/rxRS_rxPipe_1 + SLICE_X111Y7.A2 net (fanout=2) 1.259 ftop/gbe0/gmac/rxRS_rxPipe<1> + SLICE_X111Y7.CMUX Topac 0.566 ftop/gbe0/gmac/MUX_rxRS_rxF$enq_1__VAL_1<9> + ftop/gbe0/gmac/Mcompar_MUX_rxRS_rxF$enq_1__VAL_1<9>_lut<8> + ftop/gbe0/gmac/Mcompar_MUX_rxRS_rxF$enq_1__VAL_1<9>_cy<10> + SLICE_X121Y13.A1 net (fanout=1) 1.132 ftop/gbe0/gmac/MUX_rxRS_rxF$enq_1__VAL_1<9> + SLICE_X121Y13.A Tilo 0.068 ftop/gbe0/gmac/rxRS_rxF$sD_IN<9> + ftop/gbe0/gmac/Mmux_rxRS_rxF$sD_IN101 + SLICE_X126Y15.BI net (fanout=1) 0.545 ftop/gbe0/gmac/rxRS_rxF$sD_IN<9> + SLICE_X126Y15.CLK Tds 0.477 ftop/gbe0/gmac/rxRS_rxF/_n0110<6> + ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem24/SP + ------------------------------------------------- --------------------------- + Total 4.428ns (1.492ns logic, 2.936ns route) + (33.7% logic, 66.3% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 3.585ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/rxRS_rxF/sNotFullReg (FF) + Destination: ftop/gbe0/gmac/rxRS_rxActive (FF) + Requirement: 8.000ns + Data Path Delay: 4.272ns (Levels of Logic = 3) + Clock Path Skew: -0.108ns (0.730 - 0.838) + Source Clock: ftop/rxclkBnd rising at 0.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/rxRS_rxF/sNotFullReg to ftop/gbe0/gmac/rxRS_rxActive + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X128Y14.CQ Tcko 0.381 ftop/gbe0/gmac/rxRS_rxF$sFULL_N + ftop/gbe0/gmac/rxRS_rxF/sNotFullReg + SLICE_X119Y11.A4 net (fanout=5) 0.826 ftop/gbe0/gmac/rxRS_rxF$sFULL_N + SLICE_X119Y11.A Tilo 0.068 ftop/gbe0/mdi_fRequest/data1_reg<19> + ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_noadvance + SLICE_X107Y22.C4 net (fanout=44) 1.356 ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_noadvance + SLICE_X107Y22.C Tilo 0.068 ftop/gbe0/gmac/rxRS_rxActive$EN + ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_end_frame1 + SLICE_X107Y22.D3 net (fanout=2) 0.339 ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_end_frame + SLICE_X107Y22.D Tilo 0.068 ftop/gbe0/gmac/rxRS_rxActive$EN + ftop/gbe0/gmac/rxRS_rxActive$EN2 + SLICE_X113Y14.CE net (fanout=1) 0.848 ftop/gbe0/gmac/rxRS_rxActive$EN + SLICE_X113Y14.CLK Tceck 0.318 ftop/gbe0/gmac/rxRS_rxActive + ftop/gbe0/gmac/rxRS_rxActive + ------------------------------------------------- --------------------------- + Total 4.272ns (0.903ns logic, 3.369ns route) + (21.1% logic, 78.9% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 3.606ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/rxRS_rxPipe_4 (FF) + Destination: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem24/SP (RAM) + Requirement: 8.000ns + Data Path Delay: 4.367ns (Levels of Logic = 2) + Clock Path Skew: 0.008ns (0.773 - 0.765) + Source Clock: ftop/rxclkBnd rising at 0.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/rxRS_rxPipe_4 to ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem24/SP + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X108Y21.AQ Tcko 0.381 ftop/gbe0/gmac/rxRS_rxPipe<7> + ftop/gbe0/gmac/rxRS_rxPipe_4 + SLICE_X111Y7.B3 net (fanout=2) 1.206 ftop/gbe0/gmac/rxRS_rxPipe<4> + SLICE_X111Y7.CMUX Topbc 0.558 ftop/gbe0/gmac/MUX_rxRS_rxF$enq_1__VAL_1<9> + ftop/gbe0/gmac/Mcompar_MUX_rxRS_rxF$enq_1__VAL_1<9>_lut<9> + ftop/gbe0/gmac/Mcompar_MUX_rxRS_rxF$enq_1__VAL_1<9>_cy<10> + SLICE_X121Y13.A1 net (fanout=1) 1.132 ftop/gbe0/gmac/MUX_rxRS_rxF$enq_1__VAL_1<9> + SLICE_X121Y13.A Tilo 0.068 ftop/gbe0/gmac/rxRS_rxF$sD_IN<9> + ftop/gbe0/gmac/Mmux_rxRS_rxF$sD_IN101 + SLICE_X126Y15.BI net (fanout=1) 0.545 ftop/gbe0/gmac/rxRS_rxF$sD_IN<9> + SLICE_X126Y15.CLK Tds 0.477 ftop/gbe0/gmac/rxRS_rxF/_n0110<6> + ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem24/SP + ------------------------------------------------- --------------------------- + Total 4.367ns (1.484ns logic, 2.883ns route) + (34.0% logic, 66.0% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 3.626ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/rxRS_rxDV (FF) + Destination: ftop/gbe0/gmac/rxRS_preambleCnt_value_2 (FF) + Requirement: 8.000ns + Data Path Delay: 4.331ns (Levels of Logic = 3) + Clock Path Skew: -0.008ns (0.706 - 0.714) + Source Clock: ftop/rxclkBnd rising at 0.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/rxRS_rxDV to ftop/gbe0/gmac/rxRS_preambleCnt_value_2 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X97Y31.DQ Tcko 0.337 ftop/gbe0/gmac/rxRS_rxDV + ftop/gbe0/gmac/rxRS_rxDV + SLICE_X111Y15.D1 net (fanout=4) 1.620 ftop/gbe0/gmac/rxRS_rxDV + SLICE_X111Y15.D Tilo 0.068 ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_advance + ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_advance1 + SLICE_X102Y22.C4 net (fanout=10) 1.040 ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_advance + SLICE_X102Y22.C Tilo 0.068 ftop/gbe0/gmac/N8 + ftop/gbe0/gmac/rxRS_rxActive$EN1 + SLICE_X106Y22.A4 net (fanout=2) 0.559 ftop/gbe0/gmac/rxRS_rxActive$EN1 + SLICE_X106Y22.A Tilo 0.068 ftop/gbe0/gmac/_n0446_inv + ftop/gbe0/gmac/_n0446_inv1 + SLICE_X109Y22.CE net (fanout=1) 0.253 ftop/gbe0/gmac/_n0446_inv + SLICE_X109Y22.CLK Tceck 0.318 ftop/gbe0/gmac/rxRS_preambleCnt_value<3> + ftop/gbe0/gmac/rxRS_preambleCnt_value_2 + ------------------------------------------------- --------------------------- + Total 4.331ns (0.859ns logic, 3.472ns route) + (19.8% logic, 80.2% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 3.626ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/rxRS_rxDV (FF) + Destination: ftop/gbe0/gmac/rxRS_preambleCnt_value_0 (FF) + Requirement: 8.000ns + Data Path Delay: 4.331ns (Levels of Logic = 3) + Clock Path Skew: -0.008ns (0.706 - 0.714) + Source Clock: ftop/rxclkBnd rising at 0.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/rxRS_rxDV to ftop/gbe0/gmac/rxRS_preambleCnt_value_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X97Y31.DQ Tcko 0.337 ftop/gbe0/gmac/rxRS_rxDV + ftop/gbe0/gmac/rxRS_rxDV + SLICE_X111Y15.D1 net (fanout=4) 1.620 ftop/gbe0/gmac/rxRS_rxDV + SLICE_X111Y15.D Tilo 0.068 ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_advance + ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_advance1 + SLICE_X102Y22.C4 net (fanout=10) 1.040 ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_advance + SLICE_X102Y22.C Tilo 0.068 ftop/gbe0/gmac/N8 + ftop/gbe0/gmac/rxRS_rxActive$EN1 + SLICE_X106Y22.A4 net (fanout=2) 0.559 ftop/gbe0/gmac/rxRS_rxActive$EN1 + SLICE_X106Y22.A Tilo 0.068 ftop/gbe0/gmac/_n0446_inv + ftop/gbe0/gmac/_n0446_inv1 + SLICE_X109Y22.CE net (fanout=1) 0.253 ftop/gbe0/gmac/_n0446_inv + SLICE_X109Y22.CLK Tceck 0.318 ftop/gbe0/gmac/rxRS_preambleCnt_value<3> + ftop/gbe0/gmac/rxRS_preambleCnt_value_0 + ------------------------------------------------- --------------------------- + Total 4.331ns (0.859ns logic, 3.472ns route) + (19.8% logic, 80.2% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 3.626ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/rxRS_rxDV (FF) + Destination: ftop/gbe0/gmac/rxRS_preambleCnt_value_3 (FF) + Requirement: 8.000ns + Data Path Delay: 4.331ns (Levels of Logic = 3) + Clock Path Skew: -0.008ns (0.706 - 0.714) + Source Clock: ftop/rxclkBnd rising at 0.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/rxRS_rxDV to ftop/gbe0/gmac/rxRS_preambleCnt_value_3 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X97Y31.DQ Tcko 0.337 ftop/gbe0/gmac/rxRS_rxDV + ftop/gbe0/gmac/rxRS_rxDV + SLICE_X111Y15.D1 net (fanout=4) 1.620 ftop/gbe0/gmac/rxRS_rxDV + SLICE_X111Y15.D Tilo 0.068 ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_advance + ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_advance1 + SLICE_X102Y22.C4 net (fanout=10) 1.040 ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_advance + SLICE_X102Y22.C Tilo 0.068 ftop/gbe0/gmac/N8 + ftop/gbe0/gmac/rxRS_rxActive$EN1 + SLICE_X106Y22.A4 net (fanout=2) 0.559 ftop/gbe0/gmac/rxRS_rxActive$EN1 + SLICE_X106Y22.A Tilo 0.068 ftop/gbe0/gmac/_n0446_inv + ftop/gbe0/gmac/_n0446_inv1 + SLICE_X109Y22.CE net (fanout=1) 0.253 ftop/gbe0/gmac/_n0446_inv + SLICE_X109Y22.CLK Tceck 0.318 ftop/gbe0/gmac/rxRS_preambleCnt_value<3> + ftop/gbe0/gmac/rxRS_preambleCnt_value_3 + ------------------------------------------------- --------------------------- + Total 4.331ns (0.859ns logic, 3.472ns route) + (19.8% logic, 80.2% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 3.626ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/rxRS_rxDV (FF) + Destination: ftop/gbe0/gmac/rxRS_preambleCnt_value_1 (FF) + Requirement: 8.000ns + Data Path Delay: 4.331ns (Levels of Logic = 3) + Clock Path Skew: -0.008ns (0.706 - 0.714) + Source Clock: ftop/rxclkBnd rising at 0.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/rxRS_rxDV to ftop/gbe0/gmac/rxRS_preambleCnt_value_1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X97Y31.DQ Tcko 0.337 ftop/gbe0/gmac/rxRS_rxDV + ftop/gbe0/gmac/rxRS_rxDV + SLICE_X111Y15.D1 net (fanout=4) 1.620 ftop/gbe0/gmac/rxRS_rxDV + SLICE_X111Y15.D Tilo 0.068 ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_advance + ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_advance1 + SLICE_X102Y22.C4 net (fanout=10) 1.040 ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_advance + SLICE_X102Y22.C Tilo 0.068 ftop/gbe0/gmac/N8 + ftop/gbe0/gmac/rxRS_rxActive$EN1 + SLICE_X106Y22.A4 net (fanout=2) 0.559 ftop/gbe0/gmac/rxRS_rxActive$EN1 + SLICE_X106Y22.A Tilo 0.068 ftop/gbe0/gmac/_n0446_inv + ftop/gbe0/gmac/_n0446_inv1 + SLICE_X109Y22.CE net (fanout=1) 0.253 ftop/gbe0/gmac/_n0446_inv + SLICE_X109Y22.CLK Tceck 0.318 ftop/gbe0/gmac/rxRS_preambleCnt_value<3> + ftop/gbe0/gmac/rxRS_preambleCnt_value_1 + ------------------------------------------------- --------------------------- + Total 4.331ns (0.859ns logic, 3.472ns route) + (19.8% logic, 80.2% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 3.653ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/rxRS_rxActive (FF) + Destination: ftop/gbe0/gmac/rxRS_rxActive (FF) + Requirement: 8.000ns + Data Path Delay: 4.312ns (Levels of Logic = 3) + Clock Path Skew: 0.000ns + Source Clock: ftop/rxclkBnd rising at 0.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/rxRS_rxActive to ftop/gbe0/gmac/rxRS_rxActive + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X113Y14.AQ Tcko 0.337 ftop/gbe0/gmac/rxRS_rxActive + ftop/gbe0/gmac/rxRS_rxActive + SLICE_X119Y11.A1 net (fanout=3) 0.910 ftop/gbe0/gmac/rxRS_rxActive + SLICE_X119Y11.A Tilo 0.068 ftop/gbe0/mdi_fRequest/data1_reg<19> + ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_noadvance + SLICE_X107Y22.C4 net (fanout=44) 1.356 ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_noadvance + SLICE_X107Y22.C Tilo 0.068 ftop/gbe0/gmac/rxRS_rxActive$EN + ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_end_frame1 + SLICE_X107Y22.D3 net (fanout=2) 0.339 ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_end_frame + SLICE_X107Y22.D Tilo 0.068 ftop/gbe0/gmac/rxRS_rxActive$EN + ftop/gbe0/gmac/rxRS_rxActive$EN2 + SLICE_X113Y14.CE net (fanout=1) 0.848 ftop/gbe0/gmac/rxRS_rxActive$EN + SLICE_X113Y14.CLK Tceck 0.318 ftop/gbe0/gmac/rxRS_rxActive + ftop/gbe0/gmac/rxRS_rxActive + ------------------------------------------------- --------------------------- + Total 4.312ns (0.859ns logic, 3.453ns route) + (19.9% logic, 80.1% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 3.662ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/rxRS_crcEnd (FF) + Destination: ftop/gbe0/gmac/rxRS_rxActive (FF) + Requirement: 8.000ns + Data Path Delay: 4.283ns (Levels of Logic = 4) + Clock Path Skew: -0.020ns (0.087 - 0.107) + Source Clock: ftop/rxclkBnd rising at 0.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/rxRS_crcEnd to ftop/gbe0/gmac/rxRS_rxActive + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X112Y13.BQ Tcko 0.381 ftop/gbe0/gmac/rxRS_crcEnd + ftop/gbe0/gmac/rxRS_crcEnd + SLICE_X119Y11.B5 net (fanout=12) 0.654 ftop/gbe0/gmac/rxRS_crcEnd + SLICE_X119Y11.B Tilo 0.068 ftop/gbe0/mdi_fRequest/data1_reg<19> + ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_noadvance_SW0 + SLICE_X119Y11.A6 net (fanout=2) 0.115 ftop/gbe0/gmac/N10 + SLICE_X119Y11.A Tilo 0.068 ftop/gbe0/mdi_fRequest/data1_reg<19> + ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_noadvance + SLICE_X107Y22.C4 net (fanout=44) 1.356 ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_ingress_noadvance + SLICE_X107Y22.C Tilo 0.068 ftop/gbe0/gmac/rxRS_rxActive$EN + ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_end_frame1 + SLICE_X107Y22.D3 net (fanout=2) 0.339 ftop/gbe0/gmac/WILL_FIRE_RL_rxRS_end_frame + SLICE_X107Y22.D Tilo 0.068 ftop/gbe0/gmac/rxRS_rxActive$EN + ftop/gbe0/gmac/rxRS_rxActive$EN2 + SLICE_X113Y14.CE net (fanout=1) 0.848 ftop/gbe0/gmac/rxRS_rxActive$EN + SLICE_X113Y14.CLK Tceck 0.318 ftop/gbe0/gmac/rxRS_rxActive + ftop/gbe0/gmac/rxRS_rxActive + ------------------------------------------------- --------------------------- + Total 4.283ns (0.971ns logic, 3.312ns route) + (22.7% logic, 77.3% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 3.674ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/rxRS_rxER (FF) + Destination: ftop/gbe0/gmac/rxRS_preambleCnt_value_2 (FF) + Requirement: 8.000ns + Data Path Delay: 4.358ns (Levels of Logic = 1) + Clock Path Skew: 0.067ns (0.925 - 0.858) + Source Clock: ftop/rxclkBnd rising at 0.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/rxRS_rxER to ftop/gbe0/gmac/rxRS_preambleCnt_value_2 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X90Y45.DQ Tcko 0.337 ftop/gbe0/gmac/rxRS_rxER + ftop/gbe0/gmac/rxRS_rxER + SLICE_X116Y15.D4 net (fanout=14) 2.558 ftop/gbe0/gmac/rxRS_rxER + SLICE_X116Y15.D Tilo 0.068 ftop/gbe0/mdi_vrReadData_7 + ftop/gbe0/gmac/Reset_OR_DriverANDClockEnable1 + SLICE_X109Y22.SR net (fanout=1) 0.882 ftop/gbe0/gmac/Reset_OR_DriverANDClockEnable + SLICE_X109Y22.CLK Tsrck 0.513 ftop/gbe0/gmac/rxRS_preambleCnt_value<3> + ftop/gbe0/gmac/rxRS_preambleCnt_value_2 + ------------------------------------------------- --------------------------- + Total 4.358ns (0.918ns logic, 3.440ns route) + (21.1% logic, 78.9% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 3.674ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/rxRS_rxER (FF) + Destination: ftop/gbe0/gmac/rxRS_preambleCnt_value_3 (FF) + Requirement: 8.000ns + Data Path Delay: 4.358ns (Levels of Logic = 1) + Clock Path Skew: 0.067ns (0.925 - 0.858) + Source Clock: ftop/rxclkBnd rising at 0.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/rxRS_rxER to ftop/gbe0/gmac/rxRS_preambleCnt_value_3 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X90Y45.DQ Tcko 0.337 ftop/gbe0/gmac/rxRS_rxER + ftop/gbe0/gmac/rxRS_rxER + SLICE_X116Y15.D4 net (fanout=14) 2.558 ftop/gbe0/gmac/rxRS_rxER + SLICE_X116Y15.D Tilo 0.068 ftop/gbe0/mdi_vrReadData_7 + ftop/gbe0/gmac/Reset_OR_DriverANDClockEnable1 + SLICE_X109Y22.SR net (fanout=1) 0.882 ftop/gbe0/gmac/Reset_OR_DriverANDClockEnable + SLICE_X109Y22.CLK Tsrck 0.513 ftop/gbe0/gmac/rxRS_preambleCnt_value<3> + ftop/gbe0/gmac/rxRS_preambleCnt_value_3 + ------------------------------------------------- --------------------------- + Total 4.358ns (0.918ns logic, 3.440ns route) + (21.1% logic, 78.9% route) + +-------------------------------------------------------------------------------- + +Hold Paths: TS_GMII_RX_CLK = PERIOD TIMEGRP "GMII_RX_CLK" 125 MHz HIGH 50%; +-------------------------------------------------------------------------------- +Slack (hold path): 0.055ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_1 (FF) + Destination: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem21/SP (RAM) + Requirement: 0.000ns + Data Path Delay: 0.064ns (Levels of Logic = 0) + Clock Path Skew: 0.009ns (0.056 - 0.047) + Source Clock: ftop/rxclkBnd rising at 8.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_1 to ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem21/SP + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X126Y14.BQ Tcko 0.115 ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr<3> + ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_1 + SLICE_X126Y15.D2 net (fanout=6) 0.228 ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr<1> + SLICE_X126Y15.CLK Tah (-Th) 0.279 ftop/gbe0/gmac/rxRS_rxF/_n0110<6> + ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem21/SP + ------------------------------------------------- --------------------------- + Total 0.064ns (-0.164ns logic, 0.228ns route) + (-256.2% logic, 356.2% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.055ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_1 (FF) + Destination: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem22/SP (RAM) + Requirement: 0.000ns + Data Path Delay: 0.064ns (Levels of Logic = 0) + Clock Path Skew: 0.009ns (0.056 - 0.047) + Source Clock: ftop/rxclkBnd rising at 8.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_1 to ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem22/SP + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X126Y14.BQ Tcko 0.115 ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr<3> + ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_1 + SLICE_X126Y15.D2 net (fanout=6) 0.228 ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr<1> + SLICE_X126Y15.CLK Tah (-Th) 0.279 ftop/gbe0/gmac/rxRS_rxF/_n0110<6> + ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem22/SP + ------------------------------------------------- --------------------------- + Total 0.064ns (-0.164ns logic, 0.228ns route) + (-256.2% logic, 356.2% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.055ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_1 (FF) + Destination: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem21/DP (RAM) + Requirement: 0.000ns + Data Path Delay: 0.064ns (Levels of Logic = 0) + Clock Path Skew: 0.009ns (0.056 - 0.047) + Source Clock: ftop/rxclkBnd rising at 8.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_1 to ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem21/DP + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X126Y14.BQ Tcko 0.115 ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr<3> + ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_1 + SLICE_X126Y15.D2 net (fanout=6) 0.228 ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr<1> + SLICE_X126Y15.CLK Tah (-Th) 0.279 ftop/gbe0/gmac/rxRS_rxF/_n0110<6> + ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem21/DP + ------------------------------------------------- --------------------------- + Total 0.064ns (-0.164ns logic, 0.228ns route) + (-256.2% logic, 356.2% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.055ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_1 (FF) + Destination: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem22/DP (RAM) + Requirement: 0.000ns + Data Path Delay: 0.064ns (Levels of Logic = 0) + Clock Path Skew: 0.009ns (0.056 - 0.047) + Source Clock: ftop/rxclkBnd rising at 8.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_1 to ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem22/DP + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X126Y14.BQ Tcko 0.115 ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr<3> + ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_1 + SLICE_X126Y15.D2 net (fanout=6) 0.228 ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr<1> + SLICE_X126Y15.CLK Tah (-Th) 0.279 ftop/gbe0/gmac/rxRS_rxF/_n0110<6> + ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem22/DP + ------------------------------------------------- --------------------------- + Total 0.064ns (-0.164ns logic, 0.228ns route) + (-256.2% logic, 356.2% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.055ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_1 (FF) + Destination: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem23/DP (RAM) + Requirement: 0.000ns + Data Path Delay: 0.064ns (Levels of Logic = 0) + Clock Path Skew: 0.009ns (0.056 - 0.047) + Source Clock: ftop/rxclkBnd rising at 8.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_1 to ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem23/DP + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X126Y14.BQ Tcko 0.115 ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr<3> + ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_1 + SLICE_X126Y15.D2 net (fanout=6) 0.228 ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr<1> + SLICE_X126Y15.CLK Tah (-Th) 0.279 ftop/gbe0/gmac/rxRS_rxF/_n0110<6> + ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem23/DP + ------------------------------------------------- --------------------------- + Total 0.064ns (-0.164ns logic, 0.228ns route) + (-256.2% logic, 356.2% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.055ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_1 (FF) + Destination: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem24/DP (RAM) + Requirement: 0.000ns + Data Path Delay: 0.064ns (Levels of Logic = 0) + Clock Path Skew: 0.009ns (0.056 - 0.047) + Source Clock: ftop/rxclkBnd rising at 8.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_1 to ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem24/DP + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X126Y14.BQ Tcko 0.115 ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr<3> + ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_1 + SLICE_X126Y15.D2 net (fanout=6) 0.228 ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr<1> + SLICE_X126Y15.CLK Tah (-Th) 0.279 ftop/gbe0/gmac/rxRS_rxF/_n0110<6> + ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem24/DP + ------------------------------------------------- --------------------------- + Total 0.064ns (-0.164ns logic, 0.228ns route) + (-256.2% logic, 356.2% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.055ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_1 (FF) + Destination: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem23/SP (RAM) + Requirement: 0.000ns + Data Path Delay: 0.064ns (Levels of Logic = 0) + Clock Path Skew: 0.009ns (0.056 - 0.047) + Source Clock: ftop/rxclkBnd rising at 8.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_1 to ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem23/SP + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X126Y14.BQ Tcko 0.115 ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr<3> + ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_1 + SLICE_X126Y15.D2 net (fanout=6) 0.228 ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr<1> + SLICE_X126Y15.CLK Tah (-Th) 0.279 ftop/gbe0/gmac/rxRS_rxF/_n0110<6> + ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem23/SP + ------------------------------------------------- --------------------------- + Total 0.064ns (-0.164ns logic, 0.228ns route) + (-256.2% logic, 356.2% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.055ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_1 (FF) + Destination: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem24/SP (RAM) + Requirement: 0.000ns + Data Path Delay: 0.064ns (Levels of Logic = 0) + Clock Path Skew: 0.009ns (0.056 - 0.047) + Source Clock: ftop/rxclkBnd rising at 8.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_1 to ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem24/SP + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X126Y14.BQ Tcko 0.115 ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr<3> + ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_1 + SLICE_X126Y15.D2 net (fanout=6) 0.228 ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr<1> + SLICE_X126Y15.CLK Tah (-Th) 0.279 ftop/gbe0/gmac/rxRS_rxF/_n0110<6> + ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem24/SP + ------------------------------------------------- --------------------------- + Total 0.064ns (-0.164ns logic, 0.228ns route) + (-256.2% logic, 356.2% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.081ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_1 (FF) + Destination: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem1_RAMC (RAM) + Requirement: 0.000ns + Data Path Delay: 0.120ns (Levels of Logic = 0) + Clock Path Skew: 0.039ns (0.390 - 0.351) + Source Clock: ftop/rxclkBnd rising at 8.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_1 to ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem1_RAMC + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X126Y14.BQ Tcko 0.115 ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr<3> + ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_1 + SLICE_X130Y15.D2 net (fanout=6) 0.284 ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr<1> + SLICE_X130Y15.CLK Tah (-Th) 0.279 ftop/gbe0/gmac/rxRS_rxF/_n0110<5> + ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem1_RAMC + ------------------------------------------------- --------------------------- + Total 0.120ns (-0.164ns logic, 0.284ns route) + (-136.7% logic, 236.7% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.081ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_1 (FF) + Destination: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem1_RAMD (RAM) + Requirement: 0.000ns + Data Path Delay: 0.120ns (Levels of Logic = 0) + Clock Path Skew: 0.039ns (0.390 - 0.351) + Source Clock: ftop/rxclkBnd rising at 8.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_1 to ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem1_RAMD + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X126Y14.BQ Tcko 0.115 ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr<3> + ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_1 + SLICE_X130Y15.D2 net (fanout=6) 0.284 ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr<1> + SLICE_X130Y15.CLK Tah (-Th) 0.279 ftop/gbe0/gmac/rxRS_rxF/_n0110<5> + ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem1_RAMD + ------------------------------------------------- --------------------------- + Total 0.120ns (-0.164ns logic, 0.284ns route) + (-136.7% logic, 236.7% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.081ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_1 (FF) + Destination: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem1_RAMC_D1 (RAM) + Requirement: 0.000ns + Data Path Delay: 0.120ns (Levels of Logic = 0) + Clock Path Skew: 0.039ns (0.390 - 0.351) + Source Clock: ftop/rxclkBnd rising at 8.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_1 to ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem1_RAMC_D1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X126Y14.BQ Tcko 0.115 ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr<3> + ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_1 + SLICE_X130Y15.D2 net (fanout=6) 0.284 ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr<1> + SLICE_X130Y15.CLK Tah (-Th) 0.279 ftop/gbe0/gmac/rxRS_rxF/_n0110<5> + ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem1_RAMC_D1 + ------------------------------------------------- --------------------------- + Total 0.120ns (-0.164ns logic, 0.284ns route) + (-136.7% logic, 236.7% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.081ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_1 (FF) + Destination: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem1_RAMA_D1 (RAM) + Requirement: 0.000ns + Data Path Delay: 0.120ns (Levels of Logic = 0) + Clock Path Skew: 0.039ns (0.390 - 0.351) + Source Clock: ftop/rxclkBnd rising at 8.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_1 to ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem1_RAMA_D1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X126Y14.BQ Tcko 0.115 ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr<3> + ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_1 + SLICE_X130Y15.D2 net (fanout=6) 0.284 ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr<1> + SLICE_X130Y15.CLK Tah (-Th) 0.279 ftop/gbe0/gmac/rxRS_rxF/_n0110<5> + ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem1_RAMA_D1 + ------------------------------------------------- --------------------------- + Total 0.120ns (-0.164ns logic, 0.284ns route) + (-136.7% logic, 236.7% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.081ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_1 (FF) + Destination: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem1_RAMB_D1 (RAM) + Requirement: 0.000ns + Data Path Delay: 0.120ns (Levels of Logic = 0) + Clock Path Skew: 0.039ns (0.390 - 0.351) + Source Clock: ftop/rxclkBnd rising at 8.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_1 to ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem1_RAMB_D1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X126Y14.BQ Tcko 0.115 ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr<3> + ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_1 + SLICE_X130Y15.D2 net (fanout=6) 0.284 ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr<1> + SLICE_X130Y15.CLK Tah (-Th) 0.279 ftop/gbe0/gmac/rxRS_rxF/_n0110<5> + ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem1_RAMB_D1 + ------------------------------------------------- --------------------------- + Total 0.120ns (-0.164ns logic, 0.284ns route) + (-136.7% logic, 236.7% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.081ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_1 (FF) + Destination: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem1_RAMB (RAM) + Requirement: 0.000ns + Data Path Delay: 0.120ns (Levels of Logic = 0) + Clock Path Skew: 0.039ns (0.390 - 0.351) + Source Clock: ftop/rxclkBnd rising at 8.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_1 to ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem1_RAMB + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X126Y14.BQ Tcko 0.115 ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr<3> + ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_1 + SLICE_X130Y15.D2 net (fanout=6) 0.284 ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr<1> + SLICE_X130Y15.CLK Tah (-Th) 0.279 ftop/gbe0/gmac/rxRS_rxF/_n0110<5> + ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem1_RAMB + ------------------------------------------------- --------------------------- + Total 0.120ns (-0.164ns logic, 0.284ns route) + (-136.7% logic, 236.7% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.081ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_1 (FF) + Destination: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem1_RAMD_D1 (RAM) + Requirement: 0.000ns + Data Path Delay: 0.120ns (Levels of Logic = 0) + Clock Path Skew: 0.039ns (0.390 - 0.351) + Source Clock: ftop/rxclkBnd rising at 8.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_1 to ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem1_RAMD_D1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X126Y14.BQ Tcko 0.115 ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr<3> + ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_1 + SLICE_X130Y15.D2 net (fanout=6) 0.284 ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr<1> + SLICE_X130Y15.CLK Tah (-Th) 0.279 ftop/gbe0/gmac/rxRS_rxF/_n0110<5> + ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem1_RAMD_D1 + ------------------------------------------------- --------------------------- + Total 0.120ns (-0.164ns logic, 0.284ns route) + (-136.7% logic, 236.7% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.081ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_1 (FF) + Destination: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem1_RAMA (RAM) + Requirement: 0.000ns + Data Path Delay: 0.120ns (Levels of Logic = 0) + Clock Path Skew: 0.039ns (0.390 - 0.351) + Source Clock: ftop/rxclkBnd rising at 8.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_1 to ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem1_RAMA + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X126Y14.BQ Tcko 0.115 ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr<3> + ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_1 + SLICE_X130Y15.D2 net (fanout=6) 0.284 ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr<1> + SLICE_X130Y15.CLK Tah (-Th) 0.279 ftop/gbe0/gmac/rxRS_rxF/_n0110<5> + ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem1_RAMA + ------------------------------------------------- --------------------------- + Total 0.120ns (-0.164ns logic, 0.284ns route) + (-136.7% logic, 236.7% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.091ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_2 (FF) + Destination: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem1_RAMB (RAM) + Requirement: 0.000ns + Data Path Delay: 0.130ns (Levels of Logic = 0) + Clock Path Skew: 0.039ns (0.390 - 0.351) + Source Clock: ftop/rxclkBnd rising at 8.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_2 to ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem1_RAMB + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X126Y14.CQ Tcko 0.115 ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr<3> + ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_2 + SLICE_X130Y15.D3 net (fanout=6) 0.229 ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr<2> + SLICE_X130Y15.CLK Tah (-Th) 0.214 ftop/gbe0/gmac/rxRS_rxF/_n0110<5> + ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem1_RAMB + ------------------------------------------------- --------------------------- + Total 0.130ns (-0.099ns logic, 0.229ns route) + (-76.2% logic, 176.2% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.091ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_2 (FF) + Destination: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem1_RAMA (RAM) + Requirement: 0.000ns + Data Path Delay: 0.130ns (Levels of Logic = 0) + Clock Path Skew: 0.039ns (0.390 - 0.351) + Source Clock: ftop/rxclkBnd rising at 8.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_2 to ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem1_RAMA + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X126Y14.CQ Tcko 0.115 ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr<3> + ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_2 + SLICE_X130Y15.D3 net (fanout=6) 0.229 ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr<2> + SLICE_X130Y15.CLK Tah (-Th) 0.214 ftop/gbe0/gmac/rxRS_rxF/_n0110<5> + ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem1_RAMA + ------------------------------------------------- --------------------------- + Total 0.130ns (-0.099ns logic, 0.229ns route) + (-76.2% logic, 176.2% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.091ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_2 (FF) + Destination: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem1_RAMA_D1 (RAM) + Requirement: 0.000ns + Data Path Delay: 0.130ns (Levels of Logic = 0) + Clock Path Skew: 0.039ns (0.390 - 0.351) + Source Clock: ftop/rxclkBnd rising at 8.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_2 to ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem1_RAMA_D1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X126Y14.CQ Tcko 0.115 ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr<3> + ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_2 + SLICE_X130Y15.D3 net (fanout=6) 0.229 ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr<2> + SLICE_X130Y15.CLK Tah (-Th) 0.214 ftop/gbe0/gmac/rxRS_rxF/_n0110<5> + ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem1_RAMA_D1 + ------------------------------------------------- --------------------------- + Total 0.130ns (-0.099ns logic, 0.229ns route) + (-76.2% logic, 176.2% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.091ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_2 (FF) + Destination: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem1_RAMB_D1 (RAM) + Requirement: 0.000ns + Data Path Delay: 0.130ns (Levels of Logic = 0) + Clock Path Skew: 0.039ns (0.390 - 0.351) + Source Clock: ftop/rxclkBnd rising at 8.000ns + Destination Clock: ftop/rxclkBnd rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_2 to ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem1_RAMB_D1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X126Y14.CQ Tcko 0.115 ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr<3> + ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr_2 + SLICE_X130Y15.D3 net (fanout=6) 0.229 ftop/gbe0/gmac/rxRS_rxF/sGEnqPtr<2> + SLICE_X130Y15.CLK Tah (-Th) 0.214 ftop/gbe0/gmac/rxRS_rxF/_n0110<5> + ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem1_RAMB_D1 + ------------------------------------------------- --------------------------- + Total 0.130ns (-0.099ns logic, 0.229ns route) + (-76.2% logic, 176.2% route) + +-------------------------------------------------------------------------------- + +Component Switching Limit Checks: TS_GMII_RX_CLK = PERIOD TIMEGRP "GMII_RX_CLK" 125 MHz HIGH 50%; +-------------------------------------------------------------------------------- +Slack: 4.668ns (period - min period limit) + Period: 8.000ns + Min period limit: 3.332ns (300.120MHz) (Tbrper_I) + Physical resource: ftop/gbe0/gmac/rxClk_BUFR/I + Logical resource: ftop/gbe0/gmac/rxClk_BUFR/I + Location pin: BUFR_X2Y3.I + Clock network: ftop/gbe0/gmac/gmii_rxc_dly$DATAOUT +-------------------------------------------------------------------------------- +Slack: 6.000ns (period - (min low pulse limit / (low pulse / period))) + Period: 8.000ns + Low pulse: 4.000ns + Low pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/gbe0/gmac/rxRS_rxF/_n0110<6>/CLK + Logical resource: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem24/SP/CLK + Location pin: SLICE_X126Y15.CLK + Clock network: ftop/rxclkBnd +-------------------------------------------------------------------------------- +Slack: 6.000ns (period - (min high pulse limit / (high pulse / period))) + Period: 8.000ns + High pulse: 4.000ns + High pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/gbe0/gmac/rxRS_rxF/_n0110<6>/CLK + Logical resource: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem24/SP/CLK + Location pin: SLICE_X126Y15.CLK + Clock network: ftop/rxclkBnd +-------------------------------------------------------------------------------- +Slack: 6.000ns (period - (min low pulse limit / (low pulse / period))) + Period: 8.000ns + Low pulse: 4.000ns + Low pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/gbe0/gmac/rxRS_rxF/_n0110<6>/CLK + Logical resource: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem23/SP/CLK + Location pin: SLICE_X126Y15.CLK + Clock network: ftop/rxclkBnd +-------------------------------------------------------------------------------- +Slack: 6.000ns (period - (min high pulse limit / (high pulse / period))) + Period: 8.000ns + High pulse: 4.000ns + High pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/gbe0/gmac/rxRS_rxF/_n0110<6>/CLK + Logical resource: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem23/SP/CLK + Location pin: SLICE_X126Y15.CLK + Clock network: ftop/rxclkBnd +-------------------------------------------------------------------------------- +Slack: 6.000ns (period - (min low pulse limit / (low pulse / period))) + Period: 8.000ns + Low pulse: 4.000ns + Low pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/gbe0/gmac/rxRS_rxF/_n0110<6>/CLK + Logical resource: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem24/DP/CLK + Location pin: SLICE_X126Y15.CLK + Clock network: ftop/rxclkBnd +-------------------------------------------------------------------------------- +Slack: 6.000ns (period - (min high pulse limit / (high pulse / period))) + Period: 8.000ns + High pulse: 4.000ns + High pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/gbe0/gmac/rxRS_rxF/_n0110<6>/CLK + Logical resource: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem24/DP/CLK + Location pin: SLICE_X126Y15.CLK + Clock network: ftop/rxclkBnd +-------------------------------------------------------------------------------- +Slack: 6.000ns (period - (min low pulse limit / (low pulse / period))) + Period: 8.000ns + Low pulse: 4.000ns + Low pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/gbe0/gmac/rxRS_rxF/_n0110<6>/CLK + Logical resource: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem23/DP/CLK + Location pin: SLICE_X126Y15.CLK + Clock network: ftop/rxclkBnd +-------------------------------------------------------------------------------- +Slack: 6.000ns (period - (min high pulse limit / (high pulse / period))) + Period: 8.000ns + High pulse: 4.000ns + High pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/gbe0/gmac/rxRS_rxF/_n0110<6>/CLK + Logical resource: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem23/DP/CLK + Location pin: SLICE_X126Y15.CLK + Clock network: ftop/rxclkBnd +-------------------------------------------------------------------------------- +Slack: 6.000ns (period - (min low pulse limit / (low pulse / period))) + Period: 8.000ns + Low pulse: 4.000ns + Low pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/gbe0/gmac/rxRS_rxF/_n0110<6>/CLK + Logical resource: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem22/DP/CLK + Location pin: SLICE_X126Y15.CLK + Clock network: ftop/rxclkBnd +-------------------------------------------------------------------------------- +Slack: 6.000ns (period - (min high pulse limit / (high pulse / period))) + Period: 8.000ns + High pulse: 4.000ns + High pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/gbe0/gmac/rxRS_rxF/_n0110<6>/CLK + Logical resource: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem22/DP/CLK + Location pin: SLICE_X126Y15.CLK + Clock network: ftop/rxclkBnd +-------------------------------------------------------------------------------- +Slack: 6.000ns (period - (min low pulse limit / (low pulse / period))) + Period: 8.000ns + Low pulse: 4.000ns + Low pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/gbe0/gmac/rxRS_rxF/_n0110<6>/CLK + Logical resource: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem21/DP/CLK + Location pin: SLICE_X126Y15.CLK + Clock network: ftop/rxclkBnd +-------------------------------------------------------------------------------- +Slack: 6.000ns (period - (min high pulse limit / (high pulse / period))) + Period: 8.000ns + High pulse: 4.000ns + High pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/gbe0/gmac/rxRS_rxF/_n0110<6>/CLK + Logical resource: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem21/DP/CLK + Location pin: SLICE_X126Y15.CLK + Clock network: ftop/rxclkBnd +-------------------------------------------------------------------------------- +Slack: 6.000ns (period - (min low pulse limit / (low pulse / period))) + Period: 8.000ns + Low pulse: 4.000ns + Low pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/gbe0/gmac/rxRS_rxF/_n0110<6>/CLK + Logical resource: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem22/SP/CLK + Location pin: SLICE_X126Y15.CLK + Clock network: ftop/rxclkBnd +-------------------------------------------------------------------------------- +Slack: 6.000ns (period - (min high pulse limit / (high pulse / period))) + Period: 8.000ns + High pulse: 4.000ns + High pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/gbe0/gmac/rxRS_rxF/_n0110<6>/CLK + Logical resource: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem22/SP/CLK + Location pin: SLICE_X126Y15.CLK + Clock network: ftop/rxclkBnd +-------------------------------------------------------------------------------- +Slack: 6.000ns (period - (min low pulse limit / (low pulse / period))) + Period: 8.000ns + Low pulse: 4.000ns + Low pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/gbe0/gmac/rxRS_rxF/_n0110<6>/CLK + Logical resource: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem21/SP/CLK + Location pin: SLICE_X126Y15.CLK + Clock network: ftop/rxclkBnd +-------------------------------------------------------------------------------- +Slack: 6.000ns (period - (min high pulse limit / (high pulse / period))) + Period: 8.000ns + High pulse: 4.000ns + High pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/gbe0/gmac/rxRS_rxF/_n0110<6>/CLK + Logical resource: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem21/SP/CLK + Location pin: SLICE_X126Y15.CLK + Clock network: ftop/rxclkBnd +-------------------------------------------------------------------------------- +Slack: 6.000ns (period - (min low pulse limit / (low pulse / period))) + Period: 8.000ns + Low pulse: 4.000ns + Low pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/gbe0/gmac/rxRS_rxF/_n0110<5>/CLK + Logical resource: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem1_RAMA/CLK + Location pin: SLICE_X130Y15.CLK + Clock network: ftop/rxclkBnd +-------------------------------------------------------------------------------- +Slack: 6.000ns (period - (min high pulse limit / (high pulse / period))) + Period: 8.000ns + High pulse: 4.000ns + High pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/gbe0/gmac/rxRS_rxF/_n0110<5>/CLK + Logical resource: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem1_RAMA/CLK + Location pin: SLICE_X130Y15.CLK + Clock network: ftop/rxclkBnd +-------------------------------------------------------------------------------- +Slack: 6.000ns (period - (min low pulse limit / (low pulse / period))) + Period: 8.000ns + Low pulse: 4.000ns + Low pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/gbe0/gmac/rxRS_rxF/_n0110<5>/CLK + Logical resource: ftop/gbe0/gmac/rxRS_rxF/Mram_fifoMem1_RAMA_D1/CLK + Location pin: SLICE_X130Y15.CLK + Clock network: ftop/rxclkBnd +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: TS_GMII_GTX_CLK = PERIOD TIMEGRP "GMII_GTX_CLK" 125 MHz HIGH +50%; +For more information, see Period Analysis in the Timing Closure User Guide (UG612). + + 7035 paths analyzed, 691 endpoints analyzed, 0 failing endpoints + 0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors) + Minimum period is 5.800ns. +-------------------------------------------------------------------------------- +Slack (setup path): 2.200ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/txRS_txF/dDoutReg_9 (FF) + Destination: ftop/gbe0/gmac/txRS_txF/dGDeqPtr_4 (FF) + Requirement: 8.000ns + Data Path Delay: 5.710ns (Levels of Logic = 4) + Clock Path Skew: -0.055ns (0.952 - 1.007) + Source Clock: ftop/sys1_clk$O rising at 0.000ns + Destination Clock: ftop/sys1_clk$O rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/txRS_txF/dDoutReg_9 to ftop/gbe0/gmac/txRS_txF/dGDeqPtr_4 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X134Y23.BQ Tcko 0.381 ftop/gbe0/gmac/txRS_txF$dD_OUT<9> + ftop/gbe0/gmac/txRS_txF/dDoutReg_9 + SLICE_X109Y15.A6 net (fanout=1) 1.195 ftop/gbe0/gmac/txRS_txF$dD_OUT<9> + SLICE_X109Y15.A Tilo 0.068 ftop/ctop/inf/cp/rom_serverAdapter_outDataCore/tail_0_0 + ftop/gbe0/gmac/WILL_FIRE_RL_txRS_egress_Body11 + SLICE_X101Y21.B4 net (fanout=21) 0.906 ftop/gbe0/gmac/WILL_FIRE_RL_txRS_egress_Body1 + SLICE_X101Y21.B Tilo 0.068 ftop/gbe0/gmac/MUX_txRS_crc$add_1__SEL_1 + ftop/gbe0/gmac/MUX_txRS_crc$add_1__SEL_11 + SLICE_X113Y16.B4 net (fanout=11) 0.948 ftop/gbe0/gmac/MUX_txRS_crc$add_1__SEL_1 + SLICE_X113Y16.B Tilo 0.068 ftop/gbe0/gmac/txRS_txF/_n0130_inv + ftop/gbe0/gmac/txRS_txF$dDEQ + SLICE_X118Y17.A6 net (fanout=3) 0.466 ftop/gbe0/gmac/txRS_txF$dDEQ + SLICE_X118Y17.A Tilo 0.068 ftop/gbe0/gmac/txRS_txF$dEMPTY_N + ftop/gbe0/gmac/txRS_txF/dNotEmptyReg_PWR_202_o_MUX_11455_o1 + SLICE_X137Y23.CE net (fanout=3) 1.224 ftop/gbe0/gmac/txRS_txF/dNotEmptyReg_PWR_202_o_MUX_11455_o + SLICE_X137Y23.CLK Tceck 0.318 ftop/gbe0/gmac/txRS_txF/dGDeqPtr<4> + ftop/gbe0/gmac/txRS_txF/dGDeqPtr_4 + ------------------------------------------------- --------------------------- + Total 5.710ns (0.971ns logic, 4.739ns route) + (17.0% logic, 83.0% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 2.200ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/txRS_txF/dDoutReg_9 (FF) + Destination: ftop/gbe0/gmac/txRS_txF/dGDeqPtr_3 (FF) + Requirement: 8.000ns + Data Path Delay: 5.710ns (Levels of Logic = 4) + Clock Path Skew: -0.055ns (0.952 - 1.007) + Source Clock: ftop/sys1_clk$O rising at 0.000ns + Destination Clock: ftop/sys1_clk$O rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/txRS_txF/dDoutReg_9 to ftop/gbe0/gmac/txRS_txF/dGDeqPtr_3 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X134Y23.BQ Tcko 0.381 ftop/gbe0/gmac/txRS_txF$dD_OUT<9> + ftop/gbe0/gmac/txRS_txF/dDoutReg_9 + SLICE_X109Y15.A6 net (fanout=1) 1.195 ftop/gbe0/gmac/txRS_txF$dD_OUT<9> + SLICE_X109Y15.A Tilo 0.068 ftop/ctop/inf/cp/rom_serverAdapter_outDataCore/tail_0_0 + ftop/gbe0/gmac/WILL_FIRE_RL_txRS_egress_Body11 + SLICE_X101Y21.B4 net (fanout=21) 0.906 ftop/gbe0/gmac/WILL_FIRE_RL_txRS_egress_Body1 + SLICE_X101Y21.B Tilo 0.068 ftop/gbe0/gmac/MUX_txRS_crc$add_1__SEL_1 + ftop/gbe0/gmac/MUX_txRS_crc$add_1__SEL_11 + SLICE_X113Y16.B4 net (fanout=11) 0.948 ftop/gbe0/gmac/MUX_txRS_crc$add_1__SEL_1 + SLICE_X113Y16.B Tilo 0.068 ftop/gbe0/gmac/txRS_txF/_n0130_inv + ftop/gbe0/gmac/txRS_txF$dDEQ + SLICE_X118Y17.A6 net (fanout=3) 0.466 ftop/gbe0/gmac/txRS_txF$dDEQ + SLICE_X118Y17.A Tilo 0.068 ftop/gbe0/gmac/txRS_txF$dEMPTY_N + ftop/gbe0/gmac/txRS_txF/dNotEmptyReg_PWR_202_o_MUX_11455_o1 + SLICE_X137Y23.CE net (fanout=3) 1.224 ftop/gbe0/gmac/txRS_txF/dNotEmptyReg_PWR_202_o_MUX_11455_o + SLICE_X137Y23.CLK Tceck 0.318 ftop/gbe0/gmac/txRS_txF/dGDeqPtr<4> + ftop/gbe0/gmac/txRS_txF/dGDeqPtr_3 + ------------------------------------------------- --------------------------- + Total 5.710ns (0.971ns logic, 4.739ns route) + (17.0% logic, 83.0% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 2.200ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/txRS_txF/dDoutReg_9 (FF) + Destination: ftop/gbe0/gmac/txRS_txF/dGDeqPtr_1 (FF) + Requirement: 8.000ns + Data Path Delay: 5.710ns (Levels of Logic = 4) + Clock Path Skew: -0.055ns (0.952 - 1.007) + Source Clock: ftop/sys1_clk$O rising at 0.000ns + Destination Clock: ftop/sys1_clk$O rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/txRS_txF/dDoutReg_9 to ftop/gbe0/gmac/txRS_txF/dGDeqPtr_1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X134Y23.BQ Tcko 0.381 ftop/gbe0/gmac/txRS_txF$dD_OUT<9> + ftop/gbe0/gmac/txRS_txF/dDoutReg_9 + SLICE_X109Y15.A6 net (fanout=1) 1.195 ftop/gbe0/gmac/txRS_txF$dD_OUT<9> + SLICE_X109Y15.A Tilo 0.068 ftop/ctop/inf/cp/rom_serverAdapter_outDataCore/tail_0_0 + ftop/gbe0/gmac/WILL_FIRE_RL_txRS_egress_Body11 + SLICE_X101Y21.B4 net (fanout=21) 0.906 ftop/gbe0/gmac/WILL_FIRE_RL_txRS_egress_Body1 + SLICE_X101Y21.B Tilo 0.068 ftop/gbe0/gmac/MUX_txRS_crc$add_1__SEL_1 + ftop/gbe0/gmac/MUX_txRS_crc$add_1__SEL_11 + SLICE_X113Y16.B4 net (fanout=11) 0.948 ftop/gbe0/gmac/MUX_txRS_crc$add_1__SEL_1 + SLICE_X113Y16.B Tilo 0.068 ftop/gbe0/gmac/txRS_txF/_n0130_inv + ftop/gbe0/gmac/txRS_txF$dDEQ + SLICE_X118Y17.A6 net (fanout=3) 0.466 ftop/gbe0/gmac/txRS_txF$dDEQ + SLICE_X118Y17.A Tilo 0.068 ftop/gbe0/gmac/txRS_txF$dEMPTY_N + ftop/gbe0/gmac/txRS_txF/dNotEmptyReg_PWR_202_o_MUX_11455_o1 + SLICE_X137Y23.CE net (fanout=3) 1.224 ftop/gbe0/gmac/txRS_txF/dNotEmptyReg_PWR_202_o_MUX_11455_o + SLICE_X137Y23.CLK Tceck 0.318 ftop/gbe0/gmac/txRS_txF/dGDeqPtr<4> + ftop/gbe0/gmac/txRS_txF/dGDeqPtr_1 + ------------------------------------------------- --------------------------- + Total 5.710ns (0.971ns logic, 4.739ns route) + (17.0% logic, 83.0% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 2.200ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/txRS_txF/dDoutReg_9 (FF) + Destination: ftop/gbe0/gmac/txRS_txF/dGDeqPtr_2 (FF) + Requirement: 8.000ns + Data Path Delay: 5.710ns (Levels of Logic = 4) + Clock Path Skew: -0.055ns (0.952 - 1.007) + Source Clock: ftop/sys1_clk$O rising at 0.000ns + Destination Clock: ftop/sys1_clk$O rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/txRS_txF/dDoutReg_9 to ftop/gbe0/gmac/txRS_txF/dGDeqPtr_2 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X134Y23.BQ Tcko 0.381 ftop/gbe0/gmac/txRS_txF$dD_OUT<9> + ftop/gbe0/gmac/txRS_txF/dDoutReg_9 + SLICE_X109Y15.A6 net (fanout=1) 1.195 ftop/gbe0/gmac/txRS_txF$dD_OUT<9> + SLICE_X109Y15.A Tilo 0.068 ftop/ctop/inf/cp/rom_serverAdapter_outDataCore/tail_0_0 + ftop/gbe0/gmac/WILL_FIRE_RL_txRS_egress_Body11 + SLICE_X101Y21.B4 net (fanout=21) 0.906 ftop/gbe0/gmac/WILL_FIRE_RL_txRS_egress_Body1 + SLICE_X101Y21.B Tilo 0.068 ftop/gbe0/gmac/MUX_txRS_crc$add_1__SEL_1 + ftop/gbe0/gmac/MUX_txRS_crc$add_1__SEL_11 + SLICE_X113Y16.B4 net (fanout=11) 0.948 ftop/gbe0/gmac/MUX_txRS_crc$add_1__SEL_1 + SLICE_X113Y16.B Tilo 0.068 ftop/gbe0/gmac/txRS_txF/_n0130_inv + ftop/gbe0/gmac/txRS_txF$dDEQ + SLICE_X118Y17.A6 net (fanout=3) 0.466 ftop/gbe0/gmac/txRS_txF$dDEQ + SLICE_X118Y17.A Tilo 0.068 ftop/gbe0/gmac/txRS_txF$dEMPTY_N + ftop/gbe0/gmac/txRS_txF/dNotEmptyReg_PWR_202_o_MUX_11455_o1 + SLICE_X137Y23.CE net (fanout=3) 1.224 ftop/gbe0/gmac/txRS_txF/dNotEmptyReg_PWR_202_o_MUX_11455_o + SLICE_X137Y23.CLK Tceck 0.318 ftop/gbe0/gmac/txRS_txF/dGDeqPtr<4> + ftop/gbe0/gmac/txRS_txF/dGDeqPtr_2 + ------------------------------------------------- --------------------------- + Total 5.710ns (0.971ns logic, 4.739ns route) + (17.0% logic, 83.0% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 2.209ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/txRS_txF/dDoutReg_9 (FF) + Destination: ftop/gbe0/gmac/txRS_txF/dDoutReg_8 (FF) + Requirement: 8.000ns + Data Path Delay: 5.756ns (Levels of Logic = 4) + Clock Path Skew: 0.000ns + Source Clock: ftop/sys1_clk$O rising at 0.000ns + Destination Clock: ftop/sys1_clk$O rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/txRS_txF/dDoutReg_9 to ftop/gbe0/gmac/txRS_txF/dDoutReg_8 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X134Y23.BQ Tcko 0.381 ftop/gbe0/gmac/txRS_txF$dD_OUT<9> + ftop/gbe0/gmac/txRS_txF/dDoutReg_9 + SLICE_X109Y15.A6 net (fanout=1) 1.195 ftop/gbe0/gmac/txRS_txF$dD_OUT<9> + SLICE_X109Y15.A Tilo 0.068 ftop/ctop/inf/cp/rom_serverAdapter_outDataCore/tail_0_0 + ftop/gbe0/gmac/WILL_FIRE_RL_txRS_egress_Body11 + SLICE_X101Y21.B4 net (fanout=21) 0.906 ftop/gbe0/gmac/WILL_FIRE_RL_txRS_egress_Body1 + SLICE_X101Y21.B Tilo 0.068 ftop/gbe0/gmac/MUX_txRS_crc$add_1__SEL_1 + ftop/gbe0/gmac/MUX_txRS_crc$add_1__SEL_11 + SLICE_X113Y16.B4 net (fanout=11) 0.948 ftop/gbe0/gmac/MUX_txRS_crc$add_1__SEL_1 + SLICE_X113Y16.B Tilo 0.068 ftop/gbe0/gmac/txRS_txF/_n0130_inv + ftop/gbe0/gmac/txRS_txF$dDEQ + SLICE_X113Y16.C2 net (fanout=3) 0.587 ftop/gbe0/gmac/txRS_txF$dDEQ + SLICE_X113Y16.C Tilo 0.068 ftop/gbe0/gmac/txRS_txF/_n0130_inv + ftop/gbe0/gmac/txRS_txF/_n0130_inv1 + SLICE_X134Y23.CE net (fanout=3) 1.183 ftop/gbe0/gmac/txRS_txF/_n0130_inv + SLICE_X134Y23.CLK Tceck 0.284 ftop/gbe0/gmac/txRS_txF$dD_OUT<9> + ftop/gbe0/gmac/txRS_txF/dDoutReg_8 + ------------------------------------------------- --------------------------- + Total 5.756ns (0.937ns logic, 4.819ns route) + (16.3% logic, 83.7% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 2.209ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/txRS_txF/dDoutReg_9 (FF) + Destination: ftop/gbe0/gmac/txRS_txF/dDoutReg_9 (FF) + Requirement: 8.000ns + Data Path Delay: 5.756ns (Levels of Logic = 4) + Clock Path Skew: 0.000ns + Source Clock: ftop/sys1_clk$O rising at 0.000ns + Destination Clock: ftop/sys1_clk$O rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/txRS_txF/dDoutReg_9 to ftop/gbe0/gmac/txRS_txF/dDoutReg_9 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X134Y23.BQ Tcko 0.381 ftop/gbe0/gmac/txRS_txF$dD_OUT<9> + ftop/gbe0/gmac/txRS_txF/dDoutReg_9 + SLICE_X109Y15.A6 net (fanout=1) 1.195 ftop/gbe0/gmac/txRS_txF$dD_OUT<9> + SLICE_X109Y15.A Tilo 0.068 ftop/ctop/inf/cp/rom_serverAdapter_outDataCore/tail_0_0 + ftop/gbe0/gmac/WILL_FIRE_RL_txRS_egress_Body11 + SLICE_X101Y21.B4 net (fanout=21) 0.906 ftop/gbe0/gmac/WILL_FIRE_RL_txRS_egress_Body1 + SLICE_X101Y21.B Tilo 0.068 ftop/gbe0/gmac/MUX_txRS_crc$add_1__SEL_1 + ftop/gbe0/gmac/MUX_txRS_crc$add_1__SEL_11 + SLICE_X113Y16.B4 net (fanout=11) 0.948 ftop/gbe0/gmac/MUX_txRS_crc$add_1__SEL_1 + SLICE_X113Y16.B Tilo 0.068 ftop/gbe0/gmac/txRS_txF/_n0130_inv + ftop/gbe0/gmac/txRS_txF$dDEQ + SLICE_X113Y16.C2 net (fanout=3) 0.587 ftop/gbe0/gmac/txRS_txF$dDEQ + SLICE_X113Y16.C Tilo 0.068 ftop/gbe0/gmac/txRS_txF/_n0130_inv + ftop/gbe0/gmac/txRS_txF/_n0130_inv1 + SLICE_X134Y23.CE net (fanout=3) 1.183 ftop/gbe0/gmac/txRS_txF/_n0130_inv + SLICE_X134Y23.CLK Tceck 0.284 ftop/gbe0/gmac/txRS_txF$dD_OUT<9> + ftop/gbe0/gmac/txRS_txF/dDoutReg_9 + ------------------------------------------------- --------------------------- + Total 5.756ns (0.937ns logic, 4.819ns route) + (16.3% logic, 83.7% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 2.210ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/txRS_txF/dDoutReg_9 (FF) + Destination: ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_5 (FF) + Requirement: 8.000ns + Data Path Delay: 5.698ns (Levels of Logic = 4) + Clock Path Skew: -0.057ns (0.950 - 1.007) + Source Clock: ftop/sys1_clk$O rising at 0.000ns + Destination Clock: ftop/sys1_clk$O rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/txRS_txF/dDoutReg_9 to ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_5 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X134Y23.BQ Tcko 0.381 ftop/gbe0/gmac/txRS_txF$dD_OUT<9> + ftop/gbe0/gmac/txRS_txF/dDoutReg_9 + SLICE_X109Y15.A6 net (fanout=1) 1.195 ftop/gbe0/gmac/txRS_txF$dD_OUT<9> + SLICE_X109Y15.A Tilo 0.068 ftop/ctop/inf/cp/rom_serverAdapter_outDataCore/tail_0_0 + ftop/gbe0/gmac/WILL_FIRE_RL_txRS_egress_Body11 + SLICE_X101Y21.B4 net (fanout=21) 0.906 ftop/gbe0/gmac/WILL_FIRE_RL_txRS_egress_Body1 + SLICE_X101Y21.B Tilo 0.068 ftop/gbe0/gmac/MUX_txRS_crc$add_1__SEL_1 + ftop/gbe0/gmac/MUX_txRS_crc$add_1__SEL_11 + SLICE_X113Y16.B4 net (fanout=11) 0.948 ftop/gbe0/gmac/MUX_txRS_crc$add_1__SEL_1 + SLICE_X113Y16.B Tilo 0.068 ftop/gbe0/gmac/txRS_txF/_n0130_inv + ftop/gbe0/gmac/txRS_txF$dDEQ + SLICE_X118Y17.A6 net (fanout=3) 0.466 ftop/gbe0/gmac/txRS_txF$dDEQ + SLICE_X118Y17.A Tilo 0.068 ftop/gbe0/gmac/txRS_txF$dEMPTY_N + ftop/gbe0/gmac/txRS_txF/dNotEmptyReg_PWR_202_o_MUX_11455_o1 + SLICE_X136Y22.CE net (fanout=3) 1.246 ftop/gbe0/gmac/txRS_txF/dNotEmptyReg_PWR_202_o_MUX_11455_o + SLICE_X136Y22.CLK Tceck 0.284 ftop/gbe0/gmac/txRS_txF/dGDeqPtr1<5> + ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_5 + ------------------------------------------------- --------------------------- + Total 5.698ns (0.937ns logic, 4.761ns route) + (16.4% logic, 83.6% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 2.210ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/txRS_txF/dDoutReg_9 (FF) + Destination: ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_4 (FF) + Requirement: 8.000ns + Data Path Delay: 5.698ns (Levels of Logic = 4) + Clock Path Skew: -0.057ns (0.950 - 1.007) + Source Clock: ftop/sys1_clk$O rising at 0.000ns + Destination Clock: ftop/sys1_clk$O rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/txRS_txF/dDoutReg_9 to ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_4 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X134Y23.BQ Tcko 0.381 ftop/gbe0/gmac/txRS_txF$dD_OUT<9> + ftop/gbe0/gmac/txRS_txF/dDoutReg_9 + SLICE_X109Y15.A6 net (fanout=1) 1.195 ftop/gbe0/gmac/txRS_txF$dD_OUT<9> + SLICE_X109Y15.A Tilo 0.068 ftop/ctop/inf/cp/rom_serverAdapter_outDataCore/tail_0_0 + ftop/gbe0/gmac/WILL_FIRE_RL_txRS_egress_Body11 + SLICE_X101Y21.B4 net (fanout=21) 0.906 ftop/gbe0/gmac/WILL_FIRE_RL_txRS_egress_Body1 + SLICE_X101Y21.B Tilo 0.068 ftop/gbe0/gmac/MUX_txRS_crc$add_1__SEL_1 + ftop/gbe0/gmac/MUX_txRS_crc$add_1__SEL_11 + SLICE_X113Y16.B4 net (fanout=11) 0.948 ftop/gbe0/gmac/MUX_txRS_crc$add_1__SEL_1 + SLICE_X113Y16.B Tilo 0.068 ftop/gbe0/gmac/txRS_txF/_n0130_inv + ftop/gbe0/gmac/txRS_txF$dDEQ + SLICE_X118Y17.A6 net (fanout=3) 0.466 ftop/gbe0/gmac/txRS_txF$dDEQ + SLICE_X118Y17.A Tilo 0.068 ftop/gbe0/gmac/txRS_txF$dEMPTY_N + ftop/gbe0/gmac/txRS_txF/dNotEmptyReg_PWR_202_o_MUX_11455_o1 + SLICE_X136Y22.CE net (fanout=3) 1.246 ftop/gbe0/gmac/txRS_txF/dNotEmptyReg_PWR_202_o_MUX_11455_o + SLICE_X136Y22.CLK Tceck 0.284 ftop/gbe0/gmac/txRS_txF/dGDeqPtr1<5> + ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_4 + ------------------------------------------------- --------------------------- + Total 5.698ns (0.937ns logic, 4.761ns route) + (16.4% logic, 83.6% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 2.219ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/txRS_txF/dDoutReg_9 (FF) + Destination: ftop/gbe0/gmac/txRS_crc/rRemainder_13 (FF) + Requirement: 8.000ns + Data Path Delay: 5.760ns (Levels of Logic = 4) + Clock Path Skew: 0.014ns (1.021 - 1.007) + Source Clock: ftop/sys1_clk$O rising at 0.000ns + Destination Clock: ftop/sys1_clk$O rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/txRS_txF/dDoutReg_9 to ftop/gbe0/gmac/txRS_crc/rRemainder_13 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X134Y23.BQ Tcko 0.381 ftop/gbe0/gmac/txRS_txF$dD_OUT<9> + ftop/gbe0/gmac/txRS_txF/dDoutReg_9 + SLICE_X109Y15.A6 net (fanout=1) 1.195 ftop/gbe0/gmac/txRS_txF$dD_OUT<9> + SLICE_X109Y15.A Tilo 0.068 ftop/ctop/inf/cp/rom_serverAdapter_outDataCore/tail_0_0 + ftop/gbe0/gmac/WILL_FIRE_RL_txRS_egress_Body11 + SLICE_X101Y21.B4 net (fanout=21) 0.906 ftop/gbe0/gmac/WILL_FIRE_RL_txRS_egress_Body1 + SLICE_X101Y21.B Tilo 0.068 ftop/gbe0/gmac/MUX_txRS_crc$add_1__SEL_1 + ftop/gbe0/gmac/MUX_txRS_crc$add_1__SEL_11 + SLICE_X104Y3.A3 net (fanout=11) 1.406 ftop/gbe0/gmac/MUX_txRS_crc$add_1__SEL_1 + SLICE_X104Y3.A Tilo 0.068 ftop/gbe0/gmac/txRS_crc/rRemainder$EN + ftop/gbe0/gmac/txRS_crc$EN_add1 + SLICE_X104Y3.B3 net (fanout=2) 0.345 ftop/gbe0/gmac/txRS_crc$EN_add + SLICE_X104Y3.B Tilo 0.068 ftop/gbe0/gmac/txRS_crc/rRemainder$EN + ftop/gbe0/gmac/txRS_crc/rRemainder$EN11 + SLICE_X96Y6.CE net (fanout=13) 0.971 ftop/gbe0/gmac/txRS_crc/rRemainder$EN + SLICE_X96Y6.CLK Tceck 0.284 ftop/gbe0/gmac/txRS_crc/rRemainder<13> + ftop/gbe0/gmac/txRS_crc/rRemainder_13 + ------------------------------------------------- --------------------------- + Total 5.760ns (0.937ns logic, 4.823ns route) + (16.3% logic, 83.7% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 2.219ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/txRS_txF/dDoutReg_9 (FF) + Destination: ftop/gbe0/gmac/txRS_crc/rRemainder_12 (FF) + Requirement: 8.000ns + Data Path Delay: 5.760ns (Levels of Logic = 4) + Clock Path Skew: 0.014ns (1.021 - 1.007) + Source Clock: ftop/sys1_clk$O rising at 0.000ns + Destination Clock: ftop/sys1_clk$O rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/txRS_txF/dDoutReg_9 to ftop/gbe0/gmac/txRS_crc/rRemainder_12 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X134Y23.BQ Tcko 0.381 ftop/gbe0/gmac/txRS_txF$dD_OUT<9> + ftop/gbe0/gmac/txRS_txF/dDoutReg_9 + SLICE_X109Y15.A6 net (fanout=1) 1.195 ftop/gbe0/gmac/txRS_txF$dD_OUT<9> + SLICE_X109Y15.A Tilo 0.068 ftop/ctop/inf/cp/rom_serverAdapter_outDataCore/tail_0_0 + ftop/gbe0/gmac/WILL_FIRE_RL_txRS_egress_Body11 + SLICE_X101Y21.B4 net (fanout=21) 0.906 ftop/gbe0/gmac/WILL_FIRE_RL_txRS_egress_Body1 + SLICE_X101Y21.B Tilo 0.068 ftop/gbe0/gmac/MUX_txRS_crc$add_1__SEL_1 + ftop/gbe0/gmac/MUX_txRS_crc$add_1__SEL_11 + SLICE_X104Y3.A3 net (fanout=11) 1.406 ftop/gbe0/gmac/MUX_txRS_crc$add_1__SEL_1 + SLICE_X104Y3.A Tilo 0.068 ftop/gbe0/gmac/txRS_crc/rRemainder$EN + ftop/gbe0/gmac/txRS_crc$EN_add1 + SLICE_X104Y3.B3 net (fanout=2) 0.345 ftop/gbe0/gmac/txRS_crc$EN_add + SLICE_X104Y3.B Tilo 0.068 ftop/gbe0/gmac/txRS_crc/rRemainder$EN + ftop/gbe0/gmac/txRS_crc/rRemainder$EN11 + SLICE_X96Y6.CE net (fanout=13) 0.971 ftop/gbe0/gmac/txRS_crc/rRemainder$EN + SLICE_X96Y6.CLK Tceck 0.284 ftop/gbe0/gmac/txRS_crc/rRemainder<13> + ftop/gbe0/gmac/txRS_crc/rRemainder_12 + ------------------------------------------------- --------------------------- + Total 5.760ns (0.937ns logic, 4.823ns route) + (16.3% logic, 83.7% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 2.240ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/txRS_txF/dDoutReg_9 (FF) + Destination: ftop/gbe0/gmac/txRS_txF/dGDeqPtr_5 (FF) + Requirement: 8.000ns + Data Path Delay: 5.670ns (Levels of Logic = 4) + Clock Path Skew: -0.055ns (0.952 - 1.007) + Source Clock: ftop/sys1_clk$O rising at 0.000ns + Destination Clock: ftop/sys1_clk$O rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/txRS_txF/dDoutReg_9 to ftop/gbe0/gmac/txRS_txF/dGDeqPtr_5 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X134Y23.BQ Tcko 0.381 ftop/gbe0/gmac/txRS_txF$dD_OUT<9> + ftop/gbe0/gmac/txRS_txF/dDoutReg_9 + SLICE_X109Y15.A6 net (fanout=1) 1.195 ftop/gbe0/gmac/txRS_txF$dD_OUT<9> + SLICE_X109Y15.A Tilo 0.068 ftop/ctop/inf/cp/rom_serverAdapter_outDataCore/tail_0_0 + ftop/gbe0/gmac/WILL_FIRE_RL_txRS_egress_Body11 + SLICE_X101Y21.B4 net (fanout=21) 0.906 ftop/gbe0/gmac/WILL_FIRE_RL_txRS_egress_Body1 + SLICE_X101Y21.B Tilo 0.068 ftop/gbe0/gmac/MUX_txRS_crc$add_1__SEL_1 + ftop/gbe0/gmac/MUX_txRS_crc$add_1__SEL_11 + SLICE_X113Y16.B4 net (fanout=11) 0.948 ftop/gbe0/gmac/MUX_txRS_crc$add_1__SEL_1 + SLICE_X113Y16.B Tilo 0.068 ftop/gbe0/gmac/txRS_txF/_n0130_inv + ftop/gbe0/gmac/txRS_txF$dDEQ + SLICE_X118Y17.A6 net (fanout=3) 0.466 ftop/gbe0/gmac/txRS_txF$dDEQ + SLICE_X118Y17.A Tilo 0.068 ftop/gbe0/gmac/txRS_txF$dEMPTY_N + ftop/gbe0/gmac/txRS_txF/dNotEmptyReg_PWR_202_o_MUX_11455_o1 + SLICE_X137Y23.CE net (fanout=3) 1.224 ftop/gbe0/gmac/txRS_txF/dNotEmptyReg_PWR_202_o_MUX_11455_o + SLICE_X137Y23.CLK Tceck 0.278 ftop/gbe0/gmac/txRS_txF/dGDeqPtr<4> + ftop/gbe0/gmac/txRS_txF/dGDeqPtr_5 + ------------------------------------------------- --------------------------- + Total 5.670ns (0.931ns logic, 4.739ns route) + (16.4% logic, 83.6% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 2.262ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/txRS_txF/dNotEmptyReg (FF) + Destination: ftop/gbe0/gmac/txRS_txF/dDoutReg_8 (FF) + Requirement: 8.000ns + Data Path Delay: 5.643ns (Levels of Logic = 4) + Clock Path Skew: -0.060ns (0.946 - 1.006) + Source Clock: ftop/sys1_clk$O rising at 0.000ns + Destination Clock: ftop/sys1_clk$O rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/txRS_txF/dNotEmptyReg to ftop/gbe0/gmac/txRS_txF/dDoutReg_8 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X118Y17.AQ Tcko 0.381 ftop/gbe0/gmac/txRS_txF$dEMPTY_N + ftop/gbe0/gmac/txRS_txF/dNotEmptyReg + SLICE_X109Y15.A1 net (fanout=6) 1.082 ftop/gbe0/gmac/txRS_txF$dEMPTY_N + SLICE_X109Y15.A Tilo 0.068 ftop/ctop/inf/cp/rom_serverAdapter_outDataCore/tail_0_0 + ftop/gbe0/gmac/WILL_FIRE_RL_txRS_egress_Body11 + SLICE_X101Y21.B4 net (fanout=21) 0.906 ftop/gbe0/gmac/WILL_FIRE_RL_txRS_egress_Body1 + SLICE_X101Y21.B Tilo 0.068 ftop/gbe0/gmac/MUX_txRS_crc$add_1__SEL_1 + ftop/gbe0/gmac/MUX_txRS_crc$add_1__SEL_11 + SLICE_X113Y16.B4 net (fanout=11) 0.948 ftop/gbe0/gmac/MUX_txRS_crc$add_1__SEL_1 + SLICE_X113Y16.B Tilo 0.068 ftop/gbe0/gmac/txRS_txF/_n0130_inv + ftop/gbe0/gmac/txRS_txF$dDEQ + SLICE_X113Y16.C2 net (fanout=3) 0.587 ftop/gbe0/gmac/txRS_txF$dDEQ + SLICE_X113Y16.C Tilo 0.068 ftop/gbe0/gmac/txRS_txF/_n0130_inv + ftop/gbe0/gmac/txRS_txF/_n0130_inv1 + SLICE_X134Y23.CE net (fanout=3) 1.183 ftop/gbe0/gmac/txRS_txF/_n0130_inv + SLICE_X134Y23.CLK Tceck 0.284 ftop/gbe0/gmac/txRS_txF$dD_OUT<9> + ftop/gbe0/gmac/txRS_txF/dDoutReg_8 + ------------------------------------------------- --------------------------- + Total 5.643ns (0.937ns logic, 4.706ns route) + (16.6% logic, 83.4% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 2.262ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/txRS_txF/dNotEmptyReg (FF) + Destination: ftop/gbe0/gmac/txRS_txF/dDoutReg_9 (FF) + Requirement: 8.000ns + Data Path Delay: 5.643ns (Levels of Logic = 4) + Clock Path Skew: -0.060ns (0.946 - 1.006) + Source Clock: ftop/sys1_clk$O rising at 0.000ns + Destination Clock: ftop/sys1_clk$O rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/txRS_txF/dNotEmptyReg to ftop/gbe0/gmac/txRS_txF/dDoutReg_9 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X118Y17.AQ Tcko 0.381 ftop/gbe0/gmac/txRS_txF$dEMPTY_N + ftop/gbe0/gmac/txRS_txF/dNotEmptyReg + SLICE_X109Y15.A1 net (fanout=6) 1.082 ftop/gbe0/gmac/txRS_txF$dEMPTY_N + SLICE_X109Y15.A Tilo 0.068 ftop/ctop/inf/cp/rom_serverAdapter_outDataCore/tail_0_0 + ftop/gbe0/gmac/WILL_FIRE_RL_txRS_egress_Body11 + SLICE_X101Y21.B4 net (fanout=21) 0.906 ftop/gbe0/gmac/WILL_FIRE_RL_txRS_egress_Body1 + SLICE_X101Y21.B Tilo 0.068 ftop/gbe0/gmac/MUX_txRS_crc$add_1__SEL_1 + ftop/gbe0/gmac/MUX_txRS_crc$add_1__SEL_11 + SLICE_X113Y16.B4 net (fanout=11) 0.948 ftop/gbe0/gmac/MUX_txRS_crc$add_1__SEL_1 + SLICE_X113Y16.B Tilo 0.068 ftop/gbe0/gmac/txRS_txF/_n0130_inv + ftop/gbe0/gmac/txRS_txF$dDEQ + SLICE_X113Y16.C2 net (fanout=3) 0.587 ftop/gbe0/gmac/txRS_txF$dDEQ + SLICE_X113Y16.C Tilo 0.068 ftop/gbe0/gmac/txRS_txF/_n0130_inv + ftop/gbe0/gmac/txRS_txF/_n0130_inv1 + SLICE_X134Y23.CE net (fanout=3) 1.183 ftop/gbe0/gmac/txRS_txF/_n0130_inv + SLICE_X134Y23.CLK Tceck 0.284 ftop/gbe0/gmac/txRS_txF$dD_OUT<9> + ftop/gbe0/gmac/txRS_txF/dDoutReg_9 + ------------------------------------------------- --------------------------- + Total 5.643ns (0.937ns logic, 4.706ns route) + (16.6% logic, 83.4% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 2.298ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/txRS_txF/dDoutReg_9 (FF) + Destination: ftop/gbe0/gmac/txRS_crc/rRemainder_21 (FF) + Requirement: 8.000ns + Data Path Delay: 5.680ns (Levels of Logic = 4) + Clock Path Skew: 0.013ns (1.020 - 1.007) + Source Clock: ftop/sys1_clk$O rising at 0.000ns + Destination Clock: ftop/sys1_clk$O rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/txRS_txF/dDoutReg_9 to ftop/gbe0/gmac/txRS_crc/rRemainder_21 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X134Y23.BQ Tcko 0.381 ftop/gbe0/gmac/txRS_txF$dD_OUT<9> + ftop/gbe0/gmac/txRS_txF/dDoutReg_9 + SLICE_X109Y15.A6 net (fanout=1) 1.195 ftop/gbe0/gmac/txRS_txF$dD_OUT<9> + SLICE_X109Y15.A Tilo 0.068 ftop/ctop/inf/cp/rom_serverAdapter_outDataCore/tail_0_0 + ftop/gbe0/gmac/WILL_FIRE_RL_txRS_egress_Body11 + SLICE_X101Y21.B4 net (fanout=21) 0.906 ftop/gbe0/gmac/WILL_FIRE_RL_txRS_egress_Body1 + SLICE_X101Y21.B Tilo 0.068 ftop/gbe0/gmac/MUX_txRS_crc$add_1__SEL_1 + ftop/gbe0/gmac/MUX_txRS_crc$add_1__SEL_11 + SLICE_X104Y3.A3 net (fanout=11) 1.406 ftop/gbe0/gmac/MUX_txRS_crc$add_1__SEL_1 + SLICE_X104Y3.A Tilo 0.068 ftop/gbe0/gmac/txRS_crc/rRemainder$EN + ftop/gbe0/gmac/txRS_crc$EN_add1 + SLICE_X104Y3.B3 net (fanout=2) 0.345 ftop/gbe0/gmac/txRS_crc$EN_add + SLICE_X104Y3.B Tilo 0.068 ftop/gbe0/gmac/txRS_crc/rRemainder$EN + ftop/gbe0/gmac/txRS_crc/rRemainder$EN11 + SLICE_X98Y7.CE net (fanout=13) 0.857 ftop/gbe0/gmac/txRS_crc/rRemainder$EN + SLICE_X98Y7.CLK Tceck 0.318 ftop/gbe0/gmac/txRS_crc/rRemainder<21> + ftop/gbe0/gmac/txRS_crc/rRemainder_21 + ------------------------------------------------- --------------------------- + Total 5.680ns (0.971ns logic, 4.709ns route) + (17.1% logic, 82.9% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 2.298ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/txRS_txF/dDoutReg_9 (FF) + Destination: ftop/gbe0/gmac/txRS_crc/rRemainder_20 (FF) + Requirement: 8.000ns + Data Path Delay: 5.680ns (Levels of Logic = 4) + Clock Path Skew: 0.013ns (1.020 - 1.007) + Source Clock: ftop/sys1_clk$O rising at 0.000ns + Destination Clock: ftop/sys1_clk$O rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/txRS_txF/dDoutReg_9 to ftop/gbe0/gmac/txRS_crc/rRemainder_20 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X134Y23.BQ Tcko 0.381 ftop/gbe0/gmac/txRS_txF$dD_OUT<9> + ftop/gbe0/gmac/txRS_txF/dDoutReg_9 + SLICE_X109Y15.A6 net (fanout=1) 1.195 ftop/gbe0/gmac/txRS_txF$dD_OUT<9> + SLICE_X109Y15.A Tilo 0.068 ftop/ctop/inf/cp/rom_serverAdapter_outDataCore/tail_0_0 + ftop/gbe0/gmac/WILL_FIRE_RL_txRS_egress_Body11 + SLICE_X101Y21.B4 net (fanout=21) 0.906 ftop/gbe0/gmac/WILL_FIRE_RL_txRS_egress_Body1 + SLICE_X101Y21.B Tilo 0.068 ftop/gbe0/gmac/MUX_txRS_crc$add_1__SEL_1 + ftop/gbe0/gmac/MUX_txRS_crc$add_1__SEL_11 + SLICE_X104Y3.A3 net (fanout=11) 1.406 ftop/gbe0/gmac/MUX_txRS_crc$add_1__SEL_1 + SLICE_X104Y3.A Tilo 0.068 ftop/gbe0/gmac/txRS_crc/rRemainder$EN + ftop/gbe0/gmac/txRS_crc$EN_add1 + SLICE_X104Y3.B3 net (fanout=2) 0.345 ftop/gbe0/gmac/txRS_crc$EN_add + SLICE_X104Y3.B Tilo 0.068 ftop/gbe0/gmac/txRS_crc/rRemainder$EN + ftop/gbe0/gmac/txRS_crc/rRemainder$EN11 + SLICE_X98Y7.CE net (fanout=13) 0.857 ftop/gbe0/gmac/txRS_crc/rRemainder$EN + SLICE_X98Y7.CLK Tceck 0.318 ftop/gbe0/gmac/txRS_crc/rRemainder<21> + ftop/gbe0/gmac/txRS_crc/rRemainder_20 + ------------------------------------------------- --------------------------- + Total 5.680ns (0.971ns logic, 4.709ns route) + (17.1% logic, 82.9% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 2.314ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/txRS_txF/dNotEmptyReg (FF) + Destination: ftop/gbe0/gmac/txRS_txF/dGDeqPtr_1 (FF) + Requirement: 8.000ns + Data Path Delay: 5.597ns (Levels of Logic = 4) + Clock Path Skew: -0.054ns (0.952 - 1.006) + Source Clock: ftop/sys1_clk$O rising at 0.000ns + Destination Clock: ftop/sys1_clk$O rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/txRS_txF/dNotEmptyReg to ftop/gbe0/gmac/txRS_txF/dGDeqPtr_1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X118Y17.AQ Tcko 0.381 ftop/gbe0/gmac/txRS_txF$dEMPTY_N + ftop/gbe0/gmac/txRS_txF/dNotEmptyReg + SLICE_X109Y15.A1 net (fanout=6) 1.082 ftop/gbe0/gmac/txRS_txF$dEMPTY_N + SLICE_X109Y15.A Tilo 0.068 ftop/ctop/inf/cp/rom_serverAdapter_outDataCore/tail_0_0 + ftop/gbe0/gmac/WILL_FIRE_RL_txRS_egress_Body11 + SLICE_X101Y21.B4 net (fanout=21) 0.906 ftop/gbe0/gmac/WILL_FIRE_RL_txRS_egress_Body1 + SLICE_X101Y21.B Tilo 0.068 ftop/gbe0/gmac/MUX_txRS_crc$add_1__SEL_1 + ftop/gbe0/gmac/MUX_txRS_crc$add_1__SEL_11 + SLICE_X113Y16.B4 net (fanout=11) 0.948 ftop/gbe0/gmac/MUX_txRS_crc$add_1__SEL_1 + SLICE_X113Y16.B Tilo 0.068 ftop/gbe0/gmac/txRS_txF/_n0130_inv + ftop/gbe0/gmac/txRS_txF$dDEQ + SLICE_X118Y17.A6 net (fanout=3) 0.466 ftop/gbe0/gmac/txRS_txF$dDEQ + SLICE_X118Y17.A Tilo 0.068 ftop/gbe0/gmac/txRS_txF$dEMPTY_N + ftop/gbe0/gmac/txRS_txF/dNotEmptyReg_PWR_202_o_MUX_11455_o1 + SLICE_X137Y23.CE net (fanout=3) 1.224 ftop/gbe0/gmac/txRS_txF/dNotEmptyReg_PWR_202_o_MUX_11455_o + SLICE_X137Y23.CLK Tceck 0.318 ftop/gbe0/gmac/txRS_txF/dGDeqPtr<4> + ftop/gbe0/gmac/txRS_txF/dGDeqPtr_1 + ------------------------------------------------- --------------------------- + Total 5.597ns (0.971ns logic, 4.626ns route) + (17.3% logic, 82.7% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 2.314ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/txRS_txF/dNotEmptyReg (FF) + Destination: ftop/gbe0/gmac/txRS_txF/dGDeqPtr_3 (FF) + Requirement: 8.000ns + Data Path Delay: 5.597ns (Levels of Logic = 4) + Clock Path Skew: -0.054ns (0.952 - 1.006) + Source Clock: ftop/sys1_clk$O rising at 0.000ns + Destination Clock: ftop/sys1_clk$O rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/txRS_txF/dNotEmptyReg to ftop/gbe0/gmac/txRS_txF/dGDeqPtr_3 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X118Y17.AQ Tcko 0.381 ftop/gbe0/gmac/txRS_txF$dEMPTY_N + ftop/gbe0/gmac/txRS_txF/dNotEmptyReg + SLICE_X109Y15.A1 net (fanout=6) 1.082 ftop/gbe0/gmac/txRS_txF$dEMPTY_N + SLICE_X109Y15.A Tilo 0.068 ftop/ctop/inf/cp/rom_serverAdapter_outDataCore/tail_0_0 + ftop/gbe0/gmac/WILL_FIRE_RL_txRS_egress_Body11 + SLICE_X101Y21.B4 net (fanout=21) 0.906 ftop/gbe0/gmac/WILL_FIRE_RL_txRS_egress_Body1 + SLICE_X101Y21.B Tilo 0.068 ftop/gbe0/gmac/MUX_txRS_crc$add_1__SEL_1 + ftop/gbe0/gmac/MUX_txRS_crc$add_1__SEL_11 + SLICE_X113Y16.B4 net (fanout=11) 0.948 ftop/gbe0/gmac/MUX_txRS_crc$add_1__SEL_1 + SLICE_X113Y16.B Tilo 0.068 ftop/gbe0/gmac/txRS_txF/_n0130_inv + ftop/gbe0/gmac/txRS_txF$dDEQ + SLICE_X118Y17.A6 net (fanout=3) 0.466 ftop/gbe0/gmac/txRS_txF$dDEQ + SLICE_X118Y17.A Tilo 0.068 ftop/gbe0/gmac/txRS_txF$dEMPTY_N + ftop/gbe0/gmac/txRS_txF/dNotEmptyReg_PWR_202_o_MUX_11455_o1 + SLICE_X137Y23.CE net (fanout=3) 1.224 ftop/gbe0/gmac/txRS_txF/dNotEmptyReg_PWR_202_o_MUX_11455_o + SLICE_X137Y23.CLK Tceck 0.318 ftop/gbe0/gmac/txRS_txF/dGDeqPtr<4> + ftop/gbe0/gmac/txRS_txF/dGDeqPtr_3 + ------------------------------------------------- --------------------------- + Total 5.597ns (0.971ns logic, 4.626ns route) + (17.3% logic, 82.7% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 2.314ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/txRS_txF/dNotEmptyReg (FF) + Destination: ftop/gbe0/gmac/txRS_txF/dGDeqPtr_4 (FF) + Requirement: 8.000ns + Data Path Delay: 5.597ns (Levels of Logic = 4) + Clock Path Skew: -0.054ns (0.952 - 1.006) + Source Clock: ftop/sys1_clk$O rising at 0.000ns + Destination Clock: ftop/sys1_clk$O rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/txRS_txF/dNotEmptyReg to ftop/gbe0/gmac/txRS_txF/dGDeqPtr_4 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X118Y17.AQ Tcko 0.381 ftop/gbe0/gmac/txRS_txF$dEMPTY_N + ftop/gbe0/gmac/txRS_txF/dNotEmptyReg + SLICE_X109Y15.A1 net (fanout=6) 1.082 ftop/gbe0/gmac/txRS_txF$dEMPTY_N + SLICE_X109Y15.A Tilo 0.068 ftop/ctop/inf/cp/rom_serverAdapter_outDataCore/tail_0_0 + ftop/gbe0/gmac/WILL_FIRE_RL_txRS_egress_Body11 + SLICE_X101Y21.B4 net (fanout=21) 0.906 ftop/gbe0/gmac/WILL_FIRE_RL_txRS_egress_Body1 + SLICE_X101Y21.B Tilo 0.068 ftop/gbe0/gmac/MUX_txRS_crc$add_1__SEL_1 + ftop/gbe0/gmac/MUX_txRS_crc$add_1__SEL_11 + SLICE_X113Y16.B4 net (fanout=11) 0.948 ftop/gbe0/gmac/MUX_txRS_crc$add_1__SEL_1 + SLICE_X113Y16.B Tilo 0.068 ftop/gbe0/gmac/txRS_txF/_n0130_inv + ftop/gbe0/gmac/txRS_txF$dDEQ + SLICE_X118Y17.A6 net (fanout=3) 0.466 ftop/gbe0/gmac/txRS_txF$dDEQ + SLICE_X118Y17.A Tilo 0.068 ftop/gbe0/gmac/txRS_txF$dEMPTY_N + ftop/gbe0/gmac/txRS_txF/dNotEmptyReg_PWR_202_o_MUX_11455_o1 + SLICE_X137Y23.CE net (fanout=3) 1.224 ftop/gbe0/gmac/txRS_txF/dNotEmptyReg_PWR_202_o_MUX_11455_o + SLICE_X137Y23.CLK Tceck 0.318 ftop/gbe0/gmac/txRS_txF/dGDeqPtr<4> + ftop/gbe0/gmac/txRS_txF/dGDeqPtr_4 + ------------------------------------------------- --------------------------- + Total 5.597ns (0.971ns logic, 4.626ns route) + (17.3% logic, 82.7% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 2.314ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/txRS_txF/dNotEmptyReg (FF) + Destination: ftop/gbe0/gmac/txRS_txF/dGDeqPtr_2 (FF) + Requirement: 8.000ns + Data Path Delay: 5.597ns (Levels of Logic = 4) + Clock Path Skew: -0.054ns (0.952 - 1.006) + Source Clock: ftop/sys1_clk$O rising at 0.000ns + Destination Clock: ftop/sys1_clk$O rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/txRS_txF/dNotEmptyReg to ftop/gbe0/gmac/txRS_txF/dGDeqPtr_2 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X118Y17.AQ Tcko 0.381 ftop/gbe0/gmac/txRS_txF$dEMPTY_N + ftop/gbe0/gmac/txRS_txF/dNotEmptyReg + SLICE_X109Y15.A1 net (fanout=6) 1.082 ftop/gbe0/gmac/txRS_txF$dEMPTY_N + SLICE_X109Y15.A Tilo 0.068 ftop/ctop/inf/cp/rom_serverAdapter_outDataCore/tail_0_0 + ftop/gbe0/gmac/WILL_FIRE_RL_txRS_egress_Body11 + SLICE_X101Y21.B4 net (fanout=21) 0.906 ftop/gbe0/gmac/WILL_FIRE_RL_txRS_egress_Body1 + SLICE_X101Y21.B Tilo 0.068 ftop/gbe0/gmac/MUX_txRS_crc$add_1__SEL_1 + ftop/gbe0/gmac/MUX_txRS_crc$add_1__SEL_11 + SLICE_X113Y16.B4 net (fanout=11) 0.948 ftop/gbe0/gmac/MUX_txRS_crc$add_1__SEL_1 + SLICE_X113Y16.B Tilo 0.068 ftop/gbe0/gmac/txRS_txF/_n0130_inv + ftop/gbe0/gmac/txRS_txF$dDEQ + SLICE_X118Y17.A6 net (fanout=3) 0.466 ftop/gbe0/gmac/txRS_txF$dDEQ + SLICE_X118Y17.A Tilo 0.068 ftop/gbe0/gmac/txRS_txF$dEMPTY_N + ftop/gbe0/gmac/txRS_txF/dNotEmptyReg_PWR_202_o_MUX_11455_o1 + SLICE_X137Y23.CE net (fanout=3) 1.224 ftop/gbe0/gmac/txRS_txF/dNotEmptyReg_PWR_202_o_MUX_11455_o + SLICE_X137Y23.CLK Tceck 0.318 ftop/gbe0/gmac/txRS_txF/dGDeqPtr<4> + ftop/gbe0/gmac/txRS_txF/dGDeqPtr_2 + ------------------------------------------------- --------------------------- + Total 5.597ns (0.971ns logic, 4.626ns route) + (17.3% logic, 82.7% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 2.317ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/txRS_txF/dDoutReg_9 (FF) + Destination: ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_3 (FF) + Requirement: 8.000ns + Data Path Delay: 5.591ns (Levels of Logic = 4) + Clock Path Skew: -0.057ns (0.950 - 1.007) + Source Clock: ftop/sys1_clk$O rising at 0.000ns + Destination Clock: ftop/sys1_clk$O rising at 8.000ns + Clock Uncertainty: 0.035ns + + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/gbe0/gmac/txRS_txF/dDoutReg_9 to ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_3 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X134Y23.BQ Tcko 0.381 ftop/gbe0/gmac/txRS_txF$dD_OUT<9> + ftop/gbe0/gmac/txRS_txF/dDoutReg_9 + SLICE_X109Y15.A6 net (fanout=1) 1.195 ftop/gbe0/gmac/txRS_txF$dD_OUT<9> + SLICE_X109Y15.A Tilo 0.068 ftop/ctop/inf/cp/rom_serverAdapter_outDataCore/tail_0_0 + ftop/gbe0/gmac/WILL_FIRE_RL_txRS_egress_Body11 + SLICE_X101Y21.B4 net (fanout=21) 0.906 ftop/gbe0/gmac/WILL_FIRE_RL_txRS_egress_Body1 + SLICE_X101Y21.B Tilo 0.068 ftop/gbe0/gmac/MUX_txRS_crc$add_1__SEL_1 + ftop/gbe0/gmac/MUX_txRS_crc$add_1__SEL_11 + SLICE_X113Y16.B4 net (fanout=11) 0.948 ftop/gbe0/gmac/MUX_txRS_crc$add_1__SEL_1 + SLICE_X113Y16.B Tilo 0.068 ftop/gbe0/gmac/txRS_txF/_n0130_inv + ftop/gbe0/gmac/txRS_txF$dDEQ + SLICE_X118Y17.A6 net (fanout=3) 0.466 ftop/gbe0/gmac/txRS_txF$dDEQ + SLICE_X118Y17.A Tilo 0.068 ftop/gbe0/gmac/txRS_txF$dEMPTY_N + ftop/gbe0/gmac/txRS_txF/dNotEmptyReg_PWR_202_o_MUX_11455_o1 + SLICE_X137Y22.CE net (fanout=3) 1.105 ftop/gbe0/gmac/txRS_txF/dNotEmptyReg_PWR_202_o_MUX_11455_o + SLICE_X137Y22.CLK Tceck 0.318 ftop/gbe0/gmac/txRS_txF/dGDeqPtr1<3> + ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_3 + ------------------------------------------------- --------------------------- + Total 5.591ns (0.971ns logic, 4.620ns route) + (17.4% logic, 82.6% route) + +-------------------------------------------------------------------------------- + +Hold Paths: TS_GMII_GTX_CLK = PERIOD TIMEGRP "GMII_GTX_CLK" 125 MHz HIGH 50%; +-------------------------------------------------------------------------------- +Slack (hold path): 0.072ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_1 (FF) + Destination: ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_5 (FF) + Requirement: 0.000ns + Data Path Delay: 0.081ns (Levels of Logic = 1) + Clock Path Skew: 0.009ns (0.053 - 0.044) + Source Clock: ftop/sys1_clk$O rising at 8.000ns + Destination Clock: ftop/sys1_clk$O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_1 to ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_5 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X137Y22.BQ Tcko 0.098 ftop/gbe0/gmac/txRS_txF/dGDeqPtr1<3> + ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_1 + SLICE_X136Y22.D6 net (fanout=6) 0.060 ftop/gbe0/gmac/txRS_txF/dGDeqPtr1<1> + SLICE_X136Y22.CLK Tah (-Th) 0.077 ftop/gbe0/gmac/txRS_txF/dGDeqPtr1<5> + ftop/gbe0/gmac/txRS_txF/dGDeqPtr1[0]_dGDeqPtr1[5]_xor_27_OUT<4>1 + ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_5 + ------------------------------------------------- --------------------------- + Total 0.081ns (0.021ns logic, 0.060ns route) + (25.9% logic, 74.1% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.087ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/txRS_preambleCnt_value_3 (FF) + Destination: ftop/gbe0/gmac/txRS_preambleCnt_value_4 (FF) + Requirement: 0.000ns + Data Path Delay: 0.096ns (Levels of Logic = 1) + Clock Path Skew: 0.009ns (0.050 - 0.041) + Source Clock: ftop/sys1_clk$O rising at 8.000ns + Destination Clock: ftop/sys1_clk$O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/txRS_preambleCnt_value_3 to ftop/gbe0/gmac/txRS_preambleCnt_value_4 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X98Y20.DQ Tcko 0.098 ftop/gbe0/gmac/txRS_preambleCnt_value<3> + ftop/gbe0/gmac/txRS_preambleCnt_value_3 + SLICE_X99Y20.C6 net (fanout=11) 0.054 ftop/gbe0/gmac/txRS_preambleCnt_value<3> + SLICE_X99Y20.CLK Tah (-Th) 0.056 ftop/gbe0/gmac/txRS_preambleCnt_value<4> + ftop/gbe0/gmac/Mcount_txRS_preambleCnt_value_xor<4>11 + ftop/gbe0/gmac/txRS_preambleCnt_value_4 + ------------------------------------------------- --------------------------- + Total 0.096ns (0.042ns logic, 0.054ns route) + (43.8% logic, 56.2% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.091ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/txRS_txF/dSyncReg1_4 (FF) + Destination: ftop/gbe0/gmac/txRS_txF/dEnqPtr_4 (FF) + Requirement: 0.000ns + Data Path Delay: 0.101ns (Levels of Logic = 0) + Clock Path Skew: 0.010ns (0.057 - 0.047) + Source Clock: ftop/sys1_clk$O rising at 8.000ns + Destination Clock: ftop/sys1_clk$O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/txRS_txF/dSyncReg1_4 to ftop/gbe0/gmac/txRS_txF/dEnqPtr_4 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X139Y25.AQ Tcko 0.098 ftop/gbe0/gmac/txRS_txF/dSyncReg1<4> + ftop/gbe0/gmac/txRS_txF/dSyncReg1_4 + SLICE_X138Y25.DX net (fanout=1) 0.092 ftop/gbe0/gmac/txRS_txF/dSyncReg1<4> + SLICE_X138Y25.CLK Tckdi (-Th) 0.089 ftop/gbe0/gmac/txRS_txF/dEnqPtr<4> + ftop/gbe0/gmac/txRS_txF/dEnqPtr_4 + ------------------------------------------------- --------------------------- + Total 0.101ns (0.009ns logic, 0.092ns route) + (8.9% logic, 91.1% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.091ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/txRS_txRst/reset_hold_0 (FF) + Destination: ftop/gbe0/gmac/txRS_txRst/reset_hold_1 (FF) + Requirement: 0.000ns + Data Path Delay: 0.091ns (Levels of Logic = 1) + Clock Path Skew: 0.000ns + Source Clock: ftop/sys1_clk$O rising at 8.000ns + Destination Clock: ftop/sys1_clk$O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/txRS_txRst/reset_hold_0 to ftop/gbe0/gmac/txRS_txRst/reset_hold_1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X98Y24.AQ Tcko 0.098 ftop/gbe0/gmac/txRS_txRst/reset_hold<0> + ftop/gbe0/gmac/txRS_txRst/reset_hold_0 + SLICE_X98Y24.A5 net (fanout=1) 0.075 ftop/gbe0/gmac/txRS_txRst/reset_hold<0> + SLICE_X98Y24.CLK Tah (-Th) 0.082 ftop/gbe0/gmac/txRS_txRst/reset_hold<0> + ftop/gbe0/gmac/txRS_txRst/reset_hold<0>_rt + ftop/gbe0/gmac/txRS_txRst/reset_hold_1 + ------------------------------------------------- --------------------------- + Total 0.091ns (0.016ns logic, 0.075ns route) + (17.6% logic, 82.4% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.102ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/txRS_ifgCnt_value_1 (FF) + Destination: ftop/gbe0/gmac/txRS_ifgCnt_value_3 (FF) + Requirement: 0.000ns + Data Path Delay: 0.113ns (Levels of Logic = 1) + Clock Path Skew: 0.011ns (0.061 - 0.050) + Source Clock: ftop/sys1_clk$O rising at 8.000ns + Destination Clock: ftop/sys1_clk$O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/txRS_ifgCnt_value_1 to ftop/gbe0/gmac/txRS_ifgCnt_value_3 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X100Y11.BQ Tcko 0.115 ftop/gbe0/gmac/txRS_ifgCnt_value<2> + ftop/gbe0/gmac/txRS_ifgCnt_value_1 + SLICE_X101Y11.A6 net (fanout=4) 0.053 ftop/gbe0/gmac/txRS_ifgCnt_value<1> + SLICE_X101Y11.CLK Tah (-Th) 0.055 ftop/gbe0/gmac/txRS_ifgCnt_value<3> + ftop/gbe0/gmac/Mcount_txRS_ifgCnt_value_xor<3>11 + ftop/gbe0/gmac/txRS_ifgCnt_value_3 + ------------------------------------------------- --------------------------- + Total 0.113ns (0.060ns logic, 0.053ns route) + (53.1% logic, 46.9% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.109ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/txRS_ifgCnt_value_3 (FF) + Destination: ftop/gbe0/gmac/txRS_ifgCnt_value_3 (FF) + Requirement: 0.000ns + Data Path Delay: 0.109ns (Levels of Logic = 1) + Clock Path Skew: 0.000ns + Source Clock: ftop/sys1_clk$O rising at 8.000ns + Destination Clock: ftop/sys1_clk$O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/txRS_ifgCnt_value_3 to ftop/gbe0/gmac/txRS_ifgCnt_value_3 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X101Y11.AQ Tcko 0.098 ftop/gbe0/gmac/txRS_ifgCnt_value<3> + ftop/gbe0/gmac/txRS_ifgCnt_value_3 + SLICE_X101Y11.A5 net (fanout=2) 0.066 ftop/gbe0/gmac/txRS_ifgCnt_value<3> + SLICE_X101Y11.CLK Tah (-Th) 0.055 ftop/gbe0/gmac/txRS_ifgCnt_value<3> + ftop/gbe0/gmac/Mcount_txRS_ifgCnt_value_xor<3>11 + ftop/gbe0/gmac/txRS_ifgCnt_value_3 + ------------------------------------------------- --------------------------- + Total 0.109ns (0.043ns logic, 0.066ns route) + (39.4% logic, 60.6% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.111ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_4 (FF) + Destination: ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_4 (FF) + Requirement: 0.000ns + Data Path Delay: 0.111ns (Levels of Logic = 1) + Clock Path Skew: 0.000ns + Source Clock: ftop/sys1_clk$O rising at 8.000ns + Destination Clock: ftop/sys1_clk$O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_4 to ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_4 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X136Y22.CQ Tcko 0.115 ftop/gbe0/gmac/txRS_txF/dGDeqPtr1<5> + ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_4 + SLICE_X136Y22.C5 net (fanout=2) 0.072 ftop/gbe0/gmac/txRS_txF/dGDeqPtr1<4> + SLICE_X136Y22.CLK Tah (-Th) 0.076 ftop/gbe0/gmac/txRS_txF/dGDeqPtr1<5> + ftop/gbe0/gmac/txRS_txF/dGDeqPtr1[0]_dGDeqPtr1[5]_xor_27_OUT<3>1 + ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_4 + ------------------------------------------------- --------------------------- + Total 0.111ns (0.039ns logic, 0.072ns route) + (35.1% logic, 64.9% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.112ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_3 (FF) + Destination: ftop/gbe0/gmac/txRS_txF/dGDeqPtr_3 (FF) + Requirement: 0.000ns + Data Path Delay: 0.123ns (Levels of Logic = 0) + Clock Path Skew: 0.011ns (0.055 - 0.044) + Source Clock: ftop/sys1_clk$O rising at 8.000ns + Destination Clock: ftop/sys1_clk$O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_3 to ftop/gbe0/gmac/txRS_txF/dGDeqPtr_3 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X137Y22.DQ Tcko 0.098 ftop/gbe0/gmac/txRS_txF/dGDeqPtr1<3> + ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_3 + SLICE_X137Y23.CX net (fanout=4) 0.101 ftop/gbe0/gmac/txRS_txF/dGDeqPtr1<3> + SLICE_X137Y23.CLK Tckdi (-Th) 0.076 ftop/gbe0/gmac/txRS_txF/dGDeqPtr<4> + ftop/gbe0/gmac/txRS_txF/dGDeqPtr_3 + ------------------------------------------------- --------------------------- + Total 0.123ns (0.022ns logic, 0.101ns route) + (17.9% logic, 82.1% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.116ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/txRS_txF/dNotEmptyReg (FF) + Destination: ftop/gbe0/gmac/txRS_txF/dNotEmptyReg (FF) + Requirement: 0.000ns + Data Path Delay: 0.116ns (Levels of Logic = 1) + Clock Path Skew: 0.000ns + Source Clock: ftop/sys1_clk$O rising at 8.000ns + Destination Clock: ftop/sys1_clk$O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/txRS_txF/dNotEmptyReg to ftop/gbe0/gmac/txRS_txF/dNotEmptyReg + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X118Y17.AQ Tcko 0.115 ftop/gbe0/gmac/txRS_txF$dEMPTY_N + ftop/gbe0/gmac/txRS_txF/dNotEmptyReg + SLICE_X118Y17.A5 net (fanout=6) 0.077 ftop/gbe0/gmac/txRS_txF$dEMPTY_N + SLICE_X118Y17.CLK Tah (-Th) 0.076 ftop/gbe0/gmac/txRS_txF$dEMPTY_N + ftop/gbe0/gmac/txRS_txF/dNotEmptyReg_PWR_202_o_MUX_11455_o1 + ftop/gbe0/gmac/txRS_txF/dNotEmptyReg + ------------------------------------------------- --------------------------- + Total 0.116ns (0.039ns logic, 0.077ns route) + (33.6% logic, 66.4% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.116ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/txRS_ifgCnt_value_2 (FF) + Destination: ftop/gbe0/gmac/txRS_ifgCnt_value_2 (FF) + Requirement: 0.000ns + Data Path Delay: 0.116ns (Levels of Logic = 1) + Clock Path Skew: 0.000ns + Source Clock: ftop/sys1_clk$O rising at 8.000ns + Destination Clock: ftop/sys1_clk$O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/txRS_ifgCnt_value_2 to ftop/gbe0/gmac/txRS_ifgCnt_value_2 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X100Y11.CQ Tcko 0.115 ftop/gbe0/gmac/txRS_ifgCnt_value<2> + ftop/gbe0/gmac/txRS_ifgCnt_value_2 + SLICE_X100Y11.C5 net (fanout=3) 0.077 ftop/gbe0/gmac/txRS_ifgCnt_value<2> + SLICE_X100Y11.CLK Tah (-Th) 0.076 ftop/gbe0/gmac/txRS_ifgCnt_value<2> + ftop/gbe0/gmac/Mcount_txRS_ifgCnt_value_xor<2>11 + ftop/gbe0/gmac/txRS_ifgCnt_value_2 + ------------------------------------------------- --------------------------- + Total 0.116ns (0.039ns logic, 0.077ns route) + (33.6% logic, 66.4% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.122ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_2 (FF) + Destination: ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_2 (FF) + Requirement: 0.000ns + Data Path Delay: 0.122ns (Levels of Logic = 1) + Clock Path Skew: 0.000ns + Source Clock: ftop/sys1_clk$O rising at 8.000ns + Destination Clock: ftop/sys1_clk$O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_2 to ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_2 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X137Y22.CQ Tcko 0.098 ftop/gbe0/gmac/txRS_txF/dGDeqPtr1<3> + ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_2 + SLICE_X137Y22.C5 net (fanout=5) 0.080 ftop/gbe0/gmac/txRS_txF/dGDeqPtr1<2> + SLICE_X137Y22.CLK Tah (-Th) 0.056 ftop/gbe0/gmac/txRS_txF/dGDeqPtr1<3> + ftop/gbe0/gmac/txRS_txF/Mxor_dGDeqPtr1[0]_dGDeqPtr1[5]_xor_27_OUT_1_xo<0>1 + ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_2 + ------------------------------------------------- --------------------------- + Total 0.122ns (0.042ns logic, 0.080ns route) + (34.4% logic, 65.6% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.122ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_1 (FF) + Destination: ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_4 (FF) + Requirement: 0.000ns + Data Path Delay: 0.131ns (Levels of Logic = 1) + Clock Path Skew: 0.009ns (0.053 - 0.044) + Source Clock: ftop/sys1_clk$O rising at 8.000ns + Destination Clock: ftop/sys1_clk$O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_1 to ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_4 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X137Y22.BQ Tcko 0.098 ftop/gbe0/gmac/txRS_txF/dGDeqPtr1<3> + ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_1 + SLICE_X136Y22.C6 net (fanout=6) 0.109 ftop/gbe0/gmac/txRS_txF/dGDeqPtr1<1> + SLICE_X136Y22.CLK Tah (-Th) 0.076 ftop/gbe0/gmac/txRS_txF/dGDeqPtr1<5> + ftop/gbe0/gmac/txRS_txF/dGDeqPtr1[0]_dGDeqPtr1[5]_xor_27_OUT<3>1 + ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_4 + ------------------------------------------------- --------------------------- + Total 0.131ns (0.022ns logic, 0.109ns route) + (16.8% logic, 83.2% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.122ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/txRS_isSOF (FF) + Destination: ftop/gbe0/gmac/txRS_isSOF (FF) + Requirement: 0.000ns + Data Path Delay: 0.122ns (Levels of Logic = 1) + Clock Path Skew: 0.000ns + Source Clock: ftop/sys1_clk$O rising at 8.000ns + Destination Clock: ftop/sys1_clk$O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/txRS_isSOF to ftop/gbe0/gmac/txRS_isSOF + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X104Y12.AQ Tcko 0.115 ftop/gbe0/gmac/txRS_isSOF + ftop/gbe0/gmac/txRS_isSOF + SLICE_X104Y12.A5 net (fanout=10) 0.083 ftop/gbe0/gmac/txRS_isSOF + SLICE_X104Y12.CLK Tah (-Th) 0.076 ftop/gbe0/gmac/txRS_isSOF + ftop/gbe0/gmac/txRS_isSOF$D_IN1 + ftop/gbe0/gmac/txRS_isSOF + ------------------------------------------------- --------------------------- + Total 0.122ns (0.039ns logic, 0.083ns route) + (32.0% logic, 68.0% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.123ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/txRS_crc/rRemainder_26 (FF) + Destination: ftop/gbe0/gmac/txRS_crc/rRemainder_25 (FF) + Requirement: 0.000ns + Data Path Delay: 0.123ns (Levels of Logic = 1) + Clock Path Skew: 0.000ns + Source Clock: ftop/sys1_clk$O rising at 8.000ns + Destination Clock: ftop/sys1_clk$O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/txRS_crc/rRemainder_26 to ftop/gbe0/gmac/txRS_crc/rRemainder_25 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X97Y4.CQ Tcko 0.098 ftop/gbe0/gmac/txRS_crc/rRemainder<27> + ftop/gbe0/gmac/txRS_crc/rRemainder_26 + SLICE_X97Y4.B5 net (fanout=15) 0.082 ftop/gbe0/gmac/txRS_crc/rRemainder<26> + SLICE_X97Y4.CLK Tah (-Th) 0.057 ftop/gbe0/gmac/txRS_crc/rRemainder<27> + ftop/gbe0/gmac/txRS_crc/rRemainder$D_IN<25>1 + ftop/gbe0/gmac/txRS_crc/rRemainder_25 + ------------------------------------------------- --------------------------- + Total 0.123ns (0.041ns logic, 0.082ns route) + (33.3% logic, 66.7% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.124ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/txRS_crc/rRemainder_14 (FF) + Destination: ftop/gbe0/gmac/txRS_crc/rRemainder_22 (FF) + Requirement: 0.000ns + Data Path Delay: 0.136ns (Levels of Logic = 1) + Clock Path Skew: 0.012ns (0.066 - 0.054) + Source Clock: ftop/sys1_clk$O rising at 8.000ns + Destination Clock: ftop/sys1_clk$O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/txRS_crc/rRemainder_14 to ftop/gbe0/gmac/txRS_crc/rRemainder_22 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X100Y1.AQ Tcko 0.115 ftop/gbe0/gmac/txRS_crc/rRemainder<16> + ftop/gbe0/gmac/txRS_crc/rRemainder_14 + SLICE_X100Y2.B6 net (fanout=2) 0.098 ftop/gbe0/gmac/txRS_crc/rRemainder<14> + SLICE_X100Y2.CLK Tah (-Th) 0.077 ftop/gbe0/gmac/txRS_crc/rRemainder<24> + ftop/gbe0/gmac/txRS_crc/rRemainder$D_IN<22>1 + ftop/gbe0/gmac/txRS_crc/rRemainder_22 + ------------------------------------------------- --------------------------- + Total 0.136ns (0.038ns logic, 0.098ns route) + (27.9% logic, 72.1% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.124ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/txRS_preambleCnt_value_2 (FF) + Destination: ftop/gbe0/gmac/txRS_preambleCnt_value_2 (FF) + Requirement: 0.000ns + Data Path Delay: 0.124ns (Levels of Logic = 1) + Clock Path Skew: 0.000ns + Source Clock: ftop/sys1_clk$O rising at 8.000ns + Destination Clock: ftop/sys1_clk$O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/txRS_preambleCnt_value_2 to ftop/gbe0/gmac/txRS_preambleCnt_value_2 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X98Y20.CQ Tcko 0.098 ftop/gbe0/gmac/txRS_preambleCnt_value<3> + ftop/gbe0/gmac/txRS_preambleCnt_value_2 + SLICE_X98Y20.C5 net (fanout=4) 0.082 ftop/gbe0/gmac/txRS_preambleCnt_value<2> + SLICE_X98Y20.CLK Tah (-Th) 0.056 ftop/gbe0/gmac/txRS_preambleCnt_value<3> + ftop/gbe0/gmac/Mcount_txRS_preambleCnt_value_xor<2>11 + ftop/gbe0/gmac/txRS_preambleCnt_value_2 + ------------------------------------------------- --------------------------- + Total 0.124ns (0.042ns logic, 0.082ns route) + (33.9% logic, 66.1% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.125ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_1 (FF) + Destination: ftop/gbe0/gmac/txRS_txF/dGDeqPtr_1 (FF) + Requirement: 0.000ns + Data Path Delay: 0.136ns (Levels of Logic = 0) + Clock Path Skew: 0.011ns (0.055 - 0.044) + Source Clock: ftop/sys1_clk$O rising at 8.000ns + Destination Clock: ftop/sys1_clk$O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_1 to ftop/gbe0/gmac/txRS_txF/dGDeqPtr_1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X137Y22.BQ Tcko 0.098 ftop/gbe0/gmac/txRS_txF/dGDeqPtr1<3> + ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_1 + SLICE_X137Y23.AX net (fanout=6) 0.114 ftop/gbe0/gmac/txRS_txF/dGDeqPtr1<1> + SLICE_X137Y23.CLK Tckdi (-Th) 0.076 ftop/gbe0/gmac/txRS_txF/dGDeqPtr<4> + ftop/gbe0/gmac/txRS_txF/dGDeqPtr_1 + ------------------------------------------------- --------------------------- + Total 0.136ns (0.022ns logic, 0.114ns route) + (16.2% logic, 83.8% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.126ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/txRS_preambleCnt_value_4 (FF) + Destination: ftop/gbe0/gmac/txRS_preambleCnt_value_4 (FF) + Requirement: 0.000ns + Data Path Delay: 0.126ns (Levels of Logic = 1) + Clock Path Skew: 0.000ns + Source Clock: ftop/sys1_clk$O rising at 8.000ns + Destination Clock: ftop/sys1_clk$O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/txRS_preambleCnt_value_4 to ftop/gbe0/gmac/txRS_preambleCnt_value_4 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X99Y20.CQ Tcko 0.098 ftop/gbe0/gmac/txRS_preambleCnt_value<4> + ftop/gbe0/gmac/txRS_preambleCnt_value_4 + SLICE_X99Y20.C5 net (fanout=10) 0.084 ftop/gbe0/gmac/txRS_preambleCnt_value<4> + SLICE_X99Y20.CLK Tah (-Th) 0.056 ftop/gbe0/gmac/txRS_preambleCnt_value<4> + ftop/gbe0/gmac/Mcount_txRS_preambleCnt_value_xor<4>11 + ftop/gbe0/gmac/txRS_preambleCnt_value_4 + ------------------------------------------------- --------------------------- + Total 0.126ns (0.042ns logic, 0.084ns route) + (33.3% logic, 66.7% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.128ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_0 (FF) + Destination: ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_0 (FF) + Requirement: 0.000ns + Data Path Delay: 0.128ns (Levels of Logic = 1) + Clock Path Skew: 0.000ns + Source Clock: ftop/sys1_clk$O rising at 8.000ns + Destination Clock: ftop/sys1_clk$O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_0 to ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X137Y22.AQ Tcko 0.098 ftop/gbe0/gmac/txRS_txF/dGDeqPtr1<3> + ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_0 + SLICE_X137Y22.A5 net (fanout=6) 0.085 ftop/gbe0/gmac/txRS_txF/dGDeqPtr1<0> + SLICE_X137Y22.CLK Tah (-Th) 0.055 ftop/gbe0/gmac/txRS_txF/dGDeqPtr1<3> + ftop/gbe0/gmac/txRS_txF/dGDeqPtr1[0]_INV_4030_o1_INV_0 + ftop/gbe0/gmac/txRS_txF/dGDeqPtr1_0 + ------------------------------------------------- --------------------------- + Total 0.128ns (0.043ns logic, 0.085ns route) + (33.6% logic, 66.4% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.131ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/txRS_emitFCS_0 (FF) + Destination: ftop/gbe0/gmac/txRS_emitFCS_0 (FF) + Requirement: 0.000ns + Data Path Delay: 0.131ns (Levels of Logic = 1) + Clock Path Skew: 0.000ns + Source Clock: ftop/sys1_clk$O rising at 8.000ns + Destination Clock: ftop/sys1_clk$O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/gbe0/gmac/txRS_emitFCS_0 to ftop/gbe0/gmac/txRS_emitFCS_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X108Y8.AQ Tcko 0.115 ftop/gbe0/gmac/txRS_emitFCS<2> + ftop/gbe0/gmac/txRS_emitFCS_0 + SLICE_X108Y8.A5 net (fanout=37) 0.092 ftop/gbe0/gmac/txRS_emitFCS<0> + SLICE_X108Y8.CLK Tah (-Th) 0.076 ftop/gbe0/gmac/txRS_emitFCS<2> + ftop/gbe0/gmac/Mmux_txRS_emitFCS$D_IN11 + ftop/gbe0/gmac/txRS_emitFCS_0 + ------------------------------------------------- --------------------------- + Total 0.131ns (0.039ns logic, 0.092ns route) + (29.8% logic, 70.2% route) + +-------------------------------------------------------------------------------- + +Component Switching Limit Checks: TS_GMII_GTX_CLK = PERIOD TIMEGRP "GMII_GTX_CLK" 125 MHz HIGH 50%; +-------------------------------------------------------------------------------- +Slack: 6.571ns (period - min period limit) + Period: 8.000ns + Min period limit: 1.429ns (699.790MHz) (Tbcper_I) + Physical resource: ftop/sys1_clk/I0 + Logical resource: ftop/sys1_clk/I0 + Location pin: BUFGCTRL_X0Y24.I0 + Clock network: ftop/sys1_clki$O +-------------------------------------------------------------------------------- +Slack: 6.592ns (period - min period limit) + Period: 8.000ns + Min period limit: 1.408ns (710.227MHz) (Tockper) + Physical resource: gmii_tx_en_OBUF/CLK + Logical resource: ftop/gbe0/gmac/txRS_iobTxEna/CK + Location pin: OLOGIC_X2Y63.CLK + Clock network: ftop/sys1_clk$O +-------------------------------------------------------------------------------- +Slack: 6.592ns (period - min period limit) + Period: 8.000ns + Min period limit: 1.408ns (710.227MHz) (Tockper) + Physical resource: gmii_tx_er_OBUF/CLK + Logical resource: ftop/gbe0/gmac/txRS_iobTxErr/CK + Location pin: OLOGIC_X2Y62.CLK + Clock network: ftop/sys1_clk$O +-------------------------------------------------------------------------------- +Slack: 6.592ns (period - min period limit) + Period: 8.000ns + Min period limit: 1.408ns (710.227MHz) (Tockper) + Physical resource: gmii_txd_0_OBUF/CLK + Logical resource: ftop/gbe0/gmac/txRS_iobTxData/CK + Location pin: OLOGIC_X2Y64.CLK + Clock network: ftop/sys1_clk$O +-------------------------------------------------------------------------------- +Slack: 6.592ns (period - min period limit) + Period: 8.000ns + Min period limit: 1.408ns (710.227MHz) (Tockper) + Physical resource: gmii_txd_1_OBUF/CLK + Logical resource: ftop/gbe0/gmac/txRS_iobTxData_1/CK + Location pin: OLOGIC_X2Y65.CLK + Clock network: ftop/sys1_clk$O +-------------------------------------------------------------------------------- +Slack: 6.592ns (period - min period limit) + Period: 8.000ns + Min period limit: 1.408ns (710.227MHz) (Tockper) + Physical resource: gmii_txd_2_OBUF/CLK + Logical resource: ftop/gbe0/gmac/txRS_iobTxData_2/CK + Location pin: OLOGIC_X2Y66.CLK + Clock network: ftop/sys1_clk$O +-------------------------------------------------------------------------------- +Slack: 6.592ns (period - min period limit) + Period: 8.000ns + Min period limit: 1.408ns (710.227MHz) (Tockper) + Physical resource: gmii_txd_3_OBUF/CLK + Logical resource: ftop/gbe0/gmac/txRS_iobTxData_3/CK + Location pin: OLOGIC_X2Y67.CLK + Clock network: ftop/sys1_clk$O +-------------------------------------------------------------------------------- +Slack: 6.592ns (period - min period limit) + Period: 8.000ns + Min period limit: 1.408ns (710.227MHz) (Tockper) + Physical resource: gmii_txd_4_OBUF/CLK + Logical resource: ftop/gbe0/gmac/txRS_iobTxData_4/CK + Location pin: OLOGIC_X2Y68.CLK + Clock network: ftop/sys1_clk$O +-------------------------------------------------------------------------------- +Slack: 6.592ns (period - min period limit) + Period: 8.000ns + Min period limit: 1.408ns (710.227MHz) (Tockper) + Physical resource: gmii_txd_5_OBUF/CLK + Logical resource: ftop/gbe0/gmac/txRS_iobTxData_5/CK + Location pin: OLOGIC_X2Y69.CLK + Clock network: ftop/sys1_clk$O +-------------------------------------------------------------------------------- +Slack: 6.592ns (period - min period limit) + Period: 8.000ns + Min period limit: 1.408ns (710.227MHz) (Tockper) + Physical resource: gmii_txd_6_OBUF/CLK + Logical resource: ftop/gbe0/gmac/txRS_iobTxData_6/CK + Location pin: OLOGIC_X2Y70.CLK + Clock network: ftop/sys1_clk$O +-------------------------------------------------------------------------------- +Slack: 6.592ns (period - min period limit) + Period: 8.000ns + Min period limit: 1.408ns (710.227MHz) (Tockper) + Physical resource: gmii_txd_7_OBUF/CLK + Logical resource: ftop/gbe0/gmac/txRS_iobTxData_7/CK + Location pin: OLOGIC_X2Y71.CLK + Clock network: ftop/sys1_clk$O +-------------------------------------------------------------------------------- +Slack: 6.592ns (period - min period limit) + Period: 8.000ns + Min period limit: 1.408ns (710.227MHz) (Tockper) + Physical resource: gmii_gtx_clk_OBUF/CLK + Logical resource: ftop/gbe0/gmac/txRS_iobTxClk/CK + Location pin: OLOGIC_X2Y46.CLK + Clock network: ftop/sys1_clk$O +-------------------------------------------------------------------------------- +Slack: 7.168ns (period - (min high pulse limit / (high pulse / period))) + Period: 8.000ns + High pulse: 4.000ns + High pulse limit: 0.416ns (Trpw) + Physical resource: ftop/gbe0/phyRst/rstSync/reset_hold<0>/SR + Logical resource: ftop/gbe0/phyRst/rstSync/reset_hold_0/SR + Location pin: SLICE_X96Y37.SR + Clock network: ftop/gbe0/phyRst/rstSync/IN_RST_inv +-------------------------------------------------------------------------------- +Slack: 7.168ns (period - (min high pulse limit / (high pulse / period))) + Period: 8.000ns + High pulse: 4.000ns + High pulse limit: 0.416ns (Trpw) + Physical resource: gmii_rstn_OBUF/SR + Logical resource: ftop/gbe0/phyRst/rstSync/reset_hold_1/SR + Location pin: SLICE_X97Y37.SR + Clock network: ftop/gbe0/phyRst/rstSync/IN_RST_inv +-------------------------------------------------------------------------------- +Slack: 7.168ns (period - (min high pulse limit / (high pulse / period))) + Period: 8.000ns + High pulse: 4.000ns + High pulse limit: 0.416ns (Trpw) + Physical resource: ftop/gbe0/gmac/txRS_txRst/reset_hold<0>/SR + Logical resource: ftop/gbe0/gmac/txRS_txRst/reset_hold_1/SR + Location pin: SLICE_X98Y24.SR + Clock network: ftop/gbe0/gmac/txRS_txRst/IN_RST_inv +-------------------------------------------------------------------------------- +Slack: 7.168ns (period - (min high pulse limit / (high pulse / period))) + Period: 8.000ns + High pulse: 4.000ns + High pulse limit: 0.416ns (Trpw) + Physical resource: ftop/gbe0/gmac/txRS_txRst/reset_hold<0>/SR + Logical resource: ftop/gbe0/gmac/txRS_txRst/reset_hold_0/SR + Location pin: SLICE_X98Y24.SR + Clock network: ftop/gbe0/gmac/txRS_txRst/IN_RST_inv +-------------------------------------------------------------------------------- +Slack: 7.168ns (period - (min high pulse limit / (high pulse / period))) + Period: 8.000ns + High pulse: 4.000ns + High pulse limit: 0.416ns (Trpw) + Physical resource: ftop/gbe0/gmac/txRS_txOperateS$dD_OUT/SR + Logical resource: ftop/gbe0/gmac/txRS_txOperateS/dSyncReg1/SR + Location pin: SLICE_X111Y11.SR + Clock network: ftop/gbe0/gmac/txRS_txOperateS/sRST_inv +-------------------------------------------------------------------------------- +Slack: 7.168ns (period - (min high pulse limit / (high pulse / period))) + Period: 8.000ns + High pulse: 4.000ns + High pulse limit: 0.416ns (Trpw) + Physical resource: ftop/gbe0/gmac/txRS_txOperateS$dD_OUT/SR + Logical resource: ftop/gbe0/gmac/txRS_txOperateS/dSyncReg2/SR + Location pin: SLICE_X111Y11.SR + Clock network: ftop/gbe0/gmac/txRS_txOperateS/sRST_inv +-------------------------------------------------------------------------------- +Slack: 7.168ns (period - (min high pulse limit / (high pulse / period))) + Period: 8.000ns + High pulse: 4.000ns + High pulse limit: 0.416ns (Trpw) + Physical resource: ftop/gbe0/gmac/txRS_unfBit/sSyncReg/SR + Logical resource: ftop/gbe0/gmac/txRS_unfBit/sSyncReg/SR + Location pin: SLICE_X112Y12.SR + Clock network: ftop/gbe0/gmac/txRS_unfBit/sRST_inv +-------------------------------------------------------------------------------- +Slack: 7.168ns (period - (min high pulse limit / (high pulse / period))) + Period: 8.000ns + High pulse: 4.000ns + High pulse limit: 0.416ns (Trpw) + Physical resource: ftop/gbe0/gmac/txRS_txF$dEMPTY_N/SR + Logical resource: ftop/gbe0/gmac/txRS_txF/dNotEmptyReg/SR + Location pin: SLICE_X118Y17.SR + Clock network: ftop/gbe0/gmac/txRS_txF/sRST_inv +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: TS_ftop_dram0_memc_memc_u_infrastructure_clk_pll = PERIOD +TIMEGRP "ftop_dram0_memc_memc_u_infrastructure_clk_pll" TS_SYS0CLK HIGH +50%; +For more information, see Period Analysis in the Timing Closure User Guide (UG612). + + 58635 paths analyzed, 21349 endpoints analyzed, 5 failing endpoints + 5 timing errors detected. (5 setup errors, 0 hold errors, 0 component switching limit errors) + Minimum period is 5.170ns. +-------------------------------------------------------------------------------- +Slack (setup path): -0.170ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/dram0/memc_memc/u_infrastructure/rstdiv0_sync_r_7 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_init/dfi_init_complete (FF) + Requirement: 5.000ns + Data Path Delay: 4.974ns (Levels of Logic = 3) + Clock Path Skew: -0.138ns (0.927 - 1.065) + Source Clock: ftop/dram0/memc_memc$tb_clk rising at 0.000ns + Destination Clock: ftop/dram0/memc_memc$tb_clk rising at 5.000ns + Clock Uncertainty: 0.058ns + + Clock Uncertainty: 0.058ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.092ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/dram0/memc_memc/u_infrastructure/rstdiv0_sync_r_7 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_init/dfi_init_complete + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X100Y186.AQ Tcko 0.381 ftop/dram0/memc_memc/rst + ftop/dram0/memc_memc/u_infrastructure/rstdiv0_sync_r_7 + SLICE_X103Y185.B6 net (fanout=46) 0.246 ftop/dram0/memc_memc/rst + SLICE_X103Y185.B Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rst_2 + ftop/dram0/memc_memc/u_memc_ui_top/rst_1 + SLICE_X131Y210.A6 net (fanout=10) 1.802 ftop/dram0/memc_memc/u_memc_ui_top/rst_1 + SLICE_X131Y210.A Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_init/rst_9 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rst_7 + SLICE_X125Y204.B6 net (fanout=8) 0.576 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rst_7 + SLICE_X125Y204.B Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/cal2_max_cnt_rd_dly_r[4]_cal2_dly_cnt_r[9]_sub_796_OUT<4>_bdd6 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_init/rst_6 + SLICE_X125Y179.SR net (fanout=6) 1.252 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_init/rst_6 + SLICE_X125Y179.CLK Tsrck 0.513 ftop/dram0/memc_memc$phy_init_done + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_init/dfi_init_complete + ------------------------------------------------- --------------------------- + Total 4.974ns (1.098ns logic, 3.876ns route) + (22.1% logic, 77.9% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -0.120ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/dram0/memc_memc/u_infrastructure/rstdiv0_sync_r_7 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[31].rst_dq_r (FF) + Requirement: 5.000ns + Data Path Delay: 4.976ns (Levels of Logic = 3) + Clock Path Skew: -0.086ns (1.523 - 1.609) + Source Clock: ftop/dram0/memc_memc$tb_clk rising at 0.000ns + Destination Clock: ftop/dram0/memc_memc$tb_clk rising at 5.000ns + Clock Uncertainty: 0.058ns + + Clock Uncertainty: 0.058ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.092ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/dram0/memc_memc/u_infrastructure/rstdiv0_sync_r_7 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[31].rst_dq_r + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X100Y186.AQ Tcko 0.381 ftop/dram0/memc_memc/rst + ftop/dram0/memc_memc/u_infrastructure/rstdiv0_sync_r_7 + SLICE_X103Y185.B6 net (fanout=46) 0.246 ftop/dram0/memc_memc/rst + SLICE_X103Y185.B Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rst_2 + ftop/dram0/memc_memc/u_memc_ui_top/rst_1 + SLICE_X89Y158.A6 net (fanout=10) 1.644 ftop/dram0/memc_memc/u_memc_ui_top/rst_1 + SLICE_X89Y158.A Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7].rst_dqs_r + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rst_3 + SLICE_X62Y191.A6 net (fanout=8) 1.970 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rst_3 + SLICE_X62Y191.A Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[30].rst_dq_r + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/rst_5 + SLICE_X63Y191.BX net (fanout=5) 0.497 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/rst_5 + SLICE_X63Y191.CLK Tdick 0.034 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[31].rst_dq_r + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[31].rst_dq_r + ------------------------------------------------- --------------------------- + Total 4.976ns (0.619ns logic, 4.357ns route) + (12.4% logic, 87.6% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -0.098ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/dram0/memc_memc/u_infrastructure/rstdiv0_sync_r_7 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[39].rst_dq_r (FF) + Requirement: 5.000ns + Data Path Delay: 4.954ns (Levels of Logic = 3) + Clock Path Skew: -0.086ns (1.523 - 1.609) + Source Clock: ftop/dram0/memc_memc$tb_clk rising at 0.000ns + Destination Clock: ftop/dram0/memc_memc$tb_clk rising at 5.000ns + Clock Uncertainty: 0.058ns + + Clock Uncertainty: 0.058ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.092ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/dram0/memc_memc/u_infrastructure/rstdiv0_sync_r_7 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[39].rst_dq_r + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X100Y186.AQ Tcko 0.381 ftop/dram0/memc_memc/rst + ftop/dram0/memc_memc/u_infrastructure/rstdiv0_sync_r_7 + SLICE_X103Y185.B6 net (fanout=46) 0.246 ftop/dram0/memc_memc/rst + SLICE_X103Y185.B Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rst_2 + ftop/dram0/memc_memc/u_memc_ui_top/rst_1 + SLICE_X89Y158.A6 net (fanout=10) 1.644 ftop/dram0/memc_memc/u_memc_ui_top/rst_1 + SLICE_X89Y158.A Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7].rst_dqs_r + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rst_3 + SLICE_X62Y191.A6 net (fanout=8) 1.970 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rst_3 + SLICE_X62Y191.A Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[30].rst_dq_r + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/rst_5 + SLICE_X63Y191.BX net (fanout=5) 0.497 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/rst_5 + SLICE_X63Y191.CLK Tdick 0.012 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[31].rst_dq_r + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[39].rst_dq_r + ------------------------------------------------- --------------------------- + Total 4.954ns (0.597ns logic, 4.357ns route) + (12.1% logic, 87.9% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -0.003ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/dram0/memc_memc/u_infrastructure/rstdiv0_sync_r_7 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[36].rst_dq_r (FF) + Requirement: 5.000ns + Data Path Delay: 4.860ns (Levels of Logic = 3) + Clock Path Skew: -0.085ns (1.524 - 1.609) + Source Clock: ftop/dram0/memc_memc$tb_clk rising at 0.000ns + Destination Clock: ftop/dram0/memc_memc$tb_clk rising at 5.000ns + Clock Uncertainty: 0.058ns + + Clock Uncertainty: 0.058ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.092ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/dram0/memc_memc/u_infrastructure/rstdiv0_sync_r_7 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[36].rst_dq_r + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X100Y186.AQ Tcko 0.381 ftop/dram0/memc_memc/rst + ftop/dram0/memc_memc/u_infrastructure/rstdiv0_sync_r_7 + SLICE_X103Y185.B6 net (fanout=46) 0.246 ftop/dram0/memc_memc/rst + SLICE_X103Y185.B Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rst_2 + ftop/dram0/memc_memc/u_memc_ui_top/rst_1 + SLICE_X89Y158.A6 net (fanout=10) 1.644 ftop/dram0/memc_memc/u_memc_ui_top/rst_1 + SLICE_X89Y158.A Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7].rst_dqs_r + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rst_3 + SLICE_X62Y191.A6 net (fanout=8) 1.970 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rst_3 + SLICE_X62Y191.A Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[30].rst_dq_r + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/rst_5 + SLICE_X63Y193.AX net (fanout=5) 0.381 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/rst_5 + SLICE_X63Y193.CLK Tdick 0.034 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[36].rst_dq_r + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[36].rst_dq_r + ------------------------------------------------- --------------------------- + Total 4.860ns (0.619ns logic, 4.241ns route) + (12.7% logic, 87.3% route) + +-------------------------------------------------------------------------------- +Slack (setup path): -0.001ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/dram0/memc_memc/u_infrastructure/rstdiv0_sync_r_7 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[62].rst_dq_r (FF) + Requirement: 5.000ns + Data Path Delay: 4.755ns (Levels of Logic = 3) + Clock Path Skew: -0.188ns (1.536 - 1.724) + Source Clock: ftop/dram0/memc_memc$tb_clk rising at 0.000ns + Destination Clock: ftop/dram0/memc_memc$tb_clk rising at 5.000ns + Clock Uncertainty: 0.058ns + + Clock Uncertainty: 0.058ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.092ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/dram0/memc_memc/u_infrastructure/rstdiv0_sync_r_7 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[62].rst_dq_r + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X100Y186.AQ Tcko 0.381 ftop/dram0/memc_memc/rst + ftop/dram0/memc_memc/u_infrastructure/rstdiv0_sync_r_7 + SLICE_X103Y185.B6 net (fanout=46) 0.246 ftop/dram0/memc_memc/rst + SLICE_X103Y185.B Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rst_2 + ftop/dram0/memc_memc/u_memc_ui_top/rst_1 + SLICE_X89Y158.A6 net (fanout=10) 1.644 ftop/dram0/memc_memc/u_memc_ui_top/rst_1 + SLICE_X89Y158.A Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7].rst_dqs_r + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rst_3 + SLICE_X71Y143.D6 net (fanout=8) 1.198 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rst_3 + SLICE_X71Y143.D Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[59].rst_dq_r + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/rst_2 + SLICE_X69Y126.DX net (fanout=7) 1.048 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/rst_2 + SLICE_X69Y126.CLK Tdick 0.034 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[62].rst_dq_r + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[62].rst_dq_r + ------------------------------------------------- --------------------------- + Total 4.755ns (0.619ns logic, 4.136ns route) + (13.0% logic, 87.0% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.004ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.rd_addr_r_4 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[56].u_iob_dq/wr_data_fall1_r1 (FF) + Requirement: 5.000ns + Data Path Delay: 4.772ns (Levels of Logic = 2) + Clock Path Skew: -0.166ns (1.536 - 1.702) + Source Clock: ftop/dram0/memc_memc$tb_clk rising at 0.000ns + Destination Clock: ftop/dram0/memc_memc$tb_clk rising at 5.000ns + Clock Uncertainty: 0.058ns + + Clock Uncertainty: 0.058ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.092ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.rd_addr_r_4 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[56].u_iob_dq/wr_data_fall1_r1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X115Y164.DQ Tcko 0.337 ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.rd_addr_r<4> + ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.rd_addr_r_4 + SLICE_X88Y123.B5 net (fanout=144) 3.296 ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.rd_addr_r<4> + SLICE_X88Y123.BMUX Tilo 0.205 ftop/dram0/memc_memc/u_memc_ui_top/wr_data<247> + ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[41].RAM32M0_RAMB + SLICE_X71Y128.A6 net (fanout=1) 0.861 ftop/dram0/memc_memc/u_memc_ui_top/wr_data<248> + SLICE_X71Y128.CLK Tas 0.073 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[56].u_iob_dq/wr_data_fall1_r3 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_write/Mmux_wr_data_fall1521 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[56].u_iob_dq/wr_data_fall1_r1 + ------------------------------------------------- --------------------------- + Total 4.772ns (0.615ns logic, 4.157ns route) + (12.9% logic, 87.1% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.007ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/read_fifo.fifo_out_data_r_10 (FF) + Destination: ftop/dram0/memc_respF/Mshreg_GND_174_o_dat[15][127]_wide_mux_5_OUT_53_0 (FF) + Requirement: 5.000ns + Data Path Delay: 4.733ns (Levels of Logic = 2) + Clock Path Skew: -0.202ns (1.531 - 1.733) + Source Clock: ftop/dram0/memc_memc$tb_clk rising at 0.000ns + Destination Clock: ftop/dram0/memc_memc$tb_clk rising at 5.000ns + Clock Uncertainty: 0.058ns + + Clock Uncertainty: 0.058ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.092ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/read_fifo.fifo_out_data_r_10 to ftop/dram0/memc_respF/Mshreg_GND_174_o_dat[15][127]_wide_mux_5_OUT_53_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X100Y162.AQ Tcko 0.381 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/read_fifo.fifo_out_data_r<9> + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/read_fifo.fifo_out_data_r_10 + SLICE_X87Y129.D6 net (fanout=130) 2.004 ftop/dram0/memc_memc$app_rd_data_end + SLICE_X87Y129.D Tilo 0.068 ftop/dram0/N82 + ftop/dram0/memc_respF$ENQ_SW0 + SLICE_X85Y139.A6 net (fanout=22) 0.791 ftop/dram0/N82 + SLICE_X85Y139.A Tilo 0.068 ftop/dram0/memc_memc$app_rd_data<251> + ftop/dram0/memc_respF$ENQ_REPLICA_220 + SLICE_X68Y132.WE net (fanout=1) 1.342 ftop/dram0/memc_respF$ENQ_REPLICA_220 + SLICE_X68Y132.CLK Tws 0.079 ftop/dram0/memc_respF$D_OUT<55> + ftop/dram0/memc_respF/Mshreg_GND_174_o_dat[15][127]_wide_mux_5_OUT_53_0 + ------------------------------------------------- --------------------------- + Total 4.733ns (0.596ns logic, 4.137ns route) + (12.6% logic, 87.4% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.007ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/read_fifo.fifo_out_data_r_10 (FF) + Destination: ftop/dram0/memc_respF/Mshreg_GND_174_o_dat[15][127]_wide_mux_5_OUT_52_0 (FF) + Requirement: 5.000ns + Data Path Delay: 4.733ns (Levels of Logic = 2) + Clock Path Skew: -0.202ns (1.531 - 1.733) + Source Clock: ftop/dram0/memc_memc$tb_clk rising at 0.000ns + Destination Clock: ftop/dram0/memc_memc$tb_clk rising at 5.000ns + Clock Uncertainty: 0.058ns + + Clock Uncertainty: 0.058ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.092ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/read_fifo.fifo_out_data_r_10 to ftop/dram0/memc_respF/Mshreg_GND_174_o_dat[15][127]_wide_mux_5_OUT_52_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X100Y162.AQ Tcko 0.381 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/read_fifo.fifo_out_data_r<9> + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/read_fifo.fifo_out_data_r_10 + SLICE_X87Y129.D6 net (fanout=130) 2.004 ftop/dram0/memc_memc$app_rd_data_end + SLICE_X87Y129.D Tilo 0.068 ftop/dram0/N82 + ftop/dram0/memc_respF$ENQ_SW0 + SLICE_X85Y139.A6 net (fanout=22) 0.791 ftop/dram0/N82 + SLICE_X85Y139.A Tilo 0.068 ftop/dram0/memc_memc$app_rd_data<251> + ftop/dram0/memc_respF$ENQ_REPLICA_220 + SLICE_X68Y132.WE net (fanout=1) 1.342 ftop/dram0/memc_respF$ENQ_REPLICA_220 + SLICE_X68Y132.CLK Tws 0.079 ftop/dram0/memc_respF$D_OUT<55> + ftop/dram0/memc_respF/Mshreg_GND_174_o_dat[15][127]_wide_mux_5_OUT_52_0 + ------------------------------------------------- --------------------------- + Total 4.733ns (0.596ns logic, 4.137ns route) + (12.6% logic, 87.4% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.007ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/read_fifo.fifo_out_data_r_10 (FF) + Destination: ftop/dram0/memc_respF/Mshreg_GND_174_o_dat[15][127]_wide_mux_5_OUT_55_0 (FF) + Requirement: 5.000ns + Data Path Delay: 4.733ns (Levels of Logic = 2) + Clock Path Skew: -0.202ns (1.531 - 1.733) + Source Clock: ftop/dram0/memc_memc$tb_clk rising at 0.000ns + Destination Clock: ftop/dram0/memc_memc$tb_clk rising at 5.000ns + Clock Uncertainty: 0.058ns + + Clock Uncertainty: 0.058ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.092ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/read_fifo.fifo_out_data_r_10 to ftop/dram0/memc_respF/Mshreg_GND_174_o_dat[15][127]_wide_mux_5_OUT_55_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X100Y162.AQ Tcko 0.381 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/read_fifo.fifo_out_data_r<9> + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/read_fifo.fifo_out_data_r_10 + SLICE_X87Y129.D6 net (fanout=130) 2.004 ftop/dram0/memc_memc$app_rd_data_end + SLICE_X87Y129.D Tilo 0.068 ftop/dram0/N82 + ftop/dram0/memc_respF$ENQ_SW0 + SLICE_X85Y139.A6 net (fanout=22) 0.791 ftop/dram0/N82 + SLICE_X85Y139.A Tilo 0.068 ftop/dram0/memc_memc$app_rd_data<251> + ftop/dram0/memc_respF$ENQ_REPLICA_220 + SLICE_X68Y132.WE net (fanout=1) 1.342 ftop/dram0/memc_respF$ENQ_REPLICA_220 + SLICE_X68Y132.CLK Tws 0.079 ftop/dram0/memc_respF$D_OUT<55> + ftop/dram0/memc_respF/Mshreg_GND_174_o_dat[15][127]_wide_mux_5_OUT_55_0 + ------------------------------------------------- --------------------------- + Total 4.733ns (0.596ns logic, 4.137ns route) + (12.6% logic, 87.4% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.007ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/read_fifo.fifo_out_data_r_10 (FF) + Destination: ftop/dram0/memc_respF/Mshreg_GND_174_o_dat[15][127]_wide_mux_5_OUT_54_0 (FF) + Requirement: 5.000ns + Data Path Delay: 4.733ns (Levels of Logic = 2) + Clock Path Skew: -0.202ns (1.531 - 1.733) + Source Clock: ftop/dram0/memc_memc$tb_clk rising at 0.000ns + Destination Clock: ftop/dram0/memc_memc$tb_clk rising at 5.000ns + Clock Uncertainty: 0.058ns + + Clock Uncertainty: 0.058ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.092ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/read_fifo.fifo_out_data_r_10 to ftop/dram0/memc_respF/Mshreg_GND_174_o_dat[15][127]_wide_mux_5_OUT_54_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X100Y162.AQ Tcko 0.381 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/read_fifo.fifo_out_data_r<9> + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/read_fifo.fifo_out_data_r_10 + SLICE_X87Y129.D6 net (fanout=130) 2.004 ftop/dram0/memc_memc$app_rd_data_end + SLICE_X87Y129.D Tilo 0.068 ftop/dram0/N82 + ftop/dram0/memc_respF$ENQ_SW0 + SLICE_X85Y139.A6 net (fanout=22) 0.791 ftop/dram0/N82 + SLICE_X85Y139.A Tilo 0.068 ftop/dram0/memc_memc$app_rd_data<251> + ftop/dram0/memc_respF$ENQ_REPLICA_220 + SLICE_X68Y132.WE net (fanout=1) 1.342 ftop/dram0/memc_respF$ENQ_REPLICA_220 + SLICE_X68Y132.CLK Tws 0.079 ftop/dram0/memc_respF$D_OUT<55> + ftop/dram0/memc_respF/Mshreg_GND_174_o_dat[15][127]_wide_mux_5_OUT_54_0 + ------------------------------------------------- --------------------------- + Total 4.733ns (0.596ns logic, 4.137ns route) + (12.6% logic, 87.4% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.007ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/dram0/memc_memc/u_infrastructure/rstdiv0_sync_r_7 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[35].rst_dq_r (FF) + Requirement: 5.000ns + Data Path Delay: 4.850ns (Levels of Logic = 3) + Clock Path Skew: -0.085ns (1.524 - 1.609) + Source Clock: ftop/dram0/memc_memc$tb_clk rising at 0.000ns + Destination Clock: ftop/dram0/memc_memc$tb_clk rising at 5.000ns + Clock Uncertainty: 0.058ns + + Clock Uncertainty: 0.058ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.092ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/dram0/memc_memc/u_infrastructure/rstdiv0_sync_r_7 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[35].rst_dq_r + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X100Y186.AQ Tcko 0.381 ftop/dram0/memc_memc/rst + ftop/dram0/memc_memc/u_infrastructure/rstdiv0_sync_r_7 + SLICE_X103Y185.B6 net (fanout=46) 0.246 ftop/dram0/memc_memc/rst + SLICE_X103Y185.B Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rst_2 + ftop/dram0/memc_memc/u_memc_ui_top/rst_1 + SLICE_X89Y158.A6 net (fanout=10) 1.644 ftop/dram0/memc_memc/u_memc_ui_top/rst_1 + SLICE_X89Y158.A Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7].rst_dqs_r + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rst_3 + SLICE_X62Y191.A6 net (fanout=8) 1.970 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rst_3 + SLICE_X62Y191.A Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[30].rst_dq_r + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/rst_5 + SLICE_X63Y192.BX net (fanout=5) 0.371 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/rst_5 + SLICE_X63Y192.CLK Tdick 0.034 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[35].rst_dq_r + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[35].rst_dq_r + ------------------------------------------------- --------------------------- + Total 4.850ns (0.619ns logic, 4.231ns route) + (12.8% logic, 87.2% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.012ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_init/u_ff_phy_init_data_sel (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[44].u_iob_dq/wr_data_rise1_r1 (FF) + Requirement: 5.000ns + Data Path Delay: 4.789ns (Levels of Logic = 1) + Clock Path Skew: -0.141ns (1.538 - 1.679) + Source Clock: ftop/dram0/memc_memc$tb_clk rising at 0.000ns + Destination Clock: ftop/dram0/memc_memc$tb_clk rising at 5.000ns + Clock Uncertainty: 0.058ns + + Clock Uncertainty: 0.058ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.092ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_init/u_ff_phy_init_data_sel to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[44].u_iob_dq/wr_data_rise1_r1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X117Y190.AQ Tcko 0.337 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/phy_init_data_sel + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_init/u_ff_phy_init_data_sel + SLICE_X71Y156.A4 net (fanout=252) 4.379 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/phy_init_data_sel + SLICE_X71Y156.CLK Tas 0.073 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[44].u_iob_dq/wr_data_rise1_r3 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_write/Mmux_wr_data_rise1391 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[44].u_iob_dq/wr_data_rise1_r1 + ------------------------------------------------- --------------------------- + Total 4.789ns (0.410ns logic, 4.379ns route) + (8.6% logic, 91.4% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.017ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.rd_addr_r_2 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[55].u_iob_dq/wr_data_fall1_r1 (FF) + Requirement: 5.000ns + Data Path Delay: 4.740ns (Levels of Logic = 2) + Clock Path Skew: -0.185ns (1.531 - 1.716) + Source Clock: ftop/dram0/memc_memc$tb_clk rising at 0.000ns + Destination Clock: ftop/dram0/memc_memc$tb_clk rising at 5.000ns + Clock Uncertainty: 0.058ns + + Clock Uncertainty: 0.058ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.092ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.rd_addr_r_2 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[55].u_iob_dq/wr_data_fall1_r1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X111Y162.CQ Tcko 0.337 ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.rd_addr_r<3> + ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.rd_addr_r_2 + SLICE_X88Y123.C3 net (fanout=144) 3.238 ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.rd_addr_r<2> + SLICE_X88Y123.C Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/wr_data<247> + ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[41].RAM32M0_RAMC_D1 + SLICE_X67Y132.A6 net (fanout=1) 1.024 ftop/dram0/memc_memc/u_memc_ui_top/wr_data<247> + SLICE_X67Y132.CLK Tas 0.073 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[55].u_iob_dq/wr_data_fall1_r3 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_write/Mmux_wr_data_fall1511 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[55].u_iob_dq/wr_data_fall1_r1 + ------------------------------------------------- --------------------------- + Total 4.740ns (0.478ns logic, 4.262ns route) + (10.1% logic, 89.9% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.019ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/dram0/memc_memc/u_infrastructure/rstdiv0_sync_r_7 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[37].rst_dq_r (FF) + Requirement: 5.000ns + Data Path Delay: 4.838ns (Levels of Logic = 3) + Clock Path Skew: -0.085ns (1.524 - 1.609) + Source Clock: ftop/dram0/memc_memc$tb_clk rising at 0.000ns + Destination Clock: ftop/dram0/memc_memc$tb_clk rising at 5.000ns + Clock Uncertainty: 0.058ns + + Clock Uncertainty: 0.058ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.092ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/dram0/memc_memc/u_infrastructure/rstdiv0_sync_r_7 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[37].rst_dq_r + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X100Y186.AQ Tcko 0.381 ftop/dram0/memc_memc/rst + ftop/dram0/memc_memc/u_infrastructure/rstdiv0_sync_r_7 + SLICE_X103Y185.B6 net (fanout=46) 0.246 ftop/dram0/memc_memc/rst + SLICE_X103Y185.B Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rst_2 + ftop/dram0/memc_memc/u_memc_ui_top/rst_1 + SLICE_X89Y158.A6 net (fanout=10) 1.644 ftop/dram0/memc_memc/u_memc_ui_top/rst_1 + SLICE_X89Y158.A Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7].rst_dqs_r + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rst_3 + SLICE_X62Y191.A6 net (fanout=8) 1.970 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rst_3 + SLICE_X62Y191.A Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[30].rst_dq_r + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/rst_5 + SLICE_X63Y193.AX net (fanout=5) 0.381 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/rst_5 + SLICE_X63Y193.CLK Tdick 0.012 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[36].rst_dq_r + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[37].rst_dq_r + ------------------------------------------------- --------------------------- + Total 4.838ns (0.597ns logic, 4.241ns route) + (12.3% logic, 87.7% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.020ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.rd_addr_r_4 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[59].u_iob_dq/wr_data_rise1_r1 (FF) + Requirement: 5.000ns + Data Path Delay: 4.757ns (Levels of Logic = 2) + Clock Path Skew: -0.165ns (1.537 - 1.702) + Source Clock: ftop/dram0/memc_memc$tb_clk rising at 0.000ns + Destination Clock: ftop/dram0/memc_memc$tb_clk rising at 5.000ns + Clock Uncertainty: 0.058ns + + Clock Uncertainty: 0.058ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.092ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.rd_addr_r_4 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[59].u_iob_dq/wr_data_rise1_r1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X115Y164.DQ Tcko 0.337 ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.rd_addr_r<4> + ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.rd_addr_r_4 + SLICE_X96Y123.C5 net (fanout=144) 2.830 ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.rd_addr_r<4> + SLICE_X96Y123.C Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/wr_data<187> + ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[31].RAM32M0_RAMC_D1 + SLICE_X68Y124.A6 net (fanout=1) 1.492 ftop/dram0/memc_memc/u_memc_ui_top/wr_data<187> + SLICE_X68Y124.CLK Tas 0.030 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[59].u_iob_dq/wr_data_rise1_r3 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_write/Mmux_wr_data_rise1551 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[59].u_iob_dq/wr_data_rise1_r1 + ------------------------------------------------- --------------------------- + Total 4.757ns (0.435ns logic, 4.322ns route) + (9.1% logic, 90.9% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.021ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_init/u_ff_phy_init_data_sel (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[44].u_iob_dq/wr_data_fall1_r1 (FF) + Requirement: 5.000ns + Data Path Delay: 4.780ns (Levels of Logic = 1) + Clock Path Skew: -0.141ns (1.538 - 1.679) + Source Clock: ftop/dram0/memc_memc$tb_clk rising at 0.000ns + Destination Clock: ftop/dram0/memc_memc$tb_clk rising at 5.000ns + Clock Uncertainty: 0.058ns + + Clock Uncertainty: 0.058ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.092ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_init/u_ff_phy_init_data_sel to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[44].u_iob_dq/wr_data_fall1_r1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X117Y190.AQ Tcko 0.337 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/phy_init_data_sel + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_init/u_ff_phy_init_data_sel + SLICE_X70Y157.A4 net (fanout=252) 4.370 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/phy_init_data_sel + SLICE_X70Y157.CLK Tas 0.073 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[44].u_iob_dq/wr_data_fall1_r3 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_write/Mmux_wr_data_fall1391 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[44].u_iob_dq/wr_data_fall1_r1 + ------------------------------------------------- --------------------------- + Total 4.780ns (0.410ns logic, 4.370ns route) + (8.6% logic, 91.4% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.025ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.rd_addr_r_4 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[57].u_iob_dq/ocb_d4 (FF) + Requirement: 5.000ns + Data Path Delay: 4.752ns (Levels of Logic = 3) + Clock Path Skew: -0.165ns (1.537 - 1.702) + Source Clock: ftop/dram0/memc_memc$tb_clk rising at 0.000ns + Destination Clock: ftop/dram0/memc_memc$tb_clk rising at 5.000ns + Clock Uncertainty: 0.058ns + + Clock Uncertainty: 0.058ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.092ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.rd_addr_r_4 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[57].u_iob_dq/ocb_d4 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X115Y164.DQ Tcko 0.337 ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.rd_addr_r<4> + ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.rd_addr_r_4 + SLICE_X88Y137.B5 net (fanout=144) 2.906 ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.rd_addr_r<4> + SLICE_X88Y137.B Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/wr_data<55> + ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[9].RAM32M0_RAMB_D1 + SLICE_X70Y127.B6 net (fanout=1) 1.036 ftop/dram0/memc_memc/u_memc_ui_top/wr_data<57> + SLICE_X70Y127.B Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[57].u_iob_dq/ocb_d4 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_write/Mmux_wr_data_rise0531 + SLICE_X70Y127.D6 net (fanout=1) 0.123 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/wr_data_rise0<57> + SLICE_X70Y127.CLK Tas 0.214 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[57].u_iob_dq/ocb_d4 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[57].u_iob_dq/Mmux_wr_calib_dly[1]_wr_data_fall0_r2_Mux_5_o_4 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[57].u_iob_dq/Mmux_wr_calib_dly[1]_wr_data_fall0_r2_Mux_5_o_2_f7 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[57].u_iob_dq/ocb_d4 + ------------------------------------------------- --------------------------- + Total 4.752ns (0.687ns logic, 4.065ns route) + (14.5% logic, 85.5% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.038ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_init/phy_wrdata_0 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[56].u_iob_dq/ocb_d4 (FF) + Requirement: 5.000ns + Data Path Delay: 4.704ns (Levels of Logic = 2) + Clock Path Skew: -0.200ns (1.532 - 1.732) + Source Clock: ftop/dram0/memc_memc$tb_clk rising at 0.000ns + Destination Clock: ftop/dram0/memc_memc$tb_clk rising at 5.000ns + Clock Uncertainty: 0.058ns + + Clock Uncertainty: 0.058ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.092ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_init/phy_wrdata_0 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[56].u_iob_dq/ocb_d4 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X100Y165.AQ Tcko 0.381 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/phy_wrdata<101> + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_init/phy_wrdata_0 + SLICE_X70Y133.B4 net (fanout=48) 3.918 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/phy_wrdata<0> + SLICE_X70Y133.B Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[56].u_iob_dq/ocb_d4 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_write/Mmux_wr_data_rise0521 + SLICE_X70Y133.D6 net (fanout=1) 0.123 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/wr_data_rise0<56> + SLICE_X70Y133.CLK Tas 0.214 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[56].u_iob_dq/ocb_d4 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[56].u_iob_dq/Mmux_wr_calib_dly[1]_wr_data_fall0_r2_Mux_5_o_4 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[56].u_iob_dq/Mmux_wr_calib_dly[1]_wr_data_fall0_r2_Mux_5_o_2_f7 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[56].u_iob_dq/ocb_d4 + ------------------------------------------------- --------------------------- + Total 4.704ns (0.663ns logic, 4.041ns route) + (14.1% logic, 85.9% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.039ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/dram0/memc_memc/u_infrastructure/rstdiv0_sync_r_7 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_write/dqs_rst_7 (FF) + Requirement: 5.000ns + Data Path Delay: 4.727ns (Levels of Logic = 4) + Clock Path Skew: -0.176ns (1.548 - 1.724) + Source Clock: ftop/dram0/memc_memc$tb_clk rising at 0.000ns + Destination Clock: ftop/dram0/memc_memc$tb_clk rising at 5.000ns + Clock Uncertainty: 0.058ns + + Clock Uncertainty: 0.058ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.092ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/dram0/memc_memc/u_infrastructure/rstdiv0_sync_r_7 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_write/dqs_rst_7 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X100Y186.AQ Tcko 0.381 ftop/dram0/memc_memc/rst + ftop/dram0/memc_memc/u_infrastructure/rstdiv0_sync_r_7 + SLICE_X103Y185.B6 net (fanout=46) 0.246 ftop/dram0/memc_memc/rst + SLICE_X103Y185.B Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rst_2 + ftop/dram0/memc_memc/u_memc_ui_top/rst_1 + SLICE_X90Y175.A5 net (fanout=10) 1.238 ftop/dram0/memc_memc/u_memc_ui_top/rst_1 + SLICE_X90Y175.A Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_inst.gen_dm[4].u_phy_dm_iob/mask_data_rise0_r2 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rst_6 + SLICE_X89Y166.A6 net (fanout=8) 0.662 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rst_6 + SLICE_X89Y166.A Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dqs_rst<1> + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_write/rst_5 + SLICE_X88Y152.D5 net (fanout=9) 1.075 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_write/rst_5 + SLICE_X88Y152.D Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_write/Reset_OR_DriverANDClockEnable4 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_write/Reset_OR_DriverANDClockEnable41 + SLICE_X89Y151.SR net (fanout=1) 0.340 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_write/Reset_OR_DriverANDClockEnable4 + SLICE_X89Y151.CLK Tsrck 0.513 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/dqs_rst<5> + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_write/dqs_rst_7 + ------------------------------------------------- --------------------------- + Total 4.727ns (1.166ns logic, 3.561ns route) + (24.7% logic, 75.3% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.040ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/dram0/memc_memc/u_infrastructure/rstdiv0_sync_r_7 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_init/mr1_r<0>_1 (FF) + Requirement: 5.000ns + Data Path Delay: 4.848ns (Levels of Logic = 4) + Clock Path Skew: -0.054ns (1.555 - 1.609) + Source Clock: ftop/dram0/memc_memc$tb_clk rising at 0.000ns + Destination Clock: ftop/dram0/memc_memc$tb_clk rising at 5.000ns + Clock Uncertainty: 0.058ns + + Clock Uncertainty: 0.058ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.092ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: ftop/dram0/memc_memc/u_infrastructure/rstdiv0_sync_r_7 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_init/mr1_r<0>_1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X100Y186.AQ Tcko 0.381 ftop/dram0/memc_memc/rst + ftop/dram0/memc_memc/u_infrastructure/rstdiv0_sync_r_7 + SLICE_X103Y185.B6 net (fanout=46) 0.246 ftop/dram0/memc_memc/rst + SLICE_X103Y185.B Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rst_2 + ftop/dram0/memc_memc/u_memc_ui_top/rst_1 + SLICE_X131Y210.A6 net (fanout=10) 1.802 ftop/dram0/memc_memc/u_memc_ui_top/rst_1 + SLICE_X131Y210.A Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_init/rst_9 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rst_7 + SLICE_X131Y210.B6 net (fanout=8) 0.239 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rst_7 + SLICE_X131Y210.B Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_init/rst_9 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_init/rst_9 + SLICE_X133Y213.C6 net (fanout=8) 0.537 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_init/rst_9 + SLICE_X133Y213.C Tilo 0.068 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/phy_cs_n1 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_init/rst_1 + SLICE_X129Y206.SR net (fanout=8) 0.858 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_init/rst_1 + SLICE_X129Y206.CLK Tsrck 0.513 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/phy_cs_n0 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_init/mr1_r<0>_1 + ------------------------------------------------- --------------------------- + Total 4.848ns (1.166ns logic, 3.682ns route) + (24.1% logic, 75.9% route) + +-------------------------------------------------------------------------------- + +Hold Paths: TS_ftop_dram0_memc_memc_u_infrastructure_clk_pll = PERIOD TIMEGRP + "ftop_dram0_memc_memc_u_infrastructure_clk_pll" TS_SYS0CLK HIGH 50%; +-------------------------------------------------------------------------------- +Slack (hold path): 0.040ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/arb_mux0/arb_row_col0/row_arb0/grant_r_2 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/arb_mux0/arb_row_col0/row_arb0/last_master_r_2 (FF) + Requirement: 0.000ns + Data Path Delay: 0.147ns (Levels of Logic = 1) + Clock Path Skew: 0.107ns (0.759 - 0.652) + Source Clock: ftop/dram0/memc_memc$tb_clk rising at 5.000ns + Destination Clock: ftop/dram0/memc_memc$tb_clk rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/arb_mux0/arb_row_col0/row_arb0/grant_r_2 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/arb_mux0/arb_row_col0/row_arb0/last_master_r_2 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X134Y199.AQ Tcko 0.115 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/sending_row<3> + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/arb_mux0/arb_row_col0/row_arb0/grant_r_2 + SLICE_X134Y200.C6 net (fanout=29) 0.108 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/sending_row<2> + SLICE_X134Y200.CLK Tah (-Th) 0.076 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/arb_mux0/arb_row_col0/row_arb0/last_master_r<3> + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/arb_mux0/arb_row_col0/row_arb0/Mmux_last_master_ns31 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/arb_mux0/arb_row_col0/row_arb0/last_master_r_2 + ------------------------------------------------- --------------------------- + Total 0.147ns (0.039ns logic, 0.108ns route) + (26.5% logic, 73.5% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.043ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/arb_mux0/arb_row_col0/row_arb0/grant_r_1 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/arb_mux0/arb_row_col0/row_arb0/last_master_r_1 (FF) + Requirement: 0.000ns + Data Path Delay: 0.150ns (Levels of Logic = 1) + Clock Path Skew: 0.107ns (0.759 - 0.652) + Source Clock: ftop/dram0/memc_memc$tb_clk rising at 5.000ns + Destination Clock: ftop/dram0/memc_memc$tb_clk rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/arb_mux0/arb_row_col0/row_arb0/grant_r_1 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/arb_mux0/arb_row_col0/row_arb0/last_master_r_1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X135Y199.CQ Tcko 0.098 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/sending_row<1> + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/arb_mux0/arb_row_col0/row_arb0/grant_r_1 + SLICE_X134Y200.B5 net (fanout=28) 0.129 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/sending_row<1> + SLICE_X134Y200.CLK Tah (-Th) 0.077 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/arb_mux0/arb_row_col0/row_arb0/last_master_r<3> + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/arb_mux0/arb_row_col0/row_arb0/Mmux_last_master_ns21 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/arb_mux0/arb_row_col0/row_arb0/last_master_r_1 + ------------------------------------------------- --------------------------- + Total 0.150ns (0.021ns logic, 0.129ns route) + (14.0% logic, 86.0% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.055ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/cal2_dly_cnt_delta_r<7>_3 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/cal2_clkdly_cnt_r_15 (FF) + Requirement: 0.000ns + Data Path Delay: 0.067ns (Levels of Logic = 1) + Clock Path Skew: 0.012ns (0.065 - 0.053) + Source Clock: ftop/dram0/memc_memc$tb_clk rising at 5.000ns + Destination Clock: ftop/dram0/memc_memc$tb_clk rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/cal2_dly_cnt_delta_r<7>_3 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/cal2_clkdly_cnt_r_15 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X111Y204.BQ Tcko 0.098 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/cal2_dly_cnt_delta_r<7><4> + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/cal2_dly_cnt_delta_r<7>_3 + SLICE_X110Y204.D6 net (fanout=1) 0.046 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/cal2_dly_cnt_delta_r<7><3> + SLICE_X110Y204.CLK Tah (-Th) 0.077 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/cal2_clkdly_cnt_r_15 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/cal2_dly_cnt_delta_r[7][4]_INV_3569_o1 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/cal2_clkdly_cnt_r_15 + ------------------------------------------------- --------------------------- + Total 0.067ns (0.021ns logic, 0.046ns route) + (31.3% logic, 68.7% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.061ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_init/cnt_txpr_r_1 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_init/cnt_txpr_done_r (FF) + Requirement: 0.000ns + Data Path Delay: 0.072ns (Levels of Logic = 1) + Clock Path Skew: 0.011ns (0.062 - 0.051) + Source Clock: ftop/dram0/memc_memc$tb_clk rising at 5.000ns + Destination Clock: ftop/dram0/memc_memc$tb_clk rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_init/cnt_txpr_r_1 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_init/cnt_txpr_done_r + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X139Y229.BQ Tcko 0.098 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_init/cnt_txpr_r<3> + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_init/cnt_txpr_r_1 + SLICE_X138Y229.A6 net (fanout=2) 0.050 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_init/cnt_txpr_r<1> + SLICE_X138Y229.CLK Tah (-Th) 0.076 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_init/cnt_txpr_done_r + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_init/GND_117_o_GND_117_o_equal_90_o<7> + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_init/cnt_txpr_done_r + ------------------------------------------------- --------------------------- + Total 0.072ns (0.022ns logic, 0.050ns route) + (30.6% logic, 69.4% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.061ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/arb_mux0/arb_row_col0/row_arb0/grant_r_3 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/arb_mux0/arb_row_col0/row_arb0/last_master_r_3 (FF) + Requirement: 0.000ns + Data Path Delay: 0.168ns (Levels of Logic = 1) + Clock Path Skew: 0.107ns (0.759 - 0.652) + Source Clock: ftop/dram0/memc_memc$tb_clk rising at 5.000ns + Destination Clock: ftop/dram0/memc_memc$tb_clk rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/arb_mux0/arb_row_col0/row_arb0/grant_r_3 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/arb_mux0/arb_row_col0/row_arb0/last_master_r_3 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X134Y199.CQ Tcko 0.115 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/sending_row<3> + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/arb_mux0/arb_row_col0/row_arb0/grant_r_3 + SLICE_X134Y200.D5 net (fanout=29) 0.130 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/sending_row<3> + SLICE_X134Y200.CLK Tah (-Th) 0.077 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/arb_mux0/arb_row_col0/row_arb0/last_master_r<3> + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/arb_mux0/arb_row_col0/row_arb0/Mmux_last_master_ns41 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/arb_mux0/arb_row_col0/row_arb0/last_master_r_3 + ------------------------------------------------- --------------------------- + Total 0.168ns (0.038ns logic, 0.130ns route) + (22.6% logic, 77.4% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.065ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/rank_mach0/rank_common0/maint_req_r_lcl (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/rank_mach0/rank_common0/maintenance_request.upd_last_master_r (FF) + Requirement: 0.000ns + Data Path Delay: 0.077ns (Levels of Logic = 1) + Clock Path Skew: 0.012ns (0.065 - 0.053) + Source Clock: ftop/dram0/memc_memc$tb_clk rising at 5.000ns + Destination Clock: ftop/dram0/memc_memc$tb_clk rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/rank_mach0/rank_common0/maint_req_r_lcl to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/rank_mach0/rank_common0/maintenance_request.upd_last_master_r + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X141Y205.DQ Tcko 0.098 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/maint_req_r + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/rank_mach0/rank_common0/maint_req_r_lcl + SLICE_X140Y205.B6 net (fanout=13) 0.056 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/maint_req_r + SLICE_X140Y205.CLK Tah (-Th) 0.077 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/rank_mach0/rank_common0/maintenance_request.upd_last_master_r + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/rank_mach0/rank_common0/maintenance_request.upd_last_master_ns_norst1 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/rank_mach0/rank_common0/maintenance_request.upd_last_master_r + ------------------------------------------------- --------------------------- + Total 0.077ns (0.021ns logic, 0.056ns route) + (27.3% logic, 72.7% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.066ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_init/cnt_pwron_r_7 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_init/cnt_pwron_reset_done_r (FF) + Requirement: 0.000ns + Data Path Delay: 0.076ns (Levels of Logic = 1) + Clock Path Skew: 0.010ns (0.057 - 0.047) + Source Clock: ftop/dram0/memc_memc$tb_clk rising at 5.000ns + Destination Clock: ftop/dram0/memc_memc$tb_clk rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_init/cnt_pwron_r_7 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_init/cnt_pwron_reset_done_r + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X131Y214.DQ Tcko 0.098 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_init/cnt_pwron_r<7> + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_init/cnt_pwron_r_7 + SLICE_X130Y214.B6 net (fanout=3) 0.055 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_init/cnt_pwron_r<7> + SLICE_X130Y214.CLK Tah (-Th) 0.077 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_init/cnt_pwron_reset_done_r + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_init/GND_117_o_GND_117_o_equal_85_o<8>2 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_init/cnt_pwron_reset_done_r + ------------------------------------------------- --------------------------- + Total 0.076ns (0.021ns logic, 0.055ns route) + (27.6% logic, 72.4% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.067ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[41].u_iob_dq/wr_data_rise1_r3 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[41].u_iob_dq/ocb_d1 (FF) + Requirement: 0.000ns + Data Path Delay: 0.180ns (Levels of Logic = 1) + Clock Path Skew: 0.113ns (0.800 - 0.687) + Source Clock: ftop/dram0/memc_memc$tb_clk rising at 5.000ns + Destination Clock: ftop/dram0/memc_memc$tb_clk rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[41].u_iob_dq/wr_data_rise1_r3 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[41].u_iob_dq/ocb_d1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X69Y159.CQ Tcko 0.098 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[41].u_iob_dq/wr_data_rise1_r3 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[41].u_iob_dq/wr_data_rise1_r3 + SLICE_X68Y160.C5 net (fanout=1) 0.113 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[41].u_iob_dq/wr_data_rise1_r3 + SLICE_X68Y160.CLK Tah (-Th) 0.031 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[41].u_iob_dq/ocb_d1 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[41].u_iob_dq/Mmux_wr_calib_dly[1]_wr_data_rise1_r3_Mux_2_o_3 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[41].u_iob_dq/Mmux_wr_calib_dly[1]_wr_data_rise1_r3_Mux_2_o_2_f7 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[41].u_iob_dq/ocb_d1 + ------------------------------------------------- --------------------------- + Total 0.180ns (0.067ns logic, 0.113ns route) + (37.2% logic, 62.8% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.072ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/cal2_rd_active_dly_r_4 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/dbg_rd_active_dly_4 (FF) + Requirement: 0.000ns + Data Path Delay: 0.083ns (Levels of Logic = 0) + Clock Path Skew: 0.011ns (0.060 - 0.049) + Source Clock: ftop/dram0/memc_memc$tb_clk rising at 5.000ns + Destination Clock: ftop/dram0/memc_memc$tb_clk rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/cal2_rd_active_dly_r_4 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/dbg_rd_active_dly_4 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X123Y187.AQ Tcko 0.098 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/cal2_rd_active_dly_r<4> + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/cal2_rd_active_dly_r_4 + SLICE_X122Y187.AX net (fanout=1) 0.098 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/cal2_rd_active_dly_r<4> + SLICE_X122Y187.CLK Tckdi (-Th) 0.113 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_phy_pd<106> + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/dbg_rd_active_dly_4 + ------------------------------------------------- --------------------------- + Total 0.083ns (-0.015ns logic, 0.098ns route) + (-18.1% logic, 118.1% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.072ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/app_wdf_mask_r1_22 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[46].RAM32M0_RAMB (RAM) + Requirement: 0.000ns + Data Path Delay: 0.107ns (Levels of Logic = 0) + Clock Path Skew: 0.035ns (0.490 - 0.455) + Source Clock: ftop/dram0/memc_memc$tb_clk rising at 5.000ns + Destination Clock: ftop/dram0/memc_memc$tb_clk rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/app_wdf_mask_r1_22 to ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[46].RAM32M0_RAMB + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X103Y141.AQ Tcko 0.098 ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/app_wdf_mask_r1<25> + ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/app_wdf_mask_r1_22 + SLICE_X100Y141.BI net (fanout=1) 0.095 ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/app_wdf_mask_r1<22> + SLICE_X100Y141.CLK Tdh (-Th) 0.086 ftop/dram0/memc_memc/u_memc_ui_top/wr_data_mask<21> + ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[46].RAM32M0_RAMB + ------------------------------------------------- --------------------------- + Total 0.107ns (0.012ns logic, 0.095ns route) + (11.2% logic, 88.8% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.073ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_init/enable_wrlvl_cnt_1 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_init/wrlvl_active (FF) + Requirement: 0.000ns + Data Path Delay: 0.085ns (Levels of Logic = 1) + Clock Path Skew: 0.012ns (0.066 - 0.054) + Source Clock: ftop/dram0/memc_memc$tb_clk rising at 5.000ns + Destination Clock: ftop/dram0/memc_memc$tb_clk rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_init/enable_wrlvl_cnt_1 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_init/wrlvl_active + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X129Y202.BQ Tcko 0.098 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_init/enable_wrlvl_cnt<3> + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_init/enable_wrlvl_cnt_1 + SLICE_X128Y202.A6 net (fanout=7) 0.063 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_init/enable_wrlvl_cnt<1> + SLICE_X128Y202.CLK Tah (-Th) 0.076 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/wrlvl_active + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_init/wrlvl_active_glue_set + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_init/wrlvl_active + ------------------------------------------------- --------------------------- + Total 0.085ns (0.022ns logic, 0.063ns route) + (25.9% logic, 74.1% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.074ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/app_wdf_mask_r1_8 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[44].RAM32M0_RAMC (RAM) + Requirement: 0.000ns + Data Path Delay: 0.109ns (Levels of Logic = 0) + Clock Path Skew: 0.035ns (0.494 - 0.459) + Source Clock: ftop/dram0/memc_memc$tb_clk rising at 5.000ns + Destination Clock: ftop/dram0/memc_memc$tb_clk rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/app_wdf_mask_r1_8 to ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[44].RAM32M0_RAMC + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X103Y144.BQ Tcko 0.098 ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/app_wdf_mask_r1<10> + ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/app_wdf_mask_r1_8 + SLICE_X100Y144.CI net (fanout=1) 0.096 ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/app_wdf_mask_r1<8> + SLICE_X100Y144.CLK Tdh (-Th) 0.085 ftop/dram0/memc_memc/u_memc_ui_top/wr_data_mask<9> + ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[44].RAM32M0_RAMC + ------------------------------------------------- --------------------------- + Total 0.109ns (0.013ns logic, 0.096ns route) + (11.9% logic, 88.1% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.075ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/cal2_dly_cnt_delta_r<1>_3 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/cal2_clkdly_cnt_r_3 (FF) + Requirement: 0.000ns + Data Path Delay: 0.114ns (Levels of Logic = 1) + Clock Path Skew: 0.039ns (0.470 - 0.431) + Source Clock: ftop/dram0/memc_memc$tb_clk rising at 5.000ns + Destination Clock: ftop/dram0/memc_memc$tb_clk rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/cal2_dly_cnt_delta_r<1>_3 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/cal2_clkdly_cnt_r_3 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X123Y203.BQ Tcko 0.098 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/cal2_dly_cnt_delta_r<1><4> + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/cal2_dly_cnt_delta_r<1>_3 + SLICE_X120Y203.D6 net (fanout=1) 0.093 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/cal2_dly_cnt_delta_r<1><3> + SLICE_X120Y203.CLK Tah (-Th) 0.077 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/cal2_clkdly_cnt_r_3 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/cal2_dly_cnt_delta_r[1][4]_INV_3551_o1 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/cal2_clkdly_cnt_r_3 + ------------------------------------------------- --------------------------- + Total 0.114ns (0.021ns logic, 0.093ns route) + (18.4% logic, 81.6% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.077ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/read_fifo.head_r_1 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/read_fifo.head_r_4 (FF) + Requirement: 0.000ns + Data Path Delay: 0.086ns (Levels of Logic = 1) + Clock Path Skew: 0.009ns (0.053 - 0.044) + Source Clock: ftop/dram0/memc_memc$tb_clk rising at 5.000ns + Destination Clock: ftop/dram0/memc_memc$tb_clk rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/read_fifo.head_r_1 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/read_fifo.head_r_4 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X119Y182.BQ Tcko 0.098 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/read_fifo.head_r<3> + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/read_fifo.head_r_1 + SLICE_X118Y182.A6 net (fanout=5) 0.064 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/read_fifo.head_r<1> + SLICE_X118Y182.CLK Tah (-Th) 0.076 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/read_fifo.head_r<4> + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/Mcount_read_fifo.head_r_xor<4>11 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/read_fifo.head_r_4 + ------------------------------------------------- --------------------------- + Total 0.086ns (0.022ns logic, 0.064ns route) + (25.6% logic, 74.4% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.077ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/app_wdf_data_r1_196 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[32].RAM32M0_RAMA (RAM) + Requirement: 0.000ns + Data Path Delay: 0.111ns (Levels of Logic = 0) + Clock Path Skew: 0.034ns (0.483 - 0.449) + Source Clock: ftop/dram0/memc_memc$tb_clk rising at 5.000ns + Destination Clock: ftop/dram0/memc_memc$tb_clk rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/app_wdf_data_r1_196 to ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[32].RAM32M0_RAMA + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X109Y136.AQ Tcko 0.098 ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/app_wdf_data_r1<199> + ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/app_wdf_data_r1_196 + SLICE_X110Y135.AI net (fanout=1) 0.100 ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/app_wdf_data_r1<196> + SLICE_X110Y135.CLK Tdh (-Th) 0.087 ftop/dram0/memc_memc/u_memc_ui_top/wr_data<193> + ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[32].RAM32M0_RAMA + ------------------------------------------------- --------------------------- + Total 0.111ns (0.011ns logic, 0.100ns route) + (9.9% logic, 90.1% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.078ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/dram0/lrespF/sGEnqPtr1_2 (FF) + Destination: ftop/dram0/lrespF/sGEnqPtr_2 (FF) + Requirement: 0.000ns + Data Path Delay: 0.114ns (Levels of Logic = 0) + Clock Path Skew: 0.036ns (0.526 - 0.490) + Source Clock: ftop/dram0/memc_memc$tb_clk rising at 5.000ns + Destination Clock: ftop/dram0/memc_memc$tb_clk rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/dram0/lrespF/sGEnqPtr1_2 to ftop/dram0/lrespF/sGEnqPtr_2 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X70Y120.CQ Tcko 0.098 ftop/dram0/lrespF/sGEnqPtr1<2> + ftop/dram0/lrespF/sGEnqPtr1_2 + SLICE_X68Y120.CX net (fanout=3) 0.105 ftop/dram0/lrespF/sGEnqPtr1<2> + SLICE_X68Y120.CLK Tckdi (-Th) 0.089 ftop/dram0/lrespF/sGEnqPtr<2> + ftop/dram0/lrespF/sGEnqPtr_2 + ------------------------------------------------- --------------------------- + Total 0.114ns (0.009ns logic, 0.105ns route) + (7.9% logic, 92.1% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.079ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/prev_sr_fall0_r_16 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/prev_match_fall0_r_6 (FF) + Requirement: 0.000ns + Data Path Delay: 0.114ns (Levels of Logic = 1) + Clock Path Skew: 0.035ns (0.456 - 0.421) + Source Clock: ftop/dram0/memc_memc$tb_clk rising at 5.000ns + Destination Clock: ftop/dram0/memc_memc$tb_clk rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/prev_sr_fall0_r_16 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/prev_match_fall0_r_6 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X125Y185.CQ Tcko 0.098 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/prev_sr_fall0_r_17 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/prev_sr_fall0_r_16 + SLICE_X126Y185.C6 net (fanout=1) 0.092 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/prev_sr_fall0_r_16 + SLICE_X126Y185.CLK Tah (-Th) 0.076 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/prev_match_fall0_r_7 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/sr_fall0_r[6][1]_prev_sr_fall0_r[6][1]_equal_315_o21 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/prev_match_fall0_r_6 + ------------------------------------------------- --------------------------- + Total 0.114ns (0.022ns logic, 0.092ns route) + (19.3% logic, 80.7% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.080ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/cal2_clkdly_cnt_r_11 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/dbg_rd_clkdly_cnt_11 (FF) + Requirement: 0.000ns + Data Path Delay: 0.118ns (Levels of Logic = 0) + Clock Path Skew: 0.038ns (0.493 - 0.455) + Source Clock: ftop/dram0/memc_memc$tb_clk rising at 5.000ns + Destination Clock: ftop/dram0/memc_memc$tb_clk rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/cal2_clkdly_cnt_r_11 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/dbg_rd_clkdly_cnt_11 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X111Y207.DQ Tcko 0.098 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/cal2_clkdly_cnt_r_11 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/cal2_clkdly_cnt_r_11 + SLICE_X109Y207.DX net (fanout=1) 0.096 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/cal2_clkdly_cnt_r_11 + SLICE_X109Y207.CLK Tckdi (-Th) 0.076 ftop/dram0/memc_memc/dbg_rd_clkdly_cnt<11> + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/dbg_rd_clkdly_cnt_11 + ------------------------------------------------- --------------------------- + Total 0.118ns (0.022ns logic, 0.096ns route) + (18.6% logic, 81.4% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.080ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/cal2_clkdly_cnt_r_9 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/dbg_rd_clkdly_cnt_9 (FF) + Requirement: 0.000ns + Data Path Delay: 0.118ns (Levels of Logic = 0) + Clock Path Skew: 0.038ns (0.493 - 0.455) + Source Clock: ftop/dram0/memc_memc$tb_clk rising at 5.000ns + Destination Clock: ftop/dram0/memc_memc$tb_clk rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/cal2_clkdly_cnt_r_9 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/dbg_rd_clkdly_cnt_9 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X111Y207.BQ Tcko 0.098 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/cal2_clkdly_cnt_r_11 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/cal2_clkdly_cnt_r_9 + SLICE_X109Y207.BX net (fanout=1) 0.096 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/cal2_clkdly_cnt_r_9 + SLICE_X109Y207.CLK Tckdi (-Th) 0.076 ftop/dram0/memc_memc/dbg_rd_clkdly_cnt<11> + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/dbg_rd_clkdly_cnt_9 + ------------------------------------------------- --------------------------- + Total 0.118ns (0.022ns logic, 0.096ns route) + (18.6% logic, 81.4% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.081ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/wc_oserdes_cnt_r_1 (FF) + Destination: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/wc_oserdes_cnt_r_3 (FF) + Requirement: 0.000ns + Data Path Delay: 0.189ns (Levels of Logic = 1) + Clock Path Skew: 0.108ns (0.807 - 0.699) + Source Clock: ftop/dram0/memc_memc$tb_clk rising at 5.000ns + Destination Clock: ftop/dram0/memc_memc$tb_clk rising at 5.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/wc_oserdes_cnt_r_1 to ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/wc_oserdes_cnt_r_3 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X88Y159.BQ Tcko 0.115 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/wc_oserdes_cnt_r<2> + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/wc_oserdes_cnt_r_1 + SLICE_X88Y160.C4 net (fanout=5) 0.150 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/wc_oserdes_cnt_r<1> + SLICE_X88Y160.CLK Tah (-Th) 0.076 ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/wc_oserdes_cnt_r<3> + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/Mcount_wc_oserdes_cnt_r_xor<3>1 + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/wc_oserdes_cnt_r_3 + ------------------------------------------------- --------------------------- + Total 0.189ns (0.039ns logic, 0.150ns route) + (20.6% logic, 79.4% route) + +-------------------------------------------------------------------------------- + +Component Switching Limit Checks: TS_ftop_dram0_memc_memc_u_infrastructure_clk_pll = PERIOD TIMEGRP + "ftop_dram0_memc_memc_u_infrastructure_clk_pll" TS_SYS0CLK HIGH 50%; +-------------------------------------------------------------------------------- +Slack: 3.000ns (period - (min low pulse limit / (low pulse / period))) + Period: 5.000ns + Low pulse: 2.500ns + Low pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/dram0/lrespF/_n0091<35>/CLK + Logical resource: ftop/dram0/lrespF/Mram_fifoMem6_RAMA/CLK + Location pin: SLICE_X56Y121.CLK + Clock network: ftop/dram0/memc_memc$tb_clk +-------------------------------------------------------------------------------- +Slack: 3.000ns (period - (min high pulse limit / (high pulse / period))) + Period: 5.000ns + High pulse: 2.500ns + High pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/dram0/lrespF/_n0091<35>/CLK + Logical resource: ftop/dram0/lrespF/Mram_fifoMem6_RAMA/CLK + Location pin: SLICE_X56Y121.CLK + Clock network: ftop/dram0/memc_memc$tb_clk +-------------------------------------------------------------------------------- +Slack: 3.000ns (period - (min low pulse limit / (low pulse / period))) + Period: 5.000ns + Low pulse: 2.500ns + Low pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/dram0/lrespF/_n0091<35>/CLK + Logical resource: ftop/dram0/lrespF/Mram_fifoMem6_RAMA_D1/CLK + Location pin: SLICE_X56Y121.CLK + Clock network: ftop/dram0/memc_memc$tb_clk +-------------------------------------------------------------------------------- +Slack: 3.000ns (period - (min high pulse limit / (high pulse / period))) + Period: 5.000ns + High pulse: 2.500ns + High pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/dram0/lrespF/_n0091<35>/CLK + Logical resource: ftop/dram0/lrespF/Mram_fifoMem6_RAMA_D1/CLK + Location pin: SLICE_X56Y121.CLK + Clock network: ftop/dram0/memc_memc$tb_clk +-------------------------------------------------------------------------------- +Slack: 3.000ns (period - (min low pulse limit / (low pulse / period))) + Period: 5.000ns + Low pulse: 2.500ns + Low pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/dram0/lrespF/_n0091<35>/CLK + Logical resource: ftop/dram0/lrespF/Mram_fifoMem6_RAMB/CLK + Location pin: SLICE_X56Y121.CLK + Clock network: ftop/dram0/memc_memc$tb_clk +-------------------------------------------------------------------------------- +Slack: 3.000ns (period - (min high pulse limit / (high pulse / period))) + Period: 5.000ns + High pulse: 2.500ns + High pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/dram0/lrespF/_n0091<35>/CLK + Logical resource: ftop/dram0/lrespF/Mram_fifoMem6_RAMB/CLK + Location pin: SLICE_X56Y121.CLK + Clock network: ftop/dram0/memc_memc$tb_clk +-------------------------------------------------------------------------------- +Slack: 3.000ns (period - (min low pulse limit / (low pulse / period))) + Period: 5.000ns + Low pulse: 2.500ns + Low pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/dram0/lrespF/_n0091<35>/CLK + Logical resource: ftop/dram0/lrespF/Mram_fifoMem6_RAMB_D1/CLK + Location pin: SLICE_X56Y121.CLK + Clock network: ftop/dram0/memc_memc$tb_clk +-------------------------------------------------------------------------------- +Slack: 3.000ns (period - (min high pulse limit / (high pulse / period))) + Period: 5.000ns + High pulse: 2.500ns + High pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/dram0/lrespF/_n0091<35>/CLK + Logical resource: ftop/dram0/lrespF/Mram_fifoMem6_RAMB_D1/CLK + Location pin: SLICE_X56Y121.CLK + Clock network: ftop/dram0/memc_memc$tb_clk +-------------------------------------------------------------------------------- +Slack: 3.000ns (period - (min low pulse limit / (low pulse / period))) + Period: 5.000ns + Low pulse: 2.500ns + Low pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/dram0/lrespF/_n0091<35>/CLK + Logical resource: ftop/dram0/lrespF/Mram_fifoMem6_RAMC/CLK + Location pin: SLICE_X56Y121.CLK + Clock network: ftop/dram0/memc_memc$tb_clk +-------------------------------------------------------------------------------- +Slack: 3.000ns (period - (min high pulse limit / (high pulse / period))) + Period: 5.000ns + High pulse: 2.500ns + High pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/dram0/lrespF/_n0091<35>/CLK + Logical resource: ftop/dram0/lrespF/Mram_fifoMem6_RAMC/CLK + Location pin: SLICE_X56Y121.CLK + Clock network: ftop/dram0/memc_memc$tb_clk +-------------------------------------------------------------------------------- +Slack: 3.000ns (period - (min low pulse limit / (low pulse / period))) + Period: 5.000ns + Low pulse: 2.500ns + Low pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/dram0/lrespF/_n0091<35>/CLK + Logical resource: ftop/dram0/lrespF/Mram_fifoMem6_RAMC_D1/CLK + Location pin: SLICE_X56Y121.CLK + Clock network: ftop/dram0/memc_memc$tb_clk +-------------------------------------------------------------------------------- +Slack: 3.000ns (period - (min high pulse limit / (high pulse / period))) + Period: 5.000ns + High pulse: 2.500ns + High pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/dram0/lrespF/_n0091<35>/CLK + Logical resource: ftop/dram0/lrespF/Mram_fifoMem6_RAMC_D1/CLK + Location pin: SLICE_X56Y121.CLK + Clock network: ftop/dram0/memc_memc$tb_clk +-------------------------------------------------------------------------------- +Slack: 3.000ns (period - (min low pulse limit / (low pulse / period))) + Period: 5.000ns + Low pulse: 2.500ns + Low pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/dram0/lrespF/_n0091<35>/CLK + Logical resource: ftop/dram0/lrespF/Mram_fifoMem6_RAMD/CLK + Location pin: SLICE_X56Y121.CLK + Clock network: ftop/dram0/memc_memc$tb_clk +-------------------------------------------------------------------------------- +Slack: 3.000ns (period - (min high pulse limit / (high pulse / period))) + Period: 5.000ns + High pulse: 2.500ns + High pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/dram0/lrespF/_n0091<35>/CLK + Logical resource: ftop/dram0/lrespF/Mram_fifoMem6_RAMD/CLK + Location pin: SLICE_X56Y121.CLK + Clock network: ftop/dram0/memc_memc$tb_clk +-------------------------------------------------------------------------------- +Slack: 3.000ns (period - (min low pulse limit / (low pulse / period))) + Period: 5.000ns + Low pulse: 2.500ns + Low pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/dram0/lrespF/_n0091<35>/CLK + Logical resource: ftop/dram0/lrespF/Mram_fifoMem6_RAMD_D1/CLK + Location pin: SLICE_X56Y121.CLK + Clock network: ftop/dram0/memc_memc$tb_clk +-------------------------------------------------------------------------------- +Slack: 3.000ns (period - (min high pulse limit / (high pulse / period))) + Period: 5.000ns + High pulse: 2.500ns + High pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/dram0/lrespF/_n0091<35>/CLK + Logical resource: ftop/dram0/lrespF/Mram_fifoMem6_RAMD_D1/CLK + Location pin: SLICE_X56Y121.CLK + Clock network: ftop/dram0/memc_memc$tb_clk +-------------------------------------------------------------------------------- +Slack: 3.000ns (period - (min low pulse limit / (low pulse / period))) + Period: 5.000ns + Low pulse: 2.500ns + Low pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/dram0/lrespF/_n0091<125>/CLK + Logical resource: ftop/dram0/lrespF/Mram_fifoMem21_RAMA/CLK + Location pin: SLICE_X60Y105.CLK + Clock network: ftop/dram0/memc_memc$tb_clk +-------------------------------------------------------------------------------- +Slack: 3.000ns (period - (min high pulse limit / (high pulse / period))) + Period: 5.000ns + High pulse: 2.500ns + High pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/dram0/lrespF/_n0091<125>/CLK + Logical resource: ftop/dram0/lrespF/Mram_fifoMem21_RAMA/CLK + Location pin: SLICE_X60Y105.CLK + Clock network: ftop/dram0/memc_memc$tb_clk +-------------------------------------------------------------------------------- +Slack: 3.000ns (period - (min low pulse limit / (low pulse / period))) + Period: 5.000ns + Low pulse: 2.500ns + Low pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/dram0/lrespF/_n0091<125>/CLK + Logical resource: ftop/dram0/lrespF/Mram_fifoMem21_RAMA_D1/CLK + Location pin: SLICE_X60Y105.CLK + Clock network: ftop/dram0/memc_memc$tb_clk +-------------------------------------------------------------------------------- +Slack: 3.000ns (period - (min high pulse limit / (high pulse / period))) + Period: 5.000ns + High pulse: 2.500ns + High pulse limit: 1.000ns (Tmpw) + Physical resource: ftop/dram0/lrespF/_n0091<125>/CLK + Logical resource: ftop/dram0/lrespF/Mram_fifoMem21_RAMA_D1/CLK + Location pin: SLICE_X60Y105.CLK + Clock network: ftop/dram0/memc_memc$tb_clk +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: TS_ftop_dram0_memc_memc_u_infrastructure_clk_mem_pll = +PERIOD TIMEGRP "ftop_dram0_memc_memc_u_infrastructure_clk_mem_pll" +TS_SYS0CLK * 2 HIGH 50%; +For more information, see Period Analysis in the Timing Closure User Guide (UG612). + + 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints + 0 timing errors detected. (0 component switching limit errors) + Minimum period is 1.429ns. +-------------------------------------------------------------------------------- + +Component Switching Limit Checks: TS_ftop_dram0_memc_memc_u_infrastructure_clk_mem_pll = PERIOD TIMEGRP + "ftop_dram0_memc_memc_u_infrastructure_clk_mem_pll" TS_SYS0CLK * 2 + HIGH 50%; +-------------------------------------------------------------------------------- +Slack: 1.071ns (period - min period limit) + Period: 2.500ns + Min period limit: 1.429ns (699.790MHz) (Tbcper_I) + Physical resource: ftop/dram0/memc_memc/u_infrastructure/u_bufg_clk0/I0 + Logical resource: ftop/dram0/memc_memc/u_infrastructure/u_bufg_clk0/I0 + Location pin: BUFGCTRL_X0Y26.I0 + Clock network: ftop/dram0/memc_memc/u_infrastructure/clk_mem_pll +-------------------------------------------------------------------------------- +Slack: 997.500ns (max period limit - period) + Period: 2.500ns + Max period limit: 1000.000ns (1.000MHz) (Tbcper_I) + Physical resource: ftop/dram0/memc_memc/u_infrastructure/u_bufg_clk0/I0 + Logical resource: ftop/dram0/memc_memc/u_infrastructure/u_bufg_clk0/I0 + Location pin: BUFGCTRL_X0Y26.I0 + Clock network: ftop/dram0/memc_memc/u_infrastructure/clk_mem_pll +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: TS_ftop_dram0_memc_memc_clk_wr_i = PERIOD TIMEGRP +"ftop_dram0_memc_memc_clk_wr_i" TS_SYS0CLK * 2 HIGH 50%; +For more information, see Period Analysis in the Timing Closure User Guide (UG612). + + 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints + 0 timing errors detected. (0 component switching limit errors) +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "gmii_rxd<7>" OFFSET = IN 0.5 ns VALID 3 ns BEFORE COMP +"gmii_rx_clk"; +For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). + + 1 path analyzed, 1 endpoint analyzed, 0 failing endpoints + 0 timing errors detected. (0 setup errors, 0 hold errors) + Offset is -0.167ns. +-------------------------------------------------------------------------------- +Slack (setup path): 0.667ns (requirement - (data path - clock path - clock arrival + uncertainty)) + Source: gmii_rxd<7> (PAD) + Destination: ftop/gbe0/gmac/rxRS_rxData_7 (FF) + Destination Clock: ftop/rxclkBnd rising at 0.000ns + Requirement: 0.500ns + Data Path Delay: 1.104ns (Levels of Logic = 1) + Clock Path Delay: 1.296ns (Levels of Logic = 3) + Clock Uncertainty: 0.025ns + + Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Fast Process Corner: gmii_rxd<7> to ftop/gbe0/gmac/rxRS_rxData_7 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AC13.I Tiopi 0.369 gmii_rxd<7> + gmii_rxd<7> + gmii_rxd_7_IBUF + SLICE_X90Y38.DX net (fanout=1) 0.731 gmii_rxd_7_IBUF + SLICE_X90Y38.CLK Tdick 0.004 ftop/gbe0/gmac/rxRS_rxData<7> + ftop/gbe0/gmac/rxRS_rxData_7 + ------------------------------------------------- --------------------------- + Total 1.104ns (0.373ns logic, 0.731ns route) + (33.8% logic, 66.2% route) + + Minimum Clock Path at Fast Process Corner: gmii_rx_clk to ftop/gbe0/gmac/rxRS_rxData_7 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AP11.I Tiopi 0.385 gmii_rx_clk + gmii_rx_clk + gmii_rx_clk_IBUF + IODELAY_X2Y57.IDATAINnet (fanout=1) 0.000 gmii_rx_clk_IBUF + IODELAY_X2Y57.DATAOUTTioddo_IDATAIN 0.269 ftop/gbe0/gmac/gmii_rxc_dly + ftop/gbe0/gmac/gmii_rxc_dly + BUFR_X2Y3.I net (fanout=1) 0.141 ftop/gbe0/gmac/gmii_rxc_dly$DATAOUT + BUFR_X2Y3.O Tbrcko_O 0.120 ftop/gbe0/gmac/rxClk_BUFR + ftop/gbe0/gmac/rxClk_BUFR + SLICE_X90Y38.CLK net (fanout=47) 0.381 ftop/rxclkBnd + ------------------------------------------------- --------------------------- + Total 1.296ns (0.774ns logic, 0.522ns route) + (59.7% logic, 40.3% route) + +-------------------------------------------------------------------------------- + +Hold Paths: COMP "gmii_rxd<7>" OFFSET = IN 0.5 ns VALID 3 ns BEFORE COMP "gmii_rx_clk"; +-------------------------------------------------------------------------------- +Slack (hold path): 1.655ns (requirement - (clock path + clock arrival + uncertainty - data path)) + Source: gmii_rxd<7> (PAD) + Destination: ftop/gbe0/gmac/rxRS_rxData_7 (FF) + Destination Clock: ftop/rxclkBnd rising at 0.000ns + Requirement: 2.500ns + Data Path Delay: 1.703ns (Levels of Logic = 1) + Clock Path Delay: 2.523ns (Levels of Logic = 3) + Clock Uncertainty: 0.025ns + + Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Minimum Data Path at Slow Process Corner: gmii_rxd<7> to ftop/gbe0/gmac/rxRS_rxData_7 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AC13.I Tiopi 0.669 gmii_rxd<7> + gmii_rxd<7> + gmii_rxd_7_IBUF + SLICE_X90Y38.DX net (fanout=1) 1.173 gmii_rxd_7_IBUF + SLICE_X90Y38.CLK Tckdi (-Th) 0.139 ftop/gbe0/gmac/rxRS_rxData<7> + ftop/gbe0/gmac/rxRS_rxData_7 + ------------------------------------------------- --------------------------- + Total 1.703ns (0.530ns logic, 1.173ns route) + (31.1% logic, 68.9% route) + + Maximum Clock Path at Slow Process Corner: gmii_rx_clk to ftop/gbe0/gmac/rxRS_rxData_7 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AP11.I Tiopi 0.782 gmii_rx_clk + gmii_rx_clk + gmii_rx_clk_IBUF + IODELAY_X2Y57.IDATAINnet (fanout=1) 0.000 gmii_rx_clk_IBUF + IODELAY_X2Y57.DATAOUTTioddo_IDATAIN 0.088 ftop/gbe0/gmac/gmii_rxc_dly + ftop/gbe0/gmac/gmii_rxc_dly + BUFR_X2Y3.I net (fanout=1) 0.384 ftop/gbe0/gmac/gmii_rxc_dly$DATAOUT + BUFR_X2Y3.O Tbrcko_O 0.357 ftop/gbe0/gmac/rxClk_BUFR + ftop/gbe0/gmac/rxClk_BUFR + SLICE_X90Y38.CLK net (fanout=47) 0.912 ftop/rxclkBnd + ------------------------------------------------- --------------------------- + Total 2.523ns (1.227ns logic, 1.296ns route) + (48.6% logic, 51.4% route) + +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "gmii_rxd<6>" OFFSET = IN 0.5 ns VALID 3 ns BEFORE COMP +"gmii_rx_clk"; +For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). + + 1 path analyzed, 1 endpoint analyzed, 0 failing endpoints + 0 timing errors detected. (0 setup errors, 0 hold errors) + Offset is -0.163ns. +-------------------------------------------------------------------------------- +Slack (setup path): 0.663ns (requirement - (data path - clock path - clock arrival + uncertainty)) + Source: gmii_rxd<6> (PAD) + Destination: ftop/gbe0/gmac/rxRS_rxData_6 (FF) + Destination Clock: ftop/rxclkBnd rising at 0.000ns + Requirement: 0.500ns + Data Path Delay: 1.108ns (Levels of Logic = 1) + Clock Path Delay: 1.296ns (Levels of Logic = 3) + Clock Uncertainty: 0.025ns + + Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Fast Process Corner: gmii_rxd<6> to ftop/gbe0/gmac/rxRS_rxData_6 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AC12.I Tiopi 0.374 gmii_rxd<6> + gmii_rxd<6> + gmii_rxd_6_IBUF + SLICE_X90Y38.CX net (fanout=1) 0.730 gmii_rxd_6_IBUF + SLICE_X90Y38.CLK Tdick 0.004 ftop/gbe0/gmac/rxRS_rxData<7> + ftop/gbe0/gmac/rxRS_rxData_6 + ------------------------------------------------- --------------------------- + Total 1.108ns (0.378ns logic, 0.730ns route) + (34.1% logic, 65.9% route) + + Minimum Clock Path at Fast Process Corner: gmii_rx_clk to ftop/gbe0/gmac/rxRS_rxData_6 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AP11.I Tiopi 0.385 gmii_rx_clk + gmii_rx_clk + gmii_rx_clk_IBUF + IODELAY_X2Y57.IDATAINnet (fanout=1) 0.000 gmii_rx_clk_IBUF + IODELAY_X2Y57.DATAOUTTioddo_IDATAIN 0.269 ftop/gbe0/gmac/gmii_rxc_dly + ftop/gbe0/gmac/gmii_rxc_dly + BUFR_X2Y3.I net (fanout=1) 0.141 ftop/gbe0/gmac/gmii_rxc_dly$DATAOUT + BUFR_X2Y3.O Tbrcko_O 0.120 ftop/gbe0/gmac/rxClk_BUFR + ftop/gbe0/gmac/rxClk_BUFR + SLICE_X90Y38.CLK net (fanout=47) 0.381 ftop/rxclkBnd + ------------------------------------------------- --------------------------- + Total 1.296ns (0.774ns logic, 0.522ns route) + (59.7% logic, 40.3% route) + +-------------------------------------------------------------------------------- + +Hold Paths: COMP "gmii_rxd<6>" OFFSET = IN 0.5 ns VALID 3 ns BEFORE COMP "gmii_rx_clk"; +-------------------------------------------------------------------------------- +Slack (hold path): 1.666ns (requirement - (clock path + clock arrival + uncertainty - data path)) + Source: gmii_rxd<6> (PAD) + Destination: ftop/gbe0/gmac/rxRS_rxData_6 (FF) + Destination Clock: ftop/rxclkBnd rising at 0.000ns + Requirement: 2.500ns + Data Path Delay: 1.714ns (Levels of Logic = 1) + Clock Path Delay: 2.523ns (Levels of Logic = 3) + Clock Uncertainty: 0.025ns + + Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Minimum Data Path at Slow Process Corner: gmii_rxd<6> to ftop/gbe0/gmac/rxRS_rxData_6 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AC12.I Tiopi 0.672 gmii_rxd<6> + gmii_rxd<6> + gmii_rxd_6_IBUF + SLICE_X90Y38.CX net (fanout=1) 1.181 gmii_rxd_6_IBUF + SLICE_X90Y38.CLK Tckdi (-Th) 0.139 ftop/gbe0/gmac/rxRS_rxData<7> + ftop/gbe0/gmac/rxRS_rxData_6 + ------------------------------------------------- --------------------------- + Total 1.714ns (0.533ns logic, 1.181ns route) + (31.1% logic, 68.9% route) + + Maximum Clock Path at Slow Process Corner: gmii_rx_clk to ftop/gbe0/gmac/rxRS_rxData_6 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AP11.I Tiopi 0.782 gmii_rx_clk + gmii_rx_clk + gmii_rx_clk_IBUF + IODELAY_X2Y57.IDATAINnet (fanout=1) 0.000 gmii_rx_clk_IBUF + IODELAY_X2Y57.DATAOUTTioddo_IDATAIN 0.088 ftop/gbe0/gmac/gmii_rxc_dly + ftop/gbe0/gmac/gmii_rxc_dly + BUFR_X2Y3.I net (fanout=1) 0.384 ftop/gbe0/gmac/gmii_rxc_dly$DATAOUT + BUFR_X2Y3.O Tbrcko_O 0.357 ftop/gbe0/gmac/rxClk_BUFR + ftop/gbe0/gmac/rxClk_BUFR + SLICE_X90Y38.CLK net (fanout=47) 0.912 ftop/rxclkBnd + ------------------------------------------------- --------------------------- + Total 2.523ns (1.227ns logic, 1.296ns route) + (48.6% logic, 51.4% route) + +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "gmii_rxd<5>" OFFSET = IN 0.5 ns VALID 3 ns BEFORE COMP +"gmii_rx_clk"; +For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). + + 1 path analyzed, 1 endpoint analyzed, 0 failing endpoints + 0 timing errors detected. (0 setup errors, 0 hold errors) + Offset is -0.212ns. +-------------------------------------------------------------------------------- +Slack (setup path): 0.712ns (requirement - (data path - clock path - clock arrival + uncertainty)) + Source: gmii_rxd<5> (PAD) + Destination: ftop/gbe0/gmac/rxRS_rxData_5 (FF) + Destination Clock: ftop/rxclkBnd rising at 0.000ns + Requirement: 0.500ns + Data Path Delay: 1.059ns (Levels of Logic = 1) + Clock Path Delay: 1.296ns (Levels of Logic = 3) + Clock Uncertainty: 0.025ns + + Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Fast Process Corner: gmii_rxd<5> to ftop/gbe0/gmac/rxRS_rxData_5 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AD11.I Tiopi 0.390 gmii_rxd<5> + gmii_rxd<5> + gmii_rxd_5_IBUF + SLICE_X90Y38.BX net (fanout=1) 0.665 gmii_rxd_5_IBUF + SLICE_X90Y38.CLK Tdick 0.004 ftop/gbe0/gmac/rxRS_rxData<7> + ftop/gbe0/gmac/rxRS_rxData_5 + ------------------------------------------------- --------------------------- + Total 1.059ns (0.394ns logic, 0.665ns route) + (37.2% logic, 62.8% route) + + Minimum Clock Path at Fast Process Corner: gmii_rx_clk to ftop/gbe0/gmac/rxRS_rxData_5 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AP11.I Tiopi 0.385 gmii_rx_clk + gmii_rx_clk + gmii_rx_clk_IBUF + IODELAY_X2Y57.IDATAINnet (fanout=1) 0.000 gmii_rx_clk_IBUF + IODELAY_X2Y57.DATAOUTTioddo_IDATAIN 0.269 ftop/gbe0/gmac/gmii_rxc_dly + ftop/gbe0/gmac/gmii_rxc_dly + BUFR_X2Y3.I net (fanout=1) 0.141 ftop/gbe0/gmac/gmii_rxc_dly$DATAOUT + BUFR_X2Y3.O Tbrcko_O 0.120 ftop/gbe0/gmac/rxClk_BUFR + ftop/gbe0/gmac/rxClk_BUFR + SLICE_X90Y38.CLK net (fanout=47) 0.381 ftop/rxclkBnd + ------------------------------------------------- --------------------------- + Total 1.296ns (0.774ns logic, 0.522ns route) + (59.7% logic, 40.3% route) + +-------------------------------------------------------------------------------- + +Hold Paths: COMP "gmii_rxd<5>" OFFSET = IN 0.5 ns VALID 3 ns BEFORE COMP "gmii_rx_clk"; +-------------------------------------------------------------------------------- +Slack (hold path): 1.614ns (requirement - (clock path + clock arrival + uncertainty - data path)) + Source: gmii_rxd<5> (PAD) + Destination: ftop/gbe0/gmac/rxRS_rxData_5 (FF) + Destination Clock: ftop/rxclkBnd rising at 0.000ns + Requirement: 2.500ns + Data Path Delay: 1.662ns (Levels of Logic = 1) + Clock Path Delay: 2.523ns (Levels of Logic = 3) + Clock Uncertainty: 0.025ns + + Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Minimum Data Path at Slow Process Corner: gmii_rxd<5> to ftop/gbe0/gmac/rxRS_rxData_5 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AD11.I Tiopi 0.686 gmii_rxd<5> + gmii_rxd<5> + gmii_rxd_5_IBUF + SLICE_X90Y38.BX net (fanout=1) 1.115 gmii_rxd_5_IBUF + SLICE_X90Y38.CLK Tckdi (-Th) 0.139 ftop/gbe0/gmac/rxRS_rxData<7> + ftop/gbe0/gmac/rxRS_rxData_5 + ------------------------------------------------- --------------------------- + Total 1.662ns (0.547ns logic, 1.115ns route) + (32.9% logic, 67.1% route) + + Maximum Clock Path at Slow Process Corner: gmii_rx_clk to ftop/gbe0/gmac/rxRS_rxData_5 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AP11.I Tiopi 0.782 gmii_rx_clk + gmii_rx_clk + gmii_rx_clk_IBUF + IODELAY_X2Y57.IDATAINnet (fanout=1) 0.000 gmii_rx_clk_IBUF + IODELAY_X2Y57.DATAOUTTioddo_IDATAIN 0.088 ftop/gbe0/gmac/gmii_rxc_dly + ftop/gbe0/gmac/gmii_rxc_dly + BUFR_X2Y3.I net (fanout=1) 0.384 ftop/gbe0/gmac/gmii_rxc_dly$DATAOUT + BUFR_X2Y3.O Tbrcko_O 0.357 ftop/gbe0/gmac/rxClk_BUFR + ftop/gbe0/gmac/rxClk_BUFR + SLICE_X90Y38.CLK net (fanout=47) 0.912 ftop/rxclkBnd + ------------------------------------------------- --------------------------- + Total 2.523ns (1.227ns logic, 1.296ns route) + (48.6% logic, 51.4% route) + +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "gmii_rxd<4>" OFFSET = IN 0.5 ns VALID 3 ns BEFORE COMP +"gmii_rx_clk"; +For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). + + 1 path analyzed, 1 endpoint analyzed, 0 failing endpoints + 0 timing errors detected. (0 setup errors, 0 hold errors) + Offset is -0.316ns. +-------------------------------------------------------------------------------- +Slack (setup path): 0.816ns (requirement - (data path - clock path - clock arrival + uncertainty)) + Source: gmii_rxd<4> (PAD) + Destination: ftop/gbe0/gmac/rxRS_rxData_4 (FF) + Destination Clock: ftop/rxclkBnd rising at 0.000ns + Requirement: 0.500ns + Data Path Delay: 0.955ns (Levels of Logic = 1) + Clock Path Delay: 1.296ns (Levels of Logic = 3) + Clock Uncertainty: 0.025ns + + Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Fast Process Corner: gmii_rxd<4> to ftop/gbe0/gmac/rxRS_rxData_4 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AM12.I Tiopi 0.433 gmii_rxd<4> + gmii_rxd<4> + gmii_rxd_4_IBUF + SLICE_X90Y38.AX net (fanout=1) 0.518 gmii_rxd_4_IBUF + SLICE_X90Y38.CLK Tdick 0.004 ftop/gbe0/gmac/rxRS_rxData<7> + ftop/gbe0/gmac/rxRS_rxData_4 + ------------------------------------------------- --------------------------- + Total 0.955ns (0.437ns logic, 0.518ns route) + (45.8% logic, 54.2% route) + + Minimum Clock Path at Fast Process Corner: gmii_rx_clk to ftop/gbe0/gmac/rxRS_rxData_4 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AP11.I Tiopi 0.385 gmii_rx_clk + gmii_rx_clk + gmii_rx_clk_IBUF + IODELAY_X2Y57.IDATAINnet (fanout=1) 0.000 gmii_rx_clk_IBUF + IODELAY_X2Y57.DATAOUTTioddo_IDATAIN 0.269 ftop/gbe0/gmac/gmii_rxc_dly + ftop/gbe0/gmac/gmii_rxc_dly + BUFR_X2Y3.I net (fanout=1) 0.141 ftop/gbe0/gmac/gmii_rxc_dly$DATAOUT + BUFR_X2Y3.O Tbrcko_O 0.120 ftop/gbe0/gmac/rxClk_BUFR + ftop/gbe0/gmac/rxClk_BUFR + SLICE_X90Y38.CLK net (fanout=47) 0.381 ftop/rxclkBnd + ------------------------------------------------- --------------------------- + Total 1.296ns (0.774ns logic, 0.522ns route) + (59.7% logic, 40.3% route) + +-------------------------------------------------------------------------------- + +Hold Paths: COMP "gmii_rxd<4>" OFFSET = IN 0.5 ns VALID 3 ns BEFORE COMP "gmii_rx_clk"; +-------------------------------------------------------------------------------- +Slack (hold path): 1.417ns (requirement - (clock path + clock arrival + uncertainty - data path)) + Source: gmii_rxd<4> (PAD) + Destination: ftop/gbe0/gmac/rxRS_rxData_4 (FF) + Destination Clock: ftop/rxclkBnd rising at 0.000ns + Requirement: 2.500ns + Data Path Delay: 1.465ns (Levels of Logic = 1) + Clock Path Delay: 2.523ns (Levels of Logic = 3) + Clock Uncertainty: 0.025ns + + Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Minimum Data Path at Slow Process Corner: gmii_rxd<4> to ftop/gbe0/gmac/rxRS_rxData_4 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AM12.I Tiopi 0.723 gmii_rxd<4> + gmii_rxd<4> + gmii_rxd_4_IBUF + SLICE_X90Y38.AX net (fanout=1) 0.881 gmii_rxd_4_IBUF + SLICE_X90Y38.CLK Tckdi (-Th) 0.139 ftop/gbe0/gmac/rxRS_rxData<7> + ftop/gbe0/gmac/rxRS_rxData_4 + ------------------------------------------------- --------------------------- + Total 1.465ns (0.584ns logic, 0.881ns route) + (39.9% logic, 60.1% route) + + Maximum Clock Path at Slow Process Corner: gmii_rx_clk to ftop/gbe0/gmac/rxRS_rxData_4 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AP11.I Tiopi 0.782 gmii_rx_clk + gmii_rx_clk + gmii_rx_clk_IBUF + IODELAY_X2Y57.IDATAINnet (fanout=1) 0.000 gmii_rx_clk_IBUF + IODELAY_X2Y57.DATAOUTTioddo_IDATAIN 0.088 ftop/gbe0/gmac/gmii_rxc_dly + ftop/gbe0/gmac/gmii_rxc_dly + BUFR_X2Y3.I net (fanout=1) 0.384 ftop/gbe0/gmac/gmii_rxc_dly$DATAOUT + BUFR_X2Y3.O Tbrcko_O 0.357 ftop/gbe0/gmac/rxClk_BUFR + ftop/gbe0/gmac/rxClk_BUFR + SLICE_X90Y38.CLK net (fanout=47) 0.912 ftop/rxclkBnd + ------------------------------------------------- --------------------------- + Total 2.523ns (1.227ns logic, 1.296ns route) + (48.6% logic, 51.4% route) + +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "gmii_rxd<3>" OFFSET = IN 0.5 ns VALID 3 ns BEFORE COMP +"gmii_rx_clk"; +For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). + + 1 path analyzed, 1 endpoint analyzed, 0 failing endpoints + 0 timing errors detected. (0 setup errors, 0 hold errors) + Offset is -0.065ns. +-------------------------------------------------------------------------------- +Slack (setup path): 0.565ns (requirement - (data path - clock path - clock arrival + uncertainty)) + Source: gmii_rxd<3> (PAD) + Destination: ftop/gbe0/gmac/rxRS_rxData_3 (FF) + Destination Clock: ftop/rxclkBnd rising at 0.000ns + Requirement: 0.500ns + Data Path Delay: 1.226ns (Levels of Logic = 1) + Clock Path Delay: 1.316ns (Levels of Logic = 3) + Clock Uncertainty: 0.025ns + + Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Fast Process Corner: gmii_rxd<3> to ftop/gbe0/gmac/rxRS_rxData_3 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AN12.I Tiopi 0.435 gmii_rxd<3> + gmii_rxd<3> + gmii_rxd_3_IBUF + SLICE_X97Y34.DX net (fanout=1) 0.787 gmii_rxd_3_IBUF + SLICE_X97Y34.CLK Tdick 0.004 ftop/gbe0/gmac/rxRS_rxData<3> + ftop/gbe0/gmac/rxRS_rxData_3 + ------------------------------------------------- --------------------------- + Total 1.226ns (0.439ns logic, 0.787ns route) + (35.8% logic, 64.2% route) + + Minimum Clock Path at Fast Process Corner: gmii_rx_clk to ftop/gbe0/gmac/rxRS_rxData_3 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AP11.I Tiopi 0.385 gmii_rx_clk + gmii_rx_clk + gmii_rx_clk_IBUF + IODELAY_X2Y57.IDATAINnet (fanout=1) 0.000 gmii_rx_clk_IBUF + IODELAY_X2Y57.DATAOUTTioddo_IDATAIN 0.269 ftop/gbe0/gmac/gmii_rxc_dly + ftop/gbe0/gmac/gmii_rxc_dly + BUFR_X2Y3.I net (fanout=1) 0.141 ftop/gbe0/gmac/gmii_rxc_dly$DATAOUT + BUFR_X2Y3.O Tbrcko_O 0.120 ftop/gbe0/gmac/rxClk_BUFR + ftop/gbe0/gmac/rxClk_BUFR + SLICE_X97Y34.CLK net (fanout=47) 0.401 ftop/rxclkBnd + ------------------------------------------------- --------------------------- + Total 1.316ns (0.774ns logic, 0.542ns route) + (58.8% logic, 41.2% route) + +-------------------------------------------------------------------------------- + +Hold Paths: COMP "gmii_rxd<3>" OFFSET = IN 0.5 ns VALID 3 ns BEFORE COMP "gmii_rx_clk"; +-------------------------------------------------------------------------------- +Slack (hold path): 1.692ns (requirement - (clock path + clock arrival + uncertainty - data path)) + Source: gmii_rxd<3> (PAD) + Destination: ftop/gbe0/gmac/rxRS_rxData_3 (FF) + Destination Clock: ftop/rxclkBnd rising at 0.000ns + Requirement: 2.500ns + Data Path Delay: 1.786ns (Levels of Logic = 1) + Clock Path Delay: 2.569ns (Levels of Logic = 3) + Clock Uncertainty: 0.025ns + + Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Minimum Data Path at Slow Process Corner: gmii_rxd<3> to ftop/gbe0/gmac/rxRS_rxData_3 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AN12.I Tiopi 0.725 gmii_rxd<3> + gmii_rxd<3> + gmii_rxd_3_IBUF + SLICE_X97Y34.DX net (fanout=1) 1.200 gmii_rxd_3_IBUF + SLICE_X97Y34.CLK Tckdi (-Th) 0.139 ftop/gbe0/gmac/rxRS_rxData<3> + ftop/gbe0/gmac/rxRS_rxData_3 + ------------------------------------------------- --------------------------- + Total 1.786ns (0.586ns logic, 1.200ns route) + (32.8% logic, 67.2% route) + + Maximum Clock Path at Slow Process Corner: gmii_rx_clk to ftop/gbe0/gmac/rxRS_rxData_3 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AP11.I Tiopi 0.782 gmii_rx_clk + gmii_rx_clk + gmii_rx_clk_IBUF + IODELAY_X2Y57.IDATAINnet (fanout=1) 0.000 gmii_rx_clk_IBUF + IODELAY_X2Y57.DATAOUTTioddo_IDATAIN 0.088 ftop/gbe0/gmac/gmii_rxc_dly + ftop/gbe0/gmac/gmii_rxc_dly + BUFR_X2Y3.I net (fanout=1) 0.384 ftop/gbe0/gmac/gmii_rxc_dly$DATAOUT + BUFR_X2Y3.O Tbrcko_O 0.357 ftop/gbe0/gmac/rxClk_BUFR + ftop/gbe0/gmac/rxClk_BUFR + SLICE_X97Y34.CLK net (fanout=47) 0.958 ftop/rxclkBnd + ------------------------------------------------- --------------------------- + Total 2.569ns (1.227ns logic, 1.342ns route) + (47.8% logic, 52.2% route) + +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "gmii_rxd<2>" OFFSET = IN 0.5 ns VALID 3 ns BEFORE COMP +"gmii_rx_clk"; +For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). + + 1 path analyzed, 1 endpoint analyzed, 0 failing endpoints + 0 timing errors detected. (0 setup errors, 0 hold errors) + Offset is -0.141ns. +-------------------------------------------------------------------------------- +Slack (setup path): 0.641ns (requirement - (data path - clock path - clock arrival + uncertainty)) + Source: gmii_rxd<2> (PAD) + Destination: ftop/gbe0/gmac/rxRS_rxData_2 (FF) + Destination Clock: ftop/rxclkBnd rising at 0.000ns + Requirement: 0.500ns + Data Path Delay: 1.150ns (Levels of Logic = 1) + Clock Path Delay: 1.316ns (Levels of Logic = 3) + Clock Uncertainty: 0.025ns + + Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Fast Process Corner: gmii_rxd<2> to ftop/gbe0/gmac/rxRS_rxData_2 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AE14.I Tiopi 0.375 gmii_rxd<2> + gmii_rxd<2> + gmii_rxd_2_IBUF + SLICE_X97Y34.CX net (fanout=1) 0.771 gmii_rxd_2_IBUF + SLICE_X97Y34.CLK Tdick 0.004 ftop/gbe0/gmac/rxRS_rxData<3> + ftop/gbe0/gmac/rxRS_rxData_2 + ------------------------------------------------- --------------------------- + Total 1.150ns (0.379ns logic, 0.771ns route) + (33.0% logic, 67.0% route) + + Minimum Clock Path at Fast Process Corner: gmii_rx_clk to ftop/gbe0/gmac/rxRS_rxData_2 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AP11.I Tiopi 0.385 gmii_rx_clk + gmii_rx_clk + gmii_rx_clk_IBUF + IODELAY_X2Y57.IDATAINnet (fanout=1) 0.000 gmii_rx_clk_IBUF + IODELAY_X2Y57.DATAOUTTioddo_IDATAIN 0.269 ftop/gbe0/gmac/gmii_rxc_dly + ftop/gbe0/gmac/gmii_rxc_dly + BUFR_X2Y3.I net (fanout=1) 0.141 ftop/gbe0/gmac/gmii_rxc_dly$DATAOUT + BUFR_X2Y3.O Tbrcko_O 0.120 ftop/gbe0/gmac/rxClk_BUFR + ftop/gbe0/gmac/rxClk_BUFR + SLICE_X97Y34.CLK net (fanout=47) 0.401 ftop/rxclkBnd + ------------------------------------------------- --------------------------- + Total 1.316ns (0.774ns logic, 0.542ns route) + (58.8% logic, 41.2% route) + +-------------------------------------------------------------------------------- + +Hold Paths: COMP "gmii_rxd<2>" OFFSET = IN 0.5 ns VALID 3 ns BEFORE COMP "gmii_rx_clk"; +-------------------------------------------------------------------------------- +Slack (hold path): 1.653ns (requirement - (clock path + clock arrival + uncertainty - data path)) + Source: gmii_rxd<2> (PAD) + Destination: ftop/gbe0/gmac/rxRS_rxData_2 (FF) + Destination Clock: ftop/rxclkBnd rising at 0.000ns + Requirement: 2.500ns + Data Path Delay: 1.747ns (Levels of Logic = 1) + Clock Path Delay: 2.569ns (Levels of Logic = 3) + Clock Uncertainty: 0.025ns + + Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Minimum Data Path at Slow Process Corner: gmii_rxd<2> to ftop/gbe0/gmac/rxRS_rxData_2 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AE14.I Tiopi 0.673 gmii_rxd<2> + gmii_rxd<2> + gmii_rxd_2_IBUF + SLICE_X97Y34.CX net (fanout=1) 1.213 gmii_rxd_2_IBUF + SLICE_X97Y34.CLK Tckdi (-Th) 0.139 ftop/gbe0/gmac/rxRS_rxData<3> + ftop/gbe0/gmac/rxRS_rxData_2 + ------------------------------------------------- --------------------------- + Total 1.747ns (0.534ns logic, 1.213ns route) + (30.6% logic, 69.4% route) + + Maximum Clock Path at Slow Process Corner: gmii_rx_clk to ftop/gbe0/gmac/rxRS_rxData_2 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AP11.I Tiopi 0.782 gmii_rx_clk + gmii_rx_clk + gmii_rx_clk_IBUF + IODELAY_X2Y57.IDATAINnet (fanout=1) 0.000 gmii_rx_clk_IBUF + IODELAY_X2Y57.DATAOUTTioddo_IDATAIN 0.088 ftop/gbe0/gmac/gmii_rxc_dly + ftop/gbe0/gmac/gmii_rxc_dly + BUFR_X2Y3.I net (fanout=1) 0.384 ftop/gbe0/gmac/gmii_rxc_dly$DATAOUT + BUFR_X2Y3.O Tbrcko_O 0.357 ftop/gbe0/gmac/rxClk_BUFR + ftop/gbe0/gmac/rxClk_BUFR + SLICE_X97Y34.CLK net (fanout=47) 0.958 ftop/rxclkBnd + ------------------------------------------------- --------------------------- + Total 2.569ns (1.227ns logic, 1.342ns route) + (47.8% logic, 52.2% route) + +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "gmii_rxd<1>" OFFSET = IN 0.5 ns VALID 3 ns BEFORE COMP +"gmii_rx_clk"; +For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). + + 1 path analyzed, 1 endpoint analyzed, 0 failing endpoints + 0 timing errors detected. (0 setup errors, 0 hold errors) + Minimum allowable offset is 0.276ns. +-------------------------------------------------------------------------------- +Slack (setup path): 0.224ns (requirement - (data path - clock path - clock arrival + uncertainty)) + Source: gmii_rxd<1> (PAD) + Destination: ftop/gbe0/gmac/rxRS_rxData_1 (FF) + Destination Clock: ftop/rxclkBnd rising at 0.000ns + Requirement: 0.500ns + Data Path Delay: 1.567ns (Levels of Logic = 1) + Clock Path Delay: 1.316ns (Levels of Logic = 3) + Clock Uncertainty: 0.025ns + + Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Fast Process Corner: gmii_rxd<1> to ftop/gbe0/gmac/rxRS_rxData_1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AF14.I Tiopi 0.381 gmii_rxd<1> + gmii_rxd<1> + gmii_rxd_1_IBUF + SLICE_X97Y34.BX net (fanout=1) 1.182 gmii_rxd_1_IBUF + SLICE_X97Y34.CLK Tdick 0.004 ftop/gbe0/gmac/rxRS_rxData<3> + ftop/gbe0/gmac/rxRS_rxData_1 + ------------------------------------------------- --------------------------- + Total 1.567ns (0.385ns logic, 1.182ns route) + (24.6% logic, 75.4% route) + + Minimum Clock Path at Fast Process Corner: gmii_rx_clk to ftop/gbe0/gmac/rxRS_rxData_1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AP11.I Tiopi 0.385 gmii_rx_clk + gmii_rx_clk + gmii_rx_clk_IBUF + IODELAY_X2Y57.IDATAINnet (fanout=1) 0.000 gmii_rx_clk_IBUF + IODELAY_X2Y57.DATAOUTTioddo_IDATAIN 0.269 ftop/gbe0/gmac/gmii_rxc_dly + ftop/gbe0/gmac/gmii_rxc_dly + BUFR_X2Y3.I net (fanout=1) 0.141 ftop/gbe0/gmac/gmii_rxc_dly$DATAOUT + BUFR_X2Y3.O Tbrcko_O 0.120 ftop/gbe0/gmac/rxClk_BUFR + ftop/gbe0/gmac/rxClk_BUFR + SLICE_X97Y34.CLK net (fanout=47) 0.401 ftop/rxclkBnd + ------------------------------------------------- --------------------------- + Total 1.316ns (0.774ns logic, 0.542ns route) + (58.8% logic, 41.2% route) + +-------------------------------------------------------------------------------- + +Hold Paths: COMP "gmii_rxd<1>" OFFSET = IN 0.5 ns VALID 3 ns BEFORE COMP "gmii_rx_clk"; +-------------------------------------------------------------------------------- +Slack (hold path): 2.070ns (requirement - (clock path + clock arrival + uncertainty - data path)) + Source: gmii_rxd<1> (PAD) + Destination: ftop/gbe0/gmac/rxRS_rxData_1 (FF) + Destination Clock: ftop/rxclkBnd rising at 0.000ns + Requirement: 2.500ns + Data Path Delay: 2.164ns (Levels of Logic = 1) + Clock Path Delay: 2.569ns (Levels of Logic = 3) + Clock Uncertainty: 0.025ns + + Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Minimum Data Path at Slow Process Corner: gmii_rxd<1> to ftop/gbe0/gmac/rxRS_rxData_1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AF14.I Tiopi 0.678 gmii_rxd<1> + gmii_rxd<1> + gmii_rxd_1_IBUF + SLICE_X97Y34.BX net (fanout=1) 1.625 gmii_rxd_1_IBUF + SLICE_X97Y34.CLK Tckdi (-Th) 0.139 ftop/gbe0/gmac/rxRS_rxData<3> + ftop/gbe0/gmac/rxRS_rxData_1 + ------------------------------------------------- --------------------------- + Total 2.164ns (0.539ns logic, 1.625ns route) + (24.9% logic, 75.1% route) + + Maximum Clock Path at Slow Process Corner: gmii_rx_clk to ftop/gbe0/gmac/rxRS_rxData_1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AP11.I Tiopi 0.782 gmii_rx_clk + gmii_rx_clk + gmii_rx_clk_IBUF + IODELAY_X2Y57.IDATAINnet (fanout=1) 0.000 gmii_rx_clk_IBUF + IODELAY_X2Y57.DATAOUTTioddo_IDATAIN 0.088 ftop/gbe0/gmac/gmii_rxc_dly + ftop/gbe0/gmac/gmii_rxc_dly + BUFR_X2Y3.I net (fanout=1) 0.384 ftop/gbe0/gmac/gmii_rxc_dly$DATAOUT + BUFR_X2Y3.O Tbrcko_O 0.357 ftop/gbe0/gmac/rxClk_BUFR + ftop/gbe0/gmac/rxClk_BUFR + SLICE_X97Y34.CLK net (fanout=47) 0.958 ftop/rxclkBnd + ------------------------------------------------- --------------------------- + Total 2.569ns (1.227ns logic, 1.342ns route) + (47.8% logic, 52.2% route) + +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "gmii_rxd<0>" OFFSET = IN 0.5 ns VALID 3 ns BEFORE COMP +"gmii_rx_clk"; +For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). + + 1 path analyzed, 1 endpoint analyzed, 0 failing endpoints + 0 timing errors detected. (0 setup errors, 0 hold errors) + Offset is -0.137ns. +-------------------------------------------------------------------------------- +Slack (setup path): 0.637ns (requirement - (data path - clock path - clock arrival + uncertainty)) + Source: gmii_rxd<0> (PAD) + Destination: ftop/gbe0/gmac/rxRS_rxData_0 (FF) + Destination Clock: ftop/rxclkBnd rising at 0.000ns + Requirement: 0.500ns + Data Path Delay: 1.154ns (Levels of Logic = 1) + Clock Path Delay: 1.316ns (Levels of Logic = 3) + Clock Uncertainty: 0.025ns + + Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Fast Process Corner: gmii_rxd<0> to ftop/gbe0/gmac/rxRS_rxData_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AN13.I Tiopi 0.435 gmii_rxd<0> + gmii_rxd<0> + gmii_rxd_0_IBUF + SLICE_X97Y34.AX net (fanout=1) 0.715 gmii_rxd_0_IBUF + SLICE_X97Y34.CLK Tdick 0.004 ftop/gbe0/gmac/rxRS_rxData<3> + ftop/gbe0/gmac/rxRS_rxData_0 + ------------------------------------------------- --------------------------- + Total 1.154ns (0.439ns logic, 0.715ns route) + (38.0% logic, 62.0% route) + + Minimum Clock Path at Fast Process Corner: gmii_rx_clk to ftop/gbe0/gmac/rxRS_rxData_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AP11.I Tiopi 0.385 gmii_rx_clk + gmii_rx_clk + gmii_rx_clk_IBUF + IODELAY_X2Y57.IDATAINnet (fanout=1) 0.000 gmii_rx_clk_IBUF + IODELAY_X2Y57.DATAOUTTioddo_IDATAIN 0.269 ftop/gbe0/gmac/gmii_rxc_dly + ftop/gbe0/gmac/gmii_rxc_dly + BUFR_X2Y3.I net (fanout=1) 0.141 ftop/gbe0/gmac/gmii_rxc_dly$DATAOUT + BUFR_X2Y3.O Tbrcko_O 0.120 ftop/gbe0/gmac/rxClk_BUFR + ftop/gbe0/gmac/rxClk_BUFR + SLICE_X97Y34.CLK net (fanout=47) 0.401 ftop/rxclkBnd + ------------------------------------------------- --------------------------- + Total 1.316ns (0.774ns logic, 0.542ns route) + (58.8% logic, 41.2% route) + +-------------------------------------------------------------------------------- + +Hold Paths: COMP "gmii_rxd<0>" OFFSET = IN 0.5 ns VALID 3 ns BEFORE COMP "gmii_rx_clk"; +-------------------------------------------------------------------------------- +Slack (hold path): 1.577ns (requirement - (clock path + clock arrival + uncertainty - data path)) + Source: gmii_rxd<0> (PAD) + Destination: ftop/gbe0/gmac/rxRS_rxData_0 (FF) + Destination Clock: ftop/rxclkBnd rising at 0.000ns + Requirement: 2.500ns + Data Path Delay: 1.671ns (Levels of Logic = 1) + Clock Path Delay: 2.569ns (Levels of Logic = 3) + Clock Uncertainty: 0.025ns + + Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Minimum Data Path at Slow Process Corner: gmii_rxd<0> to ftop/gbe0/gmac/rxRS_rxData_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AN13.I Tiopi 0.725 gmii_rxd<0> + gmii_rxd<0> + gmii_rxd_0_IBUF + SLICE_X97Y34.AX net (fanout=1) 1.085 gmii_rxd_0_IBUF + SLICE_X97Y34.CLK Tckdi (-Th) 0.139 ftop/gbe0/gmac/rxRS_rxData<3> + ftop/gbe0/gmac/rxRS_rxData_0 + ------------------------------------------------- --------------------------- + Total 1.671ns (0.586ns logic, 1.085ns route) + (35.1% logic, 64.9% route) + + Maximum Clock Path at Slow Process Corner: gmii_rx_clk to ftop/gbe0/gmac/rxRS_rxData_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AP11.I Tiopi 0.782 gmii_rx_clk + gmii_rx_clk + gmii_rx_clk_IBUF + IODELAY_X2Y57.IDATAINnet (fanout=1) 0.000 gmii_rx_clk_IBUF + IODELAY_X2Y57.DATAOUTTioddo_IDATAIN 0.088 ftop/gbe0/gmac/gmii_rxc_dly + ftop/gbe0/gmac/gmii_rxc_dly + BUFR_X2Y3.I net (fanout=1) 0.384 ftop/gbe0/gmac/gmii_rxc_dly$DATAOUT + BUFR_X2Y3.O Tbrcko_O 0.357 ftop/gbe0/gmac/rxClk_BUFR + ftop/gbe0/gmac/rxClk_BUFR + SLICE_X97Y34.CLK net (fanout=47) 0.958 ftop/rxclkBnd + ------------------------------------------------- --------------------------- + Total 2.569ns (1.227ns logic, 1.342ns route) + (47.8% logic, 52.2% route) + +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "gmii_rx_dv" OFFSET = IN 0.5 ns VALID 3 ns BEFORE COMP +"gmii_rx_clk"; +For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). + + 1 path analyzed, 1 endpoint analyzed, 0 failing endpoints + 0 timing errors detected. (0 setup errors, 0 hold errors) + Offset is -0.069ns. +-------------------------------------------------------------------------------- +Slack (setup path): 0.569ns (requirement - (data path - clock path - clock arrival + uncertainty)) + Source: gmii_rx_dv (PAD) + Destination: ftop/gbe0/gmac/rxRS_rxDV (FF) + Destination Clock: ftop/rxclkBnd rising at 0.000ns + Requirement: 0.500ns + Data Path Delay: 1.222ns (Levels of Logic = 1) + Clock Path Delay: 1.316ns (Levels of Logic = 3) + Clock Uncertainty: 0.025ns + + Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Fast Process Corner: gmii_rx_dv to ftop/gbe0/gmac/rxRS_rxDV + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AM13.I Tiopi 0.425 gmii_rx_dv + gmii_rx_dv + gmii_rx_dv_IBUF + SLICE_X97Y31.DX net (fanout=1) 0.793 gmii_rx_dv_IBUF + SLICE_X97Y31.CLK Tdick 0.004 ftop/gbe0/gmac/rxRS_rxDV + ftop/gbe0/gmac/rxRS_rxDV + ------------------------------------------------- --------------------------- + Total 1.222ns (0.429ns logic, 0.793ns route) + (35.1% logic, 64.9% route) + + Minimum Clock Path at Fast Process Corner: gmii_rx_clk to ftop/gbe0/gmac/rxRS_rxDV + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AP11.I Tiopi 0.385 gmii_rx_clk + gmii_rx_clk + gmii_rx_clk_IBUF + IODELAY_X2Y57.IDATAINnet (fanout=1) 0.000 gmii_rx_clk_IBUF + IODELAY_X2Y57.DATAOUTTioddo_IDATAIN 0.269 ftop/gbe0/gmac/gmii_rxc_dly + ftop/gbe0/gmac/gmii_rxc_dly + BUFR_X2Y3.I net (fanout=1) 0.141 ftop/gbe0/gmac/gmii_rxc_dly$DATAOUT + BUFR_X2Y3.O Tbrcko_O 0.120 ftop/gbe0/gmac/rxClk_BUFR + ftop/gbe0/gmac/rxClk_BUFR + SLICE_X97Y31.CLK net (fanout=47) 0.401 ftop/rxclkBnd + ------------------------------------------------- --------------------------- + Total 1.316ns (0.774ns logic, 0.542ns route) + (58.8% logic, 41.2% route) + +-------------------------------------------------------------------------------- + +Hold Paths: COMP "gmii_rx_dv" OFFSET = IN 0.5 ns VALID 3 ns BEFORE COMP "gmii_rx_clk"; +-------------------------------------------------------------------------------- +Slack (hold path): 1.676ns (requirement - (clock path + clock arrival + uncertainty - data path)) + Source: gmii_rx_dv (PAD) + Destination: ftop/gbe0/gmac/rxRS_rxDV (FF) + Destination Clock: ftop/rxclkBnd rising at 0.000ns + Requirement: 2.500ns + Data Path Delay: 1.768ns (Levels of Logic = 1) + Clock Path Delay: 2.567ns (Levels of Logic = 3) + Clock Uncertainty: 0.025ns + + Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Minimum Data Path at Slow Process Corner: gmii_rx_dv to ftop/gbe0/gmac/rxRS_rxDV + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AM13.I Tiopi 0.716 gmii_rx_dv + gmii_rx_dv + gmii_rx_dv_IBUF + SLICE_X97Y31.DX net (fanout=1) 1.191 gmii_rx_dv_IBUF + SLICE_X97Y31.CLK Tckdi (-Th) 0.139 ftop/gbe0/gmac/rxRS_rxDV + ftop/gbe0/gmac/rxRS_rxDV + ------------------------------------------------- --------------------------- + Total 1.768ns (0.577ns logic, 1.191ns route) + (32.6% logic, 67.4% route) + + Maximum Clock Path at Slow Process Corner: gmii_rx_clk to ftop/gbe0/gmac/rxRS_rxDV + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AP11.I Tiopi 0.782 gmii_rx_clk + gmii_rx_clk + gmii_rx_clk_IBUF + IODELAY_X2Y57.IDATAINnet (fanout=1) 0.000 gmii_rx_clk_IBUF + IODELAY_X2Y57.DATAOUTTioddo_IDATAIN 0.088 ftop/gbe0/gmac/gmii_rxc_dly + ftop/gbe0/gmac/gmii_rxc_dly + BUFR_X2Y3.I net (fanout=1) 0.384 ftop/gbe0/gmac/gmii_rxc_dly$DATAOUT + BUFR_X2Y3.O Tbrcko_O 0.357 ftop/gbe0/gmac/rxClk_BUFR + ftop/gbe0/gmac/rxClk_BUFR + SLICE_X97Y31.CLK net (fanout=47) 0.956 ftop/rxclkBnd + ------------------------------------------------- --------------------------- + Total 2.567ns (1.227ns logic, 1.340ns route) + (47.8% logic, 52.2% route) + +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "gmii_rx_er" OFFSET = IN 0.5 ns VALID 3 ns BEFORE COMP +"gmii_rx_clk"; +For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). + + 1 path analyzed, 1 endpoint analyzed, 0 failing endpoints + 0 timing errors detected. (0 setup errors, 0 hold errors) + Offset is -0.537ns. +-------------------------------------------------------------------------------- +Slack (setup path): 1.037ns (requirement - (data path - clock path - clock arrival + uncertainty)) + Source: gmii_rx_er (PAD) + Destination: ftop/gbe0/gmac/rxRS_rxER (FF) + Destination Clock: ftop/rxclkBnd rising at 0.000ns + Requirement: 0.500ns + Data Path Delay: 0.687ns (Levels of Logic = 1) + Clock Path Delay: 1.249ns (Levels of Logic = 3) + Clock Uncertainty: 0.025ns + + Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Fast Process Corner: gmii_rx_er to ftop/gbe0/gmac/rxRS_rxER + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AG12.I Tiopi 0.393 gmii_rx_er + gmii_rx_er + gmii_rx_er_IBUF + SLICE_X90Y45.DX net (fanout=1) 0.290 gmii_rx_er_IBUF + SLICE_X90Y45.CLK Tdick 0.004 ftop/gbe0/gmac/rxRS_rxER + ftop/gbe0/gmac/rxRS_rxER + ------------------------------------------------- --------------------------- + Total 0.687ns (0.397ns logic, 0.290ns route) + (57.8% logic, 42.2% route) + + Minimum Clock Path at Fast Process Corner: gmii_rx_clk to ftop/gbe0/gmac/rxRS_rxER + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AP11.I Tiopi 0.385 gmii_rx_clk + gmii_rx_clk + gmii_rx_clk_IBUF + IODELAY_X2Y57.IDATAINnet (fanout=1) 0.000 gmii_rx_clk_IBUF + IODELAY_X2Y57.DATAOUTTioddo_IDATAIN 0.269 ftop/gbe0/gmac/gmii_rxc_dly + ftop/gbe0/gmac/gmii_rxc_dly + BUFR_X2Y3.I net (fanout=1) 0.141 ftop/gbe0/gmac/gmii_rxc_dly$DATAOUT + BUFR_X2Y3.O Tbrcko_O 0.120 ftop/gbe0/gmac/rxClk_BUFR + ftop/gbe0/gmac/rxClk_BUFR + SLICE_X90Y45.CLK net (fanout=47) 0.334 ftop/rxclkBnd + ------------------------------------------------- --------------------------- + Total 1.249ns (0.774ns logic, 0.475ns route) + (62.0% logic, 38.0% route) + +-------------------------------------------------------------------------------- + +Hold Paths: COMP "gmii_rx_er" OFFSET = IN 0.5 ns VALID 3 ns BEFORE COMP "gmii_rx_clk"; +-------------------------------------------------------------------------------- +Slack (hold path): 1.069ns (requirement - (clock path + clock arrival + uncertainty - data path)) + Source: gmii_rx_er (PAD) + Destination: ftop/gbe0/gmac/rxRS_rxER (FF) + Destination Clock: ftop/rxclkBnd rising at 0.000ns + Requirement: 2.500ns + Data Path Delay: 1.063ns (Levels of Logic = 1) + Clock Path Delay: 2.469ns (Levels of Logic = 3) + Clock Uncertainty: 0.025ns + + Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Minimum Data Path at Slow Process Corner: gmii_rx_er to ftop/gbe0/gmac/rxRS_rxER + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AG12.I Tiopi 0.689 gmii_rx_er + gmii_rx_er + gmii_rx_er_IBUF + SLICE_X90Y45.DX net (fanout=1) 0.513 gmii_rx_er_IBUF + SLICE_X90Y45.CLK Tckdi (-Th) 0.139 ftop/gbe0/gmac/rxRS_rxER + ftop/gbe0/gmac/rxRS_rxER + ------------------------------------------------- --------------------------- + Total 1.063ns (0.550ns logic, 0.513ns route) + (51.7% logic, 48.3% route) + + Maximum Clock Path at Slow Process Corner: gmii_rx_clk to ftop/gbe0/gmac/rxRS_rxER + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + AP11.I Tiopi 0.782 gmii_rx_clk + gmii_rx_clk + gmii_rx_clk_IBUF + IODELAY_X2Y57.IDATAINnet (fanout=1) 0.000 gmii_rx_clk_IBUF + IODELAY_X2Y57.DATAOUTTioddo_IDATAIN 0.088 ftop/gbe0/gmac/gmii_rxc_dly + ftop/gbe0/gmac/gmii_rxc_dly + BUFR_X2Y3.I net (fanout=1) 0.384 ftop/gbe0/gmac/gmii_rxc_dly$DATAOUT + BUFR_X2Y3.O Tbrcko_O 0.357 ftop/gbe0/gmac/rxClk_BUFR + ftop/gbe0/gmac/rxClk_BUFR + SLICE_X90Y45.CLK net (fanout=47) 0.858 ftop/rxclkBnd + ------------------------------------------------- --------------------------- + Total 2.469ns (1.227ns logic, 1.242ns route) + (49.7% logic, 50.3% route) + +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "gmii_txd<7>" OFFSET = OUT 6 ns AFTER COMP +"gmii_gtx_clk"; +For more information, see Offset Out Analysis in the Timing Closure User Guide (UG612). + + 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints + 0 timing errors detected. +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "gmii_txd<6>" OFFSET = OUT 6 ns AFTER COMP +"gmii_gtx_clk"; +For more information, see Offset Out Analysis in the Timing Closure User Guide (UG612). + + 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints + 0 timing errors detected. +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "gmii_txd<5>" OFFSET = OUT 6 ns AFTER COMP +"gmii_gtx_clk"; +For more information, see Offset Out Analysis in the Timing Closure User Guide (UG612). + + 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints + 0 timing errors detected. +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "gmii_txd<4>" OFFSET = OUT 6 ns AFTER COMP +"gmii_gtx_clk"; +For more information, see Offset Out Analysis in the Timing Closure User Guide (UG612). + + 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints + 0 timing errors detected. +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "gmii_txd<3>" OFFSET = OUT 6 ns AFTER COMP +"gmii_gtx_clk"; +For more information, see Offset Out Analysis in the Timing Closure User Guide (UG612). + + 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints + 0 timing errors detected. +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "gmii_txd<2>" OFFSET = OUT 6 ns AFTER COMP +"gmii_gtx_clk"; +For more information, see Offset Out Analysis in the Timing Closure User Guide (UG612). + + 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints + 0 timing errors detected. +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "gmii_txd<1>" OFFSET = OUT 6 ns AFTER COMP +"gmii_gtx_clk"; +For more information, see Offset Out Analysis in the Timing Closure User Guide (UG612). + + 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints + 0 timing errors detected. +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "gmii_txd<0>" OFFSET = OUT 6 ns AFTER COMP +"gmii_gtx_clk"; +For more information, see Offset Out Analysis in the Timing Closure User Guide (UG612). + + 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints + 0 timing errors detected. +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "gmii_tx_en" OFFSET = OUT 6 ns AFTER COMP +"gmii_gtx_clk"; +For more information, see Offset Out Analysis in the Timing Closure User Guide (UG612). + + 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints + 0 timing errors detected. +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "gmii_tx_er" OFFSET = OUT 6 ns AFTER COMP +"gmii_gtx_clk"; +For more information, see Offset Out Analysis in the Timing Closure User Guide (UG612). + + 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints + 0 timing errors detected. +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: Pin to Pin Skew Constraint; + + 1 path analyzed, 0 endpoints analyzed, 0 failing endpoints + 0 timing errors detected. +-------------------------------------------------------------------------------- +Slack: 0.108ns (maxskew - uncertainty - (arrival1 - arrival2)) + Max skew: 0.450ns + Arrival 1: 2.658ns ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i/PIPECLK + Arrival 2: 2.505ns ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_block_i/USERCLK + Clock Uncertainty: 0.189ns + +-------------------------------------------------------------------------------- + + +Derived Constraint Report +Derived Constraints for TS_SYS0CLK ++-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ +| | Period | Actual Period | Timing Errors | Paths Analyzed | +| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------| +| | | Direct | Derivative | Direct | Derivative | Direct | Derivative | ++-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ +|TS_SYS0CLK | 5.000ns| 4.889ns| 5.170ns| 0| 5| 91979| 58635| +| TS_ftop_dram0_memc_memc_u_infr| 5.000ns| 5.170ns| N/A| 5| 0| 58635| 0| +| astructure_clk_pll | | | | | | | | +| TS_ftop_dram0_memc_memc_u_infr| 2.500ns| 1.429ns| N/A| 0| 0| 0| 0| +| astructure_clk_mem_pll | | | | | | | | +| TS_ftop_dram0_memc_memc_clk_wr| 2.500ns| N/A| N/A| 0| 0| 0| 0| +| _i | | | | | | | | ++-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ + +Derived Constraints for TS_PCICLK ++-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ +| | Period | Actual Period | Timing Errors | Paths Analyzed | +| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------| +| | | Direct | Derivative | Direct | Derivative | Direct | Derivative | ++-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ +|TS_PCICLK | 4.000ns| 1.538ns| 5.085ns| 0| 388| 0| 13963164| +| TS_CLK_125 | 8.000ns| 10.171ns| N/A| 380| 0| 13943867| 0| +| TS_CLK_250 | 4.000ns| 4.033ns| N/A| 8| 0| 19297| 0| ++-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ + +3 constraints not met. + + +Data Sheet report: +----------------- +All values displayed in nanoseconds (ns) + +Setup/Hold to clock gmii_rx_clk +------------+------------+------------+------------+------------+------------------+--------+ + |Max Setup to| Process |Max Hold to | Process | | Clock | +Source | clk (edge) | Corner | clk (edge) | Corner |Internal Clock(s) | Phase | +------------+------------+------------+------------+------------+------------------+--------+ +gmii_rx_dv | -0.069(R)| FAST | 0.824(R)| SLOW |ftop/rxclkBnd | 0.000| +gmii_rx_er | -0.537(R)| FAST | 1.431(R)| SLOW |ftop/rxclkBnd | 0.000| +gmii_rxd<0> | -0.137(R)| FAST | 0.923(R)| SLOW |ftop/rxclkBnd | 0.000| +gmii_rxd<1> | 0.276(R)| FAST | 0.430(R)| SLOW |ftop/rxclkBnd | 0.000| +gmii_rxd<2> | -0.141(R)| FAST | 0.847(R)| SLOW |ftop/rxclkBnd | 0.000| +gmii_rxd<3> | -0.065(R)| FAST | 0.808(R)| SLOW |ftop/rxclkBnd | 0.000| +gmii_rxd<4> | -0.316(R)| FAST | 1.083(R)| SLOW |ftop/rxclkBnd | 0.000| +gmii_rxd<5> | -0.212(R)| FAST | 0.886(R)| SLOW |ftop/rxclkBnd | 0.000| +gmii_rxd<6> | -0.163(R)| FAST | 0.834(R)| SLOW |ftop/rxclkBnd | 0.000| +gmii_rxd<7> | -0.167(R)| FAST | 0.845(R)| SLOW |ftop/rxclkBnd | 0.000| +------------+------------+------------+------------+------------+------------------+--------+ + +Clock to Setup on destination clock gmii_rx_clk +---------------+---------+---------+---------+---------+ + | Src:Rise| Src:Fall| Src:Rise| Src:Fall| +Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| +---------------+---------+---------+---------+---------+ +gmii_rx_clk | 5.467| | | | +---------------+---------+---------+---------+---------+ + +Clock to Setup on destination clock sys0_clkn +---------------+---------+---------+---------+---------+ + | Src:Rise| Src:Fall| Src:Rise| Src:Fall| +Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| +---------------+---------+---------+---------+---------+ +sys0_clkn | 5.170| | | | +sys0_clkp | 5.170| | | | +---------------+---------+---------+---------+---------+ + +Clock to Setup on destination clock sys0_clkp +---------------+---------+---------+---------+---------+ + | Src:Rise| Src:Fall| Src:Rise| Src:Fall| +Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| +---------------+---------+---------+---------+---------+ +sys0_clkn | 5.170| | | | +sys0_clkp | 5.170| | | | +---------------+---------+---------+---------+---------+ + +Clock to Setup on destination clock sys1_clkn +---------------+---------+---------+---------+---------+ + | Src:Rise| Src:Fall| Src:Rise| Src:Fall| +Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| +---------------+---------+---------+---------+---------+ +sys1_clkn | 5.800| | | | +sys1_clkp | 5.800| | | | +---------------+---------+---------+---------+---------+ + +Clock to Setup on destination clock sys1_clkp +---------------+---------+---------+---------+---------+ + | Src:Rise| Src:Fall| Src:Rise| Src:Fall| +Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| +---------------+---------+---------+---------+---------+ +sys1_clkn | 5.800| | | | +sys1_clkp | 5.800| | | | +---------------+---------+---------+---------+---------+ + +COMP "gmii_rxd<7>" OFFSET = IN 0.5 ns VALID 3 ns BEFORE COMP "gmii_rx_clk"; +Worst Case Data Window 0.678; Ideal Clock Offset To Actual Clock 0.494; +------------------+------------+------------+------------+------------+---------+---------+-------------+ + | | Process | | Process | Setup | Hold |Source Offset| +Source | Setup | Corner | Hold | Corner | Slack | Slack | To Center | +------------------+------------+------------+------------+------------+---------+---------+-------------+ +gmii_rxd<7> | -0.167(R)| FAST | 0.845(R)| SLOW | 0.667| 1.655| -0.494| +------------------+------------+------------+------------+------------+---------+---------+-------------+ +Worst Case Summary| -0.167| - | 0.845| - | 0.667| 1.655| | +------------------+------------+------------+------------+------------+---------+---------+-------------+ + +COMP "gmii_rxd<6>" OFFSET = IN 0.5 ns VALID 3 ns BEFORE COMP "gmii_rx_clk"; +Worst Case Data Window 0.671; Ideal Clock Offset To Actual Clock 0.501; +------------------+------------+------------+------------+------------+---------+---------+-------------+ + | | Process | | Process | Setup | Hold |Source Offset| +Source | Setup | Corner | Hold | Corner | Slack | Slack | To Center | +------------------+------------+------------+------------+------------+---------+---------+-------------+ +gmii_rxd<6> | -0.163(R)| FAST | 0.834(R)| SLOW | 0.663| 1.666| -0.501| +------------------+------------+------------+------------+------------+---------+---------+-------------+ +Worst Case Summary| -0.163| - | 0.834| - | 0.663| 1.666| | +------------------+------------+------------+------------+------------+---------+---------+-------------+ + +COMP "gmii_rxd<5>" OFFSET = IN 0.5 ns VALID 3 ns BEFORE COMP "gmii_rx_clk"; +Worst Case Data Window 0.674; Ideal Clock Offset To Actual Clock 0.451; +------------------+------------+------------+------------+------------+---------+---------+-------------+ + | | Process | | Process | Setup | Hold |Source Offset| +Source | Setup | Corner | Hold | Corner | Slack | Slack | To Center | +------------------+------------+------------+------------+------------+---------+---------+-------------+ +gmii_rxd<5> | -0.212(R)| FAST | 0.886(R)| SLOW | 0.712| 1.614| -0.451| +------------------+------------+------------+------------+------------+---------+---------+-------------+ +Worst Case Summary| -0.212| - | 0.886| - | 0.712| 1.614| | +------------------+------------+------------+------------+------------+---------+---------+-------------+ + +COMP "gmii_rxd<4>" OFFSET = IN 0.5 ns VALID 3 ns BEFORE COMP "gmii_rx_clk"; +Worst Case Data Window 0.767; Ideal Clock Offset To Actual Clock 0.301; +------------------+------------+------------+------------+------------+---------+---------+-------------+ + | | Process | | Process | Setup | Hold |Source Offset| +Source | Setup | Corner | Hold | Corner | Slack | Slack | To Center | +------------------+------------+------------+------------+------------+---------+---------+-------------+ +gmii_rxd<4> | -0.316(R)| FAST | 1.083(R)| SLOW | 0.816| 1.417| -0.301| +------------------+------------+------------+------------+------------+---------+---------+-------------+ +Worst Case Summary| -0.316| - | 1.083| - | 0.816| 1.417| | +------------------+------------+------------+------------+------------+---------+---------+-------------+ + +COMP "gmii_rxd<3>" OFFSET = IN 0.5 ns VALID 3 ns BEFORE COMP "gmii_rx_clk"; +Worst Case Data Window 0.743; Ideal Clock Offset To Actual Clock 0.564; +------------------+------------+------------+------------+------------+---------+---------+-------------+ + | | Process | | Process | Setup | Hold |Source Offset| +Source | Setup | Corner | Hold | Corner | Slack | Slack | To Center | +------------------+------------+------------+------------+------------+---------+---------+-------------+ +gmii_rxd<3> | -0.065(R)| FAST | 0.808(R)| SLOW | 0.565| 1.692| -0.564| +------------------+------------+------------+------------+------------+---------+---------+-------------+ +Worst Case Summary| -0.065| - | 0.808| - | 0.565| 1.692| | +------------------+------------+------------+------------+------------+---------+---------+-------------+ + +COMP "gmii_rxd<2>" OFFSET = IN 0.5 ns VALID 3 ns BEFORE COMP "gmii_rx_clk"; +Worst Case Data Window 0.706; Ideal Clock Offset To Actual Clock 0.506; +------------------+------------+------------+------------+------------+---------+---------+-------------+ + | | Process | | Process | Setup | Hold |Source Offset| +Source | Setup | Corner | Hold | Corner | Slack | Slack | To Center | +------------------+------------+------------+------------+------------+---------+---------+-------------+ +gmii_rxd<2> | -0.141(R)| FAST | 0.847(R)| SLOW | 0.641| 1.653| -0.506| +------------------+------------+------------+------------+------------+---------+---------+-------------+ +Worst Case Summary| -0.141| - | 0.847| - | 0.641| 1.653| | +------------------+------------+------------+------------+------------+---------+---------+-------------+ + +COMP "gmii_rxd<1>" OFFSET = IN 0.5 ns VALID 3 ns BEFORE COMP "gmii_rx_clk"; +Worst Case Data Window 0.706; Ideal Clock Offset To Actual Clock 0.923; +------------------+------------+------------+------------+------------+---------+---------+-------------+ + | | Process | | Process | Setup | Hold |Source Offset| +Source | Setup | Corner | Hold | Corner | Slack | Slack | To Center | +------------------+------------+------------+------------+------------+---------+---------+-------------+ +gmii_rxd<1> | 0.276(R)| FAST | 0.430(R)| SLOW | 0.224| 2.070| -0.923| +------------------+------------+------------+------------+------------+---------+---------+-------------+ +Worst Case Summary| 0.276| - | 0.430| - | 0.224| 2.070| | +------------------+------------+------------+------------+------------+---------+---------+-------------+ + +COMP "gmii_rxd<0>" OFFSET = IN 0.5 ns VALID 3 ns BEFORE COMP "gmii_rx_clk"; +Worst Case Data Window 0.786; Ideal Clock Offset To Actual Clock 0.470; +------------------+------------+------------+------------+------------+---------+---------+-------------+ + | | Process | | Process | Setup | Hold |Source Offset| +Source | Setup | Corner | Hold | Corner | Slack | Slack | To Center | +------------------+------------+------------+------------+------------+---------+---------+-------------+ +gmii_rxd<0> | -0.137(R)| FAST | 0.923(R)| SLOW | 0.637| 1.577| -0.470| +------------------+------------+------------+------------+------------+---------+---------+-------------+ +Worst Case Summary| -0.137| - | 0.923| - | 0.637| 1.577| | +------------------+------------+------------+------------+------------+---------+---------+-------------+ + +COMP "gmii_rx_dv" OFFSET = IN 0.5 ns VALID 3 ns BEFORE COMP "gmii_rx_clk"; +Worst Case Data Window 0.755; Ideal Clock Offset To Actual Clock 0.554; +------------------+------------+------------+------------+------------+---------+---------+-------------+ + | | Process | | Process | Setup | Hold |Source Offset| +Source | Setup | Corner | Hold | Corner | Slack | Slack | To Center | +------------------+------------+------------+------------+------------+---------+---------+-------------+ +gmii_rx_dv | -0.069(R)| FAST | 0.824(R)| SLOW | 0.569| 1.676| -0.554| +------------------+------------+------------+------------+------------+---------+---------+-------------+ +Worst Case Summary| -0.069| - | 0.824| - | 0.569| 1.676| | +------------------+------------+------------+------------+------------+---------+---------+-------------+ + +COMP "gmii_rx_er" OFFSET = IN 0.5 ns VALID 3 ns BEFORE COMP "gmii_rx_clk"; +Worst Case Data Window 0.894; Ideal Clock Offset To Actual Clock 0.016; +------------------+------------+------------+------------+------------+---------+---------+-------------+ + | | Process | | Process | Setup | Hold |Source Offset| +Source | Setup | Corner | Hold | Corner | Slack | Slack | To Center | +------------------+------------+------------+------------+------------+---------+---------+-------------+ +gmii_rx_er | -0.537(R)| FAST | 1.431(R)| SLOW | 1.037| 1.069| -0.016| +------------------+------------+------------+------------+------------+---------+---------+-------------+ +Worst Case Summary| -0.537| - | 1.431| - | 1.037| 1.069| | +------------------+------------+------------+------------+------------+---------+---------+-------------+ + + +Timing summary: +--------------- + +Timing errors: 393 Score: 393240 (Setup/Max: 393240, Hold: 0) + +Constraints cover 14123372 paths, 0 nets, and 208981 connections + +Design statistics: + Minimum period: 10.171ns{1} (Maximum frequency: 98.319MHz) + Minimum input required time before clock: 0.276ns + + +------------------------------------Footnotes----------------------------------- +1) The minimum period statistic assumes all single cycle delays. + +Analysis completed Sun Jan 27 11:20:32 2013 +-------------------------------------------------------------------------------- + +Trace Settings: +------------------------- +Trace Settings + +Peak Memory Usage: 1637 MB + + + diff --git a/logs/ml605-20130127_1122/fpgaTop_map.mrp b/logs/ml605-20130127_1122/fpgaTop_map.mrp new file mode 100644 index 00000000..0e7354c4 --- /dev/null +++ b/logs/ml605-20130127_1122/fpgaTop_map.mrp @@ -0,0 +1,8860 @@ +Release 14.4 Map P.49d (lin64) +Xilinx Mapping Report File for Design 'fpgaTop' + +Design Information +------------------ +Command Line : map -p xc6vlx240t-ff1156-1 -w -logic_opt on -xe n -mt on -t 1 -register_duplication on -ir off -pr off +-lc off -power off -o fpgaTop_map.ncd fpgaTop.ngd fpgaTop.pcf +Target Device : xc6vlx240t +Target Package : ff1156 +Target Speed : -1 +Mapper Version : virtex6 -- $Revision: 1.55 $ +Mapped Date : Sun Jan 27 10:43:24 2013 + +Design Summary +-------------- +Number of errors: 0 +Number of warnings: 599 +Slice Logic Utilization: + Number of Slice Registers: 32,742 out of 301,440 10% + Number used as Flip Flops: 32,735 + Number used as Latches: 2 + Number used as Latch-thrus: 0 + Number used as AND/OR logics: 5 + Number of Slice LUTs: 41,259 out of 150,720 27% + Number used as logic: 35,513 out of 150,720 23% + Number using O6 output only: 32,112 + Number using O5 output only: 2,230 + Number using O5 and O6: 1,171 + Number used as ROM: 0 + Number used as Memory: 5,075 out of 58,400 8% + Number used as Dual Port RAM: 2,098 + Number using O6 output only: 106 + Number using O5 output only: 53 + Number using O5 and O6: 1,939 + Number used as Single Port RAM: 0 + Number used as Shift Register: 2,977 + Number using O6 output only: 2,977 + Number using O5 output only: 0 + Number using O5 and O6: 0 + Number used exclusively as route-thrus: 671 + Number with same-slice register load: 547 + Number with same-slice carry load: 122 + Number with other load: 2 + +Slice Logic Distribution: + Number of occupied Slices: 16,343 out of 37,680 43% + Number of LUT Flip Flop pairs used: 48,814 + Number with an unused Flip Flop: 16,997 out of 48,814 34% + Number with an unused LUT: 7,555 out of 48,814 15% + Number of fully used LUT-FF pairs: 24,262 out of 48,814 49% + Number of unique control sets: 2,046 + Number of slice register sites lost + to control set restrictions: 9,873 out of 301,440 3% + + A LUT Flip Flop pair for this architecture represents one LUT paired with + one Flip Flop within a slice. A control set is a unique combination of + clock, reset, set, and enable signals for a registered element. + The Slice Logic Distribution report is not meaningful if the design is + over-mapped for a non-slice resource or if Placement fails. + OVERMAPPING of BRAM resources should be ignored if the design is + over-mapped for a non-BRAM resource or if placement fails. + +IO Utilization: + Number of bonded IOBs: 218 out of 600 36% + Number of LOCed IOBs: 218 out of 218 100% + IOB Flip Flops: 12 + IOB Master Pads: 9 + IOB Slave Pads: 9 + Number of bonded IPADs: 12 + Number of LOCed IPADs: 4 out of 12 33% + Number of bonded OPADs: 8 + +Specific Feature Utilization: + Number of RAMB36E1/FIFO36E1s: 38 out of 416 9% + Number using RAMB36E1 only: 38 + Number using FIFO36E1 only: 0 + Number of RAMB18E1/FIFO18E1s: 3 out of 832 1% + Number using RAMB18E1 only: 3 + Number using FIFO18E1 only: 0 + Number of BUFG/BUFGCTRLs: 12 out of 32 37% + Number used as BUFGs: 11 + Number used as BUFGCTRLs: 1 + Number of ILOGICE1/ISERDESE1s: 65 out of 720 9% + Number used as ILOGICE1s: 0 + Number used as ISERDESE1s: 65 + Number of OLOGICE1/OSERDESE1s: 138 out of 720 19% + Number used as OLOGICE1s: 17 + Number used as OSERDESE1s: 121 + Number of BSCANs: 0 out of 4 0% + Number of BUFHCEs: 0 out of 144 0% + Number of BUFIODQSs: 8 out of 72 11% + Number of BUFRs: 3 out of 36 8% + Number of LOCed BUFRs: 2 out of 3 66% + Number of CAPTUREs: 0 out of 1 0% + Number of DSP48E1s: 0 out of 768 0% + Number of EFUSE_USRs: 0 out of 1 0% + Number of FRAME_ECCs: 0 out of 1 0% + Number of GTXE1s: 4 out of 20 20% + Number of LOCed GTXE1s: 4 out of 4 100% + Number of IBUFDS_GTXE1s: 2 out of 12 16% + Number of LOCed IBUFDS_GTXE1s: 1 out of 2 50% + Number of ICAPs: 0 out of 2 0% + Number of IDELAYCTRLs: 4 out of 18 22% + Number of IODELAYE1s: 91 out of 720 12% + Number of LOCed IODELAYE1s: 10 out of 91 10% + Number of MMCM_ADVs: 2 out of 12 16% + Number of PCIE_2_0s: 1 out of 2 50% + Number of LOCed PCIE_2_0s: 1 out of 1 100% + Number of STARTUPs: 1 out of 1 100% + Number of SYSMONs: 0 out of 1 0% + Number of TEMAC_SINGLEs: 0 out of 4 0% + +Average Fanout of Non-Clock Nets: 4.08 + +Peak Memory Usage: 2389 MB +Total REAL time to MAP completion: 24 mins 12 secs +Total CPU time to MAP completion (all processors): 24 mins 56 secs + +Table of Contents +----------------- +Section 1 - Errors +Section 2 - Warnings +Section 3 - Informational +Section 4 - Removed Logic Summary +Section 5 - Removed Logic +Section 6 - IOB Properties +Section 7 - RPMs +Section 8 - Guide Report +Section 9 - Area Group and Partition Summary +Section 10 - Timing Report +Section 11 - Configuration String Information +Section 12 - Control Set Information +Section 13 - Utilization by Hierarchy + +Section 1 - Errors +------------------ + +Section 2 - Warnings +-------------------- +WARNING:Pack:2515 - The LUT-1 inverter "ftop/flash0/flashC_tsd/OE_inv1_INV_0" + failed to join the OLOGIC comp matched to output buffer + "ftop/flash0/flashC_tsd/IO_10_IOBUF/OBUFT". This may result in suboptimal + timing. The LUT-1 inverter ftop/flash0/flashC_tsd/OE_inv1_INV_0 drives + multiple loads. +WARNING:Pack:2515 - The LUT-1 inverter "ftop/flash0/flashC_tsd/OE_inv1_INV_0" + failed to join the OLOGIC comp matched to output buffer + "ftop/flash0/flashC_tsd/IO_11_IOBUF/OBUFT". This may result in suboptimal + timing. The LUT-1 inverter ftop/flash0/flashC_tsd/OE_inv1_INV_0 drives + multiple loads. +WARNING:Pack:2515 - The LUT-1 inverter "ftop/flash0/flashC_tsd/OE_inv1_INV_0" + failed to join the OLOGIC comp matched to output buffer + "ftop/flash0/flashC_tsd/IO_12_IOBUF/OBUFT". This may result in suboptimal + timing. The LUT-1 inverter ftop/flash0/flashC_tsd/OE_inv1_INV_0 drives + multiple loads. +WARNING:Pack:2515 - The LUT-1 inverter "ftop/flash0/flashC_tsd/OE_inv1_INV_0" + failed to join the OLOGIC comp matched to output buffer + "ftop/flash0/flashC_tsd/IO_13_IOBUF/OBUFT". This may result in suboptimal + timing. The LUT-1 inverter ftop/flash0/flashC_tsd/OE_inv1_INV_0 drives + multiple loads. +WARNING:Pack:2515 - The LUT-1 inverter "ftop/flash0/flashC_tsd/OE_inv1_INV_0" + failed to join the OLOGIC comp matched to output buffer + "ftop/flash0/flashC_tsd/IO_14_IOBUF/OBUFT". This may result in suboptimal + timing. The LUT-1 inverter ftop/flash0/flashC_tsd/OE_inv1_INV_0 drives + multiple loads. +WARNING:Pack:2515 - The LUT-1 inverter "ftop/flash0/flashC_tsd/OE_inv1_INV_0" + failed to join the OLOGIC comp matched to output buffer + "ftop/flash0/flashC_tsd/IO_15_IOBUF/OBUFT". This may result in suboptimal + timing. The LUT-1 inverter ftop/flash0/flashC_tsd/OE_inv1_INV_0 drives + multiple loads. +WARNING:Pack:2515 - The LUT-1 inverter "ftop/flash0/flashC_tsd/OE_inv1_INV_0" + failed to join the OLOGIC comp matched to output buffer + "ftop/flash0/flashC_tsd/IO_0_IOBUF/OBUFT". This may result in suboptimal + timing. The LUT-1 inverter ftop/flash0/flashC_tsd/OE_inv1_INV_0 drives + multiple loads. +WARNING:Pack:2515 - The LUT-1 inverter "ftop/flash0/flashC_tsd/OE_inv1_INV_0" + failed to join the OLOGIC comp matched to output buffer + "ftop/flash0/flashC_tsd/IO_1_IOBUF/OBUFT". This may result in suboptimal + timing. The LUT-1 inverter ftop/flash0/flashC_tsd/OE_inv1_INV_0 drives + multiple loads. +WARNING:Pack:2515 - The LUT-1 inverter "ftop/flash0/flashC_tsd/OE_inv1_INV_0" + failed to join the OLOGIC comp matched to output buffer + "ftop/flash0/flashC_tsd/IO_2_IOBUF/OBUFT". This may result in suboptimal + timing. The LUT-1 inverter ftop/flash0/flashC_tsd/OE_inv1_INV_0 drives + multiple loads. +WARNING:Pack:2515 - The LUT-1 inverter "ftop/flash0/flashC_tsd/OE_inv1_INV_0" + failed to join the OLOGIC comp matched to output buffer + "ftop/flash0/flashC_tsd/IO_3_IOBUF/OBUFT". This may result in suboptimal + timing. The LUT-1 inverter ftop/flash0/flashC_tsd/OE_inv1_INV_0 drives + multiple loads. +WARNING:Pack:2515 - The LUT-1 inverter "ftop/flash0/flashC_tsd/OE_inv1_INV_0" + failed to join the OLOGIC comp matched to output buffer + "ftop/flash0/flashC_tsd/IO_4_IOBUF/OBUFT". This may result in suboptimal + timing. The LUT-1 inverter ftop/flash0/flashC_tsd/OE_inv1_INV_0 drives + multiple loads. +WARNING:Pack:2515 - The LUT-1 inverter "ftop/flash0/flashC_tsd/OE_inv1_INV_0" + failed to join the OLOGIC comp matched to output buffer + "ftop/flash0/flashC_tsd/IO_5_IOBUF/OBUFT". This may result in suboptimal + timing. The LUT-1 inverter ftop/flash0/flashC_tsd/OE_inv1_INV_0 drives + multiple loads. +WARNING:Pack:2515 - The LUT-1 inverter "ftop/flash0/flashC_tsd/OE_inv1_INV_0" + failed to join the OLOGIC comp matched to output buffer + "ftop/flash0/flashC_tsd/IO_6_IOBUF/OBUFT". This may result in suboptimal + timing. The LUT-1 inverter ftop/flash0/flashC_tsd/OE_inv1_INV_0 drives + multiple loads. +WARNING:Pack:2515 - The LUT-1 inverter "ftop/flash0/flashC_tsd/OE_inv1_INV_0" + failed to join the OLOGIC comp matched to output buffer + "ftop/flash0/flashC_tsd/IO_7_IOBUF/OBUFT". This may result in suboptimal + timing. The LUT-1 inverter ftop/flash0/flashC_tsd/OE_inv1_INV_0 drives + multiple loads. +WARNING:Pack:2515 - The LUT-1 inverter "ftop/flash0/flashC_tsd/OE_inv1_INV_0" + failed to join the OLOGIC comp matched to output buffer + "ftop/flash0/flashC_tsd/IO_8_IOBUF/OBUFT". This may result in suboptimal + timing. The LUT-1 inverter ftop/flash0/flashC_tsd/OE_inv1_INV_0 drives + multiple loads. +WARNING:Pack:2515 - The LUT-1 inverter "ftop/flash0/flashC_tsd/OE_inv1_INV_0" + failed to join the OLOGIC comp matched to output buffer + "ftop/flash0/flashC_tsd/IO_9_IOBUF/OBUFT". This may result in suboptimal + timing. The LUT-1 inverter ftop/flash0/flashC_tsd/OE_inv1_INV_0 drives + multiple loads. +WARNING:Timing:3175 - gmii_gtx_clk does not clock data to gmii_txd<7> +WARNING:Timing:3225 - Timing constraint COMP "gmii_txd<7>" OFFSET = OUT 6 ns AFTER COMP "gmii_gtx_clk" ignored during timing analysis +WARNING:Timing:3175 - gmii_gtx_clk does not clock data to gmii_txd<6> +WARNING:Timing:3225 - Timing constraint COMP "gmii_txd<6>" OFFSET = OUT 6 ns AFTER COMP "gmii_gtx_clk" ignored during timing analysis +WARNING:Timing:3175 - gmii_gtx_clk does not clock data to gmii_txd<5> +WARNING:Timing:3225 - Timing constraint COMP "gmii_txd<5>" OFFSET = OUT 6 ns AFTER COMP "gmii_gtx_clk" ignored during timing analysis +WARNING:Timing:3175 - gmii_gtx_clk does not clock data to gmii_txd<4> +WARNING:Timing:3225 - Timing constraint COMP "gmii_txd<4>" OFFSET = OUT 6 ns AFTER COMP "gmii_gtx_clk" ignored during timing analysis +WARNING:Timing:3175 - gmii_gtx_clk does not clock data to gmii_txd<3> +WARNING:Timing:3225 - Timing constraint COMP "gmii_txd<3>" OFFSET = OUT 6 ns AFTER COMP "gmii_gtx_clk" ignored during timing analysis +WARNING:Timing:3175 - gmii_gtx_clk does not clock data to gmii_txd<2> +WARNING:Timing:3225 - Timing constraint COMP "gmii_txd<2>" OFFSET = OUT 6 ns AFTER COMP "gmii_gtx_clk" ignored during timing analysis +WARNING:Timing:3175 - gmii_gtx_clk does not clock data to gmii_txd<1> +WARNING:Timing:3225 - Timing constraint COMP "gmii_txd<1>" OFFSET = OUT 6 ns AFTER COMP "gmii_gtx_clk" ignored during timing analysis +WARNING:Timing:3175 - gmii_gtx_clk does not clock data to gmii_txd<0> +WARNING:Timing:3225 - Timing constraint COMP "gmii_txd<0>" OFFSET = OUT 6 ns AFTER COMP "gmii_gtx_clk" ignored during timing analysis +WARNING:Timing:3175 - gmii_gtx_clk does not clock data to gmii_tx_en +WARNING:Timing:3225 - Timing constraint COMP "gmii_tx_en" OFFSET = OUT 6 ns AFTER COMP "gmii_gtx_clk" ignored during timing analysis +WARNING:Timing:3175 - gmii_gtx_clk does not clock data to gmii_tx_er +WARNING:Timing:3225 - Timing constraint COMP "gmii_tx_er" OFFSET = OUT 6 ns AFTER COMP "gmii_gtx_clk" ignored during timing analysis +WARNING:Place - MMCM comp ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv is + driving load + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdcl + k_gen/gen_ck_cpt[5].u_oserdes_cpt (type OLOGIC) + The load component should be of clock buffer type. +WARNING:Place - MMCM comp ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv is + driving load + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdcl + k_gen/gen_ck_cpt[2].u_oserdes_cpt (type OLOGIC) + The load component should be of clock buffer type. +WARNING:Place - MMCM comp ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv is + driving load + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdcl + k_gen/gen_loop_col1.u_oserdes_rsync (type OLOGIC) + The load component should be of clock buffer type. +WARNING:Place - MMCM comp ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv is + driving load + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdcl + k_gen/gen_ck_cpt[6].u_oserdes_cpt (type OLOGIC) + The load component should be of clock buffer type. +WARNING:Place - MMCM comp ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv is + driving load + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdcl + k_gen/gen_ck_cpt[3].u_oserdes_cpt (type OLOGIC) + The load component should be of clock buffer type. +WARNING:Place - MMCM comp ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv is + driving load + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdcl + k_gen/gen_ck_cpt[0].u_oserdes_cpt (type OLOGIC) + The load component should be of clock buffer type. +WARNING:Place - MMCM comp ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv is + driving load + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdcl + k_gen/gen_loop_col0.u_oserdes_rsync (type OLOGIC) + The load component should be of clock buffer type. +WARNING:Place - MMCM comp ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv is + driving load + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdcl + k_gen/gen_ck_cpt[7].u_oserdes_cpt (type OLOGIC) + The load component should be of clock buffer type. +WARNING:Place - MMCM comp ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv is + driving load + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdcl + k_gen/gen_ck_cpt[4].u_oserdes_cpt (type OLOGIC) + The load component should be of clock buffer type. +WARNING:Place - MMCM comp ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv is + driving load + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdcl + k_gen/gen_ck_cpt[1].u_oserdes_cpt (type OLOGIC) + The load component should be of clock buffer type. +WARNING:Place - MMCM comp ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv is + driving load + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdcl + k_gen/gen_ck_cpt[5].u_oserdes_cpt (type OLOGIC) + The load component should be of clock buffer type. +WARNING:Place - MMCM comp ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv is + driving load + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdcl + k_gen/gen_ck_cpt[2].u_oserdes_cpt (type OLOGIC) + The load component should be of clock buffer type. +WARNING:Place - MMCM comp ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv is + driving load + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdcl + k_gen/gen_loop_col1.u_oserdes_rsync (type OLOGIC) + The load component should be of clock buffer type. +WARNING:Place - MMCM comp ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv is + driving load + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdcl + k_gen/gen_ck_cpt[6].u_oserdes_cpt (type OLOGIC) + The load component should be of clock buffer type. +WARNING:Place - MMCM comp ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv is + driving load + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdcl + k_gen/gen_ck_cpt[3].u_oserdes_cpt (type OLOGIC) + The load component should be of clock buffer type. +WARNING:Place - MMCM comp ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv is + driving load + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdcl + k_gen/gen_ck_cpt[0].u_oserdes_cpt (type OLOGIC) + The load component should be of clock buffer type. +WARNING:Place - MMCM comp ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv is + driving load + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdcl + k_gen/gen_loop_col0.u_oserdes_rsync (type OLOGIC) + The load component should be of clock buffer type. +WARNING:Place - MMCM comp ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv is + driving load + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdcl + k_gen/gen_ck_cpt[7].u_oserdes_cpt (type OLOGIC) + The load component should be of clock buffer type. +WARNING:Place - MMCM comp ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv is + driving load + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdcl + k_gen/gen_ck_cpt[4].u_oserdes_cpt (type OLOGIC) + The load component should be of clock buffer type. +WARNING:Place - MMCM comp ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv is + driving load + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdcl + k_gen/gen_ck_cpt[1].u_oserdes_cpt (type OLOGIC) + The load component should be of clock buffer type. +WARNING:Place - MMCM comp ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv is driving load + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[5].u_oserdes_cpt (type + OLOGIC) + The load component should be of clock buffer type. +WARNING:Place - MMCM comp ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv is driving load + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[2].u_oserdes_cpt (type + OLOGIC) + The load component should be of clock buffer type. +WARNING:Place - MMCM comp ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv is driving load + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_loop_col1.u_oserdes_rsync + (type OLOGIC) + The load component should be of clock buffer type. +WARNING:Place - MMCM comp ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv is driving load + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[6].u_oserdes_cpt (type + OLOGIC) + The load component should be of clock buffer type. +WARNING:Place - MMCM comp ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv is driving load + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[3].u_oserdes_cpt (type + OLOGIC) + The load component should be of clock buffer type. +WARNING:Place - MMCM comp ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv is driving load + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[0].u_oserdes_cpt (type + OLOGIC) + The load component should be of clock buffer type. +WARNING:Place - MMCM comp ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv is driving load + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_loop_col0.u_oserdes_rsync + (type OLOGIC) + The load component should be of clock buffer type. +WARNING:Place - MMCM comp ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv is driving load + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[7].u_oserdes_cpt (type + OLOGIC) + The load component should be of clock buffer type. +WARNING:Place - MMCM comp ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv is driving load + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[4].u_oserdes_cpt (type + OLOGIC) + The load component should be of clock buffer type. +WARNING:Place - MMCM comp ftop/dram0/memc_memc/u_infrastructure/u_mmcm_adv is driving load + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[1].u_oserdes_cpt (type + OLOGIC) + The load component should be of clock buffer type. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive + any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive + any load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive + any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive any + load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive any load + pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive + any load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive any load + pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive any load + pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive any + load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive any load + pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive any load + pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive any load + pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive any + load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive any + load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive any + load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive any load + pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive any + load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive any + load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive any + load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive any + load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive any load + pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive any load + pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is incomplete. + The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive any + load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive any load + pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive any + load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive any + load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive any load + pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive any + load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive any + load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is + incomplete. The signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive any + load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive any load + pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive any load + pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive any load + pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive any load + pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal + is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal > is incomplete. The signal does not drive any + load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal + does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does + not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not drive + any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not + drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not drive + any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not drive + any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not drive + any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not drive + any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not drive + any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not drive + any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not drive + any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not drive + any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not drive + any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not drive + any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not drive + any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not drive + any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not drive + any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not drive + any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not drive + any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not drive + any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not drive + any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not drive + any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not drive + any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not drive + any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not drive + any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not drive + any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The signal does not drive + any load pins in the design. +WARNING:PhysDesignRules:2045 - The MMCM_ADV block has CLKOUT pins + that do not drive the same kind of BUFFER load. Routing from the different buffer types will not be phase aligned. + +Section 3 - Informational +------------------------- +INFO:Map:284 - Map is running with the multi-threading option on. Map currently + supports the use of up to 2 processors. Based on the the user options and + machine load, Map will use 2 processors during this run. +INFO:LIT:243 - Logical network N100 has no load. +INFO:LIT:395 - The above info message is repeated 4347 more times for the + following (max. 5 shown): + N101, + N102, + N103, + N104, + N105 + To see the details of these info messages, please use the -detail switch. +INFO:MapLib:562 - No environment variables are currently set. +INFO:LIT:244 - All of the single ended outputs in this design are using slew + rate limited output drivers. The delay on speed critical single ended outputs + can be dramatically reduced by designating them as fast outputs. +INFO:Pack:1716 - Initializing temperature to 85.000 Celsius. (default - Range: + 0.000 to 85.000 Celsius) +INFO:Pack:1720 - Initializing voltage to 0.950 Volts. (default - Range: 0.950 to + 1.050 Volts) +INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report + (.mrp). +INFO:Pack:1679 - FLOP symbol "ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/phy_init_data_sel_REPLICA_18" + (Output Signal = ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/phy_init_data_sel_REPLICA_18) was replicated + from FLOP symbol "ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_init/u_ff_phy_init_data_sel" (Output + Signal = ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/phy_init_data_sel) +INFO:Pack:1679 - FLOP symbol "ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/phy_init_data_sel_REPLICA_19" + (Output Signal = ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/phy_init_data_sel_REPLICA_19) was replicated + from FLOP symbol "ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_init/u_ff_phy_init_data_sel" (Output + Signal = ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/phy_init_data_sel) +INFO:Pack:1679 - FLOP symbol "ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/phy_init_data_sel_REPLICA_20" + (Output Signal = ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/phy_init_data_sel_REPLICA_20) was replicated + from FLOP symbol "ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_init/u_ff_phy_init_data_sel" (Output + Signal = ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/phy_init_data_sel) +INFO:Pack:1679 - FLOP symbol "ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/phy_init_data_sel_REPLICA_21" + (Output Signal = ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/phy_init_data_sel_REPLICA_21) was replicated + from FLOP symbol "ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_init/u_ff_phy_init_data_sel" (Output + Signal = ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/phy_init_data_sel) +INFO:Pack:1679 - FLOP symbol "ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/phy_init_data_sel_REPLICA_22" + (Output Signal = ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/phy_init_data_sel_REPLICA_22) was replicated + from FLOP symbol "ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_init/u_ff_phy_init_data_sel" (Output + Signal = ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/phy_init_data_sel) +INFO:Pack:1679 - FLOP symbol "ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/phy_init_data_sel_REPLICA_23" + (Output Signal = ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/phy_init_data_sel_REPLICA_23) was replicated + from FLOP symbol "ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_init/u_ff_phy_init_data_sel" (Output + Signal = ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/phy_init_data_sel) +INFO:Pack:1679 - FLOP symbol "ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/phy_init_data_sel_REPLICA_24" + (Output Signal = ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/phy_init_data_sel_REPLICA_24) was replicated + from FLOP symbol "ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_init/u_ff_phy_init_data_sel" (Output + Signal = ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/phy_init_data_sel) +INFO:Pack:1679 - FLOP symbol "ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/phy_init_data_sel_REPLICA_25" + (Output Signal = ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/phy_init_data_sel_REPLICA_25) was replicated + from FLOP symbol "ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_init/u_ff_phy_init_data_sel" (Output + Signal = ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/phy_init_data_sel) +INFO:Pack:1679 - FLOP symbol "ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/phy_init_data_sel_REPLICA_26" + (Output Signal = ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/phy_init_data_sel_REPLICA_26) was replicated + from FLOP symbol "ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_init/u_ff_phy_init_data_sel" (Output + Signal = ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/phy_init_data_sel) +INFO:Pack:1679 - FLOP symbol "ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/phy_init_data_sel_REPLICA_27" + (Output Signal = ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/phy_init_data_sel_REPLICA_27) was replicated + from FLOP symbol "ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_init/u_ff_phy_init_data_sel" (Output + Signal = ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/phy_init_data_sel) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<6>_REPLICA_28" (Output Signal = + ftop/ctop/inf/cp/cpReq<6>_REPLICA_28) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_6" (Output Signal = + ftop/ctop/inf/cp/cpReq<6>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<6>_REPLICA_29" (Output Signal = + ftop/ctop/inf/cp/cpReq<6>_REPLICA_29) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_6" (Output Signal = + ftop/ctop/inf/cp/cpReq<6>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<6>_REPLICA_30" (Output Signal = + ftop/ctop/inf/cp/cpReq<6>_REPLICA_30) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_6" (Output Signal = + ftop/ctop/inf/cp/cpReq<6>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<6>_REPLICA_31" (Output Signal = + ftop/ctop/inf/cp/cpReq<6>_REPLICA_31) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_6" (Output Signal = + ftop/ctop/inf/cp/cpReq<6>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<6>_REPLICA_32" (Output Signal = + ftop/ctop/inf/cp/cpReq<6>_REPLICA_32) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_6" (Output Signal = + ftop/ctop/inf/cp/cpReq<6>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<6>_REPLICA_33" (Output Signal = + ftop/ctop/inf/cp/cpReq<6>_REPLICA_33) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_6" (Output Signal = + ftop/ctop/inf/cp/cpReq<6>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<6>_REPLICA_34" (Output Signal = + ftop/ctop/inf/cp/cpReq<6>_REPLICA_34) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_6" (Output Signal = + ftop/ctop/inf/cp/cpReq<6>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<6>_REPLICA_35" (Output Signal = + ftop/ctop/inf/cp/cpReq<6>_REPLICA_35) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_6" (Output Signal = + ftop/ctop/inf/cp/cpReq<6>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<6>_REPLICA_36" (Output Signal = + ftop/ctop/inf/cp/cpReq<6>_REPLICA_36) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_6" (Output Signal = + ftop/ctop/inf/cp/cpReq<6>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<6>_REPLICA_37" (Output Signal = + ftop/ctop/inf/cp/cpReq<6>_REPLICA_37) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_6" (Output Signal = + ftop/ctop/inf/cp/cpReq<6>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<6>_REPLICA_38" (Output Signal = + ftop/ctop/inf/cp/cpReq<6>_REPLICA_38) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_6" (Output Signal = + ftop/ctop/inf/cp/cpReq<6>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<7>_REPLICA_39" (Output Signal = + ftop/ctop/inf/cp/cpReq<7>_REPLICA_39) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_7" (Output Signal = + ftop/ctop/inf/cp/cpReq<7>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<7>_REPLICA_40" (Output Signal = + ftop/ctop/inf/cp/cpReq<7>_REPLICA_40) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_7" (Output Signal = + ftop/ctop/inf/cp/cpReq<7>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<7>_REPLICA_41" (Output Signal = + ftop/ctop/inf/cp/cpReq<7>_REPLICA_41) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_7" (Output Signal = + ftop/ctop/inf/cp/cpReq<7>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<7>_REPLICA_42" (Output Signal = + ftop/ctop/inf/cp/cpReq<7>_REPLICA_42) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_7" (Output Signal = + ftop/ctop/inf/cp/cpReq<7>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<7>_REPLICA_43" (Output Signal = + ftop/ctop/inf/cp/cpReq<7>_REPLICA_43) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_7" (Output Signal = + ftop/ctop/inf/cp/cpReq<7>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<7>_REPLICA_44" (Output Signal = + ftop/ctop/inf/cp/cpReq<7>_REPLICA_44) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_7" (Output Signal = + ftop/ctop/inf/cp/cpReq<7>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<7>_REPLICA_45" (Output Signal = + ftop/ctop/inf/cp/cpReq<7>_REPLICA_45) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_7" (Output Signal = + ftop/ctop/inf/cp/cpReq<7>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<7>_REPLICA_46" (Output Signal = + ftop/ctop/inf/cp/cpReq<7>_REPLICA_46) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_7" (Output Signal = + ftop/ctop/inf/cp/cpReq<7>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<7>_REPLICA_47" (Output Signal = + ftop/ctop/inf/cp/cpReq<7>_REPLICA_47) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_7" (Output Signal = + ftop/ctop/inf/cp/cpReq<7>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<7>_REPLICA_48" (Output Signal = + ftop/ctop/inf/cp/cpReq<7>_REPLICA_48) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_7" (Output Signal = + ftop/ctop/inf/cp/cpReq<7>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<7>_REPLICA_49" (Output Signal = + ftop/ctop/inf/cp/cpReq<7>_REPLICA_49) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_7" (Output Signal = + ftop/ctop/inf/cp/cpReq<7>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<8>_REPLICA_50" (Output Signal = + ftop/ctop/inf/cp/cpReq<8>_REPLICA_50) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_8" (Output Signal = + ftop/ctop/inf/cp/cpReq<8>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<8>_REPLICA_51" (Output Signal = + ftop/ctop/inf/cp/cpReq<8>_REPLICA_51) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_8" (Output Signal = + ftop/ctop/inf/cp/cpReq<8>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<8>_REPLICA_52" (Output Signal = + ftop/ctop/inf/cp/cpReq<8>_REPLICA_52) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_8" (Output Signal = + ftop/ctop/inf/cp/cpReq<8>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<8>_REPLICA_53" (Output Signal = + ftop/ctop/inf/cp/cpReq<8>_REPLICA_53) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_8" (Output Signal = + ftop/ctop/inf/cp/cpReq<8>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<8>_REPLICA_54" (Output Signal = + ftop/ctop/inf/cp/cpReq<8>_REPLICA_54) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_8" (Output Signal = + ftop/ctop/inf/cp/cpReq<8>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<8>_REPLICA_55" (Output Signal = + ftop/ctop/inf/cp/cpReq<8>_REPLICA_55) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_8" (Output Signal = + ftop/ctop/inf/cp/cpReq<8>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<8>_REPLICA_56" (Output Signal = + ftop/ctop/inf/cp/cpReq<8>_REPLICA_56) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_8" (Output Signal = + ftop/ctop/inf/cp/cpReq<8>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<8>_REPLICA_57" (Output Signal = + ftop/ctop/inf/cp/cpReq<8>_REPLICA_57) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_8" (Output Signal = + ftop/ctop/inf/cp/cpReq<8>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<8>_REPLICA_58" (Output Signal = + ftop/ctop/inf/cp/cpReq<8>_REPLICA_58) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_8" (Output Signal = + ftop/ctop/inf/cp/cpReq<8>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<8>_REPLICA_59" (Output Signal = + ftop/ctop/inf/cp/cpReq<8>_REPLICA_59) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_8" (Output Signal = + ftop/ctop/inf/cp/cpReq<8>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<20>_REPLICA_77" (Output Signal = + ftop/ctop/inf/cp/cpReq<20>_REPLICA_77) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_20" (Output Signal = + ftop/ctop/inf/cp/cpReq<20>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<20>_REPLICA_78" (Output Signal = + ftop/ctop/inf/cp/cpReq<20>_REPLICA_78) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_20" (Output Signal = + ftop/ctop/inf/cp/cpReq<20>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<20>_REPLICA_79" (Output Signal = + ftop/ctop/inf/cp/cpReq<20>_REPLICA_79) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_20" (Output Signal = + ftop/ctop/inf/cp/cpReq<20>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<20>_REPLICA_80" (Output Signal = + ftop/ctop/inf/cp/cpReq<20>_REPLICA_80) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_20" (Output Signal = + ftop/ctop/inf/cp/cpReq<20>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<20>_REPLICA_81" (Output Signal = + ftop/ctop/inf/cp/cpReq<20>_REPLICA_81) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_20" (Output Signal = + ftop/ctop/inf/cp/cpReq<20>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<20>_REPLICA_82" (Output Signal = + ftop/ctop/inf/cp/cpReq<20>_REPLICA_82) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_20" (Output Signal = + ftop/ctop/inf/cp/cpReq<20>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<20>_REPLICA_83" (Output Signal = + ftop/ctop/inf/cp/cpReq<20>_REPLICA_83) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_20" (Output Signal = + ftop/ctop/inf/cp/cpReq<20>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<20>_REPLICA_84" (Output Signal = + ftop/ctop/inf/cp/cpReq<20>_REPLICA_84) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_20" (Output Signal = + ftop/ctop/inf/cp/cpReq<20>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<20>_REPLICA_85" (Output Signal = + ftop/ctop/inf/cp/cpReq<20>_REPLICA_85) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_20" (Output Signal = + ftop/ctop/inf/cp/cpReq<20>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<20>_REPLICA_86" (Output Signal = + ftop/ctop/inf/cp/cpReq<20>_REPLICA_86) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_20" (Output Signal = + ftop/ctop/inf/cp/cpReq<20>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<20>_REPLICA_87" (Output Signal = + ftop/ctop/inf/cp/cpReq<20>_REPLICA_87) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_20" (Output Signal = + ftop/ctop/inf/cp/cpReq<20>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<20>_REPLICA_88" (Output Signal = + ftop/ctop/inf/cp/cpReq<20>_REPLICA_88) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_20" (Output Signal = + ftop/ctop/inf/cp/cpReq<20>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<20>_REPLICA_89" (Output Signal = + ftop/ctop/inf/cp/cpReq<20>_REPLICA_89) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_20" (Output Signal = + ftop/ctop/inf/cp/cpReq<20>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<20>_REPLICA_90" (Output Signal = + ftop/ctop/inf/cp/cpReq<20>_REPLICA_90) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_20" (Output Signal = + ftop/ctop/inf/cp/cpReq<20>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<20>_REPLICA_91" (Output Signal = + ftop/ctop/inf/cp/cpReq<20>_REPLICA_91) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_20" (Output Signal = + ftop/ctop/inf/cp/cpReq<20>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<20>_REPLICA_92" (Output Signal = + ftop/ctop/inf/cp/cpReq<20>_REPLICA_92) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_20" (Output Signal = + ftop/ctop/inf/cp/cpReq<20>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<20>_REPLICA_93" (Output Signal = + ftop/ctop/inf/cp/cpReq<20>_REPLICA_93) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_20" (Output Signal = + ftop/ctop/inf/cp/cpReq<20>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<20>_REPLICA_94" (Output Signal = + ftop/ctop/inf/cp/cpReq<20>_REPLICA_94) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_20" (Output Signal = + ftop/ctop/inf/cp/cpReq<20>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<20>_REPLICA_95" (Output Signal = + ftop/ctop/inf/cp/cpReq<20>_REPLICA_95) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_20" (Output Signal = + ftop/ctop/inf/cp/cpReq<20>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<20>_REPLICA_96" (Output Signal = + ftop/ctop/inf/cp/cpReq<20>_REPLICA_96) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_20" (Output Signal = + ftop/ctop/inf/cp/cpReq<20>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<20>_REPLICA_97" (Output Signal = + ftop/ctop/inf/cp/cpReq<20>_REPLICA_97) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_20" (Output Signal = + ftop/ctop/inf/cp/cpReq<20>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<20>_REPLICA_98" (Output Signal = + ftop/ctop/inf/cp/cpReq<20>_REPLICA_98) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_20" (Output Signal = + ftop/ctop/inf/cp/cpReq<20>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<20>_REPLICA_99" (Output Signal = + ftop/ctop/inf/cp/cpReq<20>_REPLICA_99) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_20" (Output Signal = + ftop/ctop/inf/cp/cpReq<20>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<20>_REPLICA_100" (Output Signal = + ftop/ctop/inf/cp/cpReq<20>_REPLICA_100) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_20" (Output Signal = + ftop/ctop/inf/cp/cpReq<20>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<20>_REPLICA_101" (Output Signal = + ftop/ctop/inf/cp/cpReq<20>_REPLICA_101) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_20" (Output Signal = + ftop/ctop/inf/cp/cpReq<20>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<20>_REPLICA_102" (Output Signal = + ftop/ctop/inf/cp/cpReq<20>_REPLICA_102) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_20" (Output Signal = + ftop/ctop/inf/cp/cpReq<20>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<21>_REPLICA_168" (Output Signal = + ftop/ctop/inf/cp/cpReq<21>_REPLICA_168) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_21" (Output Signal = + ftop/ctop/inf/cp/cpReq<21>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<21>_REPLICA_169" (Output Signal = + ftop/ctop/inf/cp/cpReq<21>_REPLICA_169) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_21" (Output Signal = + ftop/ctop/inf/cp/cpReq<21>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<21>_REPLICA_170" (Output Signal = + ftop/ctop/inf/cp/cpReq<21>_REPLICA_170) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_21" (Output Signal = + ftop/ctop/inf/cp/cpReq<21>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<21>_REPLICA_171" (Output Signal = + ftop/ctop/inf/cp/cpReq<21>_REPLICA_171) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_21" (Output Signal = + ftop/ctop/inf/cp/cpReq<21>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<21>_REPLICA_172" (Output Signal = + ftop/ctop/inf/cp/cpReq<21>_REPLICA_172) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_21" (Output Signal = + ftop/ctop/inf/cp/cpReq<21>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<21>_REPLICA_173" (Output Signal = + ftop/ctop/inf/cp/cpReq<21>_REPLICA_173) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_21" (Output Signal = + ftop/ctop/inf/cp/cpReq<21>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<21>_REPLICA_174" (Output Signal = + ftop/ctop/inf/cp/cpReq<21>_REPLICA_174) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_21" (Output Signal = + ftop/ctop/inf/cp/cpReq<21>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<21>_REPLICA_175" (Output Signal = + ftop/ctop/inf/cp/cpReq<21>_REPLICA_175) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_21" (Output Signal = + ftop/ctop/inf/cp/cpReq<21>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<21>_REPLICA_176" (Output Signal = + ftop/ctop/inf/cp/cpReq<21>_REPLICA_176) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_21" (Output Signal = + ftop/ctop/inf/cp/cpReq<21>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<21>_REPLICA_177" (Output Signal = + ftop/ctop/inf/cp/cpReq<21>_REPLICA_177) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_21" (Output Signal = + ftop/ctop/inf/cp/cpReq<21>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<21>_REPLICA_178" (Output Signal = + ftop/ctop/inf/cp/cpReq<21>_REPLICA_178) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_21" (Output Signal = + ftop/ctop/inf/cp/cpReq<21>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<21>_REPLICA_179" (Output Signal = + ftop/ctop/inf/cp/cpReq<21>_REPLICA_179) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_21" (Output Signal = + ftop/ctop/inf/cp/cpReq<21>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<21>_REPLICA_180" (Output Signal = + ftop/ctop/inf/cp/cpReq<21>_REPLICA_180) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_21" (Output Signal = + ftop/ctop/inf/cp/cpReq<21>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<21>_REPLICA_181" (Output Signal = + ftop/ctop/inf/cp/cpReq<21>_REPLICA_181) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_21" (Output Signal = + ftop/ctop/inf/cp/cpReq<21>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<21>_REPLICA_182" (Output Signal = + ftop/ctop/inf/cp/cpReq<21>_REPLICA_182) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_21" (Output Signal = + ftop/ctop/inf/cp/cpReq<21>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<21>_REPLICA_183" (Output Signal = + ftop/ctop/inf/cp/cpReq<21>_REPLICA_183) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_21" (Output Signal = + ftop/ctop/inf/cp/cpReq<21>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<21>_REPLICA_184" (Output Signal = + ftop/ctop/inf/cp/cpReq<21>_REPLICA_184) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_21" (Output Signal = + ftop/ctop/inf/cp/cpReq<21>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<21>_REPLICA_185" (Output Signal = + ftop/ctop/inf/cp/cpReq<21>_REPLICA_185) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_21" (Output Signal = + ftop/ctop/inf/cp/cpReq<21>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<21>_REPLICA_186" (Output Signal = + ftop/ctop/inf/cp/cpReq<21>_REPLICA_186) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_21" (Output Signal = + ftop/ctop/inf/cp/cpReq<21>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<23>_REPLICA_321" (Output Signal = + ftop/ctop/inf/cp/cpReq<23>_REPLICA_321) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_23" (Output Signal = + ftop/ctop/inf/cp/cpReq<23>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<23>_REPLICA_322" (Output Signal = + ftop/ctop/inf/cp/cpReq<23>_REPLICA_322) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_23" (Output Signal = + ftop/ctop/inf/cp/cpReq<23>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<23>_REPLICA_323" (Output Signal = + ftop/ctop/inf/cp/cpReq<23>_REPLICA_323) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_23" (Output Signal = + ftop/ctop/inf/cp/cpReq<23>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<23>_REPLICA_324" (Output Signal = + ftop/ctop/inf/cp/cpReq<23>_REPLICA_324) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_23" (Output Signal = + ftop/ctop/inf/cp/cpReq<23>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<23>_REPLICA_325" (Output Signal = + ftop/ctop/inf/cp/cpReq<23>_REPLICA_325) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_23" (Output Signal = + ftop/ctop/inf/cp/cpReq<23>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<23>_REPLICA_326" (Output Signal = + ftop/ctop/inf/cp/cpReq<23>_REPLICA_326) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_23" (Output Signal = + ftop/ctop/inf/cp/cpReq<23>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<23>_REPLICA_327" (Output Signal = + ftop/ctop/inf/cp/cpReq<23>_REPLICA_327) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_23" (Output Signal = + ftop/ctop/inf/cp/cpReq<23>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<23>_REPLICA_328" (Output Signal = + ftop/ctop/inf/cp/cpReq<23>_REPLICA_328) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_23" (Output Signal = + ftop/ctop/inf/cp/cpReq<23>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<23>_REPLICA_329" (Output Signal = + ftop/ctop/inf/cp/cpReq<23>_REPLICA_329) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_23" (Output Signal = + ftop/ctop/inf/cp/cpReq<23>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<23>_REPLICA_330" (Output Signal = + ftop/ctop/inf/cp/cpReq<23>_REPLICA_330) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_23" (Output Signal = + ftop/ctop/inf/cp/cpReq<23>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<23>_REPLICA_331" (Output Signal = + ftop/ctop/inf/cp/cpReq<23>_REPLICA_331) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_23" (Output Signal = + ftop/ctop/inf/cp/cpReq<23>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<23>_REPLICA_332" (Output Signal = + ftop/ctop/inf/cp/cpReq<23>_REPLICA_332) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_23" (Output Signal = + ftop/ctop/inf/cp/cpReq<23>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<23>_REPLICA_333" (Output Signal = + ftop/ctop/inf/cp/cpReq<23>_REPLICA_333) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_23" (Output Signal = + ftop/ctop/inf/cp/cpReq<23>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<23>_REPLICA_334" (Output Signal = + ftop/ctop/inf/cp/cpReq<23>_REPLICA_334) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_23" (Output Signal = + ftop/ctop/inf/cp/cpReq<23>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<23>_REPLICA_335" (Output Signal = + ftop/ctop/inf/cp/cpReq<23>_REPLICA_335) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_23" (Output Signal = + ftop/ctop/inf/cp/cpReq<23>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<23>_REPLICA_336" (Output Signal = + ftop/ctop/inf/cp/cpReq<23>_REPLICA_336) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_23" (Output Signal = + ftop/ctop/inf/cp/cpReq<23>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<23>_REPLICA_337" (Output Signal = + ftop/ctop/inf/cp/cpReq<23>_REPLICA_337) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_23" (Output Signal = + ftop/ctop/inf/cp/cpReq<23>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<23>_REPLICA_338" (Output Signal = + ftop/ctop/inf/cp/cpReq<23>_REPLICA_338) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_23" (Output Signal = + ftop/ctop/inf/cp/cpReq<23>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<23>_REPLICA_339" (Output Signal = + ftop/ctop/inf/cp/cpReq<23>_REPLICA_339) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_23" (Output Signal = + ftop/ctop/inf/cp/cpReq<23>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<23>_REPLICA_340" (Output Signal = + ftop/ctop/inf/cp/cpReq<23>_REPLICA_340) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_23" (Output Signal = + ftop/ctop/inf/cp/cpReq<23>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<37>_REPLICA_371" (Output Signal = + ftop/ctop/inf/cp/cpReq<37>_REPLICA_371) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_37" (Output Signal = + ftop/ctop/inf/cp/cpReq<37>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<37>_REPLICA_372" (Output Signal = + ftop/ctop/inf/cp/cpReq<37>_REPLICA_372) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_37" (Output Signal = + ftop/ctop/inf/cp/cpReq<37>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<37>_REPLICA_373" (Output Signal = + ftop/ctop/inf/cp/cpReq<37>_REPLICA_373) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_37" (Output Signal = + ftop/ctop/inf/cp/cpReq<37>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<37>_REPLICA_374" (Output Signal = + ftop/ctop/inf/cp/cpReq<37>_REPLICA_374) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_37" (Output Signal = + ftop/ctop/inf/cp/cpReq<37>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<37>_REPLICA_375" (Output Signal = + ftop/ctop/inf/cp/cpReq<37>_REPLICA_375) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_37" (Output Signal = + ftop/ctop/inf/cp/cpReq<37>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<37>_REPLICA_376" (Output Signal = + ftop/ctop/inf/cp/cpReq<37>_REPLICA_376) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_37" (Output Signal = + ftop/ctop/inf/cp/cpReq<37>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<37>_REPLICA_377" (Output Signal = + ftop/ctop/inf/cp/cpReq<37>_REPLICA_377) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_37" (Output Signal = + ftop/ctop/inf/cp/cpReq<37>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<37>_REPLICA_378" (Output Signal = + ftop/ctop/inf/cp/cpReq<37>_REPLICA_378) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_37" (Output Signal = + ftop/ctop/inf/cp/cpReq<37>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<37>_REPLICA_379" (Output Signal = + ftop/ctop/inf/cp/cpReq<37>_REPLICA_379) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_37" (Output Signal = + ftop/ctop/inf/cp/cpReq<37>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<37>_REPLICA_380" (Output Signal = + ftop/ctop/inf/cp/cpReq<37>_REPLICA_380) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_37" (Output Signal = + ftop/ctop/inf/cp/cpReq<37>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<37>_REPLICA_381" (Output Signal = + ftop/ctop/inf/cp/cpReq<37>_REPLICA_381) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_37" (Output Signal = + ftop/ctop/inf/cp/cpReq<37>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<37>_REPLICA_382" (Output Signal = + ftop/ctop/inf/cp/cpReq<37>_REPLICA_382) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_37" (Output Signal = + ftop/ctop/inf/cp/cpReq<37>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<37>_REPLICA_383" (Output Signal = + ftop/ctop/inf/cp/cpReq<37>_REPLICA_383) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_37" (Output Signal = + ftop/ctop/inf/cp/cpReq<37>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<27>_REPLICA_390" (Output Signal = + ftop/ctop/inf/cp/cpReq<27>_REPLICA_390) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_27" (Output Signal = + ftop/ctop/inf/cp/cpReq<27>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<27>_REPLICA_391" (Output Signal = + ftop/ctop/inf/cp/cpReq<27>_REPLICA_391) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_27" (Output Signal = + ftop/ctop/inf/cp/cpReq<27>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<27>_REPLICA_392" (Output Signal = + ftop/ctop/inf/cp/cpReq<27>_REPLICA_392) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_27" (Output Signal = + ftop/ctop/inf/cp/cpReq<27>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<27>_REPLICA_393" (Output Signal = + ftop/ctop/inf/cp/cpReq<27>_REPLICA_393) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_27" (Output Signal = + ftop/ctop/inf/cp/cpReq<27>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<27>_REPLICA_394" (Output Signal = + ftop/ctop/inf/cp/cpReq<27>_REPLICA_394) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_27" (Output Signal = + ftop/ctop/inf/cp/cpReq<27>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<27>_REPLICA_395" (Output Signal = + ftop/ctop/inf/cp/cpReq<27>_REPLICA_395) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_27" (Output Signal = + ftop/ctop/inf/cp/cpReq<27>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<27>_REPLICA_396" (Output Signal = + ftop/ctop/inf/cp/cpReq<27>_REPLICA_396) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_27" (Output Signal = + ftop/ctop/inf/cp/cpReq<27>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<27>_REPLICA_397" (Output Signal = + ftop/ctop/inf/cp/cpReq<27>_REPLICA_397) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_27" (Output Signal = + ftop/ctop/inf/cp/cpReq<27>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<27>_REPLICA_398" (Output Signal = + ftop/ctop/inf/cp/cpReq<27>_REPLICA_398) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_27" (Output Signal = + ftop/ctop/inf/cp/cpReq<27>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<27>_REPLICA_399" (Output Signal = + ftop/ctop/inf/cp/cpReq<27>_REPLICA_399) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_27" (Output Signal = + ftop/ctop/inf/cp/cpReq<27>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<27>_REPLICA_400" (Output Signal = + ftop/ctop/inf/cp/cpReq<27>_REPLICA_400) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_27" (Output Signal = + ftop/ctop/inf/cp/cpReq<27>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<27>_REPLICA_401" (Output Signal = + ftop/ctop/inf/cp/cpReq<27>_REPLICA_401) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_27" (Output Signal = + ftop/ctop/inf/cp/cpReq<27>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<27>_REPLICA_402" (Output Signal = + ftop/ctop/inf/cp/cpReq<27>_REPLICA_402) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_27" (Output Signal = + ftop/ctop/inf/cp/cpReq<27>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<27>_REPLICA_403" (Output Signal = + ftop/ctop/inf/cp/cpReq<27>_REPLICA_403) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_27" (Output Signal = + ftop/ctop/inf/cp/cpReq<27>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<27>_REPLICA_404" (Output Signal = + ftop/ctop/inf/cp/cpReq<27>_REPLICA_404) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_27" (Output Signal = + ftop/ctop/inf/cp/cpReq<27>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<27>_REPLICA_405" (Output Signal = + ftop/ctop/inf/cp/cpReq<27>_REPLICA_405) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_27" (Output Signal = + ftop/ctop/inf/cp/cpReq<27>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<36>_REPLICA_543" (Output Signal = + ftop/ctop/inf/cp/cpReq<36>_REPLICA_543) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_36" (Output Signal = + ftop/ctop/inf/cp/cpReq<36>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<36>_REPLICA_544" (Output Signal = + ftop/ctop/inf/cp/cpReq<36>_REPLICA_544) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_36" (Output Signal = + ftop/ctop/inf/cp/cpReq<36>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<36>_REPLICA_545" (Output Signal = + ftop/ctop/inf/cp/cpReq<36>_REPLICA_545) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_36" (Output Signal = + ftop/ctop/inf/cp/cpReq<36>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<36>_REPLICA_546" (Output Signal = + ftop/ctop/inf/cp/cpReq<36>_REPLICA_546) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_36" (Output Signal = + ftop/ctop/inf/cp/cpReq<36>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<36>_REPLICA_547" (Output Signal = + ftop/ctop/inf/cp/cpReq<36>_REPLICA_547) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_36" (Output Signal = + ftop/ctop/inf/cp/cpReq<36>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<36>_REPLICA_548" (Output Signal = + ftop/ctop/inf/cp/cpReq<36>_REPLICA_548) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_36" (Output Signal = + ftop/ctop/inf/cp/cpReq<36>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<36>_REPLICA_549" (Output Signal = + ftop/ctop/inf/cp/cpReq<36>_REPLICA_549) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_36" (Output Signal = + ftop/ctop/inf/cp/cpReq<36>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<36>_REPLICA_550" (Output Signal = + ftop/ctop/inf/cp/cpReq<36>_REPLICA_550) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_36" (Output Signal = + ftop/ctop/inf/cp/cpReq<36>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<36>_REPLICA_551" (Output Signal = + ftop/ctop/inf/cp/cpReq<36>_REPLICA_551) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_36" (Output Signal = + ftop/ctop/inf/cp/cpReq<36>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<36>_REPLICA_552" (Output Signal = + ftop/ctop/inf/cp/cpReq<36>_REPLICA_552) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_36" (Output Signal = + ftop/ctop/inf/cp/cpReq<36>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<36>_REPLICA_553" (Output Signal = + ftop/ctop/inf/cp/cpReq<36>_REPLICA_553) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_36" (Output Signal = + ftop/ctop/inf/cp/cpReq<36>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<36>_REPLICA_554" (Output Signal = + ftop/ctop/inf/cp/cpReq<36>_REPLICA_554) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_36" (Output Signal = + ftop/ctop/inf/cp/cpReq<36>) +INFO:Pack:1679 - FLOP symbol "ftop/ctop/inf/cp/cpReq<36>_REPLICA_555" (Output Signal = + ftop/ctop/inf/cp/cpReq<36>_REPLICA_555) was replicated from FLOP symbol "ftop/ctop/inf/cp/cpReq_36" (Output Signal = + ftop/ctop/inf/cp/cpReq<36>) +INFO:Pack:1650 - Map created a placed design. + +Section 4 - Removed Logic Summary +--------------------------------- + 378 block(s) removed + 413 block(s) optimized away +1853 signal(s) removed + +Section 5 - Removed Logic +------------------------- + +The trimmed logic report below shows the logic removed from your design due to +sourceless or loadless signals, and VCC or ground connections. If the removal +of a signal or symbol results in the subsequent removal of an additional signal +or symbol, the message explaining that second removal will be indented. This +indentation will be repeated as a chain of related logic is removed. + +To quickly locate the original cause for the removal of a chain of logic, look +above the place where that logic is listed in the trimming report, then locate +the lines that are least indented (begin at the leftmost edge). + +Loadless block "ftop/ctop/inf/Msub_byteCount__h523511" (ROM) removed. +Loadless block "ftop/ctop/inf/dp0/Msub_byteCount__h29653[11:0]11" (ROM) removed. +Loadless block "ftop/ctop/inf/dp1/Msub_byteCount__h29653[11:0]11" (ROM) removed. +Loadless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/read_fifo.fifo_ram +[0].RAM32M0" (RAM32M) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/read_fifo.fifo_in_ +data_r<4>" is loadless and has been removed. + Loadless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/read_fifo.fifo_in_ +data_r_4" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/read_fifo.fifo_in_ +data_r<3>" is loadless and has been removed. + Loadless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/read_fifo.fifo_in_ +data_r_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/read_fifo.fifo_in_ +data_r<2>" is loadless and has been removed. + Loadless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/read_fifo.fifo_in_ +data_r_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/read_fifo.fifo_in_ +data_r<1>" is loadless and has been removed. + Loadless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/read_fifo.fifo_in_ +data_r_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/read_fifo.fifo_in_ +data_r<0>" is loadless and has been removed. + Loadless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/read_fifo.fifo_in_ +data_r_0" (FF) removed. +Loadless block "ftop/gbe0/gmac/gmii_rx_clk" (BUFIODQS) removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_tbuf_av<5>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_tbuf_av<4>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_tbuf_av<3>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_tbuf_av<2>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_tbuf_av<1>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_tbuf_av<0>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_cpld<11>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_cpld<10>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_cpld<9>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_cpld<8>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_cpld<7>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_cpld<6>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_cpld<5>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_cpld<4>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_cpld<3>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_cpld<2>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_cpld<1>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_cpld<0>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_cplh<7>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_cplh<6>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_cplh<5>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_cplh<4>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_cplh<3>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_cplh<2>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_cplh<1>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_cplh<0>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_npd<11>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_npd<10>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_npd<9>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_npd<8>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_npd<7>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_npd<6>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_npd<5>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_npd<4>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_npd<3>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_npd<2>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_npd<1>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_npd<0>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_nph<7>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_nph<6>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_nph<5>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_nph<4>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_nph<3>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_nph<2>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_nph<1>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_nph<0>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_pd<11>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_pd<10>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_pd<9>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_pd<8>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_pd<7>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_pd<6>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_pd<5>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_pd<4>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_pd<3>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_pd<2>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_pd<1>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_pd<0>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_ph<7>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_ph<6>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_ph<5>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_ph<4>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_ph<3>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_ph<2>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_ph<1>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_fc_ph<0>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<31>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<30>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<29>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<28>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<27>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<26>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<25>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<24>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<23>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<22>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<21>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<20>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<19>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<18>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<17>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<16>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<15>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<14>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<13>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<12>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<11>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<10>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<9>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<8>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<7>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<6>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<5>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<4>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<3>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<2>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<1>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_do<0>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_interrupt_do<7>" is sourceless and has +been removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_interrupt_do<6>" is sourceless and has +been removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_interrupt_do<5>" is sourceless and has +been removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_interrupt_do<4>" is sourceless and has +been removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_interrupt_do<3>" is sourceless and has +been removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_interrupt_do<2>" is sourceless and has +been removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_interrupt_do<1>" is sourceless and has +been removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_interrupt_do<0>" is sourceless and has +been removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_interrupt_mmenable<2>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_interrupt_mmenable<1>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_interrupt_mmenable<0>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_command<10>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_command<8>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_command<2>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_command<1>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_command<0>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_dstatus<3>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_dstatus<2>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_dstatus<1>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_dstatus<0>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_dcommand<14>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_dcommand<13>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_dcommand<12>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_dcommand<11>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_dcommand<10>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_dcommand<9>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_dcommand<8>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_dcommand<7>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_dcommand<6>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_dcommand<5>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_dcommand<4>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_dcommand<3>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_dcommand<2>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_dcommand<1>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_dcommand<0>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_lstatus<15>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_lstatus<14>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_lstatus<13>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_lstatus<11>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_lstatus<7>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_lstatus<6>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_lstatus<5>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_lstatus<4>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_lstatus<1>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_lstatus<0>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_lcommand<11>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_lcommand<10>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_lcommand<9>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_lcommand<8>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_lcommand<7>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_lcommand<6>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_lcommand<5>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_lcommand<4>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_lcommand<3>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_lcommand<1>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_lcommand<0>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_dcommand2<4>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_dcommand2<3>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_dcommand2<2>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_dcommand2<1>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_dcommand2<0>" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_pcie_link_state_n<2>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_pcie_link_state_n<1>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_pcie_link_state_n<0>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_pmcsr_powerstate<1>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_pmcsr_powerstate<0>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/pl_initial_link_width<2>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/pl_initial_link_width<1>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/pl_initial_link_width<0>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/pl_lane_reversal_mode<1>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/pl_lane_reversal_mode<0>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/pl_sel_link_width<1>" is sourceless and has +been removed. +The signal "ftop/pciw_pci0_pcie_ep/pl_sel_link_width<0>" is sourceless and has +been removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_tcfg_req_n" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_terr_drop_n" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_rsrc_dsc_n" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/trn_rerrfwd_n" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_rd_wr_done_n" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_err_cpl_rdy_n" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_interrupt_rdy_n" is sourceless and has +been removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_interrupt_msienable" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_interrupt_msixenable" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_interrupt_msixfm" is sourceless and has +been removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_pmcsr_pme_en" is sourceless and has been +removed. +The signal "ftop/pciw_pci0_pcie_ep/cfg_pmcsr_pme_status" is sourceless and has +been removed. +The signal "ftop/pciw_pci0_pcie_ep/pl_link_gen2_capable" is sourceless and has +been removed. +The signal "ftop/pciw_pci0_pcie_ep/pl_link_partner_gen2_supported" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/pl_link_upcfg_capable" is sourceless and has +been removed. +The signal "ftop/pciw_pci0_pcie_ep/pl_received_hot_rst" is sourceless and has +been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGTRANSACTIONADDR<6>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGTRANSACTIONADDR<5>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGTRANSACTIONADDR<4>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGTRANSACTIONADDR<3>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGTRANSACTIONADDR<2>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGTRANSACTIONADDR<1>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGTRANSACTIONADDR<0>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGVCTCVCMAP<6>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGVCTCVCMAP<5>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGVCTCVCMAP<4>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGVCTCVCMAP<3>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGVCTCVCMAP<2>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGVCTCVCMAP<1>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGVCTCVCMAP<0>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<63>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<62>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<61>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<60>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<59>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<58>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<57>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<56>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<55>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<54>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<53>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<52>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<51>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<50>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<49>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<48>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<47>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<46>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<45>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<44>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<43>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<42>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<41>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<40>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<39>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<38>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<37>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<36>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<35>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<34>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<33>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<32>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<31>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<30>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<29>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<28>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<27>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<26>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<25>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<24>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<23>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<22>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<21>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<20>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<19>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<18>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<17>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<16>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<15>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<14>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<13>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<12>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<11>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<10>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<9>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<8>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<7>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<6>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<5>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<4>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<3>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<2>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<1>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECA<0>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<63>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<62>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<61>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<60>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<59>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<58>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<57>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<56>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<55>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<54>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<53>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<52>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<51>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<50>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<49>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<48>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<47>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<46>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<45>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<44>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<43>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<42>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<41>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<40>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<39>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<38>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<37>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<36>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<35>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<34>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<33>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<32>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<31>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<30>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<29>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<28>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<27>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<26>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<25>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<24>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<23>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<22>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<21>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<20>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<19>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<18>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<17>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<16>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<15>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<14>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<13>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<12>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<11>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<10>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<9>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<8>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<7>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<6>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<5>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<4>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<3>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<2>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<1>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECB<0>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECC<11>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECC<10>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECC<9>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECC<8>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECC<7>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECC<6>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECC<5>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECC<4>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECC<3>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECC<2>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECC<1>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGVECC<0>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PCIEDRPDO<15>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PCIEDRPDO<14>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PCIEDRPDO<13>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PCIEDRPDO<12>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PCIEDRPDO<11>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PCIEDRPDO<10>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PCIEDRPDO<9>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PCIEDRPDO<8>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PCIEDRPDO<7>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PCIEDRPDO<6>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PCIEDRPDO<5>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PCIEDRPDO<4>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PCIEDRPDO<3>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PCIEDRPDO<2>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PCIEDRPDO<1>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PCIEDRPDO<0>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/MIMRXRADDR<12>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/MIMRXRADDR<11>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/MIMRXWADDR<12>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/MIMRXWADDR<11>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/MIMTXRADDR<12>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/MIMTXRADDR<11>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/MIMTXWADDR<12>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/MIMTXWADDR<11>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX4CHARISK<1>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX4CHARISK<0>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX4DATA<15>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX4DATA<14>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX4DATA<13>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX4DATA<12>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX4DATA<11>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX4DATA<10>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX4DATA<9>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX4DATA<8>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX4DATA<7>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX4DATA<6>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX4DATA<5>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX4DATA<4>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX4DATA<3>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX4DATA<2>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX4DATA<1>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX4DATA<0>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX4POWERDOWN<1>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX4POWERDOWN<0>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX5CHARISK<1>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX5CHARISK<0>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX5DATA<15>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX5DATA<14>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX5DATA<13>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX5DATA<12>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX5DATA<11>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX5DATA<10>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX5DATA<9>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX5DATA<8>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX5DATA<7>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX5DATA<6>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX5DATA<5>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX5DATA<4>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX5DATA<3>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX5DATA<2>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX5DATA<1>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX5DATA<0>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX5POWERDOWN<1>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX5POWERDOWN<0>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX6CHARISK<1>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX6CHARISK<0>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX6DATA<15>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX6DATA<14>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX6DATA<13>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX6DATA<12>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX6DATA<11>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX6DATA<10>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX6DATA<9>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX6DATA<8>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX6DATA<7>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX6DATA<6>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX6DATA<5>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX6DATA<4>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX6DATA<3>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX6DATA<2>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX6DATA<1>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX6DATA<0>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX6POWERDOWN<1>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX6POWERDOWN<0>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX7CHARISK<1>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX7CHARISK<0>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX7DATA<15>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX7DATA<14>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX7DATA<13>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX7DATA<12>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX7DATA<11>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX7DATA<10>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX7DATA<9>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX7DATA<8>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX7DATA<7>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX7DATA<6>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX7DATA<5>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX7DATA<4>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX7DATA<3>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX7DATA<2>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX7DATA<1>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX7DATA<0>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX7POWERDOWN<1>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX7POWERDOWN<0>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETXMARGIN<1>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETXMARGIN<0>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PLDBGVEC<11>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PLDBGVEC<10>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PLDBGVEC<9>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PLDBGVEC<8>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PLDBGVEC<7>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PLDBGVEC<6>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PLDBGVEC<5>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PLDBGVEC<4>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PLDBGVEC<3>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PLDBGVEC<2>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PLDBGVEC<1>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PLDBGVEC<0>" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PLRXPMSTATE<1>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PLRXPMSTATE<0>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PLTXPMSTATE<2>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PLTXPMSTATE<1>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PLTXPMSTATE<0>" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGAERECRCCHECKEN" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGAERECRCGENEN" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGERRAERHEADERLOGSETN" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGMSGRECEIVEDASSERTINTA" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGMSGRECEIVEDASSERTINTB" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGMSGRECEIVEDASSERTINTC" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGMSGRECEIVEDASSERTINTD" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGMSGRECEIVEDDEASSERTINTA" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGMSGRECEIVEDDEASSERTINTB" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGMSGRECEIVEDDEASSERTINTC" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGMSGRECEIVEDDEASSERTINTD" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGMSGRECEIVEDERRCOR" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGMSGRECEIVEDERRFATAL" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGMSGRECEIVEDERRNONFATAL" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGMSGRECEIVEDPMASNAK" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGMSGRECEIVEDPMETO" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGMSGRECEIVEDPMETOACK" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGMSGRECEIVEDPMPME" is +sourceless and has been removed. +The signal +"ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGMSGRECEIVEDSETSLOTPOWERLIMIT" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGMSGRECEIVEDUNLOCK" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGPMRCVASREQL1N" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGPMRCVENTERL1N" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGPMRCVENTERL23N" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGPMRCVREQACKN" is sourceless +and has been removed. +The signal +"ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGSLOTCONTROLELECTROMECHILCTLPULSE" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGTRANSACTION" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/CFGTRANSACTIONTYPE" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGSCLRA" is sourceless and has +been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGSCLRB" is sourceless and has +been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGSCLRC" is sourceless and has +been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGSCLRD" is sourceless and has +been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGSCLRE" is sourceless and has +been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGSCLRF" is sourceless and has +been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGSCLRG" is sourceless and has +been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGSCLRH" is sourceless and has +been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGSCLRI" is sourceless and has +been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGSCLRJ" is sourceless and has +been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/DBGSCLRK" is sourceless and has +been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PCIEDRPDRDY" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/LNKCLKEN" is sourceless and has +been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX4POLARITY" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX5POLARITY" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX6POLARITY" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPERX7POLARITY" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX4COMPLIANCE" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX4ELECIDLE" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX5COMPLIANCE" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX5ELECIDLE" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX6COMPLIANCE" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX6ELECIDLE" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX7COMPLIANCE" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETX7ELECIDLE" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PIPETXRESET" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/PLPHYLNKUPN" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/RECEIVEDFUNCLVLRSTN" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/TRNRECRCERRN" is sourceless and +has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/TRNTDLLPDSTRDYN" is sourceless +and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<15>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<14>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<13>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<12>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<11>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<10>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<9>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<8>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<7>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<6>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<5>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<4>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<3>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<2>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<1>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<0>" is +sourceless and has been removed. +The signal +"ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/TXRATEDONE<0>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<31>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<30>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<29>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<28>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<27>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<26>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<25>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<24>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<23>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<22>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<21>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<20>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<19>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<18>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<17>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<16>" is +sourceless and has been removed. +The signal +"ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/TXRATEDONE<1>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<47>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<46>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<45>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<44>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<43>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<42>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<41>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<40>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<39>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<38>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<37>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<36>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<35>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<34>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<33>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<32>" is +sourceless and has been removed. +The signal +"ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/TXRATEDONE<2>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<63>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<62>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<61>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<60>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<59>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<58>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<57>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<56>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<55>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<54>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<53>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<52>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<51>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<50>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<49>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/dout<48>" is +sourceless and has been removed. +The signal +"ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/TXRATEDONE<3>" is +sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/mim_tx_rdata<71>" +is sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/mim_tx_rdata<70>" +is sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/mim_tx_rdata<69>" +is sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/mim_rx_rdata<71>" +is sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/mim_rx_rdata<70>" +is sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/mim_rx_rdata<69>" +is sourceless and has been removed. +The signal "ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/mim_rx_rdata<68>" +is sourceless and has been removed. +The signal "ftop/ctop/inf/noc_sm2/pktFork/fo1/dempty" is sourceless and has been +removed. + Sourceless block "ftop/ctop/inf/noc_sm2/pktFork/fo1/_n008211" (ROM) removed. + The signal "ftop/ctop/inf/noc_sm2/pktFork/fo1/_n0082" is sourceless and has been +removed. + Sourceless block "ftop/ctop/inf/noc_sm2/pktFork/fo1/dempty" (SFF) removed. + Sourceless block "ftop/ctop/inf/noc_sm2/pktFork/fo1/dempty_glue_set" (ROM) +removed. + The signal "ftop/ctop/inf/noc_sm2/pktFork/fo1/dempty_glue_set" is sourceless and +has been removed. +The signal "ftop/ctop/inf/dp1/bram_0_memory$DOB<31>" is sourceless and has been +removed. +The signal "ftop/ctop/inf/dp1/bram_0_memory$DOB<30>" is sourceless and has been +removed. +The signal "ftop/ctop/inf/dp1/bram_0_memory$DOB<29>" is sourceless and has been +removed. +The signal "ftop/ctop/inf/dp1/bram_0_memory$DOB<28>" is sourceless and has been +removed. +The signal "ftop/ctop/inf/dp1/bram_0_memory$DOB<27>" is sourceless and has been +removed. +The signal "ftop/ctop/inf/dp1/bram_0_memory$DOB<26>" is sourceless and has been +removed. +The signal "ftop/ctop/inf/dp1/bram_0_memory$DOB<25>" is sourceless and has been +removed. +The signal "ftop/ctop/inf/dp1/bram_0_memory$DOB<24>" is sourceless and has been +removed. +The signal "ftop/ctop/inf/dp1/bram_1_memory$DOB<31>" is sourceless and has been +removed. +The signal "ftop/ctop/inf/dp1/bram_1_memory$DOB<30>" is sourceless and has been +removed. +The signal "ftop/ctop/inf/dp1/bram_1_memory$DOB<29>" is sourceless and has been +removed. +The signal "ftop/ctop/inf/dp1/bram_1_memory$DOB<28>" is sourceless and has been +removed. +The signal "ftop/ctop/inf/dp1/bram_1_memory$DOB<27>" is sourceless and has been +removed. +The signal "ftop/ctop/inf/dp1/bram_1_memory$DOB<26>" is sourceless and has been +removed. +The signal "ftop/ctop/inf/dp1/bram_1_memory$DOB<25>" is sourceless and has been +removed. +The signal "ftop/ctop/inf/dp1/bram_1_memory$DOB<24>" is sourceless and has been +removed. +The signal "ftop/ctop/inf/dp1/bram_1_memory$DOB<23>" is sourceless and has been +removed. +The signal "ftop/ctop/inf/dp1/bram_1_memory$DOB<22>" is sourceless and has been +removed. +The signal "ftop/ctop/inf/dp1/bram_1_memory$DOB<21>" is sourceless and has been +removed. +The signal "ftop/ctop/inf/dp1/bram_1_memory$DOB<20>" is sourceless and has been +removed. +The signal "ftop/ctop/inf/dp1/bram_1_memory$DOB<19>" is sourceless and has been +removed. +The signal "ftop/ctop/inf/dp1/bram_1_memory$DOB<18>" is sourceless and has been +removed. +The signal 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sourceless and has been +removed. +The signal "ftop/cap0/dataBram_0_memory/DOA<15>" is sourceless and has been +removed. +The signal "ftop/cap0/dataBram_0_memory/DOA<14>" is sourceless and has been +removed. +The signal "ftop/cap0/dataBram_0_memory/DOA<13>" is sourceless and has been +removed. +The signal "ftop/cap0/dataBram_0_memory/DOA<12>" is sourceless and has been +removed. +The signal "ftop/cap0/dataBram_0_memory/DOA<11>" is sourceless and has been +removed. +The signal "ftop/cap0/dataBram_0_memory/DOA<10>" is sourceless and has been +removed. +The signal "ftop/cap0/dataBram_0_memory/DOA<9>" is sourceless and has been +removed. +The signal "ftop/cap0/dataBram_0_memory/DOA<8>" is sourceless and has been +removed. +The signal "ftop/cap0/dataBram_0_memory/DOA<7>" is sourceless and has been +removed. +The signal "ftop/cap0/dataBram_0_memory/DOA<6>" is sourceless and has been +removed. +The signal "ftop/cap0/dataBram_0_memory/DOA<5>" is sourceless and has been +removed. +The signal "ftop/cap0/dataBram_0_memory/DOA<4>" is sourceless and has been +removed. +The signal "ftop/cap0/dataBram_0_memory/DOA<3>" is sourceless and has been +removed. +The signal "ftop/cap0/dataBram_0_memory/DOA<2>" is sourceless and has been +removed. +The signal "ftop/cap0/dataBram_0_memory/DOA<1>" is sourceless and has been +removed. +The signal "ftop/cap0/dataBram_0_memory/DOA<0>" is sourceless and has been +removed. +The signal "ftop/dram0/memc_memc/dbg_dqs_n_tap_cnt<0>" is sourceless and has +been removed. + Sourceless block "ftop/dram0/memc_memc/scl_inst" (MUX) removed. + The signal "ftop/dram0/memc_memc/scl" is sourceless and has been removed. + Sourceless block "ftop/dram0/memc_memc/sda_inst" (MUX) removed. + The signal "ftop/dram0/memc_memc/sda" is sourceless and has been removed. +The signal "ftop/dram0/memc_memc/N1" is sourceless and has been removed. +The signal "ftop/dram0/memc_memc/dbg_cpt_tap_cnt<39>" is sourceless and has been +removed. +The signal "ftop/dram0/memc_memc/dbg_cpt_tap_cnt<38>" is sourceless and has been +removed. +The signal "ftop/dram0/memc_memc/dbg_cpt_tap_cnt<37>" is sourceless and has been +removed. +The signal "ftop/dram0/memc_memc/dbg_cpt_tap_cnt<36>" is sourceless and has been +removed. +The signal "ftop/dram0/memc_memc/dbg_cpt_tap_cnt<35>" is sourceless and has been +removed. +The signal "ftop/dram0/memc_memc/dbg_cpt_tap_cnt<34>" is sourceless and has been +removed. +The signal "ftop/dram0/memc_memc/dbg_cpt_tap_cnt<33>" is sourceless and has been +removed. +The signal "ftop/dram0/memc_memc/dbg_cpt_tap_cnt<32>" is sourceless and has been +removed. +The signal "ftop/dram0/memc_memc/dbg_cpt_tap_cnt<31>" is sourceless and has been +removed. +The signal "ftop/dram0/memc_memc/dbg_cpt_tap_cnt<30>" is sourceless and has been +removed. +The signal "ftop/dram0/memc_memc/dbg_cpt_tap_cnt<29>" is sourceless and has been +removed. +The signal "ftop/dram0/memc_memc/dbg_cpt_tap_cnt<28>" is sourceless and has been +removed. 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been +removed. +The signal "ftop/dram0/memc_memc/dbg_cpt_tap_cnt<16>" is sourceless and has been +removed. +The signal "ftop/dram0/memc_memc/dbg_cpt_tap_cnt<15>" is sourceless and has been +removed. +The signal "ftop/dram0/memc_memc/dbg_cpt_tap_cnt<14>" is sourceless and has been +removed. +The signal "ftop/dram0/memc_memc/dbg_cpt_tap_cnt<13>" is sourceless and has been +removed. +The signal "ftop/dram0/memc_memc/dbg_cpt_tap_cnt<12>" is sourceless and has been +removed. +The signal "ftop/dram0/memc_memc/dbg_cpt_tap_cnt<11>" is sourceless and has been +removed. +The signal "ftop/dram0/memc_memc/dbg_cpt_tap_cnt<10>" is sourceless and has been +removed. +The signal "ftop/dram0/memc_memc/dbg_cpt_tap_cnt<9>" is sourceless and has been +removed. +The signal "ftop/dram0/memc_memc/dbg_cpt_tap_cnt<8>" is sourceless and has been +removed. +The signal "ftop/dram0/memc_memc/dbg_cpt_tap_cnt<7>" is sourceless and has been +removed. +The signal "ftop/dram0/memc_memc/dbg_cpt_tap_cnt<6>" is sourceless and has been +removed. +The signal "ftop/dram0/memc_memc/dbg_cpt_tap_cnt<5>" is sourceless and has been +removed. +The signal "ftop/dram0/memc_memc/dbg_cpt_tap_cnt<4>" is sourceless and has been +removed. +The signal "ftop/dram0/memc_memc/dbg_cpt_tap_cnt<3>" is sourceless and has been +removed. +The signal "ftop/dram0/memc_memc/dbg_cpt_tap_cnt<2>" is sourceless and has been +removed. +The signal "ftop/dram0/memc_memc/dbg_cpt_tap_cnt<1>" is sourceless and has been +removed. +The signal "ftop/dram0/memc_memc/dbg_cpt_tap_cnt<0>" is sourceless and has been +removed. +The signal "ftop/dram0/memc_memc/dbg_dq_tap_cnt<39>" is sourceless and has been +removed. +The signal "ftop/dram0/memc_memc/dbg_dq_tap_cnt<38>" is sourceless and has been +removed. +The signal "ftop/dram0/memc_memc/dbg_dq_tap_cnt<37>" is sourceless and has been +removed. +The signal "ftop/dram0/memc_memc/dbg_dq_tap_cnt<36>" is sourceless and has been +removed. +The signal "ftop/dram0/memc_memc/dbg_dq_tap_cnt<35>" is sourceless and has been +removed. +The signal "ftop/dram0/memc_memc/dbg_dq_tap_cnt<34>" is sourceless and has been +removed. +The signal "ftop/dram0/memc_memc/dbg_dq_tap_cnt<33>" is sourceless and has been +removed. +The signal "ftop/dram0/memc_memc/dbg_dq_tap_cnt<32>" is sourceless and has been +removed. +The signal "ftop/dram0/memc_memc/dbg_dq_tap_cnt<31>" is sourceless and has been +removed. +The signal "ftop/dram0/memc_memc/dbg_dq_tap_cnt<30>" is sourceless and has been +removed. +The signal "ftop/dram0/memc_memc/dbg_dq_tap_cnt<29>" is sourceless and has been +removed. +The signal "ftop/dram0/memc_memc/dbg_dq_tap_cnt<28>" is sourceless and has been +removed. +The signal "ftop/dram0/memc_memc/dbg_dq_tap_cnt<27>" is sourceless and has been +removed. +The signal "ftop/dram0/memc_memc/dbg_dq_tap_cnt<26>" is sourceless and has been +removed. +The signal "ftop/dram0/memc_memc/dbg_dq_tap_cnt<25>" is sourceless and has been +removed. +The signal "ftop/dram0/memc_memc/dbg_dq_tap_cnt<24>" is sourceless and has been +removed. +The signal "ftop/dram0/memc_memc/dbg_dq_tap_cnt<23>" is sourceless and has been +removed. +The signal "ftop/dram0/memc_memc/dbg_dq_tap_cnt<22>" is sourceless and has been +removed. +The signal "ftop/dram0/memc_memc/dbg_dq_tap_cnt<21>" is sourceless and has been +removed. +The signal "ftop/dram0/memc_memc/dbg_dq_tap_cnt<20>" is sourceless and has been +removed. +The signal "ftop/dram0/memc_memc/dbg_dq_tap_cnt<19>" is sourceless and has been +removed. +The signal "ftop/dram0/memc_memc/dbg_dq_tap_cnt<18>" is sourceless and has been +removed. +The signal "ftop/dram0/memc_memc/dbg_dq_tap_cnt<17>" is sourceless and has been +removed. +The signal "ftop/dram0/memc_memc/dbg_dq_tap_cnt<16>" is sourceless and has been +removed. +The signal "ftop/dram0/memc_memc/dbg_dq_tap_cnt<15>" is sourceless and has been +removed. +The signal "ftop/dram0/memc_memc/dbg_dq_tap_cnt<14>" is sourceless and has been +removed. +The signal "ftop/dram0/memc_memc/dbg_dq_tap_cnt<13>" is sourceless and has been +removed. +The signal "ftop/dram0/memc_memc/dbg_dq_tap_cnt<12>" is sourceless and has been +removed. +The signal "ftop/dram0/memc_memc/dbg_dq_tap_cnt<11>" is sourceless and has been +removed. +The signal "ftop/dram0/memc_memc/dbg_dq_tap_cnt<10>" is sourceless and has been +removed. +The signal "ftop/dram0/memc_memc/dbg_dq_tap_cnt<9>" is sourceless and has been +removed. +The signal "ftop/dram0/memc_memc/dbg_dq_tap_cnt<8>" is sourceless and has been +removed. +The signal "ftop/dram0/memc_memc/dbg_dq_tap_cnt<7>" is sourceless and has been +removed. +The signal "ftop/dram0/memc_memc/dbg_dq_tap_cnt<6>" is sourceless and has been +removed. +The signal "ftop/dram0/memc_memc/dbg_dq_tap_cnt<5>" is sourceless and has been +removed. +The signal "ftop/dram0/memc_memc/dbg_dq_tap_cnt<4>" is sourceless and has been +removed. +The signal "ftop/dram0/memc_memc/dbg_dq_tap_cnt<3>" is sourceless and has been +removed. +The signal "ftop/dram0/memc_memc/dbg_dq_tap_cnt<2>" is sourceless and has been +removed. +The signal "ftop/dram0/memc_memc/dbg_dq_tap_cnt<1>" is sourceless and has been +removed. +The signal "ftop/dram0/memc_memc/dbg_dq_tap_cnt<0>" is sourceless and has been +removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<39>" is +sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<38>" is +sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<37>" is +sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<36>" is +sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<35>" is +sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<34>" is +sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<33>" is +sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<32>" is +sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<31>" is +sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<30>" is +sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<29>" is +sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<28>" is +sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<27>" is +sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<26>" is +sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<25>" is +sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<24>" is +sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<23>" is +sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<22>" is +sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<21>" is +sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<20>" is +sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<19>" is +sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<18>" is +sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<17>" is +sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<16>" is +sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<15>" is +sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<14>" is +sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<13>" is +sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<12>" is +sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<11>" is +sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<10>" is +sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<9>" is sourceless +and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<8>" is sourceless +and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<7>" is sourceless +and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<6>" is sourceless +and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<5>" is sourceless +and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<4>" is sourceless +and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<3>" is sourceless +and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<2>" is sourceless +and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<1>" is sourceless +and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/dbg_dqs_tap_cnt<0>" is sourceless +and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/ddr_parity" is sourceless and has +been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_rsync_tap_cnt<9>" +is sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_rsync_tap_cnt<8>" +is sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_rsync_tap_cnt<7>" +is sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_rsync_tap_cnt<6>" +is sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_rsync_tap_cnt<5>" +is sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_rsync_tap_cnt<4>" +is sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_rsync_tap_cnt<3>" +is sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_rsync_tap_cnt<2>" +is sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_rsync_tap_cnt<1>" +is sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/dbg_rsync_tap_cnt<0>" +is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rd_dqs_rise0<7>" is +sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rd_dqs_rise0<6>" is +sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rd_dqs_rise0<5>" is +sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rd_dqs_rise0<4>" is +sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rd_dqs_rise0<3>" is +sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rd_dqs_rise0<2>" is +sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rd_dqs_rise0<1>" is +sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rd_dqs_fall0<7>" is +sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rd_dqs_fall0<6>" is +sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rd_dqs_fall0<5>" is +sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rd_dqs_fall0<4>" is +sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rd_dqs_fall0<3>" is +sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rd_dqs_fall0<2>" is +sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rd_dqs_fall0<1>" is +sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rd_dqs_fall0<0>" is +sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rd_dqs_rise1<7>" is +sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rd_dqs_rise1<6>" is +sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rd_dqs_rise1<5>" is +sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rd_dqs_rise1<4>" is +sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rd_dqs_rise1<3>" is +sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rd_dqs_rise1<2>" is +sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rd_dqs_rise1<1>" is +sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rd_dqs_fall1<7>" is +sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rd_dqs_fall1<6>" is +sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rd_dqs_fall1<5>" is +sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rd_dqs_fall1<4>" is +sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rd_dqs_fall1<3>" is +sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rd_dqs_fall1<2>" is +sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rd_dqs_fall1<1>" is +sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/rd_dqs_fall1<0>" is +sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_write/inv_dqs<0>1 +" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q_neg_r_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q_neg_r<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q_r_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q_r<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/Mmux_iserdes_q_mux11" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q_mux<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/Mmux_slip_out11" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/mux41" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<0 +>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/qout_0" (FF) removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q<1>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q_neg_r_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q_neg_r<1>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q_r_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q_r<1>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/Mmux_iserdes_q_mux21" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q_mux<1>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/Mmux_slip_out21" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out<1>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r<1>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2<1>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3<1>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/mux113" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<1 +>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/qout_1" (FF) removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q<2>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q_neg_r_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q_neg_r<2>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q_r_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q_r<2>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/Mmux_iserdes_q_mux31" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q_mux<2>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/din2_r" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/din2_r" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/Mmux_slip_out41" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out<3>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r<3>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2<3>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3<3>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/mux1121" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<3 +>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/qout_3" (FF) removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/Mmux_slip_out31" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/mux1111" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<2 +>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_rd_bitslip_early/qout_2" (FF) removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q<3>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q_neg_r_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q_neg_r<3>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q_r_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q_r<3>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/Mmux_iserdes_q_mux41" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q_mux<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q<4>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q_neg_r_4" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q_neg_r<4>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q_r_4" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q_r<4>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/Mmux_iserdes_q_mux51" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q_mux<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q<5>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q_neg_r_5" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q_neg_r<5>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q_r_5" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q_r<5>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/Mmux_iserdes_q_mux61" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_q_mux<5>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_clkb" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q_neg_r_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q_neg_r<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q_r_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q_r<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/Mmux_iserdes_q_mux11" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q_mux<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/Mmux_slip_out11" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/mux41" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<0 +>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/qout_0" (FF) removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q<1>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q_neg_r_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q_neg_r<1>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q_r_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q_r<1>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/Mmux_iserdes_q_mux21" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q_mux<1>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/Mmux_slip_out21" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out<1>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r<1>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2<1>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3<1>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/mux113" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<1 +>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/qout_1" (FF) removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q<2>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q_neg_r_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q_neg_r<2>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q_r_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q_r<2>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/Mmux_iserdes_q_mux31" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q_mux<2>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/din2_r" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/din2_r" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/Mmux_slip_out41" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out<3>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r<3>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2<3>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3<3>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/mux1121" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<3 +>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/qout_3" (FF) removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/Mmux_slip_out31" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/mux1111" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<2 +>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_rd_bitslip_early/qout_2" (FF) removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q<3>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q_neg_r_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q_neg_r<3>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q_r_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q_r<3>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/Mmux_iserdes_q_mux41" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q_mux<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q<4>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q_neg_r_4" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q_neg_r<4>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q_r_4" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q_r<4>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/Mmux_iserdes_q_mux51" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q_mux<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q<5>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q_neg_r_5" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q_neg_r<5>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q_r_5" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q_r<5>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/Mmux_iserdes_q_mux61" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_q_mux<5>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_clkb" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q_neg_r_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q_neg_r<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q_r_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q_r<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/Mmux_iserdes_q_mux11" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q_mux<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/Mmux_slip_out11" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/mux41" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<0 +>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/qout_0" (FF) removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q<1>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q_neg_r_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q_neg_r<1>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q_r_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q_r<1>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/Mmux_iserdes_q_mux21" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q_mux<1>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/Mmux_slip_out21" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out<1>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r<1>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2<1>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3<1>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/mux113" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<1 +>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/qout_1" (FF) removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q<2>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q_neg_r_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q_neg_r<2>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q_r_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q_r<2>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/Mmux_iserdes_q_mux31" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q_mux<2>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/din2_r" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/din2_r" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/Mmux_slip_out41" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out<3>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r<3>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2<3>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3<3>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/mux1121" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<3 +>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/qout_3" (FF) removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/Mmux_slip_out31" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/mux1111" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<2 +>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_rd_bitslip_early/qout_2" (FF) removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q<3>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q_neg_r_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q_neg_r<3>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q_r_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q_r<3>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/Mmux_iserdes_q_mux41" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q_mux<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q<4>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q_neg_r_4" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q_neg_r<4>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q_r_4" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q_r<4>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/Mmux_iserdes_q_mux51" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q_mux<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q<5>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q_neg_r_5" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q_neg_r<5>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q_r_5" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q_r<5>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/Mmux_iserdes_q_mux61" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_q_mux<5>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_clkb" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q_neg_r_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q_neg_r<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q_r_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q_r<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/Mmux_iserdes_q_mux11" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q_mux<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/Mmux_slip_out11" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/mux41" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<0 +>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/qout_0" (FF) removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q<1>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q_neg_r_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q_neg_r<1>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q_r_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q_r<1>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/Mmux_iserdes_q_mux21" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q_mux<1>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/Mmux_slip_out21" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out<1>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r<1>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2<1>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3<1>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/mux113" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<1 +>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/qout_1" (FF) removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q<2>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q_neg_r_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q_neg_r<2>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q_r_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q_r<2>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/Mmux_iserdes_q_mux31" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q_mux<2>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/din2_r" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/din2_r" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/Mmux_slip_out41" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out<3>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r<3>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2<3>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3<3>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/mux1121" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<3 +>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/qout_3" (FF) removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/Mmux_slip_out31" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/mux1111" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<2 +>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_rd_bitslip_early/qout_2" (FF) removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q<3>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q_neg_r_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q_neg_r<3>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q_r_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q_r<3>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/Mmux_iserdes_q_mux41" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q_mux<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q<4>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q_neg_r_4" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q_neg_r<4>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q_r_4" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q_r<4>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/Mmux_iserdes_q_mux51" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q_mux<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q<5>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q_neg_r_5" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q_neg_r<5>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q_r_5" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q_r<5>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/Mmux_iserdes_q_mux61" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_q_mux<5>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_clkb" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q_neg_r_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q_neg_r<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q_r_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q_r<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/Mmux_iserdes_q_mux11" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q_mux<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/Mmux_slip_out11" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/mux41" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<0 +>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/qout_0" (FF) removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q<1>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q_neg_r_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q_neg_r<1>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q_r_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q_r<1>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/Mmux_iserdes_q_mux21" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q_mux<1>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/Mmux_slip_out21" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out<1>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r<1>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2<1>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3<1>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/mux113" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<1 +>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/qout_1" (FF) removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q<2>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q_neg_r_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q_neg_r<2>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q_r_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q_r<2>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/Mmux_iserdes_q_mux31" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q_mux<2>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/din2_r" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/din2_r" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/Mmux_slip_out41" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out<3>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r<3>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2<3>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3<3>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/mux1121" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<3 +>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/qout_3" (FF) removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/Mmux_slip_out31" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/mux1111" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<2 +>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_rd_bitslip_early/qout_2" (FF) removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q<3>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q_neg_r_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q_neg_r<3>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q_r_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q_r<3>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/Mmux_iserdes_q_mux41" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q_mux<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q<4>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q_neg_r_4" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q_neg_r<4>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q_r_4" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q_r<4>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/Mmux_iserdes_q_mux51" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q_mux<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q<5>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q_neg_r_5" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q_neg_r<5>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q_r_5" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q_r<5>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/Mmux_iserdes_q_mux61" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_q_mux<5>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_clkb" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q_neg_r_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q_neg_r<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q_r_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q_r<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/Mmux_iserdes_q_mux11" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q_mux<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/Mmux_slip_out11" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/mux41" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<0 +>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/qout_0" (FF) removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q<1>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q_neg_r_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q_neg_r<1>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q_r_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q_r<1>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/Mmux_iserdes_q_mux21" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q_mux<1>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/Mmux_slip_out21" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out<1>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r<1>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2<1>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3<1>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/mux113" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<1 +>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/qout_1" (FF) removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q<2>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q_neg_r_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q_neg_r<2>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q_r_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q_r<2>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/Mmux_iserdes_q_mux31" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q_mux<2>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/din2_r" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/din2_r" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/Mmux_slip_out41" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out<3>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r<3>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2<3>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3<3>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/mux1121" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<3 +>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/qout_3" (FF) removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/Mmux_slip_out31" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/mux1111" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<2 +>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_rd_bitslip_early/qout_2" (FF) removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q<3>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q_neg_r_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q_neg_r<3>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q_r_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q_r<3>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/Mmux_iserdes_q_mux41" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q_mux<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q<4>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q_neg_r_4" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q_neg_r<4>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q_r_4" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q_r<4>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/Mmux_iserdes_q_mux51" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q_mux<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q<5>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q_neg_r_5" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q_neg_r<5>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q_r_5" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q_r<5>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/Mmux_iserdes_q_mux61" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_q_mux<5>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_clkb" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q_neg_r_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q_neg_r<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q_r_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q_r<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/Mmux_iserdes_q_mux11" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q_mux<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/Mmux_slip_out11" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/mux41" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<0 +>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/qout_0" (FF) removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q<1>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q_neg_r_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q_neg_r<1>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q_r_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q_r<1>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/Mmux_iserdes_q_mux21" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q_mux<1>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/Mmux_slip_out21" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out<1>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r<1>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2<1>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3_1" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3<1>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/mux113" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<1 +>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/qout_1" (FF) removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q<2>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q_neg_r_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q_neg_r<2>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q_r_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q_r<2>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/Mmux_iserdes_q_mux31" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q_mux<2>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/din2_r" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/din2_r" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/Mmux_slip_out41" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out<3>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r<3>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2<3>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3<3>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/mux1121" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<3 +>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/qout_3" (FF) removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/Mmux_slip_out31" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/mux1111" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<2 +>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_rd_bitslip_early/qout_2" (FF) removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q<3>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q_neg_r_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q_neg_r<3>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q_r_3" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q_r<3>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/Mmux_iserdes_q_mux41" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q_mux<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q<4>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q_neg_r_4" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q_neg_r<4>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q_r_4" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q_r<4>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/Mmux_iserdes_q_mux51" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q_mux<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q<5>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q_neg_r_5" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q_neg_r<5>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q_r_5" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q_r<5>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/Mmux_iserdes_q_mux61" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_q_mux<5>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_clkb" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[0 +].u_phy_dqs_iob/iserdes_q<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[0 +].u_phy_dqs_iob/iserdes_q_neg_r_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[0 +].u_phy_dqs_iob/iserdes_q_neg_r<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[0 +].u_phy_dqs_iob/iserdes_q_r_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[0 +].u_phy_dqs_iob/iserdes_q_r<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[0 +].u_phy_dqs_iob/Mmux_iserdes_q_mux11" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[0 +].u_phy_dqs_iob/iserdes_q_mux<0>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[0 +].u_phy_dqs_iob/u_rd_bitslip_early/Mmux_slip_out11" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[0 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[0 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[0 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[0 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[0 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[0 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3_0" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[0 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3<0>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[0 +].u_phy_dqs_iob/u_rd_bitslip_early/mux41" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[0 +].u_phy_dqs_iob/u_rd_bitslip_early/clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<0 +>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[0 +].u_phy_dqs_iob/u_rd_bitslip_early/qout_0" (FF) removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[0 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[0 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[0 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r2<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[0 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3_2" (FF) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[0 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r3<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[0 +].u_phy_dqs_iob/u_rd_bitslip_early/mux1111" (ROM) removed. + The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[0 +].u_phy_dqs_iob/u_rd_bitslip_early/clkdly_cnt[1]_slip_out_r3[3]_wide_mux_7_OUT<2 +>" is sourceless and has been removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[0 +].u_phy_dqs_iob/u_rd_bitslip_early/qout_2" (FF) removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[0 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out<2>" is sourceless and has been +removed. + Sourceless block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[0 +].u_phy_dqs_iob/u_rd_bitslip_early/slip_out_r_2" (FF) removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[63 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[63 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[63 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[63 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[63 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[62 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[62 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[62 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[62 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[62 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[61 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[61 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[61 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[61 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[61 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[60 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[60 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[60 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[60 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[60 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[59 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[59 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[59 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[59 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[59 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[58 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[58 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[58 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[58 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[58 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[57 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[57 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[57 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[57 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[57 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[55 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[55 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[55 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[55 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[55 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[54 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[54 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[54 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[54 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[54 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[53 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[53 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[53 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[53 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[53 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[52 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[52 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[52 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[52 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[52 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[51 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[51 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[51 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[51 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[51 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[50 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[50 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[50 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[50 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[50 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[49 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[49 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[49 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[49 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[49 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[47 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[47 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[47 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[47 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[47 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[46 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[46 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[46 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[46 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[46 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[45 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[45 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[45 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[45 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[45 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[44 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[44 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[44 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[44 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[44 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[43 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[43 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[43 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[43 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[43 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[42 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[42 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[42 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[42 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[42 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[41 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[41 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[41 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[41 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[41 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[39 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[39 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[39 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[39 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[39 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[38 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[38 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[38 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[38 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[38 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[37 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[37 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[37 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[37 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[37 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[36 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[36 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[36 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[36 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[36 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[35 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[35 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[35 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[35 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[35 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[34 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[34 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[34 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[34 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[34 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[33 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[33 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[33 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[33 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[33 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[31 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[31 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[31 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[31 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[31 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[30 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[30 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[30 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[30 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[30 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[29 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[29 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[29 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[29 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[29 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[28 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[28 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[28 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[28 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[28 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[27 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[27 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[27 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[27 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[27 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[26 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[26 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[26 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[26 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[26 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[25 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[25 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[25 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[25 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[25 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[23 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[23 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[23 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[23 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[23 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[22 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[22 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[22 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[22 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[22 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[21 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[21 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[21 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[21 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[21 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[20 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[20 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[20 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[20 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[20 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[19 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[19 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[19 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[19 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[19 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[18 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[18 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[18 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[18 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[18 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[17 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[17 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[17 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[17 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[17 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[15 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[15 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[15 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[15 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[15 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[14 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[14 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[14 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[14 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[14 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[13 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[13 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[13 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[13 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[13 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[12 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[12 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[12 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[12 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[12 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[11 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[11 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[11 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[11 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[11 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[10 +].u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[10 +].u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[10 +].u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[10 +].u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[10 +].u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[9] +.u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[9] +.u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[9] +.u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[9] +.u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[9] +.u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[7] +.u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[7] +.u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[7] +.u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[7] +.u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[7] +.u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[6] +.u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[6] +.u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[6] +.u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[6] +.u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[6] +.u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[5] +.u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[5] +.u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[5] +.u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[5] +.u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[5] +.u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[4] +.u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[4] +.u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[4] +.u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[4] +.u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[4] +.u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[3] +.u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[3] +.u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[3] +.u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[3] +.u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[3] +.u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[2] +.u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[2] +.u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[2] +.u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[2] +.u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[2] +.u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[1] +.u_iob_dq/dq_tap_cnt<4>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[1] +.u_iob_dq/dq_tap_cnt<3>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[1] +.u_iob_dq/dq_tap_cnt<2>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[1] +.u_iob_dq/dq_tap_cnt<1>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[1] +.u_iob_dq/dq_tap_cnt<0>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c0.u_rddata_sync_c0/rdata<97>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c0.u_rddata_sync_c0/rdata<99>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c0.u_rddata_sync_c0/rdata<100>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c0.u_rddata_sync_c0/rdata<101>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c0.u_rddata_sync_c0/rdata<102>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c0.u_rddata_sync_c0/rdata<103>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c0.u_rddata_sync_c0/rdata<104>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c0.u_rddata_sync_c0/rdata<105>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c0.u_rddata_sync_c0/rdata<106>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c0.u_rddata_sync_c0/rdata<107>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/rdata<160>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/rdata<161>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/rdata<162>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/rdata<163>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/rdata<164>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/rdata<165>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/rdata<166>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/rdata<167>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/rdata<168>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/rdata<169>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/rdata<170>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/rdata<171>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/rdata<172>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/rdata<173>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/rdata<174>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/rdata<175>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/rdata<176>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/rdata<177>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/rdata<178>" is sourceless and has been removed. +The signal +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/rdata<179>" is sourceless and has been removed. +The signal "ftop/dram0/memc_memc/u_infrastructure/PSDONE" is sourceless and has +been removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c0.u_rddata_sync_c0/gen_ram[100].u_RAM64X1D" (RAM64X1D) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c0.u_rddata_sync_c0/gen_ram[101].u_RAM64X1D" (RAM64X1D) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c0.u_rddata_sync_c0/gen_ram[102].u_RAM64X1D" (RAM64X1D) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c0.u_rddata_sync_c0/gen_ram[103].u_RAM64X1D" (RAM64X1D) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c0.u_rddata_sync_c0/gen_ram[104].u_RAM64X1D" (RAM64X1D) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c0.u_rddata_sync_c0/gen_ram[105].u_RAM64X1D" (RAM64X1D) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c0.u_rddata_sync_c0/gen_ram[106].u_RAM64X1D" (RAM64X1D) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c0.u_rddata_sync_c0/gen_ram[107].u_RAM64X1D" (RAM64X1D) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c0.u_rddata_sync_c0/gen_ram[97].u_RAM64X1D" (RAM64X1D) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c0.u_rddata_sync_c0/gen_ram[99].u_RAM64X1D" (RAM64X1D) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/gen_ram[160].u_RAM64X1D" (RAM64X1D) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/gen_ram[161].u_RAM64X1D" (RAM64X1D) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/gen_ram[162].u_RAM64X1D" (RAM64X1D) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/gen_ram[163].u_RAM64X1D" (RAM64X1D) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/gen_ram[164].u_RAM64X1D" (RAM64X1D) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/gen_ram[165].u_RAM64X1D" (RAM64X1D) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/gen_ram[166].u_RAM64X1D" (RAM64X1D) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/gen_ram[167].u_RAM64X1D" (RAM64X1D) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/gen_ram[168].u_RAM64X1D" (RAM64X1D) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/gen_ram[169].u_RAM64X1D" (RAM64X1D) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/gen_ram[170].u_RAM64X1D" (RAM64X1D) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/gen_ram[171].u_RAM64X1D" (RAM64X1D) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/gen_ram[172].u_RAM64X1D" (RAM64X1D) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/gen_ram[173].u_RAM64X1D" (RAM64X1D) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/gen_ram[174].u_RAM64X1D" (RAM64X1D) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/gen_ram[175].u_RAM64X1D" (RAM64X1D) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/gen_ram[176].u_RAM64X1D" (RAM64X1D) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/gen_ram[177].u_RAM64X1D" (RAM64X1D) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/gen_ram[178].u_RAM64X1D" (RAM64X1D) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddata +_sync/gen_c1.u_rddata_sync_c1/gen_ram[179].u_RAM64X1D" (RAM64X1D) removed. +Unused block "ftop/dram0/memc_memc/XST_GND" (ZERO) removed. +Unused block "ftop/dram0/memc_memc/XST_VCC" (ONE) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_control_io/u_out_ +parity" (OSERDESE1) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[0 +].u_phy_dqs_iob/u_rd_bitslip_early/Mmux_slip_out31" (ROM) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/iserdes_clkb1_INV_0" (BUF) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1 +].u_phy_dqs_iob/u_iserdes_dqs_p" (ISERDESE1) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/iserdes_clkb1_INV_0" (BUF) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[2 +].u_phy_dqs_iob/u_iserdes_dqs_p" (ISERDESE1) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/iserdes_clkb1_INV_0" (BUF) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[3 +].u_phy_dqs_iob/u_iserdes_dqs_p" (ISERDESE1) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/iserdes_clkb1_INV_0" (BUF) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[4 +].u_phy_dqs_iob/u_iserdes_dqs_p" (ISERDESE1) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/iserdes_clkb1_INV_0" (BUF) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[5 +].u_phy_dqs_iob/u_iserdes_dqs_p" (ISERDESE1) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/iserdes_clkb1_INV_0" (BUF) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[6 +].u_phy_dqs_iob/u_iserdes_dqs_p" (ISERDESE1) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/iserdes_clkb1_INV_0" (BUF) removed. +Unused block +"ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[7 +].u_phy_dqs_iob/u_iserdes_dqs_p" (ISERDESE1) removed. + +Optimized Block(s): +TYPE BLOCK +VCC XST_VCC +GND ftop/XST_GND +VCC ftop/XST_VCC +GND ftop/cap0/XST_GND +VCC ftop/cap0/XST_VCC +GND ftop/cap0/dataBram_0_memory/XST_GND +VCC ftop/cap0/dataBram_0_memory/XST_VCC +GND ftop/cap0/dataBram_0_serverAdapterB_outDataCore/XST_GND +GND ftop/cap0/metaBram_0_memory/XST_GND +VCC ftop/cap0/metaBram_0_memory/XST_VCC +GND ftop/cap0/metaBram_0_serverAdapterB_outDataCore/XST_GND +GND ftop/cap0/metaBram_1_memory/XST_GND +VCC ftop/cap0/metaBram_1_memory/XST_VCC +GND ftop/cap0/metaBram_1_serverAdapterB_outDataCore/XST_GND +GND ftop/cap0/metaBram_2_memory/XST_GND +VCC ftop/cap0/metaBram_2_memory/XST_VCC +GND ftop/cap0/metaBram_2_serverAdapterB_outDataCore/XST_GND +GND ftop/cap0/metaBram_3_memory/XST_GND +VCC ftop/cap0/metaBram_3_memory/XST_VCC +GND ftop/cap0/metaBram_3_serverAdapterB_outDataCore/XST_GND +GND ftop/cap0/wci_wslv_reqF/XST_GND +GND ftop/cap0/wsiS_reqFifo/XST_GND +VCC ftop/cap0/wsiS_reqFifo/XST_VCC +GND ftop/ctop/app/XST_GND +GND ftop/ctop/app/appW1/XST_GND +VCC ftop/ctop/app/appW1/XST_VCC +GND ftop/ctop/app/appW1/rgen_gsF/XST_GND +GND ftop/ctop/app/appW1/wci_wslv_reqF/XST_GND +GND ftop/ctop/app/appW2/XST_GND +VCC ftop/ctop/app/appW2/XST_VCC +GND ftop/ctop/app/appW2/respF_memory/XST_GND +VCC ftop/ctop/app/appW2/respF_memory/XST_VCC +GND ftop/ctop/app/appW2/wci_wslv_reqF/XST_GND +GND ftop/ctop/app/appW3/XST_GND +VCC ftop/ctop/app/appW3/XST_VCC +GND ftop/ctop/app/appW3/wci_wslv_reqF/XST_GND +GND ftop/ctop/app/appW3/wsiS_reqFifo/XST_GND +GND ftop/ctop/app/appW4/XST_GND +VCC ftop/ctop/app/appW4/XST_VCC +GND ftop/ctop/app/appW4/respF_memory/XST_GND +VCC ftop/ctop/app/appW4/respF_memory/XST_VCC +GND ftop/ctop/app/appW4/wci_wslv_reqF/XST_GND +GND ftop/ctop/app/appW4/wsiS_reqFifo/XST_GND +GND ftop/ctop/app/id/XST_GND +VCC ftop/ctop/app/id/XST_VCC +LUT2 ftop/ctop/inf/Msub_byteCount__h523510 + optimized to 1 +LUT2 ftop/ctop/inf/Msub_byteCount__h52352 + optimized to 1 +LUT2 ftop/ctop/inf/Msub_byteCount__h52353 + optimized to 1 +LUT2 ftop/ctop/inf/Msub_byteCount__h52354 + optimized to 1 +LUT2 ftop/ctop/inf/Msub_byteCount__h52355 + optimized to 1 +LUT2 ftop/ctop/inf/Msub_byteCount__h52356 + optimized to 1 +LUT2 ftop/ctop/inf/Msub_byteCount__h52357 + optimized to 1 +LUT2 ftop/ctop/inf/Msub_byteCount__h52358 + optimized to 1 +LUT2 ftop/ctop/inf/Msub_byteCount__h52359 + optimized to 1 +GND ftop/ctop/inf/XST_GND +VCC ftop/ctop/inf/XST_VCC +GND ftop/ctop/inf/cp/XST_GND +VCC ftop/ctop/inf/cp/XST_VCC +GND ftop/ctop/inf/cp/rom_memory/XST_GND +VCC ftop/ctop/inf/cp/rom_memory/XST_VCC +GND ftop/ctop/inf/cp/rom_serverAdapter_outDataCore/XST_GND +GND ftop/ctop/inf/cp/timeServ_setRefF/XST_GND +VCC ftop/ctop/inf/cp/wci_10_mReset/rstSync/XST_VCC +VCC ftop/ctop/inf/cp/wci_11_mReset/rstSync/XST_VCC +VCC ftop/ctop/inf/cp/wci_12_mReset/rstSync/XST_VCC +VCC ftop/ctop/inf/cp/wci_13_mReset/rstSync/XST_VCC +VCC ftop/ctop/inf/cp/wci_14_mReset/rstSync/XST_VCC +VCC ftop/ctop/inf/cp/wci_1_mReset/rstSync/XST_VCC +VCC ftop/ctop/inf/cp/wci_2_mReset/rstSync/XST_VCC +VCC ftop/ctop/inf/cp/wci_3_mReset/rstSync/XST_VCC +VCC ftop/ctop/inf/cp/wci_4_mReset/rstSync/XST_VCC +VCC ftop/ctop/inf/cp/wci_8_mReset/rstSync/XST_VCC +VCC ftop/ctop/inf/cp/wci_9_mReset/rstSync/XST_VCC +LUT2 ftop/ctop/inf/dp0/Msub_byteCount__h29653[11:0]10 + optimized to 1 +LUT2 ftop/ctop/inf/dp0/Msub_byteCount__h29653[11:0]2 + optimized to 1 +LUT2 ftop/ctop/inf/dp0/Msub_byteCount__h29653[11:0]3 + optimized to 1 +LUT2 ftop/ctop/inf/dp0/Msub_byteCount__h29653[11:0]4 + optimized to 1 +LUT2 ftop/ctop/inf/dp0/Msub_byteCount__h29653[11:0]5 + optimized to 1 +LUT2 ftop/ctop/inf/dp0/Msub_byteCount__h29653[11:0]6 + optimized to 1 +LUT2 ftop/ctop/inf/dp0/Msub_byteCount__h29653[11:0]7 + optimized to 1 +LUT2 ftop/ctop/inf/dp0/Msub_byteCount__h29653[11:0]8 + optimized to 1 +LUT2 ftop/ctop/inf/dp0/Msub_byteCount__h29653[11:0]9 + optimized to 1 +GND ftop/ctop/inf/dp0/XST_GND +VCC ftop/ctop/inf/dp0/XST_VCC +GND ftop/ctop/inf/dp0/bram_0_memory/XST_GND +VCC ftop/ctop/inf/dp0/bram_0_memory/XST_VCC +GND ftop/ctop/inf/dp0/bram_0_serverAdapterA_outDataCore/XST_GND +GND ftop/ctop/inf/dp0/bram_0_serverAdapterB_outDataCore/XST_GND +GND ftop/ctop/inf/dp0/bram_1_memory/XST_GND +VCC ftop/ctop/inf/dp0/bram_1_memory/XST_VCC +GND ftop/ctop/inf/dp0/bram_1_serverAdapterA_outDataCore/XST_GND +GND ftop/ctop/inf/dp0/bram_1_serverAdapterB_outDataCore/XST_GND +GND ftop/ctop/inf/dp0/bram_2_memory/XST_GND +VCC ftop/ctop/inf/dp0/bram_2_memory/XST_VCC +GND ftop/ctop/inf/dp0/bram_2_serverAdapterA_outDataCore/XST_GND +GND ftop/ctop/inf/dp0/bram_2_serverAdapterB_outDataCore/XST_GND +GND ftop/ctop/inf/dp0/bram_3_memory/XST_GND +VCC ftop/ctop/inf/dp0/bram_3_memory/XST_VCC +GND ftop/ctop/inf/dp0/bram_3_serverAdapterA_outDataCore/XST_GND +GND ftop/ctop/inf/dp0/bram_3_serverAdapterB_outDataCore/XST_GND +GND ftop/ctop/inf/dp0/wci_reqF/XST_GND +GND ftop/ctop/inf/dp0/wmi_wmi_mFlagF/XST_GND +GND ftop/ctop/inf/dp0/wmi_wmi_reqF/XST_GND +LUT2 ftop/ctop/inf/dp1/Msub_byteCount__h29653[11:0]10 + optimized to 1 +LUT2 ftop/ctop/inf/dp1/Msub_byteCount__h29653[11:0]2 + optimized to 1 +LUT2 ftop/ctop/inf/dp1/Msub_byteCount__h29653[11:0]3 + optimized to 1 +LUT2 ftop/ctop/inf/dp1/Msub_byteCount__h29653[11:0]4 + optimized to 1 +LUT2 ftop/ctop/inf/dp1/Msub_byteCount__h29653[11:0]5 + optimized to 1 +LUT2 ftop/ctop/inf/dp1/Msub_byteCount__h29653[11:0]6 + optimized to 1 +LUT2 ftop/ctop/inf/dp1/Msub_byteCount__h29653[11:0]7 + optimized to 1 +LUT2 ftop/ctop/inf/dp1/Msub_byteCount__h29653[11:0]8 + optimized to 1 +LUT2 ftop/ctop/inf/dp1/Msub_byteCount__h29653[11:0]9 + optimized to 1 +GND ftop/ctop/inf/dp1/XST_GND +VCC ftop/ctop/inf/dp1/XST_VCC +GND ftop/ctop/inf/dp1/bram_0_memory/XST_GND +VCC ftop/ctop/inf/dp1/bram_0_memory/XST_VCC +GND ftop/ctop/inf/dp1/bram_0_serverAdapterA_outDataCore/XST_GND +GND ftop/ctop/inf/dp1/bram_0_serverAdapterB_outDataCore/XST_GND +GND ftop/ctop/inf/dp1/bram_1_memory/XST_GND +VCC ftop/ctop/inf/dp1/bram_1_memory/XST_VCC +GND ftop/ctop/inf/dp1/bram_1_serverAdapterA_outDataCore/XST_GND +GND ftop/ctop/inf/dp1/bram_1_serverAdapterB_outDataCore/XST_GND +GND ftop/ctop/inf/dp1/bram_2_memory/XST_GND +VCC ftop/ctop/inf/dp1/bram_2_memory/XST_VCC +GND ftop/ctop/inf/dp1/bram_2_serverAdapterA_outDataCore/XST_GND +GND ftop/ctop/inf/dp1/bram_3_memory/XST_GND +VCC ftop/ctop/inf/dp1/bram_3_memory/XST_VCC +GND ftop/ctop/inf/dp1/bram_3_serverAdapterA_outDataCore/XST_GND +GND ftop/ctop/inf/dp1/wci_reqF/XST_GND +GND ftop/ctop/inf/dp1/wmi_wmi_dhF/XST_GND +GND ftop/ctop/inf/dp1/wmi_wmi_mFlagF/XST_GND +GND ftop/ctop/inf/dp1/wmi_wmi_reqF/XST_GND +GND ftop/dram0/XST_GND +VCC ftop/dram0/XST_VCC +GND ftop/dram0/lreqF/XST_GND +GND ftop/dram0/lrespF/XST_GND +VCC ftop/dram0/memc_mem_rst_p/XST_VCC +GND ftop/dram0/memc_memc/u_infrastructure/XST_GND +VCC ftop/dram0/memc_memc/u_infrastructure/XST_VCC +GND ftop/dram0/memc_memc/u_iodelay_ctrl/XST_GND +GND ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/XST_GND +VCC ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[0].ba +nk0/bank_compare0/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[0].ba +nk0/bank_compare0/XST_VCC +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[0].ba +nk0/bank_state0/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[1].ba +nk0/bank_compare0/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[1].ba +nk0/bank_compare0/XST_VCC +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[1].ba +nk0/bank_state0/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[2].ba +nk0/bank_compare0/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[2].ba +nk0/bank_compare0/XST_VCC +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[2].ba +nk0/bank_state0/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[3].ba +nk0/bank_compare0/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[3].ba +nk0/bank_compare0/XST_VCC +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/bank_mach0/bank_cntrl[3].ba +nk0/bank_state0/XST_VCC +GND ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/XST_GND +VCC ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/col_mach0/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/rank_mach0/rank_cntrl[0].ra +nk_cntrl0/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/rank_mach0/rank_cntrl[0].ra +nk_cntrl0/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/rank_mach0/rank_common0/XST +_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/mc0/rank_mach0/rank_common0/XST +_VCC +GND ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/XST_GND +VCC ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/gen_enable_pd.u_phy_pd +_top/gen_pd[0].gen_pd_inst.u_phy_pd/XST_GND +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/mb_wrlvl_inst.u_phy_wr +lvl/XST_GND +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_clock_io/gen_ck[ +0].u_phy_ck_iob/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_clock_io/gen_ck[ +0].u_phy_ck_iob/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_control_io/XST_G +ND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_control_io/XST_V +CC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_i +nst.gen_dm[0].u_phy_dm_iob/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_i +nst.gen_dm[0].u_phy_dm_iob/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_i +nst.gen_dm[1].u_phy_dm_iob/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_i +nst.gen_dm[1].u_phy_dm_iob/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_i +nst.gen_dm[2].u_phy_dm_iob/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_i +nst.gen_dm[2].u_phy_dm_iob/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_i +nst.gen_dm[3].u_phy_dm_iob/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_i +nst.gen_dm[3].u_phy_dm_iob/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_i +nst.gen_dm[4].u_phy_dm_iob/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_i +nst.gen_dm[4].u_phy_dm_iob/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_i +nst.gen_dm[5].u_phy_dm_iob/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_i +nst.gen_dm[5].u_phy_dm_iob/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_i +nst.gen_dm[6].u_phy_dm_iob/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_i +nst.gen_dm[6].u_phy_dm_iob/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_i +nst.gen_dm[7].u_phy_dm_iob/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dm_i +nst.gen_dm[7].u_phy_dm_iob/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[0 +].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[0 +].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[1 +0].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[1 +0].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[1 +1].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[1 +1].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[1 +2].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[1 +2].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[1 +3].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[1 +3].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[1 +4].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[1 +4].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[1 +5].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[1 +5].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[1 +6].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[1 +6].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[1 +7].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[1 +7].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[1 +8].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[1 +8].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[1 +9].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[1 +9].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[1 +].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[1 +].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[2 +0].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[2 +0].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[2 +1].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[2 +1].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[2 +2].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[2 +2].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[2 +3].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[2 +3].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[2 +4].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[2 +4].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[2 +5].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[2 +5].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[2 +6].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[2 +6].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[2 +7].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[2 +7].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[2 +8].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[2 +8].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[2 +9].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[2 +9].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[2 +].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[2 +].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[3 +0].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[3 +0].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[3 +1].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[3 +1].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[3 +2].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[3 +2].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[3 +3].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[3 +3].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[3 +4].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[3 +4].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[3 +5].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[3 +5].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[3 +6].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[3 +6].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[3 +7].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[3 +7].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[3 +8].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[3 +8].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[3 +9].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[3 +9].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[3 +].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[3 +].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[4 +0].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[4 +0].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[4 +1].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[4 +1].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[4 +2].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[4 +2].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[4 +3].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[4 +3].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[4 +4].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[4 +4].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[4 +5].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[4 +5].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[4 +6].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[4 +6].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[4 +7].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[4 +7].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[4 +8].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[4 +8].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[4 +9].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[4 +9].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[4 +].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[4 +].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[5 +0].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[5 +0].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[5 +1].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[5 +1].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[5 +2].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[5 +2].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[5 +3].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[5 +3].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[5 +4].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[5 +4].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[5 +5].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[5 +5].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[5 +6].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[5 +6].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[5 +7].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[5 +7].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[5 +8].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[5 +8].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[5 +9].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[5 +9].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[5 +].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[5 +].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[6 +0].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[6 +0].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[6 +1].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[6 +1].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[6 +2].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[6 +2].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[6 +3].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[6 +3].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[6 +].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[6 +].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[7 +].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[7 +].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[8 +].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[8 +].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[9 +].u_iob_dq/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dq[9 +].u_iob_dq/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[ +0].u_phy_dqs_iob/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[ +0].u_phy_dqs_iob/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[ +1].u_phy_dqs_iob/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[ +1].u_phy_dqs_iob/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[ +2].u_phy_dqs_iob/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[ +2].u_phy_dqs_iob/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[ +3].u_phy_dqs_iob/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[ +3].u_phy_dqs_iob/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[ +4].u_phy_dqs_iob/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[ +4].u_phy_dqs_iob/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[ +5].u_phy_dqs_iob/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[ +5].u_phy_dqs_iob/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[ +6].u_phy_dqs_iob/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[ +6].u_phy_dqs_iob/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[ +7].u_phy_dqs_iob/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[ +7].u_phy_dqs_iob/XST_VCC +GND ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_init/XST_GND +VCC ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_init/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_rdlvl/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk +_gen/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk +_gen/XST_VCC +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdctr +l_sync/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddat +a_sync/gen_c0.u_rddata_sync_c0/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddat +a_sync/gen_c0.u_rddata_sync_c0/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddat +a_sync/gen_c1.u_rddata_sync_c1/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rddat +a_sync/gen_c1.u_rddata_sync_c1/XST_VCC +GND + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_write/XST_GND +VCC + ftop/dram0/memc_memc/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_write/XST_VCC +GND ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/XST_GND +VCC ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/XST_VCC +GND ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/XST_GND +VCC ftop/dram0/memc_memc/u_memc_ui_top/u_ui_top/ui_wr_data0/XST_VCC +GND ftop/dram0/wci_wslv_reqF/XST_GND +GND ftop/flash0/XST_GND +VCC ftop/flash0/XST_VCC +GND ftop/flash0/wci_wslv_reqF/XST_GND +GND ftop/fmc150/XST_GND +VCC ftop/fmc150/XST_VCC +VCC ftop/fmc150/fcCdc_testRst/XST_VCC +VCC ftop/fmc150/spiCDC_slowReset/XST_VCC +VCC ftop/fmc150/spiDAC_slowReset/XST_VCC +GND ftop/fmc150/wci_wslv_reqF/XST_GND +GND ftop/gbe0/XST_GND +VCC ftop/gbe0/XST_VCC +GND ftop/gbe0/gmac/XST_GND +VCC ftop/gbe0/gmac/XST_VCC +GND ftop/gbe0/gmac/rxRS_rxF/XST_GND +VCC ftop/gbe0/gmac/rxRS_rxRst/XST_VCC +GND ftop/gbe0/gmac/txRS_txF/XST_GND +VCC ftop/gbe0/gmac/txRS_txRst/XST_VCC +GND ftop/gbe0/mdi_rPlayIndex/XST_GND +VCC ftop/gbe0/phyRst/rstSync/XST_VCC +GND ftop/gbe0/wci_wslv_reqF/XST_GND +GND ftop/lcd_ctrl/XST_GND +VCC ftop/lcd_ctrl/XST_VCC +GND ftop/pciw_fI2P/XST_GND +GND ftop/pciw_fP2I/XST_GND +VCC ftop/pciw_p125rst/XST_VCC +VCC ftop/pciw_p250rst/XST_VCC +GND ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/XST_GND +VCC ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/XST_VCC +GND + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[0].ram/XS +T_GND +VCC + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[0].ram/XS +T_VCC +GND + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[1].ram/XS +T_GND +VCC + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[1].ram/XS +T_VCC +GND + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[2].ram/XS +T_GND +VCC + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[2].ram/XS +T_VCC +GND + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[3].ram/XS +T_GND +VCC + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[3].ram/XS +T_VCC +GND + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[0].ram/XS +T_GND +VCC + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[0].ram/XS +T_VCC +GND + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[1].ram/XS +T_GND +VCC + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[1].ram/XS +T_VCC +GND + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[2].ram/XS +T_GND +VCC + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[2].ram/XS +T_VCC +GND + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[3].ram/XS +T_GND +VCC + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[3].ram/XS +T_VCC +VCC ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/XST_VCC +GND + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[0].GTX_DRP_CHANAL +IGN_FIX_3752/XST_GND +VCC + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[0].GTX_RX_VALID_F +ILTER/XST_VCC +GND + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[0].GTX_TX_SYNC/XS +T_GND +GND + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[1].GTX_DRP_CHANAL +IGN_FIX_3752/XST_GND +VCC + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[1].GTX_RX_VALID_F +ILTER/XST_VCC +GND + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[1].GTX_TX_SYNC/XS +T_GND +GND + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX_DRP_CHANAL +IGN_FIX_3752/XST_GND +VCC + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX_RX_VALID_F +ILTER/XST_VCC +GND + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[2].GTX_TX_SYNC/XS +T_GND +GND + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX_DRP_CHANAL +IGN_FIX_3752/XST_GND +VCC + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX_RX_VALID_F +ILTER/XST_VCC +GND + ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[3].GTX_TX_SYNC/XS +T_GND +GND ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/XST_GND +VCC ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_gt_i/gtx_v6_i/XST_VCC +GND ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_pipe_i/XST_GND +VCC ftop/pciw_pci0_pcie_ep/ep/pcie_2_0_i/pcie_pipe_i/XST_VCC +GND ftop/pciw_pci0_pcie_ep/ep/pcie_clocking_i/XST_GND +VCC ftop/pciw_pci0_pcie_ep/ep/pcie_clocking_i/XST_VCC +GND ftop/pciw_pci0_pcie_ep/ep/pcie_reset_delay_i/XST_GND +VCC ftop/pciw_pci0_pcie_ep/ep/pcie_reset_delay_i/XST_VCC +VCC ftop/sys0_rst/XST_VCC +LUT2 ftop/ctop/inf/noc_sm2/pktFork/fo1/Result<2>_SW0 + optimized to 0 + +To enable printing of redundant blocks removed and signals merged, set the +detailed map report option and rerun map. + +Section 6 - IOB Properties +-------------------------- + ++---------------------------------------------------------------------------------------------------------------------------------------------------------+ +| IOB Name | Type | Direction | IO Standard | Diff | Drive | Slew | Reg (s) | Resistor | IOB | +| | | | | Term | Strength | Rate | | | Delay | ++---------------------------------------------------------------------------------------------------------------------------------------------------------+ +| ddr3_addr<0> | IOB | OUTPUT | SSTL15 | | | | OSERDES | | | +| ddr3_addr<1> | IOB | OUTPUT | SSTL15 | | | | OSERDES | | | +| ddr3_addr<2> | IOB | OUTPUT | SSTL15 | | | | OSERDES | | | +| ddr3_addr<3> | IOB | OUTPUT | SSTL15 | | | | OSERDES | | | +| ddr3_addr<4> | IOB | OUTPUT | SSTL15 | | | | OSERDES | | | +| ddr3_addr<5> | IOB | OUTPUT | SSTL15 | | | | OSERDES | | | +| ddr3_addr<6> | IOB | OUTPUT | SSTL15 | | | | OSERDES | | | +| ddr3_addr<7> | IOB | OUTPUT | SSTL15 | | | | OSERDES | | | +| ddr3_addr<8> | IOB | OUTPUT | SSTL15 | | | | OSERDES | | | +| ddr3_addr<9> | IOB | OUTPUT | SSTL15 | | | | OSERDES | | | +| ddr3_addr<10> | IOB | OUTPUT | SSTL15 | | | | OSERDES | | | +| ddr3_addr<11> | IOB | OUTPUT | SSTL15 | | | | OSERDES | | | +| ddr3_addr<12> | IOB | OUTPUT | SSTL15 | | | | OSERDES | | | +| ddr3_ba<0> | IOB | OUTPUT | SSTL15 | | | | OSERDES | | | +| ddr3_ba<1> | IOB | OUTPUT | SSTL15 | | | | OSERDES | | | +| ddr3_ba<2> | IOB | OUTPUT | SSTL15 | | | | OSERDES | | | +| ddr3_cas_n | IOB | OUTPUT | SSTL15 | | | | OSERDES | | | +| ddr3_ck_n<0> | IOBS | OUTPUT | DIFF_SSTL15 | | | | | | | +| ddr3_ck_p<0> | IOBM | OUTPUT | DIFF_SSTL15 | | | | OSERDES | | | +| ddr3_cke<0> | IOB | OUTPUT | SSTL15 | | | | OSERDES | | | +| ddr3_cs_n<0> | IOB | OUTPUT | SSTL15 | | | | OSERDES | | | +| ddr3_dm<0> | IOB | OUTPUT | SSTL15 | | | | OSERDES | | FIXED | +| ddr3_dm<1> | IOB | OUTPUT | SSTL15 | | | | OSERDES | | FIXED | +| ddr3_dm<2> | IOB | OUTPUT | SSTL15 | | | | OSERDES | | FIXED | +| ddr3_dm<3> | IOB | OUTPUT | SSTL15 | | | | OSERDES | | FIXED | +| ddr3_dm<4> | IOB | OUTPUT | SSTL15 | | | | OSERDES | | FIXED | +| ddr3_dm<5> | IOB | OUTPUT | SSTL15 | | | | OSERDES | | FIXED | +| ddr3_dm<6> | IOB | OUTPUT | SSTL15 | | | | OSERDES | | FIXED | +| ddr3_dm<7> | IOB | OUTPUT | SSTL15 | | | | OSERDES | | FIXED | +| ddr3_dq<0> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<1> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<2> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<3> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<4> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<5> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<6> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<7> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<8> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<9> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<10> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<11> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<12> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<13> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<14> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<15> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<16> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<17> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<18> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<19> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<20> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<21> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<22> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<23> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<24> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<25> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<26> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<27> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<28> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<29> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<30> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<31> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<32> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<33> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<34> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<35> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<36> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<37> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<38> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<39> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<40> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<41> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<42> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<43> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<44> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<45> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<46> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<47> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<48> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<49> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<50> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<51> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<52> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<53> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<54> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<55> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<56> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<57> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<58> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<59> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<60> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<61> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<62> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dq<63> | IOB | BIDIR | SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dqs_n<0> | IOBS | BIDIR | DIFF_SSTL15_T_DCI | | | | OSERDES | | | +| ddr3_dqs_n<1> | IOBS | BIDIR | DIFF_SSTL15_T_DCI | | | | OSERDES | | | +| ddr3_dqs_n<2> | IOBS | BIDIR | DIFF_SSTL15_T_DCI | | | | OSERDES | | | +| ddr3_dqs_n<3> | IOBS | BIDIR | DIFF_SSTL15_T_DCI | | | | OSERDES | | | +| ddr3_dqs_n<4> | IOBS | BIDIR | DIFF_SSTL15_T_DCI | | | | OSERDES | | | +| ddr3_dqs_n<5> | IOBS | BIDIR | DIFF_SSTL15_T_DCI | | | | OSERDES | | | +| ddr3_dqs_n<6> | IOBS | BIDIR | DIFF_SSTL15_T_DCI | | | | OSERDES | | | +| ddr3_dqs_n<7> | IOBS | BIDIR | DIFF_SSTL15_T_DCI | | | | OSERDES | | | +| ddr3_dqs_p<0> | IOBM | BIDIR | DIFF_SSTL15_T_DCI | | | | ISERDESE1OSE | | | +| ddr3_dqs_p<1> | IOBM | BIDIR | DIFF_SSTL15_T_DCI | | | | OSERDES | | VAR_LOAD | +| ddr3_dqs_p<2> | IOBM | BIDIR | DIFF_SSTL15_T_DCI | | | | OSERDES | | VAR_LOAD | +| ddr3_dqs_p<3> | IOBM | BIDIR | DIFF_SSTL15_T_DCI | | | | OSERDES | | VAR_LOAD | +| ddr3_dqs_p<4> | IOBM | BIDIR | DIFF_SSTL15_T_DCI | | | | OSERDES | | VAR_LOAD | +| ddr3_dqs_p<5> | IOBM | BIDIR | DIFF_SSTL15_T_DCI | | | | OSERDES | | VAR_LOAD | +| ddr3_dqs_p<6> | IOBM | BIDIR | DIFF_SSTL15_T_DCI | | | | OSERDES | | VAR_LOAD | +| ddr3_dqs_p<7> | IOBM | BIDIR | DIFF_SSTL15_T_DCI | | | | OSERDES | | VAR_LOAD | +| ddr3_odt<0> | IOB | OUTPUT | SSTL15 | | | | OSERDES | | | +| ddr3_ras_n | IOB | OUTPUT | SSTL15 | | | | OSERDES | | | +| ddr3_reset_n | IOB | OUTPUT | SSTL15 | | | | ODDR | | | +| ddr3_we_n | IOB | OUTPUT | SSTL15 | | | | OSERDES | | | +| flash_addr<0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flash_addr<1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flash_addr<2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flash_addr<3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flash_addr<4> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flash_addr<5> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flash_addr<6> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flash_addr<7> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flash_addr<8> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flash_addr<9> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flash_addr<10> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flash_addr<11> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flash_addr<12> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flash_addr<13> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flash_addr<14> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flash_addr<15> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flash_addr<16> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flash_addr<17> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flash_addr<18> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flash_addr<19> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flash_addr<20> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flash_addr<21> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flash_addr<22> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flash_addr<23> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flash_ce_n | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flash_io_dq<0> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | | +| flash_io_dq<1> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | | +| flash_io_dq<2> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | | +| flash_io_dq<3> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | | +| flash_io_dq<4> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | | +| flash_io_dq<5> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | | +| flash_io_dq<6> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | | +| flash_io_dq<7> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | | +| flash_io_dq<8> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | | +| flash_io_dq<9> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | | +| flash_io_dq<10> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | | +| flash_io_dq<11> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | | +| flash_io_dq<12> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | | +| flash_io_dq<13> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | | +| flash_io_dq<14> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | | +| flash_io_dq<15> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | | +| flash_oe_n | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flash_wait | IOB | INPUT | LVCMOS25 | | | | | | | +| flash_we_n | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flp_cdc_clk_n | IOB | INPUT | LVDS_25 | TRUE | | | | | | +| flp_cdc_clk_p | IOB | INPUT | LVDS_25 | TRUE | | | | | | +| flp_cdc_csb | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flp_cdc_pdn | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flp_cdc_refen | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flp_cdc_rstn | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flp_cdc_sdi | IOB | INPUT | LVCMOS25 | | | | | | | +| flp_com_sclk | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flp_com_sdc2m | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flp_dac_csb | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| flp_dac_sdi | IOB | INPUT | LVCMOS25 | | | | | | | +| gmii_gtx_clk | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | ODDR | | | +| gmii_rstn | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| gmii_rx_clk | IOB | INPUT | LVCMOS25 | | | | | | FIXED | +| gmii_rx_dv | IOB | INPUT | LVCMOS25 | | | | | | | +| gmii_rx_er | IOB | INPUT | LVCMOS25 | | | | | | | +| gmii_rxd<0> | IOB | INPUT | LVCMOS25 | | | | | | | +| gmii_rxd<1> | IOB | INPUT | LVCMOS25 | | | | | | | +| gmii_rxd<2> | IOB | INPUT | LVCMOS25 | | | | | | | +| gmii_rxd<3> | IOB | INPUT | LVCMOS25 | | | | | | | +| gmii_rxd<4> | IOB | INPUT | LVCMOS25 | | | | | | | +| gmii_rxd<5> | IOB | INPUT | LVCMOS25 | | | | | | | +| gmii_rxd<6> | IOB | INPUT | LVCMOS25 | | | | | | | +| gmii_rxd<7> | IOB | INPUT | LVCMOS25 | | | | | | | +| gmii_tx_en | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | ODDR | | | +| gmii_tx_er | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | ODDR | | | +| gmii_txd<0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | ODDR | | | +| gmii_txd<1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | ODDR | | | +| gmii_txd<2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | ODDR | | | +| gmii_txd<3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | ODDR | | | +| gmii_txd<4> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | ODDR | | | +| gmii_txd<5> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | ODDR | | | +| gmii_txd<6> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | ODDR | | | +| gmii_txd<7> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | ODDR | | | +| lcd_db<0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| lcd_db<1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| lcd_db<2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| lcd_db<3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| lcd_e | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| lcd_rs | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| lcd_rw | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| led<0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| led<1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| led<2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| led<3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| led<4> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| led<5> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| led<6> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| led<7> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| led<8> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| led<9> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| led<10> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| led<11> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| led<12> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| mdio_mdc | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| mdio_mdd | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | | +| pci0_clkn | IPAD | INPUT | | | | | | | | +| pci0_clkp | IPAD | INPUT | | | | | | | | +| pci0_reset_n | IOB | INPUT | LVCMOS25 | | | | | PULLUP | | +| pci_exp_rxn<0> | IPAD | INPUT | | | | | | | | +| pci_exp_rxn<1> | IPAD | INPUT | | | | | | | | +| pci_exp_rxn<2> | IPAD | INPUT | | | | | | | | +| pci_exp_rxn<3> | IPAD | INPUT | | | | | | | | +| pci_exp_rxp<0> | IPAD | INPUT | | | | | | | | +| pci_exp_rxp<1> | IPAD | INPUT | | | | | | | | +| pci_exp_rxp<2> | IPAD | INPUT | | | | | | | | +| pci_exp_rxp<3> | IPAD | INPUT | | | | | | | | +| pci_exp_txn<0> | OPAD | OUTPUT | | | | | | | | +| pci_exp_txn<1> | OPAD | OUTPUT | | | | | | | | +| pci_exp_txn<2> | OPAD | OUTPUT | | | | | | | | +| pci_exp_txn<3> | OPAD | OUTPUT | | | | | | | | +| pci_exp_txp<0> | OPAD | OUTPUT | | | | | | | | +| pci_exp_txp<1> | OPAD | OUTPUT | | | | | | | | +| pci_exp_txp<2> | OPAD | OUTPUT | | | | | | | | +| pci_exp_txp<3> | OPAD | OUTPUT | | | | | | | | +| ppsExtIn | IOB | INPUT | LVCMOS25 | | | | | | | +| ppsOut | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| sys0_clkn | IOB | INPUT | LVDS_25 | FALSE | | | | | | +| sys0_clkp | IOB | INPUT | LVDS_25 | FALSE | | | | | | +| sys1_clkn | IPAD | INPUT | | | | | | | | +| sys1_clkp | IPAD | INPUT | | | | | | | | ++---------------------------------------------------------------------------------------------------------------------------------------------------------+ + +Section 7 - RPMs +---------------- + +Section 8 - Guide Report +------------------------ +Guide not run on this design. + +Section 9 - Area Group and Partition Summary +-------------------------------------------- + +Partition Implementation Status +------------------------------- + + No Partitions were found in this design. + +------------------------------- + +Area Group Information +---------------------- + +Area Group "AG_pcie0" + No COMPRESSION specified for Area Group "AG_pcie0" + RANGE: SLICE_X136Y147:SLICE_X155Y120 + Slice Logic Utilization: + Number of Slice Registers: 451 out of 4,480 10% + Number of Slice LUTs: 646 out of 2,240 28% + Number used as logic: 642 + Number used as Memory: 4 + Slice Logic Distribution: + Number of occupied Slices: 257 out of 560 45% + Number of LUT Flip Flop pairs used: 731 + Number with an unused Flip Flop: 312 out of 731 42% + Number with an unused LUT: 79 out of 731 10% + Number of fully used LUT-FF pairs: 340 out of 731 46% + Number of RAMB36E1/FIFO36E1s: 8 + Number using RAMB36E1 only: 8 + Number using FIFO36E1 only: 0 + + +Section 10 - Timing Report +-------------------------- +A logic-level (pre-route) timing report can be generated by using Xilinx static +timing analysis tools, Timing Analyzer (GUI) or TRCE (command line), with the +mapped NCD and PCF files. Please note that this timing report will be generated +using estimated delay information. For accurate numbers, please generate a +timing report with the post Place and Route NCD file. + +For more information about the Timing Analyzer, consult the Xilinx Timing +Analyzer Reference Manual; for more information about TRCE, consult the Xilinx +Command Line Tools User Guide "TRACE" chapter. + +Section 11 - Configuration String Details +----------------------------------------- +Use the "-detail" map option to print out Configuration Strings + +Section 12 - Control Set Information +------------------------------------ +Use the "-detail" map option to print out Control Set Information. + +Section 13 - Utilization by Hierarchy +------------------------------------- +Use the "-detail" map option to print out the Utilization by Hierarchy section. diff --git a/logs/n210-20121107_1002/fpgaTop-n210.srp b/logs/n210-20121107_1002/fpgaTop-n210.srp new file mode 100644 index 00000000..aab9b295 --- /dev/null +++ b/logs/n210-20121107_1002/fpgaTop-n210.srp @@ -0,0 +1,7094 @@ +Release 14.3 - xst P.40xd (lin64) +Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. +--> + +TABLE OF CONTENTS + 1) Synthesis Options Summary + 2) HDL Compilation + 3) Design Hierarchy Analysis + 4) HDL Analysis + 5) HDL Synthesis + 5.1) HDL Synthesis Report + 6) Advanced HDL Synthesis + 6.1) Advanced HDL Synthesis Report + 7) Low Level Synthesis + 8) Partition Report + 9) Final Report + 9.1) Device utilization summary + 9.2) Partition Resource Summary + 9.3) TIMING REPORT + + +========================================================================= +* Synthesis Options Summary * +========================================================================= +---- Source Parameters +Input File Name : "fpgaTop-n210.prj" +Input Format : mixed + +---- Target Parameters +Output File Name : "fpgaTop" +Output Format : NGC +Target Device : xc3sd3400a-fg676-5 + +---- Source Options +Top Module Name : fpgaTop +Automatic FSM Extraction : YES +FSM Encoding Algorithm : Auto +Safe Implementation : No +FSM Style : lut +RAM Extraction : Yes +RAM Style : Auto +ROM Extraction : Yes +Shift Register Extraction : YES +ROM Style : Auto +Resource Sharing : YES +Asynchronous To Synchronous : NO +Use DSP Block : auto +Automatic Register Balancing : NO + +---- Target Options +Add IO Buffers : YES +Global Maximum Fanout : 100000 +Add Generic Clock Buffer(BUFG) : 32 +Register Duplication : YES +Optimize Instantiated Primitives : NO +Use Clock Enable : Auto +Use Synchronous Set : Auto +Use Synchronous Reset : Auto +Pack IO Registers into IOBs : auto +Equivalent register Removal : YES + +---- General Options +Optimization Goal : Speed +Optimization Effort : 1 +Library Search Order : work.lso +Keep Hierarchy : soft +Netlist Hierarchy : rebuilt +RTL Output : Yes +Read Cores : optimize +Write Timing Constraints : NO +Cross Clock Analysis : NO +Hierarchy Separator : / +Bus Delimiter : <> +Case Specifier : maintain +Slice Utilization Ratio : 100 +BRAM Utilization Ratio : 100 +DSP48 Utilization Ratio : 100 +Auto BRAM Packing : NO +Slice Utilization Ratio Delta : 5 + +========================================================================= + + +========================================================================= +* HDL Compilation * +========================================================================= +Compiling verilog file "../../libsrc/hdl/bsv/BRAM1BE.v" in library work +Compiling verilog file "../../libsrc/hdl/bsv/BRAM1.v" in library work +Module compiled +Compiling verilog file "../../libsrc/hdl/bsv/BRAM1Load.v" in library work +Module compiled +Compiling verilog file "../../libsrc/hdl/bsv/BRAM2.v" in library work +Module compiled +Compiling verilog file "../../libsrc/hdl/bsv/BypassCrossingWire.v" in library work +Module compiled +Compiling verilog file "../../libsrc/hdl/bsv/BypassWire.v" in library work +Module compiled +Compiling verilog file "../../libsrc/hdl/bsv/ClockDiv.v" in library work +Module compiled +Compiling verilog file "../../libsrc/hdl/bsv/ClockInverter.v" in library work +Module compiled +Compiling verilog file "../../libsrc/hdl/bsv/Counter.v" in library work +Module compiled +Compiling verilog file "../../libsrc/hdl/bsv/FIFO10.v" in library work +Module compiled +Compiling verilog file "../../libsrc/hdl/bsv/FIFO1.v" in library work +Module compiled +Compiling verilog file "../../libsrc/hdl/bsv/FIFO20.v" in library work +Module compiled +Compiling verilog file "../../libsrc/hdl/bsv/FIFO2.v" in library work +Module compiled +Compiling verilog file "../../libsrc/hdl/bsv/MakeReset0.v" in library work +Module compiled +Compiling verilog file "../../libsrc/hdl/bsv/MakeResetA.v" in library work +Module compiled +Compiling verilog file "../../libsrc/hdl/bsv/ResetEither.v" in library work +Module compiled +Compiling verilog file "../../libsrc/hdl/bsv/ResetInverter.v" in library work +Module compiled +Compiling verilog file "../../libsrc/hdl/bsv/ResetToBool.v" in library work +Module compiled +Compiling verilog file "../../libsrc/hdl/bsv/RevertReg.v" in library work +Module compiled +Compiling verilog file "../../libsrc/hdl/bsv/SizedFIFO.v" in library work +Module compiled +Compiling verilog file "../../libsrc/hdl/bsv/SyncBit.v" in library work +Module compiled +Compiling verilog file "../../libsrc/hdl/bsv/SyncFIFO.v" in library work +Module compiled +Compiling verilog file "../../libsrc/hdl/bsv/SyncHandshake.v" in library work +Module compiled +Compiling verilog file "../../libsrc/hdl/bsv/SyncPulse.v" in library work +Module compiled +Compiling verilog file "../../libsrc/hdl/bsv/SyncRegister.v" in library work +Module compiled +Compiling verilog file "../../libsrc/hdl/bsv/SyncReset0.v" in library work +Module compiled +Compiling verilog file "../../libsrc/hdl/bsv/SyncResetA.v" in library work +Module compiled +Compiling verilog file "../../libsrc/hdl/bsv/TriState.v" in library work +Module compiled +Compiling verilog file "../../rtl/mkCRC32.v" in library work +Module compiled +Compiling verilog file "../../rtl/mkGMAC.v" in library work +Module compiled +Compiling verilog file "../../rtl/mkQBGMAC.v" in library work +Module compiled +Compiling verilog file "../../rtl/mkGbeWrk.v" in library work +Module compiled +Compiling verilog file "../../rtl/mkGbeQABS.v" in library work +Module compiled +Compiling verilog file "../../rtl/mkQABSMF3.v" in library work +Module compiled +Compiling verilog file "../../rtl/mkEDCPAdapter.v" in library work +Module compiled +Compiling verilog file "../../rtl/mkEDDPAdapter.v" in library work +Module compiled +Compiling verilog file "../../rtl/mkOCCP.v" in library work +Module compiled +Compiling verilog file "../../rtl/mkOCEDP4B.v" in library work +Module compiled +Compiling verilog file "../../rtl/mkLedN210.v" in library work +Module compiled +Compiling verilog file "../../rtl/mkIQADCWorker.v" in library work +Module compiled +Compiling verilog file "../../rtl/mkWSICaptureWorker4B.v" in library work +Module compiled +Compiling verilog file "../../rtl/mkWSIPatternWorker4B.v" in library work +Module compiled +Compiling verilog file "../../rtl/mkBiasWorker4B.v" in library work +Module compiled +Compiling verilog file "../../rtl/mkSMAdapter4B.v" in library work +Module compiled +Compiling verilog file "../../rtl/mkPWrk_n210.v" in library work +Module compiled +Compiling verilog file "../../rtl/mkFTop_n210.v" in library work +Module compiled +Compiling verilog file "../../libsrc/hdl/ocpi/n210_uuid.v" in library work +Module compiled +Compiling verilog file "../../libsrc/hdl/ocpi/arSRLFIFOD.v" in library work +Module compiled +Compiling verilog file "../../libsrc/hdl/ocpi/clock_n210.v" in library work +Module compiled +Compiling verilog file "../../libsrc/hdl/ocpi/fpgaTop_n210.v" in library work +Module compiled +Module compiled +No errors in compilation +Analysis of file <"fpgaTop-n210.prj"> succeeded. + + +========================================================================= +* Design Hierarchy Analysis * +========================================================================= +Analyzing hierarchy for module in library . + +Analyzing hierarchy for module in library . + + +Analyzing hierarchy for module in library . + +Analyzing hierarchy for module in library . + +Analyzing hierarchy for module in library . + +Analyzing hierarchy for module in library . + + + +Analyzing hierarchy for module in library . + + + + + +Analyzing hierarchy for module in library . + +Analyzing hierarchy for module in library . + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +Analyzing hierarchy for module in library . + + + + + + + + + + + + +Analyzing hierarchy for module in library . + +Analyzing hierarchy for module in library . + +Analyzing hierarchy for module in library . + +Analyzing hierarchy for module in library . + + + + + + + + + + + + + + +Analyzing hierarchy for module in library . + + + + + + +Analyzing hierarchy for module in library . + + + +Analyzing hierarchy for module in library . + +Analyzing hierarchy for module in library . + + + +========================================================================= +* HDL Analysis * +========================================================================= +Analyzing top module . +Module is correct for synthesis. + +Analyzing module in library . +Module is correct for synthesis. + + Set user-defined property "CAPACITANCE = DONT_CARE" for instance in unit . + Set user-defined property "DIFF_TERM = FALSE" for instance in unit . + Set user-defined property "DQS_BIAS = FALSE" for instance in unit . + Set user-defined property "IBUF_DELAY_VALUE = 0" for instance in unit . + Set user-defined property "IBUF_LOW_PWR = TRUE" for instance in unit . + Set user-defined property "IFD_DELAY_VALUE = AUTO" for instance in unit . + Set user-defined property "IOSTANDARD = DEFAULT" for instance in unit . +Analyzing module in library . +"../../rtl/mkBiasWorker4B.v" line 786: Found Parallel Case directive in module . +"../../rtl/mkBiasWorker4B.v" line 1018: Found Parallel Case directive in module . +"../../rtl/mkBiasWorker4B.v" line 1042: Found Parallel Case directive in module . +"../../rtl/mkBiasWorker4B.v" line 1127: Found Parallel Case directive in module . +"../../rtl/mkBiasWorker4B.v" line 1150: Found Parallel Case directive in module . +Module is correct for synthesis. + +Analyzing module in library . +Module is correct for synthesis. + +Analyzing module in library . +Module is correct for synthesis. + +Analyzing module in library . +Module is correct for synthesis. + + Set user-defined property "CLKDV_DIVIDE = 2.000000" for instance in unit . + Set user-defined property "CLKFX_DIVIDE = 4" for instance in unit . + Set user-defined property "CLKFX_MULTIPLY = 5" for instance in unit . + Set user-defined property "CLKIN_DIVIDE_BY_2 = FALSE" for instance in unit . + Set user-defined property "CLKIN_PERIOD = 10.000000" for instance in unit . + Set user-defined property "CLKOUT_PHASE_SHIFT = NONE" for instance in unit . + Set user-defined property "CLK_FEEDBACK = 1X" for instance in unit . + Set user-defined property "DESKEW_ADJUST = SYSTEM_SYNCHRONOUS" for instance in unit . + Set user-defined property "DFS_FREQUENCY_MODE = LOW" for instance in unit . + Set user-defined property "DLL_FREQUENCY_MODE = LOW" for instance in unit . + Set user-defined property "DSS_MODE = NONE" for instance in unit . + Set user-defined property "DUTY_CYCLE_CORRECTION = TRUE" for instance in unit . + Set user-defined property "FACTORY_JF = C080" for instance in unit . + Set user-defined property "PHASE_SHIFT = 0" for instance in unit . + Set user-defined property "STARTUP_WAIT = FALSE" for instance in unit . +Analyzing module in library . +"../../rtl/mkOCCP.v" line 9786: Found Parallel Case directive in module . +"../../rtl/mkOCCP.v" line 9819: Found Parallel Case directive in module . +"../../rtl/mkOCCP.v" line 9850: Found Parallel Case directive in module . +"../../rtl/mkOCCP.v" line 9881: Found Parallel Case directive in module . +"../../rtl/mkOCCP.v" line 9912: Found Parallel Case directive in module . +"../../rtl/mkOCCP.v" line 9947: Found Parallel Case directive in module . +"../../rtl/mkOCCP.v" line 9978: Found Parallel Case directive in module . +"../../rtl/mkOCCP.v" line 10009: Found Parallel Case directive in module . +"../../rtl/mkOCCP.v" line 10036: Found Parallel Case directive in module . +"../../rtl/mkOCCP.v" line 10067: Found Parallel Case directive in module . +"../../rtl/mkOCCP.v" line 10098: Found Parallel Case directive in module . +"../../rtl/mkOCCP.v" line 10129: Found Parallel Case directive in module . +"../../rtl/mkOCCP.v" line 10160: Found Parallel Case directive in module . +"../../rtl/mkOCCP.v" line 10191: Found Parallel Case directive in module . +"../../rtl/mkOCCP.v" line 10226: Found Parallel Case directive in module . +"../../rtl/mkOCCP.v" line 13212: Found Parallel Case directive in module . +"../../rtl/mkOCCP.v" line 13244: Found Parallel Case directive in module . +"../../rtl/mkOCCP.v" line 13276: Found Parallel Case directive in module . +"../../rtl/mkOCCP.v" line 13308: Found Parallel Case directive in module . +"../../rtl/mkOCCP.v" line 13340: Found Parallel Case directive in module . +"../../rtl/mkOCCP.v" line 13371: Found Parallel Case directive in module . +"../../rtl/mkOCCP.v" line 13402: Found Parallel Case directive in module . +"../../rtl/mkOCCP.v" line 13433: Found Parallel Case directive in module . +"../../rtl/mkOCCP.v" line 13464: Found Parallel Case directive in module . +"../../rtl/mkOCCP.v" line 13495: Found Parallel Case directive in module . +"../../rtl/mkOCCP.v" line 13526: Found Parallel Case directive in module . +"../../rtl/mkOCCP.v" line 13557: Found Parallel Case directive in module . +"../../rtl/mkOCCP.v" line 13588: Found Parallel Case directive in module . +"../../rtl/mkOCCP.v" line 13619: Found Parallel Case directive in module . +"../../rtl/mkOCCP.v" line 13649: Found Parallel Case directive in module . +"../../rtl/mkOCCP.v" line 13671: Found Parallel Case directive in module . +"../../rtl/mkOCCP.v" line 13692: Found Parallel Case directive in module . +"../../rtl/mkOCCP.v" line 13713: Found Parallel Case directive in module . +"../../rtl/mkOCCP.v" line 13737: Found Parallel Case directive in module . +"../../rtl/mkOCCP.v" line 13761: Found Parallel Case directive in module . +"../../rtl/mkOCCP.v" line 13785: Found Parallel Case directive in module . +"../../rtl/mkOCCP.v" line 13809: Found Parallel Case directive in module . +"../../rtl/mkOCCP.v" line 13833: Found Parallel Case directive in module . +"../../rtl/mkOCCP.v" line 13854: Found Parallel Case directive in module . +"../../rtl/mkOCCP.v" line 13876: Found Parallel Case directive in module . +"../../rtl/mkOCCP.v" line 13899: Found Parallel Case directive in module . +"../../rtl/mkOCCP.v" line 13923: Found Parallel Case directive in module . +"../../rtl/mkOCCP.v" line 13947: Found Parallel Case directive in module . +"../../rtl/mkOCCP.v" line 13971: Found Parallel Case directive in module . +"../../rtl/mkOCCP.v" line 13995: Found Parallel Case directive in module . +"../../rtl/mkOCCP.v" line 15024: Found Parallel Case directive in module . +"../../rtl/mkOCCP.v" line 15334: Found Parallel Case directive in module . +"../../rtl/mkOCCP.v" line 15537: Found Parallel Case directive in module . +"../../rtl/mkOCCP.v" line 15591: Found Parallel Case directive in module . +"../../rtl/mkOCCP.v" line 15645: Found Parallel Case directive in module . +"../../rtl/mkOCCP.v" line 15700: Found Parallel Case directive in module . +"../../rtl/mkOCCP.v" line 15755: Found Parallel Case directive in module . +"../../rtl/mkOCCP.v" line 15810: Found Parallel Case directive in module . +"../../rtl/mkOCCP.v" line 15865: Found Parallel Case directive in module . +"../../rtl/mkOCCP.v" line 15920: Found Parallel Case directive in module . +"../../rtl/mkOCCP.v" line 15975: Found Parallel Case directive in module . +"../../rtl/mkOCCP.v" line 16030: Found Parallel Case directive in module . +"../../rtl/mkOCCP.v" line 16085: Found Parallel Case directive in module . +"../../rtl/mkOCCP.v" line 16140: Found Parallel Case directive in module . +"../../rtl/mkOCCP.v" line 16195: Found Parallel Case directive in module . +"../../rtl/mkOCCP.v" line 16250: Found Parallel Case directive in module . +"../../rtl/mkOCCP.v" line 16305: Found Parallel Case directive in module . +Module is correct for synthesis. + +Analyzing module in library . +Module is correct for synthesis. + +Analyzing module in library . +Module is correct for synthesis. + +Analyzing module in library . +Module is correct for synthesis. + +Analyzing module in library . +Module is correct for synthesis. + +Analyzing module in library . +Module is correct for synthesis. + +Analyzing module in library . +Module is correct for synthesis. + +Analyzing module in library . +Module is correct for synthesis. + +Analyzing module in library . +Module is correct for synthesis. + +Analyzing module in library . +Module is correct for synthesis. + +Analyzing module in library . +Module is correct for synthesis. + +Analyzing module in library . +Module is correct for synthesis. + +Analyzing module in library . + Calling function . + Calling function . + Calling function . + Calling function . +Module is correct for synthesis. + +Analyzing module in library . +WARNING:Xst:863 - "../../libsrc/hdl/bsv/MakeResetA.v" line 54: Name conflict ( and , renaming rst as rst_rnm0). +Module is correct for synthesis. + +Analyzing module in library . +Module is correct for synthesis. + +Analyzing module in library . +Module is correct for synthesis. + +Analyzing module in library . +"../../rtl/mkEDCPAdapter.v" line 734: Found Parallel Case directive in module . +"../../rtl/mkEDCPAdapter.v" line 918: Found Parallel Case directive in module . +Module is correct for synthesis. + +Analyzing module in library . +Module is correct for synthesis. + +Analyzing module in library . +Module is correct for synthesis. + +Analyzing module in library . +Module is correct for synthesis. + +Analyzing module in library . +"../../rtl/mkEDDPAdapter.v" line 610: Found Parallel Case directive in module . +"../../rtl/mkEDDPAdapter.v" line 709: Found Parallel Case directive in module . +Module is correct for synthesis. + +Analyzing module in library . +"../../rtl/mkOCEDP4B.v" line 3875: Found Parallel Case directive in module . +"../../rtl/mkOCEDP4B.v" line 4246: Found Parallel Case directive in module . +"../../rtl/mkOCEDP4B.v" line 4623: Found Parallel Case directive in module . +"../../rtl/mkOCEDP4B.v" line 5159: Found Parallel Case directive in module . +"../../rtl/mkOCEDP4B.v" line 5352: Found Parallel Case directive in module . +"../../rtl/mkOCEDP4B.v" line 5778: Found Parallel Case directive in module . +"../../rtl/mkOCEDP4B.v" line 5798: Found Parallel Case directive in module . +"../../rtl/mkOCEDP4B.v" line 6045: Found Parallel Case directive in module . +"../../rtl/mkOCEDP4B.v" line 6068: Found Parallel Case directive in module . +"../../rtl/mkOCEDP4B.v" line 6136: Found Parallel Case directive in module . +"../../rtl/mkOCEDP4B.v" line 6154: Found Parallel Case directive in module . +"../../rtl/mkOCEDP4B.v" line 6171: Found Parallel Case directive in module . +"../../rtl/mkOCEDP4B.v" line 6187: Found Parallel Case directive in module . +"../../rtl/mkOCEDP4B.v" line 6227: Found Parallel Case directive in module . +"../../rtl/mkOCEDP4B.v" line 6245: Found Parallel Case directive in module . +"../../rtl/mkOCEDP4B.v" line 6262: Found Parallel Case directive in module . +"../../rtl/mkOCEDP4B.v" line 6279: Found Parallel Case directive in module . +"../../rtl/mkOCEDP4B.v" line 6320: Found Parallel Case directive in module . +"../../rtl/mkOCEDP4B.v" line 6338: Found Parallel Case directive in module . +"../../rtl/mkOCEDP4B.v" line 6355: Found Parallel Case directive in module . +"../../rtl/mkOCEDP4B.v" line 6372: Found Parallel Case directive in module . +"../../rtl/mkOCEDP4B.v" line 6413: Found Parallel Case directive in module . +"../../rtl/mkOCEDP4B.v" line 6431: Found Parallel Case directive in module . +"../../rtl/mkOCEDP4B.v" line 6448: Found Parallel Case directive in module . +"../../rtl/mkOCEDP4B.v" line 6465: Found Parallel Case directive in module . +"../../rtl/mkOCEDP4B.v" line 6721: Found Parallel Case directive in module . +Module is correct for synthesis. + +Analyzing module in library . +Module is correct for synthesis. + +Analyzing module in library . +Module is correct for synthesis. + +Analyzing module in library . +Module is correct for synthesis. + +Analyzing module in library . +Module is correct for synthesis. + +Analyzing module in library . +Module is correct for synthesis. + +Analyzing module in library . +Module is correct for synthesis. + +Analyzing module in library . +Module is correct for synthesis. + +Analyzing module in library . +Module is correct for synthesis. + +Analyzing module in library . +Module is correct for synthesis. + +Analyzing module in library . +Module is correct for synthesis. + +Analyzing module in library . +"../../rtl/mkOCEDP4B.v" line 3875: Found Parallel Case directive in module . +"../../rtl/mkOCEDP4B.v" line 4246: Found Parallel Case directive in module . +"../../rtl/mkOCEDP4B.v" line 4623: Found Parallel Case directive in module . +"../../rtl/mkOCEDP4B.v" line 5159: Found Parallel Case directive in module . +"../../rtl/mkOCEDP4B.v" line 5352: Found Parallel Case directive in module . +"../../rtl/mkOCEDP4B.v" line 5778: Found Parallel Case directive in module . +"../../rtl/mkOCEDP4B.v" line 5798: Found Parallel Case directive in module . +"../../rtl/mkOCEDP4B.v" line 6045: Found Parallel Case directive in module . +"../../rtl/mkOCEDP4B.v" line 6068: Found Parallel Case directive in module . +"../../rtl/mkOCEDP4B.v" line 6136: Found Parallel Case directive in module . +"../../rtl/mkOCEDP4B.v" line 6154: Found Parallel Case directive in module . +"../../rtl/mkOCEDP4B.v" line 6171: Found Parallel Case directive in module . +"../../rtl/mkOCEDP4B.v" line 6187: Found Parallel Case directive in module . +"../../rtl/mkOCEDP4B.v" line 6227: Found Parallel Case directive in module . +"../../rtl/mkOCEDP4B.v" line 6245: Found Parallel Case directive in module . +"../../rtl/mkOCEDP4B.v" line 6262: Found Parallel Case directive in module . +"../../rtl/mkOCEDP4B.v" line 6279: Found Parallel Case directive in module . +"../../rtl/mkOCEDP4B.v" line 6320: Found Parallel Case directive in module . +"../../rtl/mkOCEDP4B.v" line 6338: Found Parallel Case directive in module . +"../../rtl/mkOCEDP4B.v" line 6355: Found Parallel Case directive in module . +"../../rtl/mkOCEDP4B.v" line 6372: Found Parallel Case directive in module . +"../../rtl/mkOCEDP4B.v" line 6413: Found Parallel Case directive in module . +"../../rtl/mkOCEDP4B.v" line 6431: Found Parallel Case directive in module . +"../../rtl/mkOCEDP4B.v" line 6448: Found Parallel Case directive in module . +"../../rtl/mkOCEDP4B.v" line 6465: Found Parallel Case directive in module . +"../../rtl/mkOCEDP4B.v" line 6721: Found Parallel Case directive in module . +Module is correct for synthesis. + +Analyzing module in library . +"../../rtl/mkQABSMF3.v" line 970: Found Parallel Case directive in module . +"../../rtl/mkQABSMF3.v" line 1044: Found Parallel Case directive in module . +"../../rtl/mkQABSMF3.v" line 1112: Found Parallel Case directive in module . +"../../rtl/mkQABSMF3.v" line 1148: Found Parallel Case directive in module . +"../../rtl/mkQABSMF3.v" line 1277: Found Parallel Case directive in module . +"../../rtl/mkQABSMF3.v" line 1333: Found Parallel Case directive in module . +Module is correct for synthesis. + +Analyzing module in library . +Module is correct for synthesis. + +Analyzing module in library . +Module is correct for synthesis. + +Analyzing module in library . +"../../rtl/mkGMAC.v" line 1044: Found Parallel Case directive in module . +Module is correct for synthesis. + + Set user-defined property "DDR_ALIGNMENT = NONE" for instance in unit . + Set user-defined property "SRTYPE = SYNC" for instance in unit . + Set user-defined property "DDR_ALIGNMENT = NONE" for instance in unit . + Set user-defined property "SRTYPE = SYNC" for instance in unit . + Set user-defined property "DDR_ALIGNMENT = NONE" for instance in unit . + Set user-defined property "SRTYPE = SYNC" for instance in unit . + Set user-defined property "DDR_ALIGNMENT = NONE" for instance in unit . + Set user-defined property "SRTYPE = SYNC" for instance in unit . + Set user-defined property "DDR_ALIGNMENT = NONE" for instance in unit . + Set user-defined property "SRTYPE = SYNC" for instance in unit . + Set user-defined property "DDR_ALIGNMENT = NONE" for instance in unit . + Set user-defined property "SRTYPE = SYNC" for instance in unit . + Set user-defined property "DDR_ALIGNMENT = NONE" for instance in unit . + Set user-defined property "SRTYPE = SYNC" for instance in unit . + Set user-defined property "DDR_ALIGNMENT = NONE" for instance in unit . + Set user-defined property "SRTYPE = SYNC" for instance in unit . + Set user-defined property "DDR_ALIGNMENT = NONE" for instance in unit . + Set user-defined property "SRTYPE = SYNC" for instance in unit . + Set user-defined property "DDR_ALIGNMENT = NONE" for instance in unit . + Set user-defined property "SRTYPE = SYNC" for instance in unit . + Set user-defined property "DDR_ALIGNMENT = NONE" for instance in unit . + Set user-defined property "SRTYPE = SYNC" for instance in unit . +Analyzing module in library . +Module is correct for synthesis. + +Analyzing module in library . +Module is correct for synthesis. + +Analyzing module in library . + Calling function . + Calling function . + Calling function . + Calling function . +Module is correct for synthesis. + +Analyzing module in library . +Module is correct for synthesis. + +Analyzing module in library . +Module is correct for synthesis. + +Analyzing module in library . + Calling function . + Calling function . + Calling function . + Calling function . +Module is correct for synthesis. + +Analyzing module in library . +Module is correct for synthesis. + +Analyzing module in library . + Calling function . + Calling function . + Calling function . + Calling function . +Module is correct for synthesis. + +Analyzing module in library . +Module is correct for synthesis. + +Analyzing module in library . +Module is correct for synthesis. + +Analyzing module in library . +Module is correct for synthesis. + +Analyzing module in library . +Module is correct for synthesis. + +Analyzing module in library . +Module is correct for synthesis. + +Analyzing module in library . +Module is correct for synthesis. + +Analyzing module in library . +"../../rtl/mkGbeWrk.v" line 409: Found Parallel Case directive in module . +"../../rtl/mkGbeWrk.v" line 577: Found Parallel Case directive in module . +"../../rtl/mkGbeWrk.v" line 601: Found Parallel Case directive in module . +Module is correct for synthesis. + +Analyzing module in library . +Module is correct for synthesis. + +Analyzing module in library . +"../../rtl/mkIQADCWorker.v" line 1883: Found Parallel Case directive in module . +"../../rtl/mkIQADCWorker.v" line 2197: Found Parallel Case directive in module . +"../../rtl/mkIQADCWorker.v" line 2315: Found Parallel Case directive in module . +"../../rtl/mkIQADCWorker.v" line 2496: Found Parallel Case directive in module . +"../../rtl/mkIQADCWorker.v" line 2746: Found Parallel Case directive in module . +"../../rtl/mkIQADCWorker.v" line 2770: Found Parallel Case directive in module . +"../../rtl/mkIQADCWorker.v" line 2855: Found Parallel Case directive in module . +"../../rtl/mkIQADCWorker.v" line 2878: Found Parallel Case directive in module . +"../../rtl/mkIQADCWorker.v" line 2954: Found Parallel Case directive in module . +Module is correct for synthesis. + +Analyzing module in library . +INFO:Xst:1432 - Contents of array may be accessed with a negative index, causing simulation mismatch. +Module is correct for synthesis. + +Analyzing module in library . +Module is correct for synthesis. + +Analyzing module in library . +Module is correct for synthesis. + +Analyzing module in library . +Module is correct for synthesis. + +Analyzing module in library . +Module is correct for synthesis. + +Analyzing module in library . +Module is correct for synthesis. + +Analyzing module in library . +Module is correct for synthesis. + +Analyzing module in library . +Module is correct for synthesis. + +Analyzing module in library . +Module is correct for synthesis. + +Analyzing module in library . +Module is correct for synthesis. + +Analyzing module in library . +"../../rtl/mkPWrk_n210.v" line 802: Found Parallel Case directive in module . +"../../rtl/mkPWrk_n210.v" line 1120: Found Parallel Case directive in module . +"../../rtl/mkPWrk_n210.v" line 1144: Found Parallel Case directive in module . +Module is correct for synthesis. + +Analyzing module in library . +Module is correct for synthesis. + +Analyzing module in library . +Module is correct for synthesis. + +Analyzing module in library . +Module is correct for synthesis. + +Analyzing module in library . +Module is correct for synthesis. + +Analyzing module in library . +Module is correct for synthesis. + +Analyzing module in library . +"../../rtl/mkSMAdapter4B.v" line 1530: Found Parallel Case directive in module . +"../../rtl/mkSMAdapter4B.v" line 1834: Found Parallel Case directive in module . +"../../rtl/mkSMAdapter4B.v" line 1933: Found Parallel Case directive in module . +"../../rtl/mkSMAdapter4B.v" line 2040: Found Parallel Case directive in module . +"../../rtl/mkSMAdapter4B.v" line 2064: Found Parallel Case directive in module . +"../../rtl/mkSMAdapter4B.v" line 2108: Found Parallel Case directive in module . +"../../rtl/mkSMAdapter4B.v" line 2128: Found Parallel Case directive in module . +"../../rtl/mkSMAdapter4B.v" line 2166: Found Parallel Case directive in module . +"../../rtl/mkSMAdapter4B.v" line 2185: Found Parallel Case directive in module . +"../../rtl/mkSMAdapter4B.v" line 2221: Found Parallel Case directive in module . +"../../rtl/mkSMAdapter4B.v" line 2241: Found Parallel Case directive in module . +"../../rtl/mkSMAdapter4B.v" line 2347: Found Parallel Case directive in module . +"../../rtl/mkSMAdapter4B.v" line 2370: Found Parallel Case directive in module . +Module is correct for synthesis. + +Analyzing module in library . +Module is correct for synthesis. + +Analyzing module in library . +Module is correct for synthesis. + +Analyzing module in library . +Module is correct for synthesis. + +Analyzing module in library . +"../../rtl/mkSMAdapter4B.v" line 1530: Found Parallel Case directive in module . +"../../rtl/mkSMAdapter4B.v" line 1834: Found Parallel Case directive in module . +"../../rtl/mkSMAdapter4B.v" line 1933: Found Parallel Case directive in module . +"../../rtl/mkSMAdapter4B.v" line 2040: Found Parallel Case directive in module . +"../../rtl/mkSMAdapter4B.v" line 2064: Found Parallel Case directive in module . +"../../rtl/mkSMAdapter4B.v" line 2108: Found Parallel Case directive in module . +"../../rtl/mkSMAdapter4B.v" line 2128: Found Parallel Case directive in module . +"../../rtl/mkSMAdapter4B.v" line 2166: Found Parallel Case directive in module . +"../../rtl/mkSMAdapter4B.v" line 2185: Found Parallel Case directive in module . +"../../rtl/mkSMAdapter4B.v" line 2221: Found Parallel Case directive in module . +"../../rtl/mkSMAdapter4B.v" line 2241: Found Parallel Case directive in module . +"../../rtl/mkSMAdapter4B.v" line 2347: Found Parallel Case directive in module . +"../../rtl/mkSMAdapter4B.v" line 2370: Found Parallel Case directive in module . +Module is correct for synthesis. + + +========================================================================= +* HDL Synthesis * +========================================================================= + +Performing bidirectional port resolution... +INFO:Xst:2679 - Register in unit has a constant value of 0000 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 10 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 10 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 10 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 10 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 10 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 10 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 10 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 10 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 10 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 10 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 10 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 10 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 10 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 10 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 10 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 000 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 000 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 000 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 000 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 000 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 000 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 000 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 000 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 000 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 000 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 000 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 000 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 000 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 000 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 000 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 01000000000000000000000000000000000000000000000000 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 00000000000000000000000000000000000000000000000000 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 00000000 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0000000000000000000000000000 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0000000000000000000000000000 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 00000000000000000000000000000101010111100110001110 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 00000000 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0000000000000000 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 00000000000000000000000000000000 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 00000000000000000000000000000000 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 00000 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 1 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 1 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 00000001 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0000010000000 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 1000000000000 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 00010010001101000101011001111000 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 1 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of XXXXXXXXXX during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of XXXXXXXXXX during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of XXXXX during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of XXXXXXXXXXXXXXXX during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of X during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of XXXXXXXXXXXXXXXXX during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of XXXXXXXXXXXXXXXXX during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of XXXXXXXXXXXXXXXX during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of XXXXXXXX during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0000000000000000000000000000000000000000000000000000000000000000000 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0001001000110100 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 1 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 00000000000000000000000000000000 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 00000000000000000000000000000000 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 00000000000000000000000000000000 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 00000000000000000000000000000000 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of XXXXXXXXXXXXXXXXX during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of XXXXXXXXXX during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of XXXXXXXXXXXXXXXX during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 000000000000 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0000000000000000000000000000000000000000000000000000000000000000 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0000000000000000000000000000000000000000000000000000000000000000 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 00000000000000000000000000000000 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 00000000000000000000000000000000 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 00000 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 1 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 1 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 00000001 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0000010000000 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 1000000000000 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0000 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 00010010001101000101011001111000 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 1 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of XXXXXXXXXX during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of XXXXXXXXXX during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of XXXXX during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of XXXXXXXXXXXXXXXX during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of X during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of XXXXXXXXXXXXXXXXX during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of XXXXXXXXXXXXXXXXX during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of XXXXXXXXXXXXXXXX during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of XXXXXXXXXXXXXXXX during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of XXXXXXXXXXXXXXXX during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of XXXXXXXX during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of XXXXXXXXXXXXXXXX during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of XXXXXXXX during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of XXXXXXXX during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0000000000000000000000000000000000000000000000000000000000000000000 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 000000000000 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0000000000000000000000000000000000000000000000000000000000000000 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0000000000000000000000000000000000000000000000000000000000000000 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 1 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 1 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0000000000000000000000000000000000000000000000000000000000000000000 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 00000000000000000000000000000000 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of XXXXXXXX during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 00000000000000000000000000000000 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 00000000000000000000000000000000 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of XXXXXXXXXXXX during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 00 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 000000000001 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 00000000000000000000000000000000 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 00000000000000000000000000000000 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of XXXXXXXX during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. + +Synthesizing Unit . + Related source file is "../../libsrc/hdl/bsv/SyncResetA.v". +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. + Found 2-bit register for signal . + Summary: + inferred 2 D-type flip-flop(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../rtl/mkLedN210.v". + Found 5-bit 8-to-1 multiplexer for signal . + Found 1-bit register for signal . + Found 32-bit comparator greater for signal . + Found 32-bit up counter for signal . + Found 5-bit register for signal . + Summary: + inferred 1 Counter(s). + inferred 6 D-type flip-flop(s). + inferred 1 Comparator(s). + inferred 5 Multiplexer(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../libsrc/hdl/bsv/SizedFIFO.v". + Found 2x72-bit dual-port RAM for signal . + Found 72-bit register for signal . + Found 72-bit 4-to-1 multiplexer for signal . + Found 1-bit register for signal . + Found 1-bit register for signal >. + Found 1-bit adder for signal >. + Found 1-bit adder for signal >. + Found 1-bit register for signal . + Found 1-bit xor2 for signal created at line 199. + Found 1-bit register for signal . + Found 1-bit xor2 for signal created at line 180. + Found 1-bit register for signal >. + Summary: + inferred 1 RAM(s). + inferred 77 D-type flip-flop(s). + inferred 2 Adder/Subtractor(s). + inferred 72 Multiplexer(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../libsrc/hdl/bsv/SizedFIFO.v". + Found 2x61-bit dual-port RAM for signal . + Found 61-bit register for signal . + Found 61-bit 4-to-1 multiplexer for signal . + Found 1-bit register for signal . + Found 1-bit register for signal >. + Found 1-bit adder for signal >. + Found 1-bit adder for signal >. + Found 1-bit register for signal . + Found 1-bit xor2 for signal created at line 199. + Found 1-bit register for signal . + Found 1-bit xor2 for signal created at line 180. + Found 1-bit register for signal >. + Summary: + inferred 1 RAM(s). + inferred 66 D-type flip-flop(s). + inferred 2 Adder/Subtractor(s). + inferred 61 Multiplexer(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../libsrc/hdl/bsv/FIFO1.v". + Found 33-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 34 D-type flip-flop(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../libsrc/hdl/bsv/FIFO2.v". + Found 59-bit register for signal . + Found 59-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 120 D-type flip-flop(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../libsrc/hdl/bsv/FIFO2.v". + Found 40-bit register for signal . + Found 40-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 82 D-type flip-flop(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../libsrc/hdl/bsv/BRAM1Load.v". +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. + Found 1024x32-bit single-port RAM for signal . + Found 32-bit register for signal . + Summary: + inferred 1 RAM(s). + inferred 32 D-type flip-flop(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../libsrc/hdl/bsv/SizedFIFO.v". + Found 2x32-bit dual-port RAM for signal . + Found 32-bit register for signal . + Found 32-bit 4-to-1 multiplexer for signal . + Found 1-bit register for signal . + Found 1-bit register for signal >. + Found 1-bit adder for signal >. + Found 1-bit adder for signal >. + Found 1-bit register for signal . + Found 1-bit xor2 for signal created at line 199. + Found 1-bit register for signal . + Found 1-bit xor2 for signal created at line 180. + Found 1-bit register for signal >. + Summary: + inferred 1 RAM(s). + inferred 37 D-type flip-flop(s). + inferred 2 Adder/Subtractor(s). + inferred 32 Multiplexer(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../libsrc/hdl/bsv/SyncFIFO.v". +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. + Found 2x64-bit dual-port RAM for signal . + Found 64-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 2-bit comparator not equal for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 2-bit xor2 for signal . + Found 2-bit xor2 for signal . + Found 2-bit register for signal . + Found 2-bit comparator not equal for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 2-bit comparator not equal for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Summary: + inferred 1 RAM(s). + inferred 80 D-type flip-flop(s). + inferred 3 Comparator(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../libsrc/hdl/bsv/FIFO1.v". + Found 34-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 35 D-type flip-flop(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../libsrc/hdl/bsv/SyncHandshake.v". + Found 1-bit xor2 for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit xor2 for signal created at line 69. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 6 D-type flip-flop(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../libsrc/hdl/bsv/SyncResetA.v". +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. + Found 17-bit register for signal . + Summary: + inferred 17 D-type flip-flop(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../libsrc/hdl/bsv/FIFO2.v". + Found 79-bit register for signal . + Found 79-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 160 D-type flip-flop(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../libsrc/hdl/bsv/FIFO2.v". + Found 45-bit register for signal . + Found 45-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 92 D-type flip-flop(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../libsrc/hdl/bsv/FIFO2.v". + Found 48-bit register for signal . + Found 48-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 98 D-type flip-flop(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../libsrc/hdl/bsv/BRAM2.v". +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. + Found 2048x32-bit dual-port RAM for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Summary: + inferred 1 RAM(s). + inferred 64 D-type flip-flop(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../libsrc/hdl/bsv/BRAM2.v". +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. + Found 2048x40-bit dual-port RAM for signal . + Found 40-bit register for signal . + Found 40-bit register for signal . + Summary: + inferred 1 RAM(s). + inferred 80 D-type flip-flop(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../libsrc/hdl/bsv/FIFO2.v". + Found 128-bit register for signal . + Found 128-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 258 D-type flip-flop(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../libsrc/hdl/bsv/FIFO2.v". + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 66 D-type flip-flop(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../libsrc/hdl/bsv/FIFO20.v". + Found 1-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 2 D-type flip-flop(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../libsrc/hdl/bsv/FIFO2.v". + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Found 1-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 4 D-type flip-flop(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../libsrc/hdl/bsv/FIFO2.v". + Found 130-bit register for signal . + Found 130-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 262 D-type flip-flop(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../libsrc/hdl/bsv/FIFO2.v". + Found 139-bit register for signal . + Found 139-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 280 D-type flip-flop(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../libsrc/hdl/bsv/FIFO2.v". + Found 61-bit register for signal . + Found 61-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 124 D-type flip-flop(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../libsrc/hdl/bsv/SizedFIFO.v". + Found 2x38-bit dual-port RAM for signal . + Found 38-bit register for signal . + Found 38-bit 4-to-1 multiplexer for signal . + Found 1-bit register for signal . + Found 1-bit register for signal >. + Found 1-bit adder for signal >. + Found 1-bit adder for signal >. + Found 1-bit register for signal . + Found 1-bit xor2 for signal created at line 199. + Found 1-bit register for signal . + Found 1-bit xor2 for signal created at line 180. + Found 1-bit register for signal >. + Summary: + inferred 1 RAM(s). + inferred 43 D-type flip-flop(s). + inferred 2 Adder/Subtractor(s). + inferred 38 Multiplexer(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../libsrc/hdl/bsv/FIFO2.v". + Found 27-bit register for signal . + Found 27-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 56 D-type flip-flop(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../libsrc/hdl/bsv/FIFO2.v". + Found 17-bit register for signal . + Found 17-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 36 D-type flip-flop(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../libsrc/hdl/bsv/Counter.v". + Found 8-bit register for signal . + Found 8-bit adder for signal created at line 78. + Summary: + inferred 8 D-type flip-flop(s). + inferred 1 Adder/Subtractor(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../libsrc/hdl/bsv/Counter.v". + Found 4-bit register for signal . + Found 4-bit adder for signal created at line 78. + Summary: + inferred 4 D-type flip-flop(s). + inferred 1 Adder/Subtractor(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../libsrc/hdl/bsv/TriState.v". + Found 1-bit tristate buffer for signal >. + Summary: + inferred 1 Tristate(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../libsrc/hdl/bsv/SyncBit.v". + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 3 D-type flip-flop(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../libsrc/hdl/bsv/SyncFIFO.v". +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. + Found 8x40-bit dual-port RAM for signal . + Found 40-bit register for signal . + Found 4-bit register for signal . + Found 5-bit register for signal . + Found 5-bit register for signal . + Found 4-bit comparator not equal for signal . + Found 1-bit register for signal . + Found 4-bit register for signal . + Found 4-bit xor2 for signal . + Found 4-bit xor2 for signal . + Found 4-bit register for signal . + Found 4-bit comparator not equal for signal . + Found 5-bit register for signal . + Found 5-bit register for signal . + Found 4-bit comparator not equal for signal . + Found 1-bit register for signal . + Found 4-bit register for signal . + Summary: + inferred 1 RAM(s). + inferred 68 D-type flip-flop(s). + inferred 3 Comparator(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../libsrc/hdl/bsv/FIFO2.v". + Found 10-bit register for signal . + Found 10-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 22 D-type flip-flop(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../libsrc/hdl/bsv/SyncResetA.v". +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. + Found 8-bit register for signal . + Summary: + inferred 8 D-type flip-flop(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../rtl/mkCRC32.v". + Found 32-bit register for signal . + Found 32-bit xor2 for signal . + Summary: + inferred 32 D-type flip-flop(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../libsrc/hdl/bsv/SyncFIFO.v". +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. + Found 8x10-bit dual-port RAM for signal . + Found 10-bit register for signal . + Found 4-bit register for signal . + Found 5-bit register for signal . + Found 5-bit register for signal . + Found 4-bit comparator not equal for signal . + Found 1-bit register for signal . + Found 4-bit register for signal . + Found 4-bit xor2 for signal . + Found 4-bit xor2 for signal . + Found 4-bit register for signal . + Found 4-bit comparator not equal for signal . + Found 5-bit register for signal . + Found 5-bit register for signal . + Found 4-bit comparator not equal for signal . + Found 1-bit register for signal . + Found 4-bit register for signal . + Summary: + inferred 1 RAM(s). + inferred 38 D-type flip-flop(s). + inferred 3 Comparator(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../libsrc/hdl/bsv/ClockInverter.v". +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../libsrc/hdl/bsv/ResetInverter.v". +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../libsrc/hdl/bsv/SyncFIFO.v". +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. + Found 16x10-bit dual-port RAM for signal . + Found 10-bit register for signal . + Found 5-bit register for signal . + Found 6-bit register for signal . + Found 6-bit register for signal . + Found 5-bit comparator not equal for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 5-bit xor2 for signal . + Found 5-bit xor2 for signal . + Found 5-bit register for signal . + Found 5-bit comparator not equal for signal . + Found 6-bit register for signal . + Found 6-bit register for signal . + Found 5-bit comparator not equal for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Summary: + inferred 1 RAM(s). + inferred 44 D-type flip-flop(s). + inferred 3 Comparator(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../libsrc/hdl/ocpi/arSRLFIFOD.v". + Found 39-bit 16-to-1 multiplexer for signal <$varindex0000> created at line 51. + Found 624-bit register for signal . + Found 1-bit register for signal . + Found 39-bit register for signal . + Found 4-bit updown counter for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . +INFO:Xst:738 - HDL ADVISOR - 624 flip-flops were inferred for signal . You may be trying to describe a RAM in a way that is incompatible with block and distributed RAM resources available on Xilinx devices, or with a specific template that is not supported. Please review the Xilinx resources documentation and the XST user manual for coding guidelines. Taking advantage of RAM resources will lead to improved device usage and reduced synthesis time. + Summary: + inferred 1 Counter(s). + inferred 666 D-type flip-flop(s). + inferred 1 Adder/Subtractor(s). + inferred 39 Multiplexer(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../libsrc/hdl/bsv/BRAM2.v". +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. + Found 1024x39-bit dual-port RAM for signal . + Found 39-bit register for signal . + Found 39-bit register for signal . + Summary: + inferred 1 RAM(s). + inferred 78 D-type flip-flop(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../libsrc/hdl/bsv/ClockDiv.v". + Found 3-bit up counter for signal . + Found 3-bit comparator less for signal created at line 105. + Summary: + inferred 1 Counter(s). + inferred 1 Comparator(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../libsrc/hdl/bsv/ResetEither.v". +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../libsrc/hdl/bsv/SyncReset0.v". +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../libsrc/hdl/bsv/ResetToBool.v". +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../libsrc/hdl/bsv/FIFO2.v". + Found 53-bit register for signal . + Found 53-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 108 D-type flip-flop(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../libsrc/hdl/bsv/SizedFIFO.v". + Found 15x24-bit dual-port RAM for signal . + Found 24-bit register for signal . + Found 1-bit register for signal . + Found 4-bit register for signal . + Found 4-bit adder for signal . + Found 4-bit adder for signal . + Found 1-bit register for signal . + Found 4-bit comparator equal for signal created at line 199. + Found 1-bit register for signal . + Found 4-bit comparator equal for signal created at line 180. + Found 4-bit register for signal . + Summary: + inferred 1 RAM(s). + inferred 35 D-type flip-flop(s). + inferred 2 Adder/Subtractor(s). + inferred 2 Comparator(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../libsrc/hdl/bsv/SizedFIFO.v". + Found 15x8-bit dual-port RAM for signal . + Found 8-bit register for signal . + Found 1-bit register for signal . + Found 4-bit register for signal . + Found 4-bit adder for signal . + Found 4-bit adder for signal . + Found 1-bit register for signal . + Found 4-bit comparator equal for signal created at line 199. + Found 1-bit register for signal . + Found 4-bit comparator equal for signal created at line 180. + Found 4-bit register for signal . + Summary: + inferred 1 RAM(s). + inferred 19 D-type flip-flop(s). + inferred 2 Adder/Subtractor(s). + inferred 2 Comparator(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../libsrc/hdl/bsv/Counter.v". + Found 10-bit register for signal . + Found 10-bit adder for signal created at line 78. + Summary: + inferred 10 D-type flip-flop(s). + inferred 1 Adder/Subtractor(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../libsrc/hdl/bsv/Counter.v". + Found 32-bit register for signal . + Found 32-bit adder for signal created at line 78. + Summary: + inferred 32 D-type flip-flop(s). + inferred 1 Adder/Subtractor(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../libsrc/hdl/bsv/FIFO10.v". + Found 1-bit register for signal . + Summary: + inferred 1 D-type flip-flop(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../libsrc/hdl/bsv/BRAM2.v". +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. + Found 2048x61-bit dual-port RAM for signal . + Found 61-bit register for signal . + Found 61-bit register for signal . + Summary: + inferred 1 RAM(s). + inferred 122 D-type flip-flop(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../libsrc/hdl/bsv/FIFO2.v". + Found 34-bit register for signal . + Found 34-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 70 D-type flip-flop(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../rtl/mkBiasWorker4B.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. + Found finite state machine for signal . + ----------------------------------------------------------------------- + | States | 3 | + | Transitions | 4 | + | Inputs | 1 | + | Outputs | 3 | + | Clock | wciS0_Clk (rising_edge) | + | Clock enable | wsiM_burstKind$EN (positive) | + | Reset | wciS0_MReset_n (negative) | + | Reset type | synchronous | + | Reset State | 00 | + | Encoding | automatic | + | Implementation | LUT | + ----------------------------------------------------------------------- + Found finite state machine for signal . + ----------------------------------------------------------------------- + | States | 3 | + | Transitions | 4 | + | Inputs | 1 | + | Outputs | 3 | + | Clock | wciS0_Clk (rising_edge) | + | Clock enable | wsiS_burstKind$EN (positive) | + | Reset | wciS0_MReset_n (negative) | + | Reset type | synchronous | + | Reset State | 00 | + | Encoding | automatic | + | Implementation | LUT | + ----------------------------------------------------------------------- + Using one-hot encoding for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 2-bit adder for signal . + Found 2-bit subtractor for signal . + Found 2-bit adder for signal . + Found 2-bit subtractor for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 4-bit register for signal . + Found 2-bit register for signal . + Found 2-bit addsub for signal . + Found 1-bit xor2 for signal . + Found 2-bit register for signal . + Found 34-bit register for signal . + Found 34-bit register for signal . + Found 1-bit register for signal . + Found 2-bit comparator greater for signal created at line 572. + Found 1-bit register for signal . + Found 32-bit up counter for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 32-bit up counter for signal . + Found 2-bit register for signal . + Found 61-bit register for signal . + Found 61-bit register for signal . + Found 8-bit register for signal . + Found 1-bit register for signal . + Found 32-bit up counter for signal . + Found 1-bit register for signal . + Found 32-bit up counter for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 32-bit up counter for signal . + Found 2-bit register for signal . + Found 2-bit addsub for signal . + Found 1-bit xor2 for signal . + Found 1-bit register for signal . + Found 8-bit register for signal . + Found 2-bit comparator greater for signal . + Found 32-bit up counter for signal . + Found 1-bit register for signal . + Found 12-bit register for signal . + Found 12-bit adder for signal created at line 1277. + Found 32-bit adder for signal . + Summary: + inferred 2 Finite State Machine(s). + inferred 6 Counter(s). + inferred 314 D-type flip-flop(s). + inferred 8 Adder/Subtractor(s). + inferred 2 Comparator(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../libsrc/hdl/ocpi/clock_n210.v". +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../rtl/mkEDCPAdapter.v". +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. + Using one-hot encoding for signal . + Found 79-bit 4-to-1 multiplexer for signal . + Found 8-bit comparator equal for signal . + Found 8-bit comparator equal for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 48-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 48-bit comparator equal for signal created at line 616. + Found 48-bit comparator equal for signal created at line 616. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 9-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 48-bit register for signal . + Found 16-bit register for signal . + Found 48-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 1-bit register for signal . + Found 45-bit register for signal . + Found 9-bit register for signal . + Found 45-bit 4-to-1 multiplexer for signal . + Found 4-bit register for signal . + Found 4-bit adder for signal created at line 820. + Found 48-bit register for signal . + Summary: + inferred 476 D-type flip-flop(s). + inferred 1 Adder/Subtractor(s). + inferred 4 Comparator(s). + inferred 124 Multiplexer(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../rtl/mkEDDPAdapter.v". +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. + Found finite state machine for signal . + ----------------------------------------------------------------------- + | States | 6 | + | Transitions | 16 | + | Inputs | 3 | + | Outputs | 6 | + | Clock | CLK (rising_edge) | + | Clock enable | edpFsm_state_mkFSMstate$EN (positive) | + | Reset | RST_N (negative) | + | Reset type | synchronous | + | Reset State | 000 | + | Encoding | automatic | + | Implementation | LUT | + ----------------------------------------------------------------------- + Found 16-bit register for signal . + Found 48-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 16-bit register for signal . + Found 4-bit register for signal . + Found 4-bit adder for signal created at line 637. + Found 4-bit comparator lessequal for signal . + Found 1-bit register for signal . + Found 48-bit register for signal . + Summary: + inferred 1 Finite State Machine(s). + inferred 140 D-type flip-flop(s). + inferred 1 Adder/Subtractor(s). + inferred 1 Comparator(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../rtl/mkOCEDP4B.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. + Using one-hot encoding for signal . + Using one-hot encoding for signal . + Using one-hot encoding for signal . + Found 16-bit register for signal . + Found 16-bit subtractor for signal . + Found 16-bit register for signal . + Found 16-bit comparator equal for signal . + Found 1-bit register for signal . + Found 16-bit register for signal . + Found 16-bit subtractor for signal . + Found 16-bit register for signal . + Found 16-bit comparator equal for signal . + Found 16-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 32-bit adder for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit comparator equal for signal . + Found 1-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 1-bit register for signal . + Found 16-bit register for signal . + Found 16-bit up counter for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit up counter for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit comparator equal for signal . + Found 1-bit register for signal . + Found 16-bit up counter for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 1-bit register for signal . + Found 16-bit up counter for signal . + Found 3-bit register for signal . + Found 3-bit adder for signal . + Found 3-bit adder for signal created at line 6980. + Found 3-bit comparator less for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 3-bit adder for signal . + Found 3-bit adder for signal created at line 6986. + Found 3-bit comparator less for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 3-bit adder for signal . + Found 3-bit adder for signal created at line 7002. + Found 3-bit comparator less for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 3-bit adder for signal . + Found 3-bit adder for signal created at line 7008. + Found 3-bit comparator less for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 3-bit adder for signal . + Found 3-bit adder for signal created at line 7020. + Found 3-bit comparator less for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 3-bit adder for signal . + Found 3-bit adder for signal created at line 7034. + Found 3-bit comparator less for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 3-bit adder for signal . + Found 3-bit adder for signal created at line 7040. + Found 3-bit comparator less for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 3-bit adder for signal . + Found 3-bit adder for signal created at line 7046. + Found 3-bit comparator less for signal . + Found 2-bit register for signal . + Found 12-bit subtractor for signal . + Found 1-bit 4-to-1 multiplexer for signal . + Found 1-bit 4-to-1 multiplexer for signal . + Found 1-bit 4-to-1 multiplexer for signal . + Found 1-bit 4-to-1 multiplexer for signal . + Found 8-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 16-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 4-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 129-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 4-bit register for signal . + Found 32-bit up counter for signal . + Found 4-bit register for signal . + Found 4-bit adder for signal created at line 5236. + Found 4-bit comparator lessequal for signal . + Found 4-bit register for signal . + Found 16-bit register for signal . + Found 8-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 8-bit register for signal . + Found 8-bit register for signal . + Found 53-bit register for signal . + Found 12-bit register for signal . + Found 12-bit comparator equal for signal . + Found 12-bit up counter for signal . + Found 12-bit comparator equal for signal created at line 4284. + Found 32-bit 4-to-1 multiplexer for signal . + Found 2-bit up counter for signal . + Found 4-bit register for signal . + Found 32-bit register for signal . + Found 16-bit register for signal . + Found 1-bit register for signal . + Found 4-bit register for signal . + Found 4-bit adder for signal created at line 5484. + Found 4-bit comparator lessequal for signal . + Found 1-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 10-bit register for signal . + Found 10-bit comparator lessequal for signal . + Found 1-bit register for signal . + Found 13-bit register for signal . + Found 13-bit adder for signal . + Found 13-bit adder for signal . + Found 13-bit adder for signal . + Found 10-bit register for signal . + Found 10-bit comparator lessequal for signal . + Found 2-bit adder for signal . + Found 1-bit register for signal . + Found 13-bit register for signal . + Found 13-bit adder for signal . + Found 13-bit adder for signal . + Found 13-bit adder for signal . + Found 10-bit register for signal . + Found 10-bit comparator lessequal for signal . + Found 10-bit comparator lessequal for signal . + Found 10-bit comparator lessequal for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 2-bit adder for signal . + Found 2-bit adder for signal . + Found 2-bit adder for signal . + Found 2-bit adder for signal . + Found 2-bit adder for signal . + Found 2-bit adder for signal . + Found 2-bit adder for signal . + Found 2-bit adder for signal . + Found 32-bit 4-to-1 multiplexer for signal . + Found 1-bit 4-to-1 multiplexer for signal . + Found 1-bit 4-to-1 multiplexer for signal . + Found 32-bit 4-to-1 multiplexer for signal . + Found 1-bit 4-to-1 multiplexer for signal . + Found 1-bit 4-to-1 multiplexer for signal . + Found 32-bit 4-to-1 multiplexer for signal . + Found 1-bit 4-to-1 multiplexer for signal . + Found 1-bit 4-to-1 multiplexer for signal . + Found 32-bit 4-to-1 multiplexer for signal . + Found 1-bit 4-to-1 multiplexer for signal . + Found 1-bit 4-to-1 multiplexer for signal . + Found 1-bit 4-to-1 multiplexer for signal . + Found 32-bit 4-to-1 multiplexer for signal . + Found 1-bit 4-to-1 multiplexer for signal . + Found 1-bit 4-to-1 multiplexer for signal . + Found 16-bit adder for signal created at line 3459. + Found 16-bit adder for signal created at line 3463. + Found 32-bit adder for signal created at line 3479. + Found 32-bit adder for signal created at line 3483. + Found 16-bit adder for signal created at line 3487. + Found 16-bit adder for signal created at line 3506. + Found 16-bit adder for signal created at line 3510. + Found 16-bit adder for signal created at line 3514. + Found 16-bit adder for signal created at line 3518. + Found 16-bit adder for signal created at line 3522. + Found 11-bit 4-to-1 multiplexer for signal . + Found 11-bit 4-to-1 multiplexer for signal . + Found 11-bit adder for signal . + Found 11-bit 4-to-1 multiplexer for signal . + Found 11-bit 4-to-1 multiplexer for signal . + Found 11-bit 4-to-1 multiplexer for signal . + Found 11-bit 4-to-1 multiplexer for signal . + Found 11-bit 4-to-1 multiplexer for signal . + Found 11-bit 4-to-1 multiplexer for signal . + Found 4-bit subtractor for signal . + Found 10-bit subtractor for signal . + Found 4-bit subtractor for signal . + Found 4-bit comparator greatequal for signal created at line 3805. + Found 10-bit subtractor for signal . + Found 10-bit subtractor for signal . + Found 13-bit adder for signal . + Found 13-bit adder for signal . + Found 10-bit subtractor for signal . + Found 10-bit subtractor for signal . + Found 13-bit adder for signal . + Found 13-bit adder for signal . + Found 10-bit subtractor for signal . + Found 10-bit subtractor for signal . + Found 2-bit adder for signal . + Found 2-bit subtractor for signal . + Found 14-bit adder for signal . + Found 2-bit subtractor for signal . + Found 14-bit subtractor for signal . + Found 14-bit subtractor for signal . + Found 32-bit adder for signal . + Found 2-bit adder for signal . + Found 2-bit adder for signal . + Found 2-bit subtractor for signal . + Found 12-bit comparator not equal for signal . + Found 12-bit adder for signal created at line 6922. + Found 32-bit 4-to-1 multiplexer for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 4-bit register for signal . + Found 2-bit register for signal . + Found 2-bit addsub for signal . + Found 1-bit xor2 for signal . + Found 2-bit register for signal . + Found 34-bit register for signal . + Found 34-bit register for signal . + Found 2-bit comparator greater for signal created at line 2365. + Found 14-bit register for signal . + Found 2-bit register for signal . + Found 14-bit register for signal . + Found 14-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 15-bit register for signal . + Found 15-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 129-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 16-bit up counter for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 2-bit addsub for signal . + Found 1-bit xor2 for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 2-bit addsub for signal . + Found 1-bit xor2 for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 2-bit addsub for signal . + Found 1-bit xor2 for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 34-bit register for signal . + Found 34-bit register for signal . + Found 2-bit comparator greater for signal . + Found 32-bit register for signal . + Found 2-bit comparator greater for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 16-bit up counter for signal . + Found 1-bit register for signal . + Found 32-bit adder for signal . + Found 16-bit subtractor for signal . + Found 16-bit adder for signal . + Found 16-bit subtractor for signal . + Found 16-bit adder for signal . + Found 16-bit subtractor for signal . + Found 16-bit adder for signal . + Found 16-bit subtractor for signal . + Found 16-bit adder for signal . + Found 16-bit subtractor for signal . + Found 12-bit adder for signal . + Found 12-bit subtractor for signal . + Summary: + inferred 9 Counter(s). + inferred 1921 D-type flip-flop(s). + inferred 88 Adder/Subtractor(s). + inferred 26 Comparator(s). + inferred 327 Multiplexer(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../rtl/mkOCEDP4B.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. + Using one-hot encoding for signal . + Using one-hot encoding for signal . + Using one-hot encoding for signal . + Found 16-bit register for signal . + Found 16-bit subtractor for signal . + Found 16-bit register for signal . + Found 16-bit comparator equal for signal . + Found 1-bit register for signal . + Found 16-bit register for signal . + Found 16-bit subtractor for signal . + Found 16-bit register for signal . + Found 16-bit comparator equal for signal . + Found 16-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 32-bit adder for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit comparator equal for signal . + Found 1-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 1-bit register for signal . + Found 16-bit register for signal . + Found 16-bit up counter for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit up counter for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit comparator equal for signal . + Found 1-bit register for signal . + Found 16-bit up counter for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 1-bit register for signal . + Found 16-bit up counter for signal . + Found 3-bit register for signal . + Found 3-bit adder for signal . + Found 3-bit adder for signal created at line 6980. + Found 3-bit comparator less for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 3-bit adder for signal . + Found 3-bit adder for signal created at line 6986. + Found 3-bit comparator less for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 3-bit adder for signal . + Found 3-bit adder for signal created at line 7002. + Found 3-bit comparator less for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 3-bit adder for signal . + Found 3-bit adder for signal created at line 7008. + Found 3-bit comparator less for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 3-bit adder for signal . + Found 3-bit adder for signal created at line 7020. + Found 3-bit comparator less for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 3-bit adder for signal . + Found 3-bit adder for signal created at line 7034. + Found 3-bit comparator less for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 3-bit adder for signal . + Found 3-bit adder for signal created at line 7040. + Found 3-bit comparator less for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 3-bit adder for signal . + Found 3-bit adder for signal created at line 7046. + Found 3-bit comparator less for signal . + Found 2-bit register for signal . + Found 12-bit subtractor for signal . + Found 1-bit 4-to-1 multiplexer for signal . + Found 1-bit 4-to-1 multiplexer for signal . + Found 1-bit 4-to-1 multiplexer for signal . + Found 1-bit 4-to-1 multiplexer for signal . + Found 8-bit register for signal . + Found 8-bit register for signal . + Found 16-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 16-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 129-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 4-bit register for signal . + Found 32-bit up counter for signal . + Found 16-bit up counter for signal . + Found 1-bit register for signal . + Found 4-bit register for signal . + Found 4-bit adder for signal created at line 5236. + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 4-bit register for signal . + Found 17-bit register for signal . + Found 17-bit adder for signal . + Found 16-bit register for signal . + Found 8-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 8-bit register for signal . + Found 8-bit register for signal . + Found 1-bit register for signal . + Found 53-bit register for signal . + Found 12-bit register for signal . + Found 12-bit comparator equal for signal . + Found 12-bit up counter for signal . + Found 12-bit comparator equal for signal created at line 4284. + Found 10-bit register for signal . + Found 10-bit comparator lessequal for signal . + Found 32-bit 4-to-1 multiplexer for signal . + Found 2-bit up counter for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 16-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 10-bit register for signal . + Found 10-bit comparator lessequal for signal . + Found 1-bit register for signal . + Found 13-bit register for signal . + Found 13-bit adder for signal . + Found 13-bit adder for signal . + Found 13-bit adder for signal . + Found 10-bit register for signal . + Found 10-bit comparator lessequal for signal . + Found 2-bit adder for signal . + Found 1-bit register for signal . + Found 13-bit register for signal . + Found 13-bit adder for signal . + Found 13-bit adder for signal . + Found 13-bit adder for signal . + Found 10-bit register for signal . + Found 10-bit comparator lessequal for signal . + Found 10-bit comparator lessequal for signal . + Found 10-bit comparator lessequal for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 2-bit adder for signal . + Found 2-bit adder for signal . + Found 2-bit adder for signal . + Found 2-bit adder for signal . + Found 2-bit adder for signal . + Found 2-bit adder for signal . + Found 2-bit adder for signal . + Found 2-bit adder for signal . + Found 32-bit 4-to-1 multiplexer for signal . + Found 1-bit 4-to-1 multiplexer for signal . + Found 1-bit 4-to-1 multiplexer for signal . + Found 32-bit 4-to-1 multiplexer for signal . + Found 1-bit 4-to-1 multiplexer for signal . + Found 1-bit 4-to-1 multiplexer for signal . + Found 32-bit 4-to-1 multiplexer for signal . + Found 1-bit 4-to-1 multiplexer for signal . + Found 1-bit 4-to-1 multiplexer for signal . + Found 32-bit 4-to-1 multiplexer for signal . + Found 1-bit 4-to-1 multiplexer for signal . + Found 1-bit 4-to-1 multiplexer for signal . + Found 1-bit 4-to-1 multiplexer for signal . + Found 32-bit 4-to-1 multiplexer for signal . + Found 1-bit 4-to-1 multiplexer for signal . + Found 1-bit 4-to-1 multiplexer for signal . + Found 16-bit adder for signal created at line 3459. + Found 16-bit adder for signal created at line 3463. + Found 32-bit adder for signal created at line 3479. + Found 32-bit adder for signal created at line 3483. + Found 16-bit adder for signal created at line 3487. + Found 16-bit adder for signal created at line 3506. + Found 16-bit adder for signal created at line 3510. + Found 16-bit adder for signal created at line 3514. + Found 16-bit adder for signal created at line 3518. + Found 16-bit adder for signal created at line 3522. + Found 11-bit 4-to-1 multiplexer for signal . + Found 11-bit 4-to-1 multiplexer for signal . + Found 11-bit adder for signal . + Found 11-bit 4-to-1 multiplexer for signal . + Found 11-bit 4-to-1 multiplexer for signal . + Found 11-bit 4-to-1 multiplexer for signal . + Found 11-bit 4-to-1 multiplexer for signal . + Found 11-bit 4-to-1 multiplexer for signal . + Found 11-bit 4-to-1 multiplexer for signal . + Found 4-bit subtractor for signal . + Found 32-bit adder for signal . + Found 17-bit subtractor for signal . + Found 10-bit subtractor for signal . + Found 10-bit subtractor for signal . + Found 4-bit subtractor for signal . + Found 16-bit adder for signal . + Found 32-bit adder for signal . + Found 10-bit subtractor for signal . + Found 10-bit subtractor for signal . + Found 13-bit adder for signal . + Found 13-bit adder for signal . + Found 10-bit subtractor for signal . + Found 10-bit subtractor for signal . + Found 13-bit adder for signal . + Found 13-bit adder for signal . + Found 10-bit subtractor for signal . + Found 10-bit subtractor for signal . + Found 2-bit adder for signal . + Found 2-bit subtractor for signal . + Found 14-bit adder for signal . + Found 2-bit subtractor for signal . + Found 14-bit subtractor for signal . + Found 14-bit subtractor for signal . + Found 32-bit adder for signal . + Found 2-bit adder for signal . + Found 2-bit adder for signal . + Found 2-bit subtractor for signal . + Found 12-bit comparator not equal for signal . + Found 12-bit adder for signal created at line 6922. + Found 32-bit 4-to-1 multiplexer for signal . + Found 17-bit comparator equal for signal created at line 7230. + Found 13-bit adder for signal . + Found 13-bit comparator lessequal for signal created at line 7238. + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 4-bit register for signal . + Found 2-bit register for signal . + Found 2-bit addsub for signal . + Found 1-bit xor2 for signal . + Found 2-bit register for signal . + Found 34-bit register for signal . + Found 34-bit register for signal . + Found 2-bit comparator greater for signal created at line 2365. + Found 14-bit register for signal . + Found 2-bit register for signal . + Found 14-bit register for signal . + Found 14-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 15-bit register for signal . + Found 15-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 129-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 16-bit up counter for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 2-bit addsub for signal . + Found 1-bit xor2 for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 2-bit addsub for signal . + Found 1-bit xor2 for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 2-bit addsub for signal . + Found 1-bit xor2 for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 34-bit register for signal . + Found 34-bit register for signal . + Found 2-bit comparator greater for signal . + Found 32-bit register for signal . + Found 2-bit comparator greater for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 16-bit up counter for signal . + Found 1-bit register for signal . + Found 16-bit adder for signal . + Found 16-bit subtractor for signal . + Found 16-bit adder for signal . + Found 16-bit subtractor for signal . + Found 16-bit adder for signal . + Found 16-bit subtractor for signal . + Found 16-bit adder for signal . + Found 16-bit subtractor for signal . + Found 12-bit adder for signal . + Found 12-bit subtractor for signal . + Found 17-bit comparator lessequal for signal created at line 7284. + Summary: + inferred 10 Counter(s). + inferred 2136 D-type flip-flop(s). + inferred 92 Adder/Subtractor(s). + inferred 27 Comparator(s). + inferred 327 Multiplexer(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../rtl/mkQABSMF3.v". + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 3-bit adder for signal . + Found 120-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 3-bit adder for signal . + Found 120-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 260 D-type flip-flop(s). + inferred 2 Adder/Subtractor(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../rtl/mkGbeWrk.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. + Using one-hot encoding for signal . + Found 32-bit register for signal . + Found 2-bit adder for signal . + Found 2-bit subtractor for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 4-bit register for signal . + Found 2-bit register for signal . + Found 2-bit addsub for signal . + Found 1-bit xor2 for signal . + Found 2-bit register for signal . + Found 34-bit register for signal . + Found 34-bit register for signal . + Found 2-bit comparator greater for signal created at line 276. + Summary: + inferred 180 D-type flip-flop(s). + inferred 3 Adder/Subtractor(s). + inferred 1 Comparator(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../rtl/mkPWrk_n210.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. + Using one-hot encoding for signal . + Found 87x2-bit ROM for signal . + Found 117x3-bit ROM for signal . + Found 32-bit register for signal . + Found 8-bit down counter for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 8-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 7-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 8-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 48-bit register for signal . + Found 1-bit 117-to-1 multiplexer for signal . + Found 1-bit 87-to-1 multiplexer for signal . + Found 2-bit adder for signal . + Found 2-bit subtractor for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 4-bit register for signal . + Found 2-bit register for signal . + Found 2-bit addsub for signal . + Found 1-bit xor2 for signal . + Found 2-bit register for signal . + Found 34-bit register for signal . + Found 34-bit register for signal . + Found 2-bit comparator greater for signal created at line 519. + Found 32-bit register for signal . + Found 8-bit adder for signal . + Summary: + inferred 2 ROM(s). + inferred 1 Counter(s). + inferred 299 D-type flip-flop(s). + inferred 4 Adder/Subtractor(s). + inferred 1 Comparator(s). + inferred 2 Multiplexer(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../rtl/mkSMAdapter4B.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. + Found finite state machine for signal . + ----------------------------------------------------------------------- + | States | 3 | + | Transitions | 4 | + | Inputs | 1 | + | Outputs | 3 | + | Clock | wciS0_Clk (rising_edge) | + | Clock enable | wsiM_burstKind$EN (positive) | + | Reset | wciS0_MReset_n (negative) | + | Reset type | synchronous | + | Reset State | 00 | + | Encoding | automatic | + | Implementation | LUT | + ----------------------------------------------------------------------- + Using one-hot encoding for signal . + Found 12-bit adder for signal . + Found 24-bit adder for signal . + Found 12-bit comparator greater for signal created at line 1197. + Found 1-bit register for signal . + Found 32-bit up counter for signal . + Found 32-bit comparator not equal for signal created at line 1786. + Found 12-bit register for signal . + Found 14-bit register for signal . + Found 14-bit comparator lessequal for signal created at line 1800. + Found 14-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 14-bit register for signal . + Found 1-bit register for signal . + Found 14-bit register for signal . + Found 1-bit register for signal . + Found 14-bit adder for signal . + Found 3-bit adder for signal created at line 2560. + Found 12-bit adder for signal created at line 1497. + Found 12-bit adder for signal . + Found 14-bit subtractor for signal . + Found 32-bit adder for signal . + Found 14-bit adder for signal . + Found 16-bit subtractor for signal . + Found 2-bit adder for signal . + Found 2-bit subtractor for signal . + Found 2-bit adder for signal . + Found 2-bit subtractor for signal . + Found 2-bit adder for signal . + Found 2-bit subtractor for signal . + Found 2-bit adder for signal . + Found 2-bit subtractor for signal . + Found 2-bit adder for signal . + Found 2-bit subtractor for signal . + Found 12-bit comparator equal for signal created at line 1601. + Found 9-bit register for signal . + Found 1-bit register for signal . + Found 74-bit register for signal . + Found 12-bit register for signal . + Found 12-bit up counter for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 16-bit register for signal . + Found 32-bit up counter for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 4-bit register for signal . + Found 2-bit register for signal . + Found 2-bit addsub for signal . + Found 1-bit xor2 for signal . + Found 2-bit register for signal . + Found 34-bit register for signal . + Found 34-bit register for signal . + Found 2-bit comparator greater for signal created at line 1057. + Found 12-bit comparator not equal for signal created at line 1369. + Found 2-bit register for signal . + Found 38-bit register for signal . + Found 38-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 12-bit adder for signal created at line 2594. + Found 12-bit comparator not equal for signal created at line 2594. + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 32-bit up counter for signal . + Found 32-bit up counter for signal . + Found 32-bit up counter for signal . + Found 32-bit up counter for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 32-bit up counter for signal . + Found 2-bit register for signal . + Found 61-bit register for signal . + Found 61-bit register for signal . + Found 8-bit register for signal . + Found 1-bit register for signal . + Found 32-bit up counter for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 2-bit down counter for signal . + Found 1-bit register for signal . + Found 8-bit register for signal . + Found 2-bit comparator greater for signal . + Found 12-bit adder for signal . + Found 14-bit comparator equal for signal . + Found 6-bit comparator lessequal for signal created at line 2606. + Found 6-bit comparator lessequal for signal created at line 2606. + Found 3-bit adder for signal . + Found 3-bit adder for signal . + Summary: + inferred 1 Finite State Machine(s). + inferred 10 Counter(s). + inferred 790 D-type flip-flop(s). + inferred 25 Adder/Subtractor(s). + inferred 11 Comparator(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../rtl/mkSMAdapter4B.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. + Found finite state machine for signal . + ----------------------------------------------------------------------- + | States | 3 | + | Transitions | 4 | + | Inputs | 1 | + | Outputs | 3 | + | Clock | wciS0_Clk (rising_edge) | + | Clock enable | wsiM_burstKind$EN (positive) | + | Reset | wciS0_MReset_n (negative) | + | Reset type | synchronous | + | Reset State | 00 | + | Encoding | automatic | + | Implementation | LUT | + ----------------------------------------------------------------------- + Found finite state machine for signal . + ----------------------------------------------------------------------- + | States | 3 | + | Transitions | 4 | + | Inputs | 1 | + | Outputs | 3 | + | Clock | wciS0_Clk (rising_edge) | + | Clock enable | wsiS_burstKind$EN (positive) | + | Reset | wciS0_MReset_n (negative) | + | Reset type | synchronous | + | Reset State | 00 | + | Encoding | automatic | + | Implementation | LUT | + ----------------------------------------------------------------------- + Using one-hot encoding for signal . + Found 32-bit register for signal . + Found 32-bit adder for signal . + Found 12-bit adder for signal . + Found 24-bit adder for signal . + Found 12-bit comparator greater for signal created at line 1197. + Found 1-bit register for signal . + Found 32-bit up counter for signal . + Found 32-bit comparator not equal for signal created at line 1786. + Found 12-bit register for signal . + Found 14-bit register for signal . + Found 14-bit comparator lessequal for signal created at line 1800. + Found 14-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 14-bit register for signal . + Found 1-bit register for signal . + Found 14-bit register for signal . + Found 1-bit register for signal . + Found 14-bit adder for signal . + Found 3-bit adder for signal created at line 2560. + Found 12-bit adder for signal created at line 1497. + Found 12-bit adder for signal . + Found 14-bit subtractor for signal . + Found 32-bit adder for signal . + Found 14-bit adder for signal . + Found 16-bit subtractor for signal . + Found 2-bit adder for signal . + Found 2-bit subtractor for signal . + Found 2-bit adder for signal . + Found 2-bit subtractor for signal . + Found 2-bit adder for signal . + Found 2-bit subtractor for signal . + Found 2-bit adder for signal . + Found 2-bit subtractor for signal . + Found 2-bit adder for signal . + Found 2-bit subtractor for signal . + Found 12-bit comparator equal for signal created at line 1601. + Found 9-bit register for signal . + Found 1-bit register for signal . + Found 74-bit register for signal . + Found 12-bit register for signal . + Found 12-bit up counter for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 16-bit register for signal . + Found 32-bit up counter for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 4-bit register for signal . + Found 2-bit register for signal . + Found 2-bit addsub for signal . + Found 1-bit xor2 for signal . + Found 2-bit register for signal . + Found 34-bit register for signal . + Found 34-bit register for signal . + Found 2-bit comparator greater for signal created at line 1057. + Found 12-bit comparator not equal for signal created at line 1369. + Found 2-bit register for signal . + Found 38-bit register for signal . + Found 38-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 12-bit adder for signal created at line 2594. + Found 12-bit comparator not equal for signal created at line 2594. + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 32-bit up counter for signal . + Found 32-bit up counter for signal . + Found 32-bit up counter for signal . + Found 32-bit up counter for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 32-bit up counter for signal . + Found 2-bit register for signal . + Found 61-bit register for signal . + Found 61-bit register for signal . + Found 8-bit register for signal . + Found 1-bit register for signal . + Found 32-bit adder for signal . + Found 1-bit register for signal . + Found 32-bit up counter for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 32-bit up counter for signal . + Found 2-bit register for signal . + Found 2-bit addsub for signal . + Found 1-bit xor2 for signal . + Found 1-bit register for signal . + Found 8-bit register for signal . + Found 2-bit comparator greater for signal . + Found 32-bit up counter for signal . + Found 1-bit register for signal . + Found 12-bit register for signal . + Found 12-bit adder for signal created at line 2496. + Found 12-bit adder for signal . + Found 14-bit comparator equal for signal . + Found 6-bit comparator lessequal for signal created at line 2606. + Found 6-bit comparator lessequal for signal created at line 2606. + Found 3-bit adder for signal . + Found 3-bit adder for signal . + Summary: + inferred 2 Finite State Machine(s). + inferred 11 Counter(s). + inferred 837 D-type flip-flop(s). + inferred 29 Adder/Subtractor(s). + inferred 11 Comparator(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../libsrc/hdl/bsv/SyncRegister.v". + Found 1-bit register for signal >. + Found 1-bit register for signal >. + Summary: + inferred 2 D-type flip-flop(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../libsrc/hdl/bsv/SyncRegister.v". + Found 64-bit register for signal . + Found 64-bit register for signal . + Summary: + inferred 128 D-type flip-flop(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../libsrc/hdl/bsv/SyncRegister.v". + Found 2-bit register for signal . + Found 2-bit register for signal . + Summary: + inferred 4 D-type flip-flop(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../libsrc/hdl/bsv/SyncRegister.v". + Found 28-bit register for signal . + Found 28-bit register for signal . + Summary: + inferred 56 D-type flip-flop(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../libsrc/hdl/bsv/SyncRegister.v". + Found 8-bit register for signal . + Found 8-bit register for signal . + Summary: + inferred 16 D-type flip-flop(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../libsrc/hdl/bsv/MakeResetA.v". + Found 1-bit register for signal . + Summary: + inferred 1 D-type flip-flop(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../rtl/mkGMAC.v". +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. + Found 1-bit register for signal . + Found 12-bit adder for signal created at line 974. + Found 4-bit adder for signal created at line 978. + Found 32-bit comparator equal for signal created at line 984. + Found 12-bit adder for signal created at line 998. + Found 3-bit subtractor for signal . + Found 5-bit subtractor for signal created at line 1003. + Found 12-bit adder for signal created at line 1007. + Found 5-bit adder for signal created at line 1011. + Found 12-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 4-bit comparator greater for signal created at line 1143. + Found 6-bit register for signal . + Found 8-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 48-bit register for signal . + Found 12-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 12-bit register for signal . + Found 12-bit comparator less for signal . + Found 5-bit register for signal . + Found 5-bit comparator less for signal . + Found 1-bit register for signal . + Found 8-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 138 D-type flip-flop(s). + inferred 7 Adder/Subtractor(s). + inferred 4 Comparator(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../libsrc/hdl/bsv/SyncRegister.v". + Found 16-bit register for signal . + Found 16-bit register for signal . + Summary: + inferred 32 D-type flip-flop(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../libsrc/hdl/bsv/SyncRegister.v". + Found 32-bit register for signal . + Found 32-bit register for signal . + Summary: + inferred 64 D-type flip-flop(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../libsrc/hdl/bsv/SyncRegister.v". + Found 128-bit register for signal . + Found 128-bit register for signal . + Summary: + inferred 256 D-type flip-flop(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../rtl/mkOCCP.v". +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal <_281474976710656_MINUS_timeServ_delSecond__q1<27:0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process. + Using one-hot encoding for signal . + Using one-hot encoding for signal . + Using one-hot encoding for signal . + Using one-hot encoding for signal . + Using one-hot encoding for signal . + Using one-hot encoding for signal . + Using one-hot encoding for signal . + Using one-hot encoding for signal . + Using one-hot encoding for signal . + Using one-hot encoding for signal . + Using one-hot encoding for signal . + Using one-hot encoding for signal . + Using one-hot encoding for signal . + Using one-hot encoding for signal . + Using one-hot encoding for signal . + Found 3-bit comparator less for signal created at line 5684. + Found 32-bit register for signal . + Found 65-bit register for signal . + Found 8-bit comparator less for signal . + Found 8-bit comparator less for signal . + Found 24-bit comparator less for signal . + Found 24-bit comparator less for signal . + Found 64-bit register for signal . + Found 64-bit subtractor for signal . + Found 1-bit register for signal . + Found 33-bit 4-to-1 multiplexer for signal . + Found 2-bit comparator not equal for signal created at line 16620. + Found 1-bit 16-to-1 multiplexer for signal . + Found 32-bit adder for signal . + Found 1-bit adder for signal . + Found 1-bit subtractor for signal . + Found 1-bit adder for signal . + Found 1-bit subtractor for signal . + Found 1-bit adder for signal . + Found 1-bit subtractor for signal . + Found 1-bit adder for signal . + Found 1-bit subtractor for signal . + Found 1-bit adder for signal . + Found 1-bit subtractor for signal . + Found 1-bit adder for signal . + Found 1-bit subtractor for signal . + Found 1-bit adder for signal . + Found 1-bit subtractor for signal . + Found 1-bit adder for signal . + Found 1-bit subtractor for signal . + Found 1-bit adder for signal . + Found 1-bit subtractor for signal . + Found 1-bit adder for signal . + Found 1-bit subtractor for signal . + Found 1-bit adder for signal . + Found 1-bit subtractor for signal . + Found 1-bit adder for signal . + Found 1-bit subtractor for signal . + Found 1-bit adder for signal . + Found 1-bit subtractor for signal . + Found 1-bit adder for signal . + Found 1-bit subtractor for signal . + Found 1-bit adder for signal . + Found 1-bit subtractor for signal . + Found 32-bit 4-to-1 multiplexer for signal . + Found 32-bit 4-to-1 multiplexer for signal . + Found 32-bit 4-to-1 multiplexer for signal . + Found 32-bit 4-to-1 multiplexer for signal . + Found 32-bit 4-to-1 multiplexer for signal . + Found 32-bit 4-to-1 multiplexer for signal . + Found 32-bit 4-to-1 multiplexer for signal . + Found 32-bit 4-to-1 multiplexer for signal . + Found 32-bit register for signal . + Found 3-bit register for signal . + Found 3-bit adder for signal . + Found 3-bit adder for signal created at line 17193. + Found 2-bit register for signal . + Found 32-bit 16-to-1 multiplexer for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 8-bit register for signal . + Found 32-bit register for signal . + Found 2-bit register for signal . + Found 50-bit register for signal . + Found 1-bit register for signal . + Found 50-bit register for signal . + Found 64-bit register for signal . + Found 1-bit register for signal . + Found 28-bit comparator less for signal . + Found 28-bit comparator greater for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 28-bit up counter for signal . + Found 28-bit up counter for signal . + Found 28-bit comparator lessequal for signal . + Found 28-bit comparator less for signal . + Found 28-bit register for signal . + Found 28-bit adder for signal created at line 12113. + Found 32-bit register for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 32-bit shifter logical left for signal . + Found 32-bit shifter logical left for signal . + Found 32-bit shifter logical left for signal . + Found 32-bit shifter logical left for signal . + Found 32-bit shifter logical left for signal . + Found 32-bit shifter logical left for signal . + Found 32-bit shifter logical left for signal . + Found 32-bit shifter logical left for signal . + Found 32-bit shifter logical left for signal . + Found 32-bit shifter logical left for signal . + Found 32-bit shifter logical left for signal . + Found 32-bit shifter logical left for signal . + Found 32-bit shifter logical left for signal . + Found 32-bit shifter logical left for signal . + Found 32-bit shifter logical left for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 33-bit register for signal . + Found 33-bit register for signal . + Found 33-bit register for signal . + Found 33-bit register for signal . + Found 33-bit register for signal . + Found 33-bit register for signal . + Found 33-bit register for signal . + Found 33-bit register for signal . + Found 33-bit register for signal . + Found 33-bit register for signal . + Found 33-bit register for signal . + Found 33-bit register for signal . + Found 33-bit register for signal . + Found 33-bit register for signal . + Found 33-bit register for signal . + Found 5-bit register for signal . + Found 5-bit register for signal . + Found 5-bit register for signal . + Found 5-bit register for signal . + Found 5-bit register for signal . + Found 5-bit register for signal . + Found 5-bit register for signal . + Found 5-bit register for signal . + Found 5-bit register for signal . + Found 5-bit register for signal . + Found 5-bit register for signal . + Found 5-bit register for signal . + Found 5-bit register for signal . + Found 5-bit register for signal . + Found 5-bit register for signal . + Found 4-bit register for signal . + Found 4-bit register for signal . + Found 4-bit register for signal . + Found 4-bit register for signal . + Found 4-bit register for signal . + Found 4-bit register for signal . + Found 4-bit register for signal . + Found 4-bit register for signal . + Found 4-bit register for signal . + Found 4-bit register for signal . + Found 4-bit register for signal . + Found 4-bit register for signal . + Found 4-bit register for signal . + Found 4-bit register for signal . + Found 4-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 12-bit register for signal . + Found 12-bit register for signal . + Found 12-bit register for signal . + Found 12-bit register for signal . + Found 12-bit register for signal . + Found 12-bit register for signal . + Found 12-bit register for signal . + Found 12-bit register for signal . + Found 12-bit register for signal . + Found 12-bit register for signal . + Found 12-bit register for signal . + Found 12-bit register for signal . + Found 12-bit register for signal . + Found 12-bit register for signal . + Found 12-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 72-bit register for signal . + Found 1-bit register for signal . + Found 72-bit register for signal . + Found 1-bit register for signal . + Found 72-bit register for signal . + Found 1-bit register for signal . + Found 72-bit register for signal . + Found 1-bit register for signal . + Found 72-bit register for signal . + Found 1-bit register for signal . + Found 72-bit register for signal . + Found 1-bit register for signal . + Found 72-bit register for signal . + Found 1-bit register for signal . + Found 72-bit register for signal . + Found 1-bit register for signal . + Found 72-bit register for signal . + Found 1-bit register for signal . + Found 72-bit register for signal . + Found 1-bit register for signal . + Found 72-bit register for signal . + Found 1-bit register for signal . + Found 72-bit register for signal . + Found 1-bit register for signal . + Found 72-bit register for signal . + Found 1-bit register for signal . + Found 72-bit register for signal . + Found 1-bit register for signal . + Found 72-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 4-bit register for signal . + Found 4-bit register for signal . + Found 4-bit register for signal . + Found 4-bit register for signal . + Found 4-bit register for signal . + Found 4-bit register for signal . + Found 4-bit register for signal . + Found 4-bit register for signal . + Found 4-bit register for signal . + Found 4-bit register for signal . + Found 4-bit register for signal . + Found 4-bit register for signal . + Found 4-bit register for signal . + Found 4-bit register for signal . + Found 4-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 3-bit register for signal . + Found 32-bit register for signal . + Found 32-bit comparator less for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit comparator less for signal . + Found 32-bit register for signal . + Found 32-bit comparator less for signal . + Found 32-bit register for signal . + Found 32-bit comparator less for signal . + Found 32-bit register for signal . + Found 32-bit comparator less for signal . + Found 32-bit register for signal . + Found 32-bit comparator less for signal . + Found 32-bit comparator less for signal . + Found 32-bit register for signal . + Found 32-bit comparator less for signal . + Found 32-bit register for signal . + Found 32-bit comparator less for signal . + Found 32-bit register for signal . + Found 32-bit comparator less for signal . + Found 32-bit register for signal . + Found 32-bit comparator less for signal . + Found 32-bit register for signal . + Found 32-bit comparator less for signal . + Found 32-bit register for signal . + Found 32-bit comparator less for signal . + Found 32-bit register for signal . + Found 32-bit comparator less for signal . + Found 32-bit register for signal . + Found 32-bit comparator less for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 5-bit register for signal . + Found 5-bit register for signal . + Found 5-bit register for signal . + Found 5-bit register for signal . + Found 5-bit register for signal . + Found 5-bit register for signal . + Found 5-bit register for signal . + Found 5-bit register for signal . + Found 5-bit register for signal . + Found 5-bit register for signal . + Found 5-bit register for signal . + Found 5-bit register for signal . + Found 5-bit register for signal . + Found 5-bit register for signal . + Found 5-bit register for signal . + Found 4-bit subtractor for signal . + Found 4-bit subtractor for signal . + Found 4-bit register for signal . + Found 32-bit adder for signal . + Found 32-bit adder for signal . + Found 32-bit adder for signal . + Found 32-bit adder for signal . + Found 32-bit adder for signal . + Found 32-bit adder for signal . + Found 32-bit adder for signal . + Found 32-bit adder for signal . + Found 50-bit adder for signal . + Found 32-bit adder for signal . + Found 32-bit adder for signal . + Found 32-bit adder for signal . + Found 32-bit adder for signal . + Found 32-bit adder for signal . + Found 32-bit adder for signal . + Found 32-bit adder for signal . + Found 32-bit adder for signal . + Summary: + inferred 2 Counter(s). + inferred 3747 D-type flip-flop(s). + inferred 54 Adder/Subtractor(s). + inferred 25 Comparator(s). + inferred 322 Multiplexer(s). + inferred 15 Combinational logic shifter(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../rtl/mkIQADCWorker.v". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. + Found finite state machine for signal . + ----------------------------------------------------------------------- + | States | 11 | + | Transitions | 21 | + | Inputs | 3 | + | Outputs | 11 | + | Clock | wciS0_Clk (rising_edge) | + | Clock enable | adcCore_iseqFsm_state_mkFSMstate$EN (positive) | + | Reset | wciS0_MReset_n (negative) | + | Reset type | synchronous | + | Reset State | 0000 | + | Encoding | automatic | + | Implementation | LUT | + ----------------------------------------------------------------------- + Found finite state machine for signal . + ----------------------------------------------------------------------- + | States | 3 | + | Transitions | 4 | + | Inputs | 1 | + | Outputs | 3 | + | Clock | wciS0_Clk (rising_edge) | + | Clock enable | wsiM_burstKind$EN (positive) | + | Reset | wciS0_MReset_n (negative) | + | Reset type | synchronous | + | Reset State | 00 | + | Encoding | automatic | + | Implementation | LUT | + ----------------------------------------------------------------------- + Using one-hot encoding for signal . + Found 1-bit 18-to-1 multiplexer for signal <$varindex0000> created at line 1860. + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 18-bit register for signal . + Found 18-bit register for signal . + Found 2-bit up counter for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 11-bit comparator not equal for signal created at line 3205. + Found 1-bit xor2 for signal created at line 3205. + Found 1-bit xor2 for signal created at line 3205. + Found 1-bit xor2 for signal created at line 3205. + Found 1-bit xor2 for signal created at line 3205. + Found 1-bit xor2 for signal created at line 3205. + Found 1-bit xor2 for signal created at line 3205. + Found 1-bit xor2 for signal created at line 3205. + Found 1-bit xor2 for signal created at line 3205. + Found 1-bit xor2 for signal created at line 3205. + Found 1-bit xor2 for signal created at line 3205. + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 16-bit register for signal . + Found 16-bit comparator equal for signal . + Found 16-bit subtractor for signal created at line 3229. + Found 14-bit register for signal . + Found 14-bit register for signal . + Found 13-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 1-bit xor2 for signal created at line 3008. + Found 11-bit register for signal . + Found 11-bit adder for signal . + Found 1-bit xor2 for signal . + Found 1-bit xor2 for signal . + Found 1-bit xor2 for signal . + Found 1-bit xor2 for signal . + Found 1-bit xor2 for signal . + Found 1-bit xor2 for signal . + Found 1-bit xor2 for signal . + Found 1-bit xor2 for signal . + Found 1-bit xor2 for signal . + Found 11-bit register for signal . + Found 11-bit register for signal . + Found 1-bit xor11 for signal . + Found 1-bit xor2 for signal . + Found 1-bit xor2 for signal . + Found 1-bit xor2 for signal . + Found 1-bit xor2 for signal . + Found 1-bit xor2 for signal . + Found 1-bit xor2 for signal . + Found 1-bit xor2 for signal . + Found 1-bit xor2 for signal . + Found 1-bit xor2 for signal . + Found 1-bit xor2 for signal . + Found 11-bit register for signal . + Found 11-bit register for signal . + Found 11-bit register for signal . + Found 1-bit xor11 for signal . + Found 1-bit xor2 for signal . + Found 1-bit xor2 for signal . + Found 1-bit xor2 for signal . + Found 1-bit xor2 for signal . + Found 1-bit xor2 for signal . + Found 1-bit xor2 for signal . + Found 1-bit xor2 for signal . + Found 1-bit xor2 for signal . + Found 1-bit xor2 for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 17-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 8-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit xor2 for signal created at line 1510. + Found 18-bit register for signal . + Found 1-bit xor2 for signal created at line 2576. + Found 18-bit register for signal . + Found 18-bit register for signal . + Found 18-bit subtractor for signal . + Found 18-bit register for signal . + Found 1-bit xor2 for signal . + Found 1-bit xor2 for signal . + Found 1-bit xor2 for signal . + Found 1-bit xor2 for signal . + Found 1-bit xor2 for signal . + Found 1-bit xor2 for signal . + Found 1-bit xor2 for signal . + Found 1-bit xor2 for signal . + Found 1-bit xor2 for signal . + Found 1-bit xor2 for signal . + Found 1-bit xor2 for signal . + Found 1-bit xor2 for signal . + Found 1-bit xor2 for signal . + Found 1-bit xor2 for signal . + Found 1-bit xor2 for signal . + Found 1-bit xor2 for signal . + Found 18-bit register for signal . + Found 18-bit register for signal . + Found 1-bit xor18 for signal . + Found 1-bit register for signal . + Found 16-bit up counter for signal . + Found 32-bit register for signal . + Found 32-bit comparator not equal for signal created at line 2633. + Found 32-bit register for signal . + Found 32-bit up counter for signal . + Found 32-bit adder for signal . + Found 32-bit adder for signal . + Found 32-bit adder for signal . + Found 4-bit subtractor for signal . + Found 32-bit adder for signal . + Found 2-bit subtractor for signal . + Found 3-bit subtractor for signal . + Found 16-bit adder for signal created at line 1821. + Found 3-bit subtractor for signal created at line 1842. + Found 4-bit subtractor for signal created at line 1846. + Found 18-bit adder for signal created at line 1864. + Found 2-bit adder for signal . + Found 2-bit subtractor for signal . + Found 2-bit adder for signal . + Found 2-bit subtractor for signal . + Found 11-bit comparator not equal for signal . + Found 1-bit xor2 for signal . + Found 18-bit register for signal . + Found 32-bit register for signal . + Found 8-bit register for signal . + Found 1-bit register for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 4-bit register for signal . + Found 2-bit register for signal . + Found 2-bit addsub for signal . + Found 1-bit xor2 for signal . + Found 2-bit register for signal . + Found 34-bit register for signal . + Found 34-bit register for signal . + Found 2-bit comparator greater for signal created at line 1262. + Found 32-bit up counter for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 32-bit up counter for signal . + Found 2-bit register for signal . + Found 61-bit register for signal . + Found 61-bit register for signal . + Found 8-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 18-bit adder for signal . + Found 18-bit adder for signal . + Found 18-bit adder for signal . + Found 18-bit adder for signal . + Found 18-bit adder for signal . + Found 11-bit shifter logical left for signal . + Found 11-bit shifter logical left for signal . + Found 11-bit adder for signal . + Found 18-bit shifter logical left for signal . + Found 1-bit xor2 for signal created at line 3436. + Summary: + inferred 2 Finite State Machine(s). + inferred 5 Counter(s). + inferred 905 D-type flip-flop(s). + inferred 25 Adder/Subtractor(s). + inferred 5 Comparator(s). + inferred 5 Multiplexer(s). + inferred 3 Combinational logic shifter(s). + inferred 3 Xor(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../rtl/mkQBGMAC.v". +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. + Found 1-bit 4-to-1 multiplexer for signal . + Found 1-bit 4-to-1 multiplexer for signal . + Found 1-bit 4-to-1 multiplexer for signal . + Found 1-bit 4-to-1 multiplexer for signal . + Found 8-bit 4-to-1 multiplexer for signal . + Found 2-bit register for signal . + Found 2-bit adder for signal created at line 554. + Found 30-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 2-bit adder for signal created at line 570. + Found 1-bit register for signal . + Summary: + inferred 36 D-type flip-flop(s). + inferred 2 Adder/Subtractor(s). + inferred 12 Multiplexer(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../rtl/mkGbeQABS.v". +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. + Found 195x2-bit ROM for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit 195-to-1 multiplexer for signal . + Found 1-bit register for signal . + Found 1-bit 195-to-1 multiplexer for signal . + Found 5-bit register for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 16-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 25-bit register for signal . + Found 25-bit subtractor for signal created at line 836. + Found 25-bit comparator lessequal for signal created at line 836. + Found 25-bit comparator greater for signal . + Found 32-bit up counter for signal . + Found 32-bit up counter for signal . + Found 32-bit up counter for signal . + Found 32-bit up counter for signal . + Summary: + inferred 1 ROM(s). + inferred 4 Counter(s). + inferred 107 D-type flip-flop(s). + inferred 1 Adder/Subtractor(s). + inferred 2 Comparator(s). + inferred 2 Multiplexer(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../rtl/mkFTop_n210.v". +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. + Found 32-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 33 D-type flip-flop(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../libsrc/hdl/ocpi/fpgaTop_n210.v". +WARNING:Xst:1306 - Output is never assigned. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:1306 - Output is never assigned. +WARNING:Xst:1306 - Output is never assigned. +WARNING:Xst:1306 - Output is never assigned. +WARNING:Xst:1306 - Output is never assigned. +Unit synthesized. + +INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing. +WARNING:Xst:524 - All outputs of the instance of the block are unconnected in block . + This instance will be removed from the design along with all underlying logic +WARNING:Xst:524 - All outputs of the instance of the block are unconnected in block . + This instance will be removed from the design along with all underlying logic +WARNING:Xst:524 - All outputs of the instance of the block are unconnected in block . + This instance will be removed from the design along with all underlying logic +WARNING:Xst:524 - All outputs of the instance of the block are unconnected in block . + This instance will be removed from the design along with all underlying logic + +========================================================================= +HDL Synthesis Report + +Macro Statistics +# RAMs : 55 + 1024x32-bit single-port RAM : 1 + 1024x39-bit dual-port RAM : 1 + 15x24-bit dual-port RAM : 1 + 15x8-bit dual-port RAM : 1 + 16x10-bit dual-port RAM : 1 + 2048x32-bit dual-port RAM : 8 + 2048x40-bit dual-port RAM : 2 + 2048x61-bit dual-port RAM : 2 + 2x32-bit dual-port RAM : 21 + 2x38-bit dual-port RAM : 2 + 2x61-bit dual-port RAM : 3 + 2x64-bit dual-port RAM : 1 + 2x72-bit dual-port RAM : 8 + 8x10-bit dual-port RAM : 1 + 8x40-bit dual-port RAM : 2 +# ROMs : 3 + 117x3-bit ROM : 1 + 195x2-bit ROM : 1 + 87x2-bit ROM : 1 +# Adders/Subtractors : 411 + 1-bit adder : 83 + 1-bit subtractor : 15 + 10-bit adder : 1 + 10-bit subtractor : 14 + 11-bit adder : 4 + 12-bit adder : 17 + 12-bit subtractor : 4 + 13-bit adder : 21 + 14-bit adder : 6 + 14-bit subtractor : 6 + 16-bit adder : 25 + 16-bit subtractor : 16 + 17-bit adder : 1 + 17-bit subtractor : 1 + 18-bit adder : 6 + 18-bit subtractor : 1 + 2-bit adder : 42 + 2-bit addsub : 14 + 2-bit subtractor : 23 + 24-bit adder : 2 + 25-bit subtractor : 1 + 28-bit adder : 1 + 3-bit adder : 42 + 3-bit subtractor : 3 + 32-bit adder : 35 + 4-bit adder : 12 + 4-bit subtractor : 8 + 5-bit adder : 1 + 5-bit subtractor : 2 + 50-bit adder : 1 + 64-bit subtractor : 1 + 8-bit adder : 2 +# Counters : 51 + 12-bit up counter : 4 + 16-bit up counter : 13 + 2-bit up counter : 3 + 28-bit up counter : 2 + 3-bit up counter : 1 + 32-bit up counter : 26 + 4-bit updown counter : 1 + 8-bit down counter : 1 +# Registers : 1780 + 1-bit register : 861 + 10-bit register : 14 + 11-bit register : 6 + 12-bit register : 24 + 120-bit register : 2 + 128-bit register : 6 + 129-bit register : 3 + 13-bit register : 5 + 130-bit register : 4 + 139-bit register : 4 + 14-bit register : 16 + 15-bit register : 4 + 16-bit register : 62 + 17-bit register : 22 + 18-bit register : 9 + 2-bit register : 86 + 24-bit register : 1 + 25-bit register : 1 + 27-bit register : 2 + 28-bit register : 3 + 3-bit register : 57 + 30-bit register : 1 + 32-bit register : 182 + 33-bit register : 20 + 34-bit register : 39 + 38-bit register : 6 + 39-bit register : 19 + 4-bit register : 81 + 40-bit register : 74 + 45-bit register : 3 + 48-bit register : 12 + 5-bit register : 52 + 50-bit register : 2 + 53-bit register : 3 + 59-bit register : 4 + 6-bit register : 5 + 61-bit register : 19 + 64-bit register : 5 + 65-bit register : 1 + 7-bit register : 1 + 72-bit register : 23 + 74-bit register : 2 + 79-bit register : 2 + 8-bit register : 28 + 9-bit register : 4 +# Comparators : 137 + 10-bit comparator lessequal : 11 + 11-bit comparator not equal : 2 + 12-bit comparator equal : 6 + 12-bit comparator greater : 2 + 12-bit comparator less : 1 + 12-bit comparator not equal : 6 + 13-bit comparator lessequal : 1 + 14-bit comparator equal : 2 + 14-bit comparator lessequal : 2 + 16-bit comparator equal : 9 + 17-bit comparator equal : 1 + 17-bit comparator lessequal : 1 + 2-bit comparator greater : 14 + 2-bit comparator not equal : 4 + 24-bit comparator less : 2 + 25-bit comparator greater : 1 + 25-bit comparator lessequal : 1 + 28-bit comparator greater : 1 + 28-bit comparator less : 1 + 3-bit comparator less : 18 + 32-bit comparator equal : 1 + 32-bit comparator greater : 1 + 32-bit comparator less : 15 + 32-bit comparator not equal : 1 + 4-bit comparator equal : 4 + 4-bit comparator greatequal : 1 + 4-bit comparator greater : 1 + 4-bit comparator lessequal : 4 + 4-bit comparator not equal : 9 + 48-bit comparator equal : 2 + 5-bit comparator less : 1 + 5-bit comparator not equal : 3 + 6-bit comparator lessequal : 4 + 8-bit comparator equal : 2 + 8-bit comparator less : 2 +# Multiplexers : 123 + 1-bit 11-to-1 multiplexer : 2 + 1-bit 117-to-1 multiplexer : 1 + 1-bit 16-to-1 multiplexer : 1 + 1-bit 18-to-1 multiplexer : 1 + 1-bit 195-to-1 multiplexer : 2 + 1-bit 4-to-1 multiplexer : 34 + 1-bit 8-to-1 multiplexer : 2 + 1-bit 87-to-1 multiplexer : 1 + 11-bit 4-to-1 multiplexer : 16 + 32-bit 16-to-1 multiplexer : 1 + 32-bit 4-to-1 multiplexer : 43 + 33-bit 4-to-1 multiplexer : 1 + 38-bit 4-to-1 multiplexer : 2 + 39-bit 16-to-1 multiplexer : 1 + 45-bit 4-to-1 multiplexer : 1 + 5-bit 8-to-1 multiplexer : 1 + 61-bit 4-to-1 multiplexer : 3 + 72-bit 4-to-1 multiplexer : 8 + 79-bit 4-to-1 multiplexer : 1 + 8-bit 4-to-1 multiplexer : 1 +# Logic shifters : 18 + 11-bit shifter logical left : 2 + 18-bit shifter logical left : 1 + 32-bit shifter logical left : 15 +# Tristates : 4 + 1-bit tristate buffer : 4 +# Xors : 186 + 1-bit xor11 : 2 + 1-bit xor18 : 1 + 1-bit xor2 : 171 + 2-bit xor2 : 2 + 32-bit xor2 : 2 + 4-bit xor2 : 6 + 5-bit xor2 : 2 + +========================================================================= + +========================================================================= +* Advanced HDL Synthesis * +========================================================================= + +Analyzing FSM for best encoding. +Optimizing FSM on signal with gray encoding. +------------------- + State | Encoding +------------------- + 00 | 00 + 01 | 01 + 10 | 11 +------------------- +Analyzing FSM for best encoding. +Optimizing FSM on signal with one-hot encoding. +---------------------- + State | Encoding +---------------------- + 0000 | 00000000001 + 0001 | 00000000010 + 0010 | 00000000100 + 0011 | 00000001000 + 0100 | 00000010000 + 0101 | 00000100000 + 0110 | 00001000000 + 0111 | 00010000000 + 1000 | 00100000000 + 1001 | 01000000000 + 1010 | 10000000000 +---------------------- +Analyzing FSM for best encoding. +Optimizing FSM on signal with gray encoding. +------------------- + State | Encoding +------------------- + 00 | 00 + 01 | 01 + 10 | 11 +------------------- +Analyzing FSM for best encoding. +Optimizing FSM on signal with gray encoding. +------------------- + State | Encoding +------------------- + 00 | 00 + 01 | 01 + 10 | 11 +------------------- +Analyzing FSM for best encoding. +Optimizing FSM on signal with gray encoding. +------------------- + State | Encoding +------------------- + 00 | 00 + 01 | 01 + 10 | 11 +------------------- +Analyzing FSM for best encoding. +Optimizing FSM on signal with one-hot encoding. +Optimizing FSM on signal with one-hot encoding. +------------------- + State | Encoding +------------------- + 000 | 000001 + 001 | 000010 + 010 | 000100 + 011 | 001000 + 100 | 010000 + 101 | 100000 +------------------- +Analyzing FSM for best encoding. +Optimizing FSM on signal with gray encoding. +------------------- + State | Encoding +------------------- + 00 | 00 + 01 | 01 + 10 | 11 +------------------- +Analyzing FSM for best encoding. +Optimizing FSM on signal with gray encoding. +------------------- + State | Encoding +------------------- + 00 | 00 + 01 | 01 + 10 | 11 +------------------- +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . +WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . +WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . +WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . +WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . +WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . +WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . +WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . +WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . +WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . +WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . +WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . +WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . +WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . +WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . +WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . +WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . +WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . +WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . +WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . +WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . +WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . +WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . +WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . +WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . +WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . +WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . +WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . +WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . +WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . +WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . +WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . +WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . +WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + +Synthesizing (advanced) Unit . +INFO:Xst:3038 - The RAM appears to be read-only. If that was not your intent please check the write enable description. +INFO:Xst:3226 - The RAM will be implemented as a BLOCK RAM, absorbing the following register(s): + ----------------------------------------------------------------------- + | ram_type | Block | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 1024-word x 32-bit | | + | mode | write-first | | + | clkA | connected to signal | rise | + | enA | connected to signal | high | + | weA | connected to signal | high | + | addrA | connected to signal | | + | diA | connected to signal | | + | doA | connected to signal | | + ----------------------------------------------------------------------- + | optimization | speed | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +INFO:Xst:3226 - The RAM will be implemented as a BLOCK RAM, absorbing the following register(s): + ----------------------------------------------------------------------- + | ram_type | Block | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 2048-word x 32-bit | | + | mode | write-first | | + | clkA | connected to signal | rise | + | enA | connected to signal | high | + | weA | connected to signal | high | + | addrA | connected to signal | | + | diA | connected to signal | | + | doA | connected to signal | | + ----------------------------------------------------------------------- + | optimization | speed | | + ----------------------------------------------------------------------- + | Port B | + | aspect ratio | 2048-word x 32-bit | | + | mode | write-first | | + | clkB | connected to signal | rise | + | enB | connected to signal | high | + | weB | connected to signal | high | + | addrB | connected to signal | | + | diB | connected to signal | | + | doB | connected to signal | | + ----------------------------------------------------------------------- + | optimization | speed | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +INFO:Xst:3226 - The RAM will be implemented as a BLOCK RAM, absorbing the following register(s): + ----------------------------------------------------------------------- + | ram_type | Block | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 2048-word x 40-bit | | + | mode | write-first | | + | clkA | connected to signal | rise | + | enA | connected to signal | high | + | weA | connected to signal | high | + | addrA | connected to signal | | + | diA | connected to signal | | + | doA | connected to signal | | + ----------------------------------------------------------------------- + | optimization | speed | | + ----------------------------------------------------------------------- + | Port B | + | aspect ratio | 2048-word x 40-bit | | + | mode | write-first | | + | clkB | connected to signal | rise | + | enB | connected to signal | high | + | weB | connected to signal | high | + | addrB | connected to signal | | + | diB | connected to signal | | + | doB | connected to signal | | + ----------------------------------------------------------------------- + | optimization | speed | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +INFO:Xst:3226 - The RAM will be implemented as a BLOCK RAM, absorbing the following register(s): + ----------------------------------------------------------------------- + | ram_type | Block | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 1024-word x 39-bit | | + | mode | write-first | | + | clkA | connected to signal | rise | + | weA | connected to signal | high | + | addrA | connected to signal | | + | diA | connected to signal | | + | doA | connected to signal | | + ----------------------------------------------------------------------- + | optimization | speed | | + ----------------------------------------------------------------------- + | Port B | + | aspect ratio | 1024-word x 39-bit | | + | mode | write-first | | + | clkB | connected to signal | rise | + | addrB | connected to signal | | + | doB | connected to signal | | + ----------------------------------------------------------------------- + | optimization | speed | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +INFO:Xst:3226 - The RAM will be implemented as a BLOCK RAM, absorbing the following register(s): + ----------------------------------------------------------------------- + | ram_type | Block | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 2048-word x 61-bit | | + | mode | write-first | | + | clkA | connected to signal | rise | + | enA | connected to signal | high | + | weA | connected to signal | high | + | addrA | connected to signal | | + | diA | connected to signal | | + | doA | connected to signal | | + ----------------------------------------------------------------------- + | optimization | speed | | + ----------------------------------------------------------------------- + | Port B | + | aspect ratio | 2048-word x 61-bit | | + | mode | write-first | | + | clkB | connected to signal | rise | + | enB | connected to signal | high | + | weB | connected to signal | high | + | addrB | connected to signal | | + | diB | connected to signal | | + | doB | connected to signal | | + ----------------------------------------------------------------------- + | optimization | speed | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into accumulator : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into accumulator : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +INFO:Xst:3231 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 2-word x 72-bit | | + | clkA | connected to signal | rise | + | weA | connected to signal <_and0000_0> | high | + | addrA | connected to signal | | + | diA | connected to signal | | + ----------------------------------------------------------------------- + | Port B | + | aspect ratio | 2-word x 72-bit | | + | addrB | connected to signal | | + | doB | connected to internal node | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +INFO:Xst:3231 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 2-word x 61-bit | | + | clkA | connected to signal | rise | + | weA | connected to signal <_and0000_0> | high | + | addrA | connected to signal | | + | diA | connected to signal | | + ----------------------------------------------------------------------- + | Port B | + | aspect ratio | 2-word x 61-bit | | + | addrB | connected to signal | | + | doB | connected to internal node | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +INFO:Xst:3231 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 2-word x 32-bit | | + | clkA | connected to signal | rise | + | weA | connected to signal <_and0000_0> | high | + | addrA | connected to signal | | + | diA | connected to signal | | + ----------------------------------------------------------------------- + | Port B | + | aspect ratio | 2-word x 32-bit | | + | addrB | connected to signal | | + | doB | connected to internal node | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +INFO:Xst:3231 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 2-word x 38-bit | | + | clkA | connected to signal | rise | + | weA | connected to signal <_and0000_0> | high | + | addrA | connected to signal | | + | diA | connected to signal | | + ----------------------------------------------------------------------- + | Port B | + | aspect ratio | 2-word x 38-bit | | + | addrB | connected to signal | | + | doB | connected to internal node | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +INFO:Xst:3231 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 15-word x 24-bit | | + | clkA | connected to signal | rise | + | weA | connected to signal <_and0000_0> | high | + | addrA | connected to signal | | + | diA | connected to signal | | + ----------------------------------------------------------------------- + | Port B | + | aspect ratio | 15-word x 24-bit | | + | addrB | connected to signal | | + | doB | connected to internal node | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +INFO:Xst:3231 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 15-word x 8-bit | | + | clkA | connected to signal | rise | + | weA | connected to signal <_and0000_0> | high | + | addrA | connected to signal | | + | diA | connected to signal | | + ----------------------------------------------------------------------- + | Port B | + | aspect ratio | 15-word x 8-bit | | + | addrB | connected to signal | | + | doB | connected to internal node | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +INFO:Xst:3231 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 2-word x 64-bit | | + | clkA | connected to signal | rise | + | weA | connected to signal | high | + | addrA | connected to signal | | + | diA | connected to signal | | + ----------------------------------------------------------------------- + | Port B | + | aspect ratio | 2-word x 64-bit | | + | addrB | connected to signal | | + | doB | connected to internal node | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +INFO:Xst:3231 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 8-word x 40-bit | | + | clkA | connected to signal | rise | + | weA | connected to signal | high | + | addrA | connected to signal | | + | diA | connected to signal | | + ----------------------------------------------------------------------- + | Port B | + | aspect ratio | 8-word x 40-bit | | + | addrB | connected to signal | | + | doB | connected to internal node | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +INFO:Xst:3231 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 8-word x 10-bit | | + | clkA | connected to signal | rise | + | weA | connected to signal | high | + | addrA | connected to signal | | + | diA | connected to signal | | + ----------------------------------------------------------------------- + | Port B | + | aspect ratio | 8-word x 10-bit | | + | addrB | connected to signal | | + | doB | connected to internal node | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +INFO:Xst:3231 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 16-word x 10-bit | | + | clkA | connected to signal | rise | + | weA | connected to signal | high | + | addrA | connected to signal | | + | diA | connected to signal | | + ----------------------------------------------------------------------- + | Port B | + | aspect ratio | 16-word x 10-bit | | + | addrB | connected to signal | | + | doB | connected to internal node | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into accumulator : 1 register on signal . +The following registers are absorbed into accumulator : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into accumulator : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into accumulator : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . + Found 16-bit dynamic shift register for signal <_varindex0000<0>>. + Found 16-bit dynamic shift register for signal <_varindex0000<1>>. + Found 16-bit dynamic shift register for signal <_varindex0000<2>>. + Found 16-bit dynamic shift register for signal <_varindex0000<3>>. + Found 16-bit dynamic shift register for signal <_varindex0000<4>>. + Found 16-bit dynamic shift register for signal <_varindex0000<5>>. + Found 16-bit dynamic shift register for signal <_varindex0000<6>>. + Found 16-bit dynamic shift register for signal <_varindex0000<7>>. + Found 16-bit dynamic shift register for signal <_varindex0000<8>>. + Found 16-bit dynamic shift register for signal <_varindex0000<9>>. + Found 16-bit dynamic shift register for signal <_varindex0000<10>>. + Found 16-bit dynamic shift register for signal <_varindex0000<11>>. + Found 16-bit dynamic shift register for signal <_varindex0000<12>>. + Found 16-bit dynamic shift register for signal <_varindex0000<13>>. + Found 16-bit dynamic shift register for signal <_varindex0000<14>>. + Found 16-bit dynamic shift register for signal <_varindex0000<15>>. + Found 16-bit dynamic shift register for signal <_varindex0000<16>>. + Found 16-bit dynamic shift register for signal <_varindex0000<17>>. + Found 16-bit dynamic shift register for signal <_varindex0000<18>>. + Found 16-bit dynamic shift register for signal <_varindex0000<19>>. + Found 16-bit dynamic shift register for signal <_varindex0000<20>>. + Found 16-bit dynamic shift register for signal <_varindex0000<21>>. + Found 16-bit dynamic shift register for signal <_varindex0000<22>>. + Found 16-bit dynamic shift register for signal <_varindex0000<23>>. + Found 16-bit dynamic shift register for signal <_varindex0000<24>>. + Found 16-bit dynamic shift register for signal <_varindex0000<25>>. + Found 16-bit dynamic shift register for signal <_varindex0000<26>>. + Found 16-bit dynamic shift register for signal <_varindex0000<27>>. + Found 16-bit dynamic shift register for signal <_varindex0000<28>>. + Found 16-bit dynamic shift register for signal <_varindex0000<29>>. + Found 16-bit dynamic shift register for signal <_varindex0000<30>>. + Found 16-bit dynamic shift register for signal <_varindex0000<31>>. + Found 16-bit dynamic shift register for signal <_varindex0000<32>>. + Found 16-bit dynamic shift register for signal <_varindex0000<33>>. + Found 16-bit dynamic shift register for signal <_varindex0000<34>>. + Found 16-bit dynamic shift register for signal <_varindex0000<35>>. + Found 16-bit dynamic shift register for signal <_varindex0000<36>>. + Found 16-bit dynamic shift register for signal <_varindex0000<37>>. + Found 16-bit dynamic shift register for signal <_varindex0000<38>>. +Unit synthesized (advanced). + +========================================================================= +Advanced HDL Synthesis Report + +Macro Statistics +# FSMs : 8 +# RAMs : 55 + 1024x32-bit single-port block RAM : 1 + 1024x39-bit dual-port block RAM : 1 + 15x24-bit dual-port distributed RAM : 1 + 15x8-bit dual-port distributed RAM : 1 + 16x10-bit dual-port distributed RAM : 1 + 2048x32-bit dual-port block RAM : 8 + 2048x40-bit dual-port block RAM : 2 + 2048x61-bit dual-port block RAM : 2 + 2x32-bit dual-port distributed RAM : 21 + 2x38-bit dual-port distributed RAM : 2 + 2x61-bit dual-port distributed RAM : 3 + 2x64-bit dual-port distributed RAM : 1 + 2x72-bit dual-port distributed RAM : 8 + 8x10-bit dual-port distributed RAM : 1 + 8x40-bit dual-port distributed RAM : 2 +# ROMs : 3 + 117x3-bit ROM : 1 + 195x2-bit ROM : 1 + 87x2-bit ROM : 1 +# Adders/Subtractors : 400 + 1-bit adder : 83 + 1-bit subtractor : 15 + 10-bit adder : 1 + 10-bit subtractor : 14 + 11-bit adder : 3 + 12-bit adder : 15 + 12-bit subtractor : 4 + 13-bit adder : 21 + 14-bit adder : 6 + 14-bit subtractor : 4 + 16-bit adder : 25 + 16-bit subtractor : 16 + 17-bit adder : 1 + 17-bit subtractor : 1 + 18-bit adder : 6 + 18-bit subtractor : 1 + 2-bit adder : 42 + 2-bit addsub : 14 + 2-bit subtractor : 23 + 25-bit subtractor : 1 + 28-bit adder : 1 + 3-bit adder : 38 + 3-bit adder carry in : 2 + 3-bit subtractor : 3 + 32-bit adder : 34 + 4-bit adder : 12 + 4-bit subtractor : 9 + 5-bit adder : 1 + 5-bit subtractor : 1 + 50-bit adder : 1 + 64-bit subtractor : 1 + 8-bit adder : 1 +# Counters : 50 + 12-bit up counter : 4 + 16-bit up counter : 13 + 2-bit up counter : 3 + 28-bit up counter : 1 + 3-bit up counter : 1 + 32-bit up counter : 26 + 4-bit updown counter : 1 + 8-bit down counter : 1 +# Accumulators : 6 + 10-bit up loadable accumulator : 1 + 14-bit down loadable accumulator : 2 + 16-bit up loadable accumulator : 1 + 32-bit up loadable accumulator : 1 + 8-bit up accumulator : 1 +# Registers : 21105 + Flip-Flops : 21105 +# Shift Registers : 39 + 16-bit dynamic shift register : 39 +# Comparators : 137 + 10-bit comparator lessequal : 11 + 11-bit comparator not equal : 2 + 12-bit comparator equal : 6 + 12-bit comparator greater : 2 + 12-bit comparator less : 1 + 12-bit comparator not equal : 6 + 13-bit comparator lessequal : 1 + 14-bit comparator equal : 2 + 14-bit comparator lessequal : 2 + 16-bit comparator equal : 9 + 17-bit comparator equal : 1 + 17-bit comparator lessequal : 1 + 2-bit comparator greater : 14 + 2-bit comparator not equal : 4 + 24-bit comparator less : 2 + 25-bit comparator greater : 1 + 25-bit comparator lessequal : 1 + 28-bit comparator greater : 1 + 28-bit comparator less : 1 + 3-bit comparator less : 18 + 32-bit comparator equal : 1 + 32-bit comparator greater : 1 + 32-bit comparator less : 15 + 32-bit comparator not equal : 1 + 4-bit comparator equal : 4 + 4-bit comparator greatequal : 1 + 4-bit comparator greater : 1 + 4-bit comparator lessequal : 4 + 4-bit comparator not equal : 9 + 48-bit comparator equal : 2 + 5-bit comparator less : 1 + 5-bit comparator not equal : 3 + 6-bit comparator lessequal : 4 + 8-bit comparator equal : 2 + 8-bit comparator less : 2 +# Multiplexers : 122 + 1-bit 11-to-1 multiplexer : 2 + 1-bit 117-to-1 multiplexer : 1 + 1-bit 16-to-1 multiplexer : 1 + 1-bit 18-to-1 multiplexer : 1 + 1-bit 195-to-1 multiplexer : 2 + 1-bit 4-to-1 multiplexer : 34 + 1-bit 8-to-1 multiplexer : 2 + 1-bit 87-to-1 multiplexer : 1 + 11-bit 4-to-1 multiplexer : 16 + 32-bit 16-to-1 multiplexer : 1 + 32-bit 4-to-1 multiplexer : 43 + 33-bit 4-to-1 multiplexer : 1 + 38-bit 4-to-1 multiplexer : 2 + 45-bit 4-to-1 multiplexer : 1 + 5-bit 8-to-1 multiplexer : 1 + 61-bit 4-to-1 multiplexer : 3 + 72-bit 4-to-1 multiplexer : 8 + 79-bit 4-to-1 multiplexer : 1 + 8-bit 4-to-1 multiplexer : 1 +# Logic shifters : 18 + 11-bit shifter logical left : 2 + 18-bit shifter logical left : 1 + 32-bit shifter logical left : 15 +# Xors : 186 + 1-bit xor11 : 2 + 1-bit xor18 : 1 + 1-bit xor2 : 171 + 2-bit xor2 : 2 + 32-bit xor2 : 2 + 4-bit xor2 : 6 + 5-bit xor2 : 2 + +========================================================================= + +========================================================================= +* Low Level Synthesis * +========================================================================= +WARNING:Xst:1989 - Unit : instances , of unit are equivalent, second instance is removed +WARNING:Xst:1989 - Unit : instances , of unit are equivalent, second instance is removed +WARNING:Xst:1989 - Unit : instances , of unit are equivalent, second instance is removed +WARNING:Xst:1989 - Unit : instances , of unit are equivalent, second instance is removed +WARNING:Xst:1989 - Unit : instances , of unit are equivalent, second instance is removed +WARNING:Xst:1989 - Unit : instances , of unit are equivalent, second instance is removed +WARNING:Xst:1989 - Unit : instances , of unit are equivalent, second instance is removed +WARNING:Xst:1989 - Unit : instances , of unit are equivalent, second instance is removed +WARNING:Xst:1989 - Unit : instances , of unit are equivalent, second instance is removed +WARNING:Xst:1989 - Unit : instances , of unit are equivalent, second instance is removed + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. + +Mapping all equations... +Building and optimizing final netlist ... +WARNING:Xst:1290 - Hierarchical block is unconnected in block . + It will be removed from the design. +Found area constraint ratio of 100 (+ 5) on block fpgaTop, actual ratio is 74. +FlipFlop ftop/gbe0/gmac/gmac/txRS_emitFCS_0 has been replicated 1 time(s) +FlipFlop ftop/gbe0/gmac/gmac/txRS_emitFCS_1 has been replicated 1 time(s) + +Final Macro Processing ... + +Processing Unit : + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . +Unit processed. + +Processing Unit : +INFO:Xst:741 - HDL ADVISOR - A 17-bit shift register was found for signal and currently occupies 17 logic cells (8 slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally. +INFO:Xst:741 - HDL ADVISOR - A 17-bit shift register was found for signal and currently occupies 17 logic cells (8 slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally. +INFO:Xst:741 - HDL ADVISOR - A 17-bit shift register was found for signal and currently occupies 17 logic cells (8 slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally. +INFO:Xst:741 - HDL ADVISOR - A 17-bit shift register was found for signal and currently occupies 17 logic cells (8 slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally. +INFO:Xst:741 - HDL ADVISOR - A 17-bit shift register was found for signal and currently occupies 17 logic cells (8 slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally. +INFO:Xst:741 - HDL ADVISOR - A 17-bit shift register was found for signal and currently occupies 17 logic cells (8 slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally. +INFO:Xst:741 - HDL ADVISOR - A 17-bit shift register was found for signal and currently occupies 17 logic cells (8 slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally. +INFO:Xst:741 - HDL ADVISOR - A 17-bit shift register was found for signal and currently occupies 17 logic cells (8 slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally. +INFO:Xst:741 - HDL ADVISOR - A 17-bit shift register was found for signal and currently occupies 17 logic cells (8 slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally. +Unit processed. + +========================================================================= +Final Register Report + +Macro Statistics +# Registers : 17271 + Flip-Flops : 17271 +# Shift Registers : 28 + 2-bit shift register : 28 + +========================================================================= + +========================================================================= +* Partition Report * +========================================================================= + +Partition Implementation Status +------------------------------- + + No Partitions were found in this design. + +------------------------------- + +========================================================================= +* Final Report * +========================================================================= +Final Results +RTL Top Level Output File Name : fpgaTop.ngr +Top Level Output File Name : fpgaTop +Output Format : NGC +Optimization Goal : Speed +Keep Hierarchy : soft + +Design Statistics +# IOs : 146 + +Cell Usage : +# BELS : 39043 +# AND2 : 1 +# GND : 93 +# INV : 1189 +# LUT1 : 2421 +# LUT2 : 5071 +# LUT2_D : 92 +# LUT2_L : 16 +# LUT3 : 7208 +# LUT3_D : 112 +# LUT3_L : 40 +# LUT4 : 12778 +# LUT4_D : 327 +# LUT4_L : 305 +# MULT_AND : 9 +# MUXCY : 4368 +# MUXF5 : 1420 +# MUXF6 : 95 +# MUXF7 : 36 +# OR2 : 1 +# OR3 : 1 +# VCC : 34 +# XORCY : 3426 +# FlipFlops/Latches : 17310 +# FD : 611 +# FDC : 382 +# FDCE : 592 +# FDE : 5564 +# FDP : 17 +# FDPE : 39 +# FDR : 386 +# FDRE : 5858 +# FDRS : 16 +# FDRSE : 76 +# FDS : 2235 +# FDSE : 1523 +# ODDR2 : 11 +# RAMS : 1253 +# RAM16X1D : 1206 +# RAMB16BWER : 47 +# Shift Registers : 31 +# SRL16 : 28 +# SRL16E : 3 +# Clock Buffers : 6 +# BUFG : 4 +# BUFGP : 2 +# IO Buffers : 102 +# IBUF : 40 +# IBUFDS : 1 +# IBUFG : 1 +# IOBUF : 1 +# OBUF : 58 +# OBUFT : 1 +# DCMs : 1 +# DCM_SP : 1 +========================================================================= + +Device utilization summary: +--------------------------- + +Selected Device : 3sd3400afg676-5 + + Number of Slices: 17082 out of 23872 71% + Number of Slice Flip Flops: 17310 out of 47744 36% + Number of 4 input LUTs: 32002 out of 47744 67% + Number used as logic: 29559 + Number used as Shift registers: 31 + Number used as RAMs: 2412 + Number of IOs: 146 + Number of bonded IOBs: 103 out of 469 21% + Number of BRAMs: 47 out of 126 37% + Number of GCLKs: 6 out of 24 25% + Number of DCMs: 1 out of 8 12% + +--------------------------- +Partition Resource Summary: +--------------------------- + + No Partitions were found in this design. + +--------------------------- + + +========================================================================= +TIMING REPORT + +NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE. + FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT + GENERATED AFTER PLACE-and-ROUTE. + +Clock Information: +------------------ +-----------------------------------+------------------------+-------+ +Clock Signal | Clock buffer(FF name) | Load | +-----------------------------------+------------------------+-------+ +sys0_clkp | dcm:CLKDV | 17850 | +gmii_sysclk | IBUFG+BUFG | 562 | +sys0_clkp | dcm:CLK0 | 5 | +ftop/iqadc/adcCore_spiI_cd/cntr_2 | BUFG | 32 | +adc_clkout | BUFGP | 20 | +gmii_rx_clk | BUFGP | 136 | +-----------------------------------+------------------------+-------+ + +Asynchronous Control Signals Information: +---------------------------------------- +-----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------+-------+ +Control Signal | Buffer(FF name) | Load | +-----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------+-------+ +ftop/iqadc/adcCore_statsCC/sRST_inv(ftop/iqadc/adcCore_statsCC/sRST_inv1_INV_0:O) | NONE(ftop/iqadc/adcCore_statsCC/dD_OUT_0) | 256 | +ftop/cp/timeServ_nowInCC/sRST_inv(ftop/cp/timeServ_nowInCC/sRST_inv1_INV_0:O) | NONE(ftop/cp/timeServ_nowInCC/dD_OUT_0) | 128 | +ftop/iqadc/adcCore_iseqFsm_state_mkFSMstate_FSM_Scst_FSM_inv(ftop/iqadc/adcCore_iseqFsm_state_mkFSMstate_FSM_Scst_FSM_inv1_INV_0:O)| NONE(ftop/iqadc/adcCore_sampF_rRdPtr_rsCounter_0) | 71 | +ftop/iqadc/adcCore_sampCC/sRST_inv(ftop/iqadc/adcCore_sampCC/sRST_inv1_INV_0:O) | NONE(ftop/iqadc/adcCore_sampCC/dD_OUT_0) | 56 | +ftop/gbe0/gmac/gmac/txRS_txF/dGDeqPtr1_Acst_inv(ftop/gbe0/gmac/gmac/txRS_txF/dGDeqPtr1_Acst_inv1_INV_0:O) | NONE(ftop/gbe0/gmac/gmac/txRS_txF/dEnqPtr_0) | 46 | +ftop/gbe0/gmac/gmac/rxRS_rxF/dGDeqPtr1_Acst_inv(ftop/gbe0/gmac/gmac/rxRS_rxF/dGDeqPtr1_Acst_inv1_INV_0:O) | NONE(ftop/gbe0/gmac/gmac/rxRS_rxF/dEnqPtr_0) | 38 | +ftop/gbe0/gmac/rxF/dGDeqPtr1_Acst_inv(ftop/gbe0/gmac/rxF/dGDeqPtr1_Acst_inv1_INV_0:O) | NONE(ftop/gbe0/gmac/rxF/dEnqPtr_0) | 38 | +ftop/gbe0/gmac/txF/dGDeqPtr1_Acst_inv(ftop/gbe0/gmac/txF/dGDeqPtr1_Acst_inv1_INV_0:O) | NONE(ftop/gbe0/gmac/txF/dEnqPtr_0) | 38 | +ftop/iqadc/adcCore_sdrRst_OUT_RST_inv(ftop/iqadc/adcCore_sdrRst_OUT_RST_inv1_INV_0:O) | NONE(ftop/iqadc/adcCore_sampF_rRdPtr_rdCounterPre_0) | 33 | +ftop/iqadc/adcCore_maxBurstLengthR/sRST_inv(ftop/iqadc/adcCore_maxBurstLengthR/sRST_inv1_INV_0:O) | NONE(ftop/iqadc/adcCore_maxBurstLengthR/dD_OUT_0) | 32 | +ftop/cp/timeServ_setRefF/dGDeqPtr1_Acst_inv(ftop/cp/timeServ_setRefF/dGDeqPtr1_Acst_inv1_INV_0:O) | NONE(ftop/cp/timeServ_setRefF/dEnqPtr_0) | 22 | +ftop/iqadc/fcAdc_testRst_OUT_RST_inv(ftop/iqadc/fcAdc_testRst_OUT_RST_inv1_INV_0:O) | NONE(ftop/iqadc/fcAdc_grayCounter_rsCounter_0) | 18 | +ftop/cp/wci_mReset_10/rstSync/IN_RST_inv(ftop/cp/wci_mReset_10/rstSync/IN_RST_inv1_INV_0:O) | NONE(ftop/cp/wci_mReset_10/rstSync/reset_hold_0) | 17 | +ftop/cp/wci_mReset_13/rstSync/IN_RST_inv(ftop/cp/wci_mReset_13/rstSync/IN_RST_inv1_INV_0:O) | NONE(ftop/cp/wci_mReset_13/rstSync/reset_hold_0) | 17 | +ftop/cp/wci_mReset_14/rstSync/IN_RST_inv(ftop/cp/wci_mReset_14/rstSync/IN_RST_inv1_INV_0:O) | NONE(ftop/cp/wci_mReset_14/rstSync/reset_hold_0) | 17 | +ftop/cp/wci_mReset_2/rstSync/IN_RST_inv(ftop/cp/wci_mReset_2/rstSync/IN_RST_inv1_INV_0:O) | NONE(ftop/cp/wci_mReset_2/rstSync/reset_hold_0) | 17 | +ftop/cp/wci_mReset_3/rstSync/IN_RST_inv(ftop/cp/wci_mReset_3/rstSync/IN_RST_inv1_INV_0:O) | NONE(ftop/cp/wci_mReset_3/rstSync/reset_hold_0) | 17 | +ftop/cp/wci_mReset_4/rstSync/IN_RST_inv(ftop/cp/wci_mReset_4/rstSync/IN_RST_inv1_INV_0:O) | NONE(ftop/cp/wci_mReset_4/rstSync/reset_hold_0) | 17 | +ftop/cp/wci_mReset_7/rstSync/IN_RST_inv(ftop/cp/wci_mReset_7/rstSync/IN_RST_inv1_INV_0:O) | NONE(ftop/cp/wci_mReset_7/rstSync/reset_hold_0) | 17 | +ftop/cp/wci_mReset_9/rstSync/IN_RST_inv(ftop/cp/wci_mReset_9/rstSync/IN_RST_inv1_INV_0:O) | NONE(ftop/cp/wci_mReset_9/rstSync/reset_hold_0) | 17 | +ftop/gbe0/phyRst/rstSync/IN_RST_inv(ftop/gbe0/phyRst/rstSync/IN_RST_inv1_INV_0:O) | NONE(ftop/gbe0/phyRst/rstSync/reset_hold_0) | 17 | +ftop/cp/timeServ_nowInCC/sync/sRST_inv(ftop/cp/timeServ_nowInCC/sync/sRST_inv1_INV_0:O) | NONE(ftop/cp/timeServ_nowInCC/sync/dLastState) | 6 | +ftop/iqadc/adcCore_acquireD/sync/sRST_inv(ftop/iqadc/adcCore_acquireD/sync/sRST_inv1_INV_0:O) | NONE(ftop/iqadc/adcCore_acquireD/sync/dLastState) | 6 | +ftop/iqadc/adcCore_averageD/sync/sRST_inv(ftop/iqadc/adcCore_averageD/sync/sRST_inv1_INV_0:O) | NONE(ftop/iqadc/adcCore_averageD/sync/dLastState) | 6 | +ftop/iqadc/adcCore_maxBurstLengthR/sync/sRST_inv(ftop/iqadc/adcCore_maxBurstLengthR/sync/sRST_inv1_INV_0:O) | NONE(ftop/iqadc/adcCore_maxBurstLengthR/sync/dLastState)| 6 | +ftop/iqadc/adcCore_operateD/sync/sRST_inv(ftop/iqadc/adcCore_operateD/sync/sRST_inv1_INV_0:O) | NONE(ftop/iqadc/adcCore_operateD/sync/dLastState) | 6 | +ftop/iqadc/adcCore_sampCC/sync/sRST_inv(ftop/iqadc/adcCore_sampCC/sync/sRST_inv1_INV_0:O) | NONE(ftop/iqadc/adcCore_sampCC/sync/dLastState) | 6 | +ftop/iqadc/adcCore_statsCC/sync/sRST_inv(ftop/iqadc/adcCore_statsCC/sync/sRST_inv1_INV_0:O) | NONE(ftop/iqadc/adcCore_statsCC/sync/dLastState) | 6 | +ftop/sma0/wciS0_MReset_n_inv(ftop/sma0/wciS0_MReset_n_inv571_INV_0:O) | NONE(ftop/sma0/wci_wslv_isReset_isInReset) | 4 | +ftop/sma1/wciS0_MReset_n_inv(ftop/sma1/wciS0_MReset_n_inv611_INV_0:O) | NONE(ftop/sma1/wci_wslv_isReset_isInReset) | 4 | +ftop/bias/wciS0_MReset_n_inv(ftop/bias/wciS0_MReset_n_inv321_INV_0:O) | NONE(ftop/bias/wci_wslv_isReset_isInReset) | 3 | +ftop/gbe0/gmac/gmac/rxRS_rxOperateS/sRST_inv(ftop/gbe0/gmac/gmac/rxRS_rxOperateS/sRST_inv1_INV_0:O) | NONE(ftop/gbe0/gmac/gmac/rxRS_rxOperateS/dSyncReg1) | 3 | +ftop/gbe0/gmac/gmac/txRS_txOperateS/sRST_inv(ftop/gbe0/gmac/gmac/txRS_txOperateS/sRST_inv1_INV_0:O) | NONE(ftop/gbe0/gmac/gmac/txRS_txOperateS/dSyncReg1) | 3 | +ftop/gbe0/gmac/rxOper/sRST_inv(ftop/gbe0/gmac/rxOper/sRST_inv1_INV_0:O) | NONE(ftop/gbe0/gmac/rxOper/dSyncReg1) | 3 | +ftop/gbe0/gmac/txOper/sRST_inv(ftop/gbe0/gmac/txOper/sRST_inv1_INV_0:O) | NONE(ftop/gbe0/gmac/txOper/dSyncReg1) | 3 | +ftop/iqadc/adcCore_spiI_cd/RST_inv(ftop/iqadc/adcCore_spiI_cd/RST_inv1_INV_0:O) | NONE(ftop/iqadc/adcCore_spiI_cd/cntr_0) | 3 | +ftop/edp0/RST_N_inv(ftop/edp0/RST_N_inv1241_INV_0:O) | NONE(ftop/edp0/wci_isReset_isInReset) | 2 | +ftop/edp1/RST_N_inv(ftop/edp1/RST_N_inv1381_INV_0:O) | NONE(ftop/edp1/wci_isReset_isInReset) | 2 | +ftop/gbe0/gmac/gmac/rxRS_rxRst/IN_RST_inv(ftop/gbe0/gmac/gmac/rxRS_rxRst/IN_RST_inv1_INV_0:O) | NONE(ftop/gbe0/gmac/gmac/rxRS_rxRst/reset_hold_0) | 2 | +ftop/gbe0/gmac/gmac/txRS_txRst/IN_RST_inv(ftop/gbe0/gmac/gmac/txRS_txRst/IN_RST_inv1_INV_0:O) | NONE(ftop/gbe0/gmac/gmac/txRS_txRst/reset_hold_0) | 2 | +ftop/gmiixo_rst/IN_RST_inv(ftop/gmiixo_rst/IN_RST_inv1_INV_0:O) | NONE(ftop/gmiixo_rst/reset_hold_0) | 2 | +ftop/iqadc/adcCore_acquireD/sRST_inv(ftop/iqadc/adcCore_acquireD/sRST_inv1_INV_0:O) | NONE(ftop/iqadc/adcCore_acquireD/dD_OUT_0) | 2 | +ftop/iqadc/adcCore_averageD/sRST_inv(ftop/iqadc/adcCore_averageD/sRST_inv1_INV_0:O) | NONE(ftop/iqadc/adcCore_averageD/dD_OUT_0) | 2 | +ftop/iqadc/adcCore_operateD/sRST_inv(ftop/iqadc/adcCore_operateD/sRST_inv1_INV_0:O) | NONE(ftop/iqadc/adcCore_operateD/dD_OUT_0) | 2 | +ftop/iqadc/adcCore_sdrRst/IN_RST_inv(ftop/iqadc/adcCore_sdrRst/IN_RST_inv1_INV_0:O) | NONE(ftop/iqadc/adcCore_sdrRst/reset_hold_0) | 2 | +ftop/iqadc/adcCore_spiI_slowReset/IN_RST_inv(ftop/iqadc/adcCore_spiI_slowReset/IN_RST_inv1_INV_0:O) | NONE(ftop/iqadc/adcCore_spiI_slowReset/reset_hold_0) | 2 | +ftop/iqadc/fcAdc_testRst/IN_RST_inv(ftop/iqadc/fcAdc_testRst/IN_RST_inv1_INV_0:O) | NONE(ftop/iqadc/fcAdc_testRst/reset_hold_0) | 2 | +ftop/cp/wci_mReset_10/RST_inv(ftop/cp/wci_mReset_10/RST_inv1_INV_0:O) | NONE(ftop/cp/wci_mReset_10/rst_rnm0) | 1 | +ftop/cp/wci_mReset_13/RST_inv(ftop/cp/wci_mReset_13/RST_inv1_INV_0:O) | NONE(ftop/cp/wci_mReset_13/rst_rnm0) | 1 | +ftop/cp/wci_mReset_14/RST_inv(ftop/cp/wci_mReset_14/RST_inv1_INV_0:O) | NONE(ftop/cp/wci_mReset_14/rst_rnm0) | 1 | +ftop/cp/wci_mReset_2/RST_inv(ftop/cp/wci_mReset_2/RST_inv1_INV_0:O) | NONE(ftop/cp/wci_mReset_2/rst_rnm0) | 1 | +ftop/cp/wci_mReset_3/RST_inv(ftop/cp/wci_mReset_3/RST_inv1_INV_0:O) | NONE(ftop/cp/wci_mReset_3/rst_rnm0) | 1 | +ftop/cp/wci_mReset_4/RST_inv(ftop/cp/wci_mReset_4/RST_inv1_INV_0:O) | NONE(ftop/cp/wci_mReset_4/rst_rnm0) | 1 | +ftop/cp/wci_mReset_7/RST_inv(ftop/cp/wci_mReset_7/RST_inv1_INV_0:O) | NONE(ftop/cp/wci_mReset_7/rst_rnm0) | 1 | +ftop/cp/wci_mReset_9/RST_inv(ftop/cp/wci_mReset_9/RST_inv1_INV_0:O) | NONE(ftop/cp/wci_mReset_9/rst_rnm0) | 1 | +ftop/gbe0/phyRst/RST_inv(ftop/gbe0/phyRst/RST_inv1_INV_0:O) | NONE(ftop/gbe0/phyRst/rst_rnm0) | 1 | +ftop/gbewrk/wciS0_MReset_n_inv(ftop/gbewrk/wciS0_MReset_n_inv1_INV_0:O) | NONE(ftop/gbewrk/wci_wslv_isReset_isInReset) | 1 | +ftop/pwrk/wciS0_MReset_n_inv(ftop/pwrk/wciS0_MReset_n_inv1_INV_0:O) | NONE(ftop/pwrk/wci_wslv_isReset_isInReset) | 1 | +-----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------+-------+ + +Timing Summary: +--------------- +Speed Grade: -5 + + Minimum period: 8.662ns (Maximum Frequency: 115.443MHz) + Minimum input arrival time before clock: 1.378ns + Maximum output required time after clock: 7.658ns + Maximum combinational path delay: No path found + +Timing Detail: +-------------- +All values displayed in nanoseconds (ns) + +========================================================================= +Timing constraint: Default period analysis for Clock 'sys0_clkp' + Clock period: 7.795ns (frequency: 128.279MHz) + Total number of paths / destination ports: 5524012 / 46068 +------------------------------------------------------------------------- +Delay: 15.591ns (Levels of Logic = 47) + Source: ftop/cp/cpReq_37 (FF) + Destination: ftop/cp/cpRespF/data0_reg_0 (FF) + Source Clock: sys0_clkp rising 0.5X + Destination Clock: sys0_clkp rising 0.5X + + Data Path: ftop/cp/cpReq_37 to ftop/cp/cpRespF/data0_reg_0 + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + FDSE:C->Q 38 0.495 1.182 cpReq_37 (cpReq_37) + LUT2_D:I0->O 4 0.561 0.501 WILL_FIRE_RL_cpDispatch_F_F_F_F_T_T_F_cmp_eq00011 (WILL_FIRE_RL_cpDispatch_F_F_F_F_T_T_F_cmp_eq0001) + LUT4:I3->O 17 0.561 0.895 _theResult_____1__h75875<1>1 (_theResult_____1__h75875<1>) + LUT4_D:I3->O 10 0.561 0.773 WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F_cmp_eq00001 (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F_cmp_eq0000) + LUT3:I2->O 19 0.561 0.945 WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T1 (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T) + LUT3:I2->O 1 0.561 0.000 WILL_FIRE_RL_completeWorkerRead_wg_lut<0> (WILL_FIRE_RL_completeWorkerRead_wg_lut<0>) + MUXCY:S->O 1 0.523 0.000 WILL_FIRE_RL_completeWorkerRead_wg_cy<0> (WILL_FIRE_RL_completeWorkerRead_wg_cy<0>) + MUXCY:CI->O 1 0.065 0.000 WILL_FIRE_RL_completeWorkerRead_wg_cy<1> (WILL_FIRE_RL_completeWorkerRead_wg_cy<1>) + MUXCY:CI->O 1 0.065 0.000 WILL_FIRE_RL_completeWorkerRead_wg_cy<2> (WILL_FIRE_RL_completeWorkerRead_wg_cy<2>) + MUXCY:CI->O 1 0.065 0.000 WILL_FIRE_RL_completeWorkerRead_wg_cy<3> (WILL_FIRE_RL_completeWorkerRead_wg_cy<3>) + MUXCY:CI->O 1 0.065 0.000 WILL_FIRE_RL_completeWorkerRead_wg_cy<4> (WILL_FIRE_RL_completeWorkerRead_wg_cy<4>) + MUXCY:CI->O 1 0.065 0.000 WILL_FIRE_RL_completeWorkerRead_wg_cy<5> (WILL_FIRE_RL_completeWorkerRead_wg_cy<5>) + MUXCY:CI->O 1 0.065 0.000 WILL_FIRE_RL_completeWorkerRead_wg_cy<6> (WILL_FIRE_RL_completeWorkerRead_wg_cy<6>) + MUXCY:CI->O 1 0.065 0.000 WILL_FIRE_RL_completeWorkerRead_wg_cy<7> (WILL_FIRE_RL_completeWorkerRead_wg_cy<7>) + MUXCY:CI->O 1 0.065 0.000 WILL_FIRE_RL_completeWorkerRead_wg_cy<8> (WILL_FIRE_RL_completeWorkerRead_wg_cy<8>) + MUXCY:CI->O 1 0.065 0.000 WILL_FIRE_RL_completeWorkerRead_wg_cy<9> (WILL_FIRE_RL_completeWorkerRead_wg_cy<9>) + MUXCY:CI->O 1 0.065 0.000 WILL_FIRE_RL_completeWorkerRead_wg_cy<10> (WILL_FIRE_RL_completeWorkerRead_wg_cy<10>) + MUXCY:CI->O 1 0.065 0.000 WILL_FIRE_RL_completeWorkerRead_wg_cy<11> (WILL_FIRE_RL_completeWorkerRead_wg_cy<11>) + MUXCY:CI->O 1 0.065 0.000 WILL_FIRE_RL_completeWorkerRead_wg_cy<12> (WILL_FIRE_RL_completeWorkerRead_wg_cy<12>) + MUXCY:CI->O 1 0.065 0.000 WILL_FIRE_RL_completeWorkerRead_wg_cy<13> (WILL_FIRE_RL_completeWorkerRead_wg_cy<13>) + MUXCY:CI->O 1 0.065 0.000 WILL_FIRE_RL_completeWorkerRead_wg_cy<14> (WILL_FIRE_RL_completeWorkerRead_wg_cy<14>) + MUXCY:CI->O 1 0.065 0.000 WILL_FIRE_RL_completeWorkerRead_wg_cy<15> (WILL_FIRE_RL_completeWorkerRead_wg_cy<15>) + MUXCY:CI->O 1 0.065 0.000 WILL_FIRE_RL_completeWorkerRead_wg_cy<16> (WILL_FIRE_RL_completeWorkerRead_wg_cy<16>) + MUXCY:CI->O 1 0.065 0.000 WILL_FIRE_RL_completeWorkerRead_wg_cy<17> (WILL_FIRE_RL_completeWorkerRead_wg_cy<17>) + MUXCY:CI->O 1 0.065 0.000 WILL_FIRE_RL_completeWorkerRead_wg_cy<18> (WILL_FIRE_RL_completeWorkerRead_wg_cy<18>) + MUXCY:CI->O 1 0.065 0.000 WILL_FIRE_RL_completeWorkerRead_wg_cy<19> (WILL_FIRE_RL_completeWorkerRead_wg_cy<19>) + MUXCY:CI->O 1 0.065 0.000 WILL_FIRE_RL_completeWorkerRead_wg_cy<20> (WILL_FIRE_RL_completeWorkerRead_wg_cy<20>) + MUXCY:CI->O 1 0.065 0.000 WILL_FIRE_RL_completeWorkerRead_wg_cy<21> (WILL_FIRE_RL_completeWorkerRead_wg_cy<21>) + MUXCY:CI->O 1 0.065 0.000 WILL_FIRE_RL_completeWorkerRead_wg_cy<22> (WILL_FIRE_RL_completeWorkerRead_wg_cy<22>) + MUXCY:CI->O 1 0.065 0.000 WILL_FIRE_RL_completeWorkerRead_wg_cy<23> (WILL_FIRE_RL_completeWorkerRead_wg_cy<23>) + MUXCY:CI->O 1 0.065 0.000 WILL_FIRE_RL_completeWorkerRead_wg_cy<24> (WILL_FIRE_RL_completeWorkerRead_wg_cy<24>) + MUXCY:CI->O 1 0.065 0.000 WILL_FIRE_RL_completeWorkerRead_wg_cy<25> (WILL_FIRE_RL_completeWorkerRead_wg_cy<25>) + MUXCY:CI->O 1 0.065 0.000 WILL_FIRE_RL_completeWorkerRead_wg_cy<26> (WILL_FIRE_RL_completeWorkerRead_wg_cy<26>) + MUXCY:CI->O 1 0.065 0.000 WILL_FIRE_RL_completeWorkerRead_wg_cy<27> (WILL_FIRE_RL_completeWorkerRead_wg_cy<27>) + MUXCY:CI->O 1 0.065 0.000 WILL_FIRE_RL_completeWorkerRead_wg_cy<28> (WILL_FIRE_RL_completeWorkerRead_wg_cy<28>) + MUXCY:CI->O 1 0.065 0.000 WILL_FIRE_RL_completeWorkerRead_wg_cy<29> (WILL_FIRE_RL_completeWorkerRead_wg_cy<29>) + MUXCY:CI->O 1 0.065 0.000 WILL_FIRE_RL_completeWorkerRead_wg_cy<30> (WILL_FIRE_RL_completeWorkerRead_wg_cy<30>) + MUXCY:CI->O 1 0.065 0.000 WILL_FIRE_RL_completeWorkerRead_wg_cy<31> (WILL_FIRE_RL_completeWorkerRead_wg_cy<31>) + MUXCY:CI->O 1 0.065 0.000 WILL_FIRE_RL_completeWorkerRead_wg_cy<32> (WILL_FIRE_RL_completeWorkerRead_wg_cy<32>) + MUXCY:CI->O 1 0.065 0.000 WILL_FIRE_RL_completeWorkerRead_wg_cy<33> (WILL_FIRE_RL_completeWorkerRead_wg_cy<33>) + MUXCY:CI->O 1 0.065 0.000 WILL_FIRE_RL_completeWorkerRead_wg_cy<34> (WILL_FIRE_RL_completeWorkerRead_wg_cy<34>) + MUXCY:CI->O 1 0.065 0.000 WILL_FIRE_RL_completeWorkerRead_wg_cy<35> (WILL_FIRE_RL_completeWorkerRead_wg_cy<35>) + MUXCY:CI->O 10 0.179 0.773 WILL_FIRE_RL_completeWorkerRead_wg_cy<36> (WILL_FIRE_RL_completeWorkerRead) + LUT3:I2->O 7 0.561 0.604 cpRespF_ENQ1 (cpRespF_ENQ) + begin scope: 'cpRespF' + LUT4_D:I3->O 39 0.561 1.077 d0h1 (d0h) + LUT4_L:I3->LO 1 0.561 0.123 data0_reg_or0000<8>_SW0 (N2) + LUT3:I2->O 1 0.561 0.000 data0_reg_8_rstpot (data0_reg_8_rstpot) + FD:D 0.197 data0_reg_8 + ---------------------------------------- + Total 15.591ns (8.718ns logic, 6.873ns route) + (55.9% logic, 44.1% route) + +========================================================================= +Timing constraint: Default period analysis for Clock 'gmii_sysclk' + Clock period: 8.662ns (frequency: 115.443MHz) + Total number of paths / destination ports: 13715 / 1316 +------------------------------------------------------------------------- +Delay: 8.662ns (Levels of Logic = 8) + Source: ftop/gbe0/gmac/gmac/txRS_ifgCnt_value_2 (FF) + Destination: ftop/gbe0/gmac/gmac/txRS_crc/rRemainder_2 (FF) + Source Clock: gmii_sysclk rising + Destination Clock: gmii_sysclk rising + + Data Path: ftop/gbe0/gmac/gmac/txRS_ifgCnt_value_2 to ftop/gbe0/gmac/gmac/txRS_crc/rRemainder_2 + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + FDRE:C->Q 5 0.495 0.646 txRS_ifgCnt_value_2 (txRS_ifgCnt_value_2) + LUT3_D:I0->LO 1 0.561 0.102 txRS_ifgCnt_value_D_IN<2>11 (N83) + LUT4:I3->O 10 0.561 0.752 txRS_txData_D_IN<7>222 (N34) + LUT4_D:I3->O 10 0.561 0.752 MUX_txRS_crc_add_1__SEL_11 (MUX_txRS_crc_add_1__SEL_1) + LUT4:I3->O 8 0.561 0.645 txRS_crc_add_data<1>1 (txRS_crc_add_data<1>) + begin scope: 'txRS_crc' + LUT4_D:I3->O 8 0.561 0.645 IF_IF_rRemainder_XOR_rwAddIn_wget_BIT_0_CONCAT_ETC___d363<26>1 (IF_IF_IF_IF_IF_IF_IF_rRemainder_XOR_rwAddIn_wg_ETC___d368<31>) + LUT4:I3->O 4 0.561 0.501 rRemainder_D_IN<11>11 (N12) + LUT4:I3->O 1 0.561 0.000 rRemainder_D_IN<2>1 (rRemainder_D_IN<2>) + FDSE:D 0.197 rRemainder_2 + ---------------------------------------- + Total 8.662ns (4.619ns logic, 4.043ns route) + (53.3% logic, 46.7% route) + +========================================================================= +Timing constraint: Default period analysis for Clock 'ftop/iqadc/adcCore_spiI_cd/cntr_2' + Clock period: 6.274ns (frequency: 159.394MHz) + Total number of paths / destination ports: 223 / 63 +------------------------------------------------------------------------- +Delay: 6.274ns (Levels of Logic = 8) + Source: ftop/iqadc/adcCore_spiI_slowReset/reset_hold_1 (FF) + Destination: ftop/iqadc/adcCore_spiI_doResp (FF) + Source Clock: ftop/iqadc/adcCore_spiI_cd/cntr_2 rising + Destination Clock: ftop/iqadc/adcCore_spiI_cd/cntr_2 rising + + Data Path: ftop/iqadc/adcCore_spiI_slowReset/reset_hold_1 to ftop/iqadc/adcCore_spiI_doResp + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + FDC:C->Q 3 0.495 0.559 reset_hold_1 (reset_hold_1) + end scope: 'adcCore_spiI_slowReset' + begin scope: 'adcCore_spiI_reqF_dCombinedReset' + LUT2:I0->O 2 0.561 0.380 RST_OUT1 (RST_OUT) + end scope: 'adcCore_spiI_reqF_dCombinedReset' + begin scope: 'adcCore_spiI_reqF_dInReset' + INV:I->O 12 0.562 0.819 VAL1_INV_0 (VAL) + end scope: 'adcCore_spiI_reqF_dInReset' + LUT4_D:I3->O 6 0.561 0.571 adcCore_spiI_doResp_D_IN21 (N225) + LUT4:I3->O 2 0.561 0.446 adcCore_spiI_doResp_D_IN31 (MUX_adcCore_spiI_xmt_d_write_1__SEL_2) + LUT2:I1->O 1 0.562 0.000 adcCore_spiI_doResp_D_IN1 (adcCore_spiI_doResp_D_IN) + FDR:D 0.197 adcCore_spiI_doResp + ---------------------------------------- + Total 6.274ns (3.499ns logic, 2.775ns route) + (55.8% logic, 44.2% route) + +========================================================================= +Timing constraint: Default period analysis for Clock 'adc_clkout' + Clock period: 8.250ns (frequency: 121.219MHz) + Total number of paths / destination ports: 19534 / 19 +------------------------------------------------------------------------- +Delay: 8.250ns (Levels of Logic = 8) + Source: ftop/iqadc/fcAdc_grayCounter_rsCounter_1 (FF) + Destination: ftop/iqadc/fcAdc_grayCounter_rsCounter_0 (FF) + Source Clock: adc_clkout rising + Destination Clock: adc_clkout rising + + Data Path: ftop/iqadc/fcAdc_grayCounter_rsCounter_1 to ftop/iqadc/fcAdc_grayCounter_rsCounter_0 + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + FDC:C->Q 18 0.495 0.910 fcAdc_grayCounter_rsCounter_1 (fcAdc_grayCounter_rsCounter_1) + LUT4_D:I3->O 8 0.561 0.709 Mxor_fcAdc_grayCounter_rsCounter_60_BIT_0_67_XOR_fc_ETC___d1336_xo<0>15 (Mxor_fcAdc_grayCounter_rsCounter_60_BIT_0_67_XOR_fc_ETC___d1336_xo<0>15) + LUT4:I1->O 1 0.562 0.000 Mxor_fcAdc_grayCounter_rsCounter_60_BIT_0_67_XOR_fc_ETC___d1336_xo<0>44_SW1_F (N704) + MUXF5:I0->O 1 0.229 0.380 Mxor_fcAdc_grayCounter_rsCounter_60_BIT_0_67_XOR_fc_ETC___d1336_xo<0>44_SW1 (N2551) + LUT4:I2->O 34 0.561 1.073 IF_fcAdc_grayCounter_rsCounter_60_BIT_0_67_XOR_ETC___d1407<2>24 (IF_fcAdc_grayCounter_rsCounter_60_BIT_0_67_XOR_ETC___d1407<2>) + MUXF5:S->O 1 0.652 0.000 Mmux__varindex0000_9_f5 (Mmux__varindex0000_9_f5) + MUXF6:I0->O 1 0.239 0.000 Mmux__varindex0000_7_f6 (Mmux__varindex0000_7_f6) + MUXF7:I0->O 16 0.239 0.881 Mmux__varindex0000_5_f7 (Mmux__varindex0000_5_f7) + LUT4:I3->O 1 0.561 0.000 MUX_fcAdc_grayCounter_rsCounter_write_1__VAL_1<5> (MUX_fcAdc_grayCounter_rsCounter_write_1__VAL_1<5>) + FDC:D 0.197 fcAdc_grayCounter_rsCounter_5 + ---------------------------------------- + Total 8.250ns (4.296ns logic, 3.954ns route) + (52.1% logic, 47.9% route) + +========================================================================= +Timing constraint: Default period analysis for Clock 'gmii_rx_clk' + Clock period: 6.550ns (frequency: 152.681MHz) + Total number of paths / destination ports: 2319 / 310 +------------------------------------------------------------------------- +Delay: 6.550ns (Levels of Logic = 6) + Source: ftop/gbe0/gmac/gmac/rxRS_rxAPipe_3 (FF) + Destination: ftop/gbe0/gmac/gmac/rxRS_crc/rRemainder_4 (FF) + Source Clock: gmii_rx_clk rising + Destination Clock: gmii_rx_clk rising + + Data Path: ftop/gbe0/gmac/gmac/rxRS_rxAPipe_3 to ftop/gbe0/gmac/gmac/rxRS_crc/rRemainder_4 + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + FDRE:C->Q 4 0.495 0.607 rxRS_rxAPipe_3 (rxRS_rxAPipe_3) + LUT2_L:I0->LO 1 0.561 0.102 MUX_rxRS_rxF_enq_1__SEL_1113 (MUX_rxRS_rxF_enq_1__SEL_1113) + LUT4:I3->O 2 0.561 0.488 MUX_rxRS_rxF_enq_1__SEL_1116 (MUX_rxRS_rxF_enq_1__SEL_1116) + LUT4:I0->O 14 0.561 0.916 WILL_FIRE_RL_rxRS_ingress_noadvance1 (WILL_FIRE_RL_rxRS_ingress_noadvance) + begin scope: 'rxRS_crc' + LUT2_D:I1->O 20 0.562 0.939 rRemainder_D_IN<16>21 (N14) + LUT4:I3->O 1 0.561 0.000 rRemainder_D_IN<22>1 (rRemainder_D_IN<22>) + FDSE:D 0.197 rRemainder_22 + ---------------------------------------- + Total 6.550ns (3.498ns logic, 3.052ns route) + (53.4% logic, 46.6% route) + +========================================================================= +Timing constraint: Default OFFSET IN BEFORE for Clock 'sys0_clkp' + Total number of paths / destination ports: 29 / 29 +------------------------------------------------------------------------- +Offset: 1.378ns (Levels of Logic = 2) + Source: fpga_rstn (PAD) + Destination: ftop/clkN210/rst_fd (FF) + Destination Clock: sys0_clkp rising + + Data Path: fpga_rstn to ftop/clkN210/rst_fd + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + IBUF:I->O 1 0.824 0.357 fpga_rstn_IBUF (fpga_rstn_IBUF) + begin scope: 'ftop' + begin scope: 'clkN210' + FD:D 0.197 rst_fd + ---------------------------------------- + Total 1.378ns (1.021ns logic, 0.357ns route) + (74.1% logic, 25.9% route) + +========================================================================= +Timing constraint: Default OFFSET IN BEFORE for Clock 'ftop/iqadc/adcCore_spiI_cd/cntr_2' + Total number of paths / destination ports: 1 / 1 +------------------------------------------------------------------------- +Offset: 1.378ns (Levels of Logic = 2) + Source: adc_smiso (PAD) + Destination: ftop/iqadc/adcCore_spiI_sdiP (FF) + Destination Clock: ftop/iqadc/adcCore_spiI_cd/cntr_2 falling + + Data Path: adc_smiso to ftop/iqadc/adcCore_spiI_sdiP + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + IBUF:I->O 1 0.824 0.357 adc_smiso_IBUF (adc_smiso_IBUF) + begin scope: 'ftop' + begin scope: 'iqadc' + FD:D 0.197 adcCore_spiI_sdiP + ---------------------------------------- + Total 1.378ns (1.021ns logic, 0.357ns route) + (74.1% logic, 25.9% route) + +========================================================================= +Timing constraint: Default OFFSET IN BEFORE for Clock 'gmii_rx_clk' + Total number of paths / destination ports: 10 / 10 +------------------------------------------------------------------------- +Offset: 1.378ns (Levels of Logic = 3) + Source: gmii_rxd<0> (PAD) + Destination: ftop/gbe0/gmac/gmac/rxRS_rxData_0 (FF) + Destination Clock: gmii_rx_clk rising + + Data Path: gmii_rxd<0> to ftop/gbe0/gmac/gmac/rxRS_rxData_0 + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + IBUF:I->O 1 0.824 0.357 gmii_rxd_0_IBUF (gmii_rxd_0_IBUF) + begin scope: 'ftop' + begin scope: 'gbe0' + begin scope: 'gmac' + begin scope: 'gmac' + FD:D 0.197 rxRS_rxData_0 + ---------------------------------------- + Total 1.378ns (1.021ns logic, 0.357ns route) + (74.1% logic, 25.9% route) + +========================================================================= +Timing constraint: Default OFFSET OUT AFTER for Clock 'sys0_clkp' + Total number of paths / destination ports: 45 / 18 +------------------------------------------------------------------------- +Offset: 7.658ns (Levels of Logic = 5) + Source: ftop/ledLogic/freeCnt_23 (FF) + Destination: led<5> (PAD) + Source Clock: sys0_clkp rising 0.5X + + Data Path: ftop/ledLogic/freeCnt_23 to led<5> + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + FDR:C->Q 6 0.495 0.677 freeCnt_23 (freeCnt_23) + LUT4:I0->O 1 0.561 0.000 led<3>2 (led<3>2) + MUXF5:I0->O 2 0.229 0.382 led<3>_f5 (led<3>) + LUT4:I3->O 1 0.561 0.357 led<4>1 (led<4>) + end scope: 'ledLogic' + end scope: 'ftop' + OBUF:I->O 4.396 led_5_OBUF (led<5>) + ---------------------------------------- + Total 7.658ns (6.242ns logic, 1.416ns route) + (81.5% logic, 18.5% route) + +========================================================================= +Timing constraint: Default OFFSET OUT AFTER for Clock 'gmii_sysclk' + Total number of paths / destination ports: 1 / 1 +------------------------------------------------------------------------- +Offset: 5.248ns (Levels of Logic = 3) + Source: ftop/gbe0/gmac/gmac/gmacLED (FF) + Destination: gmii_led (PAD) + Source Clock: gmii_sysclk rising + + Data Path: ftop/gbe0/gmac/gmac/gmacLED to gmii_led + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + FDRE:C->Q 1 0.495 0.357 gmacLED (gmacLED) + end scope: 'gmac' + end scope: 'gmac' + end scope: 'gbe0' + end scope: 'ftop' + OBUF:I->O 4.396 gmii_led_OBUF (gmii_led) + ---------------------------------------- + Total 5.248ns (4.891ns logic, 0.357ns route) + (93.2% logic, 6.8% route) + +========================================================================= +Timing constraint: Default OFFSET OUT AFTER for Clock 'ftop/iqadc/adcCore_spiI_cd/cntr_2' + Total number of paths / destination ports: 4 / 3 +------------------------------------------------------------------------- +Offset: 6.233ns (Levels of Logic = 3) + Source: ftop/iqadc/adcCore_spiI_cGate (FF) + Destination: adc_sclk (PAD) + Source Clock: ftop/iqadc/adcCore_spiI_cd/cntr_2 rising + + Data Path: ftop/iqadc/adcCore_spiI_cGate to adc_sclk + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + FDR:C->Q 1 0.495 0.423 adcCore_spiI_cGate (adcCore_spiI_cGate) + end scope: 'iqadc' + end scope: 'ftop' + LUT3:I1->O 1 0.562 0.357 adc_sclk1 (adc_sclk_OBUF) + OBUF:I->O 4.396 adc_sclk_OBUF (adc_sclk) + ---------------------------------------- + Total 6.233ns (5.453ns logic, 0.780ns route) + (87.5% logic, 12.5% route) + +========================================================================= + + +Total REAL time to Xst completion: 348.00 secs +Total CPU time to Xst completion: 346.33 secs + +--> + + +Total memory usage is 1493868 kilobytes + +Number of errors : 0 ( 0 filtered) +Number of warnings : 1686 ( 0 filtered) +Number of infos : 232 ( 0 filtered) + diff --git a/logs/n210-20121107_1002/fpgaTop.bld b/logs/n210-20121107_1002/fpgaTop.bld new file mode 100644 index 00000000..b830258a --- /dev/null +++ b/logs/n210-20121107_1002/fpgaTop.bld @@ -0,0 +1,459 @@ +Release 14.3 ngdbuild P.40xd (lin64) +Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. + +Command Line: /opt/Xilinx/14.3/ISE_DS/ISE/bin/lin64/unwrapped/ngdbuild -sd +../../coregen/pcie_4243_axi_k6_gtx_x4_250 -sd ../../coregen/fft_v5_4k_strm_nat +-sd ../../coregen/ddc_4243_4ch_v5 -aul -aut -uc n210.ucf -p xc3sd3400a-fg676-5 +fpgaTop_csi.ngc fpgaTop.ngd + +Reading NGO file "/home/shep/projects/ocpi/build/tmp-n210/fpgaTop_csi.ngc" ... +Gathering constraint information from source properties... +Done. + +Annotating constraints to design from ucf file "n210.ucf" ... +Resolving constraint associations... +Checking Constraint Associations... +INFO:ConstraintSystem:178 - TNM 'SYS0CLK', used in period specification + 'TS_SYS0CLK', was traced into DCM_SP instance dcm. The following new TNM + groups and period specifications were generated at the DCM_SP output(s): + CLK0: + +INFO:ConstraintSystem:178 - TNM 'SYS0CLK', used in period specification + 'TS_SYS0CLK', was traced into DCM_SP instance dcm. The following new TNM + groups and period specifications were generated at the DCM_SP output(s): + CLKDV: + +Done... + +INFO:NgdBuild:1222 - Setting CLKIN_PERIOD attribute associated with DCM instance + dcm to 10.000000 ns based on the period specification ( [n210.ucf(470)]). +Checking expanded design ... +WARNING:NgdBuild:452 - logical net 'N4' has no driver +WARNING:NgdBuild:452 - logical net 'N5' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/bias_wsiM0_MBurstLength<0>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/bias_wsiM0_MBurstLength<10>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/bias_wsiM0_MBurstLength<11>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/bias_wsiM0_MBurstLength<1>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/bias_wsiM0_MBurstLength<2>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/bias_wsiM0_MBurstLength<3>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/bias_wsiM0_MBurstLength<4>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/bias_wsiM0_MBurstLength<5>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/bias_wsiM0_MBurstLength<6>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/bias_wsiM0_MBurstLength<7>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/bias_wsiM0_MBurstLength<8>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/bias_wsiM0_MBurstLength<9>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_10_MAddr<12>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_10_MAddr<13>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_10_MAddr<14>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_10_MAddr<15>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_10_MAddr<16>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_10_MAddr<17>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_10_MAddr<18>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_10_MAddr<19>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_10_MAddr<20>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_10_MAddr<21>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_10_MAddr<22>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_10_MAddr<23>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_10_MAddr<24>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_10_MAddr<25>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_10_MAddr<26>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_10_MAddr<27>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_10_MAddr<28>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_10_MAddr<29>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_10_MAddr<30>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_10_MAddr<31>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_10_MByteEn<0>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_10_MByteEn<1>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_10_MByteEn<2>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_10_MByteEn<3>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_13_MAddr<10>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_13_MAddr<11>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_13_MAddr<12>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_13_MAddr<13>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_13_MAddr<14>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_13_MAddr<15>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_13_MAddr<16>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_13_MAddr<17>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_13_MAddr<18>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_13_MAddr<19>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_13_MAddr<20>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_13_MAddr<21>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_13_MAddr<22>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_13_MAddr<23>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_13_MAddr<24>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_13_MAddr<25>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_13_MAddr<26>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_13_MAddr<27>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_13_MAddr<28>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_13_MAddr<29>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_13_MAddr<30>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_13_MAddr<31>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_13_MAddr<8>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_13_MAddr<9>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_13_MByteEn<0>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_13_MByteEn<1>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_13_MByteEn<2>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_13_MByteEn<3>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_14_MAddr<10>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_14_MAddr<11>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_14_MAddr<12>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_14_MAddr<13>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_14_MAddr<14>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_14_MAddr<15>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_14_MAddr<16>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_14_MAddr<17>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_14_MAddr<18>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_14_MAddr<19>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_14_MAddr<20>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_14_MAddr<21>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_14_MAddr<22>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_14_MAddr<23>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_14_MAddr<24>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_14_MAddr<25>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_14_MAddr<26>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_14_MAddr<27>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_14_MAddr<28>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_14_MAddr<29>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_14_MAddr<30>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_14_MAddr<31>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_14_MAddr<8>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_14_MAddr<9>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_14_MByteEn<0>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_14_MByteEn<1>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_14_MByteEn<2>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_14_MByteEn<3>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_2_MAddr<10>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_2_MAddr<11>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_2_MAddr<12>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_2_MAddr<13>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_2_MAddr<14>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/cp_wci_Vm_2_MAddr<15>' has no driver +WARNING:NgdBuild:452 - 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logical net 'ftop/emux_client2_request_get<4>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/emux_client2_request_get<5>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/emux_client2_request_get<6>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/emux_client2_request_get<7>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/flash_miso_i' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/gmii_col_i' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/gmii_crs_i' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/gmii_intr_i' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/sma0_wmiM0_MAddr<0>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/sma0_wmiM0_MAddr<1>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/sma0_wmiM0_MDataByteEn<0>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/sma0_wmiM0_MDataByteEn<1>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/sma0_wmiM0_MDataByteEn<2>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/sma0_wmiM0_MDataByteEn<3>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/sma0_wmiM0_MDataLast' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/sma0_wsiM0_MBurstLength<0>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/sma0_wsiM0_MBurstLength<10>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/sma0_wsiM0_MBurstLength<11>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/sma0_wsiM0_MBurstLength<1>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/sma0_wsiM0_MBurstLength<2>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/sma0_wsiM0_MBurstLength<3>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/sma0_wsiM0_MBurstLength<4>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/sma0_wsiM0_MBurstLength<5>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/sma0_wsiM0_MBurstLength<6>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/sma0_wsiM0_MBurstLength<7>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/sma0_wsiM0_MBurstLength<8>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/sma0_wsiM0_MBurstLength<9>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/sma1_wmiM0_MAddr<0>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/sma1_wmiM0_MAddr<1>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/sma1_wmiM0_MDataByteEn<0>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/sma1_wmiM0_MDataByteEn<1>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/sma1_wmiM0_MDataByteEn<2>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/sma1_wmiM0_MDataByteEn<3>' has no + driver +WARNING:NgdBuild:452 - logical net 'ftop/sma1_wmiM0_MDataLast' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/eddp1/edpReqF_D_OUT<0>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/eddp1/edpReqF_D_OUT<10>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/eddp1/edpReqF_D_OUT<11>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/eddp1/edpReqF_D_OUT<12>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/eddp1/edpReqF_D_OUT<13>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/eddp1/edpReqF_D_OUT<14>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/eddp1/edpReqF_D_OUT<15>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/eddp1/edpReqF_D_OUT<16>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/eddp1/edpReqF_D_OUT<17>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/eddp1/edpReqF_D_OUT<1>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/eddp1/edpReqF_D_OUT<2>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/eddp1/edpReqF_D_OUT<3>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/eddp1/edpReqF_D_OUT<4>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/eddp1/edpReqF_D_OUT<5>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/eddp1/edpReqF_D_OUT<6>' has no driver +WARNING:NgdBuild:452 - logical net 'ftop/eddp1/edpReqF_D_OUT<7>' has no driver + +Partition Implementation Status +------------------------------- + + No Partitions were found in this design. + +------------------------------- + +NGDBUILD Design Results Summary: + Number of errors: 0 + Number of warnings: 343 + +Total memory usage is 668516 kilobytes + +Writing NGD file "fpgaTop.ngd" ... +Total REAL time to NGDBUILD completion: 12 sec +Total CPU time to NGDBUILD completion: 12 sec + +Writing NGDBUILD log file "fpgaTop.bld"... diff --git a/logs/n210-20121107_1002/fpgaTop.par b/logs/n210-20121107_1002/fpgaTop.par new file mode 100644 index 00000000..b32f64d9 --- /dev/null +++ b/logs/n210-20121107_1002/fpgaTop.par @@ -0,0 +1,361 @@ +Release 14.3 par P.40xd (lin64) +Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. + +ar-cms520:: Wed Nov 07 09:57:47 2012 + +par -w -xe n fpgaTop_map.ncd fpgaTop.ncd fpgaTop.pcf + + +Constraints file: fpgaTop.pcf. +Loading device for application Rf_Device from file '3sd3400a.nph' in environment /opt/Xilinx/14.3/ISE_DS/ISE/. + "fpgaTop" is an NCD, version 3.2, device xc3sd3400a, package fg676, speed -5 + +Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius) +Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts) + + +Device speed data version: "PRODUCTION 1.34 2012-10-12". + + +Design Summary Report: + + Number of External IOBs 109 out of 469 23% + + Number of External Input IOBs 47 + + Number of External Input IBUFs 47 + Number of LOCed External Input IBUFs 47 out of 47 100% + + + Number of External Output IOBs 59 + + Number of External Output IOBs 59 + Number of LOCed External Output IOBs 59 out of 59 100% + + + Number of External Bidir IOBs 1 + + Number of External Bidir IOBs 1 + Number of LOCed External Bidir IOBs 1 out of 1 100% + + + Number of BUFGMUXs 6 out of 24 25% + Number of LOCed BUFGMUXs 1 out of 6 16% + + Number of DCMs 1 out of 8 12% + Number of RAMB16BWERs 47 out of 126 37% + Number of Slices 20435 out of 23872 85% + Number of SLICEMs 1294 out of 11936 10% + + + +Overall effort level (-ol): Standard +Placer effort level (-pl): High +Placer cost table entry (-t): 1 +Router effort level (-rl): High +Extra effort level (-xe): Normal + + +PinPairDelay, Key: 20142014 DCM/CLKIN->DCM/CLKIN +Delay Expression: D_DCM_DLL_LOWF_MINPERIOD_CLKIN + bel_d_dcm_dll_lowf_minperiod_clkin + Name = "MINIMUM_PERIOD-DCM_DCM/CLKIN---MODE:DLL_FREQUENCY_MODE:LOW:LOW-MODE:DFS_FREQUENCY_MODE:LOW:LOW-MODE:CLKIN_DIVIDE_BY_2:#OFF:#OFF-EXTRA:DCM_DFS_CLK_OUTPUTS" + Type = MINIMUM_PERIOD + Pin = "DCM_DCM/CLKIN" + Data = "D_DCM_DLL_LOWF_MINPERIOD_CLKIN" + NumConnDefs = 0 + NumModeDefs = 3 + RadioButton[1] = DLL_FREQUENCY_MODE:LOW + RadioButton[2] = DFS_FREQUENCY_MODE:LOW + RadioButton[3] = CLKIN_DIVIDE_BY_2:#OFF + InvertedFlag = false + SyncFlag = false + SensePosFlag = false + ExtraTag = "DCM_DFS_CLK_OUTPUTS" + +PinPairDelay, Key: 20142014 DCM/CLKIN->DCM/CLKIN +Delay Expression: D_DCM_DLL_LOWF_MAXPERIOD_CLKIN + bel_d_dcm_dll_lowf_maxperiod_clkin + Name = "MAXIMUM_PERIOD-DCM_DCM/CLKIN---MODE:DLL_FREQUENCY_MODE:LOW:LOW-MODE:DFS_FREQUENCY_MODE:LOW:LOW-MODE:CLKIN_DIVIDE_BY_2:#OFF:#OFF-EXTRA:DCM_DFS_CLK_OUTPUTS" + Type = MAXIMUM_PERIOD + Pin = "DCM_DCM/CLKIN" + Data = "D_DCM_DLL_LOWF_MAXPERIOD_CLKIN" + NumConnDefs = 0 + NumModeDefs = 3 + RadioButton[1] = DLL_FREQUENCY_MODE:LOW + RadioButton[2] = DFS_FREQUENCY_MODE:LOW + RadioButton[3] = CLKIN_DIVIDE_BY_2:#OFF + InvertedFlag = false + SyncFlag = false + SensePosFlag = false + ExtraTag = "DCM_DFS_CLK_OUTPUTS" +Starting initial Timing Analysis. REAL time: 14 secs +Finished initial Timing Analysis. REAL time: 15 secs + +WARNING:Par:288 - The signal flash_miso_IBUF has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal gmii_col_IBUF has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal gmii_crs_IBUF has no load. PAR will not attempt to route this signal. +WARNING:Par:288 - The signal gmii_intr_IBUF has no load. PAR will not attempt to route this signal. + +Starting Placer +Total REAL time at the beginning of Placer: 15 secs +Total CPU time at the beginning of Placer: 15 secs + +Phase 1.1 Initial Placement Analysis +Phase 1.1 Initial Placement Analysis (Checksum:4a84813) REAL time: 17 secs + +Phase 2.7 Design Feasibility Check +Phase 2.7 Design Feasibility Check (Checksum:4a84813) REAL time: 17 secs + +Phase 3.31 Local Placement Optimization +Phase 3.31 Local Placement Optimization (Checksum:4a84813) REAL time: 17 secs + +Phase 4.2 Initial Clock and IO Placement + +WARNING:Place:619 - This design is using a Side-BUFG site due to placement constraints on a BUFG, DCM, clock IOB or the + loads of these components. It is recommended that Top and Bottom BUFG sites be used instead of Side-BUFG sites + whenever possible because they can reach every clock region on the device. Side-BUFG sites can reach only clock + regions on the same side of the device and also preclude the use of certain Top and Bottom BUFGs in the same clock + region. +Phase 4.2 Initial Clock and IO Placement (Checksum:55d86592) REAL time: 22 secs + +............................ +................................................................................................. +Phase 5.30 Global Clock Region Assignment +Phase 5.30 Global Clock Region Assignment (Checksum:55d86592) REAL time: 35 secs + +Phase 6.36 Local Placement Optimization +Phase 6.36 Local Placement Optimization (Checksum:55d86592) REAL time: 35 secs + +Phase 7.8 Global Placement +.......................... +............................................................................................................................................................... +................................................... +................................................................................................................................................................................ +............................................... +................................................. +.............. +................................. +Phase 7.8 Global Placement (Checksum:f118591b) REAL time: 1 mins 42 secs + +Phase 8.5 Local Placement Optimization +Phase 8.5 Local Placement Optimization (Checksum:f118591b) REAL time: 1 mins 43 secs + +Phase 9.18 Placement Optimization +Phase 9.18 Placement Optimization (Checksum:7b83741a) REAL time: 2 mins 4 secs + +Phase 10.5 Local Placement Optimization +Phase 10.5 Local Placement Optimization (Checksum:7b83741a) REAL time: 2 mins 4 secs + +Total REAL time to Placer completion: 2 mins 6 secs +Total CPU time to Placer completion: 2 mins 5 secs +Writing design to file fpgaTop.ncd + + + + +PinPairDelay, Key: 20142014 DCM/CLKIN->DCM/CLKIN +Delay Expression: D_DCM_DLL_LOWF_MINPERIOD_CLKIN + bel_d_dcm_dll_lowf_minperiod_clkin + Name = "MINIMUM_PERIOD-DCM_DCM/CLKIN---MODE:DLL_FREQUENCY_MODE:LOW:LOW-MODE:DFS_FREQUENCY_MODE:LOW:LOW-MODE:CLKIN_DIVIDE_BY_2:#OFF:#OFF-EXTRA:DCM_DFS_CLK_OUTPUTS" + Type = MINIMUM_PERIOD + Pin = "DCM_DCM/CLKIN" + Data = "D_DCM_DLL_LOWF_MINPERIOD_CLKIN" + NumConnDefs = 0 + NumModeDefs = 3 + RadioButton[1] = DLL_FREQUENCY_MODE:LOW + RadioButton[2] = DFS_FREQUENCY_MODE:LOW + RadioButton[3] = CLKIN_DIVIDE_BY_2:#OFF + InvertedFlag = false + SyncFlag = false + SensePosFlag = false + ExtraTag = "DCM_DFS_CLK_OUTPUTS" + +PinPairDelay, Key: 20142014 DCM/CLKIN->DCM/CLKIN +Delay Expression: D_DCM_DLL_LOWF_MAXPERIOD_CLKIN + bel_d_dcm_dll_lowf_maxperiod_clkin + Name = "MAXIMUM_PERIOD-DCM_DCM/CLKIN---MODE:DLL_FREQUENCY_MODE:LOW:LOW-MODE:DFS_FREQUENCY_MODE:LOW:LOW-MODE:CLKIN_DIVIDE_BY_2:#OFF:#OFF-EXTRA:DCM_DFS_CLK_OUTPUTS" + Type = MAXIMUM_PERIOD + Pin = "DCM_DCM/CLKIN" + Data = "D_DCM_DLL_LOWF_MAXPERIOD_CLKIN" + NumConnDefs = 0 + NumModeDefs = 3 + RadioButton[1] = DLL_FREQUENCY_MODE:LOW + RadioButton[2] = DFS_FREQUENCY_MODE:LOW + RadioButton[3] = CLKIN_DIVIDE_BY_2:#OFF + InvertedFlag = false + SyncFlag = false + SensePosFlag = false + ExtraTag = "DCM_DFS_CLK_OUTPUTS" + +PinPairDelay, Key: 20142014 DCM/CLKIN->DCM/CLKIN +Delay Expression: D_DCM_DLL_LOWF_MINPERIOD_CLKIN + bel_d_dcm_dll_lowf_minperiod_clkin + Name = "MINIMUM_PERIOD-DCM_DCM/CLKIN---MODE:DLL_FREQUENCY_MODE:LOW:LOW-MODE:DFS_FREQUENCY_MODE:LOW:LOW-MODE:CLKIN_DIVIDE_BY_2:#OFF:#OFF-EXTRA:DCM_DFS_CLK_OUTPUTS" + Type = MINIMUM_PERIOD + Pin = "DCM_DCM/CLKIN" + Data = "D_DCM_DLL_LOWF_MINPERIOD_CLKIN" + NumConnDefs = 0 + NumModeDefs = 3 + RadioButton[1] = DLL_FREQUENCY_MODE:LOW + RadioButton[2] = DFS_FREQUENCY_MODE:LOW + RadioButton[3] = CLKIN_DIVIDE_BY_2:#OFF + InvertedFlag = false + SyncFlag = false + SensePosFlag = false + ExtraTag = "DCM_DFS_CLK_OUTPUTS" + +PinPairDelay, Key: 20142014 DCM/CLKIN->DCM/CLKIN +Delay Expression: D_DCM_DLL_LOWF_MAXPERIOD_CLKIN + bel_d_dcm_dll_lowf_maxperiod_clkin + Name = "MAXIMUM_PERIOD-DCM_DCM/CLKIN---MODE:DLL_FREQUENCY_MODE:LOW:LOW-MODE:DFS_FREQUENCY_MODE:LOW:LOW-MODE:CLKIN_DIVIDE_BY_2:#OFF:#OFF-EXTRA:DCM_DFS_CLK_OUTPUTS" + Type = MAXIMUM_PERIOD + Pin = "DCM_DCM/CLKIN" + Data = "D_DCM_DLL_LOWF_MAXPERIOD_CLKIN" + NumConnDefs = 0 + NumModeDefs = 3 + RadioButton[1] = DLL_FREQUENCY_MODE:LOW + RadioButton[2] = DFS_FREQUENCY_MODE:LOW + RadioButton[3] = CLKIN_DIVIDE_BY_2:#OFF + InvertedFlag = false + SyncFlag = false + SensePosFlag = false + ExtraTag = "DCM_DFS_CLK_OUTPUTS" +Starting Router + + +Phase 1 : 142272 unrouted; REAL time: 2 mins 24 secs + +Phase 2 : 122640 unrouted; REAL time: 2 mins 26 secs + +Phase 3 : 35084 unrouted; REAL time: 2 mins 40 secs + +Phase 4 : 35093 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 2 mins 43 secs + +Phase 5 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 3 mins 4 secs + +Updating file: fpgaTop.ncd with current fully routed design. + +Phase 6 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 3 mins 17 secs + +Phase 7 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 3 mins 19 secs + +Phase 8 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 3 mins 26 secs +WARNING:Route:455 - CLK Net:adc_sclkdrv may have excessive skew because + 0 CLK pins and 1 NON_CLK pins failed to route using a CLK template. +WARNING:Route:455 - CLK Net:ftop/clkIn_O may have excessive skew because + 2 CLK pins and 0 NON_CLK pins failed to route using a CLK template. + +Total REAL time to Router completion: 3 mins 27 secs +Total CPU time to Router completion: 3 mins 27 secs + +Partition Implementation Status +------------------------------- + + No Partitions were found in this design. + +------------------------------- + +Generating "PAR" statistics. + +************************** +Generating Clock Report +************************** + ++---------------------+--------------+------+------+------------+-------------+ +| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)| ++---------------------+--------------+------+------+------------+-------------+ +| ftop/sys1Clk | BUFGMUX_X1Y0| No |11764 | 0.472 | 1.831 | ++---------------------+--------------+------+------+------------+-------------+ +| ftop/gmiixo_clk_O | BUFGMUX_X3Y8| No | 408 | 0.381 | 1.037 | ++---------------------+--------------+------+------+------------+-------------+ +| adc_sclkdrv | BUFGMUX_X1Y10| No | 27 | 0.135 | 1.535 | ++---------------------+--------------+------+------+------------+-------------+ +| gmii_rx_clk_BUFGP | BUFGMUX_X3Y6|Yes | 80 | 0.177 | 0.942 | ++---------------------+--------------+------+------+------------+-------------+ +| adc_clkout_BUFGP | BUFGMUX_X0Y4| No | 20 | 0.177 | 0.871 | ++---------------------+--------------+------+------+------------+-------------+ +| ftop/sys0Clk | BUFGMUX_X2Y1| No | 2 | 0.000 | 1.564 | ++---------------------+--------------+------+------+------------+-------------+ +| ftop/clkIn_O | Local| | 4 | 2.312 | 3.873 | ++---------------------+--------------+------+------+------------+-------------+ + +* Net Skew is the difference between the minimum and maximum routing +only delays for the net. Note this is different from Clock Skew which +is reported in TRCE timing report. Clock Skew is the difference between +the minimum and maximum path delays which includes logic delays. + +* The fanout is the number of component pins not the individual BEL loads, +for example SLICE loads not FF loads. + +Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0) + +Asterisk (*) preceding a constraint indicates it was not met. + This may be due to a setup or hold violation. + +---------------------------------------------------------------------------------------------------------- + Constraint | Check | Worst Case | Best Case | Timing | Timing + | | Slack | Achievable | Errors | Score +---------------------------------------------------------------------------------------------------------- + TS_GMIISYSCLK = PERIOD TIMEGRP "GMIISYSCL | SETUP | 0.045ns| 7.910ns| 0| 0 + K" 8 ns HIGH 50% | HOLD | 0.643ns| | 0| 0 +---------------------------------------------------------------------------------------------------------- + TS_GMIIRXCLK = PERIOD TIMEGRP "GMIIRXCLK" | SETUP | 0.184ns| 7.816ns| 0| 0 + 8 ns HIGH 50% | HOLD | 0.693ns| | 0| 0 +---------------------------------------------------------------------------------------------------------- + TS_ftop_clkN210_clkdv_unbuf = PERIOD TIME | SETUP | 0.500ns| 19.500ns| 0| 0 + GRP "ftop_clkN210_clkdv_unbuf" TS | HOLD | 0.503ns| | 0| 0 + _SYS0CLK * 2 HIGH 50% | | | | | +---------------------------------------------------------------------------------------------------------- + TS_ftop_clkN210_clk0_unbuf = PERIOD TIMEG | SETUP | 2.149ns| 7.851ns| 0| 0 + RP "ftop_clkN210_clk0_unbuf" TS_S | HOLD | 5.709ns| | 0| 0 + YS0CLK HIGH 50% | | | | | +---------------------------------------------------------------------------------------------------------- + TS_SYS0CLK = PERIOD TIMEGRP "SYS0CLK" 10 | SETUP | 8.217ns| 1.783ns| 0| 0 + ns HIGH 50% | HOLD | 1.166ns| | 0| 0 + | MINLOWPULSE | 5.200ns| 4.800ns| 0| 0 +---------------------------------------------------------------------------------------------------------- + + +Derived Constraint Report +Review Timing Report for more details on the following derived constraints. +To create a Timing Report, run "trce -v 12 -fastpaths -o design_timing_report design.ncd design.pcf" +or "Run Timing Analysis" from Timing Analyzer (timingan). +Derived Constraints for TS_SYS0CLK ++-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ +| | Period | Actual Period | Timing Errors | Paths Analyzed | +| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------| +| | | Direct | Derivative | Direct | Derivative | Direct | Derivative | ++-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ +|TS_SYS0CLK | 10.000ns| 4.800ns| 9.750ns| 0| 0| 2| 5509129| +| TS_ftop_clkN210_clk0_unbuf | 10.000ns| 7.851ns| N/A| 0| 0| 1| 0| +| TS_ftop_clkN210_clkdv_unbuf | 20.000ns| 19.500ns| N/A| 0| 0| 5509128| 0| ++-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ + +All constraints were met. + + +Generating Pad Report. + +All signals are completely routed. + +WARNING:Par:283 - There are 4 loadless signals in this design. This design will cause Bitgen to issue DRC warnings. + +Total REAL time to PAR completion: 3 mins 34 secs +Total CPU time to PAR completion: 3 mins 34 secs + +Peak Memory Usage: 1322 MB + +Placement: Completed - No errors found. +Routing: Completed - No errors found. +Timing: Completed - No errors found. + +Number of error messages: 0 +Number of warning messages: 9 +Number of info messages: 0 + +Writing design to file fpgaTop.ncd + + + +PAR done! diff --git a/logs/n210-20121107_1002/fpgaTop.twr b/logs/n210-20121107_1002/fpgaTop.twr new file mode 100644 index 00000000..7fefbe54 --- /dev/null +++ b/logs/n210-20121107_1002/fpgaTop.twr @@ -0,0 +1,5978 @@ +-------------------------------------------------------------------------------- +Release 14.3 Trace (lin64) +Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. + +/opt/Xilinx/14.3/ISE_DS/ISE/bin/lin64/unwrapped/trce -v 20 -fastpaths -xml +fpgaTop.twx fpgaTop.ncd -o fpgaTop.twr fpgaTop.pcf + +Design file: fpgaTop.ncd +Physical constraint file: fpgaTop.pcf +Device,package,speed: xc3sd3400a,fg676,-5 (PRODUCTION 1.34 2012-10-12) +Report level: verbose report, limited to 20 items per constraint + +Environment Variable Effect +-------------------- ------ +NONE No environment variables were set +-------------------------------------------------------------------------------- + +INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612). +INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths + option. All paths that are not constrained will be reported in the + unconstrained paths section(s) of the report. +INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on + a 50 Ohm transmission line loading model. For the details of this model, + and for more information on accounting for different loading conditions, + please see the device datasheet. +INFO:Timing:3390 - This architecture does not support a default System Jitter + value, please add SYSTEM_JITTER constraint to the UCF to modify the Clock + Uncertainty calculation. +INFO:Timing:3389 - This architecture does not support 'Discrete Jitter' and + 'Phase Error' calculations, these terms will be zero in the Clock + Uncertainty calculation. Please make appropriate modification to + SYSTEM_JITTER to account for the unsupported Discrete Jitter and Phase + Error. + +================================================================================ +Timing constraint: TS_SYS0CLK = PERIOD TIMEGRP "SYS0CLK" 10 ns HIGH 50%; +For more information, see Period Analysis in the Timing Closure User Guide (UG612). + + 2 paths analyzed, 2 endpoints analyzed, 0 failing endpoints + 0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors) + Minimum period is 4.800ns. +-------------------------------------------------------------------------------- +Slack (setup path): 8.217ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/clkN210/lock_flop2 (FF) + Destination: ftop/clkN210/lock_flop3 (FF) + Requirement: 10.000ns + Data Path Delay: 1.783ns (Levels of Logic = 0) + Clock Path Skew: 0.000ns + Source Clock: ftop/clkIn_O rising at 0.000ns + Destination Clock: ftop/clkIn_O rising at 10.000ns + Clock Uncertainty: 0.000ns + + Maximum Data Path: ftop/clkN210/lock_flop2 to ftop/clkN210/lock_flop3 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X60Y3.YQ Tcko 0.596 ftop/clkN210/unlock3 + ftop/clkN210/lock_flop2 + SLICE_X60Y3.BX net (fanout=2) 0.950 ftop/clkN210/unlock2 + SLICE_X60Y3.CLK Tdick 0.237 ftop/clkN210/unlock3 + ftop/clkN210/lock_flop3 + ------------------------------------------------- --------------------------- + Total 1.783ns (0.833ns logic, 0.950ns route) + (46.7% logic, 53.3% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 8.427ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/clkN210/lock_flop (FF) + Destination: ftop/clkN210/lock_flop2 (FF) + Requirement: 10.000ns + Data Path Delay: 1.577ns (Levels of Logic = 1) + Clock Path Skew: 0.004ns (0.014 - 0.010) + Source Clock: ftop/clkIn_O rising at 0.000ns + Destination Clock: ftop/clkIn_O rising at 10.000ns + Clock Uncertainty: 0.000ns + + Maximum Data Path: ftop/clkN210/lock_flop to ftop/clkN210/lock_flop2 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X61Y0.YQ Tcko 0.524 ftop/clkN210/locked_d + ftop/clkN210/lock_flop + SLICE_X60Y3.G1 net (fanout=1) 0.382 ftop/clkN210/locked_d + SLICE_X60Y3.CLK Tgck 0.671 ftop/clkN210/unlock3 + ftop/clkN210/edge_cap + ftop/clkN210/lock_flop2 + ------------------------------------------------- --------------------------- + Total 1.577ns (1.195ns logic, 0.382ns route) + (75.8% logic, 24.2% route) + +-------------------------------------------------------------------------------- + +Hold Paths: TS_SYS0CLK = PERIOD TIMEGRP "SYS0CLK" 10 ns HIGH 50%; +-------------------------------------------------------------------------------- +Slack (hold path): 1.166ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/clkN210/lock_flop (FF) + Destination: ftop/clkN210/lock_flop2 (FF) + Requirement: 0.000ns + Data Path Delay: 1.175ns (Levels of Logic = 1) + Clock Path Skew: 0.009ns (0.017 - 0.008) + Source Clock: ftop/clkIn_O rising at 10.000ns + Destination Clock: ftop/clkIn_O rising at 10.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path: ftop/clkN210/lock_flop to ftop/clkN210/lock_flop2 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X61Y0.YQ Tcko 0.419 ftop/clkN210/locked_d + ftop/clkN210/lock_flop + SLICE_X60Y3.G1 net (fanout=1) 0.306 ftop/clkN210/locked_d + SLICE_X60Y3.CLK Tckg (-Th) -0.450 ftop/clkN210/unlock3 + ftop/clkN210/edge_cap + ftop/clkN210/lock_flop2 + ------------------------------------------------- --------------------------- + Total 1.175ns (0.869ns logic, 0.306ns route) + (74.0% logic, 26.0% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 1.339ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/clkN210/lock_flop2 (FF) + Destination: ftop/clkN210/lock_flop3 (FF) + Requirement: 0.000ns + Data Path Delay: 1.339ns (Levels of Logic = 0) + Clock Path Skew: 0.000ns + Source Clock: ftop/clkIn_O rising at 10.000ns + Destination Clock: ftop/clkIn_O rising at 10.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path: ftop/clkN210/lock_flop2 to ftop/clkN210/lock_flop3 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X60Y3.YQ Tcko 0.477 ftop/clkN210/unlock3 + ftop/clkN210/lock_flop2 + SLICE_X60Y3.BX net (fanout=2) 0.760 ftop/clkN210/unlock2 + SLICE_X60Y3.CLK Tckdi (-Th) -0.102 ftop/clkN210/unlock3 + ftop/clkN210/lock_flop3 + ------------------------------------------------- --------------------------- + Total 1.339ns (0.579ns logic, 0.760ns route) + (43.2% logic, 56.8% route) + +-------------------------------------------------------------------------------- + +Component Switching Limit Checks: TS_SYS0CLK = PERIOD TIMEGRP "SYS0CLK" 10 ns HIGH 50%; +-------------------------------------------------------------------------------- +Slack: 5.200ns (period - (min low pulse limit / (low pulse / period))) + Period: 10.000ns + Low pulse: 5.000ns + Low pulse limit: 2.400ns (Tdcmpw_CLKIN_100_150) + Physical resource: ftop/clkN210/dcm/CLKIN + Logical resource: ftop/clkN210/dcm/CLKIN + Location pin: DCM_X1Y0.CLKIN + Clock network: ftop/clkIn_O +-------------------------------------------------------------------------------- +Slack: 5.200ns (period - (min high pulse limit / (high pulse / period))) + Period: 10.000ns + High pulse: 5.000ns + High pulse limit: 2.400ns (Tdcmpw_CLKIN_100_150) + Physical resource: ftop/clkN210/dcm/CLKIN + Logical resource: ftop/clkN210/dcm/CLKIN + Location pin: DCM_X1Y0.CLKIN + Clock network: ftop/clkIn_O +-------------------------------------------------------------------------------- +Slack: 6.430ns (period - min period limit) + Period: 10.000ns + Min period limit: 3.570ns (280.112MHz) (Tdcmpc) + Physical resource: ftop/clkN210/dcm/CLKIN + Logical resource: ftop/clkN210/dcm/CLKIN + Location pin: DCM_X1Y0.CLKIN + Clock network: ftop/clkIn_O +-------------------------------------------------------------------------------- +Slack: 6.430ns (period - min period limit) + Period: 10.000ns + Min period limit: 3.570ns (280.112MHz) (Tdcmpco) + Physical resource: ftop/clkN210/dcm/CLK0 + Logical resource: ftop/clkN210/dcm/CLK0 + Location pin: DCM_X1Y0.CLK0 + Clock network: ftop/clkN210/clk0_unbuf +-------------------------------------------------------------------------------- +Slack: 8.672ns (period - (min low pulse limit / (low pulse / period))) + Period: 10.000ns + Low pulse: 5.000ns + Low pulse limit: 0.664ns (Tcl) + Physical resource: ftop/clkN210/unlock3/CLK + Logical resource: ftop/clkN210/lock_flop3/CK + Location pin: SLICE_X60Y3.CLK + Clock network: ftop/clkIn_O +-------------------------------------------------------------------------------- +Slack: 8.672ns (period - (min high pulse limit / (high pulse / period))) + Period: 10.000ns + High pulse: 5.000ns + High pulse limit: 0.664ns (Tch) + Physical resource: ftop/clkN210/unlock3/CLK + Logical resource: ftop/clkN210/lock_flop3/CK + Location pin: SLICE_X60Y3.CLK + Clock network: ftop/clkIn_O +-------------------------------------------------------------------------------- +Slack: 8.672ns (period - min period limit) + Period: 10.000ns + Min period limit: 1.328ns (753.012MHz) (Tcp) + Physical resource: ftop/clkN210/unlock3/CLK + Logical resource: ftop/clkN210/lock_flop3/CK + Location pin: SLICE_X60Y3.CLK + Clock network: ftop/clkIn_O +-------------------------------------------------------------------------------- +Slack: 8.672ns (period - (min low pulse limit / (low pulse / period))) + Period: 10.000ns + Low pulse: 5.000ns + Low pulse limit: 0.664ns (Tcl) + Physical resource: ftop/clkN210/unlock3/CLK + Logical resource: ftop/clkN210/lock_flop2/CK + Location pin: SLICE_X60Y3.CLK + Clock network: ftop/clkIn_O +-------------------------------------------------------------------------------- +Slack: 8.672ns (period - (min high pulse limit / (high pulse / period))) + Period: 10.000ns + High pulse: 5.000ns + High pulse limit: 0.664ns (Tch) + Physical resource: ftop/clkN210/unlock3/CLK + Logical resource: ftop/clkN210/lock_flop2/CK + Location pin: SLICE_X60Y3.CLK + Clock network: ftop/clkIn_O +-------------------------------------------------------------------------------- +Slack: 8.672ns (period - min period limit) + Period: 10.000ns + Min period limit: 1.328ns (753.012MHz) (Tcp) + Physical resource: ftop/clkN210/unlock3/CLK + Logical resource: ftop/clkN210/lock_flop2/CK + Location pin: SLICE_X60Y3.CLK + Clock network: ftop/clkIn_O +-------------------------------------------------------------------------------- +Slack: 8.672ns (period - (min low pulse limit / (low pulse / period))) + Period: 10.000ns + Low pulse: 5.000ns + Low pulse limit: 0.664ns (Tcl) + Physical resource: ftop/clkN210/rstInD/CLK + Logical resource: ftop/clkN210/rst_fd/CK + Location pin: SLICE_X82Y52.CLK + Clock network: ftop/clkIn_O +-------------------------------------------------------------------------------- +Slack: 8.672ns (period - (min high pulse limit / (high pulse / period))) + Period: 10.000ns + High pulse: 5.000ns + High pulse limit: 0.664ns (Tch) + Physical resource: ftop/clkN210/rstInD/CLK + Logical resource: ftop/clkN210/rst_fd/CK + Location pin: SLICE_X82Y52.CLK + Clock network: ftop/clkIn_O +-------------------------------------------------------------------------------- +Slack: 8.672ns (period - min period limit) + Period: 10.000ns + Min period limit: 1.328ns (753.012MHz) (Tcp) + Physical resource: ftop/clkN210/rstInD/CLK + Logical resource: ftop/clkN210/rst_fd/CK + Location pin: SLICE_X82Y52.CLK + Clock network: ftop/clkIn_O +-------------------------------------------------------------------------------- +Slack: 8.752ns (period - (min low pulse limit / (low pulse / period))) + Period: 10.000ns + Low pulse: 5.000ns + Low pulse limit: 0.624ns (Tcl) + Physical resource: ftop/clkN210/locked_d/CLK + Logical resource: ftop/clkN210/lock_flop/CK + Location pin: SLICE_X61Y0.CLK + Clock network: ftop/clkIn_O +-------------------------------------------------------------------------------- +Slack: 8.752ns (period - (min high pulse limit / (high pulse / period))) + Period: 10.000ns + High pulse: 5.000ns + High pulse limit: 0.624ns (Tch) + Physical resource: ftop/clkN210/locked_d/CLK + Logical resource: ftop/clkN210/lock_flop/CK + Location pin: SLICE_X61Y0.CLK + Clock network: ftop/clkIn_O +-------------------------------------------------------------------------------- +Slack: 8.752ns (period - min period limit) + Period: 10.000ns + Min period limit: 1.248ns (801.282MHz) (Tcp) + Physical resource: ftop/clkN210/locked_d/CLK + Logical resource: ftop/clkN210/lock_flop/CK + Location pin: SLICE_X61Y0.CLK + Clock network: ftop/clkIn_O +-------------------------------------------------------------------------------- +Slack: 14.653ns (period - min period limit) + Period: 20.000ns + Min period limit: 5.347ns (187.021MHz) (Tdcmpdv) + Physical resource: ftop/clkN210/dcm/CLKDV + Logical resource: ftop/clkN210/dcm/CLKDV + Location pin: DCM_X1Y0.CLKDV + Clock network: ftop/clkN210/clkdv_unbuf +-------------------------------------------------------------------------------- +Slack: 190.000ns (max period limit - period) + Period: 10.000ns + Max period limit: 200.000ns (5.000MHz) (Tdcmpc) + Physical resource: ftop/clkN210/dcm/CLKIN + Logical resource: ftop/clkN210/dcm/CLKIN + Location pin: DCM_X1Y0.CLKIN + Clock network: ftop/clkIn_O +-------------------------------------------------------------------------------- +Slack: 190.000ns (max period limit - period) + Period: 10.000ns + Max period limit: 200.000ns (5.000MHz) (Tdcmpco) + Physical resource: ftop/clkN210/dcm/CLK0 + Logical resource: ftop/clkN210/dcm/CLK0 + Location pin: DCM_X1Y0.CLK0 + Clock network: ftop/clkN210/clk0_unbuf +-------------------------------------------------------------------------------- +Slack: 3205.800ns (max period limit - period) + Period: 20.000ns + Max period limit: 3225.800ns (0.310MHz) (Tdcmpdv) + Physical resource: ftop/clkN210/dcm/CLKDV + Logical resource: ftop/clkN210/dcm/CLKDV + Location pin: DCM_X1Y0.CLKDV + Clock network: ftop/clkN210/clkdv_unbuf +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: TS_GMIISYSCLK = PERIOD TIMEGRP "GMIISYSCLK" 8 ns HIGH 50%; +For more information, see Period Analysis in the Timing Closure User Guide (UG612). + + 13712 paths analyzed, 1952 endpoints analyzed, 0 failing endpoints + 0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors) + Minimum period is 7.910ns. +-------------------------------------------------------------------------------- +Slack (setup path): 0.045ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/gmac/txRS_txData_0 (FF) + Destination: ftop/gbe0/gmac/gmac/txRS_iobTxData/FF1 (FF) + Requirement: 4.000ns + Data Path Delay: 3.908ns (Levels of Logic = 0) + Clock Path Skew: -0.047ns (0.730 - 0.777) + Source Clock: ftop/gmiixo_clk_O rising at 0.000ns + Destination Clock: ftop/gmiixo_clk_O falling at 4.000ns + Clock Uncertainty: 0.000ns + + Maximum Data Path: ftop/gbe0/gmac/gmac/txRS_txData_0 to ftop/gbe0/gmac/gmac/txRS_iobTxData/FF1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X110Y179.YQ Tcko 0.596 ftop/gbe0/gmac/gmac/txRS_txData<0> + ftop/gbe0/gmac/gmac/txRS_txData_0 + E26.O2 net (fanout=2) 2.604 ftop/gbe0/gmac/gmac/txRS_txData<0> + E26.OTCLK2 Tioock 0.708 gmii_txd<0> + ftop/gbe0/gmac/gmac/txRS_iobTxData/FF1 + ------------------------------------------------- --------------------------- + Total 3.908ns (1.304ns logic, 2.604ns route) + (33.4% logic, 66.6% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.171ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/gmac/txRS_ifgCnt_value_0 (FF) + Destination: ftop/gbe0/gmac/gmac/txRS_crc/rRemainder_12 (FF) + Requirement: 8.000ns + Data Path Delay: 7.781ns (Levels of Logic = 7) + Clock Path Skew: -0.048ns (0.365 - 0.413) + Source Clock: ftop/gmiixo_clk_O rising at 0.000ns + Destination Clock: ftop/gmiixo_clk_O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Maximum Data Path: ftop/gbe0/gmac/gmac/txRS_ifgCnt_value_0 to ftop/gbe0/gmac/gmac/txRS_crc/rRemainder_12 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X105Y190.YQ Tcko 0.524 ftop/gbe0/gmac/gmac/txRS_ifgCnt_value<1> + ftop/gbe0/gmac/gmac/txRS_ifgCnt_value_0 + SLICE_X104Y188.G1 net (fanout=5) 0.738 ftop/gbe0/gmac/gmac/txRS_ifgCnt_value<0> + SLICE_X104Y188.Y Tilo 0.616 ftop/gbe0/gmac/gmac/N34 + ftop/gbe0/gmac/gmac/txRS_ifgCnt_value_D_IN<2>11 + SLICE_X104Y188.F4 net (fanout=2) 0.057 ftop/gbe0/gmac/gmac/N40 + SLICE_X104Y188.X Tilo 0.601 ftop/gbe0/gmac/gmac/N34 + ftop/gbe0/gmac/gmac/txRS_txData_D_IN<7>222 + SLICE_X105Y188.G4 net (fanout=10) 0.143 ftop/gbe0/gmac/gmac/N34 + SLICE_X105Y188.Y Tilo 0.561 ftop/gbe0/gmac/gmac/txRS_crc_add_data<0> + ftop/gbe0/gmac/gmac/MUX_txRS_crc_add_1__SEL_11 + SLICE_X106Y188.F3 net (fanout=11) 0.636 ftop/gbe0/gmac/gmac/MUX_txRS_crc_add_1__SEL_1 + SLICE_X106Y188.X Tilo 0.601 ftop/gbe0/gmac/gmac/txRS_crc_add_data<7> + ftop/gbe0/gmac/gmac/txRS_crc_add_data<7>1 + SLICE_X107Y186.G3 net (fanout=3) 0.307 ftop/gbe0/gmac/gmac/txRS_crc_add_data<7> + SLICE_X107Y186.Y Tilo 0.561 ftop/gbe0/gmac/gmac/txRS_crc/rRemainder<0> + ftop/gbe0/gmac/gmac/txRS_crc/IF_IF_rRemainder_XOR_rwAddIn_wget_BIT_0_CONCAT_ETC___d363<26>1 + SLICE_X108Y186.F2 net (fanout=9) 0.371 ftop/gbe0/gmac/gmac/txRS_crc/IF_IF_IF_IF_IF_IF_IF_rRemainder_XOR_rwAddIn_wg_ETC___d368<31> + SLICE_X108Y186.X Tilo 0.601 ftop/gbe0/gmac/gmac/txRS_crc/N12 + ftop/gbe0/gmac/gmac/txRS_crc/rRemainder_D_IN<11>11 + SLICE_X109Y183.F2 net (fanout=4) 0.862 ftop/gbe0/gmac/gmac/txRS_crc/N12 + SLICE_X109Y183.CLK Tfck 0.602 ftop/gbe0/gmac/gmac/txRS_crc/rRemainder<12> + ftop/gbe0/gmac/gmac/txRS_crc/rRemainder_D_IN<12> + ftop/gbe0/gmac/gmac/txRS_crc/rRemainder_12 + ------------------------------------------------- --------------------------- + Total 7.781ns (4.667ns logic, 3.114ns route) + (60.0% logic, 40.0% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.183ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/txfun_inF/data0_reg_19 (FF) + Destination: ftop/gbe0/gmac/txfun_inF/data0_reg_33 (FF) + Requirement: 8.000ns + Data Path Delay: 7.732ns (Levels of Logic = 5) + Clock Path Skew: -0.085ns (0.348 - 0.433) + Source Clock: ftop/gmiixo_clk_O rising at 0.000ns + Destination Clock: ftop/gmiixo_clk_O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Maximum Data Path: ftop/gbe0/gmac/txfun_inF/data0_reg_19 to ftop/gbe0/gmac/txfun_inF/data0_reg_33 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X106Y157.YQ Tcko 0.596 ftop/gbe0/gmac/txfun_inF_D_OUT<19> + ftop/gbe0/gmac/txfun_inF/data0_reg_19 + SLICE_X109Y163.F3 net (fanout=5) 0.591 ftop/gbe0/gmac/txfun_inF_D_OUT<19> + SLICE_X109Y163.F5 Tif5 0.688 ftop/gbe0/gmac/Mmux_IF_txfun_ptr_0_EQ_0_1_THEN_NOT_txfun_inF_first_ETC___d454_4 + ftop/gbe0/gmac/Mmux_IF_txfun_ptr_0_EQ_0_1_THEN_NOT_txfun_inF_first_ETC___d454_not00021 + ftop/gbe0/gmac/Mmux_IF_txfun_ptr_0_EQ_0_1_THEN_NOT_txfun_inF_first_ETC___d454_4 + SLICE_X109Y162.FXINB net (fanout=1) 0.000 ftop/gbe0/gmac/Mmux_IF_txfun_ptr_0_EQ_0_1_THEN_NOT_txfun_inF_first_ETC___d454_4 + SLICE_X109Y162.Y Tif6y 0.239 ftop/gbe0/gmac/IF_txfun_ptr_0_EQ_0_1_THEN_NOT_txfun_inF_first_ETC___d454 + ftop/gbe0/gmac/Mmux_IF_txfun_ptr_0_EQ_0_1_THEN_NOT_txfun_inF_first_ETC___d454_2_f5 + SLICE_X108Y160.F3 net (fanout=3) 0.256 ftop/gbe0/gmac/IF_txfun_ptr_0_EQ_0_1_THEN_NOT_txfun_inF_first_ETC___d454 + SLICE_X108Y160.X Tilo 0.601 ftop/gbe0/gmac/txfun_inF_DEQ + ftop/gbe0/gmac/txfun_inF_DEQ + SLICE_X109Y160.G4 net (fanout=7) 0.082 ftop/gbe0/gmac/txfun_inF_DEQ + SLICE_X109Y160.Y Tilo 0.561 ftop/gbe0/gmac/txfun_inF/N2 + ftop/gbe0/gmac/txfun_inF/d0h1 + SLICE_X103Y147.G4 net (fanout=40) 1.956 ftop/gbe0/gmac/txfun_inF/d0h + SLICE_X103Y147.Y Tilo 0.561 ftop/gbe0/gmac/txfun_inF/N42 + ftop/gbe0/gmac/txfun_inF/data0_reg_or0000<33>_SW0 + SLICE_X102Y147.SR net (fanout=1) 1.168 ftop/gbe0/gmac/txfun_inF/N26 + SLICE_X102Y147.CLK Tsrck 0.433 ftop/gbe0/gmac/txfun_inF_D_OUT<33> + ftop/gbe0/gmac/txfun_inF/data0_reg_33 + ------------------------------------------------- --------------------------- + Total 7.732ns (3.679ns logic, 4.053ns route) + (47.6% logic, 52.4% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.198ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/gmac/txRS_txF/dNotEmptyReg (FF) + Destination: ftop/gbe0/gmac/gmac/txRS_crc/rRemainder_12 (FF) + Requirement: 8.000ns + Data Path Delay: 7.768ns (Levels of Logic = 6) + Clock Path Skew: -0.034ns (0.365 - 0.399) + Source Clock: ftop/gmiixo_clk_O rising at 0.000ns + Destination Clock: ftop/gmiixo_clk_O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Maximum Data Path: ftop/gbe0/gmac/gmac/txRS_txF/dNotEmptyReg to ftop/gbe0/gmac/gmac/txRS_crc/rRemainder_12 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X103Y186.YQ Tcko 0.524 ftop/gbe0/gmac/gmac/txRS_txF_dEMPTY_N + ftop/gbe0/gmac/gmac/txRS_txF/dNotEmptyReg + SLICE_X106Y189.G2 net (fanout=8) 0.749 ftop/gbe0/gmac/gmac/txRS_txF_dEMPTY_N + SLICE_X106Y189.Y Tilo 0.616 ftop/gbe0/gmac/gmac/N16 + ftop/gbe0/gmac/gmac/txRS_txData_D_IN<7>212 + SLICE_X105Y188.G3 net (fanout=17) 0.777 ftop/gbe0/gmac/gmac/N29 + SLICE_X105Y188.Y Tilo 0.561 ftop/gbe0/gmac/gmac/txRS_crc_add_data<0> + ftop/gbe0/gmac/gmac/MUX_txRS_crc_add_1__SEL_11 + SLICE_X106Y188.F3 net (fanout=11) 0.636 ftop/gbe0/gmac/gmac/MUX_txRS_crc_add_1__SEL_1 + SLICE_X106Y188.X Tilo 0.601 ftop/gbe0/gmac/gmac/txRS_crc_add_data<7> + ftop/gbe0/gmac/gmac/txRS_crc_add_data<7>1 + SLICE_X107Y186.G3 net (fanout=3) 0.307 ftop/gbe0/gmac/gmac/txRS_crc_add_data<7> + SLICE_X107Y186.Y Tilo 0.561 ftop/gbe0/gmac/gmac/txRS_crc/rRemainder<0> + ftop/gbe0/gmac/gmac/txRS_crc/IF_IF_rRemainder_XOR_rwAddIn_wget_BIT_0_CONCAT_ETC___d363<26>1 + SLICE_X108Y186.F2 net (fanout=9) 0.371 ftop/gbe0/gmac/gmac/txRS_crc/IF_IF_IF_IF_IF_IF_IF_rRemainder_XOR_rwAddIn_wg_ETC___d368<31> + SLICE_X108Y186.X Tilo 0.601 ftop/gbe0/gmac/gmac/txRS_crc/N12 + ftop/gbe0/gmac/gmac/txRS_crc/rRemainder_D_IN<11>11 + SLICE_X109Y183.F2 net (fanout=4) 0.862 ftop/gbe0/gmac/gmac/txRS_crc/N12 + SLICE_X109Y183.CLK Tfck 0.602 ftop/gbe0/gmac/gmac/txRS_crc/rRemainder<12> + ftop/gbe0/gmac/gmac/txRS_crc/rRemainder_D_IN<12> + ftop/gbe0/gmac/gmac/txRS_crc/rRemainder_12 + ------------------------------------------------- --------------------------- + Total 7.768ns (4.066ns logic, 3.702ns route) + (52.3% logic, 47.7% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.215ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/gmac/txRS_ifgCnt_value_0 (FF) + Destination: ftop/gbe0/gmac/gmac/txRS_crc/rRemainder_10 (FF) + Requirement: 8.000ns + Data Path Delay: 7.739ns (Levels of Logic = 7) + Clock Path Skew: -0.046ns (0.367 - 0.413) + Source Clock: ftop/gmiixo_clk_O rising at 0.000ns + Destination Clock: ftop/gmiixo_clk_O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Maximum Data Path: ftop/gbe0/gmac/gmac/txRS_ifgCnt_value_0 to ftop/gbe0/gmac/gmac/txRS_crc/rRemainder_10 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X105Y190.YQ Tcko 0.524 ftop/gbe0/gmac/gmac/txRS_ifgCnt_value<1> + ftop/gbe0/gmac/gmac/txRS_ifgCnt_value_0 + SLICE_X104Y188.G1 net (fanout=5) 0.738 ftop/gbe0/gmac/gmac/txRS_ifgCnt_value<0> + SLICE_X104Y188.Y Tilo 0.616 ftop/gbe0/gmac/gmac/N34 + ftop/gbe0/gmac/gmac/txRS_ifgCnt_value_D_IN<2>11 + SLICE_X104Y188.F4 net (fanout=2) 0.057 ftop/gbe0/gmac/gmac/N40 + SLICE_X104Y188.X Tilo 0.601 ftop/gbe0/gmac/gmac/N34 + ftop/gbe0/gmac/gmac/txRS_txData_D_IN<7>222 + SLICE_X105Y188.G4 net (fanout=10) 0.143 ftop/gbe0/gmac/gmac/N34 + SLICE_X105Y188.Y Tilo 0.561 ftop/gbe0/gmac/gmac/txRS_crc_add_data<0> + ftop/gbe0/gmac/gmac/MUX_txRS_crc_add_1__SEL_11 + SLICE_X105Y184.F2 net (fanout=11) 0.662 ftop/gbe0/gmac/gmac/MUX_txRS_crc_add_1__SEL_1 + SLICE_X105Y184.X Tilo 0.562 ftop/gbe0/gmac/gmac/txRS_crc_add_data<4> + ftop/gbe0/gmac/gmac/txRS_crc_add_data<4>1 + SLICE_X110Y182.G1 net (fanout=5) 1.105 ftop/gbe0/gmac/gmac/txRS_crc_add_data<4> + SLICE_X110Y182.Y Tilo 0.616 ftop/gbe0/gmac/gmac/txRS_crc/rRemainder<25> + ftop/gbe0/gmac/gmac/txRS_crc/rRemainder_D_IN<25>21 + SLICE_X111Y184.F3 net (fanout=4) 0.298 ftop/gbe0/gmac/gmac/txRS_crc/N18 + SLICE_X111Y184.X Tilo 0.562 ftop/gbe0/gmac/gmac/txRS_crc/N81 + ftop/gbe0/gmac/gmac/txRS_crc/rRemainder_D_IN<10>_SW0_SW0 + SLICE_X110Y185.G3 net (fanout=1) 0.023 ftop/gbe0/gmac/gmac/txRS_crc/N81 + SLICE_X110Y185.CLK Tgck 0.671 ftop/gbe0/gmac/gmac/txRS_crc/rRemainder<26> + ftop/gbe0/gmac/gmac/txRS_crc/rRemainder_D_IN<10> + ftop/gbe0/gmac/gmac/txRS_crc/rRemainder_10 + ------------------------------------------------- --------------------------- + Total 7.739ns (4.713ns logic, 3.026ns route) + (60.9% logic, 39.1% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.220ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/gmac/txRS_txF/dDoutReg_9 (FF) + Destination: ftop/gbe0/gmac/gmac/txRS_crc/rRemainder_12 (FF) + Requirement: 8.000ns + Data Path Delay: 7.746ns (Levels of Logic = 6) + Clock Path Skew: -0.034ns (0.365 - 0.399) + Source Clock: ftop/gmiixo_clk_O rising at 0.000ns + Destination Clock: ftop/gmiixo_clk_O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Maximum Data Path: ftop/gbe0/gmac/gmac/txRS_txF/dDoutReg_9 to ftop/gbe0/gmac/gmac/txRS_crc/rRemainder_12 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X102Y187.XQ Tcko 0.521 ftop/gbe0/gmac/gmac/txRS_txF_dD_OUT<9> + ftop/gbe0/gmac/gmac/txRS_txF/dDoutReg_9 + SLICE_X106Y189.G3 net (fanout=5) 0.730 ftop/gbe0/gmac/gmac/txRS_txF_dD_OUT<9> + SLICE_X106Y189.Y Tilo 0.616 ftop/gbe0/gmac/gmac/N16 + ftop/gbe0/gmac/gmac/txRS_txData_D_IN<7>212 + SLICE_X105Y188.G3 net (fanout=17) 0.777 ftop/gbe0/gmac/gmac/N29 + SLICE_X105Y188.Y Tilo 0.561 ftop/gbe0/gmac/gmac/txRS_crc_add_data<0> + ftop/gbe0/gmac/gmac/MUX_txRS_crc_add_1__SEL_11 + SLICE_X106Y188.F3 net (fanout=11) 0.636 ftop/gbe0/gmac/gmac/MUX_txRS_crc_add_1__SEL_1 + SLICE_X106Y188.X Tilo 0.601 ftop/gbe0/gmac/gmac/txRS_crc_add_data<7> + ftop/gbe0/gmac/gmac/txRS_crc_add_data<7>1 + SLICE_X107Y186.G3 net (fanout=3) 0.307 ftop/gbe0/gmac/gmac/txRS_crc_add_data<7> + SLICE_X107Y186.Y Tilo 0.561 ftop/gbe0/gmac/gmac/txRS_crc/rRemainder<0> + ftop/gbe0/gmac/gmac/txRS_crc/IF_IF_rRemainder_XOR_rwAddIn_wget_BIT_0_CONCAT_ETC___d363<26>1 + SLICE_X108Y186.F2 net (fanout=9) 0.371 ftop/gbe0/gmac/gmac/txRS_crc/IF_IF_IF_IF_IF_IF_IF_rRemainder_XOR_rwAddIn_wg_ETC___d368<31> + SLICE_X108Y186.X Tilo 0.601 ftop/gbe0/gmac/gmac/txRS_crc/N12 + ftop/gbe0/gmac/gmac/txRS_crc/rRemainder_D_IN<11>11 + SLICE_X109Y183.F2 net (fanout=4) 0.862 ftop/gbe0/gmac/gmac/txRS_crc/N12 + SLICE_X109Y183.CLK Tfck 0.602 ftop/gbe0/gmac/gmac/txRS_crc/rRemainder<12> + ftop/gbe0/gmac/gmac/txRS_crc/rRemainder_D_IN<12> + ftop/gbe0/gmac/gmac/txRS_crc/rRemainder_12 + ------------------------------------------------- --------------------------- + Total 7.746ns (4.063ns logic, 3.683ns route) + (52.5% logic, 47.5% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.241ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/gmac/txRS_isSOF (FF) + Destination: ftop/gbe0/gmac/gmac/txRS_crc/rRemainder_12 (FF) + Requirement: 8.000ns + Data Path Delay: 7.725ns (Levels of Logic = 6) + Clock Path Skew: -0.034ns (0.365 - 0.399) + Source Clock: ftop/gmiixo_clk_O rising at 0.000ns + Destination Clock: ftop/gmiixo_clk_O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Maximum Data Path: ftop/gbe0/gmac/gmac/txRS_isSOF to ftop/gbe0/gmac/gmac/txRS_crc/rRemainder_12 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X103Y187.YQ Tcko 0.524 ftop/gbe0/gmac/gmac/txRS_isSOF + ftop/gbe0/gmac/gmac/txRS_isSOF + SLICE_X104Y189.F2 net (fanout=8) 0.913 ftop/gbe0/gmac/gmac/txRS_isSOF + SLICE_X104Y189.X Tilo 0.601 ftop/gbe0/gmac/gmac/N361 + ftop/gbe0/gmac/gmac/txRS_crc_add_data<0>1_SW0_SW0 + SLICE_X105Y186.F4 net (fanout=8) 0.699 ftop/gbe0/gmac/gmac/N361 + SLICE_X105Y186.X Tilo 0.562 ftop/gbe0/gmac/gmac/N501 + ftop/gbe0/gmac/gmac/txRS_crc_add_data<0>1_SW6 + SLICE_X105Y188.F4 net (fanout=1) 0.266 ftop/gbe0/gmac/gmac/N501 + SLICE_X105Y188.X Tilo 0.562 ftop/gbe0/gmac/gmac/txRS_crc_add_data<0> + ftop/gbe0/gmac/gmac/txRS_crc_add_data<0>2 + SLICE_X108Y186.G4 net (fanout=12) 0.872 ftop/gbe0/gmac/gmac/txRS_crc_add_data<0> + SLICE_X108Y186.Y Tilo 0.616 ftop/gbe0/gmac/gmac/txRS_crc/N12 + ftop/gbe0/gmac/gmac/txRS_crc/rRemainder_D_IN<19>11 + SLICE_X108Y186.F4 net (fanout=3) 0.045 ftop/gbe0/gmac/gmac/txRS_crc/N0 + SLICE_X108Y186.X Tilo 0.601 ftop/gbe0/gmac/gmac/txRS_crc/N12 + ftop/gbe0/gmac/gmac/txRS_crc/rRemainder_D_IN<11>11 + SLICE_X109Y183.F2 net (fanout=4) 0.862 ftop/gbe0/gmac/gmac/txRS_crc/N12 + SLICE_X109Y183.CLK Tfck 0.602 ftop/gbe0/gmac/gmac/txRS_crc/rRemainder<12> + ftop/gbe0/gmac/gmac/txRS_crc/rRemainder_D_IN<12> + ftop/gbe0/gmac/gmac/txRS_crc/rRemainder_12 + ------------------------------------------------- --------------------------- + Total 7.725ns (4.068ns logic, 3.657ns route) + (52.7% logic, 47.3% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.242ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/gmac/txRS_txF/dNotEmptyReg (FF) + Destination: ftop/gbe0/gmac/gmac/txRS_crc/rRemainder_10 (FF) + Requirement: 8.000ns + Data Path Delay: 7.726ns (Levels of Logic = 6) + Clock Path Skew: -0.032ns (0.367 - 0.399) + Source Clock: ftop/gmiixo_clk_O rising at 0.000ns + Destination Clock: ftop/gmiixo_clk_O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Maximum Data Path: ftop/gbe0/gmac/gmac/txRS_txF/dNotEmptyReg to ftop/gbe0/gmac/gmac/txRS_crc/rRemainder_10 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X103Y186.YQ Tcko 0.524 ftop/gbe0/gmac/gmac/txRS_txF_dEMPTY_N + ftop/gbe0/gmac/gmac/txRS_txF/dNotEmptyReg + SLICE_X106Y189.G2 net (fanout=8) 0.749 ftop/gbe0/gmac/gmac/txRS_txF_dEMPTY_N + SLICE_X106Y189.Y Tilo 0.616 ftop/gbe0/gmac/gmac/N16 + ftop/gbe0/gmac/gmac/txRS_txData_D_IN<7>212 + SLICE_X105Y188.G3 net (fanout=17) 0.777 ftop/gbe0/gmac/gmac/N29 + SLICE_X105Y188.Y Tilo 0.561 ftop/gbe0/gmac/gmac/txRS_crc_add_data<0> + ftop/gbe0/gmac/gmac/MUX_txRS_crc_add_1__SEL_11 + SLICE_X105Y184.F2 net (fanout=11) 0.662 ftop/gbe0/gmac/gmac/MUX_txRS_crc_add_1__SEL_1 + SLICE_X105Y184.X Tilo 0.562 ftop/gbe0/gmac/gmac/txRS_crc_add_data<4> + ftop/gbe0/gmac/gmac/txRS_crc_add_data<4>1 + SLICE_X110Y182.G1 net (fanout=5) 1.105 ftop/gbe0/gmac/gmac/txRS_crc_add_data<4> + SLICE_X110Y182.Y Tilo 0.616 ftop/gbe0/gmac/gmac/txRS_crc/rRemainder<25> + ftop/gbe0/gmac/gmac/txRS_crc/rRemainder_D_IN<25>21 + SLICE_X111Y184.F3 net (fanout=4) 0.298 ftop/gbe0/gmac/gmac/txRS_crc/N18 + SLICE_X111Y184.X Tilo 0.562 ftop/gbe0/gmac/gmac/txRS_crc/N81 + ftop/gbe0/gmac/gmac/txRS_crc/rRemainder_D_IN<10>_SW0_SW0 + SLICE_X110Y185.G3 net (fanout=1) 0.023 ftop/gbe0/gmac/gmac/txRS_crc/N81 + SLICE_X110Y185.CLK Tgck 0.671 ftop/gbe0/gmac/gmac/txRS_crc/rRemainder<26> + ftop/gbe0/gmac/gmac/txRS_crc/rRemainder_D_IN<10> + ftop/gbe0/gmac/gmac/txRS_crc/rRemainder_10 + ------------------------------------------------- --------------------------- + Total 7.726ns (4.112ns logic, 3.614ns route) + (53.2% logic, 46.8% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.248ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/txfun_inF/data0_reg_38 (FF) + Destination: ftop/gbe0/gmac/txfun_inF/data0_reg_33 (FF) + Requirement: 8.000ns + Data Path Delay: 7.607ns (Levels of Logic = 5) + Clock Path Skew: -0.145ns (0.348 - 0.493) + Source Clock: ftop/gmiixo_clk_O rising at 0.000ns + Destination Clock: ftop/gmiixo_clk_O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Maximum Data Path: ftop/gbe0/gmac/txfun_inF/data0_reg_38 to ftop/gbe0/gmac/txfun_inF/data0_reg_33 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X108Y162.YQ Tcko 0.596 ftop/gbe0/gmac/txfun_inF_D_OUT<38> + ftop/gbe0/gmac/txfun_inF/data0_reg_38 + SLICE_X109Y162.F1 net (fanout=5) 0.466 ftop/gbe0/gmac/txfun_inF_D_OUT<38> + SLICE_X109Y162.F5 Tif5 0.688 ftop/gbe0/gmac/IF_txfun_ptr_0_EQ_0_1_THEN_NOT_txfun_inF_first_ETC___d454 + ftop/gbe0/gmac/Mmux_IF_txfun_ptr_0_EQ_0_1_THEN_NOT_txfun_inF_first_ETC___d454_not00001 + ftop/gbe0/gmac/Mmux_IF_txfun_ptr_0_EQ_0_1_THEN_NOT_txfun_inF_first_ETC___d454_3 + SLICE_X109Y162.FXINA net (fanout=1) 0.000 ftop/gbe0/gmac/Mmux_IF_txfun_ptr_0_EQ_0_1_THEN_NOT_txfun_inF_first_ETC___d454_3 + SLICE_X109Y162.Y Tif6y 0.239 ftop/gbe0/gmac/IF_txfun_ptr_0_EQ_0_1_THEN_NOT_txfun_inF_first_ETC___d454 + ftop/gbe0/gmac/Mmux_IF_txfun_ptr_0_EQ_0_1_THEN_NOT_txfun_inF_first_ETC___d454_2_f5 + SLICE_X108Y160.F3 net (fanout=3) 0.256 ftop/gbe0/gmac/IF_txfun_ptr_0_EQ_0_1_THEN_NOT_txfun_inF_first_ETC___d454 + SLICE_X108Y160.X Tilo 0.601 ftop/gbe0/gmac/txfun_inF_DEQ + ftop/gbe0/gmac/txfun_inF_DEQ + SLICE_X109Y160.G4 net (fanout=7) 0.082 ftop/gbe0/gmac/txfun_inF_DEQ + SLICE_X109Y160.Y Tilo 0.561 ftop/gbe0/gmac/txfun_inF/N2 + ftop/gbe0/gmac/txfun_inF/d0h1 + SLICE_X103Y147.G4 net (fanout=40) 1.956 ftop/gbe0/gmac/txfun_inF/d0h + SLICE_X103Y147.Y Tilo 0.561 ftop/gbe0/gmac/txfun_inF/N42 + ftop/gbe0/gmac/txfun_inF/data0_reg_or0000<33>_SW0 + SLICE_X102Y147.SR net (fanout=1) 1.168 ftop/gbe0/gmac/txfun_inF/N26 + SLICE_X102Y147.CLK Tsrck 0.433 ftop/gbe0/gmac/txfun_inF_D_OUT<33> + ftop/gbe0/gmac/txfun_inF/data0_reg_33 + ------------------------------------------------- --------------------------- + Total 7.607ns (3.679ns logic, 3.928ns route) + (48.4% logic, 51.6% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.253ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/gmac/txRS_isSOF (FF) + Destination: ftop/gbe0/gmac/gmac/txRS_crc/rRemainder_10 (FF) + Requirement: 8.000ns + Data Path Delay: 7.715ns (Levels of Logic = 6) + Clock Path Skew: -0.032ns (0.367 - 0.399) + Source Clock: ftop/gmiixo_clk_O rising at 0.000ns + Destination Clock: ftop/gmiixo_clk_O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Maximum Data Path: ftop/gbe0/gmac/gmac/txRS_isSOF to ftop/gbe0/gmac/gmac/txRS_crc/rRemainder_10 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X103Y187.YQ Tcko 0.524 ftop/gbe0/gmac/gmac/txRS_isSOF + ftop/gbe0/gmac/gmac/txRS_isSOF + SLICE_X104Y189.F2 net (fanout=8) 0.913 ftop/gbe0/gmac/gmac/txRS_isSOF + SLICE_X104Y189.X Tilo 0.601 ftop/gbe0/gmac/gmac/N361 + ftop/gbe0/gmac/gmac/txRS_crc_add_data<0>1_SW0_SW0 + SLICE_X106Y183.G3 net (fanout=8) 1.347 ftop/gbe0/gmac/gmac/N361 + SLICE_X106Y183.Y Tilo 0.616 ftop/gbe0/gmac/gmac/txRS_crc_add_data<2> + ftop/gbe0/gmac/gmac/txRS_crc_add_data<0>1_SW0 + SLICE_X106Y183.F3 net (fanout=1) 0.021 ftop/gbe0/gmac/gmac/txRS_crc_add_data<0>1_SW0/O + SLICE_X106Y183.X Tilo 0.601 ftop/gbe0/gmac/gmac/txRS_crc_add_data<2> + ftop/gbe0/gmac/gmac/txRS_crc_add_data<2>1 + SLICE_X111Y184.G1 net (fanout=10) 0.954 ftop/gbe0/gmac/gmac/txRS_crc_add_data<2> + SLICE_X111Y184.Y Tilo 0.561 ftop/gbe0/gmac/gmac/txRS_crc/N81 + ftop/gbe0/gmac/gmac/txRS_crc/IF_IF_IF_rRemainder_XOR_rwAddIn_wget_BIT_0_CON_ETC___d364<1>1 + SLICE_X111Y184.F4 net (fanout=4) 0.321 ftop/gbe0/gmac/gmac/txRS_crc/IF_IF_IF_rRemainder_XOR_rwAddIn_wget_BIT_0_CON_ETC___d364<1> + SLICE_X111Y184.X Tilo 0.562 ftop/gbe0/gmac/gmac/txRS_crc/N81 + ftop/gbe0/gmac/gmac/txRS_crc/rRemainder_D_IN<10>_SW0_SW0 + SLICE_X110Y185.G3 net (fanout=1) 0.023 ftop/gbe0/gmac/gmac/txRS_crc/N81 + SLICE_X110Y185.CLK Tgck 0.671 ftop/gbe0/gmac/gmac/txRS_crc/rRemainder<26> + ftop/gbe0/gmac/gmac/txRS_crc/rRemainder_D_IN<10> + ftop/gbe0/gmac/gmac/txRS_crc/rRemainder_10 + ------------------------------------------------- --------------------------- + Total 7.715ns (4.136ns logic, 3.579ns route) + (53.6% logic, 46.4% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.264ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/gmac/txRS_txF/dDoutReg_9 (FF) + Destination: ftop/gbe0/gmac/gmac/txRS_crc/rRemainder_10 (FF) + Requirement: 8.000ns + Data Path Delay: 7.704ns (Levels of Logic = 6) + Clock Path Skew: -0.032ns (0.367 - 0.399) + Source Clock: ftop/gmiixo_clk_O rising at 0.000ns + Destination Clock: ftop/gmiixo_clk_O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Maximum Data Path: ftop/gbe0/gmac/gmac/txRS_txF/dDoutReg_9 to ftop/gbe0/gmac/gmac/txRS_crc/rRemainder_10 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X102Y187.XQ Tcko 0.521 ftop/gbe0/gmac/gmac/txRS_txF_dD_OUT<9> + ftop/gbe0/gmac/gmac/txRS_txF/dDoutReg_9 + SLICE_X106Y189.G3 net (fanout=5) 0.730 ftop/gbe0/gmac/gmac/txRS_txF_dD_OUT<9> + SLICE_X106Y189.Y Tilo 0.616 ftop/gbe0/gmac/gmac/N16 + ftop/gbe0/gmac/gmac/txRS_txData_D_IN<7>212 + SLICE_X105Y188.G3 net (fanout=17) 0.777 ftop/gbe0/gmac/gmac/N29 + SLICE_X105Y188.Y Tilo 0.561 ftop/gbe0/gmac/gmac/txRS_crc_add_data<0> + ftop/gbe0/gmac/gmac/MUX_txRS_crc_add_1__SEL_11 + SLICE_X105Y184.F2 net (fanout=11) 0.662 ftop/gbe0/gmac/gmac/MUX_txRS_crc_add_1__SEL_1 + SLICE_X105Y184.X Tilo 0.562 ftop/gbe0/gmac/gmac/txRS_crc_add_data<4> + ftop/gbe0/gmac/gmac/txRS_crc_add_data<4>1 + SLICE_X110Y182.G1 net (fanout=5) 1.105 ftop/gbe0/gmac/gmac/txRS_crc_add_data<4> + SLICE_X110Y182.Y Tilo 0.616 ftop/gbe0/gmac/gmac/txRS_crc/rRemainder<25> + ftop/gbe0/gmac/gmac/txRS_crc/rRemainder_D_IN<25>21 + SLICE_X111Y184.F3 net (fanout=4) 0.298 ftop/gbe0/gmac/gmac/txRS_crc/N18 + SLICE_X111Y184.X Tilo 0.562 ftop/gbe0/gmac/gmac/txRS_crc/N81 + ftop/gbe0/gmac/gmac/txRS_crc/rRemainder_D_IN<10>_SW0_SW0 + SLICE_X110Y185.G3 net (fanout=1) 0.023 ftop/gbe0/gmac/gmac/txRS_crc/N81 + SLICE_X110Y185.CLK Tgck 0.671 ftop/gbe0/gmac/gmac/txRS_crc/rRemainder<26> + ftop/gbe0/gmac/gmac/txRS_crc/rRemainder_D_IN<10> + ftop/gbe0/gmac/gmac/txRS_crc/rRemainder_10 + ------------------------------------------------- --------------------------- + Total 7.704ns (4.109ns logic, 3.595ns route) + (53.3% logic, 46.7% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.265ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/txfun_inF/data0_reg_28 (FF) + Destination: ftop/gbe0/gmac/txfun_inF/data0_reg_33 (FF) + Requirement: 8.000ns + Data Path Delay: 7.658ns (Levels of Logic = 5) + Clock Path Skew: -0.077ns (0.348 - 0.425) + Source Clock: ftop/gmiixo_clk_O rising at 0.000ns + Destination Clock: ftop/gmiixo_clk_O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Maximum Data Path: ftop/gbe0/gmac/txfun_inF/data0_reg_28 to ftop/gbe0/gmac/txfun_inF/data0_reg_33 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X105Y162.YQ Tcko 0.524 ftop/gbe0/gmac/txfun_inF_D_OUT<28> + ftop/gbe0/gmac/txfun_inF/data0_reg_28 + SLICE_X109Y162.G4 net (fanout=5) 0.589 ftop/gbe0/gmac/txfun_inF_D_OUT<28> + SLICE_X109Y162.F5 Tif5 0.688 ftop/gbe0/gmac/IF_txfun_ptr_0_EQ_0_1_THEN_NOT_txfun_inF_first_ETC___d454 + ftop/gbe0/gmac/Mmux_IF_txfun_ptr_0_EQ_0_1_THEN_NOT_txfun_inF_first_ETC___d454_not00011 + ftop/gbe0/gmac/Mmux_IF_txfun_ptr_0_EQ_0_1_THEN_NOT_txfun_inF_first_ETC___d454_3 + SLICE_X109Y162.FXINA net (fanout=1) 0.000 ftop/gbe0/gmac/Mmux_IF_txfun_ptr_0_EQ_0_1_THEN_NOT_txfun_inF_first_ETC___d454_3 + SLICE_X109Y162.Y Tif6y 0.239 ftop/gbe0/gmac/IF_txfun_ptr_0_EQ_0_1_THEN_NOT_txfun_inF_first_ETC___d454 + ftop/gbe0/gmac/Mmux_IF_txfun_ptr_0_EQ_0_1_THEN_NOT_txfun_inF_first_ETC___d454_2_f5 + SLICE_X108Y160.F3 net (fanout=3) 0.256 ftop/gbe0/gmac/IF_txfun_ptr_0_EQ_0_1_THEN_NOT_txfun_inF_first_ETC___d454 + SLICE_X108Y160.X Tilo 0.601 ftop/gbe0/gmac/txfun_inF_DEQ + ftop/gbe0/gmac/txfun_inF_DEQ + SLICE_X109Y160.G4 net (fanout=7) 0.082 ftop/gbe0/gmac/txfun_inF_DEQ + SLICE_X109Y160.Y Tilo 0.561 ftop/gbe0/gmac/txfun_inF/N2 + ftop/gbe0/gmac/txfun_inF/d0h1 + SLICE_X103Y147.G4 net (fanout=40) 1.956 ftop/gbe0/gmac/txfun_inF/d0h + SLICE_X103Y147.Y Tilo 0.561 ftop/gbe0/gmac/txfun_inF/N42 + ftop/gbe0/gmac/txfun_inF/data0_reg_or0000<33>_SW0 + SLICE_X102Y147.SR net (fanout=1) 1.168 ftop/gbe0/gmac/txfun_inF/N26 + SLICE_X102Y147.CLK Tsrck 0.433 ftop/gbe0/gmac/txfun_inF_D_OUT<33> + ftop/gbe0/gmac/txfun_inF/data0_reg_33 + ------------------------------------------------- --------------------------- + Total 7.658ns (3.607ns logic, 4.051ns route) + (47.1% logic, 52.9% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.275ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/txfun_outF/full_reg (FF) + Destination: ftop/gbe0/gmac/txfun_inF/data0_reg_33 (FF) + Requirement: 8.000ns + Data Path Delay: 7.490ns (Levels of Logic = 4) + Clock Path Skew: -0.235ns (0.598 - 0.833) + Source Clock: ftop/gmiixo_clk_O rising at 0.000ns + Destination Clock: ftop/gmiixo_clk_O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Maximum Data Path: ftop/gbe0/gmac/txfun_outF/full_reg to ftop/gbe0/gmac/txfun_inF/data0_reg_33 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X109Y170.XQ Tcko 0.495 ftop/gbe0/gmac/txfun_outF_FULL_N + ftop/gbe0/gmac/txfun_outF/full_reg + SLICE_X108Y160.G4 net (fanout=6) 0.982 ftop/gbe0/gmac/txfun_outF_FULL_N + SLICE_X108Y160.Y Tilo 0.616 ftop/gbe0/gmac/txfun_inF_DEQ + ftop/gbe0/gmac/txfun_inF_DEQ_SW0 + SLICE_X108Y160.F4 net (fanout=1) 0.035 ftop/gbe0/gmac/txfun_inF_DEQ_SW0/O + SLICE_X108Y160.X Tilo 0.601 ftop/gbe0/gmac/txfun_inF_DEQ + ftop/gbe0/gmac/txfun_inF_DEQ + SLICE_X109Y160.G4 net (fanout=7) 0.082 ftop/gbe0/gmac/txfun_inF_DEQ + SLICE_X109Y160.Y Tilo 0.561 ftop/gbe0/gmac/txfun_inF/N2 + ftop/gbe0/gmac/txfun_inF/d0h1 + SLICE_X103Y147.G4 net (fanout=40) 1.956 ftop/gbe0/gmac/txfun_inF/d0h + SLICE_X103Y147.Y Tilo 0.561 ftop/gbe0/gmac/txfun_inF/N42 + ftop/gbe0/gmac/txfun_inF/data0_reg_or0000<33>_SW0 + SLICE_X102Y147.SR net (fanout=1) 1.168 ftop/gbe0/gmac/txfun_inF/N26 + SLICE_X102Y147.CLK Tsrck 0.433 ftop/gbe0/gmac/txfun_inF_D_OUT<33> + ftop/gbe0/gmac/txfun_inF/data0_reg_33 + ------------------------------------------------- --------------------------- + Total 7.490ns (3.267ns logic, 4.223ns route) + (43.6% logic, 56.4% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.277ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/txfun_inF/data0_reg_19 (FF) + Destination: ftop/gbe0/gmac/txfun_inF/data0_reg_33 (FF) + Requirement: 8.000ns + Data Path Delay: 7.638ns (Levels of Logic = 5) + Clock Path Skew: -0.085ns (0.348 - 0.433) + Source Clock: ftop/gmiixo_clk_O rising at 0.000ns + Destination Clock: ftop/gmiixo_clk_O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Maximum Data Path: ftop/gbe0/gmac/txfun_inF/data0_reg_19 to ftop/gbe0/gmac/txfun_inF/data0_reg_33 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X106Y157.YQ Tcko 0.596 ftop/gbe0/gmac/txfun_inF_D_OUT<19> + ftop/gbe0/gmac/txfun_inF/data0_reg_19 + SLICE_X109Y163.F3 net (fanout=5) 0.591 ftop/gbe0/gmac/txfun_inF_D_OUT<19> + SLICE_X109Y163.F5 Tif5 0.688 ftop/gbe0/gmac/Mmux_IF_txfun_ptr_0_EQ_0_1_THEN_NOT_txfun_inF_first_ETC___d454_4 + ftop/gbe0/gmac/Mmux_IF_txfun_ptr_0_EQ_0_1_THEN_NOT_txfun_inF_first_ETC___d454_not00021 + ftop/gbe0/gmac/Mmux_IF_txfun_ptr_0_EQ_0_1_THEN_NOT_txfun_inF_first_ETC___d454_4 + SLICE_X109Y162.FXINB net (fanout=1) 0.000 ftop/gbe0/gmac/Mmux_IF_txfun_ptr_0_EQ_0_1_THEN_NOT_txfun_inF_first_ETC___d454_4 + SLICE_X109Y162.Y Tif6y 0.239 ftop/gbe0/gmac/IF_txfun_ptr_0_EQ_0_1_THEN_NOT_txfun_inF_first_ETC___d454 + ftop/gbe0/gmac/Mmux_IF_txfun_ptr_0_EQ_0_1_THEN_NOT_txfun_inF_first_ETC___d454_2_f5 + SLICE_X108Y160.F3 net (fanout=3) 0.256 ftop/gbe0/gmac/IF_txfun_ptr_0_EQ_0_1_THEN_NOT_txfun_inF_first_ETC___d454 + SLICE_X108Y160.X Tilo 0.601 ftop/gbe0/gmac/txfun_inF_DEQ + ftop/gbe0/gmac/txfun_inF_DEQ + SLICE_X108Y158.G1 net (fanout=7) 0.413 ftop/gbe0/gmac/txfun_inF_DEQ + SLICE_X108Y158.Y Tilo 0.616 ftop/gbe0/gmac/txfun_inF/N01 + ftop/gbe0/gmac/txfun_inF/d0d11 + SLICE_X103Y147.G2 net (fanout=40) 1.476 ftop/gbe0/gmac/txfun_inF/d0d1 + SLICE_X103Y147.Y Tilo 0.561 ftop/gbe0/gmac/txfun_inF/N42 + ftop/gbe0/gmac/txfun_inF/data0_reg_or0000<33>_SW0 + SLICE_X102Y147.SR net (fanout=1) 1.168 ftop/gbe0/gmac/txfun_inF/N26 + SLICE_X102Y147.CLK Tsrck 0.433 ftop/gbe0/gmac/txfun_inF_D_OUT<33> + ftop/gbe0/gmac/txfun_inF/data0_reg_33 + ------------------------------------------------- --------------------------- + Total 7.638ns (3.734ns logic, 3.904ns route) + (48.9% logic, 51.1% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.279ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/txfun_inF/data0_reg_18 (FF) + Destination: ftop/gbe0/gmac/txfun_inF/data0_reg_33 (FF) + Requirement: 8.000ns + Data Path Delay: 7.584ns (Levels of Logic = 5) + Clock Path Skew: -0.137ns (0.348 - 0.485) + Source Clock: ftop/gmiixo_clk_O rising at 0.000ns + Destination Clock: ftop/gmiixo_clk_O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Maximum Data Path: ftop/gbe0/gmac/txfun_inF/data0_reg_18 to ftop/gbe0/gmac/txfun_inF/data0_reg_33 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X108Y161.YQ Tcko 0.596 ftop/gbe0/gmac/txfun_inF_D_OUT<18> + ftop/gbe0/gmac/txfun_inF/data0_reg_18 + SLICE_X109Y163.F1 net (fanout=5) 0.443 ftop/gbe0/gmac/txfun_inF_D_OUT<18> + SLICE_X109Y163.F5 Tif5 0.688 ftop/gbe0/gmac/Mmux_IF_txfun_ptr_0_EQ_0_1_THEN_NOT_txfun_inF_first_ETC___d454_4 + ftop/gbe0/gmac/Mmux_IF_txfun_ptr_0_EQ_0_1_THEN_NOT_txfun_inF_first_ETC___d454_not00021 + ftop/gbe0/gmac/Mmux_IF_txfun_ptr_0_EQ_0_1_THEN_NOT_txfun_inF_first_ETC___d454_4 + SLICE_X109Y162.FXINB net (fanout=1) 0.000 ftop/gbe0/gmac/Mmux_IF_txfun_ptr_0_EQ_0_1_THEN_NOT_txfun_inF_first_ETC___d454_4 + SLICE_X109Y162.Y Tif6y 0.239 ftop/gbe0/gmac/IF_txfun_ptr_0_EQ_0_1_THEN_NOT_txfun_inF_first_ETC___d454 + ftop/gbe0/gmac/Mmux_IF_txfun_ptr_0_EQ_0_1_THEN_NOT_txfun_inF_first_ETC___d454_2_f5 + SLICE_X108Y160.F3 net (fanout=3) 0.256 ftop/gbe0/gmac/IF_txfun_ptr_0_EQ_0_1_THEN_NOT_txfun_inF_first_ETC___d454 + SLICE_X108Y160.X Tilo 0.601 ftop/gbe0/gmac/txfun_inF_DEQ + ftop/gbe0/gmac/txfun_inF_DEQ + SLICE_X109Y160.G4 net (fanout=7) 0.082 ftop/gbe0/gmac/txfun_inF_DEQ + SLICE_X109Y160.Y Tilo 0.561 ftop/gbe0/gmac/txfun_inF/N2 + ftop/gbe0/gmac/txfun_inF/d0h1 + SLICE_X103Y147.G4 net (fanout=40) 1.956 ftop/gbe0/gmac/txfun_inF/d0h + SLICE_X103Y147.Y Tilo 0.561 ftop/gbe0/gmac/txfun_inF/N42 + ftop/gbe0/gmac/txfun_inF/data0_reg_or0000<33>_SW0 + SLICE_X102Y147.SR net (fanout=1) 1.168 ftop/gbe0/gmac/txfun_inF/N26 + SLICE_X102Y147.CLK Tsrck 0.433 ftop/gbe0/gmac/txfun_inF_D_OUT<33> + ftop/gbe0/gmac/txfun_inF/data0_reg_33 + ------------------------------------------------- --------------------------- + Total 7.584ns (3.679ns logic, 3.905ns route) + (48.5% logic, 51.5% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.293ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/gmac/txRS_txF/dNotEmptyReg (FF) + Destination: ftop/gbe0/gmac/gmac/txRS_lenCnt_value_11 (FF) + Requirement: 8.000ns + Data Path Delay: 7.524ns (Levels of Logic = 4) + Clock Path Skew: -0.183ns (0.216 - 0.399) + Source Clock: ftop/gmiixo_clk_O rising at 0.000ns + Destination Clock: ftop/gmiixo_clk_O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Maximum Data Path: ftop/gbe0/gmac/gmac/txRS_txF/dNotEmptyReg to ftop/gbe0/gmac/gmac/txRS_lenCnt_value_11 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X103Y186.YQ Tcko 0.524 ftop/gbe0/gmac/gmac/txRS_txF_dEMPTY_N + ftop/gbe0/gmac/gmac/txRS_txF/dNotEmptyReg + SLICE_X106Y189.G2 net (fanout=8) 0.749 ftop/gbe0/gmac/gmac/txRS_txF_dEMPTY_N + SLICE_X106Y189.Y Tilo 0.616 ftop/gbe0/gmac/gmac/N16 + ftop/gbe0/gmac/gmac/txRS_txData_D_IN<7>212 + SLICE_X102Y189.G1 net (fanout=17) 1.094 ftop/gbe0/gmac/gmac/N29 + SLICE_X102Y189.Y Tilo 0.616 ftop/gbe0/gmac/gmac/txRS_crc_EN_add + ftop/gbe0/gmac/gmac/txRS_crc_add_data<0>111 + SLICE_X99Y187.G1 net (fanout=3) 0.648 ftop/gbe0/gmac/gmac/N36 + SLICE_X99Y187.Y Tilo 0.561 ftop/gbe0/gmac/gmac/txRS_lenCnt_value_EN + ftop/gbe0/gmac/gmac/txRS_lenCnt_value_EN_SW0 + SLICE_X99Y187.F4 net (fanout=1) 0.022 ftop/gbe0/gmac/gmac/txRS_lenCnt_value_EN_SW0/O + SLICE_X99Y187.X Tilo 0.562 ftop/gbe0/gmac/gmac/txRS_lenCnt_value_EN + ftop/gbe0/gmac/gmac/txRS_lenCnt_value_EN + SLICE_X86Y190.CE net (fanout=7) 1.977 ftop/gbe0/gmac/gmac/txRS_lenCnt_value_EN + SLICE_X86Y190.CLK Tceck 0.155 ftop/gbe0/gmac/gmac/txRS_lenCnt_value<11> + ftop/gbe0/gmac/gmac/txRS_lenCnt_value_11 + ------------------------------------------------- --------------------------- + Total 7.524ns (3.034ns logic, 4.490ns route) + (40.3% logic, 59.7% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.293ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/gmac/txRS_txF/dNotEmptyReg (FF) + Destination: ftop/gbe0/gmac/gmac/txRS_lenCnt_value_10 (FF) + Requirement: 8.000ns + Data Path Delay: 7.524ns (Levels of Logic = 4) + Clock Path Skew: -0.183ns (0.216 - 0.399) + Source Clock: ftop/gmiixo_clk_O rising at 0.000ns + Destination Clock: ftop/gmiixo_clk_O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Maximum Data Path: ftop/gbe0/gmac/gmac/txRS_txF/dNotEmptyReg to ftop/gbe0/gmac/gmac/txRS_lenCnt_value_10 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X103Y186.YQ Tcko 0.524 ftop/gbe0/gmac/gmac/txRS_txF_dEMPTY_N + ftop/gbe0/gmac/gmac/txRS_txF/dNotEmptyReg + SLICE_X106Y189.G2 net (fanout=8) 0.749 ftop/gbe0/gmac/gmac/txRS_txF_dEMPTY_N + SLICE_X106Y189.Y Tilo 0.616 ftop/gbe0/gmac/gmac/N16 + ftop/gbe0/gmac/gmac/txRS_txData_D_IN<7>212 + SLICE_X102Y189.G1 net (fanout=17) 1.094 ftop/gbe0/gmac/gmac/N29 + SLICE_X102Y189.Y Tilo 0.616 ftop/gbe0/gmac/gmac/txRS_crc_EN_add + ftop/gbe0/gmac/gmac/txRS_crc_add_data<0>111 + SLICE_X99Y187.G1 net (fanout=3) 0.648 ftop/gbe0/gmac/gmac/N36 + SLICE_X99Y187.Y Tilo 0.561 ftop/gbe0/gmac/gmac/txRS_lenCnt_value_EN + ftop/gbe0/gmac/gmac/txRS_lenCnt_value_EN_SW0 + SLICE_X99Y187.F4 net (fanout=1) 0.022 ftop/gbe0/gmac/gmac/txRS_lenCnt_value_EN_SW0/O + SLICE_X99Y187.X Tilo 0.562 ftop/gbe0/gmac/gmac/txRS_lenCnt_value_EN + ftop/gbe0/gmac/gmac/txRS_lenCnt_value_EN + SLICE_X86Y190.CE net (fanout=7) 1.977 ftop/gbe0/gmac/gmac/txRS_lenCnt_value_EN + SLICE_X86Y190.CLK Tceck 0.155 ftop/gbe0/gmac/gmac/txRS_lenCnt_value<11> + ftop/gbe0/gmac/gmac/txRS_lenCnt_value_10 + ------------------------------------------------- --------------------------- + Total 7.524ns (3.034ns logic, 4.490ns route) + (40.3% logic, 59.7% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.303ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/gmac/txRS_ifgCnt_value_0 (FF) + Destination: ftop/gbe0/gmac/gmac/txRS_crc/rRemainder_8 (FF) + Requirement: 8.000ns + Data Path Delay: 7.644ns (Levels of Logic = 6) + Clock Path Skew: -0.053ns (0.360 - 0.413) + Source Clock: ftop/gmiixo_clk_O rising at 0.000ns + Destination Clock: ftop/gmiixo_clk_O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Maximum Data Path: ftop/gbe0/gmac/gmac/txRS_ifgCnt_value_0 to ftop/gbe0/gmac/gmac/txRS_crc/rRemainder_8 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X105Y190.YQ Tcko 0.524 ftop/gbe0/gmac/gmac/txRS_ifgCnt_value<1> + ftop/gbe0/gmac/gmac/txRS_ifgCnt_value_0 + SLICE_X104Y188.G1 net (fanout=5) 0.738 ftop/gbe0/gmac/gmac/txRS_ifgCnt_value<0> + SLICE_X104Y188.Y Tilo 0.616 ftop/gbe0/gmac/gmac/N34 + ftop/gbe0/gmac/gmac/txRS_ifgCnt_value_D_IN<2>11 + SLICE_X104Y188.F4 net (fanout=2) 0.057 ftop/gbe0/gmac/gmac/N40 + SLICE_X104Y188.X Tilo 0.601 ftop/gbe0/gmac/gmac/N34 + ftop/gbe0/gmac/gmac/txRS_txData_D_IN<7>222 + SLICE_X105Y188.G4 net (fanout=10) 0.143 ftop/gbe0/gmac/gmac/N34 + SLICE_X105Y188.Y Tilo 0.561 ftop/gbe0/gmac/gmac/txRS_crc_add_data<0> + ftop/gbe0/gmac/gmac/MUX_txRS_crc_add_1__SEL_11 + SLICE_X105Y184.F2 net (fanout=11) 0.662 ftop/gbe0/gmac/gmac/MUX_txRS_crc_add_1__SEL_1 + SLICE_X105Y184.X Tilo 0.562 ftop/gbe0/gmac/gmac/txRS_crc_add_data<4> + ftop/gbe0/gmac/gmac/txRS_crc_add_data<4>1 + SLICE_X111Y182.G4 net (fanout=5) 1.008 ftop/gbe0/gmac/gmac/txRS_crc_add_data<4> + SLICE_X111Y182.Y Tilo 0.561 ftop/gbe0/gmac/gmac/txRS_crc/rRemainder<4> + ftop/gbe0/gmac/gmac/txRS_crc/IF_IF_IF_IF_IF_rRemainder_XOR_rwAddIn_wget_BIT_ETC___d366<1>1 + SLICE_X109Y186.F1 net (fanout=5) 1.009 ftop/gbe0/gmac/gmac/txRS_crc/IF_IF_IF_IF_IF_rRemainder_XOR_rwAddIn_wget_BIT_ETC___d366<1> + SLICE_X109Y186.CLK Tfck 0.602 ftop/gbe0/gmac/gmac/txRS_crc/rRemainder<8> + ftop/gbe0/gmac/gmac/txRS_crc/rRemainder_D_IN<8> + ftop/gbe0/gmac/gmac/txRS_crc/rRemainder_8 + ------------------------------------------------- --------------------------- + Total 7.644ns (4.027ns logic, 3.617ns route) + (52.7% logic, 47.3% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.312ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/txfun_inF/data0_reg_19 (FF) + Destination: ftop/gbe0/gmac/txfun_inF/data0_reg_5 (FF) + Requirement: 8.000ns + Data Path Delay: 7.618ns (Levels of Logic = 5) + Clock Path Skew: -0.070ns (0.363 - 0.433) + Source Clock: ftop/gmiixo_clk_O rising at 0.000ns + Destination Clock: ftop/gmiixo_clk_O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Maximum Data Path: ftop/gbe0/gmac/txfun_inF/data0_reg_19 to ftop/gbe0/gmac/txfun_inF/data0_reg_5 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X106Y157.YQ Tcko 0.596 ftop/gbe0/gmac/txfun_inF_D_OUT<19> + ftop/gbe0/gmac/txfun_inF/data0_reg_19 + SLICE_X109Y163.F3 net (fanout=5) 0.591 ftop/gbe0/gmac/txfun_inF_D_OUT<19> + SLICE_X109Y163.F5 Tif5 0.688 ftop/gbe0/gmac/Mmux_IF_txfun_ptr_0_EQ_0_1_THEN_NOT_txfun_inF_first_ETC___d454_4 + ftop/gbe0/gmac/Mmux_IF_txfun_ptr_0_EQ_0_1_THEN_NOT_txfun_inF_first_ETC___d454_not00021 + ftop/gbe0/gmac/Mmux_IF_txfun_ptr_0_EQ_0_1_THEN_NOT_txfun_inF_first_ETC___d454_4 + SLICE_X109Y162.FXINB net (fanout=1) 0.000 ftop/gbe0/gmac/Mmux_IF_txfun_ptr_0_EQ_0_1_THEN_NOT_txfun_inF_first_ETC___d454_4 + SLICE_X109Y162.Y Tif6y 0.239 ftop/gbe0/gmac/IF_txfun_ptr_0_EQ_0_1_THEN_NOT_txfun_inF_first_ETC___d454 + ftop/gbe0/gmac/Mmux_IF_txfun_ptr_0_EQ_0_1_THEN_NOT_txfun_inF_first_ETC___d454_2_f5 + SLICE_X108Y160.F3 net (fanout=3) 0.256 ftop/gbe0/gmac/IF_txfun_ptr_0_EQ_0_1_THEN_NOT_txfun_inF_first_ETC___d454 + SLICE_X108Y160.X Tilo 0.601 ftop/gbe0/gmac/txfun_inF_DEQ + ftop/gbe0/gmac/txfun_inF_DEQ + SLICE_X108Y158.G1 net (fanout=7) 0.413 ftop/gbe0/gmac/txfun_inF_DEQ + SLICE_X108Y158.Y Tilo 0.616 ftop/gbe0/gmac/txfun_inF/N01 + ftop/gbe0/gmac/txfun_inF/d0d11 + SLICE_X108Y149.G2 net (fanout=40) 1.604 ftop/gbe0/gmac/txfun_inF/d0d1 + SLICE_X108Y149.Y Tilo 0.616 ftop/gbe0/gmac/txfun_inF/N66 + ftop/gbe0/gmac/txfun_inF/data0_reg_or0000<5>_SW0 + SLICE_X109Y149.SR net (fanout=1) 0.965 ftop/gbe0/gmac/txfun_inF/N8 + SLICE_X109Y149.CLK Tsrck 0.433 ftop/gbe0/gmac/txfun_inF_D_OUT<5> + ftop/gbe0/gmac/txfun_inF/data0_reg_5 + ------------------------------------------------- --------------------------- + Total 7.618ns (3.789ns logic, 3.829ns route) + (49.7% logic, 50.3% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.314ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/gmac/txRS_ifgCnt_value_0 (FF) + Destination: ftop/gbe0/gmac/gmac/txRS_crc/rRemainder_10 (FF) + Requirement: 8.000ns + Data Path Delay: 7.640ns (Levels of Logic = 7) + Clock Path Skew: -0.046ns (0.367 - 0.413) + Source Clock: ftop/gmiixo_clk_O rising at 0.000ns + Destination Clock: ftop/gmiixo_clk_O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Maximum Data Path: ftop/gbe0/gmac/gmac/txRS_ifgCnt_value_0 to ftop/gbe0/gmac/gmac/txRS_crc/rRemainder_10 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X105Y190.YQ Tcko 0.524 ftop/gbe0/gmac/gmac/txRS_ifgCnt_value<1> + ftop/gbe0/gmac/gmac/txRS_ifgCnt_value_0 + SLICE_X104Y188.G1 net (fanout=5) 0.738 ftop/gbe0/gmac/gmac/txRS_ifgCnt_value<0> + SLICE_X104Y188.Y Tilo 0.616 ftop/gbe0/gmac/gmac/N34 + ftop/gbe0/gmac/gmac/txRS_ifgCnt_value_D_IN<2>11 + SLICE_X104Y188.F4 net (fanout=2) 0.057 ftop/gbe0/gmac/gmac/N40 + SLICE_X104Y188.X Tilo 0.601 ftop/gbe0/gmac/gmac/N34 + ftop/gbe0/gmac/gmac/txRS_txData_D_IN<7>222 + SLICE_X105Y188.G4 net (fanout=10) 0.143 ftop/gbe0/gmac/gmac/N34 + SLICE_X105Y188.Y Tilo 0.561 ftop/gbe0/gmac/gmac/txRS_crc_add_data<0> + ftop/gbe0/gmac/gmac/MUX_txRS_crc_add_1__SEL_11 + SLICE_X106Y183.F1 net (fanout=11) 0.707 ftop/gbe0/gmac/gmac/MUX_txRS_crc_add_1__SEL_1 + SLICE_X106Y183.X Tilo 0.601 ftop/gbe0/gmac/gmac/txRS_crc_add_data<2> + ftop/gbe0/gmac/gmac/txRS_crc_add_data<2>1 + SLICE_X111Y184.G1 net (fanout=10) 0.954 ftop/gbe0/gmac/gmac/txRS_crc_add_data<2> + SLICE_X111Y184.Y Tilo 0.561 ftop/gbe0/gmac/gmac/txRS_crc/N81 + ftop/gbe0/gmac/gmac/txRS_crc/IF_IF_IF_rRemainder_XOR_rwAddIn_wget_BIT_0_CON_ETC___d364<1>1 + SLICE_X111Y184.F4 net (fanout=4) 0.321 ftop/gbe0/gmac/gmac/txRS_crc/IF_IF_IF_rRemainder_XOR_rwAddIn_wget_BIT_0_CON_ETC___d364<1> + SLICE_X111Y184.X Tilo 0.562 ftop/gbe0/gmac/gmac/txRS_crc/N81 + ftop/gbe0/gmac/gmac/txRS_crc/rRemainder_D_IN<10>_SW0_SW0 + SLICE_X110Y185.G3 net (fanout=1) 0.023 ftop/gbe0/gmac/gmac/txRS_crc/N81 + SLICE_X110Y185.CLK Tgck 0.671 ftop/gbe0/gmac/gmac/txRS_crc/rRemainder<26> + ftop/gbe0/gmac/gmac/txRS_crc/rRemainder_D_IN<10> + ftop/gbe0/gmac/gmac/txRS_crc/rRemainder_10 + ------------------------------------------------- --------------------------- + Total 7.640ns (4.697ns logic, 2.943ns route) + (61.5% logic, 38.5% route) + +-------------------------------------------------------------------------------- + +Hold Paths: TS_GMIISYSCLK = PERIOD TIMEGRP "GMIISYSCLK" 8 ns HIGH 50%; +-------------------------------------------------------------------------------- +Slack (hold path): 0.643ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/rxfun_sr_18 (FF) + Destination: ftop/gbe0/gmac/rxfun_outF/data1_reg_18 (FF) + Requirement: 0.000ns + Data Path Delay: 0.880ns (Levels of Logic = 0) + Clock Path Skew: 0.237ns (0.811 - 0.574) + Source Clock: ftop/gmiixo_clk_O rising at 8.000ns + Destination Clock: ftop/gmiixo_clk_O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path: ftop/gbe0/gmac/rxfun_sr_18 to ftop/gbe0/gmac/rxfun_outF/data1_reg_18 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X103Y73.YQ Tcko 0.419 ftop/gbe0/gmac/rxfun_sr<19> + ftop/gbe0/gmac/rxfun_sr_18 + SLICE_X102Y70.BY net (fanout=3) 0.324 ftop/gbe0/gmac/rxfun_sr<18> + SLICE_X102Y70.CLK Tckdi (-Th) -0.137 ftop/gbe0/gmac/rxfun_outF/data1_reg<19> + ftop/gbe0/gmac/rxfun_outF/data1_reg_18 + ------------------------------------------------- --------------------------- + Total 0.880ns (0.556ns logic, 0.324ns route) + (63.2% logic, 36.8% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.724ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/rxfun_sr_7 (FF) + Destination: ftop/gbe0/gmac/rxfun_sr_17 (FF) + Requirement: 0.000ns + Data Path Delay: 0.830ns (Levels of Logic = 0) + Clock Path Skew: 0.106ns (0.516 - 0.410) + Source Clock: ftop/gmiixo_clk_O rising at 8.000ns + Destination Clock: ftop/gmiixo_clk_O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path: ftop/gbe0/gmac/rxfun_sr_7 to ftop/gbe0/gmac/rxfun_sr_17 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X101Y70.XQ Tcko 0.396 ftop/gbe0/gmac/rxfun_sr<7> + ftop/gbe0/gmac/rxfun_sr_7 + SLICE_X102Y71.BX net (fanout=3) 0.332 ftop/gbe0/gmac/rxfun_sr<7> + SLICE_X102Y71.CLK Tckdi (-Th) -0.102 ftop/gbe0/gmac/rxfun_sr<17> + ftop/gbe0/gmac/rxfun_sr_17 + ------------------------------------------------- --------------------------- + Total 0.830ns (0.498ns logic, 0.332ns route) + (60.0% logic, 40.0% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.740ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/rxfun_sr_7 (FF) + Destination: ftop/gbe0/gmac/rxfun_outF/data1_reg_27 (FF) + Requirement: 0.000ns + Data Path Delay: 0.759ns (Levels of Logic = 0) + Clock Path Skew: 0.019ns (0.121 - 0.102) + Source Clock: ftop/gmiixo_clk_O rising at 8.000ns + Destination Clock: ftop/gmiixo_clk_O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path: ftop/gbe0/gmac/rxfun_sr_7 to ftop/gbe0/gmac/rxfun_outF/data1_reg_27 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X101Y70.XQ Tcko 0.396 ftop/gbe0/gmac/rxfun_sr<7> + ftop/gbe0/gmac/rxfun_sr_7 + SLICE_X101Y71.BX net (fanout=3) 0.301 ftop/gbe0/gmac/rxfun_sr<7> + SLICE_X101Y71.CLK Tckdi (-Th) -0.062 ftop/gbe0/gmac/rxfun_outF/data1_reg<27> + ftop/gbe0/gmac/rxfun_outF/data1_reg_27 + ------------------------------------------------- --------------------------- + Total 0.759ns (0.458ns logic, 0.301ns route) + (60.3% logic, 39.7% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.742ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/gmac/txRS_txF/dSyncReg1_3 (FF) + Destination: ftop/gbe0/gmac/gmac/txRS_txF/dEnqPtr_3 (FF) + Requirement: 0.000ns + Data Path Delay: 0.745ns (Levels of Logic = 0) + Clock Path Skew: 0.003ns (0.025 - 0.022) + Source Clock: ftop/gmiixo_clk_O rising at 8.000ns + Destination Clock: ftop/gmiixo_clk_O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path: ftop/gbe0/gmac/gmac/txRS_txF/dSyncReg1_3 to ftop/gbe0/gmac/gmac/txRS_txF/dEnqPtr_3 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X105Y180.XQ Tcko 0.396 ftop/gbe0/gmac/gmac/txRS_txF/dSyncReg1<3> + ftop/gbe0/gmac/gmac/txRS_txF/dSyncReg1_3 + SLICE_X105Y181.BX net (fanout=1) 0.287 ftop/gbe0/gmac/gmac/txRS_txF/dSyncReg1<3> + SLICE_X105Y181.CLK Tckdi (-Th) -0.062 ftop/gbe0/gmac/gmac/txRS_txF/dEnqPtr<3> + ftop/gbe0/gmac/gmac/txRS_txF/dEnqPtr_3 + ------------------------------------------------- --------------------------- + Total 0.745ns (0.458ns logic, 0.287ns route) + (61.5% logic, 38.5% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.744ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/rxF/sSyncReg1_1 (FF) + Destination: ftop/gbe0/gmac/rxF/sDeqPtr_1 (FF) + Requirement: 0.000ns + Data Path Delay: 0.745ns (Levels of Logic = 0) + Clock Path Skew: 0.001ns (0.010 - 0.009) + Source Clock: ftop/gmiixo_clk_O rising at 8.000ns + Destination Clock: ftop/gmiixo_clk_O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path: ftop/gbe0/gmac/rxF/sSyncReg1_1 to ftop/gbe0/gmac/rxF/sDeqPtr_1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X97Y60.XQ Tcko 0.396 ftop/gbe0/gmac/rxF/sSyncReg1<1> + ftop/gbe0/gmac/rxF/sSyncReg1_1 + SLICE_X97Y61.BX net (fanout=1) 0.287 ftop/gbe0/gmac/rxF/sSyncReg1<1> + SLICE_X97Y61.CLK Tckdi (-Th) -0.062 ftop/gbe0/gmac/rxF/sDeqPtr<1> + ftop/gbe0/gmac/rxF/sDeqPtr_1 + ------------------------------------------------- --------------------------- + Total 0.745ns (0.458ns logic, 0.287ns route) + (61.5% logic, 38.5% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.757ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/rxfun_sr_23 (FF) + Destination: ftop/gbe0/gmac/rxfun_outF/data1_reg_3 (FF) + Requirement: 0.000ns + Data Path Delay: 0.774ns (Levels of Logic = 0) + Clock Path Skew: 0.017ns (0.115 - 0.098) + Source Clock: ftop/gmiixo_clk_O rising at 8.000ns + Destination Clock: ftop/gmiixo_clk_O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path: ftop/gbe0/gmac/rxfun_sr_23 to ftop/gbe0/gmac/rxfun_outF/data1_reg_3 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X103Y66.XQ Tcko 0.396 ftop/gbe0/gmac/rxfun_sr<23> + ftop/gbe0/gmac/rxfun_sr_23 + SLICE_X103Y67.BX net (fanout=2) 0.316 ftop/gbe0/gmac/rxfun_sr<23> + SLICE_X103Y67.CLK Tckdi (-Th) -0.062 ftop/gbe0/gmac/rxfun_outF/data1_reg<3> + ftop/gbe0/gmac/rxfun_outF/data1_reg_3 + ------------------------------------------------- --------------------------- + Total 0.774ns (0.458ns logic, 0.316ns route) + (59.2% logic, 40.8% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.758ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/gmac/rxRS_rxF/dSyncReg1_3 (FF) + Destination: ftop/gbe0/gmac/gmac/rxRS_rxF/dEnqPtr_3 (FF) + Requirement: 0.000ns + Data Path Delay: 0.795ns (Levels of Logic = 0) + Clock Path Skew: 0.037ns (0.414 - 0.377) + Source Clock: ftop/gmiixo_clk_O rising at 8.000ns + Destination Clock: ftop/gmiixo_clk_O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path: ftop/gbe0/gmac/gmac/rxRS_rxF/dSyncReg1_3 to ftop/gbe0/gmac/gmac/rxRS_rxF/dEnqPtr_3 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X109Y130.XQ Tcko 0.396 ftop/gbe0/gmac/gmac/rxRS_rxF/dSyncReg1<3> + ftop/gbe0/gmac/gmac/rxRS_rxF/dSyncReg1_3 + SLICE_X106Y130.BX net (fanout=1) 0.297 ftop/gbe0/gmac/gmac/rxRS_rxF/dSyncReg1<3> + SLICE_X106Y130.CLK Tckdi (-Th) -0.102 ftop/gbe0/gmac/gmac/rxRS_rxF/dEnqPtr<3> + ftop/gbe0/gmac/gmac/rxRS_rxF/dEnqPtr_3 + ------------------------------------------------- --------------------------- + Total 0.795ns (0.498ns logic, 0.297ns route) + (62.6% logic, 37.4% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.761ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/gmac/txRS_txF/sSyncReg1_1 (FF) + Destination: ftop/gbe0/gmac/gmac/txRS_txF/sDeqPtr_1 (FF) + Requirement: 0.000ns + Data Path Delay: 0.766ns (Levels of Logic = 0) + Clock Path Skew: 0.005ns (0.035 - 0.030) + Source Clock: ftop/gmiixo_clk_O rising at 8.000ns + Destination Clock: ftop/gmiixo_clk_O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path: ftop/gbe0/gmac/gmac/txRS_txF/sSyncReg1_1 to ftop/gbe0/gmac/gmac/txRS_txF/sDeqPtr_1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X110Y176.XQ Tcko 0.417 ftop/gbe0/gmac/gmac/txRS_txF/sSyncReg1<1> + ftop/gbe0/gmac/gmac/txRS_txF/sSyncReg1_1 + SLICE_X111Y176.BX net (fanout=1) 0.287 ftop/gbe0/gmac/gmac/txRS_txF/sSyncReg1<1> + SLICE_X111Y176.CLK Tckdi (-Th) -0.062 ftop/gbe0/gmac/gmac/txRS_txF/sDeqPtr<1> + ftop/gbe0/gmac/gmac/txRS_txF/sDeqPtr_1 + ------------------------------------------------- --------------------------- + Total 0.766ns (0.479ns logic, 0.287ns route) + (62.5% logic, 37.5% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.762ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/rxfun_sr_9 (FF) + Destination: ftop/gbe0/gmac/rxfun_sr_19 (FF) + Requirement: 0.000ns + Data Path Delay: 0.821ns (Levels of Logic = 0) + Clock Path Skew: 0.059ns (0.427 - 0.368) + Source Clock: ftop/gmiixo_clk_O rising at 8.000ns + Destination Clock: ftop/gmiixo_clk_O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path: ftop/gbe0/gmac/rxfun_sr_9 to ftop/gbe0/gmac/rxfun_sr_19 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X104Y72.XQ Tcko 0.417 ftop/gbe0/gmac/rxfun_sr<9> + ftop/gbe0/gmac/rxfun_sr_9 + SLICE_X103Y73.BX net (fanout=3) 0.342 ftop/gbe0/gmac/rxfun_sr<9> + SLICE_X103Y73.CLK Tckdi (-Th) -0.062 ftop/gbe0/gmac/rxfun_sr<19> + ftop/gbe0/gmac/rxfun_sr_19 + ------------------------------------------------- --------------------------- + Total 0.821ns (0.479ns logic, 0.342ns route) + (58.3% logic, 41.7% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.763ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/rxfun_sr_29 (FF) + Destination: ftop/gbe0/gmac/rxfun_outF/data1_reg_9 (FF) + Requirement: 0.000ns + Data Path Delay: 0.777ns (Levels of Logic = 0) + Clock Path Skew: 0.014ns (0.094 - 0.080) + Source Clock: ftop/gmiixo_clk_O rising at 8.000ns + Destination Clock: ftop/gmiixo_clk_O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path: ftop/gbe0/gmac/rxfun_sr_29 to ftop/gbe0/gmac/rxfun_outF/data1_reg_9 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X105Y65.XQ Tcko 0.396 ftop/gbe0/gmac/rxfun_sr<29> + ftop/gbe0/gmac/rxfun_sr_29 + SLICE_X105Y64.BX net (fanout=2) 0.319 ftop/gbe0/gmac/rxfun_sr<29> + SLICE_X105Y64.CLK Tckdi (-Th) -0.062 ftop/gbe0/gmac/rxfun_outF/data1_reg<9> + ftop/gbe0/gmac/rxfun_outF/data1_reg_9 + ------------------------------------------------- --------------------------- + Total 0.777ns (0.458ns logic, 0.319ns route) + (58.9% logic, 41.1% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.765ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/gmac/rxRS_rxF/dSyncReg1_1 (FF) + Destination: ftop/gbe0/gmac/gmac/rxRS_rxF/dEnqPtr_1 (FF) + Requirement: 0.000ns + Data Path Delay: 0.766ns (Levels of Logic = 0) + Clock Path Skew: 0.001ns (0.007 - 0.006) + Source Clock: ftop/gmiixo_clk_O rising at 8.000ns + Destination Clock: ftop/gmiixo_clk_O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path: ftop/gbe0/gmac/gmac/rxRS_rxF/dSyncReg1_1 to ftop/gbe0/gmac/gmac/rxRS_rxF/dEnqPtr_1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X106Y116.XQ Tcko 0.417 ftop/gbe0/gmac/gmac/rxRS_rxF/dSyncReg1<1> + ftop/gbe0/gmac/gmac/rxRS_rxF/dSyncReg1_1 + SLICE_X107Y117.BX net (fanout=1) 0.287 ftop/gbe0/gmac/gmac/rxRS_rxF/dSyncReg1<1> + SLICE_X107Y117.CLK Tckdi (-Th) -0.062 ftop/gbe0/gmac/gmac/rxRS_rxF/dEnqPtr<1> + ftop/gbe0/gmac/gmac/rxRS_rxF/dEnqPtr_1 + ------------------------------------------------- --------------------------- + Total 0.766ns (0.479ns logic, 0.287ns route) + (62.5% logic, 37.5% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.765ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/rxF/sSyncReg1_3 (FF) + Destination: ftop/gbe0/gmac/rxF/sDeqPtr_3 (FF) + Requirement: 0.000ns + Data Path Delay: 0.766ns (Levels of Logic = 0) + Clock Path Skew: 0.001ns (0.003 - 0.002) + Source Clock: ftop/gmiixo_clk_O rising at 8.000ns + Destination Clock: ftop/gmiixo_clk_O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path: ftop/gbe0/gmac/rxF/sSyncReg1_3 to ftop/gbe0/gmac/rxF/sDeqPtr_3 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X96Y57.XQ Tcko 0.417 ftop/gbe0/gmac/rxF/sSyncReg1<3> + ftop/gbe0/gmac/rxF/sSyncReg1_3 + SLICE_X97Y57.BX net (fanout=1) 0.287 ftop/gbe0/gmac/rxF/sSyncReg1<3> + SLICE_X97Y57.CLK Tckdi (-Th) -0.062 ftop/gbe0/gmac/rxF/sDeqPtr<3> + ftop/gbe0/gmac/rxF/sDeqPtr_3 + ------------------------------------------------- --------------------------- + Total 0.766ns (0.479ns logic, 0.287ns route) + (62.5% logic, 37.5% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.765ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/rxfun_sr_21 (FF) + Destination: ftop/gbe0/gmac/rxfun_outF/data1_reg_1 (FF) + Requirement: 0.000ns + Data Path Delay: 0.822ns (Levels of Logic = 0) + Clock Path Skew: 0.057ns (0.424 - 0.367) + Source Clock: ftop/gmiixo_clk_O rising at 8.000ns + Destination Clock: ftop/gmiixo_clk_O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path: ftop/gbe0/gmac/rxfun_sr_21 to ftop/gbe0/gmac/rxfun_outF/data1_reg_1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X111Y60.XQ Tcko 0.396 ftop/gbe0/gmac/rxfun_sr<21> + ftop/gbe0/gmac/rxfun_sr_21 + SLICE_X108Y61.BX net (fanout=2) 0.324 ftop/gbe0/gmac/rxfun_sr<21> + SLICE_X108Y61.CLK Tckdi (-Th) -0.102 ftop/gbe0/gmac/rxfun_outF/data1_reg<1> + ftop/gbe0/gmac/rxfun_outF/data1_reg_1 + ------------------------------------------------- --------------------------- + Total 0.822ns (0.498ns logic, 0.324ns route) + (60.6% logic, 39.4% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.775ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/rxfun_outF/data0_reg_31 (FF) + Destination: ftop/gbe0/gmac/rxF/Mram_fifoMem32.SLICEM_G (RAM) + Requirement: 0.000ns + Data Path Delay: 1.006ns (Levels of Logic = 1) + Clock Path Skew: 0.231ns (0.805 - 0.574) + Source Clock: ftop/gmiixo_clk_O rising at 8.000ns + Destination Clock: ftop/gmiixo_clk_O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path: ftop/gbe0/gmac/rxfun_outF/data0_reg_31 to ftop/gbe0/gmac/rxF/Mram_fifoMem32.SLICEM_G + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X102Y73.YQ Tcko 0.477 ftop/gbe0/gmac/rxfun_outF_D_OUT<31> + ftop/gbe0/gmac/rxfun_outF/data0_reg_31 + SLICE_X104Y68.BY net (fanout=2) 0.659 ftop/gbe0/gmac/rxfun_outF_D_OUT<31> + SLICE_X104Y68.CLK Tdh (-Th) 0.130 ftop/gbe0/gmac/rxF/_varindex0000<31> + ftop/gbe0/gmac/rxF/Mram_fifoMem32.SLICEM_G + ------------------------------------------------- --------------------------- + Total 1.006ns (0.347ns logic, 0.659ns route) + (34.5% logic, 65.5% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.776ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/rxfun_outF/data0_reg_31 (FF) + Destination: ftop/gbe0/gmac/rxF/Mram_fifoMem32.SLICEM_F (RAM) + Requirement: 0.000ns + Data Path Delay: 1.007ns (Levels of Logic = 1) + Clock Path Skew: 0.231ns (0.805 - 0.574) + Source Clock: ftop/gmiixo_clk_O rising at 8.000ns + Destination Clock: ftop/gmiixo_clk_O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path: ftop/gbe0/gmac/rxfun_outF/data0_reg_31 to ftop/gbe0/gmac/rxF/Mram_fifoMem32.SLICEM_F + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X102Y73.YQ Tcko 0.477 ftop/gbe0/gmac/rxfun_outF_D_OUT<31> + ftop/gbe0/gmac/rxfun_outF/data0_reg_31 + SLICE_X104Y68.BY net (fanout=2) 0.659 ftop/gbe0/gmac/rxfun_outF_D_OUT<31> + SLICE_X104Y68.CLK Tdh (-Th) 0.129 ftop/gbe0/gmac/rxF/_varindex0000<31> + ftop/gbe0/gmac/rxF/Mram_fifoMem32.SLICEM_F + ------------------------------------------------- --------------------------- + Total 1.007ns (0.348ns logic, 0.659ns route) + (34.6% logic, 65.4% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.778ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/rxF/sGEnqPtr1_0 (FF) + Destination: ftop/gbe0/gmac/rxF/sGEnqPtr_0 (FF) + Requirement: 0.000ns + Data Path Delay: 0.882ns (Levels of Logic = 0) + Clock Path Skew: 0.104ns (0.425 - 0.321) + Source Clock: ftop/gmiixo_clk_O rising at 8.000ns + Destination Clock: ftop/gmiixo_clk_O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path: ftop/gbe0/gmac/rxF/sGEnqPtr1_0 to ftop/gbe0/gmac/rxF/sGEnqPtr_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X99Y62.XQ Tcko 0.396 ftop/gbe0/gmac/rxF/sGEnqPtr1<0> + ftop/gbe0/gmac/rxF/sGEnqPtr1_0 + SLICE_X101Y62.BY net (fanout=6) 0.364 ftop/gbe0/gmac/rxF/sGEnqPtr1<0> + SLICE_X101Y62.CLK Tckdi (-Th) -0.122 ftop/gbe0/gmac/rxF/sGEnqPtr<1> + ftop/gbe0/gmac/rxF/sGEnqPtr_0 + ------------------------------------------------- --------------------------- + Total 0.882ns (0.518ns logic, 0.364ns route) + (58.7% logic, 41.3% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.778ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/txOper/dSyncReg1 (FF) + Destination: ftop/gbe0/gmac/txOper/dSyncReg2 (FF) + Requirement: 0.000ns + Data Path Delay: 0.846ns (Levels of Logic = 0) + Clock Path Skew: 0.068ns (0.339 - 0.271) + Source Clock: ftop/gmiixo_clk_O rising at 8.000ns + Destination Clock: ftop/gmiixo_clk_O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path: ftop/gbe0/gmac/txOper/dSyncReg1 to ftop/gbe0/gmac/txOper/dSyncReg2 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X97Y187.YQ Tcko 0.419 ftop/gbe0/gmac/txOper/dSyncReg1 + ftop/gbe0/gmac/txOper/dSyncReg1 + SLICE_X99Y186.BY net (fanout=1) 0.305 ftop/gbe0/gmac/txOper/dSyncReg1 + SLICE_X99Y186.CLK Tckdi (-Th) -0.122 ftop/gbe0/gmac/txOper_dD_OUT + ftop/gbe0/gmac/txOper/dSyncReg2 + ------------------------------------------------- --------------------------- + Total 0.846ns (0.541ns logic, 0.305ns route) + (63.9% logic, 36.1% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.779ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/txF/dSyncReg1_1 (FF) + Destination: ftop/gbe0/gmac/txF/dEnqPtr_1 (FF) + Requirement: 0.000ns + Data Path Delay: 0.785ns (Levels of Logic = 0) + Clock Path Skew: 0.006ns (0.041 - 0.035) + Source Clock: ftop/gmiixo_clk_O rising at 8.000ns + Destination Clock: ftop/gmiixo_clk_O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path: ftop/gbe0/gmac/txF/dSyncReg1_1 to ftop/gbe0/gmac/txF/dEnqPtr_1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X103Y131.XQ Tcko 0.396 ftop/gbe0/gmac/txF/dSyncReg1<1> + ftop/gbe0/gmac/txF/dSyncReg1_1 + SLICE_X102Y131.BX net (fanout=1) 0.287 ftop/gbe0/gmac/txF/dSyncReg1<1> + SLICE_X102Y131.CLK Tckdi (-Th) -0.102 ftop/gbe0/gmac/txF/dEnqPtr<1> + ftop/gbe0/gmac/txF/dEnqPtr_1 + ------------------------------------------------- --------------------------- + Total 0.785ns (0.498ns logic, 0.287ns route) + (63.4% logic, 36.6% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.785ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/rxF/sGEnqPtr_2 (FF) + Destination: ftop/gbe0/gmac/rxF/Mram_fifoMem39.SLICEM_G (RAM) + Requirement: 0.000ns + Data Path Delay: 0.870ns (Levels of Logic = 1) + Clock Path Skew: 0.085ns (0.386 - 0.301) + Source Clock: ftop/gmiixo_clk_O rising at 8.000ns + Destination Clock: ftop/gmiixo_clk_O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path: ftop/gbe0/gmac/rxF/sGEnqPtr_2 to ftop/gbe0/gmac/rxF/Mram_fifoMem39.SLICEM_G + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X99Y58.YQ Tcko 0.419 ftop/gbe0/gmac/rxF/sGEnqPtr<3> + ftop/gbe0/gmac/rxF/sGEnqPtr_2 + SLICE_X100Y58.G3 net (fanout=43) 0.452 ftop/gbe0/gmac/rxF/sGEnqPtr<2> + SLICE_X100Y58.CLK Tah (-Th) 0.001 ftop/gbe0/gmac/rxF/_varindex0000<38> + ftop/gbe0/gmac/rxF/Mram_fifoMem39.SLICEM_G + ------------------------------------------------- --------------------------- + Total 0.870ns (0.418ns logic, 0.452ns route) + (48.0% logic, 52.0% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.785ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/rxF/sGEnqPtr_2 (FF) + Destination: ftop/gbe0/gmac/rxF/Mram_fifoMem39.SLICEM_F (RAM) + Requirement: 0.000ns + Data Path Delay: 0.870ns (Levels of Logic = 1) + Clock Path Skew: 0.085ns (0.386 - 0.301) + Source Clock: ftop/gmiixo_clk_O rising at 8.000ns + Destination Clock: ftop/gmiixo_clk_O rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path: ftop/gbe0/gmac/rxF/sGEnqPtr_2 to ftop/gbe0/gmac/rxF/Mram_fifoMem39.SLICEM_F + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X99Y58.YQ Tcko 0.419 ftop/gbe0/gmac/rxF/sGEnqPtr<3> + ftop/gbe0/gmac/rxF/sGEnqPtr_2 + SLICE_X100Y58.G3 net (fanout=43) 0.452 ftop/gbe0/gmac/rxF/sGEnqPtr<2> + SLICE_X100Y58.CLK Tah (-Th) 0.001 ftop/gbe0/gmac/rxF/_varindex0000<38> + ftop/gbe0/gmac/rxF/Mram_fifoMem39.SLICEM_F + ------------------------------------------------- --------------------------- + Total 0.870ns (0.418ns logic, 0.452ns route) + (48.0% logic, 52.0% route) + +-------------------------------------------------------------------------------- + +Component Switching Limit Checks: TS_GMIISYSCLK = PERIOD TIMEGRP "GMIISYSCLK" 8 ns HIGH 50%; +-------------------------------------------------------------------------------- +Slack: 5.344ns (period - (min low pulse limit / (low pulse / period))) + Period: 8.000ns + Low pulse: 4.000ns + Low pulse limit: 1.328ns (Trpw) + Physical resource: ftop/gbe0/gmac/gmac_RDY_tx_put/SR + Logical resource: ftop/gbe0/gmac/gmac/txRS_txF/sNotFullReg/SR + Location pin: SLICE_X106Y179.SR + Clock network: ftop/gmiixo_rst_OUT_RST +-------------------------------------------------------------------------------- +Slack: 5.344ns (period - (min high pulse limit / (high pulse / period))) + Period: 8.000ns + High pulse: 4.000ns + High pulse limit: 1.328ns (Trpw) + Physical resource: ftop/gbe0/gmac/gmac_RDY_tx_put/SR + Logical resource: ftop/gbe0/gmac/gmac/txRS_txF/sNotFullReg/SR + Location pin: SLICE_X106Y179.SR + Clock network: ftop/gmiixo_rst_OUT_RST +-------------------------------------------------------------------------------- +Slack: 5.344ns (period - (min low pulse limit / (low pulse / period))) + Period: 8.000ns + Low pulse: 4.000ns + Low pulse limit: 1.328ns (Trpw) + Physical resource: ftop/gbe0/gmac/txF/dGDeqPtr1<4>/SR + Logical resource: ftop/gbe0/gmac/txF/dGDeqPtr1_4/SR + Location pin: SLICE_X100Y126.SR + Clock network: ftop/sys1Rst +-------------------------------------------------------------------------------- +Slack: 5.344ns (period - (min high pulse limit / (high pulse / period))) + Period: 8.000ns + High pulse: 4.000ns + High pulse limit: 1.328ns (Trpw) + Physical resource: ftop/gbe0/gmac/txF/dGDeqPtr1<4>/SR + Logical resource: ftop/gbe0/gmac/txF/dGDeqPtr1_4/SR + Location pin: SLICE_X100Y126.SR + Clock network: ftop/sys1Rst +-------------------------------------------------------------------------------- +Slack: 5.344ns (period - (min low pulse limit / (low pulse / period))) + Period: 8.000ns + Low pulse: 4.000ns + Low pulse limit: 1.328ns (Trpw) + Physical resource: ftop/gbe0/gmac/gmac/txRS_txF/dSyncReg1<1>/SR + Logical resource: ftop/gbe0/gmac/gmac/txRS_txF/dSyncReg1_1/SR + Location pin: SLICE_X102Y180.SR + Clock network: ftop/gmiixo_rst_OUT_RST +-------------------------------------------------------------------------------- +Slack: 5.344ns (period - (min high pulse limit / (high pulse / period))) + Period: 8.000ns + High pulse: 4.000ns + High pulse limit: 1.328ns (Trpw) + Physical resource: ftop/gbe0/gmac/gmac/txRS_txF/dSyncReg1<1>/SR + Logical resource: ftop/gbe0/gmac/gmac/txRS_txF/dSyncReg1_1/SR + Location pin: SLICE_X102Y180.SR + Clock network: ftop/gmiixo_rst_OUT_RST +-------------------------------------------------------------------------------- +Slack: 5.344ns (period - (min low pulse limit / (low pulse / period))) + Period: 8.000ns + Low pulse: 4.000ns + Low pulse limit: 1.328ns (Trpw) + Physical resource: ftop/gbe0/gmac/gmac/txRS_txF/dSyncReg1<1>/SR + Logical resource: ftop/gbe0/gmac/gmac/txRS_txF/dSyncReg1_0/SR + Location pin: SLICE_X102Y180.SR + Clock network: ftop/gmiixo_rst_OUT_RST +-------------------------------------------------------------------------------- +Slack: 5.344ns (period - (min high pulse limit / (high pulse / period))) + Period: 8.000ns + High pulse: 4.000ns + High pulse limit: 1.328ns (Trpw) + Physical resource: ftop/gbe0/gmac/gmac/txRS_txF/dSyncReg1<1>/SR + Logical resource: ftop/gbe0/gmac/gmac/txRS_txF/dSyncReg1_0/SR + Location pin: SLICE_X102Y180.SR + Clock network: ftop/gmiixo_rst_OUT_RST +-------------------------------------------------------------------------------- +Slack: 5.344ns (period - (min low pulse limit / (low pulse / period))) + Period: 8.000ns + Low pulse: 4.000ns + Low pulse limit: 1.328ns (Trpw) + Physical resource: ftop/gbe0/gmac/gmac/txRS_txF/dSyncReg1<4>/SR + Logical resource: ftop/gbe0/gmac/gmac/txRS_txF/dSyncReg1_4/SR + Location pin: SLICE_X104Y180.SR + Clock network: ftop/gmiixo_rst_OUT_RST +-------------------------------------------------------------------------------- +Slack: 5.344ns (period - (min high pulse limit / (high pulse / period))) + Period: 8.000ns + High pulse: 4.000ns + High pulse limit: 1.328ns (Trpw) + Physical resource: ftop/gbe0/gmac/gmac/txRS_txF/dSyncReg1<4>/SR + Logical resource: ftop/gbe0/gmac/gmac/txRS_txF/dSyncReg1_4/SR + Location pin: SLICE_X104Y180.SR + Clock network: ftop/gmiixo_rst_OUT_RST +-------------------------------------------------------------------------------- +Slack: 5.344ns (period - (min low pulse limit / (low pulse / period))) + Period: 8.000ns + Low pulse: 4.000ns + Low pulse limit: 1.328ns (Trpw) + Physical resource: ftop/gbe0/gmac/gmac/txRS_txF/dGDeqPtr<5>/SR + Logical resource: ftop/gbe0/gmac/gmac/txRS_txF/dGDeqPtr_5/SR + Location pin: SLICE_X102Y183.SR + Clock network: ftop/gmiixo_rst_OUT_RST +-------------------------------------------------------------------------------- +Slack: 5.344ns (period - (min high pulse limit / (high pulse / period))) + Period: 8.000ns + High pulse: 4.000ns + High pulse limit: 1.328ns (Trpw) + Physical resource: ftop/gbe0/gmac/gmac/txRS_txF/dGDeqPtr<5>/SR + Logical resource: ftop/gbe0/gmac/gmac/txRS_txF/dGDeqPtr_5/SR + Location pin: SLICE_X102Y183.SR + Clock network: ftop/gmiixo_rst_OUT_RST +-------------------------------------------------------------------------------- +Slack: 5.344ns (period - (min low pulse limit / (low pulse / period))) + Period: 8.000ns + Low pulse: 4.000ns + Low pulse limit: 1.328ns (Trpw) + Physical resource: ftop/gbe0/gmac/gmac/txRS_txF/dGDeqPtr<5>/SR + Logical resource: ftop/gbe0/gmac/gmac/txRS_txF/dGDeqPtr_4/SR + Location pin: SLICE_X102Y183.SR + Clock network: ftop/gmiixo_rst_OUT_RST +-------------------------------------------------------------------------------- +Slack: 5.344ns (period - (min high pulse limit / (high pulse / period))) + Period: 8.000ns + High pulse: 4.000ns + High pulse limit: 1.328ns (Trpw) + Physical resource: ftop/gbe0/gmac/gmac/txRS_txF/dGDeqPtr<5>/SR + Logical resource: ftop/gbe0/gmac/gmac/txRS_txF/dGDeqPtr_4/SR + Location pin: SLICE_X102Y183.SR + Clock network: ftop/gmiixo_rst_OUT_RST +-------------------------------------------------------------------------------- +Slack: 5.344ns (period - (min low pulse limit / (low pulse / period))) + Period: 8.000ns + Low pulse: 4.000ns + Low pulse limit: 1.328ns (Trpw) + Physical resource: ftop/gbe0/gmac/gmac/rxRS_rxOperateS/sSyncReg/SR + Logical resource: ftop/gbe0/gmac/gmac/rxRS_rxOperateS/sSyncReg/SR + Location pin: SLICE_X106Y172.SR + Clock network: ftop/gmiixo_rst_OUT_RST +-------------------------------------------------------------------------------- +Slack: 5.344ns (period - (min high pulse limit / (high pulse / period))) + Period: 8.000ns + High pulse: 4.000ns + High pulse limit: 1.328ns (Trpw) + Physical resource: ftop/gbe0/gmac/gmac/rxRS_rxOperateS/sSyncReg/SR + Logical resource: ftop/gbe0/gmac/gmac/rxRS_rxOperateS/sSyncReg/SR + Location pin: SLICE_X106Y172.SR + Clock network: ftop/gmiixo_rst_OUT_RST +-------------------------------------------------------------------------------- +Slack: 5.344ns (period - (min low pulse limit / (low pulse / period))) + Period: 8.000ns + Low pulse: 4.000ns + Low pulse limit: 1.328ns (Trpw) + Physical resource: ftop/gbe0/gmac/gmac/txRS_txF/dGDeqPtr1<3>/SR + Logical resource: ftop/gbe0/gmac/gmac/txRS_txF/dGDeqPtr1_3/SR + Location pin: SLICE_X102Y184.SR + Clock network: ftop/gmiixo_rst_OUT_RST +-------------------------------------------------------------------------------- +Slack: 5.344ns (period - (min high pulse limit / (high pulse / period))) + Period: 8.000ns + High pulse: 4.000ns + High pulse limit: 1.328ns (Trpw) + Physical resource: ftop/gbe0/gmac/gmac/txRS_txF/dGDeqPtr1<3>/SR + Logical resource: ftop/gbe0/gmac/gmac/txRS_txF/dGDeqPtr1_3/SR + Location pin: SLICE_X102Y184.SR + Clock network: ftop/gmiixo_rst_OUT_RST +-------------------------------------------------------------------------------- +Slack: 5.344ns (period - (min low pulse limit / (low pulse / period))) + Period: 8.000ns + Low pulse: 4.000ns + Low pulse limit: 1.328ns (Trpw) + Physical resource: ftop/gbe0/gmac/gmac/txRS_txF/dGDeqPtr1<3>/SR + Logical resource: ftop/gbe0/gmac/gmac/txRS_txF/dGDeqPtr1_2/SR + Location pin: SLICE_X102Y184.SR + Clock network: ftop/gmiixo_rst_OUT_RST +-------------------------------------------------------------------------------- +Slack: 5.344ns (period - (min high pulse limit / (high pulse / period))) + Period: 8.000ns + High pulse: 4.000ns + High pulse limit: 1.328ns (Trpw) + Physical resource: ftop/gbe0/gmac/gmac/txRS_txF/dGDeqPtr1<3>/SR + Logical resource: ftop/gbe0/gmac/gmac/txRS_txF/dGDeqPtr1_2/SR + Location pin: SLICE_X102Y184.SR + Clock network: ftop/gmiixo_rst_OUT_RST +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: TS_GMIIRXCLK = PERIOD TIMEGRP "GMIIRXCLK" 8 ns HIGH 50%; +For more information, see Period Analysis in the Timing Closure User Guide (UG612). + + 2541 paths analyzed, 474 endpoints analyzed, 0 failing endpoints + 0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors) + Minimum period is 7.816ns. +-------------------------------------------------------------------------------- +Slack (setup path): 0.184ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/gmac/rxRS_rxOperateS/dSyncReg2 (FF) + Destination: ftop/gbe0/gmac/gmac/rxRS_rxF/Mram_fifoMem9.WE (RAM) + Requirement: 8.000ns + Data Path Delay: 7.697ns (Levels of Logic = 3) + Clock Path Skew: -0.119ns (0.553 - 0.672) + Source Clock: gmii_rx_clk_BUFGP rising at 0.000ns + Destination Clock: gmii_rx_clk_BUFGP rising at 8.000ns + Clock Uncertainty: 0.000ns + + Maximum Data Path: ftop/gbe0/gmac/gmac/rxRS_rxOperateS/dSyncReg2 to ftop/gbe0/gmac/gmac/rxRS_rxF/Mram_fifoMem9.WE + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X103Y159.YQ Tcko 0.524 ftop/gbe0/gmac/gmac/rxRS_rxOperateS_dD_OUT + ftop/gbe0/gmac/gmac/rxRS_rxOperateS/dSyncReg2 + SLICE_X106Y147.F4 net (fanout=20) 1.636 ftop/gbe0/gmac/gmac/rxRS_rxOperateS_dD_OUT + SLICE_X106Y147.X Tilo 0.601 ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1116 + ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1116 + SLICE_X106Y144.G1 net (fanout=2) 0.639 ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1116 + SLICE_X106Y144.Y Tilo 0.616 ftop/gbe0/gmac/gmac/rxRS_rxF_sENQ + ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_12 + SLICE_X106Y144.F4 net (fanout=11) 0.038 ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1 + SLICE_X106Y144.X Tilo 0.601 ftop/gbe0/gmac/gmac/rxRS_rxF_sENQ + ftop/gbe0/gmac/gmac/rxRS_rxF_sENQ + SLICE_X104Y123.SR net (fanout=17) 2.750 ftop/gbe0/gmac/gmac/rxRS_rxF_sENQ + SLICE_X104Y123.CLK Tws 0.292 ftop/gbe0/gmac/gmac/rxRS_rxF/_varindex0000<8> + ftop/gbe0/gmac/gmac/rxRS_rxF/Mram_fifoMem9.WE + ------------------------------------------------- --------------------------- + Total 7.697ns (2.634ns logic, 5.063ns route) + (34.2% logic, 65.8% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.646ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/gmac/rxRS_rxOperateS/dSyncReg2 (FF) + Destination: ftop/gbe0/gmac/gmac/rxRS_rxF/Mram_fifoMem5.WE (RAM) + Requirement: 8.000ns + Data Path Delay: 7.246ns (Levels of Logic = 3) + Clock Path Skew: -0.108ns (0.564 - 0.672) + Source Clock: gmii_rx_clk_BUFGP rising at 0.000ns + Destination Clock: gmii_rx_clk_BUFGP rising at 8.000ns + Clock Uncertainty: 0.000ns + + Maximum Data Path: ftop/gbe0/gmac/gmac/rxRS_rxOperateS/dSyncReg2 to ftop/gbe0/gmac/gmac/rxRS_rxF/Mram_fifoMem5.WE + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X103Y159.YQ Tcko 0.524 ftop/gbe0/gmac/gmac/rxRS_rxOperateS_dD_OUT + ftop/gbe0/gmac/gmac/rxRS_rxOperateS/dSyncReg2 + SLICE_X106Y147.F4 net (fanout=20) 1.636 ftop/gbe0/gmac/gmac/rxRS_rxOperateS_dD_OUT + SLICE_X106Y147.X Tilo 0.601 ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1116 + ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1116 + SLICE_X106Y144.G1 net (fanout=2) 0.639 ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1116 + SLICE_X106Y144.Y Tilo 0.616 ftop/gbe0/gmac/gmac/rxRS_rxF_sENQ + ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_12 + SLICE_X106Y144.F4 net (fanout=11) 0.038 ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1 + SLICE_X106Y144.X Tilo 0.601 ftop/gbe0/gmac/gmac/rxRS_rxF_sENQ + ftop/gbe0/gmac/gmac/rxRS_rxF_sENQ + SLICE_X108Y120.SR net (fanout=17) 2.299 ftop/gbe0/gmac/gmac/rxRS_rxF_sENQ + SLICE_X108Y120.CLK Tws 0.292 ftop/gbe0/gmac/gmac/rxRS_rxF/_varindex0000<4> + ftop/gbe0/gmac/gmac/rxRS_rxF/Mram_fifoMem5.WE + ------------------------------------------------- --------------------------- + Total 7.246ns (2.634ns logic, 4.612ns route) + (36.4% logic, 63.6% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.712ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/gmac/rxRS_crcEnd (FF) + Destination: ftop/gbe0/gmac/gmac/rxRS_rxF/Mram_fifoMem9.WE (RAM) + Requirement: 8.000ns + Data Path Delay: 7.119ns (Levels of Logic = 4) + Clock Path Skew: -0.169ns (0.553 - 0.722) + Source Clock: gmii_rx_clk_BUFGP rising at 0.000ns + Destination Clock: gmii_rx_clk_BUFGP rising at 8.000ns + Clock Uncertainty: 0.000ns + + Maximum Data Path: ftop/gbe0/gmac/gmac/rxRS_crcEnd to ftop/gbe0/gmac/gmac/rxRS_rxF/Mram_fifoMem9.WE + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X109Y147.YQ Tcko 0.524 ftop/gbe0/gmac/gmac/rxRS_crcEnd + ftop/gbe0/gmac/gmac/rxRS_crcEnd + SLICE_X106Y147.G2 net (fanout=2) 0.421 ftop/gbe0/gmac/gmac/rxRS_crcEnd + SLICE_X106Y147.Y Tilo 0.616 ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1116 + ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1113 + SLICE_X106Y147.F3 net (fanout=1) 0.021 ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1113/O + SLICE_X106Y147.X Tilo 0.601 ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1116 + ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1116 + SLICE_X106Y144.G1 net (fanout=2) 0.639 ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1116 + SLICE_X106Y144.Y Tilo 0.616 ftop/gbe0/gmac/gmac/rxRS_rxF_sENQ + ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_12 + SLICE_X106Y144.F4 net (fanout=11) 0.038 ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1 + SLICE_X106Y144.X Tilo 0.601 ftop/gbe0/gmac/gmac/rxRS_rxF_sENQ + ftop/gbe0/gmac/gmac/rxRS_rxF_sENQ + SLICE_X104Y123.SR net (fanout=17) 2.750 ftop/gbe0/gmac/gmac/rxRS_rxF_sENQ + SLICE_X104Y123.CLK Tws 0.292 ftop/gbe0/gmac/gmac/rxRS_rxF/_varindex0000<8> + ftop/gbe0/gmac/gmac/rxRS_rxF/Mram_fifoMem9.WE + ------------------------------------------------- --------------------------- + Total 7.119ns (3.250ns logic, 3.869ns route) + (45.7% logic, 54.3% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.757ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/gmac/rxRS_rxAPipe_3 (FF) + Destination: ftop/gbe0/gmac/gmac/rxRS_rxF/Mram_fifoMem9.WE (RAM) + Requirement: 8.000ns + Data Path Delay: 7.111ns (Levels of Logic = 4) + Clock Path Skew: -0.132ns (0.553 - 0.685) + Source Clock: gmii_rx_clk_BUFGP rising at 0.000ns + Destination Clock: gmii_rx_clk_BUFGP rising at 8.000ns + Clock Uncertainty: 0.000ns + + Maximum Data Path: ftop/gbe0/gmac/gmac/rxRS_rxAPipe_3 to ftop/gbe0/gmac/gmac/rxRS_rxF/Mram_fifoMem9.WE + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X104Y147.XQ Tcko 0.521 ftop/gbe0/gmac/gmac/rxRS_rxAPipe<3> + ftop/gbe0/gmac/gmac/rxRS_rxAPipe_3 + SLICE_X106Y147.G4 net (fanout=4) 0.416 ftop/gbe0/gmac/gmac/rxRS_rxAPipe<3> + SLICE_X106Y147.Y Tilo 0.616 ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1116 + ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1113 + SLICE_X106Y147.F3 net (fanout=1) 0.021 ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1113/O + SLICE_X106Y147.X Tilo 0.601 ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1116 + ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1116 + SLICE_X106Y144.G1 net (fanout=2) 0.639 ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1116 + SLICE_X106Y144.Y Tilo 0.616 ftop/gbe0/gmac/gmac/rxRS_rxF_sENQ + ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_12 + SLICE_X106Y144.F4 net (fanout=11) 0.038 ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1 + SLICE_X106Y144.X Tilo 0.601 ftop/gbe0/gmac/gmac/rxRS_rxF_sENQ + ftop/gbe0/gmac/gmac/rxRS_rxF_sENQ + SLICE_X104Y123.SR net (fanout=17) 2.750 ftop/gbe0/gmac/gmac/rxRS_rxF_sENQ + SLICE_X104Y123.CLK Tws 0.292 ftop/gbe0/gmac/gmac/rxRS_rxF/_varindex0000<8> + ftop/gbe0/gmac/gmac/rxRS_rxF/Mram_fifoMem9.WE + ------------------------------------------------- --------------------------- + Total 7.111ns (3.247ns logic, 3.864ns route) + (45.7% logic, 54.3% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.909ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/gmac/rxRS_rxOperateS/dSyncReg2 (FF) + Destination: ftop/gbe0/gmac/gmac/rxRS_rxF/Mram_fifoMem4.WE (RAM) + Requirement: 8.000ns + Data Path Delay: 6.986ns (Levels of Logic = 3) + Clock Path Skew: -0.105ns (0.567 - 0.672) + Source Clock: gmii_rx_clk_BUFGP rising at 0.000ns + Destination Clock: gmii_rx_clk_BUFGP rising at 8.000ns + Clock Uncertainty: 0.000ns + + Maximum Data Path: ftop/gbe0/gmac/gmac/rxRS_rxOperateS/dSyncReg2 to ftop/gbe0/gmac/gmac/rxRS_rxF/Mram_fifoMem4.WE + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X103Y159.YQ Tcko 0.524 ftop/gbe0/gmac/gmac/rxRS_rxOperateS_dD_OUT + ftop/gbe0/gmac/gmac/rxRS_rxOperateS/dSyncReg2 + SLICE_X106Y147.F4 net (fanout=20) 1.636 ftop/gbe0/gmac/gmac/rxRS_rxOperateS_dD_OUT + SLICE_X106Y147.X Tilo 0.601 ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1116 + ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1116 + SLICE_X106Y144.G1 net (fanout=2) 0.639 ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1116 + SLICE_X106Y144.Y Tilo 0.616 ftop/gbe0/gmac/gmac/rxRS_rxF_sENQ + ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_12 + SLICE_X106Y144.F4 net (fanout=11) 0.038 ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1 + SLICE_X106Y144.X Tilo 0.601 ftop/gbe0/gmac/gmac/rxRS_rxF_sENQ + ftop/gbe0/gmac/gmac/rxRS_rxF_sENQ + SLICE_X106Y124.SR net (fanout=17) 2.039 ftop/gbe0/gmac/gmac/rxRS_rxF_sENQ + SLICE_X106Y124.CLK Tws 0.292 ftop/gbe0/gmac/gmac/rxRS_rxF/_varindex0000<3> + ftop/gbe0/gmac/gmac/rxRS_rxF/Mram_fifoMem4.WE + ------------------------------------------------- --------------------------- + Total 6.986ns (2.634ns logic, 4.352ns route) + (37.7% logic, 62.3% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.913ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/gmac/rxRS_rxOperateS/dSyncReg2 (FF) + Destination: ftop/gbe0/gmac/gmac/rxRS_rxF/Mram_fifoMem6.WE (RAM) + Requirement: 8.000ns + Data Path Delay: 6.978ns (Levels of Logic = 3) + Clock Path Skew: -0.109ns (0.563 - 0.672) + Source Clock: gmii_rx_clk_BUFGP rising at 0.000ns + Destination Clock: gmii_rx_clk_BUFGP rising at 8.000ns + Clock Uncertainty: 0.000ns + + Maximum Data Path: ftop/gbe0/gmac/gmac/rxRS_rxOperateS/dSyncReg2 to ftop/gbe0/gmac/gmac/rxRS_rxF/Mram_fifoMem6.WE + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X103Y159.YQ Tcko 0.524 ftop/gbe0/gmac/gmac/rxRS_rxOperateS_dD_OUT + ftop/gbe0/gmac/gmac/rxRS_rxOperateS/dSyncReg2 + SLICE_X106Y147.F4 net (fanout=20) 1.636 ftop/gbe0/gmac/gmac/rxRS_rxOperateS_dD_OUT + SLICE_X106Y147.X Tilo 0.601 ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1116 + ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1116 + SLICE_X106Y144.G1 net (fanout=2) 0.639 ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1116 + SLICE_X106Y144.Y Tilo 0.616 ftop/gbe0/gmac/gmac/rxRS_rxF_sENQ + ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_12 + SLICE_X106Y144.F4 net (fanout=11) 0.038 ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1 + SLICE_X106Y144.X Tilo 0.601 ftop/gbe0/gmac/gmac/rxRS_rxF_sENQ + ftop/gbe0/gmac/gmac/rxRS_rxF_sENQ + SLICE_X108Y116.SR net (fanout=17) 2.031 ftop/gbe0/gmac/gmac/rxRS_rxF_sENQ + SLICE_X108Y116.CLK Tws 0.292 ftop/gbe0/gmac/gmac/rxRS_rxF/_varindex0000<5> + ftop/gbe0/gmac/gmac/rxRS_rxF/Mram_fifoMem6.WE + ------------------------------------------------- --------------------------- + Total 6.978ns (2.634ns logic, 4.344ns route) + (37.7% logic, 62.3% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.976ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/gmac/rxRS_rxOperateS/dSyncReg2 (FF) + Destination: ftop/gbe0/gmac/gmac/rxRS_rxF/Mram_fifoMem6.SLICEM_F (RAM) + Requirement: 8.000ns + Data Path Delay: 6.915ns (Levels of Logic = 4) + Clock Path Skew: -0.109ns (0.563 - 0.672) + Source Clock: gmii_rx_clk_BUFGP rising at 0.000ns + Destination Clock: gmii_rx_clk_BUFGP rising at 8.000ns + Clock Uncertainty: 0.000ns + + Maximum Data Path: ftop/gbe0/gmac/gmac/rxRS_rxOperateS/dSyncReg2 to ftop/gbe0/gmac/gmac/rxRS_rxF/Mram_fifoMem6.SLICEM_F + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X103Y159.YQ Tcko 0.524 ftop/gbe0/gmac/gmac/rxRS_rxOperateS_dD_OUT + ftop/gbe0/gmac/gmac/rxRS_rxOperateS/dSyncReg2 + SLICE_X106Y147.F4 net (fanout=20) 1.636 ftop/gbe0/gmac/gmac/rxRS_rxOperateS_dD_OUT + SLICE_X106Y147.X Tilo 0.601 ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1116 + ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1116 + SLICE_X106Y144.G1 net (fanout=2) 0.639 ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1116 + SLICE_X106Y144.Y Tilo 0.616 ftop/gbe0/gmac/gmac/rxRS_rxF_sENQ + ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_12 + SLICE_X109Y126.F1 net (fanout=11) 1.379 ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1 + SLICE_X109Y126.X Tilo 0.562 ftop/gbe0/gmac/gmac/rxRS_rxF_sD_IN<5> + ftop/gbe0/gmac/gmac/rxRS_rxF_sD_IN<5>1 + SLICE_X108Y116.BY net (fanout=1) 1.033 ftop/gbe0/gmac/gmac/rxRS_rxF_sD_IN<5> + SLICE_X108Y116.CLK Tds -0.075 ftop/gbe0/gmac/gmac/rxRS_rxF/_varindex0000<5> + ftop/gbe0/gmac/gmac/rxRS_rxF/Mram_fifoMem6.SLICEM_F + ------------------------------------------------- --------------------------- + Total 6.915ns (2.228ns logic, 4.687ns route) + (32.2% logic, 67.8% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.977ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/gmac/rxRS_rxOperateS/dSyncReg2 (FF) + Destination: ftop/gbe0/gmac/gmac/rxRS_rxF/Mram_fifoMem6.SLICEM_G (RAM) + Requirement: 8.000ns + Data Path Delay: 6.914ns (Levels of Logic = 4) + Clock Path Skew: -0.109ns (0.563 - 0.672) + Source Clock: gmii_rx_clk_BUFGP rising at 0.000ns + Destination Clock: gmii_rx_clk_BUFGP rising at 8.000ns + Clock Uncertainty: 0.000ns + + Maximum Data Path: ftop/gbe0/gmac/gmac/rxRS_rxOperateS/dSyncReg2 to ftop/gbe0/gmac/gmac/rxRS_rxF/Mram_fifoMem6.SLICEM_G + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X103Y159.YQ Tcko 0.524 ftop/gbe0/gmac/gmac/rxRS_rxOperateS_dD_OUT + ftop/gbe0/gmac/gmac/rxRS_rxOperateS/dSyncReg2 + SLICE_X106Y147.F4 net (fanout=20) 1.636 ftop/gbe0/gmac/gmac/rxRS_rxOperateS_dD_OUT + SLICE_X106Y147.X Tilo 0.601 ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1116 + ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1116 + SLICE_X106Y144.G1 net (fanout=2) 0.639 ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1116 + SLICE_X106Y144.Y Tilo 0.616 ftop/gbe0/gmac/gmac/rxRS_rxF_sENQ + ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_12 + SLICE_X109Y126.F1 net (fanout=11) 1.379 ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1 + SLICE_X109Y126.X Tilo 0.562 ftop/gbe0/gmac/gmac/rxRS_rxF_sD_IN<5> + ftop/gbe0/gmac/gmac/rxRS_rxF_sD_IN<5>1 + SLICE_X108Y116.BY net (fanout=1) 1.033 ftop/gbe0/gmac/gmac/rxRS_rxF_sD_IN<5> + SLICE_X108Y116.CLK Tds -0.076 ftop/gbe0/gmac/gmac/rxRS_rxF/_varindex0000<5> + ftop/gbe0/gmac/gmac/rxRS_rxF/Mram_fifoMem6.SLICEM_G + ------------------------------------------------- --------------------------- + Total 6.914ns (2.227ns logic, 4.687ns route) + (32.2% logic, 67.8% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 1.131ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/gmac/rxRS_rxOperateS/dSyncReg2 (FF) + Destination: ftop/gbe0/gmac/gmac/rxRS_rxF/Mram_fifoMem3.WE (RAM) + Requirement: 8.000ns + Data Path Delay: 6.749ns (Levels of Logic = 3) + Clock Path Skew: -0.120ns (0.552 - 0.672) + Source Clock: gmii_rx_clk_BUFGP rising at 0.000ns + Destination Clock: gmii_rx_clk_BUFGP rising at 8.000ns + Clock Uncertainty: 0.000ns + + Maximum Data Path: ftop/gbe0/gmac/gmac/rxRS_rxOperateS/dSyncReg2 to ftop/gbe0/gmac/gmac/rxRS_rxF/Mram_fifoMem3.WE + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X103Y159.YQ Tcko 0.524 ftop/gbe0/gmac/gmac/rxRS_rxOperateS_dD_OUT + ftop/gbe0/gmac/gmac/rxRS_rxOperateS/dSyncReg2 + SLICE_X106Y147.F4 net (fanout=20) 1.636 ftop/gbe0/gmac/gmac/rxRS_rxOperateS_dD_OUT + SLICE_X106Y147.X Tilo 0.601 ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1116 + ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1116 + SLICE_X106Y144.G1 net (fanout=2) 0.639 ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1116 + SLICE_X106Y144.Y Tilo 0.616 ftop/gbe0/gmac/gmac/rxRS_rxF_sENQ + ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_12 + SLICE_X106Y144.F4 net (fanout=11) 0.038 ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1 + SLICE_X106Y144.X Tilo 0.601 ftop/gbe0/gmac/gmac/rxRS_rxF_sENQ + ftop/gbe0/gmac/gmac/rxRS_rxF_sENQ + SLICE_X106Y119.SR net (fanout=17) 1.802 ftop/gbe0/gmac/gmac/rxRS_rxF_sENQ + SLICE_X106Y119.CLK Tws 0.292 ftop/gbe0/gmac/gmac/rxRS_rxF/_varindex0000<2> + ftop/gbe0/gmac/gmac/rxRS_rxF/Mram_fifoMem3.WE + ------------------------------------------------- --------------------------- + Total 6.749ns (2.634ns logic, 4.115ns route) + (39.0% logic, 61.0% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 1.147ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/gmac/rxRS_rxOperateS/dSyncReg2 (FF) + Destination: ftop/gbe0/gmac/gmac/rxRS_rxF/Mram_fifoMem2.WE (RAM) + Requirement: 8.000ns + Data Path Delay: 6.762ns (Levels of Logic = 3) + Clock Path Skew: -0.091ns (0.581 - 0.672) + Source Clock: gmii_rx_clk_BUFGP rising at 0.000ns + Destination Clock: gmii_rx_clk_BUFGP rising at 8.000ns + Clock Uncertainty: 0.000ns + + Maximum Data Path: ftop/gbe0/gmac/gmac/rxRS_rxOperateS/dSyncReg2 to ftop/gbe0/gmac/gmac/rxRS_rxF/Mram_fifoMem2.WE + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X103Y159.YQ Tcko 0.524 ftop/gbe0/gmac/gmac/rxRS_rxOperateS_dD_OUT + ftop/gbe0/gmac/gmac/rxRS_rxOperateS/dSyncReg2 + SLICE_X106Y147.F4 net (fanout=20) 1.636 ftop/gbe0/gmac/gmac/rxRS_rxOperateS_dD_OUT + SLICE_X106Y147.X Tilo 0.601 ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1116 + ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1116 + SLICE_X106Y144.G1 net (fanout=2) 0.639 ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1116 + SLICE_X106Y144.Y Tilo 0.616 ftop/gbe0/gmac/gmac/rxRS_rxF_sENQ + ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_12 + SLICE_X106Y144.F4 net (fanout=11) 0.038 ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1 + SLICE_X106Y144.X Tilo 0.601 ftop/gbe0/gmac/gmac/rxRS_rxF_sENQ + ftop/gbe0/gmac/gmac/rxRS_rxF_sENQ + SLICE_X104Y128.SR net (fanout=17) 1.815 ftop/gbe0/gmac/gmac/rxRS_rxF_sENQ + SLICE_X104Y128.CLK Tws 0.292 ftop/gbe0/gmac/gmac/rxRS_rxF/_varindex0000<1> + ftop/gbe0/gmac/gmac/rxRS_rxF/Mram_fifoMem2.WE + ------------------------------------------------- --------------------------- + Total 6.762ns (2.634ns logic, 4.128ns route) + (39.0% logic, 61.0% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 1.147ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/gmac/rxRS_rxOperateS/dSyncReg2 (FF) + Destination: ftop/gbe0/gmac/gmac/rxRS_rxF/Mram_fifoMem7.WE (RAM) + Requirement: 8.000ns + Data Path Delay: 6.762ns (Levels of Logic = 3) + Clock Path Skew: -0.091ns (0.581 - 0.672) + Source Clock: gmii_rx_clk_BUFGP rising at 0.000ns + Destination Clock: gmii_rx_clk_BUFGP rising at 8.000ns + Clock Uncertainty: 0.000ns + + Maximum Data Path: ftop/gbe0/gmac/gmac/rxRS_rxOperateS/dSyncReg2 to ftop/gbe0/gmac/gmac/rxRS_rxF/Mram_fifoMem7.WE + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X103Y159.YQ Tcko 0.524 ftop/gbe0/gmac/gmac/rxRS_rxOperateS_dD_OUT + ftop/gbe0/gmac/gmac/rxRS_rxOperateS/dSyncReg2 + SLICE_X106Y147.F4 net (fanout=20) 1.636 ftop/gbe0/gmac/gmac/rxRS_rxOperateS_dD_OUT + SLICE_X106Y147.X Tilo 0.601 ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1116 + ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1116 + SLICE_X106Y144.G1 net (fanout=2) 0.639 ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1116 + SLICE_X106Y144.Y Tilo 0.616 ftop/gbe0/gmac/gmac/rxRS_rxF_sENQ + ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_12 + SLICE_X106Y144.F4 net (fanout=11) 0.038 ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1 + SLICE_X106Y144.X Tilo 0.601 ftop/gbe0/gmac/gmac/rxRS_rxF_sENQ + ftop/gbe0/gmac/gmac/rxRS_rxF_sENQ + SLICE_X104Y129.SR net (fanout=17) 1.815 ftop/gbe0/gmac/gmac/rxRS_rxF_sENQ + SLICE_X104Y129.CLK Tws 0.292 ftop/gbe0/gmac/gmac/rxRS_rxF/_varindex0000<6> + ftop/gbe0/gmac/gmac/rxRS_rxF/Mram_fifoMem7.WE + ------------------------------------------------- --------------------------- + Total 6.762ns (2.634ns logic, 4.128ns route) + (39.0% logic, 61.0% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 1.161ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/gmac/rxRS_rxOperateS/dSyncReg2 (FF) + Destination: ftop/gbe0/gmac/gmac/rxRS_rxF/Mram_fifoMem8.WE (RAM) + Requirement: 8.000ns + Data Path Delay: 6.757ns (Levels of Logic = 3) + Clock Path Skew: -0.082ns (0.590 - 0.672) + Source Clock: gmii_rx_clk_BUFGP rising at 0.000ns + Destination Clock: gmii_rx_clk_BUFGP rising at 8.000ns + Clock Uncertainty: 0.000ns + + Maximum Data Path: ftop/gbe0/gmac/gmac/rxRS_rxOperateS/dSyncReg2 to ftop/gbe0/gmac/gmac/rxRS_rxF/Mram_fifoMem8.WE + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X103Y159.YQ Tcko 0.524 ftop/gbe0/gmac/gmac/rxRS_rxOperateS_dD_OUT + ftop/gbe0/gmac/gmac/rxRS_rxOperateS/dSyncReg2 + SLICE_X106Y147.F4 net (fanout=20) 1.636 ftop/gbe0/gmac/gmac/rxRS_rxOperateS_dD_OUT + SLICE_X106Y147.X Tilo 0.601 ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1116 + ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1116 + SLICE_X106Y144.G1 net (fanout=2) 0.639 ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1116 + SLICE_X106Y144.Y Tilo 0.616 ftop/gbe0/gmac/gmac/rxRS_rxF_sENQ + ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_12 + SLICE_X106Y144.F4 net (fanout=11) 0.038 ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1 + SLICE_X106Y144.X Tilo 0.601 ftop/gbe0/gmac/gmac/rxRS_rxF_sENQ + ftop/gbe0/gmac/gmac/rxRS_rxF_sENQ + SLICE_X104Y132.SR net (fanout=17) 1.810 ftop/gbe0/gmac/gmac/rxRS_rxF_sENQ + SLICE_X104Y132.CLK Tws 0.292 ftop/gbe0/gmac/gmac/rxRS_rxF/_varindex0000<7> + ftop/gbe0/gmac/gmac/rxRS_rxF/Mram_fifoMem8.WE + ------------------------------------------------- --------------------------- + Total 6.757ns (2.634ns logic, 4.123ns route) + (39.0% logic, 61.0% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 1.174ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/gmac/rxRS_crcEnd (FF) + Destination: ftop/gbe0/gmac/gmac/rxRS_rxF/Mram_fifoMem5.WE (RAM) + Requirement: 8.000ns + Data Path Delay: 6.668ns (Levels of Logic = 4) + Clock Path Skew: -0.158ns (0.564 - 0.722) + Source Clock: gmii_rx_clk_BUFGP rising at 0.000ns + Destination Clock: gmii_rx_clk_BUFGP rising at 8.000ns + Clock Uncertainty: 0.000ns + + Maximum Data Path: ftop/gbe0/gmac/gmac/rxRS_crcEnd to ftop/gbe0/gmac/gmac/rxRS_rxF/Mram_fifoMem5.WE + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X109Y147.YQ Tcko 0.524 ftop/gbe0/gmac/gmac/rxRS_crcEnd + ftop/gbe0/gmac/gmac/rxRS_crcEnd + SLICE_X106Y147.G2 net (fanout=2) 0.421 ftop/gbe0/gmac/gmac/rxRS_crcEnd + SLICE_X106Y147.Y Tilo 0.616 ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1116 + ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1113 + SLICE_X106Y147.F3 net (fanout=1) 0.021 ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1113/O + SLICE_X106Y147.X Tilo 0.601 ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1116 + ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1116 + SLICE_X106Y144.G1 net (fanout=2) 0.639 ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1116 + SLICE_X106Y144.Y Tilo 0.616 ftop/gbe0/gmac/gmac/rxRS_rxF_sENQ + ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_12 + SLICE_X106Y144.F4 net (fanout=11) 0.038 ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1 + SLICE_X106Y144.X Tilo 0.601 ftop/gbe0/gmac/gmac/rxRS_rxF_sENQ + ftop/gbe0/gmac/gmac/rxRS_rxF_sENQ + SLICE_X108Y120.SR net (fanout=17) 2.299 ftop/gbe0/gmac/gmac/rxRS_rxF_sENQ + SLICE_X108Y120.CLK Tws 0.292 ftop/gbe0/gmac/gmac/rxRS_rxF/_varindex0000<4> + ftop/gbe0/gmac/gmac/rxRS_rxF/Mram_fifoMem5.WE + ------------------------------------------------- --------------------------- + Total 6.668ns (3.250ns logic, 3.418ns route) + (48.7% logic, 51.3% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 1.219ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/gmac/rxRS_rxAPipe_3 (FF) + Destination: ftop/gbe0/gmac/gmac/rxRS_rxF/Mram_fifoMem5.WE (RAM) + Requirement: 8.000ns + Data Path Delay: 6.660ns (Levels of Logic = 4) + Clock Path Skew: -0.121ns (0.564 - 0.685) + Source Clock: gmii_rx_clk_BUFGP rising at 0.000ns + Destination Clock: gmii_rx_clk_BUFGP rising at 8.000ns + Clock Uncertainty: 0.000ns + + Maximum Data Path: ftop/gbe0/gmac/gmac/rxRS_rxAPipe_3 to ftop/gbe0/gmac/gmac/rxRS_rxF/Mram_fifoMem5.WE + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X104Y147.XQ Tcko 0.521 ftop/gbe0/gmac/gmac/rxRS_rxAPipe<3> + ftop/gbe0/gmac/gmac/rxRS_rxAPipe_3 + SLICE_X106Y147.G4 net (fanout=4) 0.416 ftop/gbe0/gmac/gmac/rxRS_rxAPipe<3> + SLICE_X106Y147.Y Tilo 0.616 ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1116 + ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1113 + SLICE_X106Y147.F3 net (fanout=1) 0.021 ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1113/O + SLICE_X106Y147.X Tilo 0.601 ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1116 + ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1116 + SLICE_X106Y144.G1 net (fanout=2) 0.639 ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1116 + SLICE_X106Y144.Y Tilo 0.616 ftop/gbe0/gmac/gmac/rxRS_rxF_sENQ + ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_12 + SLICE_X106Y144.F4 net (fanout=11) 0.038 ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1 + SLICE_X106Y144.X Tilo 0.601 ftop/gbe0/gmac/gmac/rxRS_rxF_sENQ + ftop/gbe0/gmac/gmac/rxRS_rxF_sENQ + SLICE_X108Y120.SR net (fanout=17) 2.299 ftop/gbe0/gmac/gmac/rxRS_rxF_sENQ + SLICE_X108Y120.CLK Tws 0.292 ftop/gbe0/gmac/gmac/rxRS_rxF/_varindex0000<4> + ftop/gbe0/gmac/gmac/rxRS_rxF/Mram_fifoMem5.WE + ------------------------------------------------- --------------------------- + Total 6.660ns (3.247ns logic, 3.413ns route) + (48.8% logic, 51.2% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 1.233ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/gmac/rxRS_rxOperateS/dSyncReg2 (FF) + Destination: ftop/gbe0/gmac/gmac/rxRS_rxF/Mram_fifoMem5.SLICEM_F (RAM) + Requirement: 8.000ns + Data Path Delay: 6.659ns (Levels of Logic = 4) + Clock Path Skew: -0.108ns (0.564 - 0.672) + Source Clock: gmii_rx_clk_BUFGP rising at 0.000ns + Destination Clock: gmii_rx_clk_BUFGP rising at 8.000ns + Clock Uncertainty: 0.000ns + + Maximum Data Path: ftop/gbe0/gmac/gmac/rxRS_rxOperateS/dSyncReg2 to ftop/gbe0/gmac/gmac/rxRS_rxF/Mram_fifoMem5.SLICEM_F + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X103Y159.YQ Tcko 0.524 ftop/gbe0/gmac/gmac/rxRS_rxOperateS_dD_OUT + ftop/gbe0/gmac/gmac/rxRS_rxOperateS/dSyncReg2 + SLICE_X106Y147.F4 net (fanout=20) 1.636 ftop/gbe0/gmac/gmac/rxRS_rxOperateS_dD_OUT + SLICE_X106Y147.X Tilo 0.601 ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1116 + ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1116 + SLICE_X106Y144.G1 net (fanout=2) 0.639 ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1116 + SLICE_X106Y144.Y Tilo 0.616 ftop/gbe0/gmac/gmac/rxRS_rxF_sENQ + ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_12 + SLICE_X109Y126.G1 net (fanout=11) 1.383 ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1 + SLICE_X109Y126.Y Tilo 0.561 ftop/gbe0/gmac/gmac/rxRS_rxF_sD_IN<5> + ftop/gbe0/gmac/gmac/rxRS_rxF_sD_IN<4>1 + SLICE_X108Y120.BY net (fanout=1) 0.774 ftop/gbe0/gmac/gmac/rxRS_rxF_sD_IN<4> + SLICE_X108Y120.CLK Tds -0.075 ftop/gbe0/gmac/gmac/rxRS_rxF/_varindex0000<4> + ftop/gbe0/gmac/gmac/rxRS_rxF/Mram_fifoMem5.SLICEM_F + ------------------------------------------------- --------------------------- + Total 6.659ns (2.227ns logic, 4.432ns route) + (33.4% logic, 66.6% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 1.234ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/gmac/rxRS_rxOperateS/dSyncReg2 (FF) + Destination: ftop/gbe0/gmac/gmac/rxRS_rxF/Mram_fifoMem5.SLICEM_G (RAM) + Requirement: 8.000ns + Data Path Delay: 6.658ns (Levels of Logic = 4) + Clock Path Skew: -0.108ns (0.564 - 0.672) + Source Clock: gmii_rx_clk_BUFGP rising at 0.000ns + Destination Clock: gmii_rx_clk_BUFGP rising at 8.000ns + Clock Uncertainty: 0.000ns + + Maximum Data Path: ftop/gbe0/gmac/gmac/rxRS_rxOperateS/dSyncReg2 to ftop/gbe0/gmac/gmac/rxRS_rxF/Mram_fifoMem5.SLICEM_G + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X103Y159.YQ Tcko 0.524 ftop/gbe0/gmac/gmac/rxRS_rxOperateS_dD_OUT + ftop/gbe0/gmac/gmac/rxRS_rxOperateS/dSyncReg2 + SLICE_X106Y147.F4 net (fanout=20) 1.636 ftop/gbe0/gmac/gmac/rxRS_rxOperateS_dD_OUT + SLICE_X106Y147.X Tilo 0.601 ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1116 + ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1116 + SLICE_X106Y144.G1 net (fanout=2) 0.639 ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1116 + SLICE_X106Y144.Y Tilo 0.616 ftop/gbe0/gmac/gmac/rxRS_rxF_sENQ + ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_12 + SLICE_X109Y126.G1 net (fanout=11) 1.383 ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1 + SLICE_X109Y126.Y Tilo 0.561 ftop/gbe0/gmac/gmac/rxRS_rxF_sD_IN<5> + ftop/gbe0/gmac/gmac/rxRS_rxF_sD_IN<4>1 + SLICE_X108Y120.BY net (fanout=1) 0.774 ftop/gbe0/gmac/gmac/rxRS_rxF_sD_IN<4> + SLICE_X108Y120.CLK Tds -0.076 ftop/gbe0/gmac/gmac/rxRS_rxF/_varindex0000<4> + ftop/gbe0/gmac/gmac/rxRS_rxF/Mram_fifoMem5.SLICEM_G + ------------------------------------------------- --------------------------- + Total 6.658ns (2.226ns logic, 4.432ns route) + (33.4% logic, 66.6% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 1.241ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/gmac/rxRS_rxOperateS/dSyncReg2 (FF) + Destination: ftop/gbe0/gmac/gmac/rxRS_rxF/Mram_fifoMem3.SLICEM_F (RAM) + Requirement: 8.000ns + Data Path Delay: 6.639ns (Levels of Logic = 4) + Clock Path Skew: -0.120ns (0.552 - 0.672) + Source Clock: gmii_rx_clk_BUFGP rising at 0.000ns + Destination Clock: gmii_rx_clk_BUFGP rising at 8.000ns + Clock Uncertainty: 0.000ns + + Maximum Data Path: ftop/gbe0/gmac/gmac/rxRS_rxOperateS/dSyncReg2 to ftop/gbe0/gmac/gmac/rxRS_rxF/Mram_fifoMem3.SLICEM_F + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X103Y159.YQ Tcko 0.524 ftop/gbe0/gmac/gmac/rxRS_rxOperateS_dD_OUT + ftop/gbe0/gmac/gmac/rxRS_rxOperateS/dSyncReg2 + SLICE_X106Y147.F4 net (fanout=20) 1.636 ftop/gbe0/gmac/gmac/rxRS_rxOperateS_dD_OUT + SLICE_X106Y147.X Tilo 0.601 ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1116 + ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1116 + SLICE_X106Y144.G1 net (fanout=2) 0.639 ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1116 + SLICE_X106Y144.Y Tilo 0.616 ftop/gbe0/gmac/gmac/rxRS_rxF_sENQ + ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_12 + SLICE_X106Y126.G4 net (fanout=11) 1.320 ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1 + SLICE_X106Y126.Y Tilo 0.616 ftop/gbe0/gmac/gmac/rxRS_rxF_sD_IN<3> + ftop/gbe0/gmac/gmac/rxRS_rxF_sD_IN<2>1 + SLICE_X106Y119.BY net (fanout=1) 0.762 ftop/gbe0/gmac/gmac/rxRS_rxF_sD_IN<2> + SLICE_X106Y119.CLK Tds -0.075 ftop/gbe0/gmac/gmac/rxRS_rxF/_varindex0000<2> + ftop/gbe0/gmac/gmac/rxRS_rxF/Mram_fifoMem3.SLICEM_F + ------------------------------------------------- --------------------------- + Total 6.639ns (2.282ns logic, 4.357ns route) + (34.4% logic, 65.6% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 1.242ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/gmac/rxRS_rxOperateS/dSyncReg2 (FF) + Destination: ftop/gbe0/gmac/gmac/rxRS_rxF/Mram_fifoMem3.SLICEM_G (RAM) + Requirement: 8.000ns + Data Path Delay: 6.638ns (Levels of Logic = 4) + Clock Path Skew: -0.120ns (0.552 - 0.672) + Source Clock: gmii_rx_clk_BUFGP rising at 0.000ns + Destination Clock: gmii_rx_clk_BUFGP rising at 8.000ns + Clock Uncertainty: 0.000ns + + Maximum Data Path: ftop/gbe0/gmac/gmac/rxRS_rxOperateS/dSyncReg2 to ftop/gbe0/gmac/gmac/rxRS_rxF/Mram_fifoMem3.SLICEM_G + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X103Y159.YQ Tcko 0.524 ftop/gbe0/gmac/gmac/rxRS_rxOperateS_dD_OUT + ftop/gbe0/gmac/gmac/rxRS_rxOperateS/dSyncReg2 + SLICE_X106Y147.F4 net (fanout=20) 1.636 ftop/gbe0/gmac/gmac/rxRS_rxOperateS_dD_OUT + SLICE_X106Y147.X Tilo 0.601 ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1116 + ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1116 + SLICE_X106Y144.G1 net (fanout=2) 0.639 ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1116 + SLICE_X106Y144.Y Tilo 0.616 ftop/gbe0/gmac/gmac/rxRS_rxF_sENQ + ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_12 + SLICE_X106Y126.G4 net (fanout=11) 1.320 ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1 + SLICE_X106Y126.Y Tilo 0.616 ftop/gbe0/gmac/gmac/rxRS_rxF_sD_IN<3> + ftop/gbe0/gmac/gmac/rxRS_rxF_sD_IN<2>1 + SLICE_X106Y119.BY net (fanout=1) 0.762 ftop/gbe0/gmac/gmac/rxRS_rxF_sD_IN<2> + SLICE_X106Y119.CLK Tds -0.076 ftop/gbe0/gmac/gmac/rxRS_rxF/_varindex0000<2> + ftop/gbe0/gmac/gmac/rxRS_rxF/Mram_fifoMem3.SLICEM_G + ------------------------------------------------- --------------------------- + Total 6.638ns (2.281ns logic, 4.357ns route) + (34.4% logic, 65.6% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 1.244ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/gmac/rxRS_rxOperateS/dSyncReg2 (FF) + Destination: ftop/gbe0/gmac/gmac/rxRS_crc/rRemainder_11 (FF) + Requirement: 8.000ns + Data Path Delay: 6.653ns (Levels of Logic = 3) + Clock Path Skew: -0.103ns (0.274 - 0.377) + Source Clock: gmii_rx_clk_BUFGP rising at 0.000ns + Destination Clock: gmii_rx_clk_BUFGP rising at 8.000ns + Clock Uncertainty: 0.000ns + + Maximum Data Path: ftop/gbe0/gmac/gmac/rxRS_rxOperateS/dSyncReg2 to ftop/gbe0/gmac/gmac/rxRS_crc/rRemainder_11 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X103Y159.YQ Tcko 0.524 ftop/gbe0/gmac/gmac/rxRS_rxOperateS_dD_OUT + ftop/gbe0/gmac/gmac/rxRS_rxOperateS/dSyncReg2 + SLICE_X106Y147.F4 net (fanout=20) 1.636 ftop/gbe0/gmac/gmac/rxRS_rxOperateS_dD_OUT + SLICE_X106Y147.X Tilo 0.601 ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1116 + ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1116 + SLICE_X107Y144.F3 net (fanout=2) 0.298 ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1116 + SLICE_X107Y144.X Tilo 0.562 ftop/gbe0/gmac/gmac/WILL_FIRE_RL_rxRS_ingress_noadvance + ftop/gbe0/gmac/gmac/WILL_FIRE_RL_rxRS_ingress_noadvance1 + SLICE_X104Y144.F4 net (fanout=34) 0.527 ftop/gbe0/gmac/gmac/WILL_FIRE_RL_rxRS_ingress_noadvance + SLICE_X104Y144.X Tilo 0.601 ftop/gbe0/gmac/gmac/rxRS_crc/rRemainder_EN + ftop/gbe0/gmac/gmac/rxRS_crc/rRemainder_EN1 + SLICE_X95Y143.CE net (fanout=17) 1.749 ftop/gbe0/gmac/gmac/rxRS_crc/rRemainder_EN + SLICE_X95Y143.CLK Tceck 0.155 ftop/gbe0/gmac/gmac/rxRS_crc/rRemainder<11> + ftop/gbe0/gmac/gmac/rxRS_crc/rRemainder_11 + ------------------------------------------------- --------------------------- + Total 6.653ns (2.443ns logic, 4.210ns route) + (36.7% logic, 63.3% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 1.244ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/gbe0/gmac/gmac/rxRS_rxOperateS/dSyncReg2 (FF) + Destination: ftop/gbe0/gmac/gmac/rxRS_crc/rRemainder_10 (FF) + Requirement: 8.000ns + Data Path Delay: 6.653ns (Levels of Logic = 3) + Clock Path Skew: -0.103ns (0.274 - 0.377) + Source Clock: gmii_rx_clk_BUFGP rising at 0.000ns + Destination Clock: gmii_rx_clk_BUFGP rising at 8.000ns + Clock Uncertainty: 0.000ns + + Maximum Data Path: ftop/gbe0/gmac/gmac/rxRS_rxOperateS/dSyncReg2 to ftop/gbe0/gmac/gmac/rxRS_crc/rRemainder_10 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X103Y159.YQ Tcko 0.524 ftop/gbe0/gmac/gmac/rxRS_rxOperateS_dD_OUT + ftop/gbe0/gmac/gmac/rxRS_rxOperateS/dSyncReg2 + SLICE_X106Y147.F4 net (fanout=20) 1.636 ftop/gbe0/gmac/gmac/rxRS_rxOperateS_dD_OUT + SLICE_X106Y147.X Tilo 0.601 ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1116 + ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1116 + SLICE_X107Y144.F3 net (fanout=2) 0.298 ftop/gbe0/gmac/gmac/MUX_rxRS_rxF_enq_1__SEL_1116 + SLICE_X107Y144.X Tilo 0.562 ftop/gbe0/gmac/gmac/WILL_FIRE_RL_rxRS_ingress_noadvance + ftop/gbe0/gmac/gmac/WILL_FIRE_RL_rxRS_ingress_noadvance1 + SLICE_X104Y144.F4 net (fanout=34) 0.527 ftop/gbe0/gmac/gmac/WILL_FIRE_RL_rxRS_ingress_noadvance + SLICE_X104Y144.X Tilo 0.601 ftop/gbe0/gmac/gmac/rxRS_crc/rRemainder_EN + ftop/gbe0/gmac/gmac/rxRS_crc/rRemainder_EN1 + SLICE_X95Y143.CE net (fanout=17) 1.749 ftop/gbe0/gmac/gmac/rxRS_crc/rRemainder_EN + SLICE_X95Y143.CLK Tceck 0.155 ftop/gbe0/gmac/gmac/rxRS_crc/rRemainder<11> + ftop/gbe0/gmac/gmac/rxRS_crc/rRemainder_10 + ------------------------------------------------- --------------------------- + Total 6.653ns (2.443ns logic, 4.210ns route) + (36.7% logic, 63.3% route) + +-------------------------------------------------------------------------------- + +Hold Paths: TS_GMIIRXCLK = PERIOD TIMEGRP "GMIIRXCLK" 8 ns HIGH 50%; +-------------------------------------------------------------------------------- +Slack (hold path): 0.693ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/gmac/rxRS_rxPipe_5 (FF) + Destination: ftop/gbe0/gmac/gmac/rxRS_rxPipe_13 (FF) + Requirement: 0.000ns + Data Path Delay: 0.782ns (Levels of Logic = 0) + Clock Path Skew: 0.089ns (0.417 - 0.328) + Source Clock: gmii_rx_clk_BUFGP rising at 8.000ns + Destination Clock: gmii_rx_clk_BUFGP rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path: ftop/gbe0/gmac/gmac/rxRS_rxPipe_5 to ftop/gbe0/gmac/gmac/rxRS_rxPipe_13 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X103Y143.XQ Tcko 0.396 ftop/gbe0/gmac/gmac/rxRS_rxPipe<5> + ftop/gbe0/gmac/gmac/rxRS_rxPipe_5 + SLICE_X101Y141.BX net (fanout=2) 0.324 ftop/gbe0/gmac/gmac/rxRS_rxPipe<5> + SLICE_X101Y141.CLK Tckdi (-Th) -0.062 ftop/gbe0/gmac/gmac/rxRS_rxPipe<13> + ftop/gbe0/gmac/gmac/rxRS_rxPipe_13 + ------------------------------------------------- --------------------------- + Total 0.782ns (0.458ns logic, 0.324ns route) + (58.6% logic, 41.4% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.758ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/gmac/rxRS_rxF/sGEnqPtr1_3 (FF) + Destination: ftop/gbe0/gmac/gmac/rxRS_rxF/sGEnqPtr_3 (FF) + Requirement: 0.000ns + Data Path Delay: 0.807ns (Levels of Logic = 0) + Clock Path Skew: 0.049ns (0.687 - 0.638) + Source Clock: gmii_rx_clk_BUFGP rising at 8.000ns + Destination Clock: gmii_rx_clk_BUFGP rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path: ftop/gbe0/gmac/gmac/rxRS_rxF/sGEnqPtr1_3 to ftop/gbe0/gmac/gmac/rxRS_rxF/sGEnqPtr_3 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X108Y137.XQ Tcko 0.417 ftop/gbe0/gmac/gmac/rxRS_rxF/sGEnqPtr1<3> + ftop/gbe0/gmac/gmac/rxRS_rxF/sGEnqPtr1_3 + SLICE_X109Y135.BX net (fanout=4) 0.328 ftop/gbe0/gmac/gmac/rxRS_rxF/sGEnqPtr1<3> + SLICE_X109Y135.CLK Tckdi (-Th) -0.062 ftop/gbe0/gmac/gmac/rxRS_rxF/sGEnqPtr<3> + ftop/gbe0/gmac/gmac/rxRS_rxF/sGEnqPtr_3 + ------------------------------------------------- --------------------------- + Total 0.807ns (0.479ns logic, 0.328ns route) + (59.4% logic, 40.6% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.759ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/gmac/rxRS_rxF/sSyncReg1_1 (FF) + Destination: ftop/gbe0/gmac/gmac/rxRS_rxF/sDeqPtr_1 (FF) + Requirement: 0.000ns + Data Path Delay: 0.766ns (Levels of Logic = 0) + Clock Path Skew: 0.007ns (0.042 - 0.035) + Source Clock: gmii_rx_clk_BUFGP rising at 8.000ns + Destination Clock: gmii_rx_clk_BUFGP rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path: ftop/gbe0/gmac/gmac/rxRS_rxF/sSyncReg1_1 to ftop/gbe0/gmac/gmac/rxRS_rxF/sDeqPtr_1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X110Y138.XQ Tcko 0.417 ftop/gbe0/gmac/gmac/rxRS_rxF/sSyncReg1<1> + ftop/gbe0/gmac/gmac/rxRS_rxF/sSyncReg1_1 + SLICE_X111Y139.BX net (fanout=1) 0.287 ftop/gbe0/gmac/gmac/rxRS_rxF/sSyncReg1<1> + SLICE_X111Y139.CLK Tckdi (-Th) -0.062 ftop/gbe0/gmac/gmac/rxRS_rxF/sDeqPtr<1> + ftop/gbe0/gmac/gmac/rxRS_rxF/sDeqPtr_1 + ------------------------------------------------- --------------------------- + Total 0.766ns (0.479ns logic, 0.287ns route) + (62.5% logic, 37.5% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.773ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/gmac/rxRS_rxPipe_35 (FF) + Destination: ftop/gbe0/gmac/gmac/rxRS_rxPipe_43 (FF) + Requirement: 0.000ns + Data Path Delay: 0.776ns (Levels of Logic = 0) + Clock Path Skew: 0.003ns (0.023 - 0.020) + Source Clock: gmii_rx_clk_BUFGP rising at 8.000ns + Destination Clock: gmii_rx_clk_BUFGP rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path: ftop/gbe0/gmac/gmac/rxRS_rxPipe_35 to ftop/gbe0/gmac/gmac/rxRS_rxPipe_43 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X107Y127.XQ Tcko 0.396 ftop/gbe0/gmac/gmac/rxRS_rxPipe<35> + ftop/gbe0/gmac/gmac/rxRS_rxPipe_35 + SLICE_X107Y126.BX net (fanout=2) 0.318 ftop/gbe0/gmac/gmac/rxRS_rxPipe<35> + SLICE_X107Y126.CLK Tckdi (-Th) -0.062 ftop/gbe0/gmac/gmac/rxRS_rxPipe<43> + ftop/gbe0/gmac/gmac/rxRS_rxPipe_43 + ------------------------------------------------- --------------------------- + Total 0.776ns (0.458ns logic, 0.318ns route) + (59.0% logic, 41.0% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.776ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/gmac/rxRS_rxPipe_13 (FF) + Destination: ftop/gbe0/gmac/gmac/rxRS_rxPipe_21 (FF) + Requirement: 0.000ns + Data Path Delay: 0.793ns (Levels of Logic = 0) + Clock Path Skew: 0.017ns (0.068 - 0.051) + Source Clock: gmii_rx_clk_BUFGP rising at 8.000ns + Destination Clock: gmii_rx_clk_BUFGP rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path: ftop/gbe0/gmac/gmac/rxRS_rxPipe_13 to ftop/gbe0/gmac/gmac/rxRS_rxPipe_21 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X101Y141.XQ Tcko 0.396 ftop/gbe0/gmac/gmac/rxRS_rxPipe<13> + ftop/gbe0/gmac/gmac/rxRS_rxPipe_13 + SLICE_X100Y139.BX net (fanout=2) 0.295 ftop/gbe0/gmac/gmac/rxRS_rxPipe<13> + SLICE_X100Y139.CLK Tckdi (-Th) -0.102 ftop/gbe0/gmac/gmac/rxRS_rxPipe<21> + ftop/gbe0/gmac/gmac/rxRS_rxPipe_21 + ------------------------------------------------- --------------------------- + Total 0.793ns (0.498ns logic, 0.295ns route) + (62.8% logic, 37.2% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.776ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/gmac/rxRS_rxPipe_3 (FF) + Destination: ftop/gbe0/gmac/gmac/rxRS_rxPipe_11 (FF) + Requirement: 0.000ns + Data Path Delay: 0.854ns (Levels of Logic = 0) + Clock Path Skew: 0.078ns (0.406 - 0.328) + Source Clock: gmii_rx_clk_BUFGP rising at 8.000ns + Destination Clock: gmii_rx_clk_BUFGP rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path: ftop/gbe0/gmac/gmac/rxRS_rxPipe_3 to ftop/gbe0/gmac/gmac/rxRS_rxPipe_11 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X103Y142.XQ Tcko 0.396 ftop/gbe0/gmac/gmac/rxRS_rxPipe<3> + ftop/gbe0/gmac/gmac/rxRS_rxPipe_3 + SLICE_X100Y142.BX net (fanout=2) 0.356 ftop/gbe0/gmac/gmac/rxRS_rxPipe<3> + SLICE_X100Y142.CLK Tckdi (-Th) -0.102 ftop/gbe0/gmac/gmac/rxRS_rxPipe<11> + ftop/gbe0/gmac/gmac/rxRS_rxPipe_11 + ------------------------------------------------- --------------------------- + Total 0.854ns (0.498ns logic, 0.356ns route) + (58.3% logic, 41.7% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.794ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/gmac/rxRS_rxPipe_23 (FF) + Destination: ftop/gbe0/gmac/gmac/rxRS_rxPipe_31 (FF) + Requirement: 0.000ns + Data Path Delay: 0.808ns (Levels of Logic = 0) + Clock Path Skew: 0.014ns (0.072 - 0.058) + Source Clock: gmii_rx_clk_BUFGP rising at 8.000ns + Destination Clock: gmii_rx_clk_BUFGP rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path: ftop/gbe0/gmac/gmac/rxRS_rxPipe_23 to ftop/gbe0/gmac/gmac/rxRS_rxPipe_31 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X101Y139.XQ Tcko 0.396 ftop/gbe0/gmac/gmac/rxRS_rxPipe<23> + ftop/gbe0/gmac/gmac/rxRS_rxPipe_23 + SLICE_X100Y136.BX net (fanout=2) 0.310 ftop/gbe0/gmac/gmac/rxRS_rxPipe<23> + SLICE_X100Y136.CLK Tckdi (-Th) -0.102 ftop/gbe0/gmac/gmac/rxRS_rxPipe<31> + ftop/gbe0/gmac/gmac/rxRS_rxPipe_31 + ------------------------------------------------- --------------------------- + Total 0.808ns (0.498ns logic, 0.310ns route) + (61.6% logic, 38.4% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.797ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/gmac/rxRS_rxPipe_15 (FF) + Destination: ftop/gbe0/gmac/gmac/rxRS_rxPipe_23 (FF) + Requirement: 0.000ns + Data Path Delay: 0.814ns (Levels of Logic = 0) + Clock Path Skew: 0.017ns (0.068 - 0.051) + Source Clock: gmii_rx_clk_BUFGP rising at 8.000ns + Destination Clock: gmii_rx_clk_BUFGP rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path: ftop/gbe0/gmac/gmac/rxRS_rxPipe_15 to ftop/gbe0/gmac/gmac/rxRS_rxPipe_23 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X101Y140.XQ Tcko 0.396 ftop/gbe0/gmac/gmac/rxRS_rxPipe<15> + ftop/gbe0/gmac/gmac/rxRS_rxPipe_15 + SLICE_X101Y139.BX net (fanout=2) 0.356 ftop/gbe0/gmac/gmac/rxRS_rxPipe<15> + SLICE_X101Y139.CLK Tckdi (-Th) -0.062 ftop/gbe0/gmac/gmac/rxRS_rxPipe<23> + ftop/gbe0/gmac/gmac/rxRS_rxPipe_23 + ------------------------------------------------- --------------------------- + Total 0.814ns (0.458ns logic, 0.356ns route) + (56.3% logic, 43.7% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.801ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/gmac/rxRS_rxPipe_17 (FF) + Destination: ftop/gbe0/gmac/gmac/rxRS_rxPipe_25 (FF) + Requirement: 0.000ns + Data Path Delay: 0.814ns (Levels of Logic = 0) + Clock Path Skew: 0.013ns (0.072 - 0.059) + Source Clock: gmii_rx_clk_BUFGP rising at 8.000ns + Destination Clock: gmii_rx_clk_BUFGP rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path: ftop/gbe0/gmac/gmac/rxRS_rxPipe_17 to ftop/gbe0/gmac/gmac/rxRS_rxPipe_25 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X98Y138.XQ Tcko 0.417 ftop/gbe0/gmac/gmac/rxRS_rxPipe<17> + ftop/gbe0/gmac/gmac/rxRS_rxPipe_17 + SLICE_X98Y136.BX net (fanout=2) 0.295 ftop/gbe0/gmac/gmac/rxRS_rxPipe<17> + SLICE_X98Y136.CLK Tckdi (-Th) -0.102 ftop/gbe0/gmac/gmac/rxRS_rxPipe<25> + ftop/gbe0/gmac/gmac/rxRS_rxPipe_25 + ------------------------------------------------- --------------------------- + Total 0.814ns (0.519ns logic, 0.295ns route) + (63.8% logic, 36.2% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.812ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/gmac/rxRS_rxPipe_33 (FF) + Destination: ftop/gbe0/gmac/gmac/rxRS_rxPipe_41 (FF) + Requirement: 0.000ns + Data Path Delay: 0.817ns (Levels of Logic = 0) + Clock Path Skew: 0.005ns (0.032 - 0.027) + Source Clock: gmii_rx_clk_BUFGP rising at 8.000ns + Destination Clock: gmii_rx_clk_BUFGP rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path: ftop/gbe0/gmac/gmac/rxRS_rxPipe_33 to ftop/gbe0/gmac/gmac/rxRS_rxPipe_41 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X103Y134.XQ Tcko 0.396 ftop/gbe0/gmac/gmac/rxRS_rxPipe<33> + ftop/gbe0/gmac/gmac/rxRS_rxPipe_33 + SLICE_X102Y134.BX net (fanout=2) 0.319 ftop/gbe0/gmac/gmac/rxRS_rxPipe<33> + SLICE_X102Y134.CLK Tckdi (-Th) -0.102 ftop/gbe0/gmac/gmac/rxRS_rxPipe<41> + ftop/gbe0/gmac/gmac/rxRS_rxPipe_41 + ------------------------------------------------- --------------------------- + Total 0.817ns (0.498ns logic, 0.319ns route) + (61.0% logic, 39.0% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.814ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/gmac/rxRS_rxF/sGEnqPtr_2 (FF) + Destination: ftop/gbe0/gmac/gmac/rxRS_rxF/Mram_fifoMem8.SLICEM_G (RAM) + Requirement: 0.000ns + Data Path Delay: 0.886ns (Levels of Logic = 1) + Clock Path Skew: 0.072ns (0.445 - 0.373) + Source Clock: gmii_rx_clk_BUFGP rising at 8.000ns + Destination Clock: gmii_rx_clk_BUFGP rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path: ftop/gbe0/gmac/gmac/rxRS_rxF/sGEnqPtr_2 to ftop/gbe0/gmac/gmac/rxRS_rxF/Mram_fifoMem8.SLICEM_G + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X109Y135.YQ Tcko 0.419 ftop/gbe0/gmac/gmac/rxRS_rxF/sGEnqPtr<3> + ftop/gbe0/gmac/gmac/rxRS_rxF/sGEnqPtr_2 + SLICE_X104Y132.G3 net (fanout=13) 0.468 ftop/gbe0/gmac/gmac/rxRS_rxF/sGEnqPtr<2> + SLICE_X104Y132.CLK Tah (-Th) 0.001 ftop/gbe0/gmac/gmac/rxRS_rxF/_varindex0000<7> + ftop/gbe0/gmac/gmac/rxRS_rxF/Mram_fifoMem8.SLICEM_G + ------------------------------------------------- --------------------------- + Total 0.886ns (0.418ns logic, 0.468ns route) + (47.2% logic, 52.8% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.814ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/gmac/rxRS_rxF/sGEnqPtr_2 (FF) + Destination: ftop/gbe0/gmac/gmac/rxRS_rxF/Mram_fifoMem8.SLICEM_F (RAM) + Requirement: 0.000ns + Data Path Delay: 0.886ns (Levels of Logic = 1) + Clock Path Skew: 0.072ns (0.445 - 0.373) + Source Clock: gmii_rx_clk_BUFGP rising at 8.000ns + Destination Clock: gmii_rx_clk_BUFGP rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path: ftop/gbe0/gmac/gmac/rxRS_rxF/sGEnqPtr_2 to ftop/gbe0/gmac/gmac/rxRS_rxF/Mram_fifoMem8.SLICEM_F + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X109Y135.YQ Tcko 0.419 ftop/gbe0/gmac/gmac/rxRS_rxF/sGEnqPtr<3> + ftop/gbe0/gmac/gmac/rxRS_rxF/sGEnqPtr_2 + SLICE_X104Y132.G3 net (fanout=13) 0.468 ftop/gbe0/gmac/gmac/rxRS_rxF/sGEnqPtr<2> + SLICE_X104Y132.CLK Tah (-Th) 0.001 ftop/gbe0/gmac/gmac/rxRS_rxF/_varindex0000<7> + ftop/gbe0/gmac/gmac/rxRS_rxF/Mram_fifoMem8.SLICEM_F + ------------------------------------------------- --------------------------- + Total 0.886ns (0.418ns logic, 0.468ns route) + (47.2% logic, 52.8% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.829ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/gmac/rxRS_rxPipe_37 (FF) + Destination: ftop/gbe0/gmac/gmac/rxRS_rxPipe_45 (FF) + Requirement: 0.000ns + Data Path Delay: 0.828ns (Levels of Logic = 0) + Clock Path Skew: -0.001ns (0.016 - 0.017) + Source Clock: gmii_rx_clk_BUFGP rising at 8.000ns + Destination Clock: gmii_rx_clk_BUFGP rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path: ftop/gbe0/gmac/gmac/rxRS_rxPipe_37 to ftop/gbe0/gmac/gmac/rxRS_rxPipe_45 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X108Y128.XQ Tcko 0.417 ftop/gbe0/gmac/gmac/rxRS_rxPipe<37> + ftop/gbe0/gmac/gmac/rxRS_rxPipe_37 + SLICE_X108Y126.BX net (fanout=2) 0.309 ftop/gbe0/gmac/gmac/rxRS_rxPipe<37> + SLICE_X108Y126.CLK Tckdi (-Th) -0.102 ftop/gbe0/gmac/gmac/rxRS_rxPipe<45> + ftop/gbe0/gmac/gmac/rxRS_rxPipe_45 + ------------------------------------------------- --------------------------- + Total 0.828ns (0.519ns logic, 0.309ns route) + (62.7% logic, 37.3% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.842ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/gmac/rxRS_rxPipe_31 (FF) + Destination: ftop/gbe0/gmac/gmac/rxRS_rxPipe_39 (FF) + Requirement: 0.000ns + Data Path Delay: 0.853ns (Levels of Logic = 0) + Clock Path Skew: 0.011ns (0.072 - 0.061) + Source Clock: gmii_rx_clk_BUFGP rising at 8.000ns + Destination Clock: gmii_rx_clk_BUFGP rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path: ftop/gbe0/gmac/gmac/rxRS_rxPipe_31 to ftop/gbe0/gmac/gmac/rxRS_rxPipe_39 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X100Y136.XQ Tcko 0.417 ftop/gbe0/gmac/gmac/rxRS_rxPipe<31> + ftop/gbe0/gmac/gmac/rxRS_rxPipe_31 + SLICE_X101Y137.BX net (fanout=4) 0.374 ftop/gbe0/gmac/gmac/rxRS_rxPipe<31> + SLICE_X101Y137.CLK Tckdi (-Th) -0.062 ftop/gbe0/gmac/gmac/rxRS_rxPipe<39> + ftop/gbe0/gmac/gmac/rxRS_rxPipe_39 + ------------------------------------------------- --------------------------- + Total 0.853ns (0.479ns logic, 0.374ns route) + (56.2% logic, 43.8% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.846ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/gmac/rxRS_rxRst/reset_hold_0 (FF) + Destination: ftop/gbe0/gmac/gmac/rxRS_rxRst/reset_hold_1 (FF) + Requirement: 0.000ns + Data Path Delay: 0.854ns (Levels of Logic = 0) + Clock Path Skew: 0.008ns (0.053 - 0.045) + Source Clock: gmii_rx_clk_BUFGP rising at 8.000ns + Destination Clock: gmii_rx_clk_BUFGP rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path: ftop/gbe0/gmac/gmac/rxRS_rxRst/reset_hold_0 to ftop/gbe0/gmac/gmac/rxRS_rxRst/reset_hold_1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X105Y130.YQ Tcko 0.419 ftop/gbe0/gmac/gmac/rxRS_rxRst/reset_hold<0> + ftop/gbe0/gmac/gmac/rxRS_rxRst/reset_hold_0 + SLICE_X105Y131.BY net (fanout=1) 0.313 ftop/gbe0/gmac/gmac/rxRS_rxRst/reset_hold<0> + SLICE_X105Y131.CLK Tckdi (-Th) -0.122 ftop/gbe0/gmac/gmac/rxRS_rxRst_OUT_RST + ftop/gbe0/gmac/gmac/rxRS_rxRst/reset_hold_1 + ------------------------------------------------- --------------------------- + Total 0.854ns (0.541ns logic, 0.313ns route) + (63.3% logic, 36.7% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.849ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/gmac/rxRS_rxPipe_6 (FF) + Destination: ftop/gbe0/gmac/gmac/rxRS_rxPipe_14 (FF) + Requirement: 0.000ns + Data Path Delay: 0.867ns (Levels of Logic = 0) + Clock Path Skew: 0.018ns (0.060 - 0.042) + Source Clock: gmii_rx_clk_BUFGP rising at 8.000ns + Destination Clock: gmii_rx_clk_BUFGP rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path: ftop/gbe0/gmac/gmac/rxRS_rxPipe_6 to ftop/gbe0/gmac/gmac/rxRS_rxPipe_14 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X101Y142.YQ Tcko 0.419 ftop/gbe0/gmac/gmac/rxRS_rxPipe<7> + ftop/gbe0/gmac/gmac/rxRS_rxPipe_6 + SLICE_X101Y140.BY net (fanout=2) 0.326 ftop/gbe0/gmac/gmac/rxRS_rxPipe<6> + SLICE_X101Y140.CLK Tckdi (-Th) -0.122 ftop/gbe0/gmac/gmac/rxRS_rxPipe<15> + ftop/gbe0/gmac/gmac/rxRS_rxPipe_14 + ------------------------------------------------- --------------------------- + Total 0.867ns (0.541ns logic, 0.326ns route) + (62.4% logic, 37.6% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.850ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/gmac/rxRS_rxPipe_12 (FF) + Destination: ftop/gbe0/gmac/gmac/rxRS_rxPipe_20 (FF) + Requirement: 0.000ns + Data Path Delay: 0.867ns (Levels of Logic = 0) + Clock Path Skew: 0.017ns (0.068 - 0.051) + Source Clock: gmii_rx_clk_BUFGP rising at 8.000ns + Destination Clock: gmii_rx_clk_BUFGP rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path: ftop/gbe0/gmac/gmac/rxRS_rxPipe_12 to ftop/gbe0/gmac/gmac/rxRS_rxPipe_20 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X101Y141.YQ Tcko 0.419 ftop/gbe0/gmac/gmac/rxRS_rxPipe<13> + ftop/gbe0/gmac/gmac/rxRS_rxPipe_12 + SLICE_X100Y139.BY net (fanout=2) 0.311 ftop/gbe0/gmac/gmac/rxRS_rxPipe<12> + SLICE_X100Y139.CLK Tckdi (-Th) -0.137 ftop/gbe0/gmac/gmac/rxRS_rxPipe<21> + ftop/gbe0/gmac/gmac/rxRS_rxPipe_20 + ------------------------------------------------- --------------------------- + Total 0.867ns (0.556ns logic, 0.311ns route) + (64.1% logic, 35.9% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.855ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/gmac/rxRS_rxPipe_22 (FF) + Destination: ftop/gbe0/gmac/gmac/rxRS_rxPipe_30 (FF) + Requirement: 0.000ns + Data Path Delay: 0.869ns (Levels of Logic = 0) + Clock Path Skew: 0.014ns (0.072 - 0.058) + Source Clock: gmii_rx_clk_BUFGP rising at 8.000ns + Destination Clock: gmii_rx_clk_BUFGP rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path: ftop/gbe0/gmac/gmac/rxRS_rxPipe_22 to ftop/gbe0/gmac/gmac/rxRS_rxPipe_30 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X101Y139.YQ Tcko 0.419 ftop/gbe0/gmac/gmac/rxRS_rxPipe<23> + ftop/gbe0/gmac/gmac/rxRS_rxPipe_22 + SLICE_X100Y136.BY net (fanout=2) 0.313 ftop/gbe0/gmac/gmac/rxRS_rxPipe<22> + SLICE_X100Y136.CLK Tckdi (-Th) -0.137 ftop/gbe0/gmac/gmac/rxRS_rxPipe<31> + ftop/gbe0/gmac/gmac/rxRS_rxPipe_30 + ------------------------------------------------- --------------------------- + Total 0.869ns (0.556ns logic, 0.313ns route) + (64.0% logic, 36.0% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.876ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/gmac/rxRS_rxF/sGEnqPtr1_4 (FF) + Destination: ftop/gbe0/gmac/gmac/rxRS_rxF/sGEnqPtr_4 (FF) + Requirement: 0.000ns + Data Path Delay: 0.909ns (Levels of Logic = 0) + Clock Path Skew: 0.033ns (0.683 - 0.650) + Source Clock: gmii_rx_clk_BUFGP rising at 8.000ns + Destination Clock: gmii_rx_clk_BUFGP rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path: ftop/gbe0/gmac/gmac/rxRS_rxF/sGEnqPtr1_4 to ftop/gbe0/gmac/gmac/rxRS_rxF/sGEnqPtr_4 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X110Y137.YQ Tcko 0.477 ftop/gbe0/gmac/gmac/rxRS_rxF/sGEnqPtr1<4> + ftop/gbe0/gmac/gmac/rxRS_rxF/sGEnqPtr1_4 + SLICE_X110Y134.BY net (fanout=4) 0.295 ftop/gbe0/gmac/gmac/rxRS_rxF/sGEnqPtr1<4> + SLICE_X110Y134.CLK Tckdi (-Th) -0.137 ftop/gbe0/gmac/gmac/rxRS_rxF/sGEnqPtr<4> + ftop/gbe0/gmac/gmac/rxRS_rxF/sGEnqPtr_4 + ------------------------------------------------- --------------------------- + Total 0.909ns (0.614ns logic, 0.295ns route) + (67.5% logic, 32.5% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.880ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/gbe0/gmac/gmac/rxRS_rxPipe_14 (FF) + Destination: ftop/gbe0/gmac/gmac/rxRS_rxPipe_22 (FF) + Requirement: 0.000ns + Data Path Delay: 0.897ns (Levels of Logic = 0) + Clock Path Skew: 0.017ns (0.068 - 0.051) + Source Clock: gmii_rx_clk_BUFGP rising at 8.000ns + Destination Clock: gmii_rx_clk_BUFGP rising at 8.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path: ftop/gbe0/gmac/gmac/rxRS_rxPipe_14 to ftop/gbe0/gmac/gmac/rxRS_rxPipe_22 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X101Y140.YQ Tcko 0.419 ftop/gbe0/gmac/gmac/rxRS_rxPipe<15> + ftop/gbe0/gmac/gmac/rxRS_rxPipe_14 + SLICE_X101Y139.BY net (fanout=2) 0.356 ftop/gbe0/gmac/gmac/rxRS_rxPipe<14> + SLICE_X101Y139.CLK Tckdi (-Th) -0.122 ftop/gbe0/gmac/gmac/rxRS_rxPipe<23> + ftop/gbe0/gmac/gmac/rxRS_rxPipe_22 + ------------------------------------------------- --------------------------- + Total 0.897ns (0.541ns logic, 0.356ns route) + (60.3% logic, 39.7% route) + +-------------------------------------------------------------------------------- + +Component Switching Limit Checks: TS_GMIIRXCLK = PERIOD TIMEGRP "GMIIRXCLK" 8 ns HIGH 50%; +-------------------------------------------------------------------------------- +Slack: 5.344ns (period - (min low pulse limit / (low pulse / period))) + Period: 8.000ns + Low pulse: 4.000ns + Low pulse limit: 1.328ns (Trpw) + Physical resource: ftop/gbe0/gmac/gmac/rxRS_rxF/sGEnqPtr1<3>/SR + Logical resource: ftop/gbe0/gmac/gmac/rxRS_rxF/sGEnqPtr1_3/SR + Location pin: SLICE_X108Y137.SR + Clock network: ftop/gbe0/gmac/gmac/rxRS_rxRst_OUT_RST +-------------------------------------------------------------------------------- +Slack: 5.344ns (period - (min high pulse limit / (high pulse / period))) + Period: 8.000ns + High pulse: 4.000ns + High pulse limit: 1.328ns (Trpw) + Physical resource: ftop/gbe0/gmac/gmac/rxRS_rxF/sGEnqPtr1<3>/SR + Logical resource: ftop/gbe0/gmac/gmac/rxRS_rxF/sGEnqPtr1_3/SR + Location pin: SLICE_X108Y137.SR + Clock network: ftop/gbe0/gmac/gmac/rxRS_rxRst_OUT_RST +-------------------------------------------------------------------------------- +Slack: 5.344ns (period - (min low pulse limit / (low pulse / period))) + Period: 8.000ns + Low pulse: 4.000ns + Low pulse limit: 1.328ns (Trpw) + Physical resource: ftop/gbe0/gmac/gmac/rxRS_rxF/sGEnqPtr1<3>/SR + Logical resource: ftop/gbe0/gmac/gmac/rxRS_rxF/sGEnqPtr1_2/SR + Location pin: SLICE_X108Y137.SR + Clock network: ftop/gbe0/gmac/gmac/rxRS_rxRst_OUT_RST +-------------------------------------------------------------------------------- +Slack: 5.344ns (period - (min high pulse limit / (high pulse / period))) + Period: 8.000ns + High pulse: 4.000ns + High pulse limit: 1.328ns (Trpw) + Physical resource: ftop/gbe0/gmac/gmac/rxRS_rxF/sGEnqPtr1<3>/SR + Logical resource: ftop/gbe0/gmac/gmac/rxRS_rxF/sGEnqPtr1_2/SR + Location pin: SLICE_X108Y137.SR + Clock network: ftop/gbe0/gmac/gmac/rxRS_rxRst_OUT_RST +-------------------------------------------------------------------------------- +Slack: 5.344ns (period - (min low pulse limit / (low pulse / period))) + Period: 8.000ns + Low pulse: 4.000ns + Low pulse limit: 1.328ns (Trpw) + Physical resource: ftop/gbe0/gmac/gmac/rxRS_rxF/sGEnqPtr1<4>/SR + Logical resource: ftop/gbe0/gmac/gmac/rxRS_rxF/sGEnqPtr1_4/SR + Location pin: SLICE_X110Y137.SR + Clock network: ftop/gbe0/gmac/gmac/rxRS_rxRst_OUT_RST +-------------------------------------------------------------------------------- +Slack: 5.344ns (period - (min high pulse limit / (high pulse / period))) + Period: 8.000ns + High pulse: 4.000ns + High pulse limit: 1.328ns (Trpw) + Physical resource: ftop/gbe0/gmac/gmac/rxRS_rxF/sGEnqPtr1<4>/SR + Logical resource: ftop/gbe0/gmac/gmac/rxRS_rxF/sGEnqPtr1_4/SR + Location pin: SLICE_X110Y137.SR + Clock network: ftop/gbe0/gmac/gmac/rxRS_rxRst_OUT_RST +-------------------------------------------------------------------------------- +Slack: 5.344ns (period - (min low pulse limit / (low pulse / period))) + Period: 8.000ns + Low pulse: 4.000ns + Low pulse limit: 1.328ns (Trpw) + Physical resource: ftop/gbe0/gmac/gmac/rxRS_rxF/sSyncReg1<1>/SR + Logical resource: ftop/gbe0/gmac/gmac/rxRS_rxF/sSyncReg1_1/SR + Location pin: SLICE_X110Y138.SR + Clock network: ftop/gbe0/gmac/gmac/rxRS_rxRst_OUT_RST +-------------------------------------------------------------------------------- +Slack: 5.344ns (period - (min high pulse limit / (high pulse / period))) + Period: 8.000ns + High pulse: 4.000ns + High pulse limit: 1.328ns (Trpw) + Physical resource: ftop/gbe0/gmac/gmac/rxRS_rxF/sSyncReg1<1>/SR + Logical resource: ftop/gbe0/gmac/gmac/rxRS_rxF/sSyncReg1_1/SR + Location pin: SLICE_X110Y138.SR + Clock network: ftop/gbe0/gmac/gmac/rxRS_rxRst_OUT_RST +-------------------------------------------------------------------------------- +Slack: 5.344ns (period - (min low pulse limit / (low pulse / period))) + Period: 8.000ns + Low pulse: 4.000ns + Low pulse limit: 1.328ns (Trpw) + Physical resource: ftop/gbe0/gmac/gmac/rxRS_rxF/sSyncReg1<1>/SR + Logical resource: ftop/gbe0/gmac/gmac/rxRS_rxF/sSyncReg1_0/SR + Location pin: SLICE_X110Y138.SR + Clock network: ftop/gbe0/gmac/gmac/rxRS_rxRst_OUT_RST +-------------------------------------------------------------------------------- +Slack: 5.344ns (period - (min high pulse limit / (high pulse / period))) + Period: 8.000ns + High pulse: 4.000ns + High pulse limit: 1.328ns (Trpw) + Physical resource: ftop/gbe0/gmac/gmac/rxRS_rxF/sSyncReg1<1>/SR + Logical resource: ftop/gbe0/gmac/gmac/rxRS_rxF/sSyncReg1_0/SR + Location pin: SLICE_X110Y138.SR + Clock network: ftop/gbe0/gmac/gmac/rxRS_rxRst_OUT_RST +-------------------------------------------------------------------------------- +Slack: 5.344ns (period - (min low pulse limit / (low pulse / period))) + Period: 8.000ns + Low pulse: 4.000ns + Low pulse limit: 1.328ns (Trpw) + Physical resource: ftop/gbe0/gmac/gmac/rxRS_rxOperateS/dSyncReg1/SR + Logical resource: ftop/gbe0/gmac/gmac/rxRS_rxOperateS/dSyncReg1/SR + Location pin: SLICE_X104Y168.SR + Clock network: ftop/gmiixo_rst_OUT_RST +-------------------------------------------------------------------------------- +Slack: 5.344ns (period - (min high pulse limit / (high pulse / period))) + Period: 8.000ns + High pulse: 4.000ns + High pulse limit: 1.328ns (Trpw) + Physical resource: ftop/gbe0/gmac/gmac/rxRS_rxOperateS/dSyncReg1/SR + Logical resource: ftop/gbe0/gmac/gmac/rxRS_rxOperateS/dSyncReg1/SR + Location pin: SLICE_X104Y168.SR + Clock network: ftop/gmiixo_rst_OUT_RST +-------------------------------------------------------------------------------- +Slack: 5.344ns (period - (min low pulse limit / (low pulse / period))) + Period: 8.000ns + Low pulse: 4.000ns + Low pulse limit: 1.328ns (Trpw) + Physical resource: ftop/gbe0/gmac/gmac/rxRS_rxF/sGEnqPtr<4>/SR + Logical resource: ftop/gbe0/gmac/gmac/rxRS_rxF/sGEnqPtr_4/SR + Location pin: SLICE_X110Y134.SR + Clock network: ftop/gbe0/gmac/gmac/rxRS_rxRst_OUT_RST +-------------------------------------------------------------------------------- +Slack: 5.344ns (period - (min high pulse limit / (high pulse / period))) + Period: 8.000ns + High pulse: 4.000ns + High pulse limit: 1.328ns (Trpw) + Physical resource: ftop/gbe0/gmac/gmac/rxRS_rxF/sGEnqPtr<4>/SR + Logical resource: ftop/gbe0/gmac/gmac/rxRS_rxF/sGEnqPtr_4/SR + Location pin: SLICE_X110Y134.SR + Clock network: ftop/gbe0/gmac/gmac/rxRS_rxRst_OUT_RST +-------------------------------------------------------------------------------- +Slack: 5.504ns (period - (min low pulse limit / (low pulse / period))) + Period: 8.000ns + Low pulse: 4.000ns + Low pulse limit: 1.248ns (Trpw) + Physical resource: ftop/gbe0/gmac/gmac/rxRS_rxF_sFULL_N/SR + Logical resource: ftop/gbe0/gmac/gmac/rxRS_rxF/sNotFullReg/SR + Location pin: SLICE_X111Y137.SR + Clock network: ftop/gbe0/gmac/gmac/rxRS_rxRst_OUT_RST +-------------------------------------------------------------------------------- +Slack: 5.504ns (period - (min high pulse limit / (high pulse / period))) + Period: 8.000ns + High pulse: 4.000ns + High pulse limit: 1.248ns (Trpw) + Physical resource: ftop/gbe0/gmac/gmac/rxRS_rxF_sFULL_N/SR + Logical resource: ftop/gbe0/gmac/gmac/rxRS_rxF/sNotFullReg/SR + Location pin: SLICE_X111Y137.SR + Clock network: ftop/gbe0/gmac/gmac/rxRS_rxRst_OUT_RST +-------------------------------------------------------------------------------- +Slack: 5.504ns (period - (min low pulse limit / (low pulse / period))) + Period: 8.000ns + Low pulse: 4.000ns + Low pulse limit: 1.248ns (Trpw) + Physical resource: ftop/gbe0/gmac/gmac/rxRS_rxF/sSyncReg1<3>/SR + Logical resource: ftop/gbe0/gmac/gmac/rxRS_rxF/sSyncReg1_3/SR + Location pin: SLICE_X107Y124.SR + Clock network: ftop/gbe0/gmac/gmac/rxRS_rxRst_OUT_RST +-------------------------------------------------------------------------------- +Slack: 5.504ns (period - (min high pulse limit / (high pulse / period))) + Period: 8.000ns + High pulse: 4.000ns + High pulse limit: 1.248ns (Trpw) + Physical resource: ftop/gbe0/gmac/gmac/rxRS_rxF/sSyncReg1<3>/SR + Logical resource: ftop/gbe0/gmac/gmac/rxRS_rxF/sSyncReg1_3/SR + Location pin: SLICE_X107Y124.SR + Clock network: ftop/gbe0/gmac/gmac/rxRS_rxRst_OUT_RST +-------------------------------------------------------------------------------- +Slack: 5.504ns (period - (min low pulse limit / (low pulse / period))) + Period: 8.000ns + Low pulse: 4.000ns + Low pulse limit: 1.248ns (Trpw) + Physical resource: ftop/gbe0/gmac/gmac/rxRS_rxF/sSyncReg1<3>/SR + Logical resource: ftop/gbe0/gmac/gmac/rxRS_rxF/sSyncReg1_2/SR + Location pin: SLICE_X107Y124.SR + Clock network: ftop/gbe0/gmac/gmac/rxRS_rxRst_OUT_RST +-------------------------------------------------------------------------------- +Slack: 5.504ns (period - (min high pulse limit / (high pulse / period))) + Period: 8.000ns + High pulse: 4.000ns + High pulse limit: 1.248ns (Trpw) + Physical resource: ftop/gbe0/gmac/gmac/rxRS_rxF/sSyncReg1<3>/SR + Logical resource: ftop/gbe0/gmac/gmac/rxRS_rxF/sSyncReg1_2/SR + Location pin: SLICE_X107Y124.SR + Clock network: ftop/gbe0/gmac/gmac/rxRS_rxRst_OUT_RST +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: TS_ftop_clkN210_clk0_unbuf = PERIOD TIMEGRP +"ftop_clkN210_clk0_unbuf" TS_SYS0CLK HIGH 50%; +For more information, see Period Analysis in the Timing Closure User Guide (UG612). + + 1 path analyzed, 1 endpoint analyzed, 0 failing endpoints + 0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors) + Minimum period is 7.851ns. +-------------------------------------------------------------------------------- +Slack (setup path): 2.149ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/clkN210/rst_fd (FF) + Destination: ftop/clkN210/clk0_rst (FF) + Requirement: 10.000ns + Data Path Delay: 2.666ns (Levels of Logic = 0) + Clock Path Skew: -5.185ns (-1.312 - 3.873) + Source Clock: ftop/clkIn_O rising at 0.000ns + Destination Clock: ftop/sys0Clk rising at 10.000ns + Clock Uncertainty: 0.000ns + + Maximum Data Path: ftop/clkN210/rst_fd to ftop/clkN210/clk0_rst + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X82Y52.YQ Tcko 0.596 ftop/clkN210/rstInD + ftop/clkN210/rst_fd + SLICE_X71Y52.SR net (fanout=3) 1.637 ftop/clkN210/rstInD + SLICE_X71Y52.CLK Tsrck 0.433 ftop/sys0Rst + ftop/clkN210/clk0_rst + ------------------------------------------------- --------------------------- + Total 2.666ns (1.029ns logic, 1.637ns route) + (38.6% logic, 61.4% route) + +-------------------------------------------------------------------------------- + +Hold Paths: TS_ftop_clkN210_clk0_unbuf = PERIOD TIMEGRP "ftop_clkN210_clk0_unbuf" + TS_SYS0CLK HIGH 50%; +-------------------------------------------------------------------------------- +Slack (hold path): 5.709ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/clkN210/rst_fd (FF) + Destination: ftop/clkN210/clk0_rst (FF) + Requirement: 0.000ns + Data Path Delay: 2.077ns (Levels of Logic = 0) + Clock Path Skew: -3.632ns (-0.534 - 3.098) + Source Clock: ftop/clkIn_O rising at 10.000ns + Destination Clock: ftop/sys0Clk rising at 10.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path: ftop/clkN210/rst_fd to ftop/clkN210/clk0_rst + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X82Y52.YQ Tcko 0.477 ftop/clkN210/rstInD + ftop/clkN210/rst_fd + SLICE_X71Y52.SR net (fanout=3) 1.310 ftop/clkN210/rstInD + SLICE_X71Y52.CLK Tcksr (-Th) -0.290 ftop/sys0Rst + ftop/clkN210/clk0_rst + ------------------------------------------------- --------------------------- + Total 2.077ns (0.767ns logic, 1.310ns route) + (36.9% logic, 63.1% route) + +-------------------------------------------------------------------------------- + +Component Switching Limit Checks: TS_ftop_clkN210_clk0_unbuf = PERIOD TIMEGRP "ftop_clkN210_clk0_unbuf" + TS_SYS0CLK HIGH 50%; +-------------------------------------------------------------------------------- +Slack: 8.752ns (period - (min low pulse limit / (low pulse / period))) + Period: 10.000ns + Low pulse: 5.000ns + Low pulse limit: 0.624ns (Tcl) + Physical resource: ftop/sys0Rst/CLK + Logical resource: ftop/clkN210/clk0_rst/CK + Location pin: SLICE_X71Y52.CLK + Clock network: ftop/sys0Clk +-------------------------------------------------------------------------------- +Slack: 8.752ns (period - (min high pulse limit / (high pulse / period))) + Period: 10.000ns + High pulse: 5.000ns + High pulse limit: 0.624ns (Tch) + Physical resource: ftop/sys0Rst/CLK + Logical resource: ftop/clkN210/clk0_rst/CK + Location pin: SLICE_X71Y52.CLK + Clock network: ftop/sys0Clk +-------------------------------------------------------------------------------- +Slack: 8.752ns (period - min period limit) + Period: 10.000ns + Min period limit: 1.248ns (801.282MHz) (Tcp) + Physical resource: ftop/sys0Rst/CLK + Logical resource: ftop/clkN210/clk0_rst/CK + Location pin: SLICE_X71Y52.CLK + Clock network: ftop/sys0Clk +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: TS_ftop_clkN210_clkdv_unbuf = PERIOD TIMEGRP +"ftop_clkN210_clkdv_unbuf" TS_SYS0CLK * 2 HIGH 50%; +For more information, see Period Analysis in the Timing Closure User Guide (UG612). + + 5509128 paths analyzed, 69343 endpoints analyzed, 0 failing endpoints + 0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors) + Minimum period is 19.500ns. +-------------------------------------------------------------------------------- +Slack (setup path): 0.500ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/cp/cpReq_27 (FF) + Destination: ftop/cp/cpRespF/data0_reg_29 (FF) + Requirement: 20.000ns + Data Path Delay: 19.461ns (Levels of Logic = 22) + Clock Path Skew: -0.039ns (0.098 - 0.137) + Source Clock: ftop/sys1Clk rising at 0.000ns + Destination Clock: ftop/sys1Clk rising at 20.000ns + Clock Uncertainty: 0.000ns + + Maximum Data Path: ftop/cp/cpReq_27 to ftop/cp/cpRespF/data0_reg_29 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X84Y107.YQ Tcko 0.596 ftop/cp/cpReq<28> + ftop/cp/cpReq_27 + SLICE_X79Y106.G4 net (fanout=3) 0.628 ftop/cp/cpReq<27> + SLICE_X79Y106.Y Tilo 0.561 ftop/cp/wn___1__h76646<3> + ftop/cp/Msub_wn___1__h76646_xor<3>11 + SLICE_X75Y111.F3 net (fanout=2) 0.476 ftop/cp/wn___1__h76646<3> + SLICE_X75Y111.X Tilo 0.562 ftop/cp/_theResult_____1__h75875<3> + ftop/cp/_theResult_____1__h75875<3>1 + SLICE_X75Y137.G2 net (fanout=17) 1.840 ftop/cp/_theResult_____1__h75875<3> + SLICE_X75Y137.Y Tilo 0.561 ftop/cp/wci_reqPend_11<3> + ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F_cmp_eq00001 + SLICE_X70Y148.G2 net (fanout=11) 1.381 ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F_cmp_eq0000 + SLICE_X70Y148.Y Tilo 0.616 ftop/cp/wci_respF_11_D_IN<3>0 + ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T1 + SLICE_X77Y110.F4 net (fanout=9) 3.018 ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T + SLICE_X77Y110.COUT Topcyf 1.026 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<11> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_lut<10> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<10> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<11> + SLICE_X77Y111.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<11> + SLICE_X77Y111.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<13> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<12> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<13> + SLICE_X77Y112.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<13> + SLICE_X77Y112.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<15> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<14> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<15> + SLICE_X77Y113.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<15> + SLICE_X77Y113.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<17> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<16> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<17> + SLICE_X77Y114.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<17> + SLICE_X77Y114.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<19> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<18> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<19> + SLICE_X77Y115.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<19> + SLICE_X77Y115.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<21> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<20> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<21> + SLICE_X77Y116.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<21> + SLICE_X77Y116.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<23> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<22> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<23> + SLICE_X77Y117.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<23> + SLICE_X77Y117.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<25> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<24> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<25> + SLICE_X77Y118.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<25> + SLICE_X77Y118.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<27> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<26> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<27> + SLICE_X77Y119.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<27> + SLICE_X77Y119.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<29> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<28> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<29> + SLICE_X77Y120.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<29> + SLICE_X77Y120.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<31> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<30> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<31> + SLICE_X77Y121.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<31> + SLICE_X77Y121.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<33> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<32> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<33> + SLICE_X77Y122.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<33> + SLICE_X77Y122.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<35> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<34> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<35> + SLICE_X77Y123.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<35> + SLICE_X77Y123.XB Tcinxb 0.216 ftop/cp/WILL_FIRE_RL_completeWorkerRead + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<36> + SLICE_X86Y116.G2 net (fanout=10) 1.943 ftop/cp/WILL_FIRE_RL_completeWorkerRead + SLICE_X86Y116.Y Tilo 0.616 ftop/cp/cpRespF/d1di + ftop/cp/cpRespF_ENQ1 + SLICE_X87Y116.G4 net (fanout=7) 0.564 ftop/cp/cpRespF_ENQ + SLICE_X87Y116.Y Tilo 0.561 ftop/cp/cpRespF/N01 + ftop/cp/cpRespF/d0h1 + SLICE_X85Y111.G3 net (fanout=40) 1.199 ftop/cp/cpRespF/d0h + SLICE_X85Y111.Y Tilo 0.561 ftop/cp_server_response_get<29> + ftop/cp/cpRespF/data0_reg_or0000<29>_SW0 + SLICE_X85Y111.F2 net (fanout=1) 0.374 ftop/cp/cpRespF/data0_reg_or0000<29>_SW0/O + SLICE_X85Y111.CLK Tfck 0.602 ftop/cp_server_response_get<29> + ftop/cp/cpRespF/data0_reg_29_rstpot + ftop/cp/cpRespF/data0_reg_29 + ------------------------------------------------- --------------------------- + Total 19.461ns (8.038ns logic, 11.423ns route) + (41.3% logic, 58.7% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.614ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/cp/cpReq_23 (FF) + Destination: ftop/cp/cpRespF/data0_reg_29 (FF) + Requirement: 20.000ns + Data Path Delay: 19.334ns (Levels of Logic = 22) + Clock Path Skew: -0.052ns (0.517 - 0.569) + Source Clock: ftop/sys1Clk rising at 0.000ns + Destination Clock: ftop/sys1Clk rising at 20.000ns + Clock Uncertainty: 0.000ns + + Maximum Data Path: ftop/cp/cpReq_23 to ftop/cp/cpRespF/data0_reg_29 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X76Y106.YQ Tcko 0.596 ftop/cp/cpReq<24> + ftop/cp/cpReq_23 + SLICE_X75Y111.G1 net (fanout=19) 0.933 ftop/cp/cpReq<23> + SLICE_X75Y111.Y Tilo 0.561 ftop/cp/_theResult_____1__h75875<3> + ftop/cp/Msub_wn__h75856_xor<3>11 + SLICE_X75Y111.F4 net (fanout=2) 0.044 ftop/cp/wn__h75856<3> + SLICE_X75Y111.X Tilo 0.562 ftop/cp/_theResult_____1__h75875<3> + ftop/cp/_theResult_____1__h75875<3>1 + SLICE_X75Y137.G2 net (fanout=17) 1.840 ftop/cp/_theResult_____1__h75875<3> + SLICE_X75Y137.Y Tilo 0.561 ftop/cp/wci_reqPend_11<3> + ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F_cmp_eq00001 + SLICE_X70Y148.G2 net (fanout=11) 1.381 ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F_cmp_eq0000 + SLICE_X70Y148.Y Tilo 0.616 ftop/cp/wci_respF_11_D_IN<3>0 + ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T1 + SLICE_X77Y110.F4 net (fanout=9) 3.018 ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T + SLICE_X77Y110.COUT Topcyf 1.026 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<11> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_lut<10> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<10> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<11> + SLICE_X77Y111.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<11> + SLICE_X77Y111.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<13> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<12> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<13> + SLICE_X77Y112.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<13> + SLICE_X77Y112.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<15> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<14> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<15> + SLICE_X77Y113.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<15> + SLICE_X77Y113.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<17> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<16> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<17> + SLICE_X77Y114.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<17> + SLICE_X77Y114.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<19> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<18> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<19> + SLICE_X77Y115.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<19> + SLICE_X77Y115.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<21> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<20> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<21> + SLICE_X77Y116.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<21> + SLICE_X77Y116.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<23> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<22> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<23> + SLICE_X77Y117.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<23> + SLICE_X77Y117.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<25> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<24> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<25> + SLICE_X77Y118.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<25> + SLICE_X77Y118.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<27> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<26> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<27> + SLICE_X77Y119.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<27> + SLICE_X77Y119.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<29> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<28> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<29> + SLICE_X77Y120.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<29> + SLICE_X77Y120.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<31> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<30> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<31> + SLICE_X77Y121.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<31> + SLICE_X77Y121.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<33> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<32> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<33> + SLICE_X77Y122.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<33> + SLICE_X77Y122.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<35> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<34> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<35> + SLICE_X77Y123.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<35> + SLICE_X77Y123.XB Tcinxb 0.216 ftop/cp/WILL_FIRE_RL_completeWorkerRead + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<36> + SLICE_X86Y116.G2 net (fanout=10) 1.943 ftop/cp/WILL_FIRE_RL_completeWorkerRead + SLICE_X86Y116.Y Tilo 0.616 ftop/cp/cpRespF/d1di + ftop/cp/cpRespF_ENQ1 + SLICE_X87Y116.G4 net (fanout=7) 0.564 ftop/cp/cpRespF_ENQ + SLICE_X87Y116.Y Tilo 0.561 ftop/cp/cpRespF/N01 + ftop/cp/cpRespF/d0h1 + SLICE_X85Y111.G3 net (fanout=40) 1.199 ftop/cp/cpRespF/d0h + SLICE_X85Y111.Y Tilo 0.561 ftop/cp_server_response_get<29> + ftop/cp/cpRespF/data0_reg_or0000<29>_SW0 + SLICE_X85Y111.F2 net (fanout=1) 0.374 ftop/cp/cpRespF/data0_reg_or0000<29>_SW0/O + SLICE_X85Y111.CLK Tfck 0.602 ftop/cp_server_response_get<29> + ftop/cp/cpRespF/data0_reg_29_rstpot + ftop/cp/cpRespF/data0_reg_29 + ------------------------------------------------- --------------------------- + Total 19.334ns (8.038ns logic, 11.296ns route) + (41.6% logic, 58.4% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.660ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/cp/cpReq_25 (FF) + Destination: ftop/cp/cpRespF/data0_reg_29 (FF) + Requirement: 20.000ns + Data Path Delay: 19.263ns (Levels of Logic = 22) + Clock Path Skew: -0.077ns (0.517 - 0.594) + Source Clock: ftop/sys1Clk rising at 0.000ns + Destination Clock: ftop/sys1Clk rising at 20.000ns + Clock Uncertainty: 0.000ns + + Maximum Data Path: ftop/cp/cpReq_25 to ftop/cp/cpRespF/data0_reg_29 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X78Y106.YQ Tcko 0.596 ftop/cp/cpReq<26> + ftop/cp/cpReq_25 + SLICE_X79Y106.G3 net (fanout=6) 0.430 ftop/cp/cpReq<25> + SLICE_X79Y106.Y Tilo 0.561 ftop/cp/wn___1__h76646<3> + ftop/cp/Msub_wn___1__h76646_xor<3>11 + SLICE_X75Y111.F3 net (fanout=2) 0.476 ftop/cp/wn___1__h76646<3> + SLICE_X75Y111.X Tilo 0.562 ftop/cp/_theResult_____1__h75875<3> + ftop/cp/_theResult_____1__h75875<3>1 + SLICE_X75Y137.G2 net (fanout=17) 1.840 ftop/cp/_theResult_____1__h75875<3> + SLICE_X75Y137.Y Tilo 0.561 ftop/cp/wci_reqPend_11<3> + ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F_cmp_eq00001 + SLICE_X70Y148.G2 net (fanout=11) 1.381 ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F_cmp_eq0000 + SLICE_X70Y148.Y Tilo 0.616 ftop/cp/wci_respF_11_D_IN<3>0 + ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T1 + SLICE_X77Y110.F4 net (fanout=9) 3.018 ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T + SLICE_X77Y110.COUT Topcyf 1.026 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<11> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_lut<10> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<10> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<11> + SLICE_X77Y111.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<11> + SLICE_X77Y111.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<13> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<12> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<13> + SLICE_X77Y112.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<13> + SLICE_X77Y112.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<15> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<14> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<15> + SLICE_X77Y113.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<15> + SLICE_X77Y113.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<17> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<16> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<17> + SLICE_X77Y114.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<17> + SLICE_X77Y114.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<19> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<18> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<19> + SLICE_X77Y115.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<19> + SLICE_X77Y115.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<21> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<20> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<21> + SLICE_X77Y116.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<21> + SLICE_X77Y116.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<23> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<22> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<23> + SLICE_X77Y117.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<23> + SLICE_X77Y117.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<25> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<24> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<25> + SLICE_X77Y118.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<25> + SLICE_X77Y118.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<27> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<26> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<27> + SLICE_X77Y119.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<27> + SLICE_X77Y119.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<29> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<28> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<29> + SLICE_X77Y120.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<29> + SLICE_X77Y120.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<31> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<30> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<31> + SLICE_X77Y121.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<31> + SLICE_X77Y121.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<33> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<32> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<33> + SLICE_X77Y122.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<33> + SLICE_X77Y122.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<35> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<34> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<35> + SLICE_X77Y123.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<35> + SLICE_X77Y123.XB Tcinxb 0.216 ftop/cp/WILL_FIRE_RL_completeWorkerRead + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<36> + SLICE_X86Y116.G2 net (fanout=10) 1.943 ftop/cp/WILL_FIRE_RL_completeWorkerRead + SLICE_X86Y116.Y Tilo 0.616 ftop/cp/cpRespF/d1di + ftop/cp/cpRespF_ENQ1 + SLICE_X87Y116.G4 net (fanout=7) 0.564 ftop/cp/cpRespF_ENQ + SLICE_X87Y116.Y Tilo 0.561 ftop/cp/cpRespF/N01 + ftop/cp/cpRespF/d0h1 + SLICE_X85Y111.G3 net (fanout=40) 1.199 ftop/cp/cpRespF/d0h + SLICE_X85Y111.Y Tilo 0.561 ftop/cp_server_response_get<29> + ftop/cp/cpRespF/data0_reg_or0000<29>_SW0 + SLICE_X85Y111.F2 net (fanout=1) 0.374 ftop/cp/cpRespF/data0_reg_or0000<29>_SW0/O + SLICE_X85Y111.CLK Tfck 0.602 ftop/cp_server_response_get<29> + ftop/cp/cpRespF/data0_reg_29_rstpot + ftop/cp/cpRespF/data0_reg_29 + ------------------------------------------------- --------------------------- + Total 19.263ns (8.038ns logic, 11.225ns route) + (41.7% logic, 58.3% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.660ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/cp/cpReq_26 (FF) + Destination: ftop/cp/cpRespF/data0_reg_29 (FF) + Requirement: 20.000ns + Data Path Delay: 19.263ns (Levels of Logic = 22) + Clock Path Skew: -0.077ns (0.517 - 0.594) + Source Clock: ftop/sys1Clk rising at 0.000ns + Destination Clock: ftop/sys1Clk rising at 20.000ns + Clock Uncertainty: 0.000ns + + Maximum Data Path: ftop/cp/cpReq_26 to ftop/cp/cpRespF/data0_reg_29 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X78Y106.XQ Tcko 0.521 ftop/cp/cpReq<26> + ftop/cp/cpReq_26 + SLICE_X79Y106.G1 net (fanout=5) 0.505 ftop/cp/cpReq<26> + SLICE_X79Y106.Y Tilo 0.561 ftop/cp/wn___1__h76646<3> + ftop/cp/Msub_wn___1__h76646_xor<3>11 + SLICE_X75Y111.F3 net (fanout=2) 0.476 ftop/cp/wn___1__h76646<3> + SLICE_X75Y111.X Tilo 0.562 ftop/cp/_theResult_____1__h75875<3> + ftop/cp/_theResult_____1__h75875<3>1 + SLICE_X75Y137.G2 net (fanout=17) 1.840 ftop/cp/_theResult_____1__h75875<3> + SLICE_X75Y137.Y Tilo 0.561 ftop/cp/wci_reqPend_11<3> + ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F_cmp_eq00001 + SLICE_X70Y148.G2 net (fanout=11) 1.381 ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F_cmp_eq0000 + SLICE_X70Y148.Y Tilo 0.616 ftop/cp/wci_respF_11_D_IN<3>0 + ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T1 + SLICE_X77Y110.F4 net (fanout=9) 3.018 ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T + SLICE_X77Y110.COUT Topcyf 1.026 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<11> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_lut<10> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<10> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<11> + SLICE_X77Y111.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<11> + SLICE_X77Y111.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<13> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<12> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<13> + SLICE_X77Y112.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<13> + SLICE_X77Y112.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<15> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<14> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<15> + SLICE_X77Y113.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<15> + SLICE_X77Y113.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<17> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<16> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<17> + SLICE_X77Y114.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<17> + SLICE_X77Y114.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<19> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<18> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<19> + SLICE_X77Y115.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<19> + SLICE_X77Y115.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<21> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<20> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<21> + SLICE_X77Y116.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<21> + SLICE_X77Y116.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<23> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<22> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<23> + SLICE_X77Y117.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<23> + SLICE_X77Y117.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<25> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<24> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<25> + SLICE_X77Y118.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<25> + SLICE_X77Y118.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<27> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<26> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<27> + SLICE_X77Y119.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<27> + SLICE_X77Y119.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<29> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<28> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<29> + SLICE_X77Y120.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<29> + SLICE_X77Y120.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<31> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<30> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<31> + SLICE_X77Y121.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<31> + SLICE_X77Y121.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<33> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<32> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<33> + SLICE_X77Y122.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<33> + SLICE_X77Y122.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<35> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<34> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<35> + SLICE_X77Y123.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<35> + SLICE_X77Y123.XB Tcinxb 0.216 ftop/cp/WILL_FIRE_RL_completeWorkerRead + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<36> + SLICE_X86Y116.G2 net (fanout=10) 1.943 ftop/cp/WILL_FIRE_RL_completeWorkerRead + SLICE_X86Y116.Y Tilo 0.616 ftop/cp/cpRespF/d1di + ftop/cp/cpRespF_ENQ1 + SLICE_X87Y116.G4 net (fanout=7) 0.564 ftop/cp/cpRespF_ENQ + SLICE_X87Y116.Y Tilo 0.561 ftop/cp/cpRespF/N01 + ftop/cp/cpRespF/d0h1 + SLICE_X85Y111.G3 net (fanout=40) 1.199 ftop/cp/cpRespF/d0h + SLICE_X85Y111.Y Tilo 0.561 ftop/cp_server_response_get<29> + ftop/cp/cpRespF/data0_reg_or0000<29>_SW0 + SLICE_X85Y111.F2 net (fanout=1) 0.374 ftop/cp/cpRespF/data0_reg_or0000<29>_SW0/O + SLICE_X85Y111.CLK Tfck 0.602 ftop/cp_server_response_get<29> + ftop/cp/cpRespF/data0_reg_29_rstpot + ftop/cp/cpRespF/data0_reg_29 + ------------------------------------------------- --------------------------- + Total 19.263ns (7.963ns logic, 11.300ns route) + (41.3% logic, 58.7% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.697ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/cp/cpReq_20 (FF) + Destination: ftop/cp/cpRespF/data0_reg_29 (FF) + Requirement: 20.000ns + Data Path Delay: 19.242ns (Levels of Logic = 22) + Clock Path Skew: -0.061ns (0.517 - 0.578) + Source Clock: ftop/sys1Clk rising at 0.000ns + Destination Clock: ftop/sys1Clk rising at 20.000ns + Clock Uncertainty: 0.000ns + + Maximum Data Path: ftop/cp/cpReq_20 to ftop/cp/cpRespF/data0_reg_29 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X79Y110.XQ Tcko 0.495 ftop/cp/cpReq<20> + ftop/cp/cpReq_20 + SLICE_X75Y111.G3 net (fanout=22) 0.942 ftop/cp/cpReq<20> + SLICE_X75Y111.Y Tilo 0.561 ftop/cp/_theResult_____1__h75875<3> + ftop/cp/Msub_wn__h75856_xor<3>11 + SLICE_X75Y111.F4 net (fanout=2) 0.044 ftop/cp/wn__h75856<3> + SLICE_X75Y111.X Tilo 0.562 ftop/cp/_theResult_____1__h75875<3> + ftop/cp/_theResult_____1__h75875<3>1 + SLICE_X75Y137.G2 net (fanout=17) 1.840 ftop/cp/_theResult_____1__h75875<3> + SLICE_X75Y137.Y Tilo 0.561 ftop/cp/wci_reqPend_11<3> + ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F_cmp_eq00001 + SLICE_X70Y148.G2 net (fanout=11) 1.381 ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F_cmp_eq0000 + SLICE_X70Y148.Y Tilo 0.616 ftop/cp/wci_respF_11_D_IN<3>0 + ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T1 + SLICE_X77Y110.F4 net (fanout=9) 3.018 ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T + SLICE_X77Y110.COUT Topcyf 1.026 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<11> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_lut<10> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<10> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<11> + SLICE_X77Y111.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<11> + SLICE_X77Y111.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<13> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<12> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<13> + SLICE_X77Y112.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<13> + SLICE_X77Y112.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<15> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<14> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<15> + SLICE_X77Y113.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<15> + SLICE_X77Y113.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<17> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<16> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<17> + SLICE_X77Y114.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<17> + SLICE_X77Y114.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<19> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<18> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<19> + SLICE_X77Y115.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<19> + SLICE_X77Y115.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<21> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<20> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<21> + SLICE_X77Y116.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<21> + SLICE_X77Y116.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<23> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<22> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<23> + SLICE_X77Y117.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<23> + SLICE_X77Y117.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<25> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<24> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<25> + SLICE_X77Y118.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<25> + SLICE_X77Y118.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<27> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<26> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<27> + SLICE_X77Y119.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<27> + SLICE_X77Y119.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<29> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<28> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<29> + SLICE_X77Y120.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<29> + SLICE_X77Y120.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<31> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<30> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<31> + SLICE_X77Y121.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<31> + SLICE_X77Y121.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<33> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<32> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<33> + SLICE_X77Y122.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<33> + SLICE_X77Y122.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<35> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<34> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<35> + SLICE_X77Y123.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<35> + SLICE_X77Y123.XB Tcinxb 0.216 ftop/cp/WILL_FIRE_RL_completeWorkerRead + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<36> + SLICE_X86Y116.G2 net (fanout=10) 1.943 ftop/cp/WILL_FIRE_RL_completeWorkerRead + SLICE_X86Y116.Y Tilo 0.616 ftop/cp/cpRespF/d1di + ftop/cp/cpRespF_ENQ1 + SLICE_X87Y116.G4 net (fanout=7) 0.564 ftop/cp/cpRespF_ENQ + SLICE_X87Y116.Y Tilo 0.561 ftop/cp/cpRespF/N01 + ftop/cp/cpRespF/d0h1 + SLICE_X85Y111.G3 net (fanout=40) 1.199 ftop/cp/cpRespF/d0h + SLICE_X85Y111.Y Tilo 0.561 ftop/cp_server_response_get<29> + ftop/cp/cpRespF/data0_reg_or0000<29>_SW0 + SLICE_X85Y111.F2 net (fanout=1) 0.374 ftop/cp/cpRespF/data0_reg_or0000<29>_SW0/O + SLICE_X85Y111.CLK Tfck 0.602 ftop/cp_server_response_get<29> + ftop/cp/cpRespF/data0_reg_29_rstpot + ftop/cp/cpRespF/data0_reg_29 + ------------------------------------------------- --------------------------- + Total 19.242ns (7.937ns logic, 11.305ns route) + (41.2% logic, 58.8% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.720ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/cp/cpReq_24 (FF) + Destination: ftop/cp/cpRespF/data0_reg_29 (FF) + Requirement: 20.000ns + Data Path Delay: 19.228ns (Levels of Logic = 22) + Clock Path Skew: -0.052ns (0.517 - 0.569) + Source Clock: ftop/sys1Clk rising at 0.000ns + Destination Clock: ftop/sys1Clk rising at 20.000ns + Clock Uncertainty: 0.000ns + + Maximum Data Path: ftop/cp/cpReq_24 to ftop/cp/cpRespF/data0_reg_29 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X76Y106.XQ Tcko 0.521 ftop/cp/cpReq<24> + ftop/cp/cpReq_24 + SLICE_X79Y106.G2 net (fanout=8) 0.470 ftop/cp/cpReq<24> + SLICE_X79Y106.Y Tilo 0.561 ftop/cp/wn___1__h76646<3> + ftop/cp/Msub_wn___1__h76646_xor<3>11 + SLICE_X75Y111.F3 net (fanout=2) 0.476 ftop/cp/wn___1__h76646<3> + SLICE_X75Y111.X Tilo 0.562 ftop/cp/_theResult_____1__h75875<3> + ftop/cp/_theResult_____1__h75875<3>1 + SLICE_X75Y137.G2 net (fanout=17) 1.840 ftop/cp/_theResult_____1__h75875<3> + SLICE_X75Y137.Y Tilo 0.561 ftop/cp/wci_reqPend_11<3> + ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F_cmp_eq00001 + SLICE_X70Y148.G2 net (fanout=11) 1.381 ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F_cmp_eq0000 + SLICE_X70Y148.Y Tilo 0.616 ftop/cp/wci_respF_11_D_IN<3>0 + ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T1 + SLICE_X77Y110.F4 net (fanout=9) 3.018 ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T + SLICE_X77Y110.COUT Topcyf 1.026 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<11> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_lut<10> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<10> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<11> + SLICE_X77Y111.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<11> + SLICE_X77Y111.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<13> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<12> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<13> + SLICE_X77Y112.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<13> + SLICE_X77Y112.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<15> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<14> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<15> + SLICE_X77Y113.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<15> + SLICE_X77Y113.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<17> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<16> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<17> + SLICE_X77Y114.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<17> + SLICE_X77Y114.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<19> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<18> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<19> + SLICE_X77Y115.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<19> + SLICE_X77Y115.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<21> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<20> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<21> + SLICE_X77Y116.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<21> + SLICE_X77Y116.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<23> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<22> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<23> + SLICE_X77Y117.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<23> + SLICE_X77Y117.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<25> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<24> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<25> + SLICE_X77Y118.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<25> + SLICE_X77Y118.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<27> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<26> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<27> + SLICE_X77Y119.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<27> + SLICE_X77Y119.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<29> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<28> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<29> + SLICE_X77Y120.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<29> + SLICE_X77Y120.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<31> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<30> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<31> + SLICE_X77Y121.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<31> + SLICE_X77Y121.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<33> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<32> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<33> + SLICE_X77Y122.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<33> + SLICE_X77Y122.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<35> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<34> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<35> + SLICE_X77Y123.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<35> + SLICE_X77Y123.XB Tcinxb 0.216 ftop/cp/WILL_FIRE_RL_completeWorkerRead + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<36> + SLICE_X86Y116.G2 net (fanout=10) 1.943 ftop/cp/WILL_FIRE_RL_completeWorkerRead + SLICE_X86Y116.Y Tilo 0.616 ftop/cp/cpRespF/d1di + ftop/cp/cpRespF_ENQ1 + SLICE_X87Y116.G4 net (fanout=7) 0.564 ftop/cp/cpRespF_ENQ + SLICE_X87Y116.Y Tilo 0.561 ftop/cp/cpRespF/N01 + ftop/cp/cpRespF/d0h1 + SLICE_X85Y111.G3 net (fanout=40) 1.199 ftop/cp/cpRespF/d0h + SLICE_X85Y111.Y Tilo 0.561 ftop/cp_server_response_get<29> + ftop/cp/cpRespF/data0_reg_or0000<29>_SW0 + SLICE_X85Y111.F2 net (fanout=1) 0.374 ftop/cp/cpRespF/data0_reg_or0000<29>_SW0/O + SLICE_X85Y111.CLK Tfck 0.602 ftop/cp_server_response_get<29> + ftop/cp/cpRespF/data0_reg_29_rstpot + ftop/cp/cpRespF/data0_reg_29 + ------------------------------------------------- --------------------------- + Total 19.228ns (7.963ns logic, 11.265ns route) + (41.4% logic, 58.6% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.727ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/cp/cpReq_37 (FF) + Destination: ftop/cp/cpRespF/data0_reg_29 (FF) + Requirement: 20.000ns + Data Path Delay: 19.212ns (Levels of Logic = 22) + Clock Path Skew: -0.061ns (0.517 - 0.578) + Source Clock: ftop/sys1Clk rising at 0.000ns + Destination Clock: ftop/sys1Clk rising at 20.000ns + Clock Uncertainty: 0.000ns + + Maximum Data Path: ftop/cp/cpReq_37 to ftop/cp/cpRespF/data0_reg_29 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X78Y110.XQ Tcko 0.521 ftop/cp/cpReq<37> + ftop/cp/cpReq_37 + SLICE_X76Y112.G1 net (fanout=38) 0.773 ftop/cp/cpReq<37> + SLICE_X76Y112.Y Tilo 0.616 ftop/cp/_theResult_____1__h75875<2> + ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_T_T_F_cmp_eq00011 + SLICE_X76Y113.F1 net (fanout=5) 0.413 ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_T_T_F_cmp_eq0001 + SLICE_X76Y113.X Tilo 0.601 ftop/cp/_theResult_____1__h75875<1> + ftop/cp/_theResult_____1__h75875<1>1 + SLICE_X75Y137.G4 net (fanout=17) 1.490 ftop/cp/_theResult_____1__h75875<1> + SLICE_X75Y137.Y Tilo 0.561 ftop/cp/wci_reqPend_11<3> + ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F_cmp_eq00001 + SLICE_X70Y148.G2 net (fanout=11) 1.381 ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F_cmp_eq0000 + SLICE_X70Y148.Y Tilo 0.616 ftop/cp/wci_respF_11_D_IN<3>0 + ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T1 + SLICE_X77Y110.F4 net (fanout=9) 3.018 ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T + SLICE_X77Y110.COUT Topcyf 1.026 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<11> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_lut<10> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<10> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<11> + SLICE_X77Y111.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<11> + SLICE_X77Y111.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<13> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<12> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<13> + SLICE_X77Y112.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<13> + SLICE_X77Y112.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<15> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<14> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<15> + SLICE_X77Y113.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<15> + SLICE_X77Y113.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<17> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<16> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<17> + SLICE_X77Y114.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<17> + SLICE_X77Y114.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<19> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<18> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<19> + SLICE_X77Y115.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<19> + SLICE_X77Y115.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<21> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<20> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<21> + SLICE_X77Y116.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<21> + SLICE_X77Y116.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<23> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<22> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<23> + SLICE_X77Y117.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<23> + SLICE_X77Y117.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<25> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<24> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<25> + SLICE_X77Y118.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<25> + SLICE_X77Y118.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<27> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<26> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<27> + SLICE_X77Y119.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<27> + SLICE_X77Y119.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<29> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<28> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<29> + SLICE_X77Y120.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<29> + SLICE_X77Y120.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<31> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<30> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<31> + SLICE_X77Y121.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<31> + SLICE_X77Y121.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<33> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<32> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<33> + SLICE_X77Y122.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<33> + SLICE_X77Y122.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<35> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<34> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<35> + SLICE_X77Y123.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<35> + SLICE_X77Y123.XB Tcinxb 0.216 ftop/cp/WILL_FIRE_RL_completeWorkerRead + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<36> + SLICE_X86Y116.G2 net (fanout=10) 1.943 ftop/cp/WILL_FIRE_RL_completeWorkerRead + SLICE_X86Y116.Y Tilo 0.616 ftop/cp/cpRespF/d1di + ftop/cp/cpRespF_ENQ1 + SLICE_X87Y116.G4 net (fanout=7) 0.564 ftop/cp/cpRespF_ENQ + SLICE_X87Y116.Y Tilo 0.561 ftop/cp/cpRespF/N01 + ftop/cp/cpRespF/d0h1 + SLICE_X85Y111.G3 net (fanout=40) 1.199 ftop/cp/cpRespF/d0h + SLICE_X85Y111.Y Tilo 0.561 ftop/cp_server_response_get<29> + ftop/cp/cpRespF/data0_reg_or0000<29>_SW0 + SLICE_X85Y111.F2 net (fanout=1) 0.374 ftop/cp/cpRespF/data0_reg_or0000<29>_SW0/O + SLICE_X85Y111.CLK Tfck 0.602 ftop/cp_server_response_get<29> + ftop/cp/cpRespF/data0_reg_29_rstpot + ftop/cp/cpRespF/data0_reg_29 + ------------------------------------------------- --------------------------- + Total 19.212ns (8.057ns logic, 11.155ns route) + (41.9% logic, 58.1% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.747ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/cp/cpReq_27 (FF) + Destination: ftop/cp/cpRespF/data0_reg_0 (FF) + Requirement: 20.000ns + Data Path Delay: 19.192ns (Levels of Logic = 22) + Clock Path Skew: -0.061ns (0.321 - 0.382) + Source Clock: ftop/sys1Clk rising at 0.000ns + Destination Clock: ftop/sys1Clk rising at 20.000ns + Clock Uncertainty: 0.000ns + + Maximum Data Path: ftop/cp/cpReq_27 to ftop/cp/cpRespF/data0_reg_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X84Y107.YQ Tcko 0.596 ftop/cp/cpReq<28> + ftop/cp/cpReq_27 + SLICE_X79Y106.G4 net (fanout=3) 0.628 ftop/cp/cpReq<27> + SLICE_X79Y106.Y Tilo 0.561 ftop/cp/wn___1__h76646<3> + ftop/cp/Msub_wn___1__h76646_xor<3>11 + SLICE_X75Y111.F3 net (fanout=2) 0.476 ftop/cp/wn___1__h76646<3> + SLICE_X75Y111.X Tilo 0.562 ftop/cp/_theResult_____1__h75875<3> + ftop/cp/_theResult_____1__h75875<3>1 + SLICE_X75Y137.G2 net (fanout=17) 1.840 ftop/cp/_theResult_____1__h75875<3> + SLICE_X75Y137.Y Tilo 0.561 ftop/cp/wci_reqPend_11<3> + ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F_cmp_eq00001 + SLICE_X70Y148.G2 net (fanout=11) 1.381 ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F_cmp_eq0000 + SLICE_X70Y148.Y Tilo 0.616 ftop/cp/wci_respF_11_D_IN<3>0 + ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T1 + SLICE_X77Y110.F4 net (fanout=9) 3.018 ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T + SLICE_X77Y110.COUT Topcyf 1.026 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<11> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_lut<10> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<10> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<11> + SLICE_X77Y111.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<11> + SLICE_X77Y111.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<13> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<12> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<13> + SLICE_X77Y112.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<13> + SLICE_X77Y112.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<15> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<14> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<15> + SLICE_X77Y113.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<15> + SLICE_X77Y113.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<17> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<16> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<17> + SLICE_X77Y114.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<17> + SLICE_X77Y114.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<19> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<18> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<19> + SLICE_X77Y115.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<19> + SLICE_X77Y115.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<21> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<20> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<21> + SLICE_X77Y116.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<21> + SLICE_X77Y116.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<23> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<22> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<23> + SLICE_X77Y117.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<23> + SLICE_X77Y117.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<25> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<24> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<25> + SLICE_X77Y118.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<25> + SLICE_X77Y118.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<27> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<26> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<27> + SLICE_X77Y119.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<27> + SLICE_X77Y119.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<29> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<28> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<29> + SLICE_X77Y120.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<29> + SLICE_X77Y120.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<31> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<30> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<31> + SLICE_X77Y121.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<31> + SLICE_X77Y121.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<33> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<32> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<33> + SLICE_X77Y122.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<33> + SLICE_X77Y122.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<35> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<34> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<35> + SLICE_X77Y123.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<35> + SLICE_X77Y123.XB Tcinxb 0.216 ftop/cp/WILL_FIRE_RL_completeWorkerRead + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<36> + SLICE_X86Y116.G2 net (fanout=10) 1.943 ftop/cp/WILL_FIRE_RL_completeWorkerRead + SLICE_X86Y116.Y Tilo 0.616 ftop/cp/cpRespF/d1di + ftop/cp/cpRespF_ENQ1 + SLICE_X87Y116.G4 net (fanout=7) 0.564 ftop/cp/cpRespF_ENQ + SLICE_X87Y116.Y Tilo 0.561 ftop/cp/cpRespF/N01 + ftop/cp/cpRespF/d0h1 + SLICE_X90Y113.G2 net (fanout=40) 1.174 ftop/cp/cpRespF/d0h + SLICE_X90Y113.Y Tilo 0.616 ftop/cp_server_response_get<0> + ftop/cp/cpRespF/data0_reg_or0000<0>_SW0 + SLICE_X90Y113.F3 net (fanout=1) 0.021 ftop/cp/cpRespF/data0_reg_or0000<0>_SW0/O + SLICE_X90Y113.CLK Tfck 0.656 ftop/cp_server_response_get<0> + ftop/cp/cpRespF/data0_reg_0_rstpot + ftop/cp/cpRespF/data0_reg_0 + ------------------------------------------------- --------------------------- + Total 19.192ns (8.147ns logic, 11.045ns route) + (42.4% logic, 57.6% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.767ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/cp/cpReq_27 (FF) + Destination: ftop/cp/cpRespF/data0_reg_34 (FF) + Requirement: 20.000ns + Data Path Delay: 19.218ns (Levels of Logic = 22) + Clock Path Skew: -0.015ns (0.367 - 0.382) + Source Clock: ftop/sys1Clk rising at 0.000ns + Destination Clock: ftop/sys1Clk rising at 20.000ns + Clock Uncertainty: 0.000ns + + Maximum Data Path: ftop/cp/cpReq_27 to ftop/cp/cpRespF/data0_reg_34 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X84Y107.YQ Tcko 0.596 ftop/cp/cpReq<28> + ftop/cp/cpReq_27 + SLICE_X79Y106.G4 net (fanout=3) 0.628 ftop/cp/cpReq<27> + SLICE_X79Y106.Y Tilo 0.561 ftop/cp/wn___1__h76646<3> + ftop/cp/Msub_wn___1__h76646_xor<3>11 + SLICE_X75Y111.F3 net (fanout=2) 0.476 ftop/cp/wn___1__h76646<3> + SLICE_X75Y111.X Tilo 0.562 ftop/cp/_theResult_____1__h75875<3> + ftop/cp/_theResult_____1__h75875<3>1 + SLICE_X75Y137.G2 net (fanout=17) 1.840 ftop/cp/_theResult_____1__h75875<3> + SLICE_X75Y137.Y Tilo 0.561 ftop/cp/wci_reqPend_11<3> + ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F_cmp_eq00001 + SLICE_X70Y148.G2 net (fanout=11) 1.381 ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F_cmp_eq0000 + SLICE_X70Y148.Y Tilo 0.616 ftop/cp/wci_respF_11_D_IN<3>0 + ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T1 + SLICE_X77Y110.F4 net (fanout=9) 3.018 ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T + SLICE_X77Y110.COUT Topcyf 1.026 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<11> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_lut<10> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<10> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<11> + SLICE_X77Y111.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<11> + SLICE_X77Y111.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<13> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<12> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<13> + SLICE_X77Y112.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<13> + SLICE_X77Y112.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<15> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<14> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<15> + SLICE_X77Y113.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<15> + SLICE_X77Y113.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<17> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<16> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<17> + SLICE_X77Y114.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<17> + SLICE_X77Y114.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<19> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<18> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<19> + SLICE_X77Y115.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<19> + SLICE_X77Y115.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<21> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<20> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<21> + SLICE_X77Y116.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<21> + SLICE_X77Y116.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<23> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<22> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<23> + SLICE_X77Y117.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<23> + SLICE_X77Y117.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<25> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<24> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<25> + SLICE_X77Y118.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<25> + SLICE_X77Y118.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<27> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<26> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<27> + SLICE_X77Y119.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<27> + SLICE_X77Y119.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<29> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<28> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<29> + SLICE_X77Y120.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<29> + SLICE_X77Y120.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<31> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<30> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<31> + SLICE_X77Y121.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<31> + SLICE_X77Y121.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<33> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<32> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<33> + SLICE_X77Y122.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<33> + SLICE_X77Y122.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<35> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<34> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<35> + SLICE_X77Y123.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<35> + SLICE_X77Y123.XB Tcinxb 0.216 ftop/cp/WILL_FIRE_RL_completeWorkerRead + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<36> + SLICE_X86Y116.G2 net (fanout=10) 1.943 ftop/cp/WILL_FIRE_RL_completeWorkerRead + SLICE_X86Y116.Y Tilo 0.616 ftop/cp/cpRespF/d1di + ftop/cp/cpRespF_ENQ1 + SLICE_X87Y116.G4 net (fanout=7) 0.564 ftop/cp/cpRespF_ENQ + SLICE_X87Y116.Y Tilo 0.561 ftop/cp/cpRespF/N01 + ftop/cp/cpRespF/d0h1 + SLICE_X92Y110.G4 net (fanout=40) 1.186 ftop/cp/cpRespF/d0h + SLICE_X92Y110.Y Tilo 0.616 ftop/cp_server_response_get<34> + ftop/cp/cpRespF/data0_reg_or0000<34>_SW0 + SLICE_X92Y110.F4 net (fanout=1) 0.035 ftop/cp/cpRespF/data0_reg_or0000<34>_SW0/O + SLICE_X92Y110.CLK Tfck 0.656 ftop/cp_server_response_get<34> + ftop/cp/cpRespF/data0_reg_34_rstpot + ftop/cp/cpRespF/data0_reg_34 + ------------------------------------------------- --------------------------- + Total 19.218ns (8.147ns logic, 11.071ns route) + (42.4% logic, 57.6% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.769ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/cp/cpReq_37 (FF) + Destination: ftop/cp/cpRespF/data0_reg_29 (FF) + Requirement: 20.000ns + Data Path Delay: 19.170ns (Levels of Logic = 14) + Clock Path Skew: -0.061ns (0.517 - 0.578) + Source Clock: ftop/sys1Clk rising at 0.000ns + Destination Clock: ftop/sys1Clk rising at 20.000ns + Clock Uncertainty: 0.000ns + + Maximum Data Path: ftop/cp/cpReq_37 to ftop/cp/cpRespF/data0_reg_29 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X78Y110.XQ Tcko 0.521 ftop/cp/cpReq<37> + ftop/cp/cpReq_37 + SLICE_X76Y112.G1 net (fanout=38) 0.773 ftop/cp/cpReq<37> + SLICE_X76Y112.Y Tilo 0.616 ftop/cp/_theResult_____1__h75875<2> + ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_T_T_F_cmp_eq00011 + SLICE_X76Y113.F1 net (fanout=5) 0.413 ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_T_T_F_cmp_eq0001 + SLICE_X76Y113.X Tilo 0.601 ftop/cp/_theResult_____1__h75875<1> + ftop/cp/_theResult_____1__h75875<1>1 + SLICE_X68Y148.G3 net (fanout=17) 3.268 ftop/cp/_theResult_____1__h75875<1> + SLICE_X68Y148.Y Tilo 0.616 ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_T_F_F_F_F_T + ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_T_T_F_cmp_eq00001 + SLICE_X68Y150.G3 net (fanout=10) 0.383 ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_T_T_F_cmp_eq0000 + SLICE_X68Y150.Y Tilo 0.616 ftop/cp/wci_respF_D_IN<3>0 + ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_T_F_F_F_T1 + SLICE_X77Y118.F4 net (fanout=9) 3.181 ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_T_F_F_F_T + SLICE_X77Y118.COUT Topcyf 1.026 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<27> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_lut<26> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<26> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<27> + SLICE_X77Y119.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<27> + SLICE_X77Y119.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<29> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<28> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<29> + SLICE_X77Y120.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<29> + SLICE_X77Y120.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<31> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<30> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<31> + SLICE_X77Y121.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<31> + SLICE_X77Y121.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<33> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<32> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<33> + SLICE_X77Y122.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<33> + SLICE_X77Y122.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<35> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<34> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<35> + SLICE_X77Y123.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<35> + SLICE_X77Y123.XB Tcinxb 0.216 ftop/cp/WILL_FIRE_RL_completeWorkerRead + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<36> + SLICE_X86Y116.G2 net (fanout=10) 1.943 ftop/cp/WILL_FIRE_RL_completeWorkerRead + SLICE_X86Y116.Y Tilo 0.616 ftop/cp/cpRespF/d1di + ftop/cp/cpRespF_ENQ1 + SLICE_X87Y116.G4 net (fanout=7) 0.564 ftop/cp/cpRespF_ENQ + SLICE_X87Y116.Y Tilo 0.561 ftop/cp/cpRespF/N01 + ftop/cp/cpRespF/d0h1 + SLICE_X85Y111.G3 net (fanout=40) 1.199 ftop/cp/cpRespF/d0h + SLICE_X85Y111.Y Tilo 0.561 ftop/cp_server_response_get<29> + ftop/cp/cpRespF/data0_reg_or0000<29>_SW0 + SLICE_X85Y111.F2 net (fanout=1) 0.374 ftop/cp/cpRespF/data0_reg_or0000<29>_SW0/O + SLICE_X85Y111.CLK Tfck 0.602 ftop/cp_server_response_get<29> + ftop/cp/cpRespF/data0_reg_29_rstpot + ftop/cp/cpRespF/data0_reg_29 + ------------------------------------------------- --------------------------- + Total 19.170ns (7.072ns logic, 12.098ns route) + (36.9% logic, 63.1% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.815ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/cp/cpReq_27 (FF) + Destination: ftop/cp/cpRespF/data0_reg_8 (FF) + Requirement: 20.000ns + Data Path Delay: 19.117ns (Levels of Logic = 22) + Clock Path Skew: -0.068ns (0.314 - 0.382) + Source Clock: ftop/sys1Clk rising at 0.000ns + Destination Clock: ftop/sys1Clk rising at 20.000ns + Clock Uncertainty: 0.000ns + + Maximum Data Path: ftop/cp/cpReq_27 to ftop/cp/cpRespF/data0_reg_8 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X84Y107.YQ Tcko 0.596 ftop/cp/cpReq<28> + ftop/cp/cpReq_27 + SLICE_X79Y106.G4 net (fanout=3) 0.628 ftop/cp/cpReq<27> + SLICE_X79Y106.Y Tilo 0.561 ftop/cp/wn___1__h76646<3> + ftop/cp/Msub_wn___1__h76646_xor<3>11 + SLICE_X75Y111.F3 net (fanout=2) 0.476 ftop/cp/wn___1__h76646<3> + SLICE_X75Y111.X Tilo 0.562 ftop/cp/_theResult_____1__h75875<3> + ftop/cp/_theResult_____1__h75875<3>1 + SLICE_X75Y137.G2 net (fanout=17) 1.840 ftop/cp/_theResult_____1__h75875<3> + SLICE_X75Y137.Y Tilo 0.561 ftop/cp/wci_reqPend_11<3> + ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F_cmp_eq00001 + SLICE_X70Y148.G2 net (fanout=11) 1.381 ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F_cmp_eq0000 + SLICE_X70Y148.Y Tilo 0.616 ftop/cp/wci_respF_11_D_IN<3>0 + ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T1 + SLICE_X77Y110.F4 net (fanout=9) 3.018 ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T + SLICE_X77Y110.COUT Topcyf 1.026 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<11> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_lut<10> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<10> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<11> + SLICE_X77Y111.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<11> + SLICE_X77Y111.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<13> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<12> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<13> + SLICE_X77Y112.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<13> + SLICE_X77Y112.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<15> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<14> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<15> + SLICE_X77Y113.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<15> + SLICE_X77Y113.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<17> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<16> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<17> + SLICE_X77Y114.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<17> + SLICE_X77Y114.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<19> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<18> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<19> + SLICE_X77Y115.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<19> + SLICE_X77Y115.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<21> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<20> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<21> + SLICE_X77Y116.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<21> + SLICE_X77Y116.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<23> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<22> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<23> + SLICE_X77Y117.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<23> + SLICE_X77Y117.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<25> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<24> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<25> + SLICE_X77Y118.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<25> + SLICE_X77Y118.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<27> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<26> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<27> + SLICE_X77Y119.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<27> + SLICE_X77Y119.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<29> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<28> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<29> + SLICE_X77Y120.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<29> + SLICE_X77Y120.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<31> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<30> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<31> + SLICE_X77Y121.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<31> + SLICE_X77Y121.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<33> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<32> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<33> + SLICE_X77Y122.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<33> + SLICE_X77Y122.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<35> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<34> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<35> + SLICE_X77Y123.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<35> + SLICE_X77Y123.XB Tcinxb 0.216 ftop/cp/WILL_FIRE_RL_completeWorkerRead + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<36> + SLICE_X86Y116.G2 net (fanout=10) 1.943 ftop/cp/WILL_FIRE_RL_completeWorkerRead + SLICE_X86Y116.Y Tilo 0.616 ftop/cp/cpRespF/d1di + ftop/cp/cpRespF_ENQ1 + SLICE_X87Y116.G4 net (fanout=7) 0.564 ftop/cp/cpRespF_ENQ + SLICE_X87Y116.Y Tilo 0.561 ftop/cp/cpRespF/N01 + ftop/cp/cpRespF/d0h1 + SLICE_X88Y112.G3 net (fanout=40) 1.085 ftop/cp/cpRespF/d0h + SLICE_X88Y112.Y Tilo 0.616 ftop/cp_server_response_get<8> + ftop/cp/cpRespF/data0_reg_or0000<8>_SW0 + SLICE_X88Y112.F4 net (fanout=1) 0.035 ftop/cp/cpRespF/data0_reg_or0000<8>_SW0/O + SLICE_X88Y112.CLK Tfck 0.656 ftop/cp_server_response_get<8> + ftop/cp/cpRespF/data0_reg_8_rstpot + ftop/cp/cpRespF/data0_reg_8 + ------------------------------------------------- --------------------------- + Total 19.117ns (8.147ns logic, 10.970ns route) + (42.6% logic, 57.4% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.829ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/cp/cpReq_27 (FF) + Destination: ftop/cp/cpRespF/data0_reg_6 (FF) + Requirement: 20.000ns + Data Path Delay: 19.103ns (Levels of Logic = 22) + Clock Path Skew: -0.068ns (0.314 - 0.382) + Source Clock: ftop/sys1Clk rising at 0.000ns + Destination Clock: ftop/sys1Clk rising at 20.000ns + Clock Uncertainty: 0.000ns + + Maximum Data Path: ftop/cp/cpReq_27 to ftop/cp/cpRespF/data0_reg_6 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X84Y107.YQ Tcko 0.596 ftop/cp/cpReq<28> + ftop/cp/cpReq_27 + SLICE_X79Y106.G4 net (fanout=3) 0.628 ftop/cp/cpReq<27> + SLICE_X79Y106.Y Tilo 0.561 ftop/cp/wn___1__h76646<3> + ftop/cp/Msub_wn___1__h76646_xor<3>11 + SLICE_X75Y111.F3 net (fanout=2) 0.476 ftop/cp/wn___1__h76646<3> + SLICE_X75Y111.X Tilo 0.562 ftop/cp/_theResult_____1__h75875<3> + ftop/cp/_theResult_____1__h75875<3>1 + SLICE_X75Y137.G2 net (fanout=17) 1.840 ftop/cp/_theResult_____1__h75875<3> + SLICE_X75Y137.Y Tilo 0.561 ftop/cp/wci_reqPend_11<3> + ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F_cmp_eq00001 + SLICE_X70Y148.G2 net (fanout=11) 1.381 ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F_cmp_eq0000 + SLICE_X70Y148.Y Tilo 0.616 ftop/cp/wci_respF_11_D_IN<3>0 + ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T1 + SLICE_X77Y110.F4 net (fanout=9) 3.018 ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T + SLICE_X77Y110.COUT Topcyf 1.026 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<11> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_lut<10> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<10> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<11> + SLICE_X77Y111.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<11> + SLICE_X77Y111.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<13> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<12> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<13> + SLICE_X77Y112.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<13> + SLICE_X77Y112.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<15> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<14> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<15> + SLICE_X77Y113.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<15> + SLICE_X77Y113.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<17> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<16> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<17> + SLICE_X77Y114.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<17> + SLICE_X77Y114.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<19> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<18> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<19> + SLICE_X77Y115.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<19> + SLICE_X77Y115.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<21> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<20> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<21> + SLICE_X77Y116.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<21> + SLICE_X77Y116.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<23> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<22> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<23> + SLICE_X77Y117.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<23> + SLICE_X77Y117.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<25> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<24> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<25> + SLICE_X77Y118.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<25> + SLICE_X77Y118.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<27> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<26> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<27> + SLICE_X77Y119.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<27> + SLICE_X77Y119.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<29> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<28> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<29> + SLICE_X77Y120.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<29> + SLICE_X77Y120.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<31> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<30> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<31> + SLICE_X77Y121.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<31> + SLICE_X77Y121.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<33> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<32> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<33> + SLICE_X77Y122.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<33> + SLICE_X77Y122.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<35> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<34> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<35> + SLICE_X77Y123.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<35> + SLICE_X77Y123.XB Tcinxb 0.216 ftop/cp/WILL_FIRE_RL_completeWorkerRead + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<36> + SLICE_X86Y116.G2 net (fanout=10) 1.943 ftop/cp/WILL_FIRE_RL_completeWorkerRead + SLICE_X86Y116.Y Tilo 0.616 ftop/cp/cpRespF/d1di + ftop/cp/cpRespF_ENQ1 + SLICE_X87Y116.G4 net (fanout=7) 0.564 ftop/cp/cpRespF_ENQ + SLICE_X87Y116.Y Tilo 0.561 ftop/cp/cpRespF/N01 + ftop/cp/cpRespF/d0h1 + SLICE_X88Y113.G3 net (fanout=40) 1.085 ftop/cp/cpRespF/d0h + SLICE_X88Y113.Y Tilo 0.616 ftop/cp_server_response_get<6> + ftop/cp/cpRespF/data0_reg_or0000<6>_SW0 + SLICE_X88Y113.F3 net (fanout=1) 0.021 ftop/cp/cpRespF/data0_reg_or0000<6>_SW0/O + SLICE_X88Y113.CLK Tfck 0.656 ftop/cp_server_response_get<6> + ftop/cp/cpRespF/data0_reg_6_rstpot + ftop/cp/cpRespF/data0_reg_6 + ------------------------------------------------- --------------------------- + Total 19.103ns (8.147ns logic, 10.956ns route) + (42.6% logic, 57.4% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.834ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/cp/cpReq_27 (FF) + Destination: ftop/cp/cpRespF/data0_reg_33 (FF) + Requirement: 20.000ns + Data Path Delay: 19.151ns (Levels of Logic = 22) + Clock Path Skew: -0.015ns (0.367 - 0.382) + Source Clock: ftop/sys1Clk rising at 0.000ns + Destination Clock: ftop/sys1Clk rising at 20.000ns + Clock Uncertainty: 0.000ns + + Maximum Data Path: ftop/cp/cpReq_27 to ftop/cp/cpRespF/data0_reg_33 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X84Y107.YQ Tcko 0.596 ftop/cp/cpReq<28> + ftop/cp/cpReq_27 + SLICE_X79Y106.G4 net (fanout=3) 0.628 ftop/cp/cpReq<27> + SLICE_X79Y106.Y Tilo 0.561 ftop/cp/wn___1__h76646<3> + ftop/cp/Msub_wn___1__h76646_xor<3>11 + SLICE_X75Y111.F3 net (fanout=2) 0.476 ftop/cp/wn___1__h76646<3> + SLICE_X75Y111.X Tilo 0.562 ftop/cp/_theResult_____1__h75875<3> + ftop/cp/_theResult_____1__h75875<3>1 + SLICE_X75Y137.G2 net (fanout=17) 1.840 ftop/cp/_theResult_____1__h75875<3> + SLICE_X75Y137.Y Tilo 0.561 ftop/cp/wci_reqPend_11<3> + ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F_cmp_eq00001 + SLICE_X70Y148.G2 net (fanout=11) 1.381 ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F_cmp_eq0000 + SLICE_X70Y148.Y Tilo 0.616 ftop/cp/wci_respF_11_D_IN<3>0 + ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T1 + SLICE_X77Y110.F4 net (fanout=9) 3.018 ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T + SLICE_X77Y110.COUT Topcyf 1.026 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<11> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_lut<10> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<10> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<11> + SLICE_X77Y111.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<11> + SLICE_X77Y111.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<13> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<12> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<13> + SLICE_X77Y112.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<13> + SLICE_X77Y112.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<15> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<14> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<15> + SLICE_X77Y113.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<15> + SLICE_X77Y113.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<17> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<16> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<17> + SLICE_X77Y114.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<17> + SLICE_X77Y114.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<19> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<18> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<19> + SLICE_X77Y115.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<19> + SLICE_X77Y115.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<21> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<20> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<21> + SLICE_X77Y116.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<21> + SLICE_X77Y116.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<23> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<22> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<23> + SLICE_X77Y117.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<23> + SLICE_X77Y117.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<25> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<24> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<25> + SLICE_X77Y118.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<25> + SLICE_X77Y118.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<27> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<26> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<27> + SLICE_X77Y119.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<27> + SLICE_X77Y119.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<29> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<28> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<29> + SLICE_X77Y120.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<29> + SLICE_X77Y120.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<31> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<30> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<31> + SLICE_X77Y121.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<31> + SLICE_X77Y121.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<33> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<32> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<33> + SLICE_X77Y122.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<33> + SLICE_X77Y122.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<35> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<34> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<35> + SLICE_X77Y123.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<35> + SLICE_X77Y123.XB Tcinxb 0.216 ftop/cp/WILL_FIRE_RL_completeWorkerRead + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<36> + SLICE_X86Y116.G2 net (fanout=10) 1.943 ftop/cp/WILL_FIRE_RL_completeWorkerRead + SLICE_X86Y116.Y Tilo 0.616 ftop/cp/cpRespF/d1di + ftop/cp/cpRespF_ENQ1 + SLICE_X87Y116.G4 net (fanout=7) 0.564 ftop/cp/cpRespF_ENQ + SLICE_X87Y116.Y Tilo 0.561 ftop/cp/cpRespF/N01 + ftop/cp/cpRespF/d0h1 + SLICE_X93Y111.G1 net (fanout=40) 1.241 ftop/cp/cpRespF/d0h + SLICE_X93Y111.Y Tilo 0.561 ftop/cp_server_response_get<33> + ftop/cp/cpRespF/data0_reg_or0000<33>_SW0 + SLICE_X93Y111.F4 net (fanout=1) 0.022 ftop/cp/cpRespF/data0_reg_or0000<33>_SW0/O + SLICE_X93Y111.CLK Tfck 0.602 ftop/cp_server_response_get<33> + ftop/cp/cpRespF/data0_reg_33_rstpot + ftop/cp/cpRespF/data0_reg_33 + ------------------------------------------------- --------------------------- + Total 19.151ns (8.038ns logic, 11.113ns route) + (42.0% logic, 58.0% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.862ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/cp/cpReq_27 (FF) + Destination: ftop/cp/cpRespF/data0_reg_26 (FF) + Requirement: 20.000ns + Data Path Delay: 19.096ns (Levels of Logic = 22) + Clock Path Skew: -0.042ns (0.340 - 0.382) + Source Clock: ftop/sys1Clk rising at 0.000ns + Destination Clock: ftop/sys1Clk rising at 20.000ns + Clock Uncertainty: 0.000ns + + Maximum Data Path: ftop/cp/cpReq_27 to ftop/cp/cpRespF/data0_reg_26 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X84Y107.YQ Tcko 0.596 ftop/cp/cpReq<28> + ftop/cp/cpReq_27 + SLICE_X79Y106.G4 net (fanout=3) 0.628 ftop/cp/cpReq<27> + SLICE_X79Y106.Y Tilo 0.561 ftop/cp/wn___1__h76646<3> + ftop/cp/Msub_wn___1__h76646_xor<3>11 + SLICE_X75Y111.F3 net (fanout=2) 0.476 ftop/cp/wn___1__h76646<3> + SLICE_X75Y111.X Tilo 0.562 ftop/cp/_theResult_____1__h75875<3> + ftop/cp/_theResult_____1__h75875<3>1 + SLICE_X75Y137.G2 net (fanout=17) 1.840 ftop/cp/_theResult_____1__h75875<3> + SLICE_X75Y137.Y Tilo 0.561 ftop/cp/wci_reqPend_11<3> + ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F_cmp_eq00001 + SLICE_X70Y148.G2 net (fanout=11) 1.381 ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F_cmp_eq0000 + SLICE_X70Y148.Y Tilo 0.616 ftop/cp/wci_respF_11_D_IN<3>0 + ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T1 + SLICE_X77Y110.F4 net (fanout=9) 3.018 ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T + SLICE_X77Y110.COUT Topcyf 1.026 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<11> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_lut<10> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<10> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<11> + SLICE_X77Y111.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<11> + SLICE_X77Y111.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<13> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<12> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<13> + SLICE_X77Y112.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<13> + SLICE_X77Y112.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<15> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<14> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<15> + SLICE_X77Y113.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<15> + SLICE_X77Y113.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<17> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<16> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<17> + SLICE_X77Y114.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<17> + SLICE_X77Y114.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<19> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<18> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<19> + SLICE_X77Y115.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<19> + SLICE_X77Y115.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<21> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<20> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<21> + SLICE_X77Y116.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<21> + SLICE_X77Y116.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<23> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<22> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<23> + SLICE_X77Y117.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<23> + SLICE_X77Y117.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<25> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<24> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<25> + SLICE_X77Y118.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<25> + SLICE_X77Y118.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<27> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<26> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<27> + SLICE_X77Y119.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<27> + SLICE_X77Y119.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<29> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<28> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<29> + SLICE_X77Y120.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<29> + SLICE_X77Y120.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<31> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<30> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<31> + SLICE_X77Y121.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<31> + SLICE_X77Y121.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<33> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<32> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<33> + SLICE_X77Y122.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<33> + SLICE_X77Y122.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<35> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<34> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<35> + SLICE_X77Y123.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<35> + SLICE_X77Y123.XB Tcinxb 0.216 ftop/cp/WILL_FIRE_RL_completeWorkerRead + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<36> + SLICE_X86Y116.G2 net (fanout=10) 1.943 ftop/cp/WILL_FIRE_RL_completeWorkerRead + SLICE_X86Y116.Y Tilo 0.616 ftop/cp/cpRespF/d1di + ftop/cp/cpRespF_ENQ1 + SLICE_X87Y116.G4 net (fanout=7) 0.564 ftop/cp/cpRespF_ENQ + SLICE_X87Y116.Y Tilo 0.561 ftop/cp/cpRespF/N01 + ftop/cp/cpRespF/d0h1 + SLICE_X89Y108.G4 net (fanout=40) 1.187 ftop/cp/cpRespF/d0h + SLICE_X89Y108.Y Tilo 0.561 ftop/cp_server_response_get<26> + ftop/cp/cpRespF/data0_reg_or0000<26>_SW0 + SLICE_X89Y108.F3 net (fanout=1) 0.021 ftop/cp/cpRespF/data0_reg_or0000<26>_SW0/O + SLICE_X89Y108.CLK Tfck 0.602 ftop/cp_server_response_get<26> + ftop/cp/cpRespF/data0_reg_26_rstpot + ftop/cp/cpRespF/data0_reg_26 + ------------------------------------------------- --------------------------- + Total 19.096ns (8.038ns logic, 11.058ns route) + (42.1% logic, 57.9% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.873ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/cp/cpReq_27 (FF) + Destination: ftop/cp/cpRespF/data0_reg_23 (FF) + Requirement: 20.000ns + Data Path Delay: 19.082ns (Levels of Logic = 22) + Clock Path Skew: -0.045ns (0.337 - 0.382) + Source Clock: ftop/sys1Clk rising at 0.000ns + Destination Clock: ftop/sys1Clk rising at 20.000ns + Clock Uncertainty: 0.000ns + + Maximum Data Path: ftop/cp/cpReq_27 to ftop/cp/cpRespF/data0_reg_23 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X84Y107.YQ Tcko 0.596 ftop/cp/cpReq<28> + ftop/cp/cpReq_27 + SLICE_X79Y106.G4 net (fanout=3) 0.628 ftop/cp/cpReq<27> + SLICE_X79Y106.Y Tilo 0.561 ftop/cp/wn___1__h76646<3> + ftop/cp/Msub_wn___1__h76646_xor<3>11 + SLICE_X75Y111.F3 net (fanout=2) 0.476 ftop/cp/wn___1__h76646<3> + SLICE_X75Y111.X Tilo 0.562 ftop/cp/_theResult_____1__h75875<3> + ftop/cp/_theResult_____1__h75875<3>1 + SLICE_X75Y137.G2 net (fanout=17) 1.840 ftop/cp/_theResult_____1__h75875<3> + SLICE_X75Y137.Y Tilo 0.561 ftop/cp/wci_reqPend_11<3> + ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F_cmp_eq00001 + SLICE_X70Y148.G2 net (fanout=11) 1.381 ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F_cmp_eq0000 + SLICE_X70Y148.Y Tilo 0.616 ftop/cp/wci_respF_11_D_IN<3>0 + ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T1 + SLICE_X77Y110.F4 net (fanout=9) 3.018 ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T + SLICE_X77Y110.COUT Topcyf 1.026 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<11> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_lut<10> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<10> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<11> + SLICE_X77Y111.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<11> + SLICE_X77Y111.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<13> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<12> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<13> + SLICE_X77Y112.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<13> + SLICE_X77Y112.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<15> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<14> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<15> + SLICE_X77Y113.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<15> + SLICE_X77Y113.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<17> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<16> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<17> + SLICE_X77Y114.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<17> + SLICE_X77Y114.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<19> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<18> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<19> + SLICE_X77Y115.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<19> + SLICE_X77Y115.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<21> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<20> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<21> + SLICE_X77Y116.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<21> + SLICE_X77Y116.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<23> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<22> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<23> + SLICE_X77Y117.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<23> + SLICE_X77Y117.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<25> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<24> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<25> + SLICE_X77Y118.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<25> + SLICE_X77Y118.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<27> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<26> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<27> + SLICE_X77Y119.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<27> + SLICE_X77Y119.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<29> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<28> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<29> + SLICE_X77Y120.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<29> + SLICE_X77Y120.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<31> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<30> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<31> + SLICE_X77Y121.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<31> + SLICE_X77Y121.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<33> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<32> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<33> + SLICE_X77Y122.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<33> + SLICE_X77Y122.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<35> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<34> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<35> + SLICE_X77Y123.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<35> + SLICE_X77Y123.XB Tcinxb 0.216 ftop/cp/WILL_FIRE_RL_completeWorkerRead + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<36> + SLICE_X86Y116.G2 net (fanout=10) 1.943 ftop/cp/WILL_FIRE_RL_completeWorkerRead + SLICE_X86Y116.Y Tilo 0.616 ftop/cp/cpRespF/d1di + ftop/cp/cpRespF_ENQ1 + SLICE_X87Y116.G4 net (fanout=7) 0.564 ftop/cp/cpRespF_ENQ + SLICE_X87Y116.Y Tilo 0.561 ftop/cp/cpRespF/N01 + ftop/cp/cpRespF/d0h1 + SLICE_X90Y110.G1 net (fanout=40) 1.050 ftop/cp/cpRespF/d0h + SLICE_X90Y110.Y Tilo 0.616 ftop/cp_server_response_get<23> + ftop/cp/cpRespF/data0_reg_or0000<23>_SW0 + SLICE_X90Y110.F4 net (fanout=1) 0.035 ftop/cp/cpRespF/data0_reg_or0000<23>_SW0/O + SLICE_X90Y110.CLK Tfck 0.656 ftop/cp_server_response_get<23> + ftop/cp/cpRespF/data0_reg_23_rstpot + ftop/cp/cpRespF/data0_reg_23 + ------------------------------------------------- --------------------------- + Total 19.082ns (8.147ns logic, 10.935ns route) + (42.7% logic, 57.3% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.884ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/cp/cpReq_27 (FF) + Destination: ftop/cp/cpRespF/data0_reg_21 (FF) + Requirement: 20.000ns + Data Path Delay: 19.061ns (Levels of Logic = 22) + Clock Path Skew: -0.055ns (0.327 - 0.382) + Source Clock: ftop/sys1Clk rising at 0.000ns + Destination Clock: ftop/sys1Clk rising at 20.000ns + Clock Uncertainty: 0.000ns + + Maximum Data Path: ftop/cp/cpReq_27 to ftop/cp/cpRespF/data0_reg_21 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X84Y107.YQ Tcko 0.596 ftop/cp/cpReq<28> + ftop/cp/cpReq_27 + SLICE_X79Y106.G4 net (fanout=3) 0.628 ftop/cp/cpReq<27> + SLICE_X79Y106.Y Tilo 0.561 ftop/cp/wn___1__h76646<3> + ftop/cp/Msub_wn___1__h76646_xor<3>11 + SLICE_X75Y111.F3 net (fanout=2) 0.476 ftop/cp/wn___1__h76646<3> + SLICE_X75Y111.X Tilo 0.562 ftop/cp/_theResult_____1__h75875<3> + ftop/cp/_theResult_____1__h75875<3>1 + SLICE_X75Y137.G2 net (fanout=17) 1.840 ftop/cp/_theResult_____1__h75875<3> + SLICE_X75Y137.Y Tilo 0.561 ftop/cp/wci_reqPend_11<3> + ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F_cmp_eq00001 + SLICE_X70Y148.G2 net (fanout=11) 1.381 ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F_cmp_eq0000 + SLICE_X70Y148.Y Tilo 0.616 ftop/cp/wci_respF_11_D_IN<3>0 + ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T1 + SLICE_X77Y110.F4 net (fanout=9) 3.018 ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T + SLICE_X77Y110.COUT Topcyf 1.026 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<11> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_lut<10> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<10> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<11> + SLICE_X77Y111.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<11> + SLICE_X77Y111.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<13> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<12> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<13> + SLICE_X77Y112.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<13> + SLICE_X77Y112.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<15> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<14> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<15> + SLICE_X77Y113.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<15> + SLICE_X77Y113.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<17> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<16> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<17> + SLICE_X77Y114.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<17> + SLICE_X77Y114.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<19> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<18> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<19> + SLICE_X77Y115.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<19> + SLICE_X77Y115.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<21> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<20> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<21> + SLICE_X77Y116.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<21> + SLICE_X77Y116.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<23> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<22> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<23> + SLICE_X77Y117.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<23> + SLICE_X77Y117.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<25> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<24> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<25> + SLICE_X77Y118.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<25> + SLICE_X77Y118.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<27> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<26> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<27> + SLICE_X77Y119.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<27> + SLICE_X77Y119.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<29> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<28> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<29> + SLICE_X77Y120.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<29> + SLICE_X77Y120.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<31> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<30> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<31> + SLICE_X77Y121.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<31> + SLICE_X77Y121.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<33> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<32> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<33> + SLICE_X77Y122.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<33> + SLICE_X77Y122.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<35> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<34> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<35> + SLICE_X77Y123.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<35> + SLICE_X77Y123.XB Tcinxb 0.216 ftop/cp/WILL_FIRE_RL_completeWorkerRead + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<36> + SLICE_X86Y116.G2 net (fanout=10) 1.943 ftop/cp/WILL_FIRE_RL_completeWorkerRead + SLICE_X86Y116.Y Tilo 0.616 ftop/cp/cpRespF/d1di + ftop/cp/cpRespF_ENQ1 + SLICE_X87Y116.G4 net (fanout=7) 0.564 ftop/cp/cpRespF_ENQ + SLICE_X87Y116.Y Tilo 0.561 ftop/cp/cpRespF/N01 + ftop/cp/cpRespF/d0h1 + SLICE_X86Y110.G1 net (fanout=40) 1.029 ftop/cp/cpRespF/d0h + SLICE_X86Y110.Y Tilo 0.616 ftop/cp_server_response_get<21> + ftop/cp/cpRespF/data0_reg_or0000<21>_SW0 + SLICE_X86Y110.F4 net (fanout=1) 0.035 ftop/cp/cpRespF/data0_reg_or0000<21>_SW0/O + SLICE_X86Y110.CLK Tfck 0.656 ftop/cp_server_response_get<21> + ftop/cp/cpRespF/data0_reg_21_rstpot + ftop/cp/cpRespF/data0_reg_21 + ------------------------------------------------- --------------------------- + Total 19.061ns (8.147ns logic, 10.914ns route) + (42.7% logic, 57.3% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.891ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/cp/cpReq_27 (FF) + Destination: ftop/cp/cpRespF/data0_reg_1 (FF) + Requirement: 20.000ns + Data Path Delay: 19.027ns (Levels of Logic = 22) + Clock Path Skew: -0.082ns (0.300 - 0.382) + Source Clock: ftop/sys1Clk rising at 0.000ns + Destination Clock: ftop/sys1Clk rising at 20.000ns + Clock Uncertainty: 0.000ns + + Maximum Data Path: ftop/cp/cpReq_27 to ftop/cp/cpRespF/data0_reg_1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X84Y107.YQ Tcko 0.596 ftop/cp/cpReq<28> + ftop/cp/cpReq_27 + SLICE_X79Y106.G4 net (fanout=3) 0.628 ftop/cp/cpReq<27> + SLICE_X79Y106.Y Tilo 0.561 ftop/cp/wn___1__h76646<3> + ftop/cp/Msub_wn___1__h76646_xor<3>11 + SLICE_X75Y111.F3 net (fanout=2) 0.476 ftop/cp/wn___1__h76646<3> + SLICE_X75Y111.X Tilo 0.562 ftop/cp/_theResult_____1__h75875<3> + ftop/cp/_theResult_____1__h75875<3>1 + SLICE_X75Y137.G2 net (fanout=17) 1.840 ftop/cp/_theResult_____1__h75875<3> + SLICE_X75Y137.Y Tilo 0.561 ftop/cp/wci_reqPend_11<3> + ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F_cmp_eq00001 + SLICE_X70Y148.G2 net (fanout=11) 1.381 ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F_cmp_eq0000 + SLICE_X70Y148.Y Tilo 0.616 ftop/cp/wci_respF_11_D_IN<3>0 + ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T1 + SLICE_X77Y110.F4 net (fanout=9) 3.018 ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T + SLICE_X77Y110.COUT Topcyf 1.026 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<11> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_lut<10> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<10> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<11> + SLICE_X77Y111.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<11> + SLICE_X77Y111.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<13> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<12> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<13> + SLICE_X77Y112.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<13> + SLICE_X77Y112.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<15> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<14> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<15> + SLICE_X77Y113.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<15> + SLICE_X77Y113.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<17> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<16> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<17> + SLICE_X77Y114.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<17> + SLICE_X77Y114.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<19> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<18> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<19> + SLICE_X77Y115.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<19> + SLICE_X77Y115.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<21> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<20> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<21> + SLICE_X77Y116.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<21> + SLICE_X77Y116.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<23> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<22> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<23> + SLICE_X77Y117.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<23> + SLICE_X77Y117.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<25> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<24> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<25> + SLICE_X77Y118.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<25> + SLICE_X77Y118.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<27> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<26> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<27> + SLICE_X77Y119.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<27> + SLICE_X77Y119.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<29> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<28> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<29> + SLICE_X77Y120.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<29> + SLICE_X77Y120.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<31> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<30> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<31> + SLICE_X77Y121.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<31> + SLICE_X77Y121.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<33> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<32> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<33> + SLICE_X77Y122.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<33> + SLICE_X77Y122.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<35> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<34> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<35> + SLICE_X77Y123.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<35> + SLICE_X77Y123.XB Tcinxb 0.216 ftop/cp/WILL_FIRE_RL_completeWorkerRead + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<36> + SLICE_X86Y116.G2 net (fanout=10) 1.943 ftop/cp/WILL_FIRE_RL_completeWorkerRead + SLICE_X86Y116.Y Tilo 0.616 ftop/cp/cpRespF/d1di + ftop/cp/cpRespF_ENQ1 + SLICE_X87Y116.G4 net (fanout=7) 0.564 ftop/cp/cpRespF_ENQ + SLICE_X87Y116.Y Tilo 0.561 ftop/cp/cpRespF/N01 + ftop/cp/cpRespF/d0h1 + SLICE_X90Y115.G2 net (fanout=40) 1.009 ftop/cp/cpRespF/d0h + SLICE_X90Y115.Y Tilo 0.616 ftop/cp_server_response_get<1> + ftop/cp/cpRespF/data0_reg_or0000<1>_SW0 + SLICE_X90Y115.F3 net (fanout=1) 0.021 ftop/cp/cpRespF/data0_reg_or0000<1>_SW0/O + SLICE_X90Y115.CLK Tfck 0.656 ftop/cp_server_response_get<1> + ftop/cp/cpRespF/data0_reg_1_rstpot + ftop/cp/cpRespF/data0_reg_1 + ------------------------------------------------- --------------------------- + Total 19.027ns (8.147ns logic, 10.880ns route) + (42.8% logic, 57.2% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.898ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/cp/cpReq_23 (FF) + Destination: ftop/cp/cpRespF/data0_reg_0 (FF) + Requirement: 20.000ns + Data Path Delay: 19.065ns (Levels of Logic = 22) + Clock Path Skew: -0.037ns (0.532 - 0.569) + Source Clock: ftop/sys1Clk rising at 0.000ns + Destination Clock: ftop/sys1Clk rising at 20.000ns + Clock Uncertainty: 0.000ns + + Maximum Data Path: ftop/cp/cpReq_23 to ftop/cp/cpRespF/data0_reg_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X76Y106.YQ Tcko 0.596 ftop/cp/cpReq<24> + ftop/cp/cpReq_23 + SLICE_X75Y111.G1 net (fanout=19) 0.933 ftop/cp/cpReq<23> + SLICE_X75Y111.Y Tilo 0.561 ftop/cp/_theResult_____1__h75875<3> + ftop/cp/Msub_wn__h75856_xor<3>11 + SLICE_X75Y111.F4 net (fanout=2) 0.044 ftop/cp/wn__h75856<3> + SLICE_X75Y111.X Tilo 0.562 ftop/cp/_theResult_____1__h75875<3> + ftop/cp/_theResult_____1__h75875<3>1 + SLICE_X75Y137.G2 net (fanout=17) 1.840 ftop/cp/_theResult_____1__h75875<3> + SLICE_X75Y137.Y Tilo 0.561 ftop/cp/wci_reqPend_11<3> + ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F_cmp_eq00001 + SLICE_X70Y148.G2 net (fanout=11) 1.381 ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F_cmp_eq0000 + SLICE_X70Y148.Y Tilo 0.616 ftop/cp/wci_respF_11_D_IN<3>0 + ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T1 + SLICE_X77Y110.F4 net (fanout=9) 3.018 ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T + SLICE_X77Y110.COUT Topcyf 1.026 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<11> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_lut<10> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<10> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<11> + SLICE_X77Y111.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<11> + SLICE_X77Y111.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<13> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<12> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<13> + SLICE_X77Y112.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<13> + SLICE_X77Y112.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<15> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<14> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<15> + SLICE_X77Y113.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<15> + SLICE_X77Y113.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<17> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<16> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<17> + SLICE_X77Y114.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<17> + SLICE_X77Y114.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<19> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<18> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<19> + SLICE_X77Y115.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<19> + SLICE_X77Y115.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<21> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<20> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<21> + SLICE_X77Y116.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<21> + SLICE_X77Y116.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<23> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<22> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<23> + SLICE_X77Y117.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<23> + SLICE_X77Y117.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<25> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<24> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<25> + SLICE_X77Y118.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<25> + SLICE_X77Y118.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<27> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<26> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<27> + SLICE_X77Y119.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<27> + SLICE_X77Y119.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<29> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<28> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<29> + SLICE_X77Y120.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<29> + SLICE_X77Y120.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<31> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<30> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<31> + SLICE_X77Y121.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<31> + SLICE_X77Y121.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<33> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<32> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<33> + SLICE_X77Y122.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<33> + SLICE_X77Y122.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<35> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<34> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<35> + SLICE_X77Y123.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<35> + SLICE_X77Y123.XB Tcinxb 0.216 ftop/cp/WILL_FIRE_RL_completeWorkerRead + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<36> + SLICE_X86Y116.G2 net (fanout=10) 1.943 ftop/cp/WILL_FIRE_RL_completeWorkerRead + SLICE_X86Y116.Y Tilo 0.616 ftop/cp/cpRespF/d1di + ftop/cp/cpRespF_ENQ1 + SLICE_X87Y116.G4 net (fanout=7) 0.564 ftop/cp/cpRespF_ENQ + SLICE_X87Y116.Y Tilo 0.561 ftop/cp/cpRespF/N01 + ftop/cp/cpRespF/d0h1 + SLICE_X90Y113.G2 net (fanout=40) 1.174 ftop/cp/cpRespF/d0h + SLICE_X90Y113.Y Tilo 0.616 ftop/cp_server_response_get<0> + ftop/cp/cpRespF/data0_reg_or0000<0>_SW0 + SLICE_X90Y113.F3 net (fanout=1) 0.021 ftop/cp/cpRespF/data0_reg_or0000<0>_SW0/O + SLICE_X90Y113.CLK Tfck 0.656 ftop/cp_server_response_get<0> + ftop/cp/cpRespF/data0_reg_0_rstpot + ftop/cp/cpRespF/data0_reg_0 + ------------------------------------------------- --------------------------- + Total 19.065ns (8.147ns logic, 10.918ns route) + (42.7% logic, 57.3% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.899ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/cp/cpReq_27 (FF) + Destination: ftop/cp/cpRespF/data0_reg_3 (FF) + Requirement: 20.000ns + Data Path Delay: 18.983ns (Levels of Logic = 22) + Clock Path Skew: -0.118ns (0.264 - 0.382) + Source Clock: ftop/sys1Clk rising at 0.000ns + Destination Clock: ftop/sys1Clk rising at 20.000ns + Clock Uncertainty: 0.000ns + + Maximum Data Path: ftop/cp/cpReq_27 to ftop/cp/cpRespF/data0_reg_3 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X84Y107.YQ Tcko 0.596 ftop/cp/cpReq<28> + ftop/cp/cpReq_27 + SLICE_X79Y106.G4 net (fanout=3) 0.628 ftop/cp/cpReq<27> + SLICE_X79Y106.Y Tilo 0.561 ftop/cp/wn___1__h76646<3> + ftop/cp/Msub_wn___1__h76646_xor<3>11 + SLICE_X75Y111.F3 net (fanout=2) 0.476 ftop/cp/wn___1__h76646<3> + SLICE_X75Y111.X Tilo 0.562 ftop/cp/_theResult_____1__h75875<3> + ftop/cp/_theResult_____1__h75875<3>1 + SLICE_X75Y137.G2 net (fanout=17) 1.840 ftop/cp/_theResult_____1__h75875<3> + SLICE_X75Y137.Y Tilo 0.561 ftop/cp/wci_reqPend_11<3> + ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F_cmp_eq00001 + SLICE_X70Y148.G2 net (fanout=11) 1.381 ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F_cmp_eq0000 + SLICE_X70Y148.Y Tilo 0.616 ftop/cp/wci_respF_11_D_IN<3>0 + ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T1 + SLICE_X77Y110.F4 net (fanout=9) 3.018 ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T + SLICE_X77Y110.COUT Topcyf 1.026 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<11> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_lut<10> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<10> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<11> + SLICE_X77Y111.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<11> + SLICE_X77Y111.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<13> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<12> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<13> + SLICE_X77Y112.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<13> + SLICE_X77Y112.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<15> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<14> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<15> + SLICE_X77Y113.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<15> + SLICE_X77Y113.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<17> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<16> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<17> + SLICE_X77Y114.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<17> + SLICE_X77Y114.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<19> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<18> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<19> + SLICE_X77Y115.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<19> + SLICE_X77Y115.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<21> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<20> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<21> + SLICE_X77Y116.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<21> + SLICE_X77Y116.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<23> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<22> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<23> + SLICE_X77Y117.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<23> + SLICE_X77Y117.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<25> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<24> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<25> + SLICE_X77Y118.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<25> + SLICE_X77Y118.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<27> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<26> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<27> + SLICE_X77Y119.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<27> + SLICE_X77Y119.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<29> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<28> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<29> + SLICE_X77Y120.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<29> + SLICE_X77Y120.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<31> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<30> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<31> + SLICE_X77Y121.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<31> + SLICE_X77Y121.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<33> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<32> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<33> + SLICE_X77Y122.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<33> + SLICE_X77Y122.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<35> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<34> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<35> + SLICE_X77Y123.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<35> + SLICE_X77Y123.XB Tcinxb 0.216 ftop/cp/WILL_FIRE_RL_completeWorkerRead + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<36> + SLICE_X86Y116.G2 net (fanout=10) 1.943 ftop/cp/WILL_FIRE_RL_completeWorkerRead + SLICE_X86Y116.Y Tilo 0.616 ftop/cp/cpRespF/d1di + ftop/cp/cpRespF_ENQ1 + SLICE_X87Y116.G4 net (fanout=7) 0.564 ftop/cp/cpRespF_ENQ + SLICE_X87Y116.Y Tilo 0.561 ftop/cp/cpRespF/N01 + ftop/cp/cpRespF/d0h1 + SLICE_X88Y117.G3 net (fanout=40) 0.671 ftop/cp/cpRespF/d0h + SLICE_X88Y117.Y Tilo 0.616 ftop/cp_server_response_get<3> + ftop/cp/cpRespF/data0_reg_or0000<3>_SW0 + SLICE_X88Y117.F2 net (fanout=1) 0.315 ftop/cp/cpRespF/data0_reg_or0000<3>_SW0/O + SLICE_X88Y117.CLK Tfck 0.656 ftop/cp_server_response_get<3> + ftop/cp/cpRespF/data0_reg_3_rstpot + ftop/cp/cpRespF/data0_reg_3 + ------------------------------------------------- --------------------------- + Total 18.983ns (8.147ns logic, 10.836ns route) + (42.9% logic, 57.1% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.899ns (requirement - (data path - clock path skew + uncertainty)) + Source: ftop/cp/cpReq_27 (FF) + Destination: ftop/cp/cpRespF/data0_reg_20 (FF) + Requirement: 20.000ns + Data Path Delay: 19.040ns (Levels of Logic = 22) + Clock Path Skew: -0.061ns (0.321 - 0.382) + Source Clock: ftop/sys1Clk rising at 0.000ns + Destination Clock: ftop/sys1Clk rising at 20.000ns + Clock Uncertainty: 0.000ns + + Maximum Data Path: ftop/cp/cpReq_27 to ftop/cp/cpRespF/data0_reg_20 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X84Y107.YQ Tcko 0.596 ftop/cp/cpReq<28> + ftop/cp/cpReq_27 + SLICE_X79Y106.G4 net (fanout=3) 0.628 ftop/cp/cpReq<27> + SLICE_X79Y106.Y Tilo 0.561 ftop/cp/wn___1__h76646<3> + ftop/cp/Msub_wn___1__h76646_xor<3>11 + SLICE_X75Y111.F3 net (fanout=2) 0.476 ftop/cp/wn___1__h76646<3> + SLICE_X75Y111.X Tilo 0.562 ftop/cp/_theResult_____1__h75875<3> + ftop/cp/_theResult_____1__h75875<3>1 + SLICE_X75Y137.G2 net (fanout=17) 1.840 ftop/cp/_theResult_____1__h75875<3> + SLICE_X75Y137.Y Tilo 0.561 ftop/cp/wci_reqPend_11<3> + ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F_cmp_eq00001 + SLICE_X70Y148.G2 net (fanout=11) 1.381 ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F_cmp_eq0000 + SLICE_X70Y148.Y Tilo 0.616 ftop/cp/wci_respF_11_D_IN<3>0 + ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T1 + SLICE_X77Y110.F4 net (fanout=9) 3.018 ftop/cp/WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T + SLICE_X77Y110.COUT Topcyf 1.026 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<11> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_lut<10> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<10> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<11> + SLICE_X77Y111.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<11> + SLICE_X77Y111.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<13> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<12> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<13> + SLICE_X77Y112.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<13> + SLICE_X77Y112.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<15> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<14> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<15> + SLICE_X77Y113.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<15> + SLICE_X77Y113.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<17> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<16> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<17> + SLICE_X77Y114.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<17> + SLICE_X77Y114.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<19> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<18> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<19> + SLICE_X77Y115.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<19> + SLICE_X77Y115.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<21> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<20> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<21> + SLICE_X77Y116.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<21> + SLICE_X77Y116.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<23> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<22> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<23> + SLICE_X77Y117.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<23> + SLICE_X77Y117.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<25> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<24> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<25> + SLICE_X77Y118.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<25> + SLICE_X77Y118.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<27> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<26> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<27> + SLICE_X77Y119.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<27> + SLICE_X77Y119.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<29> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<28> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<29> + SLICE_X77Y120.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<29> + SLICE_X77Y120.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<31> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<30> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<31> + SLICE_X77Y121.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<31> + SLICE_X77Y121.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<33> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<32> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<33> + SLICE_X77Y122.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<33> + SLICE_X77Y122.COUT Tbyp 0.130 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<35> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<34> + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<35> + SLICE_X77Y123.CIN net (fanout=1) 0.000 ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<35> + SLICE_X77Y123.XB Tcinxb 0.216 ftop/cp/WILL_FIRE_RL_completeWorkerRead + ftop/cp/WILL_FIRE_RL_completeWorkerRead_wg_cy<36> + SLICE_X86Y116.G2 net (fanout=10) 1.943 ftop/cp/WILL_FIRE_RL_completeWorkerRead + SLICE_X86Y116.Y Tilo 0.616 ftop/cp/cpRespF/d1di + ftop/cp/cpRespF_ENQ1 + SLICE_X87Y116.G4 net (fanout=7) 0.564 ftop/cp/cpRespF_ENQ + SLICE_X87Y116.Y Tilo 0.561 ftop/cp/cpRespF/N01 + ftop/cp/cpRespF/d0h1 + SLICE_X91Y112.G3 net (fanout=40) 1.131 ftop/cp/cpRespF/d0h + SLICE_X91Y112.Y Tilo 0.561 ftop/cp_server_response_get<20> + ftop/cp/cpRespF/data0_reg_or0000<20>_SW0 + SLICE_X91Y112.F3 net (fanout=1) 0.021 ftop/cp/cpRespF/data0_reg_or0000<20>_SW0/O + SLICE_X91Y112.CLK Tfck 0.602 ftop/cp_server_response_get<20> + ftop/cp/cpRespF/data0_reg_20_rstpot + ftop/cp/cpRespF/data0_reg_20 + ------------------------------------------------- --------------------------- + Total 19.040ns (8.038ns logic, 11.002ns route) + (42.2% logic, 57.8% route) + +-------------------------------------------------------------------------------- + +Hold Paths: TS_ftop_clkN210_clkdv_unbuf = PERIOD TIMEGRP "ftop_clkN210_clkdv_unbuf" + TS_SYS0CLK * 2 HIGH 50%; +-------------------------------------------------------------------------------- +Slack (hold path): 0.503ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/cp/wci_reqF_10_q_0_21 (FF) + Destination: ftop/iqadc/wci_wslv_reqF/Mram_arr22.SLICEM_G (RAM) + Requirement: 0.000ns + Data Path Delay: 0.654ns (Levels of Logic = 1) + Clock Path Skew: 0.151ns (0.825 - 0.674) + Source Clock: ftop/sys1Clk rising at 20.000ns + Destination Clock: ftop/sys1Clk rising at 20.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path: ftop/cp/wci_reqF_10_q_0_21 to ftop/iqadc/wci_wslv_reqF/Mram_arr22.SLICEM_G + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X26Y102.XQ Tcko 0.417 ftop/cp_wci_Vm_10_MData<21> + ftop/cp/wci_reqF_10_q_0_21 + SLICE_X24Y104.BY net (fanout=2) 0.367 ftop/cp_wci_Vm_10_MData<21> + SLICE_X24Y104.CLK Tdh (-Th) 0.130 ftop/iqadc/wci_wslv_reqF/_varindex0000<21> + ftop/iqadc/wci_wslv_reqF/Mram_arr22.SLICEM_G + ------------------------------------------------- --------------------------- + Total 0.654ns (0.287ns logic, 0.367ns route) + (43.9% logic, 56.1% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.504ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/cp/wci_reqF_10_q_0_21 (FF) + Destination: ftop/iqadc/wci_wslv_reqF/Mram_arr22.SLICEM_F (RAM) + Requirement: 0.000ns + Data Path Delay: 0.655ns (Levels of Logic = 1) + Clock Path Skew: 0.151ns (0.825 - 0.674) + Source Clock: ftop/sys1Clk rising at 20.000ns + Destination Clock: ftop/sys1Clk rising at 20.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path: ftop/cp/wci_reqF_10_q_0_21 to ftop/iqadc/wci_wslv_reqF/Mram_arr22.SLICEM_F + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X26Y102.XQ Tcko 0.417 ftop/cp_wci_Vm_10_MData<21> + ftop/cp/wci_reqF_10_q_0_21 + SLICE_X24Y104.BY net (fanout=2) 0.367 ftop/cp_wci_Vm_10_MData<21> + SLICE_X24Y104.CLK Tdh (-Th) 0.129 ftop/iqadc/wci_wslv_reqF/_varindex0000<21> + ftop/iqadc/wci_wslv_reqF/Mram_arr22.SLICEM_F + ------------------------------------------------- --------------------------- + Total 0.655ns (0.288ns logic, 0.367ns route) + (44.0% logic, 56.0% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.535ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/cp/wci_reqF_4_q_0_23 (FF) + Destination: ftop/sma1/wci_wslv_reqF/Mram_arr24.SLICEM_G (RAM) + Requirement: 0.000ns + Data Path Delay: 0.561ns (Levels of Logic = 1) + Clock Path Skew: 0.026ns (0.111 - 0.085) + Source Clock: ftop/sys1Clk rising at 20.000ns + Destination Clock: ftop/sys1Clk rising at 20.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path: ftop/cp/wci_reqF_4_q_0_23 to ftop/sma1/wci_wslv_reqF/Mram_arr24.SLICEM_G + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X93Y174.XQ Tcko 0.396 ftop/cp_wci_Vm_4_MData<23> + ftop/cp/wci_reqF_4_q_0_23 + SLICE_X92Y172.BY net (fanout=2) 0.295 ftop/cp_wci_Vm_4_MData<23> + SLICE_X92Y172.CLK Tdh (-Th) 0.130 ftop/sma1/wci_wslv_reqF/_varindex0000<23> + ftop/sma1/wci_wslv_reqF/Mram_arr24.SLICEM_G + ------------------------------------------------- --------------------------- + Total 0.561ns (0.266ns logic, 0.295ns route) + (47.4% logic, 52.6% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.536ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/cp/wci_reqF_4_q_0_23 (FF) + Destination: ftop/sma1/wci_wslv_reqF/Mram_arr24.SLICEM_F (RAM) + Requirement: 0.000ns + Data Path Delay: 0.562ns (Levels of Logic = 1) + Clock Path Skew: 0.026ns (0.111 - 0.085) + Source Clock: ftop/sys1Clk rising at 20.000ns + Destination Clock: ftop/sys1Clk rising at 20.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path: ftop/cp/wci_reqF_4_q_0_23 to ftop/sma1/wci_wslv_reqF/Mram_arr24.SLICEM_F + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X93Y174.XQ Tcko 0.396 ftop/cp_wci_Vm_4_MData<23> + ftop/cp/wci_reqF_4_q_0_23 + SLICE_X92Y172.BY net (fanout=2) 0.295 ftop/cp_wci_Vm_4_MData<23> + SLICE_X92Y172.CLK Tdh (-Th) 0.129 ftop/sma1/wci_wslv_reqF/_varindex0000<23> + ftop/sma1/wci_wslv_reqF/Mram_arr24.SLICEM_F + ------------------------------------------------- --------------------------- + Total 0.562ns (0.267ns logic, 0.295ns route) + (47.5% logic, 52.5% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.537ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/cp/wci_reqF_9_q_0_27 (FF) + Destination: ftop/gbewrk/wci_wslv_reqF/Mram_arr28.SLICEM_G (RAM) + Requirement: 0.000ns + Data Path Delay: 0.607ns (Levels of Logic = 1) + Clock Path Skew: 0.070ns (0.462 - 0.392) + Source Clock: ftop/sys1Clk rising at 20.000ns + Destination Clock: ftop/sys1Clk rising at 20.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path: ftop/cp/wci_reqF_9_q_0_27 to ftop/gbewrk/wci_wslv_reqF/Mram_arr28.SLICEM_G + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X59Y89.XQ Tcko 0.396 ftop/cp_wci_Vm_9_MData<27> + ftop/cp/wci_reqF_9_q_0_27 + SLICE_X56Y89.BY net (fanout=2) 0.341 ftop/cp_wci_Vm_9_MData<27> + SLICE_X56Y89.CLK Tdh (-Th) 0.130 ftop/gbewrk/wci_wslv_reqF/_varindex0000<27> + ftop/gbewrk/wci_wslv_reqF/Mram_arr28.SLICEM_G + ------------------------------------------------- --------------------------- + Total 0.607ns (0.266ns logic, 0.341ns route) + (43.8% logic, 56.2% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.538ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/cp/wci_reqF_9_q_0_27 (FF) + Destination: ftop/gbewrk/wci_wslv_reqF/Mram_arr28.SLICEM_F (RAM) + Requirement: 0.000ns + Data Path Delay: 0.608ns (Levels of Logic = 1) + Clock Path Skew: 0.070ns (0.462 - 0.392) + Source Clock: ftop/sys1Clk rising at 20.000ns + Destination Clock: ftop/sys1Clk rising at 20.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path: ftop/cp/wci_reqF_9_q_0_27 to ftop/gbewrk/wci_wslv_reqF/Mram_arr28.SLICEM_F + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X59Y89.XQ Tcko 0.396 ftop/cp_wci_Vm_9_MData<27> + ftop/cp/wci_reqF_9_q_0_27 + SLICE_X56Y89.BY net (fanout=2) 0.341 ftop/cp_wci_Vm_9_MData<27> + SLICE_X56Y89.CLK Tdh (-Th) 0.129 ftop/gbewrk/wci_wslv_reqF/_varindex0000<27> + ftop/gbewrk/wci_wslv_reqF/Mram_arr28.SLICEM_F + ------------------------------------------------- --------------------------- + Total 0.608ns (0.267ns logic, 0.341ns route) + (43.9% logic, 56.1% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.546ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/cp/td_16 (FF) + Destination: ftop/cp/timeServ_setRefF/Mram_fifoMem49.SLICEM_G (RAM) + Requirement: 0.000ns + Data Path Delay: 0.575ns (Levels of Logic = 1) + Clock Path Skew: 0.029ns (0.096 - 0.067) + Source Clock: ftop/sys1Clk rising at 20.000ns + Destination Clock: ftop/sys1Clk rising at 20.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path: ftop/cp/td_16 to ftop/cp/timeServ_setRefF/Mram_fifoMem49.SLICEM_G + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X111Y145.YQ Tcko 0.419 ftop/cp/td<17> + ftop/cp/td_16 + SLICE_X110Y143.BY net (fanout=2) 0.286 ftop/cp/td<16> + SLICE_X110Y143.CLK Tdh (-Th) 0.130 ftop/cp/timeServ_setRefF_dD_OUT<48> + ftop/cp/timeServ_setRefF/Mram_fifoMem49.SLICEM_G + ------------------------------------------------- --------------------------- + Total 0.575ns (0.289ns logic, 0.286ns route) + (50.3% logic, 49.7% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.546ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/cp/wci_reqF_14_q_0_5 (FF) + Destination: ftop/edp1/wci_reqF/Mram_arr6.SLICEM_G (RAM) + Requirement: 0.000ns + Data Path Delay: 0.607ns (Levels of Logic = 1) + Clock Path Skew: 0.061ns (0.484 - 0.423) + Source Clock: ftop/sys1Clk rising at 20.000ns + Destination Clock: ftop/sys1Clk rising at 20.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path: ftop/cp/wci_reqF_14_q_0_5 to ftop/edp1/wci_reqF/Mram_arr6.SLICEM_G + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X47Y122.XQ Tcko 0.396 ftop/cp_wci_Vm_14_MData<5> + ftop/cp/wci_reqF_14_q_0_5 + SLICE_X44Y123.BY net (fanout=2) 0.341 ftop/cp_wci_Vm_14_MData<5> + SLICE_X44Y123.CLK Tdh (-Th) 0.130 ftop/edp1/wci_reqF/_varindex0000<5> + ftop/edp1/wci_reqF/Mram_arr6.SLICEM_G + ------------------------------------------------- --------------------------- + Total 0.607ns (0.266ns logic, 0.341ns route) + (43.8% logic, 56.2% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.547ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/cp/td_16 (FF) + Destination: ftop/cp/timeServ_setRefF/Mram_fifoMem49.SLICEM_F (RAM) + Requirement: 0.000ns + Data Path Delay: 0.576ns (Levels of Logic = 1) + Clock Path Skew: 0.029ns (0.096 - 0.067) + Source Clock: ftop/sys1Clk rising at 20.000ns + Destination Clock: ftop/sys1Clk rising at 20.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path: ftop/cp/td_16 to ftop/cp/timeServ_setRefF/Mram_fifoMem49.SLICEM_F + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X111Y145.YQ Tcko 0.419 ftop/cp/td<17> + ftop/cp/td_16 + SLICE_X110Y143.BY net (fanout=2) 0.286 ftop/cp/td<16> + SLICE_X110Y143.CLK Tdh (-Th) 0.129 ftop/cp/timeServ_setRefF_dD_OUT<48> + ftop/cp/timeServ_setRefF/Mram_fifoMem49.SLICEM_F + ------------------------------------------------- --------------------------- + Total 0.576ns (0.290ns logic, 0.286ns route) + (50.3% logic, 49.7% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.547ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/cp/wci_reqF_14_q_0_5 (FF) + Destination: ftop/edp1/wci_reqF/Mram_arr6.SLICEM_F (RAM) + Requirement: 0.000ns + Data Path Delay: 0.608ns (Levels of Logic = 1) + Clock Path Skew: 0.061ns (0.484 - 0.423) + Source Clock: ftop/sys1Clk rising at 20.000ns + Destination Clock: ftop/sys1Clk rising at 20.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path: ftop/cp/wci_reqF_14_q_0_5 to ftop/edp1/wci_reqF/Mram_arr6.SLICEM_F + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X47Y122.XQ Tcko 0.396 ftop/cp_wci_Vm_14_MData<5> + ftop/cp/wci_reqF_14_q_0_5 + SLICE_X44Y123.BY net (fanout=2) 0.341 ftop/cp_wci_Vm_14_MData<5> + SLICE_X44Y123.CLK Tdh (-Th) 0.129 ftop/edp1/wci_reqF/_varindex0000<5> + ftop/edp1/wci_reqF/Mram_arr6.SLICEM_F + ------------------------------------------------- --------------------------- + Total 0.608ns (0.267ns logic, 0.341ns route) + (43.9% logic, 56.1% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.548ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/cp/wci_reqF_2_q_0_1 (FF) + Destination: ftop/sma0/wci_wslv_reqF/Mram_arr2.SLICEM_G (RAM) + Requirement: 0.000ns + Data Path Delay: 0.584ns (Levels of Logic = 1) + Clock Path Skew: 0.036ns (0.067 - 0.031) + Source Clock: ftop/sys1Clk rising at 20.000ns + Destination Clock: ftop/sys1Clk rising at 20.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path: ftop/cp/wci_reqF_2_q_0_1 to ftop/sma0/wci_wslv_reqF/Mram_arr2.SLICEM_G + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X85Y58.XQ Tcko 0.396 ftop/cp_wci_Vm_2_MData<1> + ftop/cp/wci_reqF_2_q_0_1 + SLICE_X84Y60.BY net (fanout=2) 0.318 ftop/cp_wci_Vm_2_MData<1> + SLICE_X84Y60.CLK Tdh (-Th) 0.130 ftop/sma0/wci_wslv_reqF/_varindex0000<1> + ftop/sma0/wci_wslv_reqF/Mram_arr2.SLICEM_G + ------------------------------------------------- --------------------------- + Total 0.584ns (0.266ns logic, 0.318ns route) + (45.5% logic, 54.5% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.549ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/cp/wci_reqF_9_q_0_2 (FF) + Destination: ftop/gbewrk/wci_wslv_reqF/Mram_arr3.SLICEM_G (RAM) + Requirement: 0.000ns + Data Path Delay: 0.710ns (Levels of Logic = 1) + Clock Path Skew: 0.161ns (0.936 - 0.775) + Source Clock: ftop/sys1Clk rising at 20.000ns + Destination Clock: ftop/sys1Clk rising at 20.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path: ftop/cp/wci_reqF_9_q_0_2 to ftop/gbewrk/wci_wslv_reqF/Mram_arr3.SLICEM_G + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X52Y91.YQ Tcko 0.477 ftop/cp_wci_Vm_9_MData<3> + ftop/cp/wci_reqF_9_q_0_2 + SLICE_X50Y90.BY net (fanout=2) 0.363 ftop/cp_wci_Vm_9_MData<2> + SLICE_X50Y90.CLK Tdh (-Th) 0.130 ftop/gbewrk/wci_wslv_reqF/_varindex0000<2> + ftop/gbewrk/wci_wslv_reqF/Mram_arr3.SLICEM_G + ------------------------------------------------- --------------------------- + Total 0.710ns (0.347ns logic, 0.363ns route) + (48.9% logic, 51.1% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.549ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/cp/wci_reqF_2_q_0_1 (FF) + Destination: ftop/sma0/wci_wslv_reqF/Mram_arr2.SLICEM_F (RAM) + Requirement: 0.000ns + Data Path Delay: 0.585ns (Levels of Logic = 1) + Clock Path Skew: 0.036ns (0.067 - 0.031) + Source Clock: ftop/sys1Clk rising at 20.000ns + Destination Clock: ftop/sys1Clk rising at 20.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path: ftop/cp/wci_reqF_2_q_0_1 to ftop/sma0/wci_wslv_reqF/Mram_arr2.SLICEM_F + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X85Y58.XQ Tcko 0.396 ftop/cp_wci_Vm_2_MData<1> + ftop/cp/wci_reqF_2_q_0_1 + SLICE_X84Y60.BY net (fanout=2) 0.318 ftop/cp_wci_Vm_2_MData<1> + SLICE_X84Y60.CLK Tdh (-Th) 0.129 ftop/sma0/wci_wslv_reqF/_varindex0000<1> + ftop/sma0/wci_wslv_reqF/Mram_arr2.SLICEM_F + ------------------------------------------------- --------------------------- + Total 0.585ns (0.267ns logic, 0.318ns route) + (45.6% logic, 54.4% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.550ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/cp/wci_reqF_9_q_0_2 (FF) + Destination: ftop/gbewrk/wci_wslv_reqF/Mram_arr3.SLICEM_F (RAM) + Requirement: 0.000ns + Data Path Delay: 0.711ns (Levels of Logic = 1) + Clock Path Skew: 0.161ns (0.936 - 0.775) + Source Clock: ftop/sys1Clk rising at 20.000ns + Destination Clock: ftop/sys1Clk rising at 20.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path: ftop/cp/wci_reqF_9_q_0_2 to ftop/gbewrk/wci_wslv_reqF/Mram_arr3.SLICEM_F + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X52Y91.YQ Tcko 0.477 ftop/cp_wci_Vm_9_MData<3> + ftop/cp/wci_reqF_9_q_0_2 + SLICE_X50Y90.BY net (fanout=2) 0.363 ftop/cp_wci_Vm_9_MData<2> + SLICE_X50Y90.CLK Tdh (-Th) 0.129 ftop/gbewrk/wci_wslv_reqF/_varindex0000<2> + ftop/gbewrk/wci_wslv_reqF/Mram_arr3.SLICEM_F + ------------------------------------------------- --------------------------- + Total 0.711ns (0.348ns logic, 0.363ns route) + (48.9% logic, 51.1% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.550ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/bias/wsiM_reqFifo_q_0_40 (FF) + Destination: ftop/sma1/wsiS_reqFifo/Mram_arr41.SLICEM_G (RAM) + Requirement: 0.000ns + Data Path Delay: 0.616ns (Levels of Logic = 1) + Clock Path Skew: 0.066ns (0.547 - 0.481) + Source Clock: ftop/sys1Clk rising at 20.000ns + Destination Clock: ftop/sys1Clk rising at 20.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path: ftop/bias/wsiM_reqFifo_q_0_40 to ftop/sma1/wsiS_reqFifo/Mram_arr41.SLICEM_G + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X70Y164.XQ Tcko 0.417 ftop/bias_wsiM0_MData<28> + ftop/bias/wsiM_reqFifo_q_0_40 + SLICE_X68Y167.BY net (fanout=2) 0.329 ftop/bias_wsiM0_MData<28> + SLICE_X68Y167.CLK Tdh (-Th) 0.130 ftop/sma1/wsiS_reqFifo/_varindex0000<40> + ftop/sma1/wsiS_reqFifo/Mram_arr41.SLICEM_G + ------------------------------------------------- --------------------------- + Total 0.616ns (0.287ns logic, 0.329ns route) + (46.6% logic, 53.4% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.551ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/cp/wci_reqF_9_q_0_15 (FF) + Destination: ftop/gbewrk/wci_wslv_reqF/Mram_arr16.SLICEM_G (RAM) + Requirement: 0.000ns + Data Path Delay: 0.613ns (Levels of Logic = 1) + Clock Path Skew: 0.062ns (0.465 - 0.403) + Source Clock: ftop/sys1Clk rising at 20.000ns + Destination Clock: ftop/sys1Clk rising at 20.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path: ftop/cp/wci_reqF_9_q_0_15 to ftop/gbewrk/wci_wslv_reqF/Mram_arr16.SLICEM_G + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X58Y84.XQ Tcko 0.417 ftop/cp_wci_Vm_9_MData<15> + ftop/cp/wci_reqF_9_q_0_15 + SLICE_X60Y85.BY net (fanout=2) 0.326 ftop/cp_wci_Vm_9_MData<15> + SLICE_X60Y85.CLK Tdh (-Th) 0.130 ftop/gbewrk/wci_wslv_reqF/_varindex0000<15> + ftop/gbewrk/wci_wslv_reqF/Mram_arr16.SLICEM_G + ------------------------------------------------- --------------------------- + Total 0.613ns (0.287ns logic, 0.326ns route) + (46.8% logic, 53.2% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.551ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/bias/wsiM_reqFifo_q_0_40 (FF) + Destination: ftop/sma1/wsiS_reqFifo/Mram_arr41.SLICEM_F (RAM) + Requirement: 0.000ns + Data Path Delay: 0.617ns (Levels of Logic = 1) + Clock Path Skew: 0.066ns (0.547 - 0.481) + Source Clock: ftop/sys1Clk rising at 20.000ns + Destination Clock: ftop/sys1Clk rising at 20.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path: ftop/bias/wsiM_reqFifo_q_0_40 to ftop/sma1/wsiS_reqFifo/Mram_arr41.SLICEM_F + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X70Y164.XQ Tcko 0.417 ftop/bias_wsiM0_MData<28> + ftop/bias/wsiM_reqFifo_q_0_40 + SLICE_X68Y167.BY net (fanout=2) 0.329 ftop/bias_wsiM0_MData<28> + SLICE_X68Y167.CLK Tdh (-Th) 0.129 ftop/sma1/wsiS_reqFifo/_varindex0000<40> + ftop/sma1/wsiS_reqFifo/Mram_arr41.SLICEM_F + ------------------------------------------------- --------------------------- + Total 0.617ns (0.288ns logic, 0.329ns route) + (46.7% logic, 53.3% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.552ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/cp/wci_reqF_9_q_0_15 (FF) + Destination: ftop/gbewrk/wci_wslv_reqF/Mram_arr16.SLICEM_F (RAM) + Requirement: 0.000ns + Data Path Delay: 0.614ns (Levels of Logic = 1) + Clock Path Skew: 0.062ns (0.465 - 0.403) + Source Clock: ftop/sys1Clk rising at 20.000ns + Destination Clock: ftop/sys1Clk rising at 20.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path: ftop/cp/wci_reqF_9_q_0_15 to ftop/gbewrk/wci_wslv_reqF/Mram_arr16.SLICEM_F + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X58Y84.XQ Tcko 0.417 ftop/cp_wci_Vm_9_MData<15> + ftop/cp/wci_reqF_9_q_0_15 + SLICE_X60Y85.BY net (fanout=2) 0.326 ftop/cp_wci_Vm_9_MData<15> + SLICE_X60Y85.CLK Tdh (-Th) 0.129 ftop/gbewrk/wci_wslv_reqF/_varindex0000<15> + ftop/gbewrk/wci_wslv_reqF/Mram_arr16.SLICEM_F + ------------------------------------------------- --------------------------- + Total 0.614ns (0.288ns logic, 0.326ns route) + (46.9% logic, 53.1% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.553ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/cp/wci_reqF_13_q_0_21 (FF) + Destination: ftop/edp0/wci_reqF/Mram_arr22.SLICEM_G (RAM) + Requirement: 0.000ns + Data Path Delay: 0.610ns (Levels of Logic = 1) + Clock Path Skew: 0.057ns (0.285 - 0.228) + Source Clock: ftop/sys1Clk rising at 20.000ns + Destination Clock: ftop/sys1Clk rising at 20.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path: ftop/cp/wci_reqF_13_q_0_21 to ftop/edp0/wci_reqF/Mram_arr22.SLICEM_G + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X27Y85.XQ Tcko 0.396 ftop/cp_wci_Vm_13_MData<21> + ftop/cp/wci_reqF_13_q_0_21 + SLICE_X24Y84.BY net (fanout=2) 0.344 ftop/cp_wci_Vm_13_MData<21> + SLICE_X24Y84.CLK Tdh (-Th) 0.130 ftop/edp0/wci_reqF/_varindex0000<21> + ftop/edp0/wci_reqF/Mram_arr22.SLICEM_G + ------------------------------------------------- --------------------------- + Total 0.610ns (0.266ns logic, 0.344ns route) + (43.6% logic, 56.4% route) + +-------------------------------------------------------------------------------- +Slack (hold path): 0.554ns (requirement - (clock path skew + uncertainty - data path)) + Source: ftop/cp/wci_reqF_13_q_0_21 (FF) + Destination: ftop/edp0/wci_reqF/Mram_arr22.SLICEM_F (RAM) + Requirement: 0.000ns + Data Path Delay: 0.611ns (Levels of Logic = 1) + Clock Path Skew: 0.057ns (0.285 - 0.228) + Source Clock: ftop/sys1Clk rising at 20.000ns + Destination Clock: ftop/sys1Clk rising at 20.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path: ftop/cp/wci_reqF_13_q_0_21 to ftop/edp0/wci_reqF/Mram_arr22.SLICEM_F + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X27Y85.XQ Tcko 0.396 ftop/cp_wci_Vm_13_MData<21> + ftop/cp/wci_reqF_13_q_0_21 + SLICE_X24Y84.BY net (fanout=2) 0.344 ftop/cp_wci_Vm_13_MData<21> + SLICE_X24Y84.CLK Tdh (-Th) 0.129 ftop/edp0/wci_reqF/_varindex0000<21> + ftop/edp0/wci_reqF/Mram_arr22.SLICEM_F + ------------------------------------------------- --------------------------- + Total 0.611ns (0.267ns logic, 0.344ns route) + (43.7% logic, 56.3% route) + +-------------------------------------------------------------------------------- + +Component Switching Limit Checks: TS_ftop_clkN210_clkdv_unbuf = PERIOD TIMEGRP "ftop_clkN210_clkdv_unbuf" + TS_SYS0CLK * 2 HIGH 50%; +-------------------------------------------------------------------------------- +Slack: 17.344ns (period - (min low pulse limit / (low pulse / period))) + Period: 20.000ns + Low pulse: 10.000ns + Low pulse limit: 1.328ns (Trpw) + Physical resource: ftop/iqadc/adcCore_acquireD_dD_OUT/SR + Logical resource: ftop/iqadc/adcCore_acquireD/dD_OUT_0/SR + Location pin: SLICE_X0Y99.SR + Clock network: ftop/cp_RST_N_wci_Vm_10 +-------------------------------------------------------------------------------- +Slack: 17.344ns (period - (min high pulse limit / (high pulse / period))) + Period: 20.000ns + High pulse: 10.000ns + High pulse limit: 1.328ns (Trpw) + Physical resource: ftop/iqadc/adcCore_acquireD_dD_OUT/SR + Logical resource: ftop/iqadc/adcCore_acquireD/dD_OUT_0/SR + Location pin: SLICE_X0Y99.SR + Clock network: ftop/cp_RST_N_wci_Vm_10 +-------------------------------------------------------------------------------- +Slack: 17.344ns (period - (min low pulse limit / (low pulse / period))) + Period: 20.000ns + Low pulse: 10.000ns + Low pulse limit: 1.328ns (Trpw) + Physical resource: ftop/cp/wci_mReset_10/rstSync/reset_hold<11>/SR + Logical resource: ftop/cp/wci_mReset_10/rstSync/reset_hold_11/SR + Location pin: SLICE_X42Y76.SR + Clock network: ftop/cp/wci_mReset_10/rst_rnm0 +-------------------------------------------------------------------------------- +Slack: 17.344ns (period - (min high pulse limit / (high pulse / period))) + Period: 20.000ns + High pulse: 10.000ns + High pulse limit: 1.328ns (Trpw) + Physical resource: ftop/cp/wci_mReset_10/rstSync/reset_hold<11>/SR + Logical resource: ftop/cp/wci_mReset_10/rstSync/reset_hold_11/SR + Location pin: SLICE_X42Y76.SR + Clock network: ftop/cp/wci_mReset_10/rst_rnm0 +-------------------------------------------------------------------------------- +Slack: 17.344ns (period - (min low pulse limit / (low pulse / period))) + Period: 20.000ns + Low pulse: 10.000ns + Low pulse limit: 1.328ns (Trpw) + Physical resource: ftop/cp/wci_mReset_10/rstSync/reset_hold<11>/SR + Logical resource: ftop/cp/wci_mReset_10/rstSync/reset_hold_10/SR + Location pin: SLICE_X42Y76.SR + Clock network: ftop/cp/wci_mReset_10/rst_rnm0 +-------------------------------------------------------------------------------- +Slack: 17.344ns (period - (min high pulse limit / (high pulse / period))) + Period: 20.000ns + High pulse: 10.000ns + High pulse limit: 1.328ns (Trpw) + Physical resource: ftop/cp/wci_mReset_10/rstSync/reset_hold<11>/SR + Logical resource: ftop/cp/wci_mReset_10/rstSync/reset_hold_10/SR + Location pin: SLICE_X42Y76.SR + Clock network: ftop/cp/wci_mReset_10/rst_rnm0 +-------------------------------------------------------------------------------- +Slack: 17.344ns (period - (min low pulse limit / (low pulse / period))) + Period: 20.000ns + Low pulse: 10.000ns + Low pulse limit: 1.328ns (Trpw) + Physical resource: ftop/cp/wci_mReset_10/rstSync/reset_hold<13>/SR + Logical resource: ftop/cp/wci_mReset_10/rstSync/reset_hold_13/SR + Location pin: SLICE_X44Y76.SR + Clock network: ftop/cp/wci_mReset_10/rst_rnm0 +-------------------------------------------------------------------------------- +Slack: 17.344ns (period - (min high pulse limit / (high pulse / period))) + Period: 20.000ns + High pulse: 10.000ns + High pulse limit: 1.328ns (Trpw) + Physical resource: ftop/cp/wci_mReset_10/rstSync/reset_hold<13>/SR + Logical resource: ftop/cp/wci_mReset_10/rstSync/reset_hold_13/SR + Location pin: SLICE_X44Y76.SR + Clock network: ftop/cp/wci_mReset_10/rst_rnm0 +-------------------------------------------------------------------------------- +Slack: 17.344ns (period - (min low pulse limit / (low pulse / period))) + Period: 20.000ns + Low pulse: 10.000ns + Low pulse limit: 1.328ns (Trpw) + Physical resource: ftop/cp/wci_mReset_10/rstSync/reset_hold<13>/SR + Logical resource: ftop/cp/wci_mReset_10/rstSync/reset_hold_12/SR + Location pin: SLICE_X44Y76.SR + Clock network: ftop/cp/wci_mReset_10/rst_rnm0 +-------------------------------------------------------------------------------- +Slack: 17.344ns (period - (min high pulse limit / (high pulse / period))) + Period: 20.000ns + High pulse: 10.000ns + High pulse limit: 1.328ns (Trpw) + Physical resource: ftop/cp/wci_mReset_10/rstSync/reset_hold<13>/SR + Logical resource: ftop/cp/wci_mReset_10/rstSync/reset_hold_12/SR + Location pin: SLICE_X44Y76.SR + Clock network: ftop/cp/wci_mReset_10/rst_rnm0 +-------------------------------------------------------------------------------- +Slack: 17.344ns (period - (min low pulse limit / (low pulse / period))) + Period: 20.000ns + Low pulse: 10.000ns + Low pulse limit: 1.328ns (Trpw) + Physical resource: ftop/cp/wci_mReset_10/rstSync/reset_hold<15>/SR + Logical resource: ftop/cp/wci_mReset_10/rstSync/reset_hold_15/SR + Location pin: SLICE_X44Y78.SR + Clock network: ftop/cp/wci_mReset_10/rst_rnm0 +-------------------------------------------------------------------------------- +Slack: 17.344ns (period - (min high pulse limit / (high pulse / period))) + Period: 20.000ns + High pulse: 10.000ns + High pulse limit: 1.328ns (Trpw) + Physical resource: ftop/cp/wci_mReset_10/rstSync/reset_hold<15>/SR + Logical resource: ftop/cp/wci_mReset_10/rstSync/reset_hold_15/SR + Location pin: SLICE_X44Y78.SR + Clock network: ftop/cp/wci_mReset_10/rst_rnm0 +-------------------------------------------------------------------------------- +Slack: 17.344ns (period - (min low pulse limit / (low pulse / period))) + Period: 20.000ns + Low pulse: 10.000ns + Low pulse limit: 1.328ns (Trpw) + Physical resource: ftop/cp/wci_mReset_10/rstSync/reset_hold<15>/SR + Logical resource: ftop/cp/wci_mReset_10/rstSync/reset_hold_14/SR + Location pin: SLICE_X44Y78.SR + Clock network: ftop/cp/wci_mReset_10/rst_rnm0 +-------------------------------------------------------------------------------- +Slack: 17.344ns (period - (min high pulse limit / (high pulse / period))) + Period: 20.000ns + High pulse: 10.000ns + High pulse limit: 1.328ns (Trpw) + Physical resource: ftop/cp/wci_mReset_10/rstSync/reset_hold<15>/SR + Logical resource: ftop/cp/wci_mReset_10/rstSync/reset_hold_14/SR + Location pin: SLICE_X44Y78.SR + Clock network: ftop/cp/wci_mReset_10/rst_rnm0 +-------------------------------------------------------------------------------- +Slack: 17.344ns (period - (min low pulse limit / (low pulse / period))) + Period: 20.000ns + Low pulse: 10.000ns + Low pulse limit: 1.328ns (Trpw) + Physical resource: ftop/cp/wci_mReset_7/rstSync/reset_hold<11>/SR + Logical resource: ftop/cp/wci_mReset_7/rstSync/reset_hold_11/SR + Location pin: SLICE_X54Y121.SR + Clock network: ftop/cp/wci_mReset_7/rst_rnm0 +-------------------------------------------------------------------------------- +Slack: 17.344ns (period - (min high pulse limit / (high pulse / period))) + Period: 20.000ns + High pulse: 10.000ns + High pulse limit: 1.328ns (Trpw) + Physical resource: ftop/cp/wci_mReset_7/rstSync/reset_hold<11>/SR + Logical resource: ftop/cp/wci_mReset_7/rstSync/reset_hold_11/SR + Location pin: SLICE_X54Y121.SR + Clock network: ftop/cp/wci_mReset_7/rst_rnm0 +-------------------------------------------------------------------------------- +Slack: 17.344ns (period - (min low pulse limit / (low pulse / period))) + Period: 20.000ns + Low pulse: 10.000ns + Low pulse limit: 1.328ns (Trpw) + Physical resource: ftop/cp/wci_mReset_7/rstSync/reset_hold<11>/SR + Logical resource: ftop/cp/wci_mReset_7/rstSync/reset_hold_10/SR + Location pin: SLICE_X54Y121.SR + Clock network: ftop/cp/wci_mReset_7/rst_rnm0 +-------------------------------------------------------------------------------- +Slack: 17.344ns (period - (min high pulse limit / (high pulse / period))) + Period: 20.000ns + High pulse: 10.000ns + High pulse limit: 1.328ns (Trpw) + Physical resource: ftop/cp/wci_mReset_7/rstSync/reset_hold<11>/SR + Logical resource: ftop/cp/wci_mReset_7/rstSync/reset_hold_10/SR + Location pin: SLICE_X54Y121.SR + Clock network: ftop/cp/wci_mReset_7/rst_rnm0 +-------------------------------------------------------------------------------- +Slack: 17.344ns (period - (min low pulse limit / (low pulse / period))) + Period: 20.000ns + Low pulse: 10.000ns + Low pulse limit: 1.328ns (Trpw) + Physical resource: ftop/cp/wci_mReset_7/rstSync/reset_hold<13>/SR + Logical resource: ftop/cp/wci_mReset_7/rstSync/reset_hold_13/SR + Location pin: SLICE_X54Y118.SR + Clock network: ftop/cp/wci_mReset_7/rst_rnm0 +-------------------------------------------------------------------------------- +Slack: 17.344ns (period - (min high pulse limit / (high pulse / period))) + Period: 20.000ns + High pulse: 10.000ns + High pulse limit: 1.328ns (Trpw) + Physical resource: ftop/cp/wci_mReset_7/rstSync/reset_hold<13>/SR + Logical resource: ftop/cp/wci_mReset_7/rstSync/reset_hold_13/SR + Location pin: SLICE_X54Y118.SR + Clock network: ftop/cp/wci_mReset_7/rst_rnm0 +-------------------------------------------------------------------------------- + + +Derived Constraint Report +Derived Constraints for TS_SYS0CLK ++-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ +| | Period | Actual Period | Timing Errors | Paths Analyzed | +| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------| +| | | Direct | Derivative | Direct | Derivative | Direct | Derivative | ++-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ +|TS_SYS0CLK | 10.000ns| 4.800ns| 9.750ns| 0| 0| 2| 5509129| +| TS_ftop_clkN210_clk0_unbuf | 10.000ns| 7.851ns| N/A| 0| 0| 1| 0| +| TS_ftop_clkN210_clkdv_unbuf | 20.000ns| 19.500ns| N/A| 0| 0| 5509128| 0| ++-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ + +All constraints were met. + + +Data Sheet report: +----------------- +All values displayed in nanoseconds (ns) + +Clock to Setup on destination clock gmii_rx_clk +---------------+---------+---------+---------+---------+ + | Src:Rise| Src:Fall| Src:Rise| Src:Fall| +Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| +---------------+---------+---------+---------+---------+ +gmii_rx_clk | 7.816| | | | +---------------+---------+---------+---------+---------+ + +Clock to Setup on destination clock gmii_sysclk +---------------+---------+---------+---------+---------+ + | Src:Rise| Src:Fall| Src:Rise| Src:Fall| +Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| +---------------+---------+---------+---------+---------+ +gmii_sysclk | 7.829| | 3.955| | +---------------+---------+---------+---------+---------+ + +Clock to Setup on destination clock sys0_clkn +---------------+---------+---------+---------+---------+ + | Src:Rise| Src:Fall| Src:Rise| Src:Fall| +Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| +---------------+---------+---------+---------+---------+ +sys0_clkn | 19.500| | | | +sys0_clkp | 19.500| | | | +---------------+---------+---------+---------+---------+ + +Clock to Setup on destination clock sys0_clkp +---------------+---------+---------+---------+---------+ + | Src:Rise| Src:Fall| Src:Rise| Src:Fall| +Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| +---------------+---------+---------+---------+---------+ +sys0_clkn | 19.500| | | | +sys0_clkp | 19.500| | | | +---------------+---------+---------+---------+---------+ + + +Timing summary: +--------------- + +Timing errors: 0 Score: 0 (Setup/Max: 0, Hold: 0) + +Constraints cover 5525384 paths, 0 nets, and 133143 connections + +Design statistics: + Minimum period: 19.500ns{1} (Maximum frequency: 51.282MHz) + + +------------------------------------Footnotes----------------------------------- +1) The minimum period statistic assumes all single cycle delays. + +Analysis completed Wed Nov 7 10:01:55 2012 +-------------------------------------------------------------------------------- + +Trace Settings: +------------------------- +Trace Settings + +Peak Memory Usage: 948 MB + + + diff --git a/logs/n210-20121107_1002/fpgaTop_map.mrp b/logs/n210-20121107_1002/fpgaTop_map.mrp new file mode 100644 index 00000000..99e312e8 --- /dev/null +++ b/logs/n210-20121107_1002/fpgaTop_map.mrp @@ -0,0 +1,1215 @@ +Release 14.3 Map P.40xd (lin64) +Xilinx Mapping Report File for Design 'fpgaTop' + +Design Information +------------------ +Command Line : map -p xc3sd3400a-fg676-5 -w -ir off -pr off -o fpgaTop_map.ncd +fpgaTop.ngd fpgaTop.pcf +Target Device : xc3sd3400a +Target Package : fg676 +Target Speed : -5 +Mapper Version : spartan3adsp -- $Revision: 1.55 $ +Mapped Date : Wed Nov 7 09:57:15 2012 + +Design Summary +-------------- +Number of errors: 0 +Number of warnings: 15 +Logic Utilization: + Number of Slice Flip Flops: 17,199 out of 47,744 36% + Number of 4 input LUTs: 28,844 out of 47,744 60% +Logic Distribution: + Number of occupied Slices: 20,435 out of 23,872 85% + Number of Slices containing only related logic: 20,435 out of 20,435 100% + Number of Slices containing unrelated logic: 0 out of 20,435 0% + *See NOTES below for an explanation of the effects of unrelated logic. + Total Number of 4 input LUTs: 31,274 out of 47,744 65% + Number used as logic: 26,401 + Number used as a route-thru: 2,430 + Number used for Dual Port RAMs: 2,412 + (Two LUTs used per Dual Port RAM) + Number used as Shift registers: 31 + + The Slice Logic Distribution report is not meaningful if the design is + over-mapped for a non-slice resource or if Placement fails. + + Number of bonded IOBs: 109 out of 469 23% + IOB Master Pads: 1 + IOB Slave Pads: 1 + Number of ODDR2s used: 11 + Number of DDR_ALIGNMENT = NONE 11 + Number of DDR_ALIGNMENT = C0 0 + Number of DDR_ALIGNMENT = C1 0 + Number of BUFGMUXs: 6 out of 24 25% + Number of DCMs: 1 out of 8 12% + Number of RAMB16BWERs: 47 out of 126 37% + +Average Fanout of Non-Clock Nets: 3.47 + +Peak Memory Usage: 1133 MB +Total REAL time to MAP completion: 30 secs +Total CPU time to MAP completion: 30 secs + +NOTES: + + Related logic is defined as being logic that shares connectivity - e.g. two + LUTs are "related" if they share common inputs. When assembling slices, + Map gives priority to combine logic that is related. Doing so results in + the best timing performance. + + Unrelated logic shares no connectivity. Map will only begin packing + unrelated logic into a slice once 99% of the slices are occupied through + related logic packing. + + Note that once logic distribution reaches the 99% level through related + logic packing, this does not mean the device is completely utilized. + Unrelated logic packing will then begin, continuing until all usable LUTs + and FFs are occupied. Depending on your timing budget, increased levels of + unrelated logic packing may adversely affect the overall timing performance + of your design. + +Table of Contents +----------------- +Section 1 - Errors +Section 2 - Warnings +Section 3 - Informational +Section 4 - Removed Logic Summary +Section 5 - Removed Logic +Section 6 - IOB Properties +Section 7 - RPMs +Section 8 - Guide Report +Section 9 - Area Group and Partition Summary +Section 10 - Timing Report +Section 11 - Configuration String Information +Section 12 - Control Set Information +Section 13 - Utilization by Hierarchy + +Section 1 - Errors +------------------ + +Section 2 - Warnings +-------------------- +WARNING:LIT:176 - Clock buffer is designated to drive clock loads. BUFGMUX + symbol "physical_group_adc_sclkdrv/ftop/iqadc/adcCore_spiI_cd/cntr_2_BUFG" + (output signal=adc_sclkdrv) has a mix of clock and non-clock loads. The + non-clock loads are: + Pin I0 of adc_sclk1 +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:367 - The signal is incomplete. The + signal does not drive any load pins in the design. +WARNING:PhysDesignRules:1176 - Issue with pin connections and/or configuration + on block::. The + block is configured to use input parity pin DIBP0. There is dangling output + for parity pin DOPB0. +WARNING:PhysDesignRules:1176 - Issue with pin connections and/or configuration + on block::. The + block is configured to use input parity pin DIBP0. There is dangling output + for parity pin DOPB0. +WARNING:PhysDesignRules:1176 - Issue with pin connections and/or configuration + on block::. The + block is configured to use input parity pin DIBP0. There is dangling output + for parity pin DOPB0. +WARNING:PhysDesignRules:1176 - Issue with pin connections and/or configuration + on block::. The + block is configured to use input parity pin DIBP0. There is dangling output + for parity pin DOPB0. +WARNING:PhysDesignRules:1176 - Issue with pin connections and/or configuration + on block::. The + block is configured to use input parity pin DIBP0. There is dangling output + for parity pin DOPB0. +WARNING:PhysDesignRules:1176 - Issue with pin connections and/or configuration + on block::. The + block is configured to use input parity pin DIBP0. There is dangling output + for parity pin DOPB0. +WARNING:PhysDesignRules:1176 - Issue with pin connections and/or configuration + on block::. The + block is configured to use input parity pin DIBP0. There is dangling output + for parity pin DOPB0. +WARNING:PhysDesignRules:1176 - Issue with pin connections and/or configuration + on block::. The + block is configured to use input parity pin DIBP0. There is dangling output + for parity pin DOPB0. +WARNING:PhysDesignRules:1176 - Issue with pin connections and/or configuration + on block::. The + block is configured to use input parity pin DIBP0. There is dangling output + for parity pin DOPB0. +WARNING:PhysDesignRules:1176 - Issue with pin connections and/or configuration + on block::. The + block is configured to use input parity pin DIBP0. There is dangling output + for parity pin DOPB0. + +Section 3 - Informational +------------------------- +INFO:LIT:243 - Logical network N4 has no load. +INFO:LIT:395 - The above info message is repeated 1922 more times for the + following (max. 5 shown): + N5, + dac_sen, + dac_smiso, + dac_lock, + dac_sclk + To see the details of these info messages, please use the -detail switch. +INFO:LIT:244 - All of the single ended outputs in this design are using slew + rate limited output drivers. The delay on speed critical single ended outputs + can be dramatically reduced by designating them as fast outputs. + +Section 4 - Removed Logic Summary +--------------------------------- + 104 block(s) removed + 205 block(s) optimized away + 443 signal(s) removed + +Section 5 - Removed Logic +------------------------- + +The trimmed logic report below shows the logic removed from your design due to +sourceless or loadless signals, and VCC or ground connections. If the removal +of a signal or symbol results in the subsequent removal of an additional signal +or symbol, the message explaining that second removal will be indented. This +indentation will be repeated as a chain of related logic is removed. + +To quickly locate the original cause for the removal of a chain of logic, look +above the place where that logic is listed in the trimming report, then locate +the lines that are least indented (begin at the leftmost edge). + +The signal "ftop/CLK_GATE_rxclkBnd" is sourceless and has been removed. +The signal "ftop/eddp1/edpReqF/d1di" is sourceless and has been removed. + Sourceless block "ftop/eddp1/edpReqF/data1_reg_8" (FF) removed. + The signal "ftop/eddp1/edpReqF/data1_reg<8>" is sourceless and has been removed. + Sourceless block "ftop/eddp1/edpReqF/data1_reg_9" (FF) removed. + The signal "ftop/eddp1/edpReqF/data1_reg<9>" is sourceless and has been removed. + Sourceless block "ftop/eddp1/edpReqF/data1_reg_18" (FF) removed. + The signal "ftop/eddp1/edpReqF/data1_reg<18>" is sourceless and has been +removed. + Sourceless block "ftop/eddp1/edpReqF/data1_reg_19" (FF) removed. + The signal "ftop/eddp1/edpReqF/data1_reg<19>" is sourceless and has been +removed. + Sourceless block "ftop/eddp1/edpReqF/data1_reg_20" (FF) removed. + The signal "ftop/eddp1/edpReqF/data1_reg<20>" is sourceless and has been +removed. + Sourceless block "ftop/eddp1/edpReqF/data1_reg_21" (FF) removed. + The signal "ftop/eddp1/edpReqF/data1_reg<21>" is sourceless and has been +removed. + Sourceless block "ftop/eddp1/edpReqF/data1_reg_22" (FF) removed. + The signal "ftop/eddp1/edpReqF/data1_reg<22>" is sourceless and has been +removed. + Sourceless block "ftop/eddp1/edpReqF/data1_reg_23" (FF) removed. + The signal "ftop/eddp1/edpReqF/data1_reg<23>" is sourceless and has been +removed. + Sourceless block "ftop/eddp1/edpReqF/data1_reg_24" (FF) removed. + The signal "ftop/eddp1/edpReqF/data1_reg<24>" is sourceless and has been +removed. + Sourceless block "ftop/eddp1/edpReqF/data1_reg_25" (FF) removed. + The signal "ftop/eddp1/edpReqF/data1_reg<25>" is sourceless and has been +removed. + Sourceless block "ftop/eddp1/edpReqF/data1_reg_26" (FF) removed. + The signal "ftop/eddp1/edpReqF/data1_reg<26>" is sourceless and has been +removed. + Sourceless block "ftop/eddp1/edpReqF/data1_reg_27" (FF) removed. + The signal "ftop/eddp1/edpReqF/data1_reg<27>" is sourceless and has been +removed. + Sourceless block "ftop/eddp1/edpReqF/data1_reg_28" (FF) removed. + The signal "ftop/eddp1/edpReqF/data1_reg<28>" is sourceless and has been +removed. + Sourceless block "ftop/eddp1/edpReqF/data1_reg_29" (FF) removed. + The signal "ftop/eddp1/edpReqF/data1_reg<29>" is sourceless and has been +removed. + Sourceless block "ftop/eddp1/edpReqF/data1_reg_30" (FF) removed. + The signal "ftop/eddp1/edpReqF/data1_reg<30>" is sourceless and has been +removed. + Sourceless block "ftop/eddp1/edpReqF/data1_reg_31" (FF) removed. + The signal "ftop/eddp1/edpReqF/data1_reg<31>" is sourceless and has been +removed. + Sourceless block "ftop/eddp1/edpReqF/data1_reg_32" (FF) removed. + The signal "ftop/eddp1/edpReqF/data1_reg<32>" is sourceless and has been +removed. + Sourceless block "ftop/eddp1/edpReqF/data1_reg_33" (FF) removed. + The signal "ftop/eddp1/edpReqF/data1_reg<33>" is sourceless and has been +removed. + Sourceless block "ftop/eddp1/edpReqF/data1_reg_34" (FF) removed. + The signal "ftop/eddp1/edpReqF/data1_reg<34>" is sourceless and has been +removed. + Sourceless block "ftop/eddp1/edpReqF/data1_reg_35" (FF) removed. + The signal "ftop/eddp1/edpReqF/data1_reg<35>" is sourceless and has been +removed. + Sourceless block "ftop/eddp1/edpReqF/data1_reg_36" (FF) removed. + The signal "ftop/eddp1/edpReqF/data1_reg<36>" is sourceless and has been +removed. + Sourceless block "ftop/eddp1/edpReqF/data1_reg_37" (FF) removed. + The signal "ftop/eddp1/edpReqF/data1_reg<37>" is sourceless and has been +removed. + Sourceless block "ftop/eddp1/edpReqF/data1_reg_38" (FF) removed. + The signal "ftop/eddp1/edpReqF/data1_reg<38>" is sourceless and has been +removed. + Sourceless block "ftop/eddp1/edpReqF/data1_reg_39" (FF) removed. + The signal "ftop/eddp1/edpReqF/data1_reg<39>" is sourceless and has been +removed. +The signal "ftop/eddp1/edpReqF/full_reg_mux0000" is sourceless and has been +removed. +The signal "ftop/eddp1/edpReqF/full_reg_not0001" is sourceless and has been +removed. +The signal "ftop/eddp1/dpReqF/d1di" is sourceless and has been removed. + Sourceless block "ftop/eddp1/dpReqF/data1_reg_8" (FF) removed. + The signal "ftop/eddp1/dpReqF/data1_reg<8>" is sourceless and has been removed. + Sourceless block "ftop/eddp1/dpReqF/data1_reg_9" (FF) removed. + The signal "ftop/eddp1/dpReqF/data1_reg<9>" is sourceless and has been removed. + Sourceless block "ftop/eddp1/dpReqF/data1_reg_18" (FF) removed. + The signal "ftop/eddp1/dpReqF/data1_reg<18>" is sourceless and has been removed. + Sourceless block "ftop/eddp1/dpReqF/data1_reg_19" (FF) removed. + The signal "ftop/eddp1/dpReqF/data1_reg<19>" is sourceless and has been removed. + Sourceless block "ftop/eddp1/dpReqF/data1_reg_20" (FF) removed. + The signal "ftop/eddp1/dpReqF/data1_reg<20>" is sourceless and has been removed. + Sourceless block "ftop/eddp1/dpReqF/data1_reg_21" (FF) removed. + The signal "ftop/eddp1/dpReqF/data1_reg<21>" is sourceless and has been removed. + Sourceless block "ftop/eddp1/dpReqF/data1_reg_22" (FF) removed. + The signal "ftop/eddp1/dpReqF/data1_reg<22>" is sourceless and has been removed. + Sourceless block "ftop/eddp1/dpReqF/data1_reg_23" (FF) removed. + The signal "ftop/eddp1/dpReqF/data1_reg<23>" is sourceless and has been removed. + Sourceless block "ftop/eddp1/dpReqF/data1_reg_24" (FF) removed. + The signal "ftop/eddp1/dpReqF/data1_reg<24>" is sourceless and has been removed. + Sourceless block "ftop/eddp1/dpReqF/data1_reg_25" (FF) removed. + The signal "ftop/eddp1/dpReqF/data1_reg<25>" is sourceless and has been removed. + Sourceless block "ftop/eddp1/dpReqF/data1_reg_26" (FF) removed. + The signal "ftop/eddp1/dpReqF/data1_reg<26>" is sourceless and has been removed. + Sourceless block "ftop/eddp1/dpReqF/data1_reg_27" (FF) removed. + The signal "ftop/eddp1/dpReqF/data1_reg<27>" is sourceless and has been removed. + Sourceless block "ftop/eddp1/dpReqF/data1_reg_28" (FF) removed. + The signal "ftop/eddp1/dpReqF/data1_reg<28>" is sourceless and has been removed. + Sourceless block "ftop/eddp1/dpReqF/data1_reg_29" (FF) removed. + The signal "ftop/eddp1/dpReqF/data1_reg<29>" is sourceless and has been removed. + Sourceless block "ftop/eddp1/dpReqF/data1_reg_30" (FF) removed. + The signal "ftop/eddp1/dpReqF/data1_reg<30>" is sourceless and has been removed. + Sourceless block "ftop/eddp1/dpReqF/data1_reg_31" (FF) removed. + The signal "ftop/eddp1/dpReqF/data1_reg<31>" is sourceless and has been removed. + Sourceless block "ftop/eddp1/dpReqF/data1_reg_32" (FF) removed. + The signal "ftop/eddp1/dpReqF/data1_reg<32>" is sourceless and has been removed. + Sourceless block "ftop/eddp1/dpReqF/data1_reg_33" (FF) removed. + The signal "ftop/eddp1/dpReqF/data1_reg<33>" is sourceless and has been removed. + Sourceless block "ftop/eddp1/dpReqF/data1_reg_34" (FF) removed. + The signal "ftop/eddp1/dpReqF/data1_reg<34>" is sourceless and has been removed. + Sourceless block "ftop/eddp1/dpReqF/data1_reg_35" (FF) removed. + The signal "ftop/eddp1/dpReqF/data1_reg<35>" is sourceless and has been removed. + Sourceless block "ftop/eddp1/dpReqF/data1_reg_36" (FF) removed. + The signal "ftop/eddp1/dpReqF/data1_reg<36>" is sourceless and has been removed. + Sourceless block "ftop/eddp1/dpReqF/data1_reg_37" (FF) removed. + The signal "ftop/eddp1/dpReqF/data1_reg<37>" is sourceless and has been removed. + Sourceless block "ftop/eddp1/dpReqF/data1_reg_38" (FF) removed. + The signal "ftop/eddp1/dpReqF/data1_reg<38>" is sourceless and has been removed. + Sourceless block "ftop/eddp1/dpReqF/data1_reg_39" (FF) removed. + The signal "ftop/eddp1/dpReqF/data1_reg<39>" is sourceless and has been removed. +The signal "ftop/eddp1/dpReqF/full_reg_mux0000" is sourceless and has been +removed. +The signal "ftop/eddp1/dpReqF/full_reg_not0001" is sourceless and has been +removed. +The signal "ftop/edp0/bram_memory_1_DOA<0>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory_1_DOA<10>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory_1_DOA<11>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory_1_DOA<12>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory_1_DOA<13>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory_1_DOA<14>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory_1_DOA<15>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory_1_DOA<16>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory_1_DOA<17>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory_1_DOA<18>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory_1_DOA<19>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory_1_DOA<1>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory_1_DOA<20>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory_1_DOA<21>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory_1_DOA<22>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory_1_DOA<23>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory_1_DOA<24>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory_1_DOA<25>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory_1_DOA<26>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory_1_DOA<27>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory_1_DOA<28>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory_1_DOA<29>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory_1_DOA<2>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory_1_DOA<30>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory_1_DOA<31>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory_1_DOA<3>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory_1_DOA<4>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory_1_DOA<5>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory_1_DOA<6>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory_1_DOA<7>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory_1_DOA<8>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory_1_DOA<9>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory_2_DOA<0>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory_2_DOA<10>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory_2_DOA<11>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory_2_DOA<12>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory_2_DOA<13>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory_2_DOA<14>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory_2_DOA<15>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory_2_DOA<16>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory_2_DOA<17>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory_2_DOA<18>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory_2_DOA<19>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory_2_DOA<1>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory_2_DOA<20>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory_2_DOA<21>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory_2_DOA<22>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory_2_DOA<23>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory_2_DOA<24>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory_2_DOA<25>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory_2_DOA<26>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory_2_DOA<27>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory_2_DOA<28>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory_2_DOA<29>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory_2_DOA<2>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory_2_DOA<30>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory_2_DOA<31>" is sourceless and has been removed. +The signal "ftop/edp0/bram_memory_2_DOA<3>" is sourceless and has been removed. +The signal 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is sourceless and has been removed. +The signal "ftop/edp1/bram_memory_1_DOB<14>" is sourceless and has been removed. +The signal "ftop/edp1/bram_memory_1_DOB<15>" is sourceless and has been removed. +The signal "ftop/edp1/bram_memory_1_DOB<16>" is sourceless and has been removed. +The signal "ftop/edp1/bram_memory_1_DOB<17>" is sourceless and has been removed. +The signal "ftop/edp1/bram_memory_1_DOB<18>" is sourceless and has been removed. +The signal "ftop/edp1/bram_memory_1_DOB<19>" is sourceless and has been removed. +The signal "ftop/edp1/bram_memory_1_DOB<20>" is sourceless and has been removed. +The signal "ftop/edp1/bram_memory_1_DOB<21>" is sourceless and has been removed. +The signal "ftop/edp1/bram_memory_1_DOB<22>" is sourceless and has been removed. +The signal "ftop/edp1/bram_memory_1_DOB<23>" is sourceless and has been removed. +The signal "ftop/edp1/bram_memory_1_DOB<24>" is sourceless and has been removed. +The signal "ftop/edp1/bram_memory_1_DOB<25>" is sourceless and has been removed. +The signal "ftop/edp1/bram_memory_1_DOB<26>" is sourceless and has been removed. +The signal "ftop/edp1/bram_memory_1_DOB<27>" is sourceless and has been removed. +The signal "ftop/edp1/bram_memory_1_DOB<28>" is sourceless and has been removed. +The signal "ftop/edp1/bram_memory_1_DOB<29>" is sourceless and has been removed. +The signal "ftop/edp1/bram_memory_1_DOB<30>" is sourceless and has been removed. +The signal "ftop/edp1/bram_memory_1_DOB<31>" is sourceless and has been removed. +The signal "ftop/edp1/bram_memory_1_DOB<8>" is sourceless and has been removed. +The signal "ftop/edp1/bram_memory_1_DOB<9>" is sourceless and has been removed. +The signal "ftop/edp1/bram_memory_2_DOB<0>" is sourceless and has been removed. +The signal "ftop/edp1/bram_memory_2_DOB<10>" is sourceless and has been removed. +The signal "ftop/edp1/bram_memory_2_DOB<11>" is sourceless and has been removed. +The signal "ftop/edp1/bram_memory_2_DOB<12>" is sourceless and has been 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"ftop/edp1/bram_memory_3_DOB<28>" is sourceless and has been removed. +The signal "ftop/edp1/bram_memory_3_DOB<29>" is sourceless and has been removed. +The signal "ftop/edp1/bram_memory_3_DOB<2>" is sourceless and has been removed. +The signal "ftop/edp1/bram_memory_3_DOB<30>" is sourceless and has been removed. +The signal "ftop/edp1/bram_memory_3_DOB<31>" is sourceless and has been removed. +The signal "ftop/edp1/bram_memory_3_DOB<3>" is sourceless and has been removed. +The signal "ftop/edp1/bram_memory_3_DOB<4>" is sourceless and has been removed. +The signal "ftop/edp1/bram_memory_3_DOB<5>" is sourceless and has been removed. +The signal "ftop/edp1/bram_memory_3_DOB<6>" is sourceless and has been removed. +The signal "ftop/edp1/bram_memory_3_DOB<7>" is sourceless and has been removed. +The signal "ftop/edp1/bram_memory_3_DOB<8>" is sourceless and has been removed. +The signal "ftop/edp1/bram_memory_3_DOB<9>" is sourceless and has been removed. +The signal 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Sourceless block "ftop/edp1/edp_inF/data1_reg_18" (FF) removed. + The signal "ftop/edp1/edp_inF/data1_reg<18>" is sourceless and has been removed. + Sourceless block "ftop/edp1/edp_inF/data1_reg_19" (FF) removed. + The signal "ftop/edp1/edp_inF/data1_reg<19>" is sourceless and has been removed. + Sourceless block "ftop/edp1/edp_inF/data1_reg_20" (FF) removed. + The signal "ftop/edp1/edp_inF/data1_reg<20>" is sourceless and has been removed. + Sourceless block "ftop/edp1/edp_inF/data1_reg_21" (FF) removed. + The signal "ftop/edp1/edp_inF/data1_reg<21>" is sourceless and has been removed. + Sourceless block "ftop/edp1/edp_inF/data1_reg_22" (FF) removed. + The signal "ftop/edp1/edp_inF/data1_reg<22>" is sourceless and has been removed. + Sourceless block "ftop/edp1/edp_inF/data1_reg_23" (FF) removed. + The signal "ftop/edp1/edp_inF/data1_reg<23>" is sourceless and has been removed. + Sourceless block "ftop/edp1/edp_inF/data1_reg_24" (FF) removed. + The signal "ftop/edp1/edp_inF/data1_reg<24>" is sourceless and has been removed. + Sourceless block "ftop/edp1/edp_inF/data1_reg_25" (FF) removed. + The signal "ftop/edp1/edp_inF/data1_reg<25>" is sourceless and has been removed. + Sourceless block "ftop/edp1/edp_inF/data1_reg_26" (FF) removed. + The signal "ftop/edp1/edp_inF/data1_reg<26>" is sourceless and has been removed. + Sourceless block "ftop/edp1/edp_inF/data1_reg_27" (FF) removed. + The signal "ftop/edp1/edp_inF/data1_reg<27>" is sourceless and has been removed. + Sourceless block "ftop/edp1/edp_inF/data1_reg_28" (FF) removed. + The signal "ftop/edp1/edp_inF/data1_reg<28>" is sourceless and has been removed. + Sourceless block "ftop/edp1/edp_inF/data1_reg_29" (FF) removed. + The signal "ftop/edp1/edp_inF/data1_reg<29>" is sourceless and has been removed. + Sourceless block "ftop/edp1/edp_inF/data1_reg_30" (FF) removed. + The signal "ftop/edp1/edp_inF/data1_reg<30>" is sourceless and has been removed. + Sourceless block "ftop/edp1/edp_inF/data1_reg_31" (FF) removed. + The signal "ftop/edp1/edp_inF/data1_reg<31>" is sourceless and has been removed. + Sourceless block "ftop/edp1/edp_inF/data1_reg_32" (FF) removed. + The signal "ftop/edp1/edp_inF/data1_reg<32>" is sourceless and has been removed. + Sourceless block "ftop/edp1/edp_inF/data1_reg_33" (FF) removed. + The signal "ftop/edp1/edp_inF/data1_reg<33>" is sourceless and has been removed. + Sourceless block "ftop/edp1/edp_inF/data1_reg_34" (FF) removed. + The signal "ftop/edp1/edp_inF/data1_reg<34>" is sourceless and has been removed. + Sourceless block "ftop/edp1/edp_inF/data1_reg_35" (FF) removed. + The signal "ftop/edp1/edp_inF/data1_reg<35>" is sourceless and has been removed. + Sourceless block "ftop/edp1/edp_inF/data1_reg_36" (FF) removed. + The signal "ftop/edp1/edp_inF/data1_reg<36>" is sourceless and has been removed. + Sourceless block "ftop/edp1/edp_inF/data1_reg_37" (FF) removed. + The signal "ftop/edp1/edp_inF/data1_reg<37>" is sourceless and has been removed. + Sourceless block "ftop/edp1/edp_inF/data1_reg_38" (FF) removed. + The signal "ftop/edp1/edp_inF/data1_reg<38>" is sourceless and has been removed. + Sourceless block "ftop/edp1/edp_inF/data1_reg_39" (FF) removed. + The signal "ftop/edp1/edp_inF/data1_reg<39>" is sourceless and has been removed. +The signal "ftop/edp1/edp_inF/full_reg_mux0000" is sourceless and has been +removed. +The signal "ftop/edp1/edp_inF/full_reg_not0001" is sourceless and has been +removed. +The signal "ftop/edp1/edp_outBF_memory/DOA<0>" is sourceless and has been +removed. +The signal "ftop/edp1/edp_outBF_memory/DOA<10>" is sourceless and has been +removed. +The signal "ftop/edp1/edp_outBF_memory/DOA<11>" is sourceless and has been +removed. +The signal "ftop/edp1/edp_outBF_memory/DOA<12>" is sourceless and has been +removed. +The signal "ftop/edp1/edp_outBF_memory/DOA<13>" is sourceless and has been +removed. +The signal "ftop/edp1/edp_outBF_memory/DOA<14>" is sourceless and has been +removed. +The signal "ftop/edp1/edp_outBF_memory/DOA<15>" is sourceless and has been +removed. +The signal "ftop/edp1/edp_outBF_memory/DOA<16>" is sourceless and has been +removed. +The signal "ftop/edp1/edp_outBF_memory/DOA<17>" is sourceless and has been +removed. +The signal "ftop/edp1/edp_outBF_memory/DOA<18>" is sourceless and has been +removed. +The signal "ftop/edp1/edp_outBF_memory/DOA<19>" is sourceless and has been +removed. +The signal "ftop/edp1/edp_outBF_memory/DOA<1>" is sourceless and has been +removed. +The signal "ftop/edp1/edp_outBF_memory/DOA<20>" is sourceless and has been +removed. +The signal "ftop/edp1/edp_outBF_memory/DOA<21>" is sourceless and has been +removed. +The signal "ftop/edp1/edp_outBF_memory/DOA<22>" is sourceless and has been +removed. +The signal "ftop/edp1/edp_outBF_memory/DOA<23>" is sourceless and has been +removed. +The signal "ftop/edp1/edp_outBF_memory/DOA<24>" is sourceless and has been +removed. +The signal "ftop/edp1/edp_outBF_memory/DOA<25>" is sourceless and has been +removed. +The signal "ftop/edp1/edp_outBF_memory/DOA<26>" is sourceless and has been +removed. +The signal "ftop/edp1/edp_outBF_memory/DOA<27>" is sourceless and has been +removed. +The signal "ftop/edp1/edp_outBF_memory/DOA<28>" is sourceless and has been +removed. +The signal "ftop/edp1/edp_outBF_memory/DOA<29>" is sourceless and has been +removed. +The signal "ftop/edp1/edp_outBF_memory/DOA<2>" is sourceless and has been +removed. +The signal "ftop/edp1/edp_outBF_memory/DOA<30>" is sourceless and has been +removed. +The signal "ftop/edp1/edp_outBF_memory/DOA<31>" is sourceless and has been +removed. +The signal "ftop/edp1/edp_outBF_memory/DOA<32>" is sourceless and has been +removed. +The signal "ftop/edp1/edp_outBF_memory/DOA<33>" is sourceless and has been +removed. +The signal "ftop/edp1/edp_outBF_memory/DOA<34>" is sourceless and has been +removed. +The signal "ftop/edp1/edp_outBF_memory/DOA<35>" is sourceless and has been +removed. +The signal "ftop/edp1/edp_outBF_memory/DOA<36>" is sourceless and has been +removed. +The signal "ftop/edp1/edp_outBF_memory/DOA<37>" is sourceless and has been +removed. +The signal "ftop/edp1/edp_outBF_memory/DOA<38>" is sourceless and has been +removed. +The signal "ftop/edp1/edp_outBF_memory/DOA<39>" is sourceless and has been +removed. +The signal "ftop/edp1/edp_outBF_memory/DOA<3>" is sourceless and has been +removed. +The signal "ftop/edp1/edp_outBF_memory/DOA<4>" is sourceless and has been +removed. +The signal "ftop/edp1/edp_outBF_memory/DOA<5>" is sourceless and has been +removed. +The signal "ftop/edp1/edp_outBF_memory/DOA<6>" is sourceless and has been +removed. +The signal "ftop/edp1/edp_outBF_memory/DOA<7>" is sourceless and has been +removed. +The signal "ftop/edp1/edp_outBF_memory/DOA<8>" is sourceless and has been +removed. +The signal "ftop/edp1/edp_outBF_memory/DOA<9>" is sourceless and has been +removed. +The signal "ftop/emux/fork1_d1F/d1di" is sourceless and has been removed. + Sourceless block "ftop/emux/fork1_d1F/data1_reg_8" (FF) removed. + The signal "ftop/emux/fork1_d1F/data1_reg<8>" is sourceless and has been +removed. + Sourceless block "ftop/emux/fork1_d1F/data1_reg_9" (FF) removed. + The signal "ftop/emux/fork1_d1F/data1_reg<9>" is sourceless and has been +removed. + Sourceless block "ftop/emux/fork1_d1F/data1_reg_18" (FF) removed. + The signal "ftop/emux/fork1_d1F/data1_reg<18>" is sourceless and has been +removed. + Sourceless block "ftop/emux/fork1_d1F/data1_reg_19" (FF) removed. + The signal "ftop/emux/fork1_d1F/data1_reg<19>" is sourceless and has been +removed. + Sourceless block "ftop/emux/fork1_d1F/data1_reg_20" (FF) removed. + The signal "ftop/emux/fork1_d1F/data1_reg<20>" is sourceless and has been +removed. + Sourceless block "ftop/emux/fork1_d1F/data1_reg_21" (FF) removed. + The signal "ftop/emux/fork1_d1F/data1_reg<21>" is sourceless and has been +removed. + Sourceless block "ftop/emux/fork1_d1F/data1_reg_22" (FF) removed. + The signal "ftop/emux/fork1_d1F/data1_reg<22>" is sourceless and has been +removed. + Sourceless block "ftop/emux/fork1_d1F/data1_reg_23" (FF) removed. + The signal "ftop/emux/fork1_d1F/data1_reg<23>" is sourceless and has been +removed. + Sourceless block "ftop/emux/fork1_d1F/data1_reg_24" (FF) removed. + The signal "ftop/emux/fork1_d1F/data1_reg<24>" is sourceless and has been +removed. + Sourceless block "ftop/emux/fork1_d1F/data1_reg_25" (FF) removed. + The signal "ftop/emux/fork1_d1F/data1_reg<25>" is sourceless and has been +removed. + Sourceless block "ftop/emux/fork1_d1F/data1_reg_26" (FF) removed. + The signal "ftop/emux/fork1_d1F/data1_reg<26>" is sourceless and has been +removed. + Sourceless block "ftop/emux/fork1_d1F/data1_reg_27" (FF) removed. + The signal "ftop/emux/fork1_d1F/data1_reg<27>" is sourceless and has been +removed. + Sourceless block "ftop/emux/fork1_d1F/data1_reg_28" (FF) removed. + The signal "ftop/emux/fork1_d1F/data1_reg<28>" is sourceless and has been +removed. + Sourceless block "ftop/emux/fork1_d1F/data1_reg_29" (FF) removed. + The signal "ftop/emux/fork1_d1F/data1_reg<29>" is sourceless and has been +removed. + Sourceless block "ftop/emux/fork1_d1F/data1_reg_30" (FF) removed. + The signal "ftop/emux/fork1_d1F/data1_reg<30>" is sourceless and has been +removed. + Sourceless block "ftop/emux/fork1_d1F/data1_reg_31" (FF) removed. + The signal "ftop/emux/fork1_d1F/data1_reg<31>" is sourceless and has been +removed. + Sourceless block "ftop/emux/fork1_d1F/data1_reg_32" (FF) removed. + The signal "ftop/emux/fork1_d1F/data1_reg<32>" is sourceless and has been +removed. + Sourceless block "ftop/emux/fork1_d1F/data1_reg_33" (FF) removed. + The signal "ftop/emux/fork1_d1F/data1_reg<33>" is sourceless and has been +removed. + Sourceless block "ftop/emux/fork1_d1F/data1_reg_34" (FF) removed. + The signal "ftop/emux/fork1_d1F/data1_reg<34>" is sourceless and has been +removed. + Sourceless block "ftop/emux/fork1_d1F/data1_reg_35" (FF) removed. + The signal "ftop/emux/fork1_d1F/data1_reg<35>" is sourceless and has been +removed. + Sourceless block "ftop/emux/fork1_d1F/data1_reg_36" (FF) removed. + The signal "ftop/emux/fork1_d1F/data1_reg<36>" is sourceless and has been +removed. + Sourceless block "ftop/emux/fork1_d1F/data1_reg_37" (FF) removed. + The signal "ftop/emux/fork1_d1F/data1_reg<37>" is sourceless and has been +removed. + Sourceless block "ftop/emux/fork1_d1F/data1_reg_38" (FF) removed. + The signal "ftop/emux/fork1_d1F/data1_reg<38>" is sourceless and has been +removed. + Sourceless block "ftop/emux/fork1_d1F/data1_reg_39" (FF) removed. + The signal "ftop/emux/fork1_d1F/data1_reg<39>" is sourceless and has been +removed. +The signal "ftop/emux/fork1_d1F/full_reg_mux0000" is sourceless and has been +removed. +The signal "ftop/emux/fork1_d1F/full_reg_not0001" is sourceless and has been +removed. +The signal "ftop/sma0/respF_memory/DOA<0>" is sourceless and has been removed. +The signal "ftop/sma0/respF_memory/DOA<10>" is sourceless and has been removed. +The signal "ftop/sma0/respF_memory/DOA<11>" is sourceless and has been removed. +The signal "ftop/sma0/respF_memory/DOA<12>" is sourceless and has been removed. +The signal "ftop/sma0/respF_memory/DOA<13>" is sourceless and has been removed. +The signal "ftop/sma0/respF_memory/DOA<14>" is sourceless and has been removed. +The signal "ftop/sma0/respF_memory/DOA<15>" is sourceless and has been removed. +The signal "ftop/sma0/respF_memory/DOA<16>" is sourceless and has been removed. +The signal "ftop/sma0/respF_memory/DOA<17>" is sourceless and has been removed. +The signal "ftop/sma0/respF_memory/DOA<18>" is sourceless and has been removed. +The signal "ftop/sma0/respF_memory/DOA<19>" is sourceless and has been removed. +The signal "ftop/sma0/respF_memory/DOA<1>" is sourceless and has been removed. +The signal "ftop/sma0/respF_memory/DOA<20>" is sourceless and has been removed. +The signal "ftop/sma0/respF_memory/DOA<21>" is sourceless and has been removed. +The signal "ftop/sma0/respF_memory/DOA<22>" is sourceless and has been removed. +The signal "ftop/sma0/respF_memory/DOA<23>" is sourceless and has been removed. +The signal "ftop/sma0/respF_memory/DOA<24>" is sourceless and has been removed. +The signal "ftop/sma0/respF_memory/DOA<25>" is sourceless and has been removed. +The signal "ftop/sma0/respF_memory/DOA<26>" is sourceless and has been removed. +The signal "ftop/sma0/respF_memory/DOA<27>" is sourceless and has been removed. +The signal "ftop/sma0/respF_memory/DOA<28>" is sourceless and has been removed. +The signal "ftop/sma0/respF_memory/DOA<29>" is sourceless and has been removed. +The signal "ftop/sma0/respF_memory/DOA<2>" is sourceless and has been removed. +The signal "ftop/sma0/respF_memory/DOA<30>" is sourceless and has been removed. +The signal "ftop/sma0/respF_memory/DOA<31>" is sourceless and has been removed. +The signal "ftop/sma0/respF_memory/DOA<32>" is sourceless and has been removed. +The signal "ftop/sma0/respF_memory/DOA<33>" is sourceless and has been removed. +The signal "ftop/sma0/respF_memory/DOA<34>" is sourceless and has been removed. +The signal "ftop/sma0/respF_memory/DOA<35>" is sourceless and has been removed. +The signal "ftop/sma0/respF_memory/DOA<36>" is sourceless and has been removed. +The signal "ftop/sma0/respF_memory/DOA<37>" is sourceless and has been removed. +The signal "ftop/sma0/respF_memory/DOA<38>" is sourceless and has been removed. +The signal "ftop/sma0/respF_memory/DOA<39>" is sourceless and has been removed. +The signal "ftop/sma0/respF_memory/DOA<3>" is sourceless and has been removed. +The signal "ftop/sma0/respF_memory/DOA<40>" is sourceless and has been removed. +The signal "ftop/sma0/respF_memory/DOA<41>" is sourceless and has been removed. +The signal "ftop/sma0/respF_memory/DOA<42>" is sourceless and has been removed. +The signal "ftop/sma0/respF_memory/DOA<43>" is sourceless and has been removed. +The signal "ftop/sma0/respF_memory/DOA<44>" is sourceless and has been removed. +The signal "ftop/sma0/respF_memory/DOA<4>" is sourceless and has been removed. +The signal "ftop/sma0/respF_memory/DOA<54>" is sourceless and has been removed. +The signal "ftop/sma0/respF_memory/DOA<55>" is sourceless and has been removed. +The signal "ftop/sma0/respF_memory/DOA<56>" is sourceless and has been removed. +The signal "ftop/sma0/respF_memory/DOA<57>" is sourceless and has been removed. +The signal "ftop/sma0/respF_memory/DOA<58>" is sourceless and has been removed. +The signal "ftop/sma0/respF_memory/DOA<59>" is sourceless and has been removed. +The signal "ftop/sma0/respF_memory/DOA<5>" is sourceless and has been removed. +The signal "ftop/sma0/respF_memory/DOA<60>" is sourceless and has been removed. +The signal "ftop/sma0/respF_memory/DOA<6>" is sourceless and has been removed. +The signal "ftop/sma0/respF_memory/DOA<7>" is sourceless and has been removed. +The signal "ftop/sma0/respF_memory/DOA<8>" is sourceless and has been removed. +The signal "ftop/sma0/respF_memory/DOA<9>" is sourceless and has been removed. +The signal "ftop/sma0/respF_memory/DOB<44>" is sourceless and has been removed. +The signal "ftop/sma0/respF_memory/DOB<54>" is sourceless and has been removed. +The signal "ftop/sma0/respF_memory/DOB<55>" is sourceless and has been removed. +The signal "ftop/sma1/respF_memory/DOA<54>" is sourceless and has been removed. +The signal "ftop/sma1/respF_memory/DOA<55>" is sourceless and has been removed. +The signal "ftop/sma1/respF_memory/DOA<56>" is sourceless and has been removed. +The signal "ftop/sma1/respF_memory/DOA<57>" is sourceless and has been removed. +The signal "ftop/sma1/respF_memory/DOA<58>" is sourceless and has been removed. +The signal "ftop/sma1/respF_memory/DOA<59>" is sourceless and has been removed. +The signal "ftop/sma1/respF_memory/DOA<60>" is sourceless and has been removed. +The signal "ftop/sma1/respF_memory/DOB<54>" is sourceless and has been removed. +The signal "ftop/sma1/respF_memory/DOB<55>" is sourceless and has been removed. +The signal "ftop/iqadc/adcCore_sampF_memory/DOA<36>" is sourceless and has been +removed. +The signal "ftop/iqadc/adcCore_sampF_memory/DOA<37>" is sourceless and has been +removed. +The signal "ftop/iqadc/adcCore_sampF_memory/DOA<38>" is sourceless and has been +removed. +The signal "ftop/iqadc/adcCore_sampF_memory/DOB<37>" is sourceless and has been +removed. +The signal "ftop/iqadc/adcCore_sampF_memory/DOB<38>" is sourceless and has been +removed. +The signal "ftop/gbe0/gmac/RDY_phyInterrupt" is sourceless and has been removed. +Unused block "ftop/edp1/edp_inF/d1di1" (ROM) removed. +Unused block "ftop/edp1/edp_inF/full_reg_not00011" (ROM) removed. +Unused block "ftop/eddp1/dpReqF/d1di1" (ROM) removed. +Unused block "ftop/eddp1/dpReqF/full_reg_not00011" (ROM) removed. +Unused block "ftop/eddp1/edpReqF/d1di1" (ROM) removed. +Unused block "ftop/eddp1/edpReqF/full_reg_not00011" (ROM) removed. +Unused block "ftop/emux/fork1_d1F/d1di1" (ROM) removed. +Unused block "ftop/emux/fork1_d1F/full_reg_not00011" (ROM) removed. + +Optimized Block(s): +TYPE BLOCK +GND ftop/XST_GND +VCC ftop/XST_VCC +GND ftop/bias/XST_GND +VCC ftop/bias/XST_VCC +GND ftop/bias/wci_wslv_reqF/XST_GND +GND ftop/bias/wsiS_reqFifo/XST_GND +GND ftop/clkN210/XST_GND +GND ftop/cp/XST_GND +VCC ftop/cp/XST_VCC +GND ftop/cp/adminResp1F/XST_GND +GND ftop/cp/adminResp2F/XST_GND +GND ftop/cp/adminResp3F/XST_GND +GND ftop/cp/adminResp4F/XST_GND +GND ftop/cp/adminRespF/XST_GND +GND ftop/cp/rom_memory/XST_GND +GND ftop/cp/rom_serverAdapter_outDataCore/XST_GND +GND ftop/cp/timeServ_setRefF/XST_GND +VCC ftop/cp/wci_mReset_10/rstSync/XST_VCC +VCC ftop/cp/wci_mReset_13/rstSync/XST_VCC +VCC ftop/cp/wci_mReset_14/rstSync/XST_VCC +VCC ftop/cp/wci_mReset_2/rstSync/XST_VCC +VCC ftop/cp/wci_mReset_3/rstSync/XST_VCC +VCC ftop/cp/wci_mReset_4/rstSync/XST_VCC +VCC ftop/cp/wci_mReset_7/rstSync/XST_VCC +VCC ftop/cp/wci_mReset_9/rstSync/XST_VCC +GND ftop/cp/wci_respF/XST_GND +GND ftop/cp/wci_respF_1/XST_GND +GND ftop/cp/wci_respF_10/XST_GND +GND ftop/cp/wci_respF_11/XST_GND +GND ftop/cp/wci_respF_12/XST_GND +GND ftop/cp/wci_respF_13/XST_GND +GND ftop/cp/wci_respF_14/XST_GND +GND ftop/cp/wci_respF_2/XST_GND +GND ftop/cp/wci_respF_3/XST_GND +GND ftop/cp/wci_respF_4/XST_GND +GND ftop/cp/wci_respF_5/XST_GND +GND ftop/cp/wci_respF_6/XST_GND +GND ftop/cp/wci_respF_7/XST_GND +GND ftop/cp/wci_respF_8/XST_GND +GND ftop/cp/wci_respF_9/XST_GND +GND ftop/edcp/XST_GND +VCC ftop/edcp/XST_VCC +GND ftop/eddp0/XST_GND +GND ftop/eddp1/XST_GND +GND ftop/edp0/XST_GND +VCC ftop/edp0/XST_VCC +GND ftop/edp0/bram_memory/XST_GND +GND ftop/edp0/bram_memory_1/XST_GND +GND ftop/edp0/bram_memory_2/XST_GND +GND ftop/edp0/bram_memory_3/XST_GND +GND ftop/edp0/bram_serverAdapterB_1_outDataCore/XST_GND +GND ftop/edp0/bram_serverAdapterB_2_outDataCore/XST_GND +GND ftop/edp0/bram_serverAdapterB_3_outDataCore/XST_GND +GND ftop/edp0/bram_serverAdapterB_outDataCore/XST_GND +GND ftop/edp0/edp_tlpBRAM_mReqF/XST_GND +LUT2 ftop/edp0/edp_tlpBRAM_mReqF/data0_reg_or0000<100>1 + optimized to 0 +LUT2 ftop/edp0/edp_tlpBRAM_mReqF/data0_reg_or0000<102>1 + optimized to 0 +LUT2 ftop/edp0/edp_tlpBRAM_mReqF/data0_reg_or0000<104>1 + optimized to 0 +LUT2 ftop/edp0/edp_tlpBRAM_mReqF/data0_reg_or0000<106>1 + optimized to 0 +LUT2 ftop/edp0/edp_tlpBRAM_mReqF/data0_reg_or0000<108>1 + optimized to 0 +LUT2 ftop/edp0/edp_tlpBRAM_mReqF/data0_reg_or0000<110>1 + optimized to 0 +LUT2 ftop/edp0/edp_tlpBRAM_mReqF/data0_reg_or0000<112>1 + optimized to 0 +LUT2 ftop/edp0/edp_tlpBRAM_mReqF/data0_reg_or0000<114>1 + optimized to 0 +LUT2 ftop/edp0/edp_tlpBRAM_mReqF/data0_reg_or0000<116>1 + optimized to 0 +LUT2 ftop/edp0/edp_tlpBRAM_mReqF/data0_reg_or0000<118>1 + optimized to 0 +LUT2 ftop/edp0/edp_tlpBRAM_mReqF/data0_reg_or0000<120>1 + optimized to 0 +LUT2 ftop/edp0/edp_tlpBRAM_mReqF/data0_reg_or0000<122>1 + optimized to 0 +LUT2 ftop/edp0/edp_tlpBRAM_mReqF/data0_reg_or0000<124>1 + optimized to 0 +LUT2 ftop/edp0/edp_tlpBRAM_mReqF/data0_reg_or0000<126>1 + optimized to 0 +LUT2 ftop/edp0/edp_tlpBRAM_mReqF/data0_reg_or0000<128>1 + optimized to 0 +LUT2 ftop/edp0/edp_tlpBRAM_mReqF/data0_reg_or0000<42>1 + optimized to 0 +LUT2 ftop/edp0/edp_tlpBRAM_mReqF/data0_reg_or0000<44>1 + optimized to 0 +GND ftop/edp0/edp_tlpBRAM_mRespF/XST_GND +GND ftop/edp0/wci_reqF/XST_GND +GND ftop/edp0/wmi_wmi_dhF/XST_GND +GND ftop/edp0/wmi_wmi_mFlagF/XST_GND +GND ftop/edp0/wmi_wmi_reqF/XST_GND +GND ftop/edp1/XST_GND +VCC ftop/edp1/XST_VCC +GND ftop/edp1/bram_memory/XST_GND +GND ftop/edp1/bram_memory_1/XST_GND +GND ftop/edp1/bram_memory_2/XST_GND +GND ftop/edp1/bram_memory_3/XST_GND +GND ftop/edp1/bram_serverAdapterA_1_outDataCore/XST_GND +GND ftop/edp1/bram_serverAdapterA_2_outDataCore/XST_GND +GND ftop/edp1/bram_serverAdapterA_3_outDataCore/XST_GND +GND ftop/edp1/bram_serverAdapterA_outDataCore/XST_GND +GND ftop/edp1/bram_serverAdapterB_1_outDataCore/XST_GND +GND ftop/edp1/bram_serverAdapterB_outDataCore/XST_GND +LUT2 ftop/edp1/edp_inF/d0d11 + optimized to 0 +INV ftop/edp1/edp_inF/empty_reg_not00011_INV_0 +FDSE ftop/edp1/edp_inF/full_reg + optimized to 1 +LUT3 ftop/edp1/edp_inF/full_reg_mux00001 + optimized to 1 +GND ftop/edp1/edp_outBF_memory/XST_GND +GND ftop/edp1/edp_tlpBRAM_mReqF/XST_GND +LUT2 ftop/edp1/edp_tlpBRAM_mReqF/data0_reg_or0000<0>1 + optimized to 0 +LUT2 ftop/edp1/edp_tlpBRAM_mReqF/data0_reg_or0000<10>1 + optimized to 0 +LUT2 ftop/edp1/edp_tlpBRAM_mReqF/data0_reg_or0000<128>1 + optimized to 0 +LUT2 ftop/edp1/edp_tlpBRAM_mReqF/data0_reg_or0000<2>1 + optimized to 0 +LUT2 ftop/edp1/edp_tlpBRAM_mReqF/data0_reg_or0000<42>1 + optimized to 0 +LUT2 ftop/edp1/edp_tlpBRAM_mReqF/data0_reg_or0000<44>1 + optimized to 0 +LUT2 ftop/edp1/edp_tlpBRAM_mRespF/data0_reg_or0000<129>1 + optimized to 0 +LUT2 ftop/edp1/edp_tlpBRAM_mRespF/data0_reg_or0000<131>1 + optimized to 0 +LUT2 ftop/edp1/edp_tlpBRAM_mRespF/data0_reg_or0000<133>1 + optimized to 0 +GND ftop/edp1/wci_reqF/XST_GND +GND ftop/edp1/wmi_wmi_dhF/XST_GND +GND ftop/edp1/wmi_wmi_mFlagF/XST_GND +GND ftop/edp1/wmi_wmi_reqF/XST_GND +VCC ftop/emux/XST_VCC +GND ftop/gbe0/XST_GND +VCC ftop/gbe0/XST_VCC +GND ftop/gbe0/gmac/XST_GND +VCC ftop/gbe0/gmac/XST_VCC +GND ftop/gbe0/gmac/gmac/XST_GND +VCC ftop/gbe0/gmac/gmac/XST_VCC +GND ftop/gbe0/gmac/gmac/rxRS_rxF/XST_GND +VCC ftop/gbe0/gmac/gmac/rxRS_rxRst/XST_VCC +VCC ftop/gbe0/gmac/gmac/txRS_txRst/XST_VCC +GND ftop/gbe0/gmac/rxF/XST_GND +GND ftop/gbe0/gmac/txF/XST_GND +LUT2 ftop/gbe0/mdi_fRequest/data0_reg_or0000<0>1 + optimized to 0 +LUT2 ftop/gbe0/mdi_fRequest/data0_reg_or0000<11>1 + optimized to 0 +LUT2 ftop/gbe0/mdi_fRequest/data0_reg_or0000<13>1 + optimized to 0 +LUT2 ftop/gbe0/mdi_fRequest/data0_reg_or0000<16>1 + optimized to 0 +LUT2 ftop/gbe0/mdi_fRequest/data0_reg_or0000<17>1 + optimized to 0 +LUT2 ftop/gbe0/mdi_fRequest/data0_reg_or0000<1>1 + optimized to 0 +LUT2 ftop/gbe0/mdi_fRequest/data0_reg_or0000<22>1 + optimized to 0 +LUT2 ftop/gbe0/mdi_fRequest/data0_reg_or0000<23>1 + optimized to 0 +LUT2 ftop/gbe0/mdi_fRequest/data0_reg_or0000<24>1 + optimized to 0 +LUT2 ftop/gbe0/mdi_fRequest/data0_reg_or0000<25>1 + optimized to 0 +GND ftop/gbe0/mdi_fResponse/XST_GND +GND ftop/gbe0/mdi_rPlayIndex/XST_GND +VCC ftop/gbe0/mdi_rPrescaler/XST_VCC +VCC ftop/gbe0/phyRst/rstSync/XST_VCC +GND ftop/gbewrk/XST_GND +VCC ftop/gbewrk/XST_VCC +GND ftop/gbewrk/wci_wslv_reqF/XST_GND +VCC ftop/gmiixo_rst/XST_VCC +GND ftop/iqadc/XST_GND +VCC ftop/iqadc/XST_VCC +GND ftop/iqadc/adcCore_colGate_sampF/XST_GND +GND ftop/iqadc/adcCore_sampF_memory/XST_GND +VCC ftop/iqadc/adcCore_sampF_memory/XST_VCC +VCC ftop/iqadc/adcCore_sdrRst/XST_VCC +VCC ftop/iqadc/adcCore_spiI_slowReset/XST_VCC +VCC ftop/iqadc/fcAdc_testRst/XST_VCC +GND ftop/iqadc/wci_wslv_reqF/XST_GND +GND ftop/ledLogic/XST_GND +VCC ftop/ledLogic/XST_VCC +GND ftop/pwrk/XST_GND +VCC ftop/pwrk/XST_VCC +VCC ftop/pwrk/flashC_reqF/XST_VCC +LUT3 ftop/pwrk/i2cC_fResponse/ring_empty_not000111 + optimized to 0 +GND ftop/pwrk/i2cC_rPlayIndex/XST_GND +GND ftop/pwrk/i2cC_rPrescaler/XST_GND +GND ftop/pwrk/wci_wslv_reqF/XST_GND +GND ftop/sma0/XST_GND +VCC ftop/sma0/XST_VCC +GND ftop/sma0/mesgTokenF/XST_GND +GND ftop/sma0/respF_memory/XST_GND +GND ftop/sma0/wci_wslv_reqF/XST_GND +GND ftop/sma0/wsiS_reqFifo/XST_GND +GND ftop/sma1/XST_GND +VCC ftop/sma1/XST_VCC +GND ftop/sma1/mesgTokenF/XST_GND +GND ftop/sma1/respF_memory/XST_GND +GND ftop/sma1/wci_wslv_reqF/XST_GND +GND ftop/sma1/wsiS_reqFifo/XST_GND +LUT2 ftop/eddp1/dpReqF/d0d11 + optimized to 0 +FDSE ftop/eddp1/dpReqF/full_reg + optimized to 1 +LUT3 ftop/eddp1/dpReqF/full_reg_mux00001 + optimized to 1 +LUT2 ftop/eddp1/edpReqF/d0d11 + optimized to 0 +FDSE ftop/eddp1/edpReqF/full_reg + optimized to 1 +LUT3 ftop/eddp1/edpReqF/full_reg_mux00001 + optimized to 1 +LUT2 ftop/emux/fork1_d1F/d0d11 + optimized to 0 +FDSE ftop/emux/fork1_d1F/full_reg + optimized to 1 +LUT3 ftop/emux/fork1_d1F/full_reg_mux00001 + optimized to 1 + +To enable printing of redundant blocks removed and signals merged, set the +detailed map report option and rerun map. + +Section 6 - IOB Properties +-------------------------- + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +| IOB Name | Type | Direction | IO Standard | Drive | Slew | Reg (s) | Resistor | IBUF/IFD | SUSPEND | +| | | | | Strength | Rate | | | Delay | | ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +| adc_clkout | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 | | +| adc_da<0> | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 | | +| adc_da<1> | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 | | +| adc_da<2> | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 | | +| adc_da<3> | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 | | +| adc_da<4> | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 | | +| adc_da<5> | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 | | +| adc_da<6> | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 | | +| adc_da<7> | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 | | +| adc_da<8> | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 | | +| adc_da<9> | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 | | +| adc_da<10> | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 | | +| adc_da<11> | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 | | +| adc_da<12> | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 | | +| adc_da<13> | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 | | +| adc_db<0> | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 | | +| adc_db<1> | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 | | +| adc_db<2> | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 | | +| adc_db<3> | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 | | +| adc_db<4> | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 | | +| adc_db<5> | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 | | +| adc_db<6> | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 | | +| adc_db<7> | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 | | +| adc_db<8> | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 | | +| adc_db<9> | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 | | +| adc_db<10> | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 | | +| adc_db<11> | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 | | +| adc_db<12> | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 | | +| adc_db<13> | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 | | +| adc_sclk | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 | 3STATE | +| adc_sen | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 | 3STATE | +| adc_smiso | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 | | +| adc_smosi | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 | 3STATE | +| debug<0> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 | 3STATE | +| debug<1> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 | 3STATE | +| debug<2> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 | 3STATE | +| debug<3> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 | 3STATE | +| debug<4> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 | 3STATE | +| debug<5> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 | 3STATE | +| debug<6> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 | 3STATE | +| debug<7> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 | 3STATE | +| debug<8> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 | 3STATE | +| debug<9> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 | 3STATE | +| debug<10> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 | 3STATE | +| debug<11> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 | 3STATE | +| debug<12> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 | 3STATE | +| debug<13> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 | 3STATE | +| debug<14> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 | 3STATE | +| debug<15> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 | 3STATE | +| debug<16> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 | 3STATE | +| debug<17> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 | 3STATE | +| debug<18> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 | 3STATE | +| debug<19> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 | 3STATE | +| debug<20> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 | 3STATE | +| debug<21> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 | 3STATE | +| debug<22> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 | 3STATE | +| debug<23> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 | 3STATE | +| debug<24> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 | 3STATE | +| debug<25> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 | 3STATE | +| debug<26> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 | 3STATE | +| debug<27> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 | 3STATE | +| debug<28> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 | 3STATE | +| debug<29> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 | 3STATE | +| debug<30> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 | 3STATE | +| debug<31> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 | 3STATE | +| flash_clk | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 | 3STATE | +| flash_csn | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 | 3STATE | +| flash_miso | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 | | +| flash_mosi | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 | 3STATE | +| fpga_rstn | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 | | +| gmii_col | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 | | +| gmii_crs | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 | | +| gmii_gtx_clk | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | ODDR2 | | 0 / 0 | 3STATE | +| gmii_intr | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 | | +| gmii_led | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 | 3STATE | +| gmii_rstn | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 | 3STATE | +| gmii_rx_clk | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 | | +| gmii_rx_dv | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 | | +| gmii_rx_er | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 | | +| gmii_rxd<0> | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 | | +| gmii_rxd<1> | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 | | +| gmii_rxd<2> | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 | | +| gmii_rxd<3> | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 | | +| gmii_rxd<4> | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 | | +| gmii_rxd<5> | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 | | +| gmii_rxd<6> | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 | | +| gmii_rxd<7> | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 | | +| gmii_sysclk | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 | | +| gmii_tx_en | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | ODDR2 | | 0 / 0 | 3STATE | +| gmii_tx_er | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | ODDR2 | | 0 / 0 | 3STATE | +| gmii_txd<0> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | ODDR2 | | 0 / 0 | 3STATE | +| gmii_txd<1> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | ODDR2 | | 0 / 0 | 3STATE | +| gmii_txd<2> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | ODDR2 | | 0 / 0 | 3STATE | +| gmii_txd<3> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | ODDR2 | | 0 / 0 | 3STATE | +| gmii_txd<4> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | ODDR2 | | 0 / 0 | 3STATE | +| gmii_txd<5> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | ODDR2 | | 0 / 0 | 3STATE | +| gmii_txd<6> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | ODDR2 | | 0 / 0 | 3STATE | +| gmii_txd<7> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | ODDR2 | | 0 / 0 | 3STATE | +| i2c_scl | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 | 3STATE | +| i2c_sda | IOB | BIDIR | LVCMOS25 | 12 | SLOW | | | 0 / 0 | 3STATE | +| led<1> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 | 3STATE | +| led<2> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 | 3STATE | +| led<3> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 | 3STATE | +| led<4> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 | 3STATE | +| led<5> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 | 3STATE | +| mdio_mdc | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 | 3STATE | +| mdio_mdd | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 | 3STATE | +| sys0_clkn | DIFFSI_NDT | INPUT | LVDS_25 | | | | | 0 / 0 | | +| sys0_clkp | DIFFMI_NDT | INPUT | LVDS_25 | | | | | 0 / 0 | | ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ + +Section 7 - RPMs +---------------- + +Section 8 - Guide Report +------------------------ +Guide not run on this design. + +Section 9 - Area Group and Partition Summary +-------------------------------------------- + +Partition Implementation Status +------------------------------- + + No Partitions were found in this design. + +------------------------------- + +Area Group Information +---------------------- + + No area groups were found in this design. + +---------------------- + +Section 10 - Timing Report +-------------------------- +This design was not run using timing mode. + +Section 11 - Configuration String Details +----------------------------------------- +Use the "-detail" map option to print out Configuration Strings + +Section 12 - Control Set Information +------------------------------------ +No control set information for this architecture. + +Section 13 - Utilization by Hierarchy +------------------------------------- +Use the "-detail" map option to print out the Utilization by Hierarchy section. diff --git a/rtl/mkBiasWorker16B.v b/rtl/mkBiasWorker16B.v index 44685cb2..fdebdb12 100644 --- a/rtl/mkBiasWorker16B.v +++ b/rtl/mkBiasWorker16B.v @@ -1,7 +1,7 @@ // -// Generated by Bluespec Compiler, version 2012.09.beta1 (build 29570, 2012-09.11) +// Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Tue Dec 11 16:20:59 EST 2012 +// On Fri Jun 21 16:57:44 EDT 2013 // // // Ports: @@ -343,10 +343,10 @@ module mkBiasWorker16B(wciS0_Clk, wire [1 : 0] wci_wslv_reqF_countReg$D_IN; wire wci_wslv_reqF_countReg$EN; - // register wci_wslv_respF_c_r - reg [1 : 0] wci_wslv_respF_c_r; - wire [1 : 0] wci_wslv_respF_c_r$D_IN; - wire wci_wslv_respF_c_r$EN; + // register wci_wslv_respF_cntr_r + reg [1 : 0] wci_wslv_respF_cntr_r; + wire [1 : 0] wci_wslv_respF_cntr_r$D_IN; + wire wci_wslv_respF_cntr_r$EN; // register wci_wslv_respF_q_0 reg [33 : 0] wci_wslv_respF_q_0; @@ -397,10 +397,10 @@ module mkBiasWorker16B(wciS0_Clk, reg wsiM_peerIsReady; wire wsiM_peerIsReady$D_IN, wsiM_peerIsReady$EN; - // register wsiM_reqFifo_c_r - reg [1 : 0] wsiM_reqFifo_c_r; - wire [1 : 0] wsiM_reqFifo_c_r$D_IN; - wire wsiM_reqFifo_c_r$EN; + // register wsiM_reqFifo_cntr_r + reg [1 : 0] wsiM_reqFifo_cntr_r; + wire [1 : 0] wsiM_reqFifo_cntr_r$D_IN; + wire wsiM_reqFifo_cntr_r$EN; // register wsiM_reqFifo_q_0 reg [168 : 0] wsiM_reqFifo_q_0; @@ -535,34 +535,38 @@ module mkBiasWorker16B(wciS0_Clk, MUX_wci_wslv_respF_q_1$write_1__VAL_1, MUX_wci_wslv_respF_x_wire$wset_1__VAL_1, MUX_wci_wslv_respF_x_wire$wset_1__VAL_2; - wire [1 : 0] MUX_wci_wslv_respF_c_r$write_1__VAL_1, - MUX_wci_wslv_respF_c_r$write_1__VAL_2, - MUX_wsiM_reqFifo_c_r$write_1__VAL_1, - MUX_wsiM_reqFifo_c_r$write_1__VAL_2; + wire [1 : 0] MUX_wci_wslv_respF_cntr_r$write_1__VAL_2, + MUX_wsiM_reqFifo_cntr_r$write_1__VAL_1, + MUX_wsiM_reqFifo_cntr_r$write_1__VAL_2; wire MUX_biasValue$write_1__SEL_1, MUX_biasValue$write_1__SEL_2, MUX_controlReg$write_1__SEL_1, MUX_wci_wslv_illegalEdge$write_1__SEL_1, - MUX_wci_wslv_illegalEdge$write_1__SEL_2, - MUX_wci_wslv_illegalEdge$write_1__VAL_2, + MUX_wci_wslv_illegalEdge$write_1__VAL_1, + MUX_wci_wslv_respF_q_0$write_1__SEL_1, MUX_wci_wslv_respF_q_0$write_1__SEL_2, + MUX_wci_wslv_respF_q_1$write_1__SEL_1, MUX_wci_wslv_respF_q_1$write_1__SEL_2, + MUX_wsiM_reqFifo_q_0$write_1__SEL_1, MUX_wsiM_reqFifo_q_0$write_1__SEL_2, + MUX_wsiM_reqFifo_q_1$write_1__SEL_1, MUX_wsiM_reqFifo_q_1$write_1__SEL_2, MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3; // remaining internal signals - reg [63 : 0] v__h11501, v__h11656, v__h3706, v__h3881, v__h4025; - reg [31 : 0] _theResult____h11640; - wire [127 : 0] x_data__h10386; - wire [31 : 0] rdat__h11730, - rdat__h11830, - rdat__h11844, - rdat__h11852, - rdat__h11858, - rdat__h11872, - rdat__h11880; - wire [15 : 0] x__h11734; + reg [63 : 0] v__h11230, v__h11385, v__h3574, v__h3749, v__h3893; + reg [31 : 0] _theResult____h11369; + wire [127 : 0] x_data__h10099; + wire [31 : 0] rdat__h11459, + rdat__h11559, + rdat__h11573, + rdat__h11581, + rdat__h11587, + rdat__h11601, + rdat__h11609; + wire [15 : 0] x__h11463; + wire [1 : 0] wci_wslv_respF_cntr_r_8_MINUS_1___d27; + wire _dfoo1, _dfoo3, _dfoo5, _dfoo7; // value method wciS0_sResp assign wciS0_SResp = wci_wslv_respF_q_0[33:32] ; @@ -658,53 +662,45 @@ module mkBiasWorker16B(wciS0_Clk, // rule RL_wci_cfwr assign WILL_FIRE_RL_wci_cfwr = - wci_wslv_respF_c_r != 2'd2 && wci_wslv_reqF$EMPTY_N && + wci_wslv_respF_cntr_r != 2'd2 && wci_wslv_reqF$EMPTY_N && wci_wslv_wci_cfwr_pw$whas && !WILL_FIRE_RL_wci_wslv_ctl_op_start && !WILL_FIRE_RL_wci_wslv_ctl_op_complete ; // rule RL_wci_wslv_ctl_op_complete assign WILL_FIRE_RL_wci_wslv_ctl_op_complete = - wci_wslv_respF_c_r != 2'd2 && wci_wslv_ctlOpActive && + wci_wslv_respF_cntr_r != 2'd2 && wci_wslv_ctlOpActive && wci_wslv_ctlAckReg ; // rule RL_wci_cfrd assign WILL_FIRE_RL_wci_cfrd = - wci_wslv_respF_c_r != 2'd2 && wci_wslv_reqF$EMPTY_N && + wci_wslv_respF_cntr_r != 2'd2 && wci_wslv_reqF$EMPTY_N && wci_wslv_wci_cfrd_pw$whas && !WILL_FIRE_RL_wci_wslv_ctl_op_start && !WILL_FIRE_RL_wci_wslv_ctl_op_complete ; // rule RL_wci_wslv_respF_incCtr assign WILL_FIRE_RL_wci_wslv_respF_incCtr = - ((wci_wslv_respF_c_r == 2'd0) ? - wci_wslv_respF_x_wire$whas : - wci_wslv_respF_c_r != 2'd1 || wci_wslv_respF_x_wire$whas) && - wci_wslv_respF_enqueueing$whas && - !(wci_wslv_respF_c_r != 2'd0) ; + wci_wslv_respF_x_wire$whas && wci_wslv_respF_enqueueing$whas && + !(wci_wslv_respF_cntr_r != 2'd0) ; // rule RL_wci_wslv_respF_decCtr assign WILL_FIRE_RL_wci_wslv_respF_decCtr = - wci_wslv_respF_c_r != 2'd0 && !wci_wslv_respF_enqueueing$whas ; + wci_wslv_respF_cntr_r != 2'd0 && + !wci_wslv_respF_enqueueing$whas ; // rule RL_wci_wslv_respF_both assign WILL_FIRE_RL_wci_wslv_respF_both = - ((wci_wslv_respF_c_r == 2'd1) ? - wci_wslv_respF_x_wire$whas : - wci_wslv_respF_c_r != 2'd2 || wci_wslv_respF_x_wire$whas) && - wci_wslv_respF_c_r != 2'd0 && + wci_wslv_respF_x_wire$whas && wci_wslv_respF_cntr_r != 2'd0 && wci_wslv_respF_enqueueing$whas ; // rule RL_wsiM_reqFifo_deq assign WILL_FIRE_RL_wsiM_reqFifo_deq = - wsiM_reqFifo_c_r != 2'd0 && !wsiM_sThreadBusy_d ; + wsiM_reqFifo_cntr_r != 2'd0 && !wsiM_sThreadBusy_d ; // rule RL_wsiM_reqFifo_incCtr assign WILL_FIRE_RL_wsiM_reqFifo_incCtr = - ((wsiM_reqFifo_c_r == 2'd0) ? - MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 : - wsiM_reqFifo_c_r != 2'd1 || - MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3) && + MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 && MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 && !WILL_FIRE_RL_wsiM_reqFifo_deq ; @@ -715,10 +711,7 @@ module mkBiasWorker16B(wciS0_Clk, // rule RL_wsiM_reqFifo_both assign WILL_FIRE_RL_wsiM_reqFifo_both = - ((wsiM_reqFifo_c_r == 2'd1) ? - MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 : - wsiM_reqFifo_c_r != 2'd2 || - MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3) && + MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 && WILL_FIRE_RL_wsiM_reqFifo_deq && MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 ; @@ -743,8 +736,6 @@ module mkBiasWorker16B(wciS0_Clk, assign MUX_controlReg$write_1__SEL_1 = WILL_FIRE_RL_wci_cfwr && wci_wslv_reqF$D_OUT[39:32] == 8'h04 ; assign MUX_wci_wslv_illegalEdge$write_1__SEL_1 = - WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge ; - assign MUX_wci_wslv_illegalEdge$write_1__SEL_2 = WILL_FIRE_RL_wci_wslv_ctl_op_start && (wci_wslv_reqF$D_OUT[36:34] == 3'd0 && wci_wslv_cState != 3'd0 || wci_wslv_reqF$D_OUT[36:34] == 3'd1 && wci_wslv_cState != 3'd1 && @@ -757,27 +748,35 @@ module mkBiasWorker16B(wciS0_Clk, wci_wslv_reqF$D_OUT[36:34] == 3'd5 || wci_wslv_reqF$D_OUT[36:34] == 3'd6 || wci_wslv_reqF$D_OUT[36:34] == 3'd7) ; + assign MUX_wci_wslv_respF_q_0$write_1__SEL_1 = + WILL_FIRE_RL_wci_wslv_respF_both && _dfoo3 ; assign MUX_wci_wslv_respF_q_0$write_1__SEL_2 = WILL_FIRE_RL_wci_wslv_respF_incCtr && - wci_wslv_respF_c_r == 2'd0 ; + wci_wslv_respF_cntr_r == 2'd0 ; + assign MUX_wci_wslv_respF_q_1$write_1__SEL_1 = + WILL_FIRE_RL_wci_wslv_respF_both && _dfoo1 ; assign MUX_wci_wslv_respF_q_1$write_1__SEL_2 = WILL_FIRE_RL_wci_wslv_respF_incCtr && - wci_wslv_respF_c_r == 2'd1 ; + wci_wslv_respF_cntr_r == 2'd1 ; + assign MUX_wsiM_reqFifo_q_0$write_1__SEL_1 = + WILL_FIRE_RL_wsiM_reqFifo_both && _dfoo7 ; assign MUX_wsiM_reqFifo_q_0$write_1__SEL_2 = - WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_c_r == 2'd0 ; + WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_cntr_r == 2'd0 ; + assign MUX_wsiM_reqFifo_q_1$write_1__SEL_1 = + WILL_FIRE_RL_wsiM_reqFifo_both && _dfoo5 ; assign MUX_wsiM_reqFifo_q_1$write_1__SEL_2 = - WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_c_r == 2'd1 ; + WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_cntr_r == 2'd1 ; assign MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 = - wsiM_reqFifo_c_r != 2'd2 && wsiS_reqFifo$EMPTY_N && + wsiM_reqFifo_cntr_r != 2'd2 && wsiS_reqFifo$EMPTY_N && wci_wslv_cState == 3'd2 ; - assign MUX_wci_wslv_illegalEdge$write_1__VAL_2 = + assign MUX_wci_wslv_illegalEdge$write_1__VAL_1 = wci_wslv_reqF$D_OUT[36:34] != 3'd4 && wci_wslv_reqF$D_OUT[36:34] != 3'd5 && wci_wslv_reqF$D_OUT[36:34] != 3'd6 ; - assign MUX_wci_wslv_respF_c_r$write_1__VAL_1 = wci_wslv_respF_c_r + 2'd1 ; - assign MUX_wci_wslv_respF_c_r$write_1__VAL_2 = wci_wslv_respF_c_r - 2'd1 ; + assign MUX_wci_wslv_respF_cntr_r$write_1__VAL_2 = + wci_wslv_respF_cntr_r + 2'd1 ; assign MUX_wci_wslv_respF_q_0$write_1__VAL_1 = - (wci_wslv_respF_c_r == 2'd1) ? + (wci_wslv_respF_cntr_r == 2'd1) ? MUX_wci_wslv_respF_q_0$write_1__VAL_2 : wci_wslv_respF_q_1 ; always@(WILL_FIRE_RL_wci_wslv_ctl_op_complete or @@ -799,25 +798,25 @@ module mkBiasWorker16B(wciS0_Clk, endcase end assign MUX_wci_wslv_respF_q_1$write_1__VAL_1 = - (wci_wslv_respF_c_r == 2'd2) ? + (wci_wslv_respF_cntr_r == 2'd2) ? MUX_wci_wslv_respF_q_0$write_1__VAL_2 : 34'h0AAAAAAAA ; assign MUX_wci_wslv_respF_x_wire$wset_1__VAL_1 = wci_wslv_illegalEdge ? 34'h3C0DE4202 : 34'h1C0DE4201 ; assign MUX_wci_wslv_respF_x_wire$wset_1__VAL_2 = - { 2'd1, _theResult____h11640 } ; - assign MUX_wsiM_reqFifo_c_r$write_1__VAL_1 = wsiM_reqFifo_c_r + 2'd1 ; - assign MUX_wsiM_reqFifo_c_r$write_1__VAL_2 = wsiM_reqFifo_c_r - 2'd1 ; + { 2'd1, _theResult____h11369 } ; + assign MUX_wsiM_reqFifo_cntr_r$write_1__VAL_1 = wsiM_reqFifo_cntr_r - 2'd1 ; + assign MUX_wsiM_reqFifo_cntr_r$write_1__VAL_2 = wsiM_reqFifo_cntr_r + 2'd1 ; assign MUX_wsiM_reqFifo_q_0$write_1__VAL_1 = - (wsiM_reqFifo_c_r == 2'd1) ? + (wsiM_reqFifo_cntr_r == 2'd1) ? MUX_wsiM_reqFifo_q_0$write_1__VAL_2 : wsiM_reqFifo_q_1 ; assign MUX_wsiM_reqFifo_q_0$write_1__VAL_2 = { wsiS_reqFifo$D_OUT[168:152], - x_data__h10386, + x_data__h10099, wsiS_reqFifo$D_OUT[23:0] } ; assign MUX_wsiM_reqFifo_q_1$write_1__VAL_1 = - (wsiM_reqFifo_c_r == 2'd2) ? + (wsiM_reqFifo_cntr_r == 2'd2) ? MUX_wsiM_reqFifo_q_0$write_1__VAL_2 : 169'h00000AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA00 ; @@ -892,7 +891,7 @@ module mkBiasWorker16B(wciS0_Clk, assign wci_wslv_respF_enqueueing$whas = WILL_FIRE_RL_wci_cfrd || WILL_FIRE_RL_wci_cfwr || WILL_FIRE_RL_wci_wslv_ctl_op_complete ; - assign wci_wslv_respF_dequeueing$whas = wci_wslv_respF_c_r != 2'd0 ; + assign wci_wslv_respF_dequeueing$whas = wci_wslv_respF_cntr_r != 2'd0 ; assign wci_wslv_sThreadBusy_pw$whas = 1'b0 ; assign wci_wslv_wci_cfwr_pw$whas = wci_wslv_reqF$EMPTY_N && wci_wslv_reqF$D_OUT[68] && @@ -962,11 +961,11 @@ module mkBiasWorker16B(wciS0_Clk, // register wci_wslv_illegalEdge assign wci_wslv_illegalEdge$D_IN = - !MUX_wci_wslv_illegalEdge$write_1__SEL_1 && - MUX_wci_wslv_illegalEdge$write_1__VAL_2 ; + MUX_wci_wslv_illegalEdge$write_1__SEL_1 && + MUX_wci_wslv_illegalEdge$write_1__VAL_1 ; assign wci_wslv_illegalEdge$EN = - WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge || - MUX_wci_wslv_illegalEdge$write_1__SEL_2 ; + MUX_wci_wslv_illegalEdge$write_1__SEL_1 || + WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge ; // register wci_wslv_isReset_isInReset assign wci_wslv_isReset_isInReset$D_IN = 1'd0 ; @@ -1001,24 +1000,24 @@ module mkBiasWorker16B(wciS0_Clk, (wci_wslv_wciReq$wget[71:69] != 3'd0) != wci_wslv_reqF_r_deq$whas ; - // register wci_wslv_respF_c_r - assign wci_wslv_respF_c_r$D_IN = - WILL_FIRE_RL_wci_wslv_respF_incCtr ? - MUX_wci_wslv_respF_c_r$write_1__VAL_1 : - MUX_wci_wslv_respF_c_r$write_1__VAL_2 ; - assign wci_wslv_respF_c_r$EN = - WILL_FIRE_RL_wci_wslv_respF_incCtr || - WILL_FIRE_RL_wci_wslv_respF_decCtr ; + // register wci_wslv_respF_cntr_r + assign wci_wslv_respF_cntr_r$D_IN = + WILL_FIRE_RL_wci_wslv_respF_decCtr ? + wci_wslv_respF_cntr_r_8_MINUS_1___d27 : + MUX_wci_wslv_respF_cntr_r$write_1__VAL_2 ; + assign wci_wslv_respF_cntr_r$EN = + WILL_FIRE_RL_wci_wslv_respF_decCtr || + WILL_FIRE_RL_wci_wslv_respF_incCtr ; // register wci_wslv_respF_q_0 - always@(WILL_FIRE_RL_wci_wslv_respF_both or + always@(MUX_wci_wslv_respF_q_0$write_1__SEL_1 or MUX_wci_wslv_respF_q_0$write_1__VAL_1 or MUX_wci_wslv_respF_q_0$write_1__SEL_2 or MUX_wci_wslv_respF_q_0$write_1__VAL_2 or WILL_FIRE_RL_wci_wslv_respF_decCtr or wci_wslv_respF_q_1) begin case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_wci_wslv_respF_both: + MUX_wci_wslv_respF_q_0$write_1__SEL_1: wci_wslv_respF_q_0$D_IN = MUX_wci_wslv_respF_q_0$write_1__VAL_1; MUX_wci_wslv_respF_q_0$write_1__SEL_2: wci_wslv_respF_q_0$D_IN = MUX_wci_wslv_respF_q_0$write_1__VAL_2; @@ -1029,20 +1028,20 @@ module mkBiasWorker16B(wciS0_Clk, endcase end assign wci_wslv_respF_q_0$EN = - WILL_FIRE_RL_wci_wslv_respF_both || + WILL_FIRE_RL_wci_wslv_respF_both && _dfoo3 || WILL_FIRE_RL_wci_wslv_respF_incCtr && - wci_wslv_respF_c_r == 2'd0 || + wci_wslv_respF_cntr_r == 2'd0 || WILL_FIRE_RL_wci_wslv_respF_decCtr ; // register wci_wslv_respF_q_1 - always@(WILL_FIRE_RL_wci_wslv_respF_both or + always@(MUX_wci_wslv_respF_q_1$write_1__SEL_1 or MUX_wci_wslv_respF_q_1$write_1__VAL_1 or MUX_wci_wslv_respF_q_1$write_1__SEL_2 or MUX_wci_wslv_respF_q_0$write_1__VAL_2 or WILL_FIRE_RL_wci_wslv_respF_decCtr) begin case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_wci_wslv_respF_both: + MUX_wci_wslv_respF_q_1$write_1__SEL_1: wci_wslv_respF_q_1$D_IN = MUX_wci_wslv_respF_q_1$write_1__VAL_1; MUX_wci_wslv_respF_q_1$write_1__SEL_2: wci_wslv_respF_q_1$D_IN = MUX_wci_wslv_respF_q_0$write_1__VAL_2; @@ -1053,9 +1052,9 @@ module mkBiasWorker16B(wciS0_Clk, endcase end assign wci_wslv_respF_q_1$EN = - WILL_FIRE_RL_wci_wslv_respF_both || + WILL_FIRE_RL_wci_wslv_respF_both && _dfoo1 || WILL_FIRE_RL_wci_wslv_respF_incCtr && - wci_wslv_respF_c_r == 2'd1 || + wci_wslv_respF_cntr_r == 2'd1 || WILL_FIRE_RL_wci_wslv_respF_decCtr ; // register wci_wslv_sFlagReg @@ -1110,24 +1109,24 @@ module mkBiasWorker16B(wciS0_Clk, assign wsiM_peerIsReady$D_IN = wsiM0_SReset_n ; assign wsiM_peerIsReady$EN = 1'd1 ; - // register wsiM_reqFifo_c_r - assign wsiM_reqFifo_c_r$D_IN = - WILL_FIRE_RL_wsiM_reqFifo_incCtr ? - MUX_wsiM_reqFifo_c_r$write_1__VAL_1 : - MUX_wsiM_reqFifo_c_r$write_1__VAL_2 ; - assign wsiM_reqFifo_c_r$EN = - WILL_FIRE_RL_wsiM_reqFifo_incCtr || - WILL_FIRE_RL_wsiM_reqFifo_decCtr ; + // register wsiM_reqFifo_cntr_r + assign wsiM_reqFifo_cntr_r$D_IN = + WILL_FIRE_RL_wsiM_reqFifo_decCtr ? + MUX_wsiM_reqFifo_cntr_r$write_1__VAL_1 : + MUX_wsiM_reqFifo_cntr_r$write_1__VAL_2 ; + assign wsiM_reqFifo_cntr_r$EN = + WILL_FIRE_RL_wsiM_reqFifo_decCtr || + WILL_FIRE_RL_wsiM_reqFifo_incCtr ; // register wsiM_reqFifo_q_0 - always@(WILL_FIRE_RL_wsiM_reqFifo_both or + always@(MUX_wsiM_reqFifo_q_0$write_1__SEL_1 or MUX_wsiM_reqFifo_q_0$write_1__VAL_1 or MUX_wsiM_reqFifo_q_0$write_1__SEL_2 or MUX_wsiM_reqFifo_q_0$write_1__VAL_2 or WILL_FIRE_RL_wsiM_reqFifo_decCtr or wsiM_reqFifo_q_1) begin case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_wsiM_reqFifo_both: + MUX_wsiM_reqFifo_q_0$write_1__SEL_1: wsiM_reqFifo_q_0$D_IN = MUX_wsiM_reqFifo_q_0$write_1__VAL_1; MUX_wsiM_reqFifo_q_0$write_1__SEL_2: wsiM_reqFifo_q_0$D_IN = MUX_wsiM_reqFifo_q_0$write_1__VAL_2; @@ -1138,19 +1137,20 @@ module mkBiasWorker16B(wciS0_Clk, endcase end assign wsiM_reqFifo_q_0$EN = - WILL_FIRE_RL_wsiM_reqFifo_both || - WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_c_r == 2'd0 || + WILL_FIRE_RL_wsiM_reqFifo_both && _dfoo7 || + WILL_FIRE_RL_wsiM_reqFifo_incCtr && + wsiM_reqFifo_cntr_r == 2'd0 || WILL_FIRE_RL_wsiM_reqFifo_decCtr ; // register wsiM_reqFifo_q_1 - always@(WILL_FIRE_RL_wsiM_reqFifo_both or + always@(MUX_wsiM_reqFifo_q_1$write_1__SEL_1 or MUX_wsiM_reqFifo_q_1$write_1__VAL_1 or MUX_wsiM_reqFifo_q_1$write_1__SEL_2 or MUX_wsiM_reqFifo_q_0$write_1__VAL_2 or WILL_FIRE_RL_wsiM_reqFifo_decCtr) begin case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_wsiM_reqFifo_both: + MUX_wsiM_reqFifo_q_1$write_1__SEL_1: wsiM_reqFifo_q_1$D_IN = MUX_wsiM_reqFifo_q_1$write_1__VAL_1; MUX_wsiM_reqFifo_q_1$write_1__SEL_2: wsiM_reqFifo_q_1$D_IN = MUX_wsiM_reqFifo_q_0$write_1__VAL_2; @@ -1162,8 +1162,9 @@ module mkBiasWorker16B(wciS0_Clk, endcase end assign wsiM_reqFifo_q_1$EN = - WILL_FIRE_RL_wsiM_reqFifo_both || - WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_c_r == 2'd1 || + WILL_FIRE_RL_wsiM_reqFifo_both && _dfoo5 || + WILL_FIRE_RL_wsiM_reqFifo_incCtr && + wsiM_reqFifo_cntr_r == 2'd1 || WILL_FIRE_RL_wsiM_reqFifo_decCtr ; // register wsiM_sThreadBusy_d @@ -1249,7 +1250,7 @@ module mkBiasWorker16B(wciS0_Clk, // register wsiS_reqFifo_levelsValid assign wsiS_reqFifo_levelsValid$D_IN = WILL_FIRE_RL_wsiS_reqFifo_reset ; assign wsiS_reqFifo_levelsValid$EN = - wsiM_reqFifo_c_r != 2'd2 && wsiS_reqFifo$EMPTY_N && + wsiM_reqFifo_cntr_r != 2'd2 && wsiS_reqFifo$EMPTY_N && wci_wslv_cState == 3'd2 || WILL_FIRE_RL_wsiS_reqFifo_enq || WILL_FIRE_RL_wsiS_reqFifo_reset ; @@ -1294,15 +1295,29 @@ module mkBiasWorker16B(wciS0_Clk, assign wsiS_reqFifo$CLR = 1'b0 ; // remaining internal signals - assign rdat__h11730 = hasDebugLogic ? { 16'd0, x__h11734 } : 32'd0 ; - assign rdat__h11830 = hasDebugLogic ? wsiS_extStatusW$wget[95:64] : 32'd0 ; - assign rdat__h11844 = hasDebugLogic ? wsiS_extStatusW$wget[63:32] : 32'd0 ; - assign rdat__h11852 = hasDebugLogic ? wsiS_extStatusW$wget[31:0] : 32'd0 ; - assign rdat__h11858 = hasDebugLogic ? wsiM_extStatusW$wget[95:64] : 32'd0 ; - assign rdat__h11872 = hasDebugLogic ? wsiM_extStatusW$wget[63:32] : 32'd0 ; - assign rdat__h11880 = hasDebugLogic ? wsiM_extStatusW$wget[31:0] : 32'd0 ; - assign x__h11734 = { wsiS_statusR, wsiM_statusR } ; - assign x_data__h10386 = + assign _dfoo1 = + wci_wslv_respF_cntr_r != 2'd2 || + wci_wslv_respF_cntr_r_8_MINUS_1___d27 == 2'd1 ; + assign _dfoo3 = + wci_wslv_respF_cntr_r != 2'd1 || + wci_wslv_respF_cntr_r_8_MINUS_1___d27 == 2'd0 ; + assign _dfoo5 = + wsiM_reqFifo_cntr_r != 2'd2 || + MUX_wsiM_reqFifo_cntr_r$write_1__VAL_1 == 2'd1 ; + assign _dfoo7 = + wsiM_reqFifo_cntr_r != 2'd1 || + MUX_wsiM_reqFifo_cntr_r$write_1__VAL_1 == 2'd0 ; + assign rdat__h11459 = hasDebugLogic ? { 16'd0, x__h11463 } : 32'd0 ; + assign rdat__h11559 = hasDebugLogic ? wsiS_extStatusW$wget[95:64] : 32'd0 ; + assign rdat__h11573 = hasDebugLogic ? wsiS_extStatusW$wget[63:32] : 32'd0 ; + assign rdat__h11581 = hasDebugLogic ? wsiS_extStatusW$wget[31:0] : 32'd0 ; + assign rdat__h11587 = hasDebugLogic ? wsiM_extStatusW$wget[95:64] : 32'd0 ; + assign rdat__h11601 = hasDebugLogic ? wsiM_extStatusW$wget[63:32] : 32'd0 ; + assign rdat__h11609 = hasDebugLogic ? wsiM_extStatusW$wget[31:0] : 32'd0 ; + assign wci_wslv_respF_cntr_r_8_MINUS_1___d27 = + wci_wslv_respF_cntr_r - 2'd1 ; + assign x__h11463 = { wsiS_statusR, wsiM_statusR } ; + assign x_data__h10099 = { wsiS_reqFifo$D_OUT[151:120] + biasValue, wsiS_reqFifo$D_OUT[119:88] + biasValue, wsiS_reqFifo$D_OUT[87:56] + biasValue, @@ -1310,22 +1325,22 @@ module mkBiasWorker16B(wciS0_Clk, always@(wci_wslv_reqF$D_OUT or biasValue or controlReg or - rdat__h11730 or - rdat__h11830 or - rdat__h11844 or - rdat__h11852 or rdat__h11858 or rdat__h11872 or rdat__h11880) + rdat__h11459 or + rdat__h11559 or + rdat__h11573 or + rdat__h11581 or rdat__h11587 or rdat__h11601 or rdat__h11609) begin case (wci_wslv_reqF$D_OUT[39:32]) - 8'h0: _theResult____h11640 = biasValue; - 8'h04: _theResult____h11640 = controlReg; - 8'h20: _theResult____h11640 = rdat__h11730; - 8'h24: _theResult____h11640 = rdat__h11830; - 8'h28: _theResult____h11640 = rdat__h11844; - 8'h2C: _theResult____h11640 = rdat__h11852; - 8'h30: _theResult____h11640 = rdat__h11858; - 8'h34: _theResult____h11640 = rdat__h11872; - 8'h38: _theResult____h11640 = rdat__h11880; - default: _theResult____h11640 = 32'd0; + 8'h0: _theResult____h11369 = biasValue; + 8'h04: _theResult____h11369 = controlReg; + 8'h20: _theResult____h11369 = rdat__h11459; + 8'h24: _theResult____h11369 = rdat__h11559; + 8'h28: _theResult____h11369 = rdat__h11573; + 8'h2C: _theResult____h11369 = rdat__h11581; + 8'h30: _theResult____h11369 = rdat__h11587; + 8'h34: _theResult____h11369 = rdat__h11601; + 8'h38: _theResult____h11369 = rdat__h11609; + default: _theResult____h11369 = 32'd0; endcase end @@ -1342,7 +1357,7 @@ module mkBiasWorker16B(wciS0_Clk, wci_wslv_illegalEdge <= `BSV_ASSIGNMENT_DELAY 1'd0; wci_wslv_nState <= `BSV_ASSIGNMENT_DELAY 3'd0; wci_wslv_reqF_countReg <= `BSV_ASSIGNMENT_DELAY 2'd0; - wci_wslv_respF_c_r <= `BSV_ASSIGNMENT_DELAY 2'd0; + wci_wslv_respF_cntr_r <= `BSV_ASSIGNMENT_DELAY 2'd0; wci_wslv_respF_q_0 <= `BSV_ASSIGNMENT_DELAY 34'h0AAAAAAAA; wci_wslv_respF_q_1 <= `BSV_ASSIGNMENT_DELAY 34'h0AAAAAAAA; wci_wslv_sFlagReg <= `BSV_ASSIGNMENT_DELAY 1'd0; @@ -1353,7 +1368,7 @@ module mkBiasWorker16B(wciS0_Clk, wsiM_operateD <= `BSV_ASSIGNMENT_DELAY 1'd0; wsiM_pMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0; wsiM_peerIsReady <= `BSV_ASSIGNMENT_DELAY 1'd0; - wsiM_reqFifo_c_r <= `BSV_ASSIGNMENT_DELAY 2'd0; + wsiM_reqFifo_cntr_r <= `BSV_ASSIGNMENT_DELAY 2'd0; wsiM_reqFifo_q_0 <= `BSV_ASSIGNMENT_DELAY 169'h00000AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA00; wsiM_reqFifo_q_1 <= `BSV_ASSIGNMENT_DELAY @@ -1392,8 +1407,9 @@ module mkBiasWorker16B(wciS0_Clk, if (wci_wslv_reqF_countReg$EN) wci_wslv_reqF_countReg <= `BSV_ASSIGNMENT_DELAY wci_wslv_reqF_countReg$D_IN; - if (wci_wslv_respF_c_r$EN) - wci_wslv_respF_c_r <= `BSV_ASSIGNMENT_DELAY wci_wslv_respF_c_r$D_IN; + if (wci_wslv_respF_cntr_r$EN) + wci_wslv_respF_cntr_r <= `BSV_ASSIGNMENT_DELAY + wci_wslv_respF_cntr_r$D_IN; if (wci_wslv_respF_q_0$EN) wci_wslv_respF_q_0 <= `BSV_ASSIGNMENT_DELAY wci_wslv_respF_q_0$D_IN; if (wci_wslv_respF_q_1$EN) @@ -1415,8 +1431,9 @@ module mkBiasWorker16B(wciS0_Clk, wsiM_pMesgCount <= `BSV_ASSIGNMENT_DELAY wsiM_pMesgCount$D_IN; if (wsiM_peerIsReady$EN) wsiM_peerIsReady <= `BSV_ASSIGNMENT_DELAY wsiM_peerIsReady$D_IN; - if (wsiM_reqFifo_c_r$EN) - wsiM_reqFifo_c_r <= `BSV_ASSIGNMENT_DELAY wsiM_reqFifo_c_r$D_IN; + if (wsiM_reqFifo_cntr_r$EN) + wsiM_reqFifo_cntr_r <= `BSV_ASSIGNMENT_DELAY + wsiM_reqFifo_cntr_r$D_IN; if (wsiM_reqFifo_q_0$EN) wsiM_reqFifo_q_0 <= `BSV_ASSIGNMENT_DELAY wsiM_reqFifo_q_0$D_IN; if (wsiM_reqFifo_q_1$EN) @@ -1497,7 +1514,7 @@ module mkBiasWorker16B(wciS0_Clk, wci_wslv_isReset_isInReset = 1'h0; wci_wslv_nState = 3'h2; wci_wslv_reqF_countReg = 2'h2; - wci_wslv_respF_c_r = 2'h2; + wci_wslv_respF_cntr_r = 2'h2; wci_wslv_respF_q_0 = 34'h2AAAAAAAA; wci_wslv_respF_q_1 = 34'h2AAAAAAAA; wci_wslv_sFlagReg = 1'h0; @@ -1509,7 +1526,7 @@ module mkBiasWorker16B(wciS0_Clk, wsiM_operateD = 1'h0; wsiM_pMesgCount = 32'hAAAAAAAA; wsiM_peerIsReady = 1'h0; - wsiM_reqFifo_c_r = 2'h2; + wsiM_reqFifo_cntr_r = 2'h2; wsiM_reqFifo_q_0 = 169'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; wsiM_reqFifo_q_1 = 169'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; wsiM_sThreadBusy_d = 1'h0; @@ -1543,13 +1560,13 @@ module mkBiasWorker16B(wciS0_Clk, if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_start) begin - v__h3706 = $time; + v__h3574 = $time; #0; end if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_start) $display("[%0d]: %m: WCI ControlOp: Starting-transition edge:%x from:%x", - v__h3706, + v__h3574, wci_wslv_reqF$D_OUT[36:34], wci_wslv_cState); if (wciS0_MReset_n != `BSV_RESET_VALUE) @@ -1564,54 +1581,54 @@ module mkBiasWorker16B(wciS0_Clk, if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfwr) begin - v__h11501 = $time; + v__h11230 = $time; #0; end if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfwr) $display("[%0d]: %m: WCI CONFIG WRITE Addr:%0x BE:%0x Data:%0x", - v__h11501, + v__h11230, wci_wslv_reqF$D_OUT[63:32], wci_wslv_reqF$D_OUT[67:64], wci_wslv_reqF$D_OUT[31:0]); if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge) begin - v__h4025 = $time; + v__h3893 = $time; #0; end if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge) $display("[%0d]: %m: WCI ControlOp: ILLEGAL-EDGE Completed-transition edge:%x from:%x", - v__h4025, + v__h3893, wci_wslv_cEdge, wci_wslv_cState); if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && !wci_wslv_illegalEdge) begin - v__h3881 = $time; + v__h3749 = $time; #0; end if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && !wci_wslv_illegalEdge) $display("[%0d]: %m: WCI ControlOp: Completed-transition edge:%x from:%x to:%x", - v__h3881, + v__h3749, wci_wslv_cEdge, wci_wslv_cState, wci_wslv_nState); if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfrd) begin - v__h11656 = $time; + v__h11385 = $time; #0; end if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfrd) $display("[%0d]: %m: WCI CONFIG READ Addr:%0x BE:%0x Data:%0x", - v__h11656, + v__h11385, wci_wslv_reqF$D_OUT[63:32], wci_wslv_reqF$D_OUT[67:64], - _theResult____h11640); + _theResult____h11369); if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_OrE) $display("Error: \"bsv/wrk/BiasWorker.bsv\", line 67, column 28: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n"); diff --git a/rtl/mkBiasWorker32B.v b/rtl/mkBiasWorker32B.v index 81113622..600d6541 100644 --- a/rtl/mkBiasWorker32B.v +++ b/rtl/mkBiasWorker32B.v @@ -1,7 +1,7 @@ // -// Generated by Bluespec Compiler, version 2012.09.beta1 (build 29570, 2012-09.11) +// Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Tue Dec 11 16:21:00 EST 2012 +// On Fri Jun 21 16:57:48 EDT 2013 // // // Ports: @@ -343,10 +343,10 @@ module mkBiasWorker32B(wciS0_Clk, wire [1 : 0] wci_wslv_reqF_countReg$D_IN; wire wci_wslv_reqF_countReg$EN; - // register wci_wslv_respF_c_r - reg [1 : 0] wci_wslv_respF_c_r; - wire [1 : 0] wci_wslv_respF_c_r$D_IN; - wire wci_wslv_respF_c_r$EN; + // register wci_wslv_respF_cntr_r + reg [1 : 0] wci_wslv_respF_cntr_r; + wire [1 : 0] wci_wslv_respF_cntr_r$D_IN; + wire wci_wslv_respF_cntr_r$EN; // register wci_wslv_respF_q_0 reg [33 : 0] wci_wslv_respF_q_0; @@ -397,10 +397,10 @@ module mkBiasWorker32B(wciS0_Clk, reg wsiM_peerIsReady; wire wsiM_peerIsReady$D_IN, wsiM_peerIsReady$EN; - // register wsiM_reqFifo_c_r - reg [1 : 0] wsiM_reqFifo_c_r; - wire [1 : 0] wsiM_reqFifo_c_r$D_IN; - wire wsiM_reqFifo_c_r$EN; + // register wsiM_reqFifo_cntr_r + reg [1 : 0] wsiM_reqFifo_cntr_r; + wire [1 : 0] wsiM_reqFifo_cntr_r$D_IN; + wire wsiM_reqFifo_cntr_r$EN; // register wsiM_reqFifo_q_0 reg [312 : 0] wsiM_reqFifo_q_0; @@ -535,34 +535,38 @@ module mkBiasWorker32B(wciS0_Clk, MUX_wci_wslv_respF_q_1$write_1__VAL_1, MUX_wci_wslv_respF_x_wire$wset_1__VAL_1, MUX_wci_wslv_respF_x_wire$wset_1__VAL_2; - wire [1 : 0] MUX_wci_wslv_respF_c_r$write_1__VAL_1, - MUX_wci_wslv_respF_c_r$write_1__VAL_2, - MUX_wsiM_reqFifo_c_r$write_1__VAL_1, - MUX_wsiM_reqFifo_c_r$write_1__VAL_2; + wire [1 : 0] MUX_wci_wslv_respF_cntr_r$write_1__VAL_2, + MUX_wsiM_reqFifo_cntr_r$write_1__VAL_1, + MUX_wsiM_reqFifo_cntr_r$write_1__VAL_2; wire MUX_biasValue$write_1__SEL_1, MUX_biasValue$write_1__SEL_2, MUX_controlReg$write_1__SEL_1, MUX_wci_wslv_illegalEdge$write_1__SEL_1, - MUX_wci_wslv_illegalEdge$write_1__SEL_2, - MUX_wci_wslv_illegalEdge$write_1__VAL_2, + MUX_wci_wslv_illegalEdge$write_1__VAL_1, + MUX_wci_wslv_respF_q_0$write_1__SEL_1, MUX_wci_wslv_respF_q_0$write_1__SEL_2, + MUX_wci_wslv_respF_q_1$write_1__SEL_1, MUX_wci_wslv_respF_q_1$write_1__SEL_2, + MUX_wsiM_reqFifo_q_0$write_1__SEL_1, MUX_wsiM_reqFifo_q_0$write_1__SEL_2, + MUX_wsiM_reqFifo_q_1$write_1__SEL_1, MUX_wsiM_reqFifo_q_1$write_1__SEL_2, MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3; // remaining internal signals - reg [63 : 0] v__h12281, v__h12436, v__h3706, v__h3881, v__h4025; - reg [31 : 0] _theResult____h12420; - wire [255 : 0] x_data__h10386; - wire [31 : 0] rdat__h12510, - rdat__h12610, - rdat__h12624, - rdat__h12632, - rdat__h12638, - rdat__h12652, - rdat__h12660; - wire [15 : 0] x__h12514; + reg [63 : 0] v__h12026, v__h12181, v__h3574, v__h3749, v__h3893; + reg [31 : 0] _theResult____h12165; + wire [255 : 0] x_data__h10099; + wire [31 : 0] rdat__h12255, + rdat__h12355, + rdat__h12369, + rdat__h12377, + rdat__h12383, + rdat__h12397, + rdat__h12405; + wire [15 : 0] x__h12259; + wire [1 : 0] wci_wslv_respF_cntr_r_8_MINUS_1___d27; + wire _dfoo1, _dfoo3, _dfoo5, _dfoo7; // value method wciS0_sResp assign wciS0_SResp = wci_wslv_respF_q_0[33:32] ; @@ -658,53 +662,45 @@ module mkBiasWorker32B(wciS0_Clk, // rule RL_wci_cfwr assign WILL_FIRE_RL_wci_cfwr = - wci_wslv_respF_c_r != 2'd2 && wci_wslv_reqF$EMPTY_N && + wci_wslv_respF_cntr_r != 2'd2 && wci_wslv_reqF$EMPTY_N && wci_wslv_wci_cfwr_pw$whas && !WILL_FIRE_RL_wci_wslv_ctl_op_start && !WILL_FIRE_RL_wci_wslv_ctl_op_complete ; // rule RL_wci_wslv_ctl_op_complete assign WILL_FIRE_RL_wci_wslv_ctl_op_complete = - wci_wslv_respF_c_r != 2'd2 && wci_wslv_ctlOpActive && + wci_wslv_respF_cntr_r != 2'd2 && wci_wslv_ctlOpActive && wci_wslv_ctlAckReg ; // rule RL_wci_cfrd assign WILL_FIRE_RL_wci_cfrd = - wci_wslv_respF_c_r != 2'd2 && wci_wslv_reqF$EMPTY_N && + wci_wslv_respF_cntr_r != 2'd2 && wci_wslv_reqF$EMPTY_N && wci_wslv_wci_cfrd_pw$whas && !WILL_FIRE_RL_wci_wslv_ctl_op_start && !WILL_FIRE_RL_wci_wslv_ctl_op_complete ; // rule RL_wci_wslv_respF_incCtr assign WILL_FIRE_RL_wci_wslv_respF_incCtr = - ((wci_wslv_respF_c_r == 2'd0) ? - wci_wslv_respF_x_wire$whas : - wci_wslv_respF_c_r != 2'd1 || wci_wslv_respF_x_wire$whas) && - wci_wslv_respF_enqueueing$whas && - !(wci_wslv_respF_c_r != 2'd0) ; + wci_wslv_respF_x_wire$whas && wci_wslv_respF_enqueueing$whas && + !(wci_wslv_respF_cntr_r != 2'd0) ; // rule RL_wci_wslv_respF_decCtr assign WILL_FIRE_RL_wci_wslv_respF_decCtr = - wci_wslv_respF_c_r != 2'd0 && !wci_wslv_respF_enqueueing$whas ; + wci_wslv_respF_cntr_r != 2'd0 && + !wci_wslv_respF_enqueueing$whas ; // rule RL_wci_wslv_respF_both assign WILL_FIRE_RL_wci_wslv_respF_both = - ((wci_wslv_respF_c_r == 2'd1) ? - wci_wslv_respF_x_wire$whas : - wci_wslv_respF_c_r != 2'd2 || wci_wslv_respF_x_wire$whas) && - wci_wslv_respF_c_r != 2'd0 && + wci_wslv_respF_x_wire$whas && wci_wslv_respF_cntr_r != 2'd0 && wci_wslv_respF_enqueueing$whas ; // rule RL_wsiM_reqFifo_deq assign WILL_FIRE_RL_wsiM_reqFifo_deq = - wsiM_reqFifo_c_r != 2'd0 && !wsiM_sThreadBusy_d ; + wsiM_reqFifo_cntr_r != 2'd0 && !wsiM_sThreadBusy_d ; // rule RL_wsiM_reqFifo_incCtr assign WILL_FIRE_RL_wsiM_reqFifo_incCtr = - ((wsiM_reqFifo_c_r == 2'd0) ? - MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 : - wsiM_reqFifo_c_r != 2'd1 || - MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3) && + MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 && MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 && !WILL_FIRE_RL_wsiM_reqFifo_deq ; @@ -715,10 +711,7 @@ module mkBiasWorker32B(wciS0_Clk, // rule RL_wsiM_reqFifo_both assign WILL_FIRE_RL_wsiM_reqFifo_both = - ((wsiM_reqFifo_c_r == 2'd1) ? - MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 : - wsiM_reqFifo_c_r != 2'd2 || - MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3) && + MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 && WILL_FIRE_RL_wsiM_reqFifo_deq && MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 ; @@ -743,8 +736,6 @@ module mkBiasWorker32B(wciS0_Clk, assign MUX_controlReg$write_1__SEL_1 = WILL_FIRE_RL_wci_cfwr && wci_wslv_reqF$D_OUT[39:32] == 8'h04 ; assign MUX_wci_wslv_illegalEdge$write_1__SEL_1 = - WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge ; - assign MUX_wci_wslv_illegalEdge$write_1__SEL_2 = WILL_FIRE_RL_wci_wslv_ctl_op_start && (wci_wslv_reqF$D_OUT[36:34] == 3'd0 && wci_wslv_cState != 3'd0 || wci_wslv_reqF$D_OUT[36:34] == 3'd1 && wci_wslv_cState != 3'd1 && @@ -757,27 +748,35 @@ module mkBiasWorker32B(wciS0_Clk, wci_wslv_reqF$D_OUT[36:34] == 3'd5 || wci_wslv_reqF$D_OUT[36:34] == 3'd6 || wci_wslv_reqF$D_OUT[36:34] == 3'd7) ; + assign MUX_wci_wslv_respF_q_0$write_1__SEL_1 = + WILL_FIRE_RL_wci_wslv_respF_both && _dfoo3 ; assign MUX_wci_wslv_respF_q_0$write_1__SEL_2 = WILL_FIRE_RL_wci_wslv_respF_incCtr && - wci_wslv_respF_c_r == 2'd0 ; + wci_wslv_respF_cntr_r == 2'd0 ; + assign MUX_wci_wslv_respF_q_1$write_1__SEL_1 = + WILL_FIRE_RL_wci_wslv_respF_both && _dfoo1 ; assign MUX_wci_wslv_respF_q_1$write_1__SEL_2 = WILL_FIRE_RL_wci_wslv_respF_incCtr && - wci_wslv_respF_c_r == 2'd1 ; + wci_wslv_respF_cntr_r == 2'd1 ; + assign MUX_wsiM_reqFifo_q_0$write_1__SEL_1 = + WILL_FIRE_RL_wsiM_reqFifo_both && _dfoo7 ; assign MUX_wsiM_reqFifo_q_0$write_1__SEL_2 = - WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_c_r == 2'd0 ; + WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_cntr_r == 2'd0 ; + assign MUX_wsiM_reqFifo_q_1$write_1__SEL_1 = + WILL_FIRE_RL_wsiM_reqFifo_both && _dfoo5 ; assign MUX_wsiM_reqFifo_q_1$write_1__SEL_2 = - WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_c_r == 2'd1 ; + WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_cntr_r == 2'd1 ; assign MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 = - wsiM_reqFifo_c_r != 2'd2 && wsiS_reqFifo$EMPTY_N && + wsiM_reqFifo_cntr_r != 2'd2 && wsiS_reqFifo$EMPTY_N && wci_wslv_cState == 3'd2 ; - assign MUX_wci_wslv_illegalEdge$write_1__VAL_2 = + assign MUX_wci_wslv_illegalEdge$write_1__VAL_1 = wci_wslv_reqF$D_OUT[36:34] != 3'd4 && wci_wslv_reqF$D_OUT[36:34] != 3'd5 && wci_wslv_reqF$D_OUT[36:34] != 3'd6 ; - assign MUX_wci_wslv_respF_c_r$write_1__VAL_1 = wci_wslv_respF_c_r + 2'd1 ; - assign MUX_wci_wslv_respF_c_r$write_1__VAL_2 = wci_wslv_respF_c_r - 2'd1 ; + assign MUX_wci_wslv_respF_cntr_r$write_1__VAL_2 = + wci_wslv_respF_cntr_r + 2'd1 ; assign MUX_wci_wslv_respF_q_0$write_1__VAL_1 = - (wci_wslv_respF_c_r == 2'd1) ? + (wci_wslv_respF_cntr_r == 2'd1) ? MUX_wci_wslv_respF_q_0$write_1__VAL_2 : wci_wslv_respF_q_1 ; always@(WILL_FIRE_RL_wci_wslv_ctl_op_complete or @@ -799,25 +798,25 @@ module mkBiasWorker32B(wciS0_Clk, endcase end assign MUX_wci_wslv_respF_q_1$write_1__VAL_1 = - (wci_wslv_respF_c_r == 2'd2) ? + (wci_wslv_respF_cntr_r == 2'd2) ? MUX_wci_wslv_respF_q_0$write_1__VAL_2 : 34'h0AAAAAAAA ; assign MUX_wci_wslv_respF_x_wire$wset_1__VAL_1 = wci_wslv_illegalEdge ? 34'h3C0DE4202 : 34'h1C0DE4201 ; assign MUX_wci_wslv_respF_x_wire$wset_1__VAL_2 = - { 2'd1, _theResult____h12420 } ; - assign MUX_wsiM_reqFifo_c_r$write_1__VAL_1 = wsiM_reqFifo_c_r + 2'd1 ; - assign MUX_wsiM_reqFifo_c_r$write_1__VAL_2 = wsiM_reqFifo_c_r - 2'd1 ; + { 2'd1, _theResult____h12165 } ; + assign MUX_wsiM_reqFifo_cntr_r$write_1__VAL_1 = wsiM_reqFifo_cntr_r - 2'd1 ; + assign MUX_wsiM_reqFifo_cntr_r$write_1__VAL_2 = wsiM_reqFifo_cntr_r + 2'd1 ; assign MUX_wsiM_reqFifo_q_0$write_1__VAL_1 = - (wsiM_reqFifo_c_r == 2'd1) ? + (wsiM_reqFifo_cntr_r == 2'd1) ? MUX_wsiM_reqFifo_q_0$write_1__VAL_2 : wsiM_reqFifo_q_1 ; assign MUX_wsiM_reqFifo_q_0$write_1__VAL_2 = { wsiS_reqFifo$D_OUT[312:296], - x_data__h10386, + x_data__h10099, wsiS_reqFifo$D_OUT[39:0] } ; assign MUX_wsiM_reqFifo_q_1$write_1__VAL_1 = - (wsiM_reqFifo_c_r == 2'd2) ? + (wsiM_reqFifo_cntr_r == 2'd2) ? MUX_wsiM_reqFifo_q_0$write_1__VAL_2 : 313'h00000AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA00 ; @@ -892,7 +891,7 @@ module mkBiasWorker32B(wciS0_Clk, assign wci_wslv_respF_enqueueing$whas = WILL_FIRE_RL_wci_cfrd || WILL_FIRE_RL_wci_cfwr || WILL_FIRE_RL_wci_wslv_ctl_op_complete ; - assign wci_wslv_respF_dequeueing$whas = wci_wslv_respF_c_r != 2'd0 ; + assign wci_wslv_respF_dequeueing$whas = wci_wslv_respF_cntr_r != 2'd0 ; assign wci_wslv_sThreadBusy_pw$whas = 1'b0 ; assign wci_wslv_wci_cfwr_pw$whas = wci_wslv_reqF$EMPTY_N && wci_wslv_reqF$D_OUT[68] && @@ -962,11 +961,11 @@ module mkBiasWorker32B(wciS0_Clk, // register wci_wslv_illegalEdge assign wci_wslv_illegalEdge$D_IN = - !MUX_wci_wslv_illegalEdge$write_1__SEL_1 && - MUX_wci_wslv_illegalEdge$write_1__VAL_2 ; + MUX_wci_wslv_illegalEdge$write_1__SEL_1 && + MUX_wci_wslv_illegalEdge$write_1__VAL_1 ; assign wci_wslv_illegalEdge$EN = - WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge || - MUX_wci_wslv_illegalEdge$write_1__SEL_2 ; + MUX_wci_wslv_illegalEdge$write_1__SEL_1 || + WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge ; // register wci_wslv_isReset_isInReset assign wci_wslv_isReset_isInReset$D_IN = 1'd0 ; @@ -1001,24 +1000,24 @@ module mkBiasWorker32B(wciS0_Clk, (wci_wslv_wciReq$wget[71:69] != 3'd0) != wci_wslv_reqF_r_deq$whas ; - // register wci_wslv_respF_c_r - assign wci_wslv_respF_c_r$D_IN = - WILL_FIRE_RL_wci_wslv_respF_incCtr ? - MUX_wci_wslv_respF_c_r$write_1__VAL_1 : - MUX_wci_wslv_respF_c_r$write_1__VAL_2 ; - assign wci_wslv_respF_c_r$EN = - WILL_FIRE_RL_wci_wslv_respF_incCtr || - WILL_FIRE_RL_wci_wslv_respF_decCtr ; + // register wci_wslv_respF_cntr_r + assign wci_wslv_respF_cntr_r$D_IN = + WILL_FIRE_RL_wci_wslv_respF_decCtr ? + wci_wslv_respF_cntr_r_8_MINUS_1___d27 : + MUX_wci_wslv_respF_cntr_r$write_1__VAL_2 ; + assign wci_wslv_respF_cntr_r$EN = + WILL_FIRE_RL_wci_wslv_respF_decCtr || + WILL_FIRE_RL_wci_wslv_respF_incCtr ; // register wci_wslv_respF_q_0 - always@(WILL_FIRE_RL_wci_wslv_respF_both or + always@(MUX_wci_wslv_respF_q_0$write_1__SEL_1 or MUX_wci_wslv_respF_q_0$write_1__VAL_1 or MUX_wci_wslv_respF_q_0$write_1__SEL_2 or MUX_wci_wslv_respF_q_0$write_1__VAL_2 or WILL_FIRE_RL_wci_wslv_respF_decCtr or wci_wslv_respF_q_1) begin case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_wci_wslv_respF_both: + MUX_wci_wslv_respF_q_0$write_1__SEL_1: wci_wslv_respF_q_0$D_IN = MUX_wci_wslv_respF_q_0$write_1__VAL_1; MUX_wci_wslv_respF_q_0$write_1__SEL_2: wci_wslv_respF_q_0$D_IN = MUX_wci_wslv_respF_q_0$write_1__VAL_2; @@ -1029,20 +1028,20 @@ module mkBiasWorker32B(wciS0_Clk, endcase end assign wci_wslv_respF_q_0$EN = - WILL_FIRE_RL_wci_wslv_respF_both || + WILL_FIRE_RL_wci_wslv_respF_both && _dfoo3 || WILL_FIRE_RL_wci_wslv_respF_incCtr && - wci_wslv_respF_c_r == 2'd0 || + wci_wslv_respF_cntr_r == 2'd0 || WILL_FIRE_RL_wci_wslv_respF_decCtr ; // register wci_wslv_respF_q_1 - always@(WILL_FIRE_RL_wci_wslv_respF_both or + always@(MUX_wci_wslv_respF_q_1$write_1__SEL_1 or MUX_wci_wslv_respF_q_1$write_1__VAL_1 or MUX_wci_wslv_respF_q_1$write_1__SEL_2 or MUX_wci_wslv_respF_q_0$write_1__VAL_2 or WILL_FIRE_RL_wci_wslv_respF_decCtr) begin case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_wci_wslv_respF_both: + MUX_wci_wslv_respF_q_1$write_1__SEL_1: wci_wslv_respF_q_1$D_IN = MUX_wci_wslv_respF_q_1$write_1__VAL_1; MUX_wci_wslv_respF_q_1$write_1__SEL_2: wci_wslv_respF_q_1$D_IN = MUX_wci_wslv_respF_q_0$write_1__VAL_2; @@ -1053,9 +1052,9 @@ module mkBiasWorker32B(wciS0_Clk, endcase end assign wci_wslv_respF_q_1$EN = - WILL_FIRE_RL_wci_wslv_respF_both || + WILL_FIRE_RL_wci_wslv_respF_both && _dfoo1 || WILL_FIRE_RL_wci_wslv_respF_incCtr && - wci_wslv_respF_c_r == 2'd1 || + wci_wslv_respF_cntr_r == 2'd1 || WILL_FIRE_RL_wci_wslv_respF_decCtr ; // register wci_wslv_sFlagReg @@ -1110,24 +1109,24 @@ module mkBiasWorker32B(wciS0_Clk, assign wsiM_peerIsReady$D_IN = wsiM0_SReset_n ; assign wsiM_peerIsReady$EN = 1'd1 ; - // register wsiM_reqFifo_c_r - assign wsiM_reqFifo_c_r$D_IN = - WILL_FIRE_RL_wsiM_reqFifo_incCtr ? - MUX_wsiM_reqFifo_c_r$write_1__VAL_1 : - MUX_wsiM_reqFifo_c_r$write_1__VAL_2 ; - assign wsiM_reqFifo_c_r$EN = - WILL_FIRE_RL_wsiM_reqFifo_incCtr || - WILL_FIRE_RL_wsiM_reqFifo_decCtr ; + // register wsiM_reqFifo_cntr_r + assign wsiM_reqFifo_cntr_r$D_IN = + WILL_FIRE_RL_wsiM_reqFifo_decCtr ? + MUX_wsiM_reqFifo_cntr_r$write_1__VAL_1 : + MUX_wsiM_reqFifo_cntr_r$write_1__VAL_2 ; + assign wsiM_reqFifo_cntr_r$EN = + WILL_FIRE_RL_wsiM_reqFifo_decCtr || + WILL_FIRE_RL_wsiM_reqFifo_incCtr ; // register wsiM_reqFifo_q_0 - always@(WILL_FIRE_RL_wsiM_reqFifo_both or + always@(MUX_wsiM_reqFifo_q_0$write_1__SEL_1 or MUX_wsiM_reqFifo_q_0$write_1__VAL_1 or MUX_wsiM_reqFifo_q_0$write_1__SEL_2 or MUX_wsiM_reqFifo_q_0$write_1__VAL_2 or WILL_FIRE_RL_wsiM_reqFifo_decCtr or wsiM_reqFifo_q_1) begin case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_wsiM_reqFifo_both: + MUX_wsiM_reqFifo_q_0$write_1__SEL_1: wsiM_reqFifo_q_0$D_IN = MUX_wsiM_reqFifo_q_0$write_1__VAL_1; MUX_wsiM_reqFifo_q_0$write_1__SEL_2: wsiM_reqFifo_q_0$D_IN = MUX_wsiM_reqFifo_q_0$write_1__VAL_2; @@ -1138,19 +1137,20 @@ module mkBiasWorker32B(wciS0_Clk, endcase end assign wsiM_reqFifo_q_0$EN = - WILL_FIRE_RL_wsiM_reqFifo_both || - WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_c_r == 2'd0 || + WILL_FIRE_RL_wsiM_reqFifo_both && _dfoo7 || + WILL_FIRE_RL_wsiM_reqFifo_incCtr && + wsiM_reqFifo_cntr_r == 2'd0 || WILL_FIRE_RL_wsiM_reqFifo_decCtr ; // register wsiM_reqFifo_q_1 - always@(WILL_FIRE_RL_wsiM_reqFifo_both or + always@(MUX_wsiM_reqFifo_q_1$write_1__SEL_1 or MUX_wsiM_reqFifo_q_1$write_1__VAL_1 or MUX_wsiM_reqFifo_q_1$write_1__SEL_2 or MUX_wsiM_reqFifo_q_0$write_1__VAL_2 or WILL_FIRE_RL_wsiM_reqFifo_decCtr) begin case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_wsiM_reqFifo_both: + MUX_wsiM_reqFifo_q_1$write_1__SEL_1: wsiM_reqFifo_q_1$D_IN = MUX_wsiM_reqFifo_q_1$write_1__VAL_1; MUX_wsiM_reqFifo_q_1$write_1__SEL_2: wsiM_reqFifo_q_1$D_IN = MUX_wsiM_reqFifo_q_0$write_1__VAL_2; @@ -1162,8 +1162,9 @@ module mkBiasWorker32B(wciS0_Clk, endcase end assign wsiM_reqFifo_q_1$EN = - WILL_FIRE_RL_wsiM_reqFifo_both || - WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_c_r == 2'd1 || + WILL_FIRE_RL_wsiM_reqFifo_both && _dfoo5 || + WILL_FIRE_RL_wsiM_reqFifo_incCtr && + wsiM_reqFifo_cntr_r == 2'd1 || WILL_FIRE_RL_wsiM_reqFifo_decCtr ; // register wsiM_sThreadBusy_d @@ -1249,7 +1250,7 @@ module mkBiasWorker32B(wciS0_Clk, // register wsiS_reqFifo_levelsValid assign wsiS_reqFifo_levelsValid$D_IN = WILL_FIRE_RL_wsiS_reqFifo_reset ; assign wsiS_reqFifo_levelsValid$EN = - wsiM_reqFifo_c_r != 2'd2 && wsiS_reqFifo$EMPTY_N && + wsiM_reqFifo_cntr_r != 2'd2 && wsiS_reqFifo$EMPTY_N && wci_wslv_cState == 3'd2 || WILL_FIRE_RL_wsiS_reqFifo_enq || WILL_FIRE_RL_wsiS_reqFifo_reset ; @@ -1294,15 +1295,29 @@ module mkBiasWorker32B(wciS0_Clk, assign wsiS_reqFifo$CLR = 1'b0 ; // remaining internal signals - assign rdat__h12510 = hasDebugLogic ? { 16'd0, x__h12514 } : 32'd0 ; - assign rdat__h12610 = hasDebugLogic ? wsiS_extStatusW$wget[95:64] : 32'd0 ; - assign rdat__h12624 = hasDebugLogic ? wsiS_extStatusW$wget[63:32] : 32'd0 ; - assign rdat__h12632 = hasDebugLogic ? wsiS_extStatusW$wget[31:0] : 32'd0 ; - assign rdat__h12638 = hasDebugLogic ? wsiM_extStatusW$wget[95:64] : 32'd0 ; - assign rdat__h12652 = hasDebugLogic ? wsiM_extStatusW$wget[63:32] : 32'd0 ; - assign rdat__h12660 = hasDebugLogic ? wsiM_extStatusW$wget[31:0] : 32'd0 ; - assign x__h12514 = { wsiS_statusR, wsiM_statusR } ; - assign x_data__h10386 = + assign _dfoo1 = + wci_wslv_respF_cntr_r != 2'd2 || + wci_wslv_respF_cntr_r_8_MINUS_1___d27 == 2'd1 ; + assign _dfoo3 = + wci_wslv_respF_cntr_r != 2'd1 || + wci_wslv_respF_cntr_r_8_MINUS_1___d27 == 2'd0 ; + assign _dfoo5 = + wsiM_reqFifo_cntr_r != 2'd2 || + MUX_wsiM_reqFifo_cntr_r$write_1__VAL_1 == 2'd1 ; + assign _dfoo7 = + wsiM_reqFifo_cntr_r != 2'd1 || + MUX_wsiM_reqFifo_cntr_r$write_1__VAL_1 == 2'd0 ; + assign rdat__h12255 = hasDebugLogic ? { 16'd0, x__h12259 } : 32'd0 ; + assign rdat__h12355 = hasDebugLogic ? wsiS_extStatusW$wget[95:64] : 32'd0 ; + assign rdat__h12369 = hasDebugLogic ? wsiS_extStatusW$wget[63:32] : 32'd0 ; + assign rdat__h12377 = hasDebugLogic ? wsiS_extStatusW$wget[31:0] : 32'd0 ; + assign rdat__h12383 = hasDebugLogic ? wsiM_extStatusW$wget[95:64] : 32'd0 ; + assign rdat__h12397 = hasDebugLogic ? wsiM_extStatusW$wget[63:32] : 32'd0 ; + assign rdat__h12405 = hasDebugLogic ? wsiM_extStatusW$wget[31:0] : 32'd0 ; + assign wci_wslv_respF_cntr_r_8_MINUS_1___d27 = + wci_wslv_respF_cntr_r - 2'd1 ; + assign x__h12259 = { wsiS_statusR, wsiM_statusR } ; + assign x_data__h10099 = { wsiS_reqFifo$D_OUT[295:264] + biasValue, wsiS_reqFifo$D_OUT[263:232] + biasValue, wsiS_reqFifo$D_OUT[231:200] + biasValue, @@ -1314,22 +1329,22 @@ module mkBiasWorker32B(wciS0_Clk, always@(wci_wslv_reqF$D_OUT or biasValue or controlReg or - rdat__h12510 or - rdat__h12610 or - rdat__h12624 or - rdat__h12632 or rdat__h12638 or rdat__h12652 or rdat__h12660) + rdat__h12255 or + rdat__h12355 or + rdat__h12369 or + rdat__h12377 or rdat__h12383 or rdat__h12397 or rdat__h12405) begin case (wci_wslv_reqF$D_OUT[39:32]) - 8'h0: _theResult____h12420 = biasValue; - 8'h04: _theResult____h12420 = controlReg; - 8'h20: _theResult____h12420 = rdat__h12510; - 8'h24: _theResult____h12420 = rdat__h12610; - 8'h28: _theResult____h12420 = rdat__h12624; - 8'h2C: _theResult____h12420 = rdat__h12632; - 8'h30: _theResult____h12420 = rdat__h12638; - 8'h34: _theResult____h12420 = rdat__h12652; - 8'h38: _theResult____h12420 = rdat__h12660; - default: _theResult____h12420 = 32'd0; + 8'h0: _theResult____h12165 = biasValue; + 8'h04: _theResult____h12165 = controlReg; + 8'h20: _theResult____h12165 = rdat__h12255; + 8'h24: _theResult____h12165 = rdat__h12355; + 8'h28: _theResult____h12165 = rdat__h12369; + 8'h2C: _theResult____h12165 = rdat__h12377; + 8'h30: _theResult____h12165 = rdat__h12383; + 8'h34: _theResult____h12165 = rdat__h12397; + 8'h38: _theResult____h12165 = rdat__h12405; + default: _theResult____h12165 = 32'd0; endcase end @@ -1346,7 +1361,7 @@ module mkBiasWorker32B(wciS0_Clk, wci_wslv_illegalEdge <= `BSV_ASSIGNMENT_DELAY 1'd0; wci_wslv_nState <= `BSV_ASSIGNMENT_DELAY 3'd0; wci_wslv_reqF_countReg <= `BSV_ASSIGNMENT_DELAY 2'd0; - wci_wslv_respF_c_r <= `BSV_ASSIGNMENT_DELAY 2'd0; + wci_wslv_respF_cntr_r <= `BSV_ASSIGNMENT_DELAY 2'd0; wci_wslv_respF_q_0 <= `BSV_ASSIGNMENT_DELAY 34'h0AAAAAAAA; wci_wslv_respF_q_1 <= `BSV_ASSIGNMENT_DELAY 34'h0AAAAAAAA; wci_wslv_sFlagReg <= `BSV_ASSIGNMENT_DELAY 1'd0; @@ -1357,7 +1372,7 @@ module mkBiasWorker32B(wciS0_Clk, wsiM_operateD <= `BSV_ASSIGNMENT_DELAY 1'd0; wsiM_pMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0; wsiM_peerIsReady <= `BSV_ASSIGNMENT_DELAY 1'd0; - wsiM_reqFifo_c_r <= `BSV_ASSIGNMENT_DELAY 2'd0; + wsiM_reqFifo_cntr_r <= `BSV_ASSIGNMENT_DELAY 2'd0; wsiM_reqFifo_q_0 <= `BSV_ASSIGNMENT_DELAY 313'h00000AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA00; wsiM_reqFifo_q_1 <= `BSV_ASSIGNMENT_DELAY @@ -1396,8 +1411,9 @@ module mkBiasWorker32B(wciS0_Clk, if (wci_wslv_reqF_countReg$EN) wci_wslv_reqF_countReg <= `BSV_ASSIGNMENT_DELAY wci_wslv_reqF_countReg$D_IN; - if (wci_wslv_respF_c_r$EN) - wci_wslv_respF_c_r <= `BSV_ASSIGNMENT_DELAY wci_wslv_respF_c_r$D_IN; + if (wci_wslv_respF_cntr_r$EN) + wci_wslv_respF_cntr_r <= `BSV_ASSIGNMENT_DELAY + wci_wslv_respF_cntr_r$D_IN; if (wci_wslv_respF_q_0$EN) wci_wslv_respF_q_0 <= `BSV_ASSIGNMENT_DELAY wci_wslv_respF_q_0$D_IN; if (wci_wslv_respF_q_1$EN) @@ -1419,8 +1435,9 @@ module mkBiasWorker32B(wciS0_Clk, wsiM_pMesgCount <= `BSV_ASSIGNMENT_DELAY wsiM_pMesgCount$D_IN; if (wsiM_peerIsReady$EN) wsiM_peerIsReady <= `BSV_ASSIGNMENT_DELAY wsiM_peerIsReady$D_IN; - if (wsiM_reqFifo_c_r$EN) - wsiM_reqFifo_c_r <= `BSV_ASSIGNMENT_DELAY wsiM_reqFifo_c_r$D_IN; + if (wsiM_reqFifo_cntr_r$EN) + wsiM_reqFifo_cntr_r <= `BSV_ASSIGNMENT_DELAY + wsiM_reqFifo_cntr_r$D_IN; if (wsiM_reqFifo_q_0$EN) wsiM_reqFifo_q_0 <= `BSV_ASSIGNMENT_DELAY wsiM_reqFifo_q_0$D_IN; if (wsiM_reqFifo_q_1$EN) @@ -1501,7 +1518,7 @@ module mkBiasWorker32B(wciS0_Clk, wci_wslv_isReset_isInReset = 1'h0; wci_wslv_nState = 3'h2; wci_wslv_reqF_countReg = 2'h2; - wci_wslv_respF_c_r = 2'h2; + wci_wslv_respF_cntr_r = 2'h2; wci_wslv_respF_q_0 = 34'h2AAAAAAAA; wci_wslv_respF_q_1 = 34'h2AAAAAAAA; wci_wslv_sFlagReg = 1'h0; @@ -1513,7 +1530,7 @@ module mkBiasWorker32B(wciS0_Clk, wsiM_operateD = 1'h0; wsiM_pMesgCount = 32'hAAAAAAAA; wsiM_peerIsReady = 1'h0; - wsiM_reqFifo_c_r = 2'h2; + wsiM_reqFifo_cntr_r = 2'h2; wsiM_reqFifo_q_0 = 313'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; wsiM_reqFifo_q_1 = @@ -1549,13 +1566,13 @@ module mkBiasWorker32B(wciS0_Clk, if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_start) begin - v__h3706 = $time; + v__h3574 = $time; #0; end if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_start) $display("[%0d]: %m: WCI ControlOp: Starting-transition edge:%x from:%x", - v__h3706, + v__h3574, wci_wslv_reqF$D_OUT[36:34], wci_wslv_cState); if (wciS0_MReset_n != `BSV_RESET_VALUE) @@ -1570,54 +1587,54 @@ module mkBiasWorker32B(wciS0_Clk, if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfwr) begin - v__h12281 = $time; + v__h12026 = $time; #0; end if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfwr) $display("[%0d]: %m: WCI CONFIG WRITE Addr:%0x BE:%0x Data:%0x", - v__h12281, + v__h12026, wci_wslv_reqF$D_OUT[63:32], wci_wslv_reqF$D_OUT[67:64], wci_wslv_reqF$D_OUT[31:0]); if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge) begin - v__h4025 = $time; + v__h3893 = $time; #0; end if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge) $display("[%0d]: %m: WCI ControlOp: ILLEGAL-EDGE Completed-transition edge:%x from:%x", - v__h4025, + v__h3893, wci_wslv_cEdge, wci_wslv_cState); if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && !wci_wslv_illegalEdge) begin - v__h3881 = $time; + v__h3749 = $time; #0; end if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && !wci_wslv_illegalEdge) $display("[%0d]: %m: WCI ControlOp: Completed-transition edge:%x from:%x to:%x", - v__h3881, + v__h3749, wci_wslv_cEdge, wci_wslv_cState, wci_wslv_nState); if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfrd) begin - v__h12436 = $time; + v__h12181 = $time; #0; end if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfrd) $display("[%0d]: %m: WCI CONFIG READ Addr:%0x BE:%0x Data:%0x", - v__h12436, + v__h12181, wci_wslv_reqF$D_OUT[63:32], wci_wslv_reqF$D_OUT[67:64], - _theResult____h12420); + _theResult____h12165); if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_OrE) $display("Error: \"bsv/wrk/BiasWorker.bsv\", line 67, column 28: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n"); diff --git a/rtl/mkBiasWorker4B.v b/rtl/mkBiasWorker4B.v index 16cbad42..4f0e8796 100644 --- a/rtl/mkBiasWorker4B.v +++ b/rtl/mkBiasWorker4B.v @@ -1,7 +1,7 @@ // -// Generated by Bluespec Compiler, version 2012.09.beta1 (build 29570, 2012-09.11) +// Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Tue Dec 11 16:20:57 EST 2012 +// On Fri Jun 21 16:57:46 EDT 2013 // // // Ports: @@ -342,10 +342,10 @@ module mkBiasWorker4B(wciS0_Clk, wire [1 : 0] wci_wslv_reqF_countReg$D_IN; wire wci_wslv_reqF_countReg$EN; - // register wci_wslv_respF_c_r - reg [1 : 0] wci_wslv_respF_c_r; - wire [1 : 0] wci_wslv_respF_c_r$D_IN; - wire wci_wslv_respF_c_r$EN; + // register wci_wslv_respF_cntr_r + reg [1 : 0] wci_wslv_respF_cntr_r; + wire [1 : 0] wci_wslv_respF_cntr_r$D_IN; + wire wci_wslv_respF_cntr_r$EN; // register wci_wslv_respF_q_0 reg [33 : 0] wci_wslv_respF_q_0; @@ -396,10 +396,10 @@ module mkBiasWorker4B(wciS0_Clk, reg wsiM_peerIsReady; wire wsiM_peerIsReady$D_IN, wsiM_peerIsReady$EN; - // register wsiM_reqFifo_c_r - reg [1 : 0] wsiM_reqFifo_c_r; - wire [1 : 0] wsiM_reqFifo_c_r$D_IN; - wire wsiM_reqFifo_c_r$EN; + // register wsiM_reqFifo_cntr_r + reg [1 : 0] wsiM_reqFifo_cntr_r; + wire [1 : 0] wsiM_reqFifo_cntr_r$D_IN; + wire wsiM_reqFifo_cntr_r$EN; // register wsiM_reqFifo_q_0 reg [60 : 0] wsiM_reqFifo_q_0; @@ -534,34 +534,38 @@ module mkBiasWorker4B(wciS0_Clk, MUX_wci_wslv_respF_q_1$write_1__VAL_1, MUX_wci_wslv_respF_x_wire$wset_1__VAL_1, MUX_wci_wslv_respF_x_wire$wset_1__VAL_2; - wire [1 : 0] MUX_wci_wslv_respF_c_r$write_1__VAL_1, - MUX_wci_wslv_respF_c_r$write_1__VAL_2, - MUX_wsiM_reqFifo_c_r$write_1__VAL_1, - MUX_wsiM_reqFifo_c_r$write_1__VAL_2; + wire [1 : 0] MUX_wci_wslv_respF_cntr_r$write_1__VAL_2, + MUX_wsiM_reqFifo_cntr_r$write_1__VAL_1, + MUX_wsiM_reqFifo_cntr_r$write_1__VAL_2; wire MUX_biasValue$write_1__SEL_1, MUX_biasValue$write_1__SEL_2, MUX_controlReg$write_1__SEL_1, MUX_wci_wslv_illegalEdge$write_1__SEL_1, - MUX_wci_wslv_illegalEdge$write_1__SEL_2, - MUX_wci_wslv_illegalEdge$write_1__VAL_2, + MUX_wci_wslv_illegalEdge$write_1__VAL_1, + MUX_wci_wslv_respF_q_0$write_1__SEL_1, MUX_wci_wslv_respF_q_0$write_1__SEL_2, + MUX_wci_wslv_respF_q_1$write_1__SEL_1, MUX_wci_wslv_respF_q_1$write_1__SEL_2, + MUX_wsiM_reqFifo_q_0$write_1__SEL_1, MUX_wsiM_reqFifo_q_0$write_1__SEL_2, + MUX_wsiM_reqFifo_q_1$write_1__SEL_1, MUX_wsiM_reqFifo_q_1$write_1__SEL_2, MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3; // remaining internal signals - reg [63 : 0] v__h10915, v__h11070, v__h3706, v__h3881, v__h4025; - reg [31 : 0] _theResult____h11054; - wire [31 : 0] rdat__h11144, - rdat__h11244, - rdat__h11258, - rdat__h11266, - rdat__h11272, - rdat__h11286, - rdat__h11294, - x_data__h10386; - wire [15 : 0] x__h11148; + reg [63 : 0] v__h10632, v__h10787, v__h3574, v__h3749, v__h3893; + reg [31 : 0] _theResult____h10771; + wire [31 : 0] rdat__h10861, + rdat__h10961, + rdat__h10975, + rdat__h10983, + rdat__h10989, + rdat__h11003, + rdat__h11011, + x_data__h10099; + wire [15 : 0] x__h10865; + wire [1 : 0] wci_wslv_respF_cntr_r_8_MINUS_1___d27; + wire _dfoo1, _dfoo3, _dfoo5, _dfoo7; // value method wciS0_sResp assign wciS0_SResp = wci_wslv_respF_q_0[33:32] ; @@ -657,53 +661,45 @@ module mkBiasWorker4B(wciS0_Clk, // rule RL_wci_cfwr assign WILL_FIRE_RL_wci_cfwr = - wci_wslv_respF_c_r != 2'd2 && wci_wslv_reqF$EMPTY_N && + wci_wslv_respF_cntr_r != 2'd2 && wci_wslv_reqF$EMPTY_N && wci_wslv_wci_cfwr_pw$whas && !WILL_FIRE_RL_wci_wslv_ctl_op_start && !WILL_FIRE_RL_wci_wslv_ctl_op_complete ; // rule RL_wci_wslv_ctl_op_complete assign WILL_FIRE_RL_wci_wslv_ctl_op_complete = - wci_wslv_respF_c_r != 2'd2 && wci_wslv_ctlOpActive && + wci_wslv_respF_cntr_r != 2'd2 && wci_wslv_ctlOpActive && wci_wslv_ctlAckReg ; // rule RL_wci_cfrd assign WILL_FIRE_RL_wci_cfrd = - wci_wslv_respF_c_r != 2'd2 && wci_wslv_reqF$EMPTY_N && + wci_wslv_respF_cntr_r != 2'd2 && wci_wslv_reqF$EMPTY_N && wci_wslv_wci_cfrd_pw$whas && !WILL_FIRE_RL_wci_wslv_ctl_op_start && !WILL_FIRE_RL_wci_wslv_ctl_op_complete ; // rule RL_wci_wslv_respF_incCtr assign WILL_FIRE_RL_wci_wslv_respF_incCtr = - ((wci_wslv_respF_c_r == 2'd0) ? - wci_wslv_respF_x_wire$whas : - wci_wslv_respF_c_r != 2'd1 || wci_wslv_respF_x_wire$whas) && - wci_wslv_respF_enqueueing$whas && - !(wci_wslv_respF_c_r != 2'd0) ; + wci_wslv_respF_x_wire$whas && wci_wslv_respF_enqueueing$whas && + !(wci_wslv_respF_cntr_r != 2'd0) ; // rule RL_wci_wslv_respF_decCtr assign WILL_FIRE_RL_wci_wslv_respF_decCtr = - wci_wslv_respF_c_r != 2'd0 && !wci_wslv_respF_enqueueing$whas ; + wci_wslv_respF_cntr_r != 2'd0 && + !wci_wslv_respF_enqueueing$whas ; // rule RL_wci_wslv_respF_both assign WILL_FIRE_RL_wci_wslv_respF_both = - ((wci_wslv_respF_c_r == 2'd1) ? - wci_wslv_respF_x_wire$whas : - wci_wslv_respF_c_r != 2'd2 || wci_wslv_respF_x_wire$whas) && - wci_wslv_respF_c_r != 2'd0 && + wci_wslv_respF_x_wire$whas && wci_wslv_respF_cntr_r != 2'd0 && wci_wslv_respF_enqueueing$whas ; // rule RL_wsiM_reqFifo_deq assign WILL_FIRE_RL_wsiM_reqFifo_deq = - wsiM_reqFifo_c_r != 2'd0 && !wsiM_sThreadBusy_d ; + wsiM_reqFifo_cntr_r != 2'd0 && !wsiM_sThreadBusy_d ; // rule RL_wsiM_reqFifo_incCtr assign WILL_FIRE_RL_wsiM_reqFifo_incCtr = - ((wsiM_reqFifo_c_r == 2'd0) ? - MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 : - wsiM_reqFifo_c_r != 2'd1 || - MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3) && + MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 && MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 && !WILL_FIRE_RL_wsiM_reqFifo_deq ; @@ -714,10 +710,7 @@ module mkBiasWorker4B(wciS0_Clk, // rule RL_wsiM_reqFifo_both assign WILL_FIRE_RL_wsiM_reqFifo_both = - ((wsiM_reqFifo_c_r == 2'd1) ? - MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 : - wsiM_reqFifo_c_r != 2'd2 || - MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3) && + MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 && WILL_FIRE_RL_wsiM_reqFifo_deq && MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 ; @@ -742,8 +735,6 @@ module mkBiasWorker4B(wciS0_Clk, assign MUX_controlReg$write_1__SEL_1 = WILL_FIRE_RL_wci_cfwr && wci_wslv_reqF$D_OUT[39:32] == 8'h04 ; assign MUX_wci_wslv_illegalEdge$write_1__SEL_1 = - WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge ; - assign MUX_wci_wslv_illegalEdge$write_1__SEL_2 = WILL_FIRE_RL_wci_wslv_ctl_op_start && (wci_wslv_reqF$D_OUT[36:34] == 3'd0 && wci_wslv_cState != 3'd0 || wci_wslv_reqF$D_OUT[36:34] == 3'd1 && wci_wslv_cState != 3'd1 && @@ -756,27 +747,35 @@ module mkBiasWorker4B(wciS0_Clk, wci_wslv_reqF$D_OUT[36:34] == 3'd5 || wci_wslv_reqF$D_OUT[36:34] == 3'd6 || wci_wslv_reqF$D_OUT[36:34] == 3'd7) ; + assign MUX_wci_wslv_respF_q_0$write_1__SEL_1 = + WILL_FIRE_RL_wci_wslv_respF_both && _dfoo3 ; assign MUX_wci_wslv_respF_q_0$write_1__SEL_2 = WILL_FIRE_RL_wci_wslv_respF_incCtr && - wci_wslv_respF_c_r == 2'd0 ; + wci_wslv_respF_cntr_r == 2'd0 ; + assign MUX_wci_wslv_respF_q_1$write_1__SEL_1 = + WILL_FIRE_RL_wci_wslv_respF_both && _dfoo1 ; assign MUX_wci_wslv_respF_q_1$write_1__SEL_2 = WILL_FIRE_RL_wci_wslv_respF_incCtr && - wci_wslv_respF_c_r == 2'd1 ; + wci_wslv_respF_cntr_r == 2'd1 ; + assign MUX_wsiM_reqFifo_q_0$write_1__SEL_1 = + WILL_FIRE_RL_wsiM_reqFifo_both && _dfoo7 ; assign MUX_wsiM_reqFifo_q_0$write_1__SEL_2 = - WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_c_r == 2'd0 ; + WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_cntr_r == 2'd0 ; + assign MUX_wsiM_reqFifo_q_1$write_1__SEL_1 = + WILL_FIRE_RL_wsiM_reqFifo_both && _dfoo5 ; assign MUX_wsiM_reqFifo_q_1$write_1__SEL_2 = - WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_c_r == 2'd1 ; + WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_cntr_r == 2'd1 ; assign MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 = - wsiM_reqFifo_c_r != 2'd2 && wsiS_reqFifo$EMPTY_N && + wsiM_reqFifo_cntr_r != 2'd2 && wsiS_reqFifo$EMPTY_N && wci_wslv_cState == 3'd2 ; - assign MUX_wci_wslv_illegalEdge$write_1__VAL_2 = + assign MUX_wci_wslv_illegalEdge$write_1__VAL_1 = wci_wslv_reqF$D_OUT[36:34] != 3'd4 && wci_wslv_reqF$D_OUT[36:34] != 3'd5 && wci_wslv_reqF$D_OUT[36:34] != 3'd6 ; - assign MUX_wci_wslv_respF_c_r$write_1__VAL_1 = wci_wslv_respF_c_r + 2'd1 ; - assign MUX_wci_wslv_respF_c_r$write_1__VAL_2 = wci_wslv_respF_c_r - 2'd1 ; + assign MUX_wci_wslv_respF_cntr_r$write_1__VAL_2 = + wci_wslv_respF_cntr_r + 2'd1 ; assign MUX_wci_wslv_respF_q_0$write_1__VAL_1 = - (wci_wslv_respF_c_r == 2'd1) ? + (wci_wslv_respF_cntr_r == 2'd1) ? MUX_wci_wslv_respF_q_0$write_1__VAL_2 : wci_wslv_respF_q_1 ; always@(WILL_FIRE_RL_wci_wslv_ctl_op_complete or @@ -798,25 +797,25 @@ module mkBiasWorker4B(wciS0_Clk, endcase end assign MUX_wci_wslv_respF_q_1$write_1__VAL_1 = - (wci_wslv_respF_c_r == 2'd2) ? + (wci_wslv_respF_cntr_r == 2'd2) ? MUX_wci_wslv_respF_q_0$write_1__VAL_2 : 34'h0AAAAAAAA ; assign MUX_wci_wslv_respF_x_wire$wset_1__VAL_1 = wci_wslv_illegalEdge ? 34'h3C0DE4202 : 34'h1C0DE4201 ; assign MUX_wci_wslv_respF_x_wire$wset_1__VAL_2 = - { 2'd1, _theResult____h11054 } ; - assign MUX_wsiM_reqFifo_c_r$write_1__VAL_1 = wsiM_reqFifo_c_r + 2'd1 ; - assign MUX_wsiM_reqFifo_c_r$write_1__VAL_2 = wsiM_reqFifo_c_r - 2'd1 ; + { 2'd1, _theResult____h10771 } ; + assign MUX_wsiM_reqFifo_cntr_r$write_1__VAL_1 = wsiM_reqFifo_cntr_r - 2'd1 ; + assign MUX_wsiM_reqFifo_cntr_r$write_1__VAL_2 = wsiM_reqFifo_cntr_r + 2'd1 ; assign MUX_wsiM_reqFifo_q_0$write_1__VAL_1 = - (wsiM_reqFifo_c_r == 2'd1) ? + (wsiM_reqFifo_cntr_r == 2'd1) ? MUX_wsiM_reqFifo_q_0$write_1__VAL_2 : wsiM_reqFifo_q_1 ; assign MUX_wsiM_reqFifo_q_0$write_1__VAL_2 = { wsiS_reqFifo$D_OUT[60:44], - x_data__h10386, + x_data__h10099, wsiS_reqFifo$D_OUT[11:0] } ; assign MUX_wsiM_reqFifo_q_1$write_1__VAL_1 = - (wsiM_reqFifo_c_r == 2'd2) ? + (wsiM_reqFifo_cntr_r == 2'd2) ? MUX_wsiM_reqFifo_q_0$write_1__VAL_2 : 61'h00000AAAAAAAAA00 ; @@ -891,7 +890,7 @@ module mkBiasWorker4B(wciS0_Clk, assign wci_wslv_respF_enqueueing$whas = WILL_FIRE_RL_wci_cfrd || WILL_FIRE_RL_wci_cfwr || WILL_FIRE_RL_wci_wslv_ctl_op_complete ; - assign wci_wslv_respF_dequeueing$whas = wci_wslv_respF_c_r != 2'd0 ; + assign wci_wslv_respF_dequeueing$whas = wci_wslv_respF_cntr_r != 2'd0 ; assign wci_wslv_sThreadBusy_pw$whas = 1'b0 ; assign wci_wslv_wci_cfwr_pw$whas = wci_wslv_reqF$EMPTY_N && wci_wslv_reqF$D_OUT[68] && @@ -961,11 +960,11 @@ module mkBiasWorker4B(wciS0_Clk, // register wci_wslv_illegalEdge assign wci_wslv_illegalEdge$D_IN = - !MUX_wci_wslv_illegalEdge$write_1__SEL_1 && - MUX_wci_wslv_illegalEdge$write_1__VAL_2 ; + MUX_wci_wslv_illegalEdge$write_1__SEL_1 && + MUX_wci_wslv_illegalEdge$write_1__VAL_1 ; assign wci_wslv_illegalEdge$EN = - WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge || - MUX_wci_wslv_illegalEdge$write_1__SEL_2 ; + MUX_wci_wslv_illegalEdge$write_1__SEL_1 || + WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge ; // register wci_wslv_isReset_isInReset assign wci_wslv_isReset_isInReset$D_IN = 1'd0 ; @@ -1000,24 +999,24 @@ module mkBiasWorker4B(wciS0_Clk, (wci_wslv_wciReq$wget[71:69] != 3'd0) != wci_wslv_reqF_r_deq$whas ; - // register wci_wslv_respF_c_r - assign wci_wslv_respF_c_r$D_IN = - WILL_FIRE_RL_wci_wslv_respF_incCtr ? - MUX_wci_wslv_respF_c_r$write_1__VAL_1 : - MUX_wci_wslv_respF_c_r$write_1__VAL_2 ; - assign wci_wslv_respF_c_r$EN = - WILL_FIRE_RL_wci_wslv_respF_incCtr || - WILL_FIRE_RL_wci_wslv_respF_decCtr ; + // register wci_wslv_respF_cntr_r + assign wci_wslv_respF_cntr_r$D_IN = + WILL_FIRE_RL_wci_wslv_respF_decCtr ? + wci_wslv_respF_cntr_r_8_MINUS_1___d27 : + MUX_wci_wslv_respF_cntr_r$write_1__VAL_2 ; + assign wci_wslv_respF_cntr_r$EN = + WILL_FIRE_RL_wci_wslv_respF_decCtr || + WILL_FIRE_RL_wci_wslv_respF_incCtr ; // register wci_wslv_respF_q_0 - always@(WILL_FIRE_RL_wci_wslv_respF_both or + always@(MUX_wci_wslv_respF_q_0$write_1__SEL_1 or MUX_wci_wslv_respF_q_0$write_1__VAL_1 or MUX_wci_wslv_respF_q_0$write_1__SEL_2 or MUX_wci_wslv_respF_q_0$write_1__VAL_2 or WILL_FIRE_RL_wci_wslv_respF_decCtr or wci_wslv_respF_q_1) begin case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_wci_wslv_respF_both: + MUX_wci_wslv_respF_q_0$write_1__SEL_1: wci_wslv_respF_q_0$D_IN = MUX_wci_wslv_respF_q_0$write_1__VAL_1; MUX_wci_wslv_respF_q_0$write_1__SEL_2: wci_wslv_respF_q_0$D_IN = MUX_wci_wslv_respF_q_0$write_1__VAL_2; @@ -1028,20 +1027,20 @@ module mkBiasWorker4B(wciS0_Clk, endcase end assign wci_wslv_respF_q_0$EN = - WILL_FIRE_RL_wci_wslv_respF_both || + WILL_FIRE_RL_wci_wslv_respF_both && _dfoo3 || WILL_FIRE_RL_wci_wslv_respF_incCtr && - wci_wslv_respF_c_r == 2'd0 || + wci_wslv_respF_cntr_r == 2'd0 || WILL_FIRE_RL_wci_wslv_respF_decCtr ; // register wci_wslv_respF_q_1 - always@(WILL_FIRE_RL_wci_wslv_respF_both or + always@(MUX_wci_wslv_respF_q_1$write_1__SEL_1 or MUX_wci_wslv_respF_q_1$write_1__VAL_1 or MUX_wci_wslv_respF_q_1$write_1__SEL_2 or MUX_wci_wslv_respF_q_0$write_1__VAL_2 or WILL_FIRE_RL_wci_wslv_respF_decCtr) begin case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_wci_wslv_respF_both: + MUX_wci_wslv_respF_q_1$write_1__SEL_1: wci_wslv_respF_q_1$D_IN = MUX_wci_wslv_respF_q_1$write_1__VAL_1; MUX_wci_wslv_respF_q_1$write_1__SEL_2: wci_wslv_respF_q_1$D_IN = MUX_wci_wslv_respF_q_0$write_1__VAL_2; @@ -1052,9 +1051,9 @@ module mkBiasWorker4B(wciS0_Clk, endcase end assign wci_wslv_respF_q_1$EN = - WILL_FIRE_RL_wci_wslv_respF_both || + WILL_FIRE_RL_wci_wslv_respF_both && _dfoo1 || WILL_FIRE_RL_wci_wslv_respF_incCtr && - wci_wslv_respF_c_r == 2'd1 || + wci_wslv_respF_cntr_r == 2'd1 || WILL_FIRE_RL_wci_wslv_respF_decCtr ; // register wci_wslv_sFlagReg @@ -1109,24 +1108,24 @@ module mkBiasWorker4B(wciS0_Clk, assign wsiM_peerIsReady$D_IN = wsiM0_SReset_n ; assign wsiM_peerIsReady$EN = 1'd1 ; - // register wsiM_reqFifo_c_r - assign wsiM_reqFifo_c_r$D_IN = - WILL_FIRE_RL_wsiM_reqFifo_incCtr ? - MUX_wsiM_reqFifo_c_r$write_1__VAL_1 : - MUX_wsiM_reqFifo_c_r$write_1__VAL_2 ; - assign wsiM_reqFifo_c_r$EN = - WILL_FIRE_RL_wsiM_reqFifo_incCtr || - WILL_FIRE_RL_wsiM_reqFifo_decCtr ; + // register wsiM_reqFifo_cntr_r + assign wsiM_reqFifo_cntr_r$D_IN = + WILL_FIRE_RL_wsiM_reqFifo_decCtr ? + MUX_wsiM_reqFifo_cntr_r$write_1__VAL_1 : + MUX_wsiM_reqFifo_cntr_r$write_1__VAL_2 ; + assign wsiM_reqFifo_cntr_r$EN = + WILL_FIRE_RL_wsiM_reqFifo_decCtr || + WILL_FIRE_RL_wsiM_reqFifo_incCtr ; // register wsiM_reqFifo_q_0 - always@(WILL_FIRE_RL_wsiM_reqFifo_both or + always@(MUX_wsiM_reqFifo_q_0$write_1__SEL_1 or MUX_wsiM_reqFifo_q_0$write_1__VAL_1 or MUX_wsiM_reqFifo_q_0$write_1__SEL_2 or MUX_wsiM_reqFifo_q_0$write_1__VAL_2 or WILL_FIRE_RL_wsiM_reqFifo_decCtr or wsiM_reqFifo_q_1) begin case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_wsiM_reqFifo_both: + MUX_wsiM_reqFifo_q_0$write_1__SEL_1: wsiM_reqFifo_q_0$D_IN = MUX_wsiM_reqFifo_q_0$write_1__VAL_1; MUX_wsiM_reqFifo_q_0$write_1__SEL_2: wsiM_reqFifo_q_0$D_IN = MUX_wsiM_reqFifo_q_0$write_1__VAL_2; @@ -1137,19 +1136,20 @@ module mkBiasWorker4B(wciS0_Clk, endcase end assign wsiM_reqFifo_q_0$EN = - WILL_FIRE_RL_wsiM_reqFifo_both || - WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_c_r == 2'd0 || + WILL_FIRE_RL_wsiM_reqFifo_both && _dfoo7 || + WILL_FIRE_RL_wsiM_reqFifo_incCtr && + wsiM_reqFifo_cntr_r == 2'd0 || WILL_FIRE_RL_wsiM_reqFifo_decCtr ; // register wsiM_reqFifo_q_1 - always@(WILL_FIRE_RL_wsiM_reqFifo_both or + always@(MUX_wsiM_reqFifo_q_1$write_1__SEL_1 or MUX_wsiM_reqFifo_q_1$write_1__VAL_1 or MUX_wsiM_reqFifo_q_1$write_1__SEL_2 or MUX_wsiM_reqFifo_q_0$write_1__VAL_2 or WILL_FIRE_RL_wsiM_reqFifo_decCtr) begin case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_wsiM_reqFifo_both: + MUX_wsiM_reqFifo_q_1$write_1__SEL_1: wsiM_reqFifo_q_1$D_IN = MUX_wsiM_reqFifo_q_1$write_1__VAL_1; MUX_wsiM_reqFifo_q_1$write_1__SEL_2: wsiM_reqFifo_q_1$D_IN = MUX_wsiM_reqFifo_q_0$write_1__VAL_2; @@ -1160,8 +1160,9 @@ module mkBiasWorker4B(wciS0_Clk, endcase end assign wsiM_reqFifo_q_1$EN = - WILL_FIRE_RL_wsiM_reqFifo_both || - WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_c_r == 2'd1 || + WILL_FIRE_RL_wsiM_reqFifo_both && _dfoo5 || + WILL_FIRE_RL_wsiM_reqFifo_incCtr && + wsiM_reqFifo_cntr_r == 2'd1 || WILL_FIRE_RL_wsiM_reqFifo_decCtr ; // register wsiM_sThreadBusy_d @@ -1247,7 +1248,7 @@ module mkBiasWorker4B(wciS0_Clk, // register wsiS_reqFifo_levelsValid assign wsiS_reqFifo_levelsValid$D_IN = WILL_FIRE_RL_wsiS_reqFifo_reset ; assign wsiS_reqFifo_levelsValid$EN = - wsiM_reqFifo_c_r != 2'd2 && wsiS_reqFifo$EMPTY_N && + wsiM_reqFifo_cntr_r != 2'd2 && wsiS_reqFifo$EMPTY_N && wci_wslv_cState == 3'd2 || WILL_FIRE_RL_wsiS_reqFifo_enq || WILL_FIRE_RL_wsiS_reqFifo_reset ; @@ -1292,34 +1293,48 @@ module mkBiasWorker4B(wciS0_Clk, assign wsiS_reqFifo$CLR = 1'b0 ; // remaining internal signals - assign rdat__h11144 = hasDebugLogic ? { 16'd0, x__h11148 } : 32'd0 ; - assign rdat__h11244 = hasDebugLogic ? wsiS_extStatusW$wget[95:64] : 32'd0 ; - assign rdat__h11258 = hasDebugLogic ? wsiS_extStatusW$wget[63:32] : 32'd0 ; - assign rdat__h11266 = hasDebugLogic ? wsiS_extStatusW$wget[31:0] : 32'd0 ; - assign rdat__h11272 = hasDebugLogic ? wsiM_extStatusW$wget[95:64] : 32'd0 ; - assign rdat__h11286 = hasDebugLogic ? wsiM_extStatusW$wget[63:32] : 32'd0 ; - assign rdat__h11294 = hasDebugLogic ? wsiM_extStatusW$wget[31:0] : 32'd0 ; - assign x__h11148 = { wsiS_statusR, wsiM_statusR } ; - assign x_data__h10386 = wsiS_reqFifo$D_OUT[43:12] + biasValue ; + assign _dfoo1 = + wci_wslv_respF_cntr_r != 2'd2 || + wci_wslv_respF_cntr_r_8_MINUS_1___d27 == 2'd1 ; + assign _dfoo3 = + wci_wslv_respF_cntr_r != 2'd1 || + wci_wslv_respF_cntr_r_8_MINUS_1___d27 == 2'd0 ; + assign _dfoo5 = + wsiM_reqFifo_cntr_r != 2'd2 || + MUX_wsiM_reqFifo_cntr_r$write_1__VAL_1 == 2'd1 ; + assign _dfoo7 = + wsiM_reqFifo_cntr_r != 2'd1 || + MUX_wsiM_reqFifo_cntr_r$write_1__VAL_1 == 2'd0 ; + assign rdat__h10861 = hasDebugLogic ? { 16'd0, x__h10865 } : 32'd0 ; + assign rdat__h10961 = hasDebugLogic ? wsiS_extStatusW$wget[95:64] : 32'd0 ; + assign rdat__h10975 = hasDebugLogic ? wsiS_extStatusW$wget[63:32] : 32'd0 ; + assign rdat__h10983 = hasDebugLogic ? wsiS_extStatusW$wget[31:0] : 32'd0 ; + assign rdat__h10989 = hasDebugLogic ? wsiM_extStatusW$wget[95:64] : 32'd0 ; + assign rdat__h11003 = hasDebugLogic ? wsiM_extStatusW$wget[63:32] : 32'd0 ; + assign rdat__h11011 = hasDebugLogic ? wsiM_extStatusW$wget[31:0] : 32'd0 ; + assign wci_wslv_respF_cntr_r_8_MINUS_1___d27 = + wci_wslv_respF_cntr_r - 2'd1 ; + assign x__h10865 = { wsiS_statusR, wsiM_statusR } ; + assign x_data__h10099 = wsiS_reqFifo$D_OUT[43:12] + biasValue ; always@(wci_wslv_reqF$D_OUT or biasValue or controlReg or - rdat__h11144 or - rdat__h11244 or - rdat__h11258 or - rdat__h11266 or rdat__h11272 or rdat__h11286 or rdat__h11294) + rdat__h10861 or + rdat__h10961 or + rdat__h10975 or + rdat__h10983 or rdat__h10989 or rdat__h11003 or rdat__h11011) begin case (wci_wslv_reqF$D_OUT[39:32]) - 8'h0: _theResult____h11054 = biasValue; - 8'h04: _theResult____h11054 = controlReg; - 8'h20: _theResult____h11054 = rdat__h11144; - 8'h24: _theResult____h11054 = rdat__h11244; - 8'h28: _theResult____h11054 = rdat__h11258; - 8'h2C: _theResult____h11054 = rdat__h11266; - 8'h30: _theResult____h11054 = rdat__h11272; - 8'h34: _theResult____h11054 = rdat__h11286; - 8'h38: _theResult____h11054 = rdat__h11294; - default: _theResult____h11054 = 32'd0; + 8'h0: _theResult____h10771 = biasValue; + 8'h04: _theResult____h10771 = controlReg; + 8'h20: _theResult____h10771 = rdat__h10861; + 8'h24: _theResult____h10771 = rdat__h10961; + 8'h28: _theResult____h10771 = rdat__h10975; + 8'h2C: _theResult____h10771 = rdat__h10983; + 8'h30: _theResult____h10771 = rdat__h10989; + 8'h34: _theResult____h10771 = rdat__h11003; + 8'h38: _theResult____h10771 = rdat__h11011; + default: _theResult____h10771 = 32'd0; endcase end @@ -1336,7 +1351,7 @@ module mkBiasWorker4B(wciS0_Clk, wci_wslv_illegalEdge <= `BSV_ASSIGNMENT_DELAY 1'd0; wci_wslv_nState <= `BSV_ASSIGNMENT_DELAY 3'd0; wci_wslv_reqF_countReg <= `BSV_ASSIGNMENT_DELAY 2'd0; - wci_wslv_respF_c_r <= `BSV_ASSIGNMENT_DELAY 2'd0; + wci_wslv_respF_cntr_r <= `BSV_ASSIGNMENT_DELAY 2'd0; wci_wslv_respF_q_0 <= `BSV_ASSIGNMENT_DELAY 34'h0AAAAAAAA; wci_wslv_respF_q_1 <= `BSV_ASSIGNMENT_DELAY 34'h0AAAAAAAA; wci_wslv_sFlagReg <= `BSV_ASSIGNMENT_DELAY 1'd0; @@ -1347,7 +1362,7 @@ module mkBiasWorker4B(wciS0_Clk, wsiM_operateD <= `BSV_ASSIGNMENT_DELAY 1'd0; wsiM_pMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0; wsiM_peerIsReady <= `BSV_ASSIGNMENT_DELAY 1'd0; - wsiM_reqFifo_c_r <= `BSV_ASSIGNMENT_DELAY 2'd0; + wsiM_reqFifo_cntr_r <= `BSV_ASSIGNMENT_DELAY 2'd0; wsiM_reqFifo_q_0 <= `BSV_ASSIGNMENT_DELAY 61'h00000AAAAAAAAA00; wsiM_reqFifo_q_1 <= `BSV_ASSIGNMENT_DELAY 61'h00000AAAAAAAAA00; wsiM_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY 1'd1; @@ -1384,8 +1399,9 @@ module mkBiasWorker4B(wciS0_Clk, if (wci_wslv_reqF_countReg$EN) wci_wslv_reqF_countReg <= `BSV_ASSIGNMENT_DELAY wci_wslv_reqF_countReg$D_IN; - if (wci_wslv_respF_c_r$EN) - wci_wslv_respF_c_r <= `BSV_ASSIGNMENT_DELAY wci_wslv_respF_c_r$D_IN; + if (wci_wslv_respF_cntr_r$EN) + wci_wslv_respF_cntr_r <= `BSV_ASSIGNMENT_DELAY + wci_wslv_respF_cntr_r$D_IN; if (wci_wslv_respF_q_0$EN) wci_wslv_respF_q_0 <= `BSV_ASSIGNMENT_DELAY wci_wslv_respF_q_0$D_IN; if (wci_wslv_respF_q_1$EN) @@ -1407,8 +1423,9 @@ module mkBiasWorker4B(wciS0_Clk, wsiM_pMesgCount <= `BSV_ASSIGNMENT_DELAY wsiM_pMesgCount$D_IN; if (wsiM_peerIsReady$EN) wsiM_peerIsReady <= `BSV_ASSIGNMENT_DELAY wsiM_peerIsReady$D_IN; - if (wsiM_reqFifo_c_r$EN) - wsiM_reqFifo_c_r <= `BSV_ASSIGNMENT_DELAY wsiM_reqFifo_c_r$D_IN; + if (wsiM_reqFifo_cntr_r$EN) + wsiM_reqFifo_cntr_r <= `BSV_ASSIGNMENT_DELAY + wsiM_reqFifo_cntr_r$D_IN; if (wsiM_reqFifo_q_0$EN) wsiM_reqFifo_q_0 <= `BSV_ASSIGNMENT_DELAY wsiM_reqFifo_q_0$D_IN; if (wsiM_reqFifo_q_1$EN) @@ -1489,7 +1506,7 @@ module mkBiasWorker4B(wciS0_Clk, wci_wslv_isReset_isInReset = 1'h0; wci_wslv_nState = 3'h2; wci_wslv_reqF_countReg = 2'h2; - wci_wslv_respF_c_r = 2'h2; + wci_wslv_respF_cntr_r = 2'h2; wci_wslv_respF_q_0 = 34'h2AAAAAAAA; wci_wslv_respF_q_1 = 34'h2AAAAAAAA; wci_wslv_sFlagReg = 1'h0; @@ -1501,7 +1518,7 @@ module mkBiasWorker4B(wciS0_Clk, wsiM_operateD = 1'h0; wsiM_pMesgCount = 32'hAAAAAAAA; wsiM_peerIsReady = 1'h0; - wsiM_reqFifo_c_r = 2'h2; + wsiM_reqFifo_cntr_r = 2'h2; wsiM_reqFifo_q_0 = 61'h0AAAAAAAAAAAAAAA; wsiM_reqFifo_q_1 = 61'h0AAAAAAAAAAAAAAA; wsiM_sThreadBusy_d = 1'h0; @@ -1535,13 +1552,13 @@ module mkBiasWorker4B(wciS0_Clk, if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_start) begin - v__h3706 = $time; + v__h3574 = $time; #0; end if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_start) $display("[%0d]: %m: WCI ControlOp: Starting-transition edge:%x from:%x", - v__h3706, + v__h3574, wci_wslv_reqF$D_OUT[36:34], wci_wslv_cState); if (wciS0_MReset_n != `BSV_RESET_VALUE) @@ -1556,54 +1573,54 @@ module mkBiasWorker4B(wciS0_Clk, if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfwr) begin - v__h10915 = $time; + v__h10632 = $time; #0; end if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfwr) $display("[%0d]: %m: WCI CONFIG WRITE Addr:%0x BE:%0x Data:%0x", - v__h10915, + v__h10632, wci_wslv_reqF$D_OUT[63:32], wci_wslv_reqF$D_OUT[67:64], wci_wslv_reqF$D_OUT[31:0]); if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge) begin - v__h4025 = $time; + v__h3893 = $time; #0; end if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge) $display("[%0d]: %m: WCI ControlOp: ILLEGAL-EDGE Completed-transition edge:%x from:%x", - v__h4025, + v__h3893, wci_wslv_cEdge, wci_wslv_cState); if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && !wci_wslv_illegalEdge) begin - v__h3881 = $time; + v__h3749 = $time; #0; end if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && !wci_wslv_illegalEdge) $display("[%0d]: %m: WCI ControlOp: Completed-transition edge:%x from:%x to:%x", - v__h3881, + v__h3749, wci_wslv_cEdge, wci_wslv_cState, wci_wslv_nState); if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfrd) begin - v__h11070 = $time; + v__h10787 = $time; #0; end if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfrd) $display("[%0d]: %m: WCI CONFIG READ Addr:%0x BE:%0x Data:%0x", - v__h11070, + v__h10787, wci_wslv_reqF$D_OUT[63:32], wci_wslv_reqF$D_OUT[67:64], - _theResult____h11054); + _theResult____h10771); if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_OrE) $display("Error: \"bsv/wrk/BiasWorker.bsv\", line 67, column 28: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n"); diff --git a/rtl/mkBiasWorker8B.v b/rtl/mkBiasWorker8B.v index 9be41865..7158b191 100644 --- a/rtl/mkBiasWorker8B.v +++ b/rtl/mkBiasWorker8B.v @@ -1,7 +1,7 @@ // -// Generated by Bluespec Compiler, version 2012.09.beta1 (build 29570, 2012-09.11) +// Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Tue Dec 11 16:20:58 EST 2012 +// On Fri Jun 21 16:57:47 EDT 2013 // // // Ports: @@ -341,10 +341,10 @@ module mkBiasWorker8B(wciS0_Clk, wire [1 : 0] wci_wslv_reqF_countReg$D_IN; wire wci_wslv_reqF_countReg$EN; - // register wci_wslv_respF_c_r - reg [1 : 0] wci_wslv_respF_c_r; - wire [1 : 0] wci_wslv_respF_c_r$D_IN; - wire wci_wslv_respF_c_r$EN; + // register wci_wslv_respF_cntr_r + reg [1 : 0] wci_wslv_respF_cntr_r; + wire [1 : 0] wci_wslv_respF_cntr_r$D_IN; + wire wci_wslv_respF_cntr_r$EN; // register wci_wslv_respF_q_0 reg [33 : 0] wci_wslv_respF_q_0; @@ -395,10 +395,10 @@ module mkBiasWorker8B(wciS0_Clk, reg wsiM_peerIsReady; wire wsiM_peerIsReady$D_IN, wsiM_peerIsReady$EN; - // register wsiM_reqFifo_c_r - reg [1 : 0] wsiM_reqFifo_c_r; - wire [1 : 0] wsiM_reqFifo_c_r$D_IN; - wire wsiM_reqFifo_c_r$EN; + // register wsiM_reqFifo_cntr_r + reg [1 : 0] wsiM_reqFifo_cntr_r; + wire [1 : 0] wsiM_reqFifo_cntr_r$D_IN; + wire wsiM_reqFifo_cntr_r$EN; // register wsiM_reqFifo_q_0 reg [96 : 0] wsiM_reqFifo_q_0; @@ -533,34 +533,38 @@ module mkBiasWorker8B(wciS0_Clk, MUX_wci_wslv_respF_q_1$write_1__VAL_1, MUX_wci_wslv_respF_x_wire$wset_1__VAL_1, MUX_wci_wslv_respF_x_wire$wset_1__VAL_2; - wire [1 : 0] MUX_wci_wslv_respF_c_r$write_1__VAL_1, - MUX_wci_wslv_respF_c_r$write_1__VAL_2, - MUX_wsiM_reqFifo_c_r$write_1__VAL_1, - MUX_wsiM_reqFifo_c_r$write_1__VAL_2; + wire [1 : 0] MUX_wci_wslv_respF_cntr_r$write_1__VAL_2, + MUX_wsiM_reqFifo_cntr_r$write_1__VAL_1, + MUX_wsiM_reqFifo_cntr_r$write_1__VAL_2; wire MUX_biasValue$write_1__SEL_1, MUX_biasValue$write_1__SEL_2, MUX_controlReg$write_1__SEL_1, MUX_wci_wslv_illegalEdge$write_1__SEL_1, - MUX_wci_wslv_illegalEdge$write_1__SEL_2, - MUX_wci_wslv_illegalEdge$write_1__VAL_2, + MUX_wci_wslv_illegalEdge$write_1__VAL_1, + MUX_wci_wslv_respF_q_0$write_1__SEL_1, MUX_wci_wslv_respF_q_0$write_1__SEL_2, + MUX_wci_wslv_respF_q_1$write_1__SEL_1, MUX_wci_wslv_respF_q_1$write_1__SEL_2, + MUX_wsiM_reqFifo_q_0$write_1__SEL_1, MUX_wsiM_reqFifo_q_0$write_1__SEL_2, + MUX_wsiM_reqFifo_q_1$write_1__SEL_1, MUX_wsiM_reqFifo_q_1$write_1__SEL_2, MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3; // remaining internal signals - reg [63 : 0] v__h11111, v__h11266, v__h3706, v__h3881, v__h4025; - reg [31 : 0] _theResult____h11250; - wire [63 : 0] x_data__h10386; - wire [31 : 0] rdat__h11340, - rdat__h11440, - rdat__h11454, - rdat__h11462, - rdat__h11468, - rdat__h11482, - rdat__h11490; - wire [15 : 0] x__h11344; + reg [63 : 0] v__h10832, v__h10987, v__h3574, v__h3749, v__h3893; + reg [31 : 0] _theResult____h10971; + wire [63 : 0] x_data__h10099; + wire [31 : 0] rdat__h11061, + rdat__h11161, + rdat__h11175, + rdat__h11183, + rdat__h11189, + rdat__h11203, + rdat__h11211; + wire [15 : 0] x__h11065; + wire [1 : 0] wci_wslv_respF_cntr_r_8_MINUS_1___d27; + wire _dfoo1, _dfoo3, _dfoo5, _dfoo7; // value method wciS0_sResp assign wciS0_SResp = wci_wslv_respF_q_0[33:32] ; @@ -656,53 +660,45 @@ module mkBiasWorker8B(wciS0_Clk, // rule RL_wci_cfwr assign WILL_FIRE_RL_wci_cfwr = - wci_wslv_respF_c_r != 2'd2 && wci_wslv_reqF$EMPTY_N && + wci_wslv_respF_cntr_r != 2'd2 && wci_wslv_reqF$EMPTY_N && wci_wslv_wci_cfwr_pw$whas && !WILL_FIRE_RL_wci_wslv_ctl_op_start && !WILL_FIRE_RL_wci_wslv_ctl_op_complete ; // rule RL_wci_wslv_ctl_op_complete assign WILL_FIRE_RL_wci_wslv_ctl_op_complete = - wci_wslv_respF_c_r != 2'd2 && wci_wslv_ctlOpActive && + wci_wslv_respF_cntr_r != 2'd2 && wci_wslv_ctlOpActive && wci_wslv_ctlAckReg ; // rule RL_wci_cfrd assign WILL_FIRE_RL_wci_cfrd = - wci_wslv_respF_c_r != 2'd2 && wci_wslv_reqF$EMPTY_N && + wci_wslv_respF_cntr_r != 2'd2 && wci_wslv_reqF$EMPTY_N && wci_wslv_wci_cfrd_pw$whas && !WILL_FIRE_RL_wci_wslv_ctl_op_start && !WILL_FIRE_RL_wci_wslv_ctl_op_complete ; // rule RL_wci_wslv_respF_incCtr assign WILL_FIRE_RL_wci_wslv_respF_incCtr = - ((wci_wslv_respF_c_r == 2'd0) ? - wci_wslv_respF_x_wire$whas : - wci_wslv_respF_c_r != 2'd1 || wci_wslv_respF_x_wire$whas) && - wci_wslv_respF_enqueueing$whas && - !(wci_wslv_respF_c_r != 2'd0) ; + wci_wslv_respF_x_wire$whas && wci_wslv_respF_enqueueing$whas && + !(wci_wslv_respF_cntr_r != 2'd0) ; // rule RL_wci_wslv_respF_decCtr assign WILL_FIRE_RL_wci_wslv_respF_decCtr = - wci_wslv_respF_c_r != 2'd0 && !wci_wslv_respF_enqueueing$whas ; + wci_wslv_respF_cntr_r != 2'd0 && + !wci_wslv_respF_enqueueing$whas ; // rule RL_wci_wslv_respF_both assign WILL_FIRE_RL_wci_wslv_respF_both = - ((wci_wslv_respF_c_r == 2'd1) ? - wci_wslv_respF_x_wire$whas : - wci_wslv_respF_c_r != 2'd2 || wci_wslv_respF_x_wire$whas) && - wci_wslv_respF_c_r != 2'd0 && + wci_wslv_respF_x_wire$whas && wci_wslv_respF_cntr_r != 2'd0 && wci_wslv_respF_enqueueing$whas ; // rule RL_wsiM_reqFifo_deq assign WILL_FIRE_RL_wsiM_reqFifo_deq = - wsiM_reqFifo_c_r != 2'd0 && !wsiM_sThreadBusy_d ; + wsiM_reqFifo_cntr_r != 2'd0 && !wsiM_sThreadBusy_d ; // rule RL_wsiM_reqFifo_incCtr assign WILL_FIRE_RL_wsiM_reqFifo_incCtr = - ((wsiM_reqFifo_c_r == 2'd0) ? - MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 : - wsiM_reqFifo_c_r != 2'd1 || - MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3) && + MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 && MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 && !WILL_FIRE_RL_wsiM_reqFifo_deq ; @@ -713,10 +709,7 @@ module mkBiasWorker8B(wciS0_Clk, // rule RL_wsiM_reqFifo_both assign WILL_FIRE_RL_wsiM_reqFifo_both = - ((wsiM_reqFifo_c_r == 2'd1) ? - MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 : - wsiM_reqFifo_c_r != 2'd2 || - MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3) && + MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 && WILL_FIRE_RL_wsiM_reqFifo_deq && MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 ; @@ -741,8 +734,6 @@ module mkBiasWorker8B(wciS0_Clk, assign MUX_controlReg$write_1__SEL_1 = WILL_FIRE_RL_wci_cfwr && wci_wslv_reqF$D_OUT[39:32] == 8'h04 ; assign MUX_wci_wslv_illegalEdge$write_1__SEL_1 = - WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge ; - assign MUX_wci_wslv_illegalEdge$write_1__SEL_2 = WILL_FIRE_RL_wci_wslv_ctl_op_start && (wci_wslv_reqF$D_OUT[36:34] == 3'd0 && wci_wslv_cState != 3'd0 || wci_wslv_reqF$D_OUT[36:34] == 3'd1 && wci_wslv_cState != 3'd1 && @@ -755,27 +746,35 @@ module mkBiasWorker8B(wciS0_Clk, wci_wslv_reqF$D_OUT[36:34] == 3'd5 || wci_wslv_reqF$D_OUT[36:34] == 3'd6 || wci_wslv_reqF$D_OUT[36:34] == 3'd7) ; + assign MUX_wci_wslv_respF_q_0$write_1__SEL_1 = + WILL_FIRE_RL_wci_wslv_respF_both && _dfoo3 ; assign MUX_wci_wslv_respF_q_0$write_1__SEL_2 = WILL_FIRE_RL_wci_wslv_respF_incCtr && - wci_wslv_respF_c_r == 2'd0 ; + wci_wslv_respF_cntr_r == 2'd0 ; + assign MUX_wci_wslv_respF_q_1$write_1__SEL_1 = + WILL_FIRE_RL_wci_wslv_respF_both && _dfoo1 ; assign MUX_wci_wslv_respF_q_1$write_1__SEL_2 = WILL_FIRE_RL_wci_wslv_respF_incCtr && - wci_wslv_respF_c_r == 2'd1 ; + wci_wslv_respF_cntr_r == 2'd1 ; + assign MUX_wsiM_reqFifo_q_0$write_1__SEL_1 = + WILL_FIRE_RL_wsiM_reqFifo_both && _dfoo7 ; assign MUX_wsiM_reqFifo_q_0$write_1__SEL_2 = - WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_c_r == 2'd0 ; + WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_cntr_r == 2'd0 ; + assign MUX_wsiM_reqFifo_q_1$write_1__SEL_1 = + WILL_FIRE_RL_wsiM_reqFifo_both && _dfoo5 ; assign MUX_wsiM_reqFifo_q_1$write_1__SEL_2 = - WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_c_r == 2'd1 ; + WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_cntr_r == 2'd1 ; assign MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 = - wsiM_reqFifo_c_r != 2'd2 && wsiS_reqFifo$EMPTY_N && + wsiM_reqFifo_cntr_r != 2'd2 && wsiS_reqFifo$EMPTY_N && wci_wslv_cState == 3'd2 ; - assign MUX_wci_wslv_illegalEdge$write_1__VAL_2 = + assign MUX_wci_wslv_illegalEdge$write_1__VAL_1 = wci_wslv_reqF$D_OUT[36:34] != 3'd4 && wci_wslv_reqF$D_OUT[36:34] != 3'd5 && wci_wslv_reqF$D_OUT[36:34] != 3'd6 ; - assign MUX_wci_wslv_respF_c_r$write_1__VAL_1 = wci_wslv_respF_c_r + 2'd1 ; - assign MUX_wci_wslv_respF_c_r$write_1__VAL_2 = wci_wslv_respF_c_r - 2'd1 ; + assign MUX_wci_wslv_respF_cntr_r$write_1__VAL_2 = + wci_wslv_respF_cntr_r + 2'd1 ; assign MUX_wci_wslv_respF_q_0$write_1__VAL_1 = - (wci_wslv_respF_c_r == 2'd1) ? + (wci_wslv_respF_cntr_r == 2'd1) ? MUX_wci_wslv_respF_q_0$write_1__VAL_2 : wci_wslv_respF_q_1 ; always@(WILL_FIRE_RL_wci_wslv_ctl_op_complete or @@ -797,25 +796,25 @@ module mkBiasWorker8B(wciS0_Clk, endcase end assign MUX_wci_wslv_respF_q_1$write_1__VAL_1 = - (wci_wslv_respF_c_r == 2'd2) ? + (wci_wslv_respF_cntr_r == 2'd2) ? MUX_wci_wslv_respF_q_0$write_1__VAL_2 : 34'h0AAAAAAAA ; assign MUX_wci_wslv_respF_x_wire$wset_1__VAL_1 = wci_wslv_illegalEdge ? 34'h3C0DE4202 : 34'h1C0DE4201 ; assign MUX_wci_wslv_respF_x_wire$wset_1__VAL_2 = - { 2'd1, _theResult____h11250 } ; - assign MUX_wsiM_reqFifo_c_r$write_1__VAL_1 = wsiM_reqFifo_c_r + 2'd1 ; - assign MUX_wsiM_reqFifo_c_r$write_1__VAL_2 = wsiM_reqFifo_c_r - 2'd1 ; + { 2'd1, _theResult____h10971 } ; + assign MUX_wsiM_reqFifo_cntr_r$write_1__VAL_1 = wsiM_reqFifo_cntr_r - 2'd1 ; + assign MUX_wsiM_reqFifo_cntr_r$write_1__VAL_2 = wsiM_reqFifo_cntr_r + 2'd1 ; assign MUX_wsiM_reqFifo_q_0$write_1__VAL_1 = - (wsiM_reqFifo_c_r == 2'd1) ? + (wsiM_reqFifo_cntr_r == 2'd1) ? MUX_wsiM_reqFifo_q_0$write_1__VAL_2 : wsiM_reqFifo_q_1 ; assign MUX_wsiM_reqFifo_q_0$write_1__VAL_2 = { wsiS_reqFifo$D_OUT[96:80], - x_data__h10386, + x_data__h10099, wsiS_reqFifo$D_OUT[15:0] } ; assign MUX_wsiM_reqFifo_q_1$write_1__VAL_1 = - (wsiM_reqFifo_c_r == 2'd2) ? + (wsiM_reqFifo_cntr_r == 2'd2) ? MUX_wsiM_reqFifo_q_0$write_1__VAL_2 : 97'h00000AAAAAAAAAAAAAAAAAA00 ; @@ -890,7 +889,7 @@ module mkBiasWorker8B(wciS0_Clk, assign wci_wslv_respF_enqueueing$whas = WILL_FIRE_RL_wci_cfrd || WILL_FIRE_RL_wci_cfwr || WILL_FIRE_RL_wci_wslv_ctl_op_complete ; - assign wci_wslv_respF_dequeueing$whas = wci_wslv_respF_c_r != 2'd0 ; + assign wci_wslv_respF_dequeueing$whas = wci_wslv_respF_cntr_r != 2'd0 ; assign wci_wslv_sThreadBusy_pw$whas = 1'b0 ; assign wci_wslv_wci_cfwr_pw$whas = wci_wslv_reqF$EMPTY_N && wci_wslv_reqF$D_OUT[68] && @@ -960,11 +959,11 @@ module mkBiasWorker8B(wciS0_Clk, // register wci_wslv_illegalEdge assign wci_wslv_illegalEdge$D_IN = - !MUX_wci_wslv_illegalEdge$write_1__SEL_1 && - MUX_wci_wslv_illegalEdge$write_1__VAL_2 ; + MUX_wci_wslv_illegalEdge$write_1__SEL_1 && + MUX_wci_wslv_illegalEdge$write_1__VAL_1 ; assign wci_wslv_illegalEdge$EN = - WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge || - MUX_wci_wslv_illegalEdge$write_1__SEL_2 ; + MUX_wci_wslv_illegalEdge$write_1__SEL_1 || + WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge ; // register wci_wslv_isReset_isInReset assign wci_wslv_isReset_isInReset$D_IN = 1'd0 ; @@ -999,24 +998,24 @@ module mkBiasWorker8B(wciS0_Clk, (wci_wslv_wciReq$wget[71:69] != 3'd0) != wci_wslv_reqF_r_deq$whas ; - // register wci_wslv_respF_c_r - assign wci_wslv_respF_c_r$D_IN = - WILL_FIRE_RL_wci_wslv_respF_incCtr ? - MUX_wci_wslv_respF_c_r$write_1__VAL_1 : - MUX_wci_wslv_respF_c_r$write_1__VAL_2 ; - assign wci_wslv_respF_c_r$EN = - WILL_FIRE_RL_wci_wslv_respF_incCtr || - WILL_FIRE_RL_wci_wslv_respF_decCtr ; + // register wci_wslv_respF_cntr_r + assign wci_wslv_respF_cntr_r$D_IN = + WILL_FIRE_RL_wci_wslv_respF_decCtr ? + wci_wslv_respF_cntr_r_8_MINUS_1___d27 : + MUX_wci_wslv_respF_cntr_r$write_1__VAL_2 ; + assign wci_wslv_respF_cntr_r$EN = + WILL_FIRE_RL_wci_wslv_respF_decCtr || + WILL_FIRE_RL_wci_wslv_respF_incCtr ; // register wci_wslv_respF_q_0 - always@(WILL_FIRE_RL_wci_wslv_respF_both or + always@(MUX_wci_wslv_respF_q_0$write_1__SEL_1 or MUX_wci_wslv_respF_q_0$write_1__VAL_1 or MUX_wci_wslv_respF_q_0$write_1__SEL_2 or MUX_wci_wslv_respF_q_0$write_1__VAL_2 or WILL_FIRE_RL_wci_wslv_respF_decCtr or wci_wslv_respF_q_1) begin case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_wci_wslv_respF_both: + MUX_wci_wslv_respF_q_0$write_1__SEL_1: wci_wslv_respF_q_0$D_IN = MUX_wci_wslv_respF_q_0$write_1__VAL_1; MUX_wci_wslv_respF_q_0$write_1__SEL_2: wci_wslv_respF_q_0$D_IN = MUX_wci_wslv_respF_q_0$write_1__VAL_2; @@ -1027,20 +1026,20 @@ module mkBiasWorker8B(wciS0_Clk, endcase end assign wci_wslv_respF_q_0$EN = - WILL_FIRE_RL_wci_wslv_respF_both || + WILL_FIRE_RL_wci_wslv_respF_both && _dfoo3 || WILL_FIRE_RL_wci_wslv_respF_incCtr && - wci_wslv_respF_c_r == 2'd0 || + wci_wslv_respF_cntr_r == 2'd0 || WILL_FIRE_RL_wci_wslv_respF_decCtr ; // register wci_wslv_respF_q_1 - always@(WILL_FIRE_RL_wci_wslv_respF_both or + always@(MUX_wci_wslv_respF_q_1$write_1__SEL_1 or MUX_wci_wslv_respF_q_1$write_1__VAL_1 or MUX_wci_wslv_respF_q_1$write_1__SEL_2 or MUX_wci_wslv_respF_q_0$write_1__VAL_2 or WILL_FIRE_RL_wci_wslv_respF_decCtr) begin case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_wci_wslv_respF_both: + MUX_wci_wslv_respF_q_1$write_1__SEL_1: wci_wslv_respF_q_1$D_IN = MUX_wci_wslv_respF_q_1$write_1__VAL_1; MUX_wci_wslv_respF_q_1$write_1__SEL_2: wci_wslv_respF_q_1$D_IN = MUX_wci_wslv_respF_q_0$write_1__VAL_2; @@ -1051,9 +1050,9 @@ module mkBiasWorker8B(wciS0_Clk, endcase end assign wci_wslv_respF_q_1$EN = - WILL_FIRE_RL_wci_wslv_respF_both || + WILL_FIRE_RL_wci_wslv_respF_both && _dfoo1 || WILL_FIRE_RL_wci_wslv_respF_incCtr && - wci_wslv_respF_c_r == 2'd1 || + wci_wslv_respF_cntr_r == 2'd1 || WILL_FIRE_RL_wci_wslv_respF_decCtr ; // register wci_wslv_sFlagReg @@ -1108,24 +1107,24 @@ module mkBiasWorker8B(wciS0_Clk, assign wsiM_peerIsReady$D_IN = wsiM0_SReset_n ; assign wsiM_peerIsReady$EN = 1'd1 ; - // register wsiM_reqFifo_c_r - assign wsiM_reqFifo_c_r$D_IN = - WILL_FIRE_RL_wsiM_reqFifo_incCtr ? - MUX_wsiM_reqFifo_c_r$write_1__VAL_1 : - MUX_wsiM_reqFifo_c_r$write_1__VAL_2 ; - assign wsiM_reqFifo_c_r$EN = - WILL_FIRE_RL_wsiM_reqFifo_incCtr || - WILL_FIRE_RL_wsiM_reqFifo_decCtr ; + // register wsiM_reqFifo_cntr_r + assign wsiM_reqFifo_cntr_r$D_IN = + WILL_FIRE_RL_wsiM_reqFifo_decCtr ? + MUX_wsiM_reqFifo_cntr_r$write_1__VAL_1 : + MUX_wsiM_reqFifo_cntr_r$write_1__VAL_2 ; + assign wsiM_reqFifo_cntr_r$EN = + WILL_FIRE_RL_wsiM_reqFifo_decCtr || + WILL_FIRE_RL_wsiM_reqFifo_incCtr ; // register wsiM_reqFifo_q_0 - always@(WILL_FIRE_RL_wsiM_reqFifo_both or + always@(MUX_wsiM_reqFifo_q_0$write_1__SEL_1 or MUX_wsiM_reqFifo_q_0$write_1__VAL_1 or MUX_wsiM_reqFifo_q_0$write_1__SEL_2 or MUX_wsiM_reqFifo_q_0$write_1__VAL_2 or WILL_FIRE_RL_wsiM_reqFifo_decCtr or wsiM_reqFifo_q_1) begin case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_wsiM_reqFifo_both: + MUX_wsiM_reqFifo_q_0$write_1__SEL_1: wsiM_reqFifo_q_0$D_IN = MUX_wsiM_reqFifo_q_0$write_1__VAL_1; MUX_wsiM_reqFifo_q_0$write_1__SEL_2: wsiM_reqFifo_q_0$D_IN = MUX_wsiM_reqFifo_q_0$write_1__VAL_2; @@ -1136,19 +1135,20 @@ module mkBiasWorker8B(wciS0_Clk, endcase end assign wsiM_reqFifo_q_0$EN = - WILL_FIRE_RL_wsiM_reqFifo_both || - WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_c_r == 2'd0 || + WILL_FIRE_RL_wsiM_reqFifo_both && _dfoo7 || + WILL_FIRE_RL_wsiM_reqFifo_incCtr && + wsiM_reqFifo_cntr_r == 2'd0 || WILL_FIRE_RL_wsiM_reqFifo_decCtr ; // register wsiM_reqFifo_q_1 - always@(WILL_FIRE_RL_wsiM_reqFifo_both or + always@(MUX_wsiM_reqFifo_q_1$write_1__SEL_1 or MUX_wsiM_reqFifo_q_1$write_1__VAL_1 or MUX_wsiM_reqFifo_q_1$write_1__SEL_2 or MUX_wsiM_reqFifo_q_0$write_1__VAL_2 or WILL_FIRE_RL_wsiM_reqFifo_decCtr) begin case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_wsiM_reqFifo_both: + MUX_wsiM_reqFifo_q_1$write_1__SEL_1: wsiM_reqFifo_q_1$D_IN = MUX_wsiM_reqFifo_q_1$write_1__VAL_1; MUX_wsiM_reqFifo_q_1$write_1__SEL_2: wsiM_reqFifo_q_1$D_IN = MUX_wsiM_reqFifo_q_0$write_1__VAL_2; @@ -1159,8 +1159,9 @@ module mkBiasWorker8B(wciS0_Clk, endcase end assign wsiM_reqFifo_q_1$EN = - WILL_FIRE_RL_wsiM_reqFifo_both || - WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_c_r == 2'd1 || + WILL_FIRE_RL_wsiM_reqFifo_both && _dfoo5 || + WILL_FIRE_RL_wsiM_reqFifo_incCtr && + wsiM_reqFifo_cntr_r == 2'd1 || WILL_FIRE_RL_wsiM_reqFifo_decCtr ; // register wsiM_sThreadBusy_d @@ -1246,7 +1247,7 @@ module mkBiasWorker8B(wciS0_Clk, // register wsiS_reqFifo_levelsValid assign wsiS_reqFifo_levelsValid$D_IN = WILL_FIRE_RL_wsiS_reqFifo_reset ; assign wsiS_reqFifo_levelsValid$EN = - wsiM_reqFifo_c_r != 2'd2 && wsiS_reqFifo$EMPTY_N && + wsiM_reqFifo_cntr_r != 2'd2 && wsiS_reqFifo$EMPTY_N && wci_wslv_cState == 3'd2 || WILL_FIRE_RL_wsiS_reqFifo_enq || WILL_FIRE_RL_wsiS_reqFifo_reset ; @@ -1291,36 +1292,50 @@ module mkBiasWorker8B(wciS0_Clk, assign wsiS_reqFifo$CLR = 1'b0 ; // remaining internal signals - assign rdat__h11340 = hasDebugLogic ? { 16'd0, x__h11344 } : 32'd0 ; - assign rdat__h11440 = hasDebugLogic ? wsiS_extStatusW$wget[95:64] : 32'd0 ; - assign rdat__h11454 = hasDebugLogic ? wsiS_extStatusW$wget[63:32] : 32'd0 ; - assign rdat__h11462 = hasDebugLogic ? wsiS_extStatusW$wget[31:0] : 32'd0 ; - assign rdat__h11468 = hasDebugLogic ? wsiM_extStatusW$wget[95:64] : 32'd0 ; - assign rdat__h11482 = hasDebugLogic ? wsiM_extStatusW$wget[63:32] : 32'd0 ; - assign rdat__h11490 = hasDebugLogic ? wsiM_extStatusW$wget[31:0] : 32'd0 ; - assign x__h11344 = { wsiS_statusR, wsiM_statusR } ; - assign x_data__h10386 = + assign _dfoo1 = + wci_wslv_respF_cntr_r != 2'd2 || + wci_wslv_respF_cntr_r_8_MINUS_1___d27 == 2'd1 ; + assign _dfoo3 = + wci_wslv_respF_cntr_r != 2'd1 || + wci_wslv_respF_cntr_r_8_MINUS_1___d27 == 2'd0 ; + assign _dfoo5 = + wsiM_reqFifo_cntr_r != 2'd2 || + MUX_wsiM_reqFifo_cntr_r$write_1__VAL_1 == 2'd1 ; + assign _dfoo7 = + wsiM_reqFifo_cntr_r != 2'd1 || + MUX_wsiM_reqFifo_cntr_r$write_1__VAL_1 == 2'd0 ; + assign rdat__h11061 = hasDebugLogic ? { 16'd0, x__h11065 } : 32'd0 ; + assign rdat__h11161 = hasDebugLogic ? wsiS_extStatusW$wget[95:64] : 32'd0 ; + assign rdat__h11175 = hasDebugLogic ? wsiS_extStatusW$wget[63:32] : 32'd0 ; + assign rdat__h11183 = hasDebugLogic ? wsiS_extStatusW$wget[31:0] : 32'd0 ; + assign rdat__h11189 = hasDebugLogic ? wsiM_extStatusW$wget[95:64] : 32'd0 ; + assign rdat__h11203 = hasDebugLogic ? wsiM_extStatusW$wget[63:32] : 32'd0 ; + assign rdat__h11211 = hasDebugLogic ? wsiM_extStatusW$wget[31:0] : 32'd0 ; + assign wci_wslv_respF_cntr_r_8_MINUS_1___d27 = + wci_wslv_respF_cntr_r - 2'd1 ; + assign x__h11065 = { wsiS_statusR, wsiM_statusR } ; + assign x_data__h10099 = { wsiS_reqFifo$D_OUT[79:48] + biasValue, wsiS_reqFifo$D_OUT[47:16] + biasValue } ; always@(wci_wslv_reqF$D_OUT or biasValue or controlReg or - rdat__h11340 or - rdat__h11440 or - rdat__h11454 or - rdat__h11462 or rdat__h11468 or rdat__h11482 or rdat__h11490) + rdat__h11061 or + rdat__h11161 or + rdat__h11175 or + rdat__h11183 or rdat__h11189 or rdat__h11203 or rdat__h11211) begin case (wci_wslv_reqF$D_OUT[39:32]) - 8'h0: _theResult____h11250 = biasValue; - 8'h04: _theResult____h11250 = controlReg; - 8'h20: _theResult____h11250 = rdat__h11340; - 8'h24: _theResult____h11250 = rdat__h11440; - 8'h28: _theResult____h11250 = rdat__h11454; - 8'h2C: _theResult____h11250 = rdat__h11462; - 8'h30: _theResult____h11250 = rdat__h11468; - 8'h34: _theResult____h11250 = rdat__h11482; - 8'h38: _theResult____h11250 = rdat__h11490; - default: _theResult____h11250 = 32'd0; + 8'h0: _theResult____h10971 = biasValue; + 8'h04: _theResult____h10971 = controlReg; + 8'h20: _theResult____h10971 = rdat__h11061; + 8'h24: _theResult____h10971 = rdat__h11161; + 8'h28: _theResult____h10971 = rdat__h11175; + 8'h2C: _theResult____h10971 = rdat__h11183; + 8'h30: _theResult____h10971 = rdat__h11189; + 8'h34: _theResult____h10971 = rdat__h11203; + 8'h38: _theResult____h10971 = rdat__h11211; + default: _theResult____h10971 = 32'd0; endcase end @@ -1337,7 +1352,7 @@ module mkBiasWorker8B(wciS0_Clk, wci_wslv_illegalEdge <= `BSV_ASSIGNMENT_DELAY 1'd0; wci_wslv_nState <= `BSV_ASSIGNMENT_DELAY 3'd0; wci_wslv_reqF_countReg <= `BSV_ASSIGNMENT_DELAY 2'd0; - wci_wslv_respF_c_r <= `BSV_ASSIGNMENT_DELAY 2'd0; + wci_wslv_respF_cntr_r <= `BSV_ASSIGNMENT_DELAY 2'd0; wci_wslv_respF_q_0 <= `BSV_ASSIGNMENT_DELAY 34'h0AAAAAAAA; wci_wslv_respF_q_1 <= `BSV_ASSIGNMENT_DELAY 34'h0AAAAAAAA; wci_wslv_sFlagReg <= `BSV_ASSIGNMENT_DELAY 1'd0; @@ -1348,7 +1363,7 @@ module mkBiasWorker8B(wciS0_Clk, wsiM_operateD <= `BSV_ASSIGNMENT_DELAY 1'd0; wsiM_pMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0; wsiM_peerIsReady <= `BSV_ASSIGNMENT_DELAY 1'd0; - wsiM_reqFifo_c_r <= `BSV_ASSIGNMENT_DELAY 2'd0; + wsiM_reqFifo_cntr_r <= `BSV_ASSIGNMENT_DELAY 2'd0; wsiM_reqFifo_q_0 <= `BSV_ASSIGNMENT_DELAY 97'h00000AAAAAAAAAAAAAAAAAA00; wsiM_reqFifo_q_1 <= `BSV_ASSIGNMENT_DELAY @@ -1387,8 +1402,9 @@ module mkBiasWorker8B(wciS0_Clk, if (wci_wslv_reqF_countReg$EN) wci_wslv_reqF_countReg <= `BSV_ASSIGNMENT_DELAY wci_wslv_reqF_countReg$D_IN; - if (wci_wslv_respF_c_r$EN) - wci_wslv_respF_c_r <= `BSV_ASSIGNMENT_DELAY wci_wslv_respF_c_r$D_IN; + if (wci_wslv_respF_cntr_r$EN) + wci_wslv_respF_cntr_r <= `BSV_ASSIGNMENT_DELAY + wci_wslv_respF_cntr_r$D_IN; if (wci_wslv_respF_q_0$EN) wci_wslv_respF_q_0 <= `BSV_ASSIGNMENT_DELAY wci_wslv_respF_q_0$D_IN; if (wci_wslv_respF_q_1$EN) @@ -1410,8 +1426,9 @@ module mkBiasWorker8B(wciS0_Clk, wsiM_pMesgCount <= `BSV_ASSIGNMENT_DELAY wsiM_pMesgCount$D_IN; if (wsiM_peerIsReady$EN) wsiM_peerIsReady <= `BSV_ASSIGNMENT_DELAY wsiM_peerIsReady$D_IN; - if (wsiM_reqFifo_c_r$EN) - wsiM_reqFifo_c_r <= `BSV_ASSIGNMENT_DELAY wsiM_reqFifo_c_r$D_IN; + if (wsiM_reqFifo_cntr_r$EN) + wsiM_reqFifo_cntr_r <= `BSV_ASSIGNMENT_DELAY + wsiM_reqFifo_cntr_r$D_IN; if (wsiM_reqFifo_q_0$EN) wsiM_reqFifo_q_0 <= `BSV_ASSIGNMENT_DELAY wsiM_reqFifo_q_0$D_IN; if (wsiM_reqFifo_q_1$EN) @@ -1492,7 +1509,7 @@ module mkBiasWorker8B(wciS0_Clk, wci_wslv_isReset_isInReset = 1'h0; wci_wslv_nState = 3'h2; wci_wslv_reqF_countReg = 2'h2; - wci_wslv_respF_c_r = 2'h2; + wci_wslv_respF_cntr_r = 2'h2; wci_wslv_respF_q_0 = 34'h2AAAAAAAA; wci_wslv_respF_q_1 = 34'h2AAAAAAAA; wci_wslv_sFlagReg = 1'h0; @@ -1504,7 +1521,7 @@ module mkBiasWorker8B(wciS0_Clk, wsiM_operateD = 1'h0; wsiM_pMesgCount = 32'hAAAAAAAA; wsiM_peerIsReady = 1'h0; - wsiM_reqFifo_c_r = 2'h2; + wsiM_reqFifo_cntr_r = 2'h2; wsiM_reqFifo_q_0 = 97'h0AAAAAAAAAAAAAAAAAAAAAAAA; wsiM_reqFifo_q_1 = 97'h0AAAAAAAAAAAAAAAAAAAAAAAA; wsiM_sThreadBusy_d = 1'h0; @@ -1538,13 +1555,13 @@ module mkBiasWorker8B(wciS0_Clk, if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_start) begin - v__h3706 = $time; + v__h3574 = $time; #0; end if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_start) $display("[%0d]: %m: WCI ControlOp: Starting-transition edge:%x from:%x", - v__h3706, + v__h3574, wci_wslv_reqF$D_OUT[36:34], wci_wslv_cState); if (wciS0_MReset_n != `BSV_RESET_VALUE) @@ -1559,54 +1576,54 @@ module mkBiasWorker8B(wciS0_Clk, if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfwr) begin - v__h11111 = $time; + v__h10832 = $time; #0; end if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfwr) $display("[%0d]: %m: WCI CONFIG WRITE Addr:%0x BE:%0x Data:%0x", - v__h11111, + v__h10832, wci_wslv_reqF$D_OUT[63:32], wci_wslv_reqF$D_OUT[67:64], wci_wslv_reqF$D_OUT[31:0]); if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge) begin - v__h4025 = $time; + v__h3893 = $time; #0; end if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge) $display("[%0d]: %m: WCI ControlOp: ILLEGAL-EDGE Completed-transition edge:%x from:%x", - v__h4025, + v__h3893, wci_wslv_cEdge, wci_wslv_cState); if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && !wci_wslv_illegalEdge) begin - v__h3881 = $time; + v__h3749 = $time; #0; end if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && !wci_wslv_illegalEdge) $display("[%0d]: %m: WCI ControlOp: Completed-transition edge:%x from:%x to:%x", - v__h3881, + v__h3749, wci_wslv_cEdge, wci_wslv_cState, wci_wslv_nState); if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfrd) begin - v__h11266 = $time; + v__h10987 = $time; #0; end if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfrd) $display("[%0d]: %m: WCI CONFIG READ Addr:%0x BE:%0x Data:%0x", - v__h11266, + v__h10987, wci_wslv_reqF$D_OUT[63:32], wci_wslv_reqF$D_OUT[67:64], - _theResult____h11250); + _theResult____h10971); if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_OrE) $display("Error: \"bsv/wrk/BiasWorker.bsv\", line 67, column 28: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n"); diff --git a/rtl/mkCTop16B.v b/rtl/mkCTop16B.v index c91e1c49..17b4a043 100644 --- a/rtl/mkCTop16B.v +++ b/rtl/mkCTop16B.v @@ -1,7 +1,7 @@ // -// Generated by Bluespec Compiler, version 2012.09.beta1 (build 29570, 2012-09.11) +// Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Wed Nov 28 10:39:19 EST 2012 +// On Fri Jun 21 17:01:14 EDT 2013 // // // Ports: @@ -711,54 +711,54 @@ module mkCTop16B(pciDevice, wsi_s_adc_SThreadBusy; // inlined wires - wire wtiM_peerIsReady_1$wget, - wtiM_peerIsReady_1$whas, - wtiM_peerIsReady_1_2$wget, - wtiM_peerIsReady_1_2$whas, - wtiM_peerIsReady_2_1$wget, - wtiM_peerIsReady_2_1$whas, - wtiM_sThreadBusy_pw$whas, - wtiM_sThreadBusy_pw_1$whas, - wtiM_sThreadBusy_pw_2$whas; - - // register wtiM_nowReq - reg [66 : 0] wtiM_nowReq; - wire [66 : 0] wtiM_nowReq$D_IN; - wire wtiM_nowReq$EN; - - // register wtiM_nowReq_1 - reg [66 : 0] wtiM_nowReq_1; - wire [66 : 0] wtiM_nowReq_1$D_IN; - wire wtiM_nowReq_1$EN; - - // register wtiM_nowReq_2 - reg [66 : 0] wtiM_nowReq_2; - wire [66 : 0] wtiM_nowReq_2$D_IN; - wire wtiM_nowReq_2$EN; - - // register wtiM_peerIsReady - reg wtiM_peerIsReady; - wire wtiM_peerIsReady$D_IN, wtiM_peerIsReady$EN; - - // register wtiM_peerIsReady_1_1 - reg wtiM_peerIsReady_1_1; - wire wtiM_peerIsReady_1_1$D_IN, wtiM_peerIsReady_1_1$EN; - - // register wtiM_peerIsReady_2 - reg wtiM_peerIsReady_2; - wire wtiM_peerIsReady_2$D_IN, wtiM_peerIsReady_2$EN; - - // register wtiM_sThreadBusy_d - reg wtiM_sThreadBusy_d; - wire wtiM_sThreadBusy_d$D_IN, wtiM_sThreadBusy_d$EN; - - // register wtiM_sThreadBusy_d_1 - reg wtiM_sThreadBusy_d_1; - wire wtiM_sThreadBusy_d_1$D_IN, wtiM_sThreadBusy_d_1$EN; - - // register wtiM_sThreadBusy_d_2 - reg wtiM_sThreadBusy_d_2; - wire wtiM_sThreadBusy_d_2$D_IN, wtiM_sThreadBusy_d_2$EN; + wire wtiM_0_peerIsReady_1$wget, + wtiM_0_peerIsReady_1$whas, + wtiM_0_sThreadBusy_pw$whas, + wtiM_1_peerIsReady_1$wget, + wtiM_1_peerIsReady_1$whas, + wtiM_1_sThreadBusy_pw$whas, + wtiM_2_peerIsReady_1$wget, + wtiM_2_peerIsReady_1$whas, + wtiM_2_sThreadBusy_pw$whas; + + // register wtiM_0_nowReq + reg [66 : 0] wtiM_0_nowReq; + wire [66 : 0] wtiM_0_nowReq$D_IN; + wire wtiM_0_nowReq$EN; + + // register wtiM_0_peerIsReady + reg wtiM_0_peerIsReady; + wire wtiM_0_peerIsReady$D_IN, wtiM_0_peerIsReady$EN; + + // register wtiM_0_sThreadBusy_d + reg wtiM_0_sThreadBusy_d; + wire wtiM_0_sThreadBusy_d$D_IN, wtiM_0_sThreadBusy_d$EN; + + // register wtiM_1_nowReq + reg [66 : 0] wtiM_1_nowReq; + wire [66 : 0] wtiM_1_nowReq$D_IN; + wire wtiM_1_nowReq$EN; + + // register wtiM_1_peerIsReady + reg wtiM_1_peerIsReady; + wire wtiM_1_peerIsReady$D_IN, wtiM_1_peerIsReady$EN; + + // register wtiM_1_sThreadBusy_d + reg wtiM_1_sThreadBusy_d; + wire wtiM_1_sThreadBusy_d$D_IN, wtiM_1_sThreadBusy_d$EN; + + // register wtiM_2_nowReq + reg [66 : 0] wtiM_2_nowReq; + wire [66 : 0] wtiM_2_nowReq$D_IN; + wire wtiM_2_nowReq$EN; + + // register wtiM_2_peerIsReady + reg wtiM_2_peerIsReady; + wire wtiM_2_peerIsReady$D_IN, wtiM_2_peerIsReady$EN; + + // register wtiM_2_sThreadBusy_d + reg wtiM_2_sThreadBusy_d; + wire wtiM_2_sThreadBusy_d$D_IN, wtiM_2_sThreadBusy_d$EN; // ports of submodule app wire [511 : 0] app$uuid; @@ -1688,51 +1688,51 @@ module mkCTop16B(pciDevice, .RST_N_wci_m_12(inf$RST_N_wci_m_12)); // inlined wires - assign wtiM_peerIsReady_1$wget = 1'd1 ; - assign wtiM_peerIsReady_1$whas = app$wti_s_0_SReset_n ; - assign wtiM_peerIsReady_1_2$wget = 1'd1 ; - assign wtiM_peerIsReady_1_2$whas = app$wti_s_1_SReset_n ; - assign wtiM_peerIsReady_2_1$wget = 1'd1 ; - assign wtiM_peerIsReady_2_1$whas = app$wti_s_2_SReset_n ; - assign wtiM_sThreadBusy_pw$whas = app$wti_s_0_SThreadBusy ; - assign wtiM_sThreadBusy_pw_1$whas = app$wti_s_1_SThreadBusy ; - assign wtiM_sThreadBusy_pw_2$whas = app$wti_s_2_SThreadBusy ; - - // register wtiM_nowReq - assign wtiM_nowReq$D_IN = { 3'd1, ctNow$dD_OUT } ; - assign wtiM_nowReq$EN = 1'd1 ; - - // register wtiM_nowReq_1 - assign wtiM_nowReq_1$D_IN = wtiM_nowReq$D_IN ; - assign wtiM_nowReq_1$EN = 1'd1 ; - - // register wtiM_nowReq_2 - assign wtiM_nowReq_2$D_IN = wtiM_nowReq$D_IN ; - assign wtiM_nowReq_2$EN = 1'd1 ; - - // register wtiM_peerIsReady - assign wtiM_peerIsReady$D_IN = app$wti_s_0_SReset_n ; - assign wtiM_peerIsReady$EN = 1'd1 ; - - // register wtiM_peerIsReady_1_1 - assign wtiM_peerIsReady_1_1$D_IN = app$wti_s_1_SReset_n ; - assign wtiM_peerIsReady_1_1$EN = 1'd1 ; - - // register wtiM_peerIsReady_2 - assign wtiM_peerIsReady_2$D_IN = app$wti_s_2_SReset_n ; - assign wtiM_peerIsReady_2$EN = 1'd1 ; - - // register wtiM_sThreadBusy_d - assign wtiM_sThreadBusy_d$D_IN = app$wti_s_0_SThreadBusy ; - assign wtiM_sThreadBusy_d$EN = 1'd1 ; - - // register wtiM_sThreadBusy_d_1 - assign wtiM_sThreadBusy_d_1$D_IN = app$wti_s_1_SThreadBusy ; - assign wtiM_sThreadBusy_d_1$EN = 1'd1 ; - - // register wtiM_sThreadBusy_d_2 - assign wtiM_sThreadBusy_d_2$D_IN = app$wti_s_2_SThreadBusy ; - assign wtiM_sThreadBusy_d_2$EN = 1'd1 ; + assign wtiM_0_peerIsReady_1$wget = 1'd1 ; + assign wtiM_0_peerIsReady_1$whas = app$wti_s_0_SReset_n ; + assign wtiM_1_peerIsReady_1$wget = 1'd1 ; + assign wtiM_1_peerIsReady_1$whas = app$wti_s_1_SReset_n ; + assign wtiM_2_peerIsReady_1$wget = 1'd1 ; + assign wtiM_2_peerIsReady_1$whas = app$wti_s_2_SReset_n ; + assign wtiM_0_sThreadBusy_pw$whas = app$wti_s_0_SThreadBusy ; + assign wtiM_1_sThreadBusy_pw$whas = app$wti_s_1_SThreadBusy ; + assign wtiM_2_sThreadBusy_pw$whas = app$wti_s_2_SThreadBusy ; + + // register wtiM_0_nowReq + assign wtiM_0_nowReq$D_IN = { 3'd1, ctNow$dD_OUT } ; + assign wtiM_0_nowReq$EN = 1'd1 ; + + // register wtiM_0_peerIsReady + assign wtiM_0_peerIsReady$D_IN = app$wti_s_0_SReset_n ; + assign wtiM_0_peerIsReady$EN = 1'd1 ; + + // register wtiM_0_sThreadBusy_d + assign wtiM_0_sThreadBusy_d$D_IN = app$wti_s_0_SThreadBusy ; + assign wtiM_0_sThreadBusy_d$EN = 1'd1 ; + + // register wtiM_1_nowReq + assign wtiM_1_nowReq$D_IN = wtiM_0_nowReq$D_IN ; + assign wtiM_1_nowReq$EN = 1'd1 ; + + // register wtiM_1_peerIsReady + assign wtiM_1_peerIsReady$D_IN = app$wti_s_1_SReset_n ; + assign wtiM_1_peerIsReady$EN = 1'd1 ; + + // register wtiM_1_sThreadBusy_d + assign wtiM_1_sThreadBusy_d$D_IN = app$wti_s_1_SThreadBusy ; + assign wtiM_1_sThreadBusy_d$EN = 1'd1 ; + + // register wtiM_2_nowReq + assign wtiM_2_nowReq$D_IN = wtiM_0_nowReq$D_IN ; + assign wtiM_2_nowReq$EN = 1'd1 ; + + // register wtiM_2_peerIsReady + assign wtiM_2_peerIsReady$D_IN = app$wti_s_2_SReset_n ; + assign wtiM_2_peerIsReady$EN = 1'd1 ; + + // register wtiM_2_sThreadBusy_d + assign wtiM_2_sThreadBusy_d$D_IN = app$wti_s_2_SThreadBusy ; + assign wtiM_2_sThreadBusy_d$EN = 1'd1 ; // submodule app assign app$wci_s_0_MAddr = inf$wci_m_0_MAddr ; @@ -1796,14 +1796,15 @@ module mkCTop16B(pciDevice, assign app$wsi_s_adc_MCmd = 3'h0 ; assign app$wsi_s_adc_MData = 128'h0 ; assign app$wsi_s_adc_MReqInfo = 8'h0 ; - assign app$wti_s_0_MCmd = wtiM_sThreadBusy_d ? 3'd0 : wtiM_nowReq[66:64] ; - assign app$wti_s_0_MData = wtiM_nowReq[63:0] ; + assign app$wti_s_0_MCmd = + wtiM_0_sThreadBusy_d ? 3'd0 : wtiM_0_nowReq[66:64] ; + assign app$wti_s_0_MData = wtiM_0_nowReq[63:0] ; assign app$wti_s_1_MCmd = - wtiM_sThreadBusy_d_1 ? 3'd0 : wtiM_nowReq_1[66:64] ; - assign app$wti_s_1_MData = wtiM_nowReq_1[63:0] ; + wtiM_1_sThreadBusy_d ? 3'd0 : wtiM_1_nowReq[66:64] ; + assign app$wti_s_1_MData = wtiM_1_nowReq[63:0] ; assign app$wti_s_2_MCmd = - wtiM_sThreadBusy_d_2 ? 3'd0 : wtiM_nowReq_2[66:64] ; - assign app$wti_s_2_MData = wtiM_nowReq_2[63:0] ; + wtiM_2_sThreadBusy_d ? 3'd0 : wtiM_2_nowReq[66:64] ; + assign app$wti_s_2_MData = wtiM_2_nowReq[63:0] ; assign app$wmiM0_SThreadBusy = inf$wmiDP0_SThreadBusy ; assign app$wmiM0_SDataThreadBusy = inf$wmiDP0_SDataThreadBusy ; assign app$wmiM0_SRespLast = inf$wmiDP0_SRespLast ; @@ -1918,39 +1919,39 @@ module mkCTop16B(pciDevice, begin if (RST_N == `BSV_RESET_VALUE) begin - wtiM_nowReq <= `BSV_ASSIGNMENT_DELAY 67'd0; - wtiM_nowReq_1 <= `BSV_ASSIGNMENT_DELAY 67'd0; - wtiM_nowReq_2 <= `BSV_ASSIGNMENT_DELAY 67'd0; - wtiM_peerIsReady <= `BSV_ASSIGNMENT_DELAY 1'd0; - wtiM_peerIsReady_1_1 <= `BSV_ASSIGNMENT_DELAY 1'd0; - wtiM_peerIsReady_2 <= `BSV_ASSIGNMENT_DELAY 1'd0; - wtiM_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY 1'd1; - wtiM_sThreadBusy_d_1 <= `BSV_ASSIGNMENT_DELAY 1'd1; - wtiM_sThreadBusy_d_2 <= `BSV_ASSIGNMENT_DELAY 1'd1; + wtiM_0_nowReq <= `BSV_ASSIGNMENT_DELAY 67'd0; + wtiM_0_peerIsReady <= `BSV_ASSIGNMENT_DELAY 1'd0; + wtiM_0_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY 1'd1; + wtiM_1_nowReq <= `BSV_ASSIGNMENT_DELAY 67'd0; + wtiM_1_peerIsReady <= `BSV_ASSIGNMENT_DELAY 1'd0; + wtiM_1_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY 1'd1; + wtiM_2_nowReq <= `BSV_ASSIGNMENT_DELAY 67'd0; + wtiM_2_peerIsReady <= `BSV_ASSIGNMENT_DELAY 1'd0; + wtiM_2_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY 1'd1; end else begin - if (wtiM_nowReq$EN) - wtiM_nowReq <= `BSV_ASSIGNMENT_DELAY wtiM_nowReq$D_IN; - if (wtiM_nowReq_1$EN) - wtiM_nowReq_1 <= `BSV_ASSIGNMENT_DELAY wtiM_nowReq_1$D_IN; - if (wtiM_nowReq_2$EN) - wtiM_nowReq_2 <= `BSV_ASSIGNMENT_DELAY wtiM_nowReq_2$D_IN; - if (wtiM_peerIsReady$EN) - wtiM_peerIsReady <= `BSV_ASSIGNMENT_DELAY wtiM_peerIsReady$D_IN; - if (wtiM_peerIsReady_1_1$EN) - wtiM_peerIsReady_1_1 <= `BSV_ASSIGNMENT_DELAY - wtiM_peerIsReady_1_1$D_IN; - if (wtiM_peerIsReady_2$EN) - wtiM_peerIsReady_2 <= `BSV_ASSIGNMENT_DELAY wtiM_peerIsReady_2$D_IN; - if (wtiM_sThreadBusy_d$EN) - wtiM_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY wtiM_sThreadBusy_d$D_IN; - if (wtiM_sThreadBusy_d_1$EN) - wtiM_sThreadBusy_d_1 <= `BSV_ASSIGNMENT_DELAY - wtiM_sThreadBusy_d_1$D_IN; - if (wtiM_sThreadBusy_d_2$EN) - wtiM_sThreadBusy_d_2 <= `BSV_ASSIGNMENT_DELAY - wtiM_sThreadBusy_d_2$D_IN; + if (wtiM_0_nowReq$EN) + wtiM_0_nowReq <= `BSV_ASSIGNMENT_DELAY wtiM_0_nowReq$D_IN; + if (wtiM_0_peerIsReady$EN) + wtiM_0_peerIsReady <= `BSV_ASSIGNMENT_DELAY wtiM_0_peerIsReady$D_IN; + if (wtiM_0_sThreadBusy_d$EN) + wtiM_0_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY + wtiM_0_sThreadBusy_d$D_IN; + if (wtiM_1_nowReq$EN) + wtiM_1_nowReq <= `BSV_ASSIGNMENT_DELAY wtiM_1_nowReq$D_IN; + if (wtiM_1_peerIsReady$EN) + wtiM_1_peerIsReady <= `BSV_ASSIGNMENT_DELAY wtiM_1_peerIsReady$D_IN; + if (wtiM_1_sThreadBusy_d$EN) + wtiM_1_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY + wtiM_1_sThreadBusy_d$D_IN; + if (wtiM_2_nowReq$EN) + wtiM_2_nowReq <= `BSV_ASSIGNMENT_DELAY wtiM_2_nowReq$D_IN; + if (wtiM_2_peerIsReady$EN) + wtiM_2_peerIsReady <= `BSV_ASSIGNMENT_DELAY wtiM_2_peerIsReady$D_IN; + if (wtiM_2_sThreadBusy_d$EN) + wtiM_2_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY + wtiM_2_sThreadBusy_d$D_IN; end end @@ -1959,15 +1960,15 @@ module mkCTop16B(pciDevice, `else // not BSV_NO_INITIAL_BLOCKS initial begin - wtiM_nowReq = 67'h2AAAAAAAAAAAAAAAA; - wtiM_nowReq_1 = 67'h2AAAAAAAAAAAAAAAA; - wtiM_nowReq_2 = 67'h2AAAAAAAAAAAAAAAA; - wtiM_peerIsReady = 1'h0; - wtiM_peerIsReady_1_1 = 1'h0; - wtiM_peerIsReady_2 = 1'h0; - wtiM_sThreadBusy_d = 1'h0; - wtiM_sThreadBusy_d_1 = 1'h0; - wtiM_sThreadBusy_d_2 = 1'h0; + wtiM_0_nowReq = 67'h2AAAAAAAAAAAAAAAA; + wtiM_0_peerIsReady = 1'h0; + wtiM_0_sThreadBusy_d = 1'h0; + wtiM_1_nowReq = 67'h2AAAAAAAAAAAAAAAA; + wtiM_1_peerIsReady = 1'h0; + wtiM_1_sThreadBusy_d = 1'h0; + wtiM_2_nowReq = 67'h2AAAAAAAAAAAAAAAA; + wtiM_2_peerIsReady = 1'h0; + wtiM_2_sThreadBusy_d = 1'h0; end `endif // BSV_NO_INITIAL_BLOCKS // synopsys translate_on diff --git a/rtl/mkCTop4B.v b/rtl/mkCTop4B.v index 4e61ab1e..7ab01518 100644 --- a/rtl/mkCTop4B.v +++ b/rtl/mkCTop4B.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2012.09.beta1 (build 29570, 2012-09.11) // -// On Tue Dec 11 16:21:50 EST 2012 +// On Tue Jan 1 09:13:41 EST 2013 // // // Ports: @@ -1296,7 +1296,7 @@ module mkCTop4B(pciDevice, assign gps_ppsSyncOut = inf$gps_ppsSyncOut ; // submodule app - mkOCApp4B #(.hasDebugLogic(1'd0)) app(.RST_N_rst_0(inf$RST_N_wci_m_0), + mkOCApp4B #(.hasDebugLogic(1'd1)) app(.RST_N_rst_0(inf$RST_N_wci_m_0), .RST_N_rst_1(inf$RST_N_wci_m_1), .RST_N_rst_2(inf$RST_N_wci_m_2), .RST_N_rst_3(inf$RST_N_wci_m_3), diff --git a/rtl/mkDelayWorker16B.v b/rtl/mkDelayWorker16B.v index fe3bc66d..8ec30fbd 100644 --- a/rtl/mkDelayWorker16B.v +++ b/rtl/mkDelayWorker16B.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2012.09.beta1 (build 29570, 2012-09.11) // -// On Wed Nov 28 10:35:13 EST 2012 +// On Tue Jan 22 07:32:46 EST 2013 // // // Ports: diff --git a/rtl/mkDelayWorker32B.v b/rtl/mkDelayWorker32B.v index 454361ad..f1841a56 100644 --- a/rtl/mkDelayWorker32B.v +++ b/rtl/mkDelayWorker32B.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2012.09.beta1 (build 29570, 2012-09.11) // -// On Wed Nov 28 10:35:16 EST 2012 +// On Tue Jan 22 07:32:48 EST 2013 // // // Ports: diff --git a/rtl/mkDelayWorker4B.v b/rtl/mkDelayWorker4B.v index eaf8cb43..9a9d7ed7 100644 --- a/rtl/mkDelayWorker4B.v +++ b/rtl/mkDelayWorker4B.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2012.09.beta1 (build 29570, 2012-09.11) // -// On Wed Nov 28 10:35:08 EST 2012 +// On Tue Jan 22 07:32:43 EST 2013 // // // Ports: diff --git a/rtl/mkDelayWorker8B.v b/rtl/mkDelayWorker8B.v index 46b95813..ac1a8806 100644 --- a/rtl/mkDelayWorker8B.v +++ b/rtl/mkDelayWorker8B.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2012.09.beta1 (build 29570, 2012-09.11) // -// On Wed Nov 28 10:35:11 EST 2012 +// On Tue Jan 22 07:32:45 EST 2013 // // // Ports: diff --git a/rtl/mkDramServer_s4.v b/rtl/mkDramServer_s4.v new file mode 100644 index 00000000..9fff35ff --- /dev/null +++ b/rtl/mkDramServer_s4.v @@ -0,0 +1,2437 @@ +// +// Generated by Bluespec Compiler, version 2012.09.beta1 (build 29570, 2012-09.11) +// +// On Tue Jan 1 09:12:28 EST 2013 +// +// +// Ports: +// Name I/O size props +// wciS0_SResp O 2 reg +// wciS0_SData O 32 reg +// wciS0_SThreadBusy O 1 +// wciS0_SFlag O 2 +// wmemiS0_SResp O 2 reg +// wmemiS0_SRespLast O 1 reg +// wmemiS0_SData O 128 reg +// wmemiS0_SCmdAccept O 1 +// wmemiS0_SDataAccept O 1 +// dram_addr O 13 +// dram_ba O 3 +// dram_ras_n O 1 +// dram_cas_n O 1 +// dram_we_n O 1 +// dram_reset_n O 1 +// dram_cs_n O 1 +// dram_odt O 1 +// dram_cke O 1 +// dram_dm O 2 +// dram_ck_p O 1 +// dram_ck_n O 1 +// CLK_sys0_clk I 1 clock +// RST_N_sys0_rstn I 1 reset +// wciS0_Clk I 1 clock +// wciS0_MReset_n I 1 reset +// wciS0_MCmd I 3 +// wciS0_MAddrSpace I 1 +// wciS0_MByteEn I 4 +// wciS0_MAddr I 32 +// wciS0_MData I 32 +// wciS0_MFlag I 2 unused +// wmemiS0_MCmd I 3 +// wmemiS0_MAddr I 36 +// wmemiS0_MBurstLength I 12 +// wmemiS0_MData I 128 +// wmemiS0_MDataByteEn I 16 +// dram_rdn_i I 1 +// dram_rup_i I 1 +// wmemiS0_MReqLast I 1 +// wmemiS0_MDataValid I 1 +// wmemiS0_MDataLast I 1 +// wmemiS0_MReset_n I 1 reg +// dram_io_dq IO 16 inout +// dram_io_dqs_p IO 2 inout +// dram_io_dqs_n IO 2 inout +// +// Combinational paths from inputs to outputs: +// (wmemiS0_MCmd, +// wmemiS0_MAddr, +// wmemiS0_MBurstLength, +// wmemiS0_MReqLast) -> wmemiS0_SCmdAccept +// (wmemiS0_MData, +// wmemiS0_MDataByteEn, +// wmemiS0_MDataValid, +// wmemiS0_MDataLast) -> wmemiS0_SDataAccept +// +// + +`ifdef BSV_ASSIGNMENT_DELAY +`else + `define BSV_ASSIGNMENT_DELAY +`endif + +`ifdef BSV_POSITIVE_RESET + `define BSV_RESET_VALUE 1'b1 + `define BSV_RESET_EDGE posedge +`else + `define BSV_RESET_VALUE 1'b0 + `define BSV_RESET_EDGE negedge +`endif + +module mkDramServer_s4(CLK_sys0_clk, + RST_N_sys0_rstn, + wciS0_Clk, + wciS0_MReset_n, + + dram_io_dq, + dram_io_dqs_p, + dram_io_dqs_n, + + wciS0_MCmd, + + wciS0_MAddrSpace, + + wciS0_MByteEn, + + wciS0_MAddr, + + wciS0_MData, + + wciS0_SResp, + + wciS0_SData, + + wciS0_SThreadBusy, + + wciS0_SFlag, + + wciS0_MFlag, + + wmemiS0_MCmd, + + wmemiS0_MReqLast, + + wmemiS0_MAddr, + + wmemiS0_MBurstLength, + + wmemiS0_MDataValid, + + wmemiS0_MDataLast, + + wmemiS0_MData, + + wmemiS0_MDataByteEn, + + wmemiS0_SResp, + + wmemiS0_SRespLast, + + wmemiS0_SData, + + wmemiS0_SCmdAccept, + + wmemiS0_SDataAccept, + + wmemiS0_MReset_n, + + dram_addr, + + dram_ba, + + dram_ras_n, + + dram_cas_n, + + dram_we_n, + + dram_reset_n, + + dram_cs_n, + + dram_odt, + + dram_cke, + + dram_dm, + + dram_ck_p, + + dram_ck_n, + + dram_rdn_i, + + dram_rup_i); + parameter [0 : 0] hasDebugLogic = 1'b0; + input CLK_sys0_clk; + input RST_N_sys0_rstn; + input wciS0_Clk; + input wciS0_MReset_n; + + inout [15 : 0] dram_io_dq; + inout [1 : 0] dram_io_dqs_p; + inout [1 : 0] dram_io_dqs_n; + + // action method wciS0_mCmd + input [2 : 0] wciS0_MCmd; + + // action method wciS0_mAddrSpace + input wciS0_MAddrSpace; + + // action method wciS0_mByteEn + input [3 : 0] wciS0_MByteEn; + + // action method wciS0_mAddr + input [31 : 0] wciS0_MAddr; + + // action method wciS0_mData + input [31 : 0] wciS0_MData; + + // value method wciS0_sResp + output [1 : 0] wciS0_SResp; + + // value method wciS0_sData + output [31 : 0] wciS0_SData; + + // value method wciS0_sThreadBusy + output wciS0_SThreadBusy; + + // value method wciS0_sFlag + output [1 : 0] wciS0_SFlag; + + // action method wciS0_mFlag + input [1 : 0] wciS0_MFlag; + + // action method wmemiS0_mCmd + input [2 : 0] wmemiS0_MCmd; + + // action method wmemiS0_mReqLast + input wmemiS0_MReqLast; + + // action method wmemiS0_mAddr + input [35 : 0] wmemiS0_MAddr; + + // action method wmemiS0_mBurstLength + input [11 : 0] wmemiS0_MBurstLength; + + // action method wmemiS0_mDataValid + input wmemiS0_MDataValid; + + // action method wmemiS0_mDataLast + input wmemiS0_MDataLast; + + // action method wmemiS0_mData + input [127 : 0] wmemiS0_MData; + + // action method wmemiS0_mDataByteEn + input [15 : 0] wmemiS0_MDataByteEn; + + // value method wmemiS0_sResp + output [1 : 0] wmemiS0_SResp; + + // value method wmemiS0_sRespLast + output wmemiS0_SRespLast; + + // value method wmemiS0_sData + output [127 : 0] wmemiS0_SData; + + // value method wmemiS0_sCmdAccept + output wmemiS0_SCmdAccept; + + // value method wmemiS0_sDataAccept + output wmemiS0_SDataAccept; + + // action method wmemiS0_mReset_n + input wmemiS0_MReset_n; + + // value method dram_addr + output [12 : 0] dram_addr; + + // value method dram_ba + output [2 : 0] dram_ba; + + // value method dram_ras_n + output dram_ras_n; + + // value method dram_cas_n + output dram_cas_n; + + // value method dram_we_n + output dram_we_n; + + // value method dram_reset_n + output dram_reset_n; + + // value method dram_cs_n + output dram_cs_n; + + // value method dram_odt + output dram_odt; + + // value method dram_cke + output dram_cke; + + // value method dram_dm + output [1 : 0] dram_dm; + + // value method dram_ck_p + output dram_ck_p; + + // value method dram_ck_n + output dram_ck_n; + + // action method dram_rdn + input dram_rdn_i; + + // action method dram_rup + input dram_rup_i; + + // signals for module outputs + wire [127 : 0] wmemiS0_SData; + wire [31 : 0] wciS0_SData; + wire [12 : 0] dram_addr; + wire [2 : 0] dram_ba; + wire [1 : 0] dram_dm, wciS0_SFlag, wciS0_SResp, wmemiS0_SResp; + wire dram_cas_n, + dram_ck_n, + dram_ck_p, + dram_cke, + dram_cs_n, + dram_odt, + dram_ras_n, + dram_reset_n, + dram_we_n, + wciS0_SThreadBusy, + wmemiS0_SCmdAccept, + wmemiS0_SDataAccept, + wmemiS0_SRespLast; + + // inlined wires + wire [145 : 0] wmemi_wmemiDh$wget; + wire [130 : 0] wmemi_respF_x_wire$wget; + wire [127 : 0] wmemi_Es_mData_w$wget; + wire [71 : 0] wci_wslv_wciReq$wget; + wire [63 : 0] memc_avlWData$wget; + wire [51 : 0] wmemi_wmemiReq$wget; + wire [35 : 0] wmemi_Es_mAddr_w$wget; + wire [33 : 0] wci_wslv_respF_x_wire$wget; + wire [31 : 0] wci_wci_Es_mAddr_w$wget, wci_wci_Es_mData_w$wget; + wire [23 : 0] memc_avlAddr$wget; + wire [15 : 0] wmemi_Es_mDataByteEn_w$wget; + wire [11 : 0] wmemi_Es_mBurstLength_w$wget; + wire [7 : 0] memc_avlBE$wget, + wmemiReadInFlight_acc_v1$wget, + wmemiReadInFlight_acc_v2$wget; + wire [3 : 0] wci_wci_Es_mByteEn_w$wget; + wire [2 : 0] memc_avlSize$wget, + wci_wci_Es_mCmd_w$wget, + wci_wslv_wEdge$wget, + wmemi_Es_mCmd_w$wget; + wire memc_avlAddr$whas, + memc_avlBE$whas, + memc_avlBurstBegin$wget, + memc_avlBurstBegin$whas, + memc_avlReadReq$wget, + memc_avlReadReq$whas, + memc_avlSize$whas, + memc_avlWData$whas, + memc_avlWriteReq$wget, + memc_avlWriteReq$whas, + wci_wci_Es_mAddrSpace_w$wget, + wci_wci_Es_mAddrSpace_w$whas, + wci_wci_Es_mAddr_w$whas, + wci_wci_Es_mByteEn_w$whas, + wci_wci_Es_mCmd_w$whas, + wci_wci_Es_mData_w$whas, + wci_wslv_ctlAckReg_1$wget, + wci_wslv_ctlAckReg_1$whas, + wci_wslv_reqF_r_clr$whas, + wci_wslv_reqF_r_deq$whas, + wci_wslv_reqF_r_enq$whas, + wci_wslv_respF_dequeueing$whas, + wci_wslv_respF_enqueueing$whas, + wci_wslv_respF_x_wire$whas, + wci_wslv_sFlagReg_1$wget, + wci_wslv_sFlagReg_1$whas, + wci_wslv_sThreadBusy_pw$whas, + wci_wslv_wEdge$whas, + wci_wslv_wciReq$whas, + wci_wslv_wci_cfrd_pw$whas, + wci_wslv_wci_cfwr_pw$whas, + wci_wslv_wci_ctrl_pw$whas, + wmemiReadInFlight_acc_v1$whas, + wmemiReadInFlight_acc_v2$whas, + wmemi_Es_mAddr_w$whas, + wmemi_Es_mBurstLength_w$whas, + wmemi_Es_mCmd_w$whas, + wmemi_Es_mDataByteEn_w$whas, + wmemi_Es_mDataLast_w$whas, + wmemi_Es_mDataValid_w$whas, + wmemi_Es_mData_w$whas, + wmemi_Es_mReqLast_w$whas, + wmemi_cmdAccept_w$wget, + wmemi_cmdAccept_w$whas, + wmemi_dhAccept_w$wget, + wmemi_dhAccept_w$whas, + wmemi_operateD_1$wget, + wmemi_operateD_1$whas, + wmemi_peerIsReady_1$wget, + wmemi_peerIsReady_1$whas, + wmemi_respF_dequeueing$whas, + wmemi_respF_enqueueing$whas, + wmemi_respF_x_wire$whas, + wmemi_wmemiDh$whas, + wmemi_wmemiReq$whas; + + // register dbgCtrl + reg [31 : 0] dbgCtrl; + wire [31 : 0] dbgCtrl$D_IN; + wire dbgCtrl$EN; + + // register dramCtrl + reg [31 : 0] dramCtrl; + wire [31 : 0] dramCtrl$D_IN; + wire dramCtrl$EN; + + // register mReg + reg [15 : 0] mReg; + wire [15 : 0] mReg$D_IN; + wire mReg$EN; + + // register memIsReset_isInReset + reg memIsReset_isInReset; + wire memIsReset_isInReset$D_IN, memIsReset_isInReset$EN; + + // register memc_afiCount + reg [3 : 0] memc_afiCount; + wire [3 : 0] memc_afiCount$D_IN; + wire memc_afiCount$EN; + + // register memc_curCount + reg [3 : 0] memc_curCount; + wire [3 : 0] memc_curCount$D_IN; + wire memc_curCount$EN; + + // register memc_dbg_reqCount + reg [15 : 0] memc_dbg_reqCount; + wire [15 : 0] memc_dbg_reqCount$D_IN; + wire memc_dbg_reqCount$EN; + + // register memc_dbg_respCount + reg [15 : 0] memc_dbg_respCount; + wire [15 : 0] memc_dbg_respCount$D_IN; + wire memc_dbg_respCount$EN; + + // register memc_rdStageLS + reg [63 : 0] memc_rdStageLS; + wire [63 : 0] memc_rdStageLS$D_IN; + wire memc_rdStageLS$EN; + + // register memc_secondRdBeat + reg memc_secondRdBeat; + wire memc_secondRdBeat$D_IN, memc_secondRdBeat$EN; + + // register memc_secondWrBeat + reg memc_secondWrBeat; + wire memc_secondWrBeat$D_IN, memc_secondWrBeat$EN; + + // register memc_sysCount + reg [3 : 0] memc_sysCount; + wire [3 : 0] memc_sysCount$D_IN; + wire memc_sysCount$EN; + + // register pReg + reg [15 : 0] pReg; + wire [15 : 0] pReg$D_IN; + wire pReg$EN; + + // register rdReg + reg [31 : 0] rdReg; + wire [31 : 0] rdReg$D_IN; + wire rdReg$EN; + + // register rdReg_1 + reg [31 : 0] rdReg_1; + wire [31 : 0] rdReg_1$D_IN; + wire rdReg_1$EN; + + // register rdReg_2 + reg [31 : 0] rdReg_2; + wire [31 : 0] rdReg_2$D_IN; + wire rdReg_2$EN; + + // register rdReg_3 + reg [31 : 0] rdReg_3; + wire [31 : 0] rdReg_3$D_IN; + wire rdReg_3$EN; + + // register respCount + reg [7 : 0] respCount; + wire [7 : 0] respCount$D_IN; + wire respCount$EN; + + // register splitReadInFlight + reg splitReadInFlight; + wire splitReadInFlight$D_IN, splitReadInFlight$EN; + + // register wci_wslv_cEdge + reg [2 : 0] wci_wslv_cEdge; + wire [2 : 0] wci_wslv_cEdge$D_IN; + wire wci_wslv_cEdge$EN; + + // register wci_wslv_cState + reg [2 : 0] wci_wslv_cState; + wire [2 : 0] wci_wslv_cState$D_IN; + wire wci_wslv_cState$EN; + + // register wci_wslv_ctlAckReg + reg wci_wslv_ctlAckReg; + wire wci_wslv_ctlAckReg$D_IN, wci_wslv_ctlAckReg$EN; + + // register wci_wslv_ctlOpActive + reg wci_wslv_ctlOpActive; + wire wci_wslv_ctlOpActive$D_IN, wci_wslv_ctlOpActive$EN; + + // register wci_wslv_illegalEdge + reg wci_wslv_illegalEdge; + wire wci_wslv_illegalEdge$D_IN, wci_wslv_illegalEdge$EN; + + // register wci_wslv_isReset_isInReset + reg wci_wslv_isReset_isInReset; + wire wci_wslv_isReset_isInReset$D_IN, wci_wslv_isReset_isInReset$EN; + + // register wci_wslv_nState + reg [2 : 0] wci_wslv_nState; + reg [2 : 0] wci_wslv_nState$D_IN; + wire wci_wslv_nState$EN; + + // register wci_wslv_reqF_countReg + reg [1 : 0] wci_wslv_reqF_countReg; + wire [1 : 0] wci_wslv_reqF_countReg$D_IN; + wire wci_wslv_reqF_countReg$EN; + + // register wci_wslv_respF_c_r + reg [1 : 0] wci_wslv_respF_c_r; + wire [1 : 0] wci_wslv_respF_c_r$D_IN; + wire wci_wslv_respF_c_r$EN; + + // register wci_wslv_respF_q_0 + reg [33 : 0] wci_wslv_respF_q_0; + reg [33 : 0] wci_wslv_respF_q_0$D_IN; + wire wci_wslv_respF_q_0$EN; + + // register wci_wslv_respF_q_1 + reg [33 : 0] wci_wslv_respF_q_1; + reg [33 : 0] wci_wslv_respF_q_1$D_IN; + wire wci_wslv_respF_q_1$EN; + + // register wci_wslv_sFlagReg + reg wci_wslv_sFlagReg; + wire wci_wslv_sFlagReg$D_IN, wci_wslv_sFlagReg$EN; + + // register wci_wslv_sThreadBusy_d + reg wci_wslv_sThreadBusy_d; + wire wci_wslv_sThreadBusy_d$D_IN, wci_wslv_sThreadBusy_d$EN; + + // register wdReg + reg [31 : 0] wdReg; + wire [31 : 0] wdReg$D_IN; + wire wdReg$EN; + + // register wdReg_1 + reg [31 : 0] wdReg_1; + wire [31 : 0] wdReg_1$D_IN; + wire wdReg_1$EN; + + // register wdReg_2 + reg [31 : 0] wdReg_2; + wire [31 : 0] wdReg_2$D_IN; + wire wdReg_2$EN; + + // register wdReg_3 + reg [31 : 0] wdReg_3; + wire [31 : 0] wdReg_3$D_IN; + wire wdReg_3$EN; + + // register wmemiRdReq + reg [31 : 0] wmemiRdReq; + wire [31 : 0] wmemiRdReq$D_IN; + wire wmemiRdReq$EN; + + // register wmemiRdResp + reg [31 : 0] wmemiRdResp; + wire [31 : 0] wmemiRdResp$D_IN; + wire wmemiRdResp$EN; + + // register wmemiReadInFlight_value + reg [7 : 0] wmemiReadInFlight_value; + wire [7 : 0] wmemiReadInFlight_value$D_IN; + wire wmemiReadInFlight_value$EN; + + // register wmemiWrReq + reg [31 : 0] wmemiWrReq; + wire [31 : 0] wmemiWrReq$D_IN; + wire wmemiWrReq$EN; + + // register wmemi_errorSticky + reg wmemi_errorSticky; + wire wmemi_errorSticky$D_IN, wmemi_errorSticky$EN; + + // register wmemi_isReset_isInReset + reg wmemi_isReset_isInReset; + wire wmemi_isReset_isInReset$D_IN, wmemi_isReset_isInReset$EN; + + // register wmemi_operateD + reg wmemi_operateD; + wire wmemi_operateD$D_IN, wmemi_operateD$EN; + + // register wmemi_peerIsReady + reg wmemi_peerIsReady; + wire wmemi_peerIsReady$D_IN, wmemi_peerIsReady$EN; + + // register wmemi_respF_c_r + reg [1 : 0] wmemi_respF_c_r; + wire [1 : 0] wmemi_respF_c_r$D_IN; + wire wmemi_respF_c_r$EN; + + // register wmemi_respF_q_0 + reg [130 : 0] wmemi_respF_q_0; + reg [130 : 0] wmemi_respF_q_0$D_IN; + wire wmemi_respF_q_0$EN; + + // register wmemi_respF_q_1 + reg [130 : 0] wmemi_respF_q_1; + reg [130 : 0] wmemi_respF_q_1$D_IN; + wire wmemi_respF_q_1$EN; + + // register wmemi_statusR + reg [7 : 0] wmemi_statusR; + wire [7 : 0] wmemi_statusR$D_IN; + wire wmemi_statusR$EN; + + // register wmemi_trafficSticky + reg wmemi_trafficSticky; + wire wmemi_trafficSticky$D_IN, wmemi_trafficSticky$EN; + + // ports of submodule calFail + wire calFail$dD_OUT, calFail$sD_IN, calFail$sEN; + + // ports of submodule calSuccess + wire calSuccess$dD_OUT, calSuccess$sD_IN, calSuccess$sEN; + + // ports of submodule initDone + wire initDone$dD_OUT, initDone$sD_IN, initDone$sEN; + + // ports of submodule lreqF + reg [176 : 0] lreqF$sD_IN; + wire [176 : 0] lreqF$dD_OUT; + wire lreqF$dDEQ, lreqF$dEMPTY_N, lreqF$sENQ, lreqF$sFULL_N; + + // ports of submodule lrespF + wire [127 : 0] lrespF$dD_OUT, lrespF$sD_IN; + wire lrespF$dDEQ, lrespF$dEMPTY_N, lrespF$sENQ, lrespF$sFULL_N; + + // ports of submodule memIsResetCC + wire memIsResetCC$dD_OUT, memIsResetCC$sD_IN, memIsResetCC$sEN; + + // ports of submodule memc_afiActive + wire memc_afiActive$dD_OUT, memc_afiActive$sD_IN, memc_afiActive$sEN; + + // ports of submodule memc_drstn + wire memc_drstn$OUT_RST; + + // ports of submodule memc_memc + wire [63 : 0] memc_memc$avl_rdata, memc_memc$avl_wdata; + wire [23 : 0] memc_memc$avl_addr; + wire [15 : 0] memc_memc$mem_dq; + wire [12 : 0] memc_memc$mem_a; + wire [7 : 0] memc_memc$avl_be; + wire [2 : 0] memc_memc$avl_size, memc_memc$mem_ba; + wire [1 : 0] memc_memc$mem_dm, memc_memc$mem_dqs, memc_memc$mem_dqs_n; + wire memc_memc$afi_clk, + memc_memc$afi_reset_n, + memc_memc$avl_burstbegin, + memc_memc$avl_rdata_valid, + memc_memc$avl_read_req, + memc_memc$avl_ready, + memc_memc$avl_write_req, + memc_memc$local_cal_fail, + memc_memc$local_cal_success, + memc_memc$local_init_done, + memc_memc$mem_cas_n, + memc_memc$mem_ck, + memc_memc$mem_ck_n, + memc_memc$mem_cke, + memc_memc$mem_cs_n, + memc_memc$mem_odt, + memc_memc$mem_ras_n, + memc_memc$mem_reset_n, + memc_memc$mem_we_n, + memc_memc$oct_rdn, + memc_memc$oct_rup; + + // ports of submodule memc_reqF + wire [176 : 0] memc_reqF$D_IN, memc_reqF$D_OUT; + wire memc_reqF$CLR, + memc_reqF$DEQ, + memc_reqF$EMPTY_N, + memc_reqF$ENQ, + memc_reqF$FULL_N; + + // ports of submodule memc_respF + wire [127 : 0] memc_respF$D_IN, memc_respF$D_OUT; + wire memc_respF$CLR, + memc_respF$DEQ, + memc_respF$EMPTY_N, + memc_respF$ENQ, + memc_respF$FULL_N; + + // ports of submodule memc_sysActive + wire memc_sysActive$dD_OUT, memc_sysActive$sD_IN, memc_sysActive$sEN; + + // ports of submodule requestCount + wire [15 : 0] requestCount$dD_OUT, requestCount$sD_IN; + wire requestCount$sEN, requestCount$sRDY; + + // ports of submodule responseCount + wire [15 : 0] responseCount$sD_IN; + wire responseCount$sEN, responseCount$sRDY; + + // ports of submodule splaF + wire [1 : 0] splaF$D_IN, splaF$D_OUT; + wire splaF$CLR, splaF$DEQ, splaF$EMPTY_N, splaF$ENQ, splaF$FULL_N; + + // ports of submodule wci_wslv_reqF + wire [71 : 0] wci_wslv_reqF$D_IN, wci_wslv_reqF$D_OUT; + wire wci_wslv_reqF$CLR, + wci_wslv_reqF$DEQ, + wci_wslv_reqF$EMPTY_N, + wci_wslv_reqF$ENQ; + + // ports of submodule wmemi_dhF + wire [145 : 0] wmemi_dhF$D_IN, wmemi_dhF$D_OUT; + wire wmemi_dhF$CLR, + wmemi_dhF$DEQ, + wmemi_dhF$EMPTY_N, + wmemi_dhF$ENQ, + wmemi_dhF$FULL_N; + + // ports of submodule wmemi_reqF + wire [51 : 0] wmemi_reqF$D_IN, wmemi_reqF$D_OUT; + wire wmemi_reqF$CLR, + wmemi_reqF$DEQ, + wmemi_reqF$EMPTY_N, + wmemi_reqF$ENQ, + wmemi_reqF$FULL_N; + + // rule scheduling signals + wire WILL_FIRE_RL_advance_response, + WILL_FIRE_RL_getRequest, + WILL_FIRE_RL_memc_advance_readResponse, + WILL_FIRE_RL_memc_advance_request, + WILL_FIRE_RL_memc_advance_write1, + WILL_FIRE_RL_wci_cfrd, + WILL_FIRE_RL_wci_cfwr, + WILL_FIRE_RL_wci_ctrl_EiI, + WILL_FIRE_RL_wci_ctrl_IsO, + WILL_FIRE_RL_wci_ctrl_OrE, + WILL_FIRE_RL_wci_wslv_ctl_op_complete, + WILL_FIRE_RL_wci_wslv_ctl_op_start, + WILL_FIRE_RL_wci_wslv_respF_both, + WILL_FIRE_RL_wci_wslv_respF_decCtr, + WILL_FIRE_RL_wci_wslv_respF_incCtr, + WILL_FIRE_RL_wmemi_respF_both, + WILL_FIRE_RL_wmemi_respF_decCtr, + WILL_FIRE_RL_wmemi_respF_incCtr; + + // inputs to muxes for submodule ports + reg [33 : 0] MUX_wci_wslv_respF_q_0$write_1__VAL_2; + wire [176 : 0] MUX_lreqF$enq_1__VAL_1, + MUX_lreqF$enq_1__VAL_2, + MUX_lreqF$enq_1__VAL_3; + wire [130 : 0] MUX_wmemi_respF_q_0$write_1__VAL_1, + MUX_wmemi_respF_q_0$write_1__VAL_2, + MUX_wmemi_respF_q_1$write_1__VAL_2; + wire [33 : 0] MUX_wci_wslv_respF_q_0$write_1__VAL_1, + MUX_wci_wslv_respF_q_1$write_1__VAL_1, + MUX_wci_wslv_respF_x_wire$wset_1__VAL_1, + MUX_wci_wslv_respF_x_wire$wset_1__VAL_2, + MUX_wci_wslv_respF_x_wire$wset_1__VAL_3; + wire [7 : 0] MUX_wmemiReadInFlight_value$write_1__VAL_2; + wire [1 : 0] MUX_wci_wslv_respF_c_r$write_1__VAL_1, + MUX_wci_wslv_respF_c_r$write_1__VAL_2, + MUX_wmemi_respF_c_r$write_1__VAL_1, + MUX_wmemi_respF_c_r$write_1__VAL_2; + wire MUX_lreqF$enq_1__SEL_1, + MUX_lreqF$enq_1__SEL_2, + MUX_lreqF$enq_1__SEL_3, + MUX_memc_avlBE$wset_1__SEL_1, + MUX_rdReg$write_1__SEL_1, + MUX_rdReg_1$write_1__SEL_1, + MUX_rdReg_2$write_1__SEL_1, + MUX_rdReg_3$write_1__SEL_1, + MUX_splitReadInFlight$write_1__SEL_1, + MUX_wci_wslv_illegalEdge$write_1__SEL_1, + MUX_wci_wslv_illegalEdge$write_1__SEL_2, + MUX_wci_wslv_illegalEdge$write_1__VAL_2, + MUX_wci_wslv_respF_q_0$write_1__SEL_2, + MUX_wci_wslv_respF_q_1$write_1__SEL_2, + MUX_wci_wslv_respF_x_wire$wset_1__SEL_2, + MUX_wmemi_respF_q_0$write_1__SEL_1, + MUX_wmemi_respF_q_1$write_1__SEL_1; + + // remaining internal signals + reg [63 : 0] v__h18076, v__h6589, v__h6764, v__h6908; + reg [31 : 0] IF_wci_wslv_reqF_first__09_BITS_39_TO_32_84_EQ_ETC___d512, + g_data__h13952; + wire [175 : 0] IF_wci_wslv_reqF_first__09_BIT_51_83_THEN_pReg_ETC___d434; + wire [127 : 0] x1_data__h15200, x1_data__h16201; + wire [31 : 0] dramStatus__h12575, + g_data__h17725, + rdat___1__h17815, + rdat___1__h17826, + rdat___1__h17832, + rdat___1__h17842, + rdat___1__h17852, + rdat___1__h17866, + rdat___1__h17880, + rdat___1__h17894, + rdat___1__h17908, + rdat___1__h17923, + rdat___1__h17938, + rdat___1__h17953, + x1_addr__h16199; + wire [15 : 0] x1_be__h16200, x__h17765; + wire [2 : 0] activeBits__h2005; + wire IF_wci_wslv_reqF_first__09_BIT_51_83_THEN_lreq_ETC___d459, + IF_wmemi_reqF_first__11_BITS_51_TO_49_12_EQ_1__ETC___d320, + lrespF_RDY_first__46_AND_NOT_splitReadInFlight_ETC___d362, + lrespF_RDY_first__46_AND_NOT_wmemi_respF_c_r_2_ETC___d348, + wci_wslv_reqF_i_notEmpty__08_AND_IF_wci_wslv_r_ETC___d395, + wmemiReadInFlight_value_85_SLT_16___d591; + + // value method wciS0_sResp + assign wciS0_SResp = wci_wslv_respF_q_0[33:32] ; + + // value method wciS0_sData + assign wciS0_SData = wci_wslv_respF_q_0[31:0] ; + + // value method wciS0_sThreadBusy + assign wciS0_SThreadBusy = + wci_wslv_reqF_countReg > 2'd1 || wci_wslv_isReset_isInReset ; + + // value method wciS0_sFlag + assign wciS0_SFlag = { 1'd1, wci_wslv_sFlagReg } ; + + // value method wmemiS0_sResp + assign wmemiS0_SResp = wmemi_respF_q_0[130:129] ; + + // value method wmemiS0_sRespLast + assign wmemiS0_SRespLast = wmemi_respF_q_0[128] ; + + // value method wmemiS0_sData + assign wmemiS0_SData = wmemi_respF_q_0[127:0] ; + + // value method wmemiS0_sCmdAccept + assign wmemiS0_SCmdAccept = wmemi_cmdAccept_w$whas ; + + // value method wmemiS0_sDataAccept + assign wmemiS0_SDataAccept = wmemi_dhAccept_w$whas ; + + // value method dram_addr + assign dram_addr = memc_memc$mem_a ; + + // value method dram_ba + assign dram_ba = memc_memc$mem_ba ; + + // value method dram_ras_n + assign dram_ras_n = memc_memc$mem_ras_n ; + + // value method dram_cas_n + assign dram_cas_n = memc_memc$mem_cas_n ; + + // value method dram_we_n + assign dram_we_n = memc_memc$mem_we_n ; + + // value method dram_reset_n + assign dram_reset_n = memc_memc$mem_reset_n ; + + // value method dram_cs_n + assign dram_cs_n = memc_memc$mem_cs_n ; + + // value method dram_odt + assign dram_odt = memc_memc$mem_odt ; + + // value method dram_cke + assign dram_cke = memc_memc$mem_cke ; + + // value method dram_dm + assign dram_dm = memc_memc$mem_dm ; + + // value method dram_ck_p + assign dram_ck_p = memc_memc$mem_ck ; + + // value method dram_ck_n + assign dram_ck_n = memc_memc$mem_ck_n ; + + // submodule calFail + SyncBit #(.init(1'd0)) calFail(.sCLK(memc_memc$afi_clk), + .dCLK(wciS0_Clk), + .sRST(memc_memc$afi_reset_n), + .sD_IN(calFail$sD_IN), + .sEN(calFail$sEN), + .dD_OUT(calFail$dD_OUT)); + + // submodule calSuccess + SyncBit #(.init(1'd0)) calSuccess(.sCLK(memc_memc$afi_clk), + .dCLK(wciS0_Clk), + .sRST(memc_memc$afi_reset_n), + .sD_IN(calSuccess$sD_IN), + .sEN(calSuccess$sEN), + .dD_OUT(calSuccess$dD_OUT)); + + // submodule initDone + SyncBit #(.init(1'd0)) initDone(.sCLK(memc_memc$afi_clk), + .dCLK(wciS0_Clk), + .sRST(memc_memc$afi_reset_n), + .sD_IN(initDone$sD_IN), + .sEN(initDone$sEN), + .dD_OUT(initDone$dD_OUT)); + + // submodule lreqF + SyncFIFO #(.dataWidth(32'd177), + .depth(32'd2), + .indxWidth(32'd1)) lreqF(.sCLK(wciS0_Clk), + .dCLK(memc_memc$afi_clk), + .sRST(wciS0_MReset_n), + .sD_IN(lreqF$sD_IN), + .sENQ(lreqF$sENQ), + .dDEQ(lreqF$dDEQ), + .dD_OUT(lreqF$dD_OUT), + .sFULL_N(lreqF$sFULL_N), + .dEMPTY_N(lreqF$dEMPTY_N)); + + // submodule lrespF + SyncFIFO #(.dataWidth(32'd128), + .depth(32'd2), + .indxWidth(32'd1)) lrespF(.sCLK(memc_memc$afi_clk), + .dCLK(wciS0_Clk), + .sRST(memc_memc$afi_reset_n), + .sD_IN(lrespF$sD_IN), + .sENQ(lrespF$sENQ), + .dDEQ(lrespF$dDEQ), + .dD_OUT(lrespF$dD_OUT), + .sFULL_N(lrespF$sFULL_N), + .dEMPTY_N(lrespF$dEMPTY_N)); + + // submodule memIsResetCC + SyncBit #(.init(1'd0)) memIsResetCC(.sCLK(memc_memc$afi_clk), + .dCLK(wciS0_Clk), + .sRST(memc_memc$afi_reset_n), + .sD_IN(memIsResetCC$sD_IN), + .sEN(memIsResetCC$sEN), + .dD_OUT(memIsResetCC$dD_OUT)); + + // submodule memc_afiActive + SyncBit #(.init(1'd0)) memc_afiActive(.sCLK(memc_memc$afi_clk), + .dCLK(wciS0_Clk), + .sRST(memc_memc$afi_reset_n), + .sD_IN(memc_afiActive$sD_IN), + .sEN(memc_afiActive$sEN), + .dD_OUT(memc_afiActive$dD_OUT)); + + // submodule memc_drstn + SyncResetA #(.RSTDELAY(32'd3)) memc_drstn(.CLK(CLK_sys0_clk), + .IN_RST(wciS0_MReset_n), + .OUT_RST(memc_drstn$OUT_RST)); + + // submodule memc_memc + ddr3_s4_uniphy memc_memc(.pll_ref_clk(CLK_sys0_clk), + .global_reset_n(memc_drstn$OUT_RST), + .soft_reset_n(wciS0_MReset_n), + .avl_addr(memc_memc$avl_addr), + .avl_be(memc_memc$avl_be), + .avl_burstbegin(memc_memc$avl_burstbegin), + .avl_read_req(memc_memc$avl_read_req), + .avl_size(memc_memc$avl_size), + .avl_wdata(memc_memc$avl_wdata), + .avl_write_req(memc_memc$avl_write_req), + .oct_rdn(memc_memc$oct_rdn), + .oct_rup(memc_memc$oct_rup), + .mem_a(memc_memc$mem_a), + .mem_ba(memc_memc$mem_ba), + .mem_ras_n(memc_memc$mem_ras_n), + .mem_cas_n(memc_memc$mem_cas_n), + .mem_we_n(memc_memc$mem_we_n), + .mem_reset_n(memc_memc$mem_reset_n), + .mem_cs_n(memc_memc$mem_cs_n), + .mem_odt(memc_memc$mem_odt), + .mem_cke(memc_memc$mem_cke), + .mem_dm(memc_memc$mem_dm), + .mem_ck(memc_memc$mem_ck), + .mem_ck_n(memc_memc$mem_ck_n), + .local_init_done(memc_memc$local_init_done), + .local_cal_success(memc_memc$local_cal_success), + .local_cal_fail(memc_memc$local_cal_fail), + .avl_ready(memc_memc$avl_ready), + .avl_rdata_valid(memc_memc$avl_rdata_valid), + .avl_rdata(memc_memc$avl_rdata), + .afi_clk(memc_memc$afi_clk), + .afi_reset_n(memc_memc$afi_reset_n), + .mem_dq(dram_io_dq), + .mem_dqs(dram_io_dqs_p), + .mem_dqs_n(dram_io_dqs_n)); + + // submodule memc_reqF + FIFO2 #(.width(32'd177), + .guarded(32'd1)) memc_reqF(.RST(memc_memc$afi_reset_n), + .CLK(memc_memc$afi_clk), + .D_IN(memc_reqF$D_IN), + .ENQ(memc_reqF$ENQ), + .DEQ(memc_reqF$DEQ), + .CLR(memc_reqF$CLR), + .D_OUT(memc_reqF$D_OUT), + .FULL_N(memc_reqF$FULL_N), + .EMPTY_N(memc_reqF$EMPTY_N)); + + // submodule memc_respF + arSRLFIFOD #(.width(32'd128), + .l2depth(32'd4)) memc_respF(.CLK(memc_memc$afi_clk), + .RST_N(memc_memc$afi_reset_n), + .D_IN(memc_respF$D_IN), + .CLR(memc_respF$CLR), + .DEQ(memc_respF$DEQ), + .ENQ(memc_respF$ENQ), + .D_OUT(memc_respF$D_OUT), + .EMPTY_N(memc_respF$EMPTY_N), + .FULL_N(memc_respF$FULL_N)); + + // submodule memc_sysActive + SyncBit #(.init(1'd0)) memc_sysActive(.sCLK(CLK_sys0_clk), + .dCLK(wciS0_Clk), + .sRST(RST_N_sys0_rstn), + .sD_IN(memc_sysActive$sD_IN), + .sEN(memc_sysActive$sEN), + .dD_OUT(memc_sysActive$dD_OUT)); + + // submodule requestCount + SyncRegister #(.width(32'd16), + .init(16'd0)) requestCount(.sCLK(memc_memc$afi_clk), + .dCLK(wciS0_Clk), + .sRST(memc_memc$afi_reset_n), + .sD_IN(requestCount$sD_IN), + .sEN(requestCount$sEN), + .dD_OUT(requestCount$dD_OUT), + .sRDY(requestCount$sRDY)); + + // submodule responseCount + SyncRegister #(.width(32'd16), + .init(16'd0)) responseCount(.sCLK(memc_memc$afi_clk), + .dCLK(wciS0_Clk), + .sRST(memc_memc$afi_reset_n), + .sD_IN(responseCount$sD_IN), + .sEN(responseCount$sEN), + .dD_OUT(), + .sRDY(responseCount$sRDY)); + + // submodule splaF + FIFO2 #(.width(32'd2), .guarded(32'd1)) splaF(.RST(wciS0_MReset_n), + .CLK(wciS0_Clk), + .D_IN(splaF$D_IN), + .ENQ(splaF$ENQ), + .DEQ(splaF$DEQ), + .CLR(splaF$CLR), + .D_OUT(splaF$D_OUT), + .FULL_N(splaF$FULL_N), + .EMPTY_N(splaF$EMPTY_N)); + + // submodule wci_wslv_reqF + SizedFIFO #(.p1width(32'd72), + .p2depth(32'd3), + .p3cntr_width(32'd1), + .guarded(32'd1)) wci_wslv_reqF(.RST(wciS0_MReset_n), + .CLK(wciS0_Clk), + .D_IN(wci_wslv_reqF$D_IN), + .ENQ(wci_wslv_reqF$ENQ), + .DEQ(wci_wslv_reqF$DEQ), + .CLR(wci_wslv_reqF$CLR), + .D_OUT(wci_wslv_reqF$D_OUT), + .FULL_N(), + .EMPTY_N(wci_wslv_reqF$EMPTY_N)); + + // submodule wmemi_dhF + FIFO2 #(.width(32'd146), .guarded(32'd1)) wmemi_dhF(.RST(wciS0_MReset_n), + .CLK(wciS0_Clk), + .D_IN(wmemi_dhF$D_IN), + .ENQ(wmemi_dhF$ENQ), + .DEQ(wmemi_dhF$DEQ), + .CLR(wmemi_dhF$CLR), + .D_OUT(wmemi_dhF$D_OUT), + .FULL_N(wmemi_dhF$FULL_N), + .EMPTY_N(wmemi_dhF$EMPTY_N)); + + // submodule wmemi_reqF + FIFO2 #(.width(32'd52), .guarded(32'd1)) wmemi_reqF(.RST(wciS0_MReset_n), + .CLK(wciS0_Clk), + .D_IN(wmemi_reqF$D_IN), + .ENQ(wmemi_reqF$ENQ), + .DEQ(wmemi_reqF$DEQ), + .CLR(wmemi_reqF$CLR), + .D_OUT(wmemi_reqF$D_OUT), + .FULL_N(wmemi_reqF$FULL_N), + .EMPTY_N(wmemi_reqF$EMPTY_N)); + + // rule RL_memc_advance_request + assign WILL_FIRE_RL_memc_advance_request = + memc_reqF$EMPTY_N && memc_memc$local_init_done && + memc_memc$local_cal_success && + !memc_secondWrBeat && + !memc_secondRdBeat && + memc_memc$avl_ready ; + + // rule RL_memc_advance_write1 + assign WILL_FIRE_RL_memc_advance_write1 = + memc_reqF$EMPTY_N && memc_memc$local_init_done && + memc_memc$local_cal_success && + memc_secondWrBeat ; + + // rule RL_memc_advance_readResponse + assign WILL_FIRE_RL_memc_advance_readResponse = + (!memc_secondRdBeat || memc_respF$FULL_N) && + memc_memc$local_init_done && + memc_memc$local_cal_success && + memc_memc$avl_rdata_valid ; + + // rule RL_advance_response + assign WILL_FIRE_RL_advance_response = + lrespF$dEMPTY_N && + lrespF_RDY_first__46_AND_NOT_splitReadInFlight_ETC___d362 && + !wci_wslv_wci_cfwr_pw$whas && + wmemiReadInFlight_value == 8'd0 && + !WILL_FIRE_RL_wci_wslv_ctl_op_complete ; + + // rule RL_wci_cfwr + assign WILL_FIRE_RL_wci_cfwr = + wci_wslv_respF_c_r != 2'd2 && + wci_wslv_reqF_i_notEmpty__08_AND_IF_wci_wslv_r_ETC___d395 && + wci_wslv_wci_cfwr_pw$whas && + !WILL_FIRE_RL_wci_wslv_ctl_op_start && + !WILL_FIRE_RL_wci_wslv_ctl_op_complete ; + + // rule RL_wci_cfrd + assign WILL_FIRE_RL_wci_cfrd = + wci_wslv_reqF$EMPTY_N && + IF_wci_wslv_reqF_first__09_BIT_51_83_THEN_lreq_ETC___d459 && + wci_wslv_wci_cfrd_pw$whas && + !WILL_FIRE_RL_wci_wslv_ctl_op_start && + !WILL_FIRE_RL_wci_wslv_ctl_op_complete ; + + // rule RL_wci_wslv_ctl_op_start + assign WILL_FIRE_RL_wci_wslv_ctl_op_start = + wci_wslv_reqF$EMPTY_N && wci_wslv_wci_ctrl_pw$whas && + !WILL_FIRE_RL_wci_wslv_ctl_op_complete ; + + // rule RL_wci_ctrl_EiI + assign WILL_FIRE_RL_wci_ctrl_EiI = + wci_wslv_wci_ctrl_pw$whas && + WILL_FIRE_RL_wci_wslv_ctl_op_start && + wci_wslv_cState == 3'd0 && + wci_wslv_reqF$D_OUT[36:34] == 3'd0 ; + + // rule RL_wci_ctrl_OrE + assign WILL_FIRE_RL_wci_ctrl_OrE = + wci_wslv_wci_ctrl_pw$whas && + WILL_FIRE_RL_wci_wslv_ctl_op_start && + wci_wslv_cState == 3'd2 && + wci_wslv_reqF$D_OUT[36:34] == 3'd3 ; + + // rule RL_wmemi_respF_incCtr + assign WILL_FIRE_RL_wmemi_respF_incCtr = + ((wmemi_respF_c_r == 2'd0) ? + wmemi_respF_enqueueing$whas : + wmemi_respF_c_r != 2'd1 || wmemi_respF_enqueueing$whas) && + wmemi_respF_enqueueing$whas && + !(wmemi_respF_c_r != 2'd0) ; + + // rule RL_wmemi_respF_decCtr + assign WILL_FIRE_RL_wmemi_respF_decCtr = + wmemi_respF_c_r != 2'd0 && !wmemi_respF_enqueueing$whas ; + + // rule RL_wmemi_respF_both + assign WILL_FIRE_RL_wmemi_respF_both = + ((wmemi_respF_c_r == 2'd1) ? + wmemi_respF_enqueueing$whas : + wmemi_respF_c_r != 2'd2 || wmemi_respF_enqueueing$whas) && + wmemi_respF_c_r != 2'd0 && + wmemi_respF_enqueueing$whas ; + + // rule RL_getRequest + assign WILL_FIRE_RL_getRequest = + wmemi_operateD && wmemi_peerIsReady && wmemi_reqF$EMPTY_N && + IF_wmemi_reqF_first__11_BITS_51_TO_49_12_EQ_1__ETC___d320 && + !wci_wslv_wci_cfwr_pw$whas && + !wci_wslv_wci_cfrd_pw$whas ; + + // rule RL_wci_ctrl_IsO + assign WILL_FIRE_RL_wci_ctrl_IsO = + wci_wslv_wci_ctrl_pw$whas && + WILL_FIRE_RL_wci_wslv_ctl_op_start && + wci_wslv_cState == 3'd1 && + wci_wslv_reqF$D_OUT[36:34] == 3'd1 ; + + // rule RL_wci_wslv_ctl_op_complete + assign WILL_FIRE_RL_wci_wslv_ctl_op_complete = + wci_wslv_respF_c_r != 2'd2 && wci_wslv_ctlOpActive && + wci_wslv_ctlAckReg ; + + // rule RL_wci_wslv_respF_incCtr + assign WILL_FIRE_RL_wci_wslv_respF_incCtr = + ((wci_wslv_respF_c_r == 2'd0) ? + wci_wslv_respF_x_wire$whas : + wci_wslv_respF_c_r != 2'd1 || wci_wslv_respF_x_wire$whas) && + wci_wslv_respF_enqueueing$whas && + !(wci_wslv_respF_c_r != 2'd0) ; + + // rule RL_wci_wslv_respF_decCtr + assign WILL_FIRE_RL_wci_wslv_respF_decCtr = + wci_wslv_respF_c_r != 2'd0 && !wci_wslv_respF_enqueueing$whas ; + + // rule RL_wci_wslv_respF_both + assign WILL_FIRE_RL_wci_wslv_respF_both = + ((wci_wslv_respF_c_r == 2'd1) ? + wci_wslv_respF_x_wire$whas : + wci_wslv_respF_c_r != 2'd2 || wci_wslv_respF_x_wire$whas) && + wci_wslv_respF_c_r != 2'd0 && + wci_wslv_respF_enqueueing$whas ; + + // inputs to muxes for submodule ports + assign MUX_lreqF$enq_1__SEL_1 = + WILL_FIRE_RL_getRequest && + (wmemi_reqF$D_OUT[51:49] == 3'd1 || + wmemiReadInFlight_value_85_SLT_16___d591) ; + assign MUX_lreqF$enq_1__SEL_2 = + WILL_FIRE_RL_wci_cfwr && + (wci_wslv_reqF$D_OUT[51] || + wci_wslv_reqF$D_OUT[39:32] == 8'h54 || + wci_wslv_reqF$D_OUT[39:32] == 8'h58) ; + assign MUX_lreqF$enq_1__SEL_3 = + WILL_FIRE_RL_wci_cfrd && wci_wslv_reqF$D_OUT[51] ; + assign MUX_memc_avlBE$wset_1__SEL_1 = + WILL_FIRE_RL_memc_advance_request && !memc_reqF$D_OUT[176] ; + assign MUX_rdReg$write_1__SEL_1 = + WILL_FIRE_RL_wci_cfwr && !wci_wslv_reqF$D_OUT[51] && + wci_wslv_reqF$D_OUT[39:32] == 8'h80 ; + assign MUX_rdReg_1$write_1__SEL_1 = + WILL_FIRE_RL_wci_cfwr && !wci_wslv_reqF$D_OUT[51] && + wci_wslv_reqF$D_OUT[39:32] == 8'h84 ; + assign MUX_rdReg_2$write_1__SEL_1 = + WILL_FIRE_RL_wci_cfwr && !wci_wslv_reqF$D_OUT[51] && + wci_wslv_reqF$D_OUT[39:32] == 8'h88 ; + assign MUX_rdReg_3$write_1__SEL_1 = + WILL_FIRE_RL_wci_cfwr && !wci_wslv_reqF$D_OUT[51] && + wci_wslv_reqF$D_OUT[39:32] == 8'h8C ; + assign MUX_splitReadInFlight$write_1__SEL_1 = + WILL_FIRE_RL_advance_response && splitReadInFlight ; + assign MUX_wci_wslv_illegalEdge$write_1__SEL_1 = + WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge ; + assign MUX_wci_wslv_illegalEdge$write_1__SEL_2 = + WILL_FIRE_RL_wci_wslv_ctl_op_start && + (wci_wslv_reqF$D_OUT[36:34] == 3'd0 && wci_wslv_cState != 3'd0 || + wci_wslv_reqF$D_OUT[36:34] == 3'd1 && wci_wslv_cState != 3'd1 && + wci_wslv_cState != 3'd3 || + wci_wslv_reqF$D_OUT[36:34] == 3'd2 && wci_wslv_cState != 3'd2 || + wci_wslv_reqF$D_OUT[36:34] == 3'd3 && wci_wslv_cState != 3'd3 && + wci_wslv_cState != 3'd2 && + wci_wslv_cState != 3'd1 || + wci_wslv_reqF$D_OUT[36:34] == 3'd4 || + wci_wslv_reqF$D_OUT[36:34] == 3'd5 || + wci_wslv_reqF$D_OUT[36:34] == 3'd6 || + wci_wslv_reqF$D_OUT[36:34] == 3'd7) ; + assign MUX_wci_wslv_respF_q_0$write_1__SEL_2 = + WILL_FIRE_RL_wci_wslv_respF_incCtr && + wci_wslv_respF_c_r == 2'd0 ; + assign MUX_wci_wslv_respF_q_1$write_1__SEL_2 = + WILL_FIRE_RL_wci_wslv_respF_incCtr && + wci_wslv_respF_c_r == 2'd1 ; + assign MUX_wci_wslv_respF_x_wire$wset_1__SEL_2 = + WILL_FIRE_RL_wci_cfrd && !wci_wslv_reqF$D_OUT[51] ; + assign MUX_wmemi_respF_q_0$write_1__SEL_1 = + WILL_FIRE_RL_wmemi_respF_incCtr && wmemi_respF_c_r == 2'd0 ; + assign MUX_wmemi_respF_q_1$write_1__SEL_1 = + WILL_FIRE_RL_wmemi_respF_incCtr && wmemi_respF_c_r == 2'd1 ; + assign MUX_lreqF$enq_1__VAL_1 = + { wmemi_reqF$D_OUT[51:49] != 3'd1, + (wmemi_reqF$D_OUT[51:49] == 3'd1) ? + { wmemi_reqF$D_OUT[43:12], + wmemi_dhF$D_OUT[15:0], + wmemi_dhF$D_OUT[143:16] } : + { wmemi_reqF$D_OUT[43:0], + 132'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA } } ; + assign MUX_lreqF$enq_1__VAL_2 = + { !wci_wslv_reqF$D_OUT[51] && + wci_wslv_reqF$D_OUT[39:32] != 8'h54, + IF_wci_wslv_reqF_first__09_BIT_51_83_THEN_pReg_ETC___d434 } ; + assign MUX_lreqF$enq_1__VAL_3 = + { 1'd1, + x1_addr__h16199, + 144'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA } ; + assign MUX_wci_wslv_illegalEdge$write_1__VAL_2 = + wci_wslv_reqF$D_OUT[36:34] != 3'd4 && + wci_wslv_reqF$D_OUT[36:34] != 3'd5 && + wci_wslv_reqF$D_OUT[36:34] != 3'd6 ; + assign MUX_wci_wslv_respF_c_r$write_1__VAL_1 = wci_wslv_respF_c_r + 2'd1 ; + assign MUX_wci_wslv_respF_c_r$write_1__VAL_2 = wci_wslv_respF_c_r - 2'd1 ; + assign MUX_wci_wslv_respF_q_0$write_1__VAL_1 = + (wci_wslv_respF_c_r == 2'd1) ? + MUX_wci_wslv_respF_q_0$write_1__VAL_2 : + wci_wslv_respF_q_1 ; + always@(MUX_splitReadInFlight$write_1__SEL_1 or + MUX_wci_wslv_respF_x_wire$wset_1__VAL_1 or + MUX_wci_wslv_respF_x_wire$wset_1__SEL_2 or + MUX_wci_wslv_respF_x_wire$wset_1__VAL_2 or + WILL_FIRE_RL_wci_wslv_ctl_op_complete or + MUX_wci_wslv_respF_x_wire$wset_1__VAL_3 or WILL_FIRE_RL_wci_cfwr) + begin + case (1'b1) // synopsys parallel_case + MUX_splitReadInFlight$write_1__SEL_1: + MUX_wci_wslv_respF_q_0$write_1__VAL_2 = + MUX_wci_wslv_respF_x_wire$wset_1__VAL_1; + MUX_wci_wslv_respF_x_wire$wset_1__SEL_2: + MUX_wci_wslv_respF_q_0$write_1__VAL_2 = + MUX_wci_wslv_respF_x_wire$wset_1__VAL_2; + WILL_FIRE_RL_wci_wslv_ctl_op_complete: + MUX_wci_wslv_respF_q_0$write_1__VAL_2 = + MUX_wci_wslv_respF_x_wire$wset_1__VAL_3; + WILL_FIRE_RL_wci_cfwr: + MUX_wci_wslv_respF_q_0$write_1__VAL_2 = 34'h1C0DE4201; + default: MUX_wci_wslv_respF_q_0$write_1__VAL_2 = + 34'h2AAAAAAAA /* unspecified value */ ; + endcase + end + assign MUX_wci_wslv_respF_q_1$write_1__VAL_1 = + (wci_wslv_respF_c_r == 2'd2) ? + MUX_wci_wslv_respF_q_0$write_1__VAL_2 : + 34'h0AAAAAAAA ; + assign MUX_wci_wslv_respF_x_wire$wset_1__VAL_1 = { 2'd1, g_data__h13952 } ; + assign MUX_wci_wslv_respF_x_wire$wset_1__VAL_2 = { 2'd1, g_data__h17725 } ; + assign MUX_wci_wslv_respF_x_wire$wset_1__VAL_3 = + wci_wslv_illegalEdge ? 34'h3C0DE4202 : 34'h1C0DE4201 ; + assign MUX_wmemiReadInFlight_value$write_1__VAL_2 = + wmemiReadInFlight_value + + (wmemiReadInFlight_acc_v1$whas ? 8'd1 : 8'd0) + + (wmemi_respF_enqueueing$whas ? 8'd255 : 8'd0) ; + assign MUX_wmemi_respF_c_r$write_1__VAL_1 = wmemi_respF_c_r + 2'd1 ; + assign MUX_wmemi_respF_c_r$write_1__VAL_2 = wmemi_respF_c_r - 2'd1 ; + assign MUX_wmemi_respF_q_0$write_1__VAL_1 = { 3'd3, lrespF$dD_OUT } ; + assign MUX_wmemi_respF_q_0$write_1__VAL_2 = + (wmemi_respF_c_r == 2'd1) ? + MUX_wmemi_respF_q_0$write_1__VAL_1 : + wmemi_respF_q_1 ; + assign MUX_wmemi_respF_q_1$write_1__VAL_2 = + (wmemi_respF_c_r == 2'd2) ? + MUX_wmemi_respF_q_0$write_1__VAL_1 : + 131'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA ; + + // inlined wires + assign memc_avlBurstBegin$wget = 1'd1 ; + assign memc_avlBurstBegin$whas = WILL_FIRE_RL_memc_advance_request ; + assign memc_avlAddr$wget = memc_reqF$D_OUT[170:147] ; + assign memc_avlAddr$whas = + WILL_FIRE_RL_memc_advance_write1 || + WILL_FIRE_RL_memc_advance_request ; + assign memc_avlWData$wget = + MUX_memc_avlBE$wset_1__SEL_1 ? + memc_reqF$D_OUT[63:0] : + memc_reqF$D_OUT[127:64] ; + assign memc_avlWData$whas = + WILL_FIRE_RL_memc_advance_request && !memc_reqF$D_OUT[176] || + WILL_FIRE_RL_memc_advance_write1 ; + assign memc_avlBE$wget = + MUX_memc_avlBE$wset_1__SEL_1 ? + memc_reqF$D_OUT[135:128] : + memc_reqF$D_OUT[143:136] ; + assign memc_avlBE$whas = memc_avlWData$whas ; + assign memc_avlReadReq$wget = 1'd1 ; + assign memc_avlReadReq$whas = + WILL_FIRE_RL_memc_advance_request && memc_reqF$D_OUT[176] ; + assign memc_avlWriteReq$wget = 1'd1 ; + assign memc_avlWriteReq$whas = memc_avlWData$whas ; + assign memc_avlSize$wget = 3'd2 ; + assign memc_avlSize$whas = memc_avlAddr$whas ; + assign wci_wslv_wciReq$wget = + { wciS0_MCmd, + wciS0_MAddrSpace, + wciS0_MByteEn, + wciS0_MAddr, + wciS0_MData } ; + assign wci_wslv_wciReq$whas = 1'd1 ; + assign wci_wslv_respF_x_wire$wget = MUX_wci_wslv_respF_q_0$write_1__VAL_2 ; + assign wci_wslv_respF_x_wire$whas = + WILL_FIRE_RL_advance_response && splitReadInFlight || + WILL_FIRE_RL_wci_cfrd && !wci_wslv_reqF$D_OUT[51] || + WILL_FIRE_RL_wci_wslv_ctl_op_complete || + WILL_FIRE_RL_wci_cfwr ; + assign wci_wslv_wEdge$wget = wci_wslv_reqF$D_OUT[36:34] ; + assign wci_wslv_wEdge$whas = WILL_FIRE_RL_wci_wslv_ctl_op_start ; + assign wci_wslv_sFlagReg_1$wget = 1'b0 ; + assign wci_wslv_sFlagReg_1$whas = 1'b0 ; + assign wci_wslv_ctlAckReg_1$wget = 1'd1 ; + assign wci_wslv_ctlAckReg_1$whas = + WILL_FIRE_RL_wci_ctrl_OrE || WILL_FIRE_RL_wci_ctrl_IsO || + WILL_FIRE_RL_wci_ctrl_EiI ; + assign wci_wci_Es_mCmd_w$wget = wciS0_MCmd ; + assign wci_wci_Es_mCmd_w$whas = 1'd1 ; + assign wci_wci_Es_mAddrSpace_w$wget = wciS0_MAddrSpace ; + assign wci_wci_Es_mAddrSpace_w$whas = 1'd1 ; + assign wci_wci_Es_mByteEn_w$wget = wciS0_MByteEn ; + assign wci_wci_Es_mByteEn_w$whas = 1'd1 ; + assign wci_wci_Es_mAddr_w$wget = wciS0_MAddr ; + assign wci_wci_Es_mAddr_w$whas = 1'd1 ; + assign wci_wci_Es_mData_w$wget = wciS0_MData ; + assign wci_wci_Es_mData_w$whas = 1'd1 ; + assign wmemi_wmemiReq$wget = + { wmemiS0_MCmd, + wmemiS0_MReqLast, + wmemiS0_MAddr, + wmemiS0_MBurstLength } ; + assign wmemi_wmemiReq$whas = 1'd1 ; + assign wmemi_wmemiDh$wget = + { wmemiS0_MDataValid, + wmemiS0_MDataLast, + wmemiS0_MData, + wmemiS0_MDataByteEn } ; + assign wmemi_wmemiDh$whas = 1'd1 ; + assign wmemi_cmdAccept_w$wget = 1'd1 ; + assign wmemi_cmdAccept_w$whas = + wmemi_reqF$FULL_N && wmemi_operateD && wmemi_peerIsReady && + wmemi_wmemiReq$wget[51:49] != 3'd0 && + wmemi_reqF$FULL_N ; + assign wmemi_dhAccept_w$wget = 1'd1 ; + assign wmemi_dhAccept_w$whas = + wmemi_dhF$FULL_N && wmemi_operateD && wmemi_peerIsReady && + wmemi_wmemiDh$wget[145] && + wmemi_dhF$FULL_N ; + assign wmemi_respF_x_wire$wget = MUX_wmemi_respF_q_0$write_1__VAL_1 ; + assign wmemi_respF_x_wire$whas = wmemi_respF_enqueueing$whas ; + assign wmemi_operateD_1$wget = 1'd1 ; + assign wmemi_operateD_1$whas = wci_wslv_cState == 3'd2 ; + assign wmemi_peerIsReady_1$wget = 1'd1 ; + assign wmemi_peerIsReady_1$whas = wmemiS0_MReset_n ; + assign wmemiReadInFlight_acc_v1$wget = 8'd1 ; + assign wmemiReadInFlight_acc_v1$whas = + WILL_FIRE_RL_getRequest && wmemi_reqF$D_OUT[51:49] != 3'd1 && + wmemiReadInFlight_value_85_SLT_16___d591 ; + assign wmemiReadInFlight_acc_v2$wget = 8'd255 ; + assign wmemiReadInFlight_acc_v2$whas = wmemi_respF_enqueueing$whas ; + assign wmemi_Es_mCmd_w$wget = wmemiS0_MCmd ; + assign wmemi_Es_mCmd_w$whas = 1'd1 ; + assign wmemi_Es_mAddr_w$wget = wmemiS0_MAddr ; + assign wmemi_Es_mAddr_w$whas = 1'd1 ; + assign wmemi_Es_mBurstLength_w$wget = wmemiS0_MBurstLength ; + assign wmemi_Es_mBurstLength_w$whas = 1'd1 ; + assign wmemi_Es_mData_w$wget = wmemiS0_MData ; + assign wmemi_Es_mData_w$whas = 1'd1 ; + assign wmemi_Es_mDataByteEn_w$wget = wmemiS0_MDataByteEn ; + assign wmemi_Es_mDataByteEn_w$whas = 1'd1 ; + assign wci_wslv_reqF_r_enq$whas = wci_wslv_wciReq$wget[71:69] != 3'd0 ; + assign wci_wslv_reqF_r_deq$whas = + WILL_FIRE_RL_wci_cfrd || WILL_FIRE_RL_wci_cfwr || + WILL_FIRE_RL_wci_wslv_ctl_op_start ; + assign wci_wslv_reqF_r_clr$whas = 1'b0 ; + assign wci_wslv_respF_enqueueing$whas = + WILL_FIRE_RL_advance_response && splitReadInFlight || + WILL_FIRE_RL_wci_cfrd && !wci_wslv_reqF$D_OUT[51] || + WILL_FIRE_RL_wci_cfwr || + WILL_FIRE_RL_wci_wslv_ctl_op_complete ; + assign wci_wslv_respF_dequeueing$whas = wci_wslv_respF_c_r != 2'd0 ; + assign wci_wslv_sThreadBusy_pw$whas = 1'b0 ; + assign wci_wslv_wci_cfwr_pw$whas = + wci_wslv_reqF$EMPTY_N && wci_wslv_reqF$D_OUT[68] && + wci_wslv_reqF$D_OUT[71:69] == 3'd1 ; + assign wci_wslv_wci_cfrd_pw$whas = + wci_wslv_reqF$EMPTY_N && wci_wslv_reqF$D_OUT[68] && + wci_wslv_reqF$D_OUT[71:69] == 3'd2 ; + assign wci_wslv_wci_ctrl_pw$whas = + wci_wslv_reqF$EMPTY_N && !wci_wslv_reqF$D_OUT[68] && + wci_wslv_reqF$D_OUT[71:69] == 3'd2 ; + assign wmemi_respF_enqueueing$whas = + lrespF$dEMPTY_N && + lrespF_RDY_first__46_AND_NOT_wmemi_respF_c_r_2_ETC___d348 && + (wmemiReadInFlight_value ^ 8'h80) > 8'd128 ; + assign wmemi_respF_dequeueing$whas = wmemi_respF_c_r != 2'd0 ; + assign wmemi_Es_mReqLast_w$whas = wmemiS0_MReqLast ; + assign wmemi_Es_mDataValid_w$whas = wmemiS0_MDataValid ; + assign wmemi_Es_mDataLast_w$whas = wmemiS0_MDataLast ; + + // register dbgCtrl + assign dbgCtrl$D_IN = 32'h0 ; + assign dbgCtrl$EN = 1'b0 ; + + // register dramCtrl + assign dramCtrl$D_IN = wci_wslv_reqF$D_OUT[31:0] ; + assign dramCtrl$EN = + WILL_FIRE_RL_wci_cfwr && !wci_wslv_reqF$D_OUT[51] && + wci_wslv_reqF$D_OUT[39:32] == 8'h04 ; + + // register mReg + assign mReg$D_IN = wci_wslv_reqF$D_OUT[15:0] ; + assign mReg$EN = + WILL_FIRE_RL_wci_cfwr && !wci_wslv_reqF$D_OUT[51] && + wci_wslv_reqF$D_OUT[39:32] == 8'h5C ; + + // register memIsReset_isInReset + assign memIsReset_isInReset$D_IN = 1'd0 ; + assign memIsReset_isInReset$EN = memIsReset_isInReset ; + + // register memc_afiCount + assign memc_afiCount$D_IN = memc_afiCount + 4'd1 ; + assign memc_afiCount$EN = 1'd1 ; + + // register memc_curCount + assign memc_curCount$D_IN = memc_curCount + 4'd1 ; + assign memc_curCount$EN = 1'd1 ; + + // register memc_dbg_reqCount + assign memc_dbg_reqCount$D_IN = memc_dbg_reqCount + 16'd1 ; + assign memc_dbg_reqCount$EN = WILL_FIRE_RL_memc_advance_request ; + + // register memc_dbg_respCount + assign memc_dbg_respCount$D_IN = memc_dbg_respCount + 16'd1 ; + assign memc_dbg_respCount$EN = + WILL_FIRE_RL_memc_advance_readResponse && memc_secondRdBeat ; + + // register memc_rdStageLS + assign memc_rdStageLS$D_IN = memc_memc$avl_rdata ; + assign memc_rdStageLS$EN = + WILL_FIRE_RL_memc_advance_readResponse && !memc_secondRdBeat ; + + // register memc_secondRdBeat + assign memc_secondRdBeat$D_IN = !memc_secondRdBeat ; + assign memc_secondRdBeat$EN = WILL_FIRE_RL_memc_advance_readResponse ; + + // register memc_secondWrBeat + assign memc_secondWrBeat$D_IN = MUX_memc_avlBE$wset_1__SEL_1 ; + assign memc_secondWrBeat$EN = memc_avlWData$whas ; + + // register memc_sysCount + assign memc_sysCount$D_IN = memc_sysCount + 4'd1 ; + assign memc_sysCount$EN = 1'd1 ; + + // register pReg + assign pReg$D_IN = wci_wslv_reqF$D_OUT[15:0] ; + assign pReg$EN = + WILL_FIRE_RL_wci_cfwr && !wci_wslv_reqF$D_OUT[51] && + wci_wslv_reqF$D_OUT[39:32] == 8'h50 ; + + // register rdReg + assign rdReg$D_IN = + MUX_rdReg$write_1__SEL_1 ? + wci_wslv_reqF$D_OUT[31:0] : + lrespF$dD_OUT[31:0] ; + assign rdReg$EN = + WILL_FIRE_RL_wci_cfwr && !wci_wslv_reqF$D_OUT[51] && + wci_wslv_reqF$D_OUT[39:32] == 8'h80 || + WILL_FIRE_RL_advance_response ; + + // register rdReg_1 + assign rdReg_1$D_IN = + MUX_rdReg_1$write_1__SEL_1 ? + wci_wslv_reqF$D_OUT[31:0] : + lrespF$dD_OUT[63:32] ; + assign rdReg_1$EN = + WILL_FIRE_RL_wci_cfwr && !wci_wslv_reqF$D_OUT[51] && + wci_wslv_reqF$D_OUT[39:32] == 8'h84 || + WILL_FIRE_RL_advance_response ; + + // register rdReg_2 + assign rdReg_2$D_IN = + MUX_rdReg_2$write_1__SEL_1 ? + wci_wslv_reqF$D_OUT[31:0] : + lrespF$dD_OUT[95:64] ; + assign rdReg_2$EN = + WILL_FIRE_RL_wci_cfwr && !wci_wslv_reqF$D_OUT[51] && + wci_wslv_reqF$D_OUT[39:32] == 8'h88 || + WILL_FIRE_RL_advance_response ; + + // register rdReg_3 + assign rdReg_3$D_IN = + MUX_rdReg_3$write_1__SEL_1 ? + wci_wslv_reqF$D_OUT[31:0] : + lrespF$dD_OUT[127:96] ; + assign rdReg_3$EN = + WILL_FIRE_RL_wci_cfwr && !wci_wslv_reqF$D_OUT[51] && + wci_wslv_reqF$D_OUT[39:32] == 8'h8C || + WILL_FIRE_RL_advance_response ; + + // register respCount + assign respCount$D_IN = respCount + 8'd1 ; + assign respCount$EN = WILL_FIRE_RL_advance_response ; + + // register splitReadInFlight + assign splitReadInFlight$D_IN = !MUX_splitReadInFlight$write_1__SEL_1 ; + assign splitReadInFlight$EN = + WILL_FIRE_RL_advance_response && splitReadInFlight || + WILL_FIRE_RL_wci_cfrd && wci_wslv_reqF$D_OUT[51] ; + + // register wci_wslv_cEdge + assign wci_wslv_cEdge$D_IN = wci_wslv_reqF$D_OUT[36:34] ; + assign wci_wslv_cEdge$EN = WILL_FIRE_RL_wci_wslv_ctl_op_start ; + + // register wci_wslv_cState + assign wci_wslv_cState$D_IN = wci_wslv_nState ; + assign wci_wslv_cState$EN = + WILL_FIRE_RL_wci_wslv_ctl_op_complete && !wci_wslv_illegalEdge ; + + // register wci_wslv_ctlAckReg + assign wci_wslv_ctlAckReg$D_IN = wci_wslv_ctlAckReg_1$whas ; + assign wci_wslv_ctlAckReg$EN = 1'd1 ; + + // register wci_wslv_ctlOpActive + assign wci_wslv_ctlOpActive$D_IN = !WILL_FIRE_RL_wci_wslv_ctl_op_complete ; + assign wci_wslv_ctlOpActive$EN = + WILL_FIRE_RL_wci_wslv_ctl_op_complete || + WILL_FIRE_RL_wci_wslv_ctl_op_start ; + + // register wci_wslv_illegalEdge + assign wci_wslv_illegalEdge$D_IN = + !MUX_wci_wslv_illegalEdge$write_1__SEL_1 && + MUX_wci_wslv_illegalEdge$write_1__VAL_2 ; + assign wci_wslv_illegalEdge$EN = + WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge || + MUX_wci_wslv_illegalEdge$write_1__SEL_2 ; + + // register wci_wslv_isReset_isInReset + assign wci_wslv_isReset_isInReset$D_IN = 1'd0 ; + assign wci_wslv_isReset_isInReset$EN = wci_wslv_isReset_isInReset ; + + // register wci_wslv_nState + always@(wci_wslv_reqF$D_OUT) + begin + case (wci_wslv_reqF$D_OUT[36:34]) + 3'd0: wci_wslv_nState$D_IN = 3'd1; + 3'd1: wci_wslv_nState$D_IN = 3'd2; + 3'd2: wci_wslv_nState$D_IN = 3'd3; + default: wci_wslv_nState$D_IN = 3'd0; + endcase + end + assign wci_wslv_nState$EN = + WILL_FIRE_RL_wci_wslv_ctl_op_start && + (wci_wslv_reqF$D_OUT[36:34] == 3'd0 && wci_wslv_cState == 3'd0 || + wci_wslv_reqF$D_OUT[36:34] == 3'd1 && + (wci_wslv_cState == 3'd1 || wci_wslv_cState == 3'd3) || + wci_wslv_reqF$D_OUT[36:34] == 3'd2 && wci_wslv_cState == 3'd2 || + wci_wslv_reqF$D_OUT[36:34] == 3'd3 && + (wci_wslv_cState == 3'd3 || wci_wslv_cState == 3'd2 || + wci_wslv_cState == 3'd1)) ; + + // register wci_wslv_reqF_countReg + assign wci_wslv_reqF_countReg$D_IN = + (wci_wslv_wciReq$wget[71:69] != 3'd0) ? + wci_wslv_reqF_countReg + 2'd1 : + wci_wslv_reqF_countReg - 2'd1 ; + assign wci_wslv_reqF_countReg$EN = + (wci_wslv_wciReq$wget[71:69] != 3'd0) != + wci_wslv_reqF_r_deq$whas ; + + // register wci_wslv_respF_c_r + assign wci_wslv_respF_c_r$D_IN = + WILL_FIRE_RL_wci_wslv_respF_incCtr ? + MUX_wci_wslv_respF_c_r$write_1__VAL_1 : + MUX_wci_wslv_respF_c_r$write_1__VAL_2 ; + assign wci_wslv_respF_c_r$EN = + WILL_FIRE_RL_wci_wslv_respF_incCtr || + WILL_FIRE_RL_wci_wslv_respF_decCtr ; + + // register wci_wslv_respF_q_0 + always@(WILL_FIRE_RL_wci_wslv_respF_both or + MUX_wci_wslv_respF_q_0$write_1__VAL_1 or + MUX_wci_wslv_respF_q_0$write_1__SEL_2 or + MUX_wci_wslv_respF_q_0$write_1__VAL_2 or + WILL_FIRE_RL_wci_wslv_respF_decCtr or wci_wslv_respF_q_1) + begin + case (1'b1) // synopsys parallel_case + WILL_FIRE_RL_wci_wslv_respF_both: + wci_wslv_respF_q_0$D_IN = MUX_wci_wslv_respF_q_0$write_1__VAL_1; + MUX_wci_wslv_respF_q_0$write_1__SEL_2: + wci_wslv_respF_q_0$D_IN = MUX_wci_wslv_respF_q_0$write_1__VAL_2; + WILL_FIRE_RL_wci_wslv_respF_decCtr: + wci_wslv_respF_q_0$D_IN = wci_wslv_respF_q_1; + default: wci_wslv_respF_q_0$D_IN = + 34'h2AAAAAAAA /* unspecified value */ ; + endcase + end + assign wci_wslv_respF_q_0$EN = + WILL_FIRE_RL_wci_wslv_respF_both || + WILL_FIRE_RL_wci_wslv_respF_incCtr && + wci_wslv_respF_c_r == 2'd0 || + WILL_FIRE_RL_wci_wslv_respF_decCtr ; + + // register wci_wslv_respF_q_1 + always@(WILL_FIRE_RL_wci_wslv_respF_both or + MUX_wci_wslv_respF_q_1$write_1__VAL_1 or + MUX_wci_wslv_respF_q_1$write_1__SEL_2 or + MUX_wci_wslv_respF_q_0$write_1__VAL_2 or + WILL_FIRE_RL_wci_wslv_respF_decCtr) + begin + case (1'b1) // synopsys parallel_case + WILL_FIRE_RL_wci_wslv_respF_both: + wci_wslv_respF_q_1$D_IN = MUX_wci_wslv_respF_q_1$write_1__VAL_1; + MUX_wci_wslv_respF_q_1$write_1__SEL_2: + wci_wslv_respF_q_1$D_IN = MUX_wci_wslv_respF_q_0$write_1__VAL_2; + WILL_FIRE_RL_wci_wslv_respF_decCtr: + wci_wslv_respF_q_1$D_IN = 34'h0AAAAAAAA; + default: wci_wslv_respF_q_1$D_IN = + 34'h2AAAAAAAA /* unspecified value */ ; + endcase + end + assign wci_wslv_respF_q_1$EN = + WILL_FIRE_RL_wci_wslv_respF_both || + WILL_FIRE_RL_wci_wslv_respF_incCtr && + wci_wslv_respF_c_r == 2'd1 || + WILL_FIRE_RL_wci_wslv_respF_decCtr ; + + // register wci_wslv_sFlagReg + assign wci_wslv_sFlagReg$D_IN = 1'b0 ; + assign wci_wslv_sFlagReg$EN = 1'd1 ; + + // register wci_wslv_sThreadBusy_d + assign wci_wslv_sThreadBusy_d$D_IN = 1'b0 ; + assign wci_wslv_sThreadBusy_d$EN = 1'd1 ; + + // register wdReg + assign wdReg$D_IN = wci_wslv_reqF$D_OUT[31:0] ; + assign wdReg$EN = + WILL_FIRE_RL_wci_cfwr && !wci_wslv_reqF$D_OUT[51] && + wci_wslv_reqF$D_OUT[39:32] == 8'h60 ; + + // register wdReg_1 + assign wdReg_1$D_IN = wci_wslv_reqF$D_OUT[31:0] ; + assign wdReg_1$EN = + WILL_FIRE_RL_wci_cfwr && !wci_wslv_reqF$D_OUT[51] && + wci_wslv_reqF$D_OUT[39:32] == 8'h64 ; + + // register wdReg_2 + assign wdReg_2$D_IN = wci_wslv_reqF$D_OUT[31:0] ; + assign wdReg_2$EN = + WILL_FIRE_RL_wci_cfwr && !wci_wslv_reqF$D_OUT[51] && + wci_wslv_reqF$D_OUT[39:32] == 8'h68 ; + + // register wdReg_3 + assign wdReg_3$D_IN = wci_wslv_reqF$D_OUT[31:0] ; + assign wdReg_3$EN = + WILL_FIRE_RL_wci_cfwr && !wci_wslv_reqF$D_OUT[51] && + wci_wslv_reqF$D_OUT[39:32] == 8'h6C ; + + // register wmemiRdReq + assign wmemiRdReq$D_IN = wmemiRdReq + 32'd1 ; + assign wmemiRdReq$EN = wmemiReadInFlight_acc_v1$whas ; + + // register wmemiRdResp + assign wmemiRdResp$D_IN = wmemiRdResp + 32'd1 ; + assign wmemiRdResp$EN = wmemi_respF_enqueueing$whas ; + + // register wmemiReadInFlight_value + assign wmemiReadInFlight_value$D_IN = + WILL_FIRE_RL_wci_ctrl_IsO ? + 8'd0 : + MUX_wmemiReadInFlight_value$write_1__VAL_2 ; + assign wmemiReadInFlight_value$EN = 1'b1 ; + + // register wmemiWrReq + assign wmemiWrReq$D_IN = wmemiWrReq + 32'd1 ; + assign wmemiWrReq$EN = + WILL_FIRE_RL_getRequest && wmemi_reqF$D_OUT[51:49] == 3'd1 ; + + // register wmemi_errorSticky + assign wmemi_errorSticky$D_IN = 1'b0 ; + assign wmemi_errorSticky$EN = 1'b0 ; + + // register wmemi_isReset_isInReset + assign wmemi_isReset_isInReset$D_IN = 1'd0 ; + assign wmemi_isReset_isInReset$EN = wmemi_isReset_isInReset ; + + // register wmemi_operateD + assign wmemi_operateD$D_IN = wci_wslv_cState == 3'd2 ; + assign wmemi_operateD$EN = 1'd1 ; + + // register wmemi_peerIsReady + assign wmemi_peerIsReady$D_IN = wmemiS0_MReset_n ; + assign wmemi_peerIsReady$EN = 1'd1 ; + + // register wmemi_respF_c_r + assign wmemi_respF_c_r$D_IN = + WILL_FIRE_RL_wmemi_respF_incCtr ? + MUX_wmemi_respF_c_r$write_1__VAL_1 : + MUX_wmemi_respF_c_r$write_1__VAL_2 ; + assign wmemi_respF_c_r$EN = + WILL_FIRE_RL_wmemi_respF_incCtr || + WILL_FIRE_RL_wmemi_respF_decCtr ; + + // register wmemi_respF_q_0 + always@(MUX_wmemi_respF_q_0$write_1__SEL_1 or + MUX_wmemi_respF_q_0$write_1__VAL_1 or + WILL_FIRE_RL_wmemi_respF_both or + MUX_wmemi_respF_q_0$write_1__VAL_2 or + WILL_FIRE_RL_wmemi_respF_decCtr or wmemi_respF_q_1) + begin + case (1'b1) // synopsys parallel_case + MUX_wmemi_respF_q_0$write_1__SEL_1: + wmemi_respF_q_0$D_IN = MUX_wmemi_respF_q_0$write_1__VAL_1; + WILL_FIRE_RL_wmemi_respF_both: + wmemi_respF_q_0$D_IN = MUX_wmemi_respF_q_0$write_1__VAL_2; + WILL_FIRE_RL_wmemi_respF_decCtr: wmemi_respF_q_0$D_IN = wmemi_respF_q_1; + default: wmemi_respF_q_0$D_IN = + 131'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ; + endcase + end + assign wmemi_respF_q_0$EN = + WILL_FIRE_RL_wmemi_respF_incCtr && wmemi_respF_c_r == 2'd0 || + WILL_FIRE_RL_wmemi_respF_both || + WILL_FIRE_RL_wmemi_respF_decCtr ; + + // register wmemi_respF_q_1 + always@(MUX_wmemi_respF_q_1$write_1__SEL_1 or + MUX_wmemi_respF_q_0$write_1__VAL_1 or + WILL_FIRE_RL_wmemi_respF_both or + MUX_wmemi_respF_q_1$write_1__VAL_2 or + WILL_FIRE_RL_wmemi_respF_decCtr) + begin + case (1'b1) // synopsys parallel_case + MUX_wmemi_respF_q_1$write_1__SEL_1: + wmemi_respF_q_1$D_IN = MUX_wmemi_respF_q_0$write_1__VAL_1; + WILL_FIRE_RL_wmemi_respF_both: + wmemi_respF_q_1$D_IN = MUX_wmemi_respF_q_1$write_1__VAL_2; + WILL_FIRE_RL_wmemi_respF_decCtr: + wmemi_respF_q_1$D_IN = 131'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; + default: wmemi_respF_q_1$D_IN = + 131'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ; + endcase + end + assign wmemi_respF_q_1$EN = + WILL_FIRE_RL_wmemi_respF_incCtr && wmemi_respF_c_r == 2'd1 || + WILL_FIRE_RL_wmemi_respF_both || + WILL_FIRE_RL_wmemi_respF_decCtr ; + + // register wmemi_statusR + assign wmemi_statusR$D_IN = + { wmemi_isReset_isInReset, + !wmemi_peerIsReady, + !wmemi_operateD, + wmemi_errorSticky, + 3'd0, + wmemi_trafficSticky } ; + assign wmemi_statusR$EN = 1'd1 ; + + // register wmemi_trafficSticky + assign wmemi_trafficSticky$D_IN = 1'd1 ; + assign wmemi_trafficSticky$EN = wmemi_cmdAccept_w$whas ; + + // submodule calFail + assign calFail$sD_IN = memc_memc$local_cal_fail ; + assign calFail$sEN = 1'd1 ; + + // submodule calSuccess + assign calSuccess$sD_IN = memc_memc$local_cal_success ; + assign calSuccess$sEN = 1'd1 ; + + // submodule initDone + assign initDone$sD_IN = memc_memc$local_init_done ; + assign initDone$sEN = 1'd1 ; + + // submodule lreqF + always@(MUX_lreqF$enq_1__SEL_1 or + MUX_lreqF$enq_1__VAL_1 or + MUX_lreqF$enq_1__SEL_2 or + MUX_lreqF$enq_1__VAL_2 or + MUX_lreqF$enq_1__SEL_3 or MUX_lreqF$enq_1__VAL_3) + begin + case (1'b1) // synopsys parallel_case + MUX_lreqF$enq_1__SEL_1: lreqF$sD_IN = MUX_lreqF$enq_1__VAL_1; + MUX_lreqF$enq_1__SEL_2: lreqF$sD_IN = MUX_lreqF$enq_1__VAL_2; + MUX_lreqF$enq_1__SEL_3: lreqF$sD_IN = MUX_lreqF$enq_1__VAL_3; + default: lreqF$sD_IN = + 177'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ; + endcase + end + assign lreqF$sENQ = + WILL_FIRE_RL_getRequest && + (wmemi_reqF$D_OUT[51:49] == 3'd1 || + wmemiReadInFlight_value_85_SLT_16___d591) || + WILL_FIRE_RL_wci_cfwr && + (wci_wslv_reqF$D_OUT[51] || + wci_wslv_reqF$D_OUT[39:32] == 8'h54 || + wci_wslv_reqF$D_OUT[39:32] == 8'h58) || + WILL_FIRE_RL_wci_cfrd && wci_wslv_reqF$D_OUT[51] ; + assign lreqF$dDEQ = lreqF$dEMPTY_N && memc_reqF$FULL_N ; + + // submodule lrespF + assign lrespF$sD_IN = memc_respF$D_OUT ; + assign lrespF$sENQ = lrespF$sFULL_N && memc_respF$EMPTY_N ; + assign lrespF$dDEQ = + lrespF$dEMPTY_N && + lrespF_RDY_first__46_AND_NOT_wmemi_respF_c_r_2_ETC___d348 && + (wmemiReadInFlight_value ^ 8'h80) > 8'd128 || + WILL_FIRE_RL_advance_response ; + + // submodule memIsResetCC + assign memIsResetCC$sD_IN = memIsReset_isInReset ; + assign memIsResetCC$sEN = 1'd1 ; + + // submodule memc_afiActive + assign memc_afiActive$sD_IN = memc_afiCount[3] ; + assign memc_afiActive$sEN = 1'd1 ; + + // submodule memc_memc + assign memc_memc$avl_addr = + memc_avlAddr$whas ? memc_reqF$D_OUT[170:147] : 24'd0 ; + assign memc_memc$avl_be = memc_avlWData$whas ? memc_avlBE$wget : 8'd0 ; + assign memc_memc$avl_burstbegin = WILL_FIRE_RL_memc_advance_request ; + assign memc_memc$avl_read_req = memc_avlReadReq$whas ; + assign memc_memc$avl_size = memc_avlAddr$whas ? 3'd2 : 3'd0 ; + assign memc_memc$avl_wdata = + memc_avlWData$whas ? memc_avlWData$wget : 64'd0 ; + assign memc_memc$avl_write_req = memc_avlWData$whas ; + assign memc_memc$oct_rdn = dram_rdn_i ; + assign memc_memc$oct_rup = dram_rup_i ; + + // submodule memc_reqF + assign memc_reqF$D_IN = lreqF$dD_OUT ; + assign memc_reqF$ENQ = lreqF$dEMPTY_N && memc_reqF$FULL_N ; + assign memc_reqF$DEQ = + WILL_FIRE_RL_memc_advance_request && memc_reqF$D_OUT[176] || + WILL_FIRE_RL_memc_advance_write1 ; + assign memc_reqF$CLR = 1'b0 ; + + // submodule memc_respF + assign memc_respF$D_IN = { memc_memc$avl_rdata, memc_rdStageLS } ; + assign memc_respF$CLR = 1'b0 ; + assign memc_respF$DEQ = lrespF$sFULL_N && memc_respF$EMPTY_N ; + assign memc_respF$ENQ = + WILL_FIRE_RL_memc_advance_readResponse && memc_secondRdBeat ; + + // submodule memc_sysActive + assign memc_sysActive$sD_IN = memc_sysCount[3] ; + assign memc_sysActive$sEN = 1'd1 ; + + // submodule requestCount + assign requestCount$sD_IN = memc_dbg_reqCount ; + assign requestCount$sEN = requestCount$sRDY && responseCount$sRDY ; + + // submodule responseCount + assign responseCount$sD_IN = memc_dbg_respCount ; + assign responseCount$sEN = requestCount$sRDY && responseCount$sRDY ; + + // submodule splaF + assign splaF$D_IN = wci_wslv_reqF$D_OUT[35:34] ; + assign splaF$ENQ = MUX_lreqF$enq_1__SEL_3 ; + assign splaF$DEQ = MUX_splitReadInFlight$write_1__SEL_1 ; + assign splaF$CLR = 1'b0 ; + + // submodule wci_wslv_reqF + assign wci_wslv_reqF$D_IN = wci_wslv_wciReq$wget ; + assign wci_wslv_reqF$ENQ = wci_wslv_wciReq$wget[71:69] != 3'd0 ; + assign wci_wslv_reqF$DEQ = wci_wslv_reqF_r_deq$whas ; + assign wci_wslv_reqF$CLR = 1'b0 ; + + // submodule wmemi_dhF + assign wmemi_dhF$D_IN = wmemi_wmemiDh$wget ; + assign wmemi_dhF$ENQ = wmemi_dhAccept_w$whas ; + assign wmemi_dhF$DEQ = + WILL_FIRE_RL_getRequest && wmemi_reqF$D_OUT[51:49] == 3'd1 ; + assign wmemi_dhF$CLR = 1'b0 ; + + // submodule wmemi_reqF + assign wmemi_reqF$D_IN = wmemi_wmemiReq$wget ; + assign wmemi_reqF$ENQ = wmemi_cmdAccept_w$whas ; + assign wmemi_reqF$DEQ = WILL_FIRE_RL_getRequest ; + assign wmemi_reqF$CLR = 1'b0 ; + + // remaining internal signals + assign IF_wci_wslv_reqF_first__09_BIT_51_83_THEN_lreq_ETC___d459 = + wci_wslv_reqF$D_OUT[51] ? + lreqF$sFULL_N && splaF$FULL_N : + wci_wslv_respF_c_r != 2'd2 ; + assign IF_wci_wslv_reqF_first__09_BIT_51_83_THEN_pReg_ETC___d434 = + wci_wslv_reqF$D_OUT[51] ? + { x1_addr__h16199, x1_be__h16200, x1_data__h16201 } : + { wci_wslv_reqF$D_OUT[31:0], mReg, x1_data__h15200 } ; + assign IF_wmemi_reqF_first__11_BITS_51_TO_49_12_EQ_1__ETC___d320 = + (wmemi_reqF$D_OUT[51:49] == 3'd1) ? + lreqF$sFULL_N && wmemi_dhF$EMPTY_N : + !wmemiReadInFlight_value_85_SLT_16___d591 || lreqF$sFULL_N ; + assign activeBits__h2005 = + { memc_curCount[3], + memc_sysActive$dD_OUT, + memc_afiActive$dD_OUT } ; + assign dramStatus__h12575 = { 16'd0, x__h17765 } ; + assign g_data__h17725 = + wci_wslv_reqF$D_OUT[51] ? + 32'd0 : + IF_wci_wslv_reqF_first__09_BITS_39_TO_32_84_EQ_ETC___d512 ; + assign lrespF_RDY_first__46_AND_NOT_splitReadInFlight_ETC___d362 = + lrespF$dEMPTY_N && + (!splitReadInFlight || + wci_wslv_respF_c_r != 2'd2 && splaF$EMPTY_N) ; + assign lrespF_RDY_first__46_AND_NOT_wmemi_respF_c_r_2_ETC___d348 = + lrespF$dEMPTY_N && wmemi_respF_c_r != 2'd2 && wmemi_operateD && + wmemi_peerIsReady ; + assign rdat___1__h17815 = + hasDebugLogic ? { 16'd0, requestCount$dD_OUT } : 32'd0 ; + assign rdat___1__h17826 = hasDebugLogic ? 32'hC0DE4002 : 32'd0 ; + assign rdat___1__h17832 = hasDebugLogic ? { 16'd0, pReg } : 32'd0 ; + assign rdat___1__h17842 = hasDebugLogic ? { 16'd0, mReg } : 32'd0 ; + assign rdat___1__h17852 = hasDebugLogic ? wdReg : 32'd0 ; + assign rdat___1__h17866 = hasDebugLogic ? wdReg_1 : 32'd0 ; + assign rdat___1__h17880 = hasDebugLogic ? wdReg_2 : 32'd0 ; + assign rdat___1__h17894 = hasDebugLogic ? wdReg_3 : 32'd0 ; + assign rdat___1__h17908 = hasDebugLogic ? rdReg : 32'd0 ; + assign rdat___1__h17923 = hasDebugLogic ? rdReg_1 : 32'd0 ; + assign rdat___1__h17938 = hasDebugLogic ? rdReg_2 : 32'd0 ; + assign rdat___1__h17953 = hasDebugLogic ? rdReg_3 : 32'd0 ; + assign wci_wslv_reqF_i_notEmpty__08_AND_IF_wci_wslv_r_ETC___d395 = + wci_wslv_reqF$EMPTY_N && + (wci_wslv_reqF$D_OUT[51] ? + lreqF$sFULL_N : + ((wci_wslv_reqF$D_OUT[39:32] == 8'h54) ? + lreqF$sFULL_N : + wci_wslv_reqF$D_OUT[39:32] != 8'h58 || lreqF$sFULL_N)) ; + assign wmemiReadInFlight_value_85_SLT_16___d591 = + (wmemiReadInFlight_value ^ 8'h80) < 8'd144 ; + assign x1_addr__h16199 = { pReg[12:0], wci_wslv_reqF$D_OUT[50:36], 4'd0 } ; + assign x1_be__h16200 = + { (wci_wslv_reqF$D_OUT[35:34] == 2'd3) ? 4'hF : 4'h0, + (wci_wslv_reqF$D_OUT[35:34] == 2'd2) ? 4'hF : 4'h0, + (wci_wslv_reqF$D_OUT[35:34] == 2'd1) ? 4'hF : 4'h0, + (wci_wslv_reqF$D_OUT[35:34] == 2'd0) ? 4'hF : 4'h0 } ; + assign x1_data__h15200 = { wdReg_3, wdReg_2, wdReg_1, wdReg } ; + assign x1_data__h16201 = {4{wci_wslv_reqF$D_OUT[31:0]}} ; + assign x__h17765 = + { respCount, + 1'h0, + activeBits__h2005, + memIsResetCC$dD_OUT, + calFail$dD_OUT, + calSuccess$dD_OUT, + initDone$dD_OUT } ; + always@(splaF$D_OUT or lrespF$dD_OUT) + begin + case (splaF$D_OUT) + 2'd0: g_data__h13952 = lrespF$dD_OUT[31:0]; + 2'd1: g_data__h13952 = lrespF$dD_OUT[63:32]; + 2'd2: g_data__h13952 = lrespF$dD_OUT[95:64]; + 2'd3: g_data__h13952 = lrespF$dD_OUT[127:96]; + endcase + end + always@(wci_wslv_reqF$D_OUT or + dramStatus__h12575 or + dramCtrl or + rdat___1__h17815 or + rdat___1__h17826 or + rdat___1__h17832 or + rdat___1__h17842 or + rdat___1__h17852 or + rdat___1__h17866 or + rdat___1__h17880 or + rdat___1__h17894 or + rdat___1__h17908 or + rdat___1__h17923 or rdat___1__h17938 or rdat___1__h17953) + begin + case (wci_wslv_reqF$D_OUT[39:32]) + 8'h0: + IF_wci_wslv_reqF_first__09_BITS_39_TO_32_84_EQ_ETC___d512 = + dramStatus__h12575; + 8'h04: + IF_wci_wslv_reqF_first__09_BITS_39_TO_32_84_EQ_ETC___d512 = + dramCtrl; + 8'h48: + IF_wci_wslv_reqF_first__09_BITS_39_TO_32_84_EQ_ETC___d512 = + rdat___1__h17815; + 8'h4C: + IF_wci_wslv_reqF_first__09_BITS_39_TO_32_84_EQ_ETC___d512 = + rdat___1__h17826; + 8'h50: + IF_wci_wslv_reqF_first__09_BITS_39_TO_32_84_EQ_ETC___d512 = + rdat___1__h17832; + 8'h5C: + IF_wci_wslv_reqF_first__09_BITS_39_TO_32_84_EQ_ETC___d512 = + rdat___1__h17842; + 8'h60: + IF_wci_wslv_reqF_first__09_BITS_39_TO_32_84_EQ_ETC___d512 = + rdat___1__h17852; + 8'h64: + IF_wci_wslv_reqF_first__09_BITS_39_TO_32_84_EQ_ETC___d512 = + rdat___1__h17866; + 8'h68: + IF_wci_wslv_reqF_first__09_BITS_39_TO_32_84_EQ_ETC___d512 = + rdat___1__h17880; + 8'h6C: + IF_wci_wslv_reqF_first__09_BITS_39_TO_32_84_EQ_ETC___d512 = + rdat___1__h17894; + 8'h80: + IF_wci_wslv_reqF_first__09_BITS_39_TO_32_84_EQ_ETC___d512 = + rdat___1__h17908; + 8'h84: + IF_wci_wslv_reqF_first__09_BITS_39_TO_32_84_EQ_ETC___d512 = + rdat___1__h17923; + 8'h88: + IF_wci_wslv_reqF_first__09_BITS_39_TO_32_84_EQ_ETC___d512 = + rdat___1__h17938; + 8'h8C: + IF_wci_wslv_reqF_first__09_BITS_39_TO_32_84_EQ_ETC___d512 = + rdat___1__h17953; + default: IF_wci_wslv_reqF_first__09_BITS_39_TO_32_84_EQ_ETC___d512 = + 32'd0; + endcase + end + + // handling of inlined registers + + always@(posedge wciS0_Clk) + begin + if (wciS0_MReset_n == `BSV_RESET_VALUE) + begin + dramCtrl <= `BSV_ASSIGNMENT_DELAY 32'd0; + mReg <= `BSV_ASSIGNMENT_DELAY 16'd0; + memc_curCount <= `BSV_ASSIGNMENT_DELAY 4'd0; + pReg <= `BSV_ASSIGNMENT_DELAY 16'd0; + rdReg <= `BSV_ASSIGNMENT_DELAY 32'd0; + rdReg_1 <= `BSV_ASSIGNMENT_DELAY 32'd0; + rdReg_2 <= `BSV_ASSIGNMENT_DELAY 32'd0; + rdReg_3 <= `BSV_ASSIGNMENT_DELAY 32'd0; + respCount <= `BSV_ASSIGNMENT_DELAY 8'd0; + splitReadInFlight <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_wslv_cEdge <= `BSV_ASSIGNMENT_DELAY 3'h2; + wci_wslv_cState <= `BSV_ASSIGNMENT_DELAY 3'd0; + wci_wslv_ctlAckReg <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_wslv_ctlOpActive <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_wslv_illegalEdge <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_wslv_nState <= `BSV_ASSIGNMENT_DELAY 3'd0; + wci_wslv_reqF_countReg <= `BSV_ASSIGNMENT_DELAY 2'd0; + wci_wslv_respF_c_r <= `BSV_ASSIGNMENT_DELAY 2'd0; + wci_wslv_respF_q_0 <= `BSV_ASSIGNMENT_DELAY 34'h0AAAAAAAA; + wci_wslv_respF_q_1 <= `BSV_ASSIGNMENT_DELAY 34'h0AAAAAAAA; + wci_wslv_sFlagReg <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_wslv_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY 1'd1; + wdReg <= `BSV_ASSIGNMENT_DELAY 32'd0; + wdReg_1 <= `BSV_ASSIGNMENT_DELAY 32'd0; + wdReg_2 <= `BSV_ASSIGNMENT_DELAY 32'd0; + wdReg_3 <= `BSV_ASSIGNMENT_DELAY 32'd0; + wmemiRdReq <= `BSV_ASSIGNMENT_DELAY 32'd0; + wmemiRdResp <= `BSV_ASSIGNMENT_DELAY 32'd0; + wmemiReadInFlight_value <= `BSV_ASSIGNMENT_DELAY 8'd0; + wmemiWrReq <= `BSV_ASSIGNMENT_DELAY 32'd0; + wmemi_errorSticky <= `BSV_ASSIGNMENT_DELAY 1'd0; + wmemi_operateD <= `BSV_ASSIGNMENT_DELAY 1'd0; + wmemi_peerIsReady <= `BSV_ASSIGNMENT_DELAY 1'd0; + wmemi_respF_c_r <= `BSV_ASSIGNMENT_DELAY 2'd0; + wmemi_respF_q_0 <= `BSV_ASSIGNMENT_DELAY + 131'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; + wmemi_respF_q_1 <= `BSV_ASSIGNMENT_DELAY + 131'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; + wmemi_trafficSticky <= `BSV_ASSIGNMENT_DELAY 1'd0; + end + else + begin + if (dramCtrl$EN) dramCtrl <= `BSV_ASSIGNMENT_DELAY dramCtrl$D_IN; + if (mReg$EN) mReg <= `BSV_ASSIGNMENT_DELAY mReg$D_IN; + if (memc_curCount$EN) + memc_curCount <= `BSV_ASSIGNMENT_DELAY memc_curCount$D_IN; + if (pReg$EN) pReg <= `BSV_ASSIGNMENT_DELAY pReg$D_IN; + if (rdReg$EN) rdReg <= `BSV_ASSIGNMENT_DELAY rdReg$D_IN; + if (rdReg_1$EN) rdReg_1 <= `BSV_ASSIGNMENT_DELAY rdReg_1$D_IN; + if (rdReg_2$EN) rdReg_2 <= `BSV_ASSIGNMENT_DELAY rdReg_2$D_IN; + if (rdReg_3$EN) rdReg_3 <= `BSV_ASSIGNMENT_DELAY rdReg_3$D_IN; + if (respCount$EN) respCount <= `BSV_ASSIGNMENT_DELAY respCount$D_IN; + if (splitReadInFlight$EN) + splitReadInFlight <= `BSV_ASSIGNMENT_DELAY splitReadInFlight$D_IN; + if (wci_wslv_cEdge$EN) + wci_wslv_cEdge <= `BSV_ASSIGNMENT_DELAY wci_wslv_cEdge$D_IN; + if (wci_wslv_cState$EN) + wci_wslv_cState <= `BSV_ASSIGNMENT_DELAY wci_wslv_cState$D_IN; + if (wci_wslv_ctlAckReg$EN) + wci_wslv_ctlAckReg <= `BSV_ASSIGNMENT_DELAY wci_wslv_ctlAckReg$D_IN; + if (wci_wslv_ctlOpActive$EN) + wci_wslv_ctlOpActive <= `BSV_ASSIGNMENT_DELAY + wci_wslv_ctlOpActive$D_IN; + if (wci_wslv_illegalEdge$EN) + wci_wslv_illegalEdge <= `BSV_ASSIGNMENT_DELAY + wci_wslv_illegalEdge$D_IN; + if (wci_wslv_nState$EN) + wci_wslv_nState <= `BSV_ASSIGNMENT_DELAY wci_wslv_nState$D_IN; + if (wci_wslv_reqF_countReg$EN) + wci_wslv_reqF_countReg <= `BSV_ASSIGNMENT_DELAY + wci_wslv_reqF_countReg$D_IN; + if (wci_wslv_respF_c_r$EN) + wci_wslv_respF_c_r <= `BSV_ASSIGNMENT_DELAY wci_wslv_respF_c_r$D_IN; + if (wci_wslv_respF_q_0$EN) + wci_wslv_respF_q_0 <= `BSV_ASSIGNMENT_DELAY wci_wslv_respF_q_0$D_IN; + if (wci_wslv_respF_q_1$EN) + wci_wslv_respF_q_1 <= `BSV_ASSIGNMENT_DELAY wci_wslv_respF_q_1$D_IN; + if (wci_wslv_sFlagReg$EN) + wci_wslv_sFlagReg <= `BSV_ASSIGNMENT_DELAY wci_wslv_sFlagReg$D_IN; + if (wci_wslv_sThreadBusy_d$EN) + wci_wslv_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY + wci_wslv_sThreadBusy_d$D_IN; + if (wdReg$EN) wdReg <= `BSV_ASSIGNMENT_DELAY wdReg$D_IN; + if (wdReg_1$EN) wdReg_1 <= `BSV_ASSIGNMENT_DELAY wdReg_1$D_IN; + if (wdReg_2$EN) wdReg_2 <= `BSV_ASSIGNMENT_DELAY wdReg_2$D_IN; + if (wdReg_3$EN) wdReg_3 <= `BSV_ASSIGNMENT_DELAY wdReg_3$D_IN; + if (wmemiRdReq$EN) + wmemiRdReq <= `BSV_ASSIGNMENT_DELAY wmemiRdReq$D_IN; + if (wmemiRdResp$EN) + wmemiRdResp <= `BSV_ASSIGNMENT_DELAY wmemiRdResp$D_IN; + if (wmemiReadInFlight_value$EN) + wmemiReadInFlight_value <= `BSV_ASSIGNMENT_DELAY + wmemiReadInFlight_value$D_IN; + if (wmemiWrReq$EN) + wmemiWrReq <= `BSV_ASSIGNMENT_DELAY wmemiWrReq$D_IN; + if (wmemi_errorSticky$EN) + wmemi_errorSticky <= `BSV_ASSIGNMENT_DELAY wmemi_errorSticky$D_IN; + if (wmemi_operateD$EN) + wmemi_operateD <= `BSV_ASSIGNMENT_DELAY wmemi_operateD$D_IN; + if (wmemi_peerIsReady$EN) + wmemi_peerIsReady <= `BSV_ASSIGNMENT_DELAY wmemi_peerIsReady$D_IN; + if (wmemi_respF_c_r$EN) + wmemi_respF_c_r <= `BSV_ASSIGNMENT_DELAY wmemi_respF_c_r$D_IN; + if (wmemi_respF_q_0$EN) + wmemi_respF_q_0 <= `BSV_ASSIGNMENT_DELAY wmemi_respF_q_0$D_IN; + if (wmemi_respF_q_1$EN) + wmemi_respF_q_1 <= `BSV_ASSIGNMENT_DELAY wmemi_respF_q_1$D_IN; + if (wmemi_trafficSticky$EN) + wmemi_trafficSticky <= `BSV_ASSIGNMENT_DELAY + wmemi_trafficSticky$D_IN; + end + if (wmemi_statusR$EN) + wmemi_statusR <= `BSV_ASSIGNMENT_DELAY wmemi_statusR$D_IN; + end + + always@(posedge CLK_sys0_clk) + begin + if (RST_N_sys0_rstn == `BSV_RESET_VALUE) + begin + memc_sysCount <= `BSV_ASSIGNMENT_DELAY 4'd0; + end + else + begin + if (memc_sysCount$EN) + memc_sysCount <= `BSV_ASSIGNMENT_DELAY memc_sysCount$D_IN; + end + end + + always@(posedge memc_memc$afi_clk) + begin + if (memc_memc$afi_reset_n == `BSV_RESET_VALUE) + begin + dbgCtrl <= `BSV_ASSIGNMENT_DELAY 32'd0; + memc_afiCount <= `BSV_ASSIGNMENT_DELAY 4'd0; + memc_dbg_reqCount <= `BSV_ASSIGNMENT_DELAY 16'd0; + memc_dbg_respCount <= `BSV_ASSIGNMENT_DELAY 16'd0; + memc_secondRdBeat <= `BSV_ASSIGNMENT_DELAY 1'd0; + memc_secondWrBeat <= `BSV_ASSIGNMENT_DELAY 1'd0; + end + else + begin + if (dbgCtrl$EN) dbgCtrl <= `BSV_ASSIGNMENT_DELAY dbgCtrl$D_IN; + if (memc_afiCount$EN) + memc_afiCount <= `BSV_ASSIGNMENT_DELAY memc_afiCount$D_IN; + if (memc_dbg_reqCount$EN) + memc_dbg_reqCount <= `BSV_ASSIGNMENT_DELAY memc_dbg_reqCount$D_IN; + if (memc_dbg_respCount$EN) + memc_dbg_respCount <= `BSV_ASSIGNMENT_DELAY memc_dbg_respCount$D_IN; + if (memc_secondRdBeat$EN) + memc_secondRdBeat <= `BSV_ASSIGNMENT_DELAY memc_secondRdBeat$D_IN; + if (memc_secondWrBeat$EN) + memc_secondWrBeat <= `BSV_ASSIGNMENT_DELAY memc_secondWrBeat$D_IN; + end + if (memc_rdStageLS$EN) + memc_rdStageLS <= `BSV_ASSIGNMENT_DELAY memc_rdStageLS$D_IN; + end + + always@(posedge wciS0_Clk or `BSV_RESET_EDGE wciS0_MReset_n) + if (wciS0_MReset_n == `BSV_RESET_VALUE) + begin + wci_wslv_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY 1'd1; + wmemi_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY 1'd1; + end + else + begin + if (wci_wslv_isReset_isInReset$EN) + wci_wslv_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY + wci_wslv_isReset_isInReset$D_IN; + if (wmemi_isReset_isInReset$EN) + wmemi_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY + wmemi_isReset_isInReset$D_IN; + end + + always@(posedge memc_memc$afi_clk or `BSV_RESET_EDGE memc_memc$afi_reset_n) + if (memc_memc$afi_reset_n == `BSV_RESET_VALUE) + begin + memIsReset_isInReset <= `BSV_ASSIGNMENT_DELAY 1'd1; + end + else + begin + if (memIsReset_isInReset$EN) + memIsReset_isInReset <= `BSV_ASSIGNMENT_DELAY + memIsReset_isInReset$D_IN; + end + + // synopsys translate_off + `ifdef BSV_NO_INITIAL_BLOCKS + `else // not BSV_NO_INITIAL_BLOCKS + initial + begin + dbgCtrl = 32'hAAAAAAAA; + dramCtrl = 32'hAAAAAAAA; + mReg = 16'hAAAA; + memIsReset_isInReset = 1'h0; + memc_afiCount = 4'hA; + memc_curCount = 4'hA; + memc_dbg_reqCount = 16'hAAAA; + memc_dbg_respCount = 16'hAAAA; + memc_rdStageLS = 64'hAAAAAAAAAAAAAAAA; + memc_secondRdBeat = 1'h0; + memc_secondWrBeat = 1'h0; + memc_sysCount = 4'hA; + pReg = 16'hAAAA; + rdReg = 32'hAAAAAAAA; + rdReg_1 = 32'hAAAAAAAA; + rdReg_2 = 32'hAAAAAAAA; + rdReg_3 = 32'hAAAAAAAA; + respCount = 8'hAA; + splitReadInFlight = 1'h0; + wci_wslv_cEdge = 3'h2; + wci_wslv_cState = 3'h2; + wci_wslv_ctlAckReg = 1'h0; + wci_wslv_ctlOpActive = 1'h0; + wci_wslv_illegalEdge = 1'h0; + wci_wslv_isReset_isInReset = 1'h0; + wci_wslv_nState = 3'h2; + wci_wslv_reqF_countReg = 2'h2; + wci_wslv_respF_c_r = 2'h2; + wci_wslv_respF_q_0 = 34'h2AAAAAAAA; + wci_wslv_respF_q_1 = 34'h2AAAAAAAA; + wci_wslv_sFlagReg = 1'h0; + wci_wslv_sThreadBusy_d = 1'h0; + wdReg = 32'hAAAAAAAA; + wdReg_1 = 32'hAAAAAAAA; + wdReg_2 = 32'hAAAAAAAA; + wdReg_3 = 32'hAAAAAAAA; + wmemiRdReq = 32'hAAAAAAAA; + wmemiRdResp = 32'hAAAAAAAA; + wmemiReadInFlight_value = 8'hAA; + wmemiWrReq = 32'hAAAAAAAA; + wmemi_errorSticky = 1'h0; + wmemi_isReset_isInReset = 1'h0; + wmemi_operateD = 1'h0; + wmemi_peerIsReady = 1'h0; + wmemi_respF_c_r = 2'h2; + wmemi_respF_q_0 = 131'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; + wmemi_respF_q_1 = 131'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; + wmemi_statusR = 8'hAA; + wmemi_trafficSticky = 1'h0; + end + `endif // BSV_NO_INITIAL_BLOCKS + // synopsys translate_on + + // handling of system tasks + + // synopsys translate_off + always@(negedge wciS0_Clk) + begin + #0; + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_wslv_ctl_op_start) + begin + v__h6589 = $time; + #0; + end + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_wslv_ctl_op_start) + $display("[%0d]: %m: WCI ControlOp: Starting-transition edge:%x from:%x", + v__h6589, + wci_wslv_reqF$D_OUT[36:34], + wci_wslv_cState); + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_ctrl_IsO) + begin + v__h18076 = $time; + #0; + end + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_ctrl_IsO) + $display("[%0d]: %m: Starting DramWorker dramCtrl:%0x", + v__h18076, + dramCtrl); + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_advance_response && WILL_FIRE_RL_wci_ctrl_OrE) + $display("Error: \"bsv/wrk/DramServer_s4.bsv\", line 129, column 90: (R0001)\n Mutually exclusive rules (from the ME sets [RL_advance_response] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n"); + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_advance_response && WILL_FIRE_RL_wci_ctrl_IsO) + $display("Error: \"bsv/wrk/DramServer_s4.bsv\", line 129, column 90: (R0001)\n Mutually exclusive rules (from the ME sets [RL_advance_response] and\n [RL_wci_ctrl_IsO] ) fired in the same clock cycle.\n"); + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_advance_response && WILL_FIRE_RL_wci_ctrl_EiI) + $display("Error: \"bsv/wrk/DramServer_s4.bsv\", line 129, column 90: (R0001)\n Mutually exclusive rules (from the ME sets [RL_advance_response] and\n [RL_wci_ctrl_EiI] ) fired in the same clock cycle.\n"); + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_advance_response) + $display("Error: \"bsv/wrk/DramServer_s4.bsv\", line 129, column 28: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_advance_response] ) fired in the same clock cycle.\n"); + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_OrE) + $display("Error: \"bsv/wrk/DramServer_s4.bsv\", line 129, column 28: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n"); + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_IsO) + $display("Error: \"bsv/wrk/DramServer_s4.bsv\", line 129, column 28: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_wci_ctrl_IsO] ) fired in the same clock cycle.\n"); + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_EiI) + $display("Error: \"bsv/wrk/DramServer_s4.bsv\", line 129, column 28: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_wci_ctrl_EiI] ) fired in the same clock cycle.\n"); + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_cfrd) + $display("Error: \"bsv/wrk/DramServer_s4.bsv\", line 129, column 28: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and [RL_wci_cfrd] )\n fired in the same clock cycle.\n"); + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_cfrd && WILL_FIRE_RL_advance_response) + $display("Error: \"bsv/wrk/DramServer_s4.bsv\", line 129, column 38: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n [RL_advance_response] ) fired in the same clock cycle.\n"); + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_cfrd && WILL_FIRE_RL_wci_ctrl_OrE) + $display("Error: \"bsv/wrk/DramServer_s4.bsv\", line 129, column 38: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n"); + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_cfrd && WILL_FIRE_RL_wci_ctrl_IsO) + $display("Error: \"bsv/wrk/DramServer_s4.bsv\", line 129, column 38: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n [RL_wci_ctrl_IsO] ) fired in the same clock cycle.\n"); + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_cfrd && WILL_FIRE_RL_wci_ctrl_EiI) + $display("Error: \"bsv/wrk/DramServer_s4.bsv\", line 129, column 38: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n [RL_wci_ctrl_EiI] ) fired in the same clock cycle.\n"); + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_ctrl_IsO && WILL_FIRE_RL_wci_ctrl_OrE) + $display("Error: \"bsv/wrk/DramServer_s4.bsv\", line 129, column 62: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_IsO] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n"); + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_ctrl_EiI && WILL_FIRE_RL_wci_ctrl_OrE) + $display("Error: \"bsv/wrk/DramServer_s4.bsv\", line 129, column 48: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_EiI] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n"); + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_ctrl_EiI && WILL_FIRE_RL_wci_ctrl_IsO) + $display("Error: \"bsv/wrk/DramServer_s4.bsv\", line 129, column 48: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_EiI] and\n [RL_wci_ctrl_IsO] ) fired in the same clock cycle.\n"); + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge) + begin + v__h6908 = $time; + #0; + end + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge) + $display("[%0d]: %m: WCI ControlOp: ILLEGAL-EDGE Completed-transition edge:%x from:%x", + v__h6908, + wci_wslv_cEdge, + wci_wslv_cState); + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && !wci_wslv_illegalEdge) + begin + v__h6764 = $time; + #0; + end + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && !wci_wslv_illegalEdge) + $display("[%0d]: %m: WCI ControlOp: Completed-transition edge:%x from:%x to:%x", + v__h6764, + wci_wslv_cEdge, + wci_wslv_cState, + wci_wslv_nState); + end + // synopsys translate_on +endmodule // mkDramServer_s4 + diff --git a/rtl/mkDramServer_v6.v b/rtl/mkDramServer_v6.v index 416f9a70..25be5c90 100644 --- a/rtl/mkDramServer_v6.v +++ b/rtl/mkDramServer_v6.v @@ -1,7 +1,7 @@ // -// Generated by Bluespec Compiler, version 2012.09.beta1 (build 29570, 2012-09.11) +// Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Wed Nov 28 10:31:52 EST 2012 +// On Fri Jun 21 16:57:13 EDT 2013 // // // Ports: @@ -406,10 +406,10 @@ module mkDramServer_v6(CLK_sys0_clk, reg pioReadInFlight; wire pioReadInFlight$D_IN, pioReadInFlight$EN; - // register rdReg - reg [31 : 0] rdReg; - wire [31 : 0] rdReg$D_IN; - wire rdReg$EN; + // register rdReg_0 + reg [31 : 0] rdReg_0; + wire [31 : 0] rdReg_0$D_IN; + wire rdReg_0$EN; // register rdReg_1 reg [31 : 0] rdReg_1; @@ -471,10 +471,10 @@ module mkDramServer_v6(CLK_sys0_clk, wire [1 : 0] wci_wslv_reqF_countReg$D_IN; wire wci_wslv_reqF_countReg$EN; - // register wci_wslv_respF_c_r - reg [1 : 0] wci_wslv_respF_c_r; - wire [1 : 0] wci_wslv_respF_c_r$D_IN; - wire wci_wslv_respF_c_r$EN; + // register wci_wslv_respF_cntr_r + reg [1 : 0] wci_wslv_respF_cntr_r; + wire [1 : 0] wci_wslv_respF_cntr_r$D_IN; + wire wci_wslv_respF_cntr_r$EN; // register wci_wslv_respF_q_0 reg [33 : 0] wci_wslv_respF_q_0; @@ -494,10 +494,10 @@ module mkDramServer_v6(CLK_sys0_clk, reg wci_wslv_sThreadBusy_d; wire wci_wslv_sThreadBusy_d$D_IN, wci_wslv_sThreadBusy_d$EN; - // register wdReg - reg [31 : 0] wdReg; - wire [31 : 0] wdReg$D_IN; - wire wdReg$EN; + // register wdReg_0 + reg [31 : 0] wdReg_0; + wire [31 : 0] wdReg_0$D_IN; + wire wdReg_0$EN; // register wdReg_1 reg [31 : 0] wdReg_1; @@ -550,10 +550,10 @@ module mkDramServer_v6(CLK_sys0_clk, reg wmemi_peerIsReady; wire wmemi_peerIsReady$D_IN, wmemi_peerIsReady$EN; - // register wmemi_respF_c_r - reg [1 : 0] wmemi_respF_c_r; - wire [1 : 0] wmemi_respF_c_r$D_IN; - wire wmemi_respF_c_r$EN; + // register wmemi_respF_cntr_r + reg [1 : 0] wmemi_respF_cntr_r; + wire [1 : 0] wmemi_respF_cntr_r$D_IN; + wire wmemi_respF_cntr_r$EN; // register wmemi_respF_q_0 reg [130 : 0] wmemi_respF_q_0; @@ -821,16 +821,14 @@ module mkDramServer_v6(CLK_sys0_clk, MUX_wci_wslv_respF_x_wire$wset_1__VAL_2, MUX_wci_wslv_respF_x_wire$wset_1__VAL_3; wire [7 : 0] MUX_wmemiReadInFlight_value$write_1__VAL_2; - wire [1 : 0] MUX_wci_wslv_respF_c_r$write_1__VAL_1, - MUX_wci_wslv_respF_c_r$write_1__VAL_2, - MUX_wmemi_respF_c_r$write_1__VAL_1, - MUX_wmemi_respF_c_r$write_1__VAL_2; + wire [1 : 0] MUX_wci_wslv_respF_cntr_r$write_1__VAL_2, + MUX_wmemi_respF_cntr_r$write_1__VAL_2; wire MUX_lreqF$enq_1__SEL_1, MUX_lreqF$enq_1__SEL_2, MUX_lreqF$enq_1__SEL_3, MUX_memc_firstBeat$write_1__SEL_1, MUX_memc_secondBeat$write_1__SEL_1, - MUX_rdReg$write_1__SEL_1, + MUX_rdReg_0$write_1__SEL_1, MUX_rdReg_1$write_1__SEL_1, MUX_rdReg_2$write_1__SEL_1, MUX_rdReg_3$write_1__SEL_1, @@ -838,70 +836,80 @@ module mkDramServer_v6(CLK_sys0_clk, MUX_wci_wslv_illegalEdge$write_1__SEL_1, MUX_wci_wslv_illegalEdge$write_1__SEL_2, MUX_wci_wslv_illegalEdge$write_1__VAL_2, + MUX_wci_wslv_respF_q_0$write_1__SEL_1, MUX_wci_wslv_respF_q_0$write_1__SEL_2, + MUX_wci_wslv_respF_q_1$write_1__SEL_1, MUX_wci_wslv_respF_q_1$write_1__SEL_2, MUX_wci_wslv_respF_x_wire$wset_1__SEL_2, MUX_wmemi_respF_q_0$write_1__SEL_1, - MUX_wmemi_respF_q_1$write_1__SEL_1; + MUX_wmemi_respF_q_0$write_1__SEL_2, + MUX_wmemi_respF_q_1$write_1__SEL_1, + MUX_wmemi_respF_q_1$write_1__SEL_2; // remaining internal signals - reg [63 : 0] v__h19648, v__h3715, v__h3890, v__h4034; - reg [31 : 0] CASE_wci_wslv_reqFD_OUT_BITS_39_TO_32_0_0x0_d_ETC__q1, - g_data__h15336, - x__h6057, - x__h6278; - reg CASE_x527_NOT_x527_EQ_0b11_OR_memc_respFFULL__ETC__q2; - wire [175 : 0] IF_wci_wslv_reqF_first__5_BIT_51_55_THEN_pReg__ETC___d506; - wire [127 : 0] x1_data__h16584, x1_data__h17585; - wire [31 : 0] dramStatus__h13959, - g_data__h19109, - myBE__h6094, - myBE__h6127, - rdat___1__h19172, - rdat___1__h19183, - rdat___1__h19194, - rdat___1__h19205, - rdat___1__h19216, - rdat___1__h19227, - rdat___1__h19238, - rdat___1__h19249, - rdat___1__h19260, - rdat___1__h19271, - rdat___1__h19282, - rdat___1__h19293, - rdat___1__h19304, - rdat___1__h19315, - rdat___1__h19326, - rdat___1__h19337, - rdat___1__h19344, - rdat___1__h19355, - rdat___1__h19366, - rdat___1__h19376, - rdat___1__h19386, - rdat___1__h19400, - rdat___1__h19414, - rdat___1__h19428, - rdat___1__h19442, - rdat___1__h19457, - rdat___1__h19472, - rdat___1__h19487, - rdat___1__h19502, - rdat___1__h19508, - rdat___1__h19514, - x1_addr__h17583; - wire [15 : 0] x1_be__h17584, x__h19149; - wire [2 : 0] x__h6527; - wire IF_memc_memc_app_rd_data_end__11_CONCAT_memc_r_ETC___d227, - IF_wci_wslv_reqF_first__5_BIT_51_55_THEN_lreqF_ETC___d531, - IF_wmemi_reqF_first__81_BITS_51_TO_49_82_EQ_1__ETC___d390, - dbg_rd_active_dly_RDY_write__28_AND_dbg_dqs_p__ETC___d340, - dbg_rdlvl_err_RDY_write__22_AND_dbg_cpt_tap_cn_ETC___d346, - dbg_wl_odelay_dqs_tap_cnt_RDY_write__19_AND_db_ETC___d349, - lrespF_RDY_first__16_AND_NOT_splitReadInFlight_ETC___d434, - lrespF_RDY_first__16_AND_NOT_wmemi_respF_c_r_4_ETC___d418, - wci_wslv_reqF_i_notEmpty__4_AND_IF_wci_wslv_re_ETC___d467, - wmemiReadInFlight_value_07_SLT_16___d767, - x1__h12744; + reg [63 : 0] v__h19271, v__h3583, v__h3758, v__h3902; + reg [31 : 0] IF_wci_wslv_reqF_first__3_BITS_39_TO_32_46_EQ__ETC___d663, + g_data__h15073, + x__h5920, + x__h6141; + reg CASE_x378_0b0_memc_respFFULL_N_0b101_memc_res_ETC__q1; + wire [175 : 0] IF_wci_wslv_reqF_first__3_BIT_51_45_THEN_pReg__ETC___d496; + wire [127 : 0] x1_data__h16261, x1_data__h17270; + wire [31 : 0] dramStatus__h13684, + g_data__h18737, + myBE__h5957, + myBE__h5990, + rdat___1__h18800, + rdat___1__h18811, + rdat___1__h18822, + rdat___1__h18833, + rdat___1__h18844, + rdat___1__h18855, + rdat___1__h18866, + rdat___1__h18877, + rdat___1__h18888, + rdat___1__h18899, + rdat___1__h18910, + rdat___1__h18921, + rdat___1__h18932, + rdat___1__h18943, + rdat___1__h18954, + rdat___1__h18965, + rdat___1__h18972, + rdat___1__h18983, + rdat___1__h18994, + rdat___1__h19004, + rdat___1__h19014, + rdat___1__h19028, + rdat___1__h19042, + rdat___1__h19056, + rdat___1__h19070, + rdat___1__h19085, + rdat___1__h19100, + rdat___1__h19115, + rdat___1__h19130, + rdat___1__h19136, + rdat___1__h19142, + x1_addr__h17268; + wire [15 : 0] x1_be__h17269, x__h18777; + wire [2 : 0] x__h6378; + wire [1 : 0] wci_wslv_respF_cntr_r_8_MINUS_1___d27, + wmemi_respF_cntr_r_47_MINUS_1___d256; + wire IF_memc_memc_app_rd_data_end__09_CONCAT_memc_r_ETC___d225, + IF_wci_wslv_reqF_first__3_BIT_51_45_THEN_lreqF_ETC___d521, + IF_wmemi_reqF_first__77_BITS_51_TO_49_78_EQ_1__ETC___d386, + _dfoo1, + _dfoo3, + _dfoo5, + _dfoo7, + dbg_rd_active_dly_RDY_write__24_AND_dbg_dqs_p__ETC___d336, + dbg_rdlvl_err_RDY_write__18_AND_dbg_cpt_tap_cn_ETC___d342, + dbg_wl_odelay_dqs_tap_cnt_RDY_write__15_AND_db_ETC___d345, + lrespF_RDY_first__12_AND_NOT_splitReadInFlight_ETC___d430, + lrespF_RDY_first__12_AND_NOT_wmemi_respF_cntr__ETC___d414, + wci_wslv_reqF_i_notEmpty__2_AND_IF_wci_wslv_re_ETC___d457, + wmemiReadInFlight_value_03_SLT_16___d383, + x1__h12469; // value method wciS0_sResp assign wciS0_SResp = wci_wslv_respF_q_0[33:32] ; @@ -1376,15 +1384,15 @@ module mkDramServer_v6(CLK_sys0_clk, // rule RL_advance_response assign WILL_FIRE_RL_advance_response = lrespF$dEMPTY_N && - lrespF_RDY_first__16_AND_NOT_splitReadInFlight_ETC___d434 && + lrespF_RDY_first__12_AND_NOT_splitReadInFlight_ETC___d430 && !wci_wslv_wci_cfwr_pw$whas && wmemiReadInFlight_value == 8'd0 && !WILL_FIRE_RL_wci_wslv_ctl_op_complete ; // rule RL_wci_cfwr assign WILL_FIRE_RL_wci_cfwr = - wci_wslv_respF_c_r != 2'd2 && - wci_wslv_reqF_i_notEmpty__4_AND_IF_wci_wslv_re_ETC___d467 && + wci_wslv_respF_cntr_r != 2'd2 && + wci_wslv_reqF_i_notEmpty__2_AND_IF_wci_wslv_re_ETC___d457 && wci_wslv_wci_cfwr_pw$whas && !WILL_FIRE_RL_wci_wslv_ctl_op_start && !WILL_FIRE_RL_wci_wslv_ctl_op_complete ; @@ -1392,7 +1400,7 @@ module mkDramServer_v6(CLK_sys0_clk, // rule RL_wci_cfrd assign WILL_FIRE_RL_wci_cfrd = wci_wslv_reqF$EMPTY_N && - IF_wci_wslv_reqF_first__5_BIT_51_55_THEN_lreqF_ETC___d531 && + IF_wci_wslv_reqF_first__3_BIT_51_45_THEN_lreqF_ETC___d521 && wci_wslv_wci_cfrd_pw$whas && !WILL_FIRE_RL_wci_wslv_ctl_op_start && !WILL_FIRE_RL_wci_wslv_ctl_op_complete ; @@ -1419,14 +1427,14 @@ module mkDramServer_v6(CLK_sys0_clk, // rule RL_memc_advance_readData assign WILL_FIRE_RL_memc_advance_readData = memc_rdpF$EMPTY_N && - IF_memc_memc_app_rd_data_end__11_CONCAT_memc_r_ETC___d227 && + IF_memc_memc_app_rd_data_end__09_CONCAT_memc_r_ETC___d225 && memc_memc$phy_init_done && memc_memc$app_rd_data_valid ; // rule RL_memc_advance_request assign WILL_FIRE_RL_memc_advance_request = memc_reqF$EMPTY_N && - (x1__h12744 || !memc_reqF$D_OUT[176] || memc_rdpF$FULL_N) && + (x1__h12469 || !memc_reqF$D_OUT[176] || memc_rdpF$FULL_N) && memc_memc$phy_init_done && !memc_firstBeat && !memc_secondBeat ; @@ -1444,28 +1452,22 @@ module mkDramServer_v6(CLK_sys0_clk, // rule RL_wmemi_respF_incCtr assign WILL_FIRE_RL_wmemi_respF_incCtr = - ((wmemi_respF_c_r == 2'd0) ? - wmemi_respF_enqueueing$whas : - wmemi_respF_c_r != 2'd1 || wmemi_respF_enqueueing$whas) && - wmemi_respF_enqueueing$whas && - !(wmemi_respF_c_r != 2'd0) ; + wmemi_respF_enqueueing$whas && wmemi_respF_enqueueing$whas && + !(wmemi_respF_cntr_r != 2'd0) ; // rule RL_wmemi_respF_decCtr assign WILL_FIRE_RL_wmemi_respF_decCtr = - wmemi_respF_c_r != 2'd0 && !wmemi_respF_enqueueing$whas ; + wmemi_respF_cntr_r != 2'd0 && !wmemi_respF_enqueueing$whas ; // rule RL_wmemi_respF_both assign WILL_FIRE_RL_wmemi_respF_both = - ((wmemi_respF_c_r == 2'd1) ? - wmemi_respF_enqueueing$whas : - wmemi_respF_c_r != 2'd2 || wmemi_respF_enqueueing$whas) && - wmemi_respF_c_r != 2'd0 && + wmemi_respF_enqueueing$whas && wmemi_respF_cntr_r != 2'd0 && wmemi_respF_enqueueing$whas ; // rule RL_getRequest assign WILL_FIRE_RL_getRequest = wmemi_operateD && wmemi_peerIsReady && wmemi_reqF$EMPTY_N && - IF_wmemi_reqF_first__81_BITS_51_TO_49_82_EQ_1__ETC___d390 && + IF_wmemi_reqF_first__77_BITS_51_TO_49_78_EQ_1__ETC___d386 && !wci_wslv_wci_cfwr_pw$whas && !wci_wslv_wci_cfrd_pw$whas ; @@ -1478,47 +1480,41 @@ module mkDramServer_v6(CLK_sys0_clk, // rule RL_wci_wslv_ctl_op_complete assign WILL_FIRE_RL_wci_wslv_ctl_op_complete = - wci_wslv_respF_c_r != 2'd2 && wci_wslv_ctlOpActive && + wci_wslv_respF_cntr_r != 2'd2 && wci_wslv_ctlOpActive && wci_wslv_ctlAckReg ; // rule RL_wci_wslv_respF_incCtr assign WILL_FIRE_RL_wci_wslv_respF_incCtr = - ((wci_wslv_respF_c_r == 2'd0) ? - wci_wslv_respF_x_wire$whas : - wci_wslv_respF_c_r != 2'd1 || wci_wslv_respF_x_wire$whas) && - wci_wslv_respF_enqueueing$whas && - !(wci_wslv_respF_c_r != 2'd0) ; + wci_wslv_respF_x_wire$whas && wci_wslv_respF_enqueueing$whas && + !(wci_wslv_respF_cntr_r != 2'd0) ; // rule RL_wci_wslv_respF_decCtr assign WILL_FIRE_RL_wci_wslv_respF_decCtr = - wci_wslv_respF_c_r != 2'd0 && !wci_wslv_respF_enqueueing$whas ; + wci_wslv_respF_cntr_r != 2'd0 && + !wci_wslv_respF_enqueueing$whas ; // rule RL_wci_wslv_respF_both assign WILL_FIRE_RL_wci_wslv_respF_both = - ((wci_wslv_respF_c_r == 2'd1) ? - wci_wslv_respF_x_wire$whas : - wci_wslv_respF_c_r != 2'd2 || wci_wslv_respF_x_wire$whas) && - wci_wslv_respF_c_r != 2'd0 && + wci_wslv_respF_x_wire$whas && wci_wslv_respF_cntr_r != 2'd0 && wci_wslv_respF_enqueueing$whas ; // inputs to muxes for submodule ports assign MUX_lreqF$enq_1__SEL_1 = + WILL_FIRE_RL_wci_cfrd && wci_wslv_reqF$D_OUT[51] ; + assign MUX_lreqF$enq_1__SEL_2 = WILL_FIRE_RL_getRequest && (wmemi_reqF$D_OUT[51:49] == 3'd1 || - wmemiReadInFlight_value_07_SLT_16___d767) ; - assign MUX_lreqF$enq_1__SEL_2 = + wmemiReadInFlight_value_03_SLT_16___d383) ; + assign MUX_lreqF$enq_1__SEL_3 = WILL_FIRE_RL_wci_cfwr && (wci_wslv_reqF$D_OUT[51] || wci_wslv_reqF$D_OUT[39:32] == 8'h54 || wci_wslv_reqF$D_OUT[39:32] == 8'h58) ; - assign MUX_lreqF$enq_1__SEL_3 = - WILL_FIRE_RL_wci_cfrd && wci_wslv_reqF$D_OUT[51] ; assign MUX_memc_firstBeat$write_1__SEL_1 = - WILL_FIRE_RL_memc_advance_request && memc_memc$app_rdy && - !memc_reqF$D_OUT[176] ; + WILL_FIRE_RL_memc_advance_write0 && memc_memc$app_wdf_rdy ; assign MUX_memc_secondBeat$write_1__SEL_1 = WILL_FIRE_RL_memc_advance_write1 && memc_memc$app_wdf_rdy ; - assign MUX_rdReg$write_1__SEL_1 = + assign MUX_rdReg_0$write_1__SEL_1 = WILL_FIRE_RL_wci_cfwr && !wci_wslv_reqF$D_OUT[51] && wci_wslv_reqF$D_OUT[39:32] == 8'h80 ; assign MUX_rdReg_1$write_1__SEL_1 = @@ -1547,19 +1543,31 @@ module mkDramServer_v6(CLK_sys0_clk, wci_wslv_reqF$D_OUT[36:34] == 3'd5 || wci_wslv_reqF$D_OUT[36:34] == 3'd6 || wci_wslv_reqF$D_OUT[36:34] == 3'd7) ; + assign MUX_wci_wslv_respF_q_0$write_1__SEL_1 = + WILL_FIRE_RL_wci_wslv_respF_both && _dfoo3 ; assign MUX_wci_wslv_respF_q_0$write_1__SEL_2 = WILL_FIRE_RL_wci_wslv_respF_incCtr && - wci_wslv_respF_c_r == 2'd0 ; + wci_wslv_respF_cntr_r == 2'd0 ; + assign MUX_wci_wslv_respF_q_1$write_1__SEL_1 = + WILL_FIRE_RL_wci_wslv_respF_both && _dfoo1 ; assign MUX_wci_wslv_respF_q_1$write_1__SEL_2 = WILL_FIRE_RL_wci_wslv_respF_incCtr && - wci_wslv_respF_c_r == 2'd1 ; + wci_wslv_respF_cntr_r == 2'd1 ; assign MUX_wci_wslv_respF_x_wire$wset_1__SEL_2 = WILL_FIRE_RL_wci_cfrd && !wci_wslv_reqF$D_OUT[51] ; assign MUX_wmemi_respF_q_0$write_1__SEL_1 = - WILL_FIRE_RL_wmemi_respF_incCtr && wmemi_respF_c_r == 2'd0 ; + WILL_FIRE_RL_wmemi_respF_incCtr && wmemi_respF_cntr_r == 2'd0 ; + assign MUX_wmemi_respF_q_0$write_1__SEL_2 = + WILL_FIRE_RL_wmemi_respF_both && _dfoo7 ; assign MUX_wmemi_respF_q_1$write_1__SEL_1 = - WILL_FIRE_RL_wmemi_respF_incCtr && wmemi_respF_c_r == 2'd1 ; + WILL_FIRE_RL_wmemi_respF_incCtr && wmemi_respF_cntr_r == 2'd1 ; + assign MUX_wmemi_respF_q_1$write_1__SEL_2 = + WILL_FIRE_RL_wmemi_respF_both && _dfoo5 ; assign MUX_lreqF$enq_1__VAL_1 = + { 1'd1, + x1_addr__h17268, + 144'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA } ; + assign MUX_lreqF$enq_1__VAL_2 = { wmemi_reqF$D_OUT[51:49] != 3'd1, (wmemi_reqF$D_OUT[51:49] == 3'd1) ? { wmemi_reqF$D_OUT[43:12], @@ -1567,22 +1575,18 @@ module mkDramServer_v6(CLK_sys0_clk, wmemi_dhF$D_OUT[143:16] } : { wmemi_reqF$D_OUT[43:0], 132'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA } } ; - assign MUX_lreqF$enq_1__VAL_2 = + assign MUX_lreqF$enq_1__VAL_3 = { !wci_wslv_reqF$D_OUT[51] && wci_wslv_reqF$D_OUT[39:32] != 8'h54, - IF_wci_wslv_reqF_first__5_BIT_51_55_THEN_pReg__ETC___d506 } ; - assign MUX_lreqF$enq_1__VAL_3 = - { 1'd1, - x1_addr__h17583, - 144'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA } ; + IF_wci_wslv_reqF_first__3_BIT_51_45_THEN_pReg__ETC___d496 } ; assign MUX_wci_wslv_illegalEdge$write_1__VAL_2 = wci_wslv_reqF$D_OUT[36:34] != 3'd4 && wci_wslv_reqF$D_OUT[36:34] != 3'd5 && wci_wslv_reqF$D_OUT[36:34] != 3'd6 ; - assign MUX_wci_wslv_respF_c_r$write_1__VAL_1 = wci_wslv_respF_c_r + 2'd1 ; - assign MUX_wci_wslv_respF_c_r$write_1__VAL_2 = wci_wslv_respF_c_r - 2'd1 ; + assign MUX_wci_wslv_respF_cntr_r$write_1__VAL_2 = + wci_wslv_respF_cntr_r + 2'd1 ; assign MUX_wci_wslv_respF_q_0$write_1__VAL_1 = - (wci_wslv_respF_c_r == 2'd1) ? + (wci_wslv_respF_cntr_r == 2'd1) ? MUX_wci_wslv_respF_q_0$write_1__VAL_2 : wci_wslv_respF_q_1 ; always@(MUX_splitReadInFlight$write_1__SEL_1 or @@ -1609,26 +1613,25 @@ module mkDramServer_v6(CLK_sys0_clk, endcase end assign MUX_wci_wslv_respF_q_1$write_1__VAL_1 = - (wci_wslv_respF_c_r == 2'd2) ? + (wci_wslv_respF_cntr_r == 2'd2) ? MUX_wci_wslv_respF_q_0$write_1__VAL_2 : 34'h0AAAAAAAA ; - assign MUX_wci_wslv_respF_x_wire$wset_1__VAL_1 = { 2'd1, g_data__h15336 } ; - assign MUX_wci_wslv_respF_x_wire$wset_1__VAL_2 = { 2'd1, g_data__h19109 } ; + assign MUX_wci_wslv_respF_x_wire$wset_1__VAL_1 = { 2'd1, g_data__h15073 } ; + assign MUX_wci_wslv_respF_x_wire$wset_1__VAL_2 = { 2'd1, g_data__h18737 } ; assign MUX_wci_wslv_respF_x_wire$wset_1__VAL_3 = wci_wslv_illegalEdge ? 34'h3C0DE4202 : 34'h1C0DE4201 ; assign MUX_wmemiReadInFlight_value$write_1__VAL_2 = wmemiReadInFlight_value + (wmemiReadInFlight_acc_v1$whas ? 8'd1 : 8'd0) + (wmemi_respF_enqueueing$whas ? 8'd255 : 8'd0) ; - assign MUX_wmemi_respF_c_r$write_1__VAL_1 = wmemi_respF_c_r + 2'd1 ; - assign MUX_wmemi_respF_c_r$write_1__VAL_2 = wmemi_respF_c_r - 2'd1 ; + assign MUX_wmemi_respF_cntr_r$write_1__VAL_2 = wmemi_respF_cntr_r + 2'd1 ; assign MUX_wmemi_respF_q_0$write_1__VAL_1 = { 3'd3, lrespF$dD_OUT } ; assign MUX_wmemi_respF_q_0$write_1__VAL_2 = - (wmemi_respF_c_r == 2'd1) ? + (wmemi_respF_cntr_r == 2'd1) ? MUX_wmemi_respF_q_0$write_1__VAL_1 : wmemi_respF_q_1 ; assign MUX_wmemi_respF_q_1$write_1__VAL_2 = - (wmemi_respF_c_r == 2'd2) ? + (wmemi_respF_cntr_r == 2'd2) ? MUX_wmemi_respF_q_0$write_1__VAL_1 : 131'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA ; @@ -1701,7 +1704,7 @@ module mkDramServer_v6(CLK_sys0_clk, assign wmemiReadInFlight_acc_v1$wget = 8'd1 ; assign wmemiReadInFlight_acc_v1$whas = WILL_FIRE_RL_getRequest && wmemi_reqF$D_OUT[51:49] != 3'd1 && - wmemiReadInFlight_value_07_SLT_16___d767 ; + wmemiReadInFlight_value_03_SLT_16___d383 ; assign wmemiReadInFlight_acc_v2$wget = 8'd255 ; assign wmemiReadInFlight_acc_v2$whas = wmemi_respF_enqueueing$whas ; assign wmemi_Es_mCmd_w$wget = wmemiS0_MCmd ; @@ -1724,7 +1727,7 @@ module mkDramServer_v6(CLK_sys0_clk, WILL_FIRE_RL_wci_cfrd && !wci_wslv_reqF$D_OUT[51] || WILL_FIRE_RL_wci_cfwr || WILL_FIRE_RL_wci_wslv_ctl_op_complete ; - assign wci_wslv_respF_dequeueing$whas = wci_wslv_respF_c_r != 2'd0 ; + assign wci_wslv_respF_dequeueing$whas = wci_wslv_respF_cntr_r != 2'd0 ; assign wci_wslv_sThreadBusy_pw$whas = 1'b0 ; assign wci_wslv_wci_cfwr_pw$whas = wci_wslv_reqF$EMPTY_N && wci_wslv_reqF$D_OUT[68] && @@ -1737,9 +1740,9 @@ module mkDramServer_v6(CLK_sys0_clk, wci_wslv_reqF$D_OUT[71:69] == 3'd2 ; assign wmemi_respF_enqueueing$whas = lrespF$dEMPTY_N && - lrespF_RDY_first__16_AND_NOT_wmemi_respF_c_r_4_ETC___d418 && + lrespF_RDY_first__12_AND_NOT_wmemi_respF_cntr__ETC___d414 && (wmemiReadInFlight_value ^ 8'h80) > 8'd128 ; - assign wmemi_respF_dequeueing$whas = wmemi_respF_c_r != 2'd0 ; + assign wmemi_respF_dequeueing$whas = wmemi_respF_cntr_r != 2'd0 ; assign wmemi_Es_mReqLast_w$whas = wmemiS0_MReqLast ; assign wmemi_Es_mDataValid_w$whas = wmemiS0_MDataValid ; assign wmemi_Es_mDataLast_w$whas = wmemiS0_MDataLast ; @@ -1765,11 +1768,11 @@ module mkDramServer_v6(CLK_sys0_clk, assign memIsReset_isInReset$EN = memIsReset_isInReset ; // register memc_firstBeat - assign memc_firstBeat$D_IN = MUX_memc_firstBeat$write_1__SEL_1 ; + assign memc_firstBeat$D_IN = !MUX_memc_firstBeat$write_1__SEL_1 ; assign memc_firstBeat$EN = + WILL_FIRE_RL_memc_advance_write0 && memc_memc$app_wdf_rdy || WILL_FIRE_RL_memc_advance_request && memc_memc$app_rdy && - !memc_reqF$D_OUT[176] || - WILL_FIRE_RL_memc_advance_write0 && memc_memc$app_wdf_rdy ; + !memc_reqF$D_OUT[176] ; // register memc_requestCount assign memc_requestCount$D_IN = memc_requestCount + 16'd1 ; @@ -1796,12 +1799,12 @@ module mkDramServer_v6(CLK_sys0_clk, assign pioReadInFlight$D_IN = 1'b0 ; assign pioReadInFlight$EN = 1'b0 ; - // register rdReg - assign rdReg$D_IN = - MUX_rdReg$write_1__SEL_1 ? + // register rdReg_0 + assign rdReg_0$D_IN = + MUX_rdReg_0$write_1__SEL_1 ? wci_wslv_reqF$D_OUT[31:0] : lrespF$dD_OUT[31:0] ; - assign rdReg$EN = + assign rdReg_0$EN = WILL_FIRE_RL_wci_cfwr && !wci_wslv_reqF$D_OUT[51] && wci_wslv_reqF$D_OUT[39:32] == 8'h80 || WILL_FIRE_RL_advance_response ; @@ -1906,24 +1909,24 @@ module mkDramServer_v6(CLK_sys0_clk, (wci_wslv_wciReq$wget[71:69] != 3'd0) != wci_wslv_reqF_r_deq$whas ; - // register wci_wslv_respF_c_r - assign wci_wslv_respF_c_r$D_IN = - WILL_FIRE_RL_wci_wslv_respF_incCtr ? - MUX_wci_wslv_respF_c_r$write_1__VAL_1 : - MUX_wci_wslv_respF_c_r$write_1__VAL_2 ; - assign wci_wslv_respF_c_r$EN = - WILL_FIRE_RL_wci_wslv_respF_incCtr || - WILL_FIRE_RL_wci_wslv_respF_decCtr ; + // register wci_wslv_respF_cntr_r + assign wci_wslv_respF_cntr_r$D_IN = + WILL_FIRE_RL_wci_wslv_respF_decCtr ? + wci_wslv_respF_cntr_r_8_MINUS_1___d27 : + MUX_wci_wslv_respF_cntr_r$write_1__VAL_2 ; + assign wci_wslv_respF_cntr_r$EN = + WILL_FIRE_RL_wci_wslv_respF_decCtr || + WILL_FIRE_RL_wci_wslv_respF_incCtr ; // register wci_wslv_respF_q_0 - always@(WILL_FIRE_RL_wci_wslv_respF_both or + always@(MUX_wci_wslv_respF_q_0$write_1__SEL_1 or MUX_wci_wslv_respF_q_0$write_1__VAL_1 or MUX_wci_wslv_respF_q_0$write_1__SEL_2 or MUX_wci_wslv_respF_q_0$write_1__VAL_2 or WILL_FIRE_RL_wci_wslv_respF_decCtr or wci_wslv_respF_q_1) begin case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_wci_wslv_respF_both: + MUX_wci_wslv_respF_q_0$write_1__SEL_1: wci_wslv_respF_q_0$D_IN = MUX_wci_wslv_respF_q_0$write_1__VAL_1; MUX_wci_wslv_respF_q_0$write_1__SEL_2: wci_wslv_respF_q_0$D_IN = MUX_wci_wslv_respF_q_0$write_1__VAL_2; @@ -1934,20 +1937,20 @@ module mkDramServer_v6(CLK_sys0_clk, endcase end assign wci_wslv_respF_q_0$EN = - WILL_FIRE_RL_wci_wslv_respF_both || + WILL_FIRE_RL_wci_wslv_respF_both && _dfoo3 || WILL_FIRE_RL_wci_wslv_respF_incCtr && - wci_wslv_respF_c_r == 2'd0 || + wci_wslv_respF_cntr_r == 2'd0 || WILL_FIRE_RL_wci_wslv_respF_decCtr ; // register wci_wslv_respF_q_1 - always@(WILL_FIRE_RL_wci_wslv_respF_both or + always@(MUX_wci_wslv_respF_q_1$write_1__SEL_1 or MUX_wci_wslv_respF_q_1$write_1__VAL_1 or MUX_wci_wslv_respF_q_1$write_1__SEL_2 or MUX_wci_wslv_respF_q_0$write_1__VAL_2 or WILL_FIRE_RL_wci_wslv_respF_decCtr) begin case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_wci_wslv_respF_both: + MUX_wci_wslv_respF_q_1$write_1__SEL_1: wci_wslv_respF_q_1$D_IN = MUX_wci_wslv_respF_q_1$write_1__VAL_1; MUX_wci_wslv_respF_q_1$write_1__SEL_2: wci_wslv_respF_q_1$D_IN = MUX_wci_wslv_respF_q_0$write_1__VAL_2; @@ -1958,9 +1961,9 @@ module mkDramServer_v6(CLK_sys0_clk, endcase end assign wci_wslv_respF_q_1$EN = - WILL_FIRE_RL_wci_wslv_respF_both || + WILL_FIRE_RL_wci_wslv_respF_both && _dfoo1 || WILL_FIRE_RL_wci_wslv_respF_incCtr && - wci_wslv_respF_c_r == 2'd1 || + wci_wslv_respF_cntr_r == 2'd1 || WILL_FIRE_RL_wci_wslv_respF_decCtr ; // register wci_wslv_sFlagReg @@ -1971,9 +1974,9 @@ module mkDramServer_v6(CLK_sys0_clk, assign wci_wslv_sThreadBusy_d$D_IN = 1'b0 ; assign wci_wslv_sThreadBusy_d$EN = 1'd1 ; - // register wdReg - assign wdReg$D_IN = wci_wslv_reqF$D_OUT[31:0] ; - assign wdReg$EN = + // register wdReg_0 + assign wdReg_0$D_IN = wci_wslv_reqF$D_OUT[31:0] ; + assign wdReg_0$EN = WILL_FIRE_RL_wci_cfwr && !wci_wslv_reqF$D_OUT[51] && wci_wslv_reqF$D_OUT[39:32] == 8'h60 ; @@ -2031,26 +2034,26 @@ module mkDramServer_v6(CLK_sys0_clk, assign wmemi_peerIsReady$D_IN = wmemiS0_MReset_n ; assign wmemi_peerIsReady$EN = 1'd1 ; - // register wmemi_respF_c_r - assign wmemi_respF_c_r$D_IN = - WILL_FIRE_RL_wmemi_respF_incCtr ? - MUX_wmemi_respF_c_r$write_1__VAL_1 : - MUX_wmemi_respF_c_r$write_1__VAL_2 ; - assign wmemi_respF_c_r$EN = - WILL_FIRE_RL_wmemi_respF_incCtr || - WILL_FIRE_RL_wmemi_respF_decCtr ; + // register wmemi_respF_cntr_r + assign wmemi_respF_cntr_r$D_IN = + WILL_FIRE_RL_wmemi_respF_decCtr ? + wmemi_respF_cntr_r_47_MINUS_1___d256 : + MUX_wmemi_respF_cntr_r$write_1__VAL_2 ; + assign wmemi_respF_cntr_r$EN = + WILL_FIRE_RL_wmemi_respF_decCtr || + WILL_FIRE_RL_wmemi_respF_incCtr ; // register wmemi_respF_q_0 always@(MUX_wmemi_respF_q_0$write_1__SEL_1 or MUX_wmemi_respF_q_0$write_1__VAL_1 or - WILL_FIRE_RL_wmemi_respF_both or + MUX_wmemi_respF_q_0$write_1__SEL_2 or MUX_wmemi_respF_q_0$write_1__VAL_2 or WILL_FIRE_RL_wmemi_respF_decCtr or wmemi_respF_q_1) begin case (1'b1) // synopsys parallel_case MUX_wmemi_respF_q_0$write_1__SEL_1: wmemi_respF_q_0$D_IN = MUX_wmemi_respF_q_0$write_1__VAL_1; - WILL_FIRE_RL_wmemi_respF_both: + MUX_wmemi_respF_q_0$write_1__SEL_2: wmemi_respF_q_0$D_IN = MUX_wmemi_respF_q_0$write_1__VAL_2; WILL_FIRE_RL_wmemi_respF_decCtr: wmemi_respF_q_0$D_IN = wmemi_respF_q_1; default: wmemi_respF_q_0$D_IN = @@ -2058,21 +2061,21 @@ module mkDramServer_v6(CLK_sys0_clk, endcase end assign wmemi_respF_q_0$EN = - WILL_FIRE_RL_wmemi_respF_incCtr && wmemi_respF_c_r == 2'd0 || - WILL_FIRE_RL_wmemi_respF_both || + WILL_FIRE_RL_wmemi_respF_incCtr && wmemi_respF_cntr_r == 2'd0 || + WILL_FIRE_RL_wmemi_respF_both && _dfoo7 || WILL_FIRE_RL_wmemi_respF_decCtr ; // register wmemi_respF_q_1 always@(MUX_wmemi_respF_q_1$write_1__SEL_1 or MUX_wmemi_respF_q_0$write_1__VAL_1 or - WILL_FIRE_RL_wmemi_respF_both or + MUX_wmemi_respF_q_1$write_1__SEL_2 or MUX_wmemi_respF_q_1$write_1__VAL_2 or WILL_FIRE_RL_wmemi_respF_decCtr) begin case (1'b1) // synopsys parallel_case MUX_wmemi_respF_q_1$write_1__SEL_1: wmemi_respF_q_1$D_IN = MUX_wmemi_respF_q_0$write_1__VAL_1; - WILL_FIRE_RL_wmemi_respF_both: + MUX_wmemi_respF_q_1$write_1__SEL_2: wmemi_respF_q_1$D_IN = MUX_wmemi_respF_q_1$write_1__VAL_2; WILL_FIRE_RL_wmemi_respF_decCtr: wmemi_respF_q_1$D_IN = 131'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; @@ -2081,8 +2084,8 @@ module mkDramServer_v6(CLK_sys0_clk, endcase end assign wmemi_respF_q_1$EN = - WILL_FIRE_RL_wmemi_respF_incCtr && wmemi_respF_c_r == 2'd1 || - WILL_FIRE_RL_wmemi_respF_both || + WILL_FIRE_RL_wmemi_respF_incCtr && wmemi_respF_cntr_r == 2'd1 || + WILL_FIRE_RL_wmemi_respF_both && _dfoo5 || WILL_FIRE_RL_wmemi_respF_decCtr ; // register wmemi_statusR @@ -2100,105 +2103,105 @@ module mkDramServer_v6(CLK_sys0_clk, assign wmemi_trafficSticky$EN = wmemi_cmdAccept_w$whas ; // submodule appFull - assign appFull$sD_IN = x1__h12744 ; + assign appFull$sD_IN = x1__h12469 ; assign appFull$sEN = 1'd1 ; // submodule dbg_cpt_first_edge_cnt assign dbg_cpt_first_edge_cnt$sD_IN = memc_memc$dbg_cpt_first_edge_cnt ; assign dbg_cpt_first_edge_cnt$sEN = dbg_wl_dqs_inverted$sRDY && dbg_wr_calib_clk_delay$sRDY && - dbg_wl_odelay_dqs_tap_cnt_RDY_write__19_AND_db_ETC___d349 ; + dbg_wl_odelay_dqs_tap_cnt_RDY_write__15_AND_db_ETC___d345 ; // submodule dbg_cpt_second_edge_cnt assign dbg_cpt_second_edge_cnt$sD_IN = memc_memc$dbg_cpt_second_edge_cnt ; assign dbg_cpt_second_edge_cnt$sEN = dbg_wl_dqs_inverted$sRDY && dbg_wr_calib_clk_delay$sRDY && - dbg_wl_odelay_dqs_tap_cnt_RDY_write__19_AND_db_ETC___d349 ; + dbg_wl_odelay_dqs_tap_cnt_RDY_write__15_AND_db_ETC___d345 ; // submodule dbg_cpt_tap_cnt assign dbg_cpt_tap_cnt$sD_IN = memc_memc$dbg_cpt_tap_cnt ; assign dbg_cpt_tap_cnt$sEN = dbg_wl_dqs_inverted$sRDY && dbg_wr_calib_clk_delay$sRDY && - dbg_wl_odelay_dqs_tap_cnt_RDY_write__19_AND_db_ETC___d349 ; + dbg_wl_odelay_dqs_tap_cnt_RDY_write__15_AND_db_ETC___d345 ; // submodule dbg_dq_tap_cnt assign dbg_dq_tap_cnt$sD_IN = memc_memc$dbg_dq_tap_cnt ; assign dbg_dq_tap_cnt$sEN = dbg_wl_dqs_inverted$sRDY && dbg_wr_calib_clk_delay$sRDY && - dbg_wl_odelay_dqs_tap_cnt_RDY_write__19_AND_db_ETC___d349 ; + dbg_wl_odelay_dqs_tap_cnt_RDY_write__15_AND_db_ETC___d345 ; // submodule dbg_dqs_n_tap_cnt assign dbg_dqs_n_tap_cnt$sD_IN = memc_memc$dbg_dqs_n_tap_cnt ; assign dbg_dqs_n_tap_cnt$sEN = dbg_wl_dqs_inverted$sRDY && dbg_wr_calib_clk_delay$sRDY && - dbg_wl_odelay_dqs_tap_cnt_RDY_write__19_AND_db_ETC___d349 ; + dbg_wl_odelay_dqs_tap_cnt_RDY_write__15_AND_db_ETC___d345 ; // submodule dbg_dqs_p_tap_cnt assign dbg_dqs_p_tap_cnt$sD_IN = memc_memc$dbg_dqs_p_tap_cnt ; assign dbg_dqs_p_tap_cnt$sEN = dbg_wl_dqs_inverted$sRDY && dbg_wr_calib_clk_delay$sRDY && - dbg_wl_odelay_dqs_tap_cnt_RDY_write__19_AND_db_ETC___d349 ; + dbg_wl_odelay_dqs_tap_cnt_RDY_write__15_AND_db_ETC___d345 ; // submodule dbg_rd_active_dly assign dbg_rd_active_dly$sD_IN = memc_memc$dbg_rd_active_dly ; assign dbg_rd_active_dly$sEN = dbg_wl_dqs_inverted$sRDY && dbg_wr_calib_clk_delay$sRDY && - dbg_wl_odelay_dqs_tap_cnt_RDY_write__19_AND_db_ETC___d349 ; + dbg_wl_odelay_dqs_tap_cnt_RDY_write__15_AND_db_ETC___d345 ; // submodule dbg_rd_bitslip_cnt assign dbg_rd_bitslip_cnt$sD_IN = memc_memc$dbg_rd_bitslip_cnt ; assign dbg_rd_bitslip_cnt$sEN = dbg_wl_dqs_inverted$sRDY && dbg_wr_calib_clk_delay$sRDY && - dbg_wl_odelay_dqs_tap_cnt_RDY_write__19_AND_db_ETC___d349 ; + dbg_wl_odelay_dqs_tap_cnt_RDY_write__15_AND_db_ETC___d345 ; // submodule dbg_rd_clkdly_cnt assign dbg_rd_clkdly_cnt$sD_IN = memc_memc$dbg_rd_clkdly_cnt ; assign dbg_rd_clkdly_cnt$sEN = dbg_wl_dqs_inverted$sRDY && dbg_wr_calib_clk_delay$sRDY && - dbg_wl_odelay_dqs_tap_cnt_RDY_write__19_AND_db_ETC___d349 ; + dbg_wl_odelay_dqs_tap_cnt_RDY_write__15_AND_db_ETC___d345 ; // submodule dbg_rddata assign dbg_rddata$sD_IN = memc_memc$dbg_rddata ; assign dbg_rddata$sEN = dbg_wl_dqs_inverted$sRDY && dbg_wr_calib_clk_delay$sRDY && - dbg_wl_odelay_dqs_tap_cnt_RDY_write__19_AND_db_ETC___d349 ; + dbg_wl_odelay_dqs_tap_cnt_RDY_write__15_AND_db_ETC___d345 ; // submodule dbg_rdlvl_done assign dbg_rdlvl_done$sD_IN = memc_memc$dbg_rdlvl_done ; assign dbg_rdlvl_done$sEN = dbg_wl_dqs_inverted$sRDY && dbg_wr_calib_clk_delay$sRDY && - dbg_wl_odelay_dqs_tap_cnt_RDY_write__19_AND_db_ETC___d349 ; + dbg_wl_odelay_dqs_tap_cnt_RDY_write__15_AND_db_ETC___d345 ; // submodule dbg_rdlvl_err assign dbg_rdlvl_err$sD_IN = memc_memc$dbg_rdlvl_err ; assign dbg_rdlvl_err$sEN = dbg_wl_dqs_inverted$sRDY && dbg_wr_calib_clk_delay$sRDY && - dbg_wl_odelay_dqs_tap_cnt_RDY_write__19_AND_db_ETC___d349 ; + dbg_wl_odelay_dqs_tap_cnt_RDY_write__15_AND_db_ETC___d345 ; // submodule dbg_wl_dqs_inverted assign dbg_wl_dqs_inverted$sD_IN = memc_memc$dbg_wl_dqs_inverted ; assign dbg_wl_dqs_inverted$sEN = dbg_wl_dqs_inverted$sRDY && dbg_wr_calib_clk_delay$sRDY && - dbg_wl_odelay_dqs_tap_cnt_RDY_write__19_AND_db_ETC___d349 ; + dbg_wl_odelay_dqs_tap_cnt_RDY_write__15_AND_db_ETC___d345 ; // submodule dbg_wl_odelay_dq_tap_cnt assign dbg_wl_odelay_dq_tap_cnt$sD_IN = memc_memc$dbg_wl_odelay_dq_tap_cnt ; assign dbg_wl_odelay_dq_tap_cnt$sEN = dbg_wl_dqs_inverted$sRDY && dbg_wr_calib_clk_delay$sRDY && - dbg_wl_odelay_dqs_tap_cnt_RDY_write__19_AND_db_ETC___d349 ; + dbg_wl_odelay_dqs_tap_cnt_RDY_write__15_AND_db_ETC___d345 ; // submodule dbg_wl_odelay_dqs_tap_cnt assign dbg_wl_odelay_dqs_tap_cnt$sD_IN = memc_memc$dbg_wl_odelay_dqs_tap_cnt ; assign dbg_wl_odelay_dqs_tap_cnt$sEN = dbg_wl_dqs_inverted$sRDY && dbg_wr_calib_clk_delay$sRDY && - dbg_wl_odelay_dqs_tap_cnt_RDY_write__19_AND_db_ETC___d349 ; + dbg_wl_odelay_dqs_tap_cnt_RDY_write__15_AND_db_ETC___d345 ; // submodule dbg_wr_calib_clk_delay assign dbg_wr_calib_clk_delay$sD_IN = memc_memc$dbg_wr_calib_clk_delay ; assign dbg_wr_calib_clk_delay$sEN = dbg_wl_dqs_inverted$sRDY && dbg_wr_calib_clk_delay$sRDY && - dbg_wl_odelay_dqs_tap_cnt_RDY_write__19_AND_db_ETC___d349 ; + dbg_wl_odelay_dqs_tap_cnt_RDY_write__15_AND_db_ETC___d345 ; // submodule firBeat assign firBeat$sD_IN = memc_firstBeat ; @@ -2224,14 +2227,14 @@ module mkDramServer_v6(CLK_sys0_clk, endcase end assign lreqF$sENQ = + WILL_FIRE_RL_wci_cfrd && wci_wslv_reqF$D_OUT[51] || WILL_FIRE_RL_getRequest && (wmemi_reqF$D_OUT[51:49] == 3'd1 || - wmemiReadInFlight_value_07_SLT_16___d767) || + wmemiReadInFlight_value_03_SLT_16___d383) || WILL_FIRE_RL_wci_cfwr && (wci_wslv_reqF$D_OUT[51] || wci_wslv_reqF$D_OUT[39:32] == 8'h54 || - wci_wslv_reqF$D_OUT[39:32] == 8'h58) || - WILL_FIRE_RL_wci_cfrd && wci_wslv_reqF$D_OUT[51] ; + wci_wslv_reqF$D_OUT[39:32] == 8'h58) ; assign lreqF$dDEQ = lreqF$dEMPTY_N && memc_reqF$FULL_N ; // submodule lrespF @@ -2239,7 +2242,7 @@ module mkDramServer_v6(CLK_sys0_clk, assign lrespF$sENQ = lrespF$sFULL_N && memc_respF$EMPTY_N ; assign lrespF$dDEQ = lrespF$dEMPTY_N && - lrespF_RDY_first__16_AND_NOT_wmemi_respF_c_r_4_ETC___d418 && + lrespF_RDY_first__12_AND_NOT_wmemi_respF_cntr__ETC___d414 && (wmemiReadInFlight_value ^ 8'h80) > 8'd128 || WILL_FIRE_RL_advance_response ; @@ -2253,7 +2256,7 @@ module mkDramServer_v6(CLK_sys0_clk, assign memc_memc$app_wdf_data = {2{memc_reqF$D_OUT[127:0]}} ; assign memc_memc$app_wdf_end = WILL_FIRE_RL_memc_advance_write1 ; assign memc_memc$app_wdf_mask = - WILL_FIRE_RL_memc_advance_write0 ? ~x__h6057 : ~x__h6278 ; + WILL_FIRE_RL_memc_advance_write0 ? ~x__h5920 : ~x__h6141 ; assign memc_memc$dbg_dec_cpt = 1'd0 ; assign memc_memc$dbg_dec_rd_dqs = 1'd0 ; assign memc_memc$dbg_inc_cpt = 1'd0 ; @@ -2279,15 +2282,15 @@ module mkDramServer_v6(CLK_sys0_clk, assign memc_reqF$D_IN = lreqF$dD_OUT ; assign memc_reqF$ENQ = lreqF$dEMPTY_N && memc_reqF$FULL_N ; assign memc_reqF$DEQ = + WILL_FIRE_RL_memc_advance_write1 && memc_memc$app_wdf_rdy || WILL_FIRE_RL_memc_advance_request && memc_memc$app_rdy && - memc_reqF$D_OUT[176] || - WILL_FIRE_RL_memc_advance_write1 && memc_memc$app_wdf_rdy ; + memc_reqF$D_OUT[176] ; assign memc_reqF$CLR = 1'b0 ; // submodule memc_respF - always@(x__h6527 or memc_memc$app_rd_data) + always@(x__h6378 or memc_memc$app_rd_data) begin - case (x__h6527) + case (x__h6378) 3'b0, 3'b110: memc_respF$D_IN = memc_memc$app_rd_data[127:0]; 3'b101: memc_respF$D_IN = memc_memc$app_rd_data[255:128]; default: memc_respF$D_IN = memc_memc$app_rd_data[255:128]; @@ -2295,8 +2298,8 @@ module mkDramServer_v6(CLK_sys0_clk, end assign memc_respF$ENQ = WILL_FIRE_RL_memc_advance_readData && - (x__h6527 == 3'b0 || x__h6527 == 3'b101 || x__h6527 == 3'b110 || - x__h6527 == 3'b011) ; + (x__h6378 == 3'b0 || x__h6378 == 3'b101 || x__h6378 == 3'b110 || + x__h6378 == 3'b011) ; assign memc_respF$DEQ = lrespF$sFULL_N && memc_respF$EMPTY_N ; assign memc_respF$CLR = 1'b0 ; @@ -2304,13 +2307,13 @@ module mkDramServer_v6(CLK_sys0_clk, assign requestCount$sD_IN = memc_requestCount ; assign requestCount$sEN = dbg_wl_dqs_inverted$sRDY && dbg_wr_calib_clk_delay$sRDY && - dbg_wl_odelay_dqs_tap_cnt_RDY_write__19_AND_db_ETC___d349 ; + dbg_wl_odelay_dqs_tap_cnt_RDY_write__15_AND_db_ETC___d345 ; // submodule responseCount assign responseCount$sD_IN = memc_responseCount ; assign responseCount$sEN = dbg_wl_dqs_inverted$sRDY && dbg_wr_calib_clk_delay$sRDY && - dbg_wl_odelay_dqs_tap_cnt_RDY_write__19_AND_db_ETC___d349 ; + dbg_wl_odelay_dqs_tap_cnt_RDY_write__15_AND_db_ETC___d345 ; // submodule secBeat assign secBeat$sD_IN = memc_secondBeat ; @@ -2318,7 +2321,7 @@ module mkDramServer_v6(CLK_sys0_clk, // submodule splaF assign splaF$D_IN = wci_wslv_reqF$D_OUT[35:34] ; - assign splaF$ENQ = MUX_lreqF$enq_1__SEL_3 ; + assign splaF$ENQ = MUX_lreqF$enq_1__SEL_1 ; assign splaF$DEQ = MUX_splitReadInFlight$write_1__SEL_1 ; assign splaF$CLR = 1'b0 ; @@ -2346,123 +2349,139 @@ module mkDramServer_v6(CLK_sys0_clk, assign wmemi_reqF$CLR = 1'b0 ; // remaining internal signals - assign IF_memc_memc_app_rd_data_end__11_CONCAT_memc_r_ETC___d227 = - CASE_x527_NOT_x527_EQ_0b11_OR_memc_respFFULL__ETC__q2 && + assign IF_memc_memc_app_rd_data_end__09_CONCAT_memc_r_ETC___d225 = + CASE_x378_0b0_memc_respFFULL_N_0b101_memc_res_ETC__q1 && (!memc_memc$app_rd_data_end || memc_rdpF$EMPTY_N) ; - assign IF_wci_wslv_reqF_first__5_BIT_51_55_THEN_lreqF_ETC___d531 = + assign IF_wci_wslv_reqF_first__3_BIT_51_45_THEN_lreqF_ETC___d521 = wci_wslv_reqF$D_OUT[51] ? lreqF$sFULL_N && splaF$FULL_N : - wci_wslv_respF_c_r != 2'd2 ; - assign IF_wci_wslv_reqF_first__5_BIT_51_55_THEN_pReg__ETC___d506 = + wci_wslv_respF_cntr_r != 2'd2 ; + assign IF_wci_wslv_reqF_first__3_BIT_51_45_THEN_pReg__ETC___d496 = wci_wslv_reqF$D_OUT[51] ? - { x1_addr__h17583, x1_be__h17584, x1_data__h17585 } : - { wci_wslv_reqF$D_OUT[31:0], mReg, x1_data__h16584 } ; - assign IF_wmemi_reqF_first__81_BITS_51_TO_49_82_EQ_1__ETC___d390 = + { x1_addr__h17268, x1_be__h17269, x1_data__h17270 } : + { wci_wslv_reqF$D_OUT[31:0], mReg, x1_data__h16261 } ; + assign IF_wmemi_reqF_first__77_BITS_51_TO_49_78_EQ_1__ETC___d386 = (wmemi_reqF$D_OUT[51:49] == 3'd1) ? lreqF$sFULL_N && wmemi_dhF$EMPTY_N : - !wmemiReadInFlight_value_07_SLT_16___d767 || lreqF$sFULL_N ; - assign dbg_rd_active_dly_RDY_write__28_AND_dbg_dqs_p__ETC___d340 = + !wmemiReadInFlight_value_03_SLT_16___d383 || lreqF$sFULL_N ; + assign _dfoo1 = + wci_wslv_respF_cntr_r != 2'd2 || + wci_wslv_respF_cntr_r_8_MINUS_1___d27 == 2'd1 ; + assign _dfoo3 = + wci_wslv_respF_cntr_r != 2'd1 || + wci_wslv_respF_cntr_r_8_MINUS_1___d27 == 2'd0 ; + assign _dfoo5 = + wmemi_respF_cntr_r != 2'd2 || + wmemi_respF_cntr_r_47_MINUS_1___d256 == 2'd1 ; + assign _dfoo7 = + wmemi_respF_cntr_r != 2'd1 || + wmemi_respF_cntr_r_47_MINUS_1___d256 == 2'd0 ; + assign dbg_rd_active_dly_RDY_write__24_AND_dbg_dqs_p__ETC___d336 = dbg_rd_active_dly$sRDY && dbg_dqs_p_tap_cnt$sRDY && dbg_dqs_n_tap_cnt$sRDY && dbg_dq_tap_cnt$sRDY && dbg_rddata$sRDY && requestCount$sRDY && responseCount$sRDY ; - assign dbg_rdlvl_err_RDY_write__22_AND_dbg_cpt_tap_cn_ETC___d346 = + assign dbg_rdlvl_err_RDY_write__18_AND_dbg_cpt_tap_cn_ETC___d342 = dbg_rdlvl_err$sRDY && dbg_cpt_tap_cnt$sRDY && dbg_cpt_first_edge_cnt$sRDY && dbg_cpt_second_edge_cnt$sRDY && dbg_rd_bitslip_cnt$sRDY && dbg_rd_clkdly_cnt$sRDY && - dbg_rd_active_dly_RDY_write__28_AND_dbg_dqs_p__ETC___d340 ; - assign dbg_wl_odelay_dqs_tap_cnt_RDY_write__19_AND_db_ETC___d349 = + dbg_rd_active_dly_RDY_write__24_AND_dbg_dqs_p__ETC___d336 ; + assign dbg_wl_odelay_dqs_tap_cnt_RDY_write__15_AND_db_ETC___d345 = dbg_wl_odelay_dqs_tap_cnt$sRDY && dbg_wl_odelay_dq_tap_cnt$sRDY && dbg_rdlvl_done$sRDY && - dbg_rdlvl_err_RDY_write__22_AND_dbg_cpt_tap_cn_ETC___d346 ; - assign dramStatus__h13959 = { 16'd0, x__h19149 } ; - assign g_data__h19109 = + dbg_rdlvl_err_RDY_write__18_AND_dbg_cpt_tap_cn_ETC___d342 ; + assign dramStatus__h13684 = { 16'd0, x__h18777 } ; + assign g_data__h18737 = wci_wslv_reqF$D_OUT[51] ? 32'd0 : - CASE_wci_wslv_reqFD_OUT_BITS_39_TO_32_0_0x0_d_ETC__q1 ; - assign lrespF_RDY_first__16_AND_NOT_splitReadInFlight_ETC___d434 = + IF_wci_wslv_reqF_first__3_BITS_39_TO_32_46_EQ__ETC___d663 ; + assign lrespF_RDY_first__12_AND_NOT_splitReadInFlight_ETC___d430 = lrespF$dEMPTY_N && (!splitReadInFlight || - splaF$EMPTY_N && wci_wslv_respF_c_r != 2'd2) ; - assign lrespF_RDY_first__16_AND_NOT_wmemi_respF_c_r_4_ETC___d418 = - lrespF$dEMPTY_N && wmemi_respF_c_r != 2'd2 && wmemi_operateD && + splaF$EMPTY_N && wci_wslv_respF_cntr_r != 2'd2) ; + assign lrespF_RDY_first__12_AND_NOT_wmemi_respF_cntr__ETC___d414 = + lrespF$dEMPTY_N && wmemi_respF_cntr_r != 2'd2 && + wmemi_operateD && wmemi_peerIsReady ; - assign myBE__h6094 = { 16'h0, memc_reqF$D_OUT[143:128] } ; - assign myBE__h6127 = { memc_reqF$D_OUT[143:128], 16'h0 } ; - assign rdat___1__h19172 = + assign myBE__h5957 = { 16'h0, memc_reqF$D_OUT[143:128] } ; + assign myBE__h5990 = { memc_reqF$D_OUT[143:128], 16'h0 } ; + assign rdat___1__h18800 = hasDebugLogic ? { 24'd0, dbg_wl_dqs_inverted$dD_OUT } : 32'd0 ; - assign rdat___1__h19183 = + assign rdat___1__h18811 = hasDebugLogic ? { 16'd0, dbg_wr_calib_clk_delay$dD_OUT } : 32'd0 ; - assign rdat___1__h19194 = + assign rdat___1__h18822 = hasDebugLogic ? dbg_wl_odelay_dqs_tap_cnt$dD_OUT[31:0] : 32'd0 ; - assign rdat___1__h19205 = + assign rdat___1__h18833 = hasDebugLogic ? dbg_wl_odelay_dq_tap_cnt$dD_OUT[31:0] : 32'd0 ; - assign rdat___1__h19216 = + assign rdat___1__h18844 = hasDebugLogic ? { 30'd0, dbg_rdlvl_done$dD_OUT } : 32'd0 ; - assign rdat___1__h19227 = + assign rdat___1__h18855 = hasDebugLogic ? { 30'd0, dbg_rdlvl_err$dD_OUT } : 32'd0 ; - assign rdat___1__h19238 = + assign rdat___1__h18866 = hasDebugLogic ? dbg_cpt_tap_cnt$dD_OUT[31:0] : 32'd0 ; - assign rdat___1__h19249 = + assign rdat___1__h18877 = hasDebugLogic ? dbg_cpt_first_edge_cnt$dD_OUT[31:0] : 32'd0 ; - assign rdat___1__h19260 = + assign rdat___1__h18888 = hasDebugLogic ? dbg_cpt_second_edge_cnt$dD_OUT[31:0] : 32'd0 ; - assign rdat___1__h19271 = + assign rdat___1__h18899 = hasDebugLogic ? { 8'd0, dbg_rd_bitslip_cnt$dD_OUT } : 32'd0 ; - assign rdat___1__h19282 = + assign rdat___1__h18910 = hasDebugLogic ? { 16'd0, dbg_rd_clkdly_cnt$dD_OUT } : 32'd0 ; - assign rdat___1__h19293 = + assign rdat___1__h18921 = hasDebugLogic ? { 27'd0, dbg_rd_active_dly$dD_OUT } : 32'd0 ; - assign rdat___1__h19304 = + assign rdat___1__h18932 = hasDebugLogic ? dbg_dqs_p_tap_cnt$dD_OUT[31:0] : 32'd0 ; - assign rdat___1__h19315 = + assign rdat___1__h18943 = hasDebugLogic ? dbg_dqs_n_tap_cnt$dD_OUT[31:0] : 32'd0 ; - assign rdat___1__h19326 = + assign rdat___1__h18954 = hasDebugLogic ? dbg_dq_tap_cnt$dD_OUT[31:0] : 32'd0 ; - assign rdat___1__h19337 = hasDebugLogic ? dbg_rddata$dD_OUT : 32'd0 ; - assign rdat___1__h19344 = + assign rdat___1__h18965 = hasDebugLogic ? dbg_rddata$dD_OUT : 32'd0 ; + assign rdat___1__h18972 = hasDebugLogic ? { 16'd0, requestCount$dD_OUT } : 32'd0 ; - assign rdat___1__h19355 = + assign rdat___1__h18983 = hasDebugLogic ? { 16'd0, responseCount$dD_OUT } : 32'd0 ; - assign rdat___1__h19366 = hasDebugLogic ? { 16'd0, pReg } : 32'd0 ; - assign rdat___1__h19376 = hasDebugLogic ? { 16'd0, mReg } : 32'd0 ; - assign rdat___1__h19386 = hasDebugLogic ? wdReg : 32'd0 ; - assign rdat___1__h19400 = hasDebugLogic ? wdReg_1 : 32'd0 ; - assign rdat___1__h19414 = hasDebugLogic ? wdReg_2 : 32'd0 ; - assign rdat___1__h19428 = hasDebugLogic ? wdReg_3 : 32'd0 ; - assign rdat___1__h19442 = hasDebugLogic ? rdReg : 32'd0 ; - assign rdat___1__h19457 = hasDebugLogic ? rdReg_1 : 32'd0 ; - assign rdat___1__h19472 = hasDebugLogic ? rdReg_2 : 32'd0 ; - assign rdat___1__h19487 = hasDebugLogic ? rdReg_3 : 32'd0 ; - assign rdat___1__h19502 = hasDebugLogic ? wmemiWrReq : 32'd0 ; - assign rdat___1__h19508 = hasDebugLogic ? wmemiRdReq : 32'd0 ; - assign rdat___1__h19514 = hasDebugLogic ? wmemiRdResp : 32'd0 ; - assign wci_wslv_reqF_i_notEmpty__4_AND_IF_wci_wslv_re_ETC___d467 = + assign rdat___1__h18994 = hasDebugLogic ? { 16'd0, pReg } : 32'd0 ; + assign rdat___1__h19004 = hasDebugLogic ? { 16'd0, mReg } : 32'd0 ; + assign rdat___1__h19014 = hasDebugLogic ? wdReg_0 : 32'd0 ; + assign rdat___1__h19028 = hasDebugLogic ? wdReg_1 : 32'd0 ; + assign rdat___1__h19042 = hasDebugLogic ? wdReg_2 : 32'd0 ; + assign rdat___1__h19056 = hasDebugLogic ? wdReg_3 : 32'd0 ; + assign rdat___1__h19070 = hasDebugLogic ? rdReg_0 : 32'd0 ; + assign rdat___1__h19085 = hasDebugLogic ? rdReg_1 : 32'd0 ; + assign rdat___1__h19100 = hasDebugLogic ? rdReg_2 : 32'd0 ; + assign rdat___1__h19115 = hasDebugLogic ? rdReg_3 : 32'd0 ; + assign rdat___1__h19130 = hasDebugLogic ? wmemiWrReq : 32'd0 ; + assign rdat___1__h19136 = hasDebugLogic ? wmemiRdReq : 32'd0 ; + assign rdat___1__h19142 = hasDebugLogic ? wmemiRdResp : 32'd0 ; + assign wci_wslv_reqF_i_notEmpty__2_AND_IF_wci_wslv_re_ETC___d457 = wci_wslv_reqF$EMPTY_N && (wci_wslv_reqF$D_OUT[51] ? lreqF$sFULL_N : ((wci_wslv_reqF$D_OUT[39:32] == 8'h54) ? lreqF$sFULL_N : wci_wslv_reqF$D_OUT[39:32] != 8'h58 || lreqF$sFULL_N)) ; - assign wmemiReadInFlight_value_07_SLT_16___d767 = + assign wci_wslv_respF_cntr_r_8_MINUS_1___d27 = + wci_wslv_respF_cntr_r - 2'd1 ; + assign wmemiReadInFlight_value_03_SLT_16___d383 = (wmemiReadInFlight_value ^ 8'h80) < 8'd144 ; - assign x1__h12744 = !memc_memc$app_rdy ; - assign x1_addr__h17583 = { pReg[12:0], wci_wslv_reqF$D_OUT[50:36], 4'd0 } ; - assign x1_be__h17584 = + assign wmemi_respF_cntr_r_47_MINUS_1___d256 = wmemi_respF_cntr_r - 2'd1 ; + assign x1__h12469 = !memc_memc$app_rdy ; + assign x1_addr__h17268 = { pReg[12:0], wci_wslv_reqF$D_OUT[50:36], 4'd0 } ; + assign x1_be__h17269 = { (wci_wslv_reqF$D_OUT[35:34] == 2'd3) ? 4'hF : 4'h0, (wci_wslv_reqF$D_OUT[35:34] == 2'd2) ? 4'hF : 4'h0, (wci_wslv_reqF$D_OUT[35:34] == 2'd1) ? 4'hF : 4'h0, (wci_wslv_reqF$D_OUT[35:34] == 2'd0) ? 4'hF : 4'h0 } ; - assign x1_data__h16584 = { wdReg_3, wdReg_2, wdReg_1, wdReg } ; - assign x1_data__h17585 = {4{wci_wslv_reqF$D_OUT[31:0]}} ; - assign x__h19149 = + assign x1_data__h16261 = { wdReg_3, wdReg_2, wdReg_1, wdReg_0 } ; + assign x1_data__h17270 = {4{wci_wslv_reqF$D_OUT[31:0]}} ; + assign x__h18777 = { respCount, 2'h0, memIsResetCC$dD_OUT, @@ -2471,174 +2490,177 @@ module mkDramServer_v6(CLK_sys0_clk, secBeat$dD_OUT, firBeat$dD_OUT, initComplete$dD_OUT } ; - assign x__h6527 = { memc_memc$app_rd_data_end, memc_rdpF$D_OUT } ; + assign x__h6378 = { memc_memc$app_rd_data_end, memc_rdpF$D_OUT } ; always@(splaF$D_OUT or lrespF$dD_OUT) begin case (splaF$D_OUT) - 2'd0: g_data__h15336 = lrespF$dD_OUT[31:0]; - 2'd1: g_data__h15336 = lrespF$dD_OUT[63:32]; - 2'd2: g_data__h15336 = lrespF$dD_OUT[95:64]; - 2'd3: g_data__h15336 = lrespF$dD_OUT[127:96]; + 2'd0: g_data__h15073 = lrespF$dD_OUT[31:0]; + 2'd1: g_data__h15073 = lrespF$dD_OUT[63:32]; + 2'd2: g_data__h15073 = lrespF$dD_OUT[95:64]; + 2'd3: g_data__h15073 = lrespF$dD_OUT[127:96]; + endcase + end + always@(memc_reqF$D_OUT or myBE__h5957 or myBE__h5990) + begin + case (memc_reqF$D_OUT[149:148]) + 2'b0: x__h5920 = myBE__h5957; + 2'b01: x__h5920 = myBE__h5990; + default: x__h5920 = 32'd0; + endcase + end + always@(memc_reqF$D_OUT or myBE__h5957 or myBE__h5990) + begin + case (memc_reqF$D_OUT[149:148]) + 2'b10: x__h6141 = myBE__h5957; + 2'b11: x__h6141 = myBE__h5990; + default: x__h6141 = 32'd0; + endcase + end + always@(x__h6378 or memc_respF$FULL_N) + begin + case (x__h6378) + 3'b0, 3'b101, 3'b110: + CASE_x378_0b0_memc_respFFULL_N_0b101_memc_res_ETC__q1 = + memc_respF$FULL_N; + default: CASE_x378_0b0_memc_respFFULL_N_0b101_memc_res_ETC__q1 = + x__h6378 != 3'b011 || memc_respF$FULL_N; endcase end always@(wci_wslv_reqF$D_OUT or - dramStatus__h13959 or + dramStatus__h13684 or dramCtrl or - rdat___1__h19172 or - rdat___1__h19183 or - rdat___1__h19194 or - rdat___1__h19205 or - rdat___1__h19216 or - rdat___1__h19227 or - rdat___1__h19238 or - rdat___1__h19249 or - rdat___1__h19260 or - rdat___1__h19271 or - rdat___1__h19282 or - rdat___1__h19293 or - rdat___1__h19304 or - rdat___1__h19315 or - rdat___1__h19326 or - rdat___1__h19337 or - rdat___1__h19344 or - rdat___1__h19355 or - rdat___1__h19366 or - rdat___1__h19376 or - rdat___1__h19386 or - rdat___1__h19400 or - rdat___1__h19414 or - rdat___1__h19428 or - rdat___1__h19442 or - rdat___1__h19457 or - rdat___1__h19472 or - rdat___1__h19487 or - rdat___1__h19502 or rdat___1__h19508 or rdat___1__h19514) + rdat___1__h18800 or + rdat___1__h18811 or + rdat___1__h18822 or + rdat___1__h18833 or + rdat___1__h18844 or + rdat___1__h18855 or + rdat___1__h18866 or + rdat___1__h18877 or + rdat___1__h18888 or + rdat___1__h18899 or + rdat___1__h18910 or + rdat___1__h18921 or + rdat___1__h18932 or + rdat___1__h18943 or + rdat___1__h18954 or + rdat___1__h18965 or + rdat___1__h18972 or + rdat___1__h18983 or + rdat___1__h18994 or + rdat___1__h19004 or + rdat___1__h19014 or + rdat___1__h19028 or + rdat___1__h19042 or + rdat___1__h19056 or + rdat___1__h19070 or + rdat___1__h19085 or + rdat___1__h19100 or + rdat___1__h19115 or + rdat___1__h19130 or rdat___1__h19136 or rdat___1__h19142) begin case (wci_wslv_reqF$D_OUT[39:32]) 8'h0: - CASE_wci_wslv_reqFD_OUT_BITS_39_TO_32_0_0x0_d_ETC__q1 = - dramStatus__h13959; - 8'h04: CASE_wci_wslv_reqFD_OUT_BITS_39_TO_32_0_0x0_d_ETC__q1 = dramCtrl; + IF_wci_wslv_reqF_first__3_BITS_39_TO_32_46_EQ__ETC___d663 = + dramStatus__h13684; + 8'h04: + IF_wci_wslv_reqF_first__3_BITS_39_TO_32_46_EQ__ETC___d663 = + dramCtrl; 8'h08: - CASE_wci_wslv_reqFD_OUT_BITS_39_TO_32_0_0x0_d_ETC__q1 = - rdat___1__h19172; + IF_wci_wslv_reqF_first__3_BITS_39_TO_32_46_EQ__ETC___d663 = + rdat___1__h18800; 8'h0C: - CASE_wci_wslv_reqFD_OUT_BITS_39_TO_32_0_0x0_d_ETC__q1 = - rdat___1__h19183; + IF_wci_wslv_reqF_first__3_BITS_39_TO_32_46_EQ__ETC___d663 = + rdat___1__h18811; 8'h10: - CASE_wci_wslv_reqFD_OUT_BITS_39_TO_32_0_0x0_d_ETC__q1 = - rdat___1__h19194; + IF_wci_wslv_reqF_first__3_BITS_39_TO_32_46_EQ__ETC___d663 = + rdat___1__h18822; 8'h14: - CASE_wci_wslv_reqFD_OUT_BITS_39_TO_32_0_0x0_d_ETC__q1 = - rdat___1__h19205; + IF_wci_wslv_reqF_first__3_BITS_39_TO_32_46_EQ__ETC___d663 = + rdat___1__h18833; 8'h18: - CASE_wci_wslv_reqFD_OUT_BITS_39_TO_32_0_0x0_d_ETC__q1 = - rdat___1__h19216; + IF_wci_wslv_reqF_first__3_BITS_39_TO_32_46_EQ__ETC___d663 = + rdat___1__h18844; 8'h1C: - CASE_wci_wslv_reqFD_OUT_BITS_39_TO_32_0_0x0_d_ETC__q1 = - rdat___1__h19227; + IF_wci_wslv_reqF_first__3_BITS_39_TO_32_46_EQ__ETC___d663 = + rdat___1__h18855; 8'h20: - CASE_wci_wslv_reqFD_OUT_BITS_39_TO_32_0_0x0_d_ETC__q1 = - rdat___1__h19238; + IF_wci_wslv_reqF_first__3_BITS_39_TO_32_46_EQ__ETC___d663 = + rdat___1__h18866; 8'h24: - CASE_wci_wslv_reqFD_OUT_BITS_39_TO_32_0_0x0_d_ETC__q1 = - rdat___1__h19249; + IF_wci_wslv_reqF_first__3_BITS_39_TO_32_46_EQ__ETC___d663 = + rdat___1__h18877; 8'h28: - CASE_wci_wslv_reqFD_OUT_BITS_39_TO_32_0_0x0_d_ETC__q1 = - rdat___1__h19260; + IF_wci_wslv_reqF_first__3_BITS_39_TO_32_46_EQ__ETC___d663 = + rdat___1__h18888; 8'h2C: - CASE_wci_wslv_reqFD_OUT_BITS_39_TO_32_0_0x0_d_ETC__q1 = - rdat___1__h19271; + IF_wci_wslv_reqF_first__3_BITS_39_TO_32_46_EQ__ETC___d663 = + rdat___1__h18899; 8'h30: - CASE_wci_wslv_reqFD_OUT_BITS_39_TO_32_0_0x0_d_ETC__q1 = - rdat___1__h19282; + IF_wci_wslv_reqF_first__3_BITS_39_TO_32_46_EQ__ETC___d663 = + rdat___1__h18910; 8'h34: - CASE_wci_wslv_reqFD_OUT_BITS_39_TO_32_0_0x0_d_ETC__q1 = - rdat___1__h19293; + IF_wci_wslv_reqF_first__3_BITS_39_TO_32_46_EQ__ETC___d663 = + rdat___1__h18921; 8'h38: - CASE_wci_wslv_reqFD_OUT_BITS_39_TO_32_0_0x0_d_ETC__q1 = - rdat___1__h19304; + IF_wci_wslv_reqF_first__3_BITS_39_TO_32_46_EQ__ETC___d663 = + rdat___1__h18932; 8'h3C: - CASE_wci_wslv_reqFD_OUT_BITS_39_TO_32_0_0x0_d_ETC__q1 = - rdat___1__h19315; + IF_wci_wslv_reqF_first__3_BITS_39_TO_32_46_EQ__ETC___d663 = + rdat___1__h18943; 8'h40: - CASE_wci_wslv_reqFD_OUT_BITS_39_TO_32_0_0x0_d_ETC__q1 = - rdat___1__h19326; + IF_wci_wslv_reqF_first__3_BITS_39_TO_32_46_EQ__ETC___d663 = + rdat___1__h18954; 8'h44: - CASE_wci_wslv_reqFD_OUT_BITS_39_TO_32_0_0x0_d_ETC__q1 = - rdat___1__h19337; + IF_wci_wslv_reqF_first__3_BITS_39_TO_32_46_EQ__ETC___d663 = + rdat___1__h18965; 8'h48: - CASE_wci_wslv_reqFD_OUT_BITS_39_TO_32_0_0x0_d_ETC__q1 = - rdat___1__h19344; + IF_wci_wslv_reqF_first__3_BITS_39_TO_32_46_EQ__ETC___d663 = + rdat___1__h18972; 8'h4C: - CASE_wci_wslv_reqFD_OUT_BITS_39_TO_32_0_0x0_d_ETC__q1 = - rdat___1__h19355; + IF_wci_wslv_reqF_first__3_BITS_39_TO_32_46_EQ__ETC___d663 = + rdat___1__h18983; 8'h50: - CASE_wci_wslv_reqFD_OUT_BITS_39_TO_32_0_0x0_d_ETC__q1 = - rdat___1__h19366; + IF_wci_wslv_reqF_first__3_BITS_39_TO_32_46_EQ__ETC___d663 = + rdat___1__h18994; 8'h5C: - CASE_wci_wslv_reqFD_OUT_BITS_39_TO_32_0_0x0_d_ETC__q1 = - rdat___1__h19376; + IF_wci_wslv_reqF_first__3_BITS_39_TO_32_46_EQ__ETC___d663 = + rdat___1__h19004; 8'h60: - CASE_wci_wslv_reqFD_OUT_BITS_39_TO_32_0_0x0_d_ETC__q1 = - rdat___1__h19386; + IF_wci_wslv_reqF_first__3_BITS_39_TO_32_46_EQ__ETC___d663 = + rdat___1__h19014; 8'h64: - CASE_wci_wslv_reqFD_OUT_BITS_39_TO_32_0_0x0_d_ETC__q1 = - rdat___1__h19400; + IF_wci_wslv_reqF_first__3_BITS_39_TO_32_46_EQ__ETC___d663 = + rdat___1__h19028; 8'h68: - CASE_wci_wslv_reqFD_OUT_BITS_39_TO_32_0_0x0_d_ETC__q1 = - rdat___1__h19414; + IF_wci_wslv_reqF_first__3_BITS_39_TO_32_46_EQ__ETC___d663 = + rdat___1__h19042; 8'h6C: - CASE_wci_wslv_reqFD_OUT_BITS_39_TO_32_0_0x0_d_ETC__q1 = - rdat___1__h19428; + IF_wci_wslv_reqF_first__3_BITS_39_TO_32_46_EQ__ETC___d663 = + rdat___1__h19056; 8'h80: - CASE_wci_wslv_reqFD_OUT_BITS_39_TO_32_0_0x0_d_ETC__q1 = - rdat___1__h19442; + IF_wci_wslv_reqF_first__3_BITS_39_TO_32_46_EQ__ETC___d663 = + rdat___1__h19070; 8'h84: - CASE_wci_wslv_reqFD_OUT_BITS_39_TO_32_0_0x0_d_ETC__q1 = - rdat___1__h19457; + IF_wci_wslv_reqF_first__3_BITS_39_TO_32_46_EQ__ETC___d663 = + rdat___1__h19085; 8'h88: - CASE_wci_wslv_reqFD_OUT_BITS_39_TO_32_0_0x0_d_ETC__q1 = - rdat___1__h19472; + IF_wci_wslv_reqF_first__3_BITS_39_TO_32_46_EQ__ETC___d663 = + rdat___1__h19100; 8'h8C: - CASE_wci_wslv_reqFD_OUT_BITS_39_TO_32_0_0x0_d_ETC__q1 = - rdat___1__h19487; + IF_wci_wslv_reqF_first__3_BITS_39_TO_32_46_EQ__ETC___d663 = + rdat___1__h19115; 8'h90: - CASE_wci_wslv_reqFD_OUT_BITS_39_TO_32_0_0x0_d_ETC__q1 = - rdat___1__h19502; + IF_wci_wslv_reqF_first__3_BITS_39_TO_32_46_EQ__ETC___d663 = + rdat___1__h19130; 8'h94: - CASE_wci_wslv_reqFD_OUT_BITS_39_TO_32_0_0x0_d_ETC__q1 = - rdat___1__h19508; + IF_wci_wslv_reqF_first__3_BITS_39_TO_32_46_EQ__ETC___d663 = + rdat___1__h19136; 8'h98: - CASE_wci_wslv_reqFD_OUT_BITS_39_TO_32_0_0x0_d_ETC__q1 = - rdat___1__h19514; - default: CASE_wci_wslv_reqFD_OUT_BITS_39_TO_32_0_0x0_d_ETC__q1 = 32'd0; - endcase - end - always@(memc_reqF$D_OUT or myBE__h6094 or myBE__h6127) - begin - case (memc_reqF$D_OUT[149:148]) - 2'b0: x__h6057 = myBE__h6094; - 2'b01: x__h6057 = myBE__h6127; - default: x__h6057 = 32'd0; - endcase - end - always@(memc_reqF$D_OUT or myBE__h6094 or myBE__h6127) - begin - case (memc_reqF$D_OUT[149:148]) - 2'b10: x__h6278 = myBE__h6094; - 2'b11: x__h6278 = myBE__h6127; - default: x__h6278 = 32'd0; - endcase - end - always@(x__h6527 or memc_respF$FULL_N) - begin - case (x__h6527) - 3'b0, 3'b101, 3'b110: - CASE_x527_NOT_x527_EQ_0b11_OR_memc_respFFULL__ETC__q2 = - memc_respF$FULL_N; - default: CASE_x527_NOT_x527_EQ_0b11_OR_memc_respFFULL__ETC__q2 = - x__h6527 != 3'b011 || memc_respF$FULL_N; + IF_wci_wslv_reqF_first__3_BITS_39_TO_32_46_EQ__ETC___d663 = + rdat___1__h19142; + default: IF_wci_wslv_reqF_first__3_BITS_39_TO_32_46_EQ__ETC___d663 = + 32'd0; endcase end @@ -2652,7 +2674,7 @@ module mkDramServer_v6(CLK_sys0_clk, mReg <= `BSV_ASSIGNMENT_DELAY 16'd0; pReg <= `BSV_ASSIGNMENT_DELAY 16'd0; pioReadInFlight <= `BSV_ASSIGNMENT_DELAY 1'd0; - rdReg <= `BSV_ASSIGNMENT_DELAY 32'd0; + rdReg_0 <= `BSV_ASSIGNMENT_DELAY 32'd0; rdReg_1 <= `BSV_ASSIGNMENT_DELAY 32'd0; rdReg_2 <= `BSV_ASSIGNMENT_DELAY 32'd0; rdReg_3 <= `BSV_ASSIGNMENT_DELAY 32'd0; @@ -2665,12 +2687,12 @@ module mkDramServer_v6(CLK_sys0_clk, wci_wslv_illegalEdge <= `BSV_ASSIGNMENT_DELAY 1'd0; wci_wslv_nState <= `BSV_ASSIGNMENT_DELAY 3'd0; wci_wslv_reqF_countReg <= `BSV_ASSIGNMENT_DELAY 2'd0; - wci_wslv_respF_c_r <= `BSV_ASSIGNMENT_DELAY 2'd0; + wci_wslv_respF_cntr_r <= `BSV_ASSIGNMENT_DELAY 2'd0; wci_wslv_respF_q_0 <= `BSV_ASSIGNMENT_DELAY 34'h0AAAAAAAA; wci_wslv_respF_q_1 <= `BSV_ASSIGNMENT_DELAY 34'h0AAAAAAAA; wci_wslv_sFlagReg <= `BSV_ASSIGNMENT_DELAY 1'd0; wci_wslv_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY 1'd1; - wdReg <= `BSV_ASSIGNMENT_DELAY 32'd0; + wdReg_0 <= `BSV_ASSIGNMENT_DELAY 32'd0; wdReg_1 <= `BSV_ASSIGNMENT_DELAY 32'd0; wdReg_2 <= `BSV_ASSIGNMENT_DELAY 32'd0; wdReg_3 <= `BSV_ASSIGNMENT_DELAY 32'd0; @@ -2681,7 +2703,7 @@ module mkDramServer_v6(CLK_sys0_clk, wmemi_errorSticky <= `BSV_ASSIGNMENT_DELAY 1'd0; wmemi_operateD <= `BSV_ASSIGNMENT_DELAY 1'd0; wmemi_peerIsReady <= `BSV_ASSIGNMENT_DELAY 1'd0; - wmemi_respF_c_r <= `BSV_ASSIGNMENT_DELAY 2'd0; + wmemi_respF_cntr_r <= `BSV_ASSIGNMENT_DELAY 2'd0; wmemi_respF_q_0 <= `BSV_ASSIGNMENT_DELAY 131'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; wmemi_respF_q_1 <= `BSV_ASSIGNMENT_DELAY @@ -2695,7 +2717,7 @@ module mkDramServer_v6(CLK_sys0_clk, if (pReg$EN) pReg <= `BSV_ASSIGNMENT_DELAY pReg$D_IN; if (pioReadInFlight$EN) pioReadInFlight <= `BSV_ASSIGNMENT_DELAY pioReadInFlight$D_IN; - if (rdReg$EN) rdReg <= `BSV_ASSIGNMENT_DELAY rdReg$D_IN; + if (rdReg_0$EN) rdReg_0 <= `BSV_ASSIGNMENT_DELAY rdReg_0$D_IN; if (rdReg_1$EN) rdReg_1 <= `BSV_ASSIGNMENT_DELAY rdReg_1$D_IN; if (rdReg_2$EN) rdReg_2 <= `BSV_ASSIGNMENT_DELAY rdReg_2$D_IN; if (rdReg_3$EN) rdReg_3 <= `BSV_ASSIGNMENT_DELAY rdReg_3$D_IN; @@ -2719,8 +2741,9 @@ module mkDramServer_v6(CLK_sys0_clk, if (wci_wslv_reqF_countReg$EN) wci_wslv_reqF_countReg <= `BSV_ASSIGNMENT_DELAY wci_wslv_reqF_countReg$D_IN; - if (wci_wslv_respF_c_r$EN) - wci_wslv_respF_c_r <= `BSV_ASSIGNMENT_DELAY wci_wslv_respF_c_r$D_IN; + if (wci_wslv_respF_cntr_r$EN) + wci_wslv_respF_cntr_r <= `BSV_ASSIGNMENT_DELAY + wci_wslv_respF_cntr_r$D_IN; if (wci_wslv_respF_q_0$EN) wci_wslv_respF_q_0 <= `BSV_ASSIGNMENT_DELAY wci_wslv_respF_q_0$D_IN; if (wci_wslv_respF_q_1$EN) @@ -2730,7 +2753,7 @@ module mkDramServer_v6(CLK_sys0_clk, if (wci_wslv_sThreadBusy_d$EN) wci_wslv_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY wci_wslv_sThreadBusy_d$D_IN; - if (wdReg$EN) wdReg <= `BSV_ASSIGNMENT_DELAY wdReg$D_IN; + if (wdReg_0$EN) wdReg_0 <= `BSV_ASSIGNMENT_DELAY wdReg_0$D_IN; if (wdReg_1$EN) wdReg_1 <= `BSV_ASSIGNMENT_DELAY wdReg_1$D_IN; if (wdReg_2$EN) wdReg_2 <= `BSV_ASSIGNMENT_DELAY wdReg_2$D_IN; if (wdReg_3$EN) wdReg_3 <= `BSV_ASSIGNMENT_DELAY wdReg_3$D_IN; @@ -2749,8 +2772,8 @@ module mkDramServer_v6(CLK_sys0_clk, wmemi_operateD <= `BSV_ASSIGNMENT_DELAY wmemi_operateD$D_IN; if (wmemi_peerIsReady$EN) wmemi_peerIsReady <= `BSV_ASSIGNMENT_DELAY wmemi_peerIsReady$D_IN; - if (wmemi_respF_c_r$EN) - wmemi_respF_c_r <= `BSV_ASSIGNMENT_DELAY wmemi_respF_c_r$D_IN; + if (wmemi_respF_cntr_r$EN) + wmemi_respF_cntr_r <= `BSV_ASSIGNMENT_DELAY wmemi_respF_cntr_r$D_IN; if (wmemi_respF_q_0$EN) wmemi_respF_q_0 <= `BSV_ASSIGNMENT_DELAY wmemi_respF_q_0$D_IN; if (wmemi_respF_q_1$EN) @@ -2830,7 +2853,7 @@ module mkDramServer_v6(CLK_sys0_clk, memc_secondBeat = 1'h0; pReg = 16'hAAAA; pioReadInFlight = 1'h0; - rdReg = 32'hAAAAAAAA; + rdReg_0 = 32'hAAAAAAAA; rdReg_1 = 32'hAAAAAAAA; rdReg_2 = 32'hAAAAAAAA; rdReg_3 = 32'hAAAAAAAA; @@ -2844,12 +2867,12 @@ module mkDramServer_v6(CLK_sys0_clk, wci_wslv_isReset_isInReset = 1'h0; wci_wslv_nState = 3'h2; wci_wslv_reqF_countReg = 2'h2; - wci_wslv_respF_c_r = 2'h2; + wci_wslv_respF_cntr_r = 2'h2; wci_wslv_respF_q_0 = 34'h2AAAAAAAA; wci_wslv_respF_q_1 = 34'h2AAAAAAAA; wci_wslv_sFlagReg = 1'h0; wci_wslv_sThreadBusy_d = 1'h0; - wdReg = 32'hAAAAAAAA; + wdReg_0 = 32'hAAAAAAAA; wdReg_1 = 32'hAAAAAAAA; wdReg_2 = 32'hAAAAAAAA; wdReg_3 = 32'hAAAAAAAA; @@ -2861,7 +2884,7 @@ module mkDramServer_v6(CLK_sys0_clk, wmemi_isReset_isInReset = 1'h0; wmemi_operateD = 1'h0; wmemi_peerIsReady = 1'h0; - wmemi_respF_c_r = 2'h2; + wmemi_respF_cntr_r = 2'h2; wmemi_respF_q_0 = 131'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; wmemi_respF_q_1 = 131'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; wmemi_statusR = 8'hAA; @@ -2879,25 +2902,25 @@ module mkDramServer_v6(CLK_sys0_clk, if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_start) begin - v__h3715 = $time; + v__h3583 = $time; #0; end if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_start) $display("[%0d]: %m: WCI ControlOp: Starting-transition edge:%x from:%x", - v__h3715, + v__h3583, wci_wslv_reqF$D_OUT[36:34], wci_wslv_cState); if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_ctrl_IsO) begin - v__h19648 = $time; + v__h19271 = $time; #0; end if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_ctrl_IsO) $display("[%0d]: %m: Starting DramWorker dramCtrl:%0x", - v__h19648, + v__h19271, dramCtrl); if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_advance_response && WILL_FIRE_RL_wci_ctrl_OrE) @@ -2947,25 +2970,25 @@ module mkDramServer_v6(CLK_sys0_clk, if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge) begin - v__h4034 = $time; + v__h3902 = $time; #0; end if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge) $display("[%0d]: %m: WCI ControlOp: ILLEGAL-EDGE Completed-transition edge:%x from:%x", - v__h4034, + v__h3902, wci_wslv_cEdge, wci_wslv_cState); if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && !wci_wslv_illegalEdge) begin - v__h3890 = $time; + v__h3758 = $time; #0; end if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && !wci_wslv_illegalEdge) $display("[%0d]: %m: WCI ControlOp: Completed-transition edge:%x from:%x to:%x", - v__h3890, + v__h3758, wci_wslv_cEdge, wci_wslv_cState, wci_wslv_nState); diff --git a/rtl/mkFMC150.v b/rtl/mkFMC150.v index 38288c95..54849687 100644 --- a/rtl/mkFMC150.v +++ b/rtl/mkFMC150.v @@ -1,7 +1,7 @@ // -// Generated by Bluespec Compiler, version 2012.09.beta1 (build 29570, 2012-09.11) +// Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Wed Nov 28 10:32:06 EST 2012 +// On Fri Jun 21 16:57:27 EDT 2013 // // // Ports: @@ -504,10 +504,10 @@ module mkFMC150(CLK_flp_clk, wire [1 : 0] wci_wslv_reqF_countReg$D_IN; wire wci_wslv_reqF_countReg$EN; - // register wci_wslv_respF_c_r - reg [1 : 0] wci_wslv_respF_c_r; - wire [1 : 0] wci_wslv_respF_c_r$D_IN; - wire wci_wslv_respF_c_r$EN; + // register wci_wslv_respF_cntr_r + reg [1 : 0] wci_wslv_respF_cntr_r; + wire [1 : 0] wci_wslv_respF_cntr_r$D_IN; + wire wci_wslv_respF_cntr_r$EN; // register wci_wslv_respF_q_0 reg [33 : 0] wci_wslv_respF_q_0; @@ -674,10 +674,9 @@ module mkFMC150(CLK_flp_clk, wire [5 : 0] MUX_spiCDC_rPos$write_1__VAL_1, MUX_spiCDC_rPos$write_1__VAL_2; wire [4 : 0] MUX_spiCDC_dPos$write_1__VAL_1; wire [2 : 0] MUX_spiDAC_dPos$write_1__VAL_1, MUX_spiDAC_iPos$write_1__VAL_1; - wire [1 : 0] MUX_wci_wslv_respF_c_r$write_1__VAL_1, - MUX_wci_wslv_respF_c_r$write_1__VAL_2; + wire [1 : 0] MUX_wci_wslv_respF_cntr_r$write_1__VAL_2; wire MUX_spiCDC_doResp_1$wset_1__SEL_1, - MUX_spiCDC_rcv_d$write_1__SEL_1, + MUX_spiCDC_rcv_d$write_1__SEL_2, MUX_spiCDC_reqS$write_1__SEL_1, MUX_spiDAC_doResp_1$wset_1__SEL_1, MUX_spiDAC_doResp_1$wset_1__SEL_2, @@ -687,65 +686,70 @@ module mkFMC150(CLK_flp_clk, MUX_splitReadInFlight$write_1__SEL_1, MUX_wci_wslv_illegalEdge$write_1__SEL_1, MUX_wci_wslv_illegalEdge$write_1__VAL_1, + MUX_wci_wslv_respF_q_0$write_1__SEL_1, MUX_wci_wslv_respF_q_0$write_1__SEL_2, + MUX_wci_wslv_respF_q_1$write_1__SEL_1, MUX_wci_wslv_respF_q_1$write_1__SEL_2, MUX_wci_wslv_respF_x_wire$wset_1__SEL_1, MUX_wci_wslv_respF_x_wire$wset_1__SEL_3, MUX_wci_wslv_respF_x_wire$wset_1__SEL_4; // remaining internal signals - reg [63 : 0] v__h3694, v__h3869, v__h4013, v__h42053, v__h42815; - reg [31 : 0] rdat__h42799; - reg CASE_31_MINUS_spiCDC_dPos_31_28_31_MINUS_spiCD_ETC__q4, - CASE_31_MINUS_spiCDC_dPos_31_28_x3624_0_spiCDC_ETC__q5, - CASE_spiDAC_iPos_spiDAC_reqS_BIT_8_1_spiDAC_re_ETC__q3, - IF_spiDAC_iPos_47_EQ_4_54_OR_spiDAC_iPos_47_EQ_ETC___d364; - wire [31 : 0] IF_fcCdc_grayCounter_rsCounter_15_BIT_0_22_OR__ETC___d776, - IF_fcCdc_grayCounter_rsCounter_15_BIT_0_22_XOR_ETC___d777, - rdat__h42573; + reg [63 : 0] v__h3562, v__h3737, v__h3881, v__h42276, v__h43038; + reg [31 : 0] rdat__h43022; + reg CASE_31_MINUS_spiCDC_dPos_29_30_0_spiCDC_reqS__ETC__q5, + CASE_31_MINUS_spiCDC_dPos_29_30_4_spiCDC_reqS__ETC__q4, + CASE_spiDAC_iPos_1_spiDAC_reqS_BIT_9_2_spiDAC__ETC__q2, + IF_spiDAC_iPos_45_EQ_4_52_OR_spiDAC_iPos_45_EQ_ETC___d362; + wire [31 : 0] IF_fcCdc_grayCounter_rsCounter_13_BIT_0_20_OR__ETC___d489, + IF_fcCdc_grayCounter_rsCounter_13_BIT_0_20_XOR_ETC___d490, + rdat__h42796; wire [27 : 0] spiCDC_reqS_BITS_27_TO_0__q1; - wire [17 : 0] x__h36416, y__h37821; - wire [7 : 0] spiDAC_reqS_BITS_7_TO_0__q2; - wire [4 : 0] _31_MINUS_spiCDC_dPos_31___d728, x__h13667; - wire IF_spiDAC_iPos_47_EQ_7_48_THEN_NOT_spiDAC_reqF_ETC___d367, - IF_wci_wslv_reqF_i_notEmpty__4_AND_wci_wslv_re_ETC___d770, - NOT_spiDAC_iPos_47_EQ_0_61_62_OR_NOT_spiDAC_re_ETC___d363, + wire [17 : 0] x__h36639, y__h38044; + wire [7 : 0] spiDAC_reqS_BITS_7_TO_0__q3; + wire [4 : 0] _31_MINUS_spiCDC_dPos_29___d230, x__h13601; + wire [1 : 0] wci_wslv_respF_cntr_r_8_MINUS_1___d27; + wire IF_spiDAC_iPos_45_EQ_7_46_THEN_NOT_spiDAC_reqF_ETC___d365, + IF_wci_wslv_reqF_i_notEmpty__2_AND_wci_wslv_re_ETC___d590, + NOT_spiDAC_iPos_45_EQ_0_59_60_OR_NOT_spiDAC_re_ETC___d361, + _dfoo1, + _dfoo3, _dor1spiCDC_reqF_enq_pw$EN_wset, _dor1spiDAC_reqF_enq_pw$EN_wset, - fcCdc_grayCounter_rdCounter_13_BIT_17_14_XOR_f_ETC___d657, - fcCdc_grayCounter_rdCounter_13_BIT_17_14_XOR_f_ETC___d658, - fcCdc_grayCounter_rdCounter_13_BIT_17_14_XOR_f_ETC___d659, - fcCdc_grayCounter_rdCounter_13_BIT_17_14_XOR_f_ETC___d660, - fcCdc_grayCounter_rdCounter_13_BIT_17_14_XOR_f_ETC___d661, - fcCdc_grayCounter_rdCounter_13_BIT_17_14_XOR_f_ETC___d662, - fcCdc_grayCounter_rdCounter_13_BIT_17_14_XOR_f_ETC___d663, - fcCdc_grayCounter_rdCounter_13_BIT_17_14_XOR_f_ETC___d664, - fcCdc_grayCounter_rdCounter_13_BIT_17_14_XOR_f_ETC___d665, - fcCdc_grayCounter_rdCounter_13_BIT_17_14_XOR_f_ETC___d666, - fcCdc_grayCounter_rdCounter_13_BIT_17_14_XOR_f_ETC___d667, - fcCdc_grayCounter_rdCounter_13_BIT_17_14_XOR_f_ETC___d668, - fcCdc_grayCounter_rdCounter_13_BIT_17_14_XOR_f_ETC___d672, - fcCdc_grayCounter_rdCounter_13_BIT_17_14_XOR_f_ETC___d674, - fcCdc_grayCounter_rdCounter_13_BIT_17_14_XOR_f_ETC___d675, - fcCdc_grayCounter_rdCounter_13_BIT_17_14_XOR_f_ETC___d676, - fcCdc_grayCounter_rsCounter_15_BIT_0_22_XOR_fc_ETC___d729, - x__h13624, - z__h36436, - z__h36443, - z__h36450, - z__h36457, - z__h36464, - z__h36471, - z__h36478, - z__h36485, - z__h36492, - z__h36499, - z__h36506, - z__h36513, - z__h36520, - z__h36527, - z__h36534, - z__h36541; + fcCdc_grayCounter_rdCounter_11_BIT_17_12_XOR_f_ETC___d514, + fcCdc_grayCounter_rdCounter_11_BIT_17_12_XOR_f_ETC___d517, + fcCdc_grayCounter_rdCounter_11_BIT_17_12_XOR_f_ETC___d519, + fcCdc_grayCounter_rdCounter_11_BIT_17_12_XOR_f_ETC___d522, + fcCdc_grayCounter_rdCounter_11_BIT_17_12_XOR_f_ETC___d524, + fcCdc_grayCounter_rdCounter_11_BIT_17_12_XOR_f_ETC___d527, + fcCdc_grayCounter_rdCounter_11_BIT_17_12_XOR_f_ETC___d529, + fcCdc_grayCounter_rdCounter_11_BIT_17_12_XOR_f_ETC___d532, + fcCdc_grayCounter_rdCounter_11_BIT_17_12_XOR_f_ETC___d534, + fcCdc_grayCounter_rdCounter_11_BIT_17_12_XOR_f_ETC___d537, + fcCdc_grayCounter_rdCounter_11_BIT_17_12_XOR_f_ETC___d539, + fcCdc_grayCounter_rdCounter_11_BIT_17_12_XOR_f_ETC___d542, + fcCdc_grayCounter_rdCounter_11_BIT_17_12_XOR_f_ETC___d544, + fcCdc_grayCounter_rdCounter_11_BIT_17_12_XOR_f_ETC___d547, + fcCdc_grayCounter_rdCounter_11_BIT_17_12_XOR_f_ETC___d549, + fcCdc_grayCounter_rdCounter_11_BIT_17_12_XOR_f_ETC___d552, + fcCdc_grayCounter_rsCounter_13_BIT_0_20_XOR_fc_ETC___d454, + x__h13558, + z__h36659, + z__h36666, + z__h36673, + z__h36680, + z__h36687, + z__h36694, + z__h36701, + z__h36708, + z__h36715, + z__h36722, + z__h36729, + z__h36736, + z__h36743, + z__h36750, + z__h36757, + z__h36764; // oscillator and gates for output clock CLK_padsCDC_sclk assign CLK_padsCDC_sclk = spiCDC_cd$CLK_OUT ; @@ -961,22 +965,22 @@ module mkFMC150(CLK_flp_clk, // rule RL_spi32_response assign CAN_FIRE_RL_spi32_response = - wci_wslv_respF_c_r != 2'd2 && + wci_wslv_respF_cntr_r != 2'd2 && spiCDC_respF_head_wrapped != spiCDC_respF_tail_wrapped && !spiCDC_respF_dInReset$VAL && spiCDC_cd$PREEDGE ; // rule RL_spi5_response assign CAN_FIRE_RL_spi5_response = - wci_wslv_respF_c_r != 2'd2 && + wci_wslv_respF_cntr_r != 2'd2 && spiDAC_respF_head_wrapped != spiDAC_respF_tail_wrapped && !spiDAC_respF_dInReset$VAL && spiDAC_cd$PREEDGE ; // rule RL_wci_cfwr assign WILL_FIRE_RL_wci_cfwr = - wci_wslv_respF_c_r != 2'd2 && wci_wslv_reqF$EMPTY_N && - IF_wci_wslv_reqF_i_notEmpty__4_AND_wci_wslv_re_ETC___d770 && + wci_wslv_respF_cntr_r != 2'd2 && wci_wslv_reqF$EMPTY_N && + IF_wci_wslv_reqF_i_notEmpty__2_AND_wci_wslv_re_ETC___d590 && wci_wslv_wci_cfwr_pw$whas && !WILL_FIRE_RL_wci_wslv_ctl_op_start && !WILL_FIRE_RL_wci_wslv_ctl_op_complete ; @@ -984,10 +988,10 @@ module mkFMC150(CLK_flp_clk, // rule RL_wci_cfrd assign CAN_FIRE_RL_wci_cfrd = wci_wslv_reqF$EMPTY_N && - IF_wci_wslv_reqF_i_notEmpty__4_AND_wci_wslv_re_ETC___d770 && + IF_wci_wslv_reqF_i_notEmpty__2_AND_wci_wslv_re_ETC___d590 && (wci_wslv_reqF$D_OUT[43:42] == 2'b0 || wci_wslv_reqF$D_OUT[43:42] == 2'b01 || - wci_wslv_respF_c_r != 2'd2) && + wci_wslv_respF_cntr_r != 2'd2) && wci_wslv_wci_cfrd_pw$whas ; assign WILL_FIRE_RL_wci_cfrd = CAN_FIRE_RL_wci_cfrd && !WILL_FIRE_RL_wci_wslv_ctl_op_start && @@ -1021,27 +1025,22 @@ module mkFMC150(CLK_flp_clk, // rule RL_wci_wslv_ctl_op_complete assign WILL_FIRE_RL_wci_wslv_ctl_op_complete = - wci_wslv_respF_c_r != 2'd2 && wci_wslv_ctlOpActive && + wci_wslv_respF_cntr_r != 2'd2 && wci_wslv_ctlOpActive && wci_wslv_ctlAckReg ; // rule RL_wci_wslv_respF_incCtr assign WILL_FIRE_RL_wci_wslv_respF_incCtr = - ((wci_wslv_respF_c_r == 2'd0) ? - wci_wslv_respF_x_wire$whas : - wci_wslv_respF_c_r != 2'd1 || wci_wslv_respF_x_wire$whas) && - wci_wslv_respF_enqueueing$whas && - !(wci_wslv_respF_c_r != 2'd0) ; + wci_wslv_respF_x_wire$whas && wci_wslv_respF_enqueueing$whas && + !(wci_wslv_respF_cntr_r != 2'd0) ; // rule RL_wci_wslv_respF_decCtr assign WILL_FIRE_RL_wci_wslv_respF_decCtr = - wci_wslv_respF_c_r != 2'd0 && !wci_wslv_respF_enqueueing$whas ; + wci_wslv_respF_cntr_r != 2'd0 && + !wci_wslv_respF_enqueueing$whas ; // rule RL_wci_wslv_respF_both assign WILL_FIRE_RL_wci_wslv_respF_both = - ((wci_wslv_respF_c_r == 2'd1) ? - wci_wslv_respF_x_wire$whas : - wci_wslv_respF_c_r != 2'd2 || wci_wslv_respF_x_wire$whas) && - wci_wslv_respF_c_r != 2'd0 && + wci_wslv_respF_x_wire$whas && wci_wslv_respF_cntr_r != 2'd0 && wci_wslv_respF_enqueueing$whas ; // rule RL_spiCDC_start_cs @@ -1078,7 +1077,7 @@ module mkFMC150(CLK_flp_clk, // rule RL_spiCDC_reqF_deq_update_head assign WILL_FIRE_RL_spiCDC_reqF_deq_update_head = - !spiCDC_reqF_dInReset$VAL && MUX_spiCDC_rcv_d$write_1__SEL_1 ; + !spiCDC_reqF_dInReset$VAL && MUX_spiCDC_rcv_d$write_1__SEL_2 ; // rule RL_spiCDC_respF_enq_update_tail assign WILL_FIRE_RL_spiCDC_respF_enq_update_tail = @@ -1095,7 +1094,7 @@ module mkFMC150(CLK_flp_clk, // rule RL_spiDAC_send_i assign WILL_FIRE_RL_spiDAC_send_i = - IF_spiDAC_iPos_47_EQ_7_48_THEN_NOT_spiDAC_reqF_ETC___d367 && + IF_spiDAC_iPos_45_EQ_7_46_THEN_NOT_spiDAC_reqF_ETC___d365 && spiDAC_xmt_i && !spiDAC_xcv_d && !spiDAC_doResp ; @@ -1128,7 +1127,7 @@ module mkFMC150(CLK_flp_clk, // inputs to muxes for submodule ports assign MUX_spiCDC_doResp_1$wset_1__SEL_1 = WILL_FIRE_RL_spiCDC_recv_d && spiCDC_rPos == 6'd0 ; - assign MUX_spiCDC_rcv_d$write_1__SEL_1 = + assign MUX_spiCDC_rcv_d$write_1__SEL_2 = WILL_FIRE_RL_spiCDC_send_d && spiCDC_dPos == 5'd0 ; assign MUX_spiCDC_reqS$write_1__SEL_1 = WILL_FIRE_RL_wci_cfwr && wci_wslv_reqF$D_OUT[43:42] == 2'b0 ; @@ -1157,12 +1156,16 @@ module mkFMC150(CLK_flp_clk, wci_wslv_reqF$D_OUT[36:34] == 3'd5 || wci_wslv_reqF$D_OUT[36:34] == 3'd6 || wci_wslv_reqF$D_OUT[36:34] == 3'd7) ; + assign MUX_wci_wslv_respF_q_0$write_1__SEL_1 = + WILL_FIRE_RL_wci_wslv_respF_both && _dfoo3 ; assign MUX_wci_wslv_respF_q_0$write_1__SEL_2 = WILL_FIRE_RL_wci_wslv_respF_incCtr && - wci_wslv_respF_c_r == 2'd0 ; + wci_wslv_respF_cntr_r == 2'd0 ; + assign MUX_wci_wslv_respF_q_1$write_1__SEL_1 = + WILL_FIRE_RL_wci_wslv_respF_both && _dfoo1 ; assign MUX_wci_wslv_respF_q_1$write_1__SEL_2 = WILL_FIRE_RL_wci_wslv_respF_incCtr && - wci_wslv_respF_c_r == 2'd1 ; + wci_wslv_respF_cntr_r == 2'd1 ; assign MUX_wci_wslv_respF_x_wire$wset_1__SEL_1 = WILL_FIRE_RL_wci_cfrd && wci_wslv_reqF$D_OUT[43:42] != 2'b0 && wci_wslv_reqF$D_OUT[43:42] != 2'b01 ; @@ -1173,9 +1176,9 @@ module mkFMC150(CLK_flp_clk, CAN_FIRE_RL_spi5_response && !WILL_FIRE_RL_wci_wslv_ctl_op_complete ; assign MUX_fcCdc_grayCounter_rsCounter$write_1__VAL_1 = - (~fcCdc_grayCounter_rsCounter[IF_fcCdc_grayCounter_rsCounter_15_BIT_0_22_XOR_ETC___d777[4:0]]) ? - fcCdc_grayCounter_rsCounter | x__h36416 : - fcCdc_grayCounter_rsCounter & y__h37821 ; + (~fcCdc_grayCounter_rsCounter[IF_fcCdc_grayCounter_rsCounter_13_BIT_0_20_XOR_ETC___d490[4:0]]) ? + fcCdc_grayCounter_rsCounter | x__h36639 : + fcCdc_grayCounter_rsCounter & y__h38044 ; assign MUX_oneKHz_value$write_1__VAL_1 = (oneKHz_value == 18'd124999) ? 18'd0 : oneKHz_value + 18'd1 ; assign MUX_spiCDC_dPos$write_1__VAL_1 = @@ -1199,17 +1202,17 @@ module mkFMC150(CLK_flp_clk, (spiDAC_iPos == 3'd7) ? spiDAC_reqS[13] : spiDAC_iPos != 3'd6 && spiDAC_iPos != 3'd5 && - CASE_spiDAC_iPos_spiDAC_reqS_BIT_8_1_spiDAC_re_ETC__q3 ; + CASE_spiDAC_iPos_1_spiDAC_reqS_BIT_9_2_spiDAC__ETC__q2 ; assign MUX_spiDAC_sdoR$write_1__VAL_2 = - spiDAC_reqS_BITS_7_TO_0__q2[spiDAC_dPos] ; + spiDAC_reqS_BITS_7_TO_0__q3[spiDAC_dPos] ; assign MUX_wci_wslv_illegalEdge$write_1__VAL_1 = wci_wslv_reqF$D_OUT[36:34] != 3'd4 && wci_wslv_reqF$D_OUT[36:34] != 3'd5 && wci_wslv_reqF$D_OUT[36:34] != 3'd6 ; - assign MUX_wci_wslv_respF_c_r$write_1__VAL_1 = wci_wslv_respF_c_r + 2'd1 ; - assign MUX_wci_wslv_respF_c_r$write_1__VAL_2 = wci_wslv_respF_c_r - 2'd1 ; + assign MUX_wci_wslv_respF_cntr_r$write_1__VAL_2 = + wci_wslv_respF_cntr_r + 2'd1 ; assign MUX_wci_wslv_respF_q_0$write_1__VAL_1 = - (wci_wslv_respF_c_r == 2'd1) ? + (wci_wslv_respF_cntr_r == 2'd1) ? MUX_wci_wslv_respF_q_0$write_1__VAL_2 : wci_wslv_respF_q_1 ; always@(MUX_wci_wslv_respF_x_wire$wset_1__SEL_1 or @@ -1241,10 +1244,10 @@ module mkFMC150(CLK_flp_clk, endcase end assign MUX_wci_wslv_respF_q_1$write_1__VAL_1 = - (wci_wslv_respF_c_r == 2'd2) ? + (wci_wslv_respF_cntr_r == 2'd2) ? MUX_wci_wslv_respF_q_0$write_1__VAL_2 : 34'h0AAAAAAAA ; - assign MUX_wci_wslv_respF_x_wire$wset_1__VAL_1 = { 2'd1, rdat__h42799 } ; + assign MUX_wci_wslv_respF_x_wire$wset_1__VAL_1 = { 2'd1, rdat__h43022 } ; assign MUX_wci_wslv_respF_x_wire$wset_1__VAL_2 = wci_wslv_illegalEdge ? 34'h3C0DE4202 : 34'h1C0DE4201 ; assign MUX_wci_wslv_respF_x_wire$wset_1__VAL_3 = { 6'd16, spiCDC_respS } ; @@ -1322,7 +1325,7 @@ module mkFMC150(CLK_flp_clk, MUX_wci_wslv_respF_x_wire$wset_1__SEL_3 || WILL_FIRE_RL_wci_cfwr || WILL_FIRE_RL_wci_wslv_ctl_op_complete ; - assign wci_wslv_respF_dequeueing$whas = wci_wslv_respF_c_r != 2'd0 ; + assign wci_wslv_respF_dequeueing$whas = wci_wslv_respF_cntr_r != 2'd0 ; assign wci_wslv_sThreadBusy_pw$whas = 1'b0 ; assign wci_wslv_wci_cfwr_pw$whas = wci_wslv_reqF$EMPTY_N && wci_wslv_reqF$D_OUT[68] && @@ -1336,7 +1339,7 @@ module mkFMC150(CLK_flp_clk, assign spiCDC_reqF_enq_pw$whas = _dor1spiCDC_reqF_enq_pw$EN_wset && wci_wslv_reqF$D_OUT[43:42] == 2'b0 ; - assign spiCDC_reqF_deq_pw$whas = MUX_spiCDC_rcv_d$write_1__SEL_1 ; + assign spiCDC_reqF_deq_pw$whas = MUX_spiCDC_rcv_d$write_1__SEL_2 ; assign spiCDC_reqF_sClear_pw$whas = 1'b0 ; assign spiCDC_reqF_dClear_pw$whas = 1'b0 ; assign spiCDC_reqF_deq_happened$whas = 1'b0 ; @@ -1369,23 +1372,23 @@ module mkFMC150(CLK_flp_clk, // register fcCdc_countNow assign fcCdc_countNow$D_IN = { fcCdc_grayCounter_rdCounter[17], - fcCdc_grayCounter_rdCounter_13_BIT_17_14_XOR_f_ETC___d657, - fcCdc_grayCounter_rdCounter_13_BIT_17_14_XOR_f_ETC___d672, - fcCdc_grayCounter_rdCounter_13_BIT_17_14_XOR_f_ETC___d660, - fcCdc_grayCounter_rdCounter_13_BIT_17_14_XOR_f_ETC___d658, - fcCdc_grayCounter_rdCounter_13_BIT_17_14_XOR_f_ETC___d674, - fcCdc_grayCounter_rdCounter_13_BIT_17_14_XOR_f_ETC___d659, - fcCdc_grayCounter_rdCounter_13_BIT_17_14_XOR_f_ETC___d664, - fcCdc_grayCounter_rdCounter_13_BIT_17_14_XOR_f_ETC___d663, - fcCdc_grayCounter_rdCounter_13_BIT_17_14_XOR_f_ETC___d661, - fcCdc_grayCounter_rdCounter_13_BIT_17_14_XOR_f_ETC___d675, - fcCdc_grayCounter_rdCounter_13_BIT_17_14_XOR_f_ETC___d662, - fcCdc_grayCounter_rdCounter_13_BIT_17_14_XOR_f_ETC___d668, - fcCdc_grayCounter_rdCounter_13_BIT_17_14_XOR_f_ETC___d676, - fcCdc_grayCounter_rdCounter_13_BIT_17_14_XOR_f_ETC___d665, - fcCdc_grayCounter_rdCounter_13_BIT_17_14_XOR_f_ETC___d666, - fcCdc_grayCounter_rdCounter_13_BIT_17_14_XOR_f_ETC___d667, - fcCdc_grayCounter_rdCounter_13_BIT_17_14_XOR_f_ETC___d667 ^ + fcCdc_grayCounter_rdCounter_11_BIT_17_12_XOR_f_ETC___d514, + fcCdc_grayCounter_rdCounter_11_BIT_17_12_XOR_f_ETC___d517, + fcCdc_grayCounter_rdCounter_11_BIT_17_12_XOR_f_ETC___d519, + fcCdc_grayCounter_rdCounter_11_BIT_17_12_XOR_f_ETC___d522, + fcCdc_grayCounter_rdCounter_11_BIT_17_12_XOR_f_ETC___d524, + fcCdc_grayCounter_rdCounter_11_BIT_17_12_XOR_f_ETC___d527, + fcCdc_grayCounter_rdCounter_11_BIT_17_12_XOR_f_ETC___d529, + fcCdc_grayCounter_rdCounter_11_BIT_17_12_XOR_f_ETC___d532, + fcCdc_grayCounter_rdCounter_11_BIT_17_12_XOR_f_ETC___d534, + fcCdc_grayCounter_rdCounter_11_BIT_17_12_XOR_f_ETC___d537, + fcCdc_grayCounter_rdCounter_11_BIT_17_12_XOR_f_ETC___d539, + fcCdc_grayCounter_rdCounter_11_BIT_17_12_XOR_f_ETC___d542, + fcCdc_grayCounter_rdCounter_11_BIT_17_12_XOR_f_ETC___d544, + fcCdc_grayCounter_rdCounter_11_BIT_17_12_XOR_f_ETC___d547, + fcCdc_grayCounter_rdCounter_11_BIT_17_12_XOR_f_ETC___d549, + fcCdc_grayCounter_rdCounter_11_BIT_17_12_XOR_f_ETC___d552, + fcCdc_grayCounter_rdCounter_11_BIT_17_12_XOR_f_ETC___d552 ^ fcCdc_grayCounter_rdCounter[0] } ; assign fcCdc_countNow$EN = fcCdc_pulseAction ; @@ -1457,10 +1460,10 @@ module mkFMC150(CLK_flp_clk, // register spiCDC_rcv_d assign spiCDC_rcv_d$D_IN = - MUX_spiCDC_rcv_d$write_1__SEL_1 && spiCDC_reqS[32] ; + !MUX_spiCDC_doResp_1$wset_1__SEL_1 && spiCDC_reqS[32] ; assign spiCDC_rcv_d$EN = - WILL_FIRE_RL_spiCDC_send_d && spiCDC_dPos == 5'd0 || - WILL_FIRE_RL_spiCDC_recv_d && spiCDC_rPos == 6'd0 ; + WILL_FIRE_RL_spiCDC_recv_d && spiCDC_rPos == 6'd0 || + WILL_FIRE_RL_spiCDC_send_d && spiCDC_dPos == 5'd0 ; // register spiCDC_reqF_head_wrapped assign spiCDC_reqF_head_wrapped$D_IN = @@ -1514,16 +1517,15 @@ module mkFMC150(CLK_flp_clk, // register spiCDC_sdoR assign spiCDC_sdoR$D_IN = spiCDC_reqS[32] ? - _31_MINUS_spiCDC_dPos_31___d728 != 5'd0 && - (_31_MINUS_spiCDC_dPos_31___d728 == 5'd1 || - _31_MINUS_spiCDC_dPos_31___d728 == 5'd2 || - _31_MINUS_spiCDC_dPos_31___d728 == 5'd3 || - CASE_31_MINUS_spiCDC_dPos_31_28_31_MINUS_spiCD_ETC__q4) : - CASE_31_MINUS_spiCDC_dPos_31_28_x3624_0_spiCDC_ETC__q5 ; + _31_MINUS_spiCDC_dPos_29___d230 == 5'd1 || + _31_MINUS_spiCDC_dPos_29___d230 == 5'd2 || + _31_MINUS_spiCDC_dPos_29___d230 == 5'd3 || + CASE_31_MINUS_spiCDC_dPos_29_30_4_spiCDC_reqS__ETC__q4 : + CASE_31_MINUS_spiCDC_dPos_29_30_0_spiCDC_reqS__ETC__q5 ; assign spiCDC_sdoR$EN = WILL_FIRE_RL_spiCDC_send_d ; // register spiCDC_xmt_d - assign spiCDC_xmt_d$D_IN = !MUX_spiCDC_rcv_d$write_1__SEL_1 ; + assign spiCDC_xmt_d$D_IN = !MUX_spiCDC_rcv_d$write_1__SEL_2 ; assign spiCDC_xmt_d$EN = WILL_FIRE_RL_spiCDC_send_d && spiCDC_dPos == 5'd0 || WILL_FIRE_RL_spiCDC_start_cs ; @@ -1698,24 +1700,24 @@ module mkFMC150(CLK_flp_clk, (wci_wslv_wciReq$wget[71:69] != 3'd0) != wci_wslv_reqF_r_deq$whas ; - // register wci_wslv_respF_c_r - assign wci_wslv_respF_c_r$D_IN = - WILL_FIRE_RL_wci_wslv_respF_incCtr ? - MUX_wci_wslv_respF_c_r$write_1__VAL_1 : - MUX_wci_wslv_respF_c_r$write_1__VAL_2 ; - assign wci_wslv_respF_c_r$EN = - WILL_FIRE_RL_wci_wslv_respF_incCtr || - WILL_FIRE_RL_wci_wslv_respF_decCtr ; + // register wci_wslv_respF_cntr_r + assign wci_wslv_respF_cntr_r$D_IN = + WILL_FIRE_RL_wci_wslv_respF_decCtr ? + wci_wslv_respF_cntr_r_8_MINUS_1___d27 : + MUX_wci_wslv_respF_cntr_r$write_1__VAL_2 ; + assign wci_wslv_respF_cntr_r$EN = + WILL_FIRE_RL_wci_wslv_respF_decCtr || + WILL_FIRE_RL_wci_wslv_respF_incCtr ; // register wci_wslv_respF_q_0 - always@(WILL_FIRE_RL_wci_wslv_respF_both or + always@(MUX_wci_wslv_respF_q_0$write_1__SEL_1 or MUX_wci_wslv_respF_q_0$write_1__VAL_1 or MUX_wci_wslv_respF_q_0$write_1__SEL_2 or MUX_wci_wslv_respF_q_0$write_1__VAL_2 or WILL_FIRE_RL_wci_wslv_respF_decCtr or wci_wslv_respF_q_1) begin case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_wci_wslv_respF_both: + MUX_wci_wslv_respF_q_0$write_1__SEL_1: wci_wslv_respF_q_0$D_IN = MUX_wci_wslv_respF_q_0$write_1__VAL_1; MUX_wci_wslv_respF_q_0$write_1__SEL_2: wci_wslv_respF_q_0$D_IN = MUX_wci_wslv_respF_q_0$write_1__VAL_2; @@ -1726,20 +1728,20 @@ module mkFMC150(CLK_flp_clk, endcase end assign wci_wslv_respF_q_0$EN = - WILL_FIRE_RL_wci_wslv_respF_both || + WILL_FIRE_RL_wci_wslv_respF_both && _dfoo3 || WILL_FIRE_RL_wci_wslv_respF_incCtr && - wci_wslv_respF_c_r == 2'd0 || + wci_wslv_respF_cntr_r == 2'd0 || WILL_FIRE_RL_wci_wslv_respF_decCtr ; // register wci_wslv_respF_q_1 - always@(WILL_FIRE_RL_wci_wslv_respF_both or + always@(MUX_wci_wslv_respF_q_1$write_1__SEL_1 or MUX_wci_wslv_respF_q_1$write_1__VAL_1 or MUX_wci_wslv_respF_q_1$write_1__SEL_2 or MUX_wci_wslv_respF_q_0$write_1__VAL_2 or WILL_FIRE_RL_wci_wslv_respF_decCtr) begin case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_wci_wslv_respF_both: + MUX_wci_wslv_respF_q_1$write_1__SEL_1: wci_wslv_respF_q_1$D_IN = MUX_wci_wslv_respF_q_1$write_1__VAL_1; MUX_wci_wslv_respF_q_1$write_1__SEL_2: wci_wslv_respF_q_1$D_IN = MUX_wci_wslv_respF_q_0$write_1__VAL_2; @@ -1750,9 +1752,9 @@ module mkFMC150(CLK_flp_clk, endcase end assign wci_wslv_respF_q_1$EN = - WILL_FIRE_RL_wci_wslv_respF_both || + WILL_FIRE_RL_wci_wslv_respF_both && _dfoo1 || WILL_FIRE_RL_wci_wslv_respF_incCtr && - wci_wslv_respF_c_r == 2'd1 || + wci_wslv_respF_cntr_r == 2'd1 || WILL_FIRE_RL_wci_wslv_respF_decCtr ; // register wci_wslv_sFlagReg @@ -1770,7 +1772,7 @@ module mkFMC150(CLK_flp_clk, assign wci_wslv_reqF$CLR = 1'b0 ; // remaining internal signals - assign IF_fcCdc_grayCounter_rsCounter_15_BIT_0_22_OR__ETC___d776 = + assign IF_fcCdc_grayCounter_rsCounter_13_BIT_0_20_OR__ETC___d489 = (fcCdc_grayCounter_rsCounter[0] || fcCdc_grayCounter_rsCounter[1] || fcCdc_grayCounter_rsCounter[2] || @@ -1826,17 +1828,17 @@ module mkFMC150(CLK_flp_clk, 32'd18 : 32'd19)))))))))))))))))) : 32'd17 ; - assign IF_fcCdc_grayCounter_rsCounter_15_BIT_0_22_XOR_ETC___d777 = - fcCdc_grayCounter_rsCounter_15_BIT_0_22_XOR_fc_ETC___d729 ? - IF_fcCdc_grayCounter_rsCounter_15_BIT_0_22_OR__ETC___d776 : + assign IF_fcCdc_grayCounter_rsCounter_13_BIT_0_20_XOR_ETC___d490 = + fcCdc_grayCounter_rsCounter_13_BIT_0_20_XOR_fc_ETC___d454 ? + IF_fcCdc_grayCounter_rsCounter_13_BIT_0_20_OR__ETC___d489 : 32'd0 ; - assign IF_spiDAC_iPos_47_EQ_7_48_THEN_NOT_spiDAC_reqF_ETC___d367 = + assign IF_spiDAC_iPos_45_EQ_7_46_THEN_NOT_spiDAC_reqF_ETC___d365 = (spiDAC_iPos == 3'd7) ? spiDAC_reqF_head_wrapped != spiDAC_reqF_tail_wrapped && !spiDAC_reqF_dInReset$VAL : spiDAC_iPos == 3'd6 || spiDAC_iPos == 3'd5 || - IF_spiDAC_iPos_47_EQ_4_54_OR_spiDAC_iPos_47_EQ_ETC___d364 ; - assign IF_wci_wslv_reqF_i_notEmpty__4_AND_wci_wslv_re_ETC___d770 = + IF_spiDAC_iPos_45_EQ_4_52_OR_spiDAC_iPos_45_EQ_ETC___d362 ; + assign IF_wci_wslv_reqF_i_notEmpty__2_AND_wci_wslv_re_ETC___d590 = (wci_wslv_reqF$EMPTY_N && wci_wslv_reqF$D_OUT[43:42] == 2'b0) ? spiCDC_reqF_head_wrapped == spiCDC_reqF_tail_wrapped && !spiCDC_reqF_sInReset$VAL && @@ -1846,165 +1848,173 @@ module mkFMC150(CLK_flp_clk, spiDAC_reqF_head_wrapped == spiDAC_reqF_tail_wrapped && !spiDAC_reqF_sInReset$VAL && spiDAC_cd$PREEDGE ; - assign NOT_spiDAC_iPos_47_EQ_0_61_62_OR_NOT_spiDAC_re_ETC___d363 = + assign NOT_spiDAC_iPos_45_EQ_0_59_60_OR_NOT_spiDAC_re_ETC___d361 = spiDAC_iPos != 3'd0 || spiDAC_reqF_head_wrapped != spiDAC_reqF_tail_wrapped && !spiDAC_reqF_dInReset$VAL ; - assign _31_MINUS_spiCDC_dPos_31___d728 = 5'd31 - spiCDC_dPos ; + assign _31_MINUS_spiCDC_dPos_29___d230 = 5'd31 - spiCDC_dPos ; + assign _dfoo1 = + wci_wslv_respF_cntr_r != 2'd2 || + wci_wslv_respF_cntr_r_8_MINUS_1___d27 == 2'd1 ; + assign _dfoo3 = + wci_wslv_respF_cntr_r != 2'd1 || + wci_wslv_respF_cntr_r_8_MINUS_1___d27 == 2'd0 ; assign _dor1spiCDC_reqF_enq_pw$EN_wset = WILL_FIRE_RL_wci_cfrd || WILL_FIRE_RL_wci_cfwr ; assign _dor1spiDAC_reqF_enq_pw$EN_wset = WILL_FIRE_RL_wci_cfrd || WILL_FIRE_RL_wci_cfwr ; - assign fcCdc_grayCounter_rdCounter_13_BIT_17_14_XOR_f_ETC___d657 = + assign fcCdc_grayCounter_rdCounter_11_BIT_17_12_XOR_f_ETC___d514 = fcCdc_grayCounter_rdCounter[17] ^ fcCdc_grayCounter_rdCounter[16] ; - assign fcCdc_grayCounter_rdCounter_13_BIT_17_14_XOR_f_ETC___d658 = - fcCdc_grayCounter_rdCounter_13_BIT_17_14_XOR_f_ETC___d660 ^ + assign fcCdc_grayCounter_rdCounter_11_BIT_17_12_XOR_f_ETC___d517 = + fcCdc_grayCounter_rdCounter_11_BIT_17_12_XOR_f_ETC___d514 ^ + fcCdc_grayCounter_rdCounter[15] ; + assign fcCdc_grayCounter_rdCounter_11_BIT_17_12_XOR_f_ETC___d519 = + fcCdc_grayCounter_rdCounter_11_BIT_17_12_XOR_f_ETC___d517 ^ + fcCdc_grayCounter_rdCounter[14] ; + assign fcCdc_grayCounter_rdCounter_11_BIT_17_12_XOR_f_ETC___d522 = + fcCdc_grayCounter_rdCounter_11_BIT_17_12_XOR_f_ETC___d519 ^ fcCdc_grayCounter_rdCounter[13] ; - assign fcCdc_grayCounter_rdCounter_13_BIT_17_14_XOR_f_ETC___d659 = - fcCdc_grayCounter_rdCounter_13_BIT_17_14_XOR_f_ETC___d674 ^ + assign fcCdc_grayCounter_rdCounter_11_BIT_17_12_XOR_f_ETC___d524 = + fcCdc_grayCounter_rdCounter_11_BIT_17_12_XOR_f_ETC___d522 ^ + fcCdc_grayCounter_rdCounter[12] ; + assign fcCdc_grayCounter_rdCounter_11_BIT_17_12_XOR_f_ETC___d527 = + fcCdc_grayCounter_rdCounter_11_BIT_17_12_XOR_f_ETC___d524 ^ fcCdc_grayCounter_rdCounter[11] ; - assign fcCdc_grayCounter_rdCounter_13_BIT_17_14_XOR_f_ETC___d660 = - fcCdc_grayCounter_rdCounter_13_BIT_17_14_XOR_f_ETC___d672 ^ - fcCdc_grayCounter_rdCounter[14] ; - assign fcCdc_grayCounter_rdCounter_13_BIT_17_14_XOR_f_ETC___d661 = - fcCdc_grayCounter_rdCounter_13_BIT_17_14_XOR_f_ETC___d663 ^ + assign fcCdc_grayCounter_rdCounter_11_BIT_17_12_XOR_f_ETC___d529 = + fcCdc_grayCounter_rdCounter_11_BIT_17_12_XOR_f_ETC___d527 ^ + fcCdc_grayCounter_rdCounter[10] ; + assign fcCdc_grayCounter_rdCounter_11_BIT_17_12_XOR_f_ETC___d532 = + fcCdc_grayCounter_rdCounter_11_BIT_17_12_XOR_f_ETC___d529 ^ + fcCdc_grayCounter_rdCounter[9] ; + assign fcCdc_grayCounter_rdCounter_11_BIT_17_12_XOR_f_ETC___d534 = + fcCdc_grayCounter_rdCounter_11_BIT_17_12_XOR_f_ETC___d532 ^ fcCdc_grayCounter_rdCounter[8] ; - assign fcCdc_grayCounter_rdCounter_13_BIT_17_14_XOR_f_ETC___d662 = - fcCdc_grayCounter_rdCounter_13_BIT_17_14_XOR_f_ETC___d675 ^ + assign fcCdc_grayCounter_rdCounter_11_BIT_17_12_XOR_f_ETC___d537 = + fcCdc_grayCounter_rdCounter_11_BIT_17_12_XOR_f_ETC___d534 ^ + fcCdc_grayCounter_rdCounter[7] ; + assign fcCdc_grayCounter_rdCounter_11_BIT_17_12_XOR_f_ETC___d539 = + fcCdc_grayCounter_rdCounter_11_BIT_17_12_XOR_f_ETC___d537 ^ fcCdc_grayCounter_rdCounter[6] ; - assign fcCdc_grayCounter_rdCounter_13_BIT_17_14_XOR_f_ETC___d663 = - fcCdc_grayCounter_rdCounter_13_BIT_17_14_XOR_f_ETC___d664 ^ - fcCdc_grayCounter_rdCounter[9] ; - assign fcCdc_grayCounter_rdCounter_13_BIT_17_14_XOR_f_ETC___d664 = - fcCdc_grayCounter_rdCounter_13_BIT_17_14_XOR_f_ETC___d659 ^ - fcCdc_grayCounter_rdCounter[10] ; - assign fcCdc_grayCounter_rdCounter_13_BIT_17_14_XOR_f_ETC___d665 = - fcCdc_grayCounter_rdCounter_13_BIT_17_14_XOR_f_ETC___d676 ^ + assign fcCdc_grayCounter_rdCounter_11_BIT_17_12_XOR_f_ETC___d542 = + fcCdc_grayCounter_rdCounter_11_BIT_17_12_XOR_f_ETC___d539 ^ + fcCdc_grayCounter_rdCounter[5] ; + assign fcCdc_grayCounter_rdCounter_11_BIT_17_12_XOR_f_ETC___d544 = + fcCdc_grayCounter_rdCounter_11_BIT_17_12_XOR_f_ETC___d542 ^ + fcCdc_grayCounter_rdCounter[4] ; + assign fcCdc_grayCounter_rdCounter_11_BIT_17_12_XOR_f_ETC___d547 = + fcCdc_grayCounter_rdCounter_11_BIT_17_12_XOR_f_ETC___d544 ^ fcCdc_grayCounter_rdCounter[3] ; - assign fcCdc_grayCounter_rdCounter_13_BIT_17_14_XOR_f_ETC___d666 = - fcCdc_grayCounter_rdCounter_13_BIT_17_14_XOR_f_ETC___d665 ^ + assign fcCdc_grayCounter_rdCounter_11_BIT_17_12_XOR_f_ETC___d549 = + fcCdc_grayCounter_rdCounter_11_BIT_17_12_XOR_f_ETC___d547 ^ fcCdc_grayCounter_rdCounter[2] ; - assign fcCdc_grayCounter_rdCounter_13_BIT_17_14_XOR_f_ETC___d667 = - fcCdc_grayCounter_rdCounter_13_BIT_17_14_XOR_f_ETC___d666 ^ + assign fcCdc_grayCounter_rdCounter_11_BIT_17_12_XOR_f_ETC___d552 = + fcCdc_grayCounter_rdCounter_11_BIT_17_12_XOR_f_ETC___d549 ^ fcCdc_grayCounter_rdCounter[1] ; - assign fcCdc_grayCounter_rdCounter_13_BIT_17_14_XOR_f_ETC___d668 = - fcCdc_grayCounter_rdCounter_13_BIT_17_14_XOR_f_ETC___d662 ^ - fcCdc_grayCounter_rdCounter[5] ; - assign fcCdc_grayCounter_rdCounter_13_BIT_17_14_XOR_f_ETC___d672 = - fcCdc_grayCounter_rdCounter_13_BIT_17_14_XOR_f_ETC___d657 ^ - fcCdc_grayCounter_rdCounter[15] ; - assign fcCdc_grayCounter_rdCounter_13_BIT_17_14_XOR_f_ETC___d674 = - fcCdc_grayCounter_rdCounter_13_BIT_17_14_XOR_f_ETC___d658 ^ - fcCdc_grayCounter_rdCounter[12] ; - assign fcCdc_grayCounter_rdCounter_13_BIT_17_14_XOR_f_ETC___d675 = - fcCdc_grayCounter_rdCounter_13_BIT_17_14_XOR_f_ETC___d661 ^ - fcCdc_grayCounter_rdCounter[7] ; - assign fcCdc_grayCounter_rdCounter_13_BIT_17_14_XOR_f_ETC___d676 = - fcCdc_grayCounter_rdCounter_13_BIT_17_14_XOR_f_ETC___d668 ^ - fcCdc_grayCounter_rdCounter[4] ; - assign fcCdc_grayCounter_rsCounter_15_BIT_0_22_XOR_fc_ETC___d729 = - z__h36541 ^ fcCdc_grayCounter_rsCounter[17] ; - assign rdat__h42573 = { 14'd0, fcCdc_frequency } ; + assign fcCdc_grayCounter_rsCounter_13_BIT_0_20_XOR_fc_ETC___d454 = + z__h36764 ^ fcCdc_grayCounter_rsCounter[17] ; + assign rdat__h42796 = { 14'd0, fcCdc_frequency } ; assign spiCDC_reqS_BITS_27_TO_0__q1 = spiCDC_reqS[27:0] ; - assign spiDAC_reqS_BITS_7_TO_0__q2 = spiDAC_reqS[7:0] ; - assign x__h13624 = spiCDC_reqS_BITS_27_TO_0__q1[x__h13667] ; - assign x__h13667 = 5'd27 - spiCDC_dPos ; - assign x__h36416 = + assign spiDAC_reqS_BITS_7_TO_0__q3 = spiDAC_reqS[7:0] ; + assign wci_wslv_respF_cntr_r_8_MINUS_1___d27 = + wci_wslv_respF_cntr_r - 2'd1 ; + assign x__h13558 = spiCDC_reqS_BITS_27_TO_0__q1[x__h13601] ; + assign x__h13601 = 5'd27 - spiCDC_dPos ; + assign x__h36639 = 18'd1 << - IF_fcCdc_grayCounter_rsCounter_15_BIT_0_22_XOR_ETC___d777 ; - assign y__h37821 = ~x__h36416 ; - assign z__h36436 = + IF_fcCdc_grayCounter_rsCounter_13_BIT_0_20_XOR_ETC___d490 ; + assign y__h38044 = ~x__h36639 ; + assign z__h36659 = fcCdc_grayCounter_rsCounter[0] ^ fcCdc_grayCounter_rsCounter[1] ; - assign z__h36443 = z__h36436 ^ fcCdc_grayCounter_rsCounter[2] ; - assign z__h36450 = z__h36443 ^ fcCdc_grayCounter_rsCounter[3] ; - assign z__h36457 = z__h36450 ^ fcCdc_grayCounter_rsCounter[4] ; - assign z__h36464 = z__h36457 ^ fcCdc_grayCounter_rsCounter[5] ; - assign z__h36471 = z__h36464 ^ fcCdc_grayCounter_rsCounter[6] ; - assign z__h36478 = z__h36471 ^ fcCdc_grayCounter_rsCounter[7] ; - assign z__h36485 = z__h36478 ^ fcCdc_grayCounter_rsCounter[8] ; - assign z__h36492 = z__h36485 ^ fcCdc_grayCounter_rsCounter[9] ; - assign z__h36499 = z__h36492 ^ fcCdc_grayCounter_rsCounter[10] ; - assign z__h36506 = z__h36499 ^ fcCdc_grayCounter_rsCounter[11] ; - assign z__h36513 = z__h36506 ^ fcCdc_grayCounter_rsCounter[12] ; - assign z__h36520 = z__h36513 ^ fcCdc_grayCounter_rsCounter[13] ; - assign z__h36527 = z__h36520 ^ fcCdc_grayCounter_rsCounter[14] ; - assign z__h36534 = z__h36527 ^ fcCdc_grayCounter_rsCounter[15] ; - assign z__h36541 = z__h36534 ^ fcCdc_grayCounter_rsCounter[16] ; - always@(wci_wslv_reqF$D_OUT or rdat__h42573) + assign z__h36666 = z__h36659 ^ fcCdc_grayCounter_rsCounter[2] ; + assign z__h36673 = z__h36666 ^ fcCdc_grayCounter_rsCounter[3] ; + assign z__h36680 = z__h36673 ^ fcCdc_grayCounter_rsCounter[4] ; + assign z__h36687 = z__h36680 ^ fcCdc_grayCounter_rsCounter[5] ; + assign z__h36694 = z__h36687 ^ fcCdc_grayCounter_rsCounter[6] ; + assign z__h36701 = z__h36694 ^ fcCdc_grayCounter_rsCounter[7] ; + assign z__h36708 = z__h36701 ^ fcCdc_grayCounter_rsCounter[8] ; + assign z__h36715 = z__h36708 ^ fcCdc_grayCounter_rsCounter[9] ; + assign z__h36722 = z__h36715 ^ fcCdc_grayCounter_rsCounter[10] ; + assign z__h36729 = z__h36722 ^ fcCdc_grayCounter_rsCounter[11] ; + assign z__h36736 = z__h36729 ^ fcCdc_grayCounter_rsCounter[12] ; + assign z__h36743 = z__h36736 ^ fcCdc_grayCounter_rsCounter[13] ; + assign z__h36750 = z__h36743 ^ fcCdc_grayCounter_rsCounter[14] ; + assign z__h36757 = z__h36750 ^ fcCdc_grayCounter_rsCounter[15] ; + assign z__h36764 = z__h36757 ^ fcCdc_grayCounter_rsCounter[16] ; + always@(wci_wslv_reqF$D_OUT or rdat__h42796) begin case (wci_wslv_reqF$D_OUT[43:42]) - 2'b0, 2'b01: rdat__h42799 = 32'd0; - 2'b10: rdat__h42799 = 32'hFEEDFACE; - 2'b11: rdat__h42799 = rdat__h42573; + 2'b0, 2'b01: rdat__h43022 = 32'd0; + 2'b10: rdat__h43022 = 32'hFEEDFACE; + 2'b11: rdat__h43022 = rdat__h42796; endcase end always@(spiDAC_iPos or - NOT_spiDAC_iPos_47_EQ_0_61_62_OR_NOT_spiDAC_re_ETC___d363 or + NOT_spiDAC_iPos_45_EQ_0_59_60_OR_NOT_spiDAC_re_ETC___d361 or spiDAC_reqF_head_wrapped or spiDAC_reqF_tail_wrapped or spiDAC_reqF_dInReset$VAL) begin case (spiDAC_iPos) 3'd1, 3'd2, 3'd3, 3'd4: - IF_spiDAC_iPos_47_EQ_4_54_OR_spiDAC_iPos_47_EQ_ETC___d364 = + IF_spiDAC_iPos_45_EQ_4_52_OR_spiDAC_iPos_45_EQ_ETC___d362 = spiDAC_reqF_head_wrapped != spiDAC_reqF_tail_wrapped && !spiDAC_reqF_dInReset$VAL; - default: IF_spiDAC_iPos_47_EQ_4_54_OR_spiDAC_iPos_47_EQ_ETC___d364 = - NOT_spiDAC_iPos_47_EQ_0_61_62_OR_NOT_spiDAC_re_ETC___d363; + default: IF_spiDAC_iPos_45_EQ_4_52_OR_spiDAC_iPos_45_EQ_ETC___d362 = + NOT_spiDAC_iPos_45_EQ_0_59_60_OR_NOT_spiDAC_re_ETC___d361; endcase end always@(spiDAC_iPos or spiDAC_reqS) begin case (spiDAC_iPos) 3'd1: - CASE_spiDAC_iPos_spiDAC_reqS_BIT_8_1_spiDAC_re_ETC__q3 = + CASE_spiDAC_iPos_1_spiDAC_reqS_BIT_9_2_spiDAC__ETC__q2 = spiDAC_reqS[9]; 3'd2: - CASE_spiDAC_iPos_spiDAC_reqS_BIT_8_1_spiDAC_re_ETC__q3 = + CASE_spiDAC_iPos_1_spiDAC_reqS_BIT_9_2_spiDAC__ETC__q2 = spiDAC_reqS[10]; 3'd3: - CASE_spiDAC_iPos_spiDAC_reqS_BIT_8_1_spiDAC_re_ETC__q3 = + CASE_spiDAC_iPos_1_spiDAC_reqS_BIT_9_2_spiDAC__ETC__q2 = spiDAC_reqS[11]; 3'd4: - CASE_spiDAC_iPos_spiDAC_reqS_BIT_8_1_spiDAC_re_ETC__q3 = + CASE_spiDAC_iPos_1_spiDAC_reqS_BIT_9_2_spiDAC__ETC__q2 = spiDAC_reqS[12]; - default: CASE_spiDAC_iPos_spiDAC_reqS_BIT_8_1_spiDAC_re_ETC__q3 = + default: CASE_spiDAC_iPos_1_spiDAC_reqS_BIT_9_2_spiDAC__ETC__q2 = spiDAC_reqS[8]; endcase end - always@(_31_MINUS_spiCDC_dPos_31___d728 or spiCDC_reqS) + always@(_31_MINUS_spiCDC_dPos_29___d230 or spiCDC_reqS) begin - case (_31_MINUS_spiCDC_dPos_31___d728) + case (_31_MINUS_spiCDC_dPos_29___d230) 5'd4: - CASE_31_MINUS_spiCDC_dPos_31_28_31_MINUS_spiCD_ETC__q4 = + CASE_31_MINUS_spiCDC_dPos_29_30_4_spiCDC_reqS__ETC__q4 = spiCDC_reqS[28]; 5'd5: - CASE_31_MINUS_spiCDC_dPos_31_28_31_MINUS_spiCD_ETC__q4 = + CASE_31_MINUS_spiCDC_dPos_29_30_4_spiCDC_reqS__ETC__q4 = spiCDC_reqS[29]; 5'd6: - CASE_31_MINUS_spiCDC_dPos_31_28_31_MINUS_spiCD_ETC__q4 = + CASE_31_MINUS_spiCDC_dPos_29_30_4_spiCDC_reqS__ETC__q4 = spiCDC_reqS[30]; - default: CASE_31_MINUS_spiCDC_dPos_31_28_31_MINUS_spiCD_ETC__q4 = - _31_MINUS_spiCDC_dPos_31___d728 == 5'd7 && spiCDC_reqS[31]; + default: CASE_31_MINUS_spiCDC_dPos_29_30_4_spiCDC_reqS__ETC__q4 = + _31_MINUS_spiCDC_dPos_29___d230 == 5'd7 && spiCDC_reqS[31]; endcase end - always@(_31_MINUS_spiCDC_dPos_31___d728 or x__h13624 or spiCDC_reqS) + always@(_31_MINUS_spiCDC_dPos_29___d230 or x__h13558 or spiCDC_reqS) begin - case (_31_MINUS_spiCDC_dPos_31___d728) + case (_31_MINUS_spiCDC_dPos_29___d230) 5'd0: - CASE_31_MINUS_spiCDC_dPos_31_28_x3624_0_spiCDC_ETC__q5 = + CASE_31_MINUS_spiCDC_dPos_29_30_0_spiCDC_reqS__ETC__q5 = spiCDC_reqS[28]; 5'd1: - CASE_31_MINUS_spiCDC_dPos_31_28_x3624_0_spiCDC_ETC__q5 = + CASE_31_MINUS_spiCDC_dPos_29_30_0_spiCDC_reqS__ETC__q5 = spiCDC_reqS[29]; 5'd2: - CASE_31_MINUS_spiCDC_dPos_31_28_x3624_0_spiCDC_ETC__q5 = + CASE_31_MINUS_spiCDC_dPos_29_30_0_spiCDC_reqS__ETC__q5 = spiCDC_reqS[30]; 5'd3: - CASE_31_MINUS_spiCDC_dPos_31_28_x3624_0_spiCDC_ETC__q5 = + CASE_31_MINUS_spiCDC_dPos_29_30_0_spiCDC_reqS__ETC__q5 = spiCDC_reqS[31]; - default: CASE_31_MINUS_spiCDC_dPos_31_28_x3624_0_spiCDC_ETC__q5 = - x__h13624; + default: CASE_31_MINUS_spiCDC_dPos_29_30_0_spiCDC_reqS__ETC__q5 = + x__h13558; endcase end @@ -2032,7 +2042,7 @@ module mkFMC150(CLK_flp_clk, wci_wslv_illegalEdge <= `BSV_ASSIGNMENT_DELAY 1'd0; wci_wslv_nState <= `BSV_ASSIGNMENT_DELAY 3'd0; wci_wslv_reqF_countReg <= `BSV_ASSIGNMENT_DELAY 2'd0; - wci_wslv_respF_c_r <= `BSV_ASSIGNMENT_DELAY 2'd0; + wci_wslv_respF_cntr_r <= `BSV_ASSIGNMENT_DELAY 2'd0; wci_wslv_respF_q_0 <= `BSV_ASSIGNMENT_DELAY 34'h0AAAAAAAA; wci_wslv_respF_q_1 <= `BSV_ASSIGNMENT_DELAY 34'h0AAAAAAAA; wci_wslv_sFlagReg <= `BSV_ASSIGNMENT_DELAY 1'd0; @@ -2083,8 +2093,9 @@ module mkFMC150(CLK_flp_clk, if (wci_wslv_reqF_countReg$EN) wci_wslv_reqF_countReg <= `BSV_ASSIGNMENT_DELAY wci_wslv_reqF_countReg$D_IN; - if (wci_wslv_respF_c_r$EN) - wci_wslv_respF_c_r <= `BSV_ASSIGNMENT_DELAY wci_wslv_respF_c_r$D_IN; + if (wci_wslv_respF_cntr_r$EN) + wci_wslv_respF_cntr_r <= `BSV_ASSIGNMENT_DELAY + wci_wslv_respF_cntr_r$D_IN; if (wci_wslv_respF_q_0$EN) wci_wslv_respF_q_0 <= `BSV_ASSIGNMENT_DELAY wci_wslv_respF_q_0$D_IN; if (wci_wslv_respF_q_1$EN) @@ -2290,7 +2301,7 @@ module mkFMC150(CLK_flp_clk, wci_wslv_isReset_isInReset = 1'h0; wci_wslv_nState = 3'h2; wci_wslv_reqF_countReg = 2'h2; - wci_wslv_respF_c_r = 2'h2; + wci_wslv_respF_cntr_r = 2'h2; wci_wslv_respF_q_0 = 34'h2AAAAAAAA; wci_wslv_respF_q_1 = 34'h2AAAAAAAA; wci_wslv_sFlagReg = 1'h0; @@ -2312,39 +2323,39 @@ module mkFMC150(CLK_flp_clk, if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfwr) begin - v__h42053 = $time; + v__h42276 = $time; #0; end if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfwr) $display("[%0d]: %m: WCI CONFIG WRITE Addr:%0x BE:%0x Data:%0x", - v__h42053, + v__h42276, wci_wslv_reqF$D_OUT[63:32], wci_wslv_reqF$D_OUT[67:64], wci_wslv_reqF$D_OUT[31:0]); if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfrd) begin - v__h42815 = $time; + v__h43038 = $time; #0; end if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfrd) $display("[%0d]: %m: WCI CONFIG READ Addr:%0x BE:%0x Data:%0x", - v__h42815, + v__h43038, wci_wslv_reqF$D_OUT[63:32], wci_wslv_reqF$D_OUT[67:64], - rdat__h42799); + rdat__h43022); if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_start) begin - v__h3694 = $time; + v__h3562 = $time; #0; end if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_start) $display("[%0d]: %m: WCI ControlOp: Starting-transition edge:%x from:%x", - v__h3694, + v__h3562, wci_wslv_reqF$D_OUT[36:34], wci_wslv_cState); if (wciS0_MReset_n != `BSV_RESET_VALUE) @@ -2416,25 +2427,25 @@ module mkFMC150(CLK_flp_clk, if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge) begin - v__h4013 = $time; + v__h3881 = $time; #0; end if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge) $display("[%0d]: %m: WCI ControlOp: ILLEGAL-EDGE Completed-transition edge:%x from:%x", - v__h4013, + v__h3881, wci_wslv_cEdge, wci_wslv_cState); if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && !wci_wslv_illegalEdge) begin - v__h3869 = $time; + v__h3737 = $time; #0; end if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && !wci_wslv_illegalEdge) $display("[%0d]: %m: WCI ControlOp: Completed-transition edge:%x from:%x to:%x", - v__h3869, + v__h3737, wci_wslv_cEdge, wci_wslv_cState, wci_wslv_nState); diff --git a/rtl/mkFTop_alst4.v b/rtl/mkFTop_alst4.v new file mode 100644 index 00000000..afe7d538 --- /dev/null +++ b/rtl/mkFTop_alst4.v @@ -0,0 +1,2771 @@ +// +// Generated by Bluespec Compiler, version 2012.09.beta1 (build 29570, 2012-09.11) +// +// On Tue Jan 1 09:13:45 EST 2013 +// +// +// Ports: +// Name I/O size props +// pcie_tx O 4 +// led O 16 reg +// hsmc_out O 16 reg +// led_cathode O 20 const +// led_anode O 20 +// lcd_db O 4 +// lcd_e O 1 +// lcd_rs O 1 +// lcd_rw O 1 +// gps_ppsSyncOut O 1 +// flash_addr O 24 reg +// flash_ce_n O 1 +// flash_oe_n O 1 +// flash_we_n O 1 +// flash_wp_n O 1 const +// flash_rst_n O 1 const +// flash_adv_n O 1 const +// dram_addr O 13 +// dram_ba O 3 +// dram_ras_n O 1 +// dram_cas_n O 1 +// dram_we_n O 1 +// dram_reset_n O 1 +// dram_cs_n O 1 +// dram_odt O 1 +// dram_cke O 1 +// dram_dm O 2 +// dram_ck_p O 1 +// dram_ck_n O 1 +// p125clk O 1 clock +// CLK_GATE_p125clk O 1 const +// p125rst O 1 reset +// sys0_clk I 1 clock +// sys0_rstn I 1 reset +// pcie_clk I 1 clock +// pcie_rstn I 1 reset +// pcie_rx_i I 4 +// usr_sw_i I 8 reg +// hsmc_in_i I 16 reg +// gps_ppsSyncIn_x I 1 reg +// flash_fwait_i I 1 reg +// dram_rdn_i I 1 +// dram_rup_i I 1 +// flash_io_dq IO 16 inout +// dram_io_dq IO 16 inout +// dram_io_dqs_p IO 2 inout +// dram_io_dqs_n IO 2 inout +// +// No combinational paths from inputs to outputs +// +// + +`ifdef BSV_ASSIGNMENT_DELAY +`else + `define BSV_ASSIGNMENT_DELAY +`endif + +`ifdef BSV_POSITIVE_RESET + `define BSV_RESET_VALUE 1'b1 + `define BSV_RESET_EDGE posedge +`else + `define BSV_RESET_VALUE 1'b0 + `define BSV_RESET_EDGE negedge +`endif + +module mkFTop_alst4(sys0_clk, + sys0_rstn, + pcie_clk, + pcie_rstn, + + flash_io_dq, + dram_io_dq, + dram_io_dqs_p, + dram_io_dqs_n, + + pcie_rx_i, + + pcie_tx, + + usr_sw_i, + + led, + + hsmc_in_i, + + hsmc_out, + + led_cathode, + + led_anode, + + lcd_db, + + lcd_e, + + lcd_rs, + + lcd_rw, + + gps_ppsSyncIn_x, + + gps_ppsSyncOut, + + flash_addr, + + flash_ce_n, + + flash_oe_n, + + flash_we_n, + + flash_wp_n, + + flash_rst_n, + + flash_adv_n, + + flash_fwait_i, + + dram_addr, + + dram_ba, + + dram_ras_n, + + dram_cas_n, + + dram_we_n, + + dram_reset_n, + + dram_cs_n, + + dram_odt, + + dram_cke, + + dram_dm, + + dram_ck_p, + + dram_ck_n, + + dram_rdn_i, + + dram_rup_i, + + p125clk, + CLK_GATE_p125clk, + + p125rst); + input sys0_clk; + input sys0_rstn; + input pcie_clk; + input pcie_rstn; + + inout [15 : 0] flash_io_dq; + inout [15 : 0] dram_io_dq; + inout [1 : 0] dram_io_dqs_p; + inout [1 : 0] dram_io_dqs_n; + + // action method pcie_rx + input [3 : 0] pcie_rx_i; + + // value method pcie_tx + output [3 : 0] pcie_tx; + + // action method usr_sw + input [7 : 0] usr_sw_i; + + // value method led + output [15 : 0] led; + + // action method hsmc_in + input [15 : 0] hsmc_in_i; + + // value method hsmc_out + output [15 : 0] hsmc_out; + + // value method led_cathode + output [19 : 0] led_cathode; + + // value method led_anode + output [19 : 0] led_anode; + + // value method lcd_db + output [3 : 0] lcd_db; + + // value method lcd_e + output lcd_e; + + // value method lcd_rs + output lcd_rs; + + // value method lcd_rw + output lcd_rw; + + // action method gps_ppsSyncIn + input gps_ppsSyncIn_x; + + // value method gps_ppsSyncOut + output gps_ppsSyncOut; + + // value method flash_addr + output [23 : 0] flash_addr; + + // value method flash_ce_n + output flash_ce_n; + + // value method flash_oe_n + output flash_oe_n; + + // value method flash_we_n + output flash_we_n; + + // value method flash_wp_n + output flash_wp_n; + + // value method flash_rst_n + output flash_rst_n; + + // value method flash_adv_n + output flash_adv_n; + + // action method flash_fwait + input flash_fwait_i; + + // value method dram_addr + output [12 : 0] dram_addr; + + // value method dram_ba + output [2 : 0] dram_ba; + + // value method dram_ras_n + output dram_ras_n; + + // value method dram_cas_n + output dram_cas_n; + + // value method dram_we_n + output dram_we_n; + + // value method dram_reset_n + output dram_reset_n; + + // value method dram_cs_n + output dram_cs_n; + + // value method dram_odt + output dram_odt; + + // value method dram_cke + output dram_cke; + + // value method dram_dm + output [1 : 0] dram_dm; + + // value method dram_ck_p + output dram_ck_p; + + // value method dram_ck_n + output dram_ck_n; + + // action method dram_rdn + input dram_rdn_i; + + // action method dram_rup + input dram_rup_i; + + // oscillator and gates for output clock p125clk + output p125clk; + output CLK_GATE_p125clk; + + // output resets + output p125rst; + + // signals for module outputs + wire [23 : 0] flash_addr; + wire [19 : 0] led_anode, led_cathode; + wire [15 : 0] hsmc_out, led; + wire [12 : 0] dram_addr; + wire [3 : 0] lcd_db, pcie_tx; + wire [2 : 0] dram_ba; + wire [1 : 0] dram_dm; + wire CLK_GATE_p125clk, + dram_cas_n, + dram_ck_n, + dram_ck_p, + dram_cke, + dram_cs_n, + dram_odt, + dram_ras_n, + dram_reset_n, + dram_we_n, + flash_adv_n, + flash_ce_n, + flash_oe_n, + flash_rst_n, + flash_we_n, + flash_wp_n, + gps_ppsSyncOut, + lcd_e, + lcd_rs, + lcd_rw, + p125clk, + p125rst; + + // inlined wires + wire [127 : 0] pciw_pci0_rxDws_new_data$wget, pciw_pci0_txDws_new_data$wget; + wire [2 : 0] pciw_pci0_rxDws_delta_deq$wget, + pciw_pci0_rxDws_delta_enq$wget, + pciw_pci0_txDws_delta_deq$wget, + pciw_pci0_txDws_delta_enq$wget; + wire [1 : 0] infLed$wget; + wire pciw_pci0_avaTxEmpty$wget, + pciw_pci0_avaTxEmpty$whas, + pciw_pci0_avaTxEop$wget, + pciw_pci0_avaTxEop$whas, + pciw_pci0_avaTxErr$wget, + pciw_pci0_avaTxErr$whas, + pciw_pci0_avaTxSop$wget, + pciw_pci0_avaTxSop$whas, + pciw_pci0_avaTxValid$wget, + pciw_pci0_avaTxValid$whas, + pciw_pci0_rxDws_delta_deq$whas, + pciw_pci0_rxDws_delta_enq$whas, + pciw_pci0_rxDws_new_data$whas, + pciw_pci0_rxInF_doResetClr$whas, + pciw_pci0_rxInF_doResetDeq$whas, + pciw_pci0_rxInF_doResetEnq$whas, + pciw_pci0_rxInF_r_clr$whas, + pciw_pci0_rxInF_r_deq$whas, + pciw_pci0_rxInF_r_enq$whas, + pciw_pci0_txDws_delta_deq$whas, + pciw_pci0_txDws_delta_enq$whas, + pciw_pci0_txDws_new_data$whas, + pciw_pci0_txOutF_doResetClr$whas, + pciw_pci0_txOutF_doResetDeq$whas, + pciw_pci0_txOutF_doResetEnq$whas, + pciw_pci0_txOutF_r_clr$whas, + pciw_pci0_txOutF_r_deq$whas, + pciw_pci0_txOutF_r_enq$whas; + + // register freeCnt + reg [31 : 0] freeCnt; + wire [31 : 0] freeCnt$D_IN; + wire freeCnt$EN; + + // register hsmcReg + reg [15 : 0] hsmcReg; + wire [15 : 0] hsmcReg$D_IN; + wire hsmcReg$EN; + + // register ledReg + reg [15 : 0] ledReg; + wire [15 : 0] ledReg$D_IN; + wire ledReg$EN; + + // register needs_init + reg needs_init; + wire needs_init$D_IN, needs_init$EN; + + // register pciDevice + reg [15 : 0] pciDevice; + wire [15 : 0] pciDevice$D_IN; + wire pciDevice$EN; + + // register pciw_pci0_cfgDataWr + reg pciw_pci0_cfgDataWr; + wire pciw_pci0_cfgDataWr$D_IN, pciw_pci0_cfgDataWr$EN; + + // register pciw_pci0_cfgSample + reg pciw_pci0_cfgSample; + wire pciw_pci0_cfgSample$D_IN, pciw_pci0_cfgSample$EN; + + // register pciw_pci0_deviceReg + reg [15 : 0] pciw_pci0_deviceReg; + wire [15 : 0] pciw_pci0_deviceReg$D_IN; + wire pciw_pci0_deviceReg$EN; + + // register pciw_pci0_rxDbgDeDeq + reg [15 : 0] pciw_pci0_rxDbgDeDeq; + wire [15 : 0] pciw_pci0_rxDbgDeDeq$D_IN; + wire pciw_pci0_rxDbgDeDeq$EN; + + // register pciw_pci0_rxDbgDeEof + reg [15 : 0] pciw_pci0_rxDbgDeEof; + wire [15 : 0] pciw_pci0_rxDbgDeEof$D_IN; + wire pciw_pci0_rxDbgDeEof$EN; + + // register pciw_pci0_rxDbgDeSof + reg [15 : 0] pciw_pci0_rxDbgDeSof; + wire [15 : 0] pciw_pci0_rxDbgDeSof$D_IN; + wire pciw_pci0_rxDbgDeSof$EN; + + // register pciw_pci0_rxDbgDestage + reg [15 : 0] pciw_pci0_rxDbgDestage; + wire [15 : 0] pciw_pci0_rxDbgDestage$D_IN; + wire pciw_pci0_rxDbgDestage$EN; + + // register pciw_pci0_rxDbgEnEnq + reg [15 : 0] pciw_pci0_rxDbgEnEnq; + wire [15 : 0] pciw_pci0_rxDbgEnEnq$D_IN; + wire pciw_pci0_rxDbgEnEnq$EN; + + // register pciw_pci0_rxDbgEnEof + reg [15 : 0] pciw_pci0_rxDbgEnEof; + wire [15 : 0] pciw_pci0_rxDbgEnEof$D_IN; + wire pciw_pci0_rxDbgEnEof$EN; + + // register pciw_pci0_rxDbgEnSof + reg [15 : 0] pciw_pci0_rxDbgEnSof; + wire [15 : 0] pciw_pci0_rxDbgEnSof$D_IN; + wire pciw_pci0_rxDbgEnSof$EN; + + // register pciw_pci0_rxDbgEnstage + reg [15 : 0] pciw_pci0_rxDbgEnstage; + wire [15 : 0] pciw_pci0_rxDbgEnstage$D_IN; + wire pciw_pci0_rxDbgEnstage$EN; + + // register pciw_pci0_rxDbgInstage + reg [15 : 0] pciw_pci0_rxDbgInstage; + wire [15 : 0] pciw_pci0_rxDbgInstage$D_IN; + wire pciw_pci0_rxDbgInstage$EN; + + // register pciw_pci0_rxDwrDeq + reg [10 : 0] pciw_pci0_rxDwrDeq; + wire [10 : 0] pciw_pci0_rxDwrDeq$D_IN; + wire pciw_pci0_rxDwrDeq$EN; + + // register pciw_pci0_rxDwrEnq + reg [10 : 0] pciw_pci0_rxDwrEnq; + wire [10 : 0] pciw_pci0_rxDwrEnq$D_IN; + wire pciw_pci0_rxDwrEnq$EN; + + // register pciw_pci0_rxDws_num_empty + reg [3 : 0] pciw_pci0_rxDws_num_empty; + wire [3 : 0] pciw_pci0_rxDws_num_empty$D_IN; + wire pciw_pci0_rxDws_num_empty$EN; + + // register pciw_pci0_rxDws_num_full + reg [3 : 0] pciw_pci0_rxDws_num_full; + wire [3 : 0] pciw_pci0_rxDws_num_full$D_IN; + wire pciw_pci0_rxDws_num_full$EN; + + // register pciw_pci0_rxDws_vec + reg [255 : 0] pciw_pci0_rxDws_vec; + wire [255 : 0] pciw_pci0_rxDws_vec$D_IN; + wire pciw_pci0_rxDws_vec$EN; + + // register pciw_pci0_rxInF_countReg + reg [5 : 0] pciw_pci0_rxInF_countReg; + wire [5 : 0] pciw_pci0_rxInF_countReg$D_IN; + wire pciw_pci0_rxInF_countReg$EN; + + // register pciw_pci0_rxInF_levelsValid + reg pciw_pci0_rxInF_levelsValid; + wire pciw_pci0_rxInF_levelsValid$D_IN, pciw_pci0_rxInF_levelsValid$EN; + + // register pciw_pci0_rxInFlight + reg pciw_pci0_rxInFlight; + wire pciw_pci0_rxInFlight$D_IN, pciw_pci0_rxInFlight$EN; + + // register pciw_pci0_txDbgDeDeq + reg [15 : 0] pciw_pci0_txDbgDeDeq; + wire [15 : 0] pciw_pci0_txDbgDeDeq$D_IN; + wire pciw_pci0_txDbgDeDeq$EN; + + // register pciw_pci0_txDbgDeEof + reg [15 : 0] pciw_pci0_txDbgDeEof; + wire [15 : 0] pciw_pci0_txDbgDeEof$D_IN; + wire pciw_pci0_txDbgDeEof$EN; + + // register pciw_pci0_txDbgDeSof + reg [15 : 0] pciw_pci0_txDbgDeSof; + wire [15 : 0] pciw_pci0_txDbgDeSof$D_IN; + wire pciw_pci0_txDbgDeSof$EN; + + // register pciw_pci0_txDbgDestage + reg [15 : 0] pciw_pci0_txDbgDestage; + wire [15 : 0] pciw_pci0_txDbgDestage$D_IN; + wire pciw_pci0_txDbgDestage$EN; + + // register pciw_pci0_txDbgEnEnq + reg [15 : 0] pciw_pci0_txDbgEnEnq; + wire [15 : 0] pciw_pci0_txDbgEnEnq$D_IN; + wire pciw_pci0_txDbgEnEnq$EN; + + // register pciw_pci0_txDbgEnEof + reg [15 : 0] pciw_pci0_txDbgEnEof; + wire [15 : 0] pciw_pci0_txDbgEnEof$D_IN; + wire pciw_pci0_txDbgEnEof$EN; + + // register pciw_pci0_txDbgEnSof + reg [15 : 0] pciw_pci0_txDbgEnSof; + wire [15 : 0] pciw_pci0_txDbgEnSof$D_IN; + wire pciw_pci0_txDbgEnSof$EN; + + // register pciw_pci0_txDbgEnstage + reg [15 : 0] pciw_pci0_txDbgEnstage; + wire [15 : 0] pciw_pci0_txDbgEnstage$D_IN; + wire pciw_pci0_txDbgEnstage$EN; + + // register pciw_pci0_txDbgExstage + reg [15 : 0] pciw_pci0_txDbgExstage; + wire [15 : 0] pciw_pci0_txDbgExstage$D_IN; + wire pciw_pci0_txDbgExstage$EN; + + // register pciw_pci0_txDwrDeq + reg [10 : 0] pciw_pci0_txDwrDeq; + wire [10 : 0] pciw_pci0_txDwrDeq$D_IN; + wire pciw_pci0_txDwrDeq$EN; + + // register pciw_pci0_txDwrEnq + reg [10 : 0] pciw_pci0_txDwrEnq; + wire [10 : 0] pciw_pci0_txDwrEnq$D_IN; + wire pciw_pci0_txDwrEnq$EN; + + // register pciw_pci0_txDws_num_empty + reg [3 : 0] pciw_pci0_txDws_num_empty; + wire [3 : 0] pciw_pci0_txDws_num_empty$D_IN; + wire pciw_pci0_txDws_num_empty$EN; + + // register pciw_pci0_txDws_num_full + reg [3 : 0] pciw_pci0_txDws_num_full; + wire [3 : 0] pciw_pci0_txDws_num_full$D_IN; + wire pciw_pci0_txDws_num_full$EN; + + // register pciw_pci0_txDws_vec + reg [255 : 0] pciw_pci0_txDws_vec; + wire [255 : 0] pciw_pci0_txDws_vec$D_IN; + wire pciw_pci0_txDws_vec$EN; + + // register pciw_pci0_txInFlight + reg pciw_pci0_txInFlight; + wire pciw_pci0_txInFlight$D_IN, pciw_pci0_txInFlight$EN; + + // register pciw_pci0_txOutF_countReg + reg [9 : 0] pciw_pci0_txOutF_countReg; + wire [9 : 0] pciw_pci0_txOutF_countReg$D_IN; + wire pciw_pci0_txOutF_countReg$EN; + + // register pciw_pci0_txOutF_levelsValid + reg pciw_pci0_txOutF_levelsValid; + wire pciw_pci0_txOutF_levelsValid$D_IN, pciw_pci0_txOutF_levelsValid$EN; + + // register pciw_pci0_txReadyD + reg pciw_pci0_txReadyD; + wire pciw_pci0_txReadyD$D_IN, pciw_pci0_txReadyD$EN; + + // register pciw_pciDevice + reg [15 : 0] pciw_pciDevice; + wire [15 : 0] pciw_pciDevice$D_IN; + wire pciw_pciDevice$EN; + + // register swReg + reg [7 : 0] swReg; + wire [7 : 0] swReg$D_IN; + wire swReg$EN; + + // ports of submodule ctop + wire [152 : 0] ctop$server_request_put, ctop$server_response_get; + wire [127 : 0] ctop$wmemiM0_MData, ctop$wmemiM0_SData; + wire [58 : 0] ctop$cpServer_request_put; + wire [35 : 0] ctop$wmemiM0_MAddr; + wire [31 : 0] ctop$wci_m_0_SData, + ctop$wci_m_1_MAddr, + ctop$wci_m_1_MData, + ctop$wci_m_1_SData, + ctop$wci_m_2_SData, + ctop$wci_m_3_SData, + ctop$wci_m_4_MAddr, + ctop$wci_m_4_MData, + ctop$wci_m_4_SData, + ctop$wsi_s_adc_MData; + wire [15 : 0] ctop$wmemiM0_MDataByteEn; + wire [11 : 0] ctop$wmemiM0_MBurstLength, ctop$wsi_s_adc_MBurstLength; + wire [7 : 0] ctop$wsi_s_adc_MReqInfo; + wire [3 : 0] ctop$wci_m_1_MByteEn, + ctop$wci_m_4_MByteEn, + ctop$wsi_s_adc_MByteEn; + wire [2 : 0] ctop$switch_x, + ctop$wci_m_1_MCmd, + ctop$wci_m_4_MCmd, + ctop$wmemiM0_MCmd, + ctop$wsi_s_adc_MCmd; + wire [1 : 0] ctop$led, + ctop$wci_m_0_SFlag, + ctop$wci_m_0_SResp, + ctop$wci_m_1_MFlag, + ctop$wci_m_1_SFlag, + ctop$wci_m_1_SResp, + ctop$wci_m_2_SFlag, + ctop$wci_m_2_SResp, + ctop$wci_m_3_SFlag, + ctop$wci_m_3_SResp, + ctop$wci_m_4_MFlag, + ctop$wci_m_4_SFlag, + ctop$wci_m_4_SResp, + ctop$wmemiM0_SResp; + wire ctop$EN_cpServer_request_put, + ctop$EN_cpServer_response_get, + ctop$EN_server_request_put, + ctop$EN_server_response_get, + ctop$RDY_server_request_put, + ctop$RDY_server_response_get, + ctop$RST_N_wci_m_1, + ctop$RST_N_wci_m_4, + ctop$gps_ppsSyncIn_x, + ctop$gps_ppsSyncOut, + ctop$wci_m_0_SThreadBusy, + ctop$wci_m_1_MAddrSpace, + ctop$wci_m_1_SThreadBusy, + ctop$wci_m_2_SThreadBusy, + ctop$wci_m_3_SThreadBusy, + ctop$wci_m_4_MAddrSpace, + ctop$wci_m_4_SThreadBusy, + ctop$wmemiM0_MDataLast, + ctop$wmemiM0_MDataValid, + ctop$wmemiM0_MReqLast, + ctop$wmemiM0_MReset_n, + ctop$wmemiM0_SCmdAccept, + ctop$wmemiM0_SDataAccept, + ctop$wmemiM0_SRespLast, + ctop$wsi_m_dac_SReset_n, + ctop$wsi_m_dac_SThreadBusy, + ctop$wsi_s_adc_MBurstPrecise, + ctop$wsi_s_adc_MReqLast, + ctop$wsi_s_adc_MReset_n; + + // ports of submodule dram0 + wire [127 : 0] dram0$wmemiS0_MData, dram0$wmemiS0_SData; + wire [35 : 0] dram0$wmemiS0_MAddr; + wire [31 : 0] dram0$wciS0_MAddr, dram0$wciS0_MData, dram0$wciS0_SData; + wire [15 : 0] dram0$dram_io_dq, dram0$wmemiS0_MDataByteEn; + wire [12 : 0] dram0$dram_addr; + wire [11 : 0] dram0$wmemiS0_MBurstLength; + wire [3 : 0] dram0$wciS0_MByteEn; + wire [2 : 0] dram0$dram_ba, dram0$wciS0_MCmd, dram0$wmemiS0_MCmd; + wire [1 : 0] dram0$dram_dm, + dram0$dram_io_dqs_n, + dram0$dram_io_dqs_p, + dram0$wciS0_MFlag, + dram0$wciS0_SFlag, + dram0$wciS0_SResp, + dram0$wmemiS0_SResp; + wire dram0$dram_cas_n, + dram0$dram_ck_n, + dram0$dram_ck_p, + dram0$dram_cke, + dram0$dram_cs_n, + dram0$dram_odt, + dram0$dram_ras_n, + dram0$dram_rdn_i, + dram0$dram_reset_n, + dram0$dram_rup_i, + dram0$dram_we_n, + dram0$wciS0_MAddrSpace, + dram0$wciS0_SThreadBusy, + dram0$wmemiS0_MDataLast, + dram0$wmemiS0_MDataValid, + dram0$wmemiS0_MReqLast, + dram0$wmemiS0_MReset_n, + dram0$wmemiS0_SCmdAccept, + dram0$wmemiS0_SDataAccept, + dram0$wmemiS0_SRespLast; + + // ports of submodule flash0 + wire [31 : 0] flash0$wciS0_MAddr, flash0$wciS0_MData, flash0$wciS0_SData; + wire [23 : 0] flash0$flash_addr; + wire [15 : 0] flash0$flash_io_dq; + wire [3 : 0] flash0$wciS0_MByteEn; + wire [2 : 0] flash0$wciS0_MCmd; + wire [1 : 0] flash0$wciS0_MFlag, flash0$wciS0_SFlag, flash0$wciS0_SResp; + wire flash0$flash_adv_n, + flash0$flash_ce_n, + flash0$flash_fwait_i, + flash0$flash_oe_n, + flash0$flash_rst_n, + flash0$flash_we_n, + flash0$flash_wp_n, + flash0$wciS0_MAddrSpace, + flash0$wciS0_SThreadBusy; + + // ports of submodule lcd_ctrl + wire [127 : 0] lcd_ctrl$setLine1_text, lcd_ctrl$setLine2_text; + wire [3 : 0] lcd_ctrl$db; + wire lcd_ctrl$EN_setLine1, + lcd_ctrl$EN_setLine2, + lcd_ctrl$e, + lcd_ctrl$rs, + lcd_ctrl$rw; + + // ports of submodule pciw_aliveLed_sb + wire pciw_aliveLed_sb$dD_OUT, pciw_aliveLed_sb$sD_IN, pciw_aliveLed_sb$sEN; + + // ports of submodule pciw_i2pF + wire [152 : 0] pciw_i2pF$D_IN, pciw_i2pF$D_OUT; + wire pciw_i2pF$CLR, + pciw_i2pF$DEQ, + pciw_i2pF$EMPTY_N, + pciw_i2pF$ENQ, + pciw_i2pF$FULL_N; + + // ports of submodule pciw_linkLed_sb + wire pciw_linkLed_sb$dD_OUT, pciw_linkLed_sb$sD_IN, pciw_linkLed_sb$sEN; + + // ports of submodule pciw_p2iF + wire [152 : 0] pciw_p2iF$D_IN, pciw_p2iF$D_OUT; + wire pciw_p2iF$CLR, + pciw_p2iF$DEQ, + pciw_p2iF$EMPTY_N, + pciw_p2iF$ENQ, + pciw_p2iF$FULL_N; + + // ports of submodule pciw_pci0_pcie_ep + wire [127 : 0] pciw_pci0_pcie_ep$rx_st_data0, pciw_pci0_pcie_ep$tx_st_data0; + wire [31 : 0] pciw_pci0_pcie_ep$ava_debug, pciw_pci0_pcie_ep$tl_cfg_ctl; + wire [15 : 0] pciw_pci0_pcie_ep$rx_st_be0; + wire [7 : 0] pciw_pci0_pcie_ep$rx_st_bardec0; + wire [3 : 0] pciw_pci0_pcie_ep$pcie_rx_in, + pciw_pci0_pcie_ep$pcie_tx_out, + pciw_pci0_pcie_ep$tl_cfg_add; + wire pciw_pci0_pcie_ep$ava_alive, + pciw_pci0_pcie_ep$ava_core_clk_out, + pciw_pci0_pcie_ep$ava_lnk_up, + pciw_pci0_pcie_ep$ava_srstn, + pciw_pci0_pcie_ep$rx_st_empty0, + pciw_pci0_pcie_ep$rx_st_eop0, + pciw_pci0_pcie_ep$rx_st_mask0, + pciw_pci0_pcie_ep$rx_st_ready0, + pciw_pci0_pcie_ep$rx_st_sop0, + pciw_pci0_pcie_ep$rx_st_valid0, + pciw_pci0_pcie_ep$tl_cfg_ctl_wr, + pciw_pci0_pcie_ep$tx_st_empty0, + pciw_pci0_pcie_ep$tx_st_eop0, + pciw_pci0_pcie_ep$tx_st_err0, + pciw_pci0_pcie_ep$tx_st_ready0, + pciw_pci0_pcie_ep$tx_st_sop0, + pciw_pci0_pcie_ep$tx_st_valid0; + + // ports of submodule pciw_pci0_rxEofF + wire [2 : 0] pciw_pci0_rxEofF$D_IN; + wire pciw_pci0_rxEofF$CLR, + pciw_pci0_rxEofF$DEQ, + pciw_pci0_rxEofF$EMPTY_N, + pciw_pci0_rxEofF$ENQ, + pciw_pci0_rxEofF$FULL_N; + + // ports of submodule pciw_pci0_rxHeadF + wire [30 : 0] pciw_pci0_rxHeadF$D_IN, pciw_pci0_rxHeadF$D_OUT; + wire pciw_pci0_rxHeadF$CLR, + pciw_pci0_rxHeadF$DEQ, + pciw_pci0_rxHeadF$EMPTY_N, + pciw_pci0_rxHeadF$ENQ, + pciw_pci0_rxHeadF$FULL_N; + + // ports of submodule pciw_pci0_rxInF + wire [154 : 0] pciw_pci0_rxInF$D_IN, pciw_pci0_rxInF$D_OUT; + wire pciw_pci0_rxInF$CLR, + pciw_pci0_rxInF$DEQ, + pciw_pci0_rxInF$EMPTY_N, + pciw_pci0_rxInF$ENQ, + pciw_pci0_rxInF$FULL_N; + + // ports of submodule pciw_pci0_rxOutF + wire [152 : 0] pciw_pci0_rxOutF$D_IN, pciw_pci0_rxOutF$D_OUT; + wire pciw_pci0_rxOutF$CLR, + pciw_pci0_rxOutF$DEQ, + pciw_pci0_rxOutF$EMPTY_N, + pciw_pci0_rxOutF$ENQ, + pciw_pci0_rxOutF$FULL_N; + + // ports of submodule pciw_pci0_txEofF + wire [2 : 0] pciw_pci0_txEofF$D_IN; + wire pciw_pci0_txEofF$CLR, + pciw_pci0_txEofF$DEQ, + pciw_pci0_txEofF$EMPTY_N, + pciw_pci0_txEofF$ENQ, + pciw_pci0_txEofF$FULL_N; + + // ports of submodule pciw_pci0_txExF + wire pciw_pci0_txExF$CLR, + pciw_pci0_txExF$DEQ, + pciw_pci0_txExF$D_IN, + pciw_pci0_txExF$EMPTY_N, + pciw_pci0_txExF$ENQ, + pciw_pci0_txExF$FULL_N; + + // ports of submodule pciw_pci0_txHeadF + wire [30 : 0] pciw_pci0_txHeadF$D_IN, pciw_pci0_txHeadF$D_OUT; + wire pciw_pci0_txHeadF$CLR, + pciw_pci0_txHeadF$DEQ, + pciw_pci0_txHeadF$EMPTY_N, + pciw_pci0_txHeadF$ENQ, + pciw_pci0_txHeadF$FULL_N; + + // ports of submodule pciw_pci0_txInF + wire [152 : 0] pciw_pci0_txInF$D_IN, pciw_pci0_txInF$D_OUT; + wire pciw_pci0_txInF$CLR, + pciw_pci0_txInF$DEQ, + pciw_pci0_txInF$EMPTY_N, + pciw_pci0_txInF$ENQ, + pciw_pci0_txInF$FULL_N; + + // ports of submodule pciw_pci0_txOutF + wire [154 : 0] pciw_pci0_txOutF$D_IN, pciw_pci0_txOutF$D_OUT; + wire pciw_pci0_txOutF$CLR, + pciw_pci0_txOutF$DEQ, + pciw_pci0_txOutF$EMPTY_N, + pciw_pci0_txOutF$ENQ, + pciw_pci0_txOutF$FULL_N; + + // rule scheduling signals + wire WILL_FIRE_RL_pciw_pci0_rxInF_reset, + WILL_FIRE_RL_pciw_pci0_rx_destage, + WILL_FIRE_RL_pciw_pci0_rx_enstage, + WILL_FIRE_RL_pciw_pci0_txOutF_reset, + WILL_FIRE_RL_pciw_pci0_tx_destage, + WILL_FIRE_RL_pciw_pci0_tx_enstage, + WILL_FIRE_RL_pciw_pci0_tx_exstage; + + // inputs to muxes for submodule ports + wire MUX_pciw_pci0_rxInF_levelsValid$write_1__SEL_3; + + // remaining internal signals + reg [15 : 0] IF_IF_IF_pciw_pci0_rxInFlight_76_THEN_pciw_pci_ETC___d787; + wire [255 : 0] _0_CONCAT_pciw_pci0_rxDws_new_data_wget__2_BITS_ETC___d832, + _0_CONCAT_pciw_pci0_txDws_new_data_wget__8_BITS_ETC___d833, + pciw_pci0_rxDws_vec_3_SRL_IF_pciw_pci0_rxDws_d_ETC___d834, + pciw_pci0_txDws_vec_9_SRL_IF_pciw_pci0_txDws_d_ETC___d835; + wire [127 : 0] x__h14478, x__h4523, x_data__h27615, x_data__h46011; + wire [95 : 0] IF_pciw_pci0_txInFlight_49_THEN_pciw_pci0_txDw_ETC___d481; + wire [31 : 0] IF_pciw_pci0_txHeadF_first__59_BIT_11_60_THEN__ETC___d468, + IF_pciw_pci0_txInFlight_49_THEN_pciw_pci0_txDw_ETC___d492, + pciw_pci0_pcie_ep_ava_debug__52_OR_0_CONCAT_pc_ETC___d831, + x__h56415, + x__h56417, + x__h56419, + x__h56421, + x__h56423, + x__h56425, + x__h56427, + x__h56429, + x__h56431, + x__h56433, + x__h56435, + x__h56437, + x__h56439, + x__h56441, + x__h56443, + x__h56445, + x__h56447, + x__h56449, + x__h56451, + y__h56416, + y__h56418, + y__h56420, + y__h56422, + y__h56424, + y__h56426, + y__h56428, + y__h56430, + y__h56432, + y__h56434, + y__h56436, + y__h56438, + y__h56440, + y__h56442, + y__h56444, + y__h56446, + y__h56448, + y__h56450, + y__h56452, + y__h56454; + wire [15 : 0] x_be__h27614; + wire [10 : 0] IF_IF_NOT_pciw_pci0_txInFlight_49_57_AND_NOT_I_ETC__q1, + IF_IF_pciw_pci0_rxInFlight_76_THEN_pciw_pci0_r_ETC__q2, + IF_NOT_pciw_pci0_txInFlight_49_57_AND_NOT_IF_p_ETC___d837, + IF_pciw_pci0_rxEofF_notEmpty__62_AND_pciw_pci0_ETC___d288, + IF_pciw_pci0_rxInFlight_76_THEN_pciw_pci0_rxDw_ETC___d769, + IF_pciw_pci0_txEofF_notEmpty__52_AND_pciw_pci0_ETC___d523, + IF_pciw_pci0_txInFlight_49_THEN_pciw_pci0_txDw_ETC___d838; + wire [8 : 0] x__h15731, x__h5776; + wire [7 : 0] INV_swReg_35_BIT_0_36_XOR_swReg_35_BIT_1_37_38_ETC___d764, + bar___1__h22106, + x__h18832, + x__h8877, + x_hit__h22096; + wire [2 : 0] IF_pciw_pci0_rxDws_delta_deq_whas__3_THEN_pciw_ETC___d801, + IF_pciw_pci0_rxDws_delta_enq_whas__8_THEN_pciw_ETC___d771, + IF_pciw_pci0_txDws_delta_deq_whas__9_THEN_pciw_ETC___d804, + IF_pciw_pci0_txDws_delta_enq_whas__4_THEN_pciw_ETC___d770; + wire NOT_pciw_pci0_txEofF_notEmpty__52_53_OR_NOT_pc_ETC___d495, + pciw_pci0_rxDws_num_full_7_ULE_4___d836, + pciw_pci0_txDws_num_full_3_ULE_4___d774, + pciw_pci0_txEofF_notEmpty__52_AND_pciw_pci0_tx_ETC___d817, + pciw_pci0_txOutF_i_notFull__48_AND_pciw_pci0_t_ETC___d502, + swParity__h48492, + z__h55844, + z__h55851, + z__h55858, + z__h55865, + z__h55872, + z__h55879, + z__h56129, + z__h56136, + z__h56143, + z__h56150, + z__h56157, + z__h56164, + z__h56171, + z__h56178, + z__h56185, + z__h56192, + z__h56199, + z__h56206, + z__h56213, + z__h56220, + z__h56227, + z__h56234, + z__h56241, + z__h56248, + z__h56255, + z__h56262, + z__h56269, + z__h56276, + z__h56283, + z__h56290, + z__h56297, + z__h56304, + z__h56311, + z__h56318, + z__h56325, + z__h56332; + + // oscillator and gates for output clock p125clk + assign p125clk = pciw_pci0_pcie_ep$ava_core_clk_out ; + assign CLK_GATE_p125clk = 1'b1 ; + + // output resets + assign p125rst = pciw_pci0_pcie_ep$ava_srstn ; + + // value method pcie_tx + assign pcie_tx = pciw_pci0_pcie_ep$pcie_tx_out ; + + // value method led + assign led = ledReg ; + + // value method hsmc_out + assign hsmc_out = hsmcReg ; + + // value method led_cathode + assign led_cathode = 20'd0 ; + + // value method led_anode + assign led_anode = { 4'h8, ledReg } ; + + // value method lcd_db + assign lcd_db = lcd_ctrl$db ; + + // value method lcd_e + assign lcd_e = lcd_ctrl$e ; + + // value method lcd_rs + assign lcd_rs = lcd_ctrl$rs ; + + // value method lcd_rw + assign lcd_rw = lcd_ctrl$rw ; + + // value method gps_ppsSyncOut + assign gps_ppsSyncOut = ctop$gps_ppsSyncOut ; + + // value method flash_addr + assign flash_addr = flash0$flash_addr ; + + // value method flash_ce_n + assign flash_ce_n = flash0$flash_ce_n ; + + // value method flash_oe_n + assign flash_oe_n = flash0$flash_oe_n ; + + // value method flash_we_n + assign flash_we_n = flash0$flash_we_n ; + + // value method flash_wp_n + assign flash_wp_n = flash0$flash_wp_n ; + + // value method flash_rst_n + assign flash_rst_n = flash0$flash_rst_n ; + + // value method flash_adv_n + assign flash_adv_n = flash0$flash_adv_n ; + + // value method dram_addr + assign dram_addr = dram0$dram_addr ; + + // value method dram_ba + assign dram_ba = dram0$dram_ba ; + + // value method dram_ras_n + assign dram_ras_n = dram0$dram_ras_n ; + + // value method dram_cas_n + assign dram_cas_n = dram0$dram_cas_n ; + + // value method dram_we_n + assign dram_we_n = dram0$dram_we_n ; + + // value method dram_reset_n + assign dram_reset_n = dram0$dram_reset_n ; + + // value method dram_cs_n + assign dram_cs_n = dram0$dram_cs_n ; + + // value method dram_odt + assign dram_odt = dram0$dram_odt ; + + // value method dram_cke + assign dram_cke = dram0$dram_cke ; + + // value method dram_dm + assign dram_dm = dram0$dram_dm ; + + // value method dram_ck_p + assign dram_ck_p = dram0$dram_ck_p ; + + // value method dram_ck_n + assign dram_ck_n = dram0$dram_ck_n ; + + // submodule ctop + mkCTop4B ctop(.pciDevice(pciDevice), + .CLK_sys0_clk(sys0_clk), + .RST_N_sys0_rst(sys0_rstn), + .CLK(pciw_pci0_pcie_ep$ava_core_clk_out), + .RST_N(pciw_pci0_pcie_ep$ava_srstn), + .cpServer_request_put(ctop$cpServer_request_put), + .gps_ppsSyncIn_x(ctop$gps_ppsSyncIn_x), + .server_request_put(ctop$server_request_put), + .switch_x(ctop$switch_x), + .wci_m_0_SData(ctop$wci_m_0_SData), + .wci_m_0_SFlag(ctop$wci_m_0_SFlag), + .wci_m_0_SResp(ctop$wci_m_0_SResp), + .wci_m_1_SData(ctop$wci_m_1_SData), + .wci_m_1_SFlag(ctop$wci_m_1_SFlag), + .wci_m_1_SResp(ctop$wci_m_1_SResp), + .wci_m_2_SData(ctop$wci_m_2_SData), + .wci_m_2_SFlag(ctop$wci_m_2_SFlag), + .wci_m_2_SResp(ctop$wci_m_2_SResp), + .wci_m_3_SData(ctop$wci_m_3_SData), + .wci_m_3_SFlag(ctop$wci_m_3_SFlag), + .wci_m_3_SResp(ctop$wci_m_3_SResp), + .wci_m_4_SData(ctop$wci_m_4_SData), + .wci_m_4_SFlag(ctop$wci_m_4_SFlag), + .wci_m_4_SResp(ctop$wci_m_4_SResp), + .wmemiM0_SData(ctop$wmemiM0_SData), + .wmemiM0_SResp(ctop$wmemiM0_SResp), + .wsi_s_adc_MBurstLength(ctop$wsi_s_adc_MBurstLength), + .wsi_s_adc_MByteEn(ctop$wsi_s_adc_MByteEn), + .wsi_s_adc_MCmd(ctop$wsi_s_adc_MCmd), + .wsi_s_adc_MData(ctop$wsi_s_adc_MData), + .wsi_s_adc_MReqInfo(ctop$wsi_s_adc_MReqInfo), + .EN_server_request_put(ctop$EN_server_request_put), + .EN_server_response_get(ctop$EN_server_response_get), + .EN_cpServer_request_put(ctop$EN_cpServer_request_put), + .EN_cpServer_response_get(ctop$EN_cpServer_response_get), + .wci_m_0_SThreadBusy(ctop$wci_m_0_SThreadBusy), + .wci_m_1_SThreadBusy(ctop$wci_m_1_SThreadBusy), + .wci_m_2_SThreadBusy(ctop$wci_m_2_SThreadBusy), + .wci_m_3_SThreadBusy(ctop$wci_m_3_SThreadBusy), + .wci_m_4_SThreadBusy(ctop$wci_m_4_SThreadBusy), + .wsi_s_adc_MReqLast(ctop$wsi_s_adc_MReqLast), + .wsi_s_adc_MBurstPrecise(ctop$wsi_s_adc_MBurstPrecise), + .wsi_s_adc_MReset_n(ctop$wsi_s_adc_MReset_n), + .wsi_m_dac_SThreadBusy(ctop$wsi_m_dac_SThreadBusy), + .wsi_m_dac_SReset_n(ctop$wsi_m_dac_SReset_n), + .wmemiM0_SRespLast(ctop$wmemiM0_SRespLast), + .wmemiM0_SCmdAccept(ctop$wmemiM0_SCmdAccept), + .wmemiM0_SDataAccept(ctop$wmemiM0_SDataAccept), + .RDY_server_request_put(ctop$RDY_server_request_put), + .server_response_get(ctop$server_response_get), + .RDY_server_response_get(ctop$RDY_server_response_get), + .RDY_cpServer_request_put(), + .cpServer_response_get(), + .RDY_cpServer_response_get(), + .led(ctop$led), + .wci_m_0_MCmd(), + .wci_m_0_MAddrSpace(), + .wci_m_0_MByteEn(), + .wci_m_0_MAddr(), + .wci_m_0_MData(), + .wci_m_0_MFlag(), + .wci_m_1_MCmd(ctop$wci_m_1_MCmd), + .wci_m_1_MAddrSpace(ctop$wci_m_1_MAddrSpace), + .wci_m_1_MByteEn(ctop$wci_m_1_MByteEn), + .wci_m_1_MAddr(ctop$wci_m_1_MAddr), + .wci_m_1_MData(ctop$wci_m_1_MData), + .wci_m_1_MFlag(ctop$wci_m_1_MFlag), + .wci_m_2_MCmd(), + .wci_m_2_MAddrSpace(), + .wci_m_2_MByteEn(), + .wci_m_2_MAddr(), + .wci_m_2_MData(), + .wci_m_2_MFlag(), + .wci_m_3_MCmd(), + .wci_m_3_MAddrSpace(), + .wci_m_3_MByteEn(), + .wci_m_3_MAddr(), + .wci_m_3_MData(), + .wci_m_3_MFlag(), + .wci_m_4_MCmd(ctop$wci_m_4_MCmd), + .wci_m_4_MAddrSpace(ctop$wci_m_4_MAddrSpace), + .wci_m_4_MByteEn(ctop$wci_m_4_MByteEn), + .wci_m_4_MAddr(ctop$wci_m_4_MAddr), + .wci_m_4_MData(ctop$wci_m_4_MData), + .wci_m_4_MFlag(ctop$wci_m_4_MFlag), + .cpNow(), + .RDY_cpNow(), + .wsi_s_adc_SThreadBusy(), + .wsi_s_adc_SReset_n(), + .wsi_m_dac_MCmd(), + .wsi_m_dac_MReqLast(), + .wsi_m_dac_MBurstPrecise(), + .wsi_m_dac_MBurstLength(), + .wsi_m_dac_MData(), + .wsi_m_dac_MByteEn(), + .wsi_m_dac_MReqInfo(), + .wsi_m_dac_MReset_n(), + .wmemiM0_MCmd(ctop$wmemiM0_MCmd), + .wmemiM0_MReqLast(ctop$wmemiM0_MReqLast), + .wmemiM0_MAddr(ctop$wmemiM0_MAddr), + .wmemiM0_MBurstLength(ctop$wmemiM0_MBurstLength), + .wmemiM0_MDataValid(ctop$wmemiM0_MDataValid), + .wmemiM0_MDataLast(ctop$wmemiM0_MDataLast), + .wmemiM0_MData(ctop$wmemiM0_MData), + .wmemiM0_MDataByteEn(ctop$wmemiM0_MDataByteEn), + .wmemiM0_MReset_n(ctop$wmemiM0_MReset_n), + .gps_ppsSyncOut(ctop$gps_ppsSyncOut), + .RST_N_wci_m_0(), + .RST_N_wci_m_1(ctop$RST_N_wci_m_1), + .RST_N_wci_m_2(), + .RST_N_wci_m_3(), + .RST_N_wci_m_4(ctop$RST_N_wci_m_4)); + + // submodule dram0 + mkDramServer_s4 #(.hasDebugLogic(1'd0)) dram0(.CLK_sys0_clk(sys0_clk), + .RST_N_sys0_rstn(sys0_rstn), + .wciS0_Clk(pciw_pci0_pcie_ep$ava_core_clk_out), + .wciS0_MReset_n(ctop$RST_N_wci_m_4), + .dram_rdn_i(dram0$dram_rdn_i), + .dram_rup_i(dram0$dram_rup_i), + .wciS0_MAddr(dram0$wciS0_MAddr), + .wciS0_MAddrSpace(dram0$wciS0_MAddrSpace), + .wciS0_MByteEn(dram0$wciS0_MByteEn), + .wciS0_MCmd(dram0$wciS0_MCmd), + .wciS0_MData(dram0$wciS0_MData), + .wciS0_MFlag(dram0$wciS0_MFlag), + .wmemiS0_MAddr(dram0$wmemiS0_MAddr), + .wmemiS0_MBurstLength(dram0$wmemiS0_MBurstLength), + .wmemiS0_MCmd(dram0$wmemiS0_MCmd), + .wmemiS0_MData(dram0$wmemiS0_MData), + .wmemiS0_MDataByteEn(dram0$wmemiS0_MDataByteEn), + .wmemiS0_MReqLast(dram0$wmemiS0_MReqLast), + .wmemiS0_MDataValid(dram0$wmemiS0_MDataValid), + .wmemiS0_MDataLast(dram0$wmemiS0_MDataLast), + .wmemiS0_MReset_n(dram0$wmemiS0_MReset_n), + .wciS0_SResp(dram0$wciS0_SResp), + .wciS0_SData(dram0$wciS0_SData), + .wciS0_SThreadBusy(dram0$wciS0_SThreadBusy), + .wciS0_SFlag(dram0$wciS0_SFlag), + .wmemiS0_SResp(dram0$wmemiS0_SResp), + .wmemiS0_SRespLast(dram0$wmemiS0_SRespLast), + .wmemiS0_SData(dram0$wmemiS0_SData), + .wmemiS0_SCmdAccept(dram0$wmemiS0_SCmdAccept), + .wmemiS0_SDataAccept(dram0$wmemiS0_SDataAccept), + .dram_addr(dram0$dram_addr), + .dram_ba(dram0$dram_ba), + .dram_ras_n(dram0$dram_ras_n), + .dram_cas_n(dram0$dram_cas_n), + .dram_we_n(dram0$dram_we_n), + .dram_reset_n(dram0$dram_reset_n), + .dram_cs_n(dram0$dram_cs_n), + .dram_odt(dram0$dram_odt), + .dram_cke(dram0$dram_cke), + .dram_dm(dram0$dram_dm), + .dram_ck_p(dram0$dram_ck_p), + .dram_ck_n(dram0$dram_ck_n), + .dram_io_dq(dram_io_dq), + .dram_io_dqs_p(dram_io_dqs_p), + .dram_io_dqs_n(dram_io_dqs_n)); + + // submodule flash0 + mkFlashWorker #(.hasDebugLogic(1'd1)) flash0(.wciS0_Clk(pciw_pci0_pcie_ep$ava_core_clk_out), + .wciS0_MReset_n(ctop$RST_N_wci_m_1), + .flash_fwait_i(flash0$flash_fwait_i), + .wciS0_MAddr(flash0$wciS0_MAddr), + .wciS0_MAddrSpace(flash0$wciS0_MAddrSpace), + .wciS0_MByteEn(flash0$wciS0_MByteEn), + .wciS0_MCmd(flash0$wciS0_MCmd), + .wciS0_MData(flash0$wciS0_MData), + .wciS0_MFlag(flash0$wciS0_MFlag), + .wciS0_SResp(flash0$wciS0_SResp), + .wciS0_SData(flash0$wciS0_SData), + .wciS0_SThreadBusy(flash0$wciS0_SThreadBusy), + .wciS0_SFlag(flash0$wciS0_SFlag), + .flash_addr(flash0$flash_addr), + .flash_ce_n(flash0$flash_ce_n), + .flash_oe_n(flash0$flash_oe_n), + .flash_we_n(flash0$flash_we_n), + .flash_wp_n(flash0$flash_wp_n), + .flash_rst_n(flash0$flash_rst_n), + .flash_adv_n(flash0$flash_adv_n), + .flash_io_dq(flash_io_dq)); + + // submodule lcd_ctrl + mkLCDController lcd_ctrl(.CLK(pciw_pci0_pcie_ep$ava_core_clk_out), + .RST_N(pciw_pci0_pcie_ep$ava_srstn), + .setLine1_text(lcd_ctrl$setLine1_text), + .setLine2_text(lcd_ctrl$setLine2_text), + .EN_setLine1(lcd_ctrl$EN_setLine1), + .EN_setLine2(lcd_ctrl$EN_setLine2), + .db(lcd_ctrl$db), + .e(lcd_ctrl$e), + .rs(lcd_ctrl$rs), + .rw(lcd_ctrl$rw)); + + // submodule pciw_aliveLed_sb + SyncBit #(.init(1'd0)) pciw_aliveLed_sb(.sCLK(sys0_clk), + .dCLK(pciw_pci0_pcie_ep$ava_core_clk_out), + .sRST(sys0_rstn), + .sD_IN(pciw_aliveLed_sb$sD_IN), + .sEN(pciw_aliveLed_sb$sEN), + .dD_OUT(pciw_aliveLed_sb$dD_OUT)); + + // submodule pciw_i2pF + FIFO2 #(.width(32'd153), + .guarded(32'd1)) pciw_i2pF(.RST(pciw_pci0_pcie_ep$ava_srstn), + .CLK(pciw_pci0_pcie_ep$ava_core_clk_out), + .D_IN(pciw_i2pF$D_IN), + .ENQ(pciw_i2pF$ENQ), + .DEQ(pciw_i2pF$DEQ), + .CLR(pciw_i2pF$CLR), + .D_OUT(pciw_i2pF$D_OUT), + .FULL_N(pciw_i2pF$FULL_N), + .EMPTY_N(pciw_i2pF$EMPTY_N)); + + // submodule pciw_linkLed_sb + SyncBit #(.init(1'd0)) pciw_linkLed_sb(.sCLK(sys0_clk), + .dCLK(pciw_pci0_pcie_ep$ava_core_clk_out), + .sRST(sys0_rstn), + .sD_IN(pciw_linkLed_sb$sD_IN), + .sEN(pciw_linkLed_sb$sEN), + .dD_OUT(pciw_linkLed_sb$dD_OUT)); + + // submodule pciw_p2iF + FIFO2 #(.width(32'd153), + .guarded(32'd1)) pciw_p2iF(.RST(pciw_pci0_pcie_ep$ava_srstn), + .CLK(pciw_pci0_pcie_ep$ava_core_clk_out), + .D_IN(pciw_p2iF$D_IN), + .ENQ(pciw_p2iF$ENQ), + .DEQ(pciw_p2iF$DEQ), + .CLR(pciw_p2iF$CLR), + .D_OUT(pciw_p2iF$D_OUT), + .FULL_N(pciw_p2iF$FULL_N), + .EMPTY_N(pciw_p2iF$EMPTY_N)); + + // submodule pciw_pci0_pcie_ep + pcie_hip_s4gx_gen2_x4_128_wrapper pciw_pci0_pcie_ep(.sys0_clk(sys0_clk), + .sys0_rstn(sys0_rstn), + .pcie_clk(pcie_clk), + .pcie_rstn(pcie_rstn), + .pcie_rx_in(pciw_pci0_pcie_ep$pcie_rx_in), + .rx_st_mask0(pciw_pci0_pcie_ep$rx_st_mask0), + .rx_st_ready0(pciw_pci0_pcie_ep$rx_st_ready0), + .tx_st_data0(pciw_pci0_pcie_ep$tx_st_data0), + .tx_st_empty0(pciw_pci0_pcie_ep$tx_st_empty0), + .tx_st_eop0(pciw_pci0_pcie_ep$tx_st_eop0), + .tx_st_err0(pciw_pci0_pcie_ep$tx_st_err0), + .tx_st_sop0(pciw_pci0_pcie_ep$tx_st_sop0), + .tx_st_valid0(pciw_pci0_pcie_ep$tx_st_valid0), + .tl_cfg_add(pciw_pci0_pcie_ep$tl_cfg_add), + .tl_cfg_ctl(pciw_pci0_pcie_ep$tl_cfg_ctl), + .tl_cfg_ctl_wr(pciw_pci0_pcie_ep$tl_cfg_ctl_wr), + .tl_cfg_sts(), + .tl_cfg_sts_wr(), + .pcie_tx_out(pciw_pci0_pcie_ep$pcie_tx_out), + .ava_alive(pciw_pci0_pcie_ep$ava_alive), + .ava_lnk_up(pciw_pci0_pcie_ep$ava_lnk_up), + .ava_debug(pciw_pci0_pcie_ep$ava_debug), + .rx_st_valid0(pciw_pci0_pcie_ep$rx_st_valid0), + .rx_st_bardec0(pciw_pci0_pcie_ep$rx_st_bardec0), + .rx_st_be0(pciw_pci0_pcie_ep$rx_st_be0), + .rx_st_data0(pciw_pci0_pcie_ep$rx_st_data0), + .rx_st_sop0(pciw_pci0_pcie_ep$rx_st_sop0), + .rx_st_eop0(pciw_pci0_pcie_ep$rx_st_eop0), + .rx_st_empty0(pciw_pci0_pcie_ep$rx_st_empty0), + .rx_st_err0(), + .tx_st_ready0(pciw_pci0_pcie_ep$tx_st_ready0), + .tx_cred0(), + .tx_fifo_empty0(), + .ava_core_clk_out(pciw_pci0_pcie_ep$ava_core_clk_out), + .ava_srstn(pciw_pci0_pcie_ep$ava_srstn)); + + // submodule pciw_pci0_rxEofF + FIFO2 #(.width(32'd3), + .guarded(32'd1)) pciw_pci0_rxEofF(.RST(pciw_pci0_pcie_ep$ava_srstn), + .CLK(pciw_pci0_pcie_ep$ava_core_clk_out), + .D_IN(pciw_pci0_rxEofF$D_IN), + .ENQ(pciw_pci0_rxEofF$ENQ), + .DEQ(pciw_pci0_rxEofF$DEQ), + .CLR(pciw_pci0_rxEofF$CLR), + .D_OUT(), + .FULL_N(pciw_pci0_rxEofF$FULL_N), + .EMPTY_N(pciw_pci0_rxEofF$EMPTY_N)); + + // submodule pciw_pci0_rxHeadF + FIFO2 #(.width(32'd31), + .guarded(32'd1)) pciw_pci0_rxHeadF(.RST(pciw_pci0_pcie_ep$ava_srstn), + .CLK(pciw_pci0_pcie_ep$ava_core_clk_out), + .D_IN(pciw_pci0_rxHeadF$D_IN), + .ENQ(pciw_pci0_rxHeadF$ENQ), + .DEQ(pciw_pci0_rxHeadF$DEQ), + .CLR(pciw_pci0_rxHeadF$CLR), + .D_OUT(pciw_pci0_rxHeadF$D_OUT), + .FULL_N(pciw_pci0_rxHeadF$FULL_N), + .EMPTY_N(pciw_pci0_rxHeadF$EMPTY_N)); + + // submodule pciw_pci0_rxInF + SizedFIFO #(.p1width(32'd155), + .p2depth(32'd32), + .p3cntr_width(32'd5), + .guarded(32'd1)) pciw_pci0_rxInF(.RST(pciw_pci0_pcie_ep$ava_srstn), + .CLK(pciw_pci0_pcie_ep$ava_core_clk_out), + .D_IN(pciw_pci0_rxInF$D_IN), + .ENQ(pciw_pci0_rxInF$ENQ), + .DEQ(pciw_pci0_rxInF$DEQ), + .CLR(pciw_pci0_rxInF$CLR), + .D_OUT(pciw_pci0_rxInF$D_OUT), + .FULL_N(pciw_pci0_rxInF$FULL_N), + .EMPTY_N(pciw_pci0_rxInF$EMPTY_N)); + + // submodule pciw_pci0_rxOutF + FIFO2 #(.width(32'd153), + .guarded(32'd1)) pciw_pci0_rxOutF(.RST(pciw_pci0_pcie_ep$ava_srstn), + .CLK(pciw_pci0_pcie_ep$ava_core_clk_out), + .D_IN(pciw_pci0_rxOutF$D_IN), + .ENQ(pciw_pci0_rxOutF$ENQ), + .DEQ(pciw_pci0_rxOutF$DEQ), + .CLR(pciw_pci0_rxOutF$CLR), + .D_OUT(pciw_pci0_rxOutF$D_OUT), + .FULL_N(pciw_pci0_rxOutF$FULL_N), + .EMPTY_N(pciw_pci0_rxOutF$EMPTY_N)); + + // submodule pciw_pci0_txEofF + FIFO2 #(.width(32'd3), + .guarded(32'd1)) pciw_pci0_txEofF(.RST(pciw_pci0_pcie_ep$ava_srstn), + .CLK(pciw_pci0_pcie_ep$ava_core_clk_out), + .D_IN(pciw_pci0_txEofF$D_IN), + .ENQ(pciw_pci0_txEofF$ENQ), + .DEQ(pciw_pci0_txEofF$DEQ), + .CLR(pciw_pci0_txEofF$CLR), + .D_OUT(), + .FULL_N(pciw_pci0_txEofF$FULL_N), + .EMPTY_N(pciw_pci0_txEofF$EMPTY_N)); + + // submodule pciw_pci0_txExF + FIFO2 #(.width(32'd1), + .guarded(32'd1)) pciw_pci0_txExF(.RST(pciw_pci0_pcie_ep$ava_srstn), + .CLK(pciw_pci0_pcie_ep$ava_core_clk_out), + .D_IN(pciw_pci0_txExF$D_IN), + .ENQ(pciw_pci0_txExF$ENQ), + .DEQ(pciw_pci0_txExF$DEQ), + .CLR(pciw_pci0_txExF$CLR), + .D_OUT(), + .FULL_N(pciw_pci0_txExF$FULL_N), + .EMPTY_N(pciw_pci0_txExF$EMPTY_N)); + + // submodule pciw_pci0_txHeadF + FIFO2 #(.width(32'd31), + .guarded(32'd1)) pciw_pci0_txHeadF(.RST(pciw_pci0_pcie_ep$ava_srstn), + .CLK(pciw_pci0_pcie_ep$ava_core_clk_out), + .D_IN(pciw_pci0_txHeadF$D_IN), + .ENQ(pciw_pci0_txHeadF$ENQ), + .DEQ(pciw_pci0_txHeadF$DEQ), + .CLR(pciw_pci0_txHeadF$CLR), + .D_OUT(pciw_pci0_txHeadF$D_OUT), + .FULL_N(pciw_pci0_txHeadF$FULL_N), + .EMPTY_N(pciw_pci0_txHeadF$EMPTY_N)); + + // submodule pciw_pci0_txInF + FIFO2 #(.width(32'd153), + .guarded(32'd1)) pciw_pci0_txInF(.RST(pciw_pci0_pcie_ep$ava_srstn), + .CLK(pciw_pci0_pcie_ep$ava_core_clk_out), + .D_IN(pciw_pci0_txInF$D_IN), + .ENQ(pciw_pci0_txInF$ENQ), + .DEQ(pciw_pci0_txInF$DEQ), + .CLR(pciw_pci0_txInF$CLR), + .D_OUT(pciw_pci0_txInF$D_OUT), + .FULL_N(pciw_pci0_txInF$FULL_N), + .EMPTY_N(pciw_pci0_txInF$EMPTY_N)); + + // submodule pciw_pci0_txOutF + SizedFIFO #(.p1width(32'd155), + .p2depth(32'd515), + .p3cntr_width(32'd10), + .guarded(32'd1)) pciw_pci0_txOutF(.RST(pciw_pci0_pcie_ep$ava_srstn), + .CLK(pciw_pci0_pcie_ep$ava_core_clk_out), + .D_IN(pciw_pci0_txOutF$D_IN), + .ENQ(pciw_pci0_txOutF$ENQ), + .DEQ(pciw_pci0_txOutF$DEQ), + .CLR(pciw_pci0_txOutF$CLR), + .D_OUT(pciw_pci0_txOutF$D_OUT), + .FULL_N(pciw_pci0_txOutF$FULL_N), + .EMPTY_N(pciw_pci0_txOutF$EMPTY_N)); + + // rule RL_pciw_pci0_rx_destage + assign WILL_FIRE_RL_pciw_pci0_rx_destage = + pciw_pci0_rxDws_num_full != 4'd0 && pciw_pci0_rxHeadF$EMPTY_N && + pciw_pci0_rxOutF$FULL_N && + (pciw_pci0_rxDws_num_full >= 4'd4 || pciw_pci0_rxEofF$EMPTY_N) ; + + // rule RL_pciw_pci0_rx_enstage + assign WILL_FIRE_RL_pciw_pci0_rx_enstage = + pciw_pci0_rxInF$EMPTY_N && + (!pciw_pci0_rxInF$D_OUT[153] || pciw_pci0_rxHeadF$FULL_N) && + (!pciw_pci0_rxInF$D_OUT[152] || pciw_pci0_rxEofF$FULL_N) && + pciw_pci0_rxDws_num_empty >= 4'd4 ; + + // rule RL_pciw_pci0_tx_exstage + assign WILL_FIRE_RL_pciw_pci0_tx_exstage = + pciw_pci0_txOutF$EMPTY_N && pciw_pci0_txReadyD && + pciw_pci0_txExF$EMPTY_N ; + + // rule RL_pciw_pci0_tx_destage + assign WILL_FIRE_RL_pciw_pci0_tx_destage = + pciw_pci0_txDws_num_full != 4'd0 && + pciw_pci0_txOutF_i_notFull__48_AND_pciw_pci0_t_ETC___d502 && + (pciw_pci0_txDws_num_full >= 4'd4 || pciw_pci0_txEofF$EMPTY_N) ; + + // rule RL_pciw_pci0_tx_enstage + assign WILL_FIRE_RL_pciw_pci0_tx_enstage = + pciw_pci0_txInF$EMPTY_N && + (!pciw_pci0_txInF$D_OUT[152] || pciw_pci0_txHeadF$FULL_N) && + (!pciw_pci0_txInF$D_OUT[151] || pciw_pci0_txEofF$FULL_N) && + pciw_pci0_txDws_num_empty >= 4'd4 ; + + // rule RL_pciw_pci0_rxInF_reset + assign WILL_FIRE_RL_pciw_pci0_rxInF_reset = + MUX_pciw_pci0_rxInF_levelsValid$write_1__SEL_3 || + WILL_FIRE_RL_pciw_pci0_rx_enstage ; + + // rule RL_pciw_pci0_txOutF_reset + assign WILL_FIRE_RL_pciw_pci0_txOutF_reset = + WILL_FIRE_RL_pciw_pci0_tx_destage || + WILL_FIRE_RL_pciw_pci0_tx_exstage ; + + // inputs to muxes for submodule ports + assign MUX_pciw_pci0_rxInF_levelsValid$write_1__SEL_3 = + pciw_pci0_rxInF$FULL_N && pciw_pci0_pcie_ep$rx_st_valid0 ; + + // inlined wires + assign pciw_pci0_avaTxValid$wget = 1'd1 ; + assign pciw_pci0_avaTxValid$whas = WILL_FIRE_RL_pciw_pci0_tx_exstage ; + assign pciw_pci0_avaTxErr$wget = 1'b0 ; + assign pciw_pci0_avaTxErr$whas = 1'b0 ; + assign pciw_pci0_avaTxSop$wget = pciw_pci0_txOutF$D_OUT[153] ; + assign pciw_pci0_avaTxSop$whas = WILL_FIRE_RL_pciw_pci0_tx_exstage ; + assign pciw_pci0_avaTxEop$wget = pciw_pci0_txOutF$D_OUT[152] ; + assign pciw_pci0_avaTxEop$whas = WILL_FIRE_RL_pciw_pci0_tx_exstage ; + assign pciw_pci0_avaTxEmpty$wget = pciw_pci0_txOutF$D_OUT[154] ; + assign pciw_pci0_avaTxEmpty$whas = WILL_FIRE_RL_pciw_pci0_tx_exstage ; + assign pciw_pci0_rxDws_delta_enq$wget = + (pciw_pci0_rxInF$D_OUT[153] && !pciw_pci0_rxInF$D_OUT[30] && + !pciw_pci0_rxInF$D_OUT[29]) ? + 3'd3 : + ((pciw_pci0_rxInF$D_OUT[153] && + (pciw_pci0_rxInF$D_OUT[29] || + pciw_pci0_rxInF$D_OUT[30] && pciw_pci0_rxInF$D_OUT[66])) ? + 3'd4 : + ((pciw_pci0_rxInF$D_OUT[153] && pciw_pci0_rxInF$D_OUT[30] && + !pciw_pci0_rxInF$D_OUT[29] && + !pciw_pci0_rxInF$D_OUT[66]) ? + 3'd3 : + ((!pciw_pci0_rxInF$D_OUT[153] && + !pciw_pci0_rxInF$D_OUT[154] && + pciw_pci0_rxInF$D_OUT[143:128] == 16'hFFFF) ? + 3'd4 : + ((!pciw_pci0_rxInF$D_OUT[153] && + !pciw_pci0_rxInF$D_OUT[154] && + pciw_pci0_rxInF$D_OUT[143:128] == 16'h0FFF) ? + 3'd3 : + ((!pciw_pci0_rxInF$D_OUT[153] && + pciw_pci0_rxInF$D_OUT[154] && + pciw_pci0_rxInF$D_OUT[143:136] == 8'hFF) ? + 3'd2 : + ((!pciw_pci0_rxInF$D_OUT[153] && + pciw_pci0_rxInF$D_OUT[154] && + pciw_pci0_rxInF$D_OUT[143:136] == 8'h0F) ? + 3'd1 : + 3'd0)))))) ; + assign pciw_pci0_rxDws_delta_enq$whas = WILL_FIRE_RL_pciw_pci0_rx_enstage ; + assign pciw_pci0_rxDws_delta_deq$wget = + IF_IF_pciw_pci0_rxInFlight_76_THEN_pciw_pci0_r_ETC__q2[2:0] ; + assign pciw_pci0_rxDws_delta_deq$whas = WILL_FIRE_RL_pciw_pci0_rx_destage ; + assign pciw_pci0_rxDws_new_data$wget = + pciw_pci0_rxInF$D_OUT[153] ? + { pciw_pci0_rxInF$D_OUT[29] ? + { pciw_pci0_rxInF$D_OUT[103:96], + pciw_pci0_rxInF$D_OUT[111:104], + pciw_pci0_rxInF$D_OUT[119:112], + pciw_pci0_rxInF$D_OUT[127:120] } : + pciw_pci0_rxInF$D_OUT[127:96], + pciw_pci0_rxInF$D_OUT[71:64], + pciw_pci0_rxInF$D_OUT[79:72], + pciw_pci0_rxInF$D_OUT[87:80], + pciw_pci0_rxInF$D_OUT[95:88], + pciw_pci0_rxInF$D_OUT[39:32], + pciw_pci0_rxInF$D_OUT[47:40], + pciw_pci0_rxInF$D_OUT[55:48], + pciw_pci0_rxInF$D_OUT[63:56], + pciw_pci0_rxInF$D_OUT[7:0], + pciw_pci0_rxInF$D_OUT[15:8], + pciw_pci0_rxInF$D_OUT[23:16], + pciw_pci0_rxInF$D_OUT[31:24] } : + pciw_pci0_rxInF$D_OUT[127:0] ; + assign pciw_pci0_rxDws_new_data$whas = WILL_FIRE_RL_pciw_pci0_rx_enstage ; + assign pciw_pci0_txDws_delta_enq$wget = + (pciw_pci0_txInF$D_OUT[152] && !pciw_pci0_txInF$D_OUT[126] && + !pciw_pci0_txInF$D_OUT[125]) ? + 3'd3 : + ((pciw_pci0_txInF$D_OUT[152] && + (pciw_pci0_txInF$D_OUT[125] || + pciw_pci0_txInF$D_OUT[126] && + pciw_pci0_txInF$D_OUT[143:128] == 16'hFFFF)) ? + 3'd4 : + ((pciw_pci0_txInF$D_OUT[152] && + pciw_pci0_txInF$D_OUT[126] && + !pciw_pci0_txInF$D_OUT[125] && + pciw_pci0_txInF$D_OUT[143:128] == 16'hFFF0) ? + 3'd3 : + ((!pciw_pci0_txInF$D_OUT[152] && + pciw_pci0_txInF$D_OUT[143:128] == 16'hFFFF) ? + 3'd4 : + ((!pciw_pci0_txInF$D_OUT[152] && + pciw_pci0_txInF$D_OUT[143:128] == 16'hFFF0) ? + 3'd3 : + ((!pciw_pci0_txInF$D_OUT[152] && + pciw_pci0_txInF$D_OUT[143:128] == 16'hFF00) ? + 3'd2 : + ((!pciw_pci0_txInF$D_OUT[152] && + pciw_pci0_txInF$D_OUT[143:128] == 16'hF000) ? + 3'd1 : + 3'd0)))))) ; + assign pciw_pci0_txDws_delta_enq$whas = WILL_FIRE_RL_pciw_pci0_tx_enstage ; + assign pciw_pci0_txDws_delta_deq$wget = + IF_IF_NOT_pciw_pci0_txInFlight_49_57_AND_NOT_I_ETC__q1[2:0] ; + assign pciw_pci0_txDws_delta_deq$whas = WILL_FIRE_RL_pciw_pci0_tx_destage ; + assign pciw_pci0_txDws_new_data$wget = + { pciw_pci0_txInF$D_OUT[7:0], + pciw_pci0_txInF$D_OUT[15:8], + pciw_pci0_txInF$D_OUT[23:16], + pciw_pci0_txInF$D_OUT[31:24], + pciw_pci0_txInF$D_OUT[39:32], + pciw_pci0_txInF$D_OUT[47:40], + pciw_pci0_txInF$D_OUT[55:48], + pciw_pci0_txInF$D_OUT[63:56], + pciw_pci0_txInF$D_OUT[71:64], + pciw_pci0_txInF$D_OUT[79:72], + pciw_pci0_txInF$D_OUT[87:80], + pciw_pci0_txInF$D_OUT[95:88], + pciw_pci0_txInF$D_OUT[103:96], + pciw_pci0_txInF$D_OUT[111:104], + pciw_pci0_txInF$D_OUT[119:112], + pciw_pci0_txInF$D_OUT[127:120] } ; + assign pciw_pci0_txDws_new_data$whas = WILL_FIRE_RL_pciw_pci0_tx_enstage ; + assign pciw_pci0_rxInF_r_enq$whas = + MUX_pciw_pci0_rxInF_levelsValid$write_1__SEL_3 ; + assign pciw_pci0_rxInF_r_deq$whas = WILL_FIRE_RL_pciw_pci0_rx_enstage ; + assign pciw_pci0_rxInF_r_clr$whas = 1'b0 ; + assign pciw_pci0_rxInF_doResetEnq$whas = + MUX_pciw_pci0_rxInF_levelsValid$write_1__SEL_3 ; + assign pciw_pci0_rxInF_doResetDeq$whas = WILL_FIRE_RL_pciw_pci0_rx_enstage ; + assign pciw_pci0_rxInF_doResetClr$whas = 1'b0 ; + assign pciw_pci0_txOutF_r_enq$whas = WILL_FIRE_RL_pciw_pci0_tx_destage ; + assign pciw_pci0_txOutF_r_deq$whas = WILL_FIRE_RL_pciw_pci0_tx_exstage ; + assign pciw_pci0_txOutF_r_clr$whas = 1'b0 ; + assign pciw_pci0_txOutF_doResetEnq$whas = + WILL_FIRE_RL_pciw_pci0_tx_destage ; + assign pciw_pci0_txOutF_doResetDeq$whas = + WILL_FIRE_RL_pciw_pci0_tx_exstage ; + assign pciw_pci0_txOutF_doResetClr$whas = 1'b0 ; + assign infLed$wget = ctop$led ; + + // register freeCnt + assign freeCnt$D_IN = freeCnt + 32'd1 ; + assign freeCnt$EN = 1'd1 ; + + // register hsmcReg + assign hsmcReg$D_IN = hsmc_in_i ; + assign hsmcReg$EN = 1'd1 ; + + // register ledReg + assign ledReg$D_IN = + { 6'd31, + ~ctop$led, + INV_swReg_35_BIT_0_36_XOR_swReg_35_BIT_1_37_38_ETC___d764 } ; + assign ledReg$EN = 1'd1 ; + + // register needs_init + assign needs_init$D_IN = 1'd0 ; + assign needs_init$EN = needs_init ; + + // register pciDevice + assign pciDevice$D_IN = pciw_pciDevice ; + assign pciDevice$EN = 1'd1 ; + + // register pciw_pci0_cfgDataWr + assign pciw_pci0_cfgDataWr$D_IN = pciw_pci0_pcie_ep$tl_cfg_ctl_wr ; + assign pciw_pci0_cfgDataWr$EN = 1'd1 ; + + // register pciw_pci0_cfgSample + assign pciw_pci0_cfgSample$D_IN = + pciw_pci0_cfgDataWr != pciw_pci0_pcie_ep$tl_cfg_ctl_wr ; + assign pciw_pci0_cfgSample$EN = 1'd1 ; + + // register pciw_pci0_deviceReg + assign pciw_pci0_deviceReg$D_IN = + { pciw_pci0_pcie_ep$tl_cfg_ctl[12:0], 3'd0 } ; + assign pciw_pci0_deviceReg$EN = + pciw_pci0_cfgSample && pciw_pci0_pcie_ep$tl_cfg_add == 4'hF ; + + // register pciw_pci0_rxDbgDeDeq + assign pciw_pci0_rxDbgDeDeq$D_IN = + pciw_pci0_rxDbgDeDeq + + { 13'd0, + IF_IF_pciw_pci0_rxInFlight_76_THEN_pciw_pci0_r_ETC__q2[2:0] } ; + assign pciw_pci0_rxDbgDeDeq$EN = WILL_FIRE_RL_pciw_pci0_rx_destage ; + + // register pciw_pci0_rxDbgDeEof + assign pciw_pci0_rxDbgDeEof$D_IN = pciw_pci0_rxDbgDeEof + 16'd1 ; + assign pciw_pci0_rxDbgDeEof$EN = + WILL_FIRE_RL_pciw_pci0_rx_destage && pciw_pci0_rxEofF$EMPTY_N && + pciw_pci0_rxDws_num_full_7_ULE_4___d836 ; + + // register pciw_pci0_rxDbgDeSof + assign pciw_pci0_rxDbgDeSof$D_IN = pciw_pci0_rxDbgDeSof + 16'd1 ; + assign pciw_pci0_rxDbgDeSof$EN = + WILL_FIRE_RL_pciw_pci0_rx_destage && !pciw_pci0_rxInFlight ; + + // register pciw_pci0_rxDbgDestage + assign pciw_pci0_rxDbgDestage$D_IN = pciw_pci0_rxDbgDestage + 16'd1 ; + assign pciw_pci0_rxDbgDestage$EN = WILL_FIRE_RL_pciw_pci0_rx_destage ; + + // register pciw_pci0_rxDbgEnEnq + assign pciw_pci0_rxDbgEnEnq$D_IN = + pciw_pci0_rxDbgEnEnq + + { 13'd0, + (pciw_pci0_rxInF$D_OUT[153] && !pciw_pci0_rxInF$D_OUT[30] && + !pciw_pci0_rxInF$D_OUT[29]) ? + 3'd3 : + ((pciw_pci0_rxInF$D_OUT[153] && + (pciw_pci0_rxInF$D_OUT[29] || + pciw_pci0_rxInF$D_OUT[30] && pciw_pci0_rxInF$D_OUT[66])) ? + 3'd4 : + ((pciw_pci0_rxInF$D_OUT[153] && + pciw_pci0_rxInF$D_OUT[30] && + !pciw_pci0_rxInF$D_OUT[29] && + !pciw_pci0_rxInF$D_OUT[66]) ? + 3'd3 : + ((!pciw_pci0_rxInF$D_OUT[153] && + !pciw_pci0_rxInF$D_OUT[154] && + pciw_pci0_rxInF$D_OUT[143:128] == 16'hFFFF) ? + 3'd4 : + ((!pciw_pci0_rxInF$D_OUT[153] && + !pciw_pci0_rxInF$D_OUT[154] && + pciw_pci0_rxInF$D_OUT[143:128] == 16'h0FFF) ? + 3'd3 : + ((!pciw_pci0_rxInF$D_OUT[153] && + pciw_pci0_rxInF$D_OUT[154] && + pciw_pci0_rxInF$D_OUT[143:136] == 8'hFF) ? + 3'd2 : + ((!pciw_pci0_rxInF$D_OUT[153] && + pciw_pci0_rxInF$D_OUT[154] && + pciw_pci0_rxInF$D_OUT[143:136] == 8'h0F) ? + 3'd1 : + 3'd0)))))) } ; + assign pciw_pci0_rxDbgEnEnq$EN = WILL_FIRE_RL_pciw_pci0_rx_enstage ; + + // register pciw_pci0_rxDbgEnEof + assign pciw_pci0_rxDbgEnEof$D_IN = pciw_pci0_rxDbgEnEof + 16'd1 ; + assign pciw_pci0_rxDbgEnEof$EN = + WILL_FIRE_RL_pciw_pci0_rx_enstage && pciw_pci0_rxInF$D_OUT[152] ; + + // register pciw_pci0_rxDbgEnSof + assign pciw_pci0_rxDbgEnSof$D_IN = pciw_pci0_rxDbgEnSof + 16'd1 ; + assign pciw_pci0_rxDbgEnSof$EN = + WILL_FIRE_RL_pciw_pci0_rx_enstage && pciw_pci0_rxInF$D_OUT[153] ; + + // register pciw_pci0_rxDbgEnstage + assign pciw_pci0_rxDbgEnstage$D_IN = pciw_pci0_rxDbgEnstage + 16'd1 ; + assign pciw_pci0_rxDbgEnstage$EN = WILL_FIRE_RL_pciw_pci0_rx_enstage ; + + // register pciw_pci0_rxDbgInstage + assign pciw_pci0_rxDbgInstage$D_IN = pciw_pci0_rxDbgInstage + 16'd1 ; + assign pciw_pci0_rxDbgInstage$EN = + MUX_pciw_pci0_rxInF_levelsValid$write_1__SEL_3 ; + + // register pciw_pci0_rxDwrDeq + assign pciw_pci0_rxDwrDeq$D_IN = + pciw_pci0_rxInFlight ? + pciw_pci0_rxDwrDeq - + { 8'd0, + IF_IF_pciw_pci0_rxInFlight_76_THEN_pciw_pci0_r_ETC__q2[2:0] } : + IF_pciw_pci0_rxEofF_notEmpty__62_AND_pciw_pci0_ETC___d288 ; + assign pciw_pci0_rxDwrDeq$EN = WILL_FIRE_RL_pciw_pci0_rx_destage ; + + // register pciw_pci0_rxDwrEnq + assign pciw_pci0_rxDwrEnq$D_IN = 11'h0 ; + assign pciw_pci0_rxDwrEnq$EN = 1'b0 ; + + // register pciw_pci0_rxDws_num_empty + assign pciw_pci0_rxDws_num_empty$D_IN = + pciw_pci0_rxDws_num_empty + + { 1'd0, + IF_pciw_pci0_rxDws_delta_deq_whas__3_THEN_pciw_ETC___d801 } - + { 1'd0, + IF_pciw_pci0_rxDws_delta_enq_whas__8_THEN_pciw_ETC___d771 } ; + assign pciw_pci0_rxDws_num_empty$EN = 1'd1 ; + + // register pciw_pci0_rxDws_num_full + assign pciw_pci0_rxDws_num_full$D_IN = + pciw_pci0_rxDws_num_full + + { 1'd0, + IF_pciw_pci0_rxDws_delta_enq_whas__8_THEN_pciw_ETC___d771 } - + { 1'd0, + IF_pciw_pci0_rxDws_delta_deq_whas__3_THEN_pciw_ETC___d801 } ; + assign pciw_pci0_rxDws_num_full$EN = 1'd1 ; + + // register pciw_pci0_rxDws_vec + assign pciw_pci0_rxDws_vec$D_IN = + { (WILL_FIRE_RL_pciw_pci0_rx_enstage ? + _0_CONCAT_pciw_pci0_rxDws_new_data_wget__2_BITS_ETC___d832[255:32] : + 224'd0) | + pciw_pci0_rxDws_vec_3_SRL_IF_pciw_pci0_rxDws_d_ETC___d834[255:32], + (WILL_FIRE_RL_pciw_pci0_rx_enstage ? + _0_CONCAT_pciw_pci0_rxDws_new_data_wget__2_BITS_ETC___d832[31:0] : + 32'd0) | + pciw_pci0_rxDws_vec_3_SRL_IF_pciw_pci0_rxDws_d_ETC___d834[31:0] } ; + assign pciw_pci0_rxDws_vec$EN = 1'd1 ; + + // register pciw_pci0_rxInF_countReg + assign pciw_pci0_rxInF_countReg$D_IN = + MUX_pciw_pci0_rxInF_levelsValid$write_1__SEL_3 ? + pciw_pci0_rxInF_countReg + 6'd1 : + pciw_pci0_rxInF_countReg - 6'd1 ; + assign pciw_pci0_rxInF_countReg$EN = + MUX_pciw_pci0_rxInF_levelsValid$write_1__SEL_3 != + WILL_FIRE_RL_pciw_pci0_rx_enstage ; + + // register pciw_pci0_rxInF_levelsValid + assign pciw_pci0_rxInF_levelsValid$D_IN = + WILL_FIRE_RL_pciw_pci0_rxInF_reset ; + assign pciw_pci0_rxInF_levelsValid$EN = + WILL_FIRE_RL_pciw_pci0_rx_enstage || + pciw_pci0_rxInF$FULL_N && pciw_pci0_pcie_ep$rx_st_valid0 || + WILL_FIRE_RL_pciw_pci0_rxInF_reset ; + + // register pciw_pci0_rxInFlight + assign pciw_pci0_rxInFlight$D_IN = + !pciw_pci0_rxEofF$EMPTY_N || + !pciw_pci0_rxDws_num_full_7_ULE_4___d836 ; + assign pciw_pci0_rxInFlight$EN = WILL_FIRE_RL_pciw_pci0_rx_destage ; + + // register pciw_pci0_txDbgDeDeq + assign pciw_pci0_txDbgDeDeq$D_IN = + pciw_pci0_txDbgDeDeq + + { 13'd0, + IF_IF_NOT_pciw_pci0_txInFlight_49_57_AND_NOT_I_ETC__q1[2:0] } ; + assign pciw_pci0_txDbgDeDeq$EN = WILL_FIRE_RL_pciw_pci0_tx_destage ; + + // register pciw_pci0_txDbgDeEof + assign pciw_pci0_txDbgDeEof$D_IN = pciw_pci0_txDbgDeEof + 16'd1 ; + assign pciw_pci0_txDbgDeEof$EN = + WILL_FIRE_RL_pciw_pci0_tx_destage && + pciw_pci0_txEofF_notEmpty__52_AND_pciw_pci0_tx_ETC___d817 ; + + // register pciw_pci0_txDbgDeSof + assign pciw_pci0_txDbgDeSof$D_IN = pciw_pci0_txDbgDeSof + 16'd1 ; + assign pciw_pci0_txDbgDeSof$EN = + WILL_FIRE_RL_pciw_pci0_tx_destage && !pciw_pci0_txInFlight ; + + // register pciw_pci0_txDbgDestage + assign pciw_pci0_txDbgDestage$D_IN = pciw_pci0_txDbgDestage + 16'd1 ; + assign pciw_pci0_txDbgDestage$EN = WILL_FIRE_RL_pciw_pci0_tx_destage ; + + // register pciw_pci0_txDbgEnEnq + assign pciw_pci0_txDbgEnEnq$D_IN = + pciw_pci0_txDbgEnEnq + + { 13'd0, + (pciw_pci0_txInF$D_OUT[152] && !pciw_pci0_txInF$D_OUT[126] && + !pciw_pci0_txInF$D_OUT[125]) ? + 3'd3 : + ((pciw_pci0_txInF$D_OUT[152] && + (pciw_pci0_txInF$D_OUT[125] || + pciw_pci0_txInF$D_OUT[126] && + pciw_pci0_txInF$D_OUT[143:128] == 16'hFFFF)) ? + 3'd4 : + ((pciw_pci0_txInF$D_OUT[152] && + pciw_pci0_txInF$D_OUT[126] && + !pciw_pci0_txInF$D_OUT[125] && + pciw_pci0_txInF$D_OUT[143:128] == 16'hFFF0) ? + 3'd3 : + ((!pciw_pci0_txInF$D_OUT[152] && + pciw_pci0_txInF$D_OUT[143:128] == 16'hFFFF) ? + 3'd4 : + ((!pciw_pci0_txInF$D_OUT[152] && + pciw_pci0_txInF$D_OUT[143:128] == 16'hFFF0) ? + 3'd3 : + ((!pciw_pci0_txInF$D_OUT[152] && + pciw_pci0_txInF$D_OUT[143:128] == 16'hFF00) ? + 3'd2 : + ((!pciw_pci0_txInF$D_OUT[152] && + pciw_pci0_txInF$D_OUT[143:128] == + 16'hF000) ? + 3'd1 : + 3'd0)))))) } ; + assign pciw_pci0_txDbgEnEnq$EN = WILL_FIRE_RL_pciw_pci0_tx_enstage ; + + // register pciw_pci0_txDbgEnEof + assign pciw_pci0_txDbgEnEof$D_IN = pciw_pci0_txDbgEnEof + 16'd1 ; + assign pciw_pci0_txDbgEnEof$EN = + WILL_FIRE_RL_pciw_pci0_tx_enstage && pciw_pci0_txInF$D_OUT[151] ; + + // register pciw_pci0_txDbgEnSof + assign pciw_pci0_txDbgEnSof$D_IN = pciw_pci0_txDbgEnSof + 16'd1 ; + assign pciw_pci0_txDbgEnSof$EN = + WILL_FIRE_RL_pciw_pci0_tx_enstage && pciw_pci0_txInF$D_OUT[152] ; + + // register pciw_pci0_txDbgEnstage + assign pciw_pci0_txDbgEnstage$D_IN = pciw_pci0_txDbgEnstage + 16'd1 ; + assign pciw_pci0_txDbgEnstage$EN = WILL_FIRE_RL_pciw_pci0_tx_enstage ; + + // register pciw_pci0_txDbgExstage + assign pciw_pci0_txDbgExstage$D_IN = pciw_pci0_txDbgExstage + 16'd1 ; + assign pciw_pci0_txDbgExstage$EN = WILL_FIRE_RL_pciw_pci0_tx_exstage ; + + // register pciw_pci0_txDwrDeq + assign pciw_pci0_txDwrDeq$D_IN = + pciw_pci0_txInFlight ? + pciw_pci0_txDwrDeq - + { 8'd0, + IF_IF_NOT_pciw_pci0_txInFlight_49_57_AND_NOT_I_ETC__q1[2:0] } : + IF_pciw_pci0_txEofF_notEmpty__52_AND_pciw_pci0_ETC___d523 ; + assign pciw_pci0_txDwrDeq$EN = WILL_FIRE_RL_pciw_pci0_tx_destage ; + + // register pciw_pci0_txDwrEnq + assign pciw_pci0_txDwrEnq$D_IN = 11'h0 ; + assign pciw_pci0_txDwrEnq$EN = 1'b0 ; + + // register pciw_pci0_txDws_num_empty + assign pciw_pci0_txDws_num_empty$D_IN = + pciw_pci0_txDws_num_empty + + { 1'd0, + IF_pciw_pci0_txDws_delta_deq_whas__9_THEN_pciw_ETC___d804 } - + { 1'd0, + IF_pciw_pci0_txDws_delta_enq_whas__4_THEN_pciw_ETC___d770 } ; + assign pciw_pci0_txDws_num_empty$EN = 1'd1 ; + + // register pciw_pci0_txDws_num_full + assign pciw_pci0_txDws_num_full$D_IN = + pciw_pci0_txDws_num_full + + { 1'd0, + IF_pciw_pci0_txDws_delta_enq_whas__4_THEN_pciw_ETC___d770 } - + { 1'd0, + IF_pciw_pci0_txDws_delta_deq_whas__9_THEN_pciw_ETC___d804 } ; + assign pciw_pci0_txDws_num_full$EN = 1'd1 ; + + // register pciw_pci0_txDws_vec + assign pciw_pci0_txDws_vec$D_IN = + { (WILL_FIRE_RL_pciw_pci0_tx_enstage ? + _0_CONCAT_pciw_pci0_txDws_new_data_wget__8_BITS_ETC___d833[255:32] : + 224'd0) | + pciw_pci0_txDws_vec_9_SRL_IF_pciw_pci0_txDws_d_ETC___d835[255:32], + (WILL_FIRE_RL_pciw_pci0_tx_enstage ? + _0_CONCAT_pciw_pci0_txDws_new_data_wget__8_BITS_ETC___d833[31:0] : + 32'd0) | + pciw_pci0_txDws_vec_9_SRL_IF_pciw_pci0_txDws_d_ETC___d835[31:0] } ; + assign pciw_pci0_txDws_vec$EN = 1'd1 ; + + // register pciw_pci0_txInFlight + assign pciw_pci0_txInFlight$D_IN = + NOT_pciw_pci0_txEofF_notEmpty__52_53_OR_NOT_pc_ETC___d495 ; + assign pciw_pci0_txInFlight$EN = WILL_FIRE_RL_pciw_pci0_tx_destage ; + + // register pciw_pci0_txOutF_countReg + assign pciw_pci0_txOutF_countReg$D_IN = + WILL_FIRE_RL_pciw_pci0_tx_destage ? + pciw_pci0_txOutF_countReg + 10'd1 : + pciw_pci0_txOutF_countReg - 10'd1 ; + assign pciw_pci0_txOutF_countReg$EN = + WILL_FIRE_RL_pciw_pci0_tx_destage != + WILL_FIRE_RL_pciw_pci0_tx_exstage ; + + // register pciw_pci0_txOutF_levelsValid + assign pciw_pci0_txOutF_levelsValid$D_IN = + WILL_FIRE_RL_pciw_pci0_txOutF_reset ; + assign pciw_pci0_txOutF_levelsValid$EN = + WILL_FIRE_RL_pciw_pci0_tx_exstage || + WILL_FIRE_RL_pciw_pci0_tx_destage || + WILL_FIRE_RL_pciw_pci0_txOutF_reset ; + + // register pciw_pci0_txReadyD + assign pciw_pci0_txReadyD$D_IN = pciw_pci0_pcie_ep$tx_st_ready0 ; + assign pciw_pci0_txReadyD$EN = 1'd1 ; + + // register pciw_pciDevice + assign pciw_pciDevice$D_IN = pciw_pci0_deviceReg ; + assign pciw_pciDevice$EN = 1'd1 ; + + // register swReg + assign swReg$D_IN = usr_sw_i ; + assign swReg$EN = 1'd1 ; + + // submodule ctop + assign ctop$cpServer_request_put = 59'h0 ; + assign ctop$gps_ppsSyncIn_x = gps_ppsSyncIn_x ; + assign ctop$server_request_put = pciw_p2iF$D_OUT ; + assign ctop$switch_x = 3'h0 ; + assign ctop$wci_m_0_SData = 32'h0 ; + assign ctop$wci_m_0_SFlag = 2'h0 ; + assign ctop$wci_m_0_SResp = 2'h0 ; + assign ctop$wci_m_1_SData = flash0$wciS0_SData ; + assign ctop$wci_m_1_SFlag = flash0$wciS0_SFlag ; + assign ctop$wci_m_1_SResp = flash0$wciS0_SResp ; + assign ctop$wci_m_2_SData = 32'h0 ; + assign ctop$wci_m_2_SFlag = 2'h0 ; + assign ctop$wci_m_2_SResp = 2'h0 ; + assign ctop$wci_m_3_SData = 32'h0 ; + assign ctop$wci_m_3_SFlag = 2'h0 ; + assign ctop$wci_m_3_SResp = 2'h0 ; + assign ctop$wci_m_4_SData = dram0$wciS0_SData ; + assign ctop$wci_m_4_SFlag = dram0$wciS0_SFlag ; + assign ctop$wci_m_4_SResp = dram0$wciS0_SResp ; + assign ctop$wmemiM0_SData = dram0$wmemiS0_SData ; + assign ctop$wmemiM0_SResp = dram0$wmemiS0_SResp ; + assign ctop$wsi_s_adc_MBurstLength = 12'h0 ; + assign ctop$wsi_s_adc_MByteEn = 4'h0 ; + assign ctop$wsi_s_adc_MCmd = 3'h0 ; + assign ctop$wsi_s_adc_MData = 32'h0 ; + assign ctop$wsi_s_adc_MReqInfo = 8'h0 ; + assign ctop$EN_server_request_put = + ctop$RDY_server_request_put && pciw_p2iF$EMPTY_N ; + assign ctop$EN_server_response_get = + ctop$RDY_server_response_get && pciw_i2pF$FULL_N ; + assign ctop$EN_cpServer_request_put = 1'b0 ; + assign ctop$EN_cpServer_response_get = 1'b0 ; + assign ctop$wci_m_0_SThreadBusy = 1'b0 ; + assign ctop$wci_m_1_SThreadBusy = flash0$wciS0_SThreadBusy ; + assign ctop$wci_m_2_SThreadBusy = 1'b0 ; + assign ctop$wci_m_3_SThreadBusy = 1'b0 ; + assign ctop$wci_m_4_SThreadBusy = dram0$wciS0_SThreadBusy ; + assign ctop$wsi_s_adc_MReqLast = 1'b0 ; + assign ctop$wsi_s_adc_MBurstPrecise = 1'b0 ; + assign ctop$wsi_s_adc_MReset_n = 1'b0 ; + assign ctop$wsi_m_dac_SThreadBusy = 1'b0 ; + assign ctop$wsi_m_dac_SReset_n = 1'b0 ; + assign ctop$wmemiM0_SRespLast = dram0$wmemiS0_SRespLast ; + assign ctop$wmemiM0_SCmdAccept = dram0$wmemiS0_SCmdAccept ; + assign ctop$wmemiM0_SDataAccept = dram0$wmemiS0_SDataAccept ; + + // submodule dram0 + assign dram0$dram_rdn_i = dram_rdn_i ; + assign dram0$dram_rup_i = dram_rup_i ; + assign dram0$wciS0_MAddr = ctop$wci_m_4_MAddr ; + assign dram0$wciS0_MAddrSpace = ctop$wci_m_4_MAddrSpace ; + assign dram0$wciS0_MByteEn = ctop$wci_m_4_MByteEn ; + assign dram0$wciS0_MCmd = ctop$wci_m_4_MCmd ; + assign dram0$wciS0_MData = ctop$wci_m_4_MData ; + assign dram0$wciS0_MFlag = ctop$wci_m_4_MFlag ; + assign dram0$wmemiS0_MAddr = ctop$wmemiM0_MAddr ; + assign dram0$wmemiS0_MBurstLength = ctop$wmemiM0_MBurstLength ; + assign dram0$wmemiS0_MCmd = ctop$wmemiM0_MCmd ; + assign dram0$wmemiS0_MData = ctop$wmemiM0_MData ; + assign dram0$wmemiS0_MDataByteEn = ctop$wmemiM0_MDataByteEn ; + assign dram0$wmemiS0_MReqLast = ctop$wmemiM0_MReqLast ; + assign dram0$wmemiS0_MDataValid = ctop$wmemiM0_MDataValid ; + assign dram0$wmemiS0_MDataLast = ctop$wmemiM0_MDataLast ; + assign dram0$wmemiS0_MReset_n = ctop$wmemiM0_MReset_n ; + + // submodule flash0 + assign flash0$flash_fwait_i = flash_fwait_i ; + assign flash0$wciS0_MAddr = ctop$wci_m_1_MAddr ; + assign flash0$wciS0_MAddrSpace = ctop$wci_m_1_MAddrSpace ; + assign flash0$wciS0_MByteEn = ctop$wci_m_1_MByteEn ; + assign flash0$wciS0_MCmd = ctop$wci_m_1_MCmd ; + assign flash0$wciS0_MData = ctop$wci_m_1_MData ; + assign flash0$wciS0_MFlag = ctop$wci_m_1_MFlag ; + + // submodule lcd_ctrl + assign lcd_ctrl$setLine1_text = 128'h202073656C75522063696D6F74412020 ; + assign lcd_ctrl$setLine2_text = 128'h203474736C61203A204950436E65704F ; + assign lcd_ctrl$EN_setLine1 = needs_init ; + assign lcd_ctrl$EN_setLine2 = needs_init ; + + // submodule pciw_aliveLed_sb + assign pciw_aliveLed_sb$sD_IN = pciw_pci0_pcie_ep$ava_alive ; + assign pciw_aliveLed_sb$sEN = 1'd1 ; + + // submodule pciw_i2pF + assign pciw_i2pF$D_IN = ctop$server_response_get ; + assign pciw_i2pF$ENQ = ctop$RDY_server_response_get && pciw_i2pF$FULL_N ; + assign pciw_i2pF$DEQ = pciw_i2pF$EMPTY_N && pciw_pci0_txInF$FULL_N ; + assign pciw_i2pF$CLR = 1'b0 ; + + // submodule pciw_linkLed_sb + assign pciw_linkLed_sb$sD_IN = pciw_pci0_pcie_ep$ava_lnk_up ; + assign pciw_linkLed_sb$sEN = 1'd1 ; + + // submodule pciw_p2iF + assign pciw_p2iF$D_IN = pciw_pci0_rxOutF$D_OUT ; + assign pciw_p2iF$ENQ = pciw_pci0_rxOutF$EMPTY_N && pciw_p2iF$FULL_N ; + assign pciw_p2iF$DEQ = ctop$RDY_server_request_put && pciw_p2iF$EMPTY_N ; + assign pciw_p2iF$CLR = 1'b0 ; + + // submodule pciw_pci0_pcie_ep + assign pciw_pci0_pcie_ep$pcie_rx_in = pcie_rx_i ; + assign pciw_pci0_pcie_ep$rx_st_mask0 = 1'd0 ; + assign pciw_pci0_pcie_ep$rx_st_ready0 = pciw_pci0_rxInF_countReg < 6'd30 ; + assign pciw_pci0_pcie_ep$tx_st_data0 = pciw_pci0_txOutF$D_OUT[127:0] ; + assign pciw_pci0_pcie_ep$tx_st_empty0 = + WILL_FIRE_RL_pciw_pci0_tx_exstage && + pciw_pci0_txOutF$D_OUT[154] ; + assign pciw_pci0_pcie_ep$tx_st_eop0 = + WILL_FIRE_RL_pciw_pci0_tx_exstage && + pciw_pci0_txOutF$D_OUT[152] ; + assign pciw_pci0_pcie_ep$tx_st_err0 = 1'b0 ; + assign pciw_pci0_pcie_ep$tx_st_sop0 = + WILL_FIRE_RL_pciw_pci0_tx_exstage && + pciw_pci0_txOutF$D_OUT[153] ; + assign pciw_pci0_pcie_ep$tx_st_valid0 = WILL_FIRE_RL_pciw_pci0_tx_exstage ; + + // submodule pciw_pci0_rxEofF + assign pciw_pci0_rxEofF$D_IN = 3'b010 /* unspecified value */ ; + assign pciw_pci0_rxEofF$ENQ = + WILL_FIRE_RL_pciw_pci0_rx_enstage && pciw_pci0_rxInF$D_OUT[152] ; + assign pciw_pci0_rxEofF$DEQ = + WILL_FIRE_RL_pciw_pci0_rx_destage && pciw_pci0_rxEofF$EMPTY_N && + pciw_pci0_rxDws_num_full_7_ULE_4___d836 ; + assign pciw_pci0_rxEofF$CLR = 1'b0 ; + + // submodule pciw_pci0_rxHeadF + assign pciw_pci0_rxHeadF$D_IN = + { pciw_pci0_rxInF$D_OUT[151:144], + pciw_pci0_rxInF$D_OUT[9:0], + pciw_pci0_rxInF$D_OUT[30:29], + (pciw_pci0_rxInF$D_OUT[29] ? 11'd4 : 11'd3) + + (pciw_pci0_rxInF$D_OUT[30] ? + ((pciw_pci0_rxInF$D_OUT[9:0] == 10'd0) ? + 11'd1024 : + { 1'd0, pciw_pci0_rxInF$D_OUT[9:0] }) : + 11'd0) } ; + assign pciw_pci0_rxHeadF$ENQ = + WILL_FIRE_RL_pciw_pci0_rx_enstage && pciw_pci0_rxInF$D_OUT[153] ; + assign pciw_pci0_rxHeadF$DEQ = + WILL_FIRE_RL_pciw_pci0_rx_destage && pciw_pci0_rxEofF$EMPTY_N && + pciw_pci0_rxDws_num_full_7_ULE_4___d836 ; + assign pciw_pci0_rxHeadF$CLR = 1'b0 ; + + // submodule pciw_pci0_rxInF + assign pciw_pci0_rxInF$D_IN = + { pciw_pci0_pcie_ep$rx_st_empty0, + pciw_pci0_pcie_ep$rx_st_sop0, + pciw_pci0_pcie_ep$rx_st_eop0, + x_hit__h22096, + pciw_pci0_pcie_ep$rx_st_be0, + pciw_pci0_pcie_ep$rx_st_data0 } ; + assign pciw_pci0_rxInF$ENQ = + MUX_pciw_pci0_rxInF_levelsValid$write_1__SEL_3 ; + assign pciw_pci0_rxInF$DEQ = WILL_FIRE_RL_pciw_pci0_rx_enstage ; + assign pciw_pci0_rxInF$CLR = 1'b0 ; + + // submodule pciw_pci0_rxOutF + assign pciw_pci0_rxOutF$D_IN = + { !pciw_pci0_rxInFlight, + pciw_pci0_rxEofF$EMPTY_N && + pciw_pci0_rxDws_num_full_7_ULE_4___d836, + pciw_pci0_rxHeadF$D_OUT[29:23], + x_be__h27614, + x_data__h27615 } ; + assign pciw_pci0_rxOutF$ENQ = WILL_FIRE_RL_pciw_pci0_rx_destage ; + assign pciw_pci0_rxOutF$DEQ = pciw_pci0_rxOutF$EMPTY_N && pciw_p2iF$FULL_N ; + assign pciw_pci0_rxOutF$CLR = 1'b0 ; + + // submodule pciw_pci0_txEofF + assign pciw_pci0_txEofF$D_IN = 3'b010 /* unspecified value */ ; + assign pciw_pci0_txEofF$ENQ = + WILL_FIRE_RL_pciw_pci0_tx_enstage && pciw_pci0_txInF$D_OUT[151] ; + assign pciw_pci0_txEofF$DEQ = + WILL_FIRE_RL_pciw_pci0_tx_destage && + pciw_pci0_txEofF_notEmpty__52_AND_pciw_pci0_tx_ETC___d817 ; + assign pciw_pci0_txEofF$CLR = 1'b0 ; + + // submodule pciw_pci0_txExF + assign pciw_pci0_txExF$D_IN = 1'd0 ; + assign pciw_pci0_txExF$ENQ = + WILL_FIRE_RL_pciw_pci0_tx_destage && + pciw_pci0_txEofF_notEmpty__52_AND_pciw_pci0_tx_ETC___d817 ; + assign pciw_pci0_txExF$DEQ = + WILL_FIRE_RL_pciw_pci0_tx_exstage && + pciw_pci0_txOutF$D_OUT[152] ; + assign pciw_pci0_txExF$CLR = 1'b0 ; + + // submodule pciw_pci0_txHeadF + assign pciw_pci0_txHeadF$D_IN = + { 8'd0, + pciw_pci0_txInF$D_OUT[105:96], + pciw_pci0_txInF$D_OUT[126:125], + (pciw_pci0_txInF$D_OUT[125] ? 11'd4 : 11'd3) + + (pciw_pci0_txInF$D_OUT[126] ? + ((pciw_pci0_txInF$D_OUT[105:96] == 10'd0) ? + 11'd1024 : + { 1'd0, pciw_pci0_txInF$D_OUT[105:96] }) : + 11'd0) } ; + assign pciw_pci0_txHeadF$ENQ = + WILL_FIRE_RL_pciw_pci0_tx_enstage && pciw_pci0_txInF$D_OUT[152] ; + assign pciw_pci0_txHeadF$DEQ = + WILL_FIRE_RL_pciw_pci0_tx_destage && + pciw_pci0_txEofF_notEmpty__52_AND_pciw_pci0_tx_ETC___d817 ; + assign pciw_pci0_txHeadF$CLR = 1'b0 ; + + // submodule pciw_pci0_txInF + assign pciw_pci0_txInF$D_IN = pciw_i2pF$D_OUT ; + assign pciw_pci0_txInF$ENQ = pciw_i2pF$EMPTY_N && pciw_pci0_txInF$FULL_N ; + assign pciw_pci0_txInF$DEQ = WILL_FIRE_RL_pciw_pci0_tx_enstage ; + assign pciw_pci0_txInF$CLR = 1'b0 ; + + // submodule pciw_pci0_txOutF + assign pciw_pci0_txOutF$D_IN = + { IF_IF_NOT_pciw_pci0_txInFlight_49_57_AND_NOT_I_ETC__q1[2:0] < + 3'd3, + !pciw_pci0_txInFlight, + pciw_pci0_txEofF_notEmpty__52_AND_pciw_pci0_tx_ETC___d817, + 24'd0, + x_data__h46011 } ; + assign pciw_pci0_txOutF$ENQ = WILL_FIRE_RL_pciw_pci0_tx_destage ; + assign pciw_pci0_txOutF$DEQ = WILL_FIRE_RL_pciw_pci0_tx_exstage ; + assign pciw_pci0_txOutF$CLR = 1'b0 ; + + // remaining internal signals + assign IF_IF_NOT_pciw_pci0_txInFlight_49_57_AND_NOT_I_ETC__q1 = + (IF_NOT_pciw_pci0_txInFlight_49_57_AND_NOT_IF_p_ETC___d837 <= + IF_pciw_pci0_txInFlight_49_THEN_pciw_pci0_txDw_ETC___d838) ? + IF_NOT_pciw_pci0_txInFlight_49_57_AND_NOT_IF_p_ETC___d837 : + IF_pciw_pci0_txInFlight_49_THEN_pciw_pci0_txDw_ETC___d838 ; + assign IF_IF_pciw_pci0_rxInFlight_76_THEN_pciw_pci0_r_ETC__q2 = + (IF_pciw_pci0_rxInFlight_76_THEN_pciw_pci0_rxDw_ETC___d769 < + 11'd4) ? + IF_pciw_pci0_rxInFlight_76_THEN_pciw_pci0_rxDw_ETC___d769 : + 11'd4 ; + assign IF_NOT_pciw_pci0_txInFlight_49_57_AND_NOT_IF_p_ETC___d837 = + (!pciw_pci0_txInFlight && + !IF_pciw_pci0_txInFlight_49_THEN_pciw_pci0_txDw_ETC___d481[34] && + IF_pciw_pci0_txInFlight_49_THEN_pciw_pci0_txDw_ETC___d492[30]) ? + 11'd3 : + 11'd4 ; + assign IF_pciw_pci0_rxDws_delta_deq_whas__3_THEN_pciw_ETC___d801 = + WILL_FIRE_RL_pciw_pci0_rx_destage ? + IF_IF_pciw_pci0_rxInFlight_76_THEN_pciw_pci0_r_ETC__q2[2:0] : + 3'd0 ; + assign IF_pciw_pci0_rxDws_delta_enq_whas__8_THEN_pciw_ETC___d771 = + WILL_FIRE_RL_pciw_pci0_rx_enstage ? + pciw_pci0_rxDws_delta_enq$wget : + 3'd0 ; + assign IF_pciw_pci0_rxEofF_notEmpty__62_AND_pciw_pci0_ETC___d288 = + (pciw_pci0_rxEofF$EMPTY_N && + pciw_pci0_rxDws_num_full_7_ULE_4___d836) ? + 11'd0 : + pciw_pci0_rxHeadF$D_OUT[10:0] - + { 8'd0, + IF_IF_pciw_pci0_rxInFlight_76_THEN_pciw_pci0_r_ETC__q2[2:0] } ; + assign IF_pciw_pci0_rxInFlight_76_THEN_pciw_pci0_rxDw_ETC___d769 = + pciw_pci0_rxInFlight ? + pciw_pci0_rxDwrDeq : + pciw_pci0_rxHeadF$D_OUT[10:0] ; + assign IF_pciw_pci0_txDws_delta_deq_whas__9_THEN_pciw_ETC___d804 = + WILL_FIRE_RL_pciw_pci0_tx_destage ? + IF_IF_NOT_pciw_pci0_txInFlight_49_57_AND_NOT_I_ETC__q1[2:0] : + 3'd0 ; + assign IF_pciw_pci0_txDws_delta_enq_whas__4_THEN_pciw_ETC___d770 = + WILL_FIRE_RL_pciw_pci0_tx_enstage ? + pciw_pci0_txDws_delta_enq$wget : + 3'd0 ; + assign IF_pciw_pci0_txEofF_notEmpty__52_AND_pciw_pci0_ETC___d523 = + pciw_pci0_txEofF_notEmpty__52_AND_pciw_pci0_tx_ETC___d817 ? + 11'd0 : + pciw_pci0_txHeadF$D_OUT[10:0] - + { 8'd0, + IF_IF_NOT_pciw_pci0_txInFlight_49_57_AND_NOT_I_ETC__q1[2:0] } ; + assign IF_pciw_pci0_txHeadF_first__59_BIT_11_60_THEN__ETC___d468 = + pciw_pci0_txHeadF$D_OUT[11] ? + { pciw_pci0_txDws_vec[103:96], + pciw_pci0_txDws_vec[111:104], + pciw_pci0_txDws_vec[119:112], + pciw_pci0_txDws_vec[127:120] } : + pciw_pci0_txDws_vec[127:96] ; + assign IF_pciw_pci0_txInFlight_49_THEN_pciw_pci0_txDw_ETC___d481 = + pciw_pci0_txInFlight ? + pciw_pci0_txDws_vec[127:32] : + { IF_pciw_pci0_txHeadF_first__59_BIT_11_60_THEN__ETC___d468, + pciw_pci0_txDws_vec[71:64], + pciw_pci0_txDws_vec[79:72], + pciw_pci0_txDws_vec[87:80], + pciw_pci0_txDws_vec[95:88], + pciw_pci0_txDws_vec[39:32], + pciw_pci0_txDws_vec[47:40], + pciw_pci0_txDws_vec[55:48], + pciw_pci0_txDws_vec[63:56] } ; + assign IF_pciw_pci0_txInFlight_49_THEN_pciw_pci0_txDw_ETC___d492 = + pciw_pci0_txInFlight ? + pciw_pci0_txDws_vec[31:0] : + { pciw_pci0_txDws_vec[7:0], + pciw_pci0_txDws_vec[15:8], + pciw_pci0_txDws_vec[23:16], + pciw_pci0_txDws_vec[31:24] } ; + assign IF_pciw_pci0_txInFlight_49_THEN_pciw_pci0_txDw_ETC___d838 = + pciw_pci0_txInFlight ? + pciw_pci0_txDwrDeq : + pciw_pci0_txHeadF$D_OUT[10:0] ; + assign INV_swReg_35_BIT_0_36_XOR_swReg_35_BIT_1_37_38_ETC___d764 = + { ~swParity__h48492, + ~(z__h56332 ^ + pciw_pci0_pcie_ep_ava_debug__52_OR_0_CONCAT_pc_ETC___d831[31]), + ~pciw_aliveLed_sb$dD_OUT, + ~pciw_linkLed_sb$dD_OUT, + ~freeCnt[29:26] } ; + assign NOT_pciw_pci0_txEofF_notEmpty__52_53_OR_NOT_pc_ETC___d495 = + !pciw_pci0_txEofF$EMPTY_N || + !pciw_pci0_txDws_num_full_3_ULE_4___d774 || + !pciw_pci0_txInFlight && + !IF_pciw_pci0_txInFlight_49_THEN_pciw_pci0_txDw_ETC___d481[34] && + IF_pciw_pci0_txInFlight_49_THEN_pciw_pci0_txDw_ETC___d492[30] ; + assign _0_CONCAT_pciw_pci0_rxDws_new_data_wget__2_BITS_ETC___d832 = + { 128'd0, x__h4523 } << x__h5776 ; + assign _0_CONCAT_pciw_pci0_txDws_new_data_wget__8_BITS_ETC___d833 = + { 128'd0, x__h14478 } << x__h15731 ; + assign bar___1__h22106 = + (pciw_pci0_pcie_ep$rx_st_data0[28:24] == 5'd0) ? + pciw_pci0_pcie_ep$rx_st_bardec0 : + 8'd0 ; + assign pciw_pci0_pcie_ep_ava_debug__52_OR_0_CONCAT_pc_ETC___d831 = + x__h56415 | y__h56416 ; + assign pciw_pci0_rxDws_num_full_7_ULE_4___d836 = + pciw_pci0_rxDws_num_full <= 4'd4 ; + assign pciw_pci0_rxDws_vec_3_SRL_IF_pciw_pci0_rxDws_d_ETC___d834 = + pciw_pci0_rxDws_vec >> x__h8877 ; + assign pciw_pci0_txDws_num_full_3_ULE_4___d774 = + pciw_pci0_txDws_num_full <= 4'd4 ; + assign pciw_pci0_txDws_vec_9_SRL_IF_pciw_pci0_txDws_d_ETC___d835 = + pciw_pci0_txDws_vec >> x__h18832 ; + assign pciw_pci0_txEofF_notEmpty__52_AND_pciw_pci0_tx_ETC___d817 = + pciw_pci0_txEofF$EMPTY_N && + pciw_pci0_txDws_num_full_3_ULE_4___d774 && + (pciw_pci0_txInFlight || + IF_pciw_pci0_txInFlight_49_THEN_pciw_pci0_txDw_ETC___d481[34] || + !IF_pciw_pci0_txInFlight_49_THEN_pciw_pci0_txDw_ETC___d492[30]) ; + assign pciw_pci0_txOutF_i_notFull__48_AND_pciw_pci0_t_ETC___d502 = + pciw_pci0_txOutF$FULL_N && + (pciw_pci0_txInFlight || pciw_pci0_txHeadF$EMPTY_N) && + (NOT_pciw_pci0_txEofF_notEmpty__52_53_OR_NOT_pc_ETC___d495 || + pciw_pci0_txHeadF$EMPTY_N && pciw_pci0_txEofF$EMPTY_N && + pciw_pci0_txExF$FULL_N) ; + assign swParity__h48492 = z__h55879 ^ swReg[7] ; + assign x__h14478 = + { pciw_pci0_txDws_new_data$wget[127:32] & + { (IF_pciw_pci0_txDws_delta_enq_whas__4_THEN_pciw_ETC___d770 <= + 3'd3) ? + 32'd0 : + 32'hFFFFFFFF, + (IF_pciw_pci0_txDws_delta_enq_whas__4_THEN_pciw_ETC___d770 <= + 3'd2) ? + 32'd0 : + 32'hFFFFFFFF, + (IF_pciw_pci0_txDws_delta_enq_whas__4_THEN_pciw_ETC___d770 <= + 3'd1) ? + 32'd0 : + 32'hFFFFFFFF }, + pciw_pci0_txDws_new_data$wget[31:0] & + ((IF_pciw_pci0_txDws_delta_enq_whas__4_THEN_pciw_ETC___d770 == + 3'd0) ? + 32'd0 : + 32'hFFFFFFFF) } ; + assign x__h15731 = + { pciw_pci0_txDws_num_full - + { 1'd0, + IF_pciw_pci0_txDws_delta_deq_whas__9_THEN_pciw_ETC___d804 }, + 5'd0 } ; + assign x__h18832 = + { IF_pciw_pci0_txDws_delta_deq_whas__9_THEN_pciw_ETC___d804, + 5'd0 } ; + assign x__h4523 = + { pciw_pci0_rxDws_new_data$wget[127:32] & + { (IF_pciw_pci0_rxDws_delta_enq_whas__8_THEN_pciw_ETC___d771 <= + 3'd3) ? + 32'd0 : + 32'hFFFFFFFF, + (IF_pciw_pci0_rxDws_delta_enq_whas__8_THEN_pciw_ETC___d771 <= + 3'd2) ? + 32'd0 : + 32'hFFFFFFFF, + (IF_pciw_pci0_rxDws_delta_enq_whas__8_THEN_pciw_ETC___d771 <= + 3'd1) ? + 32'd0 : + 32'hFFFFFFFF }, + pciw_pci0_rxDws_new_data$wget[31:0] & + ((IF_pciw_pci0_rxDws_delta_enq_whas__8_THEN_pciw_ETC___d771 == + 3'd0) ? + 32'd0 : + 32'hFFFFFFFF) } ; + assign x__h56415 = x__h56417 | y__h56418 ; + assign x__h56417 = x__h56419 | y__h56420 ; + assign x__h56419 = x__h56421 | y__h56422 ; + assign x__h56421 = x__h56423 | y__h56424 ; + assign x__h56423 = x__h56425 | y__h56426 ; + assign x__h56425 = x__h56427 | y__h56428 ; + assign x__h56427 = x__h56429 | y__h56430 ; + assign x__h56429 = x__h56431 | y__h56432 ; + assign x__h56431 = x__h56433 | y__h56434 ; + assign x__h56433 = x__h56435 | y__h56436 ; + assign x__h56435 = x__h56437 | y__h56438 ; + assign x__h56437 = x__h56439 | y__h56440 ; + assign x__h56439 = x__h56441 | y__h56442 ; + assign x__h56441 = x__h56443 | y__h56444 ; + assign x__h56443 = x__h56445 | y__h56446 ; + assign x__h56445 = x__h56447 | y__h56448 ; + assign x__h56447 = x__h56449 | y__h56450 ; + assign x__h56449 = x__h56451 | y__h56452 ; + assign x__h56451 = pciw_pci0_pcie_ep$ava_debug | y__h56454 ; + assign x__h5776 = + { pciw_pci0_rxDws_num_full - + { 1'd0, + IF_pciw_pci0_rxDws_delta_deq_whas__3_THEN_pciw_ETC___d801 }, + 5'd0 } ; + assign x__h8877 = + { IF_pciw_pci0_rxDws_delta_deq_whas__3_THEN_pciw_ETC___d801, + 5'd0 } ; + assign x_be__h27614 = + { IF_IF_IF_pciw_pci0_rxInFlight_76_THEN_pciw_pci_ETC___d787[0], + IF_IF_IF_pciw_pci0_rxInFlight_76_THEN_pciw_pci_ETC___d787[1], + IF_IF_IF_pciw_pci0_rxInFlight_76_THEN_pciw_pci_ETC___d787[2], + IF_IF_IF_pciw_pci0_rxInFlight_76_THEN_pciw_pci_ETC___d787[3], + IF_IF_IF_pciw_pci0_rxInFlight_76_THEN_pciw_pci_ETC___d787[4], + IF_IF_IF_pciw_pci0_rxInFlight_76_THEN_pciw_pci_ETC___d787[5], + IF_IF_IF_pciw_pci0_rxInFlight_76_THEN_pciw_pci_ETC___d787[6], + IF_IF_IF_pciw_pci0_rxInFlight_76_THEN_pciw_pci_ETC___d787[7], + IF_IF_IF_pciw_pci0_rxInFlight_76_THEN_pciw_pci_ETC___d787[8], + IF_IF_IF_pciw_pci0_rxInFlight_76_THEN_pciw_pci_ETC___d787[9], + IF_IF_IF_pciw_pci0_rxInFlight_76_THEN_pciw_pci_ETC___d787[10], + IF_IF_IF_pciw_pci0_rxInFlight_76_THEN_pciw_pci_ETC___d787[11], + IF_IF_IF_pciw_pci0_rxInFlight_76_THEN_pciw_pci_ETC___d787[12], + IF_IF_IF_pciw_pci0_rxInFlight_76_THEN_pciw_pci_ETC___d787[13], + IF_IF_IF_pciw_pci0_rxInFlight_76_THEN_pciw_pci_ETC___d787[14], + IF_IF_IF_pciw_pci0_rxInFlight_76_THEN_pciw_pci_ETC___d787[15] } ; + assign x_data__h27615 = + { pciw_pci0_rxDws_vec[7:0], + pciw_pci0_rxDws_vec[15:8], + pciw_pci0_rxDws_vec[23:16], + pciw_pci0_rxDws_vec[31:24], + pciw_pci0_rxDws_vec[39:32], + pciw_pci0_rxDws_vec[47:40], + pciw_pci0_rxDws_vec[55:48], + pciw_pci0_rxDws_vec[63:56], + pciw_pci0_rxDws_vec[71:64], + pciw_pci0_rxDws_vec[79:72], + pciw_pci0_rxDws_vec[87:80], + pciw_pci0_rxDws_vec[95:88], + pciw_pci0_rxDws_vec[103:96], + pciw_pci0_rxDws_vec[111:104], + pciw_pci0_rxDws_vec[119:112], + pciw_pci0_rxDws_vec[127:120] } ; + assign x_data__h46011 = + pciw_pci0_txInFlight ? + pciw_pci0_txDws_vec[127:0] : + { IF_pciw_pci0_txHeadF_first__59_BIT_11_60_THEN__ETC___d468, + pciw_pci0_txDws_vec[71:64], + pciw_pci0_txDws_vec[79:72], + pciw_pci0_txDws_vec[87:80], + pciw_pci0_txDws_vec[95:88], + pciw_pci0_txDws_vec[39:32], + pciw_pci0_txDws_vec[47:40], + pciw_pci0_txDws_vec[55:48], + pciw_pci0_txDws_vec[63:56], + pciw_pci0_txDws_vec[7:0], + pciw_pci0_txDws_vec[15:8], + pciw_pci0_txDws_vec[23:16], + pciw_pci0_txDws_vec[31:24] } ; + assign x_hit__h22096 = + pciw_pci0_pcie_ep$rx_st_sop0 ? bar___1__h22106 : 8'd0 ; + assign y__h56416 = { 16'd0, pciw_pci0_txDbgDeDeq } ; + assign y__h56418 = { 16'd0, pciw_pci0_txDbgEnEnq } ; + assign y__h56420 = { 16'd0, pciw_pci0_txDbgDeEof } ; + assign y__h56422 = { 16'd0, pciw_pci0_txDbgDeSof } ; + assign y__h56424 = { 16'd0, pciw_pci0_txDbgEnEof } ; + assign y__h56426 = { 16'd0, pciw_pci0_txDbgEnSof } ; + assign y__h56428 = { 16'd0, pciw_pci0_txDbgDestage } ; + assign y__h56430 = { 16'd0, pciw_pci0_txDbgEnstage } ; + assign y__h56432 = { 16'd0, pciw_pci0_txDbgExstage } ; + assign y__h56434 = { 31'd0, pciw_pci0_txInFlight } ; + assign y__h56436 = { 16'd0, pciw_pci0_rxDbgDeDeq } ; + assign y__h56438 = { 16'd0, pciw_pci0_rxDbgEnEnq } ; + assign y__h56440 = { 16'd0, pciw_pci0_rxDbgDeEof } ; + assign y__h56442 = { 16'd0, pciw_pci0_rxDbgDeSof } ; + assign y__h56444 = { 16'd0, pciw_pci0_rxDbgEnEof } ; + assign y__h56446 = { 16'd0, pciw_pci0_rxDbgEnSof } ; + assign y__h56448 = { 16'd0, pciw_pci0_rxDbgDestage } ; + assign y__h56450 = { 16'd0, pciw_pci0_rxDbgEnstage } ; + assign y__h56452 = { 16'd0, pciw_pci0_rxDbgInstage } ; + assign y__h56454 = { 31'd0, pciw_pci0_rxInFlight } ; + assign z__h55844 = swReg[0] ^ swReg[1] ; + assign z__h55851 = z__h55844 ^ swReg[2] ; + assign z__h55858 = z__h55851 ^ swReg[3] ; + assign z__h55865 = z__h55858 ^ swReg[4] ; + assign z__h55872 = z__h55865 ^ swReg[5] ; + assign z__h55879 = z__h55872 ^ swReg[6] ; + assign z__h56129 = + pciw_pci0_pcie_ep_ava_debug__52_OR_0_CONCAT_pc_ETC___d831[0] ^ + pciw_pci0_pcie_ep_ava_debug__52_OR_0_CONCAT_pc_ETC___d831[1] ; + assign z__h56136 = + z__h56129 ^ + pciw_pci0_pcie_ep_ava_debug__52_OR_0_CONCAT_pc_ETC___d831[2] ; + assign z__h56143 = + z__h56136 ^ + pciw_pci0_pcie_ep_ava_debug__52_OR_0_CONCAT_pc_ETC___d831[3] ; + assign z__h56150 = + z__h56143 ^ + pciw_pci0_pcie_ep_ava_debug__52_OR_0_CONCAT_pc_ETC___d831[4] ; + assign z__h56157 = + z__h56150 ^ + pciw_pci0_pcie_ep_ava_debug__52_OR_0_CONCAT_pc_ETC___d831[5] ; + assign z__h56164 = + z__h56157 ^ + pciw_pci0_pcie_ep_ava_debug__52_OR_0_CONCAT_pc_ETC___d831[6] ; + assign z__h56171 = + z__h56164 ^ + pciw_pci0_pcie_ep_ava_debug__52_OR_0_CONCAT_pc_ETC___d831[7] ; + assign z__h56178 = + z__h56171 ^ + pciw_pci0_pcie_ep_ava_debug__52_OR_0_CONCAT_pc_ETC___d831[8] ; + assign z__h56185 = + z__h56178 ^ + pciw_pci0_pcie_ep_ava_debug__52_OR_0_CONCAT_pc_ETC___d831[9] ; + assign z__h56192 = + z__h56185 ^ + pciw_pci0_pcie_ep_ava_debug__52_OR_0_CONCAT_pc_ETC___d831[10] ; + assign z__h56199 = + z__h56192 ^ + pciw_pci0_pcie_ep_ava_debug__52_OR_0_CONCAT_pc_ETC___d831[11] ; + assign z__h56206 = + z__h56199 ^ + pciw_pci0_pcie_ep_ava_debug__52_OR_0_CONCAT_pc_ETC___d831[12] ; + assign z__h56213 = + z__h56206 ^ + pciw_pci0_pcie_ep_ava_debug__52_OR_0_CONCAT_pc_ETC___d831[13] ; + assign z__h56220 = + z__h56213 ^ + pciw_pci0_pcie_ep_ava_debug__52_OR_0_CONCAT_pc_ETC___d831[14] ; + assign z__h56227 = + z__h56220 ^ + pciw_pci0_pcie_ep_ava_debug__52_OR_0_CONCAT_pc_ETC___d831[15] ; + assign z__h56234 = + z__h56227 ^ + pciw_pci0_pcie_ep_ava_debug__52_OR_0_CONCAT_pc_ETC___d831[16] ; + assign z__h56241 = + z__h56234 ^ + pciw_pci0_pcie_ep_ava_debug__52_OR_0_CONCAT_pc_ETC___d831[17] ; + assign z__h56248 = + z__h56241 ^ + pciw_pci0_pcie_ep_ava_debug__52_OR_0_CONCAT_pc_ETC___d831[18] ; + assign z__h56255 = + z__h56248 ^ + pciw_pci0_pcie_ep_ava_debug__52_OR_0_CONCAT_pc_ETC___d831[19] ; + assign z__h56262 = + z__h56255 ^ + pciw_pci0_pcie_ep_ava_debug__52_OR_0_CONCAT_pc_ETC___d831[20] ; + assign z__h56269 = + z__h56262 ^ + pciw_pci0_pcie_ep_ava_debug__52_OR_0_CONCAT_pc_ETC___d831[21] ; + assign z__h56276 = + z__h56269 ^ + pciw_pci0_pcie_ep_ava_debug__52_OR_0_CONCAT_pc_ETC___d831[22] ; + assign z__h56283 = + z__h56276 ^ + pciw_pci0_pcie_ep_ava_debug__52_OR_0_CONCAT_pc_ETC___d831[23] ; + assign z__h56290 = + z__h56283 ^ + pciw_pci0_pcie_ep_ava_debug__52_OR_0_CONCAT_pc_ETC___d831[24] ; + assign z__h56297 = + z__h56290 ^ + pciw_pci0_pcie_ep_ava_debug__52_OR_0_CONCAT_pc_ETC___d831[25] ; + assign z__h56304 = + z__h56297 ^ + pciw_pci0_pcie_ep_ava_debug__52_OR_0_CONCAT_pc_ETC___d831[26] ; + assign z__h56311 = + z__h56304 ^ + pciw_pci0_pcie_ep_ava_debug__52_OR_0_CONCAT_pc_ETC___d831[27] ; + assign z__h56318 = + z__h56311 ^ + pciw_pci0_pcie_ep_ava_debug__52_OR_0_CONCAT_pc_ETC___d831[28] ; + assign z__h56325 = + z__h56318 ^ + pciw_pci0_pcie_ep_ava_debug__52_OR_0_CONCAT_pc_ETC___d831[29] ; + assign z__h56332 = + z__h56325 ^ + pciw_pci0_pcie_ep_ava_debug__52_OR_0_CONCAT_pc_ETC___d831[30] ; + always@(IF_IF_pciw_pci0_rxInFlight_76_THEN_pciw_pci0_r_ETC__q2) + begin + case (IF_IF_pciw_pci0_rxInFlight_76_THEN_pciw_pci0_r_ETC__q2[2:0]) + 3'd0: IF_IF_IF_pciw_pci0_rxInFlight_76_THEN_pciw_pci_ETC___d787 = 16'h0; + 3'd1: + IF_IF_IF_pciw_pci0_rxInFlight_76_THEN_pciw_pci_ETC___d787 = + 16'h000F; + 3'd2: + IF_IF_IF_pciw_pci0_rxInFlight_76_THEN_pciw_pci_ETC___d787 = + 16'h00FF; + 3'd3: + IF_IF_IF_pciw_pci0_rxInFlight_76_THEN_pciw_pci_ETC___d787 = + 16'h0FFF; + default: IF_IF_IF_pciw_pci0_rxInFlight_76_THEN_pciw_pci_ETC___d787 = + 16'hFFFF; + endcase + end + + // handling of inlined registers + + always@(posedge pciw_pci0_pcie_ep$ava_core_clk_out) + begin + if (pciw_pci0_pcie_ep$ava_srstn == `BSV_RESET_VALUE) + begin + freeCnt <= `BSV_ASSIGNMENT_DELAY 32'd0; + hsmcReg <= `BSV_ASSIGNMENT_DELAY 16'd0; + ledReg <= `BSV_ASSIGNMENT_DELAY 16'd0; + needs_init <= `BSV_ASSIGNMENT_DELAY 1'd1; + pciDevice <= `BSV_ASSIGNMENT_DELAY 16'd0; + pciw_pci0_cfgDataWr <= `BSV_ASSIGNMENT_DELAY 1'h0; + pciw_pci0_cfgSample <= `BSV_ASSIGNMENT_DELAY 1'h0; + pciw_pci0_deviceReg <= `BSV_ASSIGNMENT_DELAY 16'hAAAA; + pciw_pci0_rxDbgDeDeq <= `BSV_ASSIGNMENT_DELAY 16'd0; + pciw_pci0_rxDbgDeEof <= `BSV_ASSIGNMENT_DELAY 16'd0; + pciw_pci0_rxDbgDeSof <= `BSV_ASSIGNMENT_DELAY 16'd0; + pciw_pci0_rxDbgDestage <= `BSV_ASSIGNMENT_DELAY 16'd0; + pciw_pci0_rxDbgEnEnq <= `BSV_ASSIGNMENT_DELAY 16'd0; + pciw_pci0_rxDbgEnEof <= `BSV_ASSIGNMENT_DELAY 16'd0; + pciw_pci0_rxDbgEnSof <= `BSV_ASSIGNMENT_DELAY 16'd0; + pciw_pci0_rxDbgEnstage <= `BSV_ASSIGNMENT_DELAY 16'd0; + pciw_pci0_rxDbgInstage <= `BSV_ASSIGNMENT_DELAY 16'd0; + pciw_pci0_rxDwrDeq <= `BSV_ASSIGNMENT_DELAY 11'd0; + pciw_pci0_rxDwrEnq <= `BSV_ASSIGNMENT_DELAY 11'd0; + pciw_pci0_rxDws_num_empty <= `BSV_ASSIGNMENT_DELAY 4'd8; + pciw_pci0_rxDws_num_full <= `BSV_ASSIGNMENT_DELAY 4'd0; + pciw_pci0_rxDws_vec <= `BSV_ASSIGNMENT_DELAY 256'd0; + pciw_pci0_rxInF_countReg <= `BSV_ASSIGNMENT_DELAY 6'd0; + pciw_pci0_rxInF_levelsValid <= `BSV_ASSIGNMENT_DELAY 1'd1; + pciw_pci0_rxInFlight <= `BSV_ASSIGNMENT_DELAY 1'd0; + pciw_pci0_txDbgDeDeq <= `BSV_ASSIGNMENT_DELAY 16'd0; + pciw_pci0_txDbgDeEof <= `BSV_ASSIGNMENT_DELAY 16'd0; + pciw_pci0_txDbgDeSof <= `BSV_ASSIGNMENT_DELAY 16'd0; + pciw_pci0_txDbgDestage <= `BSV_ASSIGNMENT_DELAY 16'd0; + pciw_pci0_txDbgEnEnq <= `BSV_ASSIGNMENT_DELAY 16'd0; + pciw_pci0_txDbgEnEof <= `BSV_ASSIGNMENT_DELAY 16'd0; + pciw_pci0_txDbgEnSof <= `BSV_ASSIGNMENT_DELAY 16'd0; + pciw_pci0_txDbgEnstage <= `BSV_ASSIGNMENT_DELAY 16'd0; + pciw_pci0_txDbgExstage <= `BSV_ASSIGNMENT_DELAY 16'd0; + pciw_pci0_txDwrDeq <= `BSV_ASSIGNMENT_DELAY 11'd0; + pciw_pci0_txDwrEnq <= `BSV_ASSIGNMENT_DELAY 11'd0; + pciw_pci0_txDws_num_empty <= `BSV_ASSIGNMENT_DELAY 4'd8; + pciw_pci0_txDws_num_full <= `BSV_ASSIGNMENT_DELAY 4'd0; + pciw_pci0_txDws_vec <= `BSV_ASSIGNMENT_DELAY 256'd0; + pciw_pci0_txInFlight <= `BSV_ASSIGNMENT_DELAY 1'd0; + pciw_pci0_txOutF_countReg <= `BSV_ASSIGNMENT_DELAY 10'd0; + pciw_pci0_txOutF_levelsValid <= `BSV_ASSIGNMENT_DELAY 1'd1; + pciw_pci0_txReadyD <= `BSV_ASSIGNMENT_DELAY 1'd0; + pciw_pciDevice <= `BSV_ASSIGNMENT_DELAY 16'd0; + swReg <= `BSV_ASSIGNMENT_DELAY 8'd0; + end + else + begin + if (freeCnt$EN) freeCnt <= `BSV_ASSIGNMENT_DELAY freeCnt$D_IN; + if (hsmcReg$EN) hsmcReg <= `BSV_ASSIGNMENT_DELAY hsmcReg$D_IN; + if (ledReg$EN) ledReg <= `BSV_ASSIGNMENT_DELAY ledReg$D_IN; + if (needs_init$EN) + needs_init <= `BSV_ASSIGNMENT_DELAY needs_init$D_IN; + if (pciDevice$EN) pciDevice <= `BSV_ASSIGNMENT_DELAY pciDevice$D_IN; + if (pciw_pci0_cfgDataWr$EN) + pciw_pci0_cfgDataWr <= `BSV_ASSIGNMENT_DELAY + pciw_pci0_cfgDataWr$D_IN; + if (pciw_pci0_cfgSample$EN) + pciw_pci0_cfgSample <= `BSV_ASSIGNMENT_DELAY + pciw_pci0_cfgSample$D_IN; + if (pciw_pci0_deviceReg$EN) + pciw_pci0_deviceReg <= `BSV_ASSIGNMENT_DELAY + pciw_pci0_deviceReg$D_IN; + if (pciw_pci0_rxDbgDeDeq$EN) + pciw_pci0_rxDbgDeDeq <= `BSV_ASSIGNMENT_DELAY + pciw_pci0_rxDbgDeDeq$D_IN; + if (pciw_pci0_rxDbgDeEof$EN) + pciw_pci0_rxDbgDeEof <= `BSV_ASSIGNMENT_DELAY + pciw_pci0_rxDbgDeEof$D_IN; + if (pciw_pci0_rxDbgDeSof$EN) + pciw_pci0_rxDbgDeSof <= `BSV_ASSIGNMENT_DELAY + pciw_pci0_rxDbgDeSof$D_IN; + if (pciw_pci0_rxDbgDestage$EN) + pciw_pci0_rxDbgDestage <= `BSV_ASSIGNMENT_DELAY + pciw_pci0_rxDbgDestage$D_IN; + if (pciw_pci0_rxDbgEnEnq$EN) + pciw_pci0_rxDbgEnEnq <= `BSV_ASSIGNMENT_DELAY + pciw_pci0_rxDbgEnEnq$D_IN; + if (pciw_pci0_rxDbgEnEof$EN) + pciw_pci0_rxDbgEnEof <= `BSV_ASSIGNMENT_DELAY + pciw_pci0_rxDbgEnEof$D_IN; + if (pciw_pci0_rxDbgEnSof$EN) + pciw_pci0_rxDbgEnSof <= `BSV_ASSIGNMENT_DELAY + pciw_pci0_rxDbgEnSof$D_IN; + if (pciw_pci0_rxDbgEnstage$EN) + pciw_pci0_rxDbgEnstage <= `BSV_ASSIGNMENT_DELAY + pciw_pci0_rxDbgEnstage$D_IN; + if (pciw_pci0_rxDbgInstage$EN) + pciw_pci0_rxDbgInstage <= `BSV_ASSIGNMENT_DELAY + pciw_pci0_rxDbgInstage$D_IN; + if (pciw_pci0_rxDwrDeq$EN) + pciw_pci0_rxDwrDeq <= `BSV_ASSIGNMENT_DELAY pciw_pci0_rxDwrDeq$D_IN; + if (pciw_pci0_rxDwrEnq$EN) + pciw_pci0_rxDwrEnq <= `BSV_ASSIGNMENT_DELAY pciw_pci0_rxDwrEnq$D_IN; + if (pciw_pci0_rxDws_num_empty$EN) + pciw_pci0_rxDws_num_empty <= `BSV_ASSIGNMENT_DELAY + pciw_pci0_rxDws_num_empty$D_IN; + if (pciw_pci0_rxDws_num_full$EN) + pciw_pci0_rxDws_num_full <= `BSV_ASSIGNMENT_DELAY + pciw_pci0_rxDws_num_full$D_IN; + if (pciw_pci0_rxDws_vec$EN) + pciw_pci0_rxDws_vec <= `BSV_ASSIGNMENT_DELAY + pciw_pci0_rxDws_vec$D_IN; + if (pciw_pci0_rxInF_countReg$EN) + pciw_pci0_rxInF_countReg <= `BSV_ASSIGNMENT_DELAY + pciw_pci0_rxInF_countReg$D_IN; + if (pciw_pci0_rxInF_levelsValid$EN) + pciw_pci0_rxInF_levelsValid <= `BSV_ASSIGNMENT_DELAY + pciw_pci0_rxInF_levelsValid$D_IN; + if (pciw_pci0_rxInFlight$EN) + pciw_pci0_rxInFlight <= `BSV_ASSIGNMENT_DELAY + pciw_pci0_rxInFlight$D_IN; + if (pciw_pci0_txDbgDeDeq$EN) + pciw_pci0_txDbgDeDeq <= `BSV_ASSIGNMENT_DELAY + pciw_pci0_txDbgDeDeq$D_IN; + if (pciw_pci0_txDbgDeEof$EN) + pciw_pci0_txDbgDeEof <= `BSV_ASSIGNMENT_DELAY + pciw_pci0_txDbgDeEof$D_IN; + if (pciw_pci0_txDbgDeSof$EN) + pciw_pci0_txDbgDeSof <= `BSV_ASSIGNMENT_DELAY + pciw_pci0_txDbgDeSof$D_IN; + if (pciw_pci0_txDbgDestage$EN) + pciw_pci0_txDbgDestage <= `BSV_ASSIGNMENT_DELAY + pciw_pci0_txDbgDestage$D_IN; + if (pciw_pci0_txDbgEnEnq$EN) + pciw_pci0_txDbgEnEnq <= `BSV_ASSIGNMENT_DELAY + pciw_pci0_txDbgEnEnq$D_IN; + if (pciw_pci0_txDbgEnEof$EN) + pciw_pci0_txDbgEnEof <= `BSV_ASSIGNMENT_DELAY + pciw_pci0_txDbgEnEof$D_IN; + if (pciw_pci0_txDbgEnSof$EN) + pciw_pci0_txDbgEnSof <= `BSV_ASSIGNMENT_DELAY + pciw_pci0_txDbgEnSof$D_IN; + if (pciw_pci0_txDbgEnstage$EN) + pciw_pci0_txDbgEnstage <= `BSV_ASSIGNMENT_DELAY + pciw_pci0_txDbgEnstage$D_IN; + if (pciw_pci0_txDbgExstage$EN) + pciw_pci0_txDbgExstage <= `BSV_ASSIGNMENT_DELAY + pciw_pci0_txDbgExstage$D_IN; + if (pciw_pci0_txDwrDeq$EN) + pciw_pci0_txDwrDeq <= `BSV_ASSIGNMENT_DELAY pciw_pci0_txDwrDeq$D_IN; + if (pciw_pci0_txDwrEnq$EN) + pciw_pci0_txDwrEnq <= `BSV_ASSIGNMENT_DELAY pciw_pci0_txDwrEnq$D_IN; + if (pciw_pci0_txDws_num_empty$EN) + pciw_pci0_txDws_num_empty <= `BSV_ASSIGNMENT_DELAY + pciw_pci0_txDws_num_empty$D_IN; + if (pciw_pci0_txDws_num_full$EN) + pciw_pci0_txDws_num_full <= `BSV_ASSIGNMENT_DELAY + pciw_pci0_txDws_num_full$D_IN; + if (pciw_pci0_txDws_vec$EN) + pciw_pci0_txDws_vec <= `BSV_ASSIGNMENT_DELAY + pciw_pci0_txDws_vec$D_IN; + if (pciw_pci0_txInFlight$EN) + pciw_pci0_txInFlight <= `BSV_ASSIGNMENT_DELAY + pciw_pci0_txInFlight$D_IN; + if (pciw_pci0_txOutF_countReg$EN) + pciw_pci0_txOutF_countReg <= `BSV_ASSIGNMENT_DELAY + pciw_pci0_txOutF_countReg$D_IN; + if (pciw_pci0_txOutF_levelsValid$EN) + pciw_pci0_txOutF_levelsValid <= `BSV_ASSIGNMENT_DELAY + pciw_pci0_txOutF_levelsValid$D_IN; + if (pciw_pci0_txReadyD$EN) + pciw_pci0_txReadyD <= `BSV_ASSIGNMENT_DELAY pciw_pci0_txReadyD$D_IN; + if (pciw_pciDevice$EN) + pciw_pciDevice <= `BSV_ASSIGNMENT_DELAY pciw_pciDevice$D_IN; + if (swReg$EN) swReg <= `BSV_ASSIGNMENT_DELAY swReg$D_IN; + end + end + + // synopsys translate_off + `ifdef BSV_NO_INITIAL_BLOCKS + `else // not BSV_NO_INITIAL_BLOCKS + initial + begin + freeCnt = 32'hAAAAAAAA; + hsmcReg = 16'hAAAA; + ledReg = 16'hAAAA; + needs_init = 1'h0; + pciDevice = 16'hAAAA; + pciw_pci0_cfgDataWr = 1'h0; + pciw_pci0_cfgSample = 1'h0; + pciw_pci0_deviceReg = 16'hAAAA; + pciw_pci0_rxDbgDeDeq = 16'hAAAA; + pciw_pci0_rxDbgDeEof = 16'hAAAA; + pciw_pci0_rxDbgDeSof = 16'hAAAA; + pciw_pci0_rxDbgDestage = 16'hAAAA; + pciw_pci0_rxDbgEnEnq = 16'hAAAA; + pciw_pci0_rxDbgEnEof = 16'hAAAA; + pciw_pci0_rxDbgEnSof = 16'hAAAA; + pciw_pci0_rxDbgEnstage = 16'hAAAA; + pciw_pci0_rxDbgInstage = 16'hAAAA; + pciw_pci0_rxDwrDeq = 11'h2AA; + pciw_pci0_rxDwrEnq = 11'h2AA; + pciw_pci0_rxDws_num_empty = 4'hA; + pciw_pci0_rxDws_num_full = 4'hA; + pciw_pci0_rxDws_vec = + 256'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; + pciw_pci0_rxInF_countReg = 6'h2A; + pciw_pci0_rxInF_levelsValid = 1'h0; + pciw_pci0_rxInFlight = 1'h0; + pciw_pci0_txDbgDeDeq = 16'hAAAA; + pciw_pci0_txDbgDeEof = 16'hAAAA; + pciw_pci0_txDbgDeSof = 16'hAAAA; + pciw_pci0_txDbgDestage = 16'hAAAA; + pciw_pci0_txDbgEnEnq = 16'hAAAA; + pciw_pci0_txDbgEnEof = 16'hAAAA; + pciw_pci0_txDbgEnSof = 16'hAAAA; + pciw_pci0_txDbgEnstage = 16'hAAAA; + pciw_pci0_txDbgExstage = 16'hAAAA; + pciw_pci0_txDwrDeq = 11'h2AA; + pciw_pci0_txDwrEnq = 11'h2AA; + pciw_pci0_txDws_num_empty = 4'hA; + pciw_pci0_txDws_num_full = 4'hA; + pciw_pci0_txDws_vec = + 256'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; + pciw_pci0_txInFlight = 1'h0; + pciw_pci0_txOutF_countReg = 10'h2AA; + pciw_pci0_txOutF_levelsValid = 1'h0; + pciw_pci0_txReadyD = 1'h0; + pciw_pciDevice = 16'hAAAA; + swReg = 8'hAA; + end + `endif // BSV_NO_INITIAL_BLOCKS + // synopsys translate_on +endmodule // mkFTop_alst4 + diff --git a/rtl/mkFTop_ml605.v b/rtl/mkFTop_ml605.v index da281e43..de44f113 100644 --- a/rtl/mkFTop_ml605.v +++ b/rtl/mkFTop_ml605.v @@ -1,7 +1,7 @@ // -// Generated by Bluespec Compiler, version 2012.09.beta1 (build 29570, 2012-09.11) +// Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Wed Nov 28 10:39:25 EST 2012 +// On Fri Jun 21 17:01:19 EDT 2013 // // // Ports: @@ -1036,14 +1036,14 @@ module mkFTop_ml605(sys0_clkp, wire [152 : 0] MUX_pciw_p2iS$write_1__VAL_1, MUX_pciw_p2iS$write_1__VAL_2; wire [81 : 0] MUX_pciw_Prelude_inst_changeSpecialWires_1_rg$write_1__VAL_1, MUX_pciw_Prelude_inst_changeSpecialWires_2_rg$write_1__VAL_1; - wire [80 : 0] MUX_pciw_fI2P$enq_1__VAL_1; + wire [80 : 0] MUX_pciw_fI2P$enq_1__VAL_2; wire MUX_pciw_Prelude_inst_changeSpecialWires_1_rg$write_1__SEL_1, MUX_pciw_Prelude_inst_changeSpecialWires_2_rg$write_1__SEL_1, MUX_pciw_p2iS$write_1__SEL_1; // remaining internal signals - wire [127 : 0] val_data__h6517, wOut_data__h6626; - wire [15 : 0] val_be__h6516, wOut_be__h6625; + wire [127 : 0] val_data__h6496, wOut_data__h6605; + wire [15 : 0] val_be__h6495, wOut_be__h6604; wire pciw_p2iAF_head_wrapped_crossed__4_EQ_pciw_p2i_ETC___d123; // oscillator and gates for output clock p125clk @@ -1849,7 +1849,7 @@ module mkFTop_ml605(sys0_clkp, pciw_i2pS[151:144], pciw_i2pS[135:128], pciw_i2pS[63:0] } ; - assign MUX_pciw_fI2P$enq_1__VAL_1 = + assign MUX_pciw_fI2P$enq_1__VAL_2 = (pciw_i2pS[135:128] == 8'd0) ? { pciw_i2pS[152:136], pciw_i2pS[127:64] } : { pciw_i2pS[152], @@ -1857,13 +1857,13 @@ module mkFTop_ml605(sys0_clkp, pciw_i2pS[150:136], pciw_i2pS[127:64] } ; assign MUX_pciw_p2iS$write_1__VAL_1 = - { pciw_fP2I$D_OUT[80:72], val_be__h6516, val_data__h6517 } ; + { pciw_fP2I$D_OUT[80:72], val_be__h6495, val_data__h6496 } ; assign MUX_pciw_p2iS$write_1__VAL_2 = { pciw_Prelude_inst_changeSpecialWires_1_rg[80], pciw_fP2I$D_OUT[79], pciw_Prelude_inst_changeSpecialWires_1_rg[78:72], - wOut_be__h6625, - wOut_data__h6626 } ; + wOut_be__h6604, + wOut_data__h6605 } ; // inlined wires assign pciw_pci0_wTrnTxSof_n$wget = !pciw_fI2P$D_OUT[80] ; @@ -2087,10 +2087,10 @@ module mkFTop_ml605(sys0_clkp, !pciw_i2pAF_sInReset_isInReset && ctop$RDY_server_response_get ; assign ctop$EN_cpServer_request_put = - ctop$RDY_cpServer_request_put && gbe0$RDY_cpClient_request_get ; + gbe0$RDY_cpClient_request_get && ctop$RDY_cpServer_request_put ; assign ctop$EN_cpServer_response_get = - ctop$RDY_cpServer_response_get && - gbe0$RDY_cpClient_response_put ; + gbe0$RDY_cpClient_response_put && + ctop$RDY_cpServer_response_get ; assign ctop$wci_m_0_SThreadBusy = fmc150$wciS0_SThreadBusy ; assign ctop$wci_m_1_SThreadBusy = flash0$wciS0_SThreadBusy ; assign ctop$wci_m_2_SThreadBusy = gbe0$wciS0_SThreadBusy ; @@ -2167,10 +2167,10 @@ module mkFTop_ml605(sys0_clkp, assign gbe0$wsiS0_MBurstPrecise = 1'b0 ; assign gbe0$wsiS0_MReset_n = 1'b0 ; assign gbe0$EN_cpClient_request_get = - ctop$RDY_cpServer_request_put && gbe0$RDY_cpClient_request_get ; + gbe0$RDY_cpClient_request_get && ctop$RDY_cpServer_request_put ; assign gbe0$EN_cpClient_response_put = - ctop$RDY_cpServer_response_get && - gbe0$RDY_cpClient_response_put ; + gbe0$RDY_cpClient_response_put && + ctop$RDY_cpServer_response_get ; // submodule lcd_ctrl assign lcd_ctrl$setLine1_text = 128'h202073656C75522063696D6F74412020 ; @@ -2180,12 +2180,12 @@ module mkFTop_ml605(sys0_clkp, // submodule pciw_fI2P assign pciw_fI2P$D_IN = - WILL_FIRE_RL_pciw_Prelude_inst_changeSpecialWires_2_downconv_connect1 ? - MUX_pciw_fI2P$enq_1__VAL_1 : - pciw_Prelude_inst_changeSpecialWires_2_rg[80:0] ; + WILL_FIRE_RL_pciw_Prelude_inst_changeSpecialWires_2_downconv_connect2 ? + pciw_Prelude_inst_changeSpecialWires_2_rg[80:0] : + MUX_pciw_fI2P$enq_1__VAL_2 ; assign pciw_fI2P$ENQ = - WILL_FIRE_RL_pciw_Prelude_inst_changeSpecialWires_2_downconv_connect1 || - WILL_FIRE_RL_pciw_Prelude_inst_changeSpecialWires_2_downconv_connect2 ; + WILL_FIRE_RL_pciw_Prelude_inst_changeSpecialWires_2_downconv_connect2 || + WILL_FIRE_RL_pciw_Prelude_inst_changeSpecialWires_2_downconv_connect1 ; assign pciw_fI2P$DEQ = pciw_pci0_pwTrnTx$whas ; assign pciw_fI2P$CLR = 1'b0 ; @@ -2283,12 +2283,12 @@ module mkFTop_ml605(sys0_clkp, pciw_p2iAF_head_wrapped == pciw_p2iAF_tail_wrapped && !pciw_p2iAF_sInReset_isInReset && pciw_preEdge$CLK_VAL ; - assign val_be__h6516 = { pciw_fP2I$D_OUT[71:64], 8'd0 } ; - assign val_data__h6517 = { pciw_fP2I$D_OUT[63:0], 64'hAAAAAAAAAAAAAAAA } ; - assign wOut_be__h6625 = + assign val_be__h6495 = { pciw_fP2I$D_OUT[71:64], 8'd0 } ; + assign val_data__h6496 = { pciw_fP2I$D_OUT[63:0], 64'hAAAAAAAAAAAAAAAA } ; + assign wOut_be__h6604 = { pciw_Prelude_inst_changeSpecialWires_1_rg[71:64], pciw_fP2I$D_OUT[71:64] } ; - assign wOut_data__h6626 = + assign wOut_data__h6605 = { pciw_Prelude_inst_changeSpecialWires_1_rg[63:0], pciw_fP2I$D_OUT[63:0] } ; diff --git a/rtl/mkFlashController2416.v b/rtl/mkFlashController2416.v index 83d60716..20633007 100644 --- a/rtl/mkFlashController2416.v +++ b/rtl/mkFlashController2416.v @@ -1,7 +1,7 @@ // -// Generated by Bluespec Compiler, version 2012.09.beta1 (build 29570, 2012-09.11) +// Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Wed Nov 28 10:31:33 EST 2012 +// On Fri Jun 21 16:56:54 EDT 2013 // // // Ports: @@ -134,8 +134,8 @@ module mkFlashController2416(CLK, // inlined wires wire rseqFsm_abort$wget, rseqFsm_abort$whas, - rseqFsm_start_reg_1_1$wget, - rseqFsm_start_reg_1_1$whas, + rseqFsm_start_reg_2$wget, + rseqFsm_start_reg_2$whas, rseqFsm_start_wire$wget, rseqFsm_start_wire$whas, rseqFsm_state_fired_1$wget, @@ -144,8 +144,8 @@ module mkFlashController2416(CLK, rseqFsm_state_set_pw$whas, wseqFsm_abort$wget, wseqFsm_abort$whas, - wseqFsm_start_reg_1_1$wget, - wseqFsm_start_reg_1_1$whas, + wseqFsm_start_reg_2$wget, + wseqFsm_start_reg_2$whas, wseqFsm_start_wire$wget, wseqFsm_start_wire$whas, wseqFsm_state_fired_1$wget, @@ -223,16 +223,16 @@ module mkFlashController2416(CLK, reg weReg; wire weReg$D_IN, weReg$EN; + // register wseqFsm_jj_1_delay_count + reg [6 : 0] wseqFsm_jj_1_delay_count; + wire [6 : 0] wseqFsm_jj_1_delay_count$D_IN; + wire wseqFsm_jj_1_delay_count$EN; + // register wseqFsm_jj_2_delay_count reg [6 : 0] wseqFsm_jj_2_delay_count; wire [6 : 0] wseqFsm_jj_2_delay_count$D_IN; wire wseqFsm_jj_2_delay_count$EN; - // register wseqFsm_jj_4_delay_count - reg [6 : 0] wseqFsm_jj_4_delay_count; - wire [6 : 0] wseqFsm_jj_4_delay_count$D_IN; - wire wseqFsm_jj_4_delay_count$EN; - // register wseqFsm_jj_delay_count reg [6 : 0] wseqFsm_jj_delay_count; wire [6 : 0] wseqFsm_jj_delay_count$D_IN; @@ -310,8 +310,8 @@ module mkFlashController2416(CLK, // inputs to muxes for submodule ports wire [14 : 0] MUX_rseqFsm_jj_delay_count$write_1__VAL_1; - wire [6 : 0] MUX_wseqFsm_jj_2_delay_count$write_1__VAL_1, - MUX_wseqFsm_jj_4_delay_count$write_1__VAL_1, + wire [6 : 0] MUX_wseqFsm_jj_1_delay_count$write_1__VAL_1, + MUX_wseqFsm_jj_2_delay_count$write_1__VAL_1, MUX_wseqFsm_jj_delay_count$write_1__VAL_1; wire MUX_ceReg$write_1__SEL_1, MUX_oeReg$write_1__SEL_1, @@ -478,13 +478,13 @@ module mkFlashController2416(CLK, // rule RL_wseqFsm_action_np_2 assign WILL_FIRE_RL_wseqFsm_action_np_2 = - !isRead && !wseqFsm_jj_2_delay_count[6] && + !isRead && !wseqFsm_jj_1_delay_count[6] && (wseqFsm_state_mkFSMstate == 5'd13 || wseqFsm_state_mkFSMstate == 5'd14) ; // rule RL_wseqFsm_action_l82c12 assign WILL_FIRE_RL_wseqFsm_action_l82c12 = - !isRead && wseqFsm_jj_2_delay_count[6] && + !isRead && wseqFsm_jj_1_delay_count[6] && (wseqFsm_state_mkFSMstate == 5'd13 || wseqFsm_state_mkFSMstate == 5'd14) ; @@ -514,13 +514,13 @@ module mkFlashController2416(CLK, // rule RL_wseqFsm_action_np_4 assign WILL_FIRE_RL_wseqFsm_action_np_4 = - !isRead && !wseqFsm_jj_4_delay_count[6] && + !isRead && !wseqFsm_jj_2_delay_count[6] && (wseqFsm_state_mkFSMstate == 5'd21 || wseqFsm_state_mkFSMstate == 5'd22) ; // rule RL_wseqFsm_action_l90c12 assign WILL_FIRE_RL_wseqFsm_action_l90c12 = - !isRead && wseqFsm_jj_4_delay_count[6] && + !isRead && wseqFsm_jj_2_delay_count[6] && (wseqFsm_state_mkFSMstate == 5'd21 || wseqFsm_state_mkFSMstate == 5'd22) ; @@ -570,10 +570,10 @@ module mkFlashController2416(CLK, WILL_FIRE_RL_nextRequest && !reqF$D_OUT[40] ; assign MUX_rseqFsm_jj_delay_count$write_1__VAL_1 = { rseqFsm_jj_delay_count[13:0], 1'd0 } ; + assign MUX_wseqFsm_jj_1_delay_count$write_1__VAL_1 = + { wseqFsm_jj_1_delay_count[5:0], 1'd0 } ; assign MUX_wseqFsm_jj_2_delay_count$write_1__VAL_1 = { wseqFsm_jj_2_delay_count[5:0], 1'd0 } ; - assign MUX_wseqFsm_jj_4_delay_count$write_1__VAL_1 = - { wseqFsm_jj_4_delay_count[5:0], 1'd0 } ; assign MUX_wseqFsm_jj_delay_count$write_1__VAL_1 = { wseqFsm_jj_delay_count[5:0], 1'd0 } ; @@ -582,8 +582,8 @@ module mkFlashController2416(CLK, assign rseqFsm_start_wire$whas = WILL_FIRE_RL_rseqFsm_fsm_start || rseqFsm_start_reg_1 && !rseqFsm_state_fired ; - assign rseqFsm_start_reg_1_1$wget = 1'd1 ; - assign rseqFsm_start_reg_1_1$whas = rseqFsm_start_wire$whas ; + assign rseqFsm_start_reg_2$wget = 1'd1 ; + assign rseqFsm_start_reg_2$whas = rseqFsm_start_wire$whas ; assign rseqFsm_abort$wget = 1'b0 ; assign rseqFsm_abort$whas = 1'b0 ; assign rseqFsm_state_fired_1$wget = 1'd1 ; @@ -592,8 +592,8 @@ module mkFlashController2416(CLK, assign wseqFsm_start_wire$whas = WILL_FIRE_RL_wseqFsm_fsm_start || wseqFsm_start_reg_1 && !wseqFsm_state_fired ; - assign wseqFsm_start_reg_1_1$wget = 1'd1 ; - assign wseqFsm_start_reg_1_1$whas = wseqFsm_start_wire$whas ; + assign wseqFsm_start_reg_2$wget = 1'd1 ; + assign wseqFsm_start_reg_2$whas = wseqFsm_start_wire$whas ; assign wseqFsm_abort$wget = 1'b0 ; assign wseqFsm_abort$whas = 1'b0 ; assign wseqFsm_state_fired_1$wget = 1'd1 ; @@ -763,21 +763,21 @@ module mkFlashController2416(CLK, WILL_FIRE_RL_wseqFsm_action_l80c12 || WILL_FIRE_RL_wseqFsm_action_l73c12 ; - // register wseqFsm_jj_2_delay_count - assign wseqFsm_jj_2_delay_count$D_IN = + // register wseqFsm_jj_1_delay_count + assign wseqFsm_jj_1_delay_count$D_IN = WILL_FIRE_RL_wseqFsm_action_np_2 ? - MUX_wseqFsm_jj_2_delay_count$write_1__VAL_1 : + MUX_wseqFsm_jj_1_delay_count$write_1__VAL_1 : 7'd1 ; - assign wseqFsm_jj_2_delay_count$EN = + assign wseqFsm_jj_1_delay_count$EN = WILL_FIRE_RL_wseqFsm_action_np_2 || WILL_FIRE_RL_wseqFsm_action_d_init_np_1 ; - // register wseqFsm_jj_4_delay_count - assign wseqFsm_jj_4_delay_count$D_IN = + // register wseqFsm_jj_2_delay_count + assign wseqFsm_jj_2_delay_count$D_IN = WILL_FIRE_RL_wseqFsm_action_np_4 ? - MUX_wseqFsm_jj_4_delay_count$write_1__VAL_1 : + MUX_wseqFsm_jj_2_delay_count$write_1__VAL_1 : 7'd1 ; - assign wseqFsm_jj_4_delay_count$EN = + assign wseqFsm_jj_2_delay_count$EN = WILL_FIRE_RL_wseqFsm_action_np_4 || WILL_FIRE_RL_wseqFsm_action_d_init_np_2 ; @@ -961,8 +961,8 @@ module mkFlashController2416(CLK, tsWD <= `BSV_ASSIGNMENT_DELAY 16'd0; wdReg <= `BSV_ASSIGNMENT_DELAY 16'd0; weReg <= `BSV_ASSIGNMENT_DELAY 1'd0; + wseqFsm_jj_1_delay_count <= `BSV_ASSIGNMENT_DELAY 7'd1; wseqFsm_jj_2_delay_count <= `BSV_ASSIGNMENT_DELAY 7'd1; - wseqFsm_jj_4_delay_count <= `BSV_ASSIGNMENT_DELAY 7'd1; wseqFsm_jj_delay_count <= `BSV_ASSIGNMENT_DELAY 7'd1; wseqFsm_start_reg <= `BSV_ASSIGNMENT_DELAY 1'd0; wseqFsm_start_reg_1 <= `BSV_ASSIGNMENT_DELAY 1'd0; @@ -998,12 +998,12 @@ module mkFlashController2416(CLK, if (tsWD$EN) tsWD <= `BSV_ASSIGNMENT_DELAY tsWD$D_IN; if (wdReg$EN) wdReg <= `BSV_ASSIGNMENT_DELAY wdReg$D_IN; if (weReg$EN) weReg <= `BSV_ASSIGNMENT_DELAY weReg$D_IN; + if (wseqFsm_jj_1_delay_count$EN) + wseqFsm_jj_1_delay_count <= `BSV_ASSIGNMENT_DELAY + wseqFsm_jj_1_delay_count$D_IN; if (wseqFsm_jj_2_delay_count$EN) wseqFsm_jj_2_delay_count <= `BSV_ASSIGNMENT_DELAY wseqFsm_jj_2_delay_count$D_IN; - if (wseqFsm_jj_4_delay_count$EN) - wseqFsm_jj_4_delay_count <= `BSV_ASSIGNMENT_DELAY - wseqFsm_jj_4_delay_count$D_IN; if (wseqFsm_jj_delay_count$EN) wseqFsm_jj_delay_count <= `BSV_ASSIGNMENT_DELAY wseqFsm_jj_delay_count$D_IN; @@ -1046,8 +1046,8 @@ module mkFlashController2416(CLK, waitReg = 1'h0; wdReg = 16'hAAAA; weReg = 1'h0; + wseqFsm_jj_1_delay_count = 7'h2A; wseqFsm_jj_2_delay_count = 7'h2A; - wseqFsm_jj_4_delay_count = 7'h2A; wseqFsm_jj_delay_count = 7'h2A; wseqFsm_start_reg = 1'h0; wseqFsm_start_reg_1 = 1'h0; diff --git a/rtl/mkFlashWorker.v b/rtl/mkFlashWorker.v index a9fed372..fabd7928 100644 --- a/rtl/mkFlashWorker.v +++ b/rtl/mkFlashWorker.v @@ -1,7 +1,7 @@ // -// Generated by Bluespec Compiler, version 2012.09.beta1 (build 29570, 2012-09.11) +// Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Wed Nov 28 10:31:59 EST 2012 +// On Fri Jun 21 16:57:20 EDT 2013 // // // Ports: @@ -165,8 +165,8 @@ module mkFlashWorker(wciS0_Clk, wire [2 : 0] wci_wci_Es_mCmd_w$wget, wci_wslv_wEdge$wget; wire flashC_rseqFsm_abort$wget, flashC_rseqFsm_abort$whas, - flashC_rseqFsm_start_reg_1_1$wget, - flashC_rseqFsm_start_reg_1_1$whas, + flashC_rseqFsm_start_reg_2$wget, + flashC_rseqFsm_start_reg_2$whas, flashC_rseqFsm_start_wire$wget, flashC_rseqFsm_start_wire$whas, flashC_rseqFsm_state_fired_1$wget, @@ -175,8 +175,8 @@ module mkFlashWorker(wciS0_Clk, flashC_rseqFsm_state_set_pw$whas, flashC_wseqFsm_abort$wget, flashC_wseqFsm_abort$whas, - flashC_wseqFsm_start_reg_1_1$wget, - flashC_wseqFsm_start_reg_1_1$whas, + flashC_wseqFsm_start_reg_2$wget, + flashC_wseqFsm_start_reg_2$whas, flashC_wseqFsm_start_wire$wget, flashC_wseqFsm_start_wire$whas, flashC_wseqFsm_state_fired_1$wget, @@ -282,16 +282,16 @@ module mkFlashWorker(wciS0_Clk, reg flashC_weReg; wire flashC_weReg$D_IN, flashC_weReg$EN; + // register flashC_wseqFsm_jj_1_delay_count + reg [6 : 0] flashC_wseqFsm_jj_1_delay_count; + wire [6 : 0] flashC_wseqFsm_jj_1_delay_count$D_IN; + wire flashC_wseqFsm_jj_1_delay_count$EN; + // register flashC_wseqFsm_jj_2_delay_count reg [6 : 0] flashC_wseqFsm_jj_2_delay_count; wire [6 : 0] flashC_wseqFsm_jj_2_delay_count$D_IN; wire flashC_wseqFsm_jj_2_delay_count$EN; - // register flashC_wseqFsm_jj_4_delay_count - reg [6 : 0] flashC_wseqFsm_jj_4_delay_count; - wire [6 : 0] flashC_wseqFsm_jj_4_delay_count$D_IN; - wire flashC_wseqFsm_jj_4_delay_count$EN; - // register flashC_wseqFsm_jj_delay_count reg [6 : 0] flashC_wseqFsm_jj_delay_count; wire [6 : 0] flashC_wseqFsm_jj_delay_count$D_IN; @@ -369,10 +369,10 @@ module mkFlashWorker(wciS0_Clk, wire [1 : 0] wci_wslv_reqF_countReg$D_IN; wire wci_wslv_reqF_countReg$EN; - // register wci_wslv_respF_c_r - reg [1 : 0] wci_wslv_respF_c_r; - wire [1 : 0] wci_wslv_respF_c_r$D_IN; - wire wci_wslv_respF_c_r$EN; + // register wci_wslv_respF_cntr_r + reg [1 : 0] wci_wslv_respF_cntr_r; + wire [1 : 0] wci_wslv_respF_cntr_r$D_IN; + wire wci_wslv_respF_cntr_r$EN; // register wci_wslv_respF_q_0 reg [33 : 0] wci_wslv_respF_q_0; @@ -482,35 +482,39 @@ module mkFlashWorker(wciS0_Clk, MUX_wci_wslv_respF_x_wire$wset_1__VAL_3; wire [31 : 0] MUX_rdReg$write_1__VAL_2; wire [14 : 0] MUX_flashC_rseqFsm_jj_delay_count$write_1__VAL_1; - wire [6 : 0] MUX_flashC_wseqFsm_jj_2_delay_count$write_1__VAL_1, - MUX_flashC_wseqFsm_jj_4_delay_count$write_1__VAL_1, + wire [6 : 0] MUX_flashC_wseqFsm_jj_1_delay_count$write_1__VAL_1, + MUX_flashC_wseqFsm_jj_2_delay_count$write_1__VAL_1, MUX_flashC_wseqFsm_jj_delay_count$write_1__VAL_1; - wire [1 : 0] MUX_wci_wslv_respF_c_r$write_1__VAL_1, - MUX_wci_wslv_respF_c_r$write_1__VAL_2; + wire [1 : 0] MUX_wci_wslv_respF_cntr_r$write_1__VAL_2; wire MUX_flashC_ceReg$write_1__SEL_1, MUX_flashC_oeReg$write_1__SEL_1, - MUX_flashC_reqF$enq_1__SEL_1, MUX_flashC_rseqFsm_start_reg$write_1__SEL_1, MUX_flashC_weReg$write_1__SEL_1, MUX_flashC_wseqFsm_start_reg$write_1__SEL_1, MUX_rdReg$write_1__SEL_1, MUX_splitReadInFlight$write_1__SEL_1, + MUX_splitReadInFlight$write_1__SEL_2, MUX_wci_wslv_illegalEdge$write_1__SEL_1, MUX_wci_wslv_illegalEdge$write_1__VAL_1, + MUX_wci_wslv_respF_q_0$write_1__SEL_1, MUX_wci_wslv_respF_q_0$write_1__SEL_2, + MUX_wci_wslv_respF_q_1$write_1__SEL_1, MUX_wci_wslv_respF_q_1$write_1__SEL_2, MUX_wci_wslv_respF_x_wire$wset_1__SEL_2; // remaining internal signals - reg [63 : 0] v__h3696, v__h3871, v__h4015, v__h87888; - reg [31 : 0] CASE_wci_wslv_reqFD_OUT_BITS_39_TO_32_0_0x0_f_ETC__q1; - wire [31 : 0] flashStatus__h86859, g_data__h87746; - wire [23 : 0] x_addr__h87646; - wire IF_flashC_reqF_first__67_BIT_40_68_THEN_flashC_ETC___d373, - flashC_rseqFsm_abort_whas__60_AND_flashC_rseqF_ETC___d227, - flashC_wseqFsm_abort_whas__33_AND_flashC_wseqF_ETC___d363, - wci_wslv_reqF_i_notEmpty__4_AND_IF_wci_wslv_re_ETC___d428, - wci_wslv_reqF_i_notEmpty__4_AND_wci_wslv_reqF__ETC___d406; + reg [63 : 0] v__h3564, v__h3739, v__h3883, v__h87698; + reg [31 : 0] IF_wci_wslv_reqF_first__3_BITS_39_TO_32_89_EQ__ETC___d442; + wire [31 : 0] flashStatus__h86674, g_data__h87561; + wire [23 : 0] x_addr__h87461; + wire [1 : 0] wci_wslv_respF_cntr_r_8_MINUS_1___d27; + wire IF_flashC_reqF_first__65_BIT_40_66_THEN_flashC_ETC___d371, + _dfoo1, + _dfoo3, + flashC_rseqFsm_abort_whas__58_AND_flashC_rseqF_ETC___d225, + flashC_wseqFsm_abort_whas__31_AND_flashC_wseqF_ETC___d361, + wci_wslv_reqF_i_notEmpty__2_AND_IF_wci_wslv_re_ETC___d426, + wci_wslv_reqF_i_notEmpty__2_AND_wci_wslv_reqF__ETC___d404; // value method wciS0_sResp assign wciS0_SResp = wci_wslv_respF_q_0[33:32] ; @@ -591,21 +595,21 @@ module mkFlashWorker(wciS0_Clk, // rule RL_advance_response assign WILL_FIRE_RL_advance_response = flashC_respF$EMPTY_N && - (!splitReadInFlight || wci_wslv_respF_c_r != 2'd2) && + (!splitReadInFlight || wci_wslv_respF_cntr_r != 2'd2) && !wci_wslv_wci_cfwr_pw$whas && !WILL_FIRE_RL_wci_wslv_ctl_op_complete ; // rule RL_wci_cfwr assign WILL_FIRE_RL_wci_cfwr = - wci_wslv_respF_c_r != 2'd2 && - wci_wslv_reqF_i_notEmpty__4_AND_wci_wslv_reqF__ETC___d406 && + wci_wslv_respF_cntr_r != 2'd2 && + wci_wslv_reqF_i_notEmpty__2_AND_wci_wslv_reqF__ETC___d404 && wci_wslv_wci_cfwr_pw$whas && !WILL_FIRE_RL_wci_wslv_ctl_op_start && !WILL_FIRE_RL_wci_wslv_ctl_op_complete ; // rule RL_wci_cfrd assign WILL_FIRE_RL_wci_cfrd = - wci_wslv_reqF_i_notEmpty__4_AND_IF_wci_wslv_re_ETC___d428 && + wci_wslv_reqF_i_notEmpty__2_AND_IF_wci_wslv_re_ETC___d426 && wci_wslv_wci_cfrd_pw$whas && !WILL_FIRE_RL_wci_wslv_ctl_op_start && !WILL_FIRE_RL_wci_wslv_ctl_op_complete ; @@ -638,27 +642,22 @@ module mkFlashWorker(wciS0_Clk, // rule RL_wci_wslv_ctl_op_complete assign WILL_FIRE_RL_wci_wslv_ctl_op_complete = - wci_wslv_respF_c_r != 2'd2 && wci_wslv_ctlOpActive && + wci_wslv_respF_cntr_r != 2'd2 && wci_wslv_ctlOpActive && wci_wslv_ctlAckReg ; // rule RL_wci_wslv_respF_incCtr assign WILL_FIRE_RL_wci_wslv_respF_incCtr = - ((wci_wslv_respF_c_r == 2'd0) ? - wci_wslv_respF_x_wire$whas : - wci_wslv_respF_c_r != 2'd1 || wci_wslv_respF_x_wire$whas) && - wci_wslv_respF_enqueueing$whas && - !(wci_wslv_respF_c_r != 2'd0) ; + wci_wslv_respF_x_wire$whas && wci_wslv_respF_enqueueing$whas && + !(wci_wslv_respF_cntr_r != 2'd0) ; // rule RL_wci_wslv_respF_decCtr assign WILL_FIRE_RL_wci_wslv_respF_decCtr = - wci_wslv_respF_c_r != 2'd0 && !wci_wslv_respF_enqueueing$whas ; + wci_wslv_respF_cntr_r != 2'd0 && + !wci_wslv_respF_enqueueing$whas ; // rule RL_wci_wslv_respF_both assign WILL_FIRE_RL_wci_wslv_respF_both = - ((wci_wslv_respF_c_r == 2'd1) ? - wci_wslv_respF_x_wire$whas : - wci_wslv_respF_c_r != 2'd2 || wci_wslv_respF_x_wire$whas) && - wci_wslv_respF_c_r != 2'd0 && + wci_wslv_respF_x_wire$whas && wci_wslv_respF_cntr_r != 2'd0 && wci_wslv_respF_enqueueing$whas ; // rule RL_flashC_rseqFsm_action_l61c12 @@ -692,7 +691,7 @@ module mkFlashWorker(wciS0_Clk, // rule RL_flashC_rseqFsm_fsm_start assign WILL_FIRE_RL_flashC_rseqFsm_fsm_start = - flashC_rseqFsm_abort_whas__60_AND_flashC_rseqF_ETC___d227 && + flashC_rseqFsm_abort_whas__58_AND_flashC_rseqF_ETC___d225 && flashC_rseqFsm_start_reg ; // rule RL_flashC_rseqFsm_action_l60c12 @@ -760,13 +759,13 @@ module mkFlashWorker(wciS0_Clk, // rule RL_flashC_wseqFsm_action_np_2 assign WILL_FIRE_RL_flashC_wseqFsm_action_np_2 = - !flashC_isRead && !flashC_wseqFsm_jj_2_delay_count[6] && + !flashC_isRead && !flashC_wseqFsm_jj_1_delay_count[6] && (flashC_wseqFsm_state_mkFSMstate == 5'd13 || flashC_wseqFsm_state_mkFSMstate == 5'd14) ; // rule RL_flashC_wseqFsm_action_l82c12 assign WILL_FIRE_RL_flashC_wseqFsm_action_l82c12 = - !flashC_isRead && flashC_wseqFsm_jj_2_delay_count[6] && + !flashC_isRead && flashC_wseqFsm_jj_1_delay_count[6] && (flashC_wseqFsm_state_mkFSMstate == 5'd13 || flashC_wseqFsm_state_mkFSMstate == 5'd14) ; @@ -796,13 +795,13 @@ module mkFlashWorker(wciS0_Clk, // rule RL_flashC_wseqFsm_action_np_4 assign WILL_FIRE_RL_flashC_wseqFsm_action_np_4 = - !flashC_isRead && !flashC_wseqFsm_jj_4_delay_count[6] && + !flashC_isRead && !flashC_wseqFsm_jj_2_delay_count[6] && (flashC_wseqFsm_state_mkFSMstate == 5'd21 || flashC_wseqFsm_state_mkFSMstate == 5'd22) ; // rule RL_flashC_wseqFsm_action_l90c12 assign WILL_FIRE_RL_flashC_wseqFsm_action_l90c12 = - !flashC_isRead && flashC_wseqFsm_jj_4_delay_count[6] && + !flashC_isRead && flashC_wseqFsm_jj_2_delay_count[6] && (flashC_wseqFsm_state_mkFSMstate == 5'd21 || flashC_wseqFsm_state_mkFSMstate == 5'd22) ; @@ -812,7 +811,7 @@ module mkFlashWorker(wciS0_Clk, // rule RL_flashC_wseqFsm_fsm_start assign WILL_FIRE_RL_flashC_wseqFsm_fsm_start = - flashC_wseqFsm_abort_whas__33_AND_flashC_wseqF_ETC___d363 && + flashC_wseqFsm_abort_whas__31_AND_flashC_wseqF_ETC___d361 && flashC_wseqFsm_start_reg ; // rule RL_flashC_wseqFsm_action_l70c12 @@ -824,10 +823,10 @@ module mkFlashWorker(wciS0_Clk, // rule RL_flashC_nextRequest assign WILL_FIRE_RL_flashC_nextRequest = flashC_reqF$EMPTY_N && - IF_flashC_reqF_first__67_BIT_40_68_THEN_flashC_ETC___d373 && - flashC_rseqFsm_abort_whas__60_AND_flashC_rseqF_ETC___d227 && + IF_flashC_reqF_first__65_BIT_40_66_THEN_flashC_ETC___d371 && + flashC_rseqFsm_abort_whas__58_AND_flashC_rseqF_ETC___d225 && !flashC_rseqFsm_start_reg && - flashC_wseqFsm_abort_whas__33_AND_flashC_wseqF_ETC___d363 && + flashC_wseqFsm_abort_whas__31_AND_flashC_wseqF_ETC___d361 && !flashC_wseqFsm_start_reg ; // rule RL_flashC_wseqFsm_idle_l69c15 @@ -844,10 +843,6 @@ module mkFlashWorker(wciS0_Clk, assign MUX_flashC_oeReg$write_1__SEL_1 = WILL_FIRE_RL_flashC_wseqFsm_action_l90c12 || WILL_FIRE_RL_flashC_rseqFsm_action_l64c12 ; - assign MUX_flashC_reqF$enq_1__SEL_1 = - WILL_FIRE_RL_wci_cfwr && - (wci_wslv_reqF$D_OUT[39:32] == 8'h14 || - wci_wslv_reqF$D_OUT[39:32] == 8'h18) ; assign MUX_flashC_rseqFsm_start_reg$write_1__SEL_1 = WILL_FIRE_RL_flashC_nextRequest && flashC_reqF$D_OUT[40] ; assign MUX_flashC_weReg$write_1__SEL_1 = @@ -859,6 +854,8 @@ module mkFlashWorker(wciS0_Clk, WILL_FIRE_RL_wci_cfwr && wci_wslv_reqF$D_OUT[39:32] == 8'h10 ; assign MUX_splitReadInFlight$write_1__SEL_1 = WILL_FIRE_RL_advance_response && splitReadInFlight ; + assign MUX_splitReadInFlight$write_1__SEL_2 = + WILL_FIRE_RL_wci_cfrd && wci_wslv_reqF$D_OUT[51] ; assign MUX_wci_wslv_illegalEdge$write_1__SEL_1 = WILL_FIRE_RL_wci_wslv_ctl_op_start && (wci_wslv_reqF$D_OUT[36:34] == 3'd0 && wci_wslv_cState != 3'd0 || @@ -872,25 +869,29 @@ module mkFlashWorker(wciS0_Clk, wci_wslv_reqF$D_OUT[36:34] == 3'd5 || wci_wslv_reqF$D_OUT[36:34] == 3'd6 || wci_wslv_reqF$D_OUT[36:34] == 3'd7) ; + assign MUX_wci_wslv_respF_q_0$write_1__SEL_1 = + WILL_FIRE_RL_wci_wslv_respF_both && _dfoo3 ; assign MUX_wci_wslv_respF_q_0$write_1__SEL_2 = WILL_FIRE_RL_wci_wslv_respF_incCtr && - wci_wslv_respF_c_r == 2'd0 ; + wci_wslv_respF_cntr_r == 2'd0 ; + assign MUX_wci_wslv_respF_q_1$write_1__SEL_1 = + WILL_FIRE_RL_wci_wslv_respF_both && _dfoo1 ; assign MUX_wci_wslv_respF_q_1$write_1__SEL_2 = WILL_FIRE_RL_wci_wslv_respF_incCtr && - wci_wslv_respF_c_r == 2'd1 ; + wci_wslv_respF_cntr_r == 2'd1 ; assign MUX_wci_wslv_respF_x_wire$wset_1__SEL_2 = WILL_FIRE_RL_wci_cfrd && !wci_wslv_reqF$D_OUT[51] ; - assign MUX_flashC_reqF$enq_1__VAL_1 = + assign MUX_flashC_reqF$enq_1__VAL_1 = { 1'd1, x_addr__h87461, 16'hAAAA } ; + assign MUX_flashC_reqF$enq_1__VAL_2 = { wci_wslv_reqF$D_OUT[39:32] != 8'h14, aReg[23:0], wdReg[15:0] } ; - assign MUX_flashC_reqF$enq_1__VAL_2 = { 1'd1, x_addr__h87646, 16'hAAAA } ; assign MUX_flashC_rseqFsm_jj_delay_count$write_1__VAL_1 = { flashC_rseqFsm_jj_delay_count[13:0], 1'd0 } ; + assign MUX_flashC_wseqFsm_jj_1_delay_count$write_1__VAL_1 = + { flashC_wseqFsm_jj_1_delay_count[5:0], 1'd0 } ; assign MUX_flashC_wseqFsm_jj_2_delay_count$write_1__VAL_1 = { flashC_wseqFsm_jj_2_delay_count[5:0], 1'd0 } ; - assign MUX_flashC_wseqFsm_jj_4_delay_count$write_1__VAL_1 = - { flashC_wseqFsm_jj_4_delay_count[5:0], 1'd0 } ; assign MUX_flashC_wseqFsm_jj_delay_count$write_1__VAL_1 = { flashC_wseqFsm_jj_delay_count[5:0], 1'd0 } ; assign MUX_rdReg$write_1__VAL_2 = { 16'd0, flashC_respF$D_OUT } ; @@ -898,10 +899,10 @@ module mkFlashWorker(wciS0_Clk, wci_wslv_reqF$D_OUT[36:34] != 3'd4 && wci_wslv_reqF$D_OUT[36:34] != 3'd5 && wci_wslv_reqF$D_OUT[36:34] != 3'd6 ; - assign MUX_wci_wslv_respF_c_r$write_1__VAL_1 = wci_wslv_respF_c_r + 2'd1 ; - assign MUX_wci_wslv_respF_c_r$write_1__VAL_2 = wci_wslv_respF_c_r - 2'd1 ; + assign MUX_wci_wslv_respF_cntr_r$write_1__VAL_2 = + wci_wslv_respF_cntr_r + 2'd1 ; assign MUX_wci_wslv_respF_q_0$write_1__VAL_1 = - (wci_wslv_respF_c_r == 2'd1) ? + (wci_wslv_respF_cntr_r == 2'd1) ? MUX_wci_wslv_respF_q_0$write_1__VAL_2 : wci_wslv_respF_q_1 ; always@(MUX_splitReadInFlight$write_1__SEL_1 or @@ -928,12 +929,12 @@ module mkFlashWorker(wciS0_Clk, endcase end assign MUX_wci_wslv_respF_q_1$write_1__VAL_1 = - (wci_wslv_respF_c_r == 2'd2) ? + (wci_wslv_respF_cntr_r == 2'd2) ? MUX_wci_wslv_respF_q_0$write_1__VAL_2 : 34'h0AAAAAAAA ; assign MUX_wci_wslv_respF_x_wire$wset_1__VAL_1 = { 18'd65536, flashC_respF$D_OUT } ; - assign MUX_wci_wslv_respF_x_wire$wset_1__VAL_2 = { 2'd1, g_data__h87746 } ; + assign MUX_wci_wslv_respF_x_wire$wset_1__VAL_2 = { 2'd1, g_data__h87561 } ; assign MUX_wci_wslv_respF_x_wire$wset_1__VAL_3 = wci_wslv_illegalEdge ? 34'h3C0DE4202 : 34'h1C0DE4201 ; @@ -973,8 +974,8 @@ module mkFlashWorker(wciS0_Clk, assign flashC_rseqFsm_start_wire$whas = WILL_FIRE_RL_flashC_rseqFsm_fsm_start || flashC_rseqFsm_start_reg_1 && !flashC_rseqFsm_state_fired ; - assign flashC_rseqFsm_start_reg_1_1$wget = 1'd1 ; - assign flashC_rseqFsm_start_reg_1_1$whas = flashC_rseqFsm_start_wire$whas ; + assign flashC_rseqFsm_start_reg_2$wget = 1'd1 ; + assign flashC_rseqFsm_start_reg_2$whas = flashC_rseqFsm_start_wire$whas ; assign flashC_rseqFsm_abort$wget = 1'b0 ; assign flashC_rseqFsm_abort$whas = 1'b0 ; assign flashC_rseqFsm_state_fired_1$wget = 1'd1 ; @@ -984,8 +985,8 @@ module mkFlashWorker(wciS0_Clk, assign flashC_wseqFsm_start_wire$whas = WILL_FIRE_RL_flashC_wseqFsm_fsm_start || flashC_wseqFsm_start_reg_1 && !flashC_wseqFsm_state_fired ; - assign flashC_wseqFsm_start_reg_1_1$wget = 1'd1 ; - assign flashC_wseqFsm_start_reg_1_1$whas = flashC_wseqFsm_start_wire$whas ; + assign flashC_wseqFsm_start_reg_2$wget = 1'd1 ; + assign flashC_wseqFsm_start_reg_2$whas = flashC_wseqFsm_start_wire$whas ; assign flashC_wseqFsm_abort$wget = 1'b0 ; assign flashC_wseqFsm_abort$whas = 1'b0 ; assign flashC_wseqFsm_state_fired_1$wget = 1'd1 ; @@ -1001,7 +1002,7 @@ module mkFlashWorker(wciS0_Clk, WILL_FIRE_RL_wci_cfrd && !wci_wslv_reqF$D_OUT[51] || WILL_FIRE_RL_wci_cfwr || WILL_FIRE_RL_wci_wslv_ctl_op_complete ; - assign wci_wslv_respF_dequeueing$whas = wci_wslv_respF_c_r != 2'd0 ; + assign wci_wslv_respF_dequeueing$whas = wci_wslv_respF_cntr_r != 2'd0 ; assign wci_wslv_sThreadBusy_pw$whas = 1'b0 ; assign wci_wslv_wci_cfwr_pw$whas = wci_wslv_reqF$EMPTY_N && wci_wslv_reqF$D_OUT[68] && @@ -1189,21 +1190,21 @@ module mkFlashWorker(wciS0_Clk, WILL_FIRE_RL_flashC_wseqFsm_action_l80c12 || WILL_FIRE_RL_flashC_wseqFsm_action_l73c12 ; - // register flashC_wseqFsm_jj_2_delay_count - assign flashC_wseqFsm_jj_2_delay_count$D_IN = + // register flashC_wseqFsm_jj_1_delay_count + assign flashC_wseqFsm_jj_1_delay_count$D_IN = WILL_FIRE_RL_flashC_wseqFsm_action_np_2 ? - MUX_flashC_wseqFsm_jj_2_delay_count$write_1__VAL_1 : + MUX_flashC_wseqFsm_jj_1_delay_count$write_1__VAL_1 : 7'd1 ; - assign flashC_wseqFsm_jj_2_delay_count$EN = + assign flashC_wseqFsm_jj_1_delay_count$EN = WILL_FIRE_RL_flashC_wseqFsm_action_np_2 || WILL_FIRE_RL_flashC_wseqFsm_action_d_init_np_1 ; - // register flashC_wseqFsm_jj_4_delay_count - assign flashC_wseqFsm_jj_4_delay_count$D_IN = + // register flashC_wseqFsm_jj_2_delay_count + assign flashC_wseqFsm_jj_2_delay_count$D_IN = WILL_FIRE_RL_flashC_wseqFsm_action_np_4 ? - MUX_flashC_wseqFsm_jj_4_delay_count$write_1__VAL_1 : + MUX_flashC_wseqFsm_jj_2_delay_count$write_1__VAL_1 : 7'd1 ; - assign flashC_wseqFsm_jj_4_delay_count$EN = + assign flashC_wseqFsm_jj_2_delay_count$EN = WILL_FIRE_RL_flashC_wseqFsm_action_np_4 || WILL_FIRE_RL_flashC_wseqFsm_action_d_init_np_2 ; @@ -1426,24 +1427,24 @@ module mkFlashWorker(wciS0_Clk, (wci_wslv_wciReq$wget[71:69] != 3'd0) != wci_wslv_reqF_r_deq$whas ; - // register wci_wslv_respF_c_r - assign wci_wslv_respF_c_r$D_IN = - WILL_FIRE_RL_wci_wslv_respF_incCtr ? - MUX_wci_wslv_respF_c_r$write_1__VAL_1 : - MUX_wci_wslv_respF_c_r$write_1__VAL_2 ; - assign wci_wslv_respF_c_r$EN = - WILL_FIRE_RL_wci_wslv_respF_incCtr || - WILL_FIRE_RL_wci_wslv_respF_decCtr ; + // register wci_wslv_respF_cntr_r + assign wci_wslv_respF_cntr_r$D_IN = + WILL_FIRE_RL_wci_wslv_respF_decCtr ? + wci_wslv_respF_cntr_r_8_MINUS_1___d27 : + MUX_wci_wslv_respF_cntr_r$write_1__VAL_2 ; + assign wci_wslv_respF_cntr_r$EN = + WILL_FIRE_RL_wci_wslv_respF_decCtr || + WILL_FIRE_RL_wci_wslv_respF_incCtr ; // register wci_wslv_respF_q_0 - always@(WILL_FIRE_RL_wci_wslv_respF_both or + always@(MUX_wci_wslv_respF_q_0$write_1__SEL_1 or MUX_wci_wslv_respF_q_0$write_1__VAL_1 or MUX_wci_wslv_respF_q_0$write_1__SEL_2 or MUX_wci_wslv_respF_q_0$write_1__VAL_2 or WILL_FIRE_RL_wci_wslv_respF_decCtr or wci_wslv_respF_q_1) begin case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_wci_wslv_respF_both: + MUX_wci_wslv_respF_q_0$write_1__SEL_1: wci_wslv_respF_q_0$D_IN = MUX_wci_wslv_respF_q_0$write_1__VAL_1; MUX_wci_wslv_respF_q_0$write_1__SEL_2: wci_wslv_respF_q_0$D_IN = MUX_wci_wslv_respF_q_0$write_1__VAL_2; @@ -1454,20 +1455,20 @@ module mkFlashWorker(wciS0_Clk, endcase end assign wci_wslv_respF_q_0$EN = - WILL_FIRE_RL_wci_wslv_respF_both || + WILL_FIRE_RL_wci_wslv_respF_both && _dfoo3 || WILL_FIRE_RL_wci_wslv_respF_incCtr && - wci_wslv_respF_c_r == 2'd0 || + wci_wslv_respF_cntr_r == 2'd0 || WILL_FIRE_RL_wci_wslv_respF_decCtr ; // register wci_wslv_respF_q_1 - always@(WILL_FIRE_RL_wci_wslv_respF_both or + always@(MUX_wci_wslv_respF_q_1$write_1__SEL_1 or MUX_wci_wslv_respF_q_1$write_1__VAL_1 or MUX_wci_wslv_respF_q_1$write_1__SEL_2 or MUX_wci_wslv_respF_q_0$write_1__VAL_2 or WILL_FIRE_RL_wci_wslv_respF_decCtr) begin case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_wci_wslv_respF_both: + MUX_wci_wslv_respF_q_1$write_1__SEL_1: wci_wslv_respF_q_1$D_IN = MUX_wci_wslv_respF_q_1$write_1__VAL_1; MUX_wci_wslv_respF_q_1$write_1__SEL_2: wci_wslv_respF_q_1$D_IN = MUX_wci_wslv_respF_q_0$write_1__VAL_2; @@ -1478,9 +1479,9 @@ module mkFlashWorker(wciS0_Clk, endcase end assign wci_wslv_respF_q_1$EN = - WILL_FIRE_RL_wci_wslv_respF_both || + WILL_FIRE_RL_wci_wslv_respF_both && _dfoo1 || WILL_FIRE_RL_wci_wslv_respF_incCtr && - wci_wslv_respF_c_r == 2'd1 || + wci_wslv_respF_cntr_r == 2'd1 || WILL_FIRE_RL_wci_wslv_respF_decCtr ; // register wci_wslv_sFlagReg @@ -1498,14 +1499,14 @@ module mkFlashWorker(wciS0_Clk, // submodule flashC_reqF assign flashC_reqF$D_IN = - MUX_flashC_reqF$enq_1__SEL_1 ? + MUX_splitReadInFlight$write_1__SEL_2 ? MUX_flashC_reqF$enq_1__VAL_1 : MUX_flashC_reqF$enq_1__VAL_2 ; assign flashC_reqF$ENQ = + WILL_FIRE_RL_wci_cfrd && wci_wslv_reqF$D_OUT[51] || WILL_FIRE_RL_wci_cfwr && (wci_wslv_reqF$D_OUT[39:32] == 8'h14 || - wci_wslv_reqF$D_OUT[39:32] == 8'h18) || - WILL_FIRE_RL_wci_cfrd && wci_wslv_reqF$D_OUT[51] ; + wci_wslv_reqF$D_OUT[39:32] == 8'h18) ; assign flashC_reqF$DEQ = WILL_FIRE_RL_flashC_nextRequest ; assign flashC_reqF$CLR = 1'b0 ; @@ -1522,49 +1523,61 @@ module mkFlashWorker(wciS0_Clk, assign wci_wslv_reqF$CLR = 1'b0 ; // remaining internal signals - assign IF_flashC_reqF_first__67_BIT_40_68_THEN_flashC_ETC___d373 = + assign IF_flashC_reqF_first__65_BIT_40_66_THEN_flashC_ETC___d371 = flashC_reqF$D_OUT[40] ? - flashC_rseqFsm_abort_whas__60_AND_flashC_rseqF_ETC___d227 && + flashC_rseqFsm_abort_whas__58_AND_flashC_rseqF_ETC___d225 && !flashC_rseqFsm_start_reg : - flashC_wseqFsm_abort_whas__33_AND_flashC_wseqF_ETC___d363 && + flashC_wseqFsm_abort_whas__31_AND_flashC_wseqF_ETC___d361 && !flashC_wseqFsm_start_reg ; - assign flashC_rseqFsm_abort_whas__60_AND_flashC_rseqF_ETC___d227 = + assign _dfoo1 = + wci_wslv_respF_cntr_r != 2'd2 || + wci_wslv_respF_cntr_r_8_MINUS_1___d27 == 2'd1 ; + assign _dfoo3 = + wci_wslv_respF_cntr_r != 2'd1 || + wci_wslv_respF_cntr_r_8_MINUS_1___d27 == 2'd0 ; + assign flashC_rseqFsm_abort_whas__58_AND_flashC_rseqF_ETC___d225 = (flashC_rseqFsm_state_mkFSMstate == 4'd0 || flashC_rseqFsm_state_mkFSMstate == 4'd7) && (!flashC_rseqFsm_start_reg_1 || flashC_rseqFsm_state_fired) ; - assign flashC_wseqFsm_abort_whas__33_AND_flashC_wseqF_ETC___d363 = + assign flashC_wseqFsm_abort_whas__31_AND_flashC_wseqF_ETC___d361 = (flashC_wseqFsm_state_mkFSMstate == 5'd0 || flashC_wseqFsm_state_mkFSMstate == 5'd24) && (!flashC_wseqFsm_start_reg_1 || flashC_wseqFsm_state_fired) ; - assign flashStatus__h86859 = { 31'd1, flashC_waitReg } ; - assign g_data__h87746 = + assign flashStatus__h86674 = { 31'd1, flashC_waitReg } ; + assign g_data__h87561 = wci_wslv_reqF$D_OUT[51] ? 32'd0 : - CASE_wci_wslv_reqFD_OUT_BITS_39_TO_32_0_0x0_f_ETC__q1 ; - assign wci_wslv_reqF_i_notEmpty__4_AND_IF_wci_wslv_re_ETC___d428 = + IF_wci_wslv_reqF_first__3_BITS_39_TO_32_89_EQ__ETC___d442 ; + assign wci_wslv_reqF_i_notEmpty__2_AND_IF_wci_wslv_re_ETC___d426 = wci_wslv_reqF$EMPTY_N && (wci_wslv_reqF$D_OUT[51] ? flashC_reqF$FULL_N : - wci_wslv_respF_c_r != 2'd2) ; - assign wci_wslv_reqF_i_notEmpty__4_AND_wci_wslv_reqF__ETC___d406 = + wci_wslv_respF_cntr_r != 2'd2) ; + assign wci_wslv_reqF_i_notEmpty__2_AND_wci_wslv_reqF__ETC___d404 = wci_wslv_reqF$EMPTY_N && ((wci_wslv_reqF$D_OUT[39:32] == 8'h14) ? flashC_reqF$FULL_N : wci_wslv_reqF$D_OUT[39:32] != 8'h18 || flashC_reqF$FULL_N) ; - assign x_addr__h87646 = { 5'h0, wci_wslv_reqF$D_OUT[50:34], 2'b0 } ; + assign wci_wslv_respF_cntr_r_8_MINUS_1___d27 = + wci_wslv_respF_cntr_r - 2'd1 ; + assign x_addr__h87461 = { 5'h0, wci_wslv_reqF$D_OUT[50:34], 2'b0 } ; always@(wci_wslv_reqF$D_OUT or - flashStatus__h86859 or flashCtrl or aReg or wdReg or rdReg) + flashStatus__h86674 or flashCtrl or aReg or wdReg or rdReg) begin case (wci_wslv_reqF$D_OUT[39:32]) 8'h0: - CASE_wci_wslv_reqFD_OUT_BITS_39_TO_32_0_0x0_f_ETC__q1 = - flashStatus__h86859; + IF_wci_wslv_reqF_first__3_BITS_39_TO_32_89_EQ__ETC___d442 = + flashStatus__h86674; 8'h04: - CASE_wci_wslv_reqFD_OUT_BITS_39_TO_32_0_0x0_f_ETC__q1 = flashCtrl; - 8'h08: CASE_wci_wslv_reqFD_OUT_BITS_39_TO_32_0_0x0_f_ETC__q1 = aReg; - 8'h0C: CASE_wci_wslv_reqFD_OUT_BITS_39_TO_32_0_0x0_f_ETC__q1 = wdReg; - 8'h10: CASE_wci_wslv_reqFD_OUT_BITS_39_TO_32_0_0x0_f_ETC__q1 = rdReg; - default: CASE_wci_wslv_reqFD_OUT_BITS_39_TO_32_0_0x0_f_ETC__q1 = 32'd0; + IF_wci_wslv_reqF_first__3_BITS_39_TO_32_89_EQ__ETC___d442 = + flashCtrl; + 8'h08: IF_wci_wslv_reqF_first__3_BITS_39_TO_32_89_EQ__ETC___d442 = aReg; + 8'h0C: + IF_wci_wslv_reqF_first__3_BITS_39_TO_32_89_EQ__ETC___d442 = wdReg; + 8'h10: + IF_wci_wslv_reqF_first__3_BITS_39_TO_32_89_EQ__ETC___d442 = rdReg; + default: IF_wci_wslv_reqF_first__3_BITS_39_TO_32_89_EQ__ETC___d442 = + 32'd0; endcase end @@ -1590,8 +1603,8 @@ module mkFlashWorker(wciS0_Clk, flashC_tsWD <= `BSV_ASSIGNMENT_DELAY 16'd0; flashC_wdReg <= `BSV_ASSIGNMENT_DELAY 16'd0; flashC_weReg <= `BSV_ASSIGNMENT_DELAY 1'd0; + flashC_wseqFsm_jj_1_delay_count <= `BSV_ASSIGNMENT_DELAY 7'd1; flashC_wseqFsm_jj_2_delay_count <= `BSV_ASSIGNMENT_DELAY 7'd1; - flashC_wseqFsm_jj_4_delay_count <= `BSV_ASSIGNMENT_DELAY 7'd1; flashC_wseqFsm_jj_delay_count <= `BSV_ASSIGNMENT_DELAY 7'd1; flashC_wseqFsm_start_reg <= `BSV_ASSIGNMENT_DELAY 1'd0; flashC_wseqFsm_start_reg_1 <= `BSV_ASSIGNMENT_DELAY 1'd0; @@ -1608,7 +1621,7 @@ module mkFlashWorker(wciS0_Clk, wci_wslv_illegalEdge <= `BSV_ASSIGNMENT_DELAY 1'd0; wci_wslv_nState <= `BSV_ASSIGNMENT_DELAY 3'd0; wci_wslv_reqF_countReg <= `BSV_ASSIGNMENT_DELAY 2'd0; - wci_wslv_respF_c_r <= `BSV_ASSIGNMENT_DELAY 2'd0; + wci_wslv_respF_cntr_r <= `BSV_ASSIGNMENT_DELAY 2'd0; wci_wslv_respF_q_0 <= `BSV_ASSIGNMENT_DELAY 34'h0AAAAAAAA; wci_wslv_respF_q_1 <= `BSV_ASSIGNMENT_DELAY 34'h0AAAAAAAA; wci_wslv_sFlagReg <= `BSV_ASSIGNMENT_DELAY 1'd0; @@ -1654,12 +1667,12 @@ module mkFlashWorker(wciS0_Clk, flashC_wdReg <= `BSV_ASSIGNMENT_DELAY flashC_wdReg$D_IN; if (flashC_weReg$EN) flashC_weReg <= `BSV_ASSIGNMENT_DELAY flashC_weReg$D_IN; + if (flashC_wseqFsm_jj_1_delay_count$EN) + flashC_wseqFsm_jj_1_delay_count <= `BSV_ASSIGNMENT_DELAY + flashC_wseqFsm_jj_1_delay_count$D_IN; if (flashC_wseqFsm_jj_2_delay_count$EN) flashC_wseqFsm_jj_2_delay_count <= `BSV_ASSIGNMENT_DELAY flashC_wseqFsm_jj_2_delay_count$D_IN; - if (flashC_wseqFsm_jj_4_delay_count$EN) - flashC_wseqFsm_jj_4_delay_count <= `BSV_ASSIGNMENT_DELAY - flashC_wseqFsm_jj_4_delay_count$D_IN; if (flashC_wseqFsm_jj_delay_count$EN) flashC_wseqFsm_jj_delay_count <= `BSV_ASSIGNMENT_DELAY flashC_wseqFsm_jj_delay_count$D_IN; @@ -1699,8 +1712,9 @@ module mkFlashWorker(wciS0_Clk, if (wci_wslv_reqF_countReg$EN) wci_wslv_reqF_countReg <= `BSV_ASSIGNMENT_DELAY wci_wslv_reqF_countReg$D_IN; - if (wci_wslv_respF_c_r$EN) - wci_wslv_respF_c_r <= `BSV_ASSIGNMENT_DELAY wci_wslv_respF_c_r$D_IN; + if (wci_wslv_respF_cntr_r$EN) + wci_wslv_respF_cntr_r <= `BSV_ASSIGNMENT_DELAY + wci_wslv_respF_cntr_r$D_IN; if (wci_wslv_respF_q_0$EN) wci_wslv_respF_q_0 <= `BSV_ASSIGNMENT_DELAY wci_wslv_respF_q_0$D_IN; if (wci_wslv_respF_q_1$EN) @@ -1750,8 +1764,8 @@ module mkFlashWorker(wciS0_Clk, flashC_waitReg = 1'h0; flashC_wdReg = 16'hAAAA; flashC_weReg = 1'h0; + flashC_wseqFsm_jj_1_delay_count = 7'h2A; flashC_wseqFsm_jj_2_delay_count = 7'h2A; - flashC_wseqFsm_jj_4_delay_count = 7'h2A; flashC_wseqFsm_jj_delay_count = 7'h2A; flashC_wseqFsm_start_reg = 1'h0; flashC_wseqFsm_start_reg_1 = 1'h0; @@ -1769,7 +1783,7 @@ module mkFlashWorker(wciS0_Clk, wci_wslv_isReset_isInReset = 1'h0; wci_wslv_nState = 3'h2; wci_wslv_reqF_countReg = 2'h2; - wci_wslv_respF_c_r = 2'h2; + wci_wslv_respF_cntr_r = 2'h2; wci_wslv_respF_q_0 = 34'h2AAAAAAAA; wci_wslv_respF_q_1 = 34'h2AAAAAAAA; wci_wslv_sFlagReg = 1'h0; @@ -1788,25 +1802,25 @@ module mkFlashWorker(wciS0_Clk, if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_start) begin - v__h3696 = $time; + v__h3564 = $time; #0; end if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_start) $display("[%0d]: %m: WCI ControlOp: Starting-transition edge:%x from:%x", - v__h3696, + v__h3564, wci_wslv_reqF$D_OUT[36:34], wci_wslv_cState); if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_ctrl_IsO) begin - v__h87888 = $time; + v__h87698 = $time; #0; end if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_ctrl_IsO) $display("[%0d]: %m: Starting flashWorker flashCtrl:%0x", - v__h87888, + v__h87698, flashCtrl); if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_advance_response && WILL_FIRE_RL_wci_ctrl_OrE) @@ -1856,25 +1870,25 @@ module mkFlashWorker(wciS0_Clk, if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge) begin - v__h4015 = $time; + v__h3883 = $time; #0; end if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge) $display("[%0d]: %m: WCI ControlOp: ILLEGAL-EDGE Completed-transition edge:%x from:%x", - v__h4015, + v__h3883, wci_wslv_cEdge, wci_wslv_cState); if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && !wci_wslv_illegalEdge) begin - v__h3871 = $time; + v__h3739 = $time; #0; end if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && !wci_wslv_illegalEdge) $display("[%0d]: %m: WCI ControlOp: Completed-transition edge:%x from:%x to:%x", - v__h3871, + v__h3739, wci_wslv_cEdge, wci_wslv_cState, wci_wslv_nState); diff --git a/rtl/mkFrameGate16B.v b/rtl/mkFrameGate16B.v new file mode 100644 index 00000000..11dfe9a1 --- /dev/null +++ b/rtl/mkFrameGate16B.v @@ -0,0 +1,1664 @@ +// +// Generated by Bluespec Compiler, version 2012.09.beta1 (build 29570, 2012-09.11) +// +// On Tue Jan 22 07:33:00 EST 2013 +// +// +// Ports: +// Name I/O size props +// wciS0_SResp O 2 reg +// wciS0_SData O 32 reg +// wciS0_SThreadBusy O 1 +// wciS0_SFlag O 2 +// wsiS0_SThreadBusy O 1 +// wsiS0_SReset_n O 1 +// wsiM0_MCmd O 3 +// wsiM0_MReqLast O 1 +// wsiM0_MBurstPrecise O 1 +// wsiM0_MBurstLength O 12 +// wsiM0_MData O 128 reg +// wsiM0_MByteEn O 16 reg +// wsiM0_MReqInfo O 8 +// wsiM0_MReset_n O 1 +// wciS0_Clk I 1 clock +// wciS0_MReset_n I 1 reset +// wciS0_MCmd I 3 +// wciS0_MAddrSpace I 1 +// wciS0_MByteEn I 4 +// wciS0_MAddr I 32 +// wciS0_MData I 32 +// wciS0_MFlag I 2 unused +// wsiS0_MCmd I 3 +// wsiS0_MBurstLength I 12 +// wsiS0_MData I 128 +// wsiS0_MByteEn I 16 +// wsiS0_MReqInfo I 8 +// wsiS0_MReqLast I 1 +// wsiS0_MBurstPrecise I 1 +// wsiS0_MReset_n I 1 reg +// wsiM0_SThreadBusy I 1 reg +// wsiM0_SReset_n I 1 reg +// +// No combinational paths from inputs to outputs +// +// + +`ifdef BSV_ASSIGNMENT_DELAY +`else + `define BSV_ASSIGNMENT_DELAY +`endif + +`ifdef BSV_POSITIVE_RESET + `define BSV_RESET_VALUE 1'b1 + `define BSV_RESET_EDGE posedge +`else + `define BSV_RESET_VALUE 1'b0 + `define BSV_RESET_EDGE negedge +`endif + +module mkFrameGate16B(wciS0_Clk, + wciS0_MReset_n, + + wciS0_MCmd, + + wciS0_MAddrSpace, + + wciS0_MByteEn, + + wciS0_MAddr, + + wciS0_MData, + + wciS0_SResp, + + wciS0_SData, + + wciS0_SThreadBusy, + + wciS0_SFlag, + + wciS0_MFlag, + + wsiS0_MCmd, + + wsiS0_MReqLast, + + wsiS0_MBurstPrecise, + + wsiS0_MBurstLength, + + wsiS0_MData, + + wsiS0_MByteEn, + + wsiS0_MReqInfo, + + wsiS0_SThreadBusy, + + wsiS0_SReset_n, + + wsiS0_MReset_n, + + wsiM0_MCmd, + + wsiM0_MReqLast, + + wsiM0_MBurstPrecise, + + wsiM0_MBurstLength, + + wsiM0_MData, + + wsiM0_MByteEn, + + wsiM0_MReqInfo, + + wsiM0_SThreadBusy, + + wsiM0_MReset_n, + + wsiM0_SReset_n); + parameter [31 : 0] fgCtrlInit = 32'b0; + parameter [0 : 0] hasDebugLogic = 1'b0; + input wciS0_Clk; + input wciS0_MReset_n; + + // action method wciS0_mCmd + input [2 : 0] wciS0_MCmd; + + // action method wciS0_mAddrSpace + input wciS0_MAddrSpace; + + // action method wciS0_mByteEn + input [3 : 0] wciS0_MByteEn; + + // action method wciS0_mAddr + input [31 : 0] wciS0_MAddr; + + // action method wciS0_mData + input [31 : 0] wciS0_MData; + + // value method wciS0_sResp + output [1 : 0] wciS0_SResp; + + // value method wciS0_sData + output [31 : 0] wciS0_SData; + + // value method wciS0_sThreadBusy + output wciS0_SThreadBusy; + + // value method wciS0_sFlag + output [1 : 0] wciS0_SFlag; + + // action method wciS0_mFlag + input [1 : 0] wciS0_MFlag; + + // action method wsiS0_mCmd + input [2 : 0] wsiS0_MCmd; + + // action method wsiS0_mReqLast + input wsiS0_MReqLast; + + // action method wsiS0_mBurstPrecise + input wsiS0_MBurstPrecise; + + // action method wsiS0_mBurstLength + input [11 : 0] wsiS0_MBurstLength; + + // action method wsiS0_mData + input [127 : 0] wsiS0_MData; + + // action method wsiS0_mByteEn + input [15 : 0] wsiS0_MByteEn; + + // action method wsiS0_mReqInfo + input [7 : 0] wsiS0_MReqInfo; + + // action method wsiS0_mDataInfo + + // value method wsiS0_sThreadBusy + output wsiS0_SThreadBusy; + + // value method wsiS0_sReset_n + output wsiS0_SReset_n; + + // action method wsiS0_mReset_n + input wsiS0_MReset_n; + + // value method wsiM0_mCmd + output [2 : 0] wsiM0_MCmd; + + // value method wsiM0_mReqLast + output wsiM0_MReqLast; + + // value method wsiM0_mBurstPrecise + output wsiM0_MBurstPrecise; + + // value method wsiM0_mBurstLength + output [11 : 0] wsiM0_MBurstLength; + + // value method wsiM0_mData + output [127 : 0] wsiM0_MData; + + // value method wsiM0_mByteEn + output [15 : 0] wsiM0_MByteEn; + + // value method wsiM0_mReqInfo + output [7 : 0] wsiM0_MReqInfo; + + // value method wsiM0_mDataInfo + + // action method wsiM0_sThreadBusy + input wsiM0_SThreadBusy; + + // value method wsiM0_mReset_n + output wsiM0_MReset_n; + + // action method wsiM0_sReset_n + input wsiM0_SReset_n; + + // signals for module outputs + wire [127 : 0] wsiM0_MData; + wire [31 : 0] wciS0_SData; + wire [15 : 0] wsiM0_MByteEn; + wire [11 : 0] wsiM0_MBurstLength; + wire [7 : 0] wsiM0_MReqInfo; + wire [2 : 0] wsiM0_MCmd; + wire [1 : 0] wciS0_SFlag, wciS0_SResp; + wire wciS0_SThreadBusy, + wsiM0_MBurstPrecise, + wsiM0_MReqLast, + wsiM0_MReset_n, + wsiS0_SReset_n, + wsiS0_SThreadBusy; + + // inlined wires + wire [168 : 0] wsiM_reqFifo_x_wire$wget, wsiS_wsiReq$wget; + wire [127 : 0] wsi_Es_mData_w$wget; + wire [95 : 0] wsiM_extStatusW$wget, wsiS_extStatusW$wget; + wire [71 : 0] wci_wciReq$wget; + wire [33 : 0] wci_respF_x_wire$wget; + wire [31 : 0] wci_Es_mAddr_w$wget, wci_Es_mData_w$wget; + wire [15 : 0] wsi_Es_mByteEn_w$wget; + wire [11 : 0] wsi_Es_mBurstLength_w$wget; + wire [7 : 0] wsi_Es_mReqInfo_w$wget; + wire [3 : 0] wci_Es_mByteEn_w$wget; + wire [2 : 0] wci_Es_mCmd_w$wget, wci_wEdge$wget, wsi_Es_mCmd_w$wget; + wire wci_Es_mAddrSpace_w$wget, + wci_Es_mAddrSpace_w$whas, + wci_Es_mAddr_w$whas, + wci_Es_mByteEn_w$whas, + wci_Es_mCmd_w$whas, + wci_Es_mData_w$whas, + wci_ctlAckReg_1$wget, + wci_ctlAckReg_1$whas, + wci_reqF_r_clr$whas, + wci_reqF_r_deq$whas, + wci_reqF_r_enq$whas, + wci_respF_dequeueing$whas, + wci_respF_enqueueing$whas, + wci_respF_x_wire$whas, + wci_sFlagReg_1$wget, + wci_sFlagReg_1$whas, + wci_sThreadBusy_pw$whas, + wci_wEdge$whas, + wci_wciReq$whas, + wci_wci_cfrd_pw$whas, + wci_wci_cfwr_pw$whas, + wci_wci_ctrl_pw$whas, + wsiM_operateD_1$wget, + wsiM_operateD_1$whas, + wsiM_peerIsReady_1$wget, + wsiM_peerIsReady_1$whas, + wsiM_reqFifo_dequeueing$whas, + wsiM_reqFifo_enqueueing$whas, + wsiM_reqFifo_x_wire$whas, + wsiM_sThreadBusy_pw$whas, + wsiS_operateD_1$wget, + wsiS_operateD_1$whas, + wsiS_peerIsReady_1$wget, + wsiS_peerIsReady_1$whas, + wsiS_reqFifo_doResetClr$whas, + wsiS_reqFifo_doResetDeq$whas, + wsiS_reqFifo_doResetEnq$whas, + wsiS_reqFifo_r_clr$whas, + wsiS_reqFifo_r_deq$whas, + wsiS_reqFifo_r_enq$whas, + wsiS_sThreadBusy_dw$wget, + wsiS_sThreadBusy_dw$whas, + wsiS_wsiReq$whas, + wsi_Es_mBurstLength_w$whas, + wsi_Es_mBurstPrecise_w$whas, + wsi_Es_mByteEn_w$whas, + wsi_Es_mCmd_w$whas, + wsi_Es_mDataInfo_w$whas, + wsi_Es_mData_w$whas, + wsi_Es_mReqInfo_w$whas, + wsi_Es_mReqLast_w$whas; + + // register byteCount + reg [31 : 0] byteCount; + wire [31 : 0] byteCount$D_IN; + wire byteCount$EN; + + // register frameGateCtrl + reg [31 : 0] frameGateCtrl; + wire [31 : 0] frameGateCtrl$D_IN; + wire frameGateCtrl$EN; + + // register frameSize + reg [31 : 0] frameSize; + wire [31 : 0] frameSize$D_IN; + wire frameSize$EN; + + // register gateSize + reg [31 : 0] gateSize; + wire [31 : 0] gateSize$D_IN; + wire gateSize$EN; + + // register gated + reg gated; + wire gated$D_IN, gated$EN; + + // register op0MesgCnt + reg [31 : 0] op0MesgCnt; + wire [31 : 0] op0MesgCnt$D_IN; + wire op0MesgCnt$EN; + + // register otherMesgCnt + reg [31 : 0] otherMesgCnt; + wire [31 : 0] otherMesgCnt$D_IN; + wire otherMesgCnt$EN; + + // register wci_cEdge + reg [2 : 0] wci_cEdge; + wire [2 : 0] wci_cEdge$D_IN; + wire wci_cEdge$EN; + + // register wci_cState + reg [2 : 0] wci_cState; + wire [2 : 0] wci_cState$D_IN; + wire wci_cState$EN; + + // register wci_ctlAckReg + reg wci_ctlAckReg; + wire wci_ctlAckReg$D_IN, wci_ctlAckReg$EN; + + // register wci_ctlOpActive + reg wci_ctlOpActive; + wire wci_ctlOpActive$D_IN, wci_ctlOpActive$EN; + + // register wci_illegalEdge + reg wci_illegalEdge; + wire wci_illegalEdge$D_IN, wci_illegalEdge$EN; + + // register wci_isReset_isInReset + reg wci_isReset_isInReset; + wire wci_isReset_isInReset$D_IN, wci_isReset_isInReset$EN; + + // register wci_nState + reg [2 : 0] wci_nState; + reg [2 : 0] wci_nState$D_IN; + wire wci_nState$EN; + + // register wci_reqF_countReg + reg [1 : 0] wci_reqF_countReg; + wire [1 : 0] wci_reqF_countReg$D_IN; + wire wci_reqF_countReg$EN; + + // register wci_respF_c_r + reg [1 : 0] wci_respF_c_r; + wire [1 : 0] wci_respF_c_r$D_IN; + wire wci_respF_c_r$EN; + + // register wci_respF_q_0 + reg [33 : 0] wci_respF_q_0; + reg [33 : 0] wci_respF_q_0$D_IN; + wire wci_respF_q_0$EN; + + // register wci_respF_q_1 + reg [33 : 0] wci_respF_q_1; + reg [33 : 0] wci_respF_q_1$D_IN; + wire wci_respF_q_1$EN; + + // register wci_sFlagReg + reg wci_sFlagReg; + wire wci_sFlagReg$D_IN, wci_sFlagReg$EN; + + // register wci_sThreadBusy_d + reg wci_sThreadBusy_d; + wire wci_sThreadBusy_d$D_IN, wci_sThreadBusy_d$EN; + + // register wsiM_burstKind + reg [1 : 0] wsiM_burstKind; + wire [1 : 0] wsiM_burstKind$D_IN; + wire wsiM_burstKind$EN; + + // register wsiM_errorSticky + reg wsiM_errorSticky; + wire wsiM_errorSticky$D_IN, wsiM_errorSticky$EN; + + // register wsiM_iMesgCount + reg [31 : 0] wsiM_iMesgCount; + wire [31 : 0] wsiM_iMesgCount$D_IN; + wire wsiM_iMesgCount$EN; + + // register wsiM_isReset_isInReset + reg wsiM_isReset_isInReset; + wire wsiM_isReset_isInReset$D_IN, wsiM_isReset_isInReset$EN; + + // register wsiM_operateD + reg wsiM_operateD; + wire wsiM_operateD$D_IN, wsiM_operateD$EN; + + // register wsiM_pMesgCount + reg [31 : 0] wsiM_pMesgCount; + wire [31 : 0] wsiM_pMesgCount$D_IN; + wire wsiM_pMesgCount$EN; + + // register wsiM_peerIsReady + reg wsiM_peerIsReady; + wire wsiM_peerIsReady$D_IN, wsiM_peerIsReady$EN; + + // register wsiM_reqFifo_c_r + reg [1 : 0] wsiM_reqFifo_c_r; + wire [1 : 0] wsiM_reqFifo_c_r$D_IN; + wire wsiM_reqFifo_c_r$EN; + + // register wsiM_reqFifo_q_0 + reg [168 : 0] wsiM_reqFifo_q_0; + reg [168 : 0] wsiM_reqFifo_q_0$D_IN; + wire wsiM_reqFifo_q_0$EN; + + // register wsiM_reqFifo_q_1 + reg [168 : 0] wsiM_reqFifo_q_1; + reg [168 : 0] wsiM_reqFifo_q_1$D_IN; + wire wsiM_reqFifo_q_1$EN; + + // register wsiM_sThreadBusy_d + reg wsiM_sThreadBusy_d; + wire wsiM_sThreadBusy_d$D_IN, wsiM_sThreadBusy_d$EN; + + // register wsiM_statusR + reg [7 : 0] wsiM_statusR; + wire [7 : 0] wsiM_statusR$D_IN; + wire wsiM_statusR$EN; + + // register wsiM_tBusyCount + reg [31 : 0] wsiM_tBusyCount; + wire [31 : 0] wsiM_tBusyCount$D_IN; + wire wsiM_tBusyCount$EN; + + // register wsiM_trafficSticky + reg wsiM_trafficSticky; + wire wsiM_trafficSticky$D_IN, wsiM_trafficSticky$EN; + + // register wsiS_burstKind + reg [1 : 0] wsiS_burstKind; + wire [1 : 0] wsiS_burstKind$D_IN; + wire wsiS_burstKind$EN; + + // register wsiS_errorSticky + reg wsiS_errorSticky; + wire wsiS_errorSticky$D_IN, wsiS_errorSticky$EN; + + // register wsiS_iMesgCount + reg [31 : 0] wsiS_iMesgCount; + wire [31 : 0] wsiS_iMesgCount$D_IN; + wire wsiS_iMesgCount$EN; + + // register wsiS_isReset_isInReset + reg wsiS_isReset_isInReset; + wire wsiS_isReset_isInReset$D_IN, wsiS_isReset_isInReset$EN; + + // register wsiS_mesgWordLength + reg [11 : 0] wsiS_mesgWordLength; + wire [11 : 0] wsiS_mesgWordLength$D_IN; + wire wsiS_mesgWordLength$EN; + + // register wsiS_operateD + reg wsiS_operateD; + wire wsiS_operateD$D_IN, wsiS_operateD$EN; + + // register wsiS_pMesgCount + reg [31 : 0] wsiS_pMesgCount; + wire [31 : 0] wsiS_pMesgCount$D_IN; + wire wsiS_pMesgCount$EN; + + // register wsiS_peerIsReady + reg wsiS_peerIsReady; + wire wsiS_peerIsReady$D_IN, wsiS_peerIsReady$EN; + + // register wsiS_reqFifo_countReg + reg [1 : 0] wsiS_reqFifo_countReg; + wire [1 : 0] wsiS_reqFifo_countReg$D_IN; + wire wsiS_reqFifo_countReg$EN; + + // register wsiS_reqFifo_levelsValid + reg wsiS_reqFifo_levelsValid; + wire wsiS_reqFifo_levelsValid$D_IN, wsiS_reqFifo_levelsValid$EN; + + // register wsiS_statusR + reg [7 : 0] wsiS_statusR; + wire [7 : 0] wsiS_statusR$D_IN; + wire wsiS_statusR$EN; + + // register wsiS_tBusyCount + reg [31 : 0] wsiS_tBusyCount; + wire [31 : 0] wsiS_tBusyCount$D_IN; + wire wsiS_tBusyCount$EN; + + // register wsiS_trafficSticky + reg wsiS_trafficSticky; + wire wsiS_trafficSticky$D_IN, wsiS_trafficSticky$EN; + + // register wsiS_wordCount + reg [11 : 0] wsiS_wordCount; + wire [11 : 0] wsiS_wordCount$D_IN; + wire wsiS_wordCount$EN; + + // ports of submodule wci_reqF + wire [71 : 0] wci_reqF$D_IN, wci_reqF$D_OUT; + wire wci_reqF$CLR, wci_reqF$DEQ, wci_reqF$EMPTY_N, wci_reqF$ENQ; + + // ports of submodule wsiS_reqFifo + wire [168 : 0] wsiS_reqFifo$D_IN, wsiS_reqFifo$D_OUT; + wire wsiS_reqFifo$CLR, + wsiS_reqFifo$DEQ, + wsiS_reqFifo$EMPTY_N, + wsiS_reqFifo$ENQ, + wsiS_reqFifo$FULL_N; + + // rule scheduling signals + wire WILL_FIRE_RL_wci_cfrd, + WILL_FIRE_RL_wci_cfwr, + WILL_FIRE_RL_wci_ctl_op_complete, + WILL_FIRE_RL_wci_ctl_op_start, + WILL_FIRE_RL_wci_ctrl_EiI, + WILL_FIRE_RL_wci_ctrl_IsO, + WILL_FIRE_RL_wci_ctrl_OrE, + WILL_FIRE_RL_wci_respF_both, + WILL_FIRE_RL_wci_respF_decCtr, + WILL_FIRE_RL_wci_respF_incCtr, + WILL_FIRE_RL_wsiM_reqFifo_both, + WILL_FIRE_RL_wsiM_reqFifo_decCtr, + WILL_FIRE_RL_wsiM_reqFifo_deq, + WILL_FIRE_RL_wsiM_reqFifo_incCtr, + WILL_FIRE_RL_wsiS_reqFifo_enq, + WILL_FIRE_RL_wsiS_reqFifo_reset, + WILL_FIRE_RL_wsipass_doMessagePush; + + // inputs to muxes for submodule ports + reg [33 : 0] MUX_wci_respF_q_0$write_1__VAL_2; + wire [168 : 0] MUX_wsiM_reqFifo_q_0$write_1__VAL_1, + MUX_wsiM_reqFifo_q_1$write_1__VAL_1; + wire [33 : 0] MUX_wci_respF_q_0$write_1__VAL_1, + MUX_wci_respF_q_1$write_1__VAL_1, + MUX_wci_respF_x_wire$wset_1__VAL_1, + MUX_wci_respF_x_wire$wset_1__VAL_2; + wire [1 : 0] MUX_wci_respF_c_r$write_1__VAL_1, + MUX_wci_respF_c_r$write_1__VAL_2, + MUX_wsiM_reqFifo_c_r$write_1__VAL_1, + MUX_wsiM_reqFifo_c_r$write_1__VAL_2; + wire MUX_wci_illegalEdge$write_1__SEL_1, + MUX_wci_illegalEdge$write_1__SEL_2, + MUX_wci_illegalEdge$write_1__VAL_2, + MUX_wci_respF_q_0$write_1__SEL_2, + MUX_wci_respF_q_1$write_1__SEL_2, + MUX_wsiM_reqFifo_q_0$write_1__SEL_2, + MUX_wsiM_reqFifo_q_1$write_1__SEL_2; + + // remaining internal signals + reg [63 : 0] v__h11217, v__h3701, v__h3876, v__h4020; + reg [31 : 0] g_data__h10929; + wire [31 : 0] frameGateStatus__h10551, + rdat__h10963, + rdat__h11063, + rdat__h11077, + rdat__h11085, + rdat__h11091, + rdat__h11105, + rdat__h11113, + rdat__h11119, + rdat__h11130, + x__h10327; + wire [15 : 0] x__h10967; + wire NOT_gated_99_05_AND_byteCount_06_EQ_frameSize__ETC___d439, + wsiS_reqFifo_i_notEmpty__92_AND_NOT_frameGateC_ETC___d303; + + // value method wciS0_sResp + assign wciS0_SResp = wci_respF_q_0[33:32] ; + + // value method wciS0_sData + assign wciS0_SData = wci_respF_q_0[31:0] ; + + // value method wciS0_sThreadBusy + assign wciS0_SThreadBusy = + wci_reqF_countReg > 2'd1 || wci_isReset_isInReset ; + + // value method wciS0_sFlag + assign wciS0_SFlag = { 1'd1, wci_sFlagReg } ; + + // value method wsiS0_sThreadBusy + assign wsiS0_SThreadBusy = + !wsiS_sThreadBusy_dw$whas || wsiS_sThreadBusy_dw$wget ; + + // value method wsiS0_sReset_n + assign wsiS0_SReset_n = !wsiS_isReset_isInReset && wsiS_operateD ; + + // value method wsiM0_mCmd + assign wsiM0_MCmd = wsiM_sThreadBusy_d ? 3'd0 : wsiM_reqFifo_q_0[168:166] ; + + // value method wsiM0_mReqLast + assign wsiM0_MReqLast = !wsiM_sThreadBusy_d && wsiM_reqFifo_q_0[165] ; + + // value method wsiM0_mBurstPrecise + assign wsiM0_MBurstPrecise = !wsiM_sThreadBusy_d && wsiM_reqFifo_q_0[164] ; + + // value method wsiM0_mBurstLength + assign wsiM0_MBurstLength = + wsiM_sThreadBusy_d ? 12'd0 : wsiM_reqFifo_q_0[163:152] ; + + // value method wsiM0_mData + assign wsiM0_MData = wsiM_reqFifo_q_0[151:24] ; + + // value method wsiM0_mByteEn + assign wsiM0_MByteEn = wsiM_reqFifo_q_0[23:8] ; + + // value method wsiM0_mReqInfo + assign wsiM0_MReqInfo = wsiM_sThreadBusy_d ? 8'd0 : wsiM_reqFifo_q_0[7:0] ; + + // value method wsiM0_mReset_n + assign wsiM0_MReset_n = !wsiM_isReset_isInReset && wsiM_operateD ; + + // submodule wci_reqF + SizedFIFO #(.p1width(32'd72), + .p2depth(32'd3), + .p3cntr_width(32'd1), + .guarded(32'd1)) wci_reqF(.RST(wciS0_MReset_n), + .CLK(wciS0_Clk), + .D_IN(wci_reqF$D_IN), + .ENQ(wci_reqF$ENQ), + .DEQ(wci_reqF$DEQ), + .CLR(wci_reqF$CLR), + .D_OUT(wci_reqF$D_OUT), + .FULL_N(), + .EMPTY_N(wci_reqF$EMPTY_N)); + + // submodule wsiS_reqFifo + SizedFIFO #(.p1width(32'd169), + .p2depth(32'd3), + .p3cntr_width(32'd1), + .guarded(32'd1)) wsiS_reqFifo(.RST(wciS0_MReset_n), + .CLK(wciS0_Clk), + .D_IN(wsiS_reqFifo$D_IN), + .ENQ(wsiS_reqFifo$ENQ), + .DEQ(wsiS_reqFifo$DEQ), + .CLR(wsiS_reqFifo$CLR), + .D_OUT(wsiS_reqFifo$D_OUT), + .FULL_N(wsiS_reqFifo$FULL_N), + .EMPTY_N(wsiS_reqFifo$EMPTY_N)); + + // rule RL_wci_ctl_op_start + assign WILL_FIRE_RL_wci_ctl_op_start = + wci_reqF$EMPTY_N && wci_wci_ctrl_pw$whas && + !WILL_FIRE_RL_wci_ctl_op_complete ; + + // rule RL_wci_ctrl_IsO + assign WILL_FIRE_RL_wci_ctrl_IsO = + wci_wci_ctrl_pw$whas && WILL_FIRE_RL_wci_ctl_op_start && + wci_cState == 3'd1 && + wci_reqF$D_OUT[36:34] == 3'd1 ; + + // rule RL_wci_ctrl_EiI + assign WILL_FIRE_RL_wci_ctrl_EiI = + wci_wci_ctrl_pw$whas && WILL_FIRE_RL_wci_ctl_op_start && + wci_cState == 3'd0 && + wci_reqF$D_OUT[36:34] == 3'd0 ; + + // rule RL_wci_ctrl_OrE + assign WILL_FIRE_RL_wci_ctrl_OrE = + wci_wci_ctrl_pw$whas && WILL_FIRE_RL_wci_ctl_op_start && + wci_cState == 3'd2 && + wci_reqF$D_OUT[36:34] == 3'd3 ; + + // rule RL_wsipass_doMessagePush + assign WILL_FIRE_RL_wsipass_doMessagePush = + wsiS_reqFifo_i_notEmpty__92_AND_NOT_frameGateC_ETC___d303 && + wci_cState == 3'd2 ; + + // rule RL_wci_cfwr + assign WILL_FIRE_RL_wci_cfwr = + wci_respF_c_r != 2'd2 && wci_reqF$EMPTY_N && + wci_wci_cfwr_pw$whas && + !WILL_FIRE_RL_wci_ctl_op_start && + !WILL_FIRE_RL_wci_ctl_op_complete ; + + // rule RL_wci_ctl_op_complete + assign WILL_FIRE_RL_wci_ctl_op_complete = + wci_respF_c_r != 2'd2 && wci_ctlOpActive && wci_ctlAckReg ; + + // rule RL_wci_cfrd + assign WILL_FIRE_RL_wci_cfrd = + wci_respF_c_r != 2'd2 && wci_reqF$EMPTY_N && + wci_wci_cfrd_pw$whas && + !WILL_FIRE_RL_wci_ctl_op_start && + !WILL_FIRE_RL_wci_ctl_op_complete ; + + // rule RL_wci_respF_incCtr + assign WILL_FIRE_RL_wci_respF_incCtr = + ((wci_respF_c_r == 2'd0) ? + wci_respF_enqueueing$whas : + wci_respF_c_r != 2'd1 || wci_respF_enqueueing$whas) && + wci_respF_enqueueing$whas && + !(wci_respF_c_r != 2'd0) ; + + // rule RL_wci_respF_decCtr + assign WILL_FIRE_RL_wci_respF_decCtr = + wci_respF_c_r != 2'd0 && !wci_respF_enqueueing$whas ; + + // rule RL_wci_respF_both + assign WILL_FIRE_RL_wci_respF_both = + ((wci_respF_c_r == 2'd1) ? + wci_respF_enqueueing$whas : + wci_respF_c_r != 2'd2 || wci_respF_enqueueing$whas) && + wci_respF_c_r != 2'd0 && + wci_respF_enqueueing$whas ; + + // rule RL_wsiM_reqFifo_deq + assign WILL_FIRE_RL_wsiM_reqFifo_deq = + wsiM_reqFifo_c_r != 2'd0 && !wsiM_sThreadBusy_d ; + + // rule RL_wsiM_reqFifo_incCtr + assign WILL_FIRE_RL_wsiM_reqFifo_incCtr = + ((wsiM_reqFifo_c_r == 2'd0) ? + wsiM_reqFifo_enqueueing$whas : + wsiM_reqFifo_c_r != 2'd1 || wsiM_reqFifo_enqueueing$whas) && + wsiM_reqFifo_enqueueing$whas && + !WILL_FIRE_RL_wsiM_reqFifo_deq ; + + // rule RL_wsiM_reqFifo_decCtr + assign WILL_FIRE_RL_wsiM_reqFifo_decCtr = + WILL_FIRE_RL_wsiM_reqFifo_deq && !wsiM_reqFifo_enqueueing$whas ; + + // rule RL_wsiM_reqFifo_both + assign WILL_FIRE_RL_wsiM_reqFifo_both = + ((wsiM_reqFifo_c_r == 2'd1) ? + wsiM_reqFifo_enqueueing$whas : + wsiM_reqFifo_c_r != 2'd2 || wsiM_reqFifo_enqueueing$whas) && + WILL_FIRE_RL_wsiM_reqFifo_deq && + wsiM_reqFifo_enqueueing$whas ; + + // rule RL_wsiS_reqFifo_enq + assign WILL_FIRE_RL_wsiS_reqFifo_enq = + wsiS_reqFifo$FULL_N && wsiS_operateD && wsiS_peerIsReady && + wsiS_wsiReq$wget[168:166] == 3'd1 ; + + // rule RL_wsiS_reqFifo_reset + assign WILL_FIRE_RL_wsiS_reqFifo_reset = + WILL_FIRE_RL_wsiS_reqFifo_enq || + WILL_FIRE_RL_wsipass_doMessagePush ; + + // inputs to muxes for submodule ports + assign MUX_wci_illegalEdge$write_1__SEL_1 = + WILL_FIRE_RL_wci_ctl_op_complete && wci_illegalEdge ; + assign MUX_wci_illegalEdge$write_1__SEL_2 = + WILL_FIRE_RL_wci_ctl_op_start && + (wci_reqF$D_OUT[36:34] == 3'd0 && wci_cState != 3'd0 || + wci_reqF$D_OUT[36:34] == 3'd1 && wci_cState != 3'd1 && + wci_cState != 3'd3 || + wci_reqF$D_OUT[36:34] == 3'd2 && wci_cState != 3'd2 || + wci_reqF$D_OUT[36:34] == 3'd3 && wci_cState != 3'd3 && + wci_cState != 3'd2 && + wci_cState != 3'd1 || + wci_reqF$D_OUT[36:34] == 3'd4 || + wci_reqF$D_OUT[36:34] == 3'd5 || + wci_reqF$D_OUT[36:34] == 3'd6 || + wci_reqF$D_OUT[36:34] == 3'd7) ; + assign MUX_wci_respF_q_0$write_1__SEL_2 = + WILL_FIRE_RL_wci_respF_incCtr && wci_respF_c_r == 2'd0 ; + assign MUX_wci_respF_q_1$write_1__SEL_2 = + WILL_FIRE_RL_wci_respF_incCtr && wci_respF_c_r == 2'd1 ; + assign MUX_wsiM_reqFifo_q_0$write_1__SEL_2 = + WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_c_r == 2'd0 ; + assign MUX_wsiM_reqFifo_q_1$write_1__SEL_2 = + WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_c_r == 2'd1 ; + assign MUX_wci_illegalEdge$write_1__VAL_2 = + wci_reqF$D_OUT[36:34] != 3'd4 && wci_reqF$D_OUT[36:34] != 3'd5 && + wci_reqF$D_OUT[36:34] != 3'd6 ; + assign MUX_wci_respF_c_r$write_1__VAL_1 = wci_respF_c_r + 2'd1 ; + assign MUX_wci_respF_c_r$write_1__VAL_2 = wci_respF_c_r - 2'd1 ; + assign MUX_wci_respF_q_0$write_1__VAL_1 = + (wci_respF_c_r == 2'd1) ? + MUX_wci_respF_q_0$write_1__VAL_2 : + wci_respF_q_1 ; + always@(WILL_FIRE_RL_wci_ctl_op_complete or + MUX_wci_respF_x_wire$wset_1__VAL_1 or + WILL_FIRE_RL_wci_cfrd or + MUX_wci_respF_x_wire$wset_1__VAL_2 or WILL_FIRE_RL_wci_cfwr) + begin + case (1'b1) // synopsys parallel_case + WILL_FIRE_RL_wci_ctl_op_complete: + MUX_wci_respF_q_0$write_1__VAL_2 = + MUX_wci_respF_x_wire$wset_1__VAL_1; + WILL_FIRE_RL_wci_cfrd: + MUX_wci_respF_q_0$write_1__VAL_2 = + MUX_wci_respF_x_wire$wset_1__VAL_2; + WILL_FIRE_RL_wci_cfwr: MUX_wci_respF_q_0$write_1__VAL_2 = 34'h1C0DE4201; + default: MUX_wci_respF_q_0$write_1__VAL_2 = + 34'h2AAAAAAAA /* unspecified value */ ; + endcase + end + assign MUX_wci_respF_q_1$write_1__VAL_1 = + (wci_respF_c_r == 2'd2) ? + MUX_wci_respF_q_0$write_1__VAL_2 : + 34'h0AAAAAAAA ; + assign MUX_wci_respF_x_wire$wset_1__VAL_1 = + wci_illegalEdge ? 34'h3C0DE4202 : 34'h1C0DE4201 ; + assign MUX_wci_respF_x_wire$wset_1__VAL_2 = { 2'd1, g_data__h10929 } ; + assign MUX_wsiM_reqFifo_c_r$write_1__VAL_1 = wsiM_reqFifo_c_r + 2'd1 ; + assign MUX_wsiM_reqFifo_c_r$write_1__VAL_2 = wsiM_reqFifo_c_r - 2'd1 ; + assign MUX_wsiM_reqFifo_q_0$write_1__VAL_1 = + (wsiM_reqFifo_c_r == 2'd1) ? + wsiS_reqFifo$D_OUT : + wsiM_reqFifo_q_1 ; + assign MUX_wsiM_reqFifo_q_1$write_1__VAL_1 = + (wsiM_reqFifo_c_r == 2'd2) ? + wsiS_reqFifo$D_OUT : + 169'h00000AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA00 ; + + // inlined wires + assign wci_wciReq$wget = + { wciS0_MCmd, + wciS0_MAddrSpace, + wciS0_MByteEn, + wciS0_MAddr, + wciS0_MData } ; + assign wci_wciReq$whas = 1'd1 ; + assign wci_respF_x_wire$wget = MUX_wci_respF_q_0$write_1__VAL_2 ; + assign wci_respF_x_wire$whas = wci_respF_enqueueing$whas ; + assign wci_wEdge$wget = wci_reqF$D_OUT[36:34] ; + assign wci_wEdge$whas = WILL_FIRE_RL_wci_ctl_op_start ; + assign wci_sFlagReg_1$wget = 1'b0 ; + assign wci_sFlagReg_1$whas = 1'b0 ; + assign wci_ctlAckReg_1$wget = 1'd1 ; + assign wci_ctlAckReg_1$whas = + WILL_FIRE_RL_wci_ctrl_OrE || WILL_FIRE_RL_wci_ctrl_IsO || + WILL_FIRE_RL_wci_ctrl_EiI ; + assign wsiS_wsiReq$wget = + { wsiS0_MCmd, + wsiS0_MReqLast, + wsiS0_MBurstPrecise, + wsiS0_MBurstLength, + wsiS0_MData, + wsiS0_MByteEn, + wsiS0_MReqInfo } ; + assign wsiS_wsiReq$whas = 1'd1 ; + assign wsiS_operateD_1$wget = 1'd1 ; + assign wsiS_operateD_1$whas = wci_cState == 3'd2 ; + assign wsiS_peerIsReady_1$wget = 1'd1 ; + assign wsiS_peerIsReady_1$whas = wsiS0_MReset_n ; + assign wsiS_sThreadBusy_dw$wget = wsiS_reqFifo_countReg > 2'd1 ; + assign wsiS_sThreadBusy_dw$whas = + wsiS_reqFifo_levelsValid && wsiS_operateD && wsiS_peerIsReady ; + assign wsiM_reqFifo_x_wire$wget = wsiS_reqFifo$D_OUT ; + assign wsiM_reqFifo_x_wire$whas = wsiM_reqFifo_enqueueing$whas ; + assign wsiM_operateD_1$wget = 1'd1 ; + assign wsiM_operateD_1$whas = wci_cState == 3'd2 ; + assign wsiM_peerIsReady_1$wget = 1'd1 ; + assign wsiM_peerIsReady_1$whas = wsiM0_SReset_n ; + assign wci_Es_mCmd_w$wget = wciS0_MCmd ; + assign wci_Es_mCmd_w$whas = 1'd1 ; + assign wci_Es_mAddrSpace_w$wget = wciS0_MAddrSpace ; + assign wci_Es_mAddrSpace_w$whas = 1'd1 ; + assign wci_Es_mByteEn_w$wget = wciS0_MByteEn ; + assign wci_Es_mByteEn_w$whas = 1'd1 ; + assign wci_Es_mAddr_w$wget = wciS0_MAddr ; + assign wci_Es_mAddr_w$whas = 1'd1 ; + assign wci_Es_mData_w$wget = wciS0_MData ; + assign wci_Es_mData_w$whas = 1'd1 ; + assign wsi_Es_mCmd_w$wget = wsiS0_MCmd ; + assign wsi_Es_mCmd_w$whas = 1'd1 ; + assign wsi_Es_mBurstLength_w$wget = wsiS0_MBurstLength ; + assign wsi_Es_mBurstLength_w$whas = 1'd1 ; + assign wsi_Es_mData_w$wget = wsiS0_MData ; + assign wsi_Es_mData_w$whas = 1'd1 ; + assign wsi_Es_mByteEn_w$wget = wsiS0_MByteEn ; + assign wsi_Es_mByteEn_w$whas = 1'd1 ; + assign wsi_Es_mReqInfo_w$wget = wsiS0_MReqInfo ; + assign wsi_Es_mReqInfo_w$whas = 1'd1 ; + assign wci_reqF_r_enq$whas = wci_wciReq$wget[71:69] != 3'd0 ; + assign wci_reqF_r_deq$whas = + WILL_FIRE_RL_wci_ctl_op_start || WILL_FIRE_RL_wci_cfrd || + WILL_FIRE_RL_wci_cfwr ; + assign wci_reqF_r_clr$whas = 1'b0 ; + assign wci_respF_enqueueing$whas = + WILL_FIRE_RL_wci_ctl_op_complete || WILL_FIRE_RL_wci_cfrd || + WILL_FIRE_RL_wci_cfwr ; + assign wci_respF_dequeueing$whas = wci_respF_c_r != 2'd0 ; + assign wci_sThreadBusy_pw$whas = 1'b0 ; + assign wci_wci_cfwr_pw$whas = + wci_reqF$EMPTY_N && wci_reqF$D_OUT[68] && + wci_reqF$D_OUT[71:69] == 3'd1 ; + assign wci_wci_cfrd_pw$whas = + wci_reqF$EMPTY_N && wci_reqF$D_OUT[68] && + wci_reqF$D_OUT[71:69] == 3'd2 ; + assign wci_wci_ctrl_pw$whas = + wci_reqF$EMPTY_N && !wci_reqF$D_OUT[68] && + wci_reqF$D_OUT[71:69] == 3'd2 ; + assign wsiS_reqFifo_r_enq$whas = WILL_FIRE_RL_wsiS_reqFifo_enq ; + assign wsiS_reqFifo_r_deq$whas = WILL_FIRE_RL_wsipass_doMessagePush ; + assign wsiS_reqFifo_r_clr$whas = 1'b0 ; + assign wsiS_reqFifo_doResetEnq$whas = WILL_FIRE_RL_wsiS_reqFifo_enq ; + assign wsiS_reqFifo_doResetDeq$whas = WILL_FIRE_RL_wsipass_doMessagePush ; + assign wsiS_reqFifo_doResetClr$whas = 1'b0 ; + assign wsiM_reqFifo_enqueueing$whas = + WILL_FIRE_RL_wsipass_doMessagePush && + (frameGateCtrl[3:0] == 4'h0 || + frameGateCtrl[3:0] == 4'h1 && !gated) ; + assign wsiM_reqFifo_dequeueing$whas = WILL_FIRE_RL_wsiM_reqFifo_deq ; + assign wsiM_sThreadBusy_pw$whas = wsiM0_SThreadBusy ; + assign wsi_Es_mReqLast_w$whas = wsiS0_MReqLast ; + assign wsi_Es_mBurstPrecise_w$whas = wsiS0_MBurstPrecise ; + assign wsi_Es_mDataInfo_w$whas = 1'd1 ; + assign wsiS_extStatusW$wget = + { wsiS_pMesgCount, wsiS_iMesgCount, wsiS_tBusyCount } ; + assign wsiM_extStatusW$wget = + { wsiM_pMesgCount, wsiM_iMesgCount, wsiM_tBusyCount } ; + + // register byteCount + assign byteCount$D_IN = + NOT_gated_99_05_AND_byteCount_06_EQ_frameSize__ETC___d439 ? + 32'd16 : + x__h10327 ; + assign byteCount$EN = WILL_FIRE_RL_wsipass_doMessagePush ; + + // register frameGateCtrl + assign frameGateCtrl$D_IN = wci_reqF$D_OUT[31:0] ; + assign frameGateCtrl$EN = + WILL_FIRE_RL_wci_cfwr && wci_reqF$D_OUT[63:32] == 32'h00000004 ; + + // register frameSize + assign frameSize$D_IN = wci_reqF$D_OUT[31:0] ; + assign frameSize$EN = + WILL_FIRE_RL_wci_cfwr && wci_reqF$D_OUT[63:32] == 32'h00000008 ; + + // register gateSize + assign gateSize$D_IN = wci_reqF$D_OUT[31:0] ; + assign gateSize$EN = + WILL_FIRE_RL_wci_cfwr && wci_reqF$D_OUT[63:32] == 32'h0000000C ; + + // register gated + assign gated$D_IN = !gated && byteCount == frameSize ; + assign gated$EN = + WILL_FIRE_RL_wsipass_doMessagePush && + NOT_gated_99_05_AND_byteCount_06_EQ_frameSize__ETC___d439 ; + + // register op0MesgCnt + assign op0MesgCnt$D_IN = 32'h0 ; + assign op0MesgCnt$EN = 1'b0 ; + + // register otherMesgCnt + assign otherMesgCnt$D_IN = 32'h0 ; + assign otherMesgCnt$EN = 1'b0 ; + + // register wci_cEdge + assign wci_cEdge$D_IN = wci_reqF$D_OUT[36:34] ; + assign wci_cEdge$EN = WILL_FIRE_RL_wci_ctl_op_start ; + + // register wci_cState + assign wci_cState$D_IN = wci_nState ; + assign wci_cState$EN = + WILL_FIRE_RL_wci_ctl_op_complete && !wci_illegalEdge ; + + // register wci_ctlAckReg + assign wci_ctlAckReg$D_IN = wci_ctlAckReg_1$whas ; + assign wci_ctlAckReg$EN = 1'd1 ; + + // register wci_ctlOpActive + assign wci_ctlOpActive$D_IN = !WILL_FIRE_RL_wci_ctl_op_complete ; + assign wci_ctlOpActive$EN = + WILL_FIRE_RL_wci_ctl_op_complete || + WILL_FIRE_RL_wci_ctl_op_start ; + + // register wci_illegalEdge + assign wci_illegalEdge$D_IN = + !MUX_wci_illegalEdge$write_1__SEL_1 && + MUX_wci_illegalEdge$write_1__VAL_2 ; + assign wci_illegalEdge$EN = + WILL_FIRE_RL_wci_ctl_op_complete && wci_illegalEdge || + MUX_wci_illegalEdge$write_1__SEL_2 ; + + // register wci_isReset_isInReset + assign wci_isReset_isInReset$D_IN = 1'd0 ; + assign wci_isReset_isInReset$EN = wci_isReset_isInReset ; + + // register wci_nState + always@(wci_reqF$D_OUT) + begin + case (wci_reqF$D_OUT[36:34]) + 3'd0: wci_nState$D_IN = 3'd1; + 3'd1: wci_nState$D_IN = 3'd2; + 3'd2: wci_nState$D_IN = 3'd3; + default: wci_nState$D_IN = 3'd0; + endcase + end + assign wci_nState$EN = + WILL_FIRE_RL_wci_ctl_op_start && + (wci_reqF$D_OUT[36:34] == 3'd0 && wci_cState == 3'd0 || + wci_reqF$D_OUT[36:34] == 3'd1 && + (wci_cState == 3'd1 || wci_cState == 3'd3) || + wci_reqF$D_OUT[36:34] == 3'd2 && wci_cState == 3'd2 || + wci_reqF$D_OUT[36:34] == 3'd3 && + (wci_cState == 3'd3 || wci_cState == 3'd2 || + wci_cState == 3'd1)) ; + + // register wci_reqF_countReg + assign wci_reqF_countReg$D_IN = + (wci_wciReq$wget[71:69] != 3'd0) ? + wci_reqF_countReg + 2'd1 : + wci_reqF_countReg - 2'd1 ; + assign wci_reqF_countReg$EN = + (wci_wciReq$wget[71:69] != 3'd0) != wci_reqF_r_deq$whas ; + + // register wci_respF_c_r + assign wci_respF_c_r$D_IN = + WILL_FIRE_RL_wci_respF_incCtr ? + MUX_wci_respF_c_r$write_1__VAL_1 : + MUX_wci_respF_c_r$write_1__VAL_2 ; + assign wci_respF_c_r$EN = + WILL_FIRE_RL_wci_respF_incCtr || WILL_FIRE_RL_wci_respF_decCtr ; + + // register wci_respF_q_0 + always@(WILL_FIRE_RL_wci_respF_both or + MUX_wci_respF_q_0$write_1__VAL_1 or + MUX_wci_respF_q_0$write_1__SEL_2 or + MUX_wci_respF_q_0$write_1__VAL_2 or + WILL_FIRE_RL_wci_respF_decCtr or wci_respF_q_1) + begin + case (1'b1) // synopsys parallel_case + WILL_FIRE_RL_wci_respF_both: + wci_respF_q_0$D_IN = MUX_wci_respF_q_0$write_1__VAL_1; + MUX_wci_respF_q_0$write_1__SEL_2: + wci_respF_q_0$D_IN = MUX_wci_respF_q_0$write_1__VAL_2; + WILL_FIRE_RL_wci_respF_decCtr: wci_respF_q_0$D_IN = wci_respF_q_1; + default: wci_respF_q_0$D_IN = 34'h2AAAAAAAA /* unspecified value */ ; + endcase + end + assign wci_respF_q_0$EN = + WILL_FIRE_RL_wci_respF_both || + WILL_FIRE_RL_wci_respF_incCtr && wci_respF_c_r == 2'd0 || + WILL_FIRE_RL_wci_respF_decCtr ; + + // register wci_respF_q_1 + always@(WILL_FIRE_RL_wci_respF_both or + MUX_wci_respF_q_1$write_1__VAL_1 or + MUX_wci_respF_q_1$write_1__SEL_2 or + MUX_wci_respF_q_0$write_1__VAL_2 or WILL_FIRE_RL_wci_respF_decCtr) + begin + case (1'b1) // synopsys parallel_case + WILL_FIRE_RL_wci_respF_both: + wci_respF_q_1$D_IN = MUX_wci_respF_q_1$write_1__VAL_1; + MUX_wci_respF_q_1$write_1__SEL_2: + wci_respF_q_1$D_IN = MUX_wci_respF_q_0$write_1__VAL_2; + WILL_FIRE_RL_wci_respF_decCtr: wci_respF_q_1$D_IN = 34'h0AAAAAAAA; + default: wci_respF_q_1$D_IN = 34'h2AAAAAAAA /* unspecified value */ ; + endcase + end + assign wci_respF_q_1$EN = + WILL_FIRE_RL_wci_respF_both || + WILL_FIRE_RL_wci_respF_incCtr && wci_respF_c_r == 2'd1 || + WILL_FIRE_RL_wci_respF_decCtr ; + + // register wci_sFlagReg + assign wci_sFlagReg$D_IN = 1'b0 ; + assign wci_sFlagReg$EN = 1'd1 ; + + // register wci_sThreadBusy_d + assign wci_sThreadBusy_d$D_IN = 1'b0 ; + assign wci_sThreadBusy_d$EN = 1'd1 ; + + // register wsiM_burstKind + assign wsiM_burstKind$D_IN = + (wsiM_burstKind == 2'd0) ? + (wsiM_reqFifo_q_0[164] ? 2'd1 : 2'd2) : + 2'd0 ; + assign wsiM_burstKind$EN = + WILL_FIRE_RL_wsiM_reqFifo_deq && + wsiM_reqFifo_q_0[168:166] == 3'd1 && + (wsiM_burstKind == 2'd0 || + (wsiM_burstKind == 2'd1 || wsiM_burstKind == 2'd2) && + wsiM_reqFifo_q_0[165]) ; + + // register wsiM_errorSticky + assign wsiM_errorSticky$D_IN = 1'b0 ; + assign wsiM_errorSticky$EN = 1'b0 ; + + // register wsiM_iMesgCount + assign wsiM_iMesgCount$D_IN = wsiM_iMesgCount + 32'd1 ; + assign wsiM_iMesgCount$EN = + WILL_FIRE_RL_wsiM_reqFifo_deq && + wsiM_reqFifo_q_0[168:166] == 3'd1 && + wsiM_burstKind == 2'd2 && + wsiM_reqFifo_q_0[165] ; + + // register wsiM_isReset_isInReset + assign wsiM_isReset_isInReset$D_IN = 1'd0 ; + assign wsiM_isReset_isInReset$EN = wsiM_isReset_isInReset ; + + // register wsiM_operateD + assign wsiM_operateD$D_IN = wci_cState == 3'd2 ; + assign wsiM_operateD$EN = 1'd1 ; + + // register wsiM_pMesgCount + assign wsiM_pMesgCount$D_IN = wsiM_pMesgCount + 32'd1 ; + assign wsiM_pMesgCount$EN = + WILL_FIRE_RL_wsiM_reqFifo_deq && + wsiM_reqFifo_q_0[168:166] == 3'd1 && + wsiM_burstKind == 2'd1 && + wsiM_reqFifo_q_0[165] ; + + // register wsiM_peerIsReady + assign wsiM_peerIsReady$D_IN = wsiM0_SReset_n ; + assign wsiM_peerIsReady$EN = 1'd1 ; + + // register wsiM_reqFifo_c_r + assign wsiM_reqFifo_c_r$D_IN = + WILL_FIRE_RL_wsiM_reqFifo_incCtr ? + MUX_wsiM_reqFifo_c_r$write_1__VAL_1 : + MUX_wsiM_reqFifo_c_r$write_1__VAL_2 ; + assign wsiM_reqFifo_c_r$EN = + WILL_FIRE_RL_wsiM_reqFifo_incCtr || + WILL_FIRE_RL_wsiM_reqFifo_decCtr ; + + // register wsiM_reqFifo_q_0 + always@(WILL_FIRE_RL_wsiM_reqFifo_both or + MUX_wsiM_reqFifo_q_0$write_1__VAL_1 or + MUX_wsiM_reqFifo_q_0$write_1__SEL_2 or + wsiS_reqFifo$D_OUT or + WILL_FIRE_RL_wsiM_reqFifo_decCtr or wsiM_reqFifo_q_1) + begin + case (1'b1) // synopsys parallel_case + WILL_FIRE_RL_wsiM_reqFifo_both: + wsiM_reqFifo_q_0$D_IN = MUX_wsiM_reqFifo_q_0$write_1__VAL_1; + MUX_wsiM_reqFifo_q_0$write_1__SEL_2: + wsiM_reqFifo_q_0$D_IN = wsiS_reqFifo$D_OUT; + WILL_FIRE_RL_wsiM_reqFifo_decCtr: + wsiM_reqFifo_q_0$D_IN = wsiM_reqFifo_q_1; + default: wsiM_reqFifo_q_0$D_IN = + 169'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ; + endcase + end + assign wsiM_reqFifo_q_0$EN = + WILL_FIRE_RL_wsiM_reqFifo_both || + WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_c_r == 2'd0 || + WILL_FIRE_RL_wsiM_reqFifo_decCtr ; + + // register wsiM_reqFifo_q_1 + always@(WILL_FIRE_RL_wsiM_reqFifo_both or + MUX_wsiM_reqFifo_q_1$write_1__VAL_1 or + MUX_wsiM_reqFifo_q_1$write_1__SEL_2 or + wsiS_reqFifo$D_OUT or WILL_FIRE_RL_wsiM_reqFifo_decCtr) + begin + case (1'b1) // synopsys parallel_case + WILL_FIRE_RL_wsiM_reqFifo_both: + wsiM_reqFifo_q_1$D_IN = MUX_wsiM_reqFifo_q_1$write_1__VAL_1; + MUX_wsiM_reqFifo_q_1$write_1__SEL_2: + wsiM_reqFifo_q_1$D_IN = wsiS_reqFifo$D_OUT; + WILL_FIRE_RL_wsiM_reqFifo_decCtr: + wsiM_reqFifo_q_1$D_IN = + 169'h00000AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA00; + default: wsiM_reqFifo_q_1$D_IN = + 169'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ; + endcase + end + assign wsiM_reqFifo_q_1$EN = + WILL_FIRE_RL_wsiM_reqFifo_both || + WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_c_r == 2'd1 || + WILL_FIRE_RL_wsiM_reqFifo_decCtr ; + + // register wsiM_sThreadBusy_d + assign wsiM_sThreadBusy_d$D_IN = wsiM0_SThreadBusy ; + assign wsiM_sThreadBusy_d$EN = 1'd1 ; + + // register wsiM_statusR + assign wsiM_statusR$D_IN = + { wsiM_isReset_isInReset, + !wsiM_peerIsReady, + !wsiM_operateD, + wsiM_errorSticky, + wsiM_burstKind != 2'd0, + wsiM_sThreadBusy_d, + 1'd0, + wsiM_trafficSticky } ; + assign wsiM_statusR$EN = 1'd1 ; + + // register wsiM_tBusyCount + assign wsiM_tBusyCount$D_IN = wsiM_tBusyCount + 32'd1 ; + assign wsiM_tBusyCount$EN = + wsiM_operateD && wsiM_peerIsReady && wsiM_sThreadBusy_d ; + + // register wsiM_trafficSticky + assign wsiM_trafficSticky$D_IN = 1'd1 ; + assign wsiM_trafficSticky$EN = + WILL_FIRE_RL_wsiM_reqFifo_deq && + wsiM_reqFifo_q_0[168:166] == 3'd1 ; + + // register wsiS_burstKind + assign wsiS_burstKind$D_IN = + (wsiS_burstKind == 2'd0) ? + (wsiS_wsiReq$wget[164] ? 2'd1 : 2'd2) : + 2'd0 ; + assign wsiS_burstKind$EN = + WILL_FIRE_RL_wsiS_reqFifo_enq && + (wsiS_burstKind == 2'd0 || + (wsiS_burstKind == 2'd1 || wsiS_burstKind == 2'd2) && + wsiS_wsiReq$wget[165]) ; + + // register wsiS_errorSticky + assign wsiS_errorSticky$D_IN = 1'b0 ; + assign wsiS_errorSticky$EN = 1'b0 ; + + // register wsiS_iMesgCount + assign wsiS_iMesgCount$D_IN = wsiS_iMesgCount + 32'd1 ; + assign wsiS_iMesgCount$EN = + WILL_FIRE_RL_wsiS_reqFifo_enq && wsiS_burstKind == 2'd2 && + wsiS_wsiReq$wget[165] ; + + // register wsiS_isReset_isInReset + assign wsiS_isReset_isInReset$D_IN = 1'd0 ; + assign wsiS_isReset_isInReset$EN = wsiS_isReset_isInReset ; + + // register wsiS_mesgWordLength + assign wsiS_mesgWordLength$D_IN = wsiS_wordCount ; + assign wsiS_mesgWordLength$EN = + WILL_FIRE_RL_wsiS_reqFifo_enq && wsiS_wsiReq$wget[165] ; + + // register wsiS_operateD + assign wsiS_operateD$D_IN = wci_cState == 3'd2 ; + assign wsiS_operateD$EN = 1'd1 ; + + // register wsiS_pMesgCount + assign wsiS_pMesgCount$D_IN = wsiS_pMesgCount + 32'd1 ; + assign wsiS_pMesgCount$EN = + WILL_FIRE_RL_wsiS_reqFifo_enq && wsiS_burstKind == 2'd1 && + wsiS_wsiReq$wget[165] ; + + // register wsiS_peerIsReady + assign wsiS_peerIsReady$D_IN = wsiS0_MReset_n ; + assign wsiS_peerIsReady$EN = 1'd1 ; + + // register wsiS_reqFifo_countReg + assign wsiS_reqFifo_countReg$D_IN = + WILL_FIRE_RL_wsiS_reqFifo_enq ? + wsiS_reqFifo_countReg + 2'd1 : + wsiS_reqFifo_countReg - 2'd1 ; + assign wsiS_reqFifo_countReg$EN = + WILL_FIRE_RL_wsiS_reqFifo_enq != + WILL_FIRE_RL_wsipass_doMessagePush ; + + // register wsiS_reqFifo_levelsValid + assign wsiS_reqFifo_levelsValid$D_IN = WILL_FIRE_RL_wsiS_reqFifo_reset ; + assign wsiS_reqFifo_levelsValid$EN = + WILL_FIRE_RL_wsipass_doMessagePush || + WILL_FIRE_RL_wsiS_reqFifo_enq || + WILL_FIRE_RL_wsiS_reqFifo_reset ; + + // register wsiS_statusR + assign wsiS_statusR$D_IN = + { wsiS_isReset_isInReset, + !wsiS_peerIsReady, + !wsiS_operateD, + wsiS_errorSticky, + wsiS_burstKind != 2'd0, + !wsiS_sThreadBusy_dw$whas || wsiS_sThreadBusy_dw$wget, + 1'd0, + wsiS_trafficSticky } ; + assign wsiS_statusR$EN = 1'd1 ; + + // register wsiS_tBusyCount + assign wsiS_tBusyCount$D_IN = wsiS_tBusyCount + 32'd1 ; + assign wsiS_tBusyCount$EN = + wsiS_operateD && wsiS_peerIsReady && + (!wsiS_sThreadBusy_dw$whas || wsiS_sThreadBusy_dw$wget) ; + + // register wsiS_trafficSticky + assign wsiS_trafficSticky$D_IN = 1'd1 ; + assign wsiS_trafficSticky$EN = WILL_FIRE_RL_wsiS_reqFifo_enq ; + + // register wsiS_wordCount + assign wsiS_wordCount$D_IN = + wsiS_wsiReq$wget[165] ? 12'd1 : wsiS_wordCount + 12'd1 ; + assign wsiS_wordCount$EN = WILL_FIRE_RL_wsiS_reqFifo_enq ; + + // submodule wci_reqF + assign wci_reqF$D_IN = wci_wciReq$wget ; + assign wci_reqF$ENQ = wci_wciReq$wget[71:69] != 3'd0 ; + assign wci_reqF$DEQ = wci_reqF_r_deq$whas ; + assign wci_reqF$CLR = 1'b0 ; + + // submodule wsiS_reqFifo + assign wsiS_reqFifo$D_IN = wsiS_wsiReq$wget ; + assign wsiS_reqFifo$ENQ = WILL_FIRE_RL_wsiS_reqFifo_enq ; + assign wsiS_reqFifo$DEQ = WILL_FIRE_RL_wsipass_doMessagePush ; + assign wsiS_reqFifo$CLR = 1'b0 ; + + // remaining internal signals + assign NOT_gated_99_05_AND_byteCount_06_EQ_frameSize__ETC___d439 = + !gated && byteCount == frameSize || + gated && byteCount == gateSize ; + assign frameGateStatus__h10551 = { 31'd0, hasDebugLogic } ; + assign rdat__h10963 = hasDebugLogic ? { 16'd0, x__h10967 } : 32'd0 ; + assign rdat__h11063 = hasDebugLogic ? wsiS_extStatusW$wget[95:64] : 32'd0 ; + assign rdat__h11077 = hasDebugLogic ? wsiS_extStatusW$wget[63:32] : 32'd0 ; + assign rdat__h11085 = hasDebugLogic ? wsiS_extStatusW$wget[31:0] : 32'd0 ; + assign rdat__h11091 = hasDebugLogic ? wsiM_extStatusW$wget[95:64] : 32'd0 ; + assign rdat__h11105 = hasDebugLogic ? wsiM_extStatusW$wget[63:32] : 32'd0 ; + assign rdat__h11113 = hasDebugLogic ? wsiM_extStatusW$wget[31:0] : 32'd0 ; + assign rdat__h11119 = hasDebugLogic ? op0MesgCnt : 32'd0 ; + assign rdat__h11130 = hasDebugLogic ? otherMesgCnt : 32'd0 ; + assign wsiS_reqFifo_i_notEmpty__92_AND_NOT_frameGateC_ETC___d303 = + wsiS_reqFifo$EMPTY_N && + (frameGateCtrl[3:0] != 4'h0 && + (frameGateCtrl[3:0] != 4'h1 || gated) || + wsiM_reqFifo_c_r != 2'd2) ; + assign x__h10327 = byteCount + 32'd16 ; + assign x__h10967 = { wsiS_statusR, wsiM_statusR } ; + always@(wci_reqF$D_OUT or + frameGateStatus__h10551 or + frameGateCtrl or + frameSize or + gateSize or + rdat__h10963 or + rdat__h11063 or + rdat__h11077 or + rdat__h11085 or + rdat__h11091 or + rdat__h11105 or rdat__h11113 or rdat__h11119 or rdat__h11130) + begin + case (wci_reqF$D_OUT[63:32]) + 32'h0: g_data__h10929 = frameGateStatus__h10551; + 32'h00000004: g_data__h10929 = frameGateCtrl; + 32'h00000008: g_data__h10929 = frameSize; + 32'h0000000C: g_data__h10929 = gateSize; + 32'h00000010: g_data__h10929 = rdat__h10963; + 32'h00000014: g_data__h10929 = rdat__h11063; + 32'h00000018: g_data__h10929 = rdat__h11077; + 32'h0000001C: g_data__h10929 = rdat__h11085; + 32'h00000020: g_data__h10929 = rdat__h11091; + 32'h00000024: g_data__h10929 = rdat__h11105; + 32'h00000028: g_data__h10929 = rdat__h11113; + 32'h0000002C: g_data__h10929 = rdat__h11119; + 32'h00000030: g_data__h10929 = rdat__h11130; + default: g_data__h10929 = 32'd0; + endcase + end + + // handling of inlined registers + + always@(posedge wciS0_Clk) + begin + if (wciS0_MReset_n == `BSV_RESET_VALUE) + begin + byteCount <= `BSV_ASSIGNMENT_DELAY 32'd16; + frameGateCtrl <= `BSV_ASSIGNMENT_DELAY fgCtrlInit; + frameSize <= `BSV_ASSIGNMENT_DELAY 32'd0; + gateSize <= `BSV_ASSIGNMENT_DELAY 32'd0; + gated <= `BSV_ASSIGNMENT_DELAY 1'd0; + op0MesgCnt <= `BSV_ASSIGNMENT_DELAY 32'd0; + otherMesgCnt <= `BSV_ASSIGNMENT_DELAY 32'd0; + wci_cEdge <= `BSV_ASSIGNMENT_DELAY 3'h2; + wci_cState <= `BSV_ASSIGNMENT_DELAY 3'd0; + wci_ctlAckReg <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_ctlOpActive <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_illegalEdge <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_nState <= `BSV_ASSIGNMENT_DELAY 3'd0; + wci_reqF_countReg <= `BSV_ASSIGNMENT_DELAY 2'd0; + wci_respF_c_r <= `BSV_ASSIGNMENT_DELAY 2'd0; + wci_respF_q_0 <= `BSV_ASSIGNMENT_DELAY 34'h0AAAAAAAA; + wci_respF_q_1 <= `BSV_ASSIGNMENT_DELAY 34'h0AAAAAAAA; + wci_sFlagReg <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY 1'd1; + wsiM_burstKind <= `BSV_ASSIGNMENT_DELAY 2'd0; + wsiM_errorSticky <= `BSV_ASSIGNMENT_DELAY 1'd0; + wsiM_iMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0; + wsiM_operateD <= `BSV_ASSIGNMENT_DELAY 1'd0; + wsiM_pMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0; + wsiM_peerIsReady <= `BSV_ASSIGNMENT_DELAY 1'd0; + wsiM_reqFifo_c_r <= `BSV_ASSIGNMENT_DELAY 2'd0; + wsiM_reqFifo_q_0 <= `BSV_ASSIGNMENT_DELAY + 169'h00000AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA00; + wsiM_reqFifo_q_1 <= `BSV_ASSIGNMENT_DELAY + 169'h00000AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA00; + wsiM_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY 1'd1; + wsiM_tBusyCount <= `BSV_ASSIGNMENT_DELAY 32'd0; + wsiM_trafficSticky <= `BSV_ASSIGNMENT_DELAY 1'd0; + wsiS_burstKind <= `BSV_ASSIGNMENT_DELAY 2'd0; + wsiS_errorSticky <= `BSV_ASSIGNMENT_DELAY 1'd0; + wsiS_iMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0; + wsiS_operateD <= `BSV_ASSIGNMENT_DELAY 1'd0; + wsiS_pMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0; + wsiS_peerIsReady <= `BSV_ASSIGNMENT_DELAY 1'd0; + wsiS_reqFifo_countReg <= `BSV_ASSIGNMENT_DELAY 2'd0; + wsiS_reqFifo_levelsValid <= `BSV_ASSIGNMENT_DELAY 1'd1; + wsiS_tBusyCount <= `BSV_ASSIGNMENT_DELAY 32'd0; + wsiS_trafficSticky <= `BSV_ASSIGNMENT_DELAY 1'd0; + wsiS_wordCount <= `BSV_ASSIGNMENT_DELAY 12'd1; + end + else + begin + if (byteCount$EN) byteCount <= `BSV_ASSIGNMENT_DELAY byteCount$D_IN; + if (frameGateCtrl$EN) + frameGateCtrl <= `BSV_ASSIGNMENT_DELAY frameGateCtrl$D_IN; + if (frameSize$EN) frameSize <= `BSV_ASSIGNMENT_DELAY frameSize$D_IN; + if (gateSize$EN) gateSize <= `BSV_ASSIGNMENT_DELAY gateSize$D_IN; + if (gated$EN) gated <= `BSV_ASSIGNMENT_DELAY gated$D_IN; + if (op0MesgCnt$EN) + op0MesgCnt <= `BSV_ASSIGNMENT_DELAY op0MesgCnt$D_IN; + if (otherMesgCnt$EN) + otherMesgCnt <= `BSV_ASSIGNMENT_DELAY otherMesgCnt$D_IN; + if (wci_cEdge$EN) wci_cEdge <= `BSV_ASSIGNMENT_DELAY wci_cEdge$D_IN; + if (wci_cState$EN) + wci_cState <= `BSV_ASSIGNMENT_DELAY wci_cState$D_IN; + if (wci_ctlAckReg$EN) + wci_ctlAckReg <= `BSV_ASSIGNMENT_DELAY wci_ctlAckReg$D_IN; + if (wci_ctlOpActive$EN) + wci_ctlOpActive <= `BSV_ASSIGNMENT_DELAY wci_ctlOpActive$D_IN; + if (wci_illegalEdge$EN) + wci_illegalEdge <= `BSV_ASSIGNMENT_DELAY wci_illegalEdge$D_IN; + if (wci_nState$EN) + wci_nState <= `BSV_ASSIGNMENT_DELAY wci_nState$D_IN; + if (wci_reqF_countReg$EN) + wci_reqF_countReg <= `BSV_ASSIGNMENT_DELAY wci_reqF_countReg$D_IN; + if (wci_respF_c_r$EN) + wci_respF_c_r <= `BSV_ASSIGNMENT_DELAY wci_respF_c_r$D_IN; + if (wci_respF_q_0$EN) + wci_respF_q_0 <= `BSV_ASSIGNMENT_DELAY wci_respF_q_0$D_IN; + if (wci_respF_q_1$EN) + wci_respF_q_1 <= `BSV_ASSIGNMENT_DELAY wci_respF_q_1$D_IN; + if (wci_sFlagReg$EN) + wci_sFlagReg <= `BSV_ASSIGNMENT_DELAY wci_sFlagReg$D_IN; + if (wci_sThreadBusy_d$EN) + wci_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY wci_sThreadBusy_d$D_IN; + if (wsiM_burstKind$EN) + wsiM_burstKind <= `BSV_ASSIGNMENT_DELAY wsiM_burstKind$D_IN; + if (wsiM_errorSticky$EN) + wsiM_errorSticky <= `BSV_ASSIGNMENT_DELAY wsiM_errorSticky$D_IN; + if (wsiM_iMesgCount$EN) + wsiM_iMesgCount <= `BSV_ASSIGNMENT_DELAY wsiM_iMesgCount$D_IN; + if (wsiM_operateD$EN) + wsiM_operateD <= `BSV_ASSIGNMENT_DELAY wsiM_operateD$D_IN; + if (wsiM_pMesgCount$EN) + wsiM_pMesgCount <= `BSV_ASSIGNMENT_DELAY wsiM_pMesgCount$D_IN; + if (wsiM_peerIsReady$EN) + wsiM_peerIsReady <= `BSV_ASSIGNMENT_DELAY wsiM_peerIsReady$D_IN; + if (wsiM_reqFifo_c_r$EN) + wsiM_reqFifo_c_r <= `BSV_ASSIGNMENT_DELAY wsiM_reqFifo_c_r$D_IN; + if (wsiM_reqFifo_q_0$EN) + wsiM_reqFifo_q_0 <= `BSV_ASSIGNMENT_DELAY wsiM_reqFifo_q_0$D_IN; + if (wsiM_reqFifo_q_1$EN) + wsiM_reqFifo_q_1 <= `BSV_ASSIGNMENT_DELAY wsiM_reqFifo_q_1$D_IN; + if (wsiM_sThreadBusy_d$EN) + wsiM_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY wsiM_sThreadBusy_d$D_IN; + if (wsiM_tBusyCount$EN) + wsiM_tBusyCount <= `BSV_ASSIGNMENT_DELAY wsiM_tBusyCount$D_IN; + if (wsiM_trafficSticky$EN) + wsiM_trafficSticky <= `BSV_ASSIGNMENT_DELAY wsiM_trafficSticky$D_IN; + if (wsiS_burstKind$EN) + wsiS_burstKind <= `BSV_ASSIGNMENT_DELAY wsiS_burstKind$D_IN; + if (wsiS_errorSticky$EN) + wsiS_errorSticky <= `BSV_ASSIGNMENT_DELAY wsiS_errorSticky$D_IN; + if (wsiS_iMesgCount$EN) + wsiS_iMesgCount <= `BSV_ASSIGNMENT_DELAY wsiS_iMesgCount$D_IN; + if (wsiS_operateD$EN) + wsiS_operateD <= `BSV_ASSIGNMENT_DELAY wsiS_operateD$D_IN; + if (wsiS_pMesgCount$EN) + wsiS_pMesgCount <= `BSV_ASSIGNMENT_DELAY wsiS_pMesgCount$D_IN; + if (wsiS_peerIsReady$EN) + wsiS_peerIsReady <= `BSV_ASSIGNMENT_DELAY wsiS_peerIsReady$D_IN; + if (wsiS_reqFifo_countReg$EN) + wsiS_reqFifo_countReg <= `BSV_ASSIGNMENT_DELAY + wsiS_reqFifo_countReg$D_IN; + if (wsiS_reqFifo_levelsValid$EN) + wsiS_reqFifo_levelsValid <= `BSV_ASSIGNMENT_DELAY + wsiS_reqFifo_levelsValid$D_IN; + if (wsiS_tBusyCount$EN) + wsiS_tBusyCount <= `BSV_ASSIGNMENT_DELAY wsiS_tBusyCount$D_IN; + if (wsiS_trafficSticky$EN) + wsiS_trafficSticky <= `BSV_ASSIGNMENT_DELAY wsiS_trafficSticky$D_IN; + if (wsiS_wordCount$EN) + wsiS_wordCount <= `BSV_ASSIGNMENT_DELAY wsiS_wordCount$D_IN; + end + if (wsiM_statusR$EN) + wsiM_statusR <= `BSV_ASSIGNMENT_DELAY wsiM_statusR$D_IN; + if (wsiS_mesgWordLength$EN) + wsiS_mesgWordLength <= `BSV_ASSIGNMENT_DELAY wsiS_mesgWordLength$D_IN; + if (wsiS_statusR$EN) + wsiS_statusR <= `BSV_ASSIGNMENT_DELAY wsiS_statusR$D_IN; + end + + always@(posedge wciS0_Clk or `BSV_RESET_EDGE wciS0_MReset_n) + if (wciS0_MReset_n == `BSV_RESET_VALUE) + begin + wci_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY 1'd1; + wsiM_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY 1'd1; + wsiS_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY 1'd1; + end + else + begin + if (wci_isReset_isInReset$EN) + wci_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY + wci_isReset_isInReset$D_IN; + if (wsiM_isReset_isInReset$EN) + wsiM_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY + wsiM_isReset_isInReset$D_IN; + if (wsiS_isReset_isInReset$EN) + wsiS_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY + wsiS_isReset_isInReset$D_IN; + end + + // synopsys translate_off + `ifdef BSV_NO_INITIAL_BLOCKS + `else // not BSV_NO_INITIAL_BLOCKS + initial + begin + byteCount = 32'hAAAAAAAA; + frameGateCtrl = 32'hAAAAAAAA; + frameSize = 32'hAAAAAAAA; + gateSize = 32'hAAAAAAAA; + gated = 1'h0; + op0MesgCnt = 32'hAAAAAAAA; + otherMesgCnt = 32'hAAAAAAAA; + wci_cEdge = 3'h2; + wci_cState = 3'h2; + wci_ctlAckReg = 1'h0; + wci_ctlOpActive = 1'h0; + wci_illegalEdge = 1'h0; + wci_isReset_isInReset = 1'h0; + wci_nState = 3'h2; + wci_reqF_countReg = 2'h2; + wci_respF_c_r = 2'h2; + wci_respF_q_0 = 34'h2AAAAAAAA; + wci_respF_q_1 = 34'h2AAAAAAAA; + wci_sFlagReg = 1'h0; + wci_sThreadBusy_d = 1'h0; + wsiM_burstKind = 2'h2; + wsiM_errorSticky = 1'h0; + wsiM_iMesgCount = 32'hAAAAAAAA; + wsiM_isReset_isInReset = 1'h0; + wsiM_operateD = 1'h0; + wsiM_pMesgCount = 32'hAAAAAAAA; + wsiM_peerIsReady = 1'h0; + wsiM_reqFifo_c_r = 2'h2; + wsiM_reqFifo_q_0 = 169'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; + wsiM_reqFifo_q_1 = 169'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; + wsiM_sThreadBusy_d = 1'h0; + wsiM_statusR = 8'hAA; + wsiM_tBusyCount = 32'hAAAAAAAA; + wsiM_trafficSticky = 1'h0; + wsiS_burstKind = 2'h2; + wsiS_errorSticky = 1'h0; + wsiS_iMesgCount = 32'hAAAAAAAA; + wsiS_isReset_isInReset = 1'h0; + wsiS_mesgWordLength = 12'hAAA; + wsiS_operateD = 1'h0; + wsiS_pMesgCount = 32'hAAAAAAAA; + wsiS_peerIsReady = 1'h0; + wsiS_reqFifo_countReg = 2'h2; + wsiS_reqFifo_levelsValid = 1'h0; + wsiS_statusR = 8'hAA; + wsiS_tBusyCount = 32'hAAAAAAAA; + wsiS_trafficSticky = 1'h0; + wsiS_wordCount = 12'hAAA; + end + `endif // BSV_NO_INITIAL_BLOCKS + // synopsys translate_on + + // handling of system tasks + + // synopsys translate_off + always@(negedge wciS0_Clk) + begin + #0; + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_ctl_op_start) + begin + v__h3701 = $time; + #0; + end + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_ctl_op_start) + $display("[%0d]: %m: WCI ControlOp: Starting-transition edge:%x from:%x", + v__h3701, + wci_reqF$D_OUT[36:34], + wci_cState); + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_ctrl_IsO) + begin + v__h11217 = $time; + #0; + end + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_ctrl_IsO) + $display("[%0d]: %m: Starting FrameGate frameGateCtrl:%0x", + v__h11217, + frameGateCtrl); + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_ctrl_IsO && WILL_FIRE_RL_wci_ctrl_OrE) + $display("Error: \"bsv/prm/FrameGate.bsv\", line 68, column 60: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_IsO] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n"); + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_ctrl_EiI && WILL_FIRE_RL_wci_ctrl_OrE) + $display("Error: \"bsv/prm/FrameGate.bsv\", line 68, column 46: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_EiI] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n"); + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_ctrl_EiI && WILL_FIRE_RL_wci_ctrl_IsO) + $display("Error: \"bsv/prm/FrameGate.bsv\", line 68, column 46: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_EiI] and\n [RL_wci_ctrl_IsO] ) fired in the same clock cycle.\n"); + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_ctl_op_complete && wci_illegalEdge) + begin + v__h4020 = $time; + #0; + end + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_ctl_op_complete && wci_illegalEdge) + $display("[%0d]: %m: WCI ControlOp: ILLEGAL-EDGE Completed-transition edge:%x from:%x", + v__h4020, + wci_cEdge, + wci_cState); + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_ctl_op_complete && !wci_illegalEdge) + begin + v__h3876 = $time; + #0; + end + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_ctl_op_complete && !wci_illegalEdge) + $display("[%0d]: %m: WCI ControlOp: Completed-transition edge:%x from:%x to:%x", + v__h3876, + wci_cEdge, + wci_cState, + wci_nState); + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_OrE) + $display("Error: \"bsv/prm/FrameGate.bsv\", line 68, column 26: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n"); + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_IsO) + $display("Error: \"bsv/prm/FrameGate.bsv\", line 68, column 26: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_wci_ctrl_IsO] ) fired in the same clock cycle.\n"); + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_EiI) + $display("Error: \"bsv/prm/FrameGate.bsv\", line 68, column 26: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_wci_ctrl_EiI] ) fired in the same clock cycle.\n"); + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_cfrd) + $display("Error: \"bsv/prm/FrameGate.bsv\", line 68, column 26: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and [RL_wci_cfrd] )\n fired in the same clock cycle.\n"); + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_cfrd && WILL_FIRE_RL_wci_ctrl_OrE) + $display("Error: \"bsv/prm/FrameGate.bsv\", line 68, column 36: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n"); + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_cfrd && WILL_FIRE_RL_wci_ctrl_IsO) + $display("Error: \"bsv/prm/FrameGate.bsv\", line 68, column 36: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n [RL_wci_ctrl_IsO] ) fired in the same clock cycle.\n"); + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_cfrd && WILL_FIRE_RL_wci_ctrl_EiI) + $display("Error: \"bsv/prm/FrameGate.bsv\", line 68, column 36: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n [RL_wci_ctrl_EiI] ) fired in the same clock cycle.\n"); + end + // synopsys translate_on +endmodule // mkFrameGate16B + diff --git a/rtl/mkFrameGate32B.v b/rtl/mkFrameGate32B.v new file mode 100644 index 00000000..9cfde3f7 --- /dev/null +++ b/rtl/mkFrameGate32B.v @@ -0,0 +1,1666 @@ +// +// Generated by Bluespec Compiler, version 2012.09.beta1 (build 29570, 2012-09.11) +// +// On Tue Jan 22 07:33:01 EST 2013 +// +// +// Ports: +// Name I/O size props +// wciS0_SResp O 2 reg +// wciS0_SData O 32 reg +// wciS0_SThreadBusy O 1 +// wciS0_SFlag O 2 +// wsiS0_SThreadBusy O 1 +// wsiS0_SReset_n O 1 +// wsiM0_MCmd O 3 +// wsiM0_MReqLast O 1 +// wsiM0_MBurstPrecise O 1 +// wsiM0_MBurstLength O 12 +// wsiM0_MData O 256 reg +// wsiM0_MByteEn O 32 reg +// wsiM0_MReqInfo O 8 +// wsiM0_MReset_n O 1 +// wciS0_Clk I 1 clock +// wciS0_MReset_n I 1 reset +// wciS0_MCmd I 3 +// wciS0_MAddrSpace I 1 +// wciS0_MByteEn I 4 +// wciS0_MAddr I 32 +// wciS0_MData I 32 +// wciS0_MFlag I 2 unused +// wsiS0_MCmd I 3 +// wsiS0_MBurstLength I 12 +// wsiS0_MData I 256 +// wsiS0_MByteEn I 32 +// wsiS0_MReqInfo I 8 +// wsiS0_MReqLast I 1 +// wsiS0_MBurstPrecise I 1 +// wsiS0_MReset_n I 1 reg +// wsiM0_SThreadBusy I 1 reg +// wsiM0_SReset_n I 1 reg +// +// No combinational paths from inputs to outputs +// +// + +`ifdef BSV_ASSIGNMENT_DELAY +`else + `define BSV_ASSIGNMENT_DELAY +`endif + +`ifdef BSV_POSITIVE_RESET + `define BSV_RESET_VALUE 1'b1 + `define BSV_RESET_EDGE posedge +`else + `define BSV_RESET_VALUE 1'b0 + `define BSV_RESET_EDGE negedge +`endif + +module mkFrameGate32B(wciS0_Clk, + wciS0_MReset_n, + + wciS0_MCmd, + + wciS0_MAddrSpace, + + wciS0_MByteEn, + + wciS0_MAddr, + + wciS0_MData, + + wciS0_SResp, + + wciS0_SData, + + wciS0_SThreadBusy, + + wciS0_SFlag, + + wciS0_MFlag, + + wsiS0_MCmd, + + wsiS0_MReqLast, + + wsiS0_MBurstPrecise, + + wsiS0_MBurstLength, + + wsiS0_MData, + + wsiS0_MByteEn, + + wsiS0_MReqInfo, + + wsiS0_SThreadBusy, + + wsiS0_SReset_n, + + wsiS0_MReset_n, + + wsiM0_MCmd, + + wsiM0_MReqLast, + + wsiM0_MBurstPrecise, + + wsiM0_MBurstLength, + + wsiM0_MData, + + wsiM0_MByteEn, + + wsiM0_MReqInfo, + + wsiM0_SThreadBusy, + + wsiM0_MReset_n, + + wsiM0_SReset_n); + parameter [31 : 0] fgCtrlInit = 32'b0; + parameter [0 : 0] hasDebugLogic = 1'b0; + input wciS0_Clk; + input wciS0_MReset_n; + + // action method wciS0_mCmd + input [2 : 0] wciS0_MCmd; + + // action method wciS0_mAddrSpace + input wciS0_MAddrSpace; + + // action method wciS0_mByteEn + input [3 : 0] wciS0_MByteEn; + + // action method wciS0_mAddr + input [31 : 0] wciS0_MAddr; + + // action method wciS0_mData + input [31 : 0] wciS0_MData; + + // value method wciS0_sResp + output [1 : 0] wciS0_SResp; + + // value method wciS0_sData + output [31 : 0] wciS0_SData; + + // value method wciS0_sThreadBusy + output wciS0_SThreadBusy; + + // value method wciS0_sFlag + output [1 : 0] wciS0_SFlag; + + // action method wciS0_mFlag + input [1 : 0] wciS0_MFlag; + + // action method wsiS0_mCmd + input [2 : 0] wsiS0_MCmd; + + // action method wsiS0_mReqLast + input wsiS0_MReqLast; + + // action method wsiS0_mBurstPrecise + input wsiS0_MBurstPrecise; + + // action method wsiS0_mBurstLength + input [11 : 0] wsiS0_MBurstLength; + + // action method wsiS0_mData + input [255 : 0] wsiS0_MData; + + // action method wsiS0_mByteEn + input [31 : 0] wsiS0_MByteEn; + + // action method wsiS0_mReqInfo + input [7 : 0] wsiS0_MReqInfo; + + // action method wsiS0_mDataInfo + + // value method wsiS0_sThreadBusy + output wsiS0_SThreadBusy; + + // value method wsiS0_sReset_n + output wsiS0_SReset_n; + + // action method wsiS0_mReset_n + input wsiS0_MReset_n; + + // value method wsiM0_mCmd + output [2 : 0] wsiM0_MCmd; + + // value method wsiM0_mReqLast + output wsiM0_MReqLast; + + // value method wsiM0_mBurstPrecise + output wsiM0_MBurstPrecise; + + // value method wsiM0_mBurstLength + output [11 : 0] wsiM0_MBurstLength; + + // value method wsiM0_mData + output [255 : 0] wsiM0_MData; + + // value method wsiM0_mByteEn + output [31 : 0] wsiM0_MByteEn; + + // value method wsiM0_mReqInfo + output [7 : 0] wsiM0_MReqInfo; + + // value method wsiM0_mDataInfo + + // action method wsiM0_sThreadBusy + input wsiM0_SThreadBusy; + + // value method wsiM0_mReset_n + output wsiM0_MReset_n; + + // action method wsiM0_sReset_n + input wsiM0_SReset_n; + + // signals for module outputs + wire [255 : 0] wsiM0_MData; + wire [31 : 0] wciS0_SData, wsiM0_MByteEn; + wire [11 : 0] wsiM0_MBurstLength; + wire [7 : 0] wsiM0_MReqInfo; + wire [2 : 0] wsiM0_MCmd; + wire [1 : 0] wciS0_SFlag, wciS0_SResp; + wire wciS0_SThreadBusy, + wsiM0_MBurstPrecise, + wsiM0_MReqLast, + wsiM0_MReset_n, + wsiS0_SReset_n, + wsiS0_SThreadBusy; + + // inlined wires + wire [312 : 0] wsiM_reqFifo_x_wire$wget, wsiS_wsiReq$wget; + wire [255 : 0] wsi_Es_mData_w$wget; + wire [95 : 0] wsiM_extStatusW$wget, wsiS_extStatusW$wget; + wire [71 : 0] wci_wciReq$wget; + wire [33 : 0] wci_respF_x_wire$wget; + wire [31 : 0] wci_Es_mAddr_w$wget, + wci_Es_mData_w$wget, + wsi_Es_mByteEn_w$wget; + wire [11 : 0] wsi_Es_mBurstLength_w$wget; + wire [7 : 0] wsi_Es_mReqInfo_w$wget; + wire [3 : 0] wci_Es_mByteEn_w$wget; + wire [2 : 0] wci_Es_mCmd_w$wget, wci_wEdge$wget, wsi_Es_mCmd_w$wget; + wire wci_Es_mAddrSpace_w$wget, + wci_Es_mAddrSpace_w$whas, + wci_Es_mAddr_w$whas, + wci_Es_mByteEn_w$whas, + wci_Es_mCmd_w$whas, + wci_Es_mData_w$whas, + wci_ctlAckReg_1$wget, + wci_ctlAckReg_1$whas, + wci_reqF_r_clr$whas, + wci_reqF_r_deq$whas, + wci_reqF_r_enq$whas, + wci_respF_dequeueing$whas, + wci_respF_enqueueing$whas, + wci_respF_x_wire$whas, + wci_sFlagReg_1$wget, + wci_sFlagReg_1$whas, + wci_sThreadBusy_pw$whas, + wci_wEdge$whas, + wci_wciReq$whas, + wci_wci_cfrd_pw$whas, + wci_wci_cfwr_pw$whas, + wci_wci_ctrl_pw$whas, + wsiM_operateD_1$wget, + wsiM_operateD_1$whas, + wsiM_peerIsReady_1$wget, + wsiM_peerIsReady_1$whas, + wsiM_reqFifo_dequeueing$whas, + wsiM_reqFifo_enqueueing$whas, + wsiM_reqFifo_x_wire$whas, + wsiM_sThreadBusy_pw$whas, + wsiS_operateD_1$wget, + wsiS_operateD_1$whas, + wsiS_peerIsReady_1$wget, + wsiS_peerIsReady_1$whas, + wsiS_reqFifo_doResetClr$whas, + wsiS_reqFifo_doResetDeq$whas, + wsiS_reqFifo_doResetEnq$whas, + wsiS_reqFifo_r_clr$whas, + wsiS_reqFifo_r_deq$whas, + wsiS_reqFifo_r_enq$whas, + wsiS_sThreadBusy_dw$wget, + wsiS_sThreadBusy_dw$whas, + wsiS_wsiReq$whas, + wsi_Es_mBurstLength_w$whas, + wsi_Es_mBurstPrecise_w$whas, + wsi_Es_mByteEn_w$whas, + wsi_Es_mCmd_w$whas, + wsi_Es_mDataInfo_w$whas, + wsi_Es_mData_w$whas, + wsi_Es_mReqInfo_w$whas, + wsi_Es_mReqLast_w$whas; + + // register byteCount + reg [31 : 0] byteCount; + wire [31 : 0] byteCount$D_IN; + wire byteCount$EN; + + // register frameGateCtrl + reg [31 : 0] frameGateCtrl; + wire [31 : 0] frameGateCtrl$D_IN; + wire frameGateCtrl$EN; + + // register frameSize + reg [31 : 0] frameSize; + wire [31 : 0] frameSize$D_IN; + wire frameSize$EN; + + // register gateSize + reg [31 : 0] gateSize; + wire [31 : 0] gateSize$D_IN; + wire gateSize$EN; + + // register gated + reg gated; + wire gated$D_IN, gated$EN; + + // register op0MesgCnt + reg [31 : 0] op0MesgCnt; + wire [31 : 0] op0MesgCnt$D_IN; + wire op0MesgCnt$EN; + + // register otherMesgCnt + reg [31 : 0] otherMesgCnt; + wire [31 : 0] otherMesgCnt$D_IN; + wire otherMesgCnt$EN; + + // register wci_cEdge + reg [2 : 0] wci_cEdge; + wire [2 : 0] wci_cEdge$D_IN; + wire wci_cEdge$EN; + + // register wci_cState + reg [2 : 0] wci_cState; + wire [2 : 0] wci_cState$D_IN; + wire wci_cState$EN; + + // register wci_ctlAckReg + reg wci_ctlAckReg; + wire wci_ctlAckReg$D_IN, wci_ctlAckReg$EN; + + // register wci_ctlOpActive + reg wci_ctlOpActive; + wire wci_ctlOpActive$D_IN, wci_ctlOpActive$EN; + + // register wci_illegalEdge + reg wci_illegalEdge; + wire wci_illegalEdge$D_IN, wci_illegalEdge$EN; + + // register wci_isReset_isInReset + reg wci_isReset_isInReset; + wire wci_isReset_isInReset$D_IN, wci_isReset_isInReset$EN; + + // register wci_nState + reg [2 : 0] wci_nState; + reg [2 : 0] wci_nState$D_IN; + wire wci_nState$EN; + + // register wci_reqF_countReg + reg [1 : 0] wci_reqF_countReg; + wire [1 : 0] wci_reqF_countReg$D_IN; + wire wci_reqF_countReg$EN; + + // register wci_respF_c_r + reg [1 : 0] wci_respF_c_r; + wire [1 : 0] wci_respF_c_r$D_IN; + wire wci_respF_c_r$EN; + + // register wci_respF_q_0 + reg [33 : 0] wci_respF_q_0; + reg [33 : 0] wci_respF_q_0$D_IN; + wire wci_respF_q_0$EN; + + // register wci_respF_q_1 + reg [33 : 0] wci_respF_q_1; + reg [33 : 0] wci_respF_q_1$D_IN; + wire wci_respF_q_1$EN; + + // register wci_sFlagReg + reg wci_sFlagReg; + wire wci_sFlagReg$D_IN, wci_sFlagReg$EN; + + // register wci_sThreadBusy_d + reg wci_sThreadBusy_d; + wire wci_sThreadBusy_d$D_IN, wci_sThreadBusy_d$EN; + + // register wsiM_burstKind + reg [1 : 0] wsiM_burstKind; + wire [1 : 0] wsiM_burstKind$D_IN; + wire wsiM_burstKind$EN; + + // register wsiM_errorSticky + reg wsiM_errorSticky; + wire wsiM_errorSticky$D_IN, wsiM_errorSticky$EN; + + // register wsiM_iMesgCount + reg [31 : 0] wsiM_iMesgCount; + wire [31 : 0] wsiM_iMesgCount$D_IN; + wire wsiM_iMesgCount$EN; + + // register wsiM_isReset_isInReset + reg wsiM_isReset_isInReset; + wire wsiM_isReset_isInReset$D_IN, wsiM_isReset_isInReset$EN; + + // register wsiM_operateD + reg wsiM_operateD; + wire wsiM_operateD$D_IN, wsiM_operateD$EN; + + // register wsiM_pMesgCount + reg [31 : 0] wsiM_pMesgCount; + wire [31 : 0] wsiM_pMesgCount$D_IN; + wire wsiM_pMesgCount$EN; + + // register wsiM_peerIsReady + reg wsiM_peerIsReady; + wire wsiM_peerIsReady$D_IN, wsiM_peerIsReady$EN; + + // register wsiM_reqFifo_c_r + reg [1 : 0] wsiM_reqFifo_c_r; + wire [1 : 0] wsiM_reqFifo_c_r$D_IN; + wire wsiM_reqFifo_c_r$EN; + + // register wsiM_reqFifo_q_0 + reg [312 : 0] wsiM_reqFifo_q_0; + reg [312 : 0] wsiM_reqFifo_q_0$D_IN; + wire wsiM_reqFifo_q_0$EN; + + // register wsiM_reqFifo_q_1 + reg [312 : 0] wsiM_reqFifo_q_1; + reg [312 : 0] wsiM_reqFifo_q_1$D_IN; + wire wsiM_reqFifo_q_1$EN; + + // register wsiM_sThreadBusy_d + reg wsiM_sThreadBusy_d; + wire wsiM_sThreadBusy_d$D_IN, wsiM_sThreadBusy_d$EN; + + // register wsiM_statusR + reg [7 : 0] wsiM_statusR; + wire [7 : 0] wsiM_statusR$D_IN; + wire wsiM_statusR$EN; + + // register wsiM_tBusyCount + reg [31 : 0] wsiM_tBusyCount; + wire [31 : 0] wsiM_tBusyCount$D_IN; + wire wsiM_tBusyCount$EN; + + // register wsiM_trafficSticky + reg wsiM_trafficSticky; + wire wsiM_trafficSticky$D_IN, wsiM_trafficSticky$EN; + + // register wsiS_burstKind + reg [1 : 0] wsiS_burstKind; + wire [1 : 0] wsiS_burstKind$D_IN; + wire wsiS_burstKind$EN; + + // register wsiS_errorSticky + reg wsiS_errorSticky; + wire wsiS_errorSticky$D_IN, wsiS_errorSticky$EN; + + // register wsiS_iMesgCount + reg [31 : 0] wsiS_iMesgCount; + wire [31 : 0] wsiS_iMesgCount$D_IN; + wire wsiS_iMesgCount$EN; + + // register wsiS_isReset_isInReset + reg wsiS_isReset_isInReset; + wire wsiS_isReset_isInReset$D_IN, wsiS_isReset_isInReset$EN; + + // register wsiS_mesgWordLength + reg [11 : 0] wsiS_mesgWordLength; + wire [11 : 0] wsiS_mesgWordLength$D_IN; + wire wsiS_mesgWordLength$EN; + + // register wsiS_operateD + reg wsiS_operateD; + wire wsiS_operateD$D_IN, wsiS_operateD$EN; + + // register wsiS_pMesgCount + reg [31 : 0] wsiS_pMesgCount; + wire [31 : 0] wsiS_pMesgCount$D_IN; + wire wsiS_pMesgCount$EN; + + // register wsiS_peerIsReady + reg wsiS_peerIsReady; + wire wsiS_peerIsReady$D_IN, wsiS_peerIsReady$EN; + + // register wsiS_reqFifo_countReg + reg [1 : 0] wsiS_reqFifo_countReg; + wire [1 : 0] wsiS_reqFifo_countReg$D_IN; + wire wsiS_reqFifo_countReg$EN; + + // register wsiS_reqFifo_levelsValid + reg wsiS_reqFifo_levelsValid; + wire wsiS_reqFifo_levelsValid$D_IN, wsiS_reqFifo_levelsValid$EN; + + // register wsiS_statusR + reg [7 : 0] wsiS_statusR; + wire [7 : 0] wsiS_statusR$D_IN; + wire wsiS_statusR$EN; + + // register wsiS_tBusyCount + reg [31 : 0] wsiS_tBusyCount; + wire [31 : 0] wsiS_tBusyCount$D_IN; + wire wsiS_tBusyCount$EN; + + // register wsiS_trafficSticky + reg wsiS_trafficSticky; + wire wsiS_trafficSticky$D_IN, wsiS_trafficSticky$EN; + + // register wsiS_wordCount + reg [11 : 0] wsiS_wordCount; + wire [11 : 0] wsiS_wordCount$D_IN; + wire wsiS_wordCount$EN; + + // ports of submodule wci_reqF + wire [71 : 0] wci_reqF$D_IN, wci_reqF$D_OUT; + wire wci_reqF$CLR, wci_reqF$DEQ, wci_reqF$EMPTY_N, wci_reqF$ENQ; + + // ports of submodule wsiS_reqFifo + wire [312 : 0] wsiS_reqFifo$D_IN, wsiS_reqFifo$D_OUT; + wire wsiS_reqFifo$CLR, + wsiS_reqFifo$DEQ, + wsiS_reqFifo$EMPTY_N, + wsiS_reqFifo$ENQ, + wsiS_reqFifo$FULL_N; + + // rule scheduling signals + wire WILL_FIRE_RL_wci_cfrd, + WILL_FIRE_RL_wci_cfwr, + WILL_FIRE_RL_wci_ctl_op_complete, + WILL_FIRE_RL_wci_ctl_op_start, + WILL_FIRE_RL_wci_ctrl_EiI, + WILL_FIRE_RL_wci_ctrl_IsO, + WILL_FIRE_RL_wci_ctrl_OrE, + WILL_FIRE_RL_wci_respF_both, + WILL_FIRE_RL_wci_respF_decCtr, + WILL_FIRE_RL_wci_respF_incCtr, + WILL_FIRE_RL_wsiM_reqFifo_both, + WILL_FIRE_RL_wsiM_reqFifo_decCtr, + WILL_FIRE_RL_wsiM_reqFifo_deq, + WILL_FIRE_RL_wsiM_reqFifo_incCtr, + WILL_FIRE_RL_wsiS_reqFifo_enq, + WILL_FIRE_RL_wsiS_reqFifo_reset, + WILL_FIRE_RL_wsipass_doMessagePush; + + // inputs to muxes for submodule ports + reg [33 : 0] MUX_wci_respF_q_0$write_1__VAL_2; + wire [312 : 0] MUX_wsiM_reqFifo_q_0$write_1__VAL_1, + MUX_wsiM_reqFifo_q_1$write_1__VAL_1; + wire [33 : 0] MUX_wci_respF_q_0$write_1__VAL_1, + MUX_wci_respF_q_1$write_1__VAL_1, + MUX_wci_respF_x_wire$wset_1__VAL_1, + MUX_wci_respF_x_wire$wset_1__VAL_2; + wire [1 : 0] MUX_wci_respF_c_r$write_1__VAL_1, + MUX_wci_respF_c_r$write_1__VAL_2, + MUX_wsiM_reqFifo_c_r$write_1__VAL_1, + MUX_wsiM_reqFifo_c_r$write_1__VAL_2; + wire MUX_wci_illegalEdge$write_1__SEL_1, + MUX_wci_illegalEdge$write_1__SEL_2, + MUX_wci_illegalEdge$write_1__VAL_2, + MUX_wci_respF_q_0$write_1__SEL_2, + MUX_wci_respF_q_1$write_1__SEL_2, + MUX_wsiM_reqFifo_q_0$write_1__SEL_2, + MUX_wsiM_reqFifo_q_1$write_1__SEL_2; + + // remaining internal signals + reg [63 : 0] v__h11217, v__h3701, v__h3876, v__h4020; + reg [31 : 0] g_data__h10929; + wire [31 : 0] frameGateStatus__h10551, + rdat__h10963, + rdat__h11063, + rdat__h11077, + rdat__h11085, + rdat__h11091, + rdat__h11105, + rdat__h11113, + rdat__h11119, + rdat__h11130, + x__h10327; + wire [15 : 0] x__h10967; + wire NOT_gated_99_05_AND_byteCount_06_EQ_frameSize__ETC___d439, + wsiS_reqFifo_i_notEmpty__92_AND_NOT_frameGateC_ETC___d303; + + // value method wciS0_sResp + assign wciS0_SResp = wci_respF_q_0[33:32] ; + + // value method wciS0_sData + assign wciS0_SData = wci_respF_q_0[31:0] ; + + // value method wciS0_sThreadBusy + assign wciS0_SThreadBusy = + wci_reqF_countReg > 2'd1 || wci_isReset_isInReset ; + + // value method wciS0_sFlag + assign wciS0_SFlag = { 1'd1, wci_sFlagReg } ; + + // value method wsiS0_sThreadBusy + assign wsiS0_SThreadBusy = + !wsiS_sThreadBusy_dw$whas || wsiS_sThreadBusy_dw$wget ; + + // value method wsiS0_sReset_n + assign wsiS0_SReset_n = !wsiS_isReset_isInReset && wsiS_operateD ; + + // value method wsiM0_mCmd + assign wsiM0_MCmd = wsiM_sThreadBusy_d ? 3'd0 : wsiM_reqFifo_q_0[312:310] ; + + // value method wsiM0_mReqLast + assign wsiM0_MReqLast = !wsiM_sThreadBusy_d && wsiM_reqFifo_q_0[309] ; + + // value method wsiM0_mBurstPrecise + assign wsiM0_MBurstPrecise = !wsiM_sThreadBusy_d && wsiM_reqFifo_q_0[308] ; + + // value method wsiM0_mBurstLength + assign wsiM0_MBurstLength = + wsiM_sThreadBusy_d ? 12'd0 : wsiM_reqFifo_q_0[307:296] ; + + // value method wsiM0_mData + assign wsiM0_MData = wsiM_reqFifo_q_0[295:40] ; + + // value method wsiM0_mByteEn + assign wsiM0_MByteEn = wsiM_reqFifo_q_0[39:8] ; + + // value method wsiM0_mReqInfo + assign wsiM0_MReqInfo = wsiM_sThreadBusy_d ? 8'd0 : wsiM_reqFifo_q_0[7:0] ; + + // value method wsiM0_mReset_n + assign wsiM0_MReset_n = !wsiM_isReset_isInReset && wsiM_operateD ; + + // submodule wci_reqF + SizedFIFO #(.p1width(32'd72), + .p2depth(32'd3), + .p3cntr_width(32'd1), + .guarded(32'd1)) wci_reqF(.RST(wciS0_MReset_n), + .CLK(wciS0_Clk), + .D_IN(wci_reqF$D_IN), + .ENQ(wci_reqF$ENQ), + .DEQ(wci_reqF$DEQ), + .CLR(wci_reqF$CLR), + .D_OUT(wci_reqF$D_OUT), + .FULL_N(), + .EMPTY_N(wci_reqF$EMPTY_N)); + + // submodule wsiS_reqFifo + SizedFIFO #(.p1width(32'd313), + .p2depth(32'd3), + .p3cntr_width(32'd1), + .guarded(32'd1)) wsiS_reqFifo(.RST(wciS0_MReset_n), + .CLK(wciS0_Clk), + .D_IN(wsiS_reqFifo$D_IN), + .ENQ(wsiS_reqFifo$ENQ), + .DEQ(wsiS_reqFifo$DEQ), + .CLR(wsiS_reqFifo$CLR), + .D_OUT(wsiS_reqFifo$D_OUT), + .FULL_N(wsiS_reqFifo$FULL_N), + .EMPTY_N(wsiS_reqFifo$EMPTY_N)); + + // rule RL_wci_ctl_op_start + assign WILL_FIRE_RL_wci_ctl_op_start = + wci_reqF$EMPTY_N && wci_wci_ctrl_pw$whas && + !WILL_FIRE_RL_wci_ctl_op_complete ; + + // rule RL_wci_ctrl_IsO + assign WILL_FIRE_RL_wci_ctrl_IsO = + wci_wci_ctrl_pw$whas && WILL_FIRE_RL_wci_ctl_op_start && + wci_cState == 3'd1 && + wci_reqF$D_OUT[36:34] == 3'd1 ; + + // rule RL_wci_ctrl_EiI + assign WILL_FIRE_RL_wci_ctrl_EiI = + wci_wci_ctrl_pw$whas && WILL_FIRE_RL_wci_ctl_op_start && + wci_cState == 3'd0 && + wci_reqF$D_OUT[36:34] == 3'd0 ; + + // rule RL_wci_ctrl_OrE + assign WILL_FIRE_RL_wci_ctrl_OrE = + wci_wci_ctrl_pw$whas && WILL_FIRE_RL_wci_ctl_op_start && + wci_cState == 3'd2 && + wci_reqF$D_OUT[36:34] == 3'd3 ; + + // rule RL_wsipass_doMessagePush + assign WILL_FIRE_RL_wsipass_doMessagePush = + wsiS_reqFifo_i_notEmpty__92_AND_NOT_frameGateC_ETC___d303 && + wci_cState == 3'd2 ; + + // rule RL_wci_cfwr + assign WILL_FIRE_RL_wci_cfwr = + wci_respF_c_r != 2'd2 && wci_reqF$EMPTY_N && + wci_wci_cfwr_pw$whas && + !WILL_FIRE_RL_wci_ctl_op_start && + !WILL_FIRE_RL_wci_ctl_op_complete ; + + // rule RL_wci_ctl_op_complete + assign WILL_FIRE_RL_wci_ctl_op_complete = + wci_respF_c_r != 2'd2 && wci_ctlOpActive && wci_ctlAckReg ; + + // rule RL_wci_cfrd + assign WILL_FIRE_RL_wci_cfrd = + wci_respF_c_r != 2'd2 && wci_reqF$EMPTY_N && + wci_wci_cfrd_pw$whas && + !WILL_FIRE_RL_wci_ctl_op_start && + !WILL_FIRE_RL_wci_ctl_op_complete ; + + // rule RL_wci_respF_incCtr + assign WILL_FIRE_RL_wci_respF_incCtr = + ((wci_respF_c_r == 2'd0) ? + wci_respF_enqueueing$whas : + wci_respF_c_r != 2'd1 || wci_respF_enqueueing$whas) && + wci_respF_enqueueing$whas && + !(wci_respF_c_r != 2'd0) ; + + // rule RL_wci_respF_decCtr + assign WILL_FIRE_RL_wci_respF_decCtr = + wci_respF_c_r != 2'd0 && !wci_respF_enqueueing$whas ; + + // rule RL_wci_respF_both + assign WILL_FIRE_RL_wci_respF_both = + ((wci_respF_c_r == 2'd1) ? + wci_respF_enqueueing$whas : + wci_respF_c_r != 2'd2 || wci_respF_enqueueing$whas) && + wci_respF_c_r != 2'd0 && + wci_respF_enqueueing$whas ; + + // rule RL_wsiM_reqFifo_deq + assign WILL_FIRE_RL_wsiM_reqFifo_deq = + wsiM_reqFifo_c_r != 2'd0 && !wsiM_sThreadBusy_d ; + + // rule RL_wsiM_reqFifo_incCtr + assign WILL_FIRE_RL_wsiM_reqFifo_incCtr = + ((wsiM_reqFifo_c_r == 2'd0) ? + wsiM_reqFifo_enqueueing$whas : + wsiM_reqFifo_c_r != 2'd1 || wsiM_reqFifo_enqueueing$whas) && + wsiM_reqFifo_enqueueing$whas && + !WILL_FIRE_RL_wsiM_reqFifo_deq ; + + // rule RL_wsiM_reqFifo_decCtr + assign WILL_FIRE_RL_wsiM_reqFifo_decCtr = + WILL_FIRE_RL_wsiM_reqFifo_deq && !wsiM_reqFifo_enqueueing$whas ; + + // rule RL_wsiM_reqFifo_both + assign WILL_FIRE_RL_wsiM_reqFifo_both = + ((wsiM_reqFifo_c_r == 2'd1) ? + wsiM_reqFifo_enqueueing$whas : + wsiM_reqFifo_c_r != 2'd2 || wsiM_reqFifo_enqueueing$whas) && + WILL_FIRE_RL_wsiM_reqFifo_deq && + wsiM_reqFifo_enqueueing$whas ; + + // rule RL_wsiS_reqFifo_enq + assign WILL_FIRE_RL_wsiS_reqFifo_enq = + wsiS_reqFifo$FULL_N && wsiS_operateD && wsiS_peerIsReady && + wsiS_wsiReq$wget[312:310] == 3'd1 ; + + // rule RL_wsiS_reqFifo_reset + assign WILL_FIRE_RL_wsiS_reqFifo_reset = + WILL_FIRE_RL_wsiS_reqFifo_enq || + WILL_FIRE_RL_wsipass_doMessagePush ; + + // inputs to muxes for submodule ports + assign MUX_wci_illegalEdge$write_1__SEL_1 = + WILL_FIRE_RL_wci_ctl_op_complete && wci_illegalEdge ; + assign MUX_wci_illegalEdge$write_1__SEL_2 = + WILL_FIRE_RL_wci_ctl_op_start && + (wci_reqF$D_OUT[36:34] == 3'd0 && wci_cState != 3'd0 || + wci_reqF$D_OUT[36:34] == 3'd1 && wci_cState != 3'd1 && + wci_cState != 3'd3 || + wci_reqF$D_OUT[36:34] == 3'd2 && wci_cState != 3'd2 || + wci_reqF$D_OUT[36:34] == 3'd3 && wci_cState != 3'd3 && + wci_cState != 3'd2 && + wci_cState != 3'd1 || + wci_reqF$D_OUT[36:34] == 3'd4 || + wci_reqF$D_OUT[36:34] == 3'd5 || + wci_reqF$D_OUT[36:34] == 3'd6 || + wci_reqF$D_OUT[36:34] == 3'd7) ; + assign MUX_wci_respF_q_0$write_1__SEL_2 = + WILL_FIRE_RL_wci_respF_incCtr && wci_respF_c_r == 2'd0 ; + assign MUX_wci_respF_q_1$write_1__SEL_2 = + WILL_FIRE_RL_wci_respF_incCtr && wci_respF_c_r == 2'd1 ; + assign MUX_wsiM_reqFifo_q_0$write_1__SEL_2 = + WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_c_r == 2'd0 ; + assign MUX_wsiM_reqFifo_q_1$write_1__SEL_2 = + WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_c_r == 2'd1 ; + assign MUX_wci_illegalEdge$write_1__VAL_2 = + wci_reqF$D_OUT[36:34] != 3'd4 && wci_reqF$D_OUT[36:34] != 3'd5 && + wci_reqF$D_OUT[36:34] != 3'd6 ; + assign MUX_wci_respF_c_r$write_1__VAL_1 = wci_respF_c_r + 2'd1 ; + assign MUX_wci_respF_c_r$write_1__VAL_2 = wci_respF_c_r - 2'd1 ; + assign MUX_wci_respF_q_0$write_1__VAL_1 = + (wci_respF_c_r == 2'd1) ? + MUX_wci_respF_q_0$write_1__VAL_2 : + wci_respF_q_1 ; + always@(WILL_FIRE_RL_wci_ctl_op_complete or + MUX_wci_respF_x_wire$wset_1__VAL_1 or + WILL_FIRE_RL_wci_cfrd or + MUX_wci_respF_x_wire$wset_1__VAL_2 or WILL_FIRE_RL_wci_cfwr) + begin + case (1'b1) // synopsys parallel_case + WILL_FIRE_RL_wci_ctl_op_complete: + MUX_wci_respF_q_0$write_1__VAL_2 = + MUX_wci_respF_x_wire$wset_1__VAL_1; + WILL_FIRE_RL_wci_cfrd: + MUX_wci_respF_q_0$write_1__VAL_2 = + MUX_wci_respF_x_wire$wset_1__VAL_2; + WILL_FIRE_RL_wci_cfwr: MUX_wci_respF_q_0$write_1__VAL_2 = 34'h1C0DE4201; + default: MUX_wci_respF_q_0$write_1__VAL_2 = + 34'h2AAAAAAAA /* unspecified value */ ; + endcase + end + assign MUX_wci_respF_q_1$write_1__VAL_1 = + (wci_respF_c_r == 2'd2) ? + MUX_wci_respF_q_0$write_1__VAL_2 : + 34'h0AAAAAAAA ; + assign MUX_wci_respF_x_wire$wset_1__VAL_1 = + wci_illegalEdge ? 34'h3C0DE4202 : 34'h1C0DE4201 ; + assign MUX_wci_respF_x_wire$wset_1__VAL_2 = { 2'd1, g_data__h10929 } ; + assign MUX_wsiM_reqFifo_c_r$write_1__VAL_1 = wsiM_reqFifo_c_r + 2'd1 ; + assign MUX_wsiM_reqFifo_c_r$write_1__VAL_2 = wsiM_reqFifo_c_r - 2'd1 ; + assign MUX_wsiM_reqFifo_q_0$write_1__VAL_1 = + (wsiM_reqFifo_c_r == 2'd1) ? + wsiS_reqFifo$D_OUT : + wsiM_reqFifo_q_1 ; + assign MUX_wsiM_reqFifo_q_1$write_1__VAL_1 = + (wsiM_reqFifo_c_r == 2'd2) ? + wsiS_reqFifo$D_OUT : + 313'h00000AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA00 ; + + // inlined wires + assign wci_wciReq$wget = + { wciS0_MCmd, + wciS0_MAddrSpace, + wciS0_MByteEn, + wciS0_MAddr, + wciS0_MData } ; + assign wci_wciReq$whas = 1'd1 ; + assign wci_respF_x_wire$wget = MUX_wci_respF_q_0$write_1__VAL_2 ; + assign wci_respF_x_wire$whas = wci_respF_enqueueing$whas ; + assign wci_wEdge$wget = wci_reqF$D_OUT[36:34] ; + assign wci_wEdge$whas = WILL_FIRE_RL_wci_ctl_op_start ; + assign wci_sFlagReg_1$wget = 1'b0 ; + assign wci_sFlagReg_1$whas = 1'b0 ; + assign wci_ctlAckReg_1$wget = 1'd1 ; + assign wci_ctlAckReg_1$whas = + WILL_FIRE_RL_wci_ctrl_OrE || WILL_FIRE_RL_wci_ctrl_IsO || + WILL_FIRE_RL_wci_ctrl_EiI ; + assign wsiS_wsiReq$wget = + { wsiS0_MCmd, + wsiS0_MReqLast, + wsiS0_MBurstPrecise, + wsiS0_MBurstLength, + wsiS0_MData, + wsiS0_MByteEn, + wsiS0_MReqInfo } ; + assign wsiS_wsiReq$whas = 1'd1 ; + assign wsiS_operateD_1$wget = 1'd1 ; + assign wsiS_operateD_1$whas = wci_cState == 3'd2 ; + assign wsiS_peerIsReady_1$wget = 1'd1 ; + assign wsiS_peerIsReady_1$whas = wsiS0_MReset_n ; + assign wsiS_sThreadBusy_dw$wget = wsiS_reqFifo_countReg > 2'd1 ; + assign wsiS_sThreadBusy_dw$whas = + wsiS_reqFifo_levelsValid && wsiS_operateD && wsiS_peerIsReady ; + assign wsiM_reqFifo_x_wire$wget = wsiS_reqFifo$D_OUT ; + assign wsiM_reqFifo_x_wire$whas = wsiM_reqFifo_enqueueing$whas ; + assign wsiM_operateD_1$wget = 1'd1 ; + assign wsiM_operateD_1$whas = wci_cState == 3'd2 ; + assign wsiM_peerIsReady_1$wget = 1'd1 ; + assign wsiM_peerIsReady_1$whas = wsiM0_SReset_n ; + assign wci_Es_mCmd_w$wget = wciS0_MCmd ; + assign wci_Es_mCmd_w$whas = 1'd1 ; + assign wci_Es_mAddrSpace_w$wget = wciS0_MAddrSpace ; + assign wci_Es_mAddrSpace_w$whas = 1'd1 ; + assign wci_Es_mByteEn_w$wget = wciS0_MByteEn ; + assign wci_Es_mByteEn_w$whas = 1'd1 ; + assign wci_Es_mAddr_w$wget = wciS0_MAddr ; + assign wci_Es_mAddr_w$whas = 1'd1 ; + assign wci_Es_mData_w$wget = wciS0_MData ; + assign wci_Es_mData_w$whas = 1'd1 ; + assign wsi_Es_mCmd_w$wget = wsiS0_MCmd ; + assign wsi_Es_mCmd_w$whas = 1'd1 ; + assign wsi_Es_mBurstLength_w$wget = wsiS0_MBurstLength ; + assign wsi_Es_mBurstLength_w$whas = 1'd1 ; + assign wsi_Es_mData_w$wget = wsiS0_MData ; + assign wsi_Es_mData_w$whas = 1'd1 ; + assign wsi_Es_mByteEn_w$wget = wsiS0_MByteEn ; + assign wsi_Es_mByteEn_w$whas = 1'd1 ; + assign wsi_Es_mReqInfo_w$wget = wsiS0_MReqInfo ; + assign wsi_Es_mReqInfo_w$whas = 1'd1 ; + assign wci_reqF_r_enq$whas = wci_wciReq$wget[71:69] != 3'd0 ; + assign wci_reqF_r_deq$whas = + WILL_FIRE_RL_wci_ctl_op_start || WILL_FIRE_RL_wci_cfrd || + WILL_FIRE_RL_wci_cfwr ; + assign wci_reqF_r_clr$whas = 1'b0 ; + assign wci_respF_enqueueing$whas = + WILL_FIRE_RL_wci_ctl_op_complete || WILL_FIRE_RL_wci_cfrd || + WILL_FIRE_RL_wci_cfwr ; + assign wci_respF_dequeueing$whas = wci_respF_c_r != 2'd0 ; + assign wci_sThreadBusy_pw$whas = 1'b0 ; + assign wci_wci_cfwr_pw$whas = + wci_reqF$EMPTY_N && wci_reqF$D_OUT[68] && + wci_reqF$D_OUT[71:69] == 3'd1 ; + assign wci_wci_cfrd_pw$whas = + wci_reqF$EMPTY_N && wci_reqF$D_OUT[68] && + wci_reqF$D_OUT[71:69] == 3'd2 ; + assign wci_wci_ctrl_pw$whas = + wci_reqF$EMPTY_N && !wci_reqF$D_OUT[68] && + wci_reqF$D_OUT[71:69] == 3'd2 ; + assign wsiS_reqFifo_r_enq$whas = WILL_FIRE_RL_wsiS_reqFifo_enq ; + assign wsiS_reqFifo_r_deq$whas = WILL_FIRE_RL_wsipass_doMessagePush ; + assign wsiS_reqFifo_r_clr$whas = 1'b0 ; + assign wsiS_reqFifo_doResetEnq$whas = WILL_FIRE_RL_wsiS_reqFifo_enq ; + assign wsiS_reqFifo_doResetDeq$whas = WILL_FIRE_RL_wsipass_doMessagePush ; + assign wsiS_reqFifo_doResetClr$whas = 1'b0 ; + assign wsiM_reqFifo_enqueueing$whas = + WILL_FIRE_RL_wsipass_doMessagePush && + (frameGateCtrl[3:0] == 4'h0 || + frameGateCtrl[3:0] == 4'h1 && !gated) ; + assign wsiM_reqFifo_dequeueing$whas = WILL_FIRE_RL_wsiM_reqFifo_deq ; + assign wsiM_sThreadBusy_pw$whas = wsiM0_SThreadBusy ; + assign wsi_Es_mReqLast_w$whas = wsiS0_MReqLast ; + assign wsi_Es_mBurstPrecise_w$whas = wsiS0_MBurstPrecise ; + assign wsi_Es_mDataInfo_w$whas = 1'd1 ; + assign wsiS_extStatusW$wget = + { wsiS_pMesgCount, wsiS_iMesgCount, wsiS_tBusyCount } ; + assign wsiM_extStatusW$wget = + { wsiM_pMesgCount, wsiM_iMesgCount, wsiM_tBusyCount } ; + + // register byteCount + assign byteCount$D_IN = + NOT_gated_99_05_AND_byteCount_06_EQ_frameSize__ETC___d439 ? + 32'd32 : + x__h10327 ; + assign byteCount$EN = WILL_FIRE_RL_wsipass_doMessagePush ; + + // register frameGateCtrl + assign frameGateCtrl$D_IN = wci_reqF$D_OUT[31:0] ; + assign frameGateCtrl$EN = + WILL_FIRE_RL_wci_cfwr && wci_reqF$D_OUT[63:32] == 32'h00000004 ; + + // register frameSize + assign frameSize$D_IN = wci_reqF$D_OUT[31:0] ; + assign frameSize$EN = + WILL_FIRE_RL_wci_cfwr && wci_reqF$D_OUT[63:32] == 32'h00000008 ; + + // register gateSize + assign gateSize$D_IN = wci_reqF$D_OUT[31:0] ; + assign gateSize$EN = + WILL_FIRE_RL_wci_cfwr && wci_reqF$D_OUT[63:32] == 32'h0000000C ; + + // register gated + assign gated$D_IN = !gated && byteCount == frameSize ; + assign gated$EN = + WILL_FIRE_RL_wsipass_doMessagePush && + NOT_gated_99_05_AND_byteCount_06_EQ_frameSize__ETC___d439 ; + + // register op0MesgCnt + assign op0MesgCnt$D_IN = 32'h0 ; + assign op0MesgCnt$EN = 1'b0 ; + + // register otherMesgCnt + assign otherMesgCnt$D_IN = 32'h0 ; + assign otherMesgCnt$EN = 1'b0 ; + + // register wci_cEdge + assign wci_cEdge$D_IN = wci_reqF$D_OUT[36:34] ; + assign wci_cEdge$EN = WILL_FIRE_RL_wci_ctl_op_start ; + + // register wci_cState + assign wci_cState$D_IN = wci_nState ; + assign wci_cState$EN = + WILL_FIRE_RL_wci_ctl_op_complete && !wci_illegalEdge ; + + // register wci_ctlAckReg + assign wci_ctlAckReg$D_IN = wci_ctlAckReg_1$whas ; + assign wci_ctlAckReg$EN = 1'd1 ; + + // register wci_ctlOpActive + assign wci_ctlOpActive$D_IN = !WILL_FIRE_RL_wci_ctl_op_complete ; + assign wci_ctlOpActive$EN = + WILL_FIRE_RL_wci_ctl_op_complete || + WILL_FIRE_RL_wci_ctl_op_start ; + + // register wci_illegalEdge + assign wci_illegalEdge$D_IN = + !MUX_wci_illegalEdge$write_1__SEL_1 && + MUX_wci_illegalEdge$write_1__VAL_2 ; + assign wci_illegalEdge$EN = + WILL_FIRE_RL_wci_ctl_op_complete && wci_illegalEdge || + MUX_wci_illegalEdge$write_1__SEL_2 ; + + // register wci_isReset_isInReset + assign wci_isReset_isInReset$D_IN = 1'd0 ; + assign wci_isReset_isInReset$EN = wci_isReset_isInReset ; + + // register wci_nState + always@(wci_reqF$D_OUT) + begin + case (wci_reqF$D_OUT[36:34]) + 3'd0: wci_nState$D_IN = 3'd1; + 3'd1: wci_nState$D_IN = 3'd2; + 3'd2: wci_nState$D_IN = 3'd3; + default: wci_nState$D_IN = 3'd0; + endcase + end + assign wci_nState$EN = + WILL_FIRE_RL_wci_ctl_op_start && + (wci_reqF$D_OUT[36:34] == 3'd0 && wci_cState == 3'd0 || + wci_reqF$D_OUT[36:34] == 3'd1 && + (wci_cState == 3'd1 || wci_cState == 3'd3) || + wci_reqF$D_OUT[36:34] == 3'd2 && wci_cState == 3'd2 || + wci_reqF$D_OUT[36:34] == 3'd3 && + (wci_cState == 3'd3 || wci_cState == 3'd2 || + wci_cState == 3'd1)) ; + + // register wci_reqF_countReg + assign wci_reqF_countReg$D_IN = + (wci_wciReq$wget[71:69] != 3'd0) ? + wci_reqF_countReg + 2'd1 : + wci_reqF_countReg - 2'd1 ; + assign wci_reqF_countReg$EN = + (wci_wciReq$wget[71:69] != 3'd0) != wci_reqF_r_deq$whas ; + + // register wci_respF_c_r + assign wci_respF_c_r$D_IN = + WILL_FIRE_RL_wci_respF_incCtr ? + MUX_wci_respF_c_r$write_1__VAL_1 : + MUX_wci_respF_c_r$write_1__VAL_2 ; + assign wci_respF_c_r$EN = + WILL_FIRE_RL_wci_respF_incCtr || WILL_FIRE_RL_wci_respF_decCtr ; + + // register wci_respF_q_0 + always@(WILL_FIRE_RL_wci_respF_both or + MUX_wci_respF_q_0$write_1__VAL_1 or + MUX_wci_respF_q_0$write_1__SEL_2 or + MUX_wci_respF_q_0$write_1__VAL_2 or + WILL_FIRE_RL_wci_respF_decCtr or wci_respF_q_1) + begin + case (1'b1) // synopsys parallel_case + WILL_FIRE_RL_wci_respF_both: + wci_respF_q_0$D_IN = MUX_wci_respF_q_0$write_1__VAL_1; + MUX_wci_respF_q_0$write_1__SEL_2: + wci_respF_q_0$D_IN = MUX_wci_respF_q_0$write_1__VAL_2; + WILL_FIRE_RL_wci_respF_decCtr: wci_respF_q_0$D_IN = wci_respF_q_1; + default: wci_respF_q_0$D_IN = 34'h2AAAAAAAA /* unspecified value */ ; + endcase + end + assign wci_respF_q_0$EN = + WILL_FIRE_RL_wci_respF_both || + WILL_FIRE_RL_wci_respF_incCtr && wci_respF_c_r == 2'd0 || + WILL_FIRE_RL_wci_respF_decCtr ; + + // register wci_respF_q_1 + always@(WILL_FIRE_RL_wci_respF_both or + MUX_wci_respF_q_1$write_1__VAL_1 or + MUX_wci_respF_q_1$write_1__SEL_2 or + MUX_wci_respF_q_0$write_1__VAL_2 or WILL_FIRE_RL_wci_respF_decCtr) + begin + case (1'b1) // synopsys parallel_case + WILL_FIRE_RL_wci_respF_both: + wci_respF_q_1$D_IN = MUX_wci_respF_q_1$write_1__VAL_1; + MUX_wci_respF_q_1$write_1__SEL_2: + wci_respF_q_1$D_IN = MUX_wci_respF_q_0$write_1__VAL_2; + WILL_FIRE_RL_wci_respF_decCtr: wci_respF_q_1$D_IN = 34'h0AAAAAAAA; + default: wci_respF_q_1$D_IN = 34'h2AAAAAAAA /* unspecified value */ ; + endcase + end + assign wci_respF_q_1$EN = + WILL_FIRE_RL_wci_respF_both || + WILL_FIRE_RL_wci_respF_incCtr && wci_respF_c_r == 2'd1 || + WILL_FIRE_RL_wci_respF_decCtr ; + + // register wci_sFlagReg + assign wci_sFlagReg$D_IN = 1'b0 ; + assign wci_sFlagReg$EN = 1'd1 ; + + // register wci_sThreadBusy_d + assign wci_sThreadBusy_d$D_IN = 1'b0 ; + assign wci_sThreadBusy_d$EN = 1'd1 ; + + // register wsiM_burstKind + assign wsiM_burstKind$D_IN = + (wsiM_burstKind == 2'd0) ? + (wsiM_reqFifo_q_0[308] ? 2'd1 : 2'd2) : + 2'd0 ; + assign wsiM_burstKind$EN = + WILL_FIRE_RL_wsiM_reqFifo_deq && + wsiM_reqFifo_q_0[312:310] == 3'd1 && + (wsiM_burstKind == 2'd0 || + (wsiM_burstKind == 2'd1 || wsiM_burstKind == 2'd2) && + wsiM_reqFifo_q_0[309]) ; + + // register wsiM_errorSticky + assign wsiM_errorSticky$D_IN = 1'b0 ; + assign wsiM_errorSticky$EN = 1'b0 ; + + // register wsiM_iMesgCount + assign wsiM_iMesgCount$D_IN = wsiM_iMesgCount + 32'd1 ; + assign wsiM_iMesgCount$EN = + WILL_FIRE_RL_wsiM_reqFifo_deq && + wsiM_reqFifo_q_0[312:310] == 3'd1 && + wsiM_burstKind == 2'd2 && + wsiM_reqFifo_q_0[309] ; + + // register wsiM_isReset_isInReset + assign wsiM_isReset_isInReset$D_IN = 1'd0 ; + assign wsiM_isReset_isInReset$EN = wsiM_isReset_isInReset ; + + // register wsiM_operateD + assign wsiM_operateD$D_IN = wci_cState == 3'd2 ; + assign wsiM_operateD$EN = 1'd1 ; + + // register wsiM_pMesgCount + assign wsiM_pMesgCount$D_IN = wsiM_pMesgCount + 32'd1 ; + assign wsiM_pMesgCount$EN = + WILL_FIRE_RL_wsiM_reqFifo_deq && + wsiM_reqFifo_q_0[312:310] == 3'd1 && + wsiM_burstKind == 2'd1 && + wsiM_reqFifo_q_0[309] ; + + // register wsiM_peerIsReady + assign wsiM_peerIsReady$D_IN = wsiM0_SReset_n ; + assign wsiM_peerIsReady$EN = 1'd1 ; + + // register wsiM_reqFifo_c_r + assign wsiM_reqFifo_c_r$D_IN = + WILL_FIRE_RL_wsiM_reqFifo_incCtr ? + MUX_wsiM_reqFifo_c_r$write_1__VAL_1 : + MUX_wsiM_reqFifo_c_r$write_1__VAL_2 ; + assign wsiM_reqFifo_c_r$EN = + WILL_FIRE_RL_wsiM_reqFifo_incCtr || + WILL_FIRE_RL_wsiM_reqFifo_decCtr ; + + // register wsiM_reqFifo_q_0 + always@(WILL_FIRE_RL_wsiM_reqFifo_both or + MUX_wsiM_reqFifo_q_0$write_1__VAL_1 or + MUX_wsiM_reqFifo_q_0$write_1__SEL_2 or + wsiS_reqFifo$D_OUT or + WILL_FIRE_RL_wsiM_reqFifo_decCtr or wsiM_reqFifo_q_1) + begin + case (1'b1) // synopsys parallel_case + WILL_FIRE_RL_wsiM_reqFifo_both: + wsiM_reqFifo_q_0$D_IN = MUX_wsiM_reqFifo_q_0$write_1__VAL_1; + MUX_wsiM_reqFifo_q_0$write_1__SEL_2: + wsiM_reqFifo_q_0$D_IN = wsiS_reqFifo$D_OUT; + WILL_FIRE_RL_wsiM_reqFifo_decCtr: + wsiM_reqFifo_q_0$D_IN = wsiM_reqFifo_q_1; + default: wsiM_reqFifo_q_0$D_IN = + 313'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ; + endcase + end + assign wsiM_reqFifo_q_0$EN = + WILL_FIRE_RL_wsiM_reqFifo_both || + WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_c_r == 2'd0 || + WILL_FIRE_RL_wsiM_reqFifo_decCtr ; + + // register wsiM_reqFifo_q_1 + always@(WILL_FIRE_RL_wsiM_reqFifo_both or + MUX_wsiM_reqFifo_q_1$write_1__VAL_1 or + MUX_wsiM_reqFifo_q_1$write_1__SEL_2 or + wsiS_reqFifo$D_OUT or WILL_FIRE_RL_wsiM_reqFifo_decCtr) + begin + case (1'b1) // synopsys parallel_case + WILL_FIRE_RL_wsiM_reqFifo_both: + wsiM_reqFifo_q_1$D_IN = MUX_wsiM_reqFifo_q_1$write_1__VAL_1; + MUX_wsiM_reqFifo_q_1$write_1__SEL_2: + wsiM_reqFifo_q_1$D_IN = wsiS_reqFifo$D_OUT; + WILL_FIRE_RL_wsiM_reqFifo_decCtr: + wsiM_reqFifo_q_1$D_IN = + 313'h00000AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA00; + default: wsiM_reqFifo_q_1$D_IN = + 313'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ; + endcase + end + assign wsiM_reqFifo_q_1$EN = + WILL_FIRE_RL_wsiM_reqFifo_both || + WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_c_r == 2'd1 || + WILL_FIRE_RL_wsiM_reqFifo_decCtr ; + + // register wsiM_sThreadBusy_d + assign wsiM_sThreadBusy_d$D_IN = wsiM0_SThreadBusy ; + assign wsiM_sThreadBusy_d$EN = 1'd1 ; + + // register wsiM_statusR + assign wsiM_statusR$D_IN = + { wsiM_isReset_isInReset, + !wsiM_peerIsReady, + !wsiM_operateD, + wsiM_errorSticky, + wsiM_burstKind != 2'd0, + wsiM_sThreadBusy_d, + 1'd0, + wsiM_trafficSticky } ; + assign wsiM_statusR$EN = 1'd1 ; + + // register wsiM_tBusyCount + assign wsiM_tBusyCount$D_IN = wsiM_tBusyCount + 32'd1 ; + assign wsiM_tBusyCount$EN = + wsiM_operateD && wsiM_peerIsReady && wsiM_sThreadBusy_d ; + + // register wsiM_trafficSticky + assign wsiM_trafficSticky$D_IN = 1'd1 ; + assign wsiM_trafficSticky$EN = + WILL_FIRE_RL_wsiM_reqFifo_deq && + wsiM_reqFifo_q_0[312:310] == 3'd1 ; + + // register wsiS_burstKind + assign wsiS_burstKind$D_IN = + (wsiS_burstKind == 2'd0) ? + (wsiS_wsiReq$wget[308] ? 2'd1 : 2'd2) : + 2'd0 ; + assign wsiS_burstKind$EN = + WILL_FIRE_RL_wsiS_reqFifo_enq && + (wsiS_burstKind == 2'd0 || + (wsiS_burstKind == 2'd1 || wsiS_burstKind == 2'd2) && + wsiS_wsiReq$wget[309]) ; + + // register wsiS_errorSticky + assign wsiS_errorSticky$D_IN = 1'b0 ; + assign wsiS_errorSticky$EN = 1'b0 ; + + // register wsiS_iMesgCount + assign wsiS_iMesgCount$D_IN = wsiS_iMesgCount + 32'd1 ; + assign wsiS_iMesgCount$EN = + WILL_FIRE_RL_wsiS_reqFifo_enq && wsiS_burstKind == 2'd2 && + wsiS_wsiReq$wget[309] ; + + // register wsiS_isReset_isInReset + assign wsiS_isReset_isInReset$D_IN = 1'd0 ; + assign wsiS_isReset_isInReset$EN = wsiS_isReset_isInReset ; + + // register wsiS_mesgWordLength + assign wsiS_mesgWordLength$D_IN = wsiS_wordCount ; + assign wsiS_mesgWordLength$EN = + WILL_FIRE_RL_wsiS_reqFifo_enq && wsiS_wsiReq$wget[309] ; + + // register wsiS_operateD + assign wsiS_operateD$D_IN = wci_cState == 3'd2 ; + assign wsiS_operateD$EN = 1'd1 ; + + // register wsiS_pMesgCount + assign wsiS_pMesgCount$D_IN = wsiS_pMesgCount + 32'd1 ; + assign wsiS_pMesgCount$EN = + WILL_FIRE_RL_wsiS_reqFifo_enq && wsiS_burstKind == 2'd1 && + wsiS_wsiReq$wget[309] ; + + // register wsiS_peerIsReady + assign wsiS_peerIsReady$D_IN = wsiS0_MReset_n ; + assign wsiS_peerIsReady$EN = 1'd1 ; + + // register wsiS_reqFifo_countReg + assign wsiS_reqFifo_countReg$D_IN = + WILL_FIRE_RL_wsiS_reqFifo_enq ? + wsiS_reqFifo_countReg + 2'd1 : + wsiS_reqFifo_countReg - 2'd1 ; + assign wsiS_reqFifo_countReg$EN = + WILL_FIRE_RL_wsiS_reqFifo_enq != + WILL_FIRE_RL_wsipass_doMessagePush ; + + // register wsiS_reqFifo_levelsValid + assign wsiS_reqFifo_levelsValid$D_IN = WILL_FIRE_RL_wsiS_reqFifo_reset ; + assign wsiS_reqFifo_levelsValid$EN = + WILL_FIRE_RL_wsipass_doMessagePush || + WILL_FIRE_RL_wsiS_reqFifo_enq || + WILL_FIRE_RL_wsiS_reqFifo_reset ; + + // register wsiS_statusR + assign wsiS_statusR$D_IN = + { wsiS_isReset_isInReset, + !wsiS_peerIsReady, + !wsiS_operateD, + wsiS_errorSticky, + wsiS_burstKind != 2'd0, + !wsiS_sThreadBusy_dw$whas || wsiS_sThreadBusy_dw$wget, + 1'd0, + wsiS_trafficSticky } ; + assign wsiS_statusR$EN = 1'd1 ; + + // register wsiS_tBusyCount + assign wsiS_tBusyCount$D_IN = wsiS_tBusyCount + 32'd1 ; + assign wsiS_tBusyCount$EN = + wsiS_operateD && wsiS_peerIsReady && + (!wsiS_sThreadBusy_dw$whas || wsiS_sThreadBusy_dw$wget) ; + + // register wsiS_trafficSticky + assign wsiS_trafficSticky$D_IN = 1'd1 ; + assign wsiS_trafficSticky$EN = WILL_FIRE_RL_wsiS_reqFifo_enq ; + + // register wsiS_wordCount + assign wsiS_wordCount$D_IN = + wsiS_wsiReq$wget[309] ? 12'd1 : wsiS_wordCount + 12'd1 ; + assign wsiS_wordCount$EN = WILL_FIRE_RL_wsiS_reqFifo_enq ; + + // submodule wci_reqF + assign wci_reqF$D_IN = wci_wciReq$wget ; + assign wci_reqF$ENQ = wci_wciReq$wget[71:69] != 3'd0 ; + assign wci_reqF$DEQ = wci_reqF_r_deq$whas ; + assign wci_reqF$CLR = 1'b0 ; + + // submodule wsiS_reqFifo + assign wsiS_reqFifo$D_IN = wsiS_wsiReq$wget ; + assign wsiS_reqFifo$ENQ = WILL_FIRE_RL_wsiS_reqFifo_enq ; + assign wsiS_reqFifo$DEQ = WILL_FIRE_RL_wsipass_doMessagePush ; + assign wsiS_reqFifo$CLR = 1'b0 ; + + // remaining internal signals + assign NOT_gated_99_05_AND_byteCount_06_EQ_frameSize__ETC___d439 = + !gated && byteCount == frameSize || + gated && byteCount == gateSize ; + assign frameGateStatus__h10551 = { 31'd0, hasDebugLogic } ; + assign rdat__h10963 = hasDebugLogic ? { 16'd0, x__h10967 } : 32'd0 ; + assign rdat__h11063 = hasDebugLogic ? wsiS_extStatusW$wget[95:64] : 32'd0 ; + assign rdat__h11077 = hasDebugLogic ? wsiS_extStatusW$wget[63:32] : 32'd0 ; + assign rdat__h11085 = hasDebugLogic ? wsiS_extStatusW$wget[31:0] : 32'd0 ; + assign rdat__h11091 = hasDebugLogic ? wsiM_extStatusW$wget[95:64] : 32'd0 ; + assign rdat__h11105 = hasDebugLogic ? wsiM_extStatusW$wget[63:32] : 32'd0 ; + assign rdat__h11113 = hasDebugLogic ? wsiM_extStatusW$wget[31:0] : 32'd0 ; + assign rdat__h11119 = hasDebugLogic ? op0MesgCnt : 32'd0 ; + assign rdat__h11130 = hasDebugLogic ? otherMesgCnt : 32'd0 ; + assign wsiS_reqFifo_i_notEmpty__92_AND_NOT_frameGateC_ETC___d303 = + wsiS_reqFifo$EMPTY_N && + (frameGateCtrl[3:0] != 4'h0 && + (frameGateCtrl[3:0] != 4'h1 || gated) || + wsiM_reqFifo_c_r != 2'd2) ; + assign x__h10327 = byteCount + 32'd32 ; + assign x__h10967 = { wsiS_statusR, wsiM_statusR } ; + always@(wci_reqF$D_OUT or + frameGateStatus__h10551 or + frameGateCtrl or + frameSize or + gateSize or + rdat__h10963 or + rdat__h11063 or + rdat__h11077 or + rdat__h11085 or + rdat__h11091 or + rdat__h11105 or rdat__h11113 or rdat__h11119 or rdat__h11130) + begin + case (wci_reqF$D_OUT[63:32]) + 32'h0: g_data__h10929 = frameGateStatus__h10551; + 32'h00000004: g_data__h10929 = frameGateCtrl; + 32'h00000008: g_data__h10929 = frameSize; + 32'h0000000C: g_data__h10929 = gateSize; + 32'h00000010: g_data__h10929 = rdat__h10963; + 32'h00000014: g_data__h10929 = rdat__h11063; + 32'h00000018: g_data__h10929 = rdat__h11077; + 32'h0000001C: g_data__h10929 = rdat__h11085; + 32'h00000020: g_data__h10929 = rdat__h11091; + 32'h00000024: g_data__h10929 = rdat__h11105; + 32'h00000028: g_data__h10929 = rdat__h11113; + 32'h0000002C: g_data__h10929 = rdat__h11119; + 32'h00000030: g_data__h10929 = rdat__h11130; + default: g_data__h10929 = 32'd0; + endcase + end + + // handling of inlined registers + + always@(posedge wciS0_Clk) + begin + if (wciS0_MReset_n == `BSV_RESET_VALUE) + begin + byteCount <= `BSV_ASSIGNMENT_DELAY 32'd32; + frameGateCtrl <= `BSV_ASSIGNMENT_DELAY fgCtrlInit; + frameSize <= `BSV_ASSIGNMENT_DELAY 32'd0; + gateSize <= `BSV_ASSIGNMENT_DELAY 32'd0; + gated <= `BSV_ASSIGNMENT_DELAY 1'd0; + op0MesgCnt <= `BSV_ASSIGNMENT_DELAY 32'd0; + otherMesgCnt <= `BSV_ASSIGNMENT_DELAY 32'd0; + wci_cEdge <= `BSV_ASSIGNMENT_DELAY 3'h2; + wci_cState <= `BSV_ASSIGNMENT_DELAY 3'd0; + wci_ctlAckReg <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_ctlOpActive <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_illegalEdge <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_nState <= `BSV_ASSIGNMENT_DELAY 3'd0; + wci_reqF_countReg <= `BSV_ASSIGNMENT_DELAY 2'd0; + wci_respF_c_r <= `BSV_ASSIGNMENT_DELAY 2'd0; + wci_respF_q_0 <= `BSV_ASSIGNMENT_DELAY 34'h0AAAAAAAA; + wci_respF_q_1 <= `BSV_ASSIGNMENT_DELAY 34'h0AAAAAAAA; + wci_sFlagReg <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY 1'd1; + wsiM_burstKind <= `BSV_ASSIGNMENT_DELAY 2'd0; + wsiM_errorSticky <= `BSV_ASSIGNMENT_DELAY 1'd0; + wsiM_iMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0; + wsiM_operateD <= `BSV_ASSIGNMENT_DELAY 1'd0; + wsiM_pMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0; + wsiM_peerIsReady <= `BSV_ASSIGNMENT_DELAY 1'd0; + wsiM_reqFifo_c_r <= `BSV_ASSIGNMENT_DELAY 2'd0; + wsiM_reqFifo_q_0 <= `BSV_ASSIGNMENT_DELAY + 313'h00000AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA00; + wsiM_reqFifo_q_1 <= `BSV_ASSIGNMENT_DELAY + 313'h00000AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA00; + wsiM_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY 1'd1; + wsiM_tBusyCount <= `BSV_ASSIGNMENT_DELAY 32'd0; + wsiM_trafficSticky <= `BSV_ASSIGNMENT_DELAY 1'd0; + wsiS_burstKind <= `BSV_ASSIGNMENT_DELAY 2'd0; + wsiS_errorSticky <= `BSV_ASSIGNMENT_DELAY 1'd0; + wsiS_iMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0; + wsiS_operateD <= `BSV_ASSIGNMENT_DELAY 1'd0; + wsiS_pMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0; + wsiS_peerIsReady <= `BSV_ASSIGNMENT_DELAY 1'd0; + wsiS_reqFifo_countReg <= `BSV_ASSIGNMENT_DELAY 2'd0; + wsiS_reqFifo_levelsValid <= `BSV_ASSIGNMENT_DELAY 1'd1; + wsiS_tBusyCount <= `BSV_ASSIGNMENT_DELAY 32'd0; + wsiS_trafficSticky <= `BSV_ASSIGNMENT_DELAY 1'd0; + wsiS_wordCount <= `BSV_ASSIGNMENT_DELAY 12'd1; + end + else + begin + if (byteCount$EN) byteCount <= `BSV_ASSIGNMENT_DELAY byteCount$D_IN; + if (frameGateCtrl$EN) + frameGateCtrl <= `BSV_ASSIGNMENT_DELAY frameGateCtrl$D_IN; + if (frameSize$EN) frameSize <= `BSV_ASSIGNMENT_DELAY frameSize$D_IN; + if (gateSize$EN) gateSize <= `BSV_ASSIGNMENT_DELAY gateSize$D_IN; + if (gated$EN) gated <= `BSV_ASSIGNMENT_DELAY gated$D_IN; + if (op0MesgCnt$EN) + op0MesgCnt <= `BSV_ASSIGNMENT_DELAY op0MesgCnt$D_IN; + if (otherMesgCnt$EN) + otherMesgCnt <= `BSV_ASSIGNMENT_DELAY otherMesgCnt$D_IN; + if (wci_cEdge$EN) wci_cEdge <= `BSV_ASSIGNMENT_DELAY wci_cEdge$D_IN; + if (wci_cState$EN) + wci_cState <= `BSV_ASSIGNMENT_DELAY wci_cState$D_IN; + if (wci_ctlAckReg$EN) + wci_ctlAckReg <= `BSV_ASSIGNMENT_DELAY wci_ctlAckReg$D_IN; + if (wci_ctlOpActive$EN) + wci_ctlOpActive <= `BSV_ASSIGNMENT_DELAY wci_ctlOpActive$D_IN; + if (wci_illegalEdge$EN) + wci_illegalEdge <= `BSV_ASSIGNMENT_DELAY wci_illegalEdge$D_IN; + if (wci_nState$EN) + wci_nState <= `BSV_ASSIGNMENT_DELAY wci_nState$D_IN; + if (wci_reqF_countReg$EN) + wci_reqF_countReg <= `BSV_ASSIGNMENT_DELAY wci_reqF_countReg$D_IN; + if (wci_respF_c_r$EN) + wci_respF_c_r <= `BSV_ASSIGNMENT_DELAY wci_respF_c_r$D_IN; + if (wci_respF_q_0$EN) + wci_respF_q_0 <= `BSV_ASSIGNMENT_DELAY wci_respF_q_0$D_IN; + if (wci_respF_q_1$EN) + wci_respF_q_1 <= `BSV_ASSIGNMENT_DELAY wci_respF_q_1$D_IN; + if (wci_sFlagReg$EN) + wci_sFlagReg <= `BSV_ASSIGNMENT_DELAY wci_sFlagReg$D_IN; + if (wci_sThreadBusy_d$EN) + wci_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY wci_sThreadBusy_d$D_IN; + if (wsiM_burstKind$EN) + wsiM_burstKind <= `BSV_ASSIGNMENT_DELAY wsiM_burstKind$D_IN; + if (wsiM_errorSticky$EN) + wsiM_errorSticky <= `BSV_ASSIGNMENT_DELAY wsiM_errorSticky$D_IN; + if (wsiM_iMesgCount$EN) + wsiM_iMesgCount <= `BSV_ASSIGNMENT_DELAY wsiM_iMesgCount$D_IN; + if (wsiM_operateD$EN) + wsiM_operateD <= `BSV_ASSIGNMENT_DELAY wsiM_operateD$D_IN; + if (wsiM_pMesgCount$EN) + wsiM_pMesgCount <= `BSV_ASSIGNMENT_DELAY wsiM_pMesgCount$D_IN; + if (wsiM_peerIsReady$EN) + wsiM_peerIsReady <= `BSV_ASSIGNMENT_DELAY wsiM_peerIsReady$D_IN; + if (wsiM_reqFifo_c_r$EN) + wsiM_reqFifo_c_r <= `BSV_ASSIGNMENT_DELAY wsiM_reqFifo_c_r$D_IN; + if (wsiM_reqFifo_q_0$EN) + wsiM_reqFifo_q_0 <= `BSV_ASSIGNMENT_DELAY wsiM_reqFifo_q_0$D_IN; + if (wsiM_reqFifo_q_1$EN) + wsiM_reqFifo_q_1 <= `BSV_ASSIGNMENT_DELAY wsiM_reqFifo_q_1$D_IN; + if (wsiM_sThreadBusy_d$EN) + wsiM_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY wsiM_sThreadBusy_d$D_IN; + if (wsiM_tBusyCount$EN) + wsiM_tBusyCount <= `BSV_ASSIGNMENT_DELAY wsiM_tBusyCount$D_IN; + if (wsiM_trafficSticky$EN) + wsiM_trafficSticky <= `BSV_ASSIGNMENT_DELAY wsiM_trafficSticky$D_IN; + if (wsiS_burstKind$EN) + wsiS_burstKind <= `BSV_ASSIGNMENT_DELAY wsiS_burstKind$D_IN; + if (wsiS_errorSticky$EN) + wsiS_errorSticky <= `BSV_ASSIGNMENT_DELAY wsiS_errorSticky$D_IN; + if (wsiS_iMesgCount$EN) + wsiS_iMesgCount <= `BSV_ASSIGNMENT_DELAY wsiS_iMesgCount$D_IN; + if (wsiS_operateD$EN) + wsiS_operateD <= `BSV_ASSIGNMENT_DELAY wsiS_operateD$D_IN; + if (wsiS_pMesgCount$EN) + wsiS_pMesgCount <= `BSV_ASSIGNMENT_DELAY wsiS_pMesgCount$D_IN; + if (wsiS_peerIsReady$EN) + wsiS_peerIsReady <= `BSV_ASSIGNMENT_DELAY wsiS_peerIsReady$D_IN; + if (wsiS_reqFifo_countReg$EN) + wsiS_reqFifo_countReg <= `BSV_ASSIGNMENT_DELAY + wsiS_reqFifo_countReg$D_IN; + if (wsiS_reqFifo_levelsValid$EN) + wsiS_reqFifo_levelsValid <= `BSV_ASSIGNMENT_DELAY + wsiS_reqFifo_levelsValid$D_IN; + if (wsiS_tBusyCount$EN) + wsiS_tBusyCount <= `BSV_ASSIGNMENT_DELAY wsiS_tBusyCount$D_IN; + if (wsiS_trafficSticky$EN) + wsiS_trafficSticky <= `BSV_ASSIGNMENT_DELAY wsiS_trafficSticky$D_IN; + if (wsiS_wordCount$EN) + wsiS_wordCount <= `BSV_ASSIGNMENT_DELAY wsiS_wordCount$D_IN; + end + if (wsiM_statusR$EN) + wsiM_statusR <= `BSV_ASSIGNMENT_DELAY wsiM_statusR$D_IN; + if (wsiS_mesgWordLength$EN) + wsiS_mesgWordLength <= `BSV_ASSIGNMENT_DELAY wsiS_mesgWordLength$D_IN; + if (wsiS_statusR$EN) + wsiS_statusR <= `BSV_ASSIGNMENT_DELAY wsiS_statusR$D_IN; + end + + always@(posedge wciS0_Clk or `BSV_RESET_EDGE wciS0_MReset_n) + if (wciS0_MReset_n == `BSV_RESET_VALUE) + begin + wci_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY 1'd1; + wsiM_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY 1'd1; + wsiS_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY 1'd1; + end + else + begin + if (wci_isReset_isInReset$EN) + wci_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY + wci_isReset_isInReset$D_IN; + if (wsiM_isReset_isInReset$EN) + wsiM_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY + wsiM_isReset_isInReset$D_IN; + if (wsiS_isReset_isInReset$EN) + wsiS_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY + wsiS_isReset_isInReset$D_IN; + end + + // synopsys translate_off + `ifdef BSV_NO_INITIAL_BLOCKS + `else // not BSV_NO_INITIAL_BLOCKS + initial + begin + byteCount = 32'hAAAAAAAA; + frameGateCtrl = 32'hAAAAAAAA; + frameSize = 32'hAAAAAAAA; + gateSize = 32'hAAAAAAAA; + gated = 1'h0; + op0MesgCnt = 32'hAAAAAAAA; + otherMesgCnt = 32'hAAAAAAAA; + wci_cEdge = 3'h2; + wci_cState = 3'h2; + wci_ctlAckReg = 1'h0; + wci_ctlOpActive = 1'h0; + wci_illegalEdge = 1'h0; + wci_isReset_isInReset = 1'h0; + wci_nState = 3'h2; + wci_reqF_countReg = 2'h2; + wci_respF_c_r = 2'h2; + wci_respF_q_0 = 34'h2AAAAAAAA; + wci_respF_q_1 = 34'h2AAAAAAAA; + wci_sFlagReg = 1'h0; + wci_sThreadBusy_d = 1'h0; + wsiM_burstKind = 2'h2; + wsiM_errorSticky = 1'h0; + wsiM_iMesgCount = 32'hAAAAAAAA; + wsiM_isReset_isInReset = 1'h0; + wsiM_operateD = 1'h0; + wsiM_pMesgCount = 32'hAAAAAAAA; + wsiM_peerIsReady = 1'h0; + wsiM_reqFifo_c_r = 2'h2; + wsiM_reqFifo_q_0 = + 313'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; + wsiM_reqFifo_q_1 = + 313'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; + wsiM_sThreadBusy_d = 1'h0; + wsiM_statusR = 8'hAA; + wsiM_tBusyCount = 32'hAAAAAAAA; + wsiM_trafficSticky = 1'h0; + wsiS_burstKind = 2'h2; + wsiS_errorSticky = 1'h0; + wsiS_iMesgCount = 32'hAAAAAAAA; + wsiS_isReset_isInReset = 1'h0; + wsiS_mesgWordLength = 12'hAAA; + wsiS_operateD = 1'h0; + wsiS_pMesgCount = 32'hAAAAAAAA; + wsiS_peerIsReady = 1'h0; + wsiS_reqFifo_countReg = 2'h2; + wsiS_reqFifo_levelsValid = 1'h0; + wsiS_statusR = 8'hAA; + wsiS_tBusyCount = 32'hAAAAAAAA; + wsiS_trafficSticky = 1'h0; + wsiS_wordCount = 12'hAAA; + end + `endif // BSV_NO_INITIAL_BLOCKS + // synopsys translate_on + + // handling of system tasks + + // synopsys translate_off + always@(negedge wciS0_Clk) + begin + #0; + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_ctl_op_start) + begin + v__h3701 = $time; + #0; + end + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_ctl_op_start) + $display("[%0d]: %m: WCI ControlOp: Starting-transition edge:%x from:%x", + v__h3701, + wci_reqF$D_OUT[36:34], + wci_cState); + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_ctrl_IsO) + begin + v__h11217 = $time; + #0; + end + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_ctrl_IsO) + $display("[%0d]: %m: Starting FrameGate frameGateCtrl:%0x", + v__h11217, + frameGateCtrl); + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_ctrl_IsO && WILL_FIRE_RL_wci_ctrl_OrE) + $display("Error: \"bsv/prm/FrameGate.bsv\", line 68, column 60: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_IsO] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n"); + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_ctrl_EiI && WILL_FIRE_RL_wci_ctrl_OrE) + $display("Error: \"bsv/prm/FrameGate.bsv\", line 68, column 46: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_EiI] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n"); + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_ctrl_EiI && WILL_FIRE_RL_wci_ctrl_IsO) + $display("Error: \"bsv/prm/FrameGate.bsv\", line 68, column 46: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_EiI] and\n [RL_wci_ctrl_IsO] ) fired in the same clock cycle.\n"); + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_ctl_op_complete && wci_illegalEdge) + begin + v__h4020 = $time; + #0; + end + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_ctl_op_complete && wci_illegalEdge) + $display("[%0d]: %m: WCI ControlOp: ILLEGAL-EDGE Completed-transition edge:%x from:%x", + v__h4020, + wci_cEdge, + wci_cState); + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_ctl_op_complete && !wci_illegalEdge) + begin + v__h3876 = $time; + #0; + end + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_ctl_op_complete && !wci_illegalEdge) + $display("[%0d]: %m: WCI ControlOp: Completed-transition edge:%x from:%x to:%x", + v__h3876, + wci_cEdge, + wci_cState, + wci_nState); + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_OrE) + $display("Error: \"bsv/prm/FrameGate.bsv\", line 68, column 26: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n"); + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_IsO) + $display("Error: \"bsv/prm/FrameGate.bsv\", line 68, column 26: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_wci_ctrl_IsO] ) fired in the same clock cycle.\n"); + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_EiI) + $display("Error: \"bsv/prm/FrameGate.bsv\", line 68, column 26: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_wci_ctrl_EiI] ) fired in the same clock cycle.\n"); + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_cfrd) + $display("Error: \"bsv/prm/FrameGate.bsv\", line 68, column 26: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and [RL_wci_cfrd] )\n fired in the same clock cycle.\n"); + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_cfrd && WILL_FIRE_RL_wci_ctrl_OrE) + $display("Error: \"bsv/prm/FrameGate.bsv\", line 68, column 36: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n"); + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_cfrd && WILL_FIRE_RL_wci_ctrl_IsO) + $display("Error: \"bsv/prm/FrameGate.bsv\", line 68, column 36: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n [RL_wci_ctrl_IsO] ) fired in the same clock cycle.\n"); + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_cfrd && WILL_FIRE_RL_wci_ctrl_EiI) + $display("Error: \"bsv/prm/FrameGate.bsv\", line 68, column 36: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n [RL_wci_ctrl_EiI] ) fired in the same clock cycle.\n"); + end + // synopsys translate_on +endmodule // mkFrameGate32B + diff --git a/rtl/mkFrameGate4B.v b/rtl/mkFrameGate4B.v new file mode 100644 index 00000000..9fba68f3 --- /dev/null +++ b/rtl/mkFrameGate4B.v @@ -0,0 +1,1658 @@ +// +// Generated by Bluespec Compiler, version 2012.09.beta1 (build 29570, 2012-09.11) +// +// On Tue Jan 22 07:32:59 EST 2013 +// +// +// Ports: +// Name I/O size props +// wciS0_SResp O 2 reg +// wciS0_SData O 32 reg +// wciS0_SThreadBusy O 1 +// wciS0_SFlag O 2 +// wsiS0_SThreadBusy O 1 +// wsiS0_SReset_n O 1 +// wsiM0_MCmd O 3 +// wsiM0_MReqLast O 1 +// wsiM0_MBurstPrecise O 1 +// wsiM0_MBurstLength O 12 +// wsiM0_MData O 32 reg +// wsiM0_MByteEn O 4 reg +// wsiM0_MReqInfo O 8 +// wsiM0_MReset_n O 1 +// wciS0_Clk I 1 clock +// wciS0_MReset_n I 1 reset +// wciS0_MCmd I 3 +// wciS0_MAddrSpace I 1 +// wciS0_MByteEn I 4 +// wciS0_MAddr I 32 +// wciS0_MData I 32 +// wciS0_MFlag I 2 unused +// wsiS0_MCmd I 3 +// wsiS0_MBurstLength I 12 +// wsiS0_MData I 32 +// wsiS0_MByteEn I 4 +// wsiS0_MReqInfo I 8 +// wsiS0_MReqLast I 1 +// wsiS0_MBurstPrecise I 1 +// wsiS0_MReset_n I 1 reg +// wsiM0_SThreadBusy I 1 reg +// wsiM0_SReset_n I 1 reg +// +// No combinational paths from inputs to outputs +// +// + +`ifdef BSV_ASSIGNMENT_DELAY +`else + `define BSV_ASSIGNMENT_DELAY +`endif + +`ifdef BSV_POSITIVE_RESET + `define BSV_RESET_VALUE 1'b1 + `define BSV_RESET_EDGE posedge +`else + `define BSV_RESET_VALUE 1'b0 + `define BSV_RESET_EDGE negedge +`endif + +module mkFrameGate4B(wciS0_Clk, + wciS0_MReset_n, + + wciS0_MCmd, + + wciS0_MAddrSpace, + + wciS0_MByteEn, + + wciS0_MAddr, + + wciS0_MData, + + wciS0_SResp, + + wciS0_SData, + + wciS0_SThreadBusy, + + wciS0_SFlag, + + wciS0_MFlag, + + wsiS0_MCmd, + + wsiS0_MReqLast, + + wsiS0_MBurstPrecise, + + wsiS0_MBurstLength, + + wsiS0_MData, + + wsiS0_MByteEn, + + wsiS0_MReqInfo, + + wsiS0_SThreadBusy, + + wsiS0_SReset_n, + + wsiS0_MReset_n, + + wsiM0_MCmd, + + wsiM0_MReqLast, + + wsiM0_MBurstPrecise, + + wsiM0_MBurstLength, + + wsiM0_MData, + + wsiM0_MByteEn, + + wsiM0_MReqInfo, + + wsiM0_SThreadBusy, + + wsiM0_MReset_n, + + wsiM0_SReset_n); + parameter [31 : 0] fgCtrlInit = 32'b0; + parameter [0 : 0] hasDebugLogic = 1'b0; + input wciS0_Clk; + input wciS0_MReset_n; + + // action method wciS0_mCmd + input [2 : 0] wciS0_MCmd; + + // action method wciS0_mAddrSpace + input wciS0_MAddrSpace; + + // action method wciS0_mByteEn + input [3 : 0] wciS0_MByteEn; + + // action method wciS0_mAddr + input [31 : 0] wciS0_MAddr; + + // action method wciS0_mData + input [31 : 0] wciS0_MData; + + // value method wciS0_sResp + output [1 : 0] wciS0_SResp; + + // value method wciS0_sData + output [31 : 0] wciS0_SData; + + // value method wciS0_sThreadBusy + output wciS0_SThreadBusy; + + // value method wciS0_sFlag + output [1 : 0] wciS0_SFlag; + + // action method wciS0_mFlag + input [1 : 0] wciS0_MFlag; + + // action method wsiS0_mCmd + input [2 : 0] wsiS0_MCmd; + + // action method wsiS0_mReqLast + input wsiS0_MReqLast; + + // action method wsiS0_mBurstPrecise + input wsiS0_MBurstPrecise; + + // action method wsiS0_mBurstLength + input [11 : 0] wsiS0_MBurstLength; + + // action method wsiS0_mData + input [31 : 0] wsiS0_MData; + + // action method wsiS0_mByteEn + input [3 : 0] wsiS0_MByteEn; + + // action method wsiS0_mReqInfo + input [7 : 0] wsiS0_MReqInfo; + + // action method wsiS0_mDataInfo + + // value method wsiS0_sThreadBusy + output wsiS0_SThreadBusy; + + // value method wsiS0_sReset_n + output wsiS0_SReset_n; + + // action method wsiS0_mReset_n + input wsiS0_MReset_n; + + // value method wsiM0_mCmd + output [2 : 0] wsiM0_MCmd; + + // value method wsiM0_mReqLast + output wsiM0_MReqLast; + + // value method wsiM0_mBurstPrecise + output wsiM0_MBurstPrecise; + + // value method wsiM0_mBurstLength + output [11 : 0] wsiM0_MBurstLength; + + // value method wsiM0_mData + output [31 : 0] wsiM0_MData; + + // value method wsiM0_mByteEn + output [3 : 0] wsiM0_MByteEn; + + // value method wsiM0_mReqInfo + output [7 : 0] wsiM0_MReqInfo; + + // value method wsiM0_mDataInfo + + // action method wsiM0_sThreadBusy + input wsiM0_SThreadBusy; + + // value method wsiM0_mReset_n + output wsiM0_MReset_n; + + // action method wsiM0_sReset_n + input wsiM0_SReset_n; + + // signals for module outputs + wire [31 : 0] wciS0_SData, wsiM0_MData; + wire [11 : 0] wsiM0_MBurstLength; + wire [7 : 0] wsiM0_MReqInfo; + wire [3 : 0] wsiM0_MByteEn; + wire [2 : 0] wsiM0_MCmd; + wire [1 : 0] wciS0_SFlag, wciS0_SResp; + wire wciS0_SThreadBusy, + wsiM0_MBurstPrecise, + wsiM0_MReqLast, + wsiM0_MReset_n, + wsiS0_SReset_n, + wsiS0_SThreadBusy; + + // inlined wires + wire [95 : 0] wsiM_extStatusW$wget, wsiS_extStatusW$wget; + wire [71 : 0] wci_wciReq$wget; + wire [60 : 0] wsiM_reqFifo_x_wire$wget, wsiS_wsiReq$wget; + wire [33 : 0] wci_respF_x_wire$wget; + wire [31 : 0] wci_Es_mAddr_w$wget, wci_Es_mData_w$wget, wsi_Es_mData_w$wget; + wire [11 : 0] wsi_Es_mBurstLength_w$wget; + wire [7 : 0] wsi_Es_mReqInfo_w$wget; + wire [3 : 0] wci_Es_mByteEn_w$wget, wsi_Es_mByteEn_w$wget; + wire [2 : 0] wci_Es_mCmd_w$wget, wci_wEdge$wget, wsi_Es_mCmd_w$wget; + wire wci_Es_mAddrSpace_w$wget, + wci_Es_mAddrSpace_w$whas, + wci_Es_mAddr_w$whas, + wci_Es_mByteEn_w$whas, + wci_Es_mCmd_w$whas, + wci_Es_mData_w$whas, + wci_ctlAckReg_1$wget, + wci_ctlAckReg_1$whas, + wci_reqF_r_clr$whas, + wci_reqF_r_deq$whas, + wci_reqF_r_enq$whas, + wci_respF_dequeueing$whas, + wci_respF_enqueueing$whas, + wci_respF_x_wire$whas, + wci_sFlagReg_1$wget, + wci_sFlagReg_1$whas, + wci_sThreadBusy_pw$whas, + wci_wEdge$whas, + wci_wciReq$whas, + wci_wci_cfrd_pw$whas, + wci_wci_cfwr_pw$whas, + wci_wci_ctrl_pw$whas, + wsiM_operateD_1$wget, + wsiM_operateD_1$whas, + wsiM_peerIsReady_1$wget, + wsiM_peerIsReady_1$whas, + wsiM_reqFifo_dequeueing$whas, + wsiM_reqFifo_enqueueing$whas, + wsiM_reqFifo_x_wire$whas, + wsiM_sThreadBusy_pw$whas, + wsiS_operateD_1$wget, + wsiS_operateD_1$whas, + wsiS_peerIsReady_1$wget, + wsiS_peerIsReady_1$whas, + wsiS_reqFifo_doResetClr$whas, + wsiS_reqFifo_doResetDeq$whas, + wsiS_reqFifo_doResetEnq$whas, + wsiS_reqFifo_r_clr$whas, + wsiS_reqFifo_r_deq$whas, + wsiS_reqFifo_r_enq$whas, + wsiS_sThreadBusy_dw$wget, + wsiS_sThreadBusy_dw$whas, + wsiS_wsiReq$whas, + wsi_Es_mBurstLength_w$whas, + wsi_Es_mBurstPrecise_w$whas, + wsi_Es_mByteEn_w$whas, + wsi_Es_mCmd_w$whas, + wsi_Es_mDataInfo_w$whas, + wsi_Es_mData_w$whas, + wsi_Es_mReqInfo_w$whas, + wsi_Es_mReqLast_w$whas; + + // register byteCount + reg [31 : 0] byteCount; + wire [31 : 0] byteCount$D_IN; + wire byteCount$EN; + + // register frameGateCtrl + reg [31 : 0] frameGateCtrl; + wire [31 : 0] frameGateCtrl$D_IN; + wire frameGateCtrl$EN; + + // register frameSize + reg [31 : 0] frameSize; + wire [31 : 0] frameSize$D_IN; + wire frameSize$EN; + + // register gateSize + reg [31 : 0] gateSize; + wire [31 : 0] gateSize$D_IN; + wire gateSize$EN; + + // register gated + reg gated; + wire gated$D_IN, gated$EN; + + // register op0MesgCnt + reg [31 : 0] op0MesgCnt; + wire [31 : 0] op0MesgCnt$D_IN; + wire op0MesgCnt$EN; + + // register otherMesgCnt + reg [31 : 0] otherMesgCnt; + wire [31 : 0] otherMesgCnt$D_IN; + wire otherMesgCnt$EN; + + // register wci_cEdge + reg [2 : 0] wci_cEdge; + wire [2 : 0] wci_cEdge$D_IN; + wire wci_cEdge$EN; + + // register wci_cState + reg [2 : 0] wci_cState; + wire [2 : 0] wci_cState$D_IN; + wire wci_cState$EN; + + // register wci_ctlAckReg + reg wci_ctlAckReg; + wire wci_ctlAckReg$D_IN, wci_ctlAckReg$EN; + + // register wci_ctlOpActive + reg wci_ctlOpActive; + wire wci_ctlOpActive$D_IN, wci_ctlOpActive$EN; + + // register wci_illegalEdge + reg wci_illegalEdge; + wire wci_illegalEdge$D_IN, wci_illegalEdge$EN; + + // register wci_isReset_isInReset + reg wci_isReset_isInReset; + wire wci_isReset_isInReset$D_IN, wci_isReset_isInReset$EN; + + // register wci_nState + reg [2 : 0] wci_nState; + reg [2 : 0] wci_nState$D_IN; + wire wci_nState$EN; + + // register wci_reqF_countReg + reg [1 : 0] wci_reqF_countReg; + wire [1 : 0] wci_reqF_countReg$D_IN; + wire wci_reqF_countReg$EN; + + // register wci_respF_c_r + reg [1 : 0] wci_respF_c_r; + wire [1 : 0] wci_respF_c_r$D_IN; + wire wci_respF_c_r$EN; + + // register wci_respF_q_0 + reg [33 : 0] wci_respF_q_0; + reg [33 : 0] wci_respF_q_0$D_IN; + wire wci_respF_q_0$EN; + + // register wci_respF_q_1 + reg [33 : 0] wci_respF_q_1; + reg [33 : 0] wci_respF_q_1$D_IN; + wire wci_respF_q_1$EN; + + // register wci_sFlagReg + reg wci_sFlagReg; + wire wci_sFlagReg$D_IN, wci_sFlagReg$EN; + + // register wci_sThreadBusy_d + reg wci_sThreadBusy_d; + wire wci_sThreadBusy_d$D_IN, wci_sThreadBusy_d$EN; + + // register wsiM_burstKind + reg [1 : 0] wsiM_burstKind; + wire [1 : 0] wsiM_burstKind$D_IN; + wire wsiM_burstKind$EN; + + // register wsiM_errorSticky + reg wsiM_errorSticky; + wire wsiM_errorSticky$D_IN, wsiM_errorSticky$EN; + + // register wsiM_iMesgCount + reg [31 : 0] wsiM_iMesgCount; + wire [31 : 0] wsiM_iMesgCount$D_IN; + wire wsiM_iMesgCount$EN; + + // register wsiM_isReset_isInReset + reg wsiM_isReset_isInReset; + wire wsiM_isReset_isInReset$D_IN, wsiM_isReset_isInReset$EN; + + // register wsiM_operateD + reg wsiM_operateD; + wire wsiM_operateD$D_IN, wsiM_operateD$EN; + + // register wsiM_pMesgCount + reg [31 : 0] wsiM_pMesgCount; + wire [31 : 0] wsiM_pMesgCount$D_IN; + wire wsiM_pMesgCount$EN; + + // register wsiM_peerIsReady + reg wsiM_peerIsReady; + wire wsiM_peerIsReady$D_IN, wsiM_peerIsReady$EN; + + // register wsiM_reqFifo_c_r + reg [1 : 0] wsiM_reqFifo_c_r; + wire [1 : 0] wsiM_reqFifo_c_r$D_IN; + wire wsiM_reqFifo_c_r$EN; + + // register wsiM_reqFifo_q_0 + reg [60 : 0] wsiM_reqFifo_q_0; + reg [60 : 0] wsiM_reqFifo_q_0$D_IN; + wire wsiM_reqFifo_q_0$EN; + + // register wsiM_reqFifo_q_1 + reg [60 : 0] wsiM_reqFifo_q_1; + reg [60 : 0] wsiM_reqFifo_q_1$D_IN; + wire wsiM_reqFifo_q_1$EN; + + // register wsiM_sThreadBusy_d + reg wsiM_sThreadBusy_d; + wire wsiM_sThreadBusy_d$D_IN, wsiM_sThreadBusy_d$EN; + + // register wsiM_statusR + reg [7 : 0] wsiM_statusR; + wire [7 : 0] wsiM_statusR$D_IN; + wire wsiM_statusR$EN; + + // register wsiM_tBusyCount + reg [31 : 0] wsiM_tBusyCount; + wire [31 : 0] wsiM_tBusyCount$D_IN; + wire wsiM_tBusyCount$EN; + + // register wsiM_trafficSticky + reg wsiM_trafficSticky; + wire wsiM_trafficSticky$D_IN, wsiM_trafficSticky$EN; + + // register wsiS_burstKind + reg [1 : 0] wsiS_burstKind; + wire [1 : 0] wsiS_burstKind$D_IN; + wire wsiS_burstKind$EN; + + // register wsiS_errorSticky + reg wsiS_errorSticky; + wire wsiS_errorSticky$D_IN, wsiS_errorSticky$EN; + + // register wsiS_iMesgCount + reg [31 : 0] wsiS_iMesgCount; + wire [31 : 0] wsiS_iMesgCount$D_IN; + wire wsiS_iMesgCount$EN; + + // register wsiS_isReset_isInReset + reg wsiS_isReset_isInReset; + wire wsiS_isReset_isInReset$D_IN, wsiS_isReset_isInReset$EN; + + // register wsiS_mesgWordLength + reg [11 : 0] wsiS_mesgWordLength; + wire [11 : 0] wsiS_mesgWordLength$D_IN; + wire wsiS_mesgWordLength$EN; + + // register wsiS_operateD + reg wsiS_operateD; + wire wsiS_operateD$D_IN, wsiS_operateD$EN; + + // register wsiS_pMesgCount + reg [31 : 0] wsiS_pMesgCount; + wire [31 : 0] wsiS_pMesgCount$D_IN; + wire wsiS_pMesgCount$EN; + + // register wsiS_peerIsReady + reg wsiS_peerIsReady; + wire wsiS_peerIsReady$D_IN, wsiS_peerIsReady$EN; + + // register wsiS_reqFifo_countReg + reg [1 : 0] wsiS_reqFifo_countReg; + wire [1 : 0] wsiS_reqFifo_countReg$D_IN; + wire wsiS_reqFifo_countReg$EN; + + // register wsiS_reqFifo_levelsValid + reg wsiS_reqFifo_levelsValid; + wire wsiS_reqFifo_levelsValid$D_IN, wsiS_reqFifo_levelsValid$EN; + + // register wsiS_statusR + reg [7 : 0] wsiS_statusR; + wire [7 : 0] wsiS_statusR$D_IN; + wire wsiS_statusR$EN; + + // register wsiS_tBusyCount + reg [31 : 0] wsiS_tBusyCount; + wire [31 : 0] wsiS_tBusyCount$D_IN; + wire wsiS_tBusyCount$EN; + + // register wsiS_trafficSticky + reg wsiS_trafficSticky; + wire wsiS_trafficSticky$D_IN, wsiS_trafficSticky$EN; + + // register wsiS_wordCount + reg [11 : 0] wsiS_wordCount; + wire [11 : 0] wsiS_wordCount$D_IN; + wire wsiS_wordCount$EN; + + // ports of submodule wci_reqF + wire [71 : 0] wci_reqF$D_IN, wci_reqF$D_OUT; + wire wci_reqF$CLR, wci_reqF$DEQ, wci_reqF$EMPTY_N, wci_reqF$ENQ; + + // ports of submodule wsiS_reqFifo + wire [60 : 0] wsiS_reqFifo$D_IN, wsiS_reqFifo$D_OUT; + wire wsiS_reqFifo$CLR, + wsiS_reqFifo$DEQ, + wsiS_reqFifo$EMPTY_N, + wsiS_reqFifo$ENQ, + wsiS_reqFifo$FULL_N; + + // rule scheduling signals + wire WILL_FIRE_RL_wci_cfrd, + WILL_FIRE_RL_wci_cfwr, + WILL_FIRE_RL_wci_ctl_op_complete, + WILL_FIRE_RL_wci_ctl_op_start, + WILL_FIRE_RL_wci_ctrl_EiI, + WILL_FIRE_RL_wci_ctrl_IsO, + WILL_FIRE_RL_wci_ctrl_OrE, + WILL_FIRE_RL_wci_respF_both, + WILL_FIRE_RL_wci_respF_decCtr, + WILL_FIRE_RL_wci_respF_incCtr, + WILL_FIRE_RL_wsiM_reqFifo_both, + WILL_FIRE_RL_wsiM_reqFifo_decCtr, + WILL_FIRE_RL_wsiM_reqFifo_deq, + WILL_FIRE_RL_wsiM_reqFifo_incCtr, + WILL_FIRE_RL_wsiS_reqFifo_enq, + WILL_FIRE_RL_wsiS_reqFifo_reset, + WILL_FIRE_RL_wsipass_doMessagePush; + + // inputs to muxes for submodule ports + reg [33 : 0] MUX_wci_respF_q_0$write_1__VAL_2; + wire [60 : 0] MUX_wsiM_reqFifo_q_0$write_1__VAL_1, + MUX_wsiM_reqFifo_q_1$write_1__VAL_1; + wire [33 : 0] MUX_wci_respF_q_0$write_1__VAL_1, + MUX_wci_respF_q_1$write_1__VAL_1, + MUX_wci_respF_x_wire$wset_1__VAL_1, + MUX_wci_respF_x_wire$wset_1__VAL_2; + wire [1 : 0] MUX_wci_respF_c_r$write_1__VAL_1, + MUX_wci_respF_c_r$write_1__VAL_2, + MUX_wsiM_reqFifo_c_r$write_1__VAL_1, + MUX_wsiM_reqFifo_c_r$write_1__VAL_2; + wire MUX_wci_illegalEdge$write_1__SEL_1, + MUX_wci_illegalEdge$write_1__SEL_2, + MUX_wci_illegalEdge$write_1__VAL_2, + MUX_wci_respF_q_0$write_1__SEL_2, + MUX_wci_respF_q_1$write_1__SEL_2, + MUX_wsiM_reqFifo_q_0$write_1__SEL_2, + MUX_wsiM_reqFifo_q_1$write_1__SEL_2; + + // remaining internal signals + reg [63 : 0] v__h11217, v__h3701, v__h3876, v__h4020; + reg [31 : 0] g_data__h10929; + wire [31 : 0] frameGateStatus__h10551, + rdat__h10963, + rdat__h11063, + rdat__h11077, + rdat__h11085, + rdat__h11091, + rdat__h11105, + rdat__h11113, + rdat__h11119, + rdat__h11130, + x__h10327; + wire [15 : 0] x__h10967; + wire NOT_gated_99_05_AND_byteCount_06_EQ_frameSize__ETC___d439, + wsiS_reqFifo_i_notEmpty__92_AND_NOT_frameGateC_ETC___d303; + + // value method wciS0_sResp + assign wciS0_SResp = wci_respF_q_0[33:32] ; + + // value method wciS0_sData + assign wciS0_SData = wci_respF_q_0[31:0] ; + + // value method wciS0_sThreadBusy + assign wciS0_SThreadBusy = + wci_reqF_countReg > 2'd1 || wci_isReset_isInReset ; + + // value method wciS0_sFlag + assign wciS0_SFlag = { 1'd1, wci_sFlagReg } ; + + // value method wsiS0_sThreadBusy + assign wsiS0_SThreadBusy = + !wsiS_sThreadBusy_dw$whas || wsiS_sThreadBusy_dw$wget ; + + // value method wsiS0_sReset_n + assign wsiS0_SReset_n = !wsiS_isReset_isInReset && wsiS_operateD ; + + // value method wsiM0_mCmd + assign wsiM0_MCmd = wsiM_sThreadBusy_d ? 3'd0 : wsiM_reqFifo_q_0[60:58] ; + + // value method wsiM0_mReqLast + assign wsiM0_MReqLast = !wsiM_sThreadBusy_d && wsiM_reqFifo_q_0[57] ; + + // value method wsiM0_mBurstPrecise + assign wsiM0_MBurstPrecise = !wsiM_sThreadBusy_d && wsiM_reqFifo_q_0[56] ; + + // value method wsiM0_mBurstLength + assign wsiM0_MBurstLength = + wsiM_sThreadBusy_d ? 12'd0 : wsiM_reqFifo_q_0[55:44] ; + + // value method wsiM0_mData + assign wsiM0_MData = wsiM_reqFifo_q_0[43:12] ; + + // value method wsiM0_mByteEn + assign wsiM0_MByteEn = wsiM_reqFifo_q_0[11:8] ; + + // value method wsiM0_mReqInfo + assign wsiM0_MReqInfo = wsiM_sThreadBusy_d ? 8'd0 : wsiM_reqFifo_q_0[7:0] ; + + // value method wsiM0_mReset_n + assign wsiM0_MReset_n = !wsiM_isReset_isInReset && wsiM_operateD ; + + // submodule wci_reqF + SizedFIFO #(.p1width(32'd72), + .p2depth(32'd3), + .p3cntr_width(32'd1), + .guarded(32'd1)) wci_reqF(.RST(wciS0_MReset_n), + .CLK(wciS0_Clk), + .D_IN(wci_reqF$D_IN), + .ENQ(wci_reqF$ENQ), + .DEQ(wci_reqF$DEQ), + .CLR(wci_reqF$CLR), + .D_OUT(wci_reqF$D_OUT), + .FULL_N(), + .EMPTY_N(wci_reqF$EMPTY_N)); + + // submodule wsiS_reqFifo + SizedFIFO #(.p1width(32'd61), + .p2depth(32'd3), + .p3cntr_width(32'd1), + .guarded(32'd1)) wsiS_reqFifo(.RST(wciS0_MReset_n), + .CLK(wciS0_Clk), + .D_IN(wsiS_reqFifo$D_IN), + .ENQ(wsiS_reqFifo$ENQ), + .DEQ(wsiS_reqFifo$DEQ), + .CLR(wsiS_reqFifo$CLR), + .D_OUT(wsiS_reqFifo$D_OUT), + .FULL_N(wsiS_reqFifo$FULL_N), + .EMPTY_N(wsiS_reqFifo$EMPTY_N)); + + // rule RL_wci_ctl_op_start + assign WILL_FIRE_RL_wci_ctl_op_start = + wci_reqF$EMPTY_N && wci_wci_ctrl_pw$whas && + !WILL_FIRE_RL_wci_ctl_op_complete ; + + // rule RL_wci_ctrl_IsO + assign WILL_FIRE_RL_wci_ctrl_IsO = + wci_wci_ctrl_pw$whas && WILL_FIRE_RL_wci_ctl_op_start && + wci_cState == 3'd1 && + wci_reqF$D_OUT[36:34] == 3'd1 ; + + // rule RL_wci_ctrl_EiI + assign WILL_FIRE_RL_wci_ctrl_EiI = + wci_wci_ctrl_pw$whas && WILL_FIRE_RL_wci_ctl_op_start && + wci_cState == 3'd0 && + wci_reqF$D_OUT[36:34] == 3'd0 ; + + // rule RL_wci_ctrl_OrE + assign WILL_FIRE_RL_wci_ctrl_OrE = + wci_wci_ctrl_pw$whas && WILL_FIRE_RL_wci_ctl_op_start && + wci_cState == 3'd2 && + wci_reqF$D_OUT[36:34] == 3'd3 ; + + // rule RL_wsipass_doMessagePush + assign WILL_FIRE_RL_wsipass_doMessagePush = + wsiS_reqFifo_i_notEmpty__92_AND_NOT_frameGateC_ETC___d303 && + wci_cState == 3'd2 ; + + // rule RL_wci_cfwr + assign WILL_FIRE_RL_wci_cfwr = + wci_respF_c_r != 2'd2 && wci_reqF$EMPTY_N && + wci_wci_cfwr_pw$whas && + !WILL_FIRE_RL_wci_ctl_op_start && + !WILL_FIRE_RL_wci_ctl_op_complete ; + + // rule RL_wci_ctl_op_complete + assign WILL_FIRE_RL_wci_ctl_op_complete = + wci_respF_c_r != 2'd2 && wci_ctlOpActive && wci_ctlAckReg ; + + // rule RL_wci_cfrd + assign WILL_FIRE_RL_wci_cfrd = + wci_respF_c_r != 2'd2 && wci_reqF$EMPTY_N && + wci_wci_cfrd_pw$whas && + !WILL_FIRE_RL_wci_ctl_op_start && + !WILL_FIRE_RL_wci_ctl_op_complete ; + + // rule RL_wci_respF_incCtr + assign WILL_FIRE_RL_wci_respF_incCtr = + ((wci_respF_c_r == 2'd0) ? + wci_respF_enqueueing$whas : + wci_respF_c_r != 2'd1 || wci_respF_enqueueing$whas) && + wci_respF_enqueueing$whas && + !(wci_respF_c_r != 2'd0) ; + + // rule RL_wci_respF_decCtr + assign WILL_FIRE_RL_wci_respF_decCtr = + wci_respF_c_r != 2'd0 && !wci_respF_enqueueing$whas ; + + // rule RL_wci_respF_both + assign WILL_FIRE_RL_wci_respF_both = + ((wci_respF_c_r == 2'd1) ? + wci_respF_enqueueing$whas : + wci_respF_c_r != 2'd2 || wci_respF_enqueueing$whas) && + wci_respF_c_r != 2'd0 && + wci_respF_enqueueing$whas ; + + // rule RL_wsiM_reqFifo_deq + assign WILL_FIRE_RL_wsiM_reqFifo_deq = + wsiM_reqFifo_c_r != 2'd0 && !wsiM_sThreadBusy_d ; + + // rule RL_wsiM_reqFifo_incCtr + assign WILL_FIRE_RL_wsiM_reqFifo_incCtr = + ((wsiM_reqFifo_c_r == 2'd0) ? + wsiM_reqFifo_enqueueing$whas : + wsiM_reqFifo_c_r != 2'd1 || wsiM_reqFifo_enqueueing$whas) && + wsiM_reqFifo_enqueueing$whas && + !WILL_FIRE_RL_wsiM_reqFifo_deq ; + + // rule RL_wsiM_reqFifo_decCtr + assign WILL_FIRE_RL_wsiM_reqFifo_decCtr = + WILL_FIRE_RL_wsiM_reqFifo_deq && !wsiM_reqFifo_enqueueing$whas ; + + // rule RL_wsiM_reqFifo_both + assign WILL_FIRE_RL_wsiM_reqFifo_both = + ((wsiM_reqFifo_c_r == 2'd1) ? + wsiM_reqFifo_enqueueing$whas : + wsiM_reqFifo_c_r != 2'd2 || wsiM_reqFifo_enqueueing$whas) && + WILL_FIRE_RL_wsiM_reqFifo_deq && + wsiM_reqFifo_enqueueing$whas ; + + // rule RL_wsiS_reqFifo_enq + assign WILL_FIRE_RL_wsiS_reqFifo_enq = + wsiS_reqFifo$FULL_N && wsiS_operateD && wsiS_peerIsReady && + wsiS_wsiReq$wget[60:58] == 3'd1 ; + + // rule RL_wsiS_reqFifo_reset + assign WILL_FIRE_RL_wsiS_reqFifo_reset = + WILL_FIRE_RL_wsiS_reqFifo_enq || + WILL_FIRE_RL_wsipass_doMessagePush ; + + // inputs to muxes for submodule ports + assign MUX_wci_illegalEdge$write_1__SEL_1 = + WILL_FIRE_RL_wci_ctl_op_complete && wci_illegalEdge ; + assign MUX_wci_illegalEdge$write_1__SEL_2 = + WILL_FIRE_RL_wci_ctl_op_start && + (wci_reqF$D_OUT[36:34] == 3'd0 && wci_cState != 3'd0 || + wci_reqF$D_OUT[36:34] == 3'd1 && wci_cState != 3'd1 && + wci_cState != 3'd3 || + wci_reqF$D_OUT[36:34] == 3'd2 && wci_cState != 3'd2 || + wci_reqF$D_OUT[36:34] == 3'd3 && wci_cState != 3'd3 && + wci_cState != 3'd2 && + wci_cState != 3'd1 || + wci_reqF$D_OUT[36:34] == 3'd4 || + wci_reqF$D_OUT[36:34] == 3'd5 || + wci_reqF$D_OUT[36:34] == 3'd6 || + wci_reqF$D_OUT[36:34] == 3'd7) ; + assign MUX_wci_respF_q_0$write_1__SEL_2 = + WILL_FIRE_RL_wci_respF_incCtr && wci_respF_c_r == 2'd0 ; + assign MUX_wci_respF_q_1$write_1__SEL_2 = + WILL_FIRE_RL_wci_respF_incCtr && wci_respF_c_r == 2'd1 ; + assign MUX_wsiM_reqFifo_q_0$write_1__SEL_2 = + WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_c_r == 2'd0 ; + assign MUX_wsiM_reqFifo_q_1$write_1__SEL_2 = + WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_c_r == 2'd1 ; + assign MUX_wci_illegalEdge$write_1__VAL_2 = + wci_reqF$D_OUT[36:34] != 3'd4 && wci_reqF$D_OUT[36:34] != 3'd5 && + wci_reqF$D_OUT[36:34] != 3'd6 ; + assign MUX_wci_respF_c_r$write_1__VAL_1 = wci_respF_c_r + 2'd1 ; + assign MUX_wci_respF_c_r$write_1__VAL_2 = wci_respF_c_r - 2'd1 ; + assign MUX_wci_respF_q_0$write_1__VAL_1 = + (wci_respF_c_r == 2'd1) ? + MUX_wci_respF_q_0$write_1__VAL_2 : + wci_respF_q_1 ; + always@(WILL_FIRE_RL_wci_ctl_op_complete or + MUX_wci_respF_x_wire$wset_1__VAL_1 or + WILL_FIRE_RL_wci_cfrd or + MUX_wci_respF_x_wire$wset_1__VAL_2 or WILL_FIRE_RL_wci_cfwr) + begin + case (1'b1) // synopsys parallel_case + WILL_FIRE_RL_wci_ctl_op_complete: + MUX_wci_respF_q_0$write_1__VAL_2 = + MUX_wci_respF_x_wire$wset_1__VAL_1; + WILL_FIRE_RL_wci_cfrd: + MUX_wci_respF_q_0$write_1__VAL_2 = + MUX_wci_respF_x_wire$wset_1__VAL_2; + WILL_FIRE_RL_wci_cfwr: MUX_wci_respF_q_0$write_1__VAL_2 = 34'h1C0DE4201; + default: MUX_wci_respF_q_0$write_1__VAL_2 = + 34'h2AAAAAAAA /* unspecified value */ ; + endcase + end + assign MUX_wci_respF_q_1$write_1__VAL_1 = + (wci_respF_c_r == 2'd2) ? + MUX_wci_respF_q_0$write_1__VAL_2 : + 34'h0AAAAAAAA ; + assign MUX_wci_respF_x_wire$wset_1__VAL_1 = + wci_illegalEdge ? 34'h3C0DE4202 : 34'h1C0DE4201 ; + assign MUX_wci_respF_x_wire$wset_1__VAL_2 = { 2'd1, g_data__h10929 } ; + assign MUX_wsiM_reqFifo_c_r$write_1__VAL_1 = wsiM_reqFifo_c_r + 2'd1 ; + assign MUX_wsiM_reqFifo_c_r$write_1__VAL_2 = wsiM_reqFifo_c_r - 2'd1 ; + assign MUX_wsiM_reqFifo_q_0$write_1__VAL_1 = + (wsiM_reqFifo_c_r == 2'd1) ? + wsiS_reqFifo$D_OUT : + wsiM_reqFifo_q_1 ; + assign MUX_wsiM_reqFifo_q_1$write_1__VAL_1 = + (wsiM_reqFifo_c_r == 2'd2) ? + wsiS_reqFifo$D_OUT : + 61'h00000AAAAAAAAA00 ; + + // inlined wires + assign wci_wciReq$wget = + { wciS0_MCmd, + wciS0_MAddrSpace, + wciS0_MByteEn, + wciS0_MAddr, + wciS0_MData } ; + assign wci_wciReq$whas = 1'd1 ; + assign wci_respF_x_wire$wget = MUX_wci_respF_q_0$write_1__VAL_2 ; + assign wci_respF_x_wire$whas = wci_respF_enqueueing$whas ; + assign wci_wEdge$wget = wci_reqF$D_OUT[36:34] ; + assign wci_wEdge$whas = WILL_FIRE_RL_wci_ctl_op_start ; + assign wci_sFlagReg_1$wget = 1'b0 ; + assign wci_sFlagReg_1$whas = 1'b0 ; + assign wci_ctlAckReg_1$wget = 1'd1 ; + assign wci_ctlAckReg_1$whas = + WILL_FIRE_RL_wci_ctrl_OrE || WILL_FIRE_RL_wci_ctrl_IsO || + WILL_FIRE_RL_wci_ctrl_EiI ; + assign wsiS_wsiReq$wget = + { wsiS0_MCmd, + wsiS0_MReqLast, + wsiS0_MBurstPrecise, + wsiS0_MBurstLength, + wsiS0_MData, + wsiS0_MByteEn, + wsiS0_MReqInfo } ; + assign wsiS_wsiReq$whas = 1'd1 ; + assign wsiS_operateD_1$wget = 1'd1 ; + assign wsiS_operateD_1$whas = wci_cState == 3'd2 ; + assign wsiS_peerIsReady_1$wget = 1'd1 ; + assign wsiS_peerIsReady_1$whas = wsiS0_MReset_n ; + assign wsiS_sThreadBusy_dw$wget = wsiS_reqFifo_countReg > 2'd1 ; + assign wsiS_sThreadBusy_dw$whas = + wsiS_reqFifo_levelsValid && wsiS_operateD && wsiS_peerIsReady ; + assign wsiM_reqFifo_x_wire$wget = wsiS_reqFifo$D_OUT ; + assign wsiM_reqFifo_x_wire$whas = wsiM_reqFifo_enqueueing$whas ; + assign wsiM_operateD_1$wget = 1'd1 ; + assign wsiM_operateD_1$whas = wci_cState == 3'd2 ; + assign wsiM_peerIsReady_1$wget = 1'd1 ; + assign wsiM_peerIsReady_1$whas = wsiM0_SReset_n ; + assign wci_Es_mCmd_w$wget = wciS0_MCmd ; + assign wci_Es_mCmd_w$whas = 1'd1 ; + assign wci_Es_mAddrSpace_w$wget = wciS0_MAddrSpace ; + assign wci_Es_mAddrSpace_w$whas = 1'd1 ; + assign wci_Es_mByteEn_w$wget = wciS0_MByteEn ; + assign wci_Es_mByteEn_w$whas = 1'd1 ; + assign wci_Es_mAddr_w$wget = wciS0_MAddr ; + assign wci_Es_mAddr_w$whas = 1'd1 ; + assign wci_Es_mData_w$wget = wciS0_MData ; + assign wci_Es_mData_w$whas = 1'd1 ; + assign wsi_Es_mCmd_w$wget = wsiS0_MCmd ; + assign wsi_Es_mCmd_w$whas = 1'd1 ; + assign wsi_Es_mBurstLength_w$wget = wsiS0_MBurstLength ; + assign wsi_Es_mBurstLength_w$whas = 1'd1 ; + assign wsi_Es_mData_w$wget = wsiS0_MData ; + assign wsi_Es_mData_w$whas = 1'd1 ; + assign wsi_Es_mByteEn_w$wget = wsiS0_MByteEn ; + assign wsi_Es_mByteEn_w$whas = 1'd1 ; + assign wsi_Es_mReqInfo_w$wget = wsiS0_MReqInfo ; + assign wsi_Es_mReqInfo_w$whas = 1'd1 ; + assign wci_reqF_r_enq$whas = wci_wciReq$wget[71:69] != 3'd0 ; + assign wci_reqF_r_deq$whas = + WILL_FIRE_RL_wci_ctl_op_start || WILL_FIRE_RL_wci_cfrd || + WILL_FIRE_RL_wci_cfwr ; + assign wci_reqF_r_clr$whas = 1'b0 ; + assign wci_respF_enqueueing$whas = + WILL_FIRE_RL_wci_ctl_op_complete || WILL_FIRE_RL_wci_cfrd || + WILL_FIRE_RL_wci_cfwr ; + assign wci_respF_dequeueing$whas = wci_respF_c_r != 2'd0 ; + assign wci_sThreadBusy_pw$whas = 1'b0 ; + assign wci_wci_cfwr_pw$whas = + wci_reqF$EMPTY_N && wci_reqF$D_OUT[68] && + wci_reqF$D_OUT[71:69] == 3'd1 ; + assign wci_wci_cfrd_pw$whas = + wci_reqF$EMPTY_N && wci_reqF$D_OUT[68] && + wci_reqF$D_OUT[71:69] == 3'd2 ; + assign wci_wci_ctrl_pw$whas = + wci_reqF$EMPTY_N && !wci_reqF$D_OUT[68] && + wci_reqF$D_OUT[71:69] == 3'd2 ; + assign wsiS_reqFifo_r_enq$whas = WILL_FIRE_RL_wsiS_reqFifo_enq ; + assign wsiS_reqFifo_r_deq$whas = WILL_FIRE_RL_wsipass_doMessagePush ; + assign wsiS_reqFifo_r_clr$whas = 1'b0 ; + assign wsiS_reqFifo_doResetEnq$whas = WILL_FIRE_RL_wsiS_reqFifo_enq ; + assign wsiS_reqFifo_doResetDeq$whas = WILL_FIRE_RL_wsipass_doMessagePush ; + assign wsiS_reqFifo_doResetClr$whas = 1'b0 ; + assign wsiM_reqFifo_enqueueing$whas = + WILL_FIRE_RL_wsipass_doMessagePush && + (frameGateCtrl[3:0] == 4'h0 || + frameGateCtrl[3:0] == 4'h1 && !gated) ; + assign wsiM_reqFifo_dequeueing$whas = WILL_FIRE_RL_wsiM_reqFifo_deq ; + assign wsiM_sThreadBusy_pw$whas = wsiM0_SThreadBusy ; + assign wsi_Es_mReqLast_w$whas = wsiS0_MReqLast ; + assign wsi_Es_mBurstPrecise_w$whas = wsiS0_MBurstPrecise ; + assign wsi_Es_mDataInfo_w$whas = 1'd1 ; + assign wsiS_extStatusW$wget = + { wsiS_pMesgCount, wsiS_iMesgCount, wsiS_tBusyCount } ; + assign wsiM_extStatusW$wget = + { wsiM_pMesgCount, wsiM_iMesgCount, wsiM_tBusyCount } ; + + // register byteCount + assign byteCount$D_IN = + NOT_gated_99_05_AND_byteCount_06_EQ_frameSize__ETC___d439 ? + 32'd4 : + x__h10327 ; + assign byteCount$EN = WILL_FIRE_RL_wsipass_doMessagePush ; + + // register frameGateCtrl + assign frameGateCtrl$D_IN = wci_reqF$D_OUT[31:0] ; + assign frameGateCtrl$EN = + WILL_FIRE_RL_wci_cfwr && wci_reqF$D_OUT[63:32] == 32'h00000004 ; + + // register frameSize + assign frameSize$D_IN = wci_reqF$D_OUT[31:0] ; + assign frameSize$EN = + WILL_FIRE_RL_wci_cfwr && wci_reqF$D_OUT[63:32] == 32'h00000008 ; + + // register gateSize + assign gateSize$D_IN = wci_reqF$D_OUT[31:0] ; + assign gateSize$EN = + WILL_FIRE_RL_wci_cfwr && wci_reqF$D_OUT[63:32] == 32'h0000000C ; + + // register gated + assign gated$D_IN = !gated && byteCount == frameSize ; + assign gated$EN = + WILL_FIRE_RL_wsipass_doMessagePush && + NOT_gated_99_05_AND_byteCount_06_EQ_frameSize__ETC___d439 ; + + // register op0MesgCnt + assign op0MesgCnt$D_IN = 32'h0 ; + assign op0MesgCnt$EN = 1'b0 ; + + // register otherMesgCnt + assign otherMesgCnt$D_IN = 32'h0 ; + assign otherMesgCnt$EN = 1'b0 ; + + // register wci_cEdge + assign wci_cEdge$D_IN = wci_reqF$D_OUT[36:34] ; + assign wci_cEdge$EN = WILL_FIRE_RL_wci_ctl_op_start ; + + // register wci_cState + assign wci_cState$D_IN = wci_nState ; + assign wci_cState$EN = + WILL_FIRE_RL_wci_ctl_op_complete && !wci_illegalEdge ; + + // register wci_ctlAckReg + assign wci_ctlAckReg$D_IN = wci_ctlAckReg_1$whas ; + assign wci_ctlAckReg$EN = 1'd1 ; + + // register wci_ctlOpActive + assign wci_ctlOpActive$D_IN = !WILL_FIRE_RL_wci_ctl_op_complete ; + assign wci_ctlOpActive$EN = + WILL_FIRE_RL_wci_ctl_op_complete || + WILL_FIRE_RL_wci_ctl_op_start ; + + // register wci_illegalEdge + assign wci_illegalEdge$D_IN = + !MUX_wci_illegalEdge$write_1__SEL_1 && + MUX_wci_illegalEdge$write_1__VAL_2 ; + assign wci_illegalEdge$EN = + WILL_FIRE_RL_wci_ctl_op_complete && wci_illegalEdge || + MUX_wci_illegalEdge$write_1__SEL_2 ; + + // register wci_isReset_isInReset + assign wci_isReset_isInReset$D_IN = 1'd0 ; + assign wci_isReset_isInReset$EN = wci_isReset_isInReset ; + + // register wci_nState + always@(wci_reqF$D_OUT) + begin + case (wci_reqF$D_OUT[36:34]) + 3'd0: wci_nState$D_IN = 3'd1; + 3'd1: wci_nState$D_IN = 3'd2; + 3'd2: wci_nState$D_IN = 3'd3; + default: wci_nState$D_IN = 3'd0; + endcase + end + assign wci_nState$EN = + WILL_FIRE_RL_wci_ctl_op_start && + (wci_reqF$D_OUT[36:34] == 3'd0 && wci_cState == 3'd0 || + wci_reqF$D_OUT[36:34] == 3'd1 && + (wci_cState == 3'd1 || wci_cState == 3'd3) || + wci_reqF$D_OUT[36:34] == 3'd2 && wci_cState == 3'd2 || + wci_reqF$D_OUT[36:34] == 3'd3 && + (wci_cState == 3'd3 || wci_cState == 3'd2 || + wci_cState == 3'd1)) ; + + // register wci_reqF_countReg + assign wci_reqF_countReg$D_IN = + (wci_wciReq$wget[71:69] != 3'd0) ? + wci_reqF_countReg + 2'd1 : + wci_reqF_countReg - 2'd1 ; + assign wci_reqF_countReg$EN = + (wci_wciReq$wget[71:69] != 3'd0) != wci_reqF_r_deq$whas ; + + // register wci_respF_c_r + assign wci_respF_c_r$D_IN = + WILL_FIRE_RL_wci_respF_incCtr ? + MUX_wci_respF_c_r$write_1__VAL_1 : + MUX_wci_respF_c_r$write_1__VAL_2 ; + assign wci_respF_c_r$EN = + WILL_FIRE_RL_wci_respF_incCtr || WILL_FIRE_RL_wci_respF_decCtr ; + + // register wci_respF_q_0 + always@(WILL_FIRE_RL_wci_respF_both or + MUX_wci_respF_q_0$write_1__VAL_1 or + MUX_wci_respF_q_0$write_1__SEL_2 or + MUX_wci_respF_q_0$write_1__VAL_2 or + WILL_FIRE_RL_wci_respF_decCtr or wci_respF_q_1) + begin + case (1'b1) // synopsys parallel_case + WILL_FIRE_RL_wci_respF_both: + wci_respF_q_0$D_IN = MUX_wci_respF_q_0$write_1__VAL_1; + MUX_wci_respF_q_0$write_1__SEL_2: + wci_respF_q_0$D_IN = MUX_wci_respF_q_0$write_1__VAL_2; + WILL_FIRE_RL_wci_respF_decCtr: wci_respF_q_0$D_IN = wci_respF_q_1; + default: wci_respF_q_0$D_IN = 34'h2AAAAAAAA /* unspecified value */ ; + endcase + end + assign wci_respF_q_0$EN = + WILL_FIRE_RL_wci_respF_both || + WILL_FIRE_RL_wci_respF_incCtr && wci_respF_c_r == 2'd0 || + WILL_FIRE_RL_wci_respF_decCtr ; + + // register wci_respF_q_1 + always@(WILL_FIRE_RL_wci_respF_both or + MUX_wci_respF_q_1$write_1__VAL_1 or + MUX_wci_respF_q_1$write_1__SEL_2 or + MUX_wci_respF_q_0$write_1__VAL_2 or WILL_FIRE_RL_wci_respF_decCtr) + begin + case (1'b1) // synopsys parallel_case + WILL_FIRE_RL_wci_respF_both: + wci_respF_q_1$D_IN = MUX_wci_respF_q_1$write_1__VAL_1; + MUX_wci_respF_q_1$write_1__SEL_2: + wci_respF_q_1$D_IN = MUX_wci_respF_q_0$write_1__VAL_2; + WILL_FIRE_RL_wci_respF_decCtr: wci_respF_q_1$D_IN = 34'h0AAAAAAAA; + default: wci_respF_q_1$D_IN = 34'h2AAAAAAAA /* unspecified value */ ; + endcase + end + assign wci_respF_q_1$EN = + WILL_FIRE_RL_wci_respF_both || + WILL_FIRE_RL_wci_respF_incCtr && wci_respF_c_r == 2'd1 || + WILL_FIRE_RL_wci_respF_decCtr ; + + // register wci_sFlagReg + assign wci_sFlagReg$D_IN = 1'b0 ; + assign wci_sFlagReg$EN = 1'd1 ; + + // register wci_sThreadBusy_d + assign wci_sThreadBusy_d$D_IN = 1'b0 ; + assign wci_sThreadBusy_d$EN = 1'd1 ; + + // register wsiM_burstKind + assign wsiM_burstKind$D_IN = + (wsiM_burstKind == 2'd0) ? + (wsiM_reqFifo_q_0[56] ? 2'd1 : 2'd2) : + 2'd0 ; + assign wsiM_burstKind$EN = + WILL_FIRE_RL_wsiM_reqFifo_deq && + wsiM_reqFifo_q_0[60:58] == 3'd1 && + (wsiM_burstKind == 2'd0 || + (wsiM_burstKind == 2'd1 || wsiM_burstKind == 2'd2) && + wsiM_reqFifo_q_0[57]) ; + + // register wsiM_errorSticky + assign wsiM_errorSticky$D_IN = 1'b0 ; + assign wsiM_errorSticky$EN = 1'b0 ; + + // register wsiM_iMesgCount + assign wsiM_iMesgCount$D_IN = wsiM_iMesgCount + 32'd1 ; + assign wsiM_iMesgCount$EN = + WILL_FIRE_RL_wsiM_reqFifo_deq && + wsiM_reqFifo_q_0[60:58] == 3'd1 && + wsiM_burstKind == 2'd2 && + wsiM_reqFifo_q_0[57] ; + + // register wsiM_isReset_isInReset + assign wsiM_isReset_isInReset$D_IN = 1'd0 ; + assign wsiM_isReset_isInReset$EN = wsiM_isReset_isInReset ; + + // register wsiM_operateD + assign wsiM_operateD$D_IN = wci_cState == 3'd2 ; + assign wsiM_operateD$EN = 1'd1 ; + + // register wsiM_pMesgCount + assign wsiM_pMesgCount$D_IN = wsiM_pMesgCount + 32'd1 ; + assign wsiM_pMesgCount$EN = + WILL_FIRE_RL_wsiM_reqFifo_deq && + wsiM_reqFifo_q_0[60:58] == 3'd1 && + wsiM_burstKind == 2'd1 && + wsiM_reqFifo_q_0[57] ; + + // register wsiM_peerIsReady + assign wsiM_peerIsReady$D_IN = wsiM0_SReset_n ; + assign wsiM_peerIsReady$EN = 1'd1 ; + + // register wsiM_reqFifo_c_r + assign wsiM_reqFifo_c_r$D_IN = + WILL_FIRE_RL_wsiM_reqFifo_incCtr ? + MUX_wsiM_reqFifo_c_r$write_1__VAL_1 : + MUX_wsiM_reqFifo_c_r$write_1__VAL_2 ; + assign wsiM_reqFifo_c_r$EN = + WILL_FIRE_RL_wsiM_reqFifo_incCtr || + WILL_FIRE_RL_wsiM_reqFifo_decCtr ; + + // register wsiM_reqFifo_q_0 + always@(WILL_FIRE_RL_wsiM_reqFifo_both or + MUX_wsiM_reqFifo_q_0$write_1__VAL_1 or + MUX_wsiM_reqFifo_q_0$write_1__SEL_2 or + wsiS_reqFifo$D_OUT or + WILL_FIRE_RL_wsiM_reqFifo_decCtr or wsiM_reqFifo_q_1) + begin + case (1'b1) // synopsys parallel_case + WILL_FIRE_RL_wsiM_reqFifo_both: + wsiM_reqFifo_q_0$D_IN = MUX_wsiM_reqFifo_q_0$write_1__VAL_1; + MUX_wsiM_reqFifo_q_0$write_1__SEL_2: + wsiM_reqFifo_q_0$D_IN = wsiS_reqFifo$D_OUT; + WILL_FIRE_RL_wsiM_reqFifo_decCtr: + wsiM_reqFifo_q_0$D_IN = wsiM_reqFifo_q_1; + default: wsiM_reqFifo_q_0$D_IN = + 61'h0AAAAAAAAAAAAAAA /* unspecified value */ ; + endcase + end + assign wsiM_reqFifo_q_0$EN = + WILL_FIRE_RL_wsiM_reqFifo_both || + WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_c_r == 2'd0 || + WILL_FIRE_RL_wsiM_reqFifo_decCtr ; + + // register wsiM_reqFifo_q_1 + always@(WILL_FIRE_RL_wsiM_reqFifo_both or + MUX_wsiM_reqFifo_q_1$write_1__VAL_1 or + MUX_wsiM_reqFifo_q_1$write_1__SEL_2 or + wsiS_reqFifo$D_OUT or WILL_FIRE_RL_wsiM_reqFifo_decCtr) + begin + case (1'b1) // synopsys parallel_case + WILL_FIRE_RL_wsiM_reqFifo_both: + wsiM_reqFifo_q_1$D_IN = MUX_wsiM_reqFifo_q_1$write_1__VAL_1; + MUX_wsiM_reqFifo_q_1$write_1__SEL_2: + wsiM_reqFifo_q_1$D_IN = wsiS_reqFifo$D_OUT; + WILL_FIRE_RL_wsiM_reqFifo_decCtr: + wsiM_reqFifo_q_1$D_IN = 61'h00000AAAAAAAAA00; + default: wsiM_reqFifo_q_1$D_IN = + 61'h0AAAAAAAAAAAAAAA /* unspecified value */ ; + endcase + end + assign wsiM_reqFifo_q_1$EN = + WILL_FIRE_RL_wsiM_reqFifo_both || + WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_c_r == 2'd1 || + WILL_FIRE_RL_wsiM_reqFifo_decCtr ; + + // register wsiM_sThreadBusy_d + assign wsiM_sThreadBusy_d$D_IN = wsiM0_SThreadBusy ; + assign wsiM_sThreadBusy_d$EN = 1'd1 ; + + // register wsiM_statusR + assign wsiM_statusR$D_IN = + { wsiM_isReset_isInReset, + !wsiM_peerIsReady, + !wsiM_operateD, + wsiM_errorSticky, + wsiM_burstKind != 2'd0, + wsiM_sThreadBusy_d, + 1'd0, + wsiM_trafficSticky } ; + assign wsiM_statusR$EN = 1'd1 ; + + // register wsiM_tBusyCount + assign wsiM_tBusyCount$D_IN = wsiM_tBusyCount + 32'd1 ; + assign wsiM_tBusyCount$EN = + wsiM_operateD && wsiM_peerIsReady && wsiM_sThreadBusy_d ; + + // register wsiM_trafficSticky + assign wsiM_trafficSticky$D_IN = 1'd1 ; + assign wsiM_trafficSticky$EN = + WILL_FIRE_RL_wsiM_reqFifo_deq && + wsiM_reqFifo_q_0[60:58] == 3'd1 ; + + // register wsiS_burstKind + assign wsiS_burstKind$D_IN = + (wsiS_burstKind == 2'd0) ? + (wsiS_wsiReq$wget[56] ? 2'd1 : 2'd2) : + 2'd0 ; + assign wsiS_burstKind$EN = + WILL_FIRE_RL_wsiS_reqFifo_enq && + (wsiS_burstKind == 2'd0 || + (wsiS_burstKind == 2'd1 || wsiS_burstKind == 2'd2) && + wsiS_wsiReq$wget[57]) ; + + // register wsiS_errorSticky + assign wsiS_errorSticky$D_IN = 1'b0 ; + assign wsiS_errorSticky$EN = 1'b0 ; + + // register wsiS_iMesgCount + assign wsiS_iMesgCount$D_IN = wsiS_iMesgCount + 32'd1 ; + assign wsiS_iMesgCount$EN = + WILL_FIRE_RL_wsiS_reqFifo_enq && wsiS_burstKind == 2'd2 && + wsiS_wsiReq$wget[57] ; + + // register wsiS_isReset_isInReset + assign wsiS_isReset_isInReset$D_IN = 1'd0 ; + assign wsiS_isReset_isInReset$EN = wsiS_isReset_isInReset ; + + // register wsiS_mesgWordLength + assign wsiS_mesgWordLength$D_IN = wsiS_wordCount ; + assign wsiS_mesgWordLength$EN = + WILL_FIRE_RL_wsiS_reqFifo_enq && wsiS_wsiReq$wget[57] ; + + // register wsiS_operateD + assign wsiS_operateD$D_IN = wci_cState == 3'd2 ; + assign wsiS_operateD$EN = 1'd1 ; + + // register wsiS_pMesgCount + assign wsiS_pMesgCount$D_IN = wsiS_pMesgCount + 32'd1 ; + assign wsiS_pMesgCount$EN = + WILL_FIRE_RL_wsiS_reqFifo_enq && wsiS_burstKind == 2'd1 && + wsiS_wsiReq$wget[57] ; + + // register wsiS_peerIsReady + assign wsiS_peerIsReady$D_IN = wsiS0_MReset_n ; + assign wsiS_peerIsReady$EN = 1'd1 ; + + // register wsiS_reqFifo_countReg + assign wsiS_reqFifo_countReg$D_IN = + WILL_FIRE_RL_wsiS_reqFifo_enq ? + wsiS_reqFifo_countReg + 2'd1 : + wsiS_reqFifo_countReg - 2'd1 ; + assign wsiS_reqFifo_countReg$EN = + WILL_FIRE_RL_wsiS_reqFifo_enq != + WILL_FIRE_RL_wsipass_doMessagePush ; + + // register wsiS_reqFifo_levelsValid + assign wsiS_reqFifo_levelsValid$D_IN = WILL_FIRE_RL_wsiS_reqFifo_reset ; + assign wsiS_reqFifo_levelsValid$EN = + WILL_FIRE_RL_wsipass_doMessagePush || + WILL_FIRE_RL_wsiS_reqFifo_enq || + WILL_FIRE_RL_wsiS_reqFifo_reset ; + + // register wsiS_statusR + assign wsiS_statusR$D_IN = + { wsiS_isReset_isInReset, + !wsiS_peerIsReady, + !wsiS_operateD, + wsiS_errorSticky, + wsiS_burstKind != 2'd0, + !wsiS_sThreadBusy_dw$whas || wsiS_sThreadBusy_dw$wget, + 1'd0, + wsiS_trafficSticky } ; + assign wsiS_statusR$EN = 1'd1 ; + + // register wsiS_tBusyCount + assign wsiS_tBusyCount$D_IN = wsiS_tBusyCount + 32'd1 ; + assign wsiS_tBusyCount$EN = + wsiS_operateD && wsiS_peerIsReady && + (!wsiS_sThreadBusy_dw$whas || wsiS_sThreadBusy_dw$wget) ; + + // register wsiS_trafficSticky + assign wsiS_trafficSticky$D_IN = 1'd1 ; + assign wsiS_trafficSticky$EN = WILL_FIRE_RL_wsiS_reqFifo_enq ; + + // register wsiS_wordCount + assign wsiS_wordCount$D_IN = + wsiS_wsiReq$wget[57] ? 12'd1 : wsiS_wordCount + 12'd1 ; + assign wsiS_wordCount$EN = WILL_FIRE_RL_wsiS_reqFifo_enq ; + + // submodule wci_reqF + assign wci_reqF$D_IN = wci_wciReq$wget ; + assign wci_reqF$ENQ = wci_wciReq$wget[71:69] != 3'd0 ; + assign wci_reqF$DEQ = wci_reqF_r_deq$whas ; + assign wci_reqF$CLR = 1'b0 ; + + // submodule wsiS_reqFifo + assign wsiS_reqFifo$D_IN = wsiS_wsiReq$wget ; + assign wsiS_reqFifo$ENQ = WILL_FIRE_RL_wsiS_reqFifo_enq ; + assign wsiS_reqFifo$DEQ = WILL_FIRE_RL_wsipass_doMessagePush ; + assign wsiS_reqFifo$CLR = 1'b0 ; + + // remaining internal signals + assign NOT_gated_99_05_AND_byteCount_06_EQ_frameSize__ETC___d439 = + !gated && byteCount == frameSize || + gated && byteCount == gateSize ; + assign frameGateStatus__h10551 = { 31'd0, hasDebugLogic } ; + assign rdat__h10963 = hasDebugLogic ? { 16'd0, x__h10967 } : 32'd0 ; + assign rdat__h11063 = hasDebugLogic ? wsiS_extStatusW$wget[95:64] : 32'd0 ; + assign rdat__h11077 = hasDebugLogic ? wsiS_extStatusW$wget[63:32] : 32'd0 ; + assign rdat__h11085 = hasDebugLogic ? wsiS_extStatusW$wget[31:0] : 32'd0 ; + assign rdat__h11091 = hasDebugLogic ? wsiM_extStatusW$wget[95:64] : 32'd0 ; + assign rdat__h11105 = hasDebugLogic ? wsiM_extStatusW$wget[63:32] : 32'd0 ; + assign rdat__h11113 = hasDebugLogic ? wsiM_extStatusW$wget[31:0] : 32'd0 ; + assign rdat__h11119 = hasDebugLogic ? op0MesgCnt : 32'd0 ; + assign rdat__h11130 = hasDebugLogic ? otherMesgCnt : 32'd0 ; + assign wsiS_reqFifo_i_notEmpty__92_AND_NOT_frameGateC_ETC___d303 = + wsiS_reqFifo$EMPTY_N && + (frameGateCtrl[3:0] != 4'h0 && + (frameGateCtrl[3:0] != 4'h1 || gated) || + wsiM_reqFifo_c_r != 2'd2) ; + assign x__h10327 = byteCount + 32'd4 ; + assign x__h10967 = { wsiS_statusR, wsiM_statusR } ; + always@(wci_reqF$D_OUT or + frameGateStatus__h10551 or + frameGateCtrl or + frameSize or + gateSize or + rdat__h10963 or + rdat__h11063 or + rdat__h11077 or + rdat__h11085 or + rdat__h11091 or + rdat__h11105 or rdat__h11113 or rdat__h11119 or rdat__h11130) + begin + case (wci_reqF$D_OUT[63:32]) + 32'h0: g_data__h10929 = frameGateStatus__h10551; + 32'h00000004: g_data__h10929 = frameGateCtrl; + 32'h00000008: g_data__h10929 = frameSize; + 32'h0000000C: g_data__h10929 = gateSize; + 32'h00000010: g_data__h10929 = rdat__h10963; + 32'h00000014: g_data__h10929 = rdat__h11063; + 32'h00000018: g_data__h10929 = rdat__h11077; + 32'h0000001C: g_data__h10929 = rdat__h11085; + 32'h00000020: g_data__h10929 = rdat__h11091; + 32'h00000024: g_data__h10929 = rdat__h11105; + 32'h00000028: g_data__h10929 = rdat__h11113; + 32'h0000002C: g_data__h10929 = rdat__h11119; + 32'h00000030: g_data__h10929 = rdat__h11130; + default: g_data__h10929 = 32'd0; + endcase + end + + // handling of inlined registers + + always@(posedge wciS0_Clk) + begin + if (wciS0_MReset_n == `BSV_RESET_VALUE) + begin + byteCount <= `BSV_ASSIGNMENT_DELAY 32'd4; + frameGateCtrl <= `BSV_ASSIGNMENT_DELAY fgCtrlInit; + frameSize <= `BSV_ASSIGNMENT_DELAY 32'd0; + gateSize <= `BSV_ASSIGNMENT_DELAY 32'd0; + gated <= `BSV_ASSIGNMENT_DELAY 1'd0; + op0MesgCnt <= `BSV_ASSIGNMENT_DELAY 32'd0; + otherMesgCnt <= `BSV_ASSIGNMENT_DELAY 32'd0; + wci_cEdge <= `BSV_ASSIGNMENT_DELAY 3'h2; + wci_cState <= `BSV_ASSIGNMENT_DELAY 3'd0; + wci_ctlAckReg <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_ctlOpActive <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_illegalEdge <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_nState <= `BSV_ASSIGNMENT_DELAY 3'd0; + wci_reqF_countReg <= `BSV_ASSIGNMENT_DELAY 2'd0; + wci_respF_c_r <= `BSV_ASSIGNMENT_DELAY 2'd0; + wci_respF_q_0 <= `BSV_ASSIGNMENT_DELAY 34'h0AAAAAAAA; + wci_respF_q_1 <= `BSV_ASSIGNMENT_DELAY 34'h0AAAAAAAA; + wci_sFlagReg <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY 1'd1; + wsiM_burstKind <= `BSV_ASSIGNMENT_DELAY 2'd0; + wsiM_errorSticky <= `BSV_ASSIGNMENT_DELAY 1'd0; + wsiM_iMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0; + wsiM_operateD <= `BSV_ASSIGNMENT_DELAY 1'd0; + wsiM_pMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0; + wsiM_peerIsReady <= `BSV_ASSIGNMENT_DELAY 1'd0; + wsiM_reqFifo_c_r <= `BSV_ASSIGNMENT_DELAY 2'd0; + wsiM_reqFifo_q_0 <= `BSV_ASSIGNMENT_DELAY 61'h00000AAAAAAAAA00; + wsiM_reqFifo_q_1 <= `BSV_ASSIGNMENT_DELAY 61'h00000AAAAAAAAA00; + wsiM_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY 1'd1; + wsiM_tBusyCount <= `BSV_ASSIGNMENT_DELAY 32'd0; + wsiM_trafficSticky <= `BSV_ASSIGNMENT_DELAY 1'd0; + wsiS_burstKind <= `BSV_ASSIGNMENT_DELAY 2'd0; + wsiS_errorSticky <= `BSV_ASSIGNMENT_DELAY 1'd0; + wsiS_iMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0; + wsiS_operateD <= `BSV_ASSIGNMENT_DELAY 1'd0; + wsiS_pMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0; + wsiS_peerIsReady <= `BSV_ASSIGNMENT_DELAY 1'd0; + wsiS_reqFifo_countReg <= `BSV_ASSIGNMENT_DELAY 2'd0; + wsiS_reqFifo_levelsValid <= `BSV_ASSIGNMENT_DELAY 1'd1; + wsiS_tBusyCount <= `BSV_ASSIGNMENT_DELAY 32'd0; + wsiS_trafficSticky <= `BSV_ASSIGNMENT_DELAY 1'd0; + wsiS_wordCount <= `BSV_ASSIGNMENT_DELAY 12'd1; + end + else + begin + if (byteCount$EN) byteCount <= `BSV_ASSIGNMENT_DELAY byteCount$D_IN; + if (frameGateCtrl$EN) + frameGateCtrl <= `BSV_ASSIGNMENT_DELAY frameGateCtrl$D_IN; + if (frameSize$EN) frameSize <= `BSV_ASSIGNMENT_DELAY frameSize$D_IN; + if (gateSize$EN) gateSize <= `BSV_ASSIGNMENT_DELAY gateSize$D_IN; + if (gated$EN) gated <= `BSV_ASSIGNMENT_DELAY gated$D_IN; + if (op0MesgCnt$EN) + op0MesgCnt <= `BSV_ASSIGNMENT_DELAY op0MesgCnt$D_IN; + if (otherMesgCnt$EN) + otherMesgCnt <= `BSV_ASSIGNMENT_DELAY otherMesgCnt$D_IN; + if (wci_cEdge$EN) wci_cEdge <= `BSV_ASSIGNMENT_DELAY wci_cEdge$D_IN; + if (wci_cState$EN) + wci_cState <= `BSV_ASSIGNMENT_DELAY wci_cState$D_IN; + if (wci_ctlAckReg$EN) + wci_ctlAckReg <= `BSV_ASSIGNMENT_DELAY wci_ctlAckReg$D_IN; + if (wci_ctlOpActive$EN) + wci_ctlOpActive <= `BSV_ASSIGNMENT_DELAY wci_ctlOpActive$D_IN; + if (wci_illegalEdge$EN) + wci_illegalEdge <= `BSV_ASSIGNMENT_DELAY wci_illegalEdge$D_IN; + if (wci_nState$EN) + wci_nState <= `BSV_ASSIGNMENT_DELAY wci_nState$D_IN; + if (wci_reqF_countReg$EN) + wci_reqF_countReg <= `BSV_ASSIGNMENT_DELAY wci_reqF_countReg$D_IN; + if (wci_respF_c_r$EN) + wci_respF_c_r <= `BSV_ASSIGNMENT_DELAY wci_respF_c_r$D_IN; + if (wci_respF_q_0$EN) + wci_respF_q_0 <= `BSV_ASSIGNMENT_DELAY wci_respF_q_0$D_IN; + if (wci_respF_q_1$EN) + wci_respF_q_1 <= `BSV_ASSIGNMENT_DELAY wci_respF_q_1$D_IN; + if (wci_sFlagReg$EN) + wci_sFlagReg <= `BSV_ASSIGNMENT_DELAY wci_sFlagReg$D_IN; + if (wci_sThreadBusy_d$EN) + wci_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY wci_sThreadBusy_d$D_IN; + if (wsiM_burstKind$EN) + wsiM_burstKind <= `BSV_ASSIGNMENT_DELAY wsiM_burstKind$D_IN; + if (wsiM_errorSticky$EN) + wsiM_errorSticky <= `BSV_ASSIGNMENT_DELAY wsiM_errorSticky$D_IN; + if (wsiM_iMesgCount$EN) + wsiM_iMesgCount <= `BSV_ASSIGNMENT_DELAY wsiM_iMesgCount$D_IN; + if (wsiM_operateD$EN) + wsiM_operateD <= `BSV_ASSIGNMENT_DELAY wsiM_operateD$D_IN; + if (wsiM_pMesgCount$EN) + wsiM_pMesgCount <= `BSV_ASSIGNMENT_DELAY wsiM_pMesgCount$D_IN; + if (wsiM_peerIsReady$EN) + wsiM_peerIsReady <= `BSV_ASSIGNMENT_DELAY wsiM_peerIsReady$D_IN; + if (wsiM_reqFifo_c_r$EN) + wsiM_reqFifo_c_r <= `BSV_ASSIGNMENT_DELAY wsiM_reqFifo_c_r$D_IN; + if (wsiM_reqFifo_q_0$EN) + wsiM_reqFifo_q_0 <= `BSV_ASSIGNMENT_DELAY wsiM_reqFifo_q_0$D_IN; + if (wsiM_reqFifo_q_1$EN) + wsiM_reqFifo_q_1 <= `BSV_ASSIGNMENT_DELAY wsiM_reqFifo_q_1$D_IN; + if (wsiM_sThreadBusy_d$EN) + wsiM_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY wsiM_sThreadBusy_d$D_IN; + if (wsiM_tBusyCount$EN) + wsiM_tBusyCount <= `BSV_ASSIGNMENT_DELAY wsiM_tBusyCount$D_IN; + if (wsiM_trafficSticky$EN) + wsiM_trafficSticky <= `BSV_ASSIGNMENT_DELAY wsiM_trafficSticky$D_IN; + if (wsiS_burstKind$EN) + wsiS_burstKind <= `BSV_ASSIGNMENT_DELAY wsiS_burstKind$D_IN; + if (wsiS_errorSticky$EN) + wsiS_errorSticky <= `BSV_ASSIGNMENT_DELAY wsiS_errorSticky$D_IN; + if (wsiS_iMesgCount$EN) + wsiS_iMesgCount <= `BSV_ASSIGNMENT_DELAY wsiS_iMesgCount$D_IN; + if (wsiS_operateD$EN) + wsiS_operateD <= `BSV_ASSIGNMENT_DELAY wsiS_operateD$D_IN; + if (wsiS_pMesgCount$EN) + wsiS_pMesgCount <= `BSV_ASSIGNMENT_DELAY wsiS_pMesgCount$D_IN; + if (wsiS_peerIsReady$EN) + wsiS_peerIsReady <= `BSV_ASSIGNMENT_DELAY wsiS_peerIsReady$D_IN; + if (wsiS_reqFifo_countReg$EN) + wsiS_reqFifo_countReg <= `BSV_ASSIGNMENT_DELAY + wsiS_reqFifo_countReg$D_IN; + if (wsiS_reqFifo_levelsValid$EN) + wsiS_reqFifo_levelsValid <= `BSV_ASSIGNMENT_DELAY + wsiS_reqFifo_levelsValid$D_IN; + if (wsiS_tBusyCount$EN) + wsiS_tBusyCount <= `BSV_ASSIGNMENT_DELAY wsiS_tBusyCount$D_IN; + if (wsiS_trafficSticky$EN) + wsiS_trafficSticky <= `BSV_ASSIGNMENT_DELAY wsiS_trafficSticky$D_IN; + if (wsiS_wordCount$EN) + wsiS_wordCount <= `BSV_ASSIGNMENT_DELAY wsiS_wordCount$D_IN; + end + if (wsiM_statusR$EN) + wsiM_statusR <= `BSV_ASSIGNMENT_DELAY wsiM_statusR$D_IN; + if (wsiS_mesgWordLength$EN) + wsiS_mesgWordLength <= `BSV_ASSIGNMENT_DELAY wsiS_mesgWordLength$D_IN; + if (wsiS_statusR$EN) + wsiS_statusR <= `BSV_ASSIGNMENT_DELAY wsiS_statusR$D_IN; + end + + always@(posedge wciS0_Clk or `BSV_RESET_EDGE wciS0_MReset_n) + if (wciS0_MReset_n == `BSV_RESET_VALUE) + begin + wci_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY 1'd1; + wsiM_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY 1'd1; + wsiS_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY 1'd1; + end + else + begin + if (wci_isReset_isInReset$EN) + wci_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY + wci_isReset_isInReset$D_IN; + if (wsiM_isReset_isInReset$EN) + wsiM_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY + wsiM_isReset_isInReset$D_IN; + if (wsiS_isReset_isInReset$EN) + wsiS_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY + wsiS_isReset_isInReset$D_IN; + end + + // synopsys translate_off + `ifdef BSV_NO_INITIAL_BLOCKS + `else // not BSV_NO_INITIAL_BLOCKS + initial + begin + byteCount = 32'hAAAAAAAA; + frameGateCtrl = 32'hAAAAAAAA; + frameSize = 32'hAAAAAAAA; + gateSize = 32'hAAAAAAAA; + gated = 1'h0; + op0MesgCnt = 32'hAAAAAAAA; + otherMesgCnt = 32'hAAAAAAAA; + wci_cEdge = 3'h2; + wci_cState = 3'h2; + wci_ctlAckReg = 1'h0; + wci_ctlOpActive = 1'h0; + wci_illegalEdge = 1'h0; + wci_isReset_isInReset = 1'h0; + wci_nState = 3'h2; + wci_reqF_countReg = 2'h2; + wci_respF_c_r = 2'h2; + wci_respF_q_0 = 34'h2AAAAAAAA; + wci_respF_q_1 = 34'h2AAAAAAAA; + wci_sFlagReg = 1'h0; + wci_sThreadBusy_d = 1'h0; + wsiM_burstKind = 2'h2; + wsiM_errorSticky = 1'h0; + wsiM_iMesgCount = 32'hAAAAAAAA; + wsiM_isReset_isInReset = 1'h0; + wsiM_operateD = 1'h0; + wsiM_pMesgCount = 32'hAAAAAAAA; + wsiM_peerIsReady = 1'h0; + wsiM_reqFifo_c_r = 2'h2; + wsiM_reqFifo_q_0 = 61'h0AAAAAAAAAAAAAAA; + wsiM_reqFifo_q_1 = 61'h0AAAAAAAAAAAAAAA; + wsiM_sThreadBusy_d = 1'h0; + wsiM_statusR = 8'hAA; + wsiM_tBusyCount = 32'hAAAAAAAA; + wsiM_trafficSticky = 1'h0; + wsiS_burstKind = 2'h2; + wsiS_errorSticky = 1'h0; + wsiS_iMesgCount = 32'hAAAAAAAA; + wsiS_isReset_isInReset = 1'h0; + wsiS_mesgWordLength = 12'hAAA; + wsiS_operateD = 1'h0; + wsiS_pMesgCount = 32'hAAAAAAAA; + wsiS_peerIsReady = 1'h0; + wsiS_reqFifo_countReg = 2'h2; + wsiS_reqFifo_levelsValid = 1'h0; + wsiS_statusR = 8'hAA; + wsiS_tBusyCount = 32'hAAAAAAAA; + wsiS_trafficSticky = 1'h0; + wsiS_wordCount = 12'hAAA; + end + `endif // BSV_NO_INITIAL_BLOCKS + // synopsys translate_on + + // handling of system tasks + + // synopsys translate_off + always@(negedge wciS0_Clk) + begin + #0; + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_ctl_op_start) + begin + v__h3701 = $time; + #0; + end + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_ctl_op_start) + $display("[%0d]: %m: WCI ControlOp: Starting-transition edge:%x from:%x", + v__h3701, + wci_reqF$D_OUT[36:34], + wci_cState); + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_ctrl_IsO) + begin + v__h11217 = $time; + #0; + end + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_ctrl_IsO) + $display("[%0d]: %m: Starting FrameGate frameGateCtrl:%0x", + v__h11217, + frameGateCtrl); + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_ctrl_IsO && WILL_FIRE_RL_wci_ctrl_OrE) + $display("Error: \"bsv/prm/FrameGate.bsv\", line 68, column 60: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_IsO] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n"); + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_ctrl_EiI && WILL_FIRE_RL_wci_ctrl_OrE) + $display("Error: \"bsv/prm/FrameGate.bsv\", line 68, column 46: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_EiI] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n"); + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_ctrl_EiI && WILL_FIRE_RL_wci_ctrl_IsO) + $display("Error: \"bsv/prm/FrameGate.bsv\", line 68, column 46: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_EiI] and\n [RL_wci_ctrl_IsO] ) fired in the same clock cycle.\n"); + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_ctl_op_complete && wci_illegalEdge) + begin + v__h4020 = $time; + #0; + end + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_ctl_op_complete && wci_illegalEdge) + $display("[%0d]: %m: WCI ControlOp: ILLEGAL-EDGE Completed-transition edge:%x from:%x", + v__h4020, + wci_cEdge, + wci_cState); + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_ctl_op_complete && !wci_illegalEdge) + begin + v__h3876 = $time; + #0; + end + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_ctl_op_complete && !wci_illegalEdge) + $display("[%0d]: %m: WCI ControlOp: Completed-transition edge:%x from:%x to:%x", + v__h3876, + wci_cEdge, + wci_cState, + wci_nState); + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_OrE) + $display("Error: \"bsv/prm/FrameGate.bsv\", line 68, column 26: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n"); + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_IsO) + $display("Error: \"bsv/prm/FrameGate.bsv\", line 68, column 26: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_wci_ctrl_IsO] ) fired in the same clock cycle.\n"); + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_EiI) + $display("Error: \"bsv/prm/FrameGate.bsv\", line 68, column 26: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_wci_ctrl_EiI] ) fired in the same clock cycle.\n"); + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_cfrd) + $display("Error: \"bsv/prm/FrameGate.bsv\", line 68, column 26: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and [RL_wci_cfrd] )\n fired in the same clock cycle.\n"); + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_cfrd && WILL_FIRE_RL_wci_ctrl_OrE) + $display("Error: \"bsv/prm/FrameGate.bsv\", line 68, column 36: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n"); + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_cfrd && WILL_FIRE_RL_wci_ctrl_IsO) + $display("Error: \"bsv/prm/FrameGate.bsv\", line 68, column 36: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n [RL_wci_ctrl_IsO] ) fired in the same clock cycle.\n"); + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_cfrd && WILL_FIRE_RL_wci_ctrl_EiI) + $display("Error: \"bsv/prm/FrameGate.bsv\", line 68, column 36: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n [RL_wci_ctrl_EiI] ) fired in the same clock cycle.\n"); + end + // synopsys translate_on +endmodule // mkFrameGate4B + diff --git a/rtl/mkFrameGate8B.v b/rtl/mkFrameGate8B.v new file mode 100644 index 00000000..70b40e71 --- /dev/null +++ b/rtl/mkFrameGate8B.v @@ -0,0 +1,1661 @@ +// +// Generated by Bluespec Compiler, version 2012.09.beta1 (build 29570, 2012-09.11) +// +// On Tue Jan 22 07:33:00 EST 2013 +// +// +// Ports: +// Name I/O size props +// wciS0_SResp O 2 reg +// wciS0_SData O 32 reg +// wciS0_SThreadBusy O 1 +// wciS0_SFlag O 2 +// wsiS0_SThreadBusy O 1 +// wsiS0_SReset_n O 1 +// wsiM0_MCmd O 3 +// wsiM0_MReqLast O 1 +// wsiM0_MBurstPrecise O 1 +// wsiM0_MBurstLength O 12 +// wsiM0_MData O 64 reg +// wsiM0_MByteEn O 8 reg +// wsiM0_MReqInfo O 8 +// wsiM0_MReset_n O 1 +// wciS0_Clk I 1 clock +// wciS0_MReset_n I 1 reset +// wciS0_MCmd I 3 +// wciS0_MAddrSpace I 1 +// wciS0_MByteEn I 4 +// wciS0_MAddr I 32 +// wciS0_MData I 32 +// wciS0_MFlag I 2 unused +// wsiS0_MCmd I 3 +// wsiS0_MBurstLength I 12 +// wsiS0_MData I 64 +// wsiS0_MByteEn I 8 +// wsiS0_MReqInfo I 8 +// wsiS0_MReqLast I 1 +// wsiS0_MBurstPrecise I 1 +// wsiS0_MReset_n I 1 reg +// wsiM0_SThreadBusy I 1 reg +// wsiM0_SReset_n I 1 reg +// +// No combinational paths from inputs to outputs +// +// + +`ifdef BSV_ASSIGNMENT_DELAY +`else + `define BSV_ASSIGNMENT_DELAY +`endif + +`ifdef BSV_POSITIVE_RESET + `define BSV_RESET_VALUE 1'b1 + `define BSV_RESET_EDGE posedge +`else + `define BSV_RESET_VALUE 1'b0 + `define BSV_RESET_EDGE negedge +`endif + +module mkFrameGate8B(wciS0_Clk, + wciS0_MReset_n, + + wciS0_MCmd, + + wciS0_MAddrSpace, + + wciS0_MByteEn, + + wciS0_MAddr, + + wciS0_MData, + + wciS0_SResp, + + wciS0_SData, + + wciS0_SThreadBusy, + + wciS0_SFlag, + + wciS0_MFlag, + + wsiS0_MCmd, + + wsiS0_MReqLast, + + wsiS0_MBurstPrecise, + + wsiS0_MBurstLength, + + wsiS0_MData, + + wsiS0_MByteEn, + + wsiS0_MReqInfo, + + wsiS0_SThreadBusy, + + wsiS0_SReset_n, + + wsiS0_MReset_n, + + wsiM0_MCmd, + + wsiM0_MReqLast, + + wsiM0_MBurstPrecise, + + wsiM0_MBurstLength, + + wsiM0_MData, + + wsiM0_MByteEn, + + wsiM0_MReqInfo, + + wsiM0_SThreadBusy, + + wsiM0_MReset_n, + + wsiM0_SReset_n); + parameter [31 : 0] fgCtrlInit = 32'b0; + parameter [0 : 0] hasDebugLogic = 1'b0; + input wciS0_Clk; + input wciS0_MReset_n; + + // action method wciS0_mCmd + input [2 : 0] wciS0_MCmd; + + // action method wciS0_mAddrSpace + input wciS0_MAddrSpace; + + // action method wciS0_mByteEn + input [3 : 0] wciS0_MByteEn; + + // action method wciS0_mAddr + input [31 : 0] wciS0_MAddr; + + // action method wciS0_mData + input [31 : 0] wciS0_MData; + + // value method wciS0_sResp + output [1 : 0] wciS0_SResp; + + // value method wciS0_sData + output [31 : 0] wciS0_SData; + + // value method wciS0_sThreadBusy + output wciS0_SThreadBusy; + + // value method wciS0_sFlag + output [1 : 0] wciS0_SFlag; + + // action method wciS0_mFlag + input [1 : 0] wciS0_MFlag; + + // action method wsiS0_mCmd + input [2 : 0] wsiS0_MCmd; + + // action method wsiS0_mReqLast + input wsiS0_MReqLast; + + // action method wsiS0_mBurstPrecise + input wsiS0_MBurstPrecise; + + // action method wsiS0_mBurstLength + input [11 : 0] wsiS0_MBurstLength; + + // action method wsiS0_mData + input [63 : 0] wsiS0_MData; + + // action method wsiS0_mByteEn + input [7 : 0] wsiS0_MByteEn; + + // action method wsiS0_mReqInfo + input [7 : 0] wsiS0_MReqInfo; + + // action method wsiS0_mDataInfo + + // value method wsiS0_sThreadBusy + output wsiS0_SThreadBusy; + + // value method wsiS0_sReset_n + output wsiS0_SReset_n; + + // action method wsiS0_mReset_n + input wsiS0_MReset_n; + + // value method wsiM0_mCmd + output [2 : 0] wsiM0_MCmd; + + // value method wsiM0_mReqLast + output wsiM0_MReqLast; + + // value method wsiM0_mBurstPrecise + output wsiM0_MBurstPrecise; + + // value method wsiM0_mBurstLength + output [11 : 0] wsiM0_MBurstLength; + + // value method wsiM0_mData + output [63 : 0] wsiM0_MData; + + // value method wsiM0_mByteEn + output [7 : 0] wsiM0_MByteEn; + + // value method wsiM0_mReqInfo + output [7 : 0] wsiM0_MReqInfo; + + // value method wsiM0_mDataInfo + + // action method wsiM0_sThreadBusy + input wsiM0_SThreadBusy; + + // value method wsiM0_mReset_n + output wsiM0_MReset_n; + + // action method wsiM0_sReset_n + input wsiM0_SReset_n; + + // signals for module outputs + wire [63 : 0] wsiM0_MData; + wire [31 : 0] wciS0_SData; + wire [11 : 0] wsiM0_MBurstLength; + wire [7 : 0] wsiM0_MByteEn, wsiM0_MReqInfo; + wire [2 : 0] wsiM0_MCmd; + wire [1 : 0] wciS0_SFlag, wciS0_SResp; + wire wciS0_SThreadBusy, + wsiM0_MBurstPrecise, + wsiM0_MReqLast, + wsiM0_MReset_n, + wsiS0_SReset_n, + wsiS0_SThreadBusy; + + // inlined wires + wire [96 : 0] wsiM_reqFifo_x_wire$wget, wsiS_wsiReq$wget; + wire [95 : 0] wsiM_extStatusW$wget, wsiS_extStatusW$wget; + wire [71 : 0] wci_wciReq$wget; + wire [63 : 0] wsi_Es_mData_w$wget; + wire [33 : 0] wci_respF_x_wire$wget; + wire [31 : 0] wci_Es_mAddr_w$wget, wci_Es_mData_w$wget; + wire [11 : 0] wsi_Es_mBurstLength_w$wget; + wire [7 : 0] wsi_Es_mByteEn_w$wget, wsi_Es_mReqInfo_w$wget; + wire [3 : 0] wci_Es_mByteEn_w$wget; + wire [2 : 0] wci_Es_mCmd_w$wget, wci_wEdge$wget, wsi_Es_mCmd_w$wget; + wire wci_Es_mAddrSpace_w$wget, + wci_Es_mAddrSpace_w$whas, + wci_Es_mAddr_w$whas, + wci_Es_mByteEn_w$whas, + wci_Es_mCmd_w$whas, + wci_Es_mData_w$whas, + wci_ctlAckReg_1$wget, + wci_ctlAckReg_1$whas, + wci_reqF_r_clr$whas, + wci_reqF_r_deq$whas, + wci_reqF_r_enq$whas, + wci_respF_dequeueing$whas, + wci_respF_enqueueing$whas, + wci_respF_x_wire$whas, + wci_sFlagReg_1$wget, + wci_sFlagReg_1$whas, + wci_sThreadBusy_pw$whas, + wci_wEdge$whas, + wci_wciReq$whas, + wci_wci_cfrd_pw$whas, + wci_wci_cfwr_pw$whas, + wci_wci_ctrl_pw$whas, + wsiM_operateD_1$wget, + wsiM_operateD_1$whas, + wsiM_peerIsReady_1$wget, + wsiM_peerIsReady_1$whas, + wsiM_reqFifo_dequeueing$whas, + wsiM_reqFifo_enqueueing$whas, + wsiM_reqFifo_x_wire$whas, + wsiM_sThreadBusy_pw$whas, + wsiS_operateD_1$wget, + wsiS_operateD_1$whas, + wsiS_peerIsReady_1$wget, + wsiS_peerIsReady_1$whas, + wsiS_reqFifo_doResetClr$whas, + wsiS_reqFifo_doResetDeq$whas, + wsiS_reqFifo_doResetEnq$whas, + wsiS_reqFifo_r_clr$whas, + wsiS_reqFifo_r_deq$whas, + wsiS_reqFifo_r_enq$whas, + wsiS_sThreadBusy_dw$wget, + wsiS_sThreadBusy_dw$whas, + wsiS_wsiReq$whas, + wsi_Es_mBurstLength_w$whas, + wsi_Es_mBurstPrecise_w$whas, + wsi_Es_mByteEn_w$whas, + wsi_Es_mCmd_w$whas, + wsi_Es_mDataInfo_w$whas, + wsi_Es_mData_w$whas, + wsi_Es_mReqInfo_w$whas, + wsi_Es_mReqLast_w$whas; + + // register byteCount + reg [31 : 0] byteCount; + wire [31 : 0] byteCount$D_IN; + wire byteCount$EN; + + // register frameGateCtrl + reg [31 : 0] frameGateCtrl; + wire [31 : 0] frameGateCtrl$D_IN; + wire frameGateCtrl$EN; + + // register frameSize + reg [31 : 0] frameSize; + wire [31 : 0] frameSize$D_IN; + wire frameSize$EN; + + // register gateSize + reg [31 : 0] gateSize; + wire [31 : 0] gateSize$D_IN; + wire gateSize$EN; + + // register gated + reg gated; + wire gated$D_IN, gated$EN; + + // register op0MesgCnt + reg [31 : 0] op0MesgCnt; + wire [31 : 0] op0MesgCnt$D_IN; + wire op0MesgCnt$EN; + + // register otherMesgCnt + reg [31 : 0] otherMesgCnt; + wire [31 : 0] otherMesgCnt$D_IN; + wire otherMesgCnt$EN; + + // register wci_cEdge + reg [2 : 0] wci_cEdge; + wire [2 : 0] wci_cEdge$D_IN; + wire wci_cEdge$EN; + + // register wci_cState + reg [2 : 0] wci_cState; + wire [2 : 0] wci_cState$D_IN; + wire wci_cState$EN; + + // register wci_ctlAckReg + reg wci_ctlAckReg; + wire wci_ctlAckReg$D_IN, wci_ctlAckReg$EN; + + // register wci_ctlOpActive + reg wci_ctlOpActive; + wire wci_ctlOpActive$D_IN, wci_ctlOpActive$EN; + + // register wci_illegalEdge + reg wci_illegalEdge; + wire wci_illegalEdge$D_IN, wci_illegalEdge$EN; + + // register wci_isReset_isInReset + reg wci_isReset_isInReset; + wire wci_isReset_isInReset$D_IN, wci_isReset_isInReset$EN; + + // register wci_nState + reg [2 : 0] wci_nState; + reg [2 : 0] wci_nState$D_IN; + wire wci_nState$EN; + + // register wci_reqF_countReg + reg [1 : 0] wci_reqF_countReg; + wire [1 : 0] wci_reqF_countReg$D_IN; + wire wci_reqF_countReg$EN; + + // register wci_respF_c_r + reg [1 : 0] wci_respF_c_r; + wire [1 : 0] wci_respF_c_r$D_IN; + wire wci_respF_c_r$EN; + + // register wci_respF_q_0 + reg [33 : 0] wci_respF_q_0; + reg [33 : 0] wci_respF_q_0$D_IN; + wire wci_respF_q_0$EN; + + // register wci_respF_q_1 + reg [33 : 0] wci_respF_q_1; + reg [33 : 0] wci_respF_q_1$D_IN; + wire wci_respF_q_1$EN; + + // register wci_sFlagReg + reg wci_sFlagReg; + wire wci_sFlagReg$D_IN, wci_sFlagReg$EN; + + // register wci_sThreadBusy_d + reg wci_sThreadBusy_d; + wire wci_sThreadBusy_d$D_IN, wci_sThreadBusy_d$EN; + + // register wsiM_burstKind + reg [1 : 0] wsiM_burstKind; + wire [1 : 0] wsiM_burstKind$D_IN; + wire wsiM_burstKind$EN; + + // register wsiM_errorSticky + reg wsiM_errorSticky; + wire wsiM_errorSticky$D_IN, wsiM_errorSticky$EN; + + // register wsiM_iMesgCount + reg [31 : 0] wsiM_iMesgCount; + wire [31 : 0] wsiM_iMesgCount$D_IN; + wire wsiM_iMesgCount$EN; + + // register wsiM_isReset_isInReset + reg wsiM_isReset_isInReset; + wire wsiM_isReset_isInReset$D_IN, wsiM_isReset_isInReset$EN; + + // register wsiM_operateD + reg wsiM_operateD; + wire wsiM_operateD$D_IN, wsiM_operateD$EN; + + // register wsiM_pMesgCount + reg [31 : 0] wsiM_pMesgCount; + wire [31 : 0] wsiM_pMesgCount$D_IN; + wire wsiM_pMesgCount$EN; + + // register wsiM_peerIsReady + reg wsiM_peerIsReady; + wire wsiM_peerIsReady$D_IN, wsiM_peerIsReady$EN; + + // register wsiM_reqFifo_c_r + reg [1 : 0] wsiM_reqFifo_c_r; + wire [1 : 0] wsiM_reqFifo_c_r$D_IN; + wire wsiM_reqFifo_c_r$EN; + + // register wsiM_reqFifo_q_0 + reg [96 : 0] wsiM_reqFifo_q_0; + reg [96 : 0] wsiM_reqFifo_q_0$D_IN; + wire wsiM_reqFifo_q_0$EN; + + // register wsiM_reqFifo_q_1 + reg [96 : 0] wsiM_reqFifo_q_1; + reg [96 : 0] wsiM_reqFifo_q_1$D_IN; + wire wsiM_reqFifo_q_1$EN; + + // register wsiM_sThreadBusy_d + reg wsiM_sThreadBusy_d; + wire wsiM_sThreadBusy_d$D_IN, wsiM_sThreadBusy_d$EN; + + // register wsiM_statusR + reg [7 : 0] wsiM_statusR; + wire [7 : 0] wsiM_statusR$D_IN; + wire wsiM_statusR$EN; + + // register wsiM_tBusyCount + reg [31 : 0] wsiM_tBusyCount; + wire [31 : 0] wsiM_tBusyCount$D_IN; + wire wsiM_tBusyCount$EN; + + // register wsiM_trafficSticky + reg wsiM_trafficSticky; + wire wsiM_trafficSticky$D_IN, wsiM_trafficSticky$EN; + + // register wsiS_burstKind + reg [1 : 0] wsiS_burstKind; + wire [1 : 0] wsiS_burstKind$D_IN; + wire wsiS_burstKind$EN; + + // register wsiS_errorSticky + reg wsiS_errorSticky; + wire wsiS_errorSticky$D_IN, wsiS_errorSticky$EN; + + // register wsiS_iMesgCount + reg [31 : 0] wsiS_iMesgCount; + wire [31 : 0] wsiS_iMesgCount$D_IN; + wire wsiS_iMesgCount$EN; + + // register wsiS_isReset_isInReset + reg wsiS_isReset_isInReset; + wire wsiS_isReset_isInReset$D_IN, wsiS_isReset_isInReset$EN; + + // register wsiS_mesgWordLength + reg [11 : 0] wsiS_mesgWordLength; + wire [11 : 0] wsiS_mesgWordLength$D_IN; + wire wsiS_mesgWordLength$EN; + + // register wsiS_operateD + reg wsiS_operateD; + wire wsiS_operateD$D_IN, wsiS_operateD$EN; + + // register wsiS_pMesgCount + reg [31 : 0] wsiS_pMesgCount; + wire [31 : 0] wsiS_pMesgCount$D_IN; + wire wsiS_pMesgCount$EN; + + // register wsiS_peerIsReady + reg wsiS_peerIsReady; + wire wsiS_peerIsReady$D_IN, wsiS_peerIsReady$EN; + + // register wsiS_reqFifo_countReg + reg [1 : 0] wsiS_reqFifo_countReg; + wire [1 : 0] wsiS_reqFifo_countReg$D_IN; + wire wsiS_reqFifo_countReg$EN; + + // register wsiS_reqFifo_levelsValid + reg wsiS_reqFifo_levelsValid; + wire wsiS_reqFifo_levelsValid$D_IN, wsiS_reqFifo_levelsValid$EN; + + // register wsiS_statusR + reg [7 : 0] wsiS_statusR; + wire [7 : 0] wsiS_statusR$D_IN; + wire wsiS_statusR$EN; + + // register wsiS_tBusyCount + reg [31 : 0] wsiS_tBusyCount; + wire [31 : 0] wsiS_tBusyCount$D_IN; + wire wsiS_tBusyCount$EN; + + // register wsiS_trafficSticky + reg wsiS_trafficSticky; + wire wsiS_trafficSticky$D_IN, wsiS_trafficSticky$EN; + + // register wsiS_wordCount + reg [11 : 0] wsiS_wordCount; + wire [11 : 0] wsiS_wordCount$D_IN; + wire wsiS_wordCount$EN; + + // ports of submodule wci_reqF + wire [71 : 0] wci_reqF$D_IN, wci_reqF$D_OUT; + wire wci_reqF$CLR, wci_reqF$DEQ, wci_reqF$EMPTY_N, wci_reqF$ENQ; + + // ports of submodule wsiS_reqFifo + wire [96 : 0] wsiS_reqFifo$D_IN, wsiS_reqFifo$D_OUT; + wire wsiS_reqFifo$CLR, + wsiS_reqFifo$DEQ, + wsiS_reqFifo$EMPTY_N, + wsiS_reqFifo$ENQ, + wsiS_reqFifo$FULL_N; + + // rule scheduling signals + wire WILL_FIRE_RL_wci_cfrd, + WILL_FIRE_RL_wci_cfwr, + WILL_FIRE_RL_wci_ctl_op_complete, + WILL_FIRE_RL_wci_ctl_op_start, + WILL_FIRE_RL_wci_ctrl_EiI, + WILL_FIRE_RL_wci_ctrl_IsO, + WILL_FIRE_RL_wci_ctrl_OrE, + WILL_FIRE_RL_wci_respF_both, + WILL_FIRE_RL_wci_respF_decCtr, + WILL_FIRE_RL_wci_respF_incCtr, + WILL_FIRE_RL_wsiM_reqFifo_both, + WILL_FIRE_RL_wsiM_reqFifo_decCtr, + WILL_FIRE_RL_wsiM_reqFifo_deq, + WILL_FIRE_RL_wsiM_reqFifo_incCtr, + WILL_FIRE_RL_wsiS_reqFifo_enq, + WILL_FIRE_RL_wsiS_reqFifo_reset, + WILL_FIRE_RL_wsipass_doMessagePush; + + // inputs to muxes for submodule ports + reg [33 : 0] MUX_wci_respF_q_0$write_1__VAL_2; + wire [96 : 0] MUX_wsiM_reqFifo_q_0$write_1__VAL_1, + MUX_wsiM_reqFifo_q_1$write_1__VAL_1; + wire [33 : 0] MUX_wci_respF_q_0$write_1__VAL_1, + MUX_wci_respF_q_1$write_1__VAL_1, + MUX_wci_respF_x_wire$wset_1__VAL_1, + MUX_wci_respF_x_wire$wset_1__VAL_2; + wire [1 : 0] MUX_wci_respF_c_r$write_1__VAL_1, + MUX_wci_respF_c_r$write_1__VAL_2, + MUX_wsiM_reqFifo_c_r$write_1__VAL_1, + MUX_wsiM_reqFifo_c_r$write_1__VAL_2; + wire MUX_wci_illegalEdge$write_1__SEL_1, + MUX_wci_illegalEdge$write_1__SEL_2, + MUX_wci_illegalEdge$write_1__VAL_2, + MUX_wci_respF_q_0$write_1__SEL_2, + MUX_wci_respF_q_1$write_1__SEL_2, + MUX_wsiM_reqFifo_q_0$write_1__SEL_2, + MUX_wsiM_reqFifo_q_1$write_1__SEL_2; + + // remaining internal signals + reg [63 : 0] v__h11217, v__h3701, v__h3876, v__h4020; + reg [31 : 0] g_data__h10929; + wire [31 : 0] frameGateStatus__h10551, + rdat__h10963, + rdat__h11063, + rdat__h11077, + rdat__h11085, + rdat__h11091, + rdat__h11105, + rdat__h11113, + rdat__h11119, + rdat__h11130, + x__h10327; + wire [15 : 0] x__h10967; + wire NOT_gated_99_05_AND_byteCount_06_EQ_frameSize__ETC___d439, + wsiS_reqFifo_i_notEmpty__92_AND_NOT_frameGateC_ETC___d303; + + // value method wciS0_sResp + assign wciS0_SResp = wci_respF_q_0[33:32] ; + + // value method wciS0_sData + assign wciS0_SData = wci_respF_q_0[31:0] ; + + // value method wciS0_sThreadBusy + assign wciS0_SThreadBusy = + wci_reqF_countReg > 2'd1 || wci_isReset_isInReset ; + + // value method wciS0_sFlag + assign wciS0_SFlag = { 1'd1, wci_sFlagReg } ; + + // value method wsiS0_sThreadBusy + assign wsiS0_SThreadBusy = + !wsiS_sThreadBusy_dw$whas || wsiS_sThreadBusy_dw$wget ; + + // value method wsiS0_sReset_n + assign wsiS0_SReset_n = !wsiS_isReset_isInReset && wsiS_operateD ; + + // value method wsiM0_mCmd + assign wsiM0_MCmd = wsiM_sThreadBusy_d ? 3'd0 : wsiM_reqFifo_q_0[96:94] ; + + // value method wsiM0_mReqLast + assign wsiM0_MReqLast = !wsiM_sThreadBusy_d && wsiM_reqFifo_q_0[93] ; + + // value method wsiM0_mBurstPrecise + assign wsiM0_MBurstPrecise = !wsiM_sThreadBusy_d && wsiM_reqFifo_q_0[92] ; + + // value method wsiM0_mBurstLength + assign wsiM0_MBurstLength = + wsiM_sThreadBusy_d ? 12'd0 : wsiM_reqFifo_q_0[91:80] ; + + // value method wsiM0_mData + assign wsiM0_MData = wsiM_reqFifo_q_0[79:16] ; + + // value method wsiM0_mByteEn + assign wsiM0_MByteEn = wsiM_reqFifo_q_0[15:8] ; + + // value method wsiM0_mReqInfo + assign wsiM0_MReqInfo = wsiM_sThreadBusy_d ? 8'd0 : wsiM_reqFifo_q_0[7:0] ; + + // value method wsiM0_mReset_n + assign wsiM0_MReset_n = !wsiM_isReset_isInReset && wsiM_operateD ; + + // submodule wci_reqF + SizedFIFO #(.p1width(32'd72), + .p2depth(32'd3), + .p3cntr_width(32'd1), + .guarded(32'd1)) wci_reqF(.RST(wciS0_MReset_n), + .CLK(wciS0_Clk), + .D_IN(wci_reqF$D_IN), + .ENQ(wci_reqF$ENQ), + .DEQ(wci_reqF$DEQ), + .CLR(wci_reqF$CLR), + .D_OUT(wci_reqF$D_OUT), + .FULL_N(), + .EMPTY_N(wci_reqF$EMPTY_N)); + + // submodule wsiS_reqFifo + SizedFIFO #(.p1width(32'd97), + .p2depth(32'd3), + .p3cntr_width(32'd1), + .guarded(32'd1)) wsiS_reqFifo(.RST(wciS0_MReset_n), + .CLK(wciS0_Clk), + .D_IN(wsiS_reqFifo$D_IN), + .ENQ(wsiS_reqFifo$ENQ), + .DEQ(wsiS_reqFifo$DEQ), + .CLR(wsiS_reqFifo$CLR), + .D_OUT(wsiS_reqFifo$D_OUT), + .FULL_N(wsiS_reqFifo$FULL_N), + .EMPTY_N(wsiS_reqFifo$EMPTY_N)); + + // rule RL_wci_ctl_op_start + assign WILL_FIRE_RL_wci_ctl_op_start = + wci_reqF$EMPTY_N && wci_wci_ctrl_pw$whas && + !WILL_FIRE_RL_wci_ctl_op_complete ; + + // rule RL_wci_ctrl_IsO + assign WILL_FIRE_RL_wci_ctrl_IsO = + wci_wci_ctrl_pw$whas && WILL_FIRE_RL_wci_ctl_op_start && + wci_cState == 3'd1 && + wci_reqF$D_OUT[36:34] == 3'd1 ; + + // rule RL_wci_ctrl_EiI + assign WILL_FIRE_RL_wci_ctrl_EiI = + wci_wci_ctrl_pw$whas && WILL_FIRE_RL_wci_ctl_op_start && + wci_cState == 3'd0 && + wci_reqF$D_OUT[36:34] == 3'd0 ; + + // rule RL_wci_ctrl_OrE + assign WILL_FIRE_RL_wci_ctrl_OrE = + wci_wci_ctrl_pw$whas && WILL_FIRE_RL_wci_ctl_op_start && + wci_cState == 3'd2 && + wci_reqF$D_OUT[36:34] == 3'd3 ; + + // rule RL_wsipass_doMessagePush + assign WILL_FIRE_RL_wsipass_doMessagePush = + wsiS_reqFifo_i_notEmpty__92_AND_NOT_frameGateC_ETC___d303 && + wci_cState == 3'd2 ; + + // rule RL_wci_cfwr + assign WILL_FIRE_RL_wci_cfwr = + wci_respF_c_r != 2'd2 && wci_reqF$EMPTY_N && + wci_wci_cfwr_pw$whas && + !WILL_FIRE_RL_wci_ctl_op_start && + !WILL_FIRE_RL_wci_ctl_op_complete ; + + // rule RL_wci_ctl_op_complete + assign WILL_FIRE_RL_wci_ctl_op_complete = + wci_respF_c_r != 2'd2 && wci_ctlOpActive && wci_ctlAckReg ; + + // rule RL_wci_cfrd + assign WILL_FIRE_RL_wci_cfrd = + wci_respF_c_r != 2'd2 && wci_reqF$EMPTY_N && + wci_wci_cfrd_pw$whas && + !WILL_FIRE_RL_wci_ctl_op_start && + !WILL_FIRE_RL_wci_ctl_op_complete ; + + // rule RL_wci_respF_incCtr + assign WILL_FIRE_RL_wci_respF_incCtr = + ((wci_respF_c_r == 2'd0) ? + wci_respF_enqueueing$whas : + wci_respF_c_r != 2'd1 || wci_respF_enqueueing$whas) && + wci_respF_enqueueing$whas && + !(wci_respF_c_r != 2'd0) ; + + // rule RL_wci_respF_decCtr + assign WILL_FIRE_RL_wci_respF_decCtr = + wci_respF_c_r != 2'd0 && !wci_respF_enqueueing$whas ; + + // rule RL_wci_respF_both + assign WILL_FIRE_RL_wci_respF_both = + ((wci_respF_c_r == 2'd1) ? + wci_respF_enqueueing$whas : + wci_respF_c_r != 2'd2 || wci_respF_enqueueing$whas) && + wci_respF_c_r != 2'd0 && + wci_respF_enqueueing$whas ; + + // rule RL_wsiM_reqFifo_deq + assign WILL_FIRE_RL_wsiM_reqFifo_deq = + wsiM_reqFifo_c_r != 2'd0 && !wsiM_sThreadBusy_d ; + + // rule RL_wsiM_reqFifo_incCtr + assign WILL_FIRE_RL_wsiM_reqFifo_incCtr = + ((wsiM_reqFifo_c_r == 2'd0) ? + wsiM_reqFifo_enqueueing$whas : + wsiM_reqFifo_c_r != 2'd1 || wsiM_reqFifo_enqueueing$whas) && + wsiM_reqFifo_enqueueing$whas && + !WILL_FIRE_RL_wsiM_reqFifo_deq ; + + // rule RL_wsiM_reqFifo_decCtr + assign WILL_FIRE_RL_wsiM_reqFifo_decCtr = + WILL_FIRE_RL_wsiM_reqFifo_deq && !wsiM_reqFifo_enqueueing$whas ; + + // rule RL_wsiM_reqFifo_both + assign WILL_FIRE_RL_wsiM_reqFifo_both = + ((wsiM_reqFifo_c_r == 2'd1) ? + wsiM_reqFifo_enqueueing$whas : + wsiM_reqFifo_c_r != 2'd2 || wsiM_reqFifo_enqueueing$whas) && + WILL_FIRE_RL_wsiM_reqFifo_deq && + wsiM_reqFifo_enqueueing$whas ; + + // rule RL_wsiS_reqFifo_enq + assign WILL_FIRE_RL_wsiS_reqFifo_enq = + wsiS_reqFifo$FULL_N && wsiS_operateD && wsiS_peerIsReady && + wsiS_wsiReq$wget[96:94] == 3'd1 ; + + // rule RL_wsiS_reqFifo_reset + assign WILL_FIRE_RL_wsiS_reqFifo_reset = + WILL_FIRE_RL_wsiS_reqFifo_enq || + WILL_FIRE_RL_wsipass_doMessagePush ; + + // inputs to muxes for submodule ports + assign MUX_wci_illegalEdge$write_1__SEL_1 = + WILL_FIRE_RL_wci_ctl_op_complete && wci_illegalEdge ; + assign MUX_wci_illegalEdge$write_1__SEL_2 = + WILL_FIRE_RL_wci_ctl_op_start && + (wci_reqF$D_OUT[36:34] == 3'd0 && wci_cState != 3'd0 || + wci_reqF$D_OUT[36:34] == 3'd1 && wci_cState != 3'd1 && + wci_cState != 3'd3 || + wci_reqF$D_OUT[36:34] == 3'd2 && wci_cState != 3'd2 || + wci_reqF$D_OUT[36:34] == 3'd3 && wci_cState != 3'd3 && + wci_cState != 3'd2 && + wci_cState != 3'd1 || + wci_reqF$D_OUT[36:34] == 3'd4 || + wci_reqF$D_OUT[36:34] == 3'd5 || + wci_reqF$D_OUT[36:34] == 3'd6 || + wci_reqF$D_OUT[36:34] == 3'd7) ; + assign MUX_wci_respF_q_0$write_1__SEL_2 = + WILL_FIRE_RL_wci_respF_incCtr && wci_respF_c_r == 2'd0 ; + assign MUX_wci_respF_q_1$write_1__SEL_2 = + WILL_FIRE_RL_wci_respF_incCtr && wci_respF_c_r == 2'd1 ; + assign MUX_wsiM_reqFifo_q_0$write_1__SEL_2 = + WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_c_r == 2'd0 ; + assign MUX_wsiM_reqFifo_q_1$write_1__SEL_2 = + WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_c_r == 2'd1 ; + assign MUX_wci_illegalEdge$write_1__VAL_2 = + wci_reqF$D_OUT[36:34] != 3'd4 && wci_reqF$D_OUT[36:34] != 3'd5 && + wci_reqF$D_OUT[36:34] != 3'd6 ; + assign MUX_wci_respF_c_r$write_1__VAL_1 = wci_respF_c_r + 2'd1 ; + assign MUX_wci_respF_c_r$write_1__VAL_2 = wci_respF_c_r - 2'd1 ; + assign MUX_wci_respF_q_0$write_1__VAL_1 = + (wci_respF_c_r == 2'd1) ? + MUX_wci_respF_q_0$write_1__VAL_2 : + wci_respF_q_1 ; + always@(WILL_FIRE_RL_wci_ctl_op_complete or + MUX_wci_respF_x_wire$wset_1__VAL_1 or + WILL_FIRE_RL_wci_cfrd or + MUX_wci_respF_x_wire$wset_1__VAL_2 or WILL_FIRE_RL_wci_cfwr) + begin + case (1'b1) // synopsys parallel_case + WILL_FIRE_RL_wci_ctl_op_complete: + MUX_wci_respF_q_0$write_1__VAL_2 = + MUX_wci_respF_x_wire$wset_1__VAL_1; + WILL_FIRE_RL_wci_cfrd: + MUX_wci_respF_q_0$write_1__VAL_2 = + MUX_wci_respF_x_wire$wset_1__VAL_2; + WILL_FIRE_RL_wci_cfwr: MUX_wci_respF_q_0$write_1__VAL_2 = 34'h1C0DE4201; + default: MUX_wci_respF_q_0$write_1__VAL_2 = + 34'h2AAAAAAAA /* unspecified value */ ; + endcase + end + assign MUX_wci_respF_q_1$write_1__VAL_1 = + (wci_respF_c_r == 2'd2) ? + MUX_wci_respF_q_0$write_1__VAL_2 : + 34'h0AAAAAAAA ; + assign MUX_wci_respF_x_wire$wset_1__VAL_1 = + wci_illegalEdge ? 34'h3C0DE4202 : 34'h1C0DE4201 ; + assign MUX_wci_respF_x_wire$wset_1__VAL_2 = { 2'd1, g_data__h10929 } ; + assign MUX_wsiM_reqFifo_c_r$write_1__VAL_1 = wsiM_reqFifo_c_r + 2'd1 ; + assign MUX_wsiM_reqFifo_c_r$write_1__VAL_2 = wsiM_reqFifo_c_r - 2'd1 ; + assign MUX_wsiM_reqFifo_q_0$write_1__VAL_1 = + (wsiM_reqFifo_c_r == 2'd1) ? + wsiS_reqFifo$D_OUT : + wsiM_reqFifo_q_1 ; + assign MUX_wsiM_reqFifo_q_1$write_1__VAL_1 = + (wsiM_reqFifo_c_r == 2'd2) ? + wsiS_reqFifo$D_OUT : + 97'h00000AAAAAAAAAAAAAAAAAA00 ; + + // inlined wires + assign wci_wciReq$wget = + { wciS0_MCmd, + wciS0_MAddrSpace, + wciS0_MByteEn, + wciS0_MAddr, + wciS0_MData } ; + assign wci_wciReq$whas = 1'd1 ; + assign wci_respF_x_wire$wget = MUX_wci_respF_q_0$write_1__VAL_2 ; + assign wci_respF_x_wire$whas = wci_respF_enqueueing$whas ; + assign wci_wEdge$wget = wci_reqF$D_OUT[36:34] ; + assign wci_wEdge$whas = WILL_FIRE_RL_wci_ctl_op_start ; + assign wci_sFlagReg_1$wget = 1'b0 ; + assign wci_sFlagReg_1$whas = 1'b0 ; + assign wci_ctlAckReg_1$wget = 1'd1 ; + assign wci_ctlAckReg_1$whas = + WILL_FIRE_RL_wci_ctrl_OrE || WILL_FIRE_RL_wci_ctrl_IsO || + WILL_FIRE_RL_wci_ctrl_EiI ; + assign wsiS_wsiReq$wget = + { wsiS0_MCmd, + wsiS0_MReqLast, + wsiS0_MBurstPrecise, + wsiS0_MBurstLength, + wsiS0_MData, + wsiS0_MByteEn, + wsiS0_MReqInfo } ; + assign wsiS_wsiReq$whas = 1'd1 ; + assign wsiS_operateD_1$wget = 1'd1 ; + assign wsiS_operateD_1$whas = wci_cState == 3'd2 ; + assign wsiS_peerIsReady_1$wget = 1'd1 ; + assign wsiS_peerIsReady_1$whas = wsiS0_MReset_n ; + assign wsiS_sThreadBusy_dw$wget = wsiS_reqFifo_countReg > 2'd1 ; + assign wsiS_sThreadBusy_dw$whas = + wsiS_reqFifo_levelsValid && wsiS_operateD && wsiS_peerIsReady ; + assign wsiM_reqFifo_x_wire$wget = wsiS_reqFifo$D_OUT ; + assign wsiM_reqFifo_x_wire$whas = wsiM_reqFifo_enqueueing$whas ; + assign wsiM_operateD_1$wget = 1'd1 ; + assign wsiM_operateD_1$whas = wci_cState == 3'd2 ; + assign wsiM_peerIsReady_1$wget = 1'd1 ; + assign wsiM_peerIsReady_1$whas = wsiM0_SReset_n ; + assign wci_Es_mCmd_w$wget = wciS0_MCmd ; + assign wci_Es_mCmd_w$whas = 1'd1 ; + assign wci_Es_mAddrSpace_w$wget = wciS0_MAddrSpace ; + assign wci_Es_mAddrSpace_w$whas = 1'd1 ; + assign wci_Es_mByteEn_w$wget = wciS0_MByteEn ; + assign wci_Es_mByteEn_w$whas = 1'd1 ; + assign wci_Es_mAddr_w$wget = wciS0_MAddr ; + assign wci_Es_mAddr_w$whas = 1'd1 ; + assign wci_Es_mData_w$wget = wciS0_MData ; + assign wci_Es_mData_w$whas = 1'd1 ; + assign wsi_Es_mCmd_w$wget = wsiS0_MCmd ; + assign wsi_Es_mCmd_w$whas = 1'd1 ; + assign wsi_Es_mBurstLength_w$wget = wsiS0_MBurstLength ; + assign wsi_Es_mBurstLength_w$whas = 1'd1 ; + assign wsi_Es_mData_w$wget = wsiS0_MData ; + assign wsi_Es_mData_w$whas = 1'd1 ; + assign wsi_Es_mByteEn_w$wget = wsiS0_MByteEn ; + assign wsi_Es_mByteEn_w$whas = 1'd1 ; + assign wsi_Es_mReqInfo_w$wget = wsiS0_MReqInfo ; + assign wsi_Es_mReqInfo_w$whas = 1'd1 ; + assign wci_reqF_r_enq$whas = wci_wciReq$wget[71:69] != 3'd0 ; + assign wci_reqF_r_deq$whas = + WILL_FIRE_RL_wci_ctl_op_start || WILL_FIRE_RL_wci_cfrd || + WILL_FIRE_RL_wci_cfwr ; + assign wci_reqF_r_clr$whas = 1'b0 ; + assign wci_respF_enqueueing$whas = + WILL_FIRE_RL_wci_ctl_op_complete || WILL_FIRE_RL_wci_cfrd || + WILL_FIRE_RL_wci_cfwr ; + assign wci_respF_dequeueing$whas = wci_respF_c_r != 2'd0 ; + assign wci_sThreadBusy_pw$whas = 1'b0 ; + assign wci_wci_cfwr_pw$whas = + wci_reqF$EMPTY_N && wci_reqF$D_OUT[68] && + wci_reqF$D_OUT[71:69] == 3'd1 ; + assign wci_wci_cfrd_pw$whas = + wci_reqF$EMPTY_N && wci_reqF$D_OUT[68] && + wci_reqF$D_OUT[71:69] == 3'd2 ; + assign wci_wci_ctrl_pw$whas = + wci_reqF$EMPTY_N && !wci_reqF$D_OUT[68] && + wci_reqF$D_OUT[71:69] == 3'd2 ; + assign wsiS_reqFifo_r_enq$whas = WILL_FIRE_RL_wsiS_reqFifo_enq ; + assign wsiS_reqFifo_r_deq$whas = WILL_FIRE_RL_wsipass_doMessagePush ; + assign wsiS_reqFifo_r_clr$whas = 1'b0 ; + assign wsiS_reqFifo_doResetEnq$whas = WILL_FIRE_RL_wsiS_reqFifo_enq ; + assign wsiS_reqFifo_doResetDeq$whas = WILL_FIRE_RL_wsipass_doMessagePush ; + assign wsiS_reqFifo_doResetClr$whas = 1'b0 ; + assign wsiM_reqFifo_enqueueing$whas = + WILL_FIRE_RL_wsipass_doMessagePush && + (frameGateCtrl[3:0] == 4'h0 || + frameGateCtrl[3:0] == 4'h1 && !gated) ; + assign wsiM_reqFifo_dequeueing$whas = WILL_FIRE_RL_wsiM_reqFifo_deq ; + assign wsiM_sThreadBusy_pw$whas = wsiM0_SThreadBusy ; + assign wsi_Es_mReqLast_w$whas = wsiS0_MReqLast ; + assign wsi_Es_mBurstPrecise_w$whas = wsiS0_MBurstPrecise ; + assign wsi_Es_mDataInfo_w$whas = 1'd1 ; + assign wsiS_extStatusW$wget = + { wsiS_pMesgCount, wsiS_iMesgCount, wsiS_tBusyCount } ; + assign wsiM_extStatusW$wget = + { wsiM_pMesgCount, wsiM_iMesgCount, wsiM_tBusyCount } ; + + // register byteCount + assign byteCount$D_IN = + NOT_gated_99_05_AND_byteCount_06_EQ_frameSize__ETC___d439 ? + 32'd8 : + x__h10327 ; + assign byteCount$EN = WILL_FIRE_RL_wsipass_doMessagePush ; + + // register frameGateCtrl + assign frameGateCtrl$D_IN = wci_reqF$D_OUT[31:0] ; + assign frameGateCtrl$EN = + WILL_FIRE_RL_wci_cfwr && wci_reqF$D_OUT[63:32] == 32'h00000004 ; + + // register frameSize + assign frameSize$D_IN = wci_reqF$D_OUT[31:0] ; + assign frameSize$EN = + WILL_FIRE_RL_wci_cfwr && wci_reqF$D_OUT[63:32] == 32'h00000008 ; + + // register gateSize + assign gateSize$D_IN = wci_reqF$D_OUT[31:0] ; + assign gateSize$EN = + WILL_FIRE_RL_wci_cfwr && wci_reqF$D_OUT[63:32] == 32'h0000000C ; + + // register gated + assign gated$D_IN = !gated && byteCount == frameSize ; + assign gated$EN = + WILL_FIRE_RL_wsipass_doMessagePush && + NOT_gated_99_05_AND_byteCount_06_EQ_frameSize__ETC___d439 ; + + // register op0MesgCnt + assign op0MesgCnt$D_IN = 32'h0 ; + assign op0MesgCnt$EN = 1'b0 ; + + // register otherMesgCnt + assign otherMesgCnt$D_IN = 32'h0 ; + assign otherMesgCnt$EN = 1'b0 ; + + // register wci_cEdge + assign wci_cEdge$D_IN = wci_reqF$D_OUT[36:34] ; + assign wci_cEdge$EN = WILL_FIRE_RL_wci_ctl_op_start ; + + // register wci_cState + assign wci_cState$D_IN = wci_nState ; + assign wci_cState$EN = + WILL_FIRE_RL_wci_ctl_op_complete && !wci_illegalEdge ; + + // register wci_ctlAckReg + assign wci_ctlAckReg$D_IN = wci_ctlAckReg_1$whas ; + assign wci_ctlAckReg$EN = 1'd1 ; + + // register wci_ctlOpActive + assign wci_ctlOpActive$D_IN = !WILL_FIRE_RL_wci_ctl_op_complete ; + assign wci_ctlOpActive$EN = + WILL_FIRE_RL_wci_ctl_op_complete || + WILL_FIRE_RL_wci_ctl_op_start ; + + // register wci_illegalEdge + assign wci_illegalEdge$D_IN = + !MUX_wci_illegalEdge$write_1__SEL_1 && + MUX_wci_illegalEdge$write_1__VAL_2 ; + assign wci_illegalEdge$EN = + WILL_FIRE_RL_wci_ctl_op_complete && wci_illegalEdge || + MUX_wci_illegalEdge$write_1__SEL_2 ; + + // register wci_isReset_isInReset + assign wci_isReset_isInReset$D_IN = 1'd0 ; + assign wci_isReset_isInReset$EN = wci_isReset_isInReset ; + + // register wci_nState + always@(wci_reqF$D_OUT) + begin + case (wci_reqF$D_OUT[36:34]) + 3'd0: wci_nState$D_IN = 3'd1; + 3'd1: wci_nState$D_IN = 3'd2; + 3'd2: wci_nState$D_IN = 3'd3; + default: wci_nState$D_IN = 3'd0; + endcase + end + assign wci_nState$EN = + WILL_FIRE_RL_wci_ctl_op_start && + (wci_reqF$D_OUT[36:34] == 3'd0 && wci_cState == 3'd0 || + wci_reqF$D_OUT[36:34] == 3'd1 && + (wci_cState == 3'd1 || wci_cState == 3'd3) || + wci_reqF$D_OUT[36:34] == 3'd2 && wci_cState == 3'd2 || + wci_reqF$D_OUT[36:34] == 3'd3 && + (wci_cState == 3'd3 || wci_cState == 3'd2 || + wci_cState == 3'd1)) ; + + // register wci_reqF_countReg + assign wci_reqF_countReg$D_IN = + (wci_wciReq$wget[71:69] != 3'd0) ? + wci_reqF_countReg + 2'd1 : + wci_reqF_countReg - 2'd1 ; + assign wci_reqF_countReg$EN = + (wci_wciReq$wget[71:69] != 3'd0) != wci_reqF_r_deq$whas ; + + // register wci_respF_c_r + assign wci_respF_c_r$D_IN = + WILL_FIRE_RL_wci_respF_incCtr ? + MUX_wci_respF_c_r$write_1__VAL_1 : + MUX_wci_respF_c_r$write_1__VAL_2 ; + assign wci_respF_c_r$EN = + WILL_FIRE_RL_wci_respF_incCtr || WILL_FIRE_RL_wci_respF_decCtr ; + + // register wci_respF_q_0 + always@(WILL_FIRE_RL_wci_respF_both or + MUX_wci_respF_q_0$write_1__VAL_1 or + MUX_wci_respF_q_0$write_1__SEL_2 or + MUX_wci_respF_q_0$write_1__VAL_2 or + WILL_FIRE_RL_wci_respF_decCtr or wci_respF_q_1) + begin + case (1'b1) // synopsys parallel_case + WILL_FIRE_RL_wci_respF_both: + wci_respF_q_0$D_IN = MUX_wci_respF_q_0$write_1__VAL_1; + MUX_wci_respF_q_0$write_1__SEL_2: + wci_respF_q_0$D_IN = MUX_wci_respF_q_0$write_1__VAL_2; + WILL_FIRE_RL_wci_respF_decCtr: wci_respF_q_0$D_IN = wci_respF_q_1; + default: wci_respF_q_0$D_IN = 34'h2AAAAAAAA /* unspecified value */ ; + endcase + end + assign wci_respF_q_0$EN = + WILL_FIRE_RL_wci_respF_both || + WILL_FIRE_RL_wci_respF_incCtr && wci_respF_c_r == 2'd0 || + WILL_FIRE_RL_wci_respF_decCtr ; + + // register wci_respF_q_1 + always@(WILL_FIRE_RL_wci_respF_both or + MUX_wci_respF_q_1$write_1__VAL_1 or + MUX_wci_respF_q_1$write_1__SEL_2 or + MUX_wci_respF_q_0$write_1__VAL_2 or WILL_FIRE_RL_wci_respF_decCtr) + begin + case (1'b1) // synopsys parallel_case + WILL_FIRE_RL_wci_respF_both: + wci_respF_q_1$D_IN = MUX_wci_respF_q_1$write_1__VAL_1; + MUX_wci_respF_q_1$write_1__SEL_2: + wci_respF_q_1$D_IN = MUX_wci_respF_q_0$write_1__VAL_2; + WILL_FIRE_RL_wci_respF_decCtr: wci_respF_q_1$D_IN = 34'h0AAAAAAAA; + default: wci_respF_q_1$D_IN = 34'h2AAAAAAAA /* unspecified value */ ; + endcase + end + assign wci_respF_q_1$EN = + WILL_FIRE_RL_wci_respF_both || + WILL_FIRE_RL_wci_respF_incCtr && wci_respF_c_r == 2'd1 || + WILL_FIRE_RL_wci_respF_decCtr ; + + // register wci_sFlagReg + assign wci_sFlagReg$D_IN = 1'b0 ; + assign wci_sFlagReg$EN = 1'd1 ; + + // register wci_sThreadBusy_d + assign wci_sThreadBusy_d$D_IN = 1'b0 ; + assign wci_sThreadBusy_d$EN = 1'd1 ; + + // register wsiM_burstKind + assign wsiM_burstKind$D_IN = + (wsiM_burstKind == 2'd0) ? + (wsiM_reqFifo_q_0[92] ? 2'd1 : 2'd2) : + 2'd0 ; + assign wsiM_burstKind$EN = + WILL_FIRE_RL_wsiM_reqFifo_deq && + wsiM_reqFifo_q_0[96:94] == 3'd1 && + (wsiM_burstKind == 2'd0 || + (wsiM_burstKind == 2'd1 || wsiM_burstKind == 2'd2) && + wsiM_reqFifo_q_0[93]) ; + + // register wsiM_errorSticky + assign wsiM_errorSticky$D_IN = 1'b0 ; + assign wsiM_errorSticky$EN = 1'b0 ; + + // register wsiM_iMesgCount + assign wsiM_iMesgCount$D_IN = wsiM_iMesgCount + 32'd1 ; + assign wsiM_iMesgCount$EN = + WILL_FIRE_RL_wsiM_reqFifo_deq && + wsiM_reqFifo_q_0[96:94] == 3'd1 && + wsiM_burstKind == 2'd2 && + wsiM_reqFifo_q_0[93] ; + + // register wsiM_isReset_isInReset + assign wsiM_isReset_isInReset$D_IN = 1'd0 ; + assign wsiM_isReset_isInReset$EN = wsiM_isReset_isInReset ; + + // register wsiM_operateD + assign wsiM_operateD$D_IN = wci_cState == 3'd2 ; + assign wsiM_operateD$EN = 1'd1 ; + + // register wsiM_pMesgCount + assign wsiM_pMesgCount$D_IN = wsiM_pMesgCount + 32'd1 ; + assign wsiM_pMesgCount$EN = + WILL_FIRE_RL_wsiM_reqFifo_deq && + wsiM_reqFifo_q_0[96:94] == 3'd1 && + wsiM_burstKind == 2'd1 && + wsiM_reqFifo_q_0[93] ; + + // register wsiM_peerIsReady + assign wsiM_peerIsReady$D_IN = wsiM0_SReset_n ; + assign wsiM_peerIsReady$EN = 1'd1 ; + + // register wsiM_reqFifo_c_r + assign wsiM_reqFifo_c_r$D_IN = + WILL_FIRE_RL_wsiM_reqFifo_incCtr ? + MUX_wsiM_reqFifo_c_r$write_1__VAL_1 : + MUX_wsiM_reqFifo_c_r$write_1__VAL_2 ; + assign wsiM_reqFifo_c_r$EN = + WILL_FIRE_RL_wsiM_reqFifo_incCtr || + WILL_FIRE_RL_wsiM_reqFifo_decCtr ; + + // register wsiM_reqFifo_q_0 + always@(WILL_FIRE_RL_wsiM_reqFifo_both or + MUX_wsiM_reqFifo_q_0$write_1__VAL_1 or + MUX_wsiM_reqFifo_q_0$write_1__SEL_2 or + wsiS_reqFifo$D_OUT or + WILL_FIRE_RL_wsiM_reqFifo_decCtr or wsiM_reqFifo_q_1) + begin + case (1'b1) // synopsys parallel_case + WILL_FIRE_RL_wsiM_reqFifo_both: + wsiM_reqFifo_q_0$D_IN = MUX_wsiM_reqFifo_q_0$write_1__VAL_1; + MUX_wsiM_reqFifo_q_0$write_1__SEL_2: + wsiM_reqFifo_q_0$D_IN = wsiS_reqFifo$D_OUT; + WILL_FIRE_RL_wsiM_reqFifo_decCtr: + wsiM_reqFifo_q_0$D_IN = wsiM_reqFifo_q_1; + default: wsiM_reqFifo_q_0$D_IN = + 97'h0AAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ; + endcase + end + assign wsiM_reqFifo_q_0$EN = + WILL_FIRE_RL_wsiM_reqFifo_both || + WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_c_r == 2'd0 || + WILL_FIRE_RL_wsiM_reqFifo_decCtr ; + + // register wsiM_reqFifo_q_1 + always@(WILL_FIRE_RL_wsiM_reqFifo_both or + MUX_wsiM_reqFifo_q_1$write_1__VAL_1 or + MUX_wsiM_reqFifo_q_1$write_1__SEL_2 or + wsiS_reqFifo$D_OUT or WILL_FIRE_RL_wsiM_reqFifo_decCtr) + begin + case (1'b1) // synopsys parallel_case + WILL_FIRE_RL_wsiM_reqFifo_both: + wsiM_reqFifo_q_1$D_IN = MUX_wsiM_reqFifo_q_1$write_1__VAL_1; + MUX_wsiM_reqFifo_q_1$write_1__SEL_2: + wsiM_reqFifo_q_1$D_IN = wsiS_reqFifo$D_OUT; + WILL_FIRE_RL_wsiM_reqFifo_decCtr: + wsiM_reqFifo_q_1$D_IN = 97'h00000AAAAAAAAAAAAAAAAAA00; + default: wsiM_reqFifo_q_1$D_IN = + 97'h0AAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ; + endcase + end + assign wsiM_reqFifo_q_1$EN = + WILL_FIRE_RL_wsiM_reqFifo_both || + WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_c_r == 2'd1 || + WILL_FIRE_RL_wsiM_reqFifo_decCtr ; + + // register wsiM_sThreadBusy_d + assign wsiM_sThreadBusy_d$D_IN = wsiM0_SThreadBusy ; + assign wsiM_sThreadBusy_d$EN = 1'd1 ; + + // register wsiM_statusR + assign wsiM_statusR$D_IN = + { wsiM_isReset_isInReset, + !wsiM_peerIsReady, + !wsiM_operateD, + wsiM_errorSticky, + wsiM_burstKind != 2'd0, + wsiM_sThreadBusy_d, + 1'd0, + wsiM_trafficSticky } ; + assign wsiM_statusR$EN = 1'd1 ; + + // register wsiM_tBusyCount + assign wsiM_tBusyCount$D_IN = wsiM_tBusyCount + 32'd1 ; + assign wsiM_tBusyCount$EN = + wsiM_operateD && wsiM_peerIsReady && wsiM_sThreadBusy_d ; + + // register wsiM_trafficSticky + assign wsiM_trafficSticky$D_IN = 1'd1 ; + assign wsiM_trafficSticky$EN = + WILL_FIRE_RL_wsiM_reqFifo_deq && + wsiM_reqFifo_q_0[96:94] == 3'd1 ; + + // register wsiS_burstKind + assign wsiS_burstKind$D_IN = + (wsiS_burstKind == 2'd0) ? + (wsiS_wsiReq$wget[92] ? 2'd1 : 2'd2) : + 2'd0 ; + assign wsiS_burstKind$EN = + WILL_FIRE_RL_wsiS_reqFifo_enq && + (wsiS_burstKind == 2'd0 || + (wsiS_burstKind == 2'd1 || wsiS_burstKind == 2'd2) && + wsiS_wsiReq$wget[93]) ; + + // register wsiS_errorSticky + assign wsiS_errorSticky$D_IN = 1'b0 ; + assign wsiS_errorSticky$EN = 1'b0 ; + + // register wsiS_iMesgCount + assign wsiS_iMesgCount$D_IN = wsiS_iMesgCount + 32'd1 ; + assign wsiS_iMesgCount$EN = + WILL_FIRE_RL_wsiS_reqFifo_enq && wsiS_burstKind == 2'd2 && + wsiS_wsiReq$wget[93] ; + + // register wsiS_isReset_isInReset + assign wsiS_isReset_isInReset$D_IN = 1'd0 ; + assign wsiS_isReset_isInReset$EN = wsiS_isReset_isInReset ; + + // register wsiS_mesgWordLength + assign wsiS_mesgWordLength$D_IN = wsiS_wordCount ; + assign wsiS_mesgWordLength$EN = + WILL_FIRE_RL_wsiS_reqFifo_enq && wsiS_wsiReq$wget[93] ; + + // register wsiS_operateD + assign wsiS_operateD$D_IN = wci_cState == 3'd2 ; + assign wsiS_operateD$EN = 1'd1 ; + + // register wsiS_pMesgCount + assign wsiS_pMesgCount$D_IN = wsiS_pMesgCount + 32'd1 ; + assign wsiS_pMesgCount$EN = + WILL_FIRE_RL_wsiS_reqFifo_enq && wsiS_burstKind == 2'd1 && + wsiS_wsiReq$wget[93] ; + + // register wsiS_peerIsReady + assign wsiS_peerIsReady$D_IN = wsiS0_MReset_n ; + assign wsiS_peerIsReady$EN = 1'd1 ; + + // register wsiS_reqFifo_countReg + assign wsiS_reqFifo_countReg$D_IN = + WILL_FIRE_RL_wsiS_reqFifo_enq ? + wsiS_reqFifo_countReg + 2'd1 : + wsiS_reqFifo_countReg - 2'd1 ; + assign wsiS_reqFifo_countReg$EN = + WILL_FIRE_RL_wsiS_reqFifo_enq != + WILL_FIRE_RL_wsipass_doMessagePush ; + + // register wsiS_reqFifo_levelsValid + assign wsiS_reqFifo_levelsValid$D_IN = WILL_FIRE_RL_wsiS_reqFifo_reset ; + assign wsiS_reqFifo_levelsValid$EN = + WILL_FIRE_RL_wsipass_doMessagePush || + WILL_FIRE_RL_wsiS_reqFifo_enq || + WILL_FIRE_RL_wsiS_reqFifo_reset ; + + // register wsiS_statusR + assign wsiS_statusR$D_IN = + { wsiS_isReset_isInReset, + !wsiS_peerIsReady, + !wsiS_operateD, + wsiS_errorSticky, + wsiS_burstKind != 2'd0, + !wsiS_sThreadBusy_dw$whas || wsiS_sThreadBusy_dw$wget, + 1'd0, + wsiS_trafficSticky } ; + assign wsiS_statusR$EN = 1'd1 ; + + // register wsiS_tBusyCount + assign wsiS_tBusyCount$D_IN = wsiS_tBusyCount + 32'd1 ; + assign wsiS_tBusyCount$EN = + wsiS_operateD && wsiS_peerIsReady && + (!wsiS_sThreadBusy_dw$whas || wsiS_sThreadBusy_dw$wget) ; + + // register wsiS_trafficSticky + assign wsiS_trafficSticky$D_IN = 1'd1 ; + assign wsiS_trafficSticky$EN = WILL_FIRE_RL_wsiS_reqFifo_enq ; + + // register wsiS_wordCount + assign wsiS_wordCount$D_IN = + wsiS_wsiReq$wget[93] ? 12'd1 : wsiS_wordCount + 12'd1 ; + assign wsiS_wordCount$EN = WILL_FIRE_RL_wsiS_reqFifo_enq ; + + // submodule wci_reqF + assign wci_reqF$D_IN = wci_wciReq$wget ; + assign wci_reqF$ENQ = wci_wciReq$wget[71:69] != 3'd0 ; + assign wci_reqF$DEQ = wci_reqF_r_deq$whas ; + assign wci_reqF$CLR = 1'b0 ; + + // submodule wsiS_reqFifo + assign wsiS_reqFifo$D_IN = wsiS_wsiReq$wget ; + assign wsiS_reqFifo$ENQ = WILL_FIRE_RL_wsiS_reqFifo_enq ; + assign wsiS_reqFifo$DEQ = WILL_FIRE_RL_wsipass_doMessagePush ; + assign wsiS_reqFifo$CLR = 1'b0 ; + + // remaining internal signals + assign NOT_gated_99_05_AND_byteCount_06_EQ_frameSize__ETC___d439 = + !gated && byteCount == frameSize || + gated && byteCount == gateSize ; + assign frameGateStatus__h10551 = { 31'd0, hasDebugLogic } ; + assign rdat__h10963 = hasDebugLogic ? { 16'd0, x__h10967 } : 32'd0 ; + assign rdat__h11063 = hasDebugLogic ? wsiS_extStatusW$wget[95:64] : 32'd0 ; + assign rdat__h11077 = hasDebugLogic ? wsiS_extStatusW$wget[63:32] : 32'd0 ; + assign rdat__h11085 = hasDebugLogic ? wsiS_extStatusW$wget[31:0] : 32'd0 ; + assign rdat__h11091 = hasDebugLogic ? wsiM_extStatusW$wget[95:64] : 32'd0 ; + assign rdat__h11105 = hasDebugLogic ? wsiM_extStatusW$wget[63:32] : 32'd0 ; + assign rdat__h11113 = hasDebugLogic ? wsiM_extStatusW$wget[31:0] : 32'd0 ; + assign rdat__h11119 = hasDebugLogic ? op0MesgCnt : 32'd0 ; + assign rdat__h11130 = hasDebugLogic ? otherMesgCnt : 32'd0 ; + assign wsiS_reqFifo_i_notEmpty__92_AND_NOT_frameGateC_ETC___d303 = + wsiS_reqFifo$EMPTY_N && + (frameGateCtrl[3:0] != 4'h0 && + (frameGateCtrl[3:0] != 4'h1 || gated) || + wsiM_reqFifo_c_r != 2'd2) ; + assign x__h10327 = byteCount + 32'd8 ; + assign x__h10967 = { wsiS_statusR, wsiM_statusR } ; + always@(wci_reqF$D_OUT or + frameGateStatus__h10551 or + frameGateCtrl or + frameSize or + gateSize or + rdat__h10963 or + rdat__h11063 or + rdat__h11077 or + rdat__h11085 or + rdat__h11091 or + rdat__h11105 or rdat__h11113 or rdat__h11119 or rdat__h11130) + begin + case (wci_reqF$D_OUT[63:32]) + 32'h0: g_data__h10929 = frameGateStatus__h10551; + 32'h00000004: g_data__h10929 = frameGateCtrl; + 32'h00000008: g_data__h10929 = frameSize; + 32'h0000000C: g_data__h10929 = gateSize; + 32'h00000010: g_data__h10929 = rdat__h10963; + 32'h00000014: g_data__h10929 = rdat__h11063; + 32'h00000018: g_data__h10929 = rdat__h11077; + 32'h0000001C: g_data__h10929 = rdat__h11085; + 32'h00000020: g_data__h10929 = rdat__h11091; + 32'h00000024: g_data__h10929 = rdat__h11105; + 32'h00000028: g_data__h10929 = rdat__h11113; + 32'h0000002C: g_data__h10929 = rdat__h11119; + 32'h00000030: g_data__h10929 = rdat__h11130; + default: g_data__h10929 = 32'd0; + endcase + end + + // handling of inlined registers + + always@(posedge wciS0_Clk) + begin + if (wciS0_MReset_n == `BSV_RESET_VALUE) + begin + byteCount <= `BSV_ASSIGNMENT_DELAY 32'd8; + frameGateCtrl <= `BSV_ASSIGNMENT_DELAY fgCtrlInit; + frameSize <= `BSV_ASSIGNMENT_DELAY 32'd0; + gateSize <= `BSV_ASSIGNMENT_DELAY 32'd0; + gated <= `BSV_ASSIGNMENT_DELAY 1'd0; + op0MesgCnt <= `BSV_ASSIGNMENT_DELAY 32'd0; + otherMesgCnt <= `BSV_ASSIGNMENT_DELAY 32'd0; + wci_cEdge <= `BSV_ASSIGNMENT_DELAY 3'h2; + wci_cState <= `BSV_ASSIGNMENT_DELAY 3'd0; + wci_ctlAckReg <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_ctlOpActive <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_illegalEdge <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_nState <= `BSV_ASSIGNMENT_DELAY 3'd0; + wci_reqF_countReg <= `BSV_ASSIGNMENT_DELAY 2'd0; + wci_respF_c_r <= `BSV_ASSIGNMENT_DELAY 2'd0; + wci_respF_q_0 <= `BSV_ASSIGNMENT_DELAY 34'h0AAAAAAAA; + wci_respF_q_1 <= `BSV_ASSIGNMENT_DELAY 34'h0AAAAAAAA; + wci_sFlagReg <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY 1'd1; + wsiM_burstKind <= `BSV_ASSIGNMENT_DELAY 2'd0; + wsiM_errorSticky <= `BSV_ASSIGNMENT_DELAY 1'd0; + wsiM_iMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0; + wsiM_operateD <= `BSV_ASSIGNMENT_DELAY 1'd0; + wsiM_pMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0; + wsiM_peerIsReady <= `BSV_ASSIGNMENT_DELAY 1'd0; + wsiM_reqFifo_c_r <= `BSV_ASSIGNMENT_DELAY 2'd0; + wsiM_reqFifo_q_0 <= `BSV_ASSIGNMENT_DELAY + 97'h00000AAAAAAAAAAAAAAAAAA00; + wsiM_reqFifo_q_1 <= `BSV_ASSIGNMENT_DELAY + 97'h00000AAAAAAAAAAAAAAAAAA00; + wsiM_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY 1'd1; + wsiM_tBusyCount <= `BSV_ASSIGNMENT_DELAY 32'd0; + wsiM_trafficSticky <= `BSV_ASSIGNMENT_DELAY 1'd0; + wsiS_burstKind <= `BSV_ASSIGNMENT_DELAY 2'd0; + wsiS_errorSticky <= `BSV_ASSIGNMENT_DELAY 1'd0; + wsiS_iMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0; + wsiS_operateD <= `BSV_ASSIGNMENT_DELAY 1'd0; + wsiS_pMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0; + wsiS_peerIsReady <= `BSV_ASSIGNMENT_DELAY 1'd0; + wsiS_reqFifo_countReg <= `BSV_ASSIGNMENT_DELAY 2'd0; + wsiS_reqFifo_levelsValid <= `BSV_ASSIGNMENT_DELAY 1'd1; + wsiS_tBusyCount <= `BSV_ASSIGNMENT_DELAY 32'd0; + wsiS_trafficSticky <= `BSV_ASSIGNMENT_DELAY 1'd0; + wsiS_wordCount <= `BSV_ASSIGNMENT_DELAY 12'd1; + end + else + begin + if (byteCount$EN) byteCount <= `BSV_ASSIGNMENT_DELAY byteCount$D_IN; + if (frameGateCtrl$EN) + frameGateCtrl <= `BSV_ASSIGNMENT_DELAY frameGateCtrl$D_IN; + if (frameSize$EN) frameSize <= `BSV_ASSIGNMENT_DELAY frameSize$D_IN; + if (gateSize$EN) gateSize <= `BSV_ASSIGNMENT_DELAY gateSize$D_IN; + if (gated$EN) gated <= `BSV_ASSIGNMENT_DELAY gated$D_IN; + if (op0MesgCnt$EN) + op0MesgCnt <= `BSV_ASSIGNMENT_DELAY op0MesgCnt$D_IN; + if (otherMesgCnt$EN) + otherMesgCnt <= `BSV_ASSIGNMENT_DELAY otherMesgCnt$D_IN; + if (wci_cEdge$EN) wci_cEdge <= `BSV_ASSIGNMENT_DELAY wci_cEdge$D_IN; + if (wci_cState$EN) + wci_cState <= `BSV_ASSIGNMENT_DELAY wci_cState$D_IN; + if (wci_ctlAckReg$EN) + wci_ctlAckReg <= `BSV_ASSIGNMENT_DELAY wci_ctlAckReg$D_IN; + if (wci_ctlOpActive$EN) + wci_ctlOpActive <= `BSV_ASSIGNMENT_DELAY wci_ctlOpActive$D_IN; + if (wci_illegalEdge$EN) + wci_illegalEdge <= `BSV_ASSIGNMENT_DELAY wci_illegalEdge$D_IN; + if (wci_nState$EN) + wci_nState <= `BSV_ASSIGNMENT_DELAY wci_nState$D_IN; + if (wci_reqF_countReg$EN) + wci_reqF_countReg <= `BSV_ASSIGNMENT_DELAY wci_reqF_countReg$D_IN; + if (wci_respF_c_r$EN) + wci_respF_c_r <= `BSV_ASSIGNMENT_DELAY wci_respF_c_r$D_IN; + if (wci_respF_q_0$EN) + wci_respF_q_0 <= `BSV_ASSIGNMENT_DELAY wci_respF_q_0$D_IN; + if (wci_respF_q_1$EN) + wci_respF_q_1 <= `BSV_ASSIGNMENT_DELAY wci_respF_q_1$D_IN; + if (wci_sFlagReg$EN) + wci_sFlagReg <= `BSV_ASSIGNMENT_DELAY wci_sFlagReg$D_IN; + if (wci_sThreadBusy_d$EN) + wci_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY wci_sThreadBusy_d$D_IN; + if (wsiM_burstKind$EN) + wsiM_burstKind <= `BSV_ASSIGNMENT_DELAY wsiM_burstKind$D_IN; + if (wsiM_errorSticky$EN) + wsiM_errorSticky <= `BSV_ASSIGNMENT_DELAY wsiM_errorSticky$D_IN; + if (wsiM_iMesgCount$EN) + wsiM_iMesgCount <= `BSV_ASSIGNMENT_DELAY wsiM_iMesgCount$D_IN; + if (wsiM_operateD$EN) + wsiM_operateD <= `BSV_ASSIGNMENT_DELAY wsiM_operateD$D_IN; + if (wsiM_pMesgCount$EN) + wsiM_pMesgCount <= `BSV_ASSIGNMENT_DELAY wsiM_pMesgCount$D_IN; + if (wsiM_peerIsReady$EN) + wsiM_peerIsReady <= `BSV_ASSIGNMENT_DELAY wsiM_peerIsReady$D_IN; + if (wsiM_reqFifo_c_r$EN) + wsiM_reqFifo_c_r <= `BSV_ASSIGNMENT_DELAY wsiM_reqFifo_c_r$D_IN; + if (wsiM_reqFifo_q_0$EN) + wsiM_reqFifo_q_0 <= `BSV_ASSIGNMENT_DELAY wsiM_reqFifo_q_0$D_IN; + if (wsiM_reqFifo_q_1$EN) + wsiM_reqFifo_q_1 <= `BSV_ASSIGNMENT_DELAY wsiM_reqFifo_q_1$D_IN; + if (wsiM_sThreadBusy_d$EN) + wsiM_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY wsiM_sThreadBusy_d$D_IN; + if (wsiM_tBusyCount$EN) + wsiM_tBusyCount <= `BSV_ASSIGNMENT_DELAY wsiM_tBusyCount$D_IN; + if (wsiM_trafficSticky$EN) + wsiM_trafficSticky <= `BSV_ASSIGNMENT_DELAY wsiM_trafficSticky$D_IN; + if (wsiS_burstKind$EN) + wsiS_burstKind <= `BSV_ASSIGNMENT_DELAY wsiS_burstKind$D_IN; + if (wsiS_errorSticky$EN) + wsiS_errorSticky <= `BSV_ASSIGNMENT_DELAY wsiS_errorSticky$D_IN; + if (wsiS_iMesgCount$EN) + wsiS_iMesgCount <= `BSV_ASSIGNMENT_DELAY wsiS_iMesgCount$D_IN; + if (wsiS_operateD$EN) + wsiS_operateD <= `BSV_ASSIGNMENT_DELAY wsiS_operateD$D_IN; + if (wsiS_pMesgCount$EN) + wsiS_pMesgCount <= `BSV_ASSIGNMENT_DELAY wsiS_pMesgCount$D_IN; + if (wsiS_peerIsReady$EN) + wsiS_peerIsReady <= `BSV_ASSIGNMENT_DELAY wsiS_peerIsReady$D_IN; + if (wsiS_reqFifo_countReg$EN) + wsiS_reqFifo_countReg <= `BSV_ASSIGNMENT_DELAY + wsiS_reqFifo_countReg$D_IN; + if (wsiS_reqFifo_levelsValid$EN) + wsiS_reqFifo_levelsValid <= `BSV_ASSIGNMENT_DELAY + wsiS_reqFifo_levelsValid$D_IN; + if (wsiS_tBusyCount$EN) + wsiS_tBusyCount <= `BSV_ASSIGNMENT_DELAY wsiS_tBusyCount$D_IN; + if (wsiS_trafficSticky$EN) + wsiS_trafficSticky <= `BSV_ASSIGNMENT_DELAY wsiS_trafficSticky$D_IN; + if (wsiS_wordCount$EN) + wsiS_wordCount <= `BSV_ASSIGNMENT_DELAY wsiS_wordCount$D_IN; + end + if (wsiM_statusR$EN) + wsiM_statusR <= `BSV_ASSIGNMENT_DELAY wsiM_statusR$D_IN; + if (wsiS_mesgWordLength$EN) + wsiS_mesgWordLength <= `BSV_ASSIGNMENT_DELAY wsiS_mesgWordLength$D_IN; + if (wsiS_statusR$EN) + wsiS_statusR <= `BSV_ASSIGNMENT_DELAY wsiS_statusR$D_IN; + end + + always@(posedge wciS0_Clk or `BSV_RESET_EDGE wciS0_MReset_n) + if (wciS0_MReset_n == `BSV_RESET_VALUE) + begin + wci_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY 1'd1; + wsiM_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY 1'd1; + wsiS_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY 1'd1; + end + else + begin + if (wci_isReset_isInReset$EN) + wci_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY + wci_isReset_isInReset$D_IN; + if (wsiM_isReset_isInReset$EN) + wsiM_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY + wsiM_isReset_isInReset$D_IN; + if (wsiS_isReset_isInReset$EN) + wsiS_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY + wsiS_isReset_isInReset$D_IN; + end + + // synopsys translate_off + `ifdef BSV_NO_INITIAL_BLOCKS + `else // not BSV_NO_INITIAL_BLOCKS + initial + begin + byteCount = 32'hAAAAAAAA; + frameGateCtrl = 32'hAAAAAAAA; + frameSize = 32'hAAAAAAAA; + gateSize = 32'hAAAAAAAA; + gated = 1'h0; + op0MesgCnt = 32'hAAAAAAAA; + otherMesgCnt = 32'hAAAAAAAA; + wci_cEdge = 3'h2; + wci_cState = 3'h2; + wci_ctlAckReg = 1'h0; + wci_ctlOpActive = 1'h0; + wci_illegalEdge = 1'h0; + wci_isReset_isInReset = 1'h0; + wci_nState = 3'h2; + wci_reqF_countReg = 2'h2; + wci_respF_c_r = 2'h2; + wci_respF_q_0 = 34'h2AAAAAAAA; + wci_respF_q_1 = 34'h2AAAAAAAA; + wci_sFlagReg = 1'h0; + wci_sThreadBusy_d = 1'h0; + wsiM_burstKind = 2'h2; + wsiM_errorSticky = 1'h0; + wsiM_iMesgCount = 32'hAAAAAAAA; + wsiM_isReset_isInReset = 1'h0; + wsiM_operateD = 1'h0; + wsiM_pMesgCount = 32'hAAAAAAAA; + wsiM_peerIsReady = 1'h0; + wsiM_reqFifo_c_r = 2'h2; + wsiM_reqFifo_q_0 = 97'h0AAAAAAAAAAAAAAAAAAAAAAAA; + wsiM_reqFifo_q_1 = 97'h0AAAAAAAAAAAAAAAAAAAAAAAA; + wsiM_sThreadBusy_d = 1'h0; + wsiM_statusR = 8'hAA; + wsiM_tBusyCount = 32'hAAAAAAAA; + wsiM_trafficSticky = 1'h0; + wsiS_burstKind = 2'h2; + wsiS_errorSticky = 1'h0; + wsiS_iMesgCount = 32'hAAAAAAAA; + wsiS_isReset_isInReset = 1'h0; + wsiS_mesgWordLength = 12'hAAA; + wsiS_operateD = 1'h0; + wsiS_pMesgCount = 32'hAAAAAAAA; + wsiS_peerIsReady = 1'h0; + wsiS_reqFifo_countReg = 2'h2; + wsiS_reqFifo_levelsValid = 1'h0; + wsiS_statusR = 8'hAA; + wsiS_tBusyCount = 32'hAAAAAAAA; + wsiS_trafficSticky = 1'h0; + wsiS_wordCount = 12'hAAA; + end + `endif // BSV_NO_INITIAL_BLOCKS + // synopsys translate_on + + // handling of system tasks + + // synopsys translate_off + always@(negedge wciS0_Clk) + begin + #0; + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_ctl_op_start) + begin + v__h3701 = $time; + #0; + end + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_ctl_op_start) + $display("[%0d]: %m: WCI ControlOp: Starting-transition edge:%x from:%x", + v__h3701, + wci_reqF$D_OUT[36:34], + wci_cState); + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_ctrl_IsO) + begin + v__h11217 = $time; + #0; + end + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_ctrl_IsO) + $display("[%0d]: %m: Starting FrameGate frameGateCtrl:%0x", + v__h11217, + frameGateCtrl); + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_ctrl_IsO && WILL_FIRE_RL_wci_ctrl_OrE) + $display("Error: \"bsv/prm/FrameGate.bsv\", line 68, column 60: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_IsO] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n"); + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_ctrl_EiI && WILL_FIRE_RL_wci_ctrl_OrE) + $display("Error: \"bsv/prm/FrameGate.bsv\", line 68, column 46: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_EiI] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n"); + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_ctrl_EiI && WILL_FIRE_RL_wci_ctrl_IsO) + $display("Error: \"bsv/prm/FrameGate.bsv\", line 68, column 46: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_EiI] and\n [RL_wci_ctrl_IsO] ) fired in the same clock cycle.\n"); + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_ctl_op_complete && wci_illegalEdge) + begin + v__h4020 = $time; + #0; + end + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_ctl_op_complete && wci_illegalEdge) + $display("[%0d]: %m: WCI ControlOp: ILLEGAL-EDGE Completed-transition edge:%x from:%x", + v__h4020, + wci_cEdge, + wci_cState); + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_ctl_op_complete && !wci_illegalEdge) + begin + v__h3876 = $time; + #0; + end + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_ctl_op_complete && !wci_illegalEdge) + $display("[%0d]: %m: WCI ControlOp: Completed-transition edge:%x from:%x to:%x", + v__h3876, + wci_cEdge, + wci_cState, + wci_nState); + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_OrE) + $display("Error: \"bsv/prm/FrameGate.bsv\", line 68, column 26: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n"); + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_IsO) + $display("Error: \"bsv/prm/FrameGate.bsv\", line 68, column 26: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_wci_ctrl_IsO] ) fired in the same clock cycle.\n"); + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_EiI) + $display("Error: \"bsv/prm/FrameGate.bsv\", line 68, column 26: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_wci_ctrl_EiI] ) fired in the same clock cycle.\n"); + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_cfrd) + $display("Error: \"bsv/prm/FrameGate.bsv\", line 68, column 26: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and [RL_wci_cfrd] )\n fired in the same clock cycle.\n"); + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_cfrd && WILL_FIRE_RL_wci_ctrl_OrE) + $display("Error: \"bsv/prm/FrameGate.bsv\", line 68, column 36: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n"); + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_cfrd && WILL_FIRE_RL_wci_ctrl_IsO) + $display("Error: \"bsv/prm/FrameGate.bsv\", line 68, column 36: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n [RL_wci_ctrl_IsO] ) fired in the same clock cycle.\n"); + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_cfrd && WILL_FIRE_RL_wci_ctrl_EiI) + $display("Error: \"bsv/prm/FrameGate.bsv\", line 68, column 36: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n [RL_wci_ctrl_EiI] ) fired in the same clock cycle.\n"); + end + // synopsys translate_on +endmodule // mkFrameGate8B + diff --git a/rtl/mkGMAC.v b/rtl/mkGMAC.v index fc6af2f6..83bfce4a 100644 --- a/rtl/mkGMAC.v +++ b/rtl/mkGMAC.v @@ -1,7 +1,7 @@ // -// Generated by Bluespec Compiler, version 2012.09.beta1 (build 29570, 2012-09.11) +// Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Wed Nov 28 10:31:28 EST 2012 +// On Fri Jun 21 16:56:48 EDT 2013 // // // Ports: @@ -525,7 +525,6 @@ module mkGMAC(CLK_rxClk, wire [4 : 0] MUX_txRS_ifgCnt_value$write_1__VAL_2, MUX_txRS_preambleCnt_value$write_1__VAL_3; wire [3 : 0] MUX_rxRS_preambleCnt_value$write_1__VAL_3; - wire [2 : 0] MUX_txRS_emitFCS$write_1__VAL_2; wire MUX_rxRS_rxF$enq_1__SEL_1, MUX_txRS_crc$add_1__SEL_1, MUX_txRS_crcDbgCnt_value$write_1__SEL_1, @@ -533,11 +532,12 @@ module mkGMAC(CLK_rxClk, MUX_txRS_ifgCnt_value$write_1__SEL_1; // remaining internal signals - reg [63 : 0] v__h12565, v__h6617; - reg [1 : 0] CASE_rxRS_rxFdD_OUT_BITS_9_TO_8_3_0_rxRS_rxF_ETC__q1, - CASE_tx_put_BITS_9_TO_8_3_0_tx_put_BITS_9_TO_8_ETC__q2; - wire txRS_lenCnt_value_45_ULT_59___d295, - txRS_preambleCnt_value_19_ULT_7___d296; + reg [63 : 0] v__h12643, v__h6699; + reg [1 : 0] CASE_rxRS_rxFdD_OUT_BITS_9_TO_8_0_rxRS_rxFdD_ETC__q1, + CASE_tx_put_BITS_9_TO_8_0_tx_put_BITS_9_TO_8_1_ETC__q2; + wire [2 : 0] x__h13660; + wire txRS_lenCnt_value_45_ULT_59___d209, + txRS_preambleCnt_value_19_ULT_7___d183; // oscillator and gates for output clock CLK_gmii_tx_tx_clk assign CLK_gmii_tx_tx_clk = txRS_iobTxClk$Q ; @@ -569,7 +569,7 @@ module mkGMAC(CLK_rxClk, // actionvalue method rx_get assign rx_get = - { CASE_rxRS_rxFdD_OUT_BITS_9_TO_8_3_0_rxRS_rxF_ETC__q1, + { CASE_rxRS_rxFdD_OUT_BITS_9_TO_8_0_rxRS_rxFdD_ETC__q1, rxRS_rxF$dD_OUT[7:0] } ; assign RDY_rx_get = rxRS_rxF$dEMPTY_N ; @@ -915,7 +915,7 @@ module mkGMAC(CLK_rxClk, // rule RL_txRS_egress_SOF assign CAN_FIRE_RL_txRS_egress_SOF = txRS_txF$dEMPTY_N && - (txRS_preambleCnt_value_19_ULT_7___d296 || + (txRS_preambleCnt_value_19_ULT_7___d183 || txRS_preambleCnt_value == 5'd7 || txRS_txF$dEMPTY_N) && txRS_txOperateS$dD_OUT && @@ -936,7 +936,7 @@ module mkGMAC(CLK_rxClk, // rule RL_txRS_egress_EOF assign CAN_FIRE_RL_txRS_egress_EOF = txRS_txF$dEMPTY_N && - (txRS_lenCnt_value_45_ULT_59___d295 || txRS_txF$dEMPTY_N) && + (txRS_lenCnt_value_45_ULT_59___d209 || txRS_txF$dEMPTY_N) && txRS_txOperateS$dD_OUT && txRS_txActive && txRS_txF$dD_OUT[9:8] == 2'd1 ; @@ -952,13 +952,13 @@ module mkGMAC(CLK_rxClk, WILL_FIRE_RL_rxRS_ingress_noadvance && rxRS_rxActive ; assign MUX_txRS_crc$add_1__SEL_1 = WILL_FIRE_RL_txRS_egress_SOF && - !txRS_preambleCnt_value_19_ULT_7___d296 && + !txRS_preambleCnt_value_19_ULT_7___d183 && txRS_preambleCnt_value != 5'd7 ; assign MUX_txRS_crcDbgCnt_value$write_1__SEL_1 = WILL_FIRE_RL_txRS_egress_FCS && txRS_emitFCS == 3'd4 ; assign MUX_txRS_emitFCS$write_1__SEL_1 = WILL_FIRE_RL_txRS_egress_EOF && - !txRS_lenCnt_value_45_ULT_59___d295 ; + !txRS_lenCnt_value_45_ULT_59___d209 ; assign MUX_txRS_ifgCnt_value$write_1__SEL_1 = WILL_FIRE_RL_txRS_egress_FCS && txRS_emitFCS == 3'd1 ; assign MUX_rxRS_crcDbgCnt_value$write_1__VAL_1 = @@ -989,7 +989,6 @@ module mkGMAC(CLK_rxClk, (txRS_crcDbgCnt_value == 12'd4095) ? txRS_crcDbgCnt_value : txRS_crcDbgCnt_value + 12'd1 ; - assign MUX_txRS_emitFCS$write_1__VAL_2 = txRS_emitFCS - 3'd1 ; assign MUX_txRS_ifgCnt_value$write_1__VAL_2 = (txRS_ifgCnt_value == 5'h0) ? txRS_ifgCnt_value : @@ -1002,17 +1001,19 @@ module mkGMAC(CLK_rxClk, (txRS_preambleCnt_value == 5'd31) ? txRS_preambleCnt_value : txRS_preambleCnt_value + 5'd1 ; - always@(txRS_emitFCS or txRS_crc$result) + always@(x__h13660 or txRS_crc$result) begin - case (txRS_emitFCS) - 3'd1: MUX_txRS_txData_1$wset_1__VAL_1 = txRS_crc$result[31:24]; - 3'd2: MUX_txRS_txData_1$wset_1__VAL_1 = txRS_crc$result[23:16]; - 3'd3: MUX_txRS_txData_1$wset_1__VAL_1 = txRS_crc$result[15:8]; - default: MUX_txRS_txData_1$wset_1__VAL_1 = txRS_crc$result[7:0]; + case (x__h13660) + 3'd0: MUX_txRS_txData_1$wset_1__VAL_1 = txRS_crc$result[31:24]; + 3'd1: MUX_txRS_txData_1$wset_1__VAL_1 = txRS_crc$result[23:16]; + 3'd2: MUX_txRS_txData_1$wset_1__VAL_1 = txRS_crc$result[15:8]; + 3'd3: MUX_txRS_txData_1$wset_1__VAL_1 = txRS_crc$result[7:0]; + default: MUX_txRS_txData_1$wset_1__VAL_1 = + 8'b10101010 /* unspecified value */ ; endcase end assign MUX_txRS_txData_1$wset_1__VAL_4 = - txRS_preambleCnt_value_19_ULT_7___d296 ? + txRS_preambleCnt_value_19_ULT_7___d183 ? 8'd85 : ((txRS_preambleCnt_value == 5'd7) ? 8'd213 : @@ -1069,7 +1070,7 @@ module mkGMAC(CLK_rxClk, txRS_txOperateS$dD_OUT && txRS_ifgCnt_value != 5'h0 ; assign txRS_lenCnt_incAction$whas = WILL_FIRE_RL_txRS_egress_SOF && - !txRS_preambleCnt_value_19_ULT_7___d296 && + !txRS_preambleCnt_value_19_ULT_7___d183 && txRS_preambleCnt_value != 5'd7 || WILL_FIRE_RL_txRS_egress_Body || WILL_FIRE_RL_txRS_egress_EOF || @@ -1077,7 +1078,7 @@ module mkGMAC(CLK_rxClk, assign txRS_lenCnt_decAction$whas = 1'b0 ; assign txRS_crcDbgCnt_incAction$whas = WILL_FIRE_RL_txRS_egress_SOF && - !txRS_preambleCnt_value_19_ULT_7___d296 && + !txRS_preambleCnt_value_19_ULT_7___d183 && txRS_preambleCnt_value != 5'd7 || WILL_FIRE_RL_txRS_egress_Body || WILL_FIRE_RL_txRS_egress_EOF ; @@ -1174,17 +1175,15 @@ module mkGMAC(CLK_rxClk, txRS_crcDbgCnt_incAction$whas && !WILL_FIRE_RL_txRS_egress_FCS ; // register txRS_doPad - assign txRS_doPad$D_IN = txRS_lenCnt_value_45_ULT_59___d295 ; + assign txRS_doPad$D_IN = txRS_lenCnt_value_45_ULT_59___d209 ; assign txRS_doPad$EN = WILL_FIRE_RL_txRS_egress_EOF ; // register txRS_emitFCS assign txRS_emitFCS$D_IN = - MUX_txRS_emitFCS$write_1__SEL_1 ? - 3'd4 : - MUX_txRS_emitFCS$write_1__VAL_2 ; + MUX_txRS_emitFCS$write_1__SEL_1 ? 3'd4 : x__h13660 ; assign txRS_emitFCS$EN = WILL_FIRE_RL_txRS_egress_EOF && - !txRS_lenCnt_value_45_ULT_59___d295 || + !txRS_lenCnt_value_45_ULT_59___d209 || WILL_FIRE_RL_txRS_egress_FCS ; // register txRS_ifgCnt_value @@ -1200,7 +1199,7 @@ module mkGMAC(CLK_rxClk, assign txRS_isSOF$D_IN = !MUX_txRS_crc$add_1__SEL_1 ; assign txRS_isSOF$EN = WILL_FIRE_RL_txRS_egress_SOF && - !txRS_preambleCnt_value_19_ULT_7___d296 && + !txRS_preambleCnt_value_19_ULT_7___d183 && txRS_preambleCnt_value != 5'd7 || WILL_FIRE_RL_txRS_egress_FCS && txRS_emitFCS == 3'd1 ; @@ -1226,7 +1225,7 @@ module mkGMAC(CLK_rxClk, assign txRS_txActive$D_IN = !MUX_txRS_emitFCS$write_1__SEL_1 ; assign txRS_txActive$EN = WILL_FIRE_RL_txRS_egress_EOF && - !txRS_lenCnt_value_45_ULT_59___d295 || + !txRS_lenCnt_value_45_ULT_59___d209 || WILL_FIRE_RL_txRS_egress_SOF ; // register txRS_txDV @@ -1300,7 +1299,7 @@ module mkGMAC(CLK_rxClk, MUX_txRS_crc$add_1__VAL_2 ; assign txRS_crc$EN_add = WILL_FIRE_RL_txRS_egress_SOF && - !txRS_preambleCnt_value_19_ULT_7___d296 && + !txRS_preambleCnt_value_19_ULT_7___d183 && txRS_preambleCnt_value != 5'd7 || WILL_FIRE_RL_txRS_egress_EOF || WILL_FIRE_RL_txRS_egress_Body ; @@ -1369,15 +1368,15 @@ module mkGMAC(CLK_rxClk, // submodule txRS_txF assign txRS_txF$sD_IN = - { CASE_tx_put_BITS_9_TO_8_3_0_tx_put_BITS_9_TO_8_ETC__q2, + { CASE_tx_put_BITS_9_TO_8_0_tx_put_BITS_9_TO_8_1_ETC__q2, tx_put[7:0] } ; assign txRS_txF$sENQ = EN_tx_put ; assign txRS_txF$dDEQ = WILL_FIRE_RL_txRS_egress_SOF && - !txRS_preambleCnt_value_19_ULT_7___d296 && + !txRS_preambleCnt_value_19_ULT_7___d183 && txRS_preambleCnt_value != 5'd7 || WILL_FIRE_RL_txRS_egress_EOF && - !txRS_lenCnt_value_45_ULT_59___d295 || + !txRS_lenCnt_value_45_ULT_59___d209 || WILL_FIRE_RL_txRS_egress_Body ; // submodule txRS_txOperateS @@ -1392,25 +1391,26 @@ module mkGMAC(CLK_rxClk, assign txRS_unfBit$sEN = txRS_txOperateS$dD_OUT ; // remaining internal signals - assign txRS_lenCnt_value_45_ULT_59___d295 = txRS_lenCnt_value < 12'd59 ; - assign txRS_preambleCnt_value_19_ULT_7___d296 = + assign txRS_lenCnt_value_45_ULT_59___d209 = txRS_lenCnt_value < 12'd59 ; + assign txRS_preambleCnt_value_19_ULT_7___d183 = txRS_preambleCnt_value < 5'd7 ; + assign x__h13660 = txRS_emitFCS - 3'd1 ; always@(rxRS_rxF$dD_OUT) begin case (rxRS_rxF$dD_OUT[9:8]) 2'd0, 2'd1, 2'd2: - CASE_rxRS_rxFdD_OUT_BITS_9_TO_8_3_0_rxRS_rxF_ETC__q1 = + CASE_rxRS_rxFdD_OUT_BITS_9_TO_8_0_rxRS_rxFdD_ETC__q1 = rxRS_rxF$dD_OUT[9:8]; - 2'd3: CASE_rxRS_rxFdD_OUT_BITS_9_TO_8_3_0_rxRS_rxF_ETC__q1 = 2'd3; + 2'd3: CASE_rxRS_rxFdD_OUT_BITS_9_TO_8_0_rxRS_rxFdD_ETC__q1 = 2'd3; endcase end always@(tx_put) begin case (tx_put[9:8]) 2'd0, 2'd1, 2'd2: - CASE_tx_put_BITS_9_TO_8_3_0_tx_put_BITS_9_TO_8_ETC__q2 = + CASE_tx_put_BITS_9_TO_8_0_tx_put_BITS_9_TO_8_1_ETC__q2 = tx_put[9:8]; - 2'd3: CASE_tx_put_BITS_9_TO_8_3_0_tx_put_BITS_9_TO_8_ETC__q2 = 2'd3; + 2'd3: CASE_tx_put_BITS_9_TO_8_0_tx_put_BITS_9_TO_8_1_ETC__q2 = 2'd3; endcase end @@ -1574,13 +1574,13 @@ module mkGMAC(CLK_rxClk, if (txRS_txRst$OUT_RST != `BSV_RESET_VALUE) if (WILL_FIRE_RL_txRS_egress_FCS && txRS_emitFCS == 3'd4) begin - v__h12565 = $time; + v__h12643 = $time; #0; end if (txRS_txRst$OUT_RST != `BSV_RESET_VALUE) if (WILL_FIRE_RL_txRS_egress_FCS && txRS_emitFCS == 3'd4) $display("[%0d]: %m: TX FCS:%08x from %d elements", - v__h12565, + v__h12643, { txRS_crc$result[7:0], txRS_crc$result[15:8], txRS_crc$result[23:16], @@ -1597,13 +1597,13 @@ module mkGMAC(CLK_rxClk, if (rxRS_rxRst$OUT_RST != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rxRS_ingress_noadvance) begin - v__h6617 = $time; + v__h6699 = $time; #0; end if (rxRS_rxRst$OUT_RST != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rxRS_ingress_noadvance) $display("[%0d]: %m: RX FCS:%08x from %d elements", - v__h6617, + v__h6699, rxRS_crc$complete, $unsigned(rxRS_crcDbgCnt_value)); end diff --git a/rtl/mkGbeWorker.v b/rtl/mkGbeWorker.v index b243c562..24f9a031 100644 --- a/rtl/mkGbeWorker.v +++ b/rtl/mkGbeWorker.v @@ -1,7 +1,7 @@ // -// Generated by Bluespec Compiler, version 2012.09.beta1 (build 29570, 2012-09.11) +// Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Wed Nov 28 10:32:12 EST 2012 +// On Fri Jun 21 16:57:33 EDT 2013 // // // Ports: @@ -516,9 +516,9 @@ module mkGbeWorker(CLK_gmii_rx_clk, wire [15 : 0] mdi_rWriteData$D_IN; wire mdi_rWriteData$EN; - // register mdi_vrReadData - reg mdi_vrReadData; - wire mdi_vrReadData$D_IN, mdi_vrReadData$EN; + // register mdi_vrReadData_0 + reg mdi_vrReadData_0; + wire mdi_vrReadData_0$D_IN, mdi_vrReadData_0$EN; // register mdi_vrReadData_1 reg mdi_vrReadData_1; @@ -755,10 +755,10 @@ module mkGbeWorker(CLK_gmii_rx_clk, wire [1 : 0] wci_wslv_reqF_countReg$D_IN; wire wci_wslv_reqF_countReg$EN; - // register wci_wslv_respF_c_r - reg [1 : 0] wci_wslv_respF_c_r; - wire [1 : 0] wci_wslv_respF_c_r$D_IN; - wire wci_wslv_respF_c_r$EN; + // register wci_wslv_respF_cntr_r + reg [1 : 0] wci_wslv_respF_cntr_r; + wire [1 : 0] wci_wslv_respF_cntr_r$D_IN; + wire wci_wslv_respF_cntr_r$EN; // register wci_wslv_respF_q_0 reg [33 : 0] wci_wslv_respF_q_0; @@ -809,10 +809,10 @@ module mkGbeWorker(CLK_gmii_rx_clk, reg wsiM_peerIsReady; wire wsiM_peerIsReady$D_IN, wsiM_peerIsReady$EN; - // register wsiM_reqFifo_c_r - reg [1 : 0] wsiM_reqFifo_c_r; - wire [1 : 0] wsiM_reqFifo_c_r$D_IN; - wire wsiM_reqFifo_c_r$EN; + // register wsiM_reqFifo_cntr_r + reg [1 : 0] wsiM_reqFifo_cntr_r; + wire [1 : 0] wsiM_reqFifo_cntr_r$D_IN; + wire wsiM_reqFifo_cntr_r$EN; // register wsiM_reqFifo_q_0 reg [60 : 0] wsiM_reqFifo_q_0; @@ -1062,7 +1062,6 @@ module mkGbeWorker(CLK_gmii_rx_clk, // rule scheduling signals wire CAN_FIRE_RL_rx_dcp, - CAN_FIRE_RL_tx_dcp, CAN_FIRE_RL_wci_cfwr, WILL_FIRE_RL_dcp_cp_response, WILL_FIRE_RL_dcp_dcp_request, @@ -1097,9 +1096,8 @@ module mkGbeWorker(CLK_gmii_rx_clk, wire [26 : 0] MUX_mdi_fRequest$enq_1__VAL_1, MUX_mdi_fRequest$enq_1__VAL_2; wire [4 : 0] MUX_rxDCPMesgPos$write_1__VAL_1; wire [3 : 0] MUX_rxHdr_mCnt$write_1__VAL_1, MUX_rxHdr_pos$write_1__VAL_1; - wire [1 : 0] MUX_wci_wslv_respF_c_r$write_1__VAL_1, - MUX_wci_wslv_respF_c_r$write_1__VAL_2, - MUX_wsiM_reqFifo_c_r$write_1__VAL_2; + wire [1 : 0] MUX_wci_wslv_respF_cntr_r$write_1__VAL_2, + MUX_wsiM_reqFifo_cntr_r$write_1__VAL_1; wire MUX_dcp_dcpRespF$enq_1__SEL_1, MUX_dcp_doInFlight$write_1__SEL_1, MUX_mdi_fRequest$enq_1__SEL_1, @@ -1112,107 +1110,118 @@ module mkGbeWorker(CLK_gmii_rx_clk, MUX_splitReadInFlight$write_1__SEL_1, MUX_wci_wslv_illegalEdge$write_1__SEL_1, MUX_wci_wslv_illegalEdge$write_1__VAL_1, + MUX_wci_wslv_respF_q_0$write_1__SEL_1, MUX_wci_wslv_respF_q_0$write_1__SEL_2, + MUX_wci_wslv_respF_q_1$write_1__SEL_1, MUX_wci_wslv_respF_q_1$write_1__SEL_2, MUX_wci_wslv_respF_x_wire$wset_1__SEL_1, MUX_wci_wslv_respF_x_wire$wset_1__SEL_3, MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3; // remaining internal signals - reg [63 : 0] v__h101757, v__h3708, v__h3883, v__h4027, v__h81480, v__h81774; - reg [31 : 0] IF_wci_wslv_reqF_first__5_BITS_39_TO_32_57_EQ__ETC___d1110; - reg [9 : 0] CASE_dcpRespFD_OUT_BITS_44_TO_43_IF_txDCPPos__ETC__q9, - CASE_txDCPPos_1_CONCAT_dcpRespFD_OUT_BITS_17__ETC__q7, - CASE_txDCPPos_1_CONCAT_dcpRespFD_OUT_BITS_17__ETC__q8; - reg [7 : 0] CASE_13_MINUS_txDCPPos_rxHdr_sV_BITS_63_TO_56__ETC__q6, - CASE_rxHdr_pos_rxHdr_pV_BITS_111_TO_104_0_rxHd_ETC__q2, - CASE_rxHdr_pos_rxHdr_sV_BITS_111_TO_104_0_rxHd_ETC__q1, - IF_rxDCPMesgPos_75_EQ_5_16_THEN_rxDCPMesg_82_B_ETC___d1200, - tag__h71936; - reg [4 : 0] CASE_dcpRespFD_OUT_BITS_44_TO_43_IF_txDCPPos__ETC__q11; - reg [1 : 0] CASE_dcp_dcpRespFD_OUT_BITS_44_TO_43_2_0_dcp__ETC__q5; - reg CASE_IF_rxDCPMesgPos_75_EQ_5_16_THEN_rxDCPMesg_ETC__q4, - CASE_dcpRespFD_OUT_BITS_44_TO_43_IF_txDCPPos__ETC__q3, - IF_txDCPPos_16_EQ_0_17_OR_txDCPPos_16_EQ_1_18__ETC___d1324; - wire [194 : 0] _1434766110945527031733894725304609466537681244_ETC__q10, - _643371375338640__q12, - bs__h12923, - bs__h25448; - wire [31 : 0] rdat___1__h81993, - rdat___1__h82044, - rdat___1__h82085, - rdat___1__h82120, - rdat___1__h82153, - rdat___1__h82194, - rdat___1__h82229, - rdat___1__h82263, - rdat___1__h82296, - rdat___1__h82330, - rdat___1__h82363, - rdat___1__h82396, - rdat___1__h82429, - rdat___1__h82462, - rdat___1__h82495, - rdat___1__h82528, - rdat___1__h82562, - rdat___1__h82595, - rdat___1__h82629, - rdat___1__h82663, - rdat___1__h82700, - rdat___1__h82737, - rdat___1__h85238, - rdat___1__h87736, - rdat___1__h90237, - rdat___1__h92735, - rdat___1__h95236, - rdat___1__h96843, - rdat___1__h98413, - rdat___1__h99983, - rdat__h81758, - status__h81559, - x__h71721; - wire [15 : 0] x__h81839, x__h81997, x_data__h28646; - wire [4 : 0] IF_txDCPPos_16_EQ_9_34_THEN_0_ELSE_txDCPPos_16_ETC___d1336, - txDCPPos_16_PLUS_1___d1251; - wire [2 : 0] d0__h12549, - d10__h12539, - d11__h12538, - d12__h12537, - d13__h12536, - d14__h12535, - d15__h12534, - d1__h12548, - d2__h12547, - d3__h12546, - d4__h12545, - d5__h12544, - d6__h12543, - d7__h12542, - d8__h12541, - d9__h12540, - pa0__h12526, - pa1__h12525, - pa2__h12524, - pa3__h12523, - pa4__h12522, - ra0__h12532, - ra1__h12531, - ra2__h12530, - ra3__h12529, - ra4__h12528; - wire IF_dcp_dcpReqF_first__42_BITS_78_TO_77_43_EQ_0_ETC___d475, - IF_dcp_dcpReqF_first__42_BITS_78_TO_77_43_EQ_1_ETC___d473, - IF_rxHdr_pos_74_EQ_0_90_THEN_rxHdr_sV_56_BITS__ETC___d659, - NOT_rxHdr_sV_56_BIT_112_57_74_AND_rxHdr_sV_56__ETC___d680, - NOT_rxHdr_sV_56_BIT_112_57_74_AND_rxHdr_sV_56__ETC___d869, - dcpRespF_i_notEmpty__12_AND_IF_dcpRespF_first__ETC___d845, - dcp_dcpReqF_first__42_BITS_39_TO_32_47_EQ_IF_d_ETC___d1172, - dcp_dcpReqF_first__42_BITS_71_TO_64_60_EQ_IF_d_ETC___d1171, - dcp_dcpReqF_first__42_BITS_78_TO_77_43_EQ_0_44_ETC___d478, - dcp_dcpReqF_first__42_BITS_78_TO_77_43_EQ_1_46_ETC___d519, - gmac_rx_get_68_BITS_9_TO_8_69_EQ_0_70_OR_gmac__ETC___d662, - rxHdr_sV_56_BIT_112_57_OR_NOT_rxHdr_sV_56_BITS_ETC___d952, - wci_wslv_reqF_i_notEmpty__4_AND_IF_wci_wslv_re_ETC___d982; + reg [63 : 0] v__h101273, v__h3576, v__h3751, v__h3895, v__h80732, v__h81026; + reg [31 : 0] IF_wci_wslv_reqF_first__3_BITS_39_TO_32_52_EQ__ETC___d1005; + reg [9 : 0] CASE_dcpRespFD_OUT_BITS_44_TO_43_0_CASE_txDCP_ETC__q11, + CASE_txDCPPos_0_0_1_10_2_0_3_0_4_49_5_0_CONCAT_ETC__q9, + CASE_txDCPPos_0_0_1_10_2_0_3_0_4_51_5_0_CONCAT_ETC__q8, + CASE_txDCPPos_0_0_1_6_2_0_3_0_4_50_1_CONCAT_dc_ETC__q10; + reg [7 : 0] CASE_rxHdr_pos_0_rxHdr_pV_BITS_7_TO_0_1_rxHdr__ETC__q2, + CASE_rxHdr_pos_0_rxHdr_sV_BITS_7_TO_0_1_rxHdr__ETC__q1, + SEL_ARR_rxDCPMesg_41_BITS_7_TO_0_75_rxDCPMesg__ETC___d691, + SEL_ARR_rxHdr_sV_52_BITS_7_TO_0_86_rxHdr_sV_52_ETC___d800, + tag__h71856; + reg [4 : 0] CASE_dcpRespFD_OUT_BITS_44_TO_43_0_IF_txDCPPo_ETC__q13; + reg [1 : 0] CASE_dcp_dcpRespFD_OUT_BITS_44_TO_43_0_dcp_dc_ETC__q7, + CASE_dcp_lastResp_BITS_44_TO_43_0_dcp_lastResp_ETC__q6; + reg CASE_SEL_ARR_rxDCPMesg_41_BITS_7_TO_0_75_rxDCP_ETC__q5, + CASE_dcpRespFD_OUT_BITS_44_TO_43_0_IF_txDCPPo_ETC__q4, + CASE_txDCPPos_0_gmacRDY_tx_put_1_gmacRDY_tx__ETC__q3, + IF_txDCPPos_37_EQ_0_38_OR_txDCPPos_37_EQ_1_39__ETC___d759; + wire [194 : 0] _1434766110945527031733894725304609466537681244_ETC__q12, + _643371375338640__q14, + bs__h12646, + bs__h25405; + wire [31 : 0] rdat___1__h81245, + rdat___1__h81296, + rdat___1__h81337, + rdat___1__h81372, + rdat___1__h81405, + rdat___1__h81446, + rdat___1__h81481, + rdat___1__h81515, + rdat___1__h81548, + rdat___1__h81582, + rdat___1__h81615, + rdat___1__h81648, + rdat___1__h81681, + rdat___1__h81714, + rdat___1__h81747, + rdat___1__h81780, + rdat___1__h81814, + rdat___1__h81847, + rdat___1__h81881, + rdat___1__h81915, + rdat___1__h81952, + rdat___1__h81989, + rdat___1__h84530, + rdat___1__h87068, + rdat___1__h89609, + rdat___1__h92147, + rdat___1__h94688, + rdat___1__h96311, + rdat___1__h97897, + rdat___1__h99483, + rdat__h81010, + status__h80811, + x__h71643; + wire [15 : 0] x__h81091, x__h81249, x_data__h28682; + wire [4 : 0] IF_txDCPPos_37_EQ_9_55_THEN_0_ELSE_txDCPPos_37_ETC___d835, + txDCPPos_37_PLUS_1___d833, + x__h71912, + x__h72062, + x__h74515; + wire [2 : 0] d0__h12272, + d10__h12262, + d11__h12261, + d12__h12260, + d13__h12259, + d14__h12258, + d15__h12257, + d1__h12271, + d2__h12270, + d3__h12269, + d4__h12268, + d5__h12267, + d6__h12266, + d7__h12265, + d8__h12264, + d9__h12263, + pa0__h12249, + pa1__h12248, + pa2__h12247, + pa3__h12246, + pa4__h12245, + ra0__h12255, + ra1__h12254, + ra2__h12253, + ra3__h12252, + ra4__h12251; + wire [1 : 0] wci_wslv_respF_cntr_r_8_MINUS_1___d27; + wire IF_NOT_rxHdr_sV_52_BIT_112_53_33_AND_rxHdr_sV__ETC___d767, + IF_dcp_dcpReqF_first__38_BITS_78_TO_77_39_EQ_0_ETC___d471, + IF_dcp_dcpReqF_first__38_BITS_78_TO_77_39_EQ_1_ETC___d469, + NOT_rxHdr_sV_52_BIT_112_53_33_AND_rxHdr_sV_52__ETC___d639, + NOT_rxHdr_sV_52_BIT_112_53_33_AND_rxHdr_sV_52__ETC___d790, + SEL_ARR_rxHdr_sV_52_BITS_7_TO_0_86_rxHdr_sV_52_ETC___d618, + _dfoo1, + _dfoo3, + dcp_dcpReqF_first__38_BITS_39_TO_32_43_EQ_IF_d_ETC___d448, + dcp_dcpReqF_first__38_BITS_71_TO_64_56_EQ_IF_d_ETC___d457, + dcp_dcpReqF_first__38_BITS_78_TO_77_39_EQ_0_40_ETC___d474, + dcp_dcpReqF_first__38_BITS_78_TO_77_39_EQ_1_42_ETC___d515, + gmac_rx_get_64_BITS_9_TO_8_65_EQ_0_66_OR_gmac__ETC___d621, + rxHdr_sV_52_BIT_112_53_OR_NOT_rxHdr_sV_52_BITS_ETC___d847, + wci_wslv_reqF_i_notEmpty__2_AND_IF_wci_wslv_re_ETC___d877; // oscillator and gates for output clock CLK_gmii_tx_tx_clk assign CLK_gmii_tx_tx_clk = gmac$CLK_gmii_tx_tx_clk ; @@ -1518,13 +1527,13 @@ module mkGbeWorker(CLK_gmii_rx_clk, // rule RL_rx_dcp assign CAN_FIRE_RL_rx_dcp = rxDCPHdrF$EMPTY_N && - CASE_IF_rxDCPMesgPos_75_EQ_5_16_THEN_rxDCPMesg_ETC__q4 && + CASE_SEL_ARR_rxDCPMesg_41_BITS_7_TO_0_75_rxDCP_ETC__q5 && wci_wslv_cState == 3'd2 ; assign WILL_FIRE_RL_rx_dcp = CAN_FIRE_RL_rx_dcp && !WILL_FIRE_RL_rx_data ; // rule RL_wci_cfwr assign CAN_FIRE_RL_wci_cfwr = - wci_wslv_respF_c_r != 2'd2 && wci_wslv_reqF$EMPTY_N && + wci_wslv_respF_cntr_r != 2'd2 && wci_wslv_reqF$EMPTY_N && (wci_wslv_reqF$D_OUT[39] ? mdi_fRequest$FULL_N : wci_wslv_reqF$D_OUT[39:32] != 8'h20 || txDBGF$FULL_N) && @@ -1561,11 +1570,11 @@ module mkGbeWorker(CLK_gmii_rx_clk, // rule RL_wsiM_reqFifo_deq assign WILL_FIRE_RL_wsiM_reqFifo_deq = - wsiM_reqFifo_c_r != 2'd0 && !wsiM_sThreadBusy_d ; + wsiM_reqFifo_cntr_r != 2'd0 && !wsiM_sThreadBusy_d ; // rule RL_wci_cfrd assign WILL_FIRE_RL_wci_cfrd = - wci_wslv_reqF_i_notEmpty__4_AND_IF_wci_wslv_re_ETC___d982 && + wci_wslv_reqF_i_notEmpty__2_AND_IF_wci_wslv_re_ETC___d877 && wci_wslv_wci_cfrd_pw$whas && !WILL_FIRE_RL_wci_wslv_ctl_op_start && !WILL_FIRE_RL_wci_wslv_ctl_op_complete && @@ -1579,37 +1588,30 @@ module mkGbeWorker(CLK_gmii_rx_clk, wci_wslv_cState == 3'd2 ; // rule RL_tx_dcp - assign CAN_FIRE_RL_tx_dcp = - ((!rxHdr_sV[112] && rxHdr_sV[15:0] == 16'hF040) ? - gmac$RDY_tx_put : - dcpRespF_i_notEmpty__12_AND_IF_dcpRespF_first__ETC___d845) && - wci_wslv_cState == 3'd2 ; - assign WILL_FIRE_RL_tx_dcp = CAN_FIRE_RL_tx_dcp && !WILL_FIRE_RL_rx_data ; + assign WILL_FIRE_RL_tx_dcp = + IF_NOT_rxHdr_sV_52_BIT_112_53_33_AND_rxHdr_sV__ETC___d767 && + wci_wslv_cState == 3'd2 && + !WILL_FIRE_RL_rx_data ; // rule RL_wci_wslv_ctl_op_complete assign WILL_FIRE_RL_wci_wslv_ctl_op_complete = - wci_wslv_respF_c_r != 2'd2 && wci_wslv_ctlOpActive && + wci_wslv_respF_cntr_r != 2'd2 && wci_wslv_ctlOpActive && wci_wslv_ctlAckReg && !MUX_wci_wslv_respF_x_wire$wset_1__SEL_3 ; // rule RL_wci_wslv_respF_incCtr assign WILL_FIRE_RL_wci_wslv_respF_incCtr = - ((wci_wslv_respF_c_r == 2'd0) ? - wci_wslv_respF_x_wire$whas : - wci_wslv_respF_c_r != 2'd1 || wci_wslv_respF_x_wire$whas) && - wci_wslv_respF_enqueueing$whas && - !(wci_wslv_respF_c_r != 2'd0) ; + wci_wslv_respF_x_wire$whas && wci_wslv_respF_enqueueing$whas && + !(wci_wslv_respF_cntr_r != 2'd0) ; // rule RL_wci_wslv_respF_decCtr assign WILL_FIRE_RL_wci_wslv_respF_decCtr = - wci_wslv_respF_c_r != 2'd0 && !wci_wslv_respF_enqueueing$whas ; + wci_wslv_respF_cntr_r != 2'd0 && + !wci_wslv_respF_enqueueing$whas ; // rule RL_wci_wslv_respF_both assign WILL_FIRE_RL_wci_wslv_respF_both = - ((wci_wslv_respF_c_r == 2'd1) ? - wci_wslv_respF_x_wire$whas : - wci_wslv_respF_c_r != 2'd2 || wci_wslv_respF_x_wire$whas) && - wci_wslv_respF_c_r != 2'd0 && + wci_wslv_respF_x_wire$whas && wci_wslv_respF_cntr_r != 2'd0 && wci_wslv_respF_enqueueing$whas ; // rule RL_mdi_run_frame @@ -1622,7 +1624,7 @@ module mkGbeWorker(CLK_gmii_rx_clk, // rule RL_dcp_dcp_request assign WILL_FIRE_RL_dcp_dcp_request = dcp_dcpReqF$EMPTY_N && - IF_dcp_dcpReqF_first__42_BITS_78_TO_77_43_EQ_0_ETC___d475 ; + IF_dcp_dcpReqF_first__38_BITS_78_TO_77_39_EQ_0_ETC___d471 ; // rule RL_dcp_cp_response assign WILL_FIRE_RL_dcp_cp_response = @@ -1642,7 +1644,7 @@ module mkGbeWorker(CLK_gmii_rx_clk, // inputs to muxes for submodule ports assign MUX_dcp_dcpRespF$enq_1__SEL_1 = WILL_FIRE_RL_dcp_dcp_request && - dcp_dcpReqF_first__42_BITS_78_TO_77_43_EQ_0_44_ETC___d478 ; + dcp_dcpReqF_first__38_BITS_78_TO_77_39_EQ_0_40_ETC___d474 ; assign MUX_dcp_doInFlight$write_1__SEL_1 = WILL_FIRE_RL_dcp_dcp_request && (dcp_dcpReqF$D_OUT[78:77] == 2'd0 && dcp_dcpReqF$D_OUT[40] || @@ -1657,15 +1659,15 @@ module mkGbeWorker(CLK_gmii_rx_clk, assign MUX_rxDCPMesgPos$write_1__SEL_1 = WILL_FIRE_RL_rx_data && (gmac$rx_get[9:8] == 2'd0 || gmac$rx_get[9:8] == 2'd1) && - NOT_rxHdr_sV_56_BIT_112_57_74_AND_rxHdr_sV_56__ETC___d680 ; + NOT_rxHdr_sV_52_BIT_112_53_33_AND_rxHdr_sV_52__ETC___d639 ; assign MUX_rxDCPPLI$write_1__SEL_1 = WILL_FIRE_RL_rx_data && (gmac$rx_get[9:8] == 2'd0 || gmac$rx_get[9:8] == 2'd1) && - NOT_rxHdr_sV_56_BIT_112_57_74_AND_rxHdr_sV_56__ETC___d680 && + NOT_rxHdr_sV_52_BIT_112_53_33_AND_rxHdr_sV_52__ETC___d639 && rxDCPMesgPos == 5'd1 ; assign MUX_rxHdr_mCnt$write_1__SEL_1 = WILL_FIRE_RL_rx_data && - gmac_rx_get_68_BITS_9_TO_8_69_EQ_0_70_OR_gmac__ETC___d662 ; + gmac_rx_get_64_BITS_9_TO_8_65_EQ_0_66_OR_gmac__ETC___d621 ; assign MUX_rxHdr_pos$write_1__SEL_1 = WILL_FIRE_RL_rx_data && (gmac$rx_get[9:8] == 2'd0 || gmac$rx_get[9:8] == 2'd1) && @@ -1685,21 +1687,27 @@ module mkGbeWorker(CLK_gmii_rx_clk, wci_wslv_reqF$D_OUT[36:34] == 3'd5 || wci_wslv_reqF$D_OUT[36:34] == 3'd6 || wci_wslv_reqF$D_OUT[36:34] == 3'd7) ; + assign MUX_wci_wslv_respF_q_0$write_1__SEL_1 = + WILL_FIRE_RL_wci_wslv_respF_both && _dfoo3 ; assign MUX_wci_wslv_respF_q_0$write_1__SEL_2 = WILL_FIRE_RL_wci_wslv_respF_incCtr && - wci_wslv_respF_c_r == 2'd0 ; + wci_wslv_respF_cntr_r == 2'd0 ; + assign MUX_wci_wslv_respF_q_1$write_1__SEL_1 = + WILL_FIRE_RL_wci_wslv_respF_both && _dfoo1 ; assign MUX_wci_wslv_respF_q_1$write_1__SEL_2 = WILL_FIRE_RL_wci_wslv_respF_incCtr && - wci_wslv_respF_c_r == 2'd1 ; + wci_wslv_respF_cntr_r == 2'd1 ; assign MUX_wci_wslv_respF_x_wire$wset_1__SEL_1 = WILL_FIRE_RL_wci_cfrd && !wci_wslv_reqF$D_OUT[39] ; assign MUX_wci_wslv_respF_x_wire$wset_1__SEL_3 = - wci_wslv_respF_c_r != 2'd2 && mdi_fResponse$EMPTY_N && + wci_wslv_respF_cntr_r != 2'd2 && mdi_fResponse$EMPTY_N && !wci_wslv_wci_cfwr_pw$whas && splitReadInFlight ; assign MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 = wsiS_reqFifo$EMPTY_N && wci_wslv_cState == 3'd2 ; - always@(dcp_dcpReqF$D_OUT or dcp_lastResp) + always@(dcp_dcpReqF$D_OUT or + CASE_dcp_lastResp_BITS_44_TO_43_0_dcp_lastResp_ETC__q6 or + dcp_lastResp) begin case (dcp_dcpReqF$D_OUT[78:77]) 2'd0: @@ -1717,10 +1725,7 @@ module mkGbeWorker(CLK_gmii_rx_clk, dcp_dcpReqF$D_OUT[71:64], 2'd0 }; default: MUX_dcp_dcpRespF$enq_1__VAL_1 = - { (dcp_lastResp[44:43] == 2'd0 || - dcp_lastResp[44:43] == 2'd1) ? - dcp_lastResp[44:43] : - 2'd2, + { CASE_dcp_lastResp_BITS_44_TO_43_0_dcp_lastResp_ETC__q6, dcp_lastResp[42:0] }; endcase end @@ -1747,10 +1752,10 @@ module mkGbeWorker(CLK_gmii_rx_clk, wci_wslv_reqF$D_OUT[36:34] != 3'd4 && wci_wslv_reqF$D_OUT[36:34] != 3'd5 && wci_wslv_reqF$D_OUT[36:34] != 3'd6 ; - assign MUX_wci_wslv_respF_c_r$write_1__VAL_1 = wci_wslv_respF_c_r + 2'd1 ; - assign MUX_wci_wslv_respF_c_r$write_1__VAL_2 = wci_wslv_respF_c_r - 2'd1 ; + assign MUX_wci_wslv_respF_cntr_r$write_1__VAL_2 = + wci_wslv_respF_cntr_r + 2'd1 ; assign MUX_wci_wslv_respF_q_0$write_1__VAL_1 = - (wci_wslv_respF_c_r == 2'd1) ? + (wci_wslv_respF_cntr_r == 2'd1) ? MUX_wci_wslv_respF_q_0$write_1__VAL_2 : wci_wslv_respF_q_1 ; always@(MUX_wci_wslv_respF_x_wire$wset_1__SEL_1 or @@ -1777,15 +1782,15 @@ module mkGbeWorker(CLK_gmii_rx_clk, endcase end assign MUX_wci_wslv_respF_q_1$write_1__VAL_1 = - (wci_wslv_respF_c_r == 2'd2) ? + (wci_wslv_respF_cntr_r == 2'd2) ? MUX_wci_wslv_respF_q_0$write_1__VAL_2 : 34'h0AAAAAAAA ; - assign MUX_wci_wslv_respF_x_wire$wset_1__VAL_1 = { 2'd1, rdat__h81758 } ; + assign MUX_wci_wslv_respF_x_wire$wset_1__VAL_1 = { 2'd1, rdat__h81010 } ; assign MUX_wci_wslv_respF_x_wire$wset_1__VAL_2 = wci_wslv_illegalEdge ? 34'h3C0DE4202 : 34'h1C0DE4201 ; assign MUX_wci_wslv_respF_x_wire$wset_1__VAL_3 = { 18'd65536, mdi_fResponse$D_OUT[15:0] } ; - assign MUX_wsiM_reqFifo_c_r$write_1__VAL_2 = wsiM_reqFifo_c_r - 2'd1 ; + assign MUX_wsiM_reqFifo_cntr_r$write_1__VAL_1 = wsiM_reqFifo_cntr_r - 2'd1 ; // inlined wires assign wci_wslv_wciReq$wget = @@ -1866,7 +1871,7 @@ module mkGbeWorker(CLK_gmii_rx_clk, MUX_wci_wslv_respF_x_wire$wset_1__SEL_3 || WILL_FIRE_RL_wci_cfwr || WILL_FIRE_RL_wci_wslv_ctl_op_complete ; - assign wci_wslv_respF_dequeueing$whas = wci_wslv_respF_c_r != 2'd0 ; + assign wci_wslv_respF_dequeueing$whas = wci_wslv_respF_cntr_r != 2'd0 ; assign wci_wslv_sThreadBusy_pw$whas = 1'b0 ; assign wci_wslv_wci_cfwr_pw$whas = wci_wslv_reqF$EMPTY_N && wci_wslv_reqF$D_OUT[68] && @@ -1922,11 +1927,11 @@ module mkGbeWorker(CLK_gmii_rx_clk, (dcp_dcpReqF$D_OUT[78:77] == 2'd0 && !dcp_dcpReqF$D_OUT[40] || dcp_dcpReqF$D_OUT[78:77] != 2'd0 && (dcp_dcpReqF$D_OUT[78:77] == 2'd1 && - (!dcp_dcpReqF_first__42_BITS_71_TO_64_60_EQ_IF_d_ETC___d1171 || + (!dcp_dcpReqF_first__38_BITS_71_TO_64_56_EQ_IF_d_ETC___d457 || !dcp_lastTag[8]) && !dcp_dcpReqF$D_OUT[76] || dcp_dcpReqF$D_OUT[78:77] != 2'd1 && - (!dcp_dcpReqF_first__42_BITS_39_TO_32_47_EQ_IF_d_ETC___d1172 || + (!dcp_dcpReqF_first__38_BITS_39_TO_32_43_EQ_IF_d_ETC___d448 || !dcp_lastTag[8]) && !dcp_dcpReqF$D_OUT[44])) ; @@ -1941,15 +1946,15 @@ module mkGbeWorker(CLK_gmii_rx_clk, // register mdi_rMDC assign mdi_rMDC$D_IN = - _1434766110945527031733894725304609466537681244_ETC__q10[mdi_rPlayIndex$Q_OUT] ; + _1434766110945527031733894725304609466537681244_ETC__q12[mdi_rPlayIndex$Q_OUT] ; assign mdi_rMDC$EN = WILL_FIRE_RL_mdi_run_frame ; // register mdi_rMDD - assign mdi_rMDD$D_IN = bs__h12923[mdi_rPlayIndex$Q_OUT] ; + assign mdi_rMDD$D_IN = bs__h12646[mdi_rPlayIndex$Q_OUT] ; assign mdi_rMDD$EN = WILL_FIRE_RL_mdi_run_frame ; // register mdi_rOutEn - assign mdi_rOutEn$D_IN = bs__h25448[mdi_rPlayIndex$Q_OUT] ; + assign mdi_rOutEn$D_IN = bs__h25405[mdi_rPlayIndex$Q_OUT] ; assign mdi_rOutEn$EN = WILL_FIRE_RL_mdi_run_frame ; // register mdi_rPhyAddr @@ -1974,117 +1979,117 @@ module mkGbeWorker(CLK_gmii_rx_clk, assign mdi_rWriteData$D_IN = mdi_fRequest$D_OUT[15:0] ; assign mdi_rWriteData$EN = MUX_mdi_rState$write_1__SEL_2 ; - // register mdi_vrReadData - assign mdi_vrReadData$D_IN = mdi_tMDD$O ; - assign mdi_vrReadData$EN = + // register mdi_vrReadData_0 + assign mdi_vrReadData_0$D_IN = mdi_tMDD$O ; + assign mdi_vrReadData_0$EN = WILL_FIRE_RL_mdi_run_frame && mdi_rPlayIndex$Q_OUT != 8'd0 && !mdi_rWrite && - _643371375338640__q12[mdi_rPlayIndex$Q_OUT] ; + _643371375338640__q14[mdi_rPlayIndex$Q_OUT] ; // register mdi_vrReadData_1 - assign mdi_vrReadData_1$D_IN = mdi_vrReadData ; + assign mdi_vrReadData_1$D_IN = mdi_vrReadData_0 ; assign mdi_vrReadData_1$EN = WILL_FIRE_RL_mdi_run_frame && mdi_rPlayIndex$Q_OUT != 8'd0 && !mdi_rWrite && - _643371375338640__q12[mdi_rPlayIndex$Q_OUT] ; + _643371375338640__q14[mdi_rPlayIndex$Q_OUT] ; // register mdi_vrReadData_10 assign mdi_vrReadData_10$D_IN = mdi_vrReadData_9 ; assign mdi_vrReadData_10$EN = WILL_FIRE_RL_mdi_run_frame && mdi_rPlayIndex$Q_OUT != 8'd0 && !mdi_rWrite && - _643371375338640__q12[mdi_rPlayIndex$Q_OUT] ; + _643371375338640__q14[mdi_rPlayIndex$Q_OUT] ; // register mdi_vrReadData_11 assign mdi_vrReadData_11$D_IN = mdi_vrReadData_10 ; assign mdi_vrReadData_11$EN = WILL_FIRE_RL_mdi_run_frame && mdi_rPlayIndex$Q_OUT != 8'd0 && !mdi_rWrite && - _643371375338640__q12[mdi_rPlayIndex$Q_OUT] ; + _643371375338640__q14[mdi_rPlayIndex$Q_OUT] ; // register mdi_vrReadData_12 assign mdi_vrReadData_12$D_IN = mdi_vrReadData_11 ; assign mdi_vrReadData_12$EN = WILL_FIRE_RL_mdi_run_frame && mdi_rPlayIndex$Q_OUT != 8'd0 && !mdi_rWrite && - _643371375338640__q12[mdi_rPlayIndex$Q_OUT] ; + _643371375338640__q14[mdi_rPlayIndex$Q_OUT] ; // register mdi_vrReadData_13 assign mdi_vrReadData_13$D_IN = mdi_vrReadData_12 ; assign mdi_vrReadData_13$EN = WILL_FIRE_RL_mdi_run_frame && mdi_rPlayIndex$Q_OUT != 8'd0 && !mdi_rWrite && - _643371375338640__q12[mdi_rPlayIndex$Q_OUT] ; + _643371375338640__q14[mdi_rPlayIndex$Q_OUT] ; // register mdi_vrReadData_14 assign mdi_vrReadData_14$D_IN = mdi_vrReadData_13 ; assign mdi_vrReadData_14$EN = WILL_FIRE_RL_mdi_run_frame && mdi_rPlayIndex$Q_OUT != 8'd0 && !mdi_rWrite && - _643371375338640__q12[mdi_rPlayIndex$Q_OUT] ; + _643371375338640__q14[mdi_rPlayIndex$Q_OUT] ; // register mdi_vrReadData_15 assign mdi_vrReadData_15$D_IN = mdi_vrReadData_14 ; assign mdi_vrReadData_15$EN = WILL_FIRE_RL_mdi_run_frame && mdi_rPlayIndex$Q_OUT != 8'd0 && !mdi_rWrite && - _643371375338640__q12[mdi_rPlayIndex$Q_OUT] ; + _643371375338640__q14[mdi_rPlayIndex$Q_OUT] ; // register mdi_vrReadData_2 assign mdi_vrReadData_2$D_IN = mdi_vrReadData_1 ; assign mdi_vrReadData_2$EN = WILL_FIRE_RL_mdi_run_frame && mdi_rPlayIndex$Q_OUT != 8'd0 && !mdi_rWrite && - _643371375338640__q12[mdi_rPlayIndex$Q_OUT] ; + _643371375338640__q14[mdi_rPlayIndex$Q_OUT] ; // register mdi_vrReadData_3 assign mdi_vrReadData_3$D_IN = mdi_vrReadData_2 ; assign mdi_vrReadData_3$EN = WILL_FIRE_RL_mdi_run_frame && mdi_rPlayIndex$Q_OUT != 8'd0 && !mdi_rWrite && - _643371375338640__q12[mdi_rPlayIndex$Q_OUT] ; + _643371375338640__q14[mdi_rPlayIndex$Q_OUT] ; // register mdi_vrReadData_4 assign mdi_vrReadData_4$D_IN = mdi_vrReadData_3 ; assign mdi_vrReadData_4$EN = WILL_FIRE_RL_mdi_run_frame && mdi_rPlayIndex$Q_OUT != 8'd0 && !mdi_rWrite && - _643371375338640__q12[mdi_rPlayIndex$Q_OUT] ; + _643371375338640__q14[mdi_rPlayIndex$Q_OUT] ; // register mdi_vrReadData_5 assign mdi_vrReadData_5$D_IN = mdi_vrReadData_4 ; assign mdi_vrReadData_5$EN = WILL_FIRE_RL_mdi_run_frame && mdi_rPlayIndex$Q_OUT != 8'd0 && !mdi_rWrite && - _643371375338640__q12[mdi_rPlayIndex$Q_OUT] ; + _643371375338640__q14[mdi_rPlayIndex$Q_OUT] ; // register mdi_vrReadData_6 assign mdi_vrReadData_6$D_IN = mdi_vrReadData_5 ; assign mdi_vrReadData_6$EN = WILL_FIRE_RL_mdi_run_frame && mdi_rPlayIndex$Q_OUT != 8'd0 && !mdi_rWrite && - _643371375338640__q12[mdi_rPlayIndex$Q_OUT] ; + _643371375338640__q14[mdi_rPlayIndex$Q_OUT] ; // register mdi_vrReadData_7 assign mdi_vrReadData_7$D_IN = mdi_vrReadData_6 ; assign mdi_vrReadData_7$EN = WILL_FIRE_RL_mdi_run_frame && mdi_rPlayIndex$Q_OUT != 8'd0 && !mdi_rWrite && - _643371375338640__q12[mdi_rPlayIndex$Q_OUT] ; + _643371375338640__q14[mdi_rPlayIndex$Q_OUT] ; // register mdi_vrReadData_8 assign mdi_vrReadData_8$D_IN = mdi_vrReadData_7 ; assign mdi_vrReadData_8$EN = WILL_FIRE_RL_mdi_run_frame && mdi_rPlayIndex$Q_OUT != 8'd0 && !mdi_rWrite && - _643371375338640__q12[mdi_rPlayIndex$Q_OUT] ; + _643371375338640__q14[mdi_rPlayIndex$Q_OUT] ; // register mdi_vrReadData_9 assign mdi_vrReadData_9$D_IN = mdi_vrReadData_8 ; assign mdi_vrReadData_9$EN = WILL_FIRE_RL_mdi_run_frame && mdi_rPlayIndex$Q_OUT != 8'd0 && !mdi_rWrite && - _643371375338640__q12[mdi_rPlayIndex$Q_OUT] ; + _643371375338640__q14[mdi_rPlayIndex$Q_OUT] ; // register phyResetWaitCnt assign phyResetWaitCnt$D_IN = @@ -2119,7 +2124,7 @@ module mkGbeWorker(CLK_gmii_rx_clk, assign rxDCPMesgPos$EN = WILL_FIRE_RL_rx_data && (gmac$rx_get[9:8] == 2'd0 || gmac$rx_get[9:8] == 2'd1) && - NOT_rxHdr_sV_56_BIT_112_57_74_AND_rxHdr_sV_56__ETC___d680 || + NOT_rxHdr_sV_52_BIT_112_53_33_AND_rxHdr_sV_52__ETC___d639 || WILL_FIRE_RL_rx_dcp ; // register rxDCPPLI @@ -2128,7 +2133,7 @@ module mkGbeWorker(CLK_gmii_rx_clk, assign rxDCPPLI$EN = WILL_FIRE_RL_rx_data && (gmac$rx_get[9:8] == 2'd0 || gmac$rx_get[9:8] == 2'd1) && - NOT_rxHdr_sV_56_BIT_112_57_74_AND_rxHdr_sV_56__ETC___d680 && + NOT_rxHdr_sV_52_BIT_112_53_33_AND_rxHdr_sV_52__ETC___d639 && rxDCPMesgPos == 5'd1 || WILL_FIRE_RL_rx_dcp ; @@ -2148,7 +2153,7 @@ module mkGbeWorker(CLK_gmii_rx_clk, 4'd0 ; assign rxHdr_mCnt$EN = WILL_FIRE_RL_rx_data && - gmac_rx_get_68_BITS_9_TO_8_69_EQ_0_70_OR_gmac__ETC___d662 || + gmac_rx_get_64_BITS_9_TO_8_65_EQ_0_66_OR_gmac__ETC___d621 || WILL_FIRE_RL_tx_dcp && !rxHdr_sV[112] && rxHdr_sV[15:0] == 16'hF040 && txDCPPos == 5'd13 ; @@ -2195,11 +2200,11 @@ module mkGbeWorker(CLK_gmii_rx_clk, rxLenCount < 32'd16 ; // register rxLenCount - assign rxLenCount$D_IN = (gmac$rx_get[9:8] == 2'd0) ? x__h71721 : 32'd0 ; + assign rxLenCount$D_IN = (gmac$rx_get[9:8] == 2'd0) ? x__h71643 : 32'd0 ; assign rxLenCount$EN = WILL_FIRE_RL_rx_data ; // register rxLenLast - assign rxLenLast$D_IN = x__h71721 ; + assign rxLenLast$D_IN = x__h71643 ; assign rxLenLast$EN = WILL_FIRE_RL_rx_data && gmac$rx_get[9:8] != 2'd0 ; // register rxOvfCount @@ -2249,8 +2254,8 @@ module mkGbeWorker(CLK_gmii_rx_clk, // register txDCPPos assign txDCPPos$D_IN = (!rxHdr_sV[112] && rxHdr_sV[15:0] == 16'hF040) ? - ((txDCPPos == 5'd13) ? 5'd0 : txDCPPos_16_PLUS_1___d1251) : - CASE_dcpRespFD_OUT_BITS_44_TO_43_IF_txDCPPos__ETC__q11 ; + ((txDCPPos == 5'd13) ? 5'd0 : txDCPPos_37_PLUS_1___d833) : + CASE_dcpRespFD_OUT_BITS_44_TO_43_0_IF_txDCPPo_ETC__q13 ; assign txDCPPos$EN = WILL_FIRE_RL_tx_dcp ; // register txUndCount @@ -2317,24 +2322,24 @@ module mkGbeWorker(CLK_gmii_rx_clk, (wci_wslv_wciReq$wget[71:69] != 3'd0) != wci_wslv_reqF_r_deq$whas ; - // register wci_wslv_respF_c_r - assign wci_wslv_respF_c_r$D_IN = - WILL_FIRE_RL_wci_wslv_respF_incCtr ? - MUX_wci_wslv_respF_c_r$write_1__VAL_1 : - MUX_wci_wslv_respF_c_r$write_1__VAL_2 ; - assign wci_wslv_respF_c_r$EN = - WILL_FIRE_RL_wci_wslv_respF_incCtr || - WILL_FIRE_RL_wci_wslv_respF_decCtr ; + // register wci_wslv_respF_cntr_r + assign wci_wslv_respF_cntr_r$D_IN = + WILL_FIRE_RL_wci_wslv_respF_decCtr ? + wci_wslv_respF_cntr_r_8_MINUS_1___d27 : + MUX_wci_wslv_respF_cntr_r$write_1__VAL_2 ; + assign wci_wslv_respF_cntr_r$EN = + WILL_FIRE_RL_wci_wslv_respF_decCtr || + WILL_FIRE_RL_wci_wslv_respF_incCtr ; // register wci_wslv_respF_q_0 - always@(WILL_FIRE_RL_wci_wslv_respF_both or + always@(MUX_wci_wslv_respF_q_0$write_1__SEL_1 or MUX_wci_wslv_respF_q_0$write_1__VAL_1 or MUX_wci_wslv_respF_q_0$write_1__SEL_2 or MUX_wci_wslv_respF_q_0$write_1__VAL_2 or WILL_FIRE_RL_wci_wslv_respF_decCtr or wci_wslv_respF_q_1) begin case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_wci_wslv_respF_both: + MUX_wci_wslv_respF_q_0$write_1__SEL_1: wci_wslv_respF_q_0$D_IN = MUX_wci_wslv_respF_q_0$write_1__VAL_1; MUX_wci_wslv_respF_q_0$write_1__SEL_2: wci_wslv_respF_q_0$D_IN = MUX_wci_wslv_respF_q_0$write_1__VAL_2; @@ -2345,20 +2350,20 @@ module mkGbeWorker(CLK_gmii_rx_clk, endcase end assign wci_wslv_respF_q_0$EN = - WILL_FIRE_RL_wci_wslv_respF_both || + WILL_FIRE_RL_wci_wslv_respF_both && _dfoo3 || WILL_FIRE_RL_wci_wslv_respF_incCtr && - wci_wslv_respF_c_r == 2'd0 || + wci_wslv_respF_cntr_r == 2'd0 || WILL_FIRE_RL_wci_wslv_respF_decCtr ; // register wci_wslv_respF_q_1 - always@(WILL_FIRE_RL_wci_wslv_respF_both or + always@(MUX_wci_wslv_respF_q_1$write_1__SEL_1 or MUX_wci_wslv_respF_q_1$write_1__VAL_1 or MUX_wci_wslv_respF_q_1$write_1__SEL_2 or MUX_wci_wslv_respF_q_0$write_1__VAL_2 or WILL_FIRE_RL_wci_wslv_respF_decCtr) begin case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_wci_wslv_respF_both: + MUX_wci_wslv_respF_q_1$write_1__SEL_1: wci_wslv_respF_q_1$D_IN = MUX_wci_wslv_respF_q_1$write_1__VAL_1; MUX_wci_wslv_respF_q_1$write_1__SEL_2: wci_wslv_respF_q_1$D_IN = MUX_wci_wslv_respF_q_0$write_1__VAL_2; @@ -2369,9 +2374,9 @@ module mkGbeWorker(CLK_gmii_rx_clk, endcase end assign wci_wslv_respF_q_1$EN = - WILL_FIRE_RL_wci_wslv_respF_both || + WILL_FIRE_RL_wci_wslv_respF_both && _dfoo1 || WILL_FIRE_RL_wci_wslv_respF_incCtr && - wci_wslv_respF_c_r == 2'd1 || + wci_wslv_respF_cntr_r == 2'd1 || WILL_FIRE_RL_wci_wslv_respF_decCtr ; // register wci_wslv_sFlagReg @@ -2426,9 +2431,9 @@ module mkGbeWorker(CLK_gmii_rx_clk, assign wsiM_peerIsReady$D_IN = wsiM0_SReset_n ; assign wsiM_peerIsReady$EN = 1'd1 ; - // register wsiM_reqFifo_c_r - assign wsiM_reqFifo_c_r$D_IN = MUX_wsiM_reqFifo_c_r$write_1__VAL_2 ; - assign wsiM_reqFifo_c_r$EN = WILL_FIRE_RL_wsiM_reqFifo_deq ; + // register wsiM_reqFifo_cntr_r + assign wsiM_reqFifo_cntr_r$D_IN = MUX_wsiM_reqFifo_cntr_r$write_1__VAL_1 ; + assign wsiM_reqFifo_cntr_r$EN = WILL_FIRE_RL_wsiM_reqFifo_deq ; // register wsiM_reqFifo_q_0 assign wsiM_reqFifo_q_0$D_IN = wsiM_reqFifo_q_1 ; @@ -2566,14 +2571,14 @@ module mkGbeWorker(CLK_gmii_rx_clk, // submodule dcpRespF assign dcpRespF$D_IN = - { CASE_dcp_dcpRespFD_OUT_BITS_44_TO_43_2_0_dcp__ETC__q5, + { CASE_dcp_dcpRespFD_OUT_BITS_44_TO_43_0_dcp_dc_ETC__q7, dcp_dcpRespF$D_OUT[42:0] } ; assign dcpRespF$ENQ = dcp_dcpRespF$EMPTY_N && dcpRespF$FULL_N && wci_wslv_cState == 3'd2 ; assign dcpRespF$DEQ = WILL_FIRE_RL_tx_dcp && - rxHdr_sV_56_BIT_112_57_OR_NOT_rxHdr_sV_56_BITS_ETC___d952 ; + rxHdr_sV_52_BIT_112_53_OR_NOT_rxHdr_sV_52_BITS_ETC___d847 ; assign dcpRespF$CLR = 1'b0 ; // submodule dcp_cpReqF @@ -2590,7 +2595,7 @@ module mkGbeWorker(CLK_gmii_rx_clk, assign dcp_cpReqF$ENQ = WILL_FIRE_RL_dcp_dcp_request && dcp_dcpReqF$D_OUT[78:77] != 2'd0 && - dcp_dcpReqF_first__42_BITS_78_TO_77_43_EQ_1_46_ETC___d519 ; + dcp_dcpReqF_first__38_BITS_78_TO_77_39_EQ_1_42_ETC___d515 ; assign dcp_cpReqF$DEQ = EN_cpClient_request_get ; assign dcp_cpReqF$CLR = 1'b0 ; @@ -2601,34 +2606,34 @@ module mkGbeWorker(CLK_gmii_rx_clk, assign dcp_cpRespF$CLR = 1'b0 ; // submodule dcp_dcpReqF - always@(IF_rxDCPMesgPos_75_EQ_5_16_THEN_rxDCPMesg_82_B_ETC___d1200 or - tag__h71936 or rxDCPMesg) + always@(SEL_ARR_rxDCPMesg_41_BITS_7_TO_0_75_rxDCPMesg__ETC___d691 or + tag__h71856 or rxDCPMesg) begin - case (IF_rxDCPMesgPos_75_EQ_5_16_THEN_rxDCPMesg_82_B_ETC___d1200[5:4]) + case (SEL_ARR_rxDCPMesg_41_BITS_7_TO_0_75_rxDCPMesg__ETC___d691[5:4]) 2'd0: - dcp_dcpReqF$D_IN = { 39'h1555555554, tag__h71936, rxDCPMesg[31:0] }; + dcp_dcpReqF$D_IN = { 39'h1555555554, tag__h71856, rxDCPMesg[31:0] }; 2'd1: dcp_dcpReqF$D_IN = - { IF_rxDCPMesgPos_75_EQ_5_16_THEN_rxDCPMesg_82_B_ETC___d1200[5:4], + { SEL_ARR_rxDCPMesg_41_BITS_7_TO_0_75_rxDCPMesg__ETC___d691[5:4], 1'h0, - IF_rxDCPMesgPos_75_EQ_5_16_THEN_rxDCPMesg_82_B_ETC___d1200[3:0], - tag__h71936, + SEL_ARR_rxDCPMesg_41_BITS_7_TO_0_75_rxDCPMesg__ETC___d691[3:0], + tag__h71856, rxDCPMesg[31:0], rxDCPMesg[63:32] }; default: dcp_dcpReqF$D_IN = { 35'h555555554, - IF_rxDCPMesgPos_75_EQ_5_16_THEN_rxDCPMesg_82_B_ETC___d1200[3:0], - tag__h71936, + SEL_ARR_rxDCPMesg_41_BITS_7_TO_0_75_rxDCPMesg__ETC___d691[3:0], + tag__h71856, rxDCPMesg[31:0] }; endcase end assign dcp_dcpReqF$ENQ = WILL_FIRE_RL_rx_dcp && - (IF_rxDCPMesgPos_75_EQ_5_16_THEN_rxDCPMesg_82_B_ETC___d1200[5:4] == + (SEL_ARR_rxDCPMesg_41_BITS_7_TO_0_75_rxDCPMesg__ETC___d691[5:4] == 2'd0 || - IF_rxDCPMesgPos_75_EQ_5_16_THEN_rxDCPMesg_82_B_ETC___d1200[5:4] == + SEL_ARR_rxDCPMesg_41_BITS_7_TO_0_75_rxDCPMesg__ETC___d691[5:4] == 2'd1 || - IF_rxDCPMesgPos_75_EQ_5_16_THEN_rxDCPMesg_82_B_ETC___d1200[5:4] == + SEL_ARR_rxDCPMesg_41_BITS_7_TO_0_75_rxDCPMesg__ETC___d691[5:4] == 2'd2) ; assign dcp_dcpReqF$DEQ = WILL_FIRE_RL_dcp_dcp_request ; assign dcp_dcpReqF$CLR = 1'b0 ; @@ -2640,7 +2645,7 @@ module mkGbeWorker(CLK_gmii_rx_clk, MUX_dcp_dcpRespF$enq_1__VAL_2 ; assign dcp_dcpRespF$ENQ = WILL_FIRE_RL_dcp_dcp_request && - dcp_dcpReqF_first__42_BITS_78_TO_77_43_EQ_0_44_ETC___d478 || + dcp_dcpReqF_first__38_BITS_78_TO_77_39_EQ_0_40_ETC___d474 || WILL_FIRE_RL_dcp_cp_response ; assign dcp_dcpRespF$DEQ = dcp_dcpRespF$EMPTY_N && dcpRespF$FULL_N && @@ -2657,12 +2662,12 @@ module mkGbeWorker(CLK_gmii_rx_clk, assign gmac$tx_put = (!rxHdr_sV[112] && rxHdr_sV[15:0] == 16'hF040) ? { 2'd0, - CASE_13_MINUS_txDCPPos_rxHdr_sV_BITS_63_TO_56__ETC__q6 } : - CASE_dcpRespFD_OUT_BITS_44_TO_43_IF_txDCPPos__ETC__q9 ; + SEL_ARR_rxHdr_sV_52_BITS_7_TO_0_86_rxHdr_sV_52_ETC___d800 } : + CASE_dcpRespFD_OUT_BITS_44_TO_43_0_CASE_txDCP_ETC__q11 ; assign gmac$EN_rx_get = WILL_FIRE_RL_rx_data ; assign gmac$EN_tx_put = WILL_FIRE_RL_tx_dcp && - NOT_rxHdr_sV_56_BIT_112_57_74_AND_rxHdr_sV_56__ETC___d869 ; + NOT_rxHdr_sV_52_BIT_112_53_33_AND_rxHdr_sV_52__ETC___d790 ; assign gmac$EN_rxOperate = wci_wslv_cState == 3'd2 && phyResetWaitCnt == 22'd0 ; assign gmac$EN_txOperate = @@ -2680,7 +2685,7 @@ module mkGbeWorker(CLK_gmii_rx_clk, assign mdi_fRequest$CLR = 1'b0 ; // submodule mdi_fResponse - assign mdi_fResponse$D_IN = { 1'd1, x_data__h28646 } ; + assign mdi_fResponse$D_IN = { 1'd1, x_data__h28682 } ; assign mdi_fResponse$ENQ = WILL_FIRE_RL_mdi_run_frame && mdi_rPlayIndex$Q_OUT == 8'd0 && !mdi_rWrite ; @@ -2745,35 +2750,37 @@ module mkGbeWorker(CLK_gmii_rx_clk, assign wsiS_reqFifo$CLR = 1'b0 ; // remaining internal signals - assign IF_dcp_dcpReqF_first__42_BITS_78_TO_77_43_EQ_0_ETC___d475 = + assign IF_NOT_rxHdr_sV_52_BIT_112_53_33_AND_rxHdr_sV__ETC___d767 = + (!rxHdr_sV[112] && rxHdr_sV[15:0] == 16'hF040) ? + gmac$RDY_tx_put : + dcpRespF$EMPTY_N && + CASE_dcpRespFD_OUT_BITS_44_TO_43_0_IF_txDCPPo_ETC__q4 ; + assign IF_dcp_dcpReqF_first__38_BITS_78_TO_77_39_EQ_0_ETC___d471 = (dcp_dcpReqF$D_OUT[78:77] == 2'd0) ? dcp_dcpRespF$FULL_N : (dcp_dcpReqF$D_OUT[78:77] == 2'd1 || - !dcp_dcpReqF_first__42_BITS_39_TO_32_47_EQ_IF_d_ETC___d1172 || + !dcp_dcpReqF_first__38_BITS_39_TO_32_43_EQ_IF_d_ETC___d448 || !dcp_lastTag[8] || dcp_dcpReqF$D_OUT[44] || dcp_dcpRespF$FULL_N) && - IF_dcp_dcpReqF_first__42_BITS_78_TO_77_43_EQ_1_ETC___d473 ; - assign IF_dcp_dcpReqF_first__42_BITS_78_TO_77_43_EQ_1_ETC___d473 = + IF_dcp_dcpReqF_first__38_BITS_78_TO_77_39_EQ_1_ETC___d469 ; + assign IF_dcp_dcpReqF_first__38_BITS_78_TO_77_39_EQ_1_ETC___d469 = (dcp_dcpReqF$D_OUT[78:77] == 2'd1) ? dcp_dcpRespF$FULL_N && - (dcp_dcpReqF_first__42_BITS_71_TO_64_60_EQ_IF_d_ETC___d1171 && + (dcp_dcpReqF_first__38_BITS_71_TO_64_56_EQ_IF_d_ETC___d457 && dcp_lastTag[8] && !dcp_dcpReqF$D_OUT[76] || dcp_cpReqF$FULL_N) : - dcp_dcpReqF_first__42_BITS_39_TO_32_47_EQ_IF_d_ETC___d1172 && + dcp_dcpReqF_first__38_BITS_39_TO_32_43_EQ_IF_d_ETC___d448 && dcp_lastTag[8] && !dcp_dcpReqF$D_OUT[44] || dcp_cpReqF$FULL_N ; - assign IF_rxHdr_pos_74_EQ_0_90_THEN_rxHdr_sV_56_BITS__ETC___d659 = - CASE_rxHdr_pos_rxHdr_sV_BITS_111_TO_104_0_rxHd_ETC__q1 == - CASE_rxHdr_pos_rxHdr_pV_BITS_111_TO_104_0_rxHd_ETC__q2 ; - assign IF_txDCPPos_16_EQ_9_34_THEN_0_ELSE_txDCPPos_16_ETC___d1336 = - (txDCPPos == 5'd9) ? 5'd0 : txDCPPos_16_PLUS_1___d1251 ; - assign NOT_rxHdr_sV_56_BIT_112_57_74_AND_rxHdr_sV_56__ETC___d680 = + assign IF_txDCPPos_37_EQ_9_55_THEN_0_ELSE_txDCPPos_37_ETC___d835 = + (txDCPPos == 5'd9) ? 5'd0 : txDCPPos_37_PLUS_1___d833 ; + assign NOT_rxHdr_sV_52_BIT_112_53_33_AND_rxHdr_sV_52__ETC___d639 = !rxHdr_sV[112] && rxHdr_sV[15:0] == 16'hF040 && { 3'd0, rxDCPMesgPos } < rxDCPPLI ; - assign NOT_rxHdr_sV_56_BIT_112_57_74_AND_rxHdr_sV_56__ETC___d869 = + assign NOT_rxHdr_sV_52_BIT_112_53_33_AND_rxHdr_sV_52__ETC___d790 = !rxHdr_sV[112] && rxHdr_sV[15:0] == 16'hF040 || dcpRespF$D_OUT[44:43] == 2'd0 && (txDCPPos == 5'd0 || txDCPPos == 5'd1 || txDCPPos == 5'd2 || @@ -2799,158 +2806,169 @@ module mkGbeWorker(CLK_gmii_rx_clk, txDCPPos == 5'd7 || txDCPPos == 5'd8 || txDCPPos == 5'd9)) ; - assign _1434766110945527031733894725304609466537681244_ETC__q10 = + assign SEL_ARR_rxHdr_sV_52_BITS_7_TO_0_86_rxHdr_sV_52_ETC___d618 = + CASE_rxHdr_pos_0_rxHdr_sV_BITS_7_TO_0_1_rxHdr__ETC__q1 == + CASE_rxHdr_pos_0_rxHdr_pV_BITS_7_TO_0_1_rxHdr__ETC__q2 ; + assign _1434766110945527031733894725304609466537681244_ETC__q12 = 195'h2492492492492492492492492492492492492492492492492 ; - assign _643371375338640__q12 = + assign _643371375338640__q14 = 195'h0000000000000000000000000000000000002492492492490 ; - assign bs__h12923 = + assign _dfoo1 = + wci_wslv_respF_cntr_r != 2'd2 || + wci_wslv_respF_cntr_r_8_MINUS_1___d27 == 2'd1 ; + assign _dfoo3 = + wci_wslv_respF_cntr_r != 2'd1 || + wci_wslv_respF_cntr_r_8_MINUS_1___d27 == 2'd0 ; + assign bs__h12646 = { mdi_rWrite ? 108'hFFFFFFFFFFFFFFFFFFFFFFFF1C7 : 108'hFFFFFFFFFFFFFFFFFFFFFFFF1F8, - pa4__h12522, - pa3__h12523, - pa2__h12524, - pa1__h12525, - pa0__h12526, - ra4__h12528, - ra3__h12529, - ra2__h12530, - ra1__h12531, - ra0__h12532, + pa4__h12245, + pa3__h12246, + pa2__h12247, + pa1__h12248, + pa0__h12249, + ra4__h12251, + ra3__h12252, + ra2__h12253, + ra1__h12254, + ra0__h12255, 6'd56, - d15__h12534, - d14__h12535, - d13__h12536, - d12__h12537, - d11__h12538, - d10__h12539, - d9__h12540, - d8__h12541, - d7__h12542, - d6__h12543, - d5__h12544, - d4__h12545, - d3__h12546, - d2__h12547, - d1__h12548, - d0__h12549, + d15__h12257, + d14__h12258, + d13__h12259, + d12__h12260, + d11__h12261, + d10__h12262, + d9__h12263, + d8__h12264, + d7__h12265, + d6__h12266, + d5__h12267, + d4__h12268, + d3__h12269, + d2__h12270, + d1__h12271, + d0__h12272, 3'b111 } ; - assign bs__h25448 = + assign bs__h25405 = mdi_rWrite ? 195'h7FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF8 : 195'h7FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE00000000000000 ; - assign d0__h12549 = {3{mdi_rWriteData[0]}} ; - assign d10__h12539 = {3{mdi_rWriteData[10]}} ; - assign d11__h12538 = {3{mdi_rWriteData[11]}} ; - assign d12__h12537 = {3{mdi_rWriteData[12]}} ; - assign d13__h12536 = {3{mdi_rWriteData[13]}} ; - assign d14__h12535 = {3{mdi_rWriteData[14]}} ; - assign d15__h12534 = {3{mdi_rWriteData[15]}} ; - assign d1__h12548 = {3{mdi_rWriteData[1]}} ; - assign d2__h12547 = {3{mdi_rWriteData[2]}} ; - assign d3__h12546 = {3{mdi_rWriteData[3]}} ; - assign d4__h12545 = {3{mdi_rWriteData[4]}} ; - assign d5__h12544 = {3{mdi_rWriteData[5]}} ; - assign d6__h12543 = {3{mdi_rWriteData[6]}} ; - assign d7__h12542 = {3{mdi_rWriteData[7]}} ; - assign d8__h12541 = {3{mdi_rWriteData[8]}} ; - assign d9__h12540 = {3{mdi_rWriteData[9]}} ; - assign dcpRespF_i_notEmpty__12_AND_IF_dcpRespF_first__ETC___d845 = - dcpRespF$EMPTY_N && - CASE_dcpRespFD_OUT_BITS_44_TO_43_IF_txDCPPos__ETC__q3 ; - assign dcp_dcpReqF_first__42_BITS_39_TO_32_47_EQ_IF_d_ETC___d1172 = + assign d0__h12272 = {3{mdi_rWriteData[0]}} ; + assign d10__h12262 = {3{mdi_rWriteData[10]}} ; + assign d11__h12261 = {3{mdi_rWriteData[11]}} ; + assign d12__h12260 = {3{mdi_rWriteData[12]}} ; + assign d13__h12259 = {3{mdi_rWriteData[13]}} ; + assign d14__h12258 = {3{mdi_rWriteData[14]}} ; + assign d15__h12257 = {3{mdi_rWriteData[15]}} ; + assign d1__h12271 = {3{mdi_rWriteData[1]}} ; + assign d2__h12270 = {3{mdi_rWriteData[2]}} ; + assign d3__h12269 = {3{mdi_rWriteData[3]}} ; + assign d4__h12268 = {3{mdi_rWriteData[4]}} ; + assign d5__h12267 = {3{mdi_rWriteData[5]}} ; + assign d6__h12266 = {3{mdi_rWriteData[6]}} ; + assign d7__h12265 = {3{mdi_rWriteData[7]}} ; + assign d8__h12264 = {3{mdi_rWriteData[8]}} ; + assign d9__h12263 = {3{mdi_rWriteData[9]}} ; + assign dcp_dcpReqF_first__38_BITS_39_TO_32_43_EQ_IF_d_ETC___d448 = dcp_dcpReqF$D_OUT[39:32] == dcp_lastTag[7:0] ; - assign dcp_dcpReqF_first__42_BITS_71_TO_64_60_EQ_IF_d_ETC___d1171 = + assign dcp_dcpReqF_first__38_BITS_71_TO_64_56_EQ_IF_d_ETC___d457 = dcp_dcpReqF$D_OUT[71:64] == dcp_lastTag[7:0] ; - assign dcp_dcpReqF_first__42_BITS_78_TO_77_43_EQ_0_44_ETC___d478 = + assign dcp_dcpReqF_first__38_BITS_78_TO_77_39_EQ_0_40_ETC___d474 = dcp_dcpReqF$D_OUT[78:77] == 2'd0 || dcp_dcpReqF$D_OUT[78:77] == 2'd1 || - dcp_dcpReqF_first__42_BITS_39_TO_32_47_EQ_IF_d_ETC___d1172 && + dcp_dcpReqF_first__38_BITS_39_TO_32_43_EQ_IF_d_ETC___d448 && dcp_lastTag[8] && !dcp_dcpReqF$D_OUT[44] ; - assign dcp_dcpReqF_first__42_BITS_78_TO_77_43_EQ_1_46_ETC___d519 = + assign dcp_dcpReqF_first__38_BITS_78_TO_77_39_EQ_1_42_ETC___d515 = dcp_dcpReqF$D_OUT[78:77] == 2'd1 && - (!dcp_dcpReqF_first__42_BITS_71_TO_64_60_EQ_IF_d_ETC___d1171 || + (!dcp_dcpReqF_first__38_BITS_71_TO_64_56_EQ_IF_d_ETC___d457 || !dcp_lastTag[8] || dcp_dcpReqF$D_OUT[76]) || dcp_dcpReqF$D_OUT[78:77] != 2'd1 && - (!dcp_dcpReqF_first__42_BITS_39_TO_32_47_EQ_IF_d_ETC___d1172 || + (!dcp_dcpReqF_first__38_BITS_39_TO_32_43_EQ_IF_d_ETC___d448 || !dcp_lastTag[8] || dcp_dcpReqF$D_OUT[44]) ; - assign gmac_rx_get_68_BITS_9_TO_8_69_EQ_0_70_OR_gmac__ETC___d662 = + assign gmac_rx_get_64_BITS_9_TO_8_65_EQ_0_66_OR_gmac__ETC___d621 = (gmac$rx_get[9:8] == 2'd0 || gmac$rx_get[9:8] == 2'd1) && rxHdr_sV[112] && !rxHdr_pV[112] && - IF_rxHdr_pos_74_EQ_0_90_THEN_rxHdr_sV_56_BITS__ETC___d659 ; - assign pa0__h12526 = {3{mdi_rPhyAddr[0]}} ; - assign pa1__h12525 = {3{mdi_rPhyAddr[1]}} ; - assign pa2__h12524 = {3{mdi_rPhyAddr[2]}} ; - assign pa3__h12523 = {3{mdi_rPhyAddr[3]}} ; - assign pa4__h12522 = {3{mdi_rPhyAddr[4]}} ; - assign ra0__h12532 = {3{mdi_rRegAddr[0]}} ; - assign ra1__h12531 = {3{mdi_rRegAddr[1]}} ; - assign ra2__h12530 = {3{mdi_rRegAddr[2]}} ; - assign ra3__h12529 = {3{mdi_rRegAddr[3]}} ; - assign ra4__h12528 = {3{mdi_rRegAddr[4]}} ; - assign rdat___1__h81993 = hasDebugLogic ? { 16'd0, x__h81997 } : 32'd0 ; - assign rdat___1__h82044 = + SEL_ARR_rxHdr_sV_52_BITS_7_TO_0_86_rxHdr_sV_52_ETC___d618 ; + assign pa0__h12249 = {3{mdi_rPhyAddr[0]}} ; + assign pa1__h12248 = {3{mdi_rPhyAddr[1]}} ; + assign pa2__h12247 = {3{mdi_rPhyAddr[2]}} ; + assign pa3__h12246 = {3{mdi_rPhyAddr[3]}} ; + assign pa4__h12245 = {3{mdi_rPhyAddr[4]}} ; + assign ra0__h12255 = {3{mdi_rRegAddr[0]}} ; + assign ra1__h12254 = {3{mdi_rRegAddr[1]}} ; + assign ra2__h12253 = {3{mdi_rRegAddr[2]}} ; + assign ra3__h12252 = {3{mdi_rRegAddr[3]}} ; + assign ra4__h12251 = {3{mdi_rRegAddr[4]}} ; + assign rdat___1__h81245 = hasDebugLogic ? { 16'd0, x__h81249 } : 32'd0 ; + assign rdat___1__h81296 = hasDebugLogic ? wsiS_extStatusW$wget[95:64] : 32'd0 ; - assign rdat___1__h82085 = + assign rdat___1__h81337 = hasDebugLogic ? wsiS_extStatusW$wget[63:32] : 32'd0 ; - assign rdat___1__h82120 = + assign rdat___1__h81372 = hasDebugLogic ? wsiS_extStatusW$wget[31:0] : 32'd0 ; - assign rdat___1__h82153 = + assign rdat___1__h81405 = hasDebugLogic ? wsiM_extStatusW$wget[95:64] : 32'd0 ; - assign rdat___1__h82194 = + assign rdat___1__h81446 = hasDebugLogic ? wsiM_extStatusW$wget[63:32] : 32'd0 ; - assign rdat___1__h82229 = hasDebugLogic ? txDBGCnt : 32'd0 ; - assign rdat___1__h82263 = hasDebugLogic ? rxCount : 32'd0 ; - assign rdat___1__h82296 = hasDebugLogic ? txCount : 32'd0 ; - assign rdat___1__h82330 = hasDebugLogic ? rxOvfCount : 32'd0 ; - assign rdat___1__h82363 = hasDebugLogic ? txUndCount : 32'd0 ; - assign rdat___1__h82396 = hasDebugLogic ? rxValidNoEOPC : 32'd0 ; - assign rdat___1__h82429 = hasDebugLogic ? rxValidEOPC : 32'd0 ; - assign rdat___1__h82462 = hasDebugLogic ? rxEmptyEOPC : 32'd0 ; - assign rdat___1__h82495 = hasDebugLogic ? rxAbortEOPC : 32'd0 ; - assign rdat___1__h82528 = hasDebugLogic ? rxDCPCnt : 32'd0 ; - assign rdat___1__h82562 = hasDebugLogic ? rxHdrMatchCnt : 32'd0 ; - assign rdat___1__h82595 = hasDebugLogic ? rxLenLast : 32'd0 ; - assign rdat___1__h82629 = hasDebugLogic ? txDCPCnt : 32'd0 ; - assign rdat___1__h82663 = hasDebugLogic ? { 28'd0, rxHdr_pos } : 32'd0 ; - assign rdat___1__h82700 = hasDebugLogic ? { 28'd0, rxHdr_mCnt } : 32'd0 ; - assign rdat___1__h82737 = + assign rdat___1__h81481 = hasDebugLogic ? txDBGCnt : 32'd0 ; + assign rdat___1__h81515 = hasDebugLogic ? rxCount : 32'd0 ; + assign rdat___1__h81548 = hasDebugLogic ? txCount : 32'd0 ; + assign rdat___1__h81582 = hasDebugLogic ? rxOvfCount : 32'd0 ; + assign rdat___1__h81615 = hasDebugLogic ? txUndCount : 32'd0 ; + assign rdat___1__h81648 = hasDebugLogic ? rxValidNoEOPC : 32'd0 ; + assign rdat___1__h81681 = hasDebugLogic ? rxValidEOPC : 32'd0 ; + assign rdat___1__h81714 = hasDebugLogic ? rxEmptyEOPC : 32'd0 ; + assign rdat___1__h81747 = hasDebugLogic ? rxAbortEOPC : 32'd0 ; + assign rdat___1__h81780 = hasDebugLogic ? rxDCPCnt : 32'd0 ; + assign rdat___1__h81814 = hasDebugLogic ? rxHdrMatchCnt : 32'd0 ; + assign rdat___1__h81847 = hasDebugLogic ? rxLenLast : 32'd0 ; + assign rdat___1__h81881 = hasDebugLogic ? txDCPCnt : 32'd0 ; + assign rdat___1__h81915 = hasDebugLogic ? { 28'd0, rxHdr_pos } : 32'd0 ; + assign rdat___1__h81952 = hasDebugLogic ? { 28'd0, rxHdr_mCnt } : 32'd0 ; + assign rdat___1__h81989 = hasDebugLogic ? { 16'd0, rxHdr_sV[111:96] } : 32'd0 ; - assign rdat___1__h85238 = hasDebugLogic ? rxHdr_sV[95:64] : 32'd0 ; - assign rdat___1__h87736 = + assign rdat___1__h84530 = hasDebugLogic ? rxHdr_sV[95:64] : 32'd0 ; + assign rdat___1__h87068 = hasDebugLogic ? { 16'd0, rxHdr_sV[63:48] } : 32'd0 ; - assign rdat___1__h90237 = hasDebugLogic ? rxHdr_sV[47:16] : 32'd0 ; - assign rdat___1__h92735 = + assign rdat___1__h89609 = hasDebugLogic ? rxHdr_sV[47:16] : 32'd0 ; + assign rdat___1__h92147 = hasDebugLogic ? { 16'd0, rxHdr_sV[15:0] } : 32'd0 ; - assign rdat___1__h95236 = hasDebugLogic ? rxHeadCap[127:96] : 32'd0 ; - assign rdat___1__h96843 = hasDebugLogic ? rxHeadCap[95:64] : 32'd0 ; - assign rdat___1__h98413 = hasDebugLogic ? rxHeadCap[63:32] : 32'd0 ; - assign rdat___1__h99983 = hasDebugLogic ? rxHeadCap[31:0] : 32'd0 ; - assign rdat__h81758 = + assign rdat___1__h94688 = hasDebugLogic ? rxHeadCap[127:96] : 32'd0 ; + assign rdat___1__h96311 = hasDebugLogic ? rxHeadCap[95:64] : 32'd0 ; + assign rdat___1__h97897 = hasDebugLogic ? rxHeadCap[63:32] : 32'd0 ; + assign rdat___1__h99483 = hasDebugLogic ? rxHeadCap[31:0] : 32'd0 ; + assign rdat__h81010 = wci_wslv_reqF$D_OUT[39] ? 32'd0 : - IF_wci_wslv_reqF_first__5_BITS_39_TO_32_57_EQ__ETC___d1110 ; - assign rxHdr_sV_56_BIT_112_57_OR_NOT_rxHdr_sV_56_BITS_ETC___d952 = + IF_wci_wslv_reqF_first__3_BITS_39_TO_32_52_EQ__ETC___d1005 ; + assign rxHdr_sV_52_BIT_112_53_OR_NOT_rxHdr_sV_52_BITS_ETC___d847 = (rxHdr_sV[112] || rxHdr_sV[15:0] != 16'hF040) && (dcpRespF$D_OUT[44:43] == 2'd0 && txDCPPos == 5'd9 || dcpRespF$D_OUT[44:43] != 2'd0 && (dcpRespF$D_OUT[44:43] == 2'd1 && txDCPPos == 5'd5 || dcpRespF$D_OUT[44:43] != 2'd1 && txDCPPos == 5'd9)) ; - assign status__h81559 = { 16'd0, x__h81839 } ; - assign txDCPPos_16_PLUS_1___d1251 = txDCPPos + 5'd1 ; - assign wci_wslv_reqF_i_notEmpty__4_AND_IF_wci_wslv_re_ETC___d982 = + assign status__h80811 = { 16'd0, x__h81091 } ; + assign txDCPPos_37_PLUS_1___d833 = txDCPPos + 5'd1 ; + assign wci_wslv_reqF_i_notEmpty__2_AND_IF_wci_wslv_re_ETC___d877 = wci_wslv_reqF$EMPTY_N && (wci_wslv_reqF$D_OUT[39] ? mdi_fRequest$FULL_N : - wci_wslv_respF_c_r != 2'd2) ; - assign x__h71721 = rxLenCount + 32'd1 ; - assign x__h81839 = { wsiM_statusR, wsiS_statusR } ; - assign x__h81997 = { wsiS_statusR, wsiM_statusR } ; - assign x_data__h28646 = + wci_wslv_respF_cntr_r != 2'd2) ; + assign wci_wslv_respF_cntr_r_8_MINUS_1___d27 = + wci_wslv_respF_cntr_r - 2'd1 ; + assign x__h71643 = rxLenCount + 32'd1 ; + assign x__h71912 = rxDCPMesgPos - 5'd5 ; + assign x__h72062 = rxDCPMesgPos - 5'd6 ; + assign x__h74515 = 5'd13 - txDCPPos ; + assign x__h81091 = { wsiM_statusR, wsiS_statusR } ; + assign x__h81249 = { wsiS_statusR, wsiM_statusR } ; + assign x_data__h28682 = { mdi_vrReadData_15, mdi_vrReadData_14, mdi_vrReadData_13, @@ -2966,339 +2984,413 @@ module mkGbeWorker(CLK_gmii_rx_clk, mdi_vrReadData_3, mdi_vrReadData_2, mdi_vrReadData_1, - mdi_vrReadData } ; - always@(rxDCPMesgPos or rxDCPMesg) + mdi_vrReadData_0 } ; + always@(x__h72062 or rxDCPMesg) begin - case (rxDCPMesgPos) - 5'd6: tag__h71936 = rxDCPMesg[7:0]; - 5'd7: tag__h71936 = rxDCPMesg[15:8]; - 5'd8: tag__h71936 = rxDCPMesg[23:16]; - 5'd9: tag__h71936 = rxDCPMesg[31:24]; - 5'd10: tag__h71936 = rxDCPMesg[39:32]; - 5'd11: tag__h71936 = rxDCPMesg[47:40]; - 5'd12: tag__h71936 = rxDCPMesg[55:48]; - 5'd13: tag__h71936 = rxDCPMesg[63:56]; - 5'd14: tag__h71936 = rxDCPMesg[71:64]; - 5'd15: tag__h71936 = rxDCPMesg[79:72]; - 5'd16: tag__h71936 = rxDCPMesg[87:80]; - 5'd17: tag__h71936 = rxDCPMesg[95:88]; - 5'd18: tag__h71936 = rxDCPMesg[103:96]; - default: tag__h71936 = rxDCPMesg[111:104]; + case (x__h72062) + 5'd0: tag__h71856 = rxDCPMesg[7:0]; + 5'd1: tag__h71856 = rxDCPMesg[15:8]; + 5'd2: tag__h71856 = rxDCPMesg[23:16]; + 5'd3: tag__h71856 = rxDCPMesg[31:24]; + 5'd4: tag__h71856 = rxDCPMesg[39:32]; + 5'd5: tag__h71856 = rxDCPMesg[47:40]; + 5'd6: tag__h71856 = rxDCPMesg[55:48]; + 5'd7: tag__h71856 = rxDCPMesg[63:56]; + 5'd8: tag__h71856 = rxDCPMesg[71:64]; + 5'd9: tag__h71856 = rxDCPMesg[79:72]; + 5'd10: tag__h71856 = rxDCPMesg[87:80]; + 5'd11: tag__h71856 = rxDCPMesg[95:88]; + 5'd12: tag__h71856 = rxDCPMesg[103:96]; + 5'd13: tag__h71856 = rxDCPMesg[111:104]; + default: tag__h71856 = 8'b10101010 /* unspecified value */ ; endcase end always@(rxHdr_pos or rxHdr_sV) begin case (rxHdr_pos) 4'd0: - CASE_rxHdr_pos_rxHdr_sV_BITS_111_TO_104_0_rxHd_ETC__q1 = + CASE_rxHdr_pos_0_rxHdr_sV_BITS_7_TO_0_1_rxHdr__ETC__q1 = rxHdr_sV[7:0]; 4'd1: - CASE_rxHdr_pos_rxHdr_sV_BITS_111_TO_104_0_rxHd_ETC__q1 = + CASE_rxHdr_pos_0_rxHdr_sV_BITS_7_TO_0_1_rxHdr__ETC__q1 = rxHdr_sV[15:8]; 4'd2: - CASE_rxHdr_pos_rxHdr_sV_BITS_111_TO_104_0_rxHd_ETC__q1 = + CASE_rxHdr_pos_0_rxHdr_sV_BITS_7_TO_0_1_rxHdr__ETC__q1 = rxHdr_sV[23:16]; 4'd3: - CASE_rxHdr_pos_rxHdr_sV_BITS_111_TO_104_0_rxHd_ETC__q1 = + CASE_rxHdr_pos_0_rxHdr_sV_BITS_7_TO_0_1_rxHdr__ETC__q1 = rxHdr_sV[31:24]; 4'd4: - CASE_rxHdr_pos_rxHdr_sV_BITS_111_TO_104_0_rxHd_ETC__q1 = + CASE_rxHdr_pos_0_rxHdr_sV_BITS_7_TO_0_1_rxHdr__ETC__q1 = rxHdr_sV[39:32]; 4'd5: - CASE_rxHdr_pos_rxHdr_sV_BITS_111_TO_104_0_rxHd_ETC__q1 = + CASE_rxHdr_pos_0_rxHdr_sV_BITS_7_TO_0_1_rxHdr__ETC__q1 = rxHdr_sV[47:40]; 4'd6: - CASE_rxHdr_pos_rxHdr_sV_BITS_111_TO_104_0_rxHd_ETC__q1 = + CASE_rxHdr_pos_0_rxHdr_sV_BITS_7_TO_0_1_rxHdr__ETC__q1 = rxHdr_sV[55:48]; 4'd7: - CASE_rxHdr_pos_rxHdr_sV_BITS_111_TO_104_0_rxHd_ETC__q1 = + CASE_rxHdr_pos_0_rxHdr_sV_BITS_7_TO_0_1_rxHdr__ETC__q1 = rxHdr_sV[63:56]; 4'd8: - CASE_rxHdr_pos_rxHdr_sV_BITS_111_TO_104_0_rxHd_ETC__q1 = + CASE_rxHdr_pos_0_rxHdr_sV_BITS_7_TO_0_1_rxHdr__ETC__q1 = rxHdr_sV[71:64]; 4'd9: - CASE_rxHdr_pos_rxHdr_sV_BITS_111_TO_104_0_rxHd_ETC__q1 = + CASE_rxHdr_pos_0_rxHdr_sV_BITS_7_TO_0_1_rxHdr__ETC__q1 = rxHdr_sV[79:72]; 4'd10: - CASE_rxHdr_pos_rxHdr_sV_BITS_111_TO_104_0_rxHd_ETC__q1 = + CASE_rxHdr_pos_0_rxHdr_sV_BITS_7_TO_0_1_rxHdr__ETC__q1 = rxHdr_sV[87:80]; 4'd11: - CASE_rxHdr_pos_rxHdr_sV_BITS_111_TO_104_0_rxHd_ETC__q1 = + CASE_rxHdr_pos_0_rxHdr_sV_BITS_7_TO_0_1_rxHdr__ETC__q1 = rxHdr_sV[95:88]; 4'd12: - CASE_rxHdr_pos_rxHdr_sV_BITS_111_TO_104_0_rxHd_ETC__q1 = + CASE_rxHdr_pos_0_rxHdr_sV_BITS_7_TO_0_1_rxHdr__ETC__q1 = rxHdr_sV[103:96]; - default: CASE_rxHdr_pos_rxHdr_sV_BITS_111_TO_104_0_rxHd_ETC__q1 = - rxHdr_sV[111:104]; + 4'd13: + CASE_rxHdr_pos_0_rxHdr_sV_BITS_7_TO_0_1_rxHdr__ETC__q1 = + rxHdr_sV[111:104]; + default: CASE_rxHdr_pos_0_rxHdr_sV_BITS_7_TO_0_1_rxHdr__ETC__q1 = + 8'b10101010 /* unspecified value */ ; endcase end always@(rxHdr_pos or rxHdr_pV) begin case (rxHdr_pos) 4'd0: - CASE_rxHdr_pos_rxHdr_pV_BITS_111_TO_104_0_rxHd_ETC__q2 = + CASE_rxHdr_pos_0_rxHdr_pV_BITS_7_TO_0_1_rxHdr__ETC__q2 = rxHdr_pV[7:0]; 4'd1: - CASE_rxHdr_pos_rxHdr_pV_BITS_111_TO_104_0_rxHd_ETC__q2 = + CASE_rxHdr_pos_0_rxHdr_pV_BITS_7_TO_0_1_rxHdr__ETC__q2 = rxHdr_pV[15:8]; 4'd2: - CASE_rxHdr_pos_rxHdr_pV_BITS_111_TO_104_0_rxHd_ETC__q2 = + CASE_rxHdr_pos_0_rxHdr_pV_BITS_7_TO_0_1_rxHdr__ETC__q2 = rxHdr_pV[23:16]; 4'd3: - CASE_rxHdr_pos_rxHdr_pV_BITS_111_TO_104_0_rxHd_ETC__q2 = + CASE_rxHdr_pos_0_rxHdr_pV_BITS_7_TO_0_1_rxHdr__ETC__q2 = rxHdr_pV[31:24]; 4'd4: - CASE_rxHdr_pos_rxHdr_pV_BITS_111_TO_104_0_rxHd_ETC__q2 = + CASE_rxHdr_pos_0_rxHdr_pV_BITS_7_TO_0_1_rxHdr__ETC__q2 = rxHdr_pV[39:32]; 4'd5: - CASE_rxHdr_pos_rxHdr_pV_BITS_111_TO_104_0_rxHd_ETC__q2 = + CASE_rxHdr_pos_0_rxHdr_pV_BITS_7_TO_0_1_rxHdr__ETC__q2 = rxHdr_pV[47:40]; 4'd6: - CASE_rxHdr_pos_rxHdr_pV_BITS_111_TO_104_0_rxHd_ETC__q2 = + CASE_rxHdr_pos_0_rxHdr_pV_BITS_7_TO_0_1_rxHdr__ETC__q2 = rxHdr_pV[55:48]; 4'd7: - CASE_rxHdr_pos_rxHdr_pV_BITS_111_TO_104_0_rxHd_ETC__q2 = + CASE_rxHdr_pos_0_rxHdr_pV_BITS_7_TO_0_1_rxHdr__ETC__q2 = rxHdr_pV[63:56]; 4'd8: - CASE_rxHdr_pos_rxHdr_pV_BITS_111_TO_104_0_rxHd_ETC__q2 = + CASE_rxHdr_pos_0_rxHdr_pV_BITS_7_TO_0_1_rxHdr__ETC__q2 = rxHdr_pV[71:64]; 4'd9: - CASE_rxHdr_pos_rxHdr_pV_BITS_111_TO_104_0_rxHd_ETC__q2 = + CASE_rxHdr_pos_0_rxHdr_pV_BITS_7_TO_0_1_rxHdr__ETC__q2 = rxHdr_pV[79:72]; 4'd10: - CASE_rxHdr_pos_rxHdr_pV_BITS_111_TO_104_0_rxHd_ETC__q2 = + CASE_rxHdr_pos_0_rxHdr_pV_BITS_7_TO_0_1_rxHdr__ETC__q2 = rxHdr_pV[87:80]; 4'd11: - CASE_rxHdr_pos_rxHdr_pV_BITS_111_TO_104_0_rxHd_ETC__q2 = + CASE_rxHdr_pos_0_rxHdr_pV_BITS_7_TO_0_1_rxHdr__ETC__q2 = rxHdr_pV[95:88]; 4'd12: - CASE_rxHdr_pos_rxHdr_pV_BITS_111_TO_104_0_rxHd_ETC__q2 = + CASE_rxHdr_pos_0_rxHdr_pV_BITS_7_TO_0_1_rxHdr__ETC__q2 = rxHdr_pV[103:96]; - default: CASE_rxHdr_pos_rxHdr_pV_BITS_111_TO_104_0_rxHd_ETC__q2 = - rxHdr_pV[111:104]; + 4'd13: + CASE_rxHdr_pos_0_rxHdr_pV_BITS_7_TO_0_1_rxHdr__ETC__q2 = + rxHdr_pV[111:104]; + default: CASE_rxHdr_pos_0_rxHdr_pV_BITS_7_TO_0_1_rxHdr__ETC__q2 = + 8'b10101010 /* unspecified value */ ; + endcase + end + always@(x__h71912 or rxDCPMesg) + begin + case (x__h71912) + 5'd0: + SEL_ARR_rxDCPMesg_41_BITS_7_TO_0_75_rxDCPMesg__ETC___d691 = + rxDCPMesg[7:0]; + 5'd1: + SEL_ARR_rxDCPMesg_41_BITS_7_TO_0_75_rxDCPMesg__ETC___d691 = + rxDCPMesg[15:8]; + 5'd2: + SEL_ARR_rxDCPMesg_41_BITS_7_TO_0_75_rxDCPMesg__ETC___d691 = + rxDCPMesg[23:16]; + 5'd3: + SEL_ARR_rxDCPMesg_41_BITS_7_TO_0_75_rxDCPMesg__ETC___d691 = + rxDCPMesg[31:24]; + 5'd4: + SEL_ARR_rxDCPMesg_41_BITS_7_TO_0_75_rxDCPMesg__ETC___d691 = + rxDCPMesg[39:32]; + 5'd5: + SEL_ARR_rxDCPMesg_41_BITS_7_TO_0_75_rxDCPMesg__ETC___d691 = + rxDCPMesg[47:40]; + 5'd6: + SEL_ARR_rxDCPMesg_41_BITS_7_TO_0_75_rxDCPMesg__ETC___d691 = + rxDCPMesg[55:48]; + 5'd7: + SEL_ARR_rxDCPMesg_41_BITS_7_TO_0_75_rxDCPMesg__ETC___d691 = + rxDCPMesg[63:56]; + 5'd8: + SEL_ARR_rxDCPMesg_41_BITS_7_TO_0_75_rxDCPMesg__ETC___d691 = + rxDCPMesg[71:64]; + 5'd9: + SEL_ARR_rxDCPMesg_41_BITS_7_TO_0_75_rxDCPMesg__ETC___d691 = + rxDCPMesg[79:72]; + 5'd10: + SEL_ARR_rxDCPMesg_41_BITS_7_TO_0_75_rxDCPMesg__ETC___d691 = + rxDCPMesg[87:80]; + 5'd11: + SEL_ARR_rxDCPMesg_41_BITS_7_TO_0_75_rxDCPMesg__ETC___d691 = + rxDCPMesg[95:88]; + 5'd12: + SEL_ARR_rxDCPMesg_41_BITS_7_TO_0_75_rxDCPMesg__ETC___d691 = + rxDCPMesg[103:96]; + 5'd13: + SEL_ARR_rxDCPMesg_41_BITS_7_TO_0_75_rxDCPMesg__ETC___d691 = + rxDCPMesg[111:104]; + default: SEL_ARR_rxDCPMesg_41_BITS_7_TO_0_75_rxDCPMesg__ETC___d691 = + 8'b10101010 /* unspecified value */ ; endcase end always@(txDCPPos or gmac$RDY_tx_put or dcpRespF$EMPTY_N) begin case (txDCPPos) 5'd0, 5'd1, 5'd2, 5'd3, 5'd4: - IF_txDCPPos_16_EQ_0_17_OR_txDCPPos_16_EQ_1_18__ETC___d1324 = + IF_txDCPPos_37_EQ_0_38_OR_txDCPPos_37_EQ_1_39__ETC___d759 = gmac$RDY_tx_put; 5'd5, 5'd6, 5'd7, 5'd8: - IF_txDCPPos_16_EQ_0_17_OR_txDCPPos_16_EQ_1_18__ETC___d1324 = + IF_txDCPPos_37_EQ_0_38_OR_txDCPPos_37_EQ_1_39__ETC___d759 = gmac$RDY_tx_put && dcpRespF$EMPTY_N; - default: IF_txDCPPos_16_EQ_0_17_OR_txDCPPos_16_EQ_1_18__ETC___d1324 = + default: IF_txDCPPos_37_EQ_0_38_OR_txDCPPos_37_EQ_1_39__ETC___d759 = txDCPPos != 5'd9 || gmac$RDY_tx_put && dcpRespF$EMPTY_N; endcase end + always@(txDCPPos or gmac$RDY_tx_put) + begin + case (txDCPPos) + 5'd0, 5'd1, 5'd2, 5'd3, 5'd4: + CASE_txDCPPos_0_gmacRDY_tx_put_1_gmacRDY_tx__ETC__q3 = + gmac$RDY_tx_put; + default: CASE_txDCPPos_0_gmacRDY_tx_put_1_gmacRDY_tx__ETC__q3 = + txDCPPos != 5'd5 || gmac$RDY_tx_put; + endcase + end always@(dcpRespF$D_OUT or - IF_txDCPPos_16_EQ_0_17_OR_txDCPPos_16_EQ_1_18__ETC___d1324 or - txDCPPos or gmac$RDY_tx_put) + IF_txDCPPos_37_EQ_0_38_OR_txDCPPos_37_EQ_1_39__ETC___d759 or + CASE_txDCPPos_0_gmacRDY_tx_put_1_gmacRDY_tx__ETC__q3) begin case (dcpRespF$D_OUT[44:43]) 2'd0: - CASE_dcpRespFD_OUT_BITS_44_TO_43_IF_txDCPPos__ETC__q3 = - IF_txDCPPos_16_EQ_0_17_OR_txDCPPos_16_EQ_1_18__ETC___d1324; + CASE_dcpRespFD_OUT_BITS_44_TO_43_0_IF_txDCPPo_ETC__q4 = + IF_txDCPPos_37_EQ_0_38_OR_txDCPPos_37_EQ_1_39__ETC___d759; 2'd1: - CASE_dcpRespFD_OUT_BITS_44_TO_43_IF_txDCPPos__ETC__q3 = - (txDCPPos == 5'd0 || txDCPPos == 5'd1 || txDCPPos == 5'd2 || - txDCPPos == 5'd3 || - txDCPPos == 5'd4) ? - gmac$RDY_tx_put : - txDCPPos != 5'd5 || gmac$RDY_tx_put; - default: CASE_dcpRespFD_OUT_BITS_44_TO_43_IF_txDCPPos__ETC__q3 = - IF_txDCPPos_16_EQ_0_17_OR_txDCPPos_16_EQ_1_18__ETC___d1324; + CASE_dcpRespFD_OUT_BITS_44_TO_43_0_IF_txDCPPo_ETC__q4 = + CASE_txDCPPos_0_gmacRDY_tx_put_1_gmacRDY_tx__ETC__q3; + default: CASE_dcpRespFD_OUT_BITS_44_TO_43_0_IF_txDCPPo_ETC__q4 = + IF_txDCPPos_37_EQ_0_38_OR_txDCPPos_37_EQ_1_39__ETC___d759; endcase end - always@(rxDCPMesgPos or rxDCPMesg) + always@(x__h74515 or rxHdr_sV or macAddress) begin - case (rxDCPMesgPos) + case (x__h74515) + 5'd0: + SEL_ARR_rxHdr_sV_52_BITS_7_TO_0_86_rxHdr_sV_52_ETC___d800 = + rxHdr_sV[7:0]; + 5'd1: + SEL_ARR_rxHdr_sV_52_BITS_7_TO_0_86_rxHdr_sV_52_ETC___d800 = + rxHdr_sV[15:8]; + 5'd2: + SEL_ARR_rxHdr_sV_52_BITS_7_TO_0_86_rxHdr_sV_52_ETC___d800 = + macAddress[7:0]; + 5'd3: + SEL_ARR_rxHdr_sV_52_BITS_7_TO_0_86_rxHdr_sV_52_ETC___d800 = + macAddress[15:8]; + 5'd4: + SEL_ARR_rxHdr_sV_52_BITS_7_TO_0_86_rxHdr_sV_52_ETC___d800 = + macAddress[23:16]; 5'd5: - IF_rxDCPMesgPos_75_EQ_5_16_THEN_rxDCPMesg_82_B_ETC___d1200 = - rxDCPMesg[7:0]; + SEL_ARR_rxHdr_sV_52_BITS_7_TO_0_86_rxHdr_sV_52_ETC___d800 = + macAddress[31:24]; 5'd6: - IF_rxDCPMesgPos_75_EQ_5_16_THEN_rxDCPMesg_82_B_ETC___d1200 = - rxDCPMesg[15:8]; + SEL_ARR_rxHdr_sV_52_BITS_7_TO_0_86_rxHdr_sV_52_ETC___d800 = + macAddress[39:32]; 5'd7: - IF_rxDCPMesgPos_75_EQ_5_16_THEN_rxDCPMesg_82_B_ETC___d1200 = - rxDCPMesg[23:16]; + SEL_ARR_rxHdr_sV_52_BITS_7_TO_0_86_rxHdr_sV_52_ETC___d800 = + macAddress[47:40]; 5'd8: - IF_rxDCPMesgPos_75_EQ_5_16_THEN_rxDCPMesg_82_B_ETC___d1200 = - rxDCPMesg[31:24]; + SEL_ARR_rxHdr_sV_52_BITS_7_TO_0_86_rxHdr_sV_52_ETC___d800 = + rxHdr_sV[23:16]; 5'd9: - IF_rxDCPMesgPos_75_EQ_5_16_THEN_rxDCPMesg_82_B_ETC___d1200 = - rxDCPMesg[39:32]; + SEL_ARR_rxHdr_sV_52_BITS_7_TO_0_86_rxHdr_sV_52_ETC___d800 = + rxHdr_sV[31:24]; 5'd10: - IF_rxDCPMesgPos_75_EQ_5_16_THEN_rxDCPMesg_82_B_ETC___d1200 = - rxDCPMesg[47:40]; + SEL_ARR_rxHdr_sV_52_BITS_7_TO_0_86_rxHdr_sV_52_ETC___d800 = + rxHdr_sV[39:32]; 5'd11: - IF_rxDCPMesgPos_75_EQ_5_16_THEN_rxDCPMesg_82_B_ETC___d1200 = - rxDCPMesg[55:48]; + SEL_ARR_rxHdr_sV_52_BITS_7_TO_0_86_rxHdr_sV_52_ETC___d800 = + rxHdr_sV[47:40]; 5'd12: - IF_rxDCPMesgPos_75_EQ_5_16_THEN_rxDCPMesg_82_B_ETC___d1200 = - rxDCPMesg[63:56]; + SEL_ARR_rxHdr_sV_52_BITS_7_TO_0_86_rxHdr_sV_52_ETC___d800 = + rxHdr_sV[55:48]; 5'd13: - IF_rxDCPMesgPos_75_EQ_5_16_THEN_rxDCPMesg_82_B_ETC___d1200 = - rxDCPMesg[71:64]; - 5'd14: - IF_rxDCPMesgPos_75_EQ_5_16_THEN_rxDCPMesg_82_B_ETC___d1200 = - rxDCPMesg[79:72]; - 5'd15: - IF_rxDCPMesgPos_75_EQ_5_16_THEN_rxDCPMesg_82_B_ETC___d1200 = - rxDCPMesg[87:80]; - 5'd16: - IF_rxDCPMesgPos_75_EQ_5_16_THEN_rxDCPMesg_82_B_ETC___d1200 = - rxDCPMesg[95:88]; - 5'd17: - IF_rxDCPMesgPos_75_EQ_5_16_THEN_rxDCPMesg_82_B_ETC___d1200 = - rxDCPMesg[103:96]; - default: IF_rxDCPMesgPos_75_EQ_5_16_THEN_rxDCPMesg_82_B_ETC___d1200 = - rxDCPMesg[111:104]; + SEL_ARR_rxHdr_sV_52_BITS_7_TO_0_86_rxHdr_sV_52_ETC___d800 = + rxHdr_sV[63:56]; + default: SEL_ARR_rxHdr_sV_52_BITS_7_TO_0_86_rxHdr_sV_52_ETC___d800 = + 8'b10101010 /* unspecified value */ ; endcase end - always@(IF_rxDCPMesgPos_75_EQ_5_16_THEN_rxDCPMesg_82_B_ETC___d1200 or + always@(SEL_ARR_rxDCPMesg_41_BITS_7_TO_0_75_rxDCPMesg__ETC___d691 or dcp_dcpReqF$FULL_N) begin - case (IF_rxDCPMesgPos_75_EQ_5_16_THEN_rxDCPMesg_82_B_ETC___d1200[5:4]) + case (SEL_ARR_rxDCPMesg_41_BITS_7_TO_0_75_rxDCPMesg__ETC___d691[5:4]) 2'd0, 2'd1: - CASE_IF_rxDCPMesgPos_75_EQ_5_16_THEN_rxDCPMesg_ETC__q4 = + CASE_SEL_ARR_rxDCPMesg_41_BITS_7_TO_0_75_rxDCP_ETC__q5 = dcp_dcpReqF$FULL_N; - default: CASE_IF_rxDCPMesgPos_75_EQ_5_16_THEN_rxDCPMesg_ETC__q4 = - IF_rxDCPMesgPos_75_EQ_5_16_THEN_rxDCPMesg_82_B_ETC___d1200[5:4] != + default: CASE_SEL_ARR_rxDCPMesg_41_BITS_7_TO_0_75_rxDCP_ETC__q5 = + SEL_ARR_rxDCPMesg_41_BITS_7_TO_0_75_rxDCPMesg__ETC___d691[5:4] != 2'd2 || dcp_dcpReqF$FULL_N; endcase end + always@(dcp_lastResp) + begin + case (dcp_lastResp[44:43]) + 2'd0, 2'd1: + CASE_dcp_lastResp_BITS_44_TO_43_0_dcp_lastResp_ETC__q6 = + dcp_lastResp[44:43]; + default: CASE_dcp_lastResp_BITS_44_TO_43_0_dcp_lastResp_ETC__q6 = 2'd2; + endcase + end always@(wci_wslv_reqF$D_OUT or - status__h81559 or + status__h80811 or gbeControl or - rdat___1__h81993 or - rdat___1__h82044 or - rdat___1__h82085 or - rdat___1__h82120 or - rdat___1__h82153 or - rdat___1__h82194 or - rdat___1__h82229 or - rdat___1__h82263 or - rdat___1__h82296 or - rdat___1__h82330 or - rdat___1__h82363 or - rdat___1__h82396 or - rdat___1__h82429 or - rdat___1__h82462 or - rdat___1__h82495 or - rdat___1__h82528 or - rdat___1__h82562 or - rdat___1__h82595 or - rdat___1__h82629 or - rdat___1__h82663 or - rdat___1__h82700 or - rdat___1__h82737 or - rdat___1__h85238 or - rdat___1__h87736 or - rdat___1__h90237 or - rdat___1__h92735 or - rdat___1__h95236 or - rdat___1__h96843 or rdat___1__h98413 or rdat___1__h99983) + rdat___1__h81245 or + rdat___1__h81296 or + rdat___1__h81337 or + rdat___1__h81372 or + rdat___1__h81405 or + rdat___1__h81446 or + rdat___1__h81481 or + rdat___1__h81515 or + rdat___1__h81548 or + rdat___1__h81582 or + rdat___1__h81615 or + rdat___1__h81648 or + rdat___1__h81681 or + rdat___1__h81714 or + rdat___1__h81747 or + rdat___1__h81780 or + rdat___1__h81814 or + rdat___1__h81847 or + rdat___1__h81881 or + rdat___1__h81915 or + rdat___1__h81952 or + rdat___1__h81989 or + rdat___1__h84530 or + rdat___1__h87068 or + rdat___1__h89609 or + rdat___1__h92147 or + rdat___1__h94688 or + rdat___1__h96311 or rdat___1__h97897 or rdat___1__h99483) begin case (wci_wslv_reqF$D_OUT[39:32]) 8'h0: - IF_wci_wslv_reqF_first__5_BITS_39_TO_32_57_EQ__ETC___d1110 = - status__h81559; + IF_wci_wslv_reqF_first__3_BITS_39_TO_32_52_EQ__ETC___d1005 = + status__h80811; 8'h04: - IF_wci_wslv_reqF_first__5_BITS_39_TO_32_57_EQ__ETC___d1110 = + IF_wci_wslv_reqF_first__3_BITS_39_TO_32_52_EQ__ETC___d1005 = gbeControl; 8'h08: - IF_wci_wslv_reqF_first__5_BITS_39_TO_32_57_EQ__ETC___d1110 = - rdat___1__h81993; + IF_wci_wslv_reqF_first__3_BITS_39_TO_32_52_EQ__ETC___d1005 = + rdat___1__h81245; 8'h0C: - IF_wci_wslv_reqF_first__5_BITS_39_TO_32_57_EQ__ETC___d1110 = - rdat___1__h82044; + IF_wci_wslv_reqF_first__3_BITS_39_TO_32_52_EQ__ETC___d1005 = + rdat___1__h81296; 8'h10: - IF_wci_wslv_reqF_first__5_BITS_39_TO_32_57_EQ__ETC___d1110 = - rdat___1__h82085; + IF_wci_wslv_reqF_first__3_BITS_39_TO_32_52_EQ__ETC___d1005 = + rdat___1__h81337; 8'h14: - IF_wci_wslv_reqF_first__5_BITS_39_TO_32_57_EQ__ETC___d1110 = - rdat___1__h82120; + IF_wci_wslv_reqF_first__3_BITS_39_TO_32_52_EQ__ETC___d1005 = + rdat___1__h81372; 8'h18: - IF_wci_wslv_reqF_first__5_BITS_39_TO_32_57_EQ__ETC___d1110 = - rdat___1__h82153; + IF_wci_wslv_reqF_first__3_BITS_39_TO_32_52_EQ__ETC___d1005 = + rdat___1__h81405; 8'h1C: - IF_wci_wslv_reqF_first__5_BITS_39_TO_32_57_EQ__ETC___d1110 = - rdat___1__h82194; + IF_wci_wslv_reqF_first__3_BITS_39_TO_32_52_EQ__ETC___d1005 = + rdat___1__h81446; 8'h20: - IF_wci_wslv_reqF_first__5_BITS_39_TO_32_57_EQ__ETC___d1110 = - rdat___1__h82229; + IF_wci_wslv_reqF_first__3_BITS_39_TO_32_52_EQ__ETC___d1005 = + rdat___1__h81481; 8'h24: - IF_wci_wslv_reqF_first__5_BITS_39_TO_32_57_EQ__ETC___d1110 = - rdat___1__h82263; + IF_wci_wslv_reqF_first__3_BITS_39_TO_32_52_EQ__ETC___d1005 = + rdat___1__h81515; 8'h28: - IF_wci_wslv_reqF_first__5_BITS_39_TO_32_57_EQ__ETC___d1110 = - rdat___1__h82296; + IF_wci_wslv_reqF_first__3_BITS_39_TO_32_52_EQ__ETC___d1005 = + rdat___1__h81548; 8'h2C: - IF_wci_wslv_reqF_first__5_BITS_39_TO_32_57_EQ__ETC___d1110 = - rdat___1__h82330; + IF_wci_wslv_reqF_first__3_BITS_39_TO_32_52_EQ__ETC___d1005 = + rdat___1__h81582; 8'h30: - IF_wci_wslv_reqF_first__5_BITS_39_TO_32_57_EQ__ETC___d1110 = - rdat___1__h82363; + IF_wci_wslv_reqF_first__3_BITS_39_TO_32_52_EQ__ETC___d1005 = + rdat___1__h81615; 8'h34: - IF_wci_wslv_reqF_first__5_BITS_39_TO_32_57_EQ__ETC___d1110 = - rdat___1__h82396; + IF_wci_wslv_reqF_first__3_BITS_39_TO_32_52_EQ__ETC___d1005 = + rdat___1__h81648; 8'h38: - IF_wci_wslv_reqF_first__5_BITS_39_TO_32_57_EQ__ETC___d1110 = - rdat___1__h82429; + IF_wci_wslv_reqF_first__3_BITS_39_TO_32_52_EQ__ETC___d1005 = + rdat___1__h81681; 8'h3C: - IF_wci_wslv_reqF_first__5_BITS_39_TO_32_57_EQ__ETC___d1110 = - rdat___1__h82462; + IF_wci_wslv_reqF_first__3_BITS_39_TO_32_52_EQ__ETC___d1005 = + rdat___1__h81714; 8'h40: - IF_wci_wslv_reqF_first__5_BITS_39_TO_32_57_EQ__ETC___d1110 = - rdat___1__h82495; + IF_wci_wslv_reqF_first__3_BITS_39_TO_32_52_EQ__ETC___d1005 = + rdat___1__h81747; 8'h44: - IF_wci_wslv_reqF_first__5_BITS_39_TO_32_57_EQ__ETC___d1110 = - rdat___1__h82528; + IF_wci_wslv_reqF_first__3_BITS_39_TO_32_52_EQ__ETC___d1005 = + rdat___1__h81780; 8'h48: - IF_wci_wslv_reqF_first__5_BITS_39_TO_32_57_EQ__ETC___d1110 = - rdat___1__h82562; + IF_wci_wslv_reqF_first__3_BITS_39_TO_32_52_EQ__ETC___d1005 = + rdat___1__h81814; 8'h4C: - IF_wci_wslv_reqF_first__5_BITS_39_TO_32_57_EQ__ETC___d1110 = - rdat___1__h82595; + IF_wci_wslv_reqF_first__3_BITS_39_TO_32_52_EQ__ETC___d1005 = + rdat___1__h81847; 8'h50: - IF_wci_wslv_reqF_first__5_BITS_39_TO_32_57_EQ__ETC___d1110 = - rdat___1__h82629; + IF_wci_wslv_reqF_first__3_BITS_39_TO_32_52_EQ__ETC___d1005 = + rdat___1__h81881; 8'h54: - IF_wci_wslv_reqF_first__5_BITS_39_TO_32_57_EQ__ETC___d1110 = - rdat___1__h82663; + IF_wci_wslv_reqF_first__3_BITS_39_TO_32_52_EQ__ETC___d1005 = + rdat___1__h81915; 8'h58: - IF_wci_wslv_reqF_first__5_BITS_39_TO_32_57_EQ__ETC___d1110 = - rdat___1__h82700; + IF_wci_wslv_reqF_first__3_BITS_39_TO_32_52_EQ__ETC___d1005 = + rdat___1__h81952; 8'h5C: - IF_wci_wslv_reqF_first__5_BITS_39_TO_32_57_EQ__ETC___d1110 = - rdat___1__h82737; + IF_wci_wslv_reqF_first__3_BITS_39_TO_32_52_EQ__ETC___d1005 = + rdat___1__h81989; 8'h60: - IF_wci_wslv_reqF_first__5_BITS_39_TO_32_57_EQ__ETC___d1110 = - rdat___1__h85238; + IF_wci_wslv_reqF_first__3_BITS_39_TO_32_52_EQ__ETC___d1005 = + rdat___1__h84530; 8'h64: - IF_wci_wslv_reqF_first__5_BITS_39_TO_32_57_EQ__ETC___d1110 = - rdat___1__h87736; + IF_wci_wslv_reqF_first__3_BITS_39_TO_32_52_EQ__ETC___d1005 = + rdat___1__h87068; 8'h68: - IF_wci_wslv_reqF_first__5_BITS_39_TO_32_57_EQ__ETC___d1110 = - rdat___1__h90237; + IF_wci_wslv_reqF_first__3_BITS_39_TO_32_52_EQ__ETC___d1005 = + rdat___1__h89609; 8'h6C: - IF_wci_wslv_reqF_first__5_BITS_39_TO_32_57_EQ__ETC___d1110 = - rdat___1__h92735; + IF_wci_wslv_reqF_first__3_BITS_39_TO_32_52_EQ__ETC___d1005 = + rdat___1__h92147; 8'h70: - IF_wci_wslv_reqF_first__5_BITS_39_TO_32_57_EQ__ETC___d1110 = - rdat___1__h95236; + IF_wci_wslv_reqF_first__3_BITS_39_TO_32_52_EQ__ETC___d1005 = + rdat___1__h94688; 8'h74: - IF_wci_wslv_reqF_first__5_BITS_39_TO_32_57_EQ__ETC___d1110 = - rdat___1__h96843; + IF_wci_wslv_reqF_first__3_BITS_39_TO_32_52_EQ__ETC___d1005 = + rdat___1__h96311; 8'h78: - IF_wci_wslv_reqF_first__5_BITS_39_TO_32_57_EQ__ETC___d1110 = - rdat___1__h98413; + IF_wci_wslv_reqF_first__3_BITS_39_TO_32_52_EQ__ETC___d1005 = + rdat___1__h97897; 8'h7C: - IF_wci_wslv_reqF_first__5_BITS_39_TO_32_57_EQ__ETC___d1110 = - rdat___1__h99983; - default: IF_wci_wslv_reqF_first__5_BITS_39_TO_32_57_EQ__ETC___d1110 = + IF_wci_wslv_reqF_first__3_BITS_39_TO_32_52_EQ__ETC___d1005 = + rdat___1__h99483; + default: IF_wci_wslv_reqF_first__3_BITS_39_TO_32_52_EQ__ETC___d1005 = 32'd0; endcase end @@ -3306,73 +3398,31 @@ module mkGbeWorker(CLK_gmii_rx_clk, begin case (dcp_dcpRespF$D_OUT[44:43]) 2'd0, 2'd1: - CASE_dcp_dcpRespFD_OUT_BITS_44_TO_43_2_0_dcp__ETC__q5 = + CASE_dcp_dcpRespFD_OUT_BITS_44_TO_43_0_dcp_dc_ETC__q7 = dcp_dcpRespF$D_OUT[44:43]; - default: CASE_dcp_dcpRespFD_OUT_BITS_44_TO_43_2_0_dcp__ETC__q5 = 2'd2; - endcase - end - always@(txDCPPos or rxHdr_sV or macAddress) - begin - case (5'd13 - txDCPPos) - 5'd0: - CASE_13_MINUS_txDCPPos_rxHdr_sV_BITS_63_TO_56__ETC__q6 = - rxHdr_sV[7:0]; - 5'd1: - CASE_13_MINUS_txDCPPos_rxHdr_sV_BITS_63_TO_56__ETC__q6 = - rxHdr_sV[15:8]; - 5'd2: - CASE_13_MINUS_txDCPPos_rxHdr_sV_BITS_63_TO_56__ETC__q6 = - macAddress[7:0]; - 5'd3: - CASE_13_MINUS_txDCPPos_rxHdr_sV_BITS_63_TO_56__ETC__q6 = - macAddress[15:8]; - 5'd4: - CASE_13_MINUS_txDCPPos_rxHdr_sV_BITS_63_TO_56__ETC__q6 = - macAddress[23:16]; - 5'd5: - CASE_13_MINUS_txDCPPos_rxHdr_sV_BITS_63_TO_56__ETC__q6 = - macAddress[31:24]; - 5'd6: - CASE_13_MINUS_txDCPPos_rxHdr_sV_BITS_63_TO_56__ETC__q6 = - macAddress[39:32]; - 5'd7: - CASE_13_MINUS_txDCPPos_rxHdr_sV_BITS_63_TO_56__ETC__q6 = - macAddress[47:40]; - 5'd8: - CASE_13_MINUS_txDCPPos_rxHdr_sV_BITS_63_TO_56__ETC__q6 = - rxHdr_sV[23:16]; - 5'd9: - CASE_13_MINUS_txDCPPos_rxHdr_sV_BITS_63_TO_56__ETC__q6 = - rxHdr_sV[31:24]; - 5'd10: - CASE_13_MINUS_txDCPPos_rxHdr_sV_BITS_63_TO_56__ETC__q6 = - rxHdr_sV[39:32]; - 5'd11: - CASE_13_MINUS_txDCPPos_rxHdr_sV_BITS_63_TO_56__ETC__q6 = - rxHdr_sV[47:40]; - 5'd12: - CASE_13_MINUS_txDCPPos_rxHdr_sV_BITS_63_TO_56__ETC__q6 = - rxHdr_sV[55:48]; - default: CASE_13_MINUS_txDCPPos_rxHdr_sV_BITS_63_TO_56__ETC__q6 = - rxHdr_sV[63:56]; + default: CASE_dcp_dcpRespFD_OUT_BITS_44_TO_43_0_dcp_dc_ETC__q7 = 2'd2; endcase end always@(txDCPPos or dcpRespF$D_OUT) begin case (txDCPPos) + 5'd0, 5'd2, 5'd3: + CASE_txDCPPos_0_0_1_10_2_0_3_0_4_51_5_0_CONCAT_ETC__q8 = 10'd0; + 5'd1: CASE_txDCPPos_0_0_1_10_2_0_3_0_4_51_5_0_CONCAT_ETC__q8 = 10'd10; + 5'd4: CASE_txDCPPos_0_0_1_10_2_0_3_0_4_51_5_0_CONCAT_ETC__q8 = 10'd51; 5'd5: - CASE_txDCPPos_1_CONCAT_dcpRespFD_OUT_BITS_17__ETC__q7 = + CASE_txDCPPos_0_0_1_10_2_0_3_0_4_51_5_0_CONCAT_ETC__q8 = { 2'd0, dcpRespF$D_OUT[9:2] }; 5'd6: - CASE_txDCPPos_1_CONCAT_dcpRespFD_OUT_BITS_17__ETC__q7 = + CASE_txDCPPos_0_0_1_10_2_0_3_0_4_51_5_0_CONCAT_ETC__q8 = { 2'd0, dcpRespF$D_OUT[41:34] }; 5'd7: - CASE_txDCPPos_1_CONCAT_dcpRespFD_OUT_BITS_17__ETC__q7 = + CASE_txDCPPos_0_0_1_10_2_0_3_0_4_51_5_0_CONCAT_ETC__q8 = { 2'd0, dcpRespF$D_OUT[33:26] }; 5'd8: - CASE_txDCPPos_1_CONCAT_dcpRespFD_OUT_BITS_17__ETC__q7 = + CASE_txDCPPos_0_0_1_10_2_0_3_0_4_51_5_0_CONCAT_ETC__q8 = { 2'd0, dcpRespF$D_OUT[25:18] }; - default: CASE_txDCPPos_1_CONCAT_dcpRespFD_OUT_BITS_17__ETC__q7 = + default: CASE_txDCPPos_0_0_1_10_2_0_3_0_4_51_5_0_CONCAT_ETC__q8 = { 2'd1, dcpRespF$D_OUT[17:10] }; endcase end @@ -3380,70 +3430,65 @@ module mkGbeWorker(CLK_gmii_rx_clk, begin case (txDCPPos) 5'd0, 5'd2, 5'd3: - CASE_txDCPPos_1_CONCAT_dcpRespFD_OUT_BITS_17__ETC__q8 = 10'd0; - 5'd1: CASE_txDCPPos_1_CONCAT_dcpRespFD_OUT_BITS_17__ETC__q8 = 10'd10; - 5'd4: CASE_txDCPPos_1_CONCAT_dcpRespFD_OUT_BITS_17__ETC__q8 = 10'd49; + CASE_txDCPPos_0_0_1_10_2_0_3_0_4_49_5_0_CONCAT_ETC__q9 = 10'd0; + 5'd1: CASE_txDCPPos_0_0_1_10_2_0_3_0_4_49_5_0_CONCAT_ETC__q9 = 10'd10; + 5'd4: CASE_txDCPPos_0_0_1_10_2_0_3_0_4_49_5_0_CONCAT_ETC__q9 = 10'd49; 5'd5: - CASE_txDCPPos_1_CONCAT_dcpRespFD_OUT_BITS_17__ETC__q8 = + CASE_txDCPPos_0_0_1_10_2_0_3_0_4_49_5_0_CONCAT_ETC__q9 = { 2'd0, dcpRespF$D_OUT[9:2] }; 5'd6: - CASE_txDCPPos_1_CONCAT_dcpRespFD_OUT_BITS_17__ETC__q8 = + CASE_txDCPPos_0_0_1_10_2_0_3_0_4_49_5_0_CONCAT_ETC__q9 = { 2'd0, dcpRespF$D_OUT[41:34] }; 5'd7: - CASE_txDCPPos_1_CONCAT_dcpRespFD_OUT_BITS_17__ETC__q8 = + CASE_txDCPPos_0_0_1_10_2_0_3_0_4_49_5_0_CONCAT_ETC__q9 = { 2'd0, dcpRespF$D_OUT[33:26] }; 5'd8: - CASE_txDCPPos_1_CONCAT_dcpRespFD_OUT_BITS_17__ETC__q8 = + CASE_txDCPPos_0_0_1_10_2_0_3_0_4_49_5_0_CONCAT_ETC__q9 = { 2'd0, dcpRespF$D_OUT[25:18] }; - default: CASE_txDCPPos_1_CONCAT_dcpRespFD_OUT_BITS_17__ETC__q8 = + default: CASE_txDCPPos_0_0_1_10_2_0_3_0_4_49_5_0_CONCAT_ETC__q9 = { 2'd1, dcpRespF$D_OUT[17:10] }; endcase end + always@(txDCPPos or dcpRespF$D_OUT) + begin + case (txDCPPos) + 5'd0, 5'd2, 5'd3: + CASE_txDCPPos_0_0_1_6_2_0_3_0_4_50_1_CONCAT_dc_ETC__q10 = 10'd0; + 5'd1: CASE_txDCPPos_0_0_1_6_2_0_3_0_4_50_1_CONCAT_dc_ETC__q10 = 10'd6; + 5'd4: CASE_txDCPPos_0_0_1_6_2_0_3_0_4_50_1_CONCAT_dc_ETC__q10 = 10'd50; + default: CASE_txDCPPos_0_0_1_6_2_0_3_0_4_50_1_CONCAT_dc_ETC__q10 = + { 2'd1, dcpRespF$D_OUT[9:2] }; + endcase + end always@(dcpRespF$D_OUT or - txDCPPos or - CASE_txDCPPos_1_CONCAT_dcpRespFD_OUT_BITS_17__ETC__q7 or - CASE_txDCPPos_1_CONCAT_dcpRespFD_OUT_BITS_17__ETC__q8) + CASE_txDCPPos_0_0_1_10_2_0_3_0_4_51_5_0_CONCAT_ETC__q8 or + CASE_txDCPPos_0_0_1_10_2_0_3_0_4_49_5_0_CONCAT_ETC__q9 or + CASE_txDCPPos_0_0_1_6_2_0_3_0_4_50_1_CONCAT_dc_ETC__q10) begin case (dcpRespF$D_OUT[44:43]) 2'd0: - CASE_dcpRespFD_OUT_BITS_44_TO_43_IF_txDCPPos__ETC__q9 = - CASE_txDCPPos_1_CONCAT_dcpRespFD_OUT_BITS_17__ETC__q8; + CASE_dcpRespFD_OUT_BITS_44_TO_43_0_CASE_txDCP_ETC__q11 = + CASE_txDCPPos_0_0_1_10_2_0_3_0_4_49_5_0_CONCAT_ETC__q9; 2'd1: - CASE_dcpRespFD_OUT_BITS_44_TO_43_IF_txDCPPos__ETC__q9 = - (txDCPPos == 5'd0) ? - 10'd0 : - ((txDCPPos == 5'd1) ? - 10'd6 : - ((txDCPPos == 5'd2 || txDCPPos == 5'd3) ? - 10'd0 : - ((txDCPPos == 5'd4) ? - 10'd50 : - { 2'd1, dcpRespF$D_OUT[9:2] }))); - default: CASE_dcpRespFD_OUT_BITS_44_TO_43_IF_txDCPPos__ETC__q9 = - (txDCPPos == 5'd0) ? - 10'd0 : - ((txDCPPos == 5'd1) ? - 10'd10 : - ((txDCPPos == 5'd2 || txDCPPos == 5'd3) ? - 10'd0 : - ((txDCPPos == 5'd4) ? - 10'd51 : - CASE_txDCPPos_1_CONCAT_dcpRespFD_OUT_BITS_17__ETC__q7))); + CASE_dcpRespFD_OUT_BITS_44_TO_43_0_CASE_txDCP_ETC__q11 = + CASE_txDCPPos_0_0_1_6_2_0_3_0_4_50_1_CONCAT_dc_ETC__q10; + default: CASE_dcpRespFD_OUT_BITS_44_TO_43_0_CASE_txDCP_ETC__q11 = + CASE_txDCPPos_0_0_1_10_2_0_3_0_4_51_5_0_CONCAT_ETC__q8; endcase end always@(dcpRespF$D_OUT or - IF_txDCPPos_16_EQ_9_34_THEN_0_ELSE_txDCPPos_16_ETC___d1336 or - txDCPPos or txDCPPos_16_PLUS_1___d1251) + IF_txDCPPos_37_EQ_9_55_THEN_0_ELSE_txDCPPos_37_ETC___d835 or + txDCPPos or txDCPPos_37_PLUS_1___d833) begin case (dcpRespF$D_OUT[44:43]) 2'd0: - CASE_dcpRespFD_OUT_BITS_44_TO_43_IF_txDCPPos__ETC__q11 = - IF_txDCPPos_16_EQ_9_34_THEN_0_ELSE_txDCPPos_16_ETC___d1336; + CASE_dcpRespFD_OUT_BITS_44_TO_43_0_IF_txDCPPo_ETC__q13 = + IF_txDCPPos_37_EQ_9_55_THEN_0_ELSE_txDCPPos_37_ETC___d835; 2'd1: - CASE_dcpRespFD_OUT_BITS_44_TO_43_IF_txDCPPos__ETC__q11 = - (txDCPPos == 5'd5) ? 5'd0 : txDCPPos_16_PLUS_1___d1251; - default: CASE_dcpRespFD_OUT_BITS_44_TO_43_IF_txDCPPos__ETC__q11 = - IF_txDCPPos_16_EQ_9_34_THEN_0_ELSE_txDCPPos_16_ETC___d1336; + CASE_dcpRespFD_OUT_BITS_44_TO_43_0_IF_txDCPPo_ETC__q13 = + (txDCPPos == 5'd5) ? 5'd0 : txDCPPos_37_PLUS_1___d833; + default: CASE_dcpRespFD_OUT_BITS_44_TO_43_0_IF_txDCPPo_ETC__q13 = + IF_txDCPPos_37_EQ_9_55_THEN_0_ELSE_txDCPPos_37_ETC___d835; endcase end @@ -3494,7 +3539,7 @@ module mkGbeWorker(CLK_gmii_rx_clk, wci_wslv_illegalEdge <= `BSV_ASSIGNMENT_DELAY 1'd0; wci_wslv_nState <= `BSV_ASSIGNMENT_DELAY 3'd0; wci_wslv_reqF_countReg <= `BSV_ASSIGNMENT_DELAY 2'd0; - wci_wslv_respF_c_r <= `BSV_ASSIGNMENT_DELAY 2'd0; + wci_wslv_respF_cntr_r <= `BSV_ASSIGNMENT_DELAY 2'd0; wci_wslv_respF_q_0 <= `BSV_ASSIGNMENT_DELAY 34'h0AAAAAAAA; wci_wslv_respF_q_1 <= `BSV_ASSIGNMENT_DELAY 34'h0AAAAAAAA; wci_wslv_sFlagReg <= `BSV_ASSIGNMENT_DELAY 1'd0; @@ -3505,7 +3550,7 @@ module mkGbeWorker(CLK_gmii_rx_clk, wsiM_operateD <= `BSV_ASSIGNMENT_DELAY 1'd0; wsiM_pMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0; wsiM_peerIsReady <= `BSV_ASSIGNMENT_DELAY 1'd0; - wsiM_reqFifo_c_r <= `BSV_ASSIGNMENT_DELAY 2'd0; + wsiM_reqFifo_cntr_r <= `BSV_ASSIGNMENT_DELAY 2'd0; wsiM_reqFifo_q_0 <= `BSV_ASSIGNMENT_DELAY 61'h00000AAAAAAAAA00; wsiM_reqFifo_q_1 <= `BSV_ASSIGNMENT_DELAY 61'h00000AAAAAAAAA00; wsiM_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY 1'd1; @@ -3594,8 +3639,9 @@ module mkGbeWorker(CLK_gmii_rx_clk, if (wci_wslv_reqF_countReg$EN) wci_wslv_reqF_countReg <= `BSV_ASSIGNMENT_DELAY wci_wslv_reqF_countReg$D_IN; - if (wci_wslv_respF_c_r$EN) - wci_wslv_respF_c_r <= `BSV_ASSIGNMENT_DELAY wci_wslv_respF_c_r$D_IN; + if (wci_wslv_respF_cntr_r$EN) + wci_wslv_respF_cntr_r <= `BSV_ASSIGNMENT_DELAY + wci_wslv_respF_cntr_r$D_IN; if (wci_wslv_respF_q_0$EN) wci_wslv_respF_q_0 <= `BSV_ASSIGNMENT_DELAY wci_wslv_respF_q_0$D_IN; if (wci_wslv_respF_q_1$EN) @@ -3617,8 +3663,9 @@ module mkGbeWorker(CLK_gmii_rx_clk, wsiM_pMesgCount <= `BSV_ASSIGNMENT_DELAY wsiM_pMesgCount$D_IN; if (wsiM_peerIsReady$EN) wsiM_peerIsReady <= `BSV_ASSIGNMENT_DELAY wsiM_peerIsReady$D_IN; - if (wsiM_reqFifo_c_r$EN) - wsiM_reqFifo_c_r <= `BSV_ASSIGNMENT_DELAY wsiM_reqFifo_c_r$D_IN; + if (wsiM_reqFifo_cntr_r$EN) + wsiM_reqFifo_cntr_r <= `BSV_ASSIGNMENT_DELAY + wsiM_reqFifo_cntr_r$D_IN; if (wsiM_reqFifo_q_0$EN) wsiM_reqFifo_q_0 <= `BSV_ASSIGNMENT_DELAY wsiM_reqFifo_q_0$D_IN; if (wsiM_reqFifo_q_1$EN) @@ -3663,8 +3710,8 @@ module mkGbeWorker(CLK_gmii_rx_clk, if (mdi_rWrite$EN) mdi_rWrite <= `BSV_ASSIGNMENT_DELAY mdi_rWrite$D_IN; if (mdi_rWriteData$EN) mdi_rWriteData <= `BSV_ASSIGNMENT_DELAY mdi_rWriteData$D_IN; - if (mdi_vrReadData$EN) - mdi_vrReadData <= `BSV_ASSIGNMENT_DELAY mdi_vrReadData$D_IN; + if (mdi_vrReadData_0$EN) + mdi_vrReadData_0 <= `BSV_ASSIGNMENT_DELAY mdi_vrReadData_0$D_IN; if (mdi_vrReadData_1$EN) mdi_vrReadData_1 <= `BSV_ASSIGNMENT_DELAY mdi_vrReadData_1$D_IN; if (mdi_vrReadData_10$EN) @@ -3771,7 +3818,7 @@ module mkGbeWorker(CLK_gmii_rx_clk, mdi_rState = 1'h0; mdi_rWrite = 1'h0; mdi_rWriteData = 16'hAAAA; - mdi_vrReadData = 1'h0; + mdi_vrReadData_0 = 1'h0; mdi_vrReadData_1 = 1'h0; mdi_vrReadData_10 = 1'h0; mdi_vrReadData_11 = 1'h0; @@ -3823,7 +3870,7 @@ module mkGbeWorker(CLK_gmii_rx_clk, wci_wslv_isReset_isInReset = 1'h0; wci_wslv_nState = 3'h2; wci_wslv_reqF_countReg = 2'h2; - wci_wslv_respF_c_r = 2'h2; + wci_wslv_respF_cntr_r = 2'h2; wci_wslv_respF_q_0 = 34'h2AAAAAAAA; wci_wslv_respF_q_1 = 34'h2AAAAAAAA; wci_wslv_sFlagReg = 1'h0; @@ -3835,7 +3882,7 @@ module mkGbeWorker(CLK_gmii_rx_clk, wsiM_operateD = 1'h0; wsiM_pMesgCount = 32'hAAAAAAAA; wsiM_peerIsReady = 1'h0; - wsiM_reqFifo_c_r = 2'h2; + wsiM_reqFifo_cntr_r = 2'h2; wsiM_reqFifo_q_0 = 61'h0AAAAAAAAAAAAAAA; wsiM_reqFifo_q_1 = 61'h0AAAAAAAAAAAAAAA; wsiM_sThreadBusy_d = 1'h0; @@ -3872,37 +3919,37 @@ module mkGbeWorker(CLK_gmii_rx_clk, if (wciS0_MReset_n != `BSV_RESET_VALUE) if (MUX_wci_wslv_respF_x_wire$wset_1__SEL_3) begin - v__h101757 = $time; + v__h101273 = $time; #0; end if (wciS0_MReset_n != `BSV_RESET_VALUE) if (MUX_wci_wslv_respF_x_wire$wset_1__SEL_3) $display("[%0d]: %m: WCI SPLIT READ Data:%0x", - v__h101757, + v__h101273, mdi_fResponse$D_OUT[15:0]); if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfwr) begin - v__h81480 = $time; + v__h80732 = $time; #0; end if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfwr) $display("[%0d]: %m: WCI CONFIG WRITE Addr:%0x BE:%0x Data:%0x", - v__h81480, + v__h80732, wci_wslv_reqF$D_OUT[63:32], wci_wslv_reqF$D_OUT[67:64], wci_wslv_reqF$D_OUT[31:0]); if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_start) begin - v__h3708 = $time; + v__h3576 = $time; #0; end if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_start) $display("[%0d]: %m: WCI ControlOp: Starting-transition edge:%x from:%x", - v__h3708, + v__h3576, wci_wslv_reqF$D_OUT[36:34], wci_wslv_cState); if (wciS0_MReset_n != `BSV_RESET_VALUE) @@ -3917,16 +3964,16 @@ module mkGbeWorker(CLK_gmii_rx_clk, if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfrd) begin - v__h81774 = $time; + v__h81026 = $time; #0; end if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfrd) $display("[%0d]: %m: WCI CONFIG READ Addr:%0x BE:%0x Data:%0x", - v__h81774, + v__h81026, wci_wslv_reqF$D_OUT[63:32], wci_wslv_reqF$D_OUT[67:64], - rdat__h81758); + rdat__h81010); if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_OrE) $display("Error: \"bsv/wrk/GbeWorker.bsv\", line 338, column 26: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n"); @@ -3951,25 +3998,25 @@ module mkGbeWorker(CLK_gmii_rx_clk, if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge) begin - v__h4027 = $time; + v__h3895 = $time; #0; end if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge) $display("[%0d]: %m: WCI ControlOp: ILLEGAL-EDGE Completed-transition edge:%x from:%x", - v__h4027, + v__h3895, wci_wslv_cEdge, wci_wslv_cState); if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && !wci_wslv_illegalEdge) begin - v__h3883 = $time; + v__h3751 = $time; #0; end if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && !wci_wslv_illegalEdge) $display("[%0d]: %m: WCI ControlOp: Completed-transition edge:%x from:%x to:%x", - v__h3883, + v__h3751, wci_wslv_cEdge, wci_wslv_cState, wci_wslv_nState); diff --git a/rtl/mkICAPWorker.v b/rtl/mkICAPWorker.v index cbcd46ee..b2096df4 100644 --- a/rtl/mkICAPWorker.v +++ b/rtl/mkICAPWorker.v @@ -1,7 +1,7 @@ // -// Generated by Bluespec Compiler, version 2012.09.beta1 (build 29570, 2012-09.11) +// Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Wed Nov 28 10:32:01 EST 2012 +// On Fri Jun 21 16:57:23 EDT 2013 // // // Ports: @@ -285,10 +285,10 @@ module mkICAPWorker(wciS0_Clk, wire [1 : 0] wci_wslv_reqF_countReg$D_IN; wire wci_wslv_reqF_countReg$EN; - // register wci_wslv_respF_c_r - reg [1 : 0] wci_wslv_respF_c_r; - wire [1 : 0] wci_wslv_respF_c_r$D_IN; - wire wci_wslv_respF_c_r$EN; + // register wci_wslv_respF_cntr_r + reg [1 : 0] wci_wslv_respF_cntr_r; + wire [1 : 0] wci_wslv_respF_cntr_r$D_IN; + wire wci_wslv_respF_cntr_r$EN; // register wci_wslv_respF_q_0 reg [33 : 0] wci_wslv_respF_q_0; @@ -403,86 +403,90 @@ module mkICAPWorker(wciS0_Clk, MUX_wci_wslv_respF_x_wire$wset_1__VAL_2; wire [10 : 0] MUX_coutF_rRdPtr_rsCounter$write_1__VAL_1, MUX_coutF_rWrPtr_rsCounter$write_1__VAL_1; - wire [1 : 0] MUX_wci_wslv_respF_c_r$write_1__VAL_1, - MUX_wci_wslv_respF_c_r$write_1__VAL_2; + wire [1 : 0] MUX_wci_wslv_respF_cntr_r$write_1__VAL_2; wire MUX_wci_wslv_illegalEdge$write_1__SEL_1, MUX_wci_wslv_illegalEdge$write_1__VAL_1, + MUX_wci_wslv_respF_q_0$write_1__SEL_1, MUX_wci_wslv_respF_q_0$write_1__SEL_2, + MUX_wci_wslv_respF_q_1$write_1__SEL_1, MUX_wci_wslv_respF_q_1$write_1__SEL_2; // remaining internal signals - reg [63 : 0] v__h26767, v__h3695, v__h3870, v__h4014; - reg [31 : 0] v__h26514; - wire [31 : 0] IF_coutF_rRdPtr_rsCounter_93_BIT_0_00_OR_coutF_ETC___d756, - IF_coutF_rWrPtr_rsCounter_24_BIT_0_31_OR_coutF_ETC___d755, - IF_coutF_rWrPtr_rsCounter_24_BIT_0_31_XOR_cout_ETC___d754, - icapStatus__h26137, - rdat__h26538, - rdat__h26544, - rdat__h26550, - rdat__h26556, - x3__h20817, - x__h19564; - wire [10 : 0] coutF_rRdPtr_rdCounter_24_BIT_10_25_CONCAT_cou_ETC___d675, - x__h16406, - x__h18708, - x__h22081, - x_dReadBin__h20521, - x_sReadBin__h20518, - y__h17293, - y__h19595; - wire [9 : 0] x2__h22050; - wire [2 : 0] x__h26631; - wire NOT_coutF_rRdPtr_rsCounter_93_EQ_coutF_rWrPtr__ETC___d601, - NOT_wci_wslv_respF_c_r_2_EQ_2_1_2_AND_wci_wslv_ETC___d592, - coutF_rRdPtr_rdCounter_24_BIT_10_25_XOR_coutF__ETC___d669, - coutF_rRdPtr_rdCounter_24_BIT_10_25_XOR_coutF__ETC___d670, - coutF_rRdPtr_rdCounter_24_BIT_10_25_XOR_coutF__ETC___d671, - coutF_rRdPtr_rdCounter_24_BIT_10_25_XOR_coutF__ETC___d672, - coutF_rRdPtr_rdCounter_24_BIT_10_25_XOR_coutF__ETC___d673, - coutF_rRdPtr_rdCounter_24_BIT_10_25_XOR_coutF__ETC___d674, - coutF_rRdPtr_rdCounter_24_BIT_10_25_XOR_coutF__ETC___d676, - coutF_rRdPtr_rdCounter_24_BIT_10_25_XOR_coutF__ETC___d678, - coutF_rRdPtr_rdCounter_24_BIT_10_25_XOR_coutF__ETC___d683, - coutF_rRdPtr_rsCounter_93_BIT_0_00_XOR_coutF_r_ETC___d722, - coutF_rRdPtr_rsCounter_93_BIT_10_19_XOR_coutF__ETC___d662, - coutF_rRdPtr_rsCounter_93_BIT_10_19_XOR_coutF__ETC___d663, - coutF_rRdPtr_rsCounter_93_BIT_10_19_XOR_coutF__ETC___d664, - coutF_rRdPtr_rsCounter_93_BIT_10_19_XOR_coutF__ETC___d665, - coutF_rRdPtr_rsCounter_93_BIT_10_19_XOR_coutF__ETC___d666, - coutF_rRdPtr_rsCounter_93_BIT_10_19_XOR_coutF__ETC___d667, - coutF_rRdPtr_rsCounter_93_BIT_10_19_XOR_coutF__ETC___d668, - coutF_rRdPtr_rsCounter_93_BIT_10_19_XOR_coutF__ETC___d680, - coutF_rRdPtr_rsCounter_93_BIT_10_19_XOR_coutF__ETC___d682, - coutF_rRdPtr_rsCounter_93_BIT_10_19_XOR_coutF__ETC___d701, - coutF_rWrPtr_rsCounter_24_BIT_0_31_XOR_coutF_r_ETC___d721, - coutF_rWrPtr_rsCounter_24_BIT_10_50_XOR_coutF__ETC___d654, - coutF_rWrPtr_rsCounter_24_BIT_10_50_XOR_coutF__ETC___d655, - coutF_rWrPtr_rsCounter_24_BIT_10_50_XOR_coutF__ETC___d656, - coutF_rWrPtr_rsCounter_24_BIT_10_50_XOR_coutF__ETC___d657, - coutF_rWrPtr_rsCounter_24_BIT_10_50_XOR_coutF__ETC___d658, - coutF_rWrPtr_rsCounter_24_BIT_10_50_XOR_coutF__ETC___d659, - coutF_rWrPtr_rsCounter_24_BIT_10_50_XOR_coutF__ETC___d660, - coutF_rWrPtr_rsCounter_24_BIT_10_50_XOR_coutF__ETC___d661, - coutF_rWrPtr_rsCounter_24_BIT_10_50_XOR_coutF__ETC___d681, - z__h17337, - z__h17344, - z__h17351, - z__h17358, - z__h17365, - z__h17372, - z__h17379, - z__h17386, - z__h17393, - z__h19639, - z__h19646, - z__h19653, - z__h19660, - z__h19667, - z__h19674, - z__h19681, - z__h19688, - z__h19695; + reg [63 : 0] v__h26628, v__h3563, v__h3738, v__h3882; + reg [31 : 0] v__h26380; + wire [31 : 0] IF_coutF_rRdPtr_rsCounter_91_BIT_0_98_OR_coutF_ETC___d439, + IF_coutF_rRdPtr_rsCounter_91_BIT_0_98_XOR_cout_ETC___d440, + IF_coutF_rWrPtr_rsCounter_22_BIT_0_29_OR_coutF_ETC___d370, + IF_coutF_rWrPtr_rsCounter_22_BIT_0_29_XOR_cout_ETC___d371, + icapStatus__h26003, + rdat__h26404, + rdat__h26410, + rdat__h26416, + rdat__h26422, + x3__h20684; + wire [10 : 0] coutF_rRdPtr_rdCounter_22_BIT_10_23_CONCAT_cou_ETC___d549, + x__h16273, + x__h18575, + x__h21947, + x_dReadBin__h20388, + x_sReadBin__h20385, + y__h17160, + y__h19462; + wire [9 : 0] x2__h21916; + wire [2 : 0] x__h26497; + wire [1 : 0] wci_wslv_respF_cntr_r_8_MINUS_1___d27; + wire NOT_coutF_rRdPtr_rsCounter_91_EQ_coutF_rWrPtr__ETC___d599, + NOT_wci_wslv_respF_cntr_r_8_EQ_2_1_2_AND_wci_w_ETC___d590, + _dfoo1, + _dfoo3, + coutF_rRdPtr_rdCounter_22_BIT_10_23_XOR_coutF__ETC___d525, + coutF_rRdPtr_rdCounter_22_BIT_10_23_XOR_coutF__ETC___d527, + coutF_rRdPtr_rdCounter_22_BIT_10_23_XOR_coutF__ETC___d530, + coutF_rRdPtr_rdCounter_22_BIT_10_23_XOR_coutF__ETC___d532, + coutF_rRdPtr_rdCounter_22_BIT_10_23_XOR_coutF__ETC___d535, + coutF_rRdPtr_rdCounter_22_BIT_10_23_XOR_coutF__ETC___d537, + coutF_rRdPtr_rdCounter_22_BIT_10_23_XOR_coutF__ETC___d540, + coutF_rRdPtr_rdCounter_22_BIT_10_23_XOR_coutF__ETC___d542, + coutF_rRdPtr_rdCounter_22_BIT_10_23_XOR_coutF__ETC___d545, + coutF_rRdPtr_rsCounter_91_BIT_0_98_XOR_coutF_r_ETC___d418, + coutF_rRdPtr_rsCounter_91_BIT_10_17_XOR_coutF__ETC___d481, + coutF_rRdPtr_rsCounter_91_BIT_10_17_XOR_coutF__ETC___d482, + coutF_rRdPtr_rsCounter_91_BIT_10_17_XOR_coutF__ETC___d484, + coutF_rRdPtr_rsCounter_91_BIT_10_17_XOR_coutF__ETC___d485, + coutF_rRdPtr_rsCounter_91_BIT_10_17_XOR_coutF__ETC___d487, + coutF_rRdPtr_rsCounter_91_BIT_10_17_XOR_coutF__ETC___d488, + coutF_rRdPtr_rsCounter_91_BIT_10_17_XOR_coutF__ETC___d490, + coutF_rRdPtr_rsCounter_91_BIT_10_17_XOR_coutF__ETC___d491, + coutF_rRdPtr_rsCounter_91_BIT_10_17_XOR_coutF__ETC___d493, + coutF_rRdPtr_rsCounter_91_BIT_10_17_XOR_coutF__ETC___d494, + coutF_rWrPtr_rsCounter_22_BIT_0_29_XOR_coutF_r_ETC___d349, + coutF_rWrPtr_rsCounter_22_BIT_10_48_XOR_coutF__ETC___d461, + coutF_rWrPtr_rsCounter_22_BIT_10_48_XOR_coutF__ETC___d462, + coutF_rWrPtr_rsCounter_22_BIT_10_48_XOR_coutF__ETC___d464, + coutF_rWrPtr_rsCounter_22_BIT_10_48_XOR_coutF__ETC___d465, + coutF_rWrPtr_rsCounter_22_BIT_10_48_XOR_coutF__ETC___d467, + coutF_rWrPtr_rsCounter_22_BIT_10_48_XOR_coutF__ETC___d468, + coutF_rWrPtr_rsCounter_22_BIT_10_48_XOR_coutF__ETC___d470, + coutF_rWrPtr_rsCounter_22_BIT_10_48_XOR_coutF__ETC___d471, + coutF_rWrPtr_rsCounter_22_BIT_10_48_XOR_coutF__ETC___d473, + z__h17204, + z__h17211, + z__h17218, + z__h17225, + z__h17232, + z__h17239, + z__h17246, + z__h17253, + z__h17260, + z__h19506, + z__h19513, + z__h19520, + z__h19527, + z__h19534, + z__h19541, + z__h19548, + z__h19555, + z__h19562; // value method wciS0_sResp assign wciS0_SResp = wci_wslv_respF_q_0[33:32] ; @@ -636,7 +640,7 @@ module mkICAPWorker(wciS0_Clk, // rule RL_wci_cfwr assign WILL_FIRE_RL_wci_cfwr = - NOT_wci_wslv_respF_c_r_2_EQ_2_1_2_AND_wci_wslv_ETC___d592 && + NOT_wci_wslv_respF_cntr_r_8_EQ_2_1_2_AND_wci_w_ETC___d590 && wci_wslv_wci_cfwr_pw$whas && !WILL_FIRE_RL_wci_wslv_ctl_op_start && !WILL_FIRE_RL_wci_wslv_ctl_op_complete ; @@ -669,7 +673,7 @@ module mkICAPWorker(wciS0_Clk, // rule RL_wci_wslv_ctl_op_complete assign WILL_FIRE_RL_wci_wslv_ctl_op_complete = - wci_wslv_respF_c_r != 2'd2 && wci_wslv_ctlOpActive && + wci_wslv_respF_cntr_r != 2'd2 && wci_wslv_ctlOpActive && wci_wslv_ctlAckReg ; // rule RL_icap_write_configration_data @@ -691,9 +695,9 @@ module mkICAPWorker(wciS0_Clk, // rule RL_wci_cfrd assign CAN_FIRE_RL_wci_cfrd = - wci_wslv_respF_c_r != 2'd2 && wci_wslv_reqF$EMPTY_N && + wci_wslv_respF_cntr_r != 2'd2 && wci_wslv_reqF$EMPTY_N && (wci_wslv_reqF$D_OUT[63:32] != 32'h0000000C || - NOT_coutF_rRdPtr_rsCounter_93_EQ_coutF_rWrPtr__ETC___d601) && + NOT_coutF_rRdPtr_rsCounter_91_EQ_coutF_rWrPtr__ETC___d599) && wci_wslv_wci_cfrd_pw$whas ; assign WILL_FIRE_RL_wci_cfrd = CAN_FIRE_RL_wci_cfrd && !WILL_FIRE_RL_wci_wslv_ctl_op_start && @@ -701,22 +705,17 @@ module mkICAPWorker(wciS0_Clk, // rule RL_wci_wslv_respF_incCtr assign WILL_FIRE_RL_wci_wslv_respF_incCtr = - ((wci_wslv_respF_c_r == 2'd0) ? - wci_wslv_respF_x_wire$whas : - wci_wslv_respF_c_r != 2'd1 || wci_wslv_respF_x_wire$whas) && - wci_wslv_respF_enqueueing$whas && - !(wci_wslv_respF_c_r != 2'd0) ; + wci_wslv_respF_x_wire$whas && wci_wslv_respF_enqueueing$whas && + !(wci_wslv_respF_cntr_r != 2'd0) ; // rule RL_wci_wslv_respF_decCtr assign WILL_FIRE_RL_wci_wslv_respF_decCtr = - wci_wslv_respF_c_r != 2'd0 && !wci_wslv_respF_enqueueing$whas ; + wci_wslv_respF_cntr_r != 2'd0 && + !wci_wslv_respF_enqueueing$whas ; // rule RL_wci_wslv_respF_both assign WILL_FIRE_RL_wci_wslv_respF_both = - ((wci_wslv_respF_c_r == 2'd1) ? - wci_wslv_respF_x_wire$whas : - wci_wslv_respF_c_r != 2'd2 || wci_wslv_respF_x_wire$whas) && - wci_wslv_respF_c_r != 2'd0 && + wci_wslv_respF_x_wire$whas && wci_wslv_respF_cntr_r != 2'd0 && wci_wslv_respF_enqueueing$whas ; // inputs to muxes for submodule ports @@ -733,28 +732,32 @@ module mkICAPWorker(wciS0_Clk, wci_wslv_reqF$D_OUT[36:34] == 3'd5 || wci_wslv_reqF$D_OUT[36:34] == 3'd6 || wci_wslv_reqF$D_OUT[36:34] == 3'd7) ; + assign MUX_wci_wslv_respF_q_0$write_1__SEL_1 = + WILL_FIRE_RL_wci_wslv_respF_both && _dfoo3 ; assign MUX_wci_wslv_respF_q_0$write_1__SEL_2 = WILL_FIRE_RL_wci_wslv_respF_incCtr && - wci_wslv_respF_c_r == 2'd0 ; + wci_wslv_respF_cntr_r == 2'd0 ; + assign MUX_wci_wslv_respF_q_1$write_1__SEL_1 = + WILL_FIRE_RL_wci_wslv_respF_both && _dfoo1 ; assign MUX_wci_wslv_respF_q_1$write_1__SEL_2 = WILL_FIRE_RL_wci_wslv_respF_incCtr && - wci_wslv_respF_c_r == 2'd1 ; + wci_wslv_respF_cntr_r == 2'd1 ; assign MUX_coutF_rRdPtr_rsCounter$write_1__VAL_1 = - (~coutF_rRdPtr_rsCounter[x__h19564[3:0]]) ? - coutF_rRdPtr_rsCounter | x__h18708 : - coutF_rRdPtr_rsCounter & y__h19595 ; + (~coutF_rRdPtr_rsCounter[IF_coutF_rRdPtr_rsCounter_91_BIT_0_98_XOR_cout_ETC___d440[3:0]]) ? + coutF_rRdPtr_rsCounter | x__h18575 : + coutF_rRdPtr_rsCounter & y__h19462 ; assign MUX_coutF_rWrPtr_rsCounter$write_1__VAL_1 = - (~coutF_rWrPtr_rsCounter[IF_coutF_rWrPtr_rsCounter_24_BIT_0_31_XOR_cout_ETC___d754[3:0]]) ? - coutF_rWrPtr_rsCounter | x__h16406 : - coutF_rWrPtr_rsCounter & y__h17293 ; + (~coutF_rWrPtr_rsCounter[IF_coutF_rWrPtr_rsCounter_22_BIT_0_29_XOR_cout_ETC___d371[3:0]]) ? + coutF_rWrPtr_rsCounter | x__h16273 : + coutF_rWrPtr_rsCounter & y__h17160 ; assign MUX_wci_wslv_illegalEdge$write_1__VAL_1 = wci_wslv_reqF$D_OUT[36:34] != 3'd4 && wci_wslv_reqF$D_OUT[36:34] != 3'd5 && wci_wslv_reqF$D_OUT[36:34] != 3'd6 ; - assign MUX_wci_wslv_respF_c_r$write_1__VAL_1 = wci_wslv_respF_c_r + 2'd1 ; - assign MUX_wci_wslv_respF_c_r$write_1__VAL_2 = wci_wslv_respF_c_r - 2'd1 ; + assign MUX_wci_wslv_respF_cntr_r$write_1__VAL_2 = + wci_wslv_respF_cntr_r + 2'd1 ; assign MUX_wci_wslv_respF_q_0$write_1__VAL_1 = - (wci_wslv_respF_c_r == 2'd1) ? + (wci_wslv_respF_cntr_r == 2'd1) ? MUX_wci_wslv_respF_q_0$write_1__VAL_2 : wci_wslv_respF_q_1 ; always@(WILL_FIRE_RL_wci_wslv_ctl_op_complete or @@ -776,12 +779,12 @@ module mkICAPWorker(wciS0_Clk, endcase end assign MUX_wci_wslv_respF_q_1$write_1__VAL_1 = - (wci_wslv_respF_c_r == 2'd2) ? + (wci_wslv_respF_cntr_r == 2'd2) ? MUX_wci_wslv_respF_q_0$write_1__VAL_2 : 34'h0AAAAAAAA ; assign MUX_wci_wslv_respF_x_wire$wset_1__VAL_1 = wci_wslv_illegalEdge ? 34'h3C0DE4202 : 34'h1C0DE4201 ; - assign MUX_wci_wslv_respF_x_wire$wset_1__VAL_2 = { 2'd1, v__h26514 } ; + assign MUX_wci_wslv_respF_x_wire$wset_1__VAL_2 = { 2'd1, v__h26380 } ; // inlined wires assign wci_wslv_wciReq$wget = @@ -875,7 +878,7 @@ module mkICAPWorker(wciS0_Clk, assign wci_wslv_respF_enqueueing$whas = WILL_FIRE_RL_wci_cfrd || WILL_FIRE_RL_wci_cfwr || WILL_FIRE_RL_wci_wslv_ctl_op_complete ; - assign wci_wslv_respF_dequeueing$whas = wci_wslv_respF_c_r != 2'd0 ; + assign wci_wslv_respF_dequeueing$whas = wci_wslv_respF_cntr_r != 2'd0 ; assign wci_wslv_sThreadBusy_pw$whas = 1'b0 ; assign wci_wslv_wci_cfwr_pw$whas = wci_wslv_reqF$EMPTY_N && wci_wslv_reqF$D_OUT[68] && @@ -904,27 +907,27 @@ module mkICAPWorker(wciS0_Clk, wci_wslv_reqF$D_OUT[63:32] == 32'h0000000C ; assign coutF_pwEnqueue$whas = coutF_rWrPtr_rsCounter != - { coutF_rRdPtr_rdCounter_24_BIT_10_25_CONCAT_cou_ETC___d675[10], - coutF_rRdPtr_rdCounter_24_BIT_10_25_CONCAT_cou_ETC___d675[10] ^ - coutF_rRdPtr_rdCounter_24_BIT_10_25_CONCAT_cou_ETC___d675[9], - coutF_rRdPtr_rdCounter_24_BIT_10_25_CONCAT_cou_ETC___d675[9] ^ - coutF_rRdPtr_rdCounter_24_BIT_10_25_CONCAT_cou_ETC___d675[8], - coutF_rRdPtr_rdCounter_24_BIT_10_25_CONCAT_cou_ETC___d675[8] ^ - coutF_rRdPtr_rdCounter_24_BIT_10_25_CONCAT_cou_ETC___d675[7], - coutF_rRdPtr_rdCounter_24_BIT_10_25_CONCAT_cou_ETC___d675[7] ^ - coutF_rRdPtr_rdCounter_24_BIT_10_25_CONCAT_cou_ETC___d675[6], - coutF_rRdPtr_rdCounter_24_BIT_10_25_CONCAT_cou_ETC___d675[6] ^ - coutF_rRdPtr_rdCounter_24_BIT_10_25_CONCAT_cou_ETC___d675[5], - coutF_rRdPtr_rdCounter_24_BIT_10_25_CONCAT_cou_ETC___d675[5] ^ - coutF_rRdPtr_rdCounter_24_BIT_10_25_CONCAT_cou_ETC___d675[4], - coutF_rRdPtr_rdCounter_24_BIT_10_25_CONCAT_cou_ETC___d675[4] ^ - coutF_rRdPtr_rdCounter_24_BIT_10_25_CONCAT_cou_ETC___d675[3], - coutF_rRdPtr_rdCounter_24_BIT_10_25_CONCAT_cou_ETC___d675[3] ^ - coutF_rRdPtr_rdCounter_24_BIT_10_25_CONCAT_cou_ETC___d675[2], - coutF_rRdPtr_rdCounter_24_BIT_10_25_CONCAT_cou_ETC___d675[2] ^ - coutF_rRdPtr_rdCounter_24_BIT_10_25_CONCAT_cou_ETC___d675[1], - coutF_rRdPtr_rdCounter_24_BIT_10_25_CONCAT_cou_ETC___d675[1] ^ - coutF_rRdPtr_rdCounter_24_BIT_10_25_CONCAT_cou_ETC___d675[0] } && + { coutF_rRdPtr_rdCounter_22_BIT_10_23_CONCAT_cou_ETC___d549[10], + coutF_rRdPtr_rdCounter_22_BIT_10_23_CONCAT_cou_ETC___d549[10] ^ + coutF_rRdPtr_rdCounter_22_BIT_10_23_CONCAT_cou_ETC___d549[9], + coutF_rRdPtr_rdCounter_22_BIT_10_23_CONCAT_cou_ETC___d549[9] ^ + coutF_rRdPtr_rdCounter_22_BIT_10_23_CONCAT_cou_ETC___d549[8], + coutF_rRdPtr_rdCounter_22_BIT_10_23_CONCAT_cou_ETC___d549[8] ^ + coutF_rRdPtr_rdCounter_22_BIT_10_23_CONCAT_cou_ETC___d549[7], + coutF_rRdPtr_rdCounter_22_BIT_10_23_CONCAT_cou_ETC___d549[7] ^ + coutF_rRdPtr_rdCounter_22_BIT_10_23_CONCAT_cou_ETC___d549[6], + coutF_rRdPtr_rdCounter_22_BIT_10_23_CONCAT_cou_ETC___d549[6] ^ + coutF_rRdPtr_rdCounter_22_BIT_10_23_CONCAT_cou_ETC___d549[5], + coutF_rRdPtr_rdCounter_22_BIT_10_23_CONCAT_cou_ETC___d549[5] ^ + coutF_rRdPtr_rdCounter_22_BIT_10_23_CONCAT_cou_ETC___d549[4], + coutF_rRdPtr_rdCounter_22_BIT_10_23_CONCAT_cou_ETC___d549[4] ^ + coutF_rRdPtr_rdCounter_22_BIT_10_23_CONCAT_cou_ETC___d549[3], + coutF_rRdPtr_rdCounter_22_BIT_10_23_CONCAT_cou_ETC___d549[3] ^ + coutF_rRdPtr_rdCounter_22_BIT_10_23_CONCAT_cou_ETC___d549[2], + coutF_rRdPtr_rdCounter_22_BIT_10_23_CONCAT_cou_ETC___d549[2] ^ + coutF_rRdPtr_rdCounter_22_BIT_10_23_CONCAT_cou_ETC___d549[1], + coutF_rRdPtr_rdCounter_22_BIT_10_23_CONCAT_cou_ETC___d549[1] ^ + coutF_rRdPtr_rdCounter_22_BIT_10_23_CONCAT_cou_ETC___d549[0] } && icap_coutF$EMPTY_N ; assign coutF_rWrPtr_wdCounterCrossing$wget = coutF_rWrPtr_rsCounter ; assign coutF_rRdPtr_wdCounterCrossing$wget = coutF_rRdPtr_rsCounter ; @@ -1079,24 +1082,24 @@ module mkICAPWorker(wciS0_Clk, (wci_wslv_wciReq$wget[71:69] != 3'd0) != wci_wslv_reqF_r_deq$whas ; - // register wci_wslv_respF_c_r - assign wci_wslv_respF_c_r$D_IN = - WILL_FIRE_RL_wci_wslv_respF_incCtr ? - MUX_wci_wslv_respF_c_r$write_1__VAL_1 : - MUX_wci_wslv_respF_c_r$write_1__VAL_2 ; - assign wci_wslv_respF_c_r$EN = - WILL_FIRE_RL_wci_wslv_respF_incCtr || - WILL_FIRE_RL_wci_wslv_respF_decCtr ; + // register wci_wslv_respF_cntr_r + assign wci_wslv_respF_cntr_r$D_IN = + WILL_FIRE_RL_wci_wslv_respF_decCtr ? + wci_wslv_respF_cntr_r_8_MINUS_1___d27 : + MUX_wci_wslv_respF_cntr_r$write_1__VAL_2 ; + assign wci_wslv_respF_cntr_r$EN = + WILL_FIRE_RL_wci_wslv_respF_decCtr || + WILL_FIRE_RL_wci_wslv_respF_incCtr ; // register wci_wslv_respF_q_0 - always@(WILL_FIRE_RL_wci_wslv_respF_both or + always@(MUX_wci_wslv_respF_q_0$write_1__SEL_1 or MUX_wci_wslv_respF_q_0$write_1__VAL_1 or MUX_wci_wslv_respF_q_0$write_1__SEL_2 or MUX_wci_wslv_respF_q_0$write_1__VAL_2 or WILL_FIRE_RL_wci_wslv_respF_decCtr or wci_wslv_respF_q_1) begin case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_wci_wslv_respF_both: + MUX_wci_wslv_respF_q_0$write_1__SEL_1: wci_wslv_respF_q_0$D_IN = MUX_wci_wslv_respF_q_0$write_1__VAL_1; MUX_wci_wslv_respF_q_0$write_1__SEL_2: wci_wslv_respF_q_0$D_IN = MUX_wci_wslv_respF_q_0$write_1__VAL_2; @@ -1107,20 +1110,20 @@ module mkICAPWorker(wciS0_Clk, endcase end assign wci_wslv_respF_q_0$EN = - WILL_FIRE_RL_wci_wslv_respF_both || + WILL_FIRE_RL_wci_wslv_respF_both && _dfoo3 || WILL_FIRE_RL_wci_wslv_respF_incCtr && - wci_wslv_respF_c_r == 2'd0 || + wci_wslv_respF_cntr_r == 2'd0 || WILL_FIRE_RL_wci_wslv_respF_decCtr ; // register wci_wslv_respF_q_1 - always@(WILL_FIRE_RL_wci_wslv_respF_both or + always@(MUX_wci_wslv_respF_q_1$write_1__SEL_1 or MUX_wci_wslv_respF_q_1$write_1__VAL_1 or MUX_wci_wslv_respF_q_1$write_1__SEL_2 or MUX_wci_wslv_respF_q_0$write_1__VAL_2 or WILL_FIRE_RL_wci_wslv_respF_decCtr) begin case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_wci_wslv_respF_both: + MUX_wci_wslv_respF_q_1$write_1__SEL_1: wci_wslv_respF_q_1$D_IN = MUX_wci_wslv_respF_q_1$write_1__VAL_1; MUX_wci_wslv_respF_q_1$write_1__SEL_2: wci_wslv_respF_q_1$D_IN = MUX_wci_wslv_respF_q_0$write_1__VAL_2; @@ -1131,9 +1134,9 @@ module mkICAPWorker(wciS0_Clk, endcase end assign wci_wslv_respF_q_1$EN = - WILL_FIRE_RL_wci_wslv_respF_both || + WILL_FIRE_RL_wci_wslv_respF_both && _dfoo1 || WILL_FIRE_RL_wci_wslv_respF_incCtr && - wci_wslv_respF_c_r == 2'd1 || + wci_wslv_respF_cntr_r == 2'd1 || WILL_FIRE_RL_wci_wslv_respF_decCtr ; // register wci_wslv_sFlagReg @@ -1146,20 +1149,20 @@ module mkICAPWorker(wciS0_Clk, // submodule coutF_memory assign coutF_memory$ADDRA = - { coutF_rWrPtr_rsCounter_24_BIT_10_50_XOR_coutF__ETC___d654, - coutF_rWrPtr_rsCounter_24_BIT_10_50_XOR_coutF__ETC___d681, - coutF_rWrPtr_rsCounter_24_BIT_10_50_XOR_coutF__ETC___d656, - coutF_rWrPtr_rsCounter_24_BIT_10_50_XOR_coutF__ETC___d655, - coutF_rWrPtr_rsCounter_24_BIT_10_50_XOR_coutF__ETC___d657, - coutF_rWrPtr_rsCounter_24_BIT_10_50_XOR_coutF__ETC___d658, - coutF_rWrPtr_rsCounter_24_BIT_10_50_XOR_coutF__ETC___d660, - coutF_rWrPtr_rsCounter_24_BIT_10_50_XOR_coutF__ETC___d659, - coutF_rWrPtr_rsCounter_24_BIT_10_50_XOR_coutF__ETC___d661, - coutF_rWrPtr_rsCounter_24_BIT_10_50_XOR_coutF__ETC___d661 ^ + { coutF_rWrPtr_rsCounter_22_BIT_10_48_XOR_coutF__ETC___d461, + coutF_rWrPtr_rsCounter_22_BIT_10_48_XOR_coutF__ETC___d462, + coutF_rWrPtr_rsCounter_22_BIT_10_48_XOR_coutF__ETC___d464, + coutF_rWrPtr_rsCounter_22_BIT_10_48_XOR_coutF__ETC___d465, + coutF_rWrPtr_rsCounter_22_BIT_10_48_XOR_coutF__ETC___d467, + coutF_rWrPtr_rsCounter_22_BIT_10_48_XOR_coutF__ETC___d468, + coutF_rWrPtr_rsCounter_22_BIT_10_48_XOR_coutF__ETC___d470, + coutF_rWrPtr_rsCounter_22_BIT_10_48_XOR_coutF__ETC___d471, + coutF_rWrPtr_rsCounter_22_BIT_10_48_XOR_coutF__ETC___d473, + coutF_rWrPtr_rsCounter_22_BIT_10_48_XOR_coutF__ETC___d473 ^ coutF_rWrPtr_rsCounter[0] } ; assign coutF_memory$ADDRB = - coutF_pwDequeue$whas ? x__h22081[9:0] : x2__h22050 ; - assign coutF_memory$DIA = x3__h20817 ; + coutF_pwDequeue$whas ? x__h21947[9:0] : x2__h21916 ; + assign coutF_memory$DIA = x3__h20684 ; assign coutF_memory$DIB = 32'hAAAAAAAA /* unspecified value */ ; assign coutF_memory$WEA = coutF_pwEnqueue$whas ; assign coutF_memory$WEB = 1'd0 ; @@ -1239,7 +1242,7 @@ module mkICAPWorker(wciS0_Clk, assign wci_wslv_reqF$CLR = 1'b0 ; // remaining internal signals - assign IF_coutF_rRdPtr_rsCounter_93_BIT_0_00_OR_coutF_ETC___d756 = + assign IF_coutF_rRdPtr_rsCounter_91_BIT_0_98_OR_coutF_ETC___d439 = (coutF_rRdPtr_rsCounter[0] || coutF_rRdPtr_rsCounter[1] || coutF_rRdPtr_rsCounter[2] || coutF_rRdPtr_rsCounter[3] || @@ -1273,7 +1276,11 @@ module mkICAPWorker(wciS0_Clk, 32'd11 : 32'd12))))))))))) : 32'd10 ; - assign IF_coutF_rWrPtr_rsCounter_24_BIT_0_31_OR_coutF_ETC___d755 = + assign IF_coutF_rRdPtr_rsCounter_91_BIT_0_98_XOR_cout_ETC___d440 = + coutF_rRdPtr_rsCounter_91_BIT_0_98_XOR_coutF_r_ETC___d418 ? + IF_coutF_rRdPtr_rsCounter_91_BIT_0_98_OR_coutF_ETC___d439 : + 32'd0 ; + assign IF_coutF_rWrPtr_rsCounter_22_BIT_0_29_OR_coutF_ETC___d370 = (coutF_rWrPtr_rsCounter[0] || coutF_rWrPtr_rsCounter[1] || coutF_rWrPtr_rsCounter[2] || coutF_rWrPtr_rsCounter[3] || @@ -1307,193 +1314,199 @@ module mkICAPWorker(wciS0_Clk, 32'd11 : 32'd12))))))))))) : 32'd10 ; - assign IF_coutF_rWrPtr_rsCounter_24_BIT_0_31_XOR_cout_ETC___d754 = - coutF_rWrPtr_rsCounter_24_BIT_0_31_XOR_coutF_r_ETC___d721 ? - IF_coutF_rWrPtr_rsCounter_24_BIT_0_31_OR_coutF_ETC___d755 : + assign IF_coutF_rWrPtr_rsCounter_22_BIT_0_29_XOR_cout_ETC___d371 = + coutF_rWrPtr_rsCounter_22_BIT_0_29_XOR_coutF_r_ETC___d349 ? + IF_coutF_rWrPtr_rsCounter_22_BIT_0_29_OR_coutF_ETC___d370 : 32'd0 ; - assign NOT_coutF_rRdPtr_rsCounter_93_EQ_coutF_rWrPtr__ETC___d601 = + assign NOT_coutF_rRdPtr_rsCounter_91_EQ_coutF_rWrPtr__ETC___d599 = coutF_rRdPtr_rsCounter != coutF_rWrPtr_rdCounter ; - assign NOT_wci_wslv_respF_c_r_2_EQ_2_1_2_AND_wci_wslv_ETC___d592 = - wci_wslv_respF_c_r != 2'd2 && wci_wslv_reqF$EMPTY_N && + assign NOT_wci_wslv_respF_cntr_r_8_EQ_2_1_2_AND_wci_w_ETC___d590 = + wci_wslv_respF_cntr_r != 2'd2 && wci_wslv_reqF$EMPTY_N && (wci_wslv_reqF$D_OUT[63:32] != 32'h00000008 || cinF_head_wrapped == cinF_tail_wrapped && !cinF_sInReset$VAL && cd$PREEDGE) ; - assign coutF_rRdPtr_rdCounter_24_BIT_10_25_CONCAT_cou_ETC___d675 = - x_dReadBin__h20521 + 11'd512 ; - assign coutF_rRdPtr_rdCounter_24_BIT_10_25_XOR_coutF__ETC___d669 = + assign _dfoo1 = + wci_wslv_respF_cntr_r != 2'd2 || + wci_wslv_respF_cntr_r_8_MINUS_1___d27 == 2'd1 ; + assign _dfoo3 = + wci_wslv_respF_cntr_r != 2'd1 || + wci_wslv_respF_cntr_r_8_MINUS_1___d27 == 2'd0 ; + assign coutF_rRdPtr_rdCounter_22_BIT_10_23_CONCAT_cou_ETC___d549 = + x_dReadBin__h20388 + 11'd512 ; + assign coutF_rRdPtr_rdCounter_22_BIT_10_23_XOR_coutF__ETC___d525 = coutF_rRdPtr_rdCounter[10] ^ coutF_rRdPtr_rdCounter[9] ; - assign coutF_rRdPtr_rdCounter_24_BIT_10_25_XOR_coutF__ETC___d670 = - coutF_rRdPtr_rdCounter_24_BIT_10_25_XOR_coutF__ETC___d669 ^ + assign coutF_rRdPtr_rdCounter_22_BIT_10_23_XOR_coutF__ETC___d527 = + coutF_rRdPtr_rdCounter_22_BIT_10_23_XOR_coutF__ETC___d525 ^ coutF_rRdPtr_rdCounter[8] ; - assign coutF_rRdPtr_rdCounter_24_BIT_10_25_XOR_coutF__ETC___d671 = - coutF_rRdPtr_rdCounter_24_BIT_10_25_XOR_coutF__ETC___d683 ^ + assign coutF_rRdPtr_rdCounter_22_BIT_10_23_XOR_coutF__ETC___d530 = + coutF_rRdPtr_rdCounter_22_BIT_10_23_XOR_coutF__ETC___d527 ^ + coutF_rRdPtr_rdCounter[7] ; + assign coutF_rRdPtr_rdCounter_22_BIT_10_23_XOR_coutF__ETC___d532 = + coutF_rRdPtr_rdCounter_22_BIT_10_23_XOR_coutF__ETC___d530 ^ coutF_rRdPtr_rdCounter[6] ; - assign coutF_rRdPtr_rdCounter_24_BIT_10_25_XOR_coutF__ETC___d672 = - coutF_rRdPtr_rdCounter_24_BIT_10_25_XOR_coutF__ETC___d671 ^ + assign coutF_rRdPtr_rdCounter_22_BIT_10_23_XOR_coutF__ETC___d535 = + coutF_rRdPtr_rdCounter_22_BIT_10_23_XOR_coutF__ETC___d532 ^ coutF_rRdPtr_rdCounter[5] ; - assign coutF_rRdPtr_rdCounter_24_BIT_10_25_XOR_coutF__ETC___d673 = - coutF_rRdPtr_rdCounter_24_BIT_10_25_XOR_coutF__ETC___d678 ^ + assign coutF_rRdPtr_rdCounter_22_BIT_10_23_XOR_coutF__ETC___d537 = + coutF_rRdPtr_rdCounter_22_BIT_10_23_XOR_coutF__ETC___d535 ^ + coutF_rRdPtr_rdCounter[4] ; + assign coutF_rRdPtr_rdCounter_22_BIT_10_23_XOR_coutF__ETC___d540 = + coutF_rRdPtr_rdCounter_22_BIT_10_23_XOR_coutF__ETC___d537 ^ coutF_rRdPtr_rdCounter[3] ; - assign coutF_rRdPtr_rdCounter_24_BIT_10_25_XOR_coutF__ETC___d674 = - coutF_rRdPtr_rdCounter_24_BIT_10_25_XOR_coutF__ETC___d673 ^ + assign coutF_rRdPtr_rdCounter_22_BIT_10_23_XOR_coutF__ETC___d542 = + coutF_rRdPtr_rdCounter_22_BIT_10_23_XOR_coutF__ETC___d540 ^ coutF_rRdPtr_rdCounter[2] ; - assign coutF_rRdPtr_rdCounter_24_BIT_10_25_XOR_coutF__ETC___d676 = - coutF_rRdPtr_rdCounter_24_BIT_10_25_XOR_coutF__ETC___d674 ^ + assign coutF_rRdPtr_rdCounter_22_BIT_10_23_XOR_coutF__ETC___d545 = + coutF_rRdPtr_rdCounter_22_BIT_10_23_XOR_coutF__ETC___d542 ^ coutF_rRdPtr_rdCounter[1] ; - assign coutF_rRdPtr_rdCounter_24_BIT_10_25_XOR_coutF__ETC___d678 = - coutF_rRdPtr_rdCounter_24_BIT_10_25_XOR_coutF__ETC___d672 ^ - coutF_rRdPtr_rdCounter[4] ; - assign coutF_rRdPtr_rdCounter_24_BIT_10_25_XOR_coutF__ETC___d683 = - coutF_rRdPtr_rdCounter_24_BIT_10_25_XOR_coutF__ETC___d670 ^ - coutF_rRdPtr_rdCounter[7] ; - assign coutF_rRdPtr_rsCounter_93_BIT_0_00_XOR_coutF_r_ETC___d722 = - z__h19695 ^ coutF_rRdPtr_rsCounter[10] ; - assign coutF_rRdPtr_rsCounter_93_BIT_10_19_XOR_coutF__ETC___d662 = + assign coutF_rRdPtr_rsCounter_91_BIT_0_98_XOR_coutF_r_ETC___d418 = + z__h19562 ^ coutF_rRdPtr_rsCounter[10] ; + assign coutF_rRdPtr_rsCounter_91_BIT_10_17_XOR_coutF__ETC___d481 = coutF_rRdPtr_rsCounter[10] ^ coutF_rRdPtr_rsCounter[9] ; - assign coutF_rRdPtr_rsCounter_93_BIT_10_19_XOR_coutF__ETC___d663 = - coutF_rRdPtr_rsCounter_93_BIT_10_19_XOR_coutF__ETC___d662 ^ + assign coutF_rRdPtr_rsCounter_91_BIT_10_17_XOR_coutF__ETC___d482 = + coutF_rRdPtr_rsCounter_91_BIT_10_17_XOR_coutF__ETC___d481 ^ coutF_rRdPtr_rsCounter[8] ; - assign coutF_rRdPtr_rsCounter_93_BIT_10_19_XOR_coutF__ETC___d664 = - coutF_rRdPtr_rsCounter_93_BIT_10_19_XOR_coutF__ETC___d663 ^ + assign coutF_rRdPtr_rsCounter_91_BIT_10_17_XOR_coutF__ETC___d484 = + coutF_rRdPtr_rsCounter_91_BIT_10_17_XOR_coutF__ETC___d482 ^ coutF_rRdPtr_rsCounter[7] ; - assign coutF_rRdPtr_rsCounter_93_BIT_10_19_XOR_coutF__ETC___d665 = - coutF_rRdPtr_rsCounter_93_BIT_10_19_XOR_coutF__ETC___d664 ^ + assign coutF_rRdPtr_rsCounter_91_BIT_10_17_XOR_coutF__ETC___d485 = + coutF_rRdPtr_rsCounter_91_BIT_10_17_XOR_coutF__ETC___d484 ^ coutF_rRdPtr_rsCounter[6] ; - assign coutF_rRdPtr_rsCounter_93_BIT_10_19_XOR_coutF__ETC___d666 = - coutF_rRdPtr_rsCounter_93_BIT_10_19_XOR_coutF__ETC___d680 ^ + assign coutF_rRdPtr_rsCounter_91_BIT_10_17_XOR_coutF__ETC___d487 = + coutF_rRdPtr_rsCounter_91_BIT_10_17_XOR_coutF__ETC___d485 ^ + coutF_rRdPtr_rsCounter[5] ; + assign coutF_rRdPtr_rsCounter_91_BIT_10_17_XOR_coutF__ETC___d488 = + coutF_rRdPtr_rsCounter_91_BIT_10_17_XOR_coutF__ETC___d487 ^ coutF_rRdPtr_rsCounter[4] ; - assign coutF_rRdPtr_rsCounter_93_BIT_10_19_XOR_coutF__ETC___d667 = - coutF_rRdPtr_rsCounter_93_BIT_10_19_XOR_coutF__ETC___d666 ^ + assign coutF_rRdPtr_rsCounter_91_BIT_10_17_XOR_coutF__ETC___d490 = + coutF_rRdPtr_rsCounter_91_BIT_10_17_XOR_coutF__ETC___d488 ^ coutF_rRdPtr_rsCounter[3] ; - assign coutF_rRdPtr_rsCounter_93_BIT_10_19_XOR_coutF__ETC___d668 = - coutF_rRdPtr_rsCounter_93_BIT_10_19_XOR_coutF__ETC___d682 ^ - coutF_rRdPtr_rsCounter[1] ; - assign coutF_rRdPtr_rsCounter_93_BIT_10_19_XOR_coutF__ETC___d680 = - coutF_rRdPtr_rsCounter_93_BIT_10_19_XOR_coutF__ETC___d665 ^ - coutF_rRdPtr_rsCounter[5] ; - assign coutF_rRdPtr_rsCounter_93_BIT_10_19_XOR_coutF__ETC___d682 = - coutF_rRdPtr_rsCounter_93_BIT_10_19_XOR_coutF__ETC___d667 ^ + assign coutF_rRdPtr_rsCounter_91_BIT_10_17_XOR_coutF__ETC___d491 = + coutF_rRdPtr_rsCounter_91_BIT_10_17_XOR_coutF__ETC___d490 ^ coutF_rRdPtr_rsCounter[2] ; - assign coutF_rRdPtr_rsCounter_93_BIT_10_19_XOR_coutF__ETC___d701 = - coutF_rRdPtr_rsCounter_93_BIT_10_19_XOR_coutF__ETC___d668 ^ + assign coutF_rRdPtr_rsCounter_91_BIT_10_17_XOR_coutF__ETC___d493 = + coutF_rRdPtr_rsCounter_91_BIT_10_17_XOR_coutF__ETC___d491 ^ + coutF_rRdPtr_rsCounter[1] ; + assign coutF_rRdPtr_rsCounter_91_BIT_10_17_XOR_coutF__ETC___d494 = + coutF_rRdPtr_rsCounter_91_BIT_10_17_XOR_coutF__ETC___d493 ^ coutF_rRdPtr_rsCounter[0] ; - assign coutF_rWrPtr_rsCounter_24_BIT_0_31_XOR_coutF_r_ETC___d721 = - z__h17393 ^ coutF_rWrPtr_rsCounter[10] ; - assign coutF_rWrPtr_rsCounter_24_BIT_10_50_XOR_coutF__ETC___d654 = + assign coutF_rWrPtr_rsCounter_22_BIT_0_29_XOR_coutF_r_ETC___d349 = + z__h17260 ^ coutF_rWrPtr_rsCounter[10] ; + assign coutF_rWrPtr_rsCounter_22_BIT_10_48_XOR_coutF__ETC___d461 = coutF_rWrPtr_rsCounter[10] ^ coutF_rWrPtr_rsCounter[9] ; - assign coutF_rWrPtr_rsCounter_24_BIT_10_50_XOR_coutF__ETC___d655 = - coutF_rWrPtr_rsCounter_24_BIT_10_50_XOR_coutF__ETC___d656 ^ - coutF_rWrPtr_rsCounter[6] ; - assign coutF_rWrPtr_rsCounter_24_BIT_10_50_XOR_coutF__ETC___d656 = - coutF_rWrPtr_rsCounter_24_BIT_10_50_XOR_coutF__ETC___d681 ^ + assign coutF_rWrPtr_rsCounter_22_BIT_10_48_XOR_coutF__ETC___d462 = + coutF_rWrPtr_rsCounter_22_BIT_10_48_XOR_coutF__ETC___d461 ^ + coutF_rWrPtr_rsCounter[8] ; + assign coutF_rWrPtr_rsCounter_22_BIT_10_48_XOR_coutF__ETC___d464 = + coutF_rWrPtr_rsCounter_22_BIT_10_48_XOR_coutF__ETC___d462 ^ coutF_rWrPtr_rsCounter[7] ; - assign coutF_rWrPtr_rsCounter_24_BIT_10_50_XOR_coutF__ETC___d657 = - coutF_rWrPtr_rsCounter_24_BIT_10_50_XOR_coutF__ETC___d655 ^ + assign coutF_rWrPtr_rsCounter_22_BIT_10_48_XOR_coutF__ETC___d465 = + coutF_rWrPtr_rsCounter_22_BIT_10_48_XOR_coutF__ETC___d464 ^ + coutF_rWrPtr_rsCounter[6] ; + assign coutF_rWrPtr_rsCounter_22_BIT_10_48_XOR_coutF__ETC___d467 = + coutF_rWrPtr_rsCounter_22_BIT_10_48_XOR_coutF__ETC___d465 ^ coutF_rWrPtr_rsCounter[5] ; - assign coutF_rWrPtr_rsCounter_24_BIT_10_50_XOR_coutF__ETC___d658 = - coutF_rWrPtr_rsCounter_24_BIT_10_50_XOR_coutF__ETC___d657 ^ + assign coutF_rWrPtr_rsCounter_22_BIT_10_48_XOR_coutF__ETC___d468 = + coutF_rWrPtr_rsCounter_22_BIT_10_48_XOR_coutF__ETC___d467 ^ coutF_rWrPtr_rsCounter[4] ; - assign coutF_rWrPtr_rsCounter_24_BIT_10_50_XOR_coutF__ETC___d659 = - coutF_rWrPtr_rsCounter_24_BIT_10_50_XOR_coutF__ETC___d660 ^ - coutF_rWrPtr_rsCounter[2] ; - assign coutF_rWrPtr_rsCounter_24_BIT_10_50_XOR_coutF__ETC___d660 = - coutF_rWrPtr_rsCounter_24_BIT_10_50_XOR_coutF__ETC___d658 ^ + assign coutF_rWrPtr_rsCounter_22_BIT_10_48_XOR_coutF__ETC___d470 = + coutF_rWrPtr_rsCounter_22_BIT_10_48_XOR_coutF__ETC___d468 ^ coutF_rWrPtr_rsCounter[3] ; - assign coutF_rWrPtr_rsCounter_24_BIT_10_50_XOR_coutF__ETC___d661 = - coutF_rWrPtr_rsCounter_24_BIT_10_50_XOR_coutF__ETC___d659 ^ + assign coutF_rWrPtr_rsCounter_22_BIT_10_48_XOR_coutF__ETC___d471 = + coutF_rWrPtr_rsCounter_22_BIT_10_48_XOR_coutF__ETC___d470 ^ + coutF_rWrPtr_rsCounter[2] ; + assign coutF_rWrPtr_rsCounter_22_BIT_10_48_XOR_coutF__ETC___d473 = + coutF_rWrPtr_rsCounter_22_BIT_10_48_XOR_coutF__ETC___d471 ^ coutF_rWrPtr_rsCounter[1] ; - assign coutF_rWrPtr_rsCounter_24_BIT_10_50_XOR_coutF__ETC___d681 = - coutF_rWrPtr_rsCounter_24_BIT_10_50_XOR_coutF__ETC___d654 ^ - coutF_rWrPtr_rsCounter[8] ; - assign icapStatus__h26137 = { 29'd0, x__h26631 } ; - assign rdat__h26538 = hasDebugLogic ? dwWritten : 32'd0 ; - assign rdat__h26544 = hasDebugLogic ? dwRead : 32'd0 ; - assign rdat__h26550 = hasDebugLogic ? inCnt$dD_OUT : 32'd0 ; - assign rdat__h26556 = hasDebugLogic ? outCnt$dD_OUT : 32'd0 ; - assign x2__h22050 = - { coutF_rRdPtr_rsCounter_93_BIT_10_19_XOR_coutF__ETC___d662, - coutF_rRdPtr_rsCounter_93_BIT_10_19_XOR_coutF__ETC___d663, - coutF_rRdPtr_rsCounter_93_BIT_10_19_XOR_coutF__ETC___d664, - coutF_rRdPtr_rsCounter_93_BIT_10_19_XOR_coutF__ETC___d665, - coutF_rRdPtr_rsCounter_93_BIT_10_19_XOR_coutF__ETC___d680, - coutF_rRdPtr_rsCounter_93_BIT_10_19_XOR_coutF__ETC___d666, - coutF_rRdPtr_rsCounter_93_BIT_10_19_XOR_coutF__ETC___d667, - coutF_rRdPtr_rsCounter_93_BIT_10_19_XOR_coutF__ETC___d682, - coutF_rRdPtr_rsCounter_93_BIT_10_19_XOR_coutF__ETC___d668, - coutF_rRdPtr_rsCounter_93_BIT_10_19_XOR_coutF__ETC___d701 } ; - assign x3__h20817 = coutF_pwEnqueue$whas ? icap_coutF$D_OUT : 32'd0 ; - assign x__h16406 = + assign icapStatus__h26003 = { 29'd0, x__h26497 } ; + assign rdat__h26404 = hasDebugLogic ? dwWritten : 32'd0 ; + assign rdat__h26410 = hasDebugLogic ? dwRead : 32'd0 ; + assign rdat__h26416 = hasDebugLogic ? inCnt$dD_OUT : 32'd0 ; + assign rdat__h26422 = hasDebugLogic ? outCnt$dD_OUT : 32'd0 ; + assign wci_wslv_respF_cntr_r_8_MINUS_1___d27 = + wci_wslv_respF_cntr_r - 2'd1 ; + assign x2__h21916 = + { coutF_rRdPtr_rsCounter_91_BIT_10_17_XOR_coutF__ETC___d481, + coutF_rRdPtr_rsCounter_91_BIT_10_17_XOR_coutF__ETC___d482, + coutF_rRdPtr_rsCounter_91_BIT_10_17_XOR_coutF__ETC___d484, + coutF_rRdPtr_rsCounter_91_BIT_10_17_XOR_coutF__ETC___d485, + coutF_rRdPtr_rsCounter_91_BIT_10_17_XOR_coutF__ETC___d487, + coutF_rRdPtr_rsCounter_91_BIT_10_17_XOR_coutF__ETC___d488, + coutF_rRdPtr_rsCounter_91_BIT_10_17_XOR_coutF__ETC___d490, + coutF_rRdPtr_rsCounter_91_BIT_10_17_XOR_coutF__ETC___d491, + coutF_rRdPtr_rsCounter_91_BIT_10_17_XOR_coutF__ETC___d493, + coutF_rRdPtr_rsCounter_91_BIT_10_17_XOR_coutF__ETC___d494 } ; + assign x3__h20684 = coutF_pwEnqueue$whas ? icap_coutF$D_OUT : 32'd0 ; + assign x__h16273 = 11'd1 << - IF_coutF_rWrPtr_rsCounter_24_BIT_0_31_XOR_cout_ETC___d754 ; - assign x__h18708 = 11'd1 << x__h19564 ; - assign x__h19564 = - coutF_rRdPtr_rsCounter_93_BIT_0_00_XOR_coutF_r_ETC___d722 ? - IF_coutF_rRdPtr_rsCounter_93_BIT_0_00_OR_coutF_ETC___d756 : - 32'd0 ; - assign x__h22081 = x_sReadBin__h20518 + 11'd1 ; - assign x__h26631 = - { NOT_coutF_rRdPtr_rsCounter_93_EQ_coutF_rWrPtr__ETC___d601, + IF_coutF_rWrPtr_rsCounter_22_BIT_0_29_XOR_cout_ETC___d371 ; + assign x__h18575 = + 11'd1 << + IF_coutF_rRdPtr_rsCounter_91_BIT_0_98_XOR_cout_ETC___d440 ; + assign x__h21947 = x_sReadBin__h20385 + 11'd1 ; + assign x__h26497 = + { NOT_coutF_rRdPtr_rsCounter_91_EQ_coutF_rWrPtr__ETC___d599, icapCtrl[1:0] } ; - assign x_dReadBin__h20521 = + assign x_dReadBin__h20388 = { coutF_rRdPtr_rdCounter[10], - coutF_rRdPtr_rdCounter_24_BIT_10_25_XOR_coutF__ETC___d669, - coutF_rRdPtr_rdCounter_24_BIT_10_25_XOR_coutF__ETC___d670, - coutF_rRdPtr_rdCounter_24_BIT_10_25_XOR_coutF__ETC___d683, - coutF_rRdPtr_rdCounter_24_BIT_10_25_XOR_coutF__ETC___d671, - coutF_rRdPtr_rdCounter_24_BIT_10_25_XOR_coutF__ETC___d672, - coutF_rRdPtr_rdCounter_24_BIT_10_25_XOR_coutF__ETC___d678, - coutF_rRdPtr_rdCounter_24_BIT_10_25_XOR_coutF__ETC___d673, - coutF_rRdPtr_rdCounter_24_BIT_10_25_XOR_coutF__ETC___d674, - coutF_rRdPtr_rdCounter_24_BIT_10_25_XOR_coutF__ETC___d676, - coutF_rRdPtr_rdCounter_24_BIT_10_25_XOR_coutF__ETC___d676 ^ + coutF_rRdPtr_rdCounter_22_BIT_10_23_XOR_coutF__ETC___d525, + coutF_rRdPtr_rdCounter_22_BIT_10_23_XOR_coutF__ETC___d527, + coutF_rRdPtr_rdCounter_22_BIT_10_23_XOR_coutF__ETC___d530, + coutF_rRdPtr_rdCounter_22_BIT_10_23_XOR_coutF__ETC___d532, + coutF_rRdPtr_rdCounter_22_BIT_10_23_XOR_coutF__ETC___d535, + coutF_rRdPtr_rdCounter_22_BIT_10_23_XOR_coutF__ETC___d537, + coutF_rRdPtr_rdCounter_22_BIT_10_23_XOR_coutF__ETC___d540, + coutF_rRdPtr_rdCounter_22_BIT_10_23_XOR_coutF__ETC___d542, + coutF_rRdPtr_rdCounter_22_BIT_10_23_XOR_coutF__ETC___d545, + coutF_rRdPtr_rdCounter_22_BIT_10_23_XOR_coutF__ETC___d545 ^ coutF_rRdPtr_rdCounter[0] } ; - assign x_sReadBin__h20518 = + assign x_sReadBin__h20385 = { coutF_rRdPtr_rsCounter[10], - coutF_rRdPtr_rsCounter_93_BIT_10_19_XOR_coutF__ETC___d662, - coutF_rRdPtr_rsCounter_93_BIT_10_19_XOR_coutF__ETC___d663, - coutF_rRdPtr_rsCounter_93_BIT_10_19_XOR_coutF__ETC___d664, - coutF_rRdPtr_rsCounter_93_BIT_10_19_XOR_coutF__ETC___d665, - coutF_rRdPtr_rsCounter_93_BIT_10_19_XOR_coutF__ETC___d680, - coutF_rRdPtr_rsCounter_93_BIT_10_19_XOR_coutF__ETC___d666, - coutF_rRdPtr_rsCounter_93_BIT_10_19_XOR_coutF__ETC___d667, - coutF_rRdPtr_rsCounter_93_BIT_10_19_XOR_coutF__ETC___d682, - coutF_rRdPtr_rsCounter_93_BIT_10_19_XOR_coutF__ETC___d668, - coutF_rRdPtr_rsCounter_93_BIT_10_19_XOR_coutF__ETC___d701 } ; - assign y__h17293 = ~x__h16406 ; - assign y__h19595 = ~x__h18708 ; - assign z__h17337 = coutF_rWrPtr_rsCounter[0] ^ coutF_rWrPtr_rsCounter[1] ; - assign z__h17344 = z__h17337 ^ coutF_rWrPtr_rsCounter[2] ; - assign z__h17351 = z__h17344 ^ coutF_rWrPtr_rsCounter[3] ; - assign z__h17358 = z__h17351 ^ coutF_rWrPtr_rsCounter[4] ; - assign z__h17365 = z__h17358 ^ coutF_rWrPtr_rsCounter[5] ; - assign z__h17372 = z__h17365 ^ coutF_rWrPtr_rsCounter[6] ; - assign z__h17379 = z__h17372 ^ coutF_rWrPtr_rsCounter[7] ; - assign z__h17386 = z__h17379 ^ coutF_rWrPtr_rsCounter[8] ; - assign z__h17393 = z__h17386 ^ coutF_rWrPtr_rsCounter[9] ; - assign z__h19639 = coutF_rRdPtr_rsCounter[0] ^ coutF_rRdPtr_rsCounter[1] ; - assign z__h19646 = z__h19639 ^ coutF_rRdPtr_rsCounter[2] ; - assign z__h19653 = z__h19646 ^ coutF_rRdPtr_rsCounter[3] ; - assign z__h19660 = z__h19653 ^ coutF_rRdPtr_rsCounter[4] ; - assign z__h19667 = z__h19660 ^ coutF_rRdPtr_rsCounter[5] ; - assign z__h19674 = z__h19667 ^ coutF_rRdPtr_rsCounter[6] ; - assign z__h19681 = z__h19674 ^ coutF_rRdPtr_rsCounter[7] ; - assign z__h19688 = z__h19681 ^ coutF_rRdPtr_rsCounter[8] ; - assign z__h19695 = z__h19688 ^ coutF_rRdPtr_rsCounter[9] ; + coutF_rRdPtr_rsCounter_91_BIT_10_17_XOR_coutF__ETC___d481, + coutF_rRdPtr_rsCounter_91_BIT_10_17_XOR_coutF__ETC___d482, + coutF_rRdPtr_rsCounter_91_BIT_10_17_XOR_coutF__ETC___d484, + coutF_rRdPtr_rsCounter_91_BIT_10_17_XOR_coutF__ETC___d485, + coutF_rRdPtr_rsCounter_91_BIT_10_17_XOR_coutF__ETC___d487, + coutF_rRdPtr_rsCounter_91_BIT_10_17_XOR_coutF__ETC___d488, + coutF_rRdPtr_rsCounter_91_BIT_10_17_XOR_coutF__ETC___d490, + coutF_rRdPtr_rsCounter_91_BIT_10_17_XOR_coutF__ETC___d491, + coutF_rRdPtr_rsCounter_91_BIT_10_17_XOR_coutF__ETC___d493, + coutF_rRdPtr_rsCounter_91_BIT_10_17_XOR_coutF__ETC___d494 } ; + assign y__h17160 = ~x__h16273 ; + assign y__h19462 = ~x__h18575 ; + assign z__h17204 = coutF_rWrPtr_rsCounter[0] ^ coutF_rWrPtr_rsCounter[1] ; + assign z__h17211 = z__h17204 ^ coutF_rWrPtr_rsCounter[2] ; + assign z__h17218 = z__h17211 ^ coutF_rWrPtr_rsCounter[3] ; + assign z__h17225 = z__h17218 ^ coutF_rWrPtr_rsCounter[4] ; + assign z__h17232 = z__h17225 ^ coutF_rWrPtr_rsCounter[5] ; + assign z__h17239 = z__h17232 ^ coutF_rWrPtr_rsCounter[6] ; + assign z__h17246 = z__h17239 ^ coutF_rWrPtr_rsCounter[7] ; + assign z__h17253 = z__h17246 ^ coutF_rWrPtr_rsCounter[8] ; + assign z__h17260 = z__h17253 ^ coutF_rWrPtr_rsCounter[9] ; + assign z__h19506 = coutF_rRdPtr_rsCounter[0] ^ coutF_rRdPtr_rsCounter[1] ; + assign z__h19513 = z__h19506 ^ coutF_rRdPtr_rsCounter[2] ; + assign z__h19520 = z__h19513 ^ coutF_rRdPtr_rsCounter[3] ; + assign z__h19527 = z__h19520 ^ coutF_rRdPtr_rsCounter[4] ; + assign z__h19534 = z__h19527 ^ coutF_rRdPtr_rsCounter[5] ; + assign z__h19541 = z__h19534 ^ coutF_rRdPtr_rsCounter[6] ; + assign z__h19548 = z__h19541 ^ coutF_rRdPtr_rsCounter[7] ; + assign z__h19555 = z__h19548 ^ coutF_rRdPtr_rsCounter[8] ; + assign z__h19562 = z__h19555 ^ coutF_rRdPtr_rsCounter[9] ; always@(wci_wslv_reqF$D_OUT or - icapStatus__h26137 or + icapStatus__h26003 or icapCtrl or coutF_memory$DOB or - rdat__h26538 or rdat__h26544 or rdat__h26550 or rdat__h26556) + rdat__h26404 or rdat__h26410 or rdat__h26416 or rdat__h26422) begin case (wci_wslv_reqF$D_OUT[63:32]) - 32'h0: v__h26514 = icapStatus__h26137; - 32'h00000004: v__h26514 = icapCtrl; - 32'h0000000C: v__h26514 = coutF_memory$DOB; - 32'h00000040: v__h26514 = rdat__h26538; - 32'h00000044: v__h26514 = rdat__h26544; - 32'h00000048: v__h26514 = rdat__h26550; - 32'h0000004C: v__h26514 = rdat__h26556; - default: v__h26514 = 32'd0; + 32'h0: v__h26380 = icapStatus__h26003; + 32'h00000004: v__h26380 = icapCtrl; + 32'h0000000C: v__h26380 = coutF_memory$DOB; + 32'h00000040: v__h26380 = rdat__h26404; + 32'h00000044: v__h26380 = rdat__h26410; + 32'h00000048: v__h26380 = rdat__h26416; + 32'h0000004C: v__h26380 = rdat__h26422; + default: v__h26380 = 32'd0; endcase end @@ -1514,7 +1527,7 @@ module mkICAPWorker(wciS0_Clk, wci_wslv_illegalEdge <= `BSV_ASSIGNMENT_DELAY 1'd0; wci_wslv_nState <= `BSV_ASSIGNMENT_DELAY 3'd0; wci_wslv_reqF_countReg <= `BSV_ASSIGNMENT_DELAY 2'd0; - wci_wslv_respF_c_r <= `BSV_ASSIGNMENT_DELAY 2'd0; + wci_wslv_respF_cntr_r <= `BSV_ASSIGNMENT_DELAY 2'd0; wci_wslv_respF_q_0 <= `BSV_ASSIGNMENT_DELAY 34'h0AAAAAAAA; wci_wslv_respF_q_1 <= `BSV_ASSIGNMENT_DELAY 34'h0AAAAAAAA; wci_wslv_sFlagReg <= `BSV_ASSIGNMENT_DELAY 1'd0; @@ -1544,8 +1557,9 @@ module mkICAPWorker(wciS0_Clk, if (wci_wslv_reqF_countReg$EN) wci_wslv_reqF_countReg <= `BSV_ASSIGNMENT_DELAY wci_wslv_reqF_countReg$D_IN; - if (wci_wslv_respF_c_r$EN) - wci_wslv_respF_c_r <= `BSV_ASSIGNMENT_DELAY wci_wslv_respF_c_r$D_IN; + if (wci_wslv_respF_cntr_r$EN) + wci_wslv_respF_cntr_r <= `BSV_ASSIGNMENT_DELAY + wci_wslv_respF_cntr_r$D_IN; if (wci_wslv_respF_q_0$EN) wci_wslv_respF_q_0 <= `BSV_ASSIGNMENT_DELAY wci_wslv_respF_q_0$D_IN; if (wci_wslv_respF_q_1$EN) @@ -1669,7 +1683,7 @@ module mkICAPWorker(wciS0_Clk, wci_wslv_isReset_isInReset = 1'h0; wci_wslv_nState = 3'h2; wci_wslv_reqF_countReg = 2'h2; - wci_wslv_respF_c_r = 2'h2; + wci_wslv_respF_cntr_r = 2'h2; wci_wslv_respF_q_0 = 34'h2AAAAAAAA; wci_wslv_respF_q_1 = 34'h2AAAAAAAA; wci_wslv_sFlagReg = 1'h0; @@ -1687,24 +1701,24 @@ module mkICAPWorker(wciS0_Clk, if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_start) begin - v__h3695 = $time; + v__h3563 = $time; #0; end if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_start) $display("[%0d]: %m: WCI ControlOp: Starting-transition edge:%x from:%x", - v__h3695, + v__h3563, wci_wslv_reqF$D_OUT[36:34], wci_wslv_cState); if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_ctrl_IsO) begin - v__h26767 = $time; + v__h26628 = $time; #0; end if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_ctrl_IsO) - $display("[%0d]: %m: Starting ICAPWorker", v__h26767); + $display("[%0d]: %m: Starting ICAPWorker", v__h26628); if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_ctrl_IsO && WILL_FIRE_RL_wci_ctrl_OrE) $display("Error: \"bsv/wrk/ICAPWorker.bsv\", line 77, column 60: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_IsO] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n"); @@ -1717,25 +1731,25 @@ module mkICAPWorker(wciS0_Clk, if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge) begin - v__h4014 = $time; + v__h3882 = $time; #0; end if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge) $display("[%0d]: %m: WCI ControlOp: ILLEGAL-EDGE Completed-transition edge:%x from:%x", - v__h4014, + v__h3882, wci_wslv_cEdge, wci_wslv_cState); if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && !wci_wslv_illegalEdge) begin - v__h3870 = $time; + v__h3738 = $time; #0; end if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && !wci_wslv_illegalEdge) $display("[%0d]: %m: WCI ControlOp: Completed-transition edge:%x from:%x to:%x", - v__h3870, + v__h3738, wci_wslv_cEdge, wci_wslv_cState, wci_wslv_nState); diff --git a/rtl/mkMemiTestWorker.v b/rtl/mkMemiTestWorker.v index 12990a48..82167f8a 100644 --- a/rtl/mkMemiTestWorker.v +++ b/rtl/mkMemiTestWorker.v @@ -1,7 +1,7 @@ // -// Generated by Bluespec Compiler, version 2012.09.beta1 (build 29570, 2012-09.11) +// Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Tue Dec 11 16:21:03 EST 2012 +// On Fri Jun 21 16:57:50 EDT 2013 // // // Ports: @@ -345,10 +345,10 @@ module mkMemiTestWorker(wciS0_Clk, wire [1 : 0] wci_wslv_reqF_countReg$D_IN; wire wci_wslv_reqF_countReg$EN; - // register wci_wslv_respF_c_r - reg [1 : 0] wci_wslv_respF_c_r; - wire [1 : 0] wci_wslv_respF_c_r$D_IN; - wire wci_wslv_respF_c_r$EN; + // register wci_wslv_respF_cntr_r + reg [1 : 0] wci_wslv_respF_cntr_r; + wire [1 : 0] wci_wslv_respF_cntr_r$D_IN; + wire wci_wslv_respF_cntr_r$EN; // register wci_wslv_respF_q_0 reg [33 : 0] wci_wslv_respF_q_0; @@ -392,10 +392,10 @@ module mkMemiTestWorker(wciS0_Clk, reg wmemi_busyWithMessage; wire wmemi_busyWithMessage$D_IN, wmemi_busyWithMessage$EN; - // register wmemi_dhF_c_r - reg [1 : 0] wmemi_dhF_c_r; - wire [1 : 0] wmemi_dhF_c_r$D_IN; - wire wmemi_dhF_c_r$EN; + // register wmemi_dhF_cntr_r + reg [1 : 0] wmemi_dhF_cntr_r; + wire [1 : 0] wmemi_dhF_cntr_r$D_IN; + wire wmemi_dhF_cntr_r$EN; // register wmemi_dhF_q_0 reg [145 : 0] wmemi_dhF_q_0; @@ -423,10 +423,10 @@ module mkMemiTestWorker(wciS0_Clk, reg wmemi_peerIsReady; wire wmemi_peerIsReady$D_IN, wmemi_peerIsReady$EN; - // register wmemi_reqF_c_r - reg [1 : 0] wmemi_reqF_c_r; - wire [1 : 0] wmemi_reqF_c_r$D_IN; - wire wmemi_reqF_c_r$EN; + // register wmemi_reqF_cntr_r + reg [1 : 0] wmemi_reqF_cntr_r; + wire [1 : 0] wmemi_reqF_cntr_r$D_IN; + wire wmemi_reqF_cntr_r$EN; // register wmemi_reqF_q_0 reg [51 : 0] wmemi_reqF_q_0; @@ -513,7 +513,7 @@ module mkMemiTestWorker(wciS0_Clk, reg [33 : 0] MUX_wci_wslv_respF_q_0$write_1__VAL_2; wire [145 : 0] MUX_wmemi_dhF_q_0$write_1__VAL_1, MUX_wmemi_dhF_q_0$write_1__VAL_2, - MUX_wmemi_dhF_q_1$write_1__VAL_1; + MUX_wmemi_dhF_q_1$write_1__VAL_2; wire [51 : 0] MUX_wmemi_reqF_q_0$write_1__VAL_1, MUX_wmemi_reqF_q_0$write_1__VAL_2, MUX_wmemi_reqF_q_1$write_1__VAL_1, @@ -524,31 +524,46 @@ module mkMemiTestWorker(wciS0_Clk, MUX_wci_wslv_respF_x_wire$wset_1__VAL_1, MUX_wci_wslv_respF_x_wire$wset_1__VAL_2; wire [31 : 0] MUX_unrollCnt$write_1__VAL_2; - wire [1 : 0] MUX_wci_wslv_respF_c_r$write_1__VAL_1, - MUX_wci_wslv_respF_c_r$write_1__VAL_2, - MUX_wmemi_dhF_c_r$write_1__VAL_1, - MUX_wmemi_dhF_c_r$write_1__VAL_2, - MUX_wmemi_reqF_c_r$write_1__VAL_1, - MUX_wmemi_reqF_c_r$write_1__VAL_2; + wire [1 : 0] MUX_wci_wslv_respF_cntr_r$write_1__VAL_2, + MUX_wmemi_dhF_cntr_r$write_1__VAL_2, + MUX_wmemi_reqF_cntr_r$write_1__VAL_2; wire MUX_isReader$write_1__SEL_1, MUX_isReader$write_1__SEL_2, MUX_isTesting$write_1__SEL_1, MUX_unrollCnt$write_1__SEL_1, MUX_wci_wslv_illegalEdge$write_1__SEL_1, MUX_wci_wslv_illegalEdge$write_1__VAL_1, + MUX_wci_wslv_respF_q_0$write_1__SEL_1, MUX_wci_wslv_respF_q_0$write_1__SEL_2, + MUX_wci_wslv_respF_q_1$write_1__SEL_1, MUX_wci_wslv_respF_q_1$write_1__SEL_2, + MUX_wmemi_dhF_q_0$write_1__SEL_1, MUX_wmemi_dhF_q_0$write_1__SEL_2, + MUX_wmemi_dhF_q_1$write_1__SEL_1, MUX_wmemi_dhF_q_1$write_1__SEL_2, + MUX_wmemi_reqF_q_0$write_1__SEL_1, MUX_wmemi_reqF_q_0$write_1__SEL_2, + MUX_wmemi_reqF_q_1$write_1__SEL_1, MUX_wmemi_reqF_q_1$write_1__SEL_2; // remaining internal signals - reg [63 : 0] v__h14490, v__h15261, v__h3700, v__h3875, v__h4019; - reg [31 : 0] g_data__h15071; - wire [35 : 0] addr__h13927; - wire [31 : 0] rdat__h15093, testStatus__h14567; - wire NOT_rgen_gsF_first__13_EQ_wmemi_respF_first__1_ETC___d317; + reg [63 : 0] v__h14155, v__h14921, v__h3568, v__h3743, v__h3887; + reg [31 : 0] g_data__h14736; + wire [35 : 0] addr__h13592; + wire [31 : 0] rdat__h14758, testStatus__h14232; + wire [1 : 0] wci_wslv_respF_cntr_r_8_MINUS_1___d27, + wmemi_dhF_cntr_r_84_MINUS_1___d193, + wmemi_reqF_cntr_r_61_MINUS_1___d170; + wire NOT_rgen_gsF_first__07_EQ_wmemi_respF_first__0_ETC___d311, + NOT_wmemi_dhF_cntr_r_84_EQ_2_97_98_AND_wmemi_o_ETC___d264, + _dfoo1, + _dfoo11, + _dfoo3, + _dfoo5, + _dfoo7, + _dfoo9, + wci_wslv_cState_4_EQ_2_5_AND_isTesting_66_67_A_ETC___d272, + wci_wslv_cState_4_EQ_2_5_AND_isTesting_66_67_A_ETC___d294; // value method wciS0_sResp assign wciS0_SResp = wci_wslv_respF_q_0[33:32] ; @@ -639,29 +654,22 @@ module mkMemiTestWorker(wciS0_Clk, // rule RL_wci_cfrd assign WILL_FIRE_RL_wci_cfrd = - wci_wslv_respF_c_r != 2'd2 && wci_wslv_reqF$EMPTY_N && + wci_wslv_respF_cntr_r != 2'd2 && wci_wslv_reqF$EMPTY_N && wci_wslv_wci_cfrd_pw$whas && !WILL_FIRE_RL_wci_wslv_ctl_op_start && !WILL_FIRE_RL_wci_wslv_ctl_op_complete ; // rule RL_write_req assign WILL_FIRE_RL_write_req = - wmemi_reqF_c_r != 2'd2 && wmemi_dhF_c_r != 2'd2 && - wmemi_operateD && - wmemi_peerIsReady && - wgen_gsF$EMPTY_N && - wci_wslv_cState == 3'd2 && - isTesting && - isWriter && - !isReader ; + wmemi_reqF_cntr_r != 2'd2 && + NOT_wmemi_dhF_cntr_r_84_EQ_2_97_98_AND_wmemi_o_ETC___d264 && + wci_wslv_cState_4_EQ_2_5_AND_isTesting_66_67_A_ETC___d272 ; // rule RL_read_req assign WILL_FIRE_RL_read_req = - wmemi_reqF_c_r != 2'd2 && wmemi_operateD && wmemi_peerIsReady && - wci_wslv_cState == 3'd2 && - isTesting && - !isWriter && - isReader ; + wmemi_reqF_cntr_r != 2'd2 && wmemi_operateD && + wmemi_peerIsReady && + wci_wslv_cState_4_EQ_2_5_AND_isTesting_66_67_A_ETC___d294 ; // rule RL_read_resp assign WILL_FIRE_RL_read_resp = @@ -671,7 +679,7 @@ module mkMemiTestWorker(wciS0_Clk, // rule RL_wci_cfwr assign WILL_FIRE_RL_wci_cfwr = - wci_wslv_respF_c_r != 2'd2 && wci_wslv_reqF$EMPTY_N && + wci_wslv_respF_cntr_r != 2'd2 && wci_wslv_reqF$EMPTY_N && wci_wslv_wci_cfwr_pw$whas && !WILL_FIRE_RL_wci_wslv_ctl_op_start && !WILL_FIRE_RL_wci_wslv_ctl_op_complete ; @@ -704,35 +712,27 @@ module mkMemiTestWorker(wciS0_Clk, // rule RL_wci_wslv_ctl_op_complete assign WILL_FIRE_RL_wci_wslv_ctl_op_complete = - wci_wslv_respF_c_r != 2'd2 && wci_wslv_ctlOpActive && + wci_wslv_respF_cntr_r != 2'd2 && wci_wslv_ctlOpActive && wci_wslv_ctlAckReg ; // rule RL_wci_wslv_respF_incCtr assign WILL_FIRE_RL_wci_wslv_respF_incCtr = - ((wci_wslv_respF_c_r == 2'd0) ? - wci_wslv_respF_x_wire$whas : - wci_wslv_respF_c_r != 2'd1 || wci_wslv_respF_x_wire$whas) && - wci_wslv_respF_enqueueing$whas && - !(wci_wslv_respF_c_r != 2'd0) ; + wci_wslv_respF_x_wire$whas && wci_wslv_respF_enqueueing$whas && + !(wci_wslv_respF_cntr_r != 2'd0) ; // rule RL_wci_wslv_respF_decCtr assign WILL_FIRE_RL_wci_wslv_respF_decCtr = - wci_wslv_respF_c_r != 2'd0 && !wci_wslv_respF_enqueueing$whas ; + wci_wslv_respF_cntr_r != 2'd0 && + !wci_wslv_respF_enqueueing$whas ; // rule RL_wci_wslv_respF_both assign WILL_FIRE_RL_wci_wslv_respF_both = - ((wci_wslv_respF_c_r == 2'd1) ? - wci_wslv_respF_x_wire$whas : - wci_wslv_respF_c_r != 2'd2 || wci_wslv_respF_x_wire$whas) && - wci_wslv_respF_c_r != 2'd0 && + wci_wslv_respF_x_wire$whas && wci_wslv_respF_cntr_r != 2'd0 && wci_wslv_respF_enqueueing$whas ; // rule RL_wmemi_reqF_incCtr assign WILL_FIRE_RL_wmemi_reqF_incCtr = - ((wmemi_reqF_c_r == 2'd0) ? - wmemi_reqF_x_wire$whas : - wmemi_reqF_c_r != 2'd1 || wmemi_reqF_x_wire$whas) && - wmemi_reqF_enqueueing$whas && + wmemi_reqF_x_wire$whas && wmemi_reqF_enqueueing$whas && !wmemi_reqF_dequeueing$whas ; // rule RL_wmemi_reqF_decCtr @@ -741,18 +741,12 @@ module mkMemiTestWorker(wciS0_Clk, // rule RL_wmemi_reqF_both assign WILL_FIRE_RL_wmemi_reqF_both = - ((wmemi_reqF_c_r == 2'd1) ? - wmemi_reqF_x_wire$whas : - wmemi_reqF_c_r != 2'd2 || wmemi_reqF_x_wire$whas) && - wmemi_reqF_dequeueing$whas && + wmemi_reqF_x_wire$whas && wmemi_reqF_dequeueing$whas && wmemi_reqF_enqueueing$whas ; // rule RL_wmemi_dhF_incCtr assign WILL_FIRE_RL_wmemi_dhF_incCtr = - ((wmemi_dhF_c_r == 2'd0) ? - WILL_FIRE_RL_write_req : - wmemi_dhF_c_r != 2'd1 || WILL_FIRE_RL_write_req) && - WILL_FIRE_RL_write_req && + WILL_FIRE_RL_write_req && WILL_FIRE_RL_write_req && !wmemi_dhF_dequeueing$whas ; // rule RL_wmemi_dhF_decCtr @@ -761,10 +755,7 @@ module mkMemiTestWorker(wciS0_Clk, // rule RL_wmemi_dhF_both assign WILL_FIRE_RL_wmemi_dhF_both = - ((wmemi_dhF_c_r == 2'd1) ? - WILL_FIRE_RL_write_req : - wmemi_dhF_c_r != 2'd2 || WILL_FIRE_RL_write_req) && - wmemi_dhF_dequeueing$whas && + WILL_FIRE_RL_write_req && wmemi_dhF_dequeueing$whas && WILL_FIRE_RL_write_req ; // inputs to muxes for submodule ports @@ -792,30 +783,42 @@ module mkMemiTestWorker(wciS0_Clk, wci_wslv_reqF$D_OUT[36:34] == 3'd5 || wci_wslv_reqF$D_OUT[36:34] == 3'd6 || wci_wslv_reqF$D_OUT[36:34] == 3'd7) ; + assign MUX_wci_wslv_respF_q_0$write_1__SEL_1 = + WILL_FIRE_RL_wci_wslv_respF_both && _dfoo3 ; assign MUX_wci_wslv_respF_q_0$write_1__SEL_2 = WILL_FIRE_RL_wci_wslv_respF_incCtr && - wci_wslv_respF_c_r == 2'd0 ; + wci_wslv_respF_cntr_r == 2'd0 ; + assign MUX_wci_wslv_respF_q_1$write_1__SEL_1 = + WILL_FIRE_RL_wci_wslv_respF_both && _dfoo1 ; assign MUX_wci_wslv_respF_q_1$write_1__SEL_2 = WILL_FIRE_RL_wci_wslv_respF_incCtr && - wci_wslv_respF_c_r == 2'd1 ; + wci_wslv_respF_cntr_r == 2'd1 ; + assign MUX_wmemi_dhF_q_0$write_1__SEL_1 = + WILL_FIRE_RL_wmemi_dhF_incCtr && wmemi_dhF_cntr_r == 2'd0 ; assign MUX_wmemi_dhF_q_0$write_1__SEL_2 = - WILL_FIRE_RL_wmemi_dhF_incCtr && wmemi_dhF_c_r == 2'd0 ; + WILL_FIRE_RL_wmemi_dhF_both && _dfoo11 ; + assign MUX_wmemi_dhF_q_1$write_1__SEL_1 = + WILL_FIRE_RL_wmemi_dhF_incCtr && wmemi_dhF_cntr_r == 2'd1 ; assign MUX_wmemi_dhF_q_1$write_1__SEL_2 = - WILL_FIRE_RL_wmemi_dhF_incCtr && wmemi_dhF_c_r == 2'd1 ; + WILL_FIRE_RL_wmemi_dhF_both && _dfoo9 ; + assign MUX_wmemi_reqF_q_0$write_1__SEL_1 = + WILL_FIRE_RL_wmemi_reqF_both && _dfoo7 ; assign MUX_wmemi_reqF_q_0$write_1__SEL_2 = - WILL_FIRE_RL_wmemi_reqF_incCtr && wmemi_reqF_c_r == 2'd0 ; + WILL_FIRE_RL_wmemi_reqF_incCtr && wmemi_reqF_cntr_r == 2'd0 ; + assign MUX_wmemi_reqF_q_1$write_1__SEL_1 = + WILL_FIRE_RL_wmemi_reqF_both && _dfoo5 ; assign MUX_wmemi_reqF_q_1$write_1__SEL_2 = - WILL_FIRE_RL_wmemi_reqF_incCtr && wmemi_reqF_c_r == 2'd1 ; + WILL_FIRE_RL_wmemi_reqF_incCtr && wmemi_reqF_cntr_r == 2'd1 ; assign MUX_unrollCnt$write_1__VAL_2 = (unrollCnt == 32'd1) ? seqLen : unrollCnt - 32'd1 ; assign MUX_wci_wslv_illegalEdge$write_1__VAL_1 = wci_wslv_reqF$D_OUT[36:34] != 3'd4 && wci_wslv_reqF$D_OUT[36:34] != 3'd5 && wci_wslv_reqF$D_OUT[36:34] != 3'd6 ; - assign MUX_wci_wslv_respF_c_r$write_1__VAL_1 = wci_wslv_respF_c_r + 2'd1 ; - assign MUX_wci_wslv_respF_c_r$write_1__VAL_2 = wci_wslv_respF_c_r - 2'd1 ; + assign MUX_wci_wslv_respF_cntr_r$write_1__VAL_2 = + wci_wslv_respF_cntr_r + 2'd1 ; assign MUX_wci_wslv_respF_q_0$write_1__VAL_1 = - (wci_wslv_respF_c_r == 2'd1) ? + (wci_wslv_respF_cntr_r == 2'd1) ? MUX_wci_wslv_respF_q_0$write_1__VAL_2 : wci_wslv_respF_q_1 ; always@(WILL_FIRE_RL_wci_wslv_ctl_op_complete or @@ -837,28 +840,26 @@ module mkMemiTestWorker(wciS0_Clk, endcase end assign MUX_wci_wslv_respF_q_1$write_1__VAL_1 = - (wci_wslv_respF_c_r == 2'd2) ? + (wci_wslv_respF_cntr_r == 2'd2) ? MUX_wci_wslv_respF_q_0$write_1__VAL_2 : 34'h0AAAAAAAA ; assign MUX_wci_wslv_respF_x_wire$wset_1__VAL_1 = wci_wslv_illegalEdge ? 34'h3C0DE4202 : 34'h1C0DE4201 ; - assign MUX_wci_wslv_respF_x_wire$wset_1__VAL_2 = { 2'd1, g_data__h15071 } ; - assign MUX_wmemi_dhF_c_r$write_1__VAL_1 = wmemi_dhF_c_r + 2'd1 ; - assign MUX_wmemi_dhF_c_r$write_1__VAL_2 = wmemi_dhF_c_r - 2'd1 ; + assign MUX_wci_wslv_respF_x_wire$wset_1__VAL_2 = { 2'd1, g_data__h14736 } ; + assign MUX_wmemi_dhF_cntr_r$write_1__VAL_2 = wmemi_dhF_cntr_r + 2'd1 ; assign MUX_wmemi_dhF_q_0$write_1__VAL_1 = - (wmemi_dhF_c_r == 2'd1) ? - MUX_wmemi_dhF_q_0$write_1__VAL_2 : - wmemi_dhF_q_1 ; - assign MUX_wmemi_dhF_q_0$write_1__VAL_2 = { 2'd3, wgen_gsF$D_OUT, 16'd65535 } ; - assign MUX_wmemi_dhF_q_1$write_1__VAL_1 = - (wmemi_dhF_c_r == 2'd2) ? - MUX_wmemi_dhF_q_0$write_1__VAL_2 : + assign MUX_wmemi_dhF_q_0$write_1__VAL_2 = + (wmemi_dhF_cntr_r == 2'd1) ? + MUX_wmemi_dhF_q_0$write_1__VAL_1 : + wmemi_dhF_q_1 ; + assign MUX_wmemi_dhF_q_1$write_1__VAL_2 = + (wmemi_dhF_cntr_r == 2'd2) ? + MUX_wmemi_dhF_q_0$write_1__VAL_1 : 146'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA ; - assign MUX_wmemi_reqF_c_r$write_1__VAL_1 = wmemi_reqF_c_r + 2'd1 ; - assign MUX_wmemi_reqF_c_r$write_1__VAL_2 = wmemi_reqF_c_r - 2'd1 ; + assign MUX_wmemi_reqF_cntr_r$write_1__VAL_2 = wmemi_reqF_cntr_r + 2'd1 ; assign MUX_wmemi_reqF_q_0$write_1__VAL_1 = - (wmemi_reqF_c_r == 2'd1) ? + (wmemi_reqF_cntr_r == 2'd1) ? MUX_wmemi_reqF_q_0$write_1__VAL_2 : wmemi_reqF_q_1 ; assign MUX_wmemi_reqF_q_0$write_1__VAL_2 = @@ -866,11 +867,11 @@ module mkMemiTestWorker(wciS0_Clk, MUX_wmemi_reqF_x_wire$wset_1__VAL_1 : MUX_wmemi_reqF_x_wire$wset_1__VAL_2 ; assign MUX_wmemi_reqF_q_1$write_1__VAL_1 = - (wmemi_reqF_c_r == 2'd2) ? + (wmemi_reqF_cntr_r == 2'd2) ? MUX_wmemi_reqF_q_0$write_1__VAL_2 : 52'h0AAAAAAAAAAAA ; - assign MUX_wmemi_reqF_x_wire$wset_1__VAL_1 = { 4'd3, addr__h13927, 12'd1 } ; - assign MUX_wmemi_reqF_x_wire$wset_1__VAL_2 = { 4'd5, addr__h13927, 12'd1 } ; + assign MUX_wmemi_reqF_x_wire$wset_1__VAL_1 = { 4'd3, addr__h13592, 12'd1 } ; + assign MUX_wmemi_reqF_x_wire$wset_1__VAL_2 = { 4'd5, addr__h13592, 12'd1 } ; // inlined wires assign wci_wslv_wciReq$wget = @@ -905,7 +906,7 @@ module mkMemiTestWorker(wciS0_Clk, assign wmemi_reqF_x_wire$wget = MUX_wmemi_reqF_q_0$write_1__VAL_2 ; assign wmemi_reqF_x_wire$whas = WILL_FIRE_RL_write_req || WILL_FIRE_RL_read_req ; - assign wmemi_dhF_x_wire$wget = MUX_wmemi_dhF_q_0$write_1__VAL_2 ; + assign wmemi_dhF_x_wire$wget = MUX_wmemi_dhF_q_0$write_1__VAL_1 ; assign wmemi_dhF_x_wire$whas = WILL_FIRE_RL_write_req ; assign wmemi_wmemiResponse$wget = { wmemiM0_SResp, wmemiM0_SRespLast, wmemiM0_SData } ; @@ -930,7 +931,7 @@ module mkMemiTestWorker(wciS0_Clk, assign wci_wslv_respF_enqueueing$whas = WILL_FIRE_RL_wci_cfrd || WILL_FIRE_RL_wci_cfwr || WILL_FIRE_RL_wci_wslv_ctl_op_complete ; - assign wci_wslv_respF_dequeueing$whas = wci_wslv_respF_c_r != 2'd0 ; + assign wci_wslv_respF_dequeueing$whas = wci_wslv_respF_cntr_r != 2'd0 ; assign wci_wslv_sThreadBusy_pw$whas = 1'b0 ; assign wci_wslv_wci_cfwr_pw$whas = wci_wslv_reqF$EMPTY_N && wci_wslv_reqF$D_OUT[68] && @@ -944,17 +945,17 @@ module mkMemiTestWorker(wciS0_Clk, assign wmemi_reqF_enqueueing$whas = WILL_FIRE_RL_read_req || WILL_FIRE_RL_write_req ; assign wmemi_reqF_dequeueing$whas = - wmemiM0_SCmdAccept && wmemi_reqF_c_r != 2'd0 ; + wmemiM0_SCmdAccept && wmemi_reqF_cntr_r != 2'd0 ; assign wmemi_dhF_enqueueing$whas = WILL_FIRE_RL_write_req ; assign wmemi_dhF_dequeueing$whas = - wmemiM0_SDataAccept && wmemi_dhF_c_r != 2'd0 ; + wmemiM0_SDataAccept && wmemi_dhF_cntr_r != 2'd0 ; assign wmemi_Em_sRespLast_w$whas = wmemiM0_SRespLast ; // register errorCount assign errorCount$D_IN = errorCount + 32'd1 ; assign errorCount$EN = WILL_FIRE_RL_read_resp && - NOT_rgen_gsF_first__13_EQ_wmemi_respF_first__1_ETC___d317 ; + NOT_rgen_gsF_first__07_EQ_wmemi_respF_first__0_ETC___d311 ; // register freeCnt assign freeCnt$D_IN = freeCnt + 32'd1 ; @@ -976,7 +977,7 @@ module mkMemiTestWorker(wciS0_Clk, wci_wslv_reqF$D_OUT[63:32] == 32'h00000030 ; assign isTesting$EN = WILL_FIRE_RL_read_resp && - NOT_rgen_gsF_first__13_EQ_wmemi_respF_first__1_ETC___d317 && + NOT_rgen_gsF_first__07_EQ_wmemi_respF_first__0_ETC___d311 && tstCtrl[0] || WILL_FIRE_RL_wci_cfwr && (wci_wslv_reqF$D_OUT[63:32] == 32'h00000030 || @@ -1100,24 +1101,24 @@ module mkMemiTestWorker(wciS0_Clk, (wci_wslv_wciReq$wget[71:69] != 3'd0) != wci_wslv_reqF_r_deq$whas ; - // register wci_wslv_respF_c_r - assign wci_wslv_respF_c_r$D_IN = - WILL_FIRE_RL_wci_wslv_respF_incCtr ? - MUX_wci_wslv_respF_c_r$write_1__VAL_1 : - MUX_wci_wslv_respF_c_r$write_1__VAL_2 ; - assign wci_wslv_respF_c_r$EN = - WILL_FIRE_RL_wci_wslv_respF_incCtr || - WILL_FIRE_RL_wci_wslv_respF_decCtr ; + // register wci_wslv_respF_cntr_r + assign wci_wslv_respF_cntr_r$D_IN = + WILL_FIRE_RL_wci_wslv_respF_decCtr ? + wci_wslv_respF_cntr_r_8_MINUS_1___d27 : + MUX_wci_wslv_respF_cntr_r$write_1__VAL_2 ; + assign wci_wslv_respF_cntr_r$EN = + WILL_FIRE_RL_wci_wslv_respF_decCtr || + WILL_FIRE_RL_wci_wslv_respF_incCtr ; // register wci_wslv_respF_q_0 - always@(WILL_FIRE_RL_wci_wslv_respF_both or + always@(MUX_wci_wslv_respF_q_0$write_1__SEL_1 or MUX_wci_wslv_respF_q_0$write_1__VAL_1 or MUX_wci_wslv_respF_q_0$write_1__SEL_2 or MUX_wci_wslv_respF_q_0$write_1__VAL_2 or WILL_FIRE_RL_wci_wslv_respF_decCtr or wci_wslv_respF_q_1) begin case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_wci_wslv_respF_both: + MUX_wci_wslv_respF_q_0$write_1__SEL_1: wci_wslv_respF_q_0$D_IN = MUX_wci_wslv_respF_q_0$write_1__VAL_1; MUX_wci_wslv_respF_q_0$write_1__SEL_2: wci_wslv_respF_q_0$D_IN = MUX_wci_wslv_respF_q_0$write_1__VAL_2; @@ -1128,20 +1129,20 @@ module mkMemiTestWorker(wciS0_Clk, endcase end assign wci_wslv_respF_q_0$EN = - WILL_FIRE_RL_wci_wslv_respF_both || + WILL_FIRE_RL_wci_wslv_respF_both && _dfoo3 || WILL_FIRE_RL_wci_wslv_respF_incCtr && - wci_wslv_respF_c_r == 2'd0 || + wci_wslv_respF_cntr_r == 2'd0 || WILL_FIRE_RL_wci_wslv_respF_decCtr ; // register wci_wslv_respF_q_1 - always@(WILL_FIRE_RL_wci_wslv_respF_both or + always@(MUX_wci_wslv_respF_q_1$write_1__SEL_1 or MUX_wci_wslv_respF_q_1$write_1__VAL_1 or MUX_wci_wslv_respF_q_1$write_1__SEL_2 or MUX_wci_wslv_respF_q_0$write_1__VAL_2 or WILL_FIRE_RL_wci_wslv_respF_decCtr) begin case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_wci_wslv_respF_both: + MUX_wci_wslv_respF_q_1$write_1__SEL_1: wci_wslv_respF_q_1$D_IN = MUX_wci_wslv_respF_q_1$write_1__VAL_1; MUX_wci_wslv_respF_q_1$write_1__SEL_2: wci_wslv_respF_q_1$D_IN = MUX_wci_wslv_respF_q_0$write_1__VAL_2; @@ -1152,9 +1153,9 @@ module mkMemiTestWorker(wciS0_Clk, endcase end assign wci_wslv_respF_q_1$EN = - WILL_FIRE_RL_wci_wslv_respF_both || + WILL_FIRE_RL_wci_wslv_respF_both && _dfoo1 || WILL_FIRE_RL_wci_wslv_respF_incCtr && - wci_wslv_respF_c_r == 2'd1 || + wci_wslv_respF_cntr_r == 2'd1 || WILL_FIRE_RL_wci_wslv_respF_decCtr ; // register wci_wslv_sFlagReg @@ -1175,37 +1176,46 @@ module mkMemiTestWorker(wciS0_Clk, // register wmemiRdReq assign wmemiRdReq$D_IN = wmemiRdReq + 32'd1 ; - assign wmemiRdReq$EN = WILL_FIRE_RL_read_req ; + assign wmemiRdReq$EN = + wmemi_reqF_cntr_r != 2'd2 && wmemi_operateD && + wmemi_peerIsReady && + wci_wslv_cState_4_EQ_2_5_AND_isTesting_66_67_A_ETC___d294 ; // register wmemiRdResp assign wmemiRdResp$D_IN = wmemiRdResp + 32'd1 ; - assign wmemiRdResp$EN = WILL_FIRE_RL_read_resp ; + assign wmemiRdResp$EN = + rgen_gsF$EMPTY_N && wmemi_respF$EMPTY_N && + wci_wslv_cState == 3'd2 && + isTesting ; // register wmemiWrReq assign wmemiWrReq$D_IN = wmemiWrReq + 32'd1 ; - assign wmemiWrReq$EN = WILL_FIRE_RL_write_req ; + assign wmemiWrReq$EN = + wmemi_reqF_cntr_r != 2'd2 && + NOT_wmemi_dhF_cntr_r_84_EQ_2_97_98_AND_wmemi_o_ETC___d264 && + wci_wslv_cState_4_EQ_2_5_AND_isTesting_66_67_A_ETC___d272 ; // register wmemi_busyWithMessage assign wmemi_busyWithMessage$D_IN = 1'b0 ; assign wmemi_busyWithMessage$EN = 1'b0 ; - // register wmemi_dhF_c_r - assign wmemi_dhF_c_r$D_IN = - WILL_FIRE_RL_wmemi_dhF_incCtr ? - MUX_wmemi_dhF_c_r$write_1__VAL_1 : - MUX_wmemi_dhF_c_r$write_1__VAL_2 ; - assign wmemi_dhF_c_r$EN = - WILL_FIRE_RL_wmemi_dhF_incCtr || WILL_FIRE_RL_wmemi_dhF_decCtr ; + // register wmemi_dhF_cntr_r + assign wmemi_dhF_cntr_r$D_IN = + WILL_FIRE_RL_wmemi_dhF_decCtr ? + wmemi_dhF_cntr_r_84_MINUS_1___d193 : + MUX_wmemi_dhF_cntr_r$write_1__VAL_2 ; + assign wmemi_dhF_cntr_r$EN = + WILL_FIRE_RL_wmemi_dhF_decCtr || WILL_FIRE_RL_wmemi_dhF_incCtr ; // register wmemi_dhF_q_0 - always@(WILL_FIRE_RL_wmemi_dhF_both or + always@(MUX_wmemi_dhF_q_0$write_1__SEL_1 or MUX_wmemi_dhF_q_0$write_1__VAL_1 or MUX_wmemi_dhF_q_0$write_1__SEL_2 or MUX_wmemi_dhF_q_0$write_1__VAL_2 or WILL_FIRE_RL_wmemi_dhF_decCtr or wmemi_dhF_q_1) begin case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_wmemi_dhF_both: + MUX_wmemi_dhF_q_0$write_1__SEL_1: wmemi_dhF_q_0$D_IN = MUX_wmemi_dhF_q_0$write_1__VAL_1; MUX_wmemi_dhF_q_0$write_1__SEL_2: wmemi_dhF_q_0$D_IN = MUX_wmemi_dhF_q_0$write_1__VAL_2; @@ -1215,21 +1225,21 @@ module mkMemiTestWorker(wciS0_Clk, endcase end assign wmemi_dhF_q_0$EN = - WILL_FIRE_RL_wmemi_dhF_both || - WILL_FIRE_RL_wmemi_dhF_incCtr && wmemi_dhF_c_r == 2'd0 || + WILL_FIRE_RL_wmemi_dhF_incCtr && wmemi_dhF_cntr_r == 2'd0 || + WILL_FIRE_RL_wmemi_dhF_both && _dfoo11 || WILL_FIRE_RL_wmemi_dhF_decCtr ; // register wmemi_dhF_q_1 - always@(WILL_FIRE_RL_wmemi_dhF_both or - MUX_wmemi_dhF_q_1$write_1__VAL_1 or + always@(MUX_wmemi_dhF_q_1$write_1__SEL_1 or + MUX_wmemi_dhF_q_0$write_1__VAL_1 or MUX_wmemi_dhF_q_1$write_1__SEL_2 or - MUX_wmemi_dhF_q_0$write_1__VAL_2 or WILL_FIRE_RL_wmemi_dhF_decCtr) + MUX_wmemi_dhF_q_1$write_1__VAL_2 or WILL_FIRE_RL_wmemi_dhF_decCtr) begin case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_wmemi_dhF_both: - wmemi_dhF_q_1$D_IN = MUX_wmemi_dhF_q_1$write_1__VAL_1; + MUX_wmemi_dhF_q_1$write_1__SEL_1: + wmemi_dhF_q_1$D_IN = MUX_wmemi_dhF_q_0$write_1__VAL_1; MUX_wmemi_dhF_q_1$write_1__SEL_2: - wmemi_dhF_q_1$D_IN = MUX_wmemi_dhF_q_0$write_1__VAL_2; + wmemi_dhF_q_1$D_IN = MUX_wmemi_dhF_q_1$write_1__VAL_2; WILL_FIRE_RL_wmemi_dhF_decCtr: wmemi_dhF_q_1$D_IN = 146'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; default: wmemi_dhF_q_1$D_IN = @@ -1237,8 +1247,8 @@ module mkMemiTestWorker(wciS0_Clk, endcase end assign wmemi_dhF_q_1$EN = - WILL_FIRE_RL_wmemi_dhF_both || - WILL_FIRE_RL_wmemi_dhF_incCtr && wmemi_dhF_c_r == 2'd1 || + WILL_FIRE_RL_wmemi_dhF_incCtr && wmemi_dhF_cntr_r == 2'd1 || + WILL_FIRE_RL_wmemi_dhF_both && _dfoo9 || WILL_FIRE_RL_wmemi_dhF_decCtr ; // register wmemi_errorSticky @@ -1257,24 +1267,24 @@ module mkMemiTestWorker(wciS0_Clk, assign wmemi_peerIsReady$D_IN = 1'b1 ; assign wmemi_peerIsReady$EN = 1'd1 ; - // register wmemi_reqF_c_r - assign wmemi_reqF_c_r$D_IN = - WILL_FIRE_RL_wmemi_reqF_incCtr ? - MUX_wmemi_reqF_c_r$write_1__VAL_1 : - MUX_wmemi_reqF_c_r$write_1__VAL_2 ; - assign wmemi_reqF_c_r$EN = - WILL_FIRE_RL_wmemi_reqF_incCtr || - WILL_FIRE_RL_wmemi_reqF_decCtr ; + // register wmemi_reqF_cntr_r + assign wmemi_reqF_cntr_r$D_IN = + WILL_FIRE_RL_wmemi_reqF_decCtr ? + wmemi_reqF_cntr_r_61_MINUS_1___d170 : + MUX_wmemi_reqF_cntr_r$write_1__VAL_2 ; + assign wmemi_reqF_cntr_r$EN = + WILL_FIRE_RL_wmemi_reqF_decCtr || + WILL_FIRE_RL_wmemi_reqF_incCtr ; // register wmemi_reqF_q_0 - always@(WILL_FIRE_RL_wmemi_reqF_both or + always@(MUX_wmemi_reqF_q_0$write_1__SEL_1 or MUX_wmemi_reqF_q_0$write_1__VAL_1 or MUX_wmemi_reqF_q_0$write_1__SEL_2 or MUX_wmemi_reqF_q_0$write_1__VAL_2 or WILL_FIRE_RL_wmemi_reqF_decCtr or wmemi_reqF_q_1) begin case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_wmemi_reqF_both: + MUX_wmemi_reqF_q_0$write_1__SEL_1: wmemi_reqF_q_0$D_IN = MUX_wmemi_reqF_q_0$write_1__VAL_1; MUX_wmemi_reqF_q_0$write_1__SEL_2: wmemi_reqF_q_0$D_IN = MUX_wmemi_reqF_q_0$write_1__VAL_2; @@ -1284,18 +1294,18 @@ module mkMemiTestWorker(wciS0_Clk, endcase end assign wmemi_reqF_q_0$EN = - WILL_FIRE_RL_wmemi_reqF_both || - WILL_FIRE_RL_wmemi_reqF_incCtr && wmemi_reqF_c_r == 2'd0 || + WILL_FIRE_RL_wmemi_reqF_both && _dfoo7 || + WILL_FIRE_RL_wmemi_reqF_incCtr && wmemi_reqF_cntr_r == 2'd0 || WILL_FIRE_RL_wmemi_reqF_decCtr ; // register wmemi_reqF_q_1 - always@(WILL_FIRE_RL_wmemi_reqF_both or + always@(MUX_wmemi_reqF_q_1$write_1__SEL_1 or MUX_wmemi_reqF_q_1$write_1__VAL_1 or MUX_wmemi_reqF_q_1$write_1__SEL_2 or MUX_wmemi_reqF_q_0$write_1__VAL_2 or WILL_FIRE_RL_wmemi_reqF_decCtr) begin case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_wmemi_reqF_both: + MUX_wmemi_reqF_q_1$write_1__SEL_1: wmemi_reqF_q_1$D_IN = MUX_wmemi_reqF_q_1$write_1__VAL_1; MUX_wmemi_reqF_q_1$write_1__SEL_2: wmemi_reqF_q_1$D_IN = MUX_wmemi_reqF_q_0$write_1__VAL_2; @@ -1305,8 +1315,8 @@ module mkMemiTestWorker(wciS0_Clk, endcase end assign wmemi_reqF_q_1$EN = - WILL_FIRE_RL_wmemi_reqF_both || - WILL_FIRE_RL_wmemi_reqF_incCtr && wmemi_reqF_c_r == 2'd1 || + WILL_FIRE_RL_wmemi_reqF_both && _dfoo5 || + WILL_FIRE_RL_wmemi_reqF_incCtr && wmemi_reqF_cntr_r == 2'd1 || WILL_FIRE_RL_wmemi_reqF_decCtr ; // register wmemi_statusR @@ -1358,34 +1368,64 @@ module mkMemiTestWorker(wciS0_Clk, assign wmemi_respF$CLR = 1'b0 ; // remaining internal signals - assign NOT_rgen_gsF_first__13_EQ_wmemi_respF_first__1_ETC___d317 = + assign NOT_rgen_gsF_first__07_EQ_wmemi_respF_first__0_ETC___d311 = rgen_gsF$D_OUT != wmemi_respF$D_OUT[127:0] ; - assign addr__h13927 = { hwordAddr, 4'h0 } ; - assign rdat__h15093 = { 24'd0, wmemi_statusR } ; - assign testStatus__h14567 = { 31'h0, isReader } ; + assign NOT_wmemi_dhF_cntr_r_84_EQ_2_97_98_AND_wmemi_o_ETC___d264 = + wmemi_dhF_cntr_r != 2'd2 && wmemi_operateD && + wmemi_peerIsReady && + wgen_gsF$EMPTY_N ; + assign _dfoo1 = + wci_wslv_respF_cntr_r != 2'd2 || + wci_wslv_respF_cntr_r_8_MINUS_1___d27 == 2'd1 ; + assign _dfoo11 = + wmemi_dhF_cntr_r != 2'd1 || + wmemi_dhF_cntr_r_84_MINUS_1___d193 == 2'd0 ; + assign _dfoo3 = + wci_wslv_respF_cntr_r != 2'd1 || + wci_wslv_respF_cntr_r_8_MINUS_1___d27 == 2'd0 ; + assign _dfoo5 = + wmemi_reqF_cntr_r != 2'd2 || + wmemi_reqF_cntr_r_61_MINUS_1___d170 == 2'd1 ; + assign _dfoo7 = + wmemi_reqF_cntr_r != 2'd1 || + wmemi_reqF_cntr_r_61_MINUS_1___d170 == 2'd0 ; + assign _dfoo9 = + wmemi_dhF_cntr_r != 2'd2 || + wmemi_dhF_cntr_r_84_MINUS_1___d193 == 2'd1 ; + assign addr__h13592 = { hwordAddr, 4'h0 } ; + assign rdat__h14758 = { 24'd0, wmemi_statusR } ; + assign testStatus__h14232 = { 31'h0, isReader } ; + assign wci_wslv_cState_4_EQ_2_5_AND_isTesting_66_67_A_ETC___d272 = + wci_wslv_cState == 3'd2 && isTesting && isWriter && !isReader ; + assign wci_wslv_cState_4_EQ_2_5_AND_isTesting_66_67_A_ETC___d294 = + wci_wslv_cState == 3'd2 && isTesting && !isWriter && isReader ; + assign wci_wslv_respF_cntr_r_8_MINUS_1___d27 = + wci_wslv_respF_cntr_r - 2'd1 ; + assign wmemi_dhF_cntr_r_84_MINUS_1___d193 = wmemi_dhF_cntr_r - 2'd1 ; + assign wmemi_reqF_cntr_r_61_MINUS_1___d170 = wmemi_reqF_cntr_r - 2'd1 ; always@(wci_wslv_reqF$D_OUT or tstCtrl or seqLen or - rdat__h15093 or + rdat__h14758 or testCycleCount or errorCount or wtDuration or rdDuration or - wmemiWrReq or wmemiRdReq or wmemiRdResp or testStatus__h14567) + wmemiWrReq or wmemiRdReq or wmemiRdResp or testStatus__h14232) begin case (wci_wslv_reqF$D_OUT[63:32]) - 32'h0: g_data__h15071 = tstCtrl; - 32'h00000004: g_data__h15071 = seqLen; - 32'h00000008: g_data__h15071 = rdat__h15093; - 32'h0000000C: g_data__h15071 = testCycleCount; - 32'h00000010: g_data__h15071 = errorCount; - 32'h00000014: g_data__h15071 = wtDuration; - 32'h00000018: g_data__h15071 = rdDuration; - 32'h0000001C: g_data__h15071 = wmemiWrReq; - 32'h00000020: g_data__h15071 = wmemiRdReq; - 32'h00000024: g_data__h15071 = wmemiRdResp; - 32'h00000028: g_data__h15071 = testStatus__h14567; - default: g_data__h15071 = 32'd0; + 32'h0: g_data__h14736 = tstCtrl; + 32'h00000004: g_data__h14736 = seqLen; + 32'h00000008: g_data__h14736 = rdat__h14758; + 32'h0000000C: g_data__h14736 = testCycleCount; + 32'h00000010: g_data__h14736 = errorCount; + 32'h00000014: g_data__h14736 = wtDuration; + 32'h00000018: g_data__h14736 = rdDuration; + 32'h0000001C: g_data__h14736 = wmemiWrReq; + 32'h00000020: g_data__h14736 = wmemiRdReq; + 32'h00000024: g_data__h14736 = wmemiRdResp; + 32'h00000028: g_data__h14736 = testStatus__h14232; + default: g_data__h14736 = 32'd0; endcase end @@ -1417,7 +1457,7 @@ module mkMemiTestWorker(wciS0_Clk, wci_wslv_illegalEdge <= `BSV_ASSIGNMENT_DELAY 1'd0; wci_wslv_nState <= `BSV_ASSIGNMENT_DELAY 3'd0; wci_wslv_reqF_countReg <= `BSV_ASSIGNMENT_DELAY 2'd0; - wci_wslv_respF_c_r <= `BSV_ASSIGNMENT_DELAY 2'd0; + wci_wslv_respF_cntr_r <= `BSV_ASSIGNMENT_DELAY 2'd0; wci_wslv_respF_q_0 <= `BSV_ASSIGNMENT_DELAY 34'h0AAAAAAAA; wci_wslv_respF_q_1 <= `BSV_ASSIGNMENT_DELAY 34'h0AAAAAAAA; wci_wslv_sFlagReg <= `BSV_ASSIGNMENT_DELAY 1'd0; @@ -1428,7 +1468,7 @@ module mkMemiTestWorker(wciS0_Clk, wmemiRdResp <= `BSV_ASSIGNMENT_DELAY 32'd0; wmemiWrReq <= `BSV_ASSIGNMENT_DELAY 32'd0; wmemi_busyWithMessage <= `BSV_ASSIGNMENT_DELAY 1'd0; - wmemi_dhF_c_r <= `BSV_ASSIGNMENT_DELAY 2'd0; + wmemi_dhF_cntr_r <= `BSV_ASSIGNMENT_DELAY 2'd0; wmemi_dhF_q_0 <= `BSV_ASSIGNMENT_DELAY 146'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; wmemi_dhF_q_1 <= `BSV_ASSIGNMENT_DELAY @@ -1436,7 +1476,7 @@ module mkMemiTestWorker(wciS0_Clk, wmemi_errorSticky <= `BSV_ASSIGNMENT_DELAY 1'd0; wmemi_operateD <= `BSV_ASSIGNMENT_DELAY 1'd0; wmemi_peerIsReady <= `BSV_ASSIGNMENT_DELAY 1'd1; - wmemi_reqF_c_r <= `BSV_ASSIGNMENT_DELAY 2'd0; + wmemi_reqF_cntr_r <= `BSV_ASSIGNMENT_DELAY 2'd0; wmemi_reqF_q_0 <= `BSV_ASSIGNMENT_DELAY 52'h0AAAAAAAAAAAA; wmemi_reqF_q_1 <= `BSV_ASSIGNMENT_DELAY 52'h0AAAAAAAAAAAA; wmemi_trafficSticky <= `BSV_ASSIGNMENT_DELAY 1'd0; @@ -1480,8 +1520,9 @@ module mkMemiTestWorker(wciS0_Clk, if (wci_wslv_reqF_countReg$EN) wci_wslv_reqF_countReg <= `BSV_ASSIGNMENT_DELAY wci_wslv_reqF_countReg$D_IN; - if (wci_wslv_respF_c_r$EN) - wci_wslv_respF_c_r <= `BSV_ASSIGNMENT_DELAY wci_wslv_respF_c_r$D_IN; + if (wci_wslv_respF_cntr_r$EN) + wci_wslv_respF_cntr_r <= `BSV_ASSIGNMENT_DELAY + wci_wslv_respF_cntr_r$D_IN; if (wci_wslv_respF_q_0$EN) wci_wslv_respF_q_0 <= `BSV_ASSIGNMENT_DELAY wci_wslv_respF_q_0$D_IN; if (wci_wslv_respF_q_1$EN) @@ -1501,8 +1542,8 @@ module mkMemiTestWorker(wciS0_Clk, if (wmemi_busyWithMessage$EN) wmemi_busyWithMessage <= `BSV_ASSIGNMENT_DELAY wmemi_busyWithMessage$D_IN; - if (wmemi_dhF_c_r$EN) - wmemi_dhF_c_r <= `BSV_ASSIGNMENT_DELAY wmemi_dhF_c_r$D_IN; + if (wmemi_dhF_cntr_r$EN) + wmemi_dhF_cntr_r <= `BSV_ASSIGNMENT_DELAY wmemi_dhF_cntr_r$D_IN; if (wmemi_dhF_q_0$EN) wmemi_dhF_q_0 <= `BSV_ASSIGNMENT_DELAY wmemi_dhF_q_0$D_IN; if (wmemi_dhF_q_1$EN) @@ -1513,8 +1554,8 @@ module mkMemiTestWorker(wciS0_Clk, wmemi_operateD <= `BSV_ASSIGNMENT_DELAY wmemi_operateD$D_IN; if (wmemi_peerIsReady$EN) wmemi_peerIsReady <= `BSV_ASSIGNMENT_DELAY wmemi_peerIsReady$D_IN; - if (wmemi_reqF_c_r$EN) - wmemi_reqF_c_r <= `BSV_ASSIGNMENT_DELAY wmemi_reqF_c_r$D_IN; + if (wmemi_reqF_cntr_r$EN) + wmemi_reqF_cntr_r <= `BSV_ASSIGNMENT_DELAY wmemi_reqF_cntr_r$D_IN; if (wmemi_reqF_q_0$EN) wmemi_reqF_q_0 <= `BSV_ASSIGNMENT_DELAY wmemi_reqF_q_0$D_IN; if (wmemi_reqF_q_1$EN) @@ -1574,7 +1615,7 @@ module mkMemiTestWorker(wciS0_Clk, wci_wslv_isReset_isInReset = 1'h0; wci_wslv_nState = 3'h2; wci_wslv_reqF_countReg = 2'h2; - wci_wslv_respF_c_r = 2'h2; + wci_wslv_respF_cntr_r = 2'h2; wci_wslv_respF_q_0 = 34'h2AAAAAAAA; wci_wslv_respF_q_1 = 34'h2AAAAAAAA; wci_wslv_sFlagReg = 1'h0; @@ -1584,14 +1625,14 @@ module mkMemiTestWorker(wciS0_Clk, wmemiRdResp = 32'hAAAAAAAA; wmemiWrReq = 32'hAAAAAAAA; wmemi_busyWithMessage = 1'h0; - wmemi_dhF_c_r = 2'h2; + wmemi_dhF_cntr_r = 2'h2; wmemi_dhF_q_0 = 146'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; wmemi_dhF_q_1 = 146'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; wmemi_errorSticky = 1'h0; wmemi_isReset_isInReset = 1'h0; wmemi_operateD = 1'h0; wmemi_peerIsReady = 1'h0; - wmemi_reqF_c_r = 2'h2; + wmemi_reqF_cntr_r = 2'h2; wmemi_reqF_q_0 = 52'hAAAAAAAAAAAAA; wmemi_reqF_q_1 = 52'hAAAAAAAAAAAAA; wmemi_statusR = 8'hAA; @@ -1610,39 +1651,39 @@ module mkMemiTestWorker(wciS0_Clk, #0; if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_read_resp && - NOT_rgen_gsF_first__13_EQ_wmemi_respF_first__1_ETC___d317) + NOT_rgen_gsF_first__07_EQ_wmemi_respF_first__0_ETC___d311) begin - v__h14490 = $time; + v__h14155 = $time; #0; end if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_read_resp && - NOT_rgen_gsF_first__13_EQ_wmemi_respF_first__1_ETC___d317) + NOT_rgen_gsF_first__07_EQ_wmemi_respF_first__0_ETC___d311) $display("[%0d]: %m: read_resp MISMATCH: exp:%0x got:%0x", - v__h14490, + v__h14155, rgen_gsF$D_OUT, wmemi_respF$D_OUT[127:0]); if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_start) begin - v__h3700 = $time; + v__h3568 = $time; #0; end if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_start) $display("[%0d]: %m: WCI ControlOp: Starting-transition edge:%x from:%x", - v__h3700, + v__h3568, wci_wslv_reqF$D_OUT[36:34], wci_wslv_cState); if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_ctrl_IsO) begin - v__h15261 = $time; + v__h14921 = $time; #0; end if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_ctrl_IsO) - $display("[%0d]: %m: Starting MemiTestWorker", v__h15261); + $display("[%0d]: %m: Starting MemiTestWorker", v__h14921); if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_OrE) $display("Error: \"bsv/wrk/MemiTestWorker.bsv\", line 119, column 26: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n"); @@ -1676,25 +1717,25 @@ module mkMemiTestWorker(wciS0_Clk, if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge) begin - v__h4019 = $time; + v__h3887 = $time; #0; end if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge) $display("[%0d]: %m: WCI ControlOp: ILLEGAL-EDGE Completed-transition edge:%x from:%x", - v__h4019, + v__h3887, wci_wslv_cEdge, wci_wslv_cState); if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && !wci_wslv_illegalEdge) begin - v__h3875 = $time; + v__h3743 = $time; #0; end if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && !wci_wslv_illegalEdge) $display("[%0d]: %m: WCI ControlOp: Completed-transition edge:%x from:%x to:%x", - v__h3875, + v__h3743, wci_wslv_cEdge, wci_wslv_cState, wci_wslv_nState); diff --git a/rtl/mkOCApp16B.v b/rtl/mkOCApp16B.v index 86ae7b55..2869144c 100644 --- a/rtl/mkOCApp16B.v +++ b/rtl/mkOCApp16B.v @@ -1,7 +1,7 @@ // -// Generated by Bluespec Compiler, version 2012.09.beta1 (build 29570, 2012-09.11) +// Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Wed Nov 28 10:38:00 EST 2012 +// On Fri Jun 21 16:58:05 EDT 2013 // // // Ports: diff --git a/rtl/mkOCApp4B.v b/rtl/mkOCApp4B.v index 3b9ef0ed..f8d630c9 100644 --- a/rtl/mkOCApp4B.v +++ b/rtl/mkOCApp4B.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2012.09.beta1 (build 29570, 2012-09.11) // -// On Tue Dec 11 16:21:22 EST 2012 +// On Tue Jan 22 07:33:09 EST 2013 // // // Ports: @@ -10,10 +10,10 @@ // wci_s_0_SData O 32 const // wci_s_0_SThreadBusy O 1 const // wci_s_0_SFlag O 2 const -// wci_s_1_SResp O 2 reg -// wci_s_1_SData O 32 reg -// wci_s_1_SThreadBusy O 1 -// wci_s_1_SFlag O 2 +// wci_s_1_SResp O 2 const +// wci_s_1_SData O 32 const +// wci_s_1_SThreadBusy O 1 const +// wci_s_1_SFlag O 2 const // wci_s_2_SResp O 2 reg // wci_s_2_SData O 32 reg // wci_s_2_SThreadBusy O 1 @@ -26,14 +26,14 @@ // wci_s_4_SData O 32 reg // wci_s_4_SThreadBusy O 1 // wci_s_4_SFlag O 2 -// wci_s_5_SResp O 2 const -// wci_s_5_SData O 32 const -// wci_s_5_SThreadBusy O 1 const -// wci_s_5_SFlag O 2 const -// wci_s_6_SResp O 2 const -// wci_s_6_SData O 32 const -// wci_s_6_SThreadBusy O 1 const -// wci_s_6_SFlag O 2 const +// wci_s_5_SResp O 2 reg +// wci_s_5_SData O 32 reg +// wci_s_5_SThreadBusy O 1 +// wci_s_5_SFlag O 2 +// wci_s_6_SResp O 2 reg +// wci_s_6_SData O 32 reg +// wci_s_6_SThreadBusy O 1 +// wci_s_6_SFlag O 2 // wci_s_7_SResp O 2 const // wci_s_7_SData O 32 const // wci_s_7_SThreadBusy O 1 const @@ -89,12 +89,12 @@ // wsi_m_dac_MReset_n O 1 // uuid O 512 const // RST_N_rst_0 I 1 unused -// RST_N_rst_1 I 1 reset +// RST_N_rst_1 I 1 unused // RST_N_rst_2 I 1 reset // RST_N_rst_3 I 1 reset // RST_N_rst_4 I 1 reset -// RST_N_rst_5 I 1 unused -// RST_N_rst_6 I 1 unused +// RST_N_rst_5 I 1 reset +// RST_N_rst_6 I 1 reset // RST_N_rst_7 I 1 unused // CLK I 1 clock // RST_N I 1 unused @@ -104,11 +104,11 @@ // wci_s_0_MAddr I 32 unused // wci_s_0_MData I 32 unused // wci_s_0_MFlag I 2 unused -// wci_s_1_MCmd I 3 -// wci_s_1_MAddrSpace I 1 -// wci_s_1_MByteEn I 4 -// wci_s_1_MAddr I 32 -// wci_s_1_MData I 32 +// wci_s_1_MCmd I 3 unused +// wci_s_1_MAddrSpace I 1 unused +// wci_s_1_MByteEn I 4 unused +// wci_s_1_MAddr I 32 unused +// wci_s_1_MData I 32 unused // wci_s_1_MFlag I 2 unused // wci_s_2_MCmd I 3 // wci_s_2_MAddrSpace I 1 @@ -128,17 +128,17 @@ // wci_s_4_MAddr I 32 // wci_s_4_MData I 32 // wci_s_4_MFlag I 2 unused -// wci_s_5_MCmd I 3 unused -// wci_s_5_MAddrSpace I 1 unused -// wci_s_5_MByteEn I 4 unused -// wci_s_5_MAddr I 32 unused -// wci_s_5_MData I 32 unused +// wci_s_5_MCmd I 3 +// wci_s_5_MAddrSpace I 1 +// wci_s_5_MByteEn I 4 +// wci_s_5_MAddr I 32 +// wci_s_5_MData I 32 // wci_s_5_MFlag I 2 unused -// wci_s_6_MCmd I 3 unused -// wci_s_6_MAddrSpace I 1 unused -// wci_s_6_MByteEn I 4 unused -// wci_s_6_MAddr I 32 unused -// wci_s_6_MData I 32 unused +// wci_s_6_MCmd I 3 +// wci_s_6_MAddrSpace I 1 +// wci_s_6_MByteEn I 4 +// wci_s_6_MAddr I 32 +// wci_s_6_MData I 32 // wci_s_6_MFlag I 2 unused // wci_s_7_MCmd I 3 unused // wci_s_7_MAddrSpace I 1 unused @@ -1135,19 +1135,15 @@ module mkOCApp4B(RST_N_rst_0, // inlined wires wire [31 : 0] tieOff0_wci_Es_mAddr_w$wget, tieOff0_wci_Es_mData_w$wget, - tieOff5_wci_Es_mAddr_w$wget, - tieOff5_wci_Es_mData_w$wget, - tieOff6_wci_Es_mAddr_w$wget, - tieOff6_wci_Es_mData_w$wget, + tieOff1_wci_Es_mAddr_w$wget, + tieOff1_wci_Es_mData_w$wget, tieOff7_wci_Es_mAddr_w$wget, tieOff7_wci_Es_mData_w$wget; wire [3 : 0] tieOff0_wci_Es_mByteEn_w$wget, - tieOff5_wci_Es_mByteEn_w$wget, - tieOff6_wci_Es_mByteEn_w$wget, + tieOff1_wci_Es_mByteEn_w$wget, tieOff7_wci_Es_mByteEn_w$wget; wire [2 : 0] tieOff0_wci_Es_mCmd_w$wget, - tieOff5_wci_Es_mCmd_w$wget, - tieOff6_wci_Es_mCmd_w$wget, + tieOff1_wci_Es_mCmd_w$wget, tieOff7_wci_Es_mCmd_w$wget; wire tieOff0_wci_Es_mAddrSpace_w$wget, tieOff0_wci_Es_mAddrSpace_w$whas, @@ -1155,18 +1151,12 @@ module mkOCApp4B(RST_N_rst_0, tieOff0_wci_Es_mByteEn_w$whas, tieOff0_wci_Es_mCmd_w$whas, tieOff0_wci_Es_mData_w$whas, - tieOff5_wci_Es_mAddrSpace_w$wget, - tieOff5_wci_Es_mAddrSpace_w$whas, - tieOff5_wci_Es_mAddr_w$whas, - tieOff5_wci_Es_mByteEn_w$whas, - tieOff5_wci_Es_mCmd_w$whas, - tieOff5_wci_Es_mData_w$whas, - tieOff6_wci_Es_mAddrSpace_w$wget, - tieOff6_wci_Es_mAddrSpace_w$whas, - tieOff6_wci_Es_mAddr_w$whas, - tieOff6_wci_Es_mByteEn_w$whas, - tieOff6_wci_Es_mCmd_w$whas, - tieOff6_wci_Es_mData_w$whas, + tieOff1_wci_Es_mAddrSpace_w$wget, + tieOff1_wci_Es_mAddrSpace_w$whas, + tieOff1_wci_Es_mAddr_w$whas, + tieOff1_wci_Es_mByteEn_w$whas, + tieOff1_wci_Es_mCmd_w$whas, + tieOff1_wci_Es_mData_w$whas, tieOff7_wci_Es_mAddrSpace_w$wget, tieOff7_wci_Es_mAddrSpace_w$whas, tieOff7_wci_Es_mAddr_w$whas, @@ -1174,28 +1164,6 @@ module mkOCApp4B(RST_N_rst_0, tieOff7_wci_Es_mCmd_w$whas, tieOff7_wci_Es_mData_w$whas; - // ports of submodule appW1 - wire [127 : 0] appW1$wmemiM0_MData, appW1$wmemiM0_SData; - wire [35 : 0] appW1$wmemiM0_MAddr; - wire [31 : 0] appW1$wciS0_MAddr, appW1$wciS0_MData, appW1$wciS0_SData; - wire [15 : 0] appW1$wmemiM0_MDataByteEn; - wire [11 : 0] appW1$wmemiM0_MBurstLength; - wire [3 : 0] appW1$wciS0_MByteEn; - wire [2 : 0] appW1$wciS0_MCmd, appW1$wmemiM0_MCmd; - wire [1 : 0] appW1$wciS0_MFlag, - appW1$wciS0_SFlag, - appW1$wciS0_SResp, - appW1$wmemiM0_SResp; - wire appW1$wciS0_MAddrSpace, - appW1$wciS0_SThreadBusy, - appW1$wmemiM0_MDataLast, - appW1$wmemiM0_MDataValid, - appW1$wmemiM0_MReqLast, - appW1$wmemiM0_MReset_n, - appW1$wmemiM0_SCmdAccept, - appW1$wmemiM0_SDataAccept, - appW1$wmemiM0_SRespLast; - // ports of submodule appW2 wire [31 : 0] appW2$wciS0_MAddr, appW2$wciS0_MData, @@ -1247,18 +1215,36 @@ module mkOCApp4B(RST_N_rst_0, appW2$wsiS0_SThreadBusy; // ports of submodule appW3 + wire [127 : 0] appW3$wmemiM0_MData, appW3$wmemiM0_SData; + wire [35 : 0] appW3$wmemiM0_MAddr; wire [31 : 0] appW3$wciS0_MAddr, appW3$wciS0_MData, appW3$wciS0_SData, appW3$wsiM0_MData, appW3$wsiS0_MData; - wire [11 : 0] appW3$wsiM0_MBurstLength, appW3$wsiS0_MBurstLength; + wire [15 : 0] appW3$wmemiM0_MDataByteEn; + wire [11 : 0] appW3$wmemiM0_MBurstLength, + appW3$wsiM0_MBurstLength, + appW3$wsiS0_MBurstLength; wire [7 : 0] appW3$wsiM0_MReqInfo, appW3$wsiS0_MReqInfo; wire [3 : 0] appW3$wciS0_MByteEn, appW3$wsiM0_MByteEn, appW3$wsiS0_MByteEn; - wire [2 : 0] appW3$wciS0_MCmd, appW3$wsiM0_MCmd, appW3$wsiS0_MCmd; - wire [1 : 0] appW3$wciS0_MFlag, appW3$wciS0_SFlag, appW3$wciS0_SResp; + wire [2 : 0] appW3$wciS0_MCmd, + appW3$wmemiM0_MCmd, + appW3$wsiM0_MCmd, + appW3$wsiS0_MCmd; + wire [1 : 0] appW3$wciS0_MFlag, + appW3$wciS0_SFlag, + appW3$wciS0_SResp, + appW3$wmemiM0_SResp; wire appW3$wciS0_MAddrSpace, appW3$wciS0_SThreadBusy, + appW3$wmemiM0_MDataLast, + appW3$wmemiM0_MDataValid, + appW3$wmemiM0_MReqLast, + appW3$wmemiM0_MReset_n, + appW3$wmemiM0_SCmdAccept, + appW3$wmemiM0_SDataAccept, + appW3$wmemiM0_SRespLast, appW3$wsiM0_MBurstPrecise, appW3$wsiM0_MReqLast, appW3$wsiM0_MReset_n, @@ -1320,6 +1306,80 @@ module mkOCApp4B(RST_N_rst_0, appW4$wsiS0_SReset_n, appW4$wsiS0_SThreadBusy; + // ports of submodule appW5 + wire [31 : 0] appW5$wciS0_MAddr, + appW5$wciS0_MData, + appW5$wciS0_SData, + appW5$wsiM0_MData, + appW5$wsiM1_MData, + appW5$wsiS0_MData, + appW5$wsiS1_MData; + wire [11 : 0] appW5$wsiM0_MBurstLength, + appW5$wsiM1_MBurstLength, + appW5$wsiS0_MBurstLength, + appW5$wsiS1_MBurstLength; + wire [7 : 0] appW5$wsiM0_MReqInfo, + appW5$wsiM1_MReqInfo, + appW5$wsiS0_MReqInfo, + appW5$wsiS1_MReqInfo; + wire [3 : 0] appW5$wciS0_MByteEn, + appW5$wsiM0_MByteEn, + appW5$wsiM1_MByteEn, + appW5$wsiS0_MByteEn, + appW5$wsiS1_MByteEn; + wire [2 : 0] appW5$wciS0_MCmd, + appW5$wsiM0_MCmd, + appW5$wsiM1_MCmd, + appW5$wsiS0_MCmd, + appW5$wsiS1_MCmd; + wire [1 : 0] appW5$wciS0_MFlag, appW5$wciS0_SFlag, appW5$wciS0_SResp; + wire appW5$wciS0_MAddrSpace, + appW5$wciS0_SThreadBusy, + appW5$wsiM0_MBurstPrecise, + appW5$wsiM0_MReqLast, + appW5$wsiM0_MReset_n, + appW5$wsiM0_SReset_n, + appW5$wsiM0_SThreadBusy, + appW5$wsiM1_MBurstPrecise, + appW5$wsiM1_MReqLast, + appW5$wsiM1_MReset_n, + appW5$wsiM1_SReset_n, + appW5$wsiM1_SThreadBusy, + appW5$wsiS0_MBurstPrecise, + appW5$wsiS0_MReqLast, + appW5$wsiS0_MReset_n, + appW5$wsiS0_SReset_n, + appW5$wsiS0_SThreadBusy, + appW5$wsiS1_MBurstPrecise, + appW5$wsiS1_MReqLast, + appW5$wsiS1_MReset_n, + appW5$wsiS1_SReset_n, + appW5$wsiS1_SThreadBusy; + + // ports of submodule appW6 + wire [31 : 0] appW6$wciS0_MAddr, + appW6$wciS0_MData, + appW6$wciS0_SData, + appW6$wsiM0_MData, + appW6$wsiS0_MData; + wire [11 : 0] appW6$wsiM0_MBurstLength, appW6$wsiS0_MBurstLength; + wire [7 : 0] appW6$wsiM0_MReqInfo, appW6$wsiS0_MReqInfo; + wire [3 : 0] appW6$wciS0_MByteEn, appW6$wsiM0_MByteEn, appW6$wsiS0_MByteEn; + wire [2 : 0] appW6$wciS0_MCmd, appW6$wsiM0_MCmd, appW6$wsiS0_MCmd; + wire [1 : 0] appW6$wciS0_MFlag, appW6$wciS0_SFlag, appW6$wciS0_SResp; + wire appW6$wciS0_MAddrSpace, + appW6$wciS0_SThreadBusy, + appW6$wsiM0_MBurstPrecise, + appW6$wsiM0_MReqLast, + appW6$wsiM0_MReset_n, + appW6$wsiM0_SReset_n, + appW6$wsiM0_SThreadBusy, + appW6$wsiS0_MBurstPrecise, + appW6$wsiS0_MReqLast, + appW6$wsiS0_MReset_n, + appW6$wsiS0_SReset_n, + appW6$wsiS0_SThreadBusy; + // ports of submodule id wire [511 : 0] id$uuid; @@ -1336,16 +1396,16 @@ module mkOCApp4B(RST_N_rst_0, assign wci_s_0_SFlag = 2'b0 ; // value method wci_s_1_sResp - assign wci_s_1_SResp = appW1$wciS0_SResp ; + assign wci_s_1_SResp = 2'd0 ; // value method wci_s_1_sData - assign wci_s_1_SData = appW1$wciS0_SData ; + assign wci_s_1_SData = 32'hAAAAAAAA ; // value method wci_s_1_sThreadBusy - assign wci_s_1_SThreadBusy = appW1$wciS0_SThreadBusy ; + assign wci_s_1_SThreadBusy = 1'd1 ; // value method wci_s_1_sFlag - assign wci_s_1_SFlag = appW1$wciS0_SFlag ; + assign wci_s_1_SFlag = 2'b0 ; // value method wci_s_2_sResp assign wci_s_2_SResp = appW2$wciS0_SResp ; @@ -1384,28 +1444,28 @@ module mkOCApp4B(RST_N_rst_0, assign wci_s_4_SFlag = appW4$wciS0_SFlag ; // value method wci_s_5_sResp - assign wci_s_5_SResp = 2'd0 ; + assign wci_s_5_SResp = appW5$wciS0_SResp ; // value method wci_s_5_sData - assign wci_s_5_SData = 32'hAAAAAAAA ; + assign wci_s_5_SData = appW5$wciS0_SData ; // value method wci_s_5_sThreadBusy - assign wci_s_5_SThreadBusy = 1'd1 ; + assign wci_s_5_SThreadBusy = appW5$wciS0_SThreadBusy ; // value method wci_s_5_sFlag - assign wci_s_5_SFlag = 2'b0 ; + assign wci_s_5_SFlag = appW5$wciS0_SFlag ; // value method wci_s_6_sResp - assign wci_s_6_SResp = 2'd0 ; + assign wci_s_6_SResp = appW6$wciS0_SResp ; // value method wci_s_6_sData - assign wci_s_6_SData = 32'hAAAAAAAA ; + assign wci_s_6_SData = appW6$wciS0_SData ; // value method wci_s_6_sThreadBusy - assign wci_s_6_SThreadBusy = 1'd1 ; + assign wci_s_6_SThreadBusy = appW6$wciS0_SThreadBusy ; // value method wci_s_6_sFlag - assign wci_s_6_SFlag = 2'b0 ; + assign wci_s_6_SFlag = appW6$wciS0_SFlag ; // value method wci_s_7_sResp assign wci_s_7_SResp = 2'd0 ; @@ -1510,37 +1570,37 @@ module mkOCApp4B(RST_N_rst_0, assign wmiM1_MReset_n = appW4$wmiM0_MReset_n ; // value method wmemiM0_mCmd - assign wmemiM0_MCmd = appW1$wmemiM0_MCmd ; + assign wmemiM0_MCmd = appW3$wmemiM0_MCmd ; // value method wmemiM0_mReqLast - assign wmemiM0_MReqLast = appW1$wmemiM0_MReqLast ; + assign wmemiM0_MReqLast = appW3$wmemiM0_MReqLast ; // value method wmemiM0_mAddr - assign wmemiM0_MAddr = appW1$wmemiM0_MAddr ; + assign wmemiM0_MAddr = appW3$wmemiM0_MAddr ; // value method wmemiM0_mBurstLength - assign wmemiM0_MBurstLength = appW1$wmemiM0_MBurstLength ; + assign wmemiM0_MBurstLength = appW3$wmemiM0_MBurstLength ; // value method wmemiM0_mDataValid - assign wmemiM0_MDataValid = appW1$wmemiM0_MDataValid ; + assign wmemiM0_MDataValid = appW3$wmemiM0_MDataValid ; // value method wmemiM0_mDataLast - assign wmemiM0_MDataLast = appW1$wmemiM0_MDataLast ; + assign wmemiM0_MDataLast = appW3$wmemiM0_MDataLast ; // value method wmemiM0_mData - assign wmemiM0_MData = appW1$wmemiM0_MData ; + assign wmemiM0_MData = appW3$wmemiM0_MData ; // value method wmemiM0_mDataByteEn - assign wmemiM0_MDataByteEn = appW1$wmemiM0_MDataByteEn ; + assign wmemiM0_MDataByteEn = appW3$wmemiM0_MDataByteEn ; // value method wmemiM0_mReset_n - assign wmemiM0_MReset_n = appW1$wmemiM0_MReset_n ; + assign wmemiM0_MReset_n = appW3$wmemiM0_MReset_n ; // value method wsi_s_adc_sThreadBusy - assign wsi_s_adc_SThreadBusy = appW2$wsiS0_SThreadBusy ; + assign wsi_s_adc_SThreadBusy = appW5$wsiS1_SThreadBusy ; // value method wsi_s_adc_sReset_n - assign wsi_s_adc_SReset_n = appW2$wsiS0_SReset_n ; + assign wsi_s_adc_SReset_n = appW5$wsiS1_SReset_n ; // value method wsi_m_dac_mCmd assign wsi_m_dac_MCmd = appW4$wsiM0_MCmd ; @@ -1569,34 +1629,6 @@ module mkOCApp4B(RST_N_rst_0, // value method uuid assign uuid = id$uuid ; - // submodule appW1 - mkMemiTestWorker #(.hasDebugLogic(hasDebugLogic)) appW1(.wciS0_Clk(CLK), - .wciS0_MReset_n(RST_N_rst_1), - .wciS0_MAddr(appW1$wciS0_MAddr), - .wciS0_MAddrSpace(appW1$wciS0_MAddrSpace), - .wciS0_MByteEn(appW1$wciS0_MByteEn), - .wciS0_MCmd(appW1$wciS0_MCmd), - .wciS0_MData(appW1$wciS0_MData), - .wciS0_MFlag(appW1$wciS0_MFlag), - .wmemiM0_SData(appW1$wmemiM0_SData), - .wmemiM0_SResp(appW1$wmemiM0_SResp), - .wmemiM0_SRespLast(appW1$wmemiM0_SRespLast), - .wmemiM0_SCmdAccept(appW1$wmemiM0_SCmdAccept), - .wmemiM0_SDataAccept(appW1$wmemiM0_SDataAccept), - .wciS0_SResp(appW1$wciS0_SResp), - .wciS0_SData(appW1$wciS0_SData), - .wciS0_SThreadBusy(appW1$wciS0_SThreadBusy), - .wciS0_SFlag(appW1$wciS0_SFlag), - .wmemiM0_MCmd(appW1$wmemiM0_MCmd), - .wmemiM0_MReqLast(appW1$wmemiM0_MReqLast), - .wmemiM0_MAddr(appW1$wmemiM0_MAddr), - .wmemiM0_MBurstLength(appW1$wmemiM0_MBurstLength), - .wmemiM0_MDataValid(appW1$wmemiM0_MDataValid), - .wmemiM0_MDataLast(appW1$wmemiM0_MDataLast), - .wmemiM0_MData(appW1$wmemiM0_MData), - .wmemiM0_MDataByteEn(appW1$wmemiM0_MDataByteEn), - .wmemiM0_MReset_n(appW1$wmemiM0_MReset_n)); - // submodule appW2 mkSMAdapter4B #(.smaCtrlInit(32'h00000001), .hasDebugLogic(hasDebugLogic)) appW2(.wciS0_Clk(CLK), @@ -1652,38 +1684,53 @@ module mkOCApp4B(RST_N_rst_0, .wsiS0_SReset_n(appW2$wsiS0_SReset_n)); // submodule appW3 - mkBiasWorker4B #(.hasDebugLogic(hasDebugLogic)) appW3(.wciS0_Clk(CLK), - .wciS0_MReset_n(RST_N_rst_3), - .wciS0_MAddr(appW3$wciS0_MAddr), - .wciS0_MAddrSpace(appW3$wciS0_MAddrSpace), - .wciS0_MByteEn(appW3$wciS0_MByteEn), - .wciS0_MCmd(appW3$wciS0_MCmd), - .wciS0_MData(appW3$wciS0_MData), - .wciS0_MFlag(appW3$wciS0_MFlag), - .wsiS0_MBurstLength(appW3$wsiS0_MBurstLength), - .wsiS0_MByteEn(appW3$wsiS0_MByteEn), - .wsiS0_MCmd(appW3$wsiS0_MCmd), - .wsiS0_MData(appW3$wsiS0_MData), - .wsiS0_MReqInfo(appW3$wsiS0_MReqInfo), - .wsiS0_MReqLast(appW3$wsiS0_MReqLast), - .wsiS0_MBurstPrecise(appW3$wsiS0_MBurstPrecise), - .wsiS0_MReset_n(appW3$wsiS0_MReset_n), - .wsiM0_SThreadBusy(appW3$wsiM0_SThreadBusy), - .wsiM0_SReset_n(appW3$wsiM0_SReset_n), - .wciS0_SResp(appW3$wciS0_SResp), - .wciS0_SData(appW3$wciS0_SData), - .wciS0_SThreadBusy(appW3$wciS0_SThreadBusy), - .wciS0_SFlag(appW3$wciS0_SFlag), - .wsiS0_SThreadBusy(appW3$wsiS0_SThreadBusy), - .wsiS0_SReset_n(appW3$wsiS0_SReset_n), - .wsiM0_MCmd(appW3$wsiM0_MCmd), - .wsiM0_MReqLast(appW3$wsiM0_MReqLast), - .wsiM0_MBurstPrecise(appW3$wsiM0_MBurstPrecise), - .wsiM0_MBurstLength(appW3$wsiM0_MBurstLength), - .wsiM0_MData(appW3$wsiM0_MData), - .wsiM0_MByteEn(appW3$wsiM0_MByteEn), - .wsiM0_MReqInfo(appW3$wsiM0_MReqInfo), - .wsiM0_MReset_n(appW3$wsiM0_MReset_n)); + mkDelayWorker4B #(.dlyCtrlInit(32'h0), + .hasDebugLogic(hasDebugLogic)) appW3(.wciS0_Clk(CLK), + .wciS0_MReset_n(RST_N_rst_3), + .wciS0_MAddr(appW3$wciS0_MAddr), + .wciS0_MAddrSpace(appW3$wciS0_MAddrSpace), + .wciS0_MByteEn(appW3$wciS0_MByteEn), + .wciS0_MCmd(appW3$wciS0_MCmd), + .wciS0_MData(appW3$wciS0_MData), + .wciS0_MFlag(appW3$wciS0_MFlag), + .wmemiM0_SData(appW3$wmemiM0_SData), + .wmemiM0_SResp(appW3$wmemiM0_SResp), + .wsiS0_MBurstLength(appW3$wsiS0_MBurstLength), + .wsiS0_MByteEn(appW3$wsiS0_MByteEn), + .wsiS0_MCmd(appW3$wsiS0_MCmd), + .wsiS0_MData(appW3$wsiS0_MData), + .wsiS0_MReqInfo(appW3$wsiS0_MReqInfo), + .wsiS0_MReqLast(appW3$wsiS0_MReqLast), + .wsiS0_MBurstPrecise(appW3$wsiS0_MBurstPrecise), + .wsiS0_MReset_n(appW3$wsiS0_MReset_n), + .wsiM0_SThreadBusy(appW3$wsiM0_SThreadBusy), + .wsiM0_SReset_n(appW3$wsiM0_SReset_n), + .wmemiM0_SRespLast(appW3$wmemiM0_SRespLast), + .wmemiM0_SCmdAccept(appW3$wmemiM0_SCmdAccept), + .wmemiM0_SDataAccept(appW3$wmemiM0_SDataAccept), + .wciS0_SResp(appW3$wciS0_SResp), + .wciS0_SData(appW3$wciS0_SData), + .wciS0_SThreadBusy(appW3$wciS0_SThreadBusy), + .wciS0_SFlag(appW3$wciS0_SFlag), + .wsiS0_SThreadBusy(appW3$wsiS0_SThreadBusy), + .wsiS0_SReset_n(appW3$wsiS0_SReset_n), + .wsiM0_MCmd(appW3$wsiM0_MCmd), + .wsiM0_MReqLast(appW3$wsiM0_MReqLast), + .wsiM0_MBurstPrecise(appW3$wsiM0_MBurstPrecise), + .wsiM0_MBurstLength(appW3$wsiM0_MBurstLength), + .wsiM0_MData(appW3$wsiM0_MData), + .wsiM0_MByteEn(appW3$wsiM0_MByteEn), + .wsiM0_MReqInfo(appW3$wsiM0_MReqInfo), + .wsiM0_MReset_n(appW3$wsiM0_MReset_n), + .wmemiM0_MCmd(appW3$wmemiM0_MCmd), + .wmemiM0_MReqLast(appW3$wmemiM0_MReqLast), + .wmemiM0_MAddr(appW3$wmemiM0_MAddr), + .wmemiM0_MBurstLength(appW3$wmemiM0_MBurstLength), + .wmemiM0_MDataValid(appW3$wmemiM0_MDataValid), + .wmemiM0_MDataLast(appW3$wmemiM0_MDataLast), + .wmemiM0_MData(appW3$wmemiM0_MData), + .wmemiM0_MDataByteEn(appW3$wmemiM0_MDataByteEn), + .wmemiM0_MReset_n(appW3$wmemiM0_MReset_n)); // submodule appW4 mkSMAdapter4B #(.smaCtrlInit(32'h00000002), @@ -1739,6 +1786,96 @@ module mkOCApp4B(RST_N_rst_0, .wsiS0_SThreadBusy(appW4$wsiS0_SThreadBusy), .wsiS0_SReset_n(appW4$wsiS0_SReset_n)); + // submodule appW5 + mkWsiSplitter2x24B #(.ctrlInit(32'h0), + .hasDebugLogic(hasDebugLogic)) appW5(.wciS0_Clk(CLK), + .wciS0_MReset_n(RST_N_rst_5), + .wciS0_MAddr(appW5$wciS0_MAddr), + .wciS0_MAddrSpace(appW5$wciS0_MAddrSpace), + .wciS0_MByteEn(appW5$wciS0_MByteEn), + .wciS0_MCmd(appW5$wciS0_MCmd), + .wciS0_MData(appW5$wciS0_MData), + .wciS0_MFlag(appW5$wciS0_MFlag), + .wsiS0_MBurstLength(appW5$wsiS0_MBurstLength), + .wsiS0_MByteEn(appW5$wsiS0_MByteEn), + .wsiS0_MCmd(appW5$wsiS0_MCmd), + .wsiS0_MData(appW5$wsiS0_MData), + .wsiS0_MReqInfo(appW5$wsiS0_MReqInfo), + .wsiS1_MBurstLength(appW5$wsiS1_MBurstLength), + .wsiS1_MByteEn(appW5$wsiS1_MByteEn), + .wsiS1_MCmd(appW5$wsiS1_MCmd), + .wsiS1_MData(appW5$wsiS1_MData), + .wsiS1_MReqInfo(appW5$wsiS1_MReqInfo), + .wsiS0_MReqLast(appW5$wsiS0_MReqLast), + .wsiS0_MBurstPrecise(appW5$wsiS0_MBurstPrecise), + .wsiS0_MReset_n(appW5$wsiS0_MReset_n), + .wsiS1_MReqLast(appW5$wsiS1_MReqLast), + .wsiS1_MBurstPrecise(appW5$wsiS1_MBurstPrecise), + .wsiS1_MReset_n(appW5$wsiS1_MReset_n), + .wsiM0_SThreadBusy(appW5$wsiM0_SThreadBusy), + .wsiM0_SReset_n(appW5$wsiM0_SReset_n), + .wsiM1_SThreadBusy(appW5$wsiM1_SThreadBusy), + .wsiM1_SReset_n(appW5$wsiM1_SReset_n), + .wciS0_SResp(appW5$wciS0_SResp), + .wciS0_SData(appW5$wciS0_SData), + .wciS0_SThreadBusy(appW5$wciS0_SThreadBusy), + .wciS0_SFlag(appW5$wciS0_SFlag), + .wsiS0_SThreadBusy(appW5$wsiS0_SThreadBusy), + .wsiS0_SReset_n(appW5$wsiS0_SReset_n), + .wsiS1_SThreadBusy(appW5$wsiS1_SThreadBusy), + .wsiS1_SReset_n(appW5$wsiS1_SReset_n), + .wsiM0_MCmd(appW5$wsiM0_MCmd), + .wsiM0_MReqLast(appW5$wsiM0_MReqLast), + .wsiM0_MBurstPrecise(appW5$wsiM0_MBurstPrecise), + .wsiM0_MBurstLength(appW5$wsiM0_MBurstLength), + .wsiM0_MData(appW5$wsiM0_MData), + .wsiM0_MByteEn(appW5$wsiM0_MByteEn), + .wsiM0_MReqInfo(appW5$wsiM0_MReqInfo), + .wsiM0_MReset_n(appW5$wsiM0_MReset_n), + .wsiM1_MCmd(appW5$wsiM1_MCmd), + .wsiM1_MReqLast(appW5$wsiM1_MReqLast), + .wsiM1_MBurstPrecise(appW5$wsiM1_MBurstPrecise), + .wsiM1_MBurstLength(appW5$wsiM1_MBurstLength), + .wsiM1_MData(appW5$wsiM1_MData), + .wsiM1_MByteEn(appW5$wsiM1_MByteEn), + .wsiM1_MReqInfo(appW5$wsiM1_MReqInfo), + .wsiM1_MReset_n(appW5$wsiM1_MReset_n)); + + // submodule appW6 + mkFrameGate4B #(.fgCtrlInit(32'h0), + .hasDebugLogic(hasDebugLogic)) appW6(.wciS0_Clk(CLK), + .wciS0_MReset_n(RST_N_rst_6), + .wciS0_MAddr(appW6$wciS0_MAddr), + .wciS0_MAddrSpace(appW6$wciS0_MAddrSpace), + .wciS0_MByteEn(appW6$wciS0_MByteEn), + .wciS0_MCmd(appW6$wciS0_MCmd), + .wciS0_MData(appW6$wciS0_MData), + .wciS0_MFlag(appW6$wciS0_MFlag), + .wsiS0_MBurstLength(appW6$wsiS0_MBurstLength), + .wsiS0_MByteEn(appW6$wsiS0_MByteEn), + .wsiS0_MCmd(appW6$wsiS0_MCmd), + .wsiS0_MData(appW6$wsiS0_MData), + .wsiS0_MReqInfo(appW6$wsiS0_MReqInfo), + .wsiS0_MReqLast(appW6$wsiS0_MReqLast), + .wsiS0_MBurstPrecise(appW6$wsiS0_MBurstPrecise), + .wsiS0_MReset_n(appW6$wsiS0_MReset_n), + .wsiM0_SThreadBusy(appW6$wsiM0_SThreadBusy), + .wsiM0_SReset_n(appW6$wsiM0_SReset_n), + .wciS0_SResp(appW6$wciS0_SResp), + .wciS0_SData(appW6$wciS0_SData), + .wciS0_SThreadBusy(appW6$wciS0_SThreadBusy), + .wciS0_SFlag(appW6$wciS0_SFlag), + .wsiS0_SThreadBusy(appW6$wsiS0_SThreadBusy), + .wsiS0_SReset_n(appW6$wsiS0_SReset_n), + .wsiM0_MCmd(appW6$wsiM0_MCmd), + .wsiM0_MReqLast(appW6$wsiM0_MReqLast), + .wsiM0_MBurstPrecise(appW6$wsiM0_MBurstPrecise), + .wsiM0_MBurstLength(appW6$wsiM0_MBurstLength), + .wsiM0_MData(appW6$wsiM0_MData), + .wsiM0_MByteEn(appW6$wsiM0_MByteEn), + .wsiM0_MReqInfo(appW6$wsiM0_MReqInfo), + .wsiM0_MReset_n(appW6$wsiM0_MReset_n)); + // submodule id mkUUID id(.uuid(id$uuid)); @@ -1753,26 +1890,16 @@ module mkOCApp4B(RST_N_rst_0, assign tieOff0_wci_Es_mAddr_w$whas = 1'd1 ; assign tieOff0_wci_Es_mData_w$wget = wci_s_0_MData ; assign tieOff0_wci_Es_mData_w$whas = 1'd1 ; - assign tieOff5_wci_Es_mCmd_w$wget = wci_s_5_MCmd ; - assign tieOff5_wci_Es_mCmd_w$whas = 1'd1 ; - assign tieOff5_wci_Es_mAddrSpace_w$wget = wci_s_5_MAddrSpace ; - assign tieOff5_wci_Es_mAddrSpace_w$whas = 1'd1 ; - assign tieOff5_wci_Es_mByteEn_w$wget = wci_s_5_MByteEn ; - assign tieOff5_wci_Es_mByteEn_w$whas = 1'd1 ; - assign tieOff5_wci_Es_mAddr_w$wget = wci_s_5_MAddr ; - assign tieOff5_wci_Es_mAddr_w$whas = 1'd1 ; - assign tieOff5_wci_Es_mData_w$wget = wci_s_5_MData ; - assign tieOff5_wci_Es_mData_w$whas = 1'd1 ; - assign tieOff6_wci_Es_mCmd_w$wget = wci_s_6_MCmd ; - assign tieOff6_wci_Es_mCmd_w$whas = 1'd1 ; - assign tieOff6_wci_Es_mAddrSpace_w$wget = wci_s_6_MAddrSpace ; - assign tieOff6_wci_Es_mAddrSpace_w$whas = 1'd1 ; - assign tieOff6_wci_Es_mByteEn_w$wget = wci_s_6_MByteEn ; - assign tieOff6_wci_Es_mByteEn_w$whas = 1'd1 ; - assign tieOff6_wci_Es_mAddr_w$wget = wci_s_6_MAddr ; - assign tieOff6_wci_Es_mAddr_w$whas = 1'd1 ; - assign tieOff6_wci_Es_mData_w$wget = wci_s_6_MData ; - assign tieOff6_wci_Es_mData_w$whas = 1'd1 ; + assign tieOff1_wci_Es_mCmd_w$wget = wci_s_1_MCmd ; + assign tieOff1_wci_Es_mCmd_w$whas = 1'd1 ; + assign tieOff1_wci_Es_mAddrSpace_w$wget = wci_s_1_MAddrSpace ; + assign tieOff1_wci_Es_mAddrSpace_w$whas = 1'd1 ; + assign tieOff1_wci_Es_mByteEn_w$wget = wci_s_1_MByteEn ; + assign tieOff1_wci_Es_mByteEn_w$whas = 1'd1 ; + assign tieOff1_wci_Es_mAddr_w$wget = wci_s_1_MAddr ; + assign tieOff1_wci_Es_mAddr_w$whas = 1'd1 ; + assign tieOff1_wci_Es_mData_w$wget = wci_s_1_MData ; + assign tieOff1_wci_Es_mData_w$whas = 1'd1 ; assign tieOff7_wci_Es_mCmd_w$wget = wci_s_7_MCmd ; assign tieOff7_wci_Es_mCmd_w$whas = 1'd1 ; assign tieOff7_wci_Es_mAddrSpace_w$wget = wci_s_7_MAddrSpace ; @@ -1784,19 +1911,6 @@ module mkOCApp4B(RST_N_rst_0, assign tieOff7_wci_Es_mData_w$wget = wci_s_7_MData ; assign tieOff7_wci_Es_mData_w$whas = 1'd1 ; - // submodule appW1 - assign appW1$wciS0_MAddr = wci_s_1_MAddr ; - assign appW1$wciS0_MAddrSpace = wci_s_1_MAddrSpace ; - assign appW1$wciS0_MByteEn = wci_s_1_MByteEn ; - assign appW1$wciS0_MCmd = wci_s_1_MCmd ; - assign appW1$wciS0_MData = wci_s_1_MData ; - assign appW1$wciS0_MFlag = wci_s_1_MFlag ; - assign appW1$wmemiM0_SData = wmemiM0_SData ; - assign appW1$wmemiM0_SResp = wmemiM0_SResp ; - assign appW1$wmemiM0_SRespLast = wmemiM0_SRespLast ; - assign appW1$wmemiM0_SCmdAccept = wmemiM0_SCmdAccept ; - assign appW1$wmemiM0_SDataAccept = wmemiM0_SDataAccept ; - // submodule appW2 assign appW2$wciS0_MAddr = wci_s_2_MAddr ; assign appW2$wciS0_MAddrSpace = wci_s_2_MAddrSpace ; @@ -1807,20 +1921,20 @@ module mkOCApp4B(RST_N_rst_0, assign appW2$wmiM0_SData = wmiM0_SData ; assign appW2$wmiM0_SFlag = wmiM0_SFlag ; assign appW2$wmiM0_SResp = wmiM0_SResp ; - assign appW2$wsiS0_MBurstLength = wsi_s_adc_MBurstLength ; - assign appW2$wsiS0_MByteEn = wsi_s_adc_MByteEn ; - assign appW2$wsiS0_MCmd = wsi_s_adc_MCmd ; - assign appW2$wsiS0_MData = wsi_s_adc_MData ; - assign appW2$wsiS0_MReqInfo = wsi_s_adc_MReqInfo ; + assign appW2$wsiS0_MBurstLength = appW6$wsiM0_MBurstLength ; + assign appW2$wsiS0_MByteEn = appW6$wsiM0_MByteEn ; + assign appW2$wsiS0_MCmd = appW6$wsiM0_MCmd ; + assign appW2$wsiS0_MData = appW6$wsiM0_MData ; + assign appW2$wsiS0_MReqInfo = appW6$wsiM0_MReqInfo ; assign appW2$wmiM0_SThreadBusy = wmiM0_SThreadBusy ; assign appW2$wmiM0_SDataThreadBusy = wmiM0_SDataThreadBusy ; assign appW2$wmiM0_SRespLast = wmiM0_SRespLast ; assign appW2$wmiM0_SReset_n = wmiM0_SReset_n ; - assign appW2$wsiM0_SThreadBusy = appW3$wsiS0_SThreadBusy ; - assign appW2$wsiM0_SReset_n = appW3$wsiS0_SReset_n ; - assign appW2$wsiS0_MReqLast = wsi_s_adc_MReqLast ; - assign appW2$wsiS0_MBurstPrecise = wsi_s_adc_MBurstPrecise ; - assign appW2$wsiS0_MReset_n = wsi_s_adc_MReset_n ; + assign appW2$wsiM0_SThreadBusy = appW5$wsiS0_SThreadBusy ; + assign appW2$wsiM0_SReset_n = appW5$wsiS0_SReset_n ; + assign appW2$wsiS0_MReqLast = appW6$wsiM0_MReqLast ; + assign appW2$wsiS0_MBurstPrecise = appW6$wsiM0_MBurstPrecise ; + assign appW2$wsiS0_MReset_n = appW6$wsiM0_MReset_n ; // submodule appW3 assign appW3$wciS0_MAddr = wci_s_3_MAddr ; @@ -1829,16 +1943,21 @@ module mkOCApp4B(RST_N_rst_0, assign appW3$wciS0_MCmd = wci_s_3_MCmd ; assign appW3$wciS0_MData = wci_s_3_MData ; assign appW3$wciS0_MFlag = wci_s_3_MFlag ; - assign appW3$wsiS0_MBurstLength = appW2$wsiM0_MBurstLength ; - assign appW3$wsiS0_MByteEn = appW2$wsiM0_MByteEn ; - assign appW3$wsiS0_MCmd = appW2$wsiM0_MCmd ; - assign appW3$wsiS0_MData = appW2$wsiM0_MData ; - assign appW3$wsiS0_MReqInfo = appW2$wsiM0_MReqInfo ; - assign appW3$wsiS0_MReqLast = appW2$wsiM0_MReqLast ; - assign appW3$wsiS0_MBurstPrecise = appW2$wsiM0_MBurstPrecise ; - assign appW3$wsiS0_MReset_n = appW2$wsiM0_MReset_n ; + assign appW3$wmemiM0_SData = wmemiM0_SData ; + assign appW3$wmemiM0_SResp = wmemiM0_SResp ; + assign appW3$wsiS0_MBurstLength = appW5$wsiM0_MBurstLength ; + assign appW3$wsiS0_MByteEn = appW5$wsiM0_MByteEn ; + assign appW3$wsiS0_MCmd = appW5$wsiM0_MCmd ; + assign appW3$wsiS0_MData = appW5$wsiM0_MData ; + assign appW3$wsiS0_MReqInfo = appW5$wsiM0_MReqInfo ; + assign appW3$wsiS0_MReqLast = appW5$wsiM0_MReqLast ; + assign appW3$wsiS0_MBurstPrecise = appW5$wsiM0_MBurstPrecise ; + assign appW3$wsiS0_MReset_n = appW5$wsiM0_MReset_n ; assign appW3$wsiM0_SThreadBusy = appW4$wsiS0_SThreadBusy ; assign appW3$wsiM0_SReset_n = appW4$wsiS0_SReset_n ; + assign appW3$wmemiM0_SRespLast = wmemiM0_SRespLast ; + assign appW3$wmemiM0_SCmdAccept = wmemiM0_SCmdAccept ; + assign appW3$wmemiM0_SDataAccept = wmemiM0_SDataAccept ; // submodule appW4 assign appW4$wciS0_MAddr = wci_s_4_MAddr ; @@ -1864,5 +1983,51 @@ module mkOCApp4B(RST_N_rst_0, assign appW4$wsiS0_MReqLast = appW3$wsiM0_MReqLast ; assign appW4$wsiS0_MBurstPrecise = appW3$wsiM0_MBurstPrecise ; assign appW4$wsiS0_MReset_n = appW3$wsiM0_MReset_n ; + + // submodule appW5 + assign appW5$wciS0_MAddr = wci_s_5_MAddr ; + assign appW5$wciS0_MAddrSpace = wci_s_5_MAddrSpace ; + assign appW5$wciS0_MByteEn = wci_s_5_MByteEn ; + assign appW5$wciS0_MCmd = wci_s_5_MCmd ; + assign appW5$wciS0_MData = wci_s_5_MData ; + assign appW5$wciS0_MFlag = wci_s_5_MFlag ; + assign appW5$wsiS0_MBurstLength = appW2$wsiM0_MBurstLength ; + assign appW5$wsiS0_MByteEn = appW2$wsiM0_MByteEn ; + assign appW5$wsiS0_MCmd = appW2$wsiM0_MCmd ; + assign appW5$wsiS0_MData = appW2$wsiM0_MData ; + assign appW5$wsiS0_MReqInfo = appW2$wsiM0_MReqInfo ; + assign appW5$wsiS1_MBurstLength = wsi_s_adc_MBurstLength ; + assign appW5$wsiS1_MByteEn = wsi_s_adc_MByteEn ; + assign appW5$wsiS1_MCmd = wsi_s_adc_MCmd ; + assign appW5$wsiS1_MData = wsi_s_adc_MData ; + assign appW5$wsiS1_MReqInfo = wsi_s_adc_MReqInfo ; + assign appW5$wsiS0_MReqLast = appW2$wsiM0_MReqLast ; + assign appW5$wsiS0_MBurstPrecise = appW2$wsiM0_MBurstPrecise ; + assign appW5$wsiS0_MReset_n = appW2$wsiM0_MReset_n ; + assign appW5$wsiS1_MReqLast = wsi_s_adc_MReqLast ; + assign appW5$wsiS1_MBurstPrecise = wsi_s_adc_MBurstPrecise ; + assign appW5$wsiS1_MReset_n = wsi_s_adc_MReset_n ; + assign appW5$wsiM0_SThreadBusy = appW3$wsiS0_SThreadBusy ; + assign appW5$wsiM0_SReset_n = appW3$wsiS0_SReset_n ; + assign appW5$wsiM1_SThreadBusy = appW6$wsiS0_SThreadBusy ; + assign appW5$wsiM1_SReset_n = appW6$wsiS0_SReset_n ; + + // submodule appW6 + assign appW6$wciS0_MAddr = wci_s_6_MAddr ; + assign appW6$wciS0_MAddrSpace = wci_s_6_MAddrSpace ; + assign appW6$wciS0_MByteEn = wci_s_6_MByteEn ; + assign appW6$wciS0_MCmd = wci_s_6_MCmd ; + assign appW6$wciS0_MData = wci_s_6_MData ; + assign appW6$wciS0_MFlag = wci_s_6_MFlag ; + assign appW6$wsiS0_MBurstLength = appW5$wsiM1_MBurstLength ; + assign appW6$wsiS0_MByteEn = appW5$wsiM1_MByteEn ; + assign appW6$wsiS0_MCmd = appW5$wsiM1_MCmd ; + assign appW6$wsiS0_MData = appW5$wsiM1_MData ; + assign appW6$wsiS0_MReqInfo = appW5$wsiM1_MReqInfo ; + assign appW6$wsiS0_MReqLast = appW5$wsiM1_MReqLast ; + assign appW6$wsiS0_MBurstPrecise = appW5$wsiM1_MBurstPrecise ; + assign appW6$wsiS0_MReset_n = appW5$wsiM1_MReset_n ; + assign appW6$wsiM0_SThreadBusy = appW2$wsiS0_SThreadBusy ; + assign appW6$wsiM0_SReset_n = appW2$wsiS0_SReset_n ; endmodule // mkOCApp4B diff --git a/rtl/mkOCApp4B_scenario3a.v b/rtl/mkOCApp4B_scenario3a.v new file mode 100644 index 00000000..f8d630c9 --- /dev/null +++ b/rtl/mkOCApp4B_scenario3a.v @@ -0,0 +1,2033 @@ +// +// Generated by Bluespec Compiler, version 2012.09.beta1 (build 29570, 2012-09.11) +// +// On Tue Jan 22 07:33:09 EST 2013 +// +// +// Ports: +// Name I/O size props +// wci_s_0_SResp O 2 const +// wci_s_0_SData O 32 const +// wci_s_0_SThreadBusy O 1 const +// wci_s_0_SFlag O 2 const +// wci_s_1_SResp O 2 const +// wci_s_1_SData O 32 const +// wci_s_1_SThreadBusy O 1 const +// wci_s_1_SFlag O 2 const +// wci_s_2_SResp O 2 reg +// wci_s_2_SData O 32 reg +// wci_s_2_SThreadBusy O 1 +// wci_s_2_SFlag O 2 +// wci_s_3_SResp O 2 reg +// wci_s_3_SData O 32 reg +// wci_s_3_SThreadBusy O 1 +// wci_s_3_SFlag O 2 +// wci_s_4_SResp O 2 reg +// wci_s_4_SData O 32 reg +// wci_s_4_SThreadBusy O 1 +// wci_s_4_SFlag O 2 +// wci_s_5_SResp O 2 reg +// wci_s_5_SData O 32 reg +// wci_s_5_SThreadBusy O 1 +// wci_s_5_SFlag O 2 +// wci_s_6_SResp O 2 reg +// wci_s_6_SData O 32 reg +// wci_s_6_SThreadBusy O 1 +// wci_s_6_SFlag O 2 +// wci_s_7_SResp O 2 const +// wci_s_7_SData O 32 const +// wci_s_7_SThreadBusy O 1 const +// wci_s_7_SFlag O 2 const +// wti_s_0_SThreadBusy O 1 const +// wti_s_0_SReset_n O 1 const +// wti_s_1_SThreadBusy O 1 const +// wti_s_1_SReset_n O 1 const +// wti_s_2_SThreadBusy O 1 const +// wti_s_2_SReset_n O 1 const +// wmiM0_MCmd O 3 +// wmiM0_MReqLast O 1 +// wmiM0_MReqInfo O 1 +// wmiM0_MAddrSpace O 1 +// wmiM0_MAddr O 14 +// wmiM0_MBurstLength O 12 +// wmiM0_MDataValid O 1 +// wmiM0_MDataLast O 1 +// wmiM0_MData O 32 +// wmiM0_MDataByteEn O 4 +// wmiM0_MFlag O 32 +// wmiM0_MReset_n O 1 +// wmiM1_MCmd O 3 +// wmiM1_MReqLast O 1 +// wmiM1_MReqInfo O 1 +// wmiM1_MAddrSpace O 1 +// wmiM1_MAddr O 14 +// wmiM1_MBurstLength O 12 +// wmiM1_MDataValid O 1 +// wmiM1_MDataLast O 1 +// wmiM1_MData O 32 +// wmiM1_MDataByteEn O 4 +// wmiM1_MFlag O 32 +// wmiM1_MReset_n O 1 +// wmemiM0_MCmd O 3 reg +// wmemiM0_MReqLast O 1 reg +// wmemiM0_MAddr O 36 reg +// wmemiM0_MBurstLength O 12 reg +// wmemiM0_MDataValid O 1 reg +// wmemiM0_MDataLast O 1 reg +// wmemiM0_MData O 128 reg +// wmemiM0_MDataByteEn O 16 reg +// wmemiM0_MReset_n O 1 +// wsi_s_adc_SThreadBusy O 1 +// wsi_s_adc_SReset_n O 1 +// wsi_m_dac_MCmd O 3 +// wsi_m_dac_MReqLast O 1 +// wsi_m_dac_MBurstPrecise O 1 +// wsi_m_dac_MBurstLength O 12 +// wsi_m_dac_MData O 32 reg +// wsi_m_dac_MByteEn O 4 reg +// wsi_m_dac_MReqInfo O 8 +// wsi_m_dac_MReset_n O 1 +// uuid O 512 const +// RST_N_rst_0 I 1 unused +// RST_N_rst_1 I 1 unused +// RST_N_rst_2 I 1 reset +// RST_N_rst_3 I 1 reset +// RST_N_rst_4 I 1 reset +// RST_N_rst_5 I 1 reset +// RST_N_rst_6 I 1 reset +// RST_N_rst_7 I 1 unused +// CLK I 1 clock +// RST_N I 1 unused +// wci_s_0_MCmd I 3 unused +// wci_s_0_MAddrSpace I 1 unused +// wci_s_0_MByteEn I 4 unused +// wci_s_0_MAddr I 32 unused +// wci_s_0_MData I 32 unused +// wci_s_0_MFlag I 2 unused +// wci_s_1_MCmd I 3 unused +// wci_s_1_MAddrSpace I 1 unused +// wci_s_1_MByteEn I 4 unused +// wci_s_1_MAddr I 32 unused +// wci_s_1_MData I 32 unused +// wci_s_1_MFlag I 2 unused +// wci_s_2_MCmd I 3 +// wci_s_2_MAddrSpace I 1 +// wci_s_2_MByteEn I 4 +// wci_s_2_MAddr I 32 +// wci_s_2_MData I 32 +// wci_s_2_MFlag I 2 unused +// wci_s_3_MCmd I 3 +// wci_s_3_MAddrSpace I 1 +// wci_s_3_MByteEn I 4 +// wci_s_3_MAddr I 32 +// wci_s_3_MData I 32 +// wci_s_3_MFlag I 2 unused +// wci_s_4_MCmd I 3 +// wci_s_4_MAddrSpace I 1 +// wci_s_4_MByteEn I 4 +// wci_s_4_MAddr I 32 +// wci_s_4_MData I 32 +// wci_s_4_MFlag I 2 unused +// wci_s_5_MCmd I 3 +// wci_s_5_MAddrSpace I 1 +// wci_s_5_MByteEn I 4 +// wci_s_5_MAddr I 32 +// wci_s_5_MData I 32 +// wci_s_5_MFlag I 2 unused +// wci_s_6_MCmd I 3 +// wci_s_6_MAddrSpace I 1 +// wci_s_6_MByteEn I 4 +// wci_s_6_MAddr I 32 +// wci_s_6_MData I 32 +// wci_s_6_MFlag I 2 unused +// wci_s_7_MCmd I 3 unused +// wci_s_7_MAddrSpace I 1 unused +// wci_s_7_MByteEn I 4 unused +// wci_s_7_MAddr I 32 unused +// wci_s_7_MData I 32 unused +// wci_s_7_MFlag I 2 unused +// wti_s_0_MCmd I 3 unused +// wti_s_0_MData I 64 unused +// wti_s_1_MCmd I 3 unused +// wti_s_1_MData I 64 unused +// wti_s_2_MCmd I 3 unused +// wti_s_2_MData I 64 unused +// wmiM0_SResp I 2 +// wmiM0_SData I 32 +// wmiM0_SFlag I 32 reg +// wmiM1_SResp I 2 +// wmiM1_SData I 32 +// wmiM1_SFlag I 32 reg +// wmemiM0_SResp I 2 +// wmemiM0_SData I 128 +// wsi_s_adc_MCmd I 3 +// wsi_s_adc_MBurstLength I 12 +// wsi_s_adc_MData I 32 +// wsi_s_adc_MByteEn I 4 +// wsi_s_adc_MReqInfo I 8 +// wmiM0_SThreadBusy I 1 reg +// wmiM0_SDataThreadBusy I 1 reg +// wmiM0_SRespLast I 1 unused +// wmiM0_SReset_n I 1 reg +// wmiM1_SThreadBusy I 1 reg +// wmiM1_SDataThreadBusy I 1 reg +// wmiM1_SRespLast I 1 unused +// wmiM1_SReset_n I 1 reg +// wmemiM0_SRespLast I 1 +// wmemiM0_SCmdAccept I 1 +// wmemiM0_SDataAccept I 1 +// wsi_s_adc_MReqLast I 1 +// wsi_s_adc_MBurstPrecise I 1 +// wsi_s_adc_MReset_n I 1 reg +// wsi_m_dac_SThreadBusy I 1 reg +// wsi_m_dac_SReset_n I 1 reg +// +// No combinational paths from inputs to outputs +// +// + +`ifdef BSV_ASSIGNMENT_DELAY +`else + `define BSV_ASSIGNMENT_DELAY +`endif + +`ifdef BSV_POSITIVE_RESET + `define BSV_RESET_VALUE 1'b1 + `define BSV_RESET_EDGE posedge +`else + `define BSV_RESET_VALUE 1'b0 + `define BSV_RESET_EDGE negedge +`endif + +module mkOCApp4B(RST_N_rst_0, + RST_N_rst_1, + RST_N_rst_2, + RST_N_rst_3, + RST_N_rst_4, + RST_N_rst_5, + RST_N_rst_6, + RST_N_rst_7, + CLK, + RST_N, + + wci_s_0_MCmd, + + wci_s_0_MAddrSpace, + + wci_s_0_MByteEn, + + wci_s_0_MAddr, + + wci_s_0_MData, + + wci_s_0_SResp, + + wci_s_0_SData, + + wci_s_0_SThreadBusy, + + wci_s_0_SFlag, + + wci_s_0_MFlag, + + wci_s_1_MCmd, + + wci_s_1_MAddrSpace, + + wci_s_1_MByteEn, + + wci_s_1_MAddr, + + wci_s_1_MData, + + wci_s_1_SResp, + + wci_s_1_SData, + + wci_s_1_SThreadBusy, + + wci_s_1_SFlag, + + wci_s_1_MFlag, + + wci_s_2_MCmd, + + wci_s_2_MAddrSpace, + + wci_s_2_MByteEn, + + wci_s_2_MAddr, + + wci_s_2_MData, + + wci_s_2_SResp, + + wci_s_2_SData, + + wci_s_2_SThreadBusy, + + wci_s_2_SFlag, + + wci_s_2_MFlag, + + wci_s_3_MCmd, + + wci_s_3_MAddrSpace, + + wci_s_3_MByteEn, + + wci_s_3_MAddr, + + wci_s_3_MData, + + wci_s_3_SResp, + + wci_s_3_SData, + + wci_s_3_SThreadBusy, + + wci_s_3_SFlag, + + wci_s_3_MFlag, + + wci_s_4_MCmd, + + wci_s_4_MAddrSpace, + + wci_s_4_MByteEn, + + wci_s_4_MAddr, + + wci_s_4_MData, + + wci_s_4_SResp, + + wci_s_4_SData, + + wci_s_4_SThreadBusy, + + wci_s_4_SFlag, + + wci_s_4_MFlag, + + wci_s_5_MCmd, + + wci_s_5_MAddrSpace, + + wci_s_5_MByteEn, + + wci_s_5_MAddr, + + wci_s_5_MData, + + wci_s_5_SResp, + + wci_s_5_SData, + + wci_s_5_SThreadBusy, + + wci_s_5_SFlag, + + wci_s_5_MFlag, + + wci_s_6_MCmd, + + wci_s_6_MAddrSpace, + + wci_s_6_MByteEn, + + wci_s_6_MAddr, + + wci_s_6_MData, + + wci_s_6_SResp, + + wci_s_6_SData, + + wci_s_6_SThreadBusy, + + wci_s_6_SFlag, + + wci_s_6_MFlag, + + wci_s_7_MCmd, + + wci_s_7_MAddrSpace, + + wci_s_7_MByteEn, + + wci_s_7_MAddr, + + wci_s_7_MData, + + wci_s_7_SResp, + + wci_s_7_SData, + + wci_s_7_SThreadBusy, + + wci_s_7_SFlag, + + wci_s_7_MFlag, + + wti_s_0_MCmd, + + wti_s_0_MData, + + wti_s_0_SThreadBusy, + + wti_s_0_SReset_n, + + wti_s_1_MCmd, + + wti_s_1_MData, + + wti_s_1_SThreadBusy, + + wti_s_1_SReset_n, + + wti_s_2_MCmd, + + wti_s_2_MData, + + wti_s_2_SThreadBusy, + + wti_s_2_SReset_n, + + wmiM0_MCmd, + + wmiM0_MReqLast, + + wmiM0_MReqInfo, + + wmiM0_MAddrSpace, + + wmiM0_MAddr, + + wmiM0_MBurstLength, + + wmiM0_MDataValid, + + wmiM0_MDataLast, + + wmiM0_MData, + + wmiM0_MDataByteEn, + + wmiM0_SResp, + + wmiM0_SData, + + wmiM0_SThreadBusy, + + wmiM0_SDataThreadBusy, + + wmiM0_SRespLast, + + wmiM0_SFlag, + + wmiM0_MFlag, + + wmiM0_MReset_n, + + wmiM0_SReset_n, + + wmiM1_MCmd, + + wmiM1_MReqLast, + + wmiM1_MReqInfo, + + wmiM1_MAddrSpace, + + wmiM1_MAddr, + + wmiM1_MBurstLength, + + wmiM1_MDataValid, + + wmiM1_MDataLast, + + wmiM1_MData, + + wmiM1_MDataByteEn, + + wmiM1_SResp, + + wmiM1_SData, + + wmiM1_SThreadBusy, + + wmiM1_SDataThreadBusy, + + wmiM1_SRespLast, + + wmiM1_SFlag, + + wmiM1_MFlag, + + wmiM1_MReset_n, + + wmiM1_SReset_n, + + wmemiM0_MCmd, + + wmemiM0_MReqLast, + + wmemiM0_MAddr, + + wmemiM0_MBurstLength, + + wmemiM0_MDataValid, + + wmemiM0_MDataLast, + + wmemiM0_MData, + + wmemiM0_MDataByteEn, + + wmemiM0_SResp, + + wmemiM0_SRespLast, + + wmemiM0_SData, + + wmemiM0_SCmdAccept, + + wmemiM0_SDataAccept, + + wmemiM0_MReset_n, + + wsi_s_adc_MCmd, + + wsi_s_adc_MReqLast, + + wsi_s_adc_MBurstPrecise, + + wsi_s_adc_MBurstLength, + + wsi_s_adc_MData, + + wsi_s_adc_MByteEn, + + wsi_s_adc_MReqInfo, + + wsi_s_adc_SThreadBusy, + + wsi_s_adc_SReset_n, + + wsi_s_adc_MReset_n, + + wsi_m_dac_MCmd, + + wsi_m_dac_MReqLast, + + wsi_m_dac_MBurstPrecise, + + wsi_m_dac_MBurstLength, + + wsi_m_dac_MData, + + wsi_m_dac_MByteEn, + + wsi_m_dac_MReqInfo, + + wsi_m_dac_SThreadBusy, + + wsi_m_dac_MReset_n, + + wsi_m_dac_SReset_n, + + uuid); + parameter [0 : 0] hasDebugLogic = 1'b0; + input RST_N_rst_0; + input RST_N_rst_1; + input RST_N_rst_2; + input RST_N_rst_3; + input RST_N_rst_4; + input RST_N_rst_5; + input RST_N_rst_6; + input RST_N_rst_7; + input CLK; + input RST_N; + + // action method wci_s_0_mCmd + input [2 : 0] wci_s_0_MCmd; + + // action method wci_s_0_mAddrSpace + input wci_s_0_MAddrSpace; + + // action method wci_s_0_mByteEn + input [3 : 0] wci_s_0_MByteEn; + + // action method wci_s_0_mAddr + input [31 : 0] wci_s_0_MAddr; + + // action method wci_s_0_mData + input [31 : 0] wci_s_0_MData; + + // value method wci_s_0_sResp + output [1 : 0] wci_s_0_SResp; + + // value method wci_s_0_sData + output [31 : 0] wci_s_0_SData; + + // value method wci_s_0_sThreadBusy + output wci_s_0_SThreadBusy; + + // value method wci_s_0_sFlag + output [1 : 0] wci_s_0_SFlag; + + // action method wci_s_0_mFlag + input [1 : 0] wci_s_0_MFlag; + + // action method wci_s_1_mCmd + input [2 : 0] wci_s_1_MCmd; + + // action method wci_s_1_mAddrSpace + input wci_s_1_MAddrSpace; + + // action method wci_s_1_mByteEn + input [3 : 0] wci_s_1_MByteEn; + + // action method wci_s_1_mAddr + input [31 : 0] wci_s_1_MAddr; + + // action method wci_s_1_mData + input [31 : 0] wci_s_1_MData; + + // value method wci_s_1_sResp + output [1 : 0] wci_s_1_SResp; + + // value method wci_s_1_sData + output [31 : 0] wci_s_1_SData; + + // value method wci_s_1_sThreadBusy + output wci_s_1_SThreadBusy; + + // value method wci_s_1_sFlag + output [1 : 0] wci_s_1_SFlag; + + // action method wci_s_1_mFlag + input [1 : 0] wci_s_1_MFlag; + + // action method wci_s_2_mCmd + input [2 : 0] wci_s_2_MCmd; + + // action method wci_s_2_mAddrSpace + input wci_s_2_MAddrSpace; + + // action method wci_s_2_mByteEn + input [3 : 0] wci_s_2_MByteEn; + + // action method wci_s_2_mAddr + input [31 : 0] wci_s_2_MAddr; + + // action method wci_s_2_mData + input [31 : 0] wci_s_2_MData; + + // value method wci_s_2_sResp + output [1 : 0] wci_s_2_SResp; + + // value method wci_s_2_sData + output [31 : 0] wci_s_2_SData; + + // value method wci_s_2_sThreadBusy + output wci_s_2_SThreadBusy; + + // value method wci_s_2_sFlag + output [1 : 0] wci_s_2_SFlag; + + // action method wci_s_2_mFlag + input [1 : 0] wci_s_2_MFlag; + + // action method wci_s_3_mCmd + input [2 : 0] wci_s_3_MCmd; + + // action method wci_s_3_mAddrSpace + input wci_s_3_MAddrSpace; + + // action method wci_s_3_mByteEn + input [3 : 0] wci_s_3_MByteEn; + + // action method wci_s_3_mAddr + input [31 : 0] wci_s_3_MAddr; + + // action method wci_s_3_mData + input [31 : 0] wci_s_3_MData; + + // value method wci_s_3_sResp + output [1 : 0] wci_s_3_SResp; + + // value method wci_s_3_sData + output [31 : 0] wci_s_3_SData; + + // value method wci_s_3_sThreadBusy + output wci_s_3_SThreadBusy; + + // value method wci_s_3_sFlag + output [1 : 0] wci_s_3_SFlag; + + // action method wci_s_3_mFlag + input [1 : 0] wci_s_3_MFlag; + + // action method wci_s_4_mCmd + input [2 : 0] wci_s_4_MCmd; + + // action method wci_s_4_mAddrSpace + input wci_s_4_MAddrSpace; + + // action method wci_s_4_mByteEn + input [3 : 0] wci_s_4_MByteEn; + + // action method wci_s_4_mAddr + input [31 : 0] wci_s_4_MAddr; + + // action method wci_s_4_mData + input [31 : 0] wci_s_4_MData; + + // value method wci_s_4_sResp + output [1 : 0] wci_s_4_SResp; + + // value method wci_s_4_sData + output [31 : 0] wci_s_4_SData; + + // value method wci_s_4_sThreadBusy + output wci_s_4_SThreadBusy; + + // value method wci_s_4_sFlag + output [1 : 0] wci_s_4_SFlag; + + // action method wci_s_4_mFlag + input [1 : 0] wci_s_4_MFlag; + + // action method wci_s_5_mCmd + input [2 : 0] wci_s_5_MCmd; + + // action method wci_s_5_mAddrSpace + input wci_s_5_MAddrSpace; + + // action method wci_s_5_mByteEn + input [3 : 0] wci_s_5_MByteEn; + + // action method wci_s_5_mAddr + input [31 : 0] wci_s_5_MAddr; + + // action method wci_s_5_mData + input [31 : 0] wci_s_5_MData; + + // value method wci_s_5_sResp + output [1 : 0] wci_s_5_SResp; + + // value method wci_s_5_sData + output [31 : 0] wci_s_5_SData; + + // value method wci_s_5_sThreadBusy + output wci_s_5_SThreadBusy; + + // value method wci_s_5_sFlag + output [1 : 0] wci_s_5_SFlag; + + // action method wci_s_5_mFlag + input [1 : 0] wci_s_5_MFlag; + + // action method wci_s_6_mCmd + input [2 : 0] wci_s_6_MCmd; + + // action method wci_s_6_mAddrSpace + input wci_s_6_MAddrSpace; + + // action method wci_s_6_mByteEn + input [3 : 0] wci_s_6_MByteEn; + + // action method wci_s_6_mAddr + input [31 : 0] wci_s_6_MAddr; + + // action method wci_s_6_mData + input [31 : 0] wci_s_6_MData; + + // value method wci_s_6_sResp + output [1 : 0] wci_s_6_SResp; + + // value method wci_s_6_sData + output [31 : 0] wci_s_6_SData; + + // value method wci_s_6_sThreadBusy + output wci_s_6_SThreadBusy; + + // value method wci_s_6_sFlag + output [1 : 0] wci_s_6_SFlag; + + // action method wci_s_6_mFlag + input [1 : 0] wci_s_6_MFlag; + + // action method wci_s_7_mCmd + input [2 : 0] wci_s_7_MCmd; + + // action method wci_s_7_mAddrSpace + input wci_s_7_MAddrSpace; + + // action method wci_s_7_mByteEn + input [3 : 0] wci_s_7_MByteEn; + + // action method wci_s_7_mAddr + input [31 : 0] wci_s_7_MAddr; + + // action method wci_s_7_mData + input [31 : 0] wci_s_7_MData; + + // value method wci_s_7_sResp + output [1 : 0] wci_s_7_SResp; + + // value method wci_s_7_sData + output [31 : 0] wci_s_7_SData; + + // value method wci_s_7_sThreadBusy + output wci_s_7_SThreadBusy; + + // value method wci_s_7_sFlag + output [1 : 0] wci_s_7_SFlag; + + // action method wci_s_7_mFlag + input [1 : 0] wci_s_7_MFlag; + + // action method wti_s_0_mCmd + input [2 : 0] wti_s_0_MCmd; + + // action method wti_s_0_mData + input [63 : 0] wti_s_0_MData; + + // value method wti_s_0_sThreadBusy + output wti_s_0_SThreadBusy; + + // value method wti_s_0_sReset_n + output wti_s_0_SReset_n; + + // action method wti_s_1_mCmd + input [2 : 0] wti_s_1_MCmd; + + // action method wti_s_1_mData + input [63 : 0] wti_s_1_MData; + + // value method wti_s_1_sThreadBusy + output wti_s_1_SThreadBusy; + + // value method wti_s_1_sReset_n + output wti_s_1_SReset_n; + + // action method wti_s_2_mCmd + input [2 : 0] wti_s_2_MCmd; + + // action method wti_s_2_mData + input [63 : 0] wti_s_2_MData; + + // value method wti_s_2_sThreadBusy + output wti_s_2_SThreadBusy; + + // value method wti_s_2_sReset_n + output wti_s_2_SReset_n; + + // value method wmiM0_mCmd + output [2 : 0] wmiM0_MCmd; + + // value method wmiM0_mReqLast + output wmiM0_MReqLast; + + // value method wmiM0_mReqInfo + output wmiM0_MReqInfo; + + // value method wmiM0_mAddrSpace + output wmiM0_MAddrSpace; + + // value method wmiM0_mAddr + output [13 : 0] wmiM0_MAddr; + + // value method wmiM0_mBurstLength + output [11 : 0] wmiM0_MBurstLength; + + // value method wmiM0_mDataValid + output wmiM0_MDataValid; + + // value method wmiM0_mDataLast + output wmiM0_MDataLast; + + // value method wmiM0_mData + output [31 : 0] wmiM0_MData; + + // value method wmiM0_mDataInfo + + // value method wmiM0_mDataByteEn + output [3 : 0] wmiM0_MDataByteEn; + + // action method wmiM0_sResp + input [1 : 0] wmiM0_SResp; + + // action method wmiM0_sData + input [31 : 0] wmiM0_SData; + + // action method wmiM0_sThreadBusy + input wmiM0_SThreadBusy; + + // action method wmiM0_sDataThreadBusy + input wmiM0_SDataThreadBusy; + + // action method wmiM0_sRespLast + input wmiM0_SRespLast; + + // action method wmiM0_sFlag + input [31 : 0] wmiM0_SFlag; + + // value method wmiM0_mFlag + output [31 : 0] wmiM0_MFlag; + + // value method wmiM0_mReset_n + output wmiM0_MReset_n; + + // action method wmiM0_sReset_n + input wmiM0_SReset_n; + + // value method wmiM1_mCmd + output [2 : 0] wmiM1_MCmd; + + // value method wmiM1_mReqLast + output wmiM1_MReqLast; + + // value method wmiM1_mReqInfo + output wmiM1_MReqInfo; + + // value method wmiM1_mAddrSpace + output wmiM1_MAddrSpace; + + // value method wmiM1_mAddr + output [13 : 0] wmiM1_MAddr; + + // value method wmiM1_mBurstLength + output [11 : 0] wmiM1_MBurstLength; + + // value method wmiM1_mDataValid + output wmiM1_MDataValid; + + // value method wmiM1_mDataLast + output wmiM1_MDataLast; + + // value method wmiM1_mData + output [31 : 0] wmiM1_MData; + + // value method wmiM1_mDataInfo + + // value method wmiM1_mDataByteEn + output [3 : 0] wmiM1_MDataByteEn; + + // action method wmiM1_sResp + input [1 : 0] wmiM1_SResp; + + // action method wmiM1_sData + input [31 : 0] wmiM1_SData; + + // action method wmiM1_sThreadBusy + input wmiM1_SThreadBusy; + + // action method wmiM1_sDataThreadBusy + input wmiM1_SDataThreadBusy; + + // action method wmiM1_sRespLast + input wmiM1_SRespLast; + + // action method wmiM1_sFlag + input [31 : 0] wmiM1_SFlag; + + // value method wmiM1_mFlag + output [31 : 0] wmiM1_MFlag; + + // value method wmiM1_mReset_n + output wmiM1_MReset_n; + + // action method wmiM1_sReset_n + input wmiM1_SReset_n; + + // value method wmemiM0_mCmd + output [2 : 0] wmemiM0_MCmd; + + // value method wmemiM0_mReqLast + output wmemiM0_MReqLast; + + // value method wmemiM0_mAddr + output [35 : 0] wmemiM0_MAddr; + + // value method wmemiM0_mBurstLength + output [11 : 0] wmemiM0_MBurstLength; + + // value method wmemiM0_mDataValid + output wmemiM0_MDataValid; + + // value method wmemiM0_mDataLast + output wmemiM0_MDataLast; + + // value method wmemiM0_mData + output [127 : 0] wmemiM0_MData; + + // value method wmemiM0_mDataByteEn + output [15 : 0] wmemiM0_MDataByteEn; + + // action method wmemiM0_sResp + input [1 : 0] wmemiM0_SResp; + + // action method wmemiM0_sRespLast + input wmemiM0_SRespLast; + + // action method wmemiM0_sData + input [127 : 0] wmemiM0_SData; + + // action method wmemiM0_sCmdAccept + input wmemiM0_SCmdAccept; + + // action method wmemiM0_sDataAccept + input wmemiM0_SDataAccept; + + // value method wmemiM0_mReset_n + output wmemiM0_MReset_n; + + // action method wsi_s_adc_mCmd + input [2 : 0] wsi_s_adc_MCmd; + + // action method wsi_s_adc_mReqLast + input wsi_s_adc_MReqLast; + + // action method wsi_s_adc_mBurstPrecise + input wsi_s_adc_MBurstPrecise; + + // action method wsi_s_adc_mBurstLength + input [11 : 0] wsi_s_adc_MBurstLength; + + // action method wsi_s_adc_mData + input [31 : 0] wsi_s_adc_MData; + + // action method wsi_s_adc_mByteEn + input [3 : 0] wsi_s_adc_MByteEn; + + // action method wsi_s_adc_mReqInfo + input [7 : 0] wsi_s_adc_MReqInfo; + + // action method wsi_s_adc_mDataInfo + + // value method wsi_s_adc_sThreadBusy + output wsi_s_adc_SThreadBusy; + + // value method wsi_s_adc_sReset_n + output wsi_s_adc_SReset_n; + + // action method wsi_s_adc_mReset_n + input wsi_s_adc_MReset_n; + + // value method wsi_m_dac_mCmd + output [2 : 0] wsi_m_dac_MCmd; + + // value method wsi_m_dac_mReqLast + output wsi_m_dac_MReqLast; + + // value method wsi_m_dac_mBurstPrecise + output wsi_m_dac_MBurstPrecise; + + // value method wsi_m_dac_mBurstLength + output [11 : 0] wsi_m_dac_MBurstLength; + + // value method wsi_m_dac_mData + output [31 : 0] wsi_m_dac_MData; + + // value method wsi_m_dac_mByteEn + output [3 : 0] wsi_m_dac_MByteEn; + + // value method wsi_m_dac_mReqInfo + output [7 : 0] wsi_m_dac_MReqInfo; + + // value method wsi_m_dac_mDataInfo + + // action method wsi_m_dac_sThreadBusy + input wsi_m_dac_SThreadBusy; + + // value method wsi_m_dac_mReset_n + output wsi_m_dac_MReset_n; + + // action method wsi_m_dac_sReset_n + input wsi_m_dac_SReset_n; + + // value method uuid + output [511 : 0] uuid; + + // signals for module outputs + wire [511 : 0] uuid; + wire [127 : 0] wmemiM0_MData; + wire [35 : 0] wmemiM0_MAddr; + wire [31 : 0] wci_s_0_SData, + wci_s_1_SData, + wci_s_2_SData, + wci_s_3_SData, + wci_s_4_SData, + wci_s_5_SData, + wci_s_6_SData, + wci_s_7_SData, + wmiM0_MData, + wmiM0_MFlag, + wmiM1_MData, + wmiM1_MFlag, + wsi_m_dac_MData; + wire [15 : 0] wmemiM0_MDataByteEn; + wire [13 : 0] wmiM0_MAddr, wmiM1_MAddr; + wire [11 : 0] wmemiM0_MBurstLength, + wmiM0_MBurstLength, + wmiM1_MBurstLength, + wsi_m_dac_MBurstLength; + wire [7 : 0] wsi_m_dac_MReqInfo; + wire [3 : 0] wmiM0_MDataByteEn, wmiM1_MDataByteEn, wsi_m_dac_MByteEn; + wire [2 : 0] wmemiM0_MCmd, wmiM0_MCmd, wmiM1_MCmd, wsi_m_dac_MCmd; + wire [1 : 0] wci_s_0_SFlag, + wci_s_0_SResp, + wci_s_1_SFlag, + wci_s_1_SResp, + wci_s_2_SFlag, + wci_s_2_SResp, + wci_s_3_SFlag, + wci_s_3_SResp, + wci_s_4_SFlag, + wci_s_4_SResp, + wci_s_5_SFlag, + wci_s_5_SResp, + wci_s_6_SFlag, + wci_s_6_SResp, + wci_s_7_SFlag, + wci_s_7_SResp; + wire wci_s_0_SThreadBusy, + wci_s_1_SThreadBusy, + wci_s_2_SThreadBusy, + wci_s_3_SThreadBusy, + wci_s_4_SThreadBusy, + wci_s_5_SThreadBusy, + wci_s_6_SThreadBusy, + wci_s_7_SThreadBusy, + wmemiM0_MDataLast, + wmemiM0_MDataValid, + wmemiM0_MReqLast, + wmemiM0_MReset_n, + wmiM0_MAddrSpace, + wmiM0_MDataLast, + wmiM0_MDataValid, + wmiM0_MReqInfo, + wmiM0_MReqLast, + wmiM0_MReset_n, + wmiM1_MAddrSpace, + wmiM1_MDataLast, + wmiM1_MDataValid, + wmiM1_MReqInfo, + wmiM1_MReqLast, + wmiM1_MReset_n, + wsi_m_dac_MBurstPrecise, + wsi_m_dac_MReqLast, + wsi_m_dac_MReset_n, + wsi_s_adc_SReset_n, + wsi_s_adc_SThreadBusy, + wti_s_0_SReset_n, + wti_s_0_SThreadBusy, + wti_s_1_SReset_n, + wti_s_1_SThreadBusy, + wti_s_2_SReset_n, + wti_s_2_SThreadBusy; + + // inlined wires + wire [31 : 0] tieOff0_wci_Es_mAddr_w$wget, + tieOff0_wci_Es_mData_w$wget, + tieOff1_wci_Es_mAddr_w$wget, + tieOff1_wci_Es_mData_w$wget, + tieOff7_wci_Es_mAddr_w$wget, + tieOff7_wci_Es_mData_w$wget; + wire [3 : 0] tieOff0_wci_Es_mByteEn_w$wget, + tieOff1_wci_Es_mByteEn_w$wget, + tieOff7_wci_Es_mByteEn_w$wget; + wire [2 : 0] tieOff0_wci_Es_mCmd_w$wget, + tieOff1_wci_Es_mCmd_w$wget, + tieOff7_wci_Es_mCmd_w$wget; + wire tieOff0_wci_Es_mAddrSpace_w$wget, + tieOff0_wci_Es_mAddrSpace_w$whas, + tieOff0_wci_Es_mAddr_w$whas, + tieOff0_wci_Es_mByteEn_w$whas, + tieOff0_wci_Es_mCmd_w$whas, + tieOff0_wci_Es_mData_w$whas, + tieOff1_wci_Es_mAddrSpace_w$wget, + tieOff1_wci_Es_mAddrSpace_w$whas, + tieOff1_wci_Es_mAddr_w$whas, + tieOff1_wci_Es_mByteEn_w$whas, + tieOff1_wci_Es_mCmd_w$whas, + tieOff1_wci_Es_mData_w$whas, + tieOff7_wci_Es_mAddrSpace_w$wget, + tieOff7_wci_Es_mAddrSpace_w$whas, + tieOff7_wci_Es_mAddr_w$whas, + tieOff7_wci_Es_mByteEn_w$whas, + tieOff7_wci_Es_mCmd_w$whas, + tieOff7_wci_Es_mData_w$whas; + + // ports of submodule appW2 + wire [31 : 0] appW2$wciS0_MAddr, + appW2$wciS0_MData, + appW2$wciS0_SData, + appW2$wmiM0_MData, + appW2$wmiM0_MFlag, + appW2$wmiM0_SData, + appW2$wmiM0_SFlag, + appW2$wsiM0_MData, + appW2$wsiS0_MData; + wire [13 : 0] appW2$wmiM0_MAddr; + wire [11 : 0] appW2$wmiM0_MBurstLength, + appW2$wsiM0_MBurstLength, + appW2$wsiS0_MBurstLength; + wire [7 : 0] appW2$wsiM0_MReqInfo, appW2$wsiS0_MReqInfo; + wire [3 : 0] appW2$wciS0_MByteEn, + appW2$wmiM0_MDataByteEn, + appW2$wsiM0_MByteEn, + appW2$wsiS0_MByteEn; + wire [2 : 0] appW2$wciS0_MCmd, + appW2$wmiM0_MCmd, + appW2$wsiM0_MCmd, + appW2$wsiS0_MCmd; + wire [1 : 0] appW2$wciS0_MFlag, + appW2$wciS0_SFlag, + appW2$wciS0_SResp, + appW2$wmiM0_SResp; + wire appW2$wciS0_MAddrSpace, + appW2$wciS0_SThreadBusy, + appW2$wmiM0_MAddrSpace, + appW2$wmiM0_MDataLast, + appW2$wmiM0_MDataValid, + appW2$wmiM0_MReqInfo, + appW2$wmiM0_MReqLast, + appW2$wmiM0_MReset_n, + appW2$wmiM0_SDataThreadBusy, + appW2$wmiM0_SReset_n, + appW2$wmiM0_SRespLast, + appW2$wmiM0_SThreadBusy, + appW2$wsiM0_MBurstPrecise, + appW2$wsiM0_MReqLast, + appW2$wsiM0_MReset_n, + appW2$wsiM0_SReset_n, + appW2$wsiM0_SThreadBusy, + appW2$wsiS0_MBurstPrecise, + appW2$wsiS0_MReqLast, + appW2$wsiS0_MReset_n, + appW2$wsiS0_SReset_n, + appW2$wsiS0_SThreadBusy; + + // ports of submodule appW3 + wire [127 : 0] appW3$wmemiM0_MData, appW3$wmemiM0_SData; + wire [35 : 0] appW3$wmemiM0_MAddr; + wire [31 : 0] appW3$wciS0_MAddr, + appW3$wciS0_MData, + appW3$wciS0_SData, + appW3$wsiM0_MData, + appW3$wsiS0_MData; + wire [15 : 0] appW3$wmemiM0_MDataByteEn; + wire [11 : 0] appW3$wmemiM0_MBurstLength, + appW3$wsiM0_MBurstLength, + appW3$wsiS0_MBurstLength; + wire [7 : 0] appW3$wsiM0_MReqInfo, appW3$wsiS0_MReqInfo; + wire [3 : 0] appW3$wciS0_MByteEn, appW3$wsiM0_MByteEn, appW3$wsiS0_MByteEn; + wire [2 : 0] appW3$wciS0_MCmd, + appW3$wmemiM0_MCmd, + appW3$wsiM0_MCmd, + appW3$wsiS0_MCmd; + wire [1 : 0] appW3$wciS0_MFlag, + appW3$wciS0_SFlag, + appW3$wciS0_SResp, + appW3$wmemiM0_SResp; + wire appW3$wciS0_MAddrSpace, + appW3$wciS0_SThreadBusy, + appW3$wmemiM0_MDataLast, + appW3$wmemiM0_MDataValid, + appW3$wmemiM0_MReqLast, + appW3$wmemiM0_MReset_n, + appW3$wmemiM0_SCmdAccept, + appW3$wmemiM0_SDataAccept, + appW3$wmemiM0_SRespLast, + appW3$wsiM0_MBurstPrecise, + appW3$wsiM0_MReqLast, + appW3$wsiM0_MReset_n, + appW3$wsiM0_SReset_n, + appW3$wsiM0_SThreadBusy, + appW3$wsiS0_MBurstPrecise, + appW3$wsiS0_MReqLast, + appW3$wsiS0_MReset_n, + appW3$wsiS0_SReset_n, + appW3$wsiS0_SThreadBusy; + + // ports of submodule appW4 + wire [31 : 0] appW4$wciS0_MAddr, + appW4$wciS0_MData, + appW4$wciS0_SData, + appW4$wmiM0_MData, + appW4$wmiM0_MFlag, + appW4$wmiM0_SData, + appW4$wmiM0_SFlag, + appW4$wsiM0_MData, + appW4$wsiS0_MData; + wire [13 : 0] appW4$wmiM0_MAddr; + wire [11 : 0] appW4$wmiM0_MBurstLength, + appW4$wsiM0_MBurstLength, + appW4$wsiS0_MBurstLength; + wire [7 : 0] appW4$wsiM0_MReqInfo, appW4$wsiS0_MReqInfo; + wire [3 : 0] appW4$wciS0_MByteEn, + appW4$wmiM0_MDataByteEn, + appW4$wsiM0_MByteEn, + appW4$wsiS0_MByteEn; + wire [2 : 0] appW4$wciS0_MCmd, + appW4$wmiM0_MCmd, + appW4$wsiM0_MCmd, + appW4$wsiS0_MCmd; + wire [1 : 0] appW4$wciS0_MFlag, + appW4$wciS0_SFlag, + appW4$wciS0_SResp, + appW4$wmiM0_SResp; + wire appW4$wciS0_MAddrSpace, + appW4$wciS0_SThreadBusy, + appW4$wmiM0_MAddrSpace, + appW4$wmiM0_MDataLast, + appW4$wmiM0_MDataValid, + appW4$wmiM0_MReqInfo, + appW4$wmiM0_MReqLast, + appW4$wmiM0_MReset_n, + appW4$wmiM0_SDataThreadBusy, + appW4$wmiM0_SReset_n, + appW4$wmiM0_SRespLast, + appW4$wmiM0_SThreadBusy, + appW4$wsiM0_MBurstPrecise, + appW4$wsiM0_MReqLast, + appW4$wsiM0_MReset_n, + appW4$wsiM0_SReset_n, + appW4$wsiM0_SThreadBusy, + appW4$wsiS0_MBurstPrecise, + appW4$wsiS0_MReqLast, + appW4$wsiS0_MReset_n, + appW4$wsiS0_SReset_n, + appW4$wsiS0_SThreadBusy; + + // ports of submodule appW5 + wire [31 : 0] appW5$wciS0_MAddr, + appW5$wciS0_MData, + appW5$wciS0_SData, + appW5$wsiM0_MData, + appW5$wsiM1_MData, + appW5$wsiS0_MData, + appW5$wsiS1_MData; + wire [11 : 0] appW5$wsiM0_MBurstLength, + appW5$wsiM1_MBurstLength, + appW5$wsiS0_MBurstLength, + appW5$wsiS1_MBurstLength; + wire [7 : 0] appW5$wsiM0_MReqInfo, + appW5$wsiM1_MReqInfo, + appW5$wsiS0_MReqInfo, + appW5$wsiS1_MReqInfo; + wire [3 : 0] appW5$wciS0_MByteEn, + appW5$wsiM0_MByteEn, + appW5$wsiM1_MByteEn, + appW5$wsiS0_MByteEn, + appW5$wsiS1_MByteEn; + wire [2 : 0] appW5$wciS0_MCmd, + appW5$wsiM0_MCmd, + appW5$wsiM1_MCmd, + appW5$wsiS0_MCmd, + appW5$wsiS1_MCmd; + wire [1 : 0] appW5$wciS0_MFlag, appW5$wciS0_SFlag, appW5$wciS0_SResp; + wire appW5$wciS0_MAddrSpace, + appW5$wciS0_SThreadBusy, + appW5$wsiM0_MBurstPrecise, + appW5$wsiM0_MReqLast, + appW5$wsiM0_MReset_n, + appW5$wsiM0_SReset_n, + appW5$wsiM0_SThreadBusy, + appW5$wsiM1_MBurstPrecise, + appW5$wsiM1_MReqLast, + appW5$wsiM1_MReset_n, + appW5$wsiM1_SReset_n, + appW5$wsiM1_SThreadBusy, + appW5$wsiS0_MBurstPrecise, + appW5$wsiS0_MReqLast, + appW5$wsiS0_MReset_n, + appW5$wsiS0_SReset_n, + appW5$wsiS0_SThreadBusy, + appW5$wsiS1_MBurstPrecise, + appW5$wsiS1_MReqLast, + appW5$wsiS1_MReset_n, + appW5$wsiS1_SReset_n, + appW5$wsiS1_SThreadBusy; + + // ports of submodule appW6 + wire [31 : 0] appW6$wciS0_MAddr, + appW6$wciS0_MData, + appW6$wciS0_SData, + appW6$wsiM0_MData, + appW6$wsiS0_MData; + wire [11 : 0] appW6$wsiM0_MBurstLength, appW6$wsiS0_MBurstLength; + wire [7 : 0] appW6$wsiM0_MReqInfo, appW6$wsiS0_MReqInfo; + wire [3 : 0] appW6$wciS0_MByteEn, appW6$wsiM0_MByteEn, appW6$wsiS0_MByteEn; + wire [2 : 0] appW6$wciS0_MCmd, appW6$wsiM0_MCmd, appW6$wsiS0_MCmd; + wire [1 : 0] appW6$wciS0_MFlag, appW6$wciS0_SFlag, appW6$wciS0_SResp; + wire appW6$wciS0_MAddrSpace, + appW6$wciS0_SThreadBusy, + appW6$wsiM0_MBurstPrecise, + appW6$wsiM0_MReqLast, + appW6$wsiM0_MReset_n, + appW6$wsiM0_SReset_n, + appW6$wsiM0_SThreadBusy, + appW6$wsiS0_MBurstPrecise, + appW6$wsiS0_MReqLast, + appW6$wsiS0_MReset_n, + appW6$wsiS0_SReset_n, + appW6$wsiS0_SThreadBusy; + + // ports of submodule id + wire [511 : 0] id$uuid; + + // value method wci_s_0_sResp + assign wci_s_0_SResp = 2'd0 ; + + // value method wci_s_0_sData + assign wci_s_0_SData = 32'hAAAAAAAA ; + + // value method wci_s_0_sThreadBusy + assign wci_s_0_SThreadBusy = 1'd1 ; + + // value method wci_s_0_sFlag + assign wci_s_0_SFlag = 2'b0 ; + + // value method wci_s_1_sResp + assign wci_s_1_SResp = 2'd0 ; + + // value method wci_s_1_sData + assign wci_s_1_SData = 32'hAAAAAAAA ; + + // value method wci_s_1_sThreadBusy + assign wci_s_1_SThreadBusy = 1'd1 ; + + // value method wci_s_1_sFlag + assign wci_s_1_SFlag = 2'b0 ; + + // value method wci_s_2_sResp + assign wci_s_2_SResp = appW2$wciS0_SResp ; + + // value method wci_s_2_sData + assign wci_s_2_SData = appW2$wciS0_SData ; + + // value method wci_s_2_sThreadBusy + assign wci_s_2_SThreadBusy = appW2$wciS0_SThreadBusy ; + + // value method wci_s_2_sFlag + assign wci_s_2_SFlag = appW2$wciS0_SFlag ; + + // value method wci_s_3_sResp + assign wci_s_3_SResp = appW3$wciS0_SResp ; + + // value method wci_s_3_sData + assign wci_s_3_SData = appW3$wciS0_SData ; + + // value method wci_s_3_sThreadBusy + assign wci_s_3_SThreadBusy = appW3$wciS0_SThreadBusy ; + + // value method wci_s_3_sFlag + assign wci_s_3_SFlag = appW3$wciS0_SFlag ; + + // value method wci_s_4_sResp + assign wci_s_4_SResp = appW4$wciS0_SResp ; + + // value method wci_s_4_sData + assign wci_s_4_SData = appW4$wciS0_SData ; + + // value method wci_s_4_sThreadBusy + assign wci_s_4_SThreadBusy = appW4$wciS0_SThreadBusy ; + + // value method wci_s_4_sFlag + assign wci_s_4_SFlag = appW4$wciS0_SFlag ; + + // value method wci_s_5_sResp + assign wci_s_5_SResp = appW5$wciS0_SResp ; + + // value method wci_s_5_sData + assign wci_s_5_SData = appW5$wciS0_SData ; + + // value method wci_s_5_sThreadBusy + assign wci_s_5_SThreadBusy = appW5$wciS0_SThreadBusy ; + + // value method wci_s_5_sFlag + assign wci_s_5_SFlag = appW5$wciS0_SFlag ; + + // value method wci_s_6_sResp + assign wci_s_6_SResp = appW6$wciS0_SResp ; + + // value method wci_s_6_sData + assign wci_s_6_SData = appW6$wciS0_SData ; + + // value method wci_s_6_sThreadBusy + assign wci_s_6_SThreadBusy = appW6$wciS0_SThreadBusy ; + + // value method wci_s_6_sFlag + assign wci_s_6_SFlag = appW6$wciS0_SFlag ; + + // value method wci_s_7_sResp + assign wci_s_7_SResp = 2'd0 ; + + // value method wci_s_7_sData + assign wci_s_7_SData = 32'hAAAAAAAA ; + + // value method wci_s_7_sThreadBusy + assign wci_s_7_SThreadBusy = 1'd1 ; + + // value method wci_s_7_sFlag + assign wci_s_7_SFlag = 2'b0 ; + + // value method wti_s_0_sThreadBusy + assign wti_s_0_SThreadBusy = 1'h0 ; + + // value method wti_s_0_sReset_n + assign wti_s_0_SReset_n = 1'h0 ; + + // value method wti_s_1_sThreadBusy + assign wti_s_1_SThreadBusy = 1'h0 ; + + // value method wti_s_1_sReset_n + assign wti_s_1_SReset_n = 1'h0 ; + + // value method wti_s_2_sThreadBusy + assign wti_s_2_SThreadBusy = 1'h0 ; + + // value method wti_s_2_sReset_n + assign wti_s_2_SReset_n = 1'h0 ; + + // value method wmiM0_mCmd + assign wmiM0_MCmd = appW2$wmiM0_MCmd ; + + // value method wmiM0_mReqLast + assign wmiM0_MReqLast = appW2$wmiM0_MReqLast ; + + // value method wmiM0_mReqInfo + assign wmiM0_MReqInfo = appW2$wmiM0_MReqInfo ; + + // value method wmiM0_mAddrSpace + assign wmiM0_MAddrSpace = appW2$wmiM0_MAddrSpace ; + + // value method wmiM0_mAddr + assign wmiM0_MAddr = appW2$wmiM0_MAddr ; + + // value method wmiM0_mBurstLength + assign wmiM0_MBurstLength = appW2$wmiM0_MBurstLength ; + + // value method wmiM0_mDataValid + assign wmiM0_MDataValid = appW2$wmiM0_MDataValid ; + + // value method wmiM0_mDataLast + assign wmiM0_MDataLast = appW2$wmiM0_MDataLast ; + + // value method wmiM0_mData + assign wmiM0_MData = appW2$wmiM0_MData ; + + // value method wmiM0_mDataByteEn + assign wmiM0_MDataByteEn = appW2$wmiM0_MDataByteEn ; + + // value method wmiM0_mFlag + assign wmiM0_MFlag = appW2$wmiM0_MFlag ; + + // value method wmiM0_mReset_n + assign wmiM0_MReset_n = appW2$wmiM0_MReset_n ; + + // value method wmiM1_mCmd + assign wmiM1_MCmd = appW4$wmiM0_MCmd ; + + // value method wmiM1_mReqLast + assign wmiM1_MReqLast = appW4$wmiM0_MReqLast ; + + // value method wmiM1_mReqInfo + assign wmiM1_MReqInfo = appW4$wmiM0_MReqInfo ; + + // value method wmiM1_mAddrSpace + assign wmiM1_MAddrSpace = appW4$wmiM0_MAddrSpace ; + + // value method wmiM1_mAddr + assign wmiM1_MAddr = appW4$wmiM0_MAddr ; + + // value method wmiM1_mBurstLength + assign wmiM1_MBurstLength = appW4$wmiM0_MBurstLength ; + + // value method wmiM1_mDataValid + assign wmiM1_MDataValid = appW4$wmiM0_MDataValid ; + + // value method wmiM1_mDataLast + assign wmiM1_MDataLast = appW4$wmiM0_MDataLast ; + + // value method wmiM1_mData + assign wmiM1_MData = appW4$wmiM0_MData ; + + // value method wmiM1_mDataByteEn + assign wmiM1_MDataByteEn = appW4$wmiM0_MDataByteEn ; + + // value method wmiM1_mFlag + assign wmiM1_MFlag = appW4$wmiM0_MFlag ; + + // value method wmiM1_mReset_n + assign wmiM1_MReset_n = appW4$wmiM0_MReset_n ; + + // value method wmemiM0_mCmd + assign wmemiM0_MCmd = appW3$wmemiM0_MCmd ; + + // value method wmemiM0_mReqLast + assign wmemiM0_MReqLast = appW3$wmemiM0_MReqLast ; + + // value method wmemiM0_mAddr + assign wmemiM0_MAddr = appW3$wmemiM0_MAddr ; + + // value method wmemiM0_mBurstLength + assign wmemiM0_MBurstLength = appW3$wmemiM0_MBurstLength ; + + // value method wmemiM0_mDataValid + assign wmemiM0_MDataValid = appW3$wmemiM0_MDataValid ; + + // value method wmemiM0_mDataLast + assign wmemiM0_MDataLast = appW3$wmemiM0_MDataLast ; + + // value method wmemiM0_mData + assign wmemiM0_MData = appW3$wmemiM0_MData ; + + // value method wmemiM0_mDataByteEn + assign wmemiM0_MDataByteEn = appW3$wmemiM0_MDataByteEn ; + + // value method wmemiM0_mReset_n + assign wmemiM0_MReset_n = appW3$wmemiM0_MReset_n ; + + // value method wsi_s_adc_sThreadBusy + assign wsi_s_adc_SThreadBusy = appW5$wsiS1_SThreadBusy ; + + // value method wsi_s_adc_sReset_n + assign wsi_s_adc_SReset_n = appW5$wsiS1_SReset_n ; + + // value method wsi_m_dac_mCmd + assign wsi_m_dac_MCmd = appW4$wsiM0_MCmd ; + + // value method wsi_m_dac_mReqLast + assign wsi_m_dac_MReqLast = appW4$wsiM0_MReqLast ; + + // value method wsi_m_dac_mBurstPrecise + assign wsi_m_dac_MBurstPrecise = appW4$wsiM0_MBurstPrecise ; + + // value method wsi_m_dac_mBurstLength + assign wsi_m_dac_MBurstLength = appW4$wsiM0_MBurstLength ; + + // value method wsi_m_dac_mData + assign wsi_m_dac_MData = appW4$wsiM0_MData ; + + // value method wsi_m_dac_mByteEn + assign wsi_m_dac_MByteEn = appW4$wsiM0_MByteEn ; + + // value method wsi_m_dac_mReqInfo + assign wsi_m_dac_MReqInfo = appW4$wsiM0_MReqInfo ; + + // value method wsi_m_dac_mReset_n + assign wsi_m_dac_MReset_n = appW4$wsiM0_MReset_n ; + + // value method uuid + assign uuid = id$uuid ; + + // submodule appW2 + mkSMAdapter4B #(.smaCtrlInit(32'h00000001), + .hasDebugLogic(hasDebugLogic)) appW2(.wciS0_Clk(CLK), + .wciS0_MReset_n(RST_N_rst_2), + .wciS0_MAddr(appW2$wciS0_MAddr), + .wciS0_MAddrSpace(appW2$wciS0_MAddrSpace), + .wciS0_MByteEn(appW2$wciS0_MByteEn), + .wciS0_MCmd(appW2$wciS0_MCmd), + .wciS0_MData(appW2$wciS0_MData), + .wciS0_MFlag(appW2$wciS0_MFlag), + .wmiM0_SData(appW2$wmiM0_SData), + .wmiM0_SFlag(appW2$wmiM0_SFlag), + .wmiM0_SResp(appW2$wmiM0_SResp), + .wsiS0_MBurstLength(appW2$wsiS0_MBurstLength), + .wsiS0_MByteEn(appW2$wsiS0_MByteEn), + .wsiS0_MCmd(appW2$wsiS0_MCmd), + .wsiS0_MData(appW2$wsiS0_MData), + .wsiS0_MReqInfo(appW2$wsiS0_MReqInfo), + .wmiM0_SThreadBusy(appW2$wmiM0_SThreadBusy), + .wmiM0_SDataThreadBusy(appW2$wmiM0_SDataThreadBusy), + .wmiM0_SRespLast(appW2$wmiM0_SRespLast), + .wmiM0_SReset_n(appW2$wmiM0_SReset_n), + .wsiM0_SThreadBusy(appW2$wsiM0_SThreadBusy), + .wsiM0_SReset_n(appW2$wsiM0_SReset_n), + .wsiS0_MReqLast(appW2$wsiS0_MReqLast), + .wsiS0_MBurstPrecise(appW2$wsiS0_MBurstPrecise), + .wsiS0_MReset_n(appW2$wsiS0_MReset_n), + .wciS0_SResp(appW2$wciS0_SResp), + .wciS0_SData(appW2$wciS0_SData), + .wciS0_SThreadBusy(appW2$wciS0_SThreadBusy), + .wciS0_SFlag(appW2$wciS0_SFlag), + .wmiM0_MCmd(appW2$wmiM0_MCmd), + .wmiM0_MReqLast(appW2$wmiM0_MReqLast), + .wmiM0_MReqInfo(appW2$wmiM0_MReqInfo), + .wmiM0_MAddrSpace(appW2$wmiM0_MAddrSpace), + .wmiM0_MAddr(appW2$wmiM0_MAddr), + .wmiM0_MBurstLength(appW2$wmiM0_MBurstLength), + .wmiM0_MDataValid(appW2$wmiM0_MDataValid), + .wmiM0_MDataLast(appW2$wmiM0_MDataLast), + .wmiM0_MData(appW2$wmiM0_MData), + .wmiM0_MDataByteEn(appW2$wmiM0_MDataByteEn), + .wmiM0_MFlag(appW2$wmiM0_MFlag), + .wmiM0_MReset_n(appW2$wmiM0_MReset_n), + .wsiM0_MCmd(appW2$wsiM0_MCmd), + .wsiM0_MReqLast(appW2$wsiM0_MReqLast), + .wsiM0_MBurstPrecise(appW2$wsiM0_MBurstPrecise), + .wsiM0_MBurstLength(appW2$wsiM0_MBurstLength), + .wsiM0_MData(appW2$wsiM0_MData), + .wsiM0_MByteEn(appW2$wsiM0_MByteEn), + .wsiM0_MReqInfo(appW2$wsiM0_MReqInfo), + .wsiM0_MReset_n(appW2$wsiM0_MReset_n), + .wsiS0_SThreadBusy(appW2$wsiS0_SThreadBusy), + .wsiS0_SReset_n(appW2$wsiS0_SReset_n)); + + // submodule appW3 + mkDelayWorker4B #(.dlyCtrlInit(32'h0), + .hasDebugLogic(hasDebugLogic)) appW3(.wciS0_Clk(CLK), + .wciS0_MReset_n(RST_N_rst_3), + .wciS0_MAddr(appW3$wciS0_MAddr), + .wciS0_MAddrSpace(appW3$wciS0_MAddrSpace), + .wciS0_MByteEn(appW3$wciS0_MByteEn), + .wciS0_MCmd(appW3$wciS0_MCmd), + .wciS0_MData(appW3$wciS0_MData), + .wciS0_MFlag(appW3$wciS0_MFlag), + .wmemiM0_SData(appW3$wmemiM0_SData), + .wmemiM0_SResp(appW3$wmemiM0_SResp), + .wsiS0_MBurstLength(appW3$wsiS0_MBurstLength), + .wsiS0_MByteEn(appW3$wsiS0_MByteEn), + .wsiS0_MCmd(appW3$wsiS0_MCmd), + .wsiS0_MData(appW3$wsiS0_MData), + .wsiS0_MReqInfo(appW3$wsiS0_MReqInfo), + .wsiS0_MReqLast(appW3$wsiS0_MReqLast), + .wsiS0_MBurstPrecise(appW3$wsiS0_MBurstPrecise), + .wsiS0_MReset_n(appW3$wsiS0_MReset_n), + .wsiM0_SThreadBusy(appW3$wsiM0_SThreadBusy), + .wsiM0_SReset_n(appW3$wsiM0_SReset_n), + .wmemiM0_SRespLast(appW3$wmemiM0_SRespLast), + .wmemiM0_SCmdAccept(appW3$wmemiM0_SCmdAccept), + .wmemiM0_SDataAccept(appW3$wmemiM0_SDataAccept), + .wciS0_SResp(appW3$wciS0_SResp), + .wciS0_SData(appW3$wciS0_SData), + .wciS0_SThreadBusy(appW3$wciS0_SThreadBusy), + .wciS0_SFlag(appW3$wciS0_SFlag), + .wsiS0_SThreadBusy(appW3$wsiS0_SThreadBusy), + .wsiS0_SReset_n(appW3$wsiS0_SReset_n), + .wsiM0_MCmd(appW3$wsiM0_MCmd), + .wsiM0_MReqLast(appW3$wsiM0_MReqLast), + .wsiM0_MBurstPrecise(appW3$wsiM0_MBurstPrecise), + .wsiM0_MBurstLength(appW3$wsiM0_MBurstLength), + .wsiM0_MData(appW3$wsiM0_MData), + .wsiM0_MByteEn(appW3$wsiM0_MByteEn), + .wsiM0_MReqInfo(appW3$wsiM0_MReqInfo), + .wsiM0_MReset_n(appW3$wsiM0_MReset_n), + .wmemiM0_MCmd(appW3$wmemiM0_MCmd), + .wmemiM0_MReqLast(appW3$wmemiM0_MReqLast), + .wmemiM0_MAddr(appW3$wmemiM0_MAddr), + .wmemiM0_MBurstLength(appW3$wmemiM0_MBurstLength), + .wmemiM0_MDataValid(appW3$wmemiM0_MDataValid), + .wmemiM0_MDataLast(appW3$wmemiM0_MDataLast), + .wmemiM0_MData(appW3$wmemiM0_MData), + .wmemiM0_MDataByteEn(appW3$wmemiM0_MDataByteEn), + .wmemiM0_MReset_n(appW3$wmemiM0_MReset_n)); + + // submodule appW4 + mkSMAdapter4B #(.smaCtrlInit(32'h00000002), + .hasDebugLogic(hasDebugLogic)) appW4(.wciS0_Clk(CLK), + .wciS0_MReset_n(RST_N_rst_4), + .wciS0_MAddr(appW4$wciS0_MAddr), + .wciS0_MAddrSpace(appW4$wciS0_MAddrSpace), + .wciS0_MByteEn(appW4$wciS0_MByteEn), + .wciS0_MCmd(appW4$wciS0_MCmd), + .wciS0_MData(appW4$wciS0_MData), + .wciS0_MFlag(appW4$wciS0_MFlag), + .wmiM0_SData(appW4$wmiM0_SData), + .wmiM0_SFlag(appW4$wmiM0_SFlag), + .wmiM0_SResp(appW4$wmiM0_SResp), + .wsiS0_MBurstLength(appW4$wsiS0_MBurstLength), + .wsiS0_MByteEn(appW4$wsiS0_MByteEn), + .wsiS0_MCmd(appW4$wsiS0_MCmd), + .wsiS0_MData(appW4$wsiS0_MData), + .wsiS0_MReqInfo(appW4$wsiS0_MReqInfo), + .wmiM0_SThreadBusy(appW4$wmiM0_SThreadBusy), + .wmiM0_SDataThreadBusy(appW4$wmiM0_SDataThreadBusy), + .wmiM0_SRespLast(appW4$wmiM0_SRespLast), + .wmiM0_SReset_n(appW4$wmiM0_SReset_n), + .wsiM0_SThreadBusy(appW4$wsiM0_SThreadBusy), + .wsiM0_SReset_n(appW4$wsiM0_SReset_n), + .wsiS0_MReqLast(appW4$wsiS0_MReqLast), + .wsiS0_MBurstPrecise(appW4$wsiS0_MBurstPrecise), + .wsiS0_MReset_n(appW4$wsiS0_MReset_n), + .wciS0_SResp(appW4$wciS0_SResp), + .wciS0_SData(appW4$wciS0_SData), + .wciS0_SThreadBusy(appW4$wciS0_SThreadBusy), + .wciS0_SFlag(appW4$wciS0_SFlag), + .wmiM0_MCmd(appW4$wmiM0_MCmd), + .wmiM0_MReqLast(appW4$wmiM0_MReqLast), + .wmiM0_MReqInfo(appW4$wmiM0_MReqInfo), + .wmiM0_MAddrSpace(appW4$wmiM0_MAddrSpace), + .wmiM0_MAddr(appW4$wmiM0_MAddr), + .wmiM0_MBurstLength(appW4$wmiM0_MBurstLength), + .wmiM0_MDataValid(appW4$wmiM0_MDataValid), + .wmiM0_MDataLast(appW4$wmiM0_MDataLast), + .wmiM0_MData(appW4$wmiM0_MData), + .wmiM0_MDataByteEn(appW4$wmiM0_MDataByteEn), + .wmiM0_MFlag(appW4$wmiM0_MFlag), + .wmiM0_MReset_n(appW4$wmiM0_MReset_n), + .wsiM0_MCmd(appW4$wsiM0_MCmd), + .wsiM0_MReqLast(appW4$wsiM0_MReqLast), + .wsiM0_MBurstPrecise(appW4$wsiM0_MBurstPrecise), + .wsiM0_MBurstLength(appW4$wsiM0_MBurstLength), + .wsiM0_MData(appW4$wsiM0_MData), + .wsiM0_MByteEn(appW4$wsiM0_MByteEn), + .wsiM0_MReqInfo(appW4$wsiM0_MReqInfo), + .wsiM0_MReset_n(appW4$wsiM0_MReset_n), + .wsiS0_SThreadBusy(appW4$wsiS0_SThreadBusy), + .wsiS0_SReset_n(appW4$wsiS0_SReset_n)); + + // submodule appW5 + mkWsiSplitter2x24B #(.ctrlInit(32'h0), + .hasDebugLogic(hasDebugLogic)) appW5(.wciS0_Clk(CLK), + .wciS0_MReset_n(RST_N_rst_5), + .wciS0_MAddr(appW5$wciS0_MAddr), + .wciS0_MAddrSpace(appW5$wciS0_MAddrSpace), + .wciS0_MByteEn(appW5$wciS0_MByteEn), + .wciS0_MCmd(appW5$wciS0_MCmd), + .wciS0_MData(appW5$wciS0_MData), + .wciS0_MFlag(appW5$wciS0_MFlag), + .wsiS0_MBurstLength(appW5$wsiS0_MBurstLength), + .wsiS0_MByteEn(appW5$wsiS0_MByteEn), + .wsiS0_MCmd(appW5$wsiS0_MCmd), + .wsiS0_MData(appW5$wsiS0_MData), + .wsiS0_MReqInfo(appW5$wsiS0_MReqInfo), + .wsiS1_MBurstLength(appW5$wsiS1_MBurstLength), + .wsiS1_MByteEn(appW5$wsiS1_MByteEn), + .wsiS1_MCmd(appW5$wsiS1_MCmd), + .wsiS1_MData(appW5$wsiS1_MData), + .wsiS1_MReqInfo(appW5$wsiS1_MReqInfo), + .wsiS0_MReqLast(appW5$wsiS0_MReqLast), + .wsiS0_MBurstPrecise(appW5$wsiS0_MBurstPrecise), + .wsiS0_MReset_n(appW5$wsiS0_MReset_n), + .wsiS1_MReqLast(appW5$wsiS1_MReqLast), + .wsiS1_MBurstPrecise(appW5$wsiS1_MBurstPrecise), + .wsiS1_MReset_n(appW5$wsiS1_MReset_n), + .wsiM0_SThreadBusy(appW5$wsiM0_SThreadBusy), + .wsiM0_SReset_n(appW5$wsiM0_SReset_n), + .wsiM1_SThreadBusy(appW5$wsiM1_SThreadBusy), + .wsiM1_SReset_n(appW5$wsiM1_SReset_n), + .wciS0_SResp(appW5$wciS0_SResp), + .wciS0_SData(appW5$wciS0_SData), + .wciS0_SThreadBusy(appW5$wciS0_SThreadBusy), + .wciS0_SFlag(appW5$wciS0_SFlag), + .wsiS0_SThreadBusy(appW5$wsiS0_SThreadBusy), + .wsiS0_SReset_n(appW5$wsiS0_SReset_n), + .wsiS1_SThreadBusy(appW5$wsiS1_SThreadBusy), + .wsiS1_SReset_n(appW5$wsiS1_SReset_n), + .wsiM0_MCmd(appW5$wsiM0_MCmd), + .wsiM0_MReqLast(appW5$wsiM0_MReqLast), + .wsiM0_MBurstPrecise(appW5$wsiM0_MBurstPrecise), + .wsiM0_MBurstLength(appW5$wsiM0_MBurstLength), + .wsiM0_MData(appW5$wsiM0_MData), + .wsiM0_MByteEn(appW5$wsiM0_MByteEn), + .wsiM0_MReqInfo(appW5$wsiM0_MReqInfo), + .wsiM0_MReset_n(appW5$wsiM0_MReset_n), + .wsiM1_MCmd(appW5$wsiM1_MCmd), + .wsiM1_MReqLast(appW5$wsiM1_MReqLast), + .wsiM1_MBurstPrecise(appW5$wsiM1_MBurstPrecise), + .wsiM1_MBurstLength(appW5$wsiM1_MBurstLength), + .wsiM1_MData(appW5$wsiM1_MData), + .wsiM1_MByteEn(appW5$wsiM1_MByteEn), + .wsiM1_MReqInfo(appW5$wsiM1_MReqInfo), + .wsiM1_MReset_n(appW5$wsiM1_MReset_n)); + + // submodule appW6 + mkFrameGate4B #(.fgCtrlInit(32'h0), + .hasDebugLogic(hasDebugLogic)) appW6(.wciS0_Clk(CLK), + .wciS0_MReset_n(RST_N_rst_6), + .wciS0_MAddr(appW6$wciS0_MAddr), + .wciS0_MAddrSpace(appW6$wciS0_MAddrSpace), + .wciS0_MByteEn(appW6$wciS0_MByteEn), + .wciS0_MCmd(appW6$wciS0_MCmd), + .wciS0_MData(appW6$wciS0_MData), + .wciS0_MFlag(appW6$wciS0_MFlag), + .wsiS0_MBurstLength(appW6$wsiS0_MBurstLength), + .wsiS0_MByteEn(appW6$wsiS0_MByteEn), + .wsiS0_MCmd(appW6$wsiS0_MCmd), + .wsiS0_MData(appW6$wsiS0_MData), + .wsiS0_MReqInfo(appW6$wsiS0_MReqInfo), + .wsiS0_MReqLast(appW6$wsiS0_MReqLast), + .wsiS0_MBurstPrecise(appW6$wsiS0_MBurstPrecise), + .wsiS0_MReset_n(appW6$wsiS0_MReset_n), + .wsiM0_SThreadBusy(appW6$wsiM0_SThreadBusy), + .wsiM0_SReset_n(appW6$wsiM0_SReset_n), + .wciS0_SResp(appW6$wciS0_SResp), + .wciS0_SData(appW6$wciS0_SData), + .wciS0_SThreadBusy(appW6$wciS0_SThreadBusy), + .wciS0_SFlag(appW6$wciS0_SFlag), + .wsiS0_SThreadBusy(appW6$wsiS0_SThreadBusy), + .wsiS0_SReset_n(appW6$wsiS0_SReset_n), + .wsiM0_MCmd(appW6$wsiM0_MCmd), + .wsiM0_MReqLast(appW6$wsiM0_MReqLast), + .wsiM0_MBurstPrecise(appW6$wsiM0_MBurstPrecise), + .wsiM0_MBurstLength(appW6$wsiM0_MBurstLength), + .wsiM0_MData(appW6$wsiM0_MData), + .wsiM0_MByteEn(appW6$wsiM0_MByteEn), + .wsiM0_MReqInfo(appW6$wsiM0_MReqInfo), + .wsiM0_MReset_n(appW6$wsiM0_MReset_n)); + + // submodule id + mkUUID id(.uuid(id$uuid)); + + // inlined wires + assign tieOff0_wci_Es_mCmd_w$wget = wci_s_0_MCmd ; + assign tieOff0_wci_Es_mCmd_w$whas = 1'd1 ; + assign tieOff0_wci_Es_mAddrSpace_w$wget = wci_s_0_MAddrSpace ; + assign tieOff0_wci_Es_mAddrSpace_w$whas = 1'd1 ; + assign tieOff0_wci_Es_mByteEn_w$wget = wci_s_0_MByteEn ; + assign tieOff0_wci_Es_mByteEn_w$whas = 1'd1 ; + assign tieOff0_wci_Es_mAddr_w$wget = wci_s_0_MAddr ; + assign tieOff0_wci_Es_mAddr_w$whas = 1'd1 ; + assign tieOff0_wci_Es_mData_w$wget = wci_s_0_MData ; + assign tieOff0_wci_Es_mData_w$whas = 1'd1 ; + assign tieOff1_wci_Es_mCmd_w$wget = wci_s_1_MCmd ; + assign tieOff1_wci_Es_mCmd_w$whas = 1'd1 ; + assign tieOff1_wci_Es_mAddrSpace_w$wget = wci_s_1_MAddrSpace ; + assign tieOff1_wci_Es_mAddrSpace_w$whas = 1'd1 ; + assign tieOff1_wci_Es_mByteEn_w$wget = wci_s_1_MByteEn ; + assign tieOff1_wci_Es_mByteEn_w$whas = 1'd1 ; + assign tieOff1_wci_Es_mAddr_w$wget = wci_s_1_MAddr ; + assign tieOff1_wci_Es_mAddr_w$whas = 1'd1 ; + assign tieOff1_wci_Es_mData_w$wget = wci_s_1_MData ; + assign tieOff1_wci_Es_mData_w$whas = 1'd1 ; + assign tieOff7_wci_Es_mCmd_w$wget = wci_s_7_MCmd ; + assign tieOff7_wci_Es_mCmd_w$whas = 1'd1 ; + assign tieOff7_wci_Es_mAddrSpace_w$wget = wci_s_7_MAddrSpace ; + assign tieOff7_wci_Es_mAddrSpace_w$whas = 1'd1 ; + assign tieOff7_wci_Es_mByteEn_w$wget = wci_s_7_MByteEn ; + assign tieOff7_wci_Es_mByteEn_w$whas = 1'd1 ; + assign tieOff7_wci_Es_mAddr_w$wget = wci_s_7_MAddr ; + assign tieOff7_wci_Es_mAddr_w$whas = 1'd1 ; + assign tieOff7_wci_Es_mData_w$wget = wci_s_7_MData ; + assign tieOff7_wci_Es_mData_w$whas = 1'd1 ; + + // submodule appW2 + assign appW2$wciS0_MAddr = wci_s_2_MAddr ; + assign appW2$wciS0_MAddrSpace = wci_s_2_MAddrSpace ; + assign appW2$wciS0_MByteEn = wci_s_2_MByteEn ; + assign appW2$wciS0_MCmd = wci_s_2_MCmd ; + assign appW2$wciS0_MData = wci_s_2_MData ; + assign appW2$wciS0_MFlag = wci_s_2_MFlag ; + assign appW2$wmiM0_SData = wmiM0_SData ; + assign appW2$wmiM0_SFlag = wmiM0_SFlag ; + assign appW2$wmiM0_SResp = wmiM0_SResp ; + assign appW2$wsiS0_MBurstLength = appW6$wsiM0_MBurstLength ; + assign appW2$wsiS0_MByteEn = appW6$wsiM0_MByteEn ; + assign appW2$wsiS0_MCmd = appW6$wsiM0_MCmd ; + assign appW2$wsiS0_MData = appW6$wsiM0_MData ; + assign appW2$wsiS0_MReqInfo = appW6$wsiM0_MReqInfo ; + assign appW2$wmiM0_SThreadBusy = wmiM0_SThreadBusy ; + assign appW2$wmiM0_SDataThreadBusy = wmiM0_SDataThreadBusy ; + assign appW2$wmiM0_SRespLast = wmiM0_SRespLast ; + assign appW2$wmiM0_SReset_n = wmiM0_SReset_n ; + assign appW2$wsiM0_SThreadBusy = appW5$wsiS0_SThreadBusy ; + assign appW2$wsiM0_SReset_n = appW5$wsiS0_SReset_n ; + assign appW2$wsiS0_MReqLast = appW6$wsiM0_MReqLast ; + assign appW2$wsiS0_MBurstPrecise = appW6$wsiM0_MBurstPrecise ; + assign appW2$wsiS0_MReset_n = appW6$wsiM0_MReset_n ; + + // submodule appW3 + assign appW3$wciS0_MAddr = wci_s_3_MAddr ; + assign appW3$wciS0_MAddrSpace = wci_s_3_MAddrSpace ; + assign appW3$wciS0_MByteEn = wci_s_3_MByteEn ; + assign appW3$wciS0_MCmd = wci_s_3_MCmd ; + assign appW3$wciS0_MData = wci_s_3_MData ; + assign appW3$wciS0_MFlag = wci_s_3_MFlag ; + assign appW3$wmemiM0_SData = wmemiM0_SData ; + assign appW3$wmemiM0_SResp = wmemiM0_SResp ; + assign appW3$wsiS0_MBurstLength = appW5$wsiM0_MBurstLength ; + assign appW3$wsiS0_MByteEn = appW5$wsiM0_MByteEn ; + assign appW3$wsiS0_MCmd = appW5$wsiM0_MCmd ; + assign appW3$wsiS0_MData = appW5$wsiM0_MData ; + assign appW3$wsiS0_MReqInfo = appW5$wsiM0_MReqInfo ; + assign appW3$wsiS0_MReqLast = appW5$wsiM0_MReqLast ; + assign appW3$wsiS0_MBurstPrecise = appW5$wsiM0_MBurstPrecise ; + assign appW3$wsiS0_MReset_n = appW5$wsiM0_MReset_n ; + assign appW3$wsiM0_SThreadBusy = appW4$wsiS0_SThreadBusy ; + assign appW3$wsiM0_SReset_n = appW4$wsiS0_SReset_n ; + assign appW3$wmemiM0_SRespLast = wmemiM0_SRespLast ; + assign appW3$wmemiM0_SCmdAccept = wmemiM0_SCmdAccept ; + assign appW3$wmemiM0_SDataAccept = wmemiM0_SDataAccept ; + + // submodule appW4 + assign appW4$wciS0_MAddr = wci_s_4_MAddr ; + assign appW4$wciS0_MAddrSpace = wci_s_4_MAddrSpace ; + assign appW4$wciS0_MByteEn = wci_s_4_MByteEn ; + assign appW4$wciS0_MCmd = wci_s_4_MCmd ; + assign appW4$wciS0_MData = wci_s_4_MData ; + assign appW4$wciS0_MFlag = wci_s_4_MFlag ; + assign appW4$wmiM0_SData = wmiM1_SData ; + assign appW4$wmiM0_SFlag = wmiM1_SFlag ; + assign appW4$wmiM0_SResp = wmiM1_SResp ; + assign appW4$wsiS0_MBurstLength = appW3$wsiM0_MBurstLength ; + assign appW4$wsiS0_MByteEn = appW3$wsiM0_MByteEn ; + assign appW4$wsiS0_MCmd = appW3$wsiM0_MCmd ; + assign appW4$wsiS0_MData = appW3$wsiM0_MData ; + assign appW4$wsiS0_MReqInfo = appW3$wsiM0_MReqInfo ; + assign appW4$wmiM0_SThreadBusy = wmiM1_SThreadBusy ; + assign appW4$wmiM0_SDataThreadBusy = wmiM1_SDataThreadBusy ; + assign appW4$wmiM0_SRespLast = wmiM1_SRespLast ; + assign appW4$wmiM0_SReset_n = wmiM1_SReset_n ; + assign appW4$wsiM0_SThreadBusy = wsi_m_dac_SThreadBusy ; + assign appW4$wsiM0_SReset_n = wsi_m_dac_SReset_n ; + assign appW4$wsiS0_MReqLast = appW3$wsiM0_MReqLast ; + assign appW4$wsiS0_MBurstPrecise = appW3$wsiM0_MBurstPrecise ; + assign appW4$wsiS0_MReset_n = appW3$wsiM0_MReset_n ; + + // submodule appW5 + assign appW5$wciS0_MAddr = wci_s_5_MAddr ; + assign appW5$wciS0_MAddrSpace = wci_s_5_MAddrSpace ; + assign appW5$wciS0_MByteEn = wci_s_5_MByteEn ; + assign appW5$wciS0_MCmd = wci_s_5_MCmd ; + assign appW5$wciS0_MData = wci_s_5_MData ; + assign appW5$wciS0_MFlag = wci_s_5_MFlag ; + assign appW5$wsiS0_MBurstLength = appW2$wsiM0_MBurstLength ; + assign appW5$wsiS0_MByteEn = appW2$wsiM0_MByteEn ; + assign appW5$wsiS0_MCmd = appW2$wsiM0_MCmd ; + assign appW5$wsiS0_MData = appW2$wsiM0_MData ; + assign appW5$wsiS0_MReqInfo = appW2$wsiM0_MReqInfo ; + assign appW5$wsiS1_MBurstLength = wsi_s_adc_MBurstLength ; + assign appW5$wsiS1_MByteEn = wsi_s_adc_MByteEn ; + assign appW5$wsiS1_MCmd = wsi_s_adc_MCmd ; + assign appW5$wsiS1_MData = wsi_s_adc_MData ; + assign appW5$wsiS1_MReqInfo = wsi_s_adc_MReqInfo ; + assign appW5$wsiS0_MReqLast = appW2$wsiM0_MReqLast ; + assign appW5$wsiS0_MBurstPrecise = appW2$wsiM0_MBurstPrecise ; + assign appW5$wsiS0_MReset_n = appW2$wsiM0_MReset_n ; + assign appW5$wsiS1_MReqLast = wsi_s_adc_MReqLast ; + assign appW5$wsiS1_MBurstPrecise = wsi_s_adc_MBurstPrecise ; + assign appW5$wsiS1_MReset_n = wsi_s_adc_MReset_n ; + assign appW5$wsiM0_SThreadBusy = appW3$wsiS0_SThreadBusy ; + assign appW5$wsiM0_SReset_n = appW3$wsiS0_SReset_n ; + assign appW5$wsiM1_SThreadBusy = appW6$wsiS0_SThreadBusy ; + assign appW5$wsiM1_SReset_n = appW6$wsiS0_SReset_n ; + + // submodule appW6 + assign appW6$wciS0_MAddr = wci_s_6_MAddr ; + assign appW6$wciS0_MAddrSpace = wci_s_6_MAddrSpace ; + assign appW6$wciS0_MByteEn = wci_s_6_MByteEn ; + assign appW6$wciS0_MCmd = wci_s_6_MCmd ; + assign appW6$wciS0_MData = wci_s_6_MData ; + assign appW6$wciS0_MFlag = wci_s_6_MFlag ; + assign appW6$wsiS0_MBurstLength = appW5$wsiM1_MBurstLength ; + assign appW6$wsiS0_MByteEn = appW5$wsiM1_MByteEn ; + assign appW6$wsiS0_MCmd = appW5$wsiM1_MCmd ; + assign appW6$wsiS0_MData = appW5$wsiM1_MData ; + assign appW6$wsiS0_MReqInfo = appW5$wsiM1_MReqInfo ; + assign appW6$wsiS0_MReqLast = appW5$wsiM1_MReqLast ; + assign appW6$wsiS0_MBurstPrecise = appW5$wsiM1_MBurstPrecise ; + assign appW6$wsiS0_MReset_n = appW5$wsiM1_MReset_n ; + assign appW6$wsiM0_SThreadBusy = appW2$wsiS0_SThreadBusy ; + assign appW6$wsiM0_SReset_n = appW2$wsiS0_SReset_n ; +endmodule // mkOCApp4B + diff --git a/rtl/mkOCCP.v b/rtl/mkOCCP.v index 9620db54..125241a4 100644 --- a/rtl/mkOCCP.v +++ b/rtl/mkOCCP.v @@ -1,7 +1,7 @@ // -// Generated by Bluespec Compiler, version 2012.09.beta1 (build 29570, 2012-09.11) +// Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Tue Dec 11 16:20:35 EST 2012 +// On Fri Jun 21 17:00:25 EDT 2013 // // // Ports: @@ -1167,77 +1167,81 @@ module mkOCCP(pciDevice, // inlined wires wire [511 : 0] uuidV$wget; - wire [71 : 0] wci_reqF_10_x_wire$wget, - wci_reqF_11_x_wire$wget, - wci_reqF_12_x_wire$wget, - wci_reqF_13_x_wire$wget, - wci_reqF_14_x_wire$wget, - wci_reqF_1_x_wire$wget, - wci_reqF_2_x_wire$wget, - wci_reqF_3_x_wire$wget, - wci_reqF_4_x_wire$wget, - wci_reqF_5_x_wire$wget, - wci_reqF_6_x_wire$wget, - wci_reqF_7_x_wire$wget, - wci_reqF_8_x_wire$wget, - wci_reqF_9_x_wire$wget, - wci_reqF_x_wire$wget; + wire [71 : 0] wci_0_reqF_x_wire$wget, + wci_10_reqF_x_wire$wget, + wci_11_reqF_x_wire$wget, + wci_12_reqF_x_wire$wget, + wci_13_reqF_x_wire$wget, + wci_14_reqF_x_wire$wget, + wci_1_reqF_x_wire$wget, + wci_2_reqF_x_wire$wget, + wci_3_reqF_x_wire$wget, + wci_4_reqF_x_wire$wget, + wci_5_reqF_x_wire$wget, + wci_6_reqF_x_wire$wget, + wci_7_reqF_x_wire$wget, + wci_8_reqF_x_wire$wget, + wci_9_reqF_x_wire$wget; wire [63 : 0] devDNAV$wget, deviceDNA$wget; wire [49 : 0] timeServ_jamFracVal_1$wget; - wire [33 : 0] wci_wciResponse$wget, - wci_wciResponse_1$wget, - wci_wciResponse_10$wget, - wci_wciResponse_11$wget, - wci_wciResponse_12$wget, - wci_wciResponse_13$wget, - wci_wciResponse_14$wget, - wci_wciResponse_2$wget, - wci_wciResponse_3$wget, - wci_wciResponse_4$wget, - wci_wciResponse_5$wget, - wci_wciResponse_6$wget, - wci_wciResponse_7$wget, - wci_wciResponse_8$wget, - wci_wciResponse_9$wget; + wire [33 : 0] wci_0_wciResponse$wget, + wci_10_wciResponse$wget, + wci_11_wciResponse$wget, + wci_12_wciResponse$wget, + wci_13_wciResponse$wget, + wci_14_wciResponse$wget, + wci_1_wciResponse$wget, + wci_2_wciResponse$wget, + wci_3_wciResponse$wget, + wci_4_wciResponse$wget, + wci_5_wciResponse$wget, + wci_6_wciResponse$wget, + wci_7_wciResponse$wget, + wci_8_wciResponse$wget, + wci_9_wciResponse$wget; wire [31 : 0] rom_serverAdapter_outData_enqData$wget, rom_serverAdapter_outData_outData$wget, - wci_Emv_respData_w$wget, - wci_Emv_respData_w_1$wget, - wci_Emv_respData_w_10$wget, - wci_Emv_respData_w_11$wget, - wci_Emv_respData_w_12$wget, - wci_Emv_respData_w_13$wget, - wci_Emv_respData_w_14$wget, - wci_Emv_respData_w_2$wget, - wci_Emv_respData_w_3$wget, - wci_Emv_respData_w_4$wget, - wci_Emv_respData_w_5$wget, - wci_Emv_respData_w_6$wget, - wci_Emv_respData_w_7$wget, - wci_Emv_respData_w_8$wget, - wci_Emv_respData_w_9$wget; + wci_Emv_0_respData_w$wget, + wci_Emv_10_respData_w$wget, + wci_Emv_11_respData_w$wget, + wci_Emv_12_respData_w$wget, + wci_Emv_13_respData_w$wget, + wci_Emv_14_respData_w$wget, + wci_Emv_1_respData_w$wget, + wci_Emv_2_respData_w$wget, + wci_Emv_3_respData_w$wget, + wci_Emv_4_respData_w$wget, + wci_Emv_5_respData_w$wget, + wci_Emv_6_respData_w$wget, + wci_Emv_7_respData_w$wget, + wci_Emv_8_respData_w$wget, + wci_Emv_9_respData_w$wget; wire [2 : 0] rom_serverAdapter_cnt_1$wget, rom_serverAdapter_cnt_2$wget, rom_serverAdapter_cnt_3$wget; wire [1 : 0] rom_serverAdapter_s1_1$wget, rom_serverAdapter_writeWithResp$wget, - wci_Emv_resp_w$wget, - wci_Emv_resp_w_1$wget, - wci_Emv_resp_w_10$wget, - wci_Emv_resp_w_11$wget, - wci_Emv_resp_w_12$wget, - wci_Emv_resp_w_13$wget, - wci_Emv_resp_w_14$wget, - wci_Emv_resp_w_2$wget, - wci_Emv_resp_w_3$wget, - wci_Emv_resp_w_4$wget, - wci_Emv_resp_w_5$wget, - wci_Emv_resp_w_6$wget, - wci_Emv_resp_w_7$wget, - wci_Emv_resp_w_8$wget, - wci_Emv_resp_w_9$wget; + wci_Emv_0_resp_w$wget, + wci_Emv_10_resp_w$wget, + wci_Emv_11_resp_w$wget, + wci_Emv_12_resp_w$wget, + wci_Emv_13_resp_w$wget, + wci_Emv_14_resp_w$wget, + wci_Emv_1_resp_w$wget, + wci_Emv_2_resp_w$wget, + wci_Emv_3_resp_w$wget, + wci_Emv_4_resp_w$wget, + wci_Emv_5_resp_w$wget, + wci_Emv_6_resp_w$wget, + wci_Emv_7_resp_w$wget, + wci_Emv_8_resp_w$wget, + wci_Emv_9_resp_w$wget; wire devDNAV$whas, deviceDNA$whas, + dna_rdReg_1$wget, + dna_rdReg_1$whas, + dna_shftReg_1$wget, + dna_shftReg_1$whas, rom_serverAdapter_cnt_1$whas, rom_serverAdapter_cnt_2$whas, rom_serverAdapter_cnt_3$whas, @@ -1252,171 +1256,171 @@ module mkOCCP(pciDevice, uuidV$whas, warmResetP_1$wget, warmResetP_1$whas, - wci_Emv_respData_w$whas, - wci_Emv_respData_w_1$whas, - wci_Emv_respData_w_10$whas, - wci_Emv_respData_w_11$whas, - wci_Emv_respData_w_12$whas, - wci_Emv_respData_w_13$whas, - wci_Emv_respData_w_14$whas, - wci_Emv_respData_w_2$whas, - wci_Emv_respData_w_3$whas, - wci_Emv_respData_w_4$whas, - wci_Emv_respData_w_5$whas, - wci_Emv_respData_w_6$whas, - wci_Emv_respData_w_7$whas, - wci_Emv_respData_w_8$whas, - wci_Emv_respData_w_9$whas, - wci_Emv_resp_w$whas, - wci_Emv_resp_w_1$whas, - wci_Emv_resp_w_10$whas, - wci_Emv_resp_w_11$whas, - wci_Emv_resp_w_12$whas, - wci_Emv_resp_w_13$whas, - wci_Emv_resp_w_14$whas, - wci_Emv_resp_w_2$whas, - wci_Emv_resp_w_3$whas, - wci_Emv_resp_w_4$whas, - wci_Emv_resp_w_5$whas, - wci_Emv_resp_w_6$whas, - wci_Emv_resp_w_7$whas, - wci_Emv_resp_w_8$whas, - wci_Emv_resp_w_9$whas, - wci_reqF_10_dequeueing$whas, - wci_reqF_10_enqueueing$whas, - wci_reqF_10_x_wire$whas, - wci_reqF_11_dequeueing$whas, - wci_reqF_11_enqueueing$whas, - wci_reqF_11_x_wire$whas, - wci_reqF_12_dequeueing$whas, - wci_reqF_12_enqueueing$whas, - wci_reqF_12_x_wire$whas, - wci_reqF_13_dequeueing$whas, - wci_reqF_13_enqueueing$whas, - wci_reqF_13_x_wire$whas, - wci_reqF_14_dequeueing$whas, - wci_reqF_14_enqueueing$whas, - wci_reqF_14_x_wire$whas, - wci_reqF_1_dequeueing$whas, - wci_reqF_1_enqueueing$whas, - wci_reqF_1_x_wire$whas, - wci_reqF_2_dequeueing$whas, - wci_reqF_2_enqueueing$whas, - wci_reqF_2_x_wire$whas, - wci_reqF_3_dequeueing$whas, - wci_reqF_3_enqueueing$whas, - wci_reqF_3_x_wire$whas, - wci_reqF_4_dequeueing$whas, - wci_reqF_4_enqueueing$whas, - wci_reqF_4_x_wire$whas, - wci_reqF_5_dequeueing$whas, - wci_reqF_5_enqueueing$whas, - wci_reqF_5_x_wire$whas, - wci_reqF_6_dequeueing$whas, - wci_reqF_6_enqueueing$whas, - wci_reqF_6_x_wire$whas, - wci_reqF_7_dequeueing$whas, - wci_reqF_7_enqueueing$whas, - wci_reqF_7_x_wire$whas, - wci_reqF_8_dequeueing$whas, - wci_reqF_8_enqueueing$whas, - wci_reqF_8_x_wire$whas, - wci_reqF_9_dequeueing$whas, - wci_reqF_9_enqueueing$whas, - wci_reqF_9_x_wire$whas, - wci_reqF_dequeueing$whas, - wci_reqF_enqueueing$whas, - wci_reqF_x_wire$whas, - wci_sThreadBusy_pw$whas, - wci_sThreadBusy_pw_1$whas, - wci_sThreadBusy_pw_10$whas, - wci_sThreadBusy_pw_11$whas, - wci_sThreadBusy_pw_12$whas, - wci_sThreadBusy_pw_13$whas, - wci_sThreadBusy_pw_14$whas, - wci_sThreadBusy_pw_2$whas, - wci_sThreadBusy_pw_3$whas, - wci_sThreadBusy_pw_4$whas, - wci_sThreadBusy_pw_5$whas, - wci_sThreadBusy_pw_6$whas, - wci_sThreadBusy_pw_7$whas, - wci_sThreadBusy_pw_8$whas, - wci_sThreadBusy_pw_9$whas, - wci_sfCapClear_1$wget, - wci_sfCapClear_1$whas, - wci_sfCapClear_10_1$wget, - wci_sfCapClear_10_1$whas, - wci_sfCapClear_11_1$wget, - wci_sfCapClear_11_1$whas, - wci_sfCapClear_12_1$wget, - wci_sfCapClear_12_1$whas, - wci_sfCapClear_13_1$wget, - wci_sfCapClear_13_1$whas, - wci_sfCapClear_14_1$wget, - wci_sfCapClear_14_1$whas, - wci_sfCapClear_1_2$wget, - wci_sfCapClear_1_2$whas, - wci_sfCapClear_2_1$wget, - wci_sfCapClear_2_1$whas, - wci_sfCapClear_3_1$wget, - wci_sfCapClear_3_1$whas, - wci_sfCapClear_4_1$wget, - wci_sfCapClear_4_1$whas, - wci_sfCapClear_5_1$wget, - wci_sfCapClear_5_1$whas, - wci_sfCapClear_6_1$wget, - wci_sfCapClear_6_1$whas, - wci_sfCapClear_7_1$wget, - wci_sfCapClear_7_1$whas, - wci_sfCapClear_8_1$wget, - wci_sfCapClear_8_1$whas, - wci_sfCapClear_9_1$wget, - wci_sfCapClear_9_1$whas, - wci_sfCapSet_1$wget, - wci_sfCapSet_1$whas, - wci_sfCapSet_10_1$wget, - wci_sfCapSet_10_1$whas, - wci_sfCapSet_11_1$wget, - wci_sfCapSet_11_1$whas, - wci_sfCapSet_12_1$wget, - wci_sfCapSet_12_1$whas, - wci_sfCapSet_13_1$wget, - wci_sfCapSet_13_1$whas, - wci_sfCapSet_14_1$wget, - wci_sfCapSet_14_1$whas, - wci_sfCapSet_1_2$wget, - wci_sfCapSet_1_2$whas, - wci_sfCapSet_2_1$wget, - wci_sfCapSet_2_1$whas, - wci_sfCapSet_3_1$wget, - wci_sfCapSet_3_1$whas, - wci_sfCapSet_4_1$wget, - wci_sfCapSet_4_1$whas, - wci_sfCapSet_5_1$wget, - wci_sfCapSet_5_1$whas, - wci_sfCapSet_6_1$wget, - wci_sfCapSet_6_1$whas, - wci_sfCapSet_7_1$wget, - wci_sfCapSet_7_1$whas, - wci_sfCapSet_8_1$wget, - wci_sfCapSet_8_1$whas, - wci_sfCapSet_9_1$wget, - wci_sfCapSet_9_1$whas, - wci_wciResponse$whas, - wci_wciResponse_1$whas, - wci_wciResponse_10$whas, - wci_wciResponse_11$whas, - wci_wciResponse_12$whas, - wci_wciResponse_13$whas, - wci_wciResponse_14$whas, - wci_wciResponse_2$whas, - wci_wciResponse_3$whas, - wci_wciResponse_4$whas, - wci_wciResponse_5$whas, - wci_wciResponse_6$whas, - wci_wciResponse_7$whas, - wci_wciResponse_8$whas, - wci_wciResponse_9$whas; + wci_0_reqF_dequeueing$whas, + wci_0_reqF_enqueueing$whas, + wci_0_reqF_x_wire$whas, + wci_0_sThreadBusy_pw$whas, + wci_0_sfCapClear_1$wget, + wci_0_sfCapClear_1$whas, + wci_0_sfCapSet_1$wget, + wci_0_sfCapSet_1$whas, + wci_0_wciResponse$whas, + wci_10_reqF_dequeueing$whas, + wci_10_reqF_enqueueing$whas, + wci_10_reqF_x_wire$whas, + wci_10_sThreadBusy_pw$whas, + wci_10_sfCapClear_1$wget, + wci_10_sfCapClear_1$whas, + wci_10_sfCapSet_1$wget, + wci_10_sfCapSet_1$whas, + wci_10_wciResponse$whas, + wci_11_reqF_dequeueing$whas, + wci_11_reqF_enqueueing$whas, + wci_11_reqF_x_wire$whas, + wci_11_sThreadBusy_pw$whas, + wci_11_sfCapClear_1$wget, + wci_11_sfCapClear_1$whas, + wci_11_sfCapSet_1$wget, + wci_11_sfCapSet_1$whas, + wci_11_wciResponse$whas, + wci_12_reqF_dequeueing$whas, + wci_12_reqF_enqueueing$whas, + wci_12_reqF_x_wire$whas, + wci_12_sThreadBusy_pw$whas, + wci_12_sfCapClear_1$wget, + wci_12_sfCapClear_1$whas, + wci_12_sfCapSet_1$wget, + wci_12_sfCapSet_1$whas, + wci_12_wciResponse$whas, + wci_13_reqF_dequeueing$whas, + wci_13_reqF_enqueueing$whas, + wci_13_reqF_x_wire$whas, + wci_13_sThreadBusy_pw$whas, + wci_13_sfCapClear_1$wget, + wci_13_sfCapClear_1$whas, + wci_13_sfCapSet_1$wget, + wci_13_sfCapSet_1$whas, + wci_13_wciResponse$whas, + wci_14_reqF_dequeueing$whas, + wci_14_reqF_enqueueing$whas, + wci_14_reqF_x_wire$whas, + wci_14_sThreadBusy_pw$whas, + wci_14_sfCapClear_1$wget, + wci_14_sfCapClear_1$whas, + wci_14_sfCapSet_1$wget, + wci_14_sfCapSet_1$whas, + wci_14_wciResponse$whas, + wci_1_reqF_dequeueing$whas, + wci_1_reqF_enqueueing$whas, + wci_1_reqF_x_wire$whas, + wci_1_sThreadBusy_pw$whas, + wci_1_sfCapClear_1$wget, + wci_1_sfCapClear_1$whas, + wci_1_sfCapSet_1$wget, + wci_1_sfCapSet_1$whas, + wci_1_wciResponse$whas, + wci_2_reqF_dequeueing$whas, + wci_2_reqF_enqueueing$whas, + wci_2_reqF_x_wire$whas, + wci_2_sThreadBusy_pw$whas, + wci_2_sfCapClear_1$wget, + wci_2_sfCapClear_1$whas, + wci_2_sfCapSet_1$wget, + wci_2_sfCapSet_1$whas, + wci_2_wciResponse$whas, + wci_3_reqF_dequeueing$whas, + wci_3_reqF_enqueueing$whas, + wci_3_reqF_x_wire$whas, + wci_3_sThreadBusy_pw$whas, + wci_3_sfCapClear_1$wget, + wci_3_sfCapClear_1$whas, + wci_3_sfCapSet_1$wget, + wci_3_sfCapSet_1$whas, + wci_3_wciResponse$whas, + wci_4_reqF_dequeueing$whas, + wci_4_reqF_enqueueing$whas, + wci_4_reqF_x_wire$whas, + wci_4_sThreadBusy_pw$whas, + wci_4_sfCapClear_1$wget, + wci_4_sfCapClear_1$whas, + wci_4_sfCapSet_1$wget, + wci_4_sfCapSet_1$whas, + wci_4_wciResponse$whas, + wci_5_reqF_dequeueing$whas, + wci_5_reqF_enqueueing$whas, + wci_5_reqF_x_wire$whas, + wci_5_sThreadBusy_pw$whas, + wci_5_sfCapClear_1$wget, + wci_5_sfCapClear_1$whas, + wci_5_sfCapSet_1$wget, + wci_5_sfCapSet_1$whas, + wci_5_wciResponse$whas, + wci_6_reqF_dequeueing$whas, + wci_6_reqF_enqueueing$whas, + wci_6_reqF_x_wire$whas, + wci_6_sThreadBusy_pw$whas, + wci_6_sfCapClear_1$wget, + wci_6_sfCapClear_1$whas, + wci_6_sfCapSet_1$wget, + wci_6_sfCapSet_1$whas, + wci_6_wciResponse$whas, + wci_7_reqF_dequeueing$whas, + wci_7_reqF_enqueueing$whas, + wci_7_reqF_x_wire$whas, + wci_7_sThreadBusy_pw$whas, + wci_7_sfCapClear_1$wget, + wci_7_sfCapClear_1$whas, + wci_7_sfCapSet_1$wget, + wci_7_sfCapSet_1$whas, + wci_7_wciResponse$whas, + wci_8_reqF_dequeueing$whas, + wci_8_reqF_enqueueing$whas, + wci_8_reqF_x_wire$whas, + wci_8_sThreadBusy_pw$whas, + wci_8_sfCapClear_1$wget, + wci_8_sfCapClear_1$whas, + wci_8_sfCapSet_1$wget, + wci_8_sfCapSet_1$whas, + wci_8_wciResponse$whas, + wci_9_reqF_dequeueing$whas, + wci_9_reqF_enqueueing$whas, + wci_9_reqF_x_wire$whas, + wci_9_sThreadBusy_pw$whas, + wci_9_sfCapClear_1$wget, + wci_9_sfCapClear_1$whas, + wci_9_sfCapSet_1$wget, + wci_9_sfCapSet_1$whas, + wci_9_wciResponse$whas, + wci_Emv_0_respData_w$whas, + wci_Emv_0_resp_w$whas, + wci_Emv_10_respData_w$whas, + wci_Emv_10_resp_w$whas, + wci_Emv_11_respData_w$whas, + wci_Emv_11_resp_w$whas, + wci_Emv_12_respData_w$whas, + wci_Emv_12_resp_w$whas, + wci_Emv_13_respData_w$whas, + wci_Emv_13_resp_w$whas, + wci_Emv_14_respData_w$whas, + wci_Emv_14_resp_w$whas, + wci_Emv_1_respData_w$whas, + wci_Emv_1_resp_w$whas, + wci_Emv_2_respData_w$whas, + wci_Emv_2_resp_w$whas, + wci_Emv_3_respData_w$whas, + wci_Emv_3_resp_w$whas, + wci_Emv_4_respData_w$whas, + wci_Emv_4_resp_w$whas, + wci_Emv_5_respData_w$whas, + wci_Emv_5_resp_w$whas, + wci_Emv_6_respData_w$whas, + wci_Emv_6_resp_w$whas, + wci_Emv_7_respData_w$whas, + wci_Emv_7_resp_w$whas, + wci_Emv_8_respData_w$whas, + wci_Emv_8_resp_w$whas, + wci_Emv_9_respData_w$whas, + wci_Emv_9_resp_w$whas; // register cpControl reg [31 : 0] cpControl; @@ -1438,6 +1442,24 @@ module mkOCCP(pciDevice, reg dispatched$D_IN; wire dispatched$EN; + // register dna_cnt + reg [6 : 0] dna_cnt; + wire [6 : 0] dna_cnt$D_IN; + wire dna_cnt$EN; + + // register dna_rdReg + reg dna_rdReg; + wire dna_rdReg$D_IN, dna_rdReg$EN; + + // register dna_shftReg + reg dna_shftReg; + wire dna_shftReg$D_IN, dna_shftReg$EN; + + // register dna_sr + reg [56 : 0] dna_sr; + wire [56 : 0] dna_sr$D_IN; + wire dna_sr$EN; + // register readCntReg reg [31 : 0] readCntReg; wire [31 : 0] readCntReg$D_IN; @@ -1614,1595 +1636,1595 @@ module mkOCCP(pciDevice, reg warmResetP; wire warmResetP$D_IN, warmResetP$EN; - // register wci_busy - reg wci_busy; - wire wci_busy$D_IN, wci_busy$EN; - - // register wci_busy_1 - reg wci_busy_1; - wire wci_busy_1$D_IN, wci_busy_1$EN; - - // register wci_busy_10 - reg wci_busy_10; - wire wci_busy_10$D_IN, wci_busy_10$EN; - - // register wci_busy_11 - reg wci_busy_11; - wire wci_busy_11$D_IN, wci_busy_11$EN; - - // register wci_busy_12 - reg wci_busy_12; - wire wci_busy_12$D_IN, wci_busy_12$EN; - - // register wci_busy_13 - reg wci_busy_13; - wire wci_busy_13$D_IN, wci_busy_13$EN; - - // register wci_busy_14 - reg wci_busy_14; - wire wci_busy_14$D_IN, wci_busy_14$EN; - - // register wci_busy_2 - reg wci_busy_2; - wire wci_busy_2$D_IN, wci_busy_2$EN; - - // register wci_busy_3 - reg wci_busy_3; - wire wci_busy_3$D_IN, wci_busy_3$EN; - - // register wci_busy_4 - reg wci_busy_4; - wire wci_busy_4$D_IN, wci_busy_4$EN; - - // register wci_busy_5 - reg wci_busy_5; - wire wci_busy_5$D_IN, wci_busy_5$EN; - - // register wci_busy_6 - reg wci_busy_6; - wire wci_busy_6$D_IN, wci_busy_6$EN; - - // register wci_busy_7 - reg wci_busy_7; - wire wci_busy_7$D_IN, wci_busy_7$EN; - - // register wci_busy_8 - reg wci_busy_8; - wire wci_busy_8$D_IN, wci_busy_8$EN; - - // register wci_busy_9 - reg wci_busy_9; - wire wci_busy_9$D_IN, wci_busy_9$EN; - - // register wci_lastConfigAddr - reg [32 : 0] wci_lastConfigAddr; - wire [32 : 0] wci_lastConfigAddr$D_IN; - wire wci_lastConfigAddr$EN; - - // register wci_lastConfigAddr_1 - reg [32 : 0] wci_lastConfigAddr_1; - wire [32 : 0] wci_lastConfigAddr_1$D_IN; - wire wci_lastConfigAddr_1$EN; - - // register wci_lastConfigAddr_10 - reg [32 : 0] wci_lastConfigAddr_10; - wire [32 : 0] wci_lastConfigAddr_10$D_IN; - wire wci_lastConfigAddr_10$EN; - - // register wci_lastConfigAddr_11 - reg [32 : 0] wci_lastConfigAddr_11; - wire [32 : 0] wci_lastConfigAddr_11$D_IN; - wire wci_lastConfigAddr_11$EN; - - // register wci_lastConfigAddr_12 - reg [32 : 0] wci_lastConfigAddr_12; - wire [32 : 0] wci_lastConfigAddr_12$D_IN; - wire wci_lastConfigAddr_12$EN; - - // register wci_lastConfigAddr_13 - reg [32 : 0] wci_lastConfigAddr_13; - wire [32 : 0] wci_lastConfigAddr_13$D_IN; - wire wci_lastConfigAddr_13$EN; - - // register wci_lastConfigAddr_14 - reg [32 : 0] wci_lastConfigAddr_14; - wire [32 : 0] wci_lastConfigAddr_14$D_IN; - wire wci_lastConfigAddr_14$EN; - - // register wci_lastConfigAddr_2 - reg [32 : 0] wci_lastConfigAddr_2; - wire [32 : 0] wci_lastConfigAddr_2$D_IN; - wire wci_lastConfigAddr_2$EN; - - // register wci_lastConfigAddr_3 - reg [32 : 0] wci_lastConfigAddr_3; - wire [32 : 0] wci_lastConfigAddr_3$D_IN; - wire wci_lastConfigAddr_3$EN; - - // register wci_lastConfigAddr_4 - reg [32 : 0] wci_lastConfigAddr_4; - wire [32 : 0] wci_lastConfigAddr_4$D_IN; - wire wci_lastConfigAddr_4$EN; - - // register wci_lastConfigAddr_5 - reg [32 : 0] wci_lastConfigAddr_5; - wire [32 : 0] wci_lastConfigAddr_5$D_IN; - wire wci_lastConfigAddr_5$EN; - - // register wci_lastConfigAddr_6 - reg [32 : 0] wci_lastConfigAddr_6; - wire [32 : 0] wci_lastConfigAddr_6$D_IN; - wire wci_lastConfigAddr_6$EN; - - // register wci_lastConfigAddr_7 - reg [32 : 0] wci_lastConfigAddr_7; - wire [32 : 0] wci_lastConfigAddr_7$D_IN; - wire wci_lastConfigAddr_7$EN; - - // register wci_lastConfigAddr_8 - reg [32 : 0] wci_lastConfigAddr_8; - wire [32 : 0] wci_lastConfigAddr_8$D_IN; - wire wci_lastConfigAddr_8$EN; - - // register wci_lastConfigAddr_9 - reg [32 : 0] wci_lastConfigAddr_9; - wire [32 : 0] wci_lastConfigAddr_9$D_IN; - wire wci_lastConfigAddr_9$EN; - - // register wci_lastConfigBE - reg [4 : 0] wci_lastConfigBE; - wire [4 : 0] wci_lastConfigBE$D_IN; - wire wci_lastConfigBE$EN; - - // register wci_lastConfigBE_1 - reg [4 : 0] wci_lastConfigBE_1; - wire [4 : 0] wci_lastConfigBE_1$D_IN; - wire wci_lastConfigBE_1$EN; - - // register wci_lastConfigBE_10 - reg [4 : 0] wci_lastConfigBE_10; - wire [4 : 0] wci_lastConfigBE_10$D_IN; - wire wci_lastConfigBE_10$EN; - - // register wci_lastConfigBE_11 - reg [4 : 0] wci_lastConfigBE_11; - wire [4 : 0] wci_lastConfigBE_11$D_IN; - wire wci_lastConfigBE_11$EN; - - // register wci_lastConfigBE_12 - reg [4 : 0] wci_lastConfigBE_12; - wire [4 : 0] wci_lastConfigBE_12$D_IN; - wire wci_lastConfigBE_12$EN; - - // register wci_lastConfigBE_13 - reg [4 : 0] wci_lastConfigBE_13; - wire [4 : 0] wci_lastConfigBE_13$D_IN; - wire wci_lastConfigBE_13$EN; - - // register wci_lastConfigBE_14 - reg [4 : 0] wci_lastConfigBE_14; - wire [4 : 0] wci_lastConfigBE_14$D_IN; - wire wci_lastConfigBE_14$EN; - - // register wci_lastConfigBE_2 - reg [4 : 0] wci_lastConfigBE_2; - wire [4 : 0] wci_lastConfigBE_2$D_IN; - wire wci_lastConfigBE_2$EN; - - // register wci_lastConfigBE_3 - reg [4 : 0] wci_lastConfigBE_3; - wire [4 : 0] wci_lastConfigBE_3$D_IN; - wire wci_lastConfigBE_3$EN; - - // register wci_lastConfigBE_4 - reg [4 : 0] wci_lastConfigBE_4; - wire [4 : 0] wci_lastConfigBE_4$D_IN; - wire wci_lastConfigBE_4$EN; - - // register wci_lastConfigBE_5 - reg [4 : 0] wci_lastConfigBE_5; - wire [4 : 0] wci_lastConfigBE_5$D_IN; - wire wci_lastConfigBE_5$EN; - - // register wci_lastConfigBE_6 - reg [4 : 0] wci_lastConfigBE_6; - wire [4 : 0] wci_lastConfigBE_6$D_IN; - wire wci_lastConfigBE_6$EN; - - // register wci_lastConfigBE_7 - reg [4 : 0] wci_lastConfigBE_7; - wire [4 : 0] wci_lastConfigBE_7$D_IN; - wire wci_lastConfigBE_7$EN; - - // register wci_lastConfigBE_8 - reg [4 : 0] wci_lastConfigBE_8; - wire [4 : 0] wci_lastConfigBE_8$D_IN; - wire wci_lastConfigBE_8$EN; - - // register wci_lastConfigBE_9 - reg [4 : 0] wci_lastConfigBE_9; - wire [4 : 0] wci_lastConfigBE_9$D_IN; - wire wci_lastConfigBE_9$EN; - - // register wci_lastControlOp - reg [3 : 0] wci_lastControlOp; - wire [3 : 0] wci_lastControlOp$D_IN; - wire wci_lastControlOp$EN; - - // register wci_lastControlOp_1 - reg [3 : 0] wci_lastControlOp_1; - wire [3 : 0] wci_lastControlOp_1$D_IN; - wire wci_lastControlOp_1$EN; - - // register wci_lastControlOp_10 - reg [3 : 0] wci_lastControlOp_10; - wire [3 : 0] wci_lastControlOp_10$D_IN; - wire wci_lastControlOp_10$EN; - - // register wci_lastControlOp_11 - reg [3 : 0] wci_lastControlOp_11; - wire [3 : 0] wci_lastControlOp_11$D_IN; - wire wci_lastControlOp_11$EN; - - // register wci_lastControlOp_12 - reg [3 : 0] wci_lastControlOp_12; - wire [3 : 0] wci_lastControlOp_12$D_IN; - wire wci_lastControlOp_12$EN; - - // register wci_lastControlOp_13 - reg [3 : 0] wci_lastControlOp_13; - wire [3 : 0] wci_lastControlOp_13$D_IN; - wire wci_lastControlOp_13$EN; - - // register wci_lastControlOp_14 - reg [3 : 0] wci_lastControlOp_14; - wire [3 : 0] wci_lastControlOp_14$D_IN; - wire wci_lastControlOp_14$EN; - - // register wci_lastControlOp_2 - reg [3 : 0] wci_lastControlOp_2; - wire [3 : 0] wci_lastControlOp_2$D_IN; - wire wci_lastControlOp_2$EN; - - // register wci_lastControlOp_3 - reg [3 : 0] wci_lastControlOp_3; - wire [3 : 0] wci_lastControlOp_3$D_IN; - wire wci_lastControlOp_3$EN; - - // register wci_lastControlOp_4 - reg [3 : 0] wci_lastControlOp_4; - wire [3 : 0] wci_lastControlOp_4$D_IN; - wire wci_lastControlOp_4$EN; - - // register wci_lastControlOp_5 - reg [3 : 0] wci_lastControlOp_5; - wire [3 : 0] wci_lastControlOp_5$D_IN; - wire wci_lastControlOp_5$EN; - - // register wci_lastControlOp_6 - reg [3 : 0] wci_lastControlOp_6; - wire [3 : 0] wci_lastControlOp_6$D_IN; - wire wci_lastControlOp_6$EN; - - // register wci_lastControlOp_7 - reg [3 : 0] wci_lastControlOp_7; - wire [3 : 0] wci_lastControlOp_7$D_IN; - wire wci_lastControlOp_7$EN; - - // register wci_lastControlOp_8 - reg [3 : 0] wci_lastControlOp_8; - wire [3 : 0] wci_lastControlOp_8$D_IN; - wire wci_lastControlOp_8$EN; - - // register wci_lastControlOp_9 - reg [3 : 0] wci_lastControlOp_9; - wire [3 : 0] wci_lastControlOp_9$D_IN; - wire wci_lastControlOp_9$EN; - - // register wci_lastOpWrite - reg [1 : 0] wci_lastOpWrite; - wire [1 : 0] wci_lastOpWrite$D_IN; - wire wci_lastOpWrite$EN; - - // register wci_lastOpWrite_1 - reg [1 : 0] wci_lastOpWrite_1; - wire [1 : 0] wci_lastOpWrite_1$D_IN; - wire wci_lastOpWrite_1$EN; - - // register wci_lastOpWrite_10 - reg [1 : 0] wci_lastOpWrite_10; - wire [1 : 0] wci_lastOpWrite_10$D_IN; - wire wci_lastOpWrite_10$EN; - - // register wci_lastOpWrite_11 - reg [1 : 0] wci_lastOpWrite_11; - wire [1 : 0] wci_lastOpWrite_11$D_IN; - wire wci_lastOpWrite_11$EN; - - // register wci_lastOpWrite_12 - reg [1 : 0] wci_lastOpWrite_12; - wire [1 : 0] wci_lastOpWrite_12$D_IN; - wire wci_lastOpWrite_12$EN; - - // register wci_lastOpWrite_13 - reg [1 : 0] wci_lastOpWrite_13; - wire [1 : 0] wci_lastOpWrite_13$D_IN; - wire wci_lastOpWrite_13$EN; - - // register wci_lastOpWrite_14 - reg [1 : 0] wci_lastOpWrite_14; - wire [1 : 0] wci_lastOpWrite_14$D_IN; - wire wci_lastOpWrite_14$EN; - - // register wci_lastOpWrite_2 - reg [1 : 0] wci_lastOpWrite_2; - wire [1 : 0] wci_lastOpWrite_2$D_IN; - wire wci_lastOpWrite_2$EN; - - // register wci_lastOpWrite_3 - reg [1 : 0] wci_lastOpWrite_3; - wire [1 : 0] wci_lastOpWrite_3$D_IN; - wire wci_lastOpWrite_3$EN; - - // register wci_lastOpWrite_4 - reg [1 : 0] wci_lastOpWrite_4; - wire [1 : 0] wci_lastOpWrite_4$D_IN; - wire wci_lastOpWrite_4$EN; - - // register wci_lastOpWrite_5 - reg [1 : 0] wci_lastOpWrite_5; - wire [1 : 0] wci_lastOpWrite_5$D_IN; - wire wci_lastOpWrite_5$EN; - - // register wci_lastOpWrite_6 - reg [1 : 0] wci_lastOpWrite_6; - wire [1 : 0] wci_lastOpWrite_6$D_IN; - wire wci_lastOpWrite_6$EN; - - // register wci_lastOpWrite_7 - reg [1 : 0] wci_lastOpWrite_7; - wire [1 : 0] wci_lastOpWrite_7$D_IN; - wire wci_lastOpWrite_7$EN; - - // register wci_lastOpWrite_8 - reg [1 : 0] wci_lastOpWrite_8; - wire [1 : 0] wci_lastOpWrite_8$D_IN; - wire wci_lastOpWrite_8$EN; - - // register wci_lastOpWrite_9 - reg [1 : 0] wci_lastOpWrite_9; - wire [1 : 0] wci_lastOpWrite_9$D_IN; - wire wci_lastOpWrite_9$EN; - - // register wci_mFlagReg - reg [1 : 0] wci_mFlagReg; - wire [1 : 0] wci_mFlagReg$D_IN; - wire wci_mFlagReg$EN; - - // register wci_mFlagReg_1 - reg [1 : 0] wci_mFlagReg_1; - wire [1 : 0] wci_mFlagReg_1$D_IN; - wire wci_mFlagReg_1$EN; - - // register wci_mFlagReg_10 - reg [1 : 0] wci_mFlagReg_10; - wire [1 : 0] wci_mFlagReg_10$D_IN; - wire wci_mFlagReg_10$EN; - - // register wci_mFlagReg_11 - reg [1 : 0] wci_mFlagReg_11; - wire [1 : 0] wci_mFlagReg_11$D_IN; - wire wci_mFlagReg_11$EN; - - // register wci_mFlagReg_12 - reg [1 : 0] wci_mFlagReg_12; - wire [1 : 0] wci_mFlagReg_12$D_IN; - wire wci_mFlagReg_12$EN; - - // register wci_mFlagReg_13 - reg [1 : 0] wci_mFlagReg_13; - wire [1 : 0] wci_mFlagReg_13$D_IN; - wire wci_mFlagReg_13$EN; - - // register wci_mFlagReg_14 - reg [1 : 0] wci_mFlagReg_14; - wire [1 : 0] wci_mFlagReg_14$D_IN; - wire wci_mFlagReg_14$EN; - - // register wci_mFlagReg_2 - reg [1 : 0] wci_mFlagReg_2; - wire [1 : 0] wci_mFlagReg_2$D_IN; - wire wci_mFlagReg_2$EN; - - // register wci_mFlagReg_3 - reg [1 : 0] wci_mFlagReg_3; - wire [1 : 0] wci_mFlagReg_3$D_IN; - wire wci_mFlagReg_3$EN; - - // register wci_mFlagReg_4 - reg [1 : 0] wci_mFlagReg_4; - wire [1 : 0] wci_mFlagReg_4$D_IN; - wire wci_mFlagReg_4$EN; - - // register wci_mFlagReg_5 - reg [1 : 0] wci_mFlagReg_5; - wire [1 : 0] wci_mFlagReg_5$D_IN; - wire wci_mFlagReg_5$EN; - - // register wci_mFlagReg_6 - reg [1 : 0] wci_mFlagReg_6; - wire [1 : 0] wci_mFlagReg_6$D_IN; - wire wci_mFlagReg_6$EN; - - // register wci_mFlagReg_7 - reg [1 : 0] wci_mFlagReg_7; - wire [1 : 0] wci_mFlagReg_7$D_IN; - wire wci_mFlagReg_7$EN; - - // register wci_mFlagReg_8 - reg [1 : 0] wci_mFlagReg_8; - wire [1 : 0] wci_mFlagReg_8$D_IN; - wire wci_mFlagReg_8$EN; - - // register wci_mFlagReg_9 - reg [1 : 0] wci_mFlagReg_9; - wire [1 : 0] wci_mFlagReg_9$D_IN; - wire wci_mFlagReg_9$EN; - - // register wci_pageWindow - reg [11 : 0] wci_pageWindow; - wire [11 : 0] wci_pageWindow$D_IN; - wire wci_pageWindow$EN; - - // register wci_pageWindow_1 - reg [11 : 0] wci_pageWindow_1; - wire [11 : 0] wci_pageWindow_1$D_IN; - wire wci_pageWindow_1$EN; - - // register wci_pageWindow_10 - reg [11 : 0] wci_pageWindow_10; - wire [11 : 0] wci_pageWindow_10$D_IN; - wire wci_pageWindow_10$EN; - - // register wci_pageWindow_11 - reg [11 : 0] wci_pageWindow_11; - wire [11 : 0] wci_pageWindow_11$D_IN; - wire wci_pageWindow_11$EN; - - // register wci_pageWindow_12 - reg [11 : 0] wci_pageWindow_12; - wire [11 : 0] wci_pageWindow_12$D_IN; - wire wci_pageWindow_12$EN; - - // register wci_pageWindow_13 - reg [11 : 0] wci_pageWindow_13; - wire [11 : 0] wci_pageWindow_13$D_IN; - wire wci_pageWindow_13$EN; - - // register wci_pageWindow_14 - reg [11 : 0] wci_pageWindow_14; - wire [11 : 0] wci_pageWindow_14$D_IN; - wire wci_pageWindow_14$EN; - - // register wci_pageWindow_2 - reg [11 : 0] wci_pageWindow_2; - wire [11 : 0] wci_pageWindow_2$D_IN; - wire wci_pageWindow_2$EN; - - // register wci_pageWindow_3 - reg [11 : 0] wci_pageWindow_3; - wire [11 : 0] wci_pageWindow_3$D_IN; - wire wci_pageWindow_3$EN; - - // register wci_pageWindow_4 - reg [11 : 0] wci_pageWindow_4; - wire [11 : 0] wci_pageWindow_4$D_IN; - wire wci_pageWindow_4$EN; - - // register wci_pageWindow_5 - reg [11 : 0] wci_pageWindow_5; - wire [11 : 0] wci_pageWindow_5$D_IN; - wire wci_pageWindow_5$EN; - - // register wci_pageWindow_6 - reg [11 : 0] wci_pageWindow_6; - wire [11 : 0] wci_pageWindow_6$D_IN; - wire wci_pageWindow_6$EN; - - // register wci_pageWindow_7 - reg [11 : 0] wci_pageWindow_7; - wire [11 : 0] wci_pageWindow_7$D_IN; - wire wci_pageWindow_7$EN; - - // register wci_pageWindow_8 - reg [11 : 0] wci_pageWindow_8; - wire [11 : 0] wci_pageWindow_8$D_IN; - wire wci_pageWindow_8$EN; - - // register wci_pageWindow_9 - reg [11 : 0] wci_pageWindow_9; - wire [11 : 0] wci_pageWindow_9$D_IN; - wire wci_pageWindow_9$EN; - - // register wci_reqERR - reg [2 : 0] wci_reqERR; - wire [2 : 0] wci_reqERR$D_IN; - wire wci_reqERR$EN; - - // register wci_reqERR_1 - reg [2 : 0] wci_reqERR_1; - wire [2 : 0] wci_reqERR_1$D_IN; - wire wci_reqERR_1$EN; - - // register wci_reqERR_10 - reg [2 : 0] wci_reqERR_10; - wire [2 : 0] wci_reqERR_10$D_IN; - wire wci_reqERR_10$EN; - - // register wci_reqERR_11 - reg [2 : 0] wci_reqERR_11; - wire [2 : 0] wci_reqERR_11$D_IN; - wire wci_reqERR_11$EN; - - // register wci_reqERR_12 - reg [2 : 0] wci_reqERR_12; - wire [2 : 0] wci_reqERR_12$D_IN; - wire wci_reqERR_12$EN; - - // register wci_reqERR_13 - reg [2 : 0] wci_reqERR_13; - wire [2 : 0] wci_reqERR_13$D_IN; - wire wci_reqERR_13$EN; - - // register wci_reqERR_14 - reg [2 : 0] wci_reqERR_14; - wire [2 : 0] wci_reqERR_14$D_IN; - wire wci_reqERR_14$EN; - - // register wci_reqERR_2 - reg [2 : 0] wci_reqERR_2; - wire [2 : 0] wci_reqERR_2$D_IN; - wire wci_reqERR_2$EN; - - // register wci_reqERR_3 - reg [2 : 0] wci_reqERR_3; - wire [2 : 0] wci_reqERR_3$D_IN; - wire wci_reqERR_3$EN; - - // register wci_reqERR_4 - reg [2 : 0] wci_reqERR_4; - wire [2 : 0] wci_reqERR_4$D_IN; - wire wci_reqERR_4$EN; - - // register wci_reqERR_5 - reg [2 : 0] wci_reqERR_5; - wire [2 : 0] wci_reqERR_5$D_IN; - wire wci_reqERR_5$EN; - - // register wci_reqERR_6 - reg [2 : 0] wci_reqERR_6; - wire [2 : 0] wci_reqERR_6$D_IN; - wire wci_reqERR_6$EN; - - // register wci_reqERR_7 - reg [2 : 0] wci_reqERR_7; - wire [2 : 0] wci_reqERR_7$D_IN; - wire wci_reqERR_7$EN; - - // register wci_reqERR_8 - reg [2 : 0] wci_reqERR_8; - wire [2 : 0] wci_reqERR_8$D_IN; - wire wci_reqERR_8$EN; - - // register wci_reqERR_9 - reg [2 : 0] wci_reqERR_9; - wire [2 : 0] wci_reqERR_9$D_IN; - wire wci_reqERR_9$EN; - - // register wci_reqFAIL - reg [2 : 0] wci_reqFAIL; - wire [2 : 0] wci_reqFAIL$D_IN; - wire wci_reqFAIL$EN; - - // register wci_reqFAIL_1 - reg [2 : 0] wci_reqFAIL_1; - wire [2 : 0] wci_reqFAIL_1$D_IN; - wire wci_reqFAIL_1$EN; - - // register wci_reqFAIL_10 - reg [2 : 0] wci_reqFAIL_10; - wire [2 : 0] wci_reqFAIL_10$D_IN; - wire wci_reqFAIL_10$EN; - - // register wci_reqFAIL_11 - reg [2 : 0] wci_reqFAIL_11; - wire [2 : 0] wci_reqFAIL_11$D_IN; - wire wci_reqFAIL_11$EN; - - // register wci_reqFAIL_12 - reg [2 : 0] wci_reqFAIL_12; - wire [2 : 0] wci_reqFAIL_12$D_IN; - wire wci_reqFAIL_12$EN; - - // register wci_reqFAIL_13 - reg [2 : 0] wci_reqFAIL_13; - wire [2 : 0] wci_reqFAIL_13$D_IN; - wire wci_reqFAIL_13$EN; - - // register wci_reqFAIL_14 - reg [2 : 0] wci_reqFAIL_14; - wire [2 : 0] wci_reqFAIL_14$D_IN; - wire wci_reqFAIL_14$EN; - - // register wci_reqFAIL_2 - reg [2 : 0] wci_reqFAIL_2; - wire [2 : 0] wci_reqFAIL_2$D_IN; - wire wci_reqFAIL_2$EN; - - // register wci_reqFAIL_3 - reg [2 : 0] wci_reqFAIL_3; - wire [2 : 0] wci_reqFAIL_3$D_IN; - wire wci_reqFAIL_3$EN; - - // register wci_reqFAIL_4 - reg [2 : 0] wci_reqFAIL_4; - wire [2 : 0] wci_reqFAIL_4$D_IN; - wire wci_reqFAIL_4$EN; - - // register wci_reqFAIL_5 - reg [2 : 0] wci_reqFAIL_5; - wire [2 : 0] wci_reqFAIL_5$D_IN; - wire wci_reqFAIL_5$EN; - - // register wci_reqFAIL_6 - reg [2 : 0] wci_reqFAIL_6; - wire [2 : 0] wci_reqFAIL_6$D_IN; - wire wci_reqFAIL_6$EN; - - // register wci_reqFAIL_7 - reg [2 : 0] wci_reqFAIL_7; - wire [2 : 0] wci_reqFAIL_7$D_IN; - wire wci_reqFAIL_7$EN; - - // register wci_reqFAIL_8 - reg [2 : 0] wci_reqFAIL_8; - wire [2 : 0] wci_reqFAIL_8$D_IN; - wire wci_reqFAIL_8$EN; - - // register wci_reqFAIL_9 - reg [2 : 0] wci_reqFAIL_9; - wire [2 : 0] wci_reqFAIL_9$D_IN; - wire wci_reqFAIL_9$EN; - - // register wci_reqF_10_c_r - reg wci_reqF_10_c_r; - wire wci_reqF_10_c_r$D_IN, wci_reqF_10_c_r$EN; - - // register wci_reqF_10_q_0 - reg [71 : 0] wci_reqF_10_q_0; - reg [71 : 0] wci_reqF_10_q_0$D_IN; - wire wci_reqF_10_q_0$EN; - - // register wci_reqF_11_c_r - reg wci_reqF_11_c_r; - wire wci_reqF_11_c_r$D_IN, wci_reqF_11_c_r$EN; - - // register wci_reqF_11_q_0 - reg [71 : 0] wci_reqF_11_q_0; - reg [71 : 0] wci_reqF_11_q_0$D_IN; - wire wci_reqF_11_q_0$EN; - - // register wci_reqF_12_c_r - reg wci_reqF_12_c_r; - wire wci_reqF_12_c_r$D_IN, wci_reqF_12_c_r$EN; - - // register wci_reqF_12_q_0 - reg [71 : 0] wci_reqF_12_q_0; - reg [71 : 0] wci_reqF_12_q_0$D_IN; - wire wci_reqF_12_q_0$EN; - - // register wci_reqF_13_c_r - reg wci_reqF_13_c_r; - wire wci_reqF_13_c_r$D_IN, wci_reqF_13_c_r$EN; - - // register wci_reqF_13_q_0 - reg [71 : 0] wci_reqF_13_q_0; - reg [71 : 0] wci_reqF_13_q_0$D_IN; - wire wci_reqF_13_q_0$EN; - - // register wci_reqF_14_c_r - reg wci_reqF_14_c_r; - wire wci_reqF_14_c_r$D_IN, wci_reqF_14_c_r$EN; - - // register wci_reqF_14_q_0 - reg [71 : 0] wci_reqF_14_q_0; - reg [71 : 0] wci_reqF_14_q_0$D_IN; - wire wci_reqF_14_q_0$EN; - - // register wci_reqF_1_c_r - reg wci_reqF_1_c_r; - wire wci_reqF_1_c_r$D_IN, wci_reqF_1_c_r$EN; - - // register wci_reqF_1_q_0 - reg [71 : 0] wci_reqF_1_q_0; - reg [71 : 0] wci_reqF_1_q_0$D_IN; - wire wci_reqF_1_q_0$EN; - - // register wci_reqF_2_c_r - reg wci_reqF_2_c_r; - wire wci_reqF_2_c_r$D_IN, wci_reqF_2_c_r$EN; - - // register wci_reqF_2_q_0 - reg [71 : 0] wci_reqF_2_q_0; - reg [71 : 0] wci_reqF_2_q_0$D_IN; - wire wci_reqF_2_q_0$EN; - - // register wci_reqF_3_c_r - reg wci_reqF_3_c_r; - wire wci_reqF_3_c_r$D_IN, wci_reqF_3_c_r$EN; - - // register wci_reqF_3_q_0 - reg [71 : 0] wci_reqF_3_q_0; - reg [71 : 0] wci_reqF_3_q_0$D_IN; - wire wci_reqF_3_q_0$EN; - - // register wci_reqF_4_c_r - reg wci_reqF_4_c_r; - wire wci_reqF_4_c_r$D_IN, wci_reqF_4_c_r$EN; - - // register wci_reqF_4_q_0 - reg [71 : 0] wci_reqF_4_q_0; - reg [71 : 0] wci_reqF_4_q_0$D_IN; - wire wci_reqF_4_q_0$EN; - - // register wci_reqF_5_c_r - reg wci_reqF_5_c_r; - wire wci_reqF_5_c_r$D_IN, wci_reqF_5_c_r$EN; - - // register wci_reqF_5_q_0 - reg [71 : 0] wci_reqF_5_q_0; - reg [71 : 0] wci_reqF_5_q_0$D_IN; - wire wci_reqF_5_q_0$EN; - - // register wci_reqF_6_c_r - reg wci_reqF_6_c_r; - wire wci_reqF_6_c_r$D_IN, wci_reqF_6_c_r$EN; - - // register wci_reqF_6_q_0 - reg [71 : 0] wci_reqF_6_q_0; - reg [71 : 0] wci_reqF_6_q_0$D_IN; - wire wci_reqF_6_q_0$EN; - - // register wci_reqF_7_c_r - reg wci_reqF_7_c_r; - wire wci_reqF_7_c_r$D_IN, wci_reqF_7_c_r$EN; - - // register wci_reqF_7_q_0 - reg [71 : 0] wci_reqF_7_q_0; - reg [71 : 0] wci_reqF_7_q_0$D_IN; - wire wci_reqF_7_q_0$EN; - - // register wci_reqF_8_c_r - reg wci_reqF_8_c_r; - wire wci_reqF_8_c_r$D_IN, wci_reqF_8_c_r$EN; - - // register wci_reqF_8_q_0 - reg [71 : 0] wci_reqF_8_q_0; - reg [71 : 0] wci_reqF_8_q_0$D_IN; - wire wci_reqF_8_q_0$EN; - - // register wci_reqF_9_c_r - reg wci_reqF_9_c_r; - wire wci_reqF_9_c_r$D_IN, wci_reqF_9_c_r$EN; - - // register wci_reqF_9_q_0 - reg [71 : 0] wci_reqF_9_q_0; - reg [71 : 0] wci_reqF_9_q_0$D_IN; - wire wci_reqF_9_q_0$EN; - - // register wci_reqF_c_r - reg wci_reqF_c_r; - wire wci_reqF_c_r$D_IN, wci_reqF_c_r$EN; - - // register wci_reqF_q_0 - reg [71 : 0] wci_reqF_q_0; - reg [71 : 0] wci_reqF_q_0$D_IN; - wire wci_reqF_q_0$EN; - - // register wci_reqPend - reg [1 : 0] wci_reqPend; - reg [1 : 0] wci_reqPend$D_IN; - wire wci_reqPend$EN; - - // register wci_reqPend_1 - reg [1 : 0] wci_reqPend_1; - reg [1 : 0] wci_reqPend_1$D_IN; - wire wci_reqPend_1$EN; - - // register wci_reqPend_10 - reg [1 : 0] wci_reqPend_10; - reg [1 : 0] wci_reqPend_10$D_IN; - wire wci_reqPend_10$EN; - - // register wci_reqPend_11 - reg [1 : 0] wci_reqPend_11; - reg [1 : 0] wci_reqPend_11$D_IN; - wire wci_reqPend_11$EN; - - // register wci_reqPend_12 - reg [1 : 0] wci_reqPend_12; - reg [1 : 0] wci_reqPend_12$D_IN; - wire wci_reqPend_12$EN; - - // register wci_reqPend_13 - reg [1 : 0] wci_reqPend_13; - reg [1 : 0] wci_reqPend_13$D_IN; - wire wci_reqPend_13$EN; - - // register wci_reqPend_14 - reg [1 : 0] wci_reqPend_14; - reg [1 : 0] wci_reqPend_14$D_IN; - wire wci_reqPend_14$EN; - - // register wci_reqPend_2 - reg [1 : 0] wci_reqPend_2; - reg [1 : 0] wci_reqPend_2$D_IN; - wire wci_reqPend_2$EN; - - // register wci_reqPend_3 - reg [1 : 0] wci_reqPend_3; - reg [1 : 0] wci_reqPend_3$D_IN; - wire wci_reqPend_3$EN; - - // register wci_reqPend_4 - reg [1 : 0] wci_reqPend_4; - reg [1 : 0] wci_reqPend_4$D_IN; - wire wci_reqPend_4$EN; - - // register wci_reqPend_5 - reg [1 : 0] wci_reqPend_5; - reg [1 : 0] wci_reqPend_5$D_IN; - wire wci_reqPend_5$EN; - - // register wci_reqPend_6 - reg [1 : 0] wci_reqPend_6; - reg [1 : 0] wci_reqPend_6$D_IN; - wire wci_reqPend_6$EN; - - // register wci_reqPend_7 - reg [1 : 0] wci_reqPend_7; - reg [1 : 0] wci_reqPend_7$D_IN; - wire wci_reqPend_7$EN; - - // register wci_reqPend_8 - reg [1 : 0] wci_reqPend_8; - reg [1 : 0] wci_reqPend_8$D_IN; - wire wci_reqPend_8$EN; - - // register wci_reqPend_9 - reg [1 : 0] wci_reqPend_9; - reg [1 : 0] wci_reqPend_9$D_IN; - wire wci_reqPend_9$EN; - - // register wci_reqTO - reg [2 : 0] wci_reqTO; - wire [2 : 0] wci_reqTO$D_IN; - wire wci_reqTO$EN; - - // register wci_reqTO_1 - reg [2 : 0] wci_reqTO_1; - wire [2 : 0] wci_reqTO_1$D_IN; - wire wci_reqTO_1$EN; - - // register wci_reqTO_10 - reg [2 : 0] wci_reqTO_10; - wire [2 : 0] wci_reqTO_10$D_IN; - wire wci_reqTO_10$EN; - - // register wci_reqTO_11 - reg [2 : 0] wci_reqTO_11; - wire [2 : 0] wci_reqTO_11$D_IN; - wire wci_reqTO_11$EN; - - // register wci_reqTO_12 - reg [2 : 0] wci_reqTO_12; - wire [2 : 0] wci_reqTO_12$D_IN; - wire wci_reqTO_12$EN; - - // register wci_reqTO_13 - reg [2 : 0] wci_reqTO_13; - wire [2 : 0] wci_reqTO_13$D_IN; - wire wci_reqTO_13$EN; - - // register wci_reqTO_14 - reg [2 : 0] wci_reqTO_14; - wire [2 : 0] wci_reqTO_14$D_IN; - wire wci_reqTO_14$EN; - - // register wci_reqTO_2 - reg [2 : 0] wci_reqTO_2; - wire [2 : 0] wci_reqTO_2$D_IN; - wire wci_reqTO_2$EN; - - // register wci_reqTO_3 - reg [2 : 0] wci_reqTO_3; - wire [2 : 0] wci_reqTO_3$D_IN; - wire wci_reqTO_3$EN; - - // register wci_reqTO_4 - reg [2 : 0] wci_reqTO_4; - wire [2 : 0] wci_reqTO_4$D_IN; - wire wci_reqTO_4$EN; - - // register wci_reqTO_5 - reg [2 : 0] wci_reqTO_5; - wire [2 : 0] wci_reqTO_5$D_IN; - wire wci_reqTO_5$EN; - - // register wci_reqTO_6 - reg [2 : 0] wci_reqTO_6; - wire [2 : 0] wci_reqTO_6$D_IN; - wire wci_reqTO_6$EN; - - // register wci_reqTO_7 - reg [2 : 0] wci_reqTO_7; - wire [2 : 0] wci_reqTO_7$D_IN; - wire wci_reqTO_7$EN; - - // register wci_reqTO_8 - reg [2 : 0] wci_reqTO_8; - wire [2 : 0] wci_reqTO_8$D_IN; - wire wci_reqTO_8$EN; - - // register wci_reqTO_9 - reg [2 : 0] wci_reqTO_9; - wire [2 : 0] wci_reqTO_9$D_IN; - wire wci_reqTO_9$EN; - - // register wci_respTimr - reg [31 : 0] wci_respTimr; - wire [31 : 0] wci_respTimr$D_IN; - wire wci_respTimr$EN; - - // register wci_respTimrAct - reg wci_respTimrAct; - wire wci_respTimrAct$D_IN, wci_respTimrAct$EN; - - // register wci_respTimrAct_1 - reg wci_respTimrAct_1; - wire wci_respTimrAct_1$D_IN, wci_respTimrAct_1$EN; - - // register wci_respTimrAct_10 - reg wci_respTimrAct_10; - wire wci_respTimrAct_10$D_IN, wci_respTimrAct_10$EN; - - // register wci_respTimrAct_11 - reg wci_respTimrAct_11; - wire wci_respTimrAct_11$D_IN, wci_respTimrAct_11$EN; - - // register wci_respTimrAct_12 - reg wci_respTimrAct_12; - wire wci_respTimrAct_12$D_IN, wci_respTimrAct_12$EN; - - // register wci_respTimrAct_13 - reg wci_respTimrAct_13; - wire wci_respTimrAct_13$D_IN, wci_respTimrAct_13$EN; - - // register wci_respTimrAct_14 - reg wci_respTimrAct_14; - wire wci_respTimrAct_14$D_IN, wci_respTimrAct_14$EN; - - // register wci_respTimrAct_2 - reg wci_respTimrAct_2; - wire wci_respTimrAct_2$D_IN, wci_respTimrAct_2$EN; - - // register wci_respTimrAct_3 - reg wci_respTimrAct_3; - wire wci_respTimrAct_3$D_IN, wci_respTimrAct_3$EN; - - // register wci_respTimrAct_4 - reg wci_respTimrAct_4; - wire wci_respTimrAct_4$D_IN, wci_respTimrAct_4$EN; - - // register wci_respTimrAct_5 - reg wci_respTimrAct_5; - wire wci_respTimrAct_5$D_IN, wci_respTimrAct_5$EN; - - // register wci_respTimrAct_6 - reg wci_respTimrAct_6; - wire wci_respTimrAct_6$D_IN, wci_respTimrAct_6$EN; - - // register wci_respTimrAct_7 - reg wci_respTimrAct_7; - wire wci_respTimrAct_7$D_IN, wci_respTimrAct_7$EN; - - // register wci_respTimrAct_8 - reg wci_respTimrAct_8; - wire wci_respTimrAct_8$D_IN, wci_respTimrAct_8$EN; - - // register wci_respTimrAct_9 - reg wci_respTimrAct_9; - wire wci_respTimrAct_9$D_IN, wci_respTimrAct_9$EN; - - // register wci_respTimr_1 - reg [31 : 0] wci_respTimr_1; - wire [31 : 0] wci_respTimr_1$D_IN; - wire wci_respTimr_1$EN; - - // register wci_respTimr_10 - reg [31 : 0] wci_respTimr_10; - wire [31 : 0] wci_respTimr_10$D_IN; - wire wci_respTimr_10$EN; - - // register wci_respTimr_11 - reg [31 : 0] wci_respTimr_11; - wire [31 : 0] wci_respTimr_11$D_IN; - wire wci_respTimr_11$EN; - - // register wci_respTimr_12 - reg [31 : 0] wci_respTimr_12; - wire [31 : 0] wci_respTimr_12$D_IN; - wire wci_respTimr_12$EN; - - // register wci_respTimr_13 - reg [31 : 0] wci_respTimr_13; - wire [31 : 0] wci_respTimr_13$D_IN; - wire wci_respTimr_13$EN; - - // register wci_respTimr_14 - reg [31 : 0] wci_respTimr_14; - wire [31 : 0] wci_respTimr_14$D_IN; - wire wci_respTimr_14$EN; - - // register wci_respTimr_2 - reg [31 : 0] wci_respTimr_2; - wire [31 : 0] wci_respTimr_2$D_IN; - wire wci_respTimr_2$EN; - - // register wci_respTimr_3 - reg [31 : 0] wci_respTimr_3; - wire [31 : 0] wci_respTimr_3$D_IN; - wire wci_respTimr_3$EN; - - // register wci_respTimr_4 - reg [31 : 0] wci_respTimr_4; - wire [31 : 0] wci_respTimr_4$D_IN; - wire wci_respTimr_4$EN; - - // register wci_respTimr_5 - reg [31 : 0] wci_respTimr_5; - wire [31 : 0] wci_respTimr_5$D_IN; - wire wci_respTimr_5$EN; - - // register wci_respTimr_6 - reg [31 : 0] wci_respTimr_6; - wire [31 : 0] wci_respTimr_6$D_IN; - wire wci_respTimr_6$EN; - - // register wci_respTimr_7 - reg [31 : 0] wci_respTimr_7; - wire [31 : 0] wci_respTimr_7$D_IN; - wire wci_respTimr_7$EN; - - // register wci_respTimr_8 - reg [31 : 0] wci_respTimr_8; - wire [31 : 0] wci_respTimr_8$D_IN; - wire wci_respTimr_8$EN; - - // register wci_respTimr_9 - reg [31 : 0] wci_respTimr_9; - wire [31 : 0] wci_respTimr_9$D_IN; - wire wci_respTimr_9$EN; - - // register wci_sThreadBusy_d - reg wci_sThreadBusy_d; - wire wci_sThreadBusy_d$D_IN, wci_sThreadBusy_d$EN; - - // register wci_sThreadBusy_d_1 - reg wci_sThreadBusy_d_1; - wire wci_sThreadBusy_d_1$D_IN, wci_sThreadBusy_d_1$EN; - - // register wci_sThreadBusy_d_10 - reg wci_sThreadBusy_d_10; - wire wci_sThreadBusy_d_10$D_IN, wci_sThreadBusy_d_10$EN; - - // register wci_sThreadBusy_d_11 - reg wci_sThreadBusy_d_11; - wire wci_sThreadBusy_d_11$D_IN, wci_sThreadBusy_d_11$EN; - - // register wci_sThreadBusy_d_12 - reg wci_sThreadBusy_d_12; - wire wci_sThreadBusy_d_12$D_IN, wci_sThreadBusy_d_12$EN; - - // register wci_sThreadBusy_d_13 - reg wci_sThreadBusy_d_13; - wire wci_sThreadBusy_d_13$D_IN, wci_sThreadBusy_d_13$EN; - - // register wci_sThreadBusy_d_14 - reg wci_sThreadBusy_d_14; - wire wci_sThreadBusy_d_14$D_IN, wci_sThreadBusy_d_14$EN; - - // register wci_sThreadBusy_d_2 - reg wci_sThreadBusy_d_2; - wire wci_sThreadBusy_d_2$D_IN, wci_sThreadBusy_d_2$EN; - - // register wci_sThreadBusy_d_3 - reg wci_sThreadBusy_d_3; - wire wci_sThreadBusy_d_3$D_IN, wci_sThreadBusy_d_3$EN; - - // register wci_sThreadBusy_d_4 - reg wci_sThreadBusy_d_4; - wire wci_sThreadBusy_d_4$D_IN, wci_sThreadBusy_d_4$EN; - - // register wci_sThreadBusy_d_5 - reg wci_sThreadBusy_d_5; - wire wci_sThreadBusy_d_5$D_IN, wci_sThreadBusy_d_5$EN; - - // register wci_sThreadBusy_d_6 - reg wci_sThreadBusy_d_6; - wire wci_sThreadBusy_d_6$D_IN, wci_sThreadBusy_d_6$EN; - - // register wci_sThreadBusy_d_7 - reg wci_sThreadBusy_d_7; - wire wci_sThreadBusy_d_7$D_IN, wci_sThreadBusy_d_7$EN; - - // register wci_sThreadBusy_d_8 - reg wci_sThreadBusy_d_8; - wire wci_sThreadBusy_d_8$D_IN, wci_sThreadBusy_d_8$EN; - - // register wci_sThreadBusy_d_9 - reg wci_sThreadBusy_d_9; - wire wci_sThreadBusy_d_9$D_IN, wci_sThreadBusy_d_9$EN; - - // register wci_sfCap - reg wci_sfCap; - wire wci_sfCap$D_IN, wci_sfCap$EN; - - // register wci_sfCapClear - reg wci_sfCapClear; - wire wci_sfCapClear$D_IN, wci_sfCapClear$EN; - - // register wci_sfCapClear_10 - reg wci_sfCapClear_10; - wire wci_sfCapClear_10$D_IN, wci_sfCapClear_10$EN; - - // register wci_sfCapClear_11 - reg wci_sfCapClear_11; - wire wci_sfCapClear_11$D_IN, wci_sfCapClear_11$EN; - - // register wci_sfCapClear_12 - reg wci_sfCapClear_12; - wire wci_sfCapClear_12$D_IN, wci_sfCapClear_12$EN; - - // register wci_sfCapClear_13 - reg wci_sfCapClear_13; - wire wci_sfCapClear_13$D_IN, wci_sfCapClear_13$EN; - - // register wci_sfCapClear_14 - reg wci_sfCapClear_14; - wire wci_sfCapClear_14$D_IN, wci_sfCapClear_14$EN; - - // register wci_sfCapClear_1_1 - reg wci_sfCapClear_1_1; - wire wci_sfCapClear_1_1$D_IN, wci_sfCapClear_1_1$EN; - - // register wci_sfCapClear_2 - reg wci_sfCapClear_2; - wire wci_sfCapClear_2$D_IN, wci_sfCapClear_2$EN; - - // register wci_sfCapClear_3 - reg wci_sfCapClear_3; - wire wci_sfCapClear_3$D_IN, wci_sfCapClear_3$EN; - - // register wci_sfCapClear_4 - reg wci_sfCapClear_4; - wire wci_sfCapClear_4$D_IN, wci_sfCapClear_4$EN; - - // register wci_sfCapClear_5 - reg wci_sfCapClear_5; - wire wci_sfCapClear_5$D_IN, wci_sfCapClear_5$EN; - - // register wci_sfCapClear_6 - reg wci_sfCapClear_6; - wire wci_sfCapClear_6$D_IN, wci_sfCapClear_6$EN; - - // register wci_sfCapClear_7 - reg wci_sfCapClear_7; - wire wci_sfCapClear_7$D_IN, wci_sfCapClear_7$EN; - - // register wci_sfCapClear_8 - reg wci_sfCapClear_8; - wire wci_sfCapClear_8$D_IN, wci_sfCapClear_8$EN; - - // register wci_sfCapClear_9 - reg wci_sfCapClear_9; - wire wci_sfCapClear_9$D_IN, wci_sfCapClear_9$EN; - - // register wci_sfCapSet - reg wci_sfCapSet; - wire wci_sfCapSet$D_IN, wci_sfCapSet$EN; - - // register wci_sfCapSet_10 - reg wci_sfCapSet_10; - wire wci_sfCapSet_10$D_IN, wci_sfCapSet_10$EN; - - // register wci_sfCapSet_11 - reg wci_sfCapSet_11; - wire wci_sfCapSet_11$D_IN, wci_sfCapSet_11$EN; - - // register wci_sfCapSet_12 - reg wci_sfCapSet_12; - wire wci_sfCapSet_12$D_IN, wci_sfCapSet_12$EN; - - // register wci_sfCapSet_13 - reg wci_sfCapSet_13; - wire wci_sfCapSet_13$D_IN, wci_sfCapSet_13$EN; - - // register wci_sfCapSet_14 - reg wci_sfCapSet_14; - wire wci_sfCapSet_14$D_IN, wci_sfCapSet_14$EN; - - // register wci_sfCapSet_1_1 - reg wci_sfCapSet_1_1; - wire wci_sfCapSet_1_1$D_IN, wci_sfCapSet_1_1$EN; - - // register wci_sfCapSet_2 - reg wci_sfCapSet_2; - wire wci_sfCapSet_2$D_IN, wci_sfCapSet_2$EN; - - // register wci_sfCapSet_3 - reg wci_sfCapSet_3; - wire wci_sfCapSet_3$D_IN, wci_sfCapSet_3$EN; - - // register wci_sfCapSet_4 - reg wci_sfCapSet_4; - wire wci_sfCapSet_4$D_IN, wci_sfCapSet_4$EN; - - // register wci_sfCapSet_5 - reg wci_sfCapSet_5; - wire wci_sfCapSet_5$D_IN, wci_sfCapSet_5$EN; - - // register wci_sfCapSet_6 - reg wci_sfCapSet_6; - wire wci_sfCapSet_6$D_IN, wci_sfCapSet_6$EN; - - // register wci_sfCapSet_7 - reg wci_sfCapSet_7; - wire wci_sfCapSet_7$D_IN, wci_sfCapSet_7$EN; - - // register wci_sfCapSet_8 - reg wci_sfCapSet_8; - wire wci_sfCapSet_8$D_IN, wci_sfCapSet_8$EN; - - // register wci_sfCapSet_9 - reg wci_sfCapSet_9; - wire wci_sfCapSet_9$D_IN, wci_sfCapSet_9$EN; - - // register wci_sfCap_1 - reg wci_sfCap_1; - wire wci_sfCap_1$D_IN, wci_sfCap_1$EN; - - // register wci_sfCap_10 - reg wci_sfCap_10; - wire wci_sfCap_10$D_IN, wci_sfCap_10$EN; - - // register wci_sfCap_11 - reg wci_sfCap_11; - wire wci_sfCap_11$D_IN, wci_sfCap_11$EN; - - // register wci_sfCap_12 - reg wci_sfCap_12; - wire wci_sfCap_12$D_IN, wci_sfCap_12$EN; - - // register wci_sfCap_13 - reg wci_sfCap_13; - wire wci_sfCap_13$D_IN, wci_sfCap_13$EN; - - // register wci_sfCap_14 - reg wci_sfCap_14; - wire wci_sfCap_14$D_IN, wci_sfCap_14$EN; - - // register wci_sfCap_2 - reg wci_sfCap_2; - wire wci_sfCap_2$D_IN, wci_sfCap_2$EN; - - // register wci_sfCap_3 - reg wci_sfCap_3; - wire wci_sfCap_3$D_IN, wci_sfCap_3$EN; - - // register wci_sfCap_4 - reg wci_sfCap_4; - wire wci_sfCap_4$D_IN, wci_sfCap_4$EN; - - // register wci_sfCap_5 - reg wci_sfCap_5; - wire wci_sfCap_5$D_IN, wci_sfCap_5$EN; - - // register wci_sfCap_6 - reg wci_sfCap_6; - wire wci_sfCap_6$D_IN, wci_sfCap_6$EN; - - // register wci_sfCap_7 - reg wci_sfCap_7; - wire wci_sfCap_7$D_IN, wci_sfCap_7$EN; - - // register wci_sfCap_8 - reg wci_sfCap_8; - wire wci_sfCap_8$D_IN, wci_sfCap_8$EN; - - // register wci_sfCap_9 - reg wci_sfCap_9; - wire wci_sfCap_9$D_IN, wci_sfCap_9$EN; - - // register wci_slvPresent - reg wci_slvPresent; - wire wci_slvPresent$D_IN, wci_slvPresent$EN; - - // register wci_slvPresent_1 - reg wci_slvPresent_1; - wire wci_slvPresent_1$D_IN, wci_slvPresent_1$EN; - - // register wci_slvPresent_10 - reg wci_slvPresent_10; - wire wci_slvPresent_10$D_IN, wci_slvPresent_10$EN; - - // register wci_slvPresent_11 - reg wci_slvPresent_11; - wire wci_slvPresent_11$D_IN, wci_slvPresent_11$EN; - - // register wci_slvPresent_12 - reg wci_slvPresent_12; - wire wci_slvPresent_12$D_IN, wci_slvPresent_12$EN; - - // register wci_slvPresent_13 - reg wci_slvPresent_13; - wire wci_slvPresent_13$D_IN, wci_slvPresent_13$EN; - - // register wci_slvPresent_14 - reg wci_slvPresent_14; - wire wci_slvPresent_14$D_IN, wci_slvPresent_14$EN; - - // register wci_slvPresent_2 - reg wci_slvPresent_2; - wire wci_slvPresent_2$D_IN, wci_slvPresent_2$EN; - - // register wci_slvPresent_3 - reg wci_slvPresent_3; - wire wci_slvPresent_3$D_IN, wci_slvPresent_3$EN; - - // register wci_slvPresent_4 - reg wci_slvPresent_4; - wire wci_slvPresent_4$D_IN, wci_slvPresent_4$EN; - - // register wci_slvPresent_5 - reg wci_slvPresent_5; - wire wci_slvPresent_5$D_IN, wci_slvPresent_5$EN; - - // register wci_slvPresent_6 - reg wci_slvPresent_6; - wire wci_slvPresent_6$D_IN, wci_slvPresent_6$EN; - - // register wci_slvPresent_7 - reg wci_slvPresent_7; - wire wci_slvPresent_7$D_IN, wci_slvPresent_7$EN; - - // register wci_slvPresent_8 - reg wci_slvPresent_8; - wire wci_slvPresent_8$D_IN, wci_slvPresent_8$EN; - - // register wci_slvPresent_9 - reg wci_slvPresent_9; - wire wci_slvPresent_9$D_IN, wci_slvPresent_9$EN; - - // register wci_wReset_n - reg wci_wReset_n; - wire wci_wReset_n$D_IN, wci_wReset_n$EN; - - // register wci_wReset_n_1 - reg wci_wReset_n_1; - wire wci_wReset_n_1$D_IN, wci_wReset_n_1$EN; - - // register wci_wReset_n_10 - reg wci_wReset_n_10; - wire wci_wReset_n_10$D_IN, wci_wReset_n_10$EN; - - // register wci_wReset_n_11 - reg wci_wReset_n_11; - wire wci_wReset_n_11$D_IN, wci_wReset_n_11$EN; - - // register wci_wReset_n_12 - reg wci_wReset_n_12; - wire wci_wReset_n_12$D_IN, wci_wReset_n_12$EN; - - // register wci_wReset_n_13 - reg wci_wReset_n_13; - wire wci_wReset_n_13$D_IN, wci_wReset_n_13$EN; - - // register wci_wReset_n_14 - reg wci_wReset_n_14; - wire wci_wReset_n_14$D_IN, wci_wReset_n_14$EN; - - // register wci_wReset_n_2 - reg wci_wReset_n_2; - wire wci_wReset_n_2$D_IN, wci_wReset_n_2$EN; - - // register wci_wReset_n_3 - reg wci_wReset_n_3; - wire wci_wReset_n_3$D_IN, wci_wReset_n_3$EN; - - // register wci_wReset_n_4 - reg wci_wReset_n_4; - wire wci_wReset_n_4$D_IN, wci_wReset_n_4$EN; - - // register wci_wReset_n_5 - reg wci_wReset_n_5; - wire wci_wReset_n_5$D_IN, wci_wReset_n_5$EN; - - // register wci_wReset_n_6 - reg wci_wReset_n_6; - wire wci_wReset_n_6$D_IN, wci_wReset_n_6$EN; - - // register wci_wReset_n_7 - reg wci_wReset_n_7; - wire wci_wReset_n_7$D_IN, wci_wReset_n_7$EN; - - // register wci_wReset_n_8 - reg wci_wReset_n_8; - wire wci_wReset_n_8$D_IN, wci_wReset_n_8$EN; - - // register wci_wReset_n_9 - reg wci_wReset_n_9; - wire wci_wReset_n_9$D_IN, wci_wReset_n_9$EN; - - // register wci_wStatus - reg [31 : 0] wci_wStatus; - wire [31 : 0] wci_wStatus$D_IN; - wire wci_wStatus$EN; - - // register wci_wStatus_1 - reg [31 : 0] wci_wStatus_1; - wire [31 : 0] wci_wStatus_1$D_IN; - wire wci_wStatus_1$EN; - - // register wci_wStatus_10 - reg [31 : 0] wci_wStatus_10; - wire [31 : 0] wci_wStatus_10$D_IN; - wire wci_wStatus_10$EN; - - // register wci_wStatus_11 - reg [31 : 0] wci_wStatus_11; - wire [31 : 0] wci_wStatus_11$D_IN; - wire wci_wStatus_11$EN; - - // register wci_wStatus_12 - reg [31 : 0] wci_wStatus_12; - wire [31 : 0] wci_wStatus_12$D_IN; - wire wci_wStatus_12$EN; - - // register wci_wStatus_13 - reg [31 : 0] wci_wStatus_13; - wire [31 : 0] wci_wStatus_13$D_IN; - wire wci_wStatus_13$EN; - - // register wci_wStatus_14 - reg [31 : 0] wci_wStatus_14; - wire [31 : 0] wci_wStatus_14$D_IN; - wire wci_wStatus_14$EN; - - // register wci_wStatus_2 - reg [31 : 0] wci_wStatus_2; - wire [31 : 0] wci_wStatus_2$D_IN; - wire wci_wStatus_2$EN; - - // register wci_wStatus_3 - reg [31 : 0] wci_wStatus_3; - wire [31 : 0] wci_wStatus_3$D_IN; - wire wci_wStatus_3$EN; - - // register wci_wStatus_4 - reg [31 : 0] wci_wStatus_4; - wire [31 : 0] wci_wStatus_4$D_IN; - wire wci_wStatus_4$EN; - - // register wci_wStatus_5 - reg [31 : 0] wci_wStatus_5; - wire [31 : 0] wci_wStatus_5$D_IN; - wire wci_wStatus_5$EN; - - // register wci_wStatus_6 - reg [31 : 0] wci_wStatus_6; - wire [31 : 0] wci_wStatus_6$D_IN; - wire wci_wStatus_6$EN; - - // register wci_wStatus_7 - reg [31 : 0] wci_wStatus_7; - wire [31 : 0] wci_wStatus_7$D_IN; - wire wci_wStatus_7$EN; - - // register wci_wStatus_8 - reg [31 : 0] wci_wStatus_8; - wire [31 : 0] wci_wStatus_8$D_IN; - wire wci_wStatus_8$EN; - - // register wci_wStatus_9 - reg [31 : 0] wci_wStatus_9; - wire [31 : 0] wci_wStatus_9$D_IN; - wire wci_wStatus_9$EN; - - // register wci_wTimeout - reg [4 : 0] wci_wTimeout; - wire [4 : 0] wci_wTimeout$D_IN; - wire wci_wTimeout$EN; - - // register wci_wTimeout_1 - reg [4 : 0] wci_wTimeout_1; - wire [4 : 0] wci_wTimeout_1$D_IN; - wire wci_wTimeout_1$EN; - - // register wci_wTimeout_10 - reg [4 : 0] wci_wTimeout_10; - wire [4 : 0] wci_wTimeout_10$D_IN; - wire wci_wTimeout_10$EN; - - // register wci_wTimeout_11 - reg [4 : 0] wci_wTimeout_11; - wire [4 : 0] wci_wTimeout_11$D_IN; - wire wci_wTimeout_11$EN; - - // register wci_wTimeout_12 - reg [4 : 0] wci_wTimeout_12; - wire [4 : 0] wci_wTimeout_12$D_IN; - wire wci_wTimeout_12$EN; - - // register wci_wTimeout_13 - reg [4 : 0] wci_wTimeout_13; - wire [4 : 0] wci_wTimeout_13$D_IN; - wire wci_wTimeout_13$EN; - - // register wci_wTimeout_14 - reg [4 : 0] wci_wTimeout_14; - wire [4 : 0] wci_wTimeout_14$D_IN; - wire wci_wTimeout_14$EN; - - // register wci_wTimeout_2 - reg [4 : 0] wci_wTimeout_2; - wire [4 : 0] wci_wTimeout_2$D_IN; - wire wci_wTimeout_2$EN; - - // register wci_wTimeout_3 - reg [4 : 0] wci_wTimeout_3; - wire [4 : 0] wci_wTimeout_3$D_IN; - wire wci_wTimeout_3$EN; - - // register wci_wTimeout_4 - reg [4 : 0] wci_wTimeout_4; - wire [4 : 0] wci_wTimeout_4$D_IN; - wire wci_wTimeout_4$EN; - - // register wci_wTimeout_5 - reg [4 : 0] wci_wTimeout_5; - wire [4 : 0] wci_wTimeout_5$D_IN; - wire wci_wTimeout_5$EN; - - // register wci_wTimeout_6 - reg [4 : 0] wci_wTimeout_6; - wire [4 : 0] wci_wTimeout_6$D_IN; - wire wci_wTimeout_6$EN; - - // register wci_wTimeout_7 - reg [4 : 0] wci_wTimeout_7; - wire [4 : 0] wci_wTimeout_7$D_IN; - wire wci_wTimeout_7$EN; - - // register wci_wTimeout_8 - reg [4 : 0] wci_wTimeout_8; - wire [4 : 0] wci_wTimeout_8$D_IN; - wire wci_wTimeout_8$EN; - - // register wci_wTimeout_9 - reg [4 : 0] wci_wTimeout_9; - wire [4 : 0] wci_wTimeout_9$D_IN; - wire wci_wTimeout_9$EN; + // register wci_0_busy + reg wci_0_busy; + wire wci_0_busy$D_IN, wci_0_busy$EN; + + // register wci_0_lastConfigAddr + reg [32 : 0] wci_0_lastConfigAddr; + wire [32 : 0] wci_0_lastConfigAddr$D_IN; + wire wci_0_lastConfigAddr$EN; + + // register wci_0_lastConfigBE + reg [4 : 0] wci_0_lastConfigBE; + wire [4 : 0] wci_0_lastConfigBE$D_IN; + wire wci_0_lastConfigBE$EN; + + // register wci_0_lastControlOp + reg [3 : 0] wci_0_lastControlOp; + wire [3 : 0] wci_0_lastControlOp$D_IN; + wire wci_0_lastControlOp$EN; + + // register wci_0_lastOpWrite + reg [1 : 0] wci_0_lastOpWrite; + wire [1 : 0] wci_0_lastOpWrite$D_IN; + wire wci_0_lastOpWrite$EN; + + // register wci_0_mFlagReg + reg [1 : 0] wci_0_mFlagReg; + wire [1 : 0] wci_0_mFlagReg$D_IN; + wire wci_0_mFlagReg$EN; + + // register wci_0_pageWindow + reg [11 : 0] wci_0_pageWindow; + wire [11 : 0] wci_0_pageWindow$D_IN; + wire wci_0_pageWindow$EN; + + // register wci_0_reqERR + reg [2 : 0] wci_0_reqERR; + wire [2 : 0] wci_0_reqERR$D_IN; + wire wci_0_reqERR$EN; + + // register wci_0_reqFAIL + reg [2 : 0] wci_0_reqFAIL; + wire [2 : 0] wci_0_reqFAIL$D_IN; + wire wci_0_reqFAIL$EN; + + // register wci_0_reqF_cntr_r + reg wci_0_reqF_cntr_r; + wire wci_0_reqF_cntr_r$D_IN, wci_0_reqF_cntr_r$EN; + + // register wci_0_reqF_q_0 + reg [71 : 0] wci_0_reqF_q_0; + reg [71 : 0] wci_0_reqF_q_0$D_IN; + wire wci_0_reqF_q_0$EN; + + // register wci_0_reqPend + reg [1 : 0] wci_0_reqPend; + reg [1 : 0] wci_0_reqPend$D_IN; + wire wci_0_reqPend$EN; + + // register wci_0_reqTO + reg [2 : 0] wci_0_reqTO; + wire [2 : 0] wci_0_reqTO$D_IN; + wire wci_0_reqTO$EN; + + // register wci_0_respTimr + reg [31 : 0] wci_0_respTimr; + wire [31 : 0] wci_0_respTimr$D_IN; + wire wci_0_respTimr$EN; + + // register wci_0_respTimrAct + reg wci_0_respTimrAct; + wire wci_0_respTimrAct$D_IN, wci_0_respTimrAct$EN; + + // register wci_0_sThreadBusy_d + reg wci_0_sThreadBusy_d; + wire wci_0_sThreadBusy_d$D_IN, wci_0_sThreadBusy_d$EN; + + // register wci_0_sfCap + reg wci_0_sfCap; + wire wci_0_sfCap$D_IN, wci_0_sfCap$EN; + + // register wci_0_sfCapClear + reg wci_0_sfCapClear; + wire wci_0_sfCapClear$D_IN, wci_0_sfCapClear$EN; + + // register wci_0_sfCapSet + reg wci_0_sfCapSet; + wire wci_0_sfCapSet$D_IN, wci_0_sfCapSet$EN; + + // register wci_0_slvPresent + reg wci_0_slvPresent; + wire wci_0_slvPresent$D_IN, wci_0_slvPresent$EN; + + // register wci_0_wReset_n + reg wci_0_wReset_n; + wire wci_0_wReset_n$D_IN, wci_0_wReset_n$EN; + + // register wci_0_wStatus + reg [31 : 0] wci_0_wStatus; + wire [31 : 0] wci_0_wStatus$D_IN; + wire wci_0_wStatus$EN; + + // register wci_0_wTimeout + reg [4 : 0] wci_0_wTimeout; + wire [4 : 0] wci_0_wTimeout$D_IN; + wire wci_0_wTimeout$EN; + + // register wci_10_busy + reg wci_10_busy; + wire wci_10_busy$D_IN, wci_10_busy$EN; + + // register wci_10_lastConfigAddr + reg [32 : 0] wci_10_lastConfigAddr; + wire [32 : 0] wci_10_lastConfigAddr$D_IN; + wire wci_10_lastConfigAddr$EN; + + // register wci_10_lastConfigBE + reg [4 : 0] wci_10_lastConfigBE; + wire [4 : 0] wci_10_lastConfigBE$D_IN; + wire wci_10_lastConfigBE$EN; + + // register wci_10_lastControlOp + reg [3 : 0] wci_10_lastControlOp; + wire [3 : 0] wci_10_lastControlOp$D_IN; + wire wci_10_lastControlOp$EN; + + // register wci_10_lastOpWrite + reg [1 : 0] wci_10_lastOpWrite; + wire [1 : 0] wci_10_lastOpWrite$D_IN; + wire wci_10_lastOpWrite$EN; + + // register wci_10_mFlagReg + reg [1 : 0] wci_10_mFlagReg; + wire [1 : 0] wci_10_mFlagReg$D_IN; + wire wci_10_mFlagReg$EN; + + // register wci_10_pageWindow + reg [11 : 0] wci_10_pageWindow; + wire [11 : 0] wci_10_pageWindow$D_IN; + wire wci_10_pageWindow$EN; + + // register wci_10_reqERR + reg [2 : 0] wci_10_reqERR; + wire [2 : 0] wci_10_reqERR$D_IN; + wire wci_10_reqERR$EN; + + // register wci_10_reqFAIL + reg [2 : 0] wci_10_reqFAIL; + wire [2 : 0] wci_10_reqFAIL$D_IN; + wire wci_10_reqFAIL$EN; + + // register wci_10_reqF_cntr_r + reg wci_10_reqF_cntr_r; + wire wci_10_reqF_cntr_r$D_IN, wci_10_reqF_cntr_r$EN; + + // register wci_10_reqF_q_0 + reg [71 : 0] wci_10_reqF_q_0; + reg [71 : 0] wci_10_reqF_q_0$D_IN; + wire wci_10_reqF_q_0$EN; + + // register wci_10_reqPend + reg [1 : 0] wci_10_reqPend; + reg [1 : 0] wci_10_reqPend$D_IN; + wire wci_10_reqPend$EN; + + // register wci_10_reqTO + reg [2 : 0] wci_10_reqTO; + wire [2 : 0] wci_10_reqTO$D_IN; + wire wci_10_reqTO$EN; + + // register wci_10_respTimr + reg [31 : 0] wci_10_respTimr; + wire [31 : 0] wci_10_respTimr$D_IN; + wire wci_10_respTimr$EN; + + // register wci_10_respTimrAct + reg wci_10_respTimrAct; + wire wci_10_respTimrAct$D_IN, wci_10_respTimrAct$EN; + + // register wci_10_sThreadBusy_d + reg wci_10_sThreadBusy_d; + wire wci_10_sThreadBusy_d$D_IN, wci_10_sThreadBusy_d$EN; + + // register wci_10_sfCap + reg wci_10_sfCap; + wire wci_10_sfCap$D_IN, wci_10_sfCap$EN; + + // register wci_10_sfCapClear + reg wci_10_sfCapClear; + wire wci_10_sfCapClear$D_IN, wci_10_sfCapClear$EN; + + // register wci_10_sfCapSet + reg wci_10_sfCapSet; + wire wci_10_sfCapSet$D_IN, wci_10_sfCapSet$EN; + + // register wci_10_slvPresent + reg wci_10_slvPresent; + wire wci_10_slvPresent$D_IN, wci_10_slvPresent$EN; + + // register wci_10_wReset_n + reg wci_10_wReset_n; + wire wci_10_wReset_n$D_IN, wci_10_wReset_n$EN; + + // register wci_10_wStatus + reg [31 : 0] wci_10_wStatus; + wire [31 : 0] wci_10_wStatus$D_IN; + wire wci_10_wStatus$EN; + + // register wci_10_wTimeout + reg [4 : 0] wci_10_wTimeout; + wire [4 : 0] wci_10_wTimeout$D_IN; + wire wci_10_wTimeout$EN; + + // register wci_11_busy + reg wci_11_busy; + wire wci_11_busy$D_IN, wci_11_busy$EN; + + // register wci_11_lastConfigAddr + reg [32 : 0] wci_11_lastConfigAddr; + wire [32 : 0] wci_11_lastConfigAddr$D_IN; + wire wci_11_lastConfigAddr$EN; + + // register wci_11_lastConfigBE + reg [4 : 0] wci_11_lastConfigBE; + wire [4 : 0] wci_11_lastConfigBE$D_IN; + wire wci_11_lastConfigBE$EN; + + // register wci_11_lastControlOp + reg [3 : 0] wci_11_lastControlOp; + wire [3 : 0] wci_11_lastControlOp$D_IN; + wire wci_11_lastControlOp$EN; + + // register wci_11_lastOpWrite + reg [1 : 0] wci_11_lastOpWrite; + wire [1 : 0] wci_11_lastOpWrite$D_IN; + wire wci_11_lastOpWrite$EN; + + // register wci_11_mFlagReg + reg [1 : 0] wci_11_mFlagReg; + wire [1 : 0] wci_11_mFlagReg$D_IN; + wire wci_11_mFlagReg$EN; + + // register wci_11_pageWindow + reg [11 : 0] wci_11_pageWindow; + wire [11 : 0] wci_11_pageWindow$D_IN; + wire wci_11_pageWindow$EN; + + // register wci_11_reqERR + reg [2 : 0] wci_11_reqERR; + wire [2 : 0] wci_11_reqERR$D_IN; + wire wci_11_reqERR$EN; + + // register wci_11_reqFAIL + reg [2 : 0] wci_11_reqFAIL; + wire [2 : 0] wci_11_reqFAIL$D_IN; + wire wci_11_reqFAIL$EN; + + // register wci_11_reqF_cntr_r + reg wci_11_reqF_cntr_r; + wire wci_11_reqF_cntr_r$D_IN, wci_11_reqF_cntr_r$EN; + + // register wci_11_reqF_q_0 + reg [71 : 0] wci_11_reqF_q_0; + reg [71 : 0] wci_11_reqF_q_0$D_IN; + wire wci_11_reqF_q_0$EN; + + // register wci_11_reqPend + reg [1 : 0] wci_11_reqPend; + reg [1 : 0] wci_11_reqPend$D_IN; + wire wci_11_reqPend$EN; + + // register wci_11_reqTO + reg [2 : 0] wci_11_reqTO; + wire [2 : 0] wci_11_reqTO$D_IN; + wire wci_11_reqTO$EN; + + // register wci_11_respTimr + reg [31 : 0] wci_11_respTimr; + wire [31 : 0] wci_11_respTimr$D_IN; + wire wci_11_respTimr$EN; + + // register wci_11_respTimrAct + reg wci_11_respTimrAct; + wire wci_11_respTimrAct$D_IN, wci_11_respTimrAct$EN; + + // register wci_11_sThreadBusy_d + reg wci_11_sThreadBusy_d; + wire wci_11_sThreadBusy_d$D_IN, wci_11_sThreadBusy_d$EN; + + // register wci_11_sfCap + reg wci_11_sfCap; + wire wci_11_sfCap$D_IN, wci_11_sfCap$EN; + + // register wci_11_sfCapClear + reg wci_11_sfCapClear; + wire wci_11_sfCapClear$D_IN, wci_11_sfCapClear$EN; + + // register wci_11_sfCapSet + reg wci_11_sfCapSet; + wire wci_11_sfCapSet$D_IN, wci_11_sfCapSet$EN; + + // register wci_11_slvPresent + reg wci_11_slvPresent; + wire wci_11_slvPresent$D_IN, wci_11_slvPresent$EN; + + // register wci_11_wReset_n + reg wci_11_wReset_n; + wire wci_11_wReset_n$D_IN, wci_11_wReset_n$EN; + + // register wci_11_wStatus + reg [31 : 0] wci_11_wStatus; + wire [31 : 0] wci_11_wStatus$D_IN; + wire wci_11_wStatus$EN; + + // register wci_11_wTimeout + reg [4 : 0] wci_11_wTimeout; + wire [4 : 0] wci_11_wTimeout$D_IN; + wire wci_11_wTimeout$EN; + + // register wci_12_busy + reg wci_12_busy; + wire wci_12_busy$D_IN, wci_12_busy$EN; + + // register wci_12_lastConfigAddr + reg [32 : 0] wci_12_lastConfigAddr; + wire [32 : 0] wci_12_lastConfigAddr$D_IN; + wire wci_12_lastConfigAddr$EN; + + // register wci_12_lastConfigBE + reg [4 : 0] wci_12_lastConfigBE; + wire [4 : 0] wci_12_lastConfigBE$D_IN; + wire wci_12_lastConfigBE$EN; + + // register wci_12_lastControlOp + reg [3 : 0] wci_12_lastControlOp; + wire [3 : 0] wci_12_lastControlOp$D_IN; + wire wci_12_lastControlOp$EN; + + // register wci_12_lastOpWrite + reg [1 : 0] wci_12_lastOpWrite; + wire [1 : 0] wci_12_lastOpWrite$D_IN; + wire wci_12_lastOpWrite$EN; + + // register wci_12_mFlagReg + reg [1 : 0] wci_12_mFlagReg; + wire [1 : 0] wci_12_mFlagReg$D_IN; + wire wci_12_mFlagReg$EN; + + // register wci_12_pageWindow + reg [11 : 0] wci_12_pageWindow; + wire [11 : 0] wci_12_pageWindow$D_IN; + wire wci_12_pageWindow$EN; + + // register wci_12_reqERR + reg [2 : 0] wci_12_reqERR; + wire [2 : 0] wci_12_reqERR$D_IN; + wire wci_12_reqERR$EN; + + // register wci_12_reqFAIL + reg [2 : 0] wci_12_reqFAIL; + wire [2 : 0] wci_12_reqFAIL$D_IN; + wire wci_12_reqFAIL$EN; + + // register wci_12_reqF_cntr_r + reg wci_12_reqF_cntr_r; + wire wci_12_reqF_cntr_r$D_IN, wci_12_reqF_cntr_r$EN; + + // register wci_12_reqF_q_0 + reg [71 : 0] wci_12_reqF_q_0; + reg [71 : 0] wci_12_reqF_q_0$D_IN; + wire wci_12_reqF_q_0$EN; + + // register wci_12_reqPend + reg [1 : 0] wci_12_reqPend; + reg [1 : 0] wci_12_reqPend$D_IN; + wire wci_12_reqPend$EN; + + // register wci_12_reqTO + reg [2 : 0] wci_12_reqTO; + wire [2 : 0] wci_12_reqTO$D_IN; + wire wci_12_reqTO$EN; + + // register wci_12_respTimr + reg [31 : 0] wci_12_respTimr; + wire [31 : 0] wci_12_respTimr$D_IN; + wire wci_12_respTimr$EN; + + // register wci_12_respTimrAct + reg wci_12_respTimrAct; + wire wci_12_respTimrAct$D_IN, wci_12_respTimrAct$EN; + + // register wci_12_sThreadBusy_d + reg wci_12_sThreadBusy_d; + wire wci_12_sThreadBusy_d$D_IN, wci_12_sThreadBusy_d$EN; + + // register wci_12_sfCap + reg wci_12_sfCap; + wire wci_12_sfCap$D_IN, wci_12_sfCap$EN; + + // register wci_12_sfCapClear + reg wci_12_sfCapClear; + wire wci_12_sfCapClear$D_IN, wci_12_sfCapClear$EN; + + // register wci_12_sfCapSet + reg wci_12_sfCapSet; + wire wci_12_sfCapSet$D_IN, wci_12_sfCapSet$EN; + + // register wci_12_slvPresent + reg wci_12_slvPresent; + wire wci_12_slvPresent$D_IN, wci_12_slvPresent$EN; + + // register wci_12_wReset_n + reg wci_12_wReset_n; + wire wci_12_wReset_n$D_IN, wci_12_wReset_n$EN; + + // register wci_12_wStatus + reg [31 : 0] wci_12_wStatus; + wire [31 : 0] wci_12_wStatus$D_IN; + wire wci_12_wStatus$EN; + + // register wci_12_wTimeout + reg [4 : 0] wci_12_wTimeout; + wire [4 : 0] wci_12_wTimeout$D_IN; + wire wci_12_wTimeout$EN; + + // register wci_13_busy + reg wci_13_busy; + wire wci_13_busy$D_IN, wci_13_busy$EN; + + // register wci_13_lastConfigAddr + reg [32 : 0] wci_13_lastConfigAddr; + wire [32 : 0] wci_13_lastConfigAddr$D_IN; + wire wci_13_lastConfigAddr$EN; + + // register wci_13_lastConfigBE + reg [4 : 0] wci_13_lastConfigBE; + wire [4 : 0] wci_13_lastConfigBE$D_IN; + wire wci_13_lastConfigBE$EN; + + // register wci_13_lastControlOp + reg [3 : 0] wci_13_lastControlOp; + wire [3 : 0] wci_13_lastControlOp$D_IN; + wire wci_13_lastControlOp$EN; + + // register wci_13_lastOpWrite + reg [1 : 0] wci_13_lastOpWrite; + wire [1 : 0] wci_13_lastOpWrite$D_IN; + wire wci_13_lastOpWrite$EN; + + // register wci_13_mFlagReg + reg [1 : 0] wci_13_mFlagReg; + wire [1 : 0] wci_13_mFlagReg$D_IN; + wire wci_13_mFlagReg$EN; + + // register wci_13_pageWindow + reg [11 : 0] wci_13_pageWindow; + wire [11 : 0] wci_13_pageWindow$D_IN; + wire wci_13_pageWindow$EN; + + // register wci_13_reqERR + reg [2 : 0] wci_13_reqERR; + wire [2 : 0] wci_13_reqERR$D_IN; + wire wci_13_reqERR$EN; + + // register wci_13_reqFAIL + reg [2 : 0] wci_13_reqFAIL; + wire [2 : 0] wci_13_reqFAIL$D_IN; + wire wci_13_reqFAIL$EN; + + // register wci_13_reqF_cntr_r + reg wci_13_reqF_cntr_r; + wire wci_13_reqF_cntr_r$D_IN, wci_13_reqF_cntr_r$EN; + + // register wci_13_reqF_q_0 + reg [71 : 0] wci_13_reqF_q_0; + reg [71 : 0] wci_13_reqF_q_0$D_IN; + wire wci_13_reqF_q_0$EN; + + // register wci_13_reqPend + reg [1 : 0] wci_13_reqPend; + reg [1 : 0] wci_13_reqPend$D_IN; + wire wci_13_reqPend$EN; + + // register wci_13_reqTO + reg [2 : 0] wci_13_reqTO; + wire [2 : 0] wci_13_reqTO$D_IN; + wire wci_13_reqTO$EN; + + // register wci_13_respTimr + reg [31 : 0] wci_13_respTimr; + wire [31 : 0] wci_13_respTimr$D_IN; + wire wci_13_respTimr$EN; + + // register wci_13_respTimrAct + reg wci_13_respTimrAct; + wire wci_13_respTimrAct$D_IN, wci_13_respTimrAct$EN; + + // register wci_13_sThreadBusy_d + reg wci_13_sThreadBusy_d; + wire wci_13_sThreadBusy_d$D_IN, wci_13_sThreadBusy_d$EN; + + // register wci_13_sfCap + reg wci_13_sfCap; + wire wci_13_sfCap$D_IN, wci_13_sfCap$EN; + + // register wci_13_sfCapClear + reg wci_13_sfCapClear; + wire wci_13_sfCapClear$D_IN, wci_13_sfCapClear$EN; + + // register wci_13_sfCapSet + reg wci_13_sfCapSet; + wire wci_13_sfCapSet$D_IN, wci_13_sfCapSet$EN; + + // register wci_13_slvPresent + reg wci_13_slvPresent; + wire wci_13_slvPresent$D_IN, wci_13_slvPresent$EN; + + // register wci_13_wReset_n + reg wci_13_wReset_n; + wire wci_13_wReset_n$D_IN, wci_13_wReset_n$EN; + + // register wci_13_wStatus + reg [31 : 0] wci_13_wStatus; + wire [31 : 0] wci_13_wStatus$D_IN; + wire wci_13_wStatus$EN; + + // register wci_13_wTimeout + reg [4 : 0] wci_13_wTimeout; + wire [4 : 0] wci_13_wTimeout$D_IN; + wire wci_13_wTimeout$EN; + + // register wci_14_busy + reg wci_14_busy; + wire wci_14_busy$D_IN, wci_14_busy$EN; + + // register wci_14_lastConfigAddr + reg [32 : 0] wci_14_lastConfigAddr; + wire [32 : 0] wci_14_lastConfigAddr$D_IN; + wire wci_14_lastConfigAddr$EN; + + // register wci_14_lastConfigBE + reg [4 : 0] wci_14_lastConfigBE; + wire [4 : 0] wci_14_lastConfigBE$D_IN; + wire wci_14_lastConfigBE$EN; + + // register wci_14_lastControlOp + reg [3 : 0] wci_14_lastControlOp; + wire [3 : 0] wci_14_lastControlOp$D_IN; + wire wci_14_lastControlOp$EN; + + // register wci_14_lastOpWrite + reg [1 : 0] wci_14_lastOpWrite; + wire [1 : 0] wci_14_lastOpWrite$D_IN; + wire wci_14_lastOpWrite$EN; + + // register wci_14_mFlagReg + reg [1 : 0] wci_14_mFlagReg; + wire [1 : 0] wci_14_mFlagReg$D_IN; + wire wci_14_mFlagReg$EN; + + // register wci_14_pageWindow + reg [11 : 0] wci_14_pageWindow; + wire [11 : 0] wci_14_pageWindow$D_IN; + wire wci_14_pageWindow$EN; + + // register wci_14_reqERR + reg [2 : 0] wci_14_reqERR; + wire [2 : 0] wci_14_reqERR$D_IN; + wire wci_14_reqERR$EN; + + // register wci_14_reqFAIL + reg [2 : 0] wci_14_reqFAIL; + wire [2 : 0] wci_14_reqFAIL$D_IN; + wire wci_14_reqFAIL$EN; + + // register wci_14_reqF_cntr_r + reg wci_14_reqF_cntr_r; + wire wci_14_reqF_cntr_r$D_IN, wci_14_reqF_cntr_r$EN; + + // register wci_14_reqF_q_0 + reg [71 : 0] wci_14_reqF_q_0; + reg [71 : 0] wci_14_reqF_q_0$D_IN; + wire wci_14_reqF_q_0$EN; + + // register wci_14_reqPend + reg [1 : 0] wci_14_reqPend; + reg [1 : 0] wci_14_reqPend$D_IN; + wire wci_14_reqPend$EN; + + // register wci_14_reqTO + reg [2 : 0] wci_14_reqTO; + wire [2 : 0] wci_14_reqTO$D_IN; + wire wci_14_reqTO$EN; + + // register wci_14_respTimr + reg [31 : 0] wci_14_respTimr; + wire [31 : 0] wci_14_respTimr$D_IN; + wire wci_14_respTimr$EN; + + // register wci_14_respTimrAct + reg wci_14_respTimrAct; + wire wci_14_respTimrAct$D_IN, wci_14_respTimrAct$EN; + + // register wci_14_sThreadBusy_d + reg wci_14_sThreadBusy_d; + wire wci_14_sThreadBusy_d$D_IN, wci_14_sThreadBusy_d$EN; + + // register wci_14_sfCap + reg wci_14_sfCap; + wire wci_14_sfCap$D_IN, wci_14_sfCap$EN; + + // register wci_14_sfCapClear + reg wci_14_sfCapClear; + wire wci_14_sfCapClear$D_IN, wci_14_sfCapClear$EN; + + // register wci_14_sfCapSet + reg wci_14_sfCapSet; + wire wci_14_sfCapSet$D_IN, wci_14_sfCapSet$EN; + + // register wci_14_slvPresent + reg wci_14_slvPresent; + wire wci_14_slvPresent$D_IN, wci_14_slvPresent$EN; + + // register wci_14_wReset_n + reg wci_14_wReset_n; + wire wci_14_wReset_n$D_IN, wci_14_wReset_n$EN; + + // register wci_14_wStatus + reg [31 : 0] wci_14_wStatus; + wire [31 : 0] wci_14_wStatus$D_IN; + wire wci_14_wStatus$EN; + + // register wci_14_wTimeout + reg [4 : 0] wci_14_wTimeout; + wire [4 : 0] wci_14_wTimeout$D_IN; + wire wci_14_wTimeout$EN; + + // register wci_1_busy + reg wci_1_busy; + wire wci_1_busy$D_IN, wci_1_busy$EN; + + // register wci_1_lastConfigAddr + reg [32 : 0] wci_1_lastConfigAddr; + wire [32 : 0] wci_1_lastConfigAddr$D_IN; + wire wci_1_lastConfigAddr$EN; + + // register wci_1_lastConfigBE + reg [4 : 0] wci_1_lastConfigBE; + wire [4 : 0] wci_1_lastConfigBE$D_IN; + wire wci_1_lastConfigBE$EN; + + // register wci_1_lastControlOp + reg [3 : 0] wci_1_lastControlOp; + wire [3 : 0] wci_1_lastControlOp$D_IN; + wire wci_1_lastControlOp$EN; + + // register wci_1_lastOpWrite + reg [1 : 0] wci_1_lastOpWrite; + wire [1 : 0] wci_1_lastOpWrite$D_IN; + wire wci_1_lastOpWrite$EN; + + // register wci_1_mFlagReg + reg [1 : 0] wci_1_mFlagReg; + wire [1 : 0] wci_1_mFlagReg$D_IN; + wire wci_1_mFlagReg$EN; + + // register wci_1_pageWindow + reg [11 : 0] wci_1_pageWindow; + wire [11 : 0] wci_1_pageWindow$D_IN; + wire wci_1_pageWindow$EN; + + // register wci_1_reqERR + reg [2 : 0] wci_1_reqERR; + wire [2 : 0] wci_1_reqERR$D_IN; + wire wci_1_reqERR$EN; + + // register wci_1_reqFAIL + reg [2 : 0] wci_1_reqFAIL; + wire [2 : 0] wci_1_reqFAIL$D_IN; + wire wci_1_reqFAIL$EN; + + // register wci_1_reqF_cntr_r + reg wci_1_reqF_cntr_r; + wire wci_1_reqF_cntr_r$D_IN, wci_1_reqF_cntr_r$EN; + + // register wci_1_reqF_q_0 + reg [71 : 0] wci_1_reqF_q_0; + reg [71 : 0] wci_1_reqF_q_0$D_IN; + wire wci_1_reqF_q_0$EN; + + // register wci_1_reqPend + reg [1 : 0] wci_1_reqPend; + reg [1 : 0] wci_1_reqPend$D_IN; + wire wci_1_reqPend$EN; + + // register wci_1_reqTO + reg [2 : 0] wci_1_reqTO; + wire [2 : 0] wci_1_reqTO$D_IN; + wire wci_1_reqTO$EN; + + // register wci_1_respTimr + reg [31 : 0] wci_1_respTimr; + wire [31 : 0] wci_1_respTimr$D_IN; + wire wci_1_respTimr$EN; + + // register wci_1_respTimrAct + reg wci_1_respTimrAct; + wire wci_1_respTimrAct$D_IN, wci_1_respTimrAct$EN; + + // register wci_1_sThreadBusy_d + reg wci_1_sThreadBusy_d; + wire wci_1_sThreadBusy_d$D_IN, wci_1_sThreadBusy_d$EN; + + // register wci_1_sfCap + reg wci_1_sfCap; + wire wci_1_sfCap$D_IN, wci_1_sfCap$EN; + + // register wci_1_sfCapClear + reg wci_1_sfCapClear; + wire wci_1_sfCapClear$D_IN, wci_1_sfCapClear$EN; + + // register wci_1_sfCapSet + reg wci_1_sfCapSet; + wire wci_1_sfCapSet$D_IN, wci_1_sfCapSet$EN; + + // register wci_1_slvPresent + reg wci_1_slvPresent; + wire wci_1_slvPresent$D_IN, wci_1_slvPresent$EN; + + // register wci_1_wReset_n + reg wci_1_wReset_n; + wire wci_1_wReset_n$D_IN, wci_1_wReset_n$EN; + + // register wci_1_wStatus + reg [31 : 0] wci_1_wStatus; + wire [31 : 0] wci_1_wStatus$D_IN; + wire wci_1_wStatus$EN; + + // register wci_1_wTimeout + reg [4 : 0] wci_1_wTimeout; + wire [4 : 0] wci_1_wTimeout$D_IN; + wire wci_1_wTimeout$EN; + + // register wci_2_busy + reg wci_2_busy; + wire wci_2_busy$D_IN, wci_2_busy$EN; + + // register wci_2_lastConfigAddr + reg [32 : 0] wci_2_lastConfigAddr; + wire [32 : 0] wci_2_lastConfigAddr$D_IN; + wire wci_2_lastConfigAddr$EN; + + // register wci_2_lastConfigBE + reg [4 : 0] wci_2_lastConfigBE; + wire [4 : 0] wci_2_lastConfigBE$D_IN; + wire wci_2_lastConfigBE$EN; + + // register wci_2_lastControlOp + reg [3 : 0] wci_2_lastControlOp; + wire [3 : 0] wci_2_lastControlOp$D_IN; + wire wci_2_lastControlOp$EN; + + // register wci_2_lastOpWrite + reg [1 : 0] wci_2_lastOpWrite; + wire [1 : 0] wci_2_lastOpWrite$D_IN; + wire wci_2_lastOpWrite$EN; + + // register wci_2_mFlagReg + reg [1 : 0] wci_2_mFlagReg; + wire [1 : 0] wci_2_mFlagReg$D_IN; + wire wci_2_mFlagReg$EN; + + // register wci_2_pageWindow + reg [11 : 0] wci_2_pageWindow; + wire [11 : 0] wci_2_pageWindow$D_IN; + wire wci_2_pageWindow$EN; + + // register wci_2_reqERR + reg [2 : 0] wci_2_reqERR; + wire [2 : 0] wci_2_reqERR$D_IN; + wire wci_2_reqERR$EN; + + // register wci_2_reqFAIL + reg [2 : 0] wci_2_reqFAIL; + wire [2 : 0] wci_2_reqFAIL$D_IN; + wire wci_2_reqFAIL$EN; + + // register wci_2_reqF_cntr_r + reg wci_2_reqF_cntr_r; + wire wci_2_reqF_cntr_r$D_IN, wci_2_reqF_cntr_r$EN; + + // register wci_2_reqF_q_0 + reg [71 : 0] wci_2_reqF_q_0; + reg [71 : 0] wci_2_reqF_q_0$D_IN; + wire wci_2_reqF_q_0$EN; + + // register wci_2_reqPend + reg [1 : 0] wci_2_reqPend; + reg [1 : 0] wci_2_reqPend$D_IN; + wire wci_2_reqPend$EN; + + // register wci_2_reqTO + reg [2 : 0] wci_2_reqTO; + wire [2 : 0] wci_2_reqTO$D_IN; + wire wci_2_reqTO$EN; + + // register wci_2_respTimr + reg [31 : 0] wci_2_respTimr; + wire [31 : 0] wci_2_respTimr$D_IN; + wire wci_2_respTimr$EN; + + // register wci_2_respTimrAct + reg wci_2_respTimrAct; + wire wci_2_respTimrAct$D_IN, wci_2_respTimrAct$EN; + + // register wci_2_sThreadBusy_d + reg wci_2_sThreadBusy_d; + wire wci_2_sThreadBusy_d$D_IN, wci_2_sThreadBusy_d$EN; + + // register wci_2_sfCap + reg wci_2_sfCap; + wire wci_2_sfCap$D_IN, wci_2_sfCap$EN; + + // register wci_2_sfCapClear + reg wci_2_sfCapClear; + wire wci_2_sfCapClear$D_IN, wci_2_sfCapClear$EN; + + // register wci_2_sfCapSet + reg wci_2_sfCapSet; + wire wci_2_sfCapSet$D_IN, wci_2_sfCapSet$EN; + + // register wci_2_slvPresent + reg wci_2_slvPresent; + wire wci_2_slvPresent$D_IN, wci_2_slvPresent$EN; + + // register wci_2_wReset_n + reg wci_2_wReset_n; + wire wci_2_wReset_n$D_IN, wci_2_wReset_n$EN; + + // register wci_2_wStatus + reg [31 : 0] wci_2_wStatus; + wire [31 : 0] wci_2_wStatus$D_IN; + wire wci_2_wStatus$EN; + + // register wci_2_wTimeout + reg [4 : 0] wci_2_wTimeout; + wire [4 : 0] wci_2_wTimeout$D_IN; + wire wci_2_wTimeout$EN; + + // register wci_3_busy + reg wci_3_busy; + wire wci_3_busy$D_IN, wci_3_busy$EN; + + // register wci_3_lastConfigAddr + reg [32 : 0] wci_3_lastConfigAddr; + wire [32 : 0] wci_3_lastConfigAddr$D_IN; + wire wci_3_lastConfigAddr$EN; + + // register wci_3_lastConfigBE + reg [4 : 0] wci_3_lastConfigBE; + wire [4 : 0] wci_3_lastConfigBE$D_IN; + wire wci_3_lastConfigBE$EN; + + // register wci_3_lastControlOp + reg [3 : 0] wci_3_lastControlOp; + wire [3 : 0] wci_3_lastControlOp$D_IN; + wire wci_3_lastControlOp$EN; + + // register wci_3_lastOpWrite + reg [1 : 0] wci_3_lastOpWrite; + wire [1 : 0] wci_3_lastOpWrite$D_IN; + wire wci_3_lastOpWrite$EN; + + // register wci_3_mFlagReg + reg [1 : 0] wci_3_mFlagReg; + wire [1 : 0] wci_3_mFlagReg$D_IN; + wire wci_3_mFlagReg$EN; + + // register wci_3_pageWindow + reg [11 : 0] wci_3_pageWindow; + wire [11 : 0] wci_3_pageWindow$D_IN; + wire wci_3_pageWindow$EN; + + // register wci_3_reqERR + reg [2 : 0] wci_3_reqERR; + wire [2 : 0] wci_3_reqERR$D_IN; + wire wci_3_reqERR$EN; + + // register wci_3_reqFAIL + reg [2 : 0] wci_3_reqFAIL; + wire [2 : 0] wci_3_reqFAIL$D_IN; + wire wci_3_reqFAIL$EN; + + // register wci_3_reqF_cntr_r + reg wci_3_reqF_cntr_r; + wire wci_3_reqF_cntr_r$D_IN, wci_3_reqF_cntr_r$EN; + + // register wci_3_reqF_q_0 + reg [71 : 0] wci_3_reqF_q_0; + reg [71 : 0] wci_3_reqF_q_0$D_IN; + wire wci_3_reqF_q_0$EN; + + // register wci_3_reqPend + reg [1 : 0] wci_3_reqPend; + reg [1 : 0] wci_3_reqPend$D_IN; + wire wci_3_reqPend$EN; + + // register wci_3_reqTO + reg [2 : 0] wci_3_reqTO; + wire [2 : 0] wci_3_reqTO$D_IN; + wire wci_3_reqTO$EN; + + // register wci_3_respTimr + reg [31 : 0] wci_3_respTimr; + wire [31 : 0] wci_3_respTimr$D_IN; + wire wci_3_respTimr$EN; + + // register wci_3_respTimrAct + reg wci_3_respTimrAct; + wire wci_3_respTimrAct$D_IN, wci_3_respTimrAct$EN; + + // register wci_3_sThreadBusy_d + reg wci_3_sThreadBusy_d; + wire wci_3_sThreadBusy_d$D_IN, wci_3_sThreadBusy_d$EN; + + // register wci_3_sfCap + reg wci_3_sfCap; + wire wci_3_sfCap$D_IN, wci_3_sfCap$EN; + + // register wci_3_sfCapClear + reg wci_3_sfCapClear; + wire wci_3_sfCapClear$D_IN, wci_3_sfCapClear$EN; + + // register wci_3_sfCapSet + reg wci_3_sfCapSet; + wire wci_3_sfCapSet$D_IN, wci_3_sfCapSet$EN; + + // register wci_3_slvPresent + reg wci_3_slvPresent; + wire wci_3_slvPresent$D_IN, wci_3_slvPresent$EN; + + // register wci_3_wReset_n + reg wci_3_wReset_n; + wire wci_3_wReset_n$D_IN, wci_3_wReset_n$EN; + + // register wci_3_wStatus + reg [31 : 0] wci_3_wStatus; + wire [31 : 0] wci_3_wStatus$D_IN; + wire wci_3_wStatus$EN; + + // register wci_3_wTimeout + reg [4 : 0] wci_3_wTimeout; + wire [4 : 0] wci_3_wTimeout$D_IN; + wire wci_3_wTimeout$EN; + + // register wci_4_busy + reg wci_4_busy; + wire wci_4_busy$D_IN, wci_4_busy$EN; + + // register wci_4_lastConfigAddr + reg [32 : 0] wci_4_lastConfigAddr; + wire [32 : 0] wci_4_lastConfigAddr$D_IN; + wire wci_4_lastConfigAddr$EN; + + // register wci_4_lastConfigBE + reg [4 : 0] wci_4_lastConfigBE; + wire [4 : 0] wci_4_lastConfigBE$D_IN; + wire wci_4_lastConfigBE$EN; + + // register wci_4_lastControlOp + reg [3 : 0] wci_4_lastControlOp; + wire [3 : 0] wci_4_lastControlOp$D_IN; + wire wci_4_lastControlOp$EN; + + // register wci_4_lastOpWrite + reg [1 : 0] wci_4_lastOpWrite; + wire [1 : 0] wci_4_lastOpWrite$D_IN; + wire wci_4_lastOpWrite$EN; + + // register wci_4_mFlagReg + reg [1 : 0] wci_4_mFlagReg; + wire [1 : 0] wci_4_mFlagReg$D_IN; + wire wci_4_mFlagReg$EN; + + // register wci_4_pageWindow + reg [11 : 0] wci_4_pageWindow; + wire [11 : 0] wci_4_pageWindow$D_IN; + wire wci_4_pageWindow$EN; + + // register wci_4_reqERR + reg [2 : 0] wci_4_reqERR; + wire [2 : 0] wci_4_reqERR$D_IN; + wire wci_4_reqERR$EN; + + // register wci_4_reqFAIL + reg [2 : 0] wci_4_reqFAIL; + wire [2 : 0] wci_4_reqFAIL$D_IN; + wire wci_4_reqFAIL$EN; + + // register wci_4_reqF_cntr_r + reg wci_4_reqF_cntr_r; + wire wci_4_reqF_cntr_r$D_IN, wci_4_reqF_cntr_r$EN; + + // register wci_4_reqF_q_0 + reg [71 : 0] wci_4_reqF_q_0; + reg [71 : 0] wci_4_reqF_q_0$D_IN; + wire wci_4_reqF_q_0$EN; + + // register wci_4_reqPend + reg [1 : 0] wci_4_reqPend; + reg [1 : 0] wci_4_reqPend$D_IN; + wire wci_4_reqPend$EN; + + // register wci_4_reqTO + reg [2 : 0] wci_4_reqTO; + wire [2 : 0] wci_4_reqTO$D_IN; + wire wci_4_reqTO$EN; + + // register wci_4_respTimr + reg [31 : 0] wci_4_respTimr; + wire [31 : 0] wci_4_respTimr$D_IN; + wire wci_4_respTimr$EN; + + // register wci_4_respTimrAct + reg wci_4_respTimrAct; + wire wci_4_respTimrAct$D_IN, wci_4_respTimrAct$EN; + + // register wci_4_sThreadBusy_d + reg wci_4_sThreadBusy_d; + wire wci_4_sThreadBusy_d$D_IN, wci_4_sThreadBusy_d$EN; + + // register wci_4_sfCap + reg wci_4_sfCap; + wire wci_4_sfCap$D_IN, wci_4_sfCap$EN; + + // register wci_4_sfCapClear + reg wci_4_sfCapClear; + wire wci_4_sfCapClear$D_IN, wci_4_sfCapClear$EN; + + // register wci_4_sfCapSet + reg wci_4_sfCapSet; + wire wci_4_sfCapSet$D_IN, wci_4_sfCapSet$EN; + + // register wci_4_slvPresent + reg wci_4_slvPresent; + wire wci_4_slvPresent$D_IN, wci_4_slvPresent$EN; + + // register wci_4_wReset_n + reg wci_4_wReset_n; + wire wci_4_wReset_n$D_IN, wci_4_wReset_n$EN; + + // register wci_4_wStatus + reg [31 : 0] wci_4_wStatus; + wire [31 : 0] wci_4_wStatus$D_IN; + wire wci_4_wStatus$EN; + + // register wci_4_wTimeout + reg [4 : 0] wci_4_wTimeout; + wire [4 : 0] wci_4_wTimeout$D_IN; + wire wci_4_wTimeout$EN; + + // register wci_5_busy + reg wci_5_busy; + wire wci_5_busy$D_IN, wci_5_busy$EN; + + // register wci_5_lastConfigAddr + reg [32 : 0] wci_5_lastConfigAddr; + wire [32 : 0] wci_5_lastConfigAddr$D_IN; + wire wci_5_lastConfigAddr$EN; + + // register wci_5_lastConfigBE + reg [4 : 0] wci_5_lastConfigBE; + wire [4 : 0] wci_5_lastConfigBE$D_IN; + wire wci_5_lastConfigBE$EN; + + // register wci_5_lastControlOp + reg [3 : 0] wci_5_lastControlOp; + wire [3 : 0] wci_5_lastControlOp$D_IN; + wire wci_5_lastControlOp$EN; + + // register wci_5_lastOpWrite + reg [1 : 0] wci_5_lastOpWrite; + wire [1 : 0] wci_5_lastOpWrite$D_IN; + wire wci_5_lastOpWrite$EN; + + // register wci_5_mFlagReg + reg [1 : 0] wci_5_mFlagReg; + wire [1 : 0] wci_5_mFlagReg$D_IN; + wire wci_5_mFlagReg$EN; + + // register wci_5_pageWindow + reg [11 : 0] wci_5_pageWindow; + wire [11 : 0] wci_5_pageWindow$D_IN; + wire wci_5_pageWindow$EN; + + // register wci_5_reqERR + reg [2 : 0] wci_5_reqERR; + wire [2 : 0] wci_5_reqERR$D_IN; + wire wci_5_reqERR$EN; + + // register wci_5_reqFAIL + reg [2 : 0] wci_5_reqFAIL; + wire [2 : 0] wci_5_reqFAIL$D_IN; + wire wci_5_reqFAIL$EN; + + // register wci_5_reqF_cntr_r + reg wci_5_reqF_cntr_r; + wire wci_5_reqF_cntr_r$D_IN, wci_5_reqF_cntr_r$EN; + + // register wci_5_reqF_q_0 + reg [71 : 0] wci_5_reqF_q_0; + reg [71 : 0] wci_5_reqF_q_0$D_IN; + wire wci_5_reqF_q_0$EN; + + // register wci_5_reqPend + reg [1 : 0] wci_5_reqPend; + reg [1 : 0] wci_5_reqPend$D_IN; + wire wci_5_reqPend$EN; + + // register wci_5_reqTO + reg [2 : 0] wci_5_reqTO; + wire [2 : 0] wci_5_reqTO$D_IN; + wire wci_5_reqTO$EN; + + // register wci_5_respTimr + reg [31 : 0] wci_5_respTimr; + wire [31 : 0] wci_5_respTimr$D_IN; + wire wci_5_respTimr$EN; + + // register wci_5_respTimrAct + reg wci_5_respTimrAct; + wire wci_5_respTimrAct$D_IN, wci_5_respTimrAct$EN; + + // register wci_5_sThreadBusy_d + reg wci_5_sThreadBusy_d; + wire wci_5_sThreadBusy_d$D_IN, wci_5_sThreadBusy_d$EN; + + // register wci_5_sfCap + reg wci_5_sfCap; + wire wci_5_sfCap$D_IN, wci_5_sfCap$EN; + + // register wci_5_sfCapClear + reg wci_5_sfCapClear; + wire wci_5_sfCapClear$D_IN, wci_5_sfCapClear$EN; + + // register wci_5_sfCapSet + reg wci_5_sfCapSet; + wire wci_5_sfCapSet$D_IN, wci_5_sfCapSet$EN; + + // register wci_5_slvPresent + reg wci_5_slvPresent; + wire wci_5_slvPresent$D_IN, wci_5_slvPresent$EN; + + // register wci_5_wReset_n + reg wci_5_wReset_n; + wire wci_5_wReset_n$D_IN, wci_5_wReset_n$EN; + + // register wci_5_wStatus + reg [31 : 0] wci_5_wStatus; + wire [31 : 0] wci_5_wStatus$D_IN; + wire wci_5_wStatus$EN; + + // register wci_5_wTimeout + reg [4 : 0] wci_5_wTimeout; + wire [4 : 0] wci_5_wTimeout$D_IN; + wire wci_5_wTimeout$EN; + + // register wci_6_busy + reg wci_6_busy; + wire wci_6_busy$D_IN, wci_6_busy$EN; + + // register wci_6_lastConfigAddr + reg [32 : 0] wci_6_lastConfigAddr; + wire [32 : 0] wci_6_lastConfigAddr$D_IN; + wire wci_6_lastConfigAddr$EN; + + // register wci_6_lastConfigBE + reg [4 : 0] wci_6_lastConfigBE; + wire [4 : 0] wci_6_lastConfigBE$D_IN; + wire wci_6_lastConfigBE$EN; + + // register wci_6_lastControlOp + reg [3 : 0] wci_6_lastControlOp; + wire [3 : 0] wci_6_lastControlOp$D_IN; + wire wci_6_lastControlOp$EN; + + // register wci_6_lastOpWrite + reg [1 : 0] wci_6_lastOpWrite; + wire [1 : 0] wci_6_lastOpWrite$D_IN; + wire wci_6_lastOpWrite$EN; + + // register wci_6_mFlagReg + reg [1 : 0] wci_6_mFlagReg; + wire [1 : 0] wci_6_mFlagReg$D_IN; + wire wci_6_mFlagReg$EN; + + // register wci_6_pageWindow + reg [11 : 0] wci_6_pageWindow; + wire [11 : 0] wci_6_pageWindow$D_IN; + wire wci_6_pageWindow$EN; + + // register wci_6_reqERR + reg [2 : 0] wci_6_reqERR; + wire [2 : 0] wci_6_reqERR$D_IN; + wire wci_6_reqERR$EN; + + // register wci_6_reqFAIL + reg [2 : 0] wci_6_reqFAIL; + wire [2 : 0] wci_6_reqFAIL$D_IN; + wire wci_6_reqFAIL$EN; + + // register wci_6_reqF_cntr_r + reg wci_6_reqF_cntr_r; + wire wci_6_reqF_cntr_r$D_IN, wci_6_reqF_cntr_r$EN; + + // register wci_6_reqF_q_0 + reg [71 : 0] wci_6_reqF_q_0; + reg [71 : 0] wci_6_reqF_q_0$D_IN; + wire wci_6_reqF_q_0$EN; + + // register wci_6_reqPend + reg [1 : 0] wci_6_reqPend; + reg [1 : 0] wci_6_reqPend$D_IN; + wire wci_6_reqPend$EN; + + // register wci_6_reqTO + reg [2 : 0] wci_6_reqTO; + wire [2 : 0] wci_6_reqTO$D_IN; + wire wci_6_reqTO$EN; + + // register wci_6_respTimr + reg [31 : 0] wci_6_respTimr; + wire [31 : 0] wci_6_respTimr$D_IN; + wire wci_6_respTimr$EN; + + // register wci_6_respTimrAct + reg wci_6_respTimrAct; + wire wci_6_respTimrAct$D_IN, wci_6_respTimrAct$EN; + + // register wci_6_sThreadBusy_d + reg wci_6_sThreadBusy_d; + wire wci_6_sThreadBusy_d$D_IN, wci_6_sThreadBusy_d$EN; + + // register wci_6_sfCap + reg wci_6_sfCap; + wire wci_6_sfCap$D_IN, wci_6_sfCap$EN; + + // register wci_6_sfCapClear + reg wci_6_sfCapClear; + wire wci_6_sfCapClear$D_IN, wci_6_sfCapClear$EN; + + // register wci_6_sfCapSet + reg wci_6_sfCapSet; + wire wci_6_sfCapSet$D_IN, wci_6_sfCapSet$EN; + + // register wci_6_slvPresent + reg wci_6_slvPresent; + wire wci_6_slvPresent$D_IN, wci_6_slvPresent$EN; + + // register wci_6_wReset_n + reg wci_6_wReset_n; + wire wci_6_wReset_n$D_IN, wci_6_wReset_n$EN; + + // register wci_6_wStatus + reg [31 : 0] wci_6_wStatus; + wire [31 : 0] wci_6_wStatus$D_IN; + wire wci_6_wStatus$EN; + + // register wci_6_wTimeout + reg [4 : 0] wci_6_wTimeout; + wire [4 : 0] wci_6_wTimeout$D_IN; + wire wci_6_wTimeout$EN; + + // register wci_7_busy + reg wci_7_busy; + wire wci_7_busy$D_IN, wci_7_busy$EN; + + // register wci_7_lastConfigAddr + reg [32 : 0] wci_7_lastConfigAddr; + wire [32 : 0] wci_7_lastConfigAddr$D_IN; + wire wci_7_lastConfigAddr$EN; + + // register wci_7_lastConfigBE + reg [4 : 0] wci_7_lastConfigBE; + wire [4 : 0] wci_7_lastConfigBE$D_IN; + wire wci_7_lastConfigBE$EN; + + // register wci_7_lastControlOp + reg [3 : 0] wci_7_lastControlOp; + wire [3 : 0] wci_7_lastControlOp$D_IN; + wire wci_7_lastControlOp$EN; + + // register wci_7_lastOpWrite + reg [1 : 0] wci_7_lastOpWrite; + wire [1 : 0] wci_7_lastOpWrite$D_IN; + wire wci_7_lastOpWrite$EN; + + // register wci_7_mFlagReg + reg [1 : 0] wci_7_mFlagReg; + wire [1 : 0] wci_7_mFlagReg$D_IN; + wire wci_7_mFlagReg$EN; + + // register wci_7_pageWindow + reg [11 : 0] wci_7_pageWindow; + wire [11 : 0] wci_7_pageWindow$D_IN; + wire wci_7_pageWindow$EN; + + // register wci_7_reqERR + reg [2 : 0] wci_7_reqERR; + wire [2 : 0] wci_7_reqERR$D_IN; + wire wci_7_reqERR$EN; + + // register wci_7_reqFAIL + reg [2 : 0] wci_7_reqFAIL; + wire [2 : 0] wci_7_reqFAIL$D_IN; + wire wci_7_reqFAIL$EN; + + // register wci_7_reqF_cntr_r + reg wci_7_reqF_cntr_r; + wire wci_7_reqF_cntr_r$D_IN, wci_7_reqF_cntr_r$EN; + + // register wci_7_reqF_q_0 + reg [71 : 0] wci_7_reqF_q_0; + reg [71 : 0] wci_7_reqF_q_0$D_IN; + wire wci_7_reqF_q_0$EN; + + // register wci_7_reqPend + reg [1 : 0] wci_7_reqPend; + reg [1 : 0] wci_7_reqPend$D_IN; + wire wci_7_reqPend$EN; + + // register wci_7_reqTO + reg [2 : 0] wci_7_reqTO; + wire [2 : 0] wci_7_reqTO$D_IN; + wire wci_7_reqTO$EN; + + // register wci_7_respTimr + reg [31 : 0] wci_7_respTimr; + wire [31 : 0] wci_7_respTimr$D_IN; + wire wci_7_respTimr$EN; + + // register wci_7_respTimrAct + reg wci_7_respTimrAct; + wire wci_7_respTimrAct$D_IN, wci_7_respTimrAct$EN; + + // register wci_7_sThreadBusy_d + reg wci_7_sThreadBusy_d; + wire wci_7_sThreadBusy_d$D_IN, wci_7_sThreadBusy_d$EN; + + // register wci_7_sfCap + reg wci_7_sfCap; + wire wci_7_sfCap$D_IN, wci_7_sfCap$EN; + + // register wci_7_sfCapClear + reg wci_7_sfCapClear; + wire wci_7_sfCapClear$D_IN, wci_7_sfCapClear$EN; + + // register wci_7_sfCapSet + reg wci_7_sfCapSet; + wire wci_7_sfCapSet$D_IN, wci_7_sfCapSet$EN; + + // register wci_7_slvPresent + reg wci_7_slvPresent; + wire wci_7_slvPresent$D_IN, wci_7_slvPresent$EN; + + // register wci_7_wReset_n + reg wci_7_wReset_n; + wire wci_7_wReset_n$D_IN, wci_7_wReset_n$EN; + + // register wci_7_wStatus + reg [31 : 0] wci_7_wStatus; + wire [31 : 0] wci_7_wStatus$D_IN; + wire wci_7_wStatus$EN; + + // register wci_7_wTimeout + reg [4 : 0] wci_7_wTimeout; + wire [4 : 0] wci_7_wTimeout$D_IN; + wire wci_7_wTimeout$EN; + + // register wci_8_busy + reg wci_8_busy; + wire wci_8_busy$D_IN, wci_8_busy$EN; + + // register wci_8_lastConfigAddr + reg [32 : 0] wci_8_lastConfigAddr; + wire [32 : 0] wci_8_lastConfigAddr$D_IN; + wire wci_8_lastConfigAddr$EN; + + // register wci_8_lastConfigBE + reg [4 : 0] wci_8_lastConfigBE; + wire [4 : 0] wci_8_lastConfigBE$D_IN; + wire wci_8_lastConfigBE$EN; + + // register wci_8_lastControlOp + reg [3 : 0] wci_8_lastControlOp; + wire [3 : 0] wci_8_lastControlOp$D_IN; + wire wci_8_lastControlOp$EN; + + // register wci_8_lastOpWrite + reg [1 : 0] wci_8_lastOpWrite; + wire [1 : 0] wci_8_lastOpWrite$D_IN; + wire wci_8_lastOpWrite$EN; + + // register wci_8_mFlagReg + reg [1 : 0] wci_8_mFlagReg; + wire [1 : 0] wci_8_mFlagReg$D_IN; + wire wci_8_mFlagReg$EN; + + // register wci_8_pageWindow + reg [11 : 0] wci_8_pageWindow; + wire [11 : 0] wci_8_pageWindow$D_IN; + wire wci_8_pageWindow$EN; + + // register wci_8_reqERR + reg [2 : 0] wci_8_reqERR; + wire [2 : 0] wci_8_reqERR$D_IN; + wire wci_8_reqERR$EN; + + // register wci_8_reqFAIL + reg [2 : 0] wci_8_reqFAIL; + wire [2 : 0] wci_8_reqFAIL$D_IN; + wire wci_8_reqFAIL$EN; + + // register wci_8_reqF_cntr_r + reg wci_8_reqF_cntr_r; + wire wci_8_reqF_cntr_r$D_IN, wci_8_reqF_cntr_r$EN; + + // register wci_8_reqF_q_0 + reg [71 : 0] wci_8_reqF_q_0; + reg [71 : 0] wci_8_reqF_q_0$D_IN; + wire wci_8_reqF_q_0$EN; + + // register wci_8_reqPend + reg [1 : 0] wci_8_reqPend; + reg [1 : 0] wci_8_reqPend$D_IN; + wire wci_8_reqPend$EN; + + // register wci_8_reqTO + reg [2 : 0] wci_8_reqTO; + wire [2 : 0] wci_8_reqTO$D_IN; + wire wci_8_reqTO$EN; + + // register wci_8_respTimr + reg [31 : 0] wci_8_respTimr; + wire [31 : 0] wci_8_respTimr$D_IN; + wire wci_8_respTimr$EN; + + // register wci_8_respTimrAct + reg wci_8_respTimrAct; + wire wci_8_respTimrAct$D_IN, wci_8_respTimrAct$EN; + + // register wci_8_sThreadBusy_d + reg wci_8_sThreadBusy_d; + wire wci_8_sThreadBusy_d$D_IN, wci_8_sThreadBusy_d$EN; + + // register wci_8_sfCap + reg wci_8_sfCap; + wire wci_8_sfCap$D_IN, wci_8_sfCap$EN; + + // register wci_8_sfCapClear + reg wci_8_sfCapClear; + wire wci_8_sfCapClear$D_IN, wci_8_sfCapClear$EN; + + // register wci_8_sfCapSet + reg wci_8_sfCapSet; + wire wci_8_sfCapSet$D_IN, wci_8_sfCapSet$EN; + + // register wci_8_slvPresent + reg wci_8_slvPresent; + wire wci_8_slvPresent$D_IN, wci_8_slvPresent$EN; + + // register wci_8_wReset_n + reg wci_8_wReset_n; + wire wci_8_wReset_n$D_IN, wci_8_wReset_n$EN; + + // register wci_8_wStatus + reg [31 : 0] wci_8_wStatus; + wire [31 : 0] wci_8_wStatus$D_IN; + wire wci_8_wStatus$EN; + + // register wci_8_wTimeout + reg [4 : 0] wci_8_wTimeout; + wire [4 : 0] wci_8_wTimeout$D_IN; + wire wci_8_wTimeout$EN; + + // register wci_9_busy + reg wci_9_busy; + wire wci_9_busy$D_IN, wci_9_busy$EN; + + // register wci_9_lastConfigAddr + reg [32 : 0] wci_9_lastConfigAddr; + wire [32 : 0] wci_9_lastConfigAddr$D_IN; + wire wci_9_lastConfigAddr$EN; + + // register wci_9_lastConfigBE + reg [4 : 0] wci_9_lastConfigBE; + wire [4 : 0] wci_9_lastConfigBE$D_IN; + wire wci_9_lastConfigBE$EN; + + // register wci_9_lastControlOp + reg [3 : 0] wci_9_lastControlOp; + wire [3 : 0] wci_9_lastControlOp$D_IN; + wire wci_9_lastControlOp$EN; + + // register wci_9_lastOpWrite + reg [1 : 0] wci_9_lastOpWrite; + wire [1 : 0] wci_9_lastOpWrite$D_IN; + wire wci_9_lastOpWrite$EN; + + // register wci_9_mFlagReg + reg [1 : 0] wci_9_mFlagReg; + wire [1 : 0] wci_9_mFlagReg$D_IN; + wire wci_9_mFlagReg$EN; + + // register wci_9_pageWindow + reg [11 : 0] wci_9_pageWindow; + wire [11 : 0] wci_9_pageWindow$D_IN; + wire wci_9_pageWindow$EN; + + // register wci_9_reqERR + reg [2 : 0] wci_9_reqERR; + wire [2 : 0] wci_9_reqERR$D_IN; + wire wci_9_reqERR$EN; + + // register wci_9_reqFAIL + reg [2 : 0] wci_9_reqFAIL; + wire [2 : 0] wci_9_reqFAIL$D_IN; + wire wci_9_reqFAIL$EN; + + // register wci_9_reqF_cntr_r + reg wci_9_reqF_cntr_r; + wire wci_9_reqF_cntr_r$D_IN, wci_9_reqF_cntr_r$EN; + + // register wci_9_reqF_q_0 + reg [71 : 0] wci_9_reqF_q_0; + reg [71 : 0] wci_9_reqF_q_0$D_IN; + wire wci_9_reqF_q_0$EN; + + // register wci_9_reqPend + reg [1 : 0] wci_9_reqPend; + reg [1 : 0] wci_9_reqPend$D_IN; + wire wci_9_reqPend$EN; + + // register wci_9_reqTO + reg [2 : 0] wci_9_reqTO; + wire [2 : 0] wci_9_reqTO$D_IN; + wire wci_9_reqTO$EN; + + // register wci_9_respTimr + reg [31 : 0] wci_9_respTimr; + wire [31 : 0] wci_9_respTimr$D_IN; + wire wci_9_respTimr$EN; + + // register wci_9_respTimrAct + reg wci_9_respTimrAct; + wire wci_9_respTimrAct$D_IN, wci_9_respTimrAct$EN; + + // register wci_9_sThreadBusy_d + reg wci_9_sThreadBusy_d; + wire wci_9_sThreadBusy_d$D_IN, wci_9_sThreadBusy_d$EN; + + // register wci_9_sfCap + reg wci_9_sfCap; + wire wci_9_sfCap$D_IN, wci_9_sfCap$EN; + + // register wci_9_sfCapClear + reg wci_9_sfCapClear; + wire wci_9_sfCapClear$D_IN, wci_9_sfCapClear$EN; + + // register wci_9_sfCapSet + reg wci_9_sfCapSet; + wire wci_9_sfCapSet$D_IN, wci_9_sfCapSet$EN; + + // register wci_9_slvPresent + reg wci_9_slvPresent; + wire wci_9_slvPresent$D_IN, wci_9_slvPresent$EN; + + // register wci_9_wReset_n + reg wci_9_wReset_n; + wire wci_9_wReset_n$D_IN, wci_9_wReset_n$EN; + + // register wci_9_wStatus + reg [31 : 0] wci_9_wStatus; + wire [31 : 0] wci_9_wStatus$D_IN; + wire wci_9_wStatus$EN; + + // register wci_9_wTimeout + reg [4 : 0] wci_9_wTimeout; + wire [4 : 0] wci_9_wTimeout$D_IN; + wire wci_9_wTimeout$EN; // register wrkAct reg [3 : 0] wrkAct; @@ -3258,6 +3280,9 @@ module mkOCCP(pciDevice, wire [39 : 0] cpRespF$D_IN, cpRespF$D_OUT; wire cpRespF$CLR, cpRespF$DEQ, cpRespF$EMPTY_N, cpRespF$ENQ, cpRespF$FULL_N; + // ports of submodule dna_dna + wire dna_dna$CLK, dna_dna$DIN, dna_dna$DOUT, dna_dna$READ, dna_dna$SHIFT; + // ports of submodule rom_memory wire [31 : 0] rom_memory$DI, rom_memory$DO; wire [9 : 0] rom_memory$ADDR; @@ -3319,185 +3344,185 @@ module mkOCCP(pciDevice, timeServ_setRefF$sENQ, timeServ_setRefF$sFULL_N; - // ports of submodule wci_mReset - wire wci_mReset$ASSERT_IN, wci_mReset$OUT_RST; - - // ports of submodule wci_mReset_1 - wire wci_mReset_1$ASSERT_IN, wci_mReset_1$OUT_RST; - - // ports of submodule wci_mReset_10 - wire wci_mReset_10$ASSERT_IN, wci_mReset_10$OUT_RST; - - // ports of submodule wci_mReset_11 - wire wci_mReset_11$ASSERT_IN, wci_mReset_11$OUT_RST; - - // ports of submodule wci_mReset_12 - wire wci_mReset_12$ASSERT_IN, wci_mReset_12$OUT_RST; - - // ports of submodule wci_mReset_13 - wire wci_mReset_13$ASSERT_IN, wci_mReset_13$OUT_RST; - - // ports of submodule wci_mReset_14 - wire wci_mReset_14$ASSERT_IN, wci_mReset_14$OUT_RST; - - // ports of submodule wci_mReset_2 - wire wci_mReset_2$ASSERT_IN, wci_mReset_2$OUT_RST; - - // ports of submodule wci_mReset_3 - wire wci_mReset_3$ASSERT_IN, wci_mReset_3$OUT_RST; - - // ports of submodule wci_mReset_4 - wire wci_mReset_4$ASSERT_IN, wci_mReset_4$OUT_RST; - - // ports of submodule wci_mReset_5 - wire wci_mReset_5$ASSERT_IN, wci_mReset_5$OUT_RST; - - // ports of submodule wci_mReset_6 - wire wci_mReset_6$ASSERT_IN, wci_mReset_6$OUT_RST; - - // ports of submodule wci_mReset_7 - wire wci_mReset_7$ASSERT_IN, wci_mReset_7$OUT_RST; - - // ports of submodule wci_mReset_8 - wire wci_mReset_8$ASSERT_IN, wci_mReset_8$OUT_RST; - - // ports of submodule wci_mReset_9 - wire wci_mReset_9$ASSERT_IN, wci_mReset_9$OUT_RST; - - // ports of submodule wci_respF - reg [33 : 0] wci_respF$D_IN; - wire [33 : 0] wci_respF$D_OUT; - wire wci_respF$CLR, - wci_respF$DEQ, - wci_respF$EMPTY_N, - wci_respF$ENQ, - wci_respF$FULL_N; - - // ports of submodule wci_respF_1 - reg [33 : 0] wci_respF_1$D_IN; - wire [33 : 0] wci_respF_1$D_OUT; - wire wci_respF_1$CLR, - wci_respF_1$DEQ, - wci_respF_1$EMPTY_N, - wci_respF_1$ENQ, - wci_respF_1$FULL_N; - - // ports of submodule wci_respF_10 - reg [33 : 0] wci_respF_10$D_IN; - wire [33 : 0] wci_respF_10$D_OUT; - wire wci_respF_10$CLR, - wci_respF_10$DEQ, - wci_respF_10$EMPTY_N, - wci_respF_10$ENQ, - wci_respF_10$FULL_N; - - // ports of submodule wci_respF_11 - reg [33 : 0] wci_respF_11$D_IN; - wire [33 : 0] wci_respF_11$D_OUT; - wire wci_respF_11$CLR, - wci_respF_11$DEQ, - wci_respF_11$EMPTY_N, - wci_respF_11$ENQ, - wci_respF_11$FULL_N; - - // ports of submodule wci_respF_12 - reg [33 : 0] wci_respF_12$D_IN; - wire [33 : 0] wci_respF_12$D_OUT; - wire wci_respF_12$CLR, - wci_respF_12$DEQ, - wci_respF_12$EMPTY_N, - wci_respF_12$ENQ, - wci_respF_12$FULL_N; - - // ports of submodule wci_respF_13 - reg [33 : 0] wci_respF_13$D_IN; - wire [33 : 0] wci_respF_13$D_OUT; - wire wci_respF_13$CLR, - wci_respF_13$DEQ, - wci_respF_13$EMPTY_N, - wci_respF_13$ENQ, - wci_respF_13$FULL_N; - - // ports of submodule wci_respF_14 - reg [33 : 0] wci_respF_14$D_IN; - wire [33 : 0] wci_respF_14$D_OUT; - wire wci_respF_14$CLR, - wci_respF_14$DEQ, - wci_respF_14$EMPTY_N, - wci_respF_14$ENQ, - wci_respF_14$FULL_N; - - // ports of submodule wci_respF_2 - reg [33 : 0] wci_respF_2$D_IN; - wire [33 : 0] wci_respF_2$D_OUT; - wire wci_respF_2$CLR, - wci_respF_2$DEQ, - wci_respF_2$EMPTY_N, - wci_respF_2$ENQ, - wci_respF_2$FULL_N; - - // ports of submodule wci_respF_3 - reg [33 : 0] wci_respF_3$D_IN; - wire [33 : 0] wci_respF_3$D_OUT; - wire wci_respF_3$CLR, - wci_respF_3$DEQ, - wci_respF_3$EMPTY_N, - wci_respF_3$ENQ, - wci_respF_3$FULL_N; - - // ports of submodule wci_respF_4 - reg [33 : 0] wci_respF_4$D_IN; - wire [33 : 0] wci_respF_4$D_OUT; - wire wci_respF_4$CLR, - wci_respF_4$DEQ, - wci_respF_4$EMPTY_N, - wci_respF_4$ENQ, - wci_respF_4$FULL_N; - - // ports of submodule wci_respF_5 - reg [33 : 0] wci_respF_5$D_IN; - wire [33 : 0] wci_respF_5$D_OUT; - wire wci_respF_5$CLR, - wci_respF_5$DEQ, - wci_respF_5$EMPTY_N, - wci_respF_5$ENQ, - wci_respF_5$FULL_N; - - // ports of submodule wci_respF_6 - reg [33 : 0] wci_respF_6$D_IN; - wire [33 : 0] wci_respF_6$D_OUT; - wire wci_respF_6$CLR, - wci_respF_6$DEQ, - wci_respF_6$EMPTY_N, - wci_respF_6$ENQ, - wci_respF_6$FULL_N; - - // ports of submodule wci_respF_7 - reg [33 : 0] wci_respF_7$D_IN; - wire [33 : 0] wci_respF_7$D_OUT; - wire wci_respF_7$CLR, - wci_respF_7$DEQ, - wci_respF_7$EMPTY_N, - wci_respF_7$ENQ, - wci_respF_7$FULL_N; - - // ports of submodule wci_respF_8 - reg [33 : 0] wci_respF_8$D_IN; - wire [33 : 0] wci_respF_8$D_OUT; - wire wci_respF_8$CLR, - wci_respF_8$DEQ, - wci_respF_8$EMPTY_N, - wci_respF_8$ENQ, - wci_respF_8$FULL_N; - - // ports of submodule wci_respF_9 - reg [33 : 0] wci_respF_9$D_IN; - wire [33 : 0] wci_respF_9$D_OUT; - wire wci_respF_9$CLR, - wci_respF_9$DEQ, - wci_respF_9$EMPTY_N, - wci_respF_9$ENQ, - wci_respF_9$FULL_N; + // ports of submodule wci_0_mReset + wire wci_0_mReset$ASSERT_IN, wci_0_mReset$OUT_RST; + + // ports of submodule wci_0_respF + reg [33 : 0] wci_0_respF$D_IN; + wire [33 : 0] wci_0_respF$D_OUT; + wire wci_0_respF$CLR, + wci_0_respF$DEQ, + wci_0_respF$EMPTY_N, + wci_0_respF$ENQ, + wci_0_respF$FULL_N; + + // ports of submodule wci_10_mReset + wire wci_10_mReset$ASSERT_IN, wci_10_mReset$OUT_RST; + + // ports of submodule wci_10_respF + reg [33 : 0] wci_10_respF$D_IN; + wire [33 : 0] wci_10_respF$D_OUT; + wire wci_10_respF$CLR, + wci_10_respF$DEQ, + wci_10_respF$EMPTY_N, + wci_10_respF$ENQ, + wci_10_respF$FULL_N; + + // ports of submodule wci_11_mReset + wire wci_11_mReset$ASSERT_IN, wci_11_mReset$OUT_RST; + + // ports of submodule wci_11_respF + reg [33 : 0] wci_11_respF$D_IN; + wire [33 : 0] wci_11_respF$D_OUT; + wire wci_11_respF$CLR, + wci_11_respF$DEQ, + wci_11_respF$EMPTY_N, + wci_11_respF$ENQ, + wci_11_respF$FULL_N; + + // ports of submodule wci_12_mReset + wire wci_12_mReset$ASSERT_IN, wci_12_mReset$OUT_RST; + + // ports of submodule wci_12_respF + reg [33 : 0] wci_12_respF$D_IN; + wire [33 : 0] wci_12_respF$D_OUT; + wire wci_12_respF$CLR, + wci_12_respF$DEQ, + wci_12_respF$EMPTY_N, + wci_12_respF$ENQ, + wci_12_respF$FULL_N; + + // ports of submodule wci_13_mReset + wire wci_13_mReset$ASSERT_IN, wci_13_mReset$OUT_RST; + + // ports of submodule wci_13_respF + reg [33 : 0] wci_13_respF$D_IN; + wire [33 : 0] wci_13_respF$D_OUT; + wire wci_13_respF$CLR, + wci_13_respF$DEQ, + wci_13_respF$EMPTY_N, + wci_13_respF$ENQ, + wci_13_respF$FULL_N; + + // ports of submodule wci_14_mReset + wire wci_14_mReset$ASSERT_IN, wci_14_mReset$OUT_RST; + + // ports of submodule wci_14_respF + reg [33 : 0] wci_14_respF$D_IN; + wire [33 : 0] wci_14_respF$D_OUT; + wire wci_14_respF$CLR, + wci_14_respF$DEQ, + wci_14_respF$EMPTY_N, + wci_14_respF$ENQ, + wci_14_respF$FULL_N; + + // ports of submodule wci_1_mReset + wire wci_1_mReset$ASSERT_IN, wci_1_mReset$OUT_RST; + + // ports of submodule wci_1_respF + reg [33 : 0] wci_1_respF$D_IN; + wire [33 : 0] wci_1_respF$D_OUT; + wire wci_1_respF$CLR, + wci_1_respF$DEQ, + wci_1_respF$EMPTY_N, + wci_1_respF$ENQ, + wci_1_respF$FULL_N; + + // ports of submodule wci_2_mReset + wire wci_2_mReset$ASSERT_IN, wci_2_mReset$OUT_RST; + + // ports of submodule wci_2_respF + reg [33 : 0] wci_2_respF$D_IN; + wire [33 : 0] wci_2_respF$D_OUT; + wire wci_2_respF$CLR, + wci_2_respF$DEQ, + wci_2_respF$EMPTY_N, + wci_2_respF$ENQ, + wci_2_respF$FULL_N; + + // ports of submodule wci_3_mReset + wire wci_3_mReset$ASSERT_IN, wci_3_mReset$OUT_RST; + + // ports of submodule wci_3_respF + reg [33 : 0] wci_3_respF$D_IN; + wire [33 : 0] wci_3_respF$D_OUT; + wire wci_3_respF$CLR, + wci_3_respF$DEQ, + wci_3_respF$EMPTY_N, + wci_3_respF$ENQ, + wci_3_respF$FULL_N; + + // ports of submodule wci_4_mReset + wire wci_4_mReset$ASSERT_IN, wci_4_mReset$OUT_RST; + + // ports of submodule wci_4_respF + reg [33 : 0] wci_4_respF$D_IN; + wire [33 : 0] wci_4_respF$D_OUT; + wire wci_4_respF$CLR, + wci_4_respF$DEQ, + wci_4_respF$EMPTY_N, + wci_4_respF$ENQ, + wci_4_respF$FULL_N; + + // ports of submodule wci_5_mReset + wire wci_5_mReset$ASSERT_IN, wci_5_mReset$OUT_RST; + + // ports of submodule wci_5_respF + reg [33 : 0] wci_5_respF$D_IN; + wire [33 : 0] wci_5_respF$D_OUT; + wire wci_5_respF$CLR, + wci_5_respF$DEQ, + wci_5_respF$EMPTY_N, + wci_5_respF$ENQ, + wci_5_respF$FULL_N; + + // ports of submodule wci_6_mReset + wire wci_6_mReset$ASSERT_IN, wci_6_mReset$OUT_RST; + + // ports of submodule wci_6_respF + reg [33 : 0] wci_6_respF$D_IN; + wire [33 : 0] wci_6_respF$D_OUT; + wire wci_6_respF$CLR, + wci_6_respF$DEQ, + wci_6_respF$EMPTY_N, + wci_6_respF$ENQ, + wci_6_respF$FULL_N; + + // ports of submodule wci_7_mReset + wire wci_7_mReset$ASSERT_IN, wci_7_mReset$OUT_RST; + + // ports of submodule wci_7_respF + reg [33 : 0] wci_7_respF$D_IN; + wire [33 : 0] wci_7_respF$D_OUT; + wire wci_7_respF$CLR, + wci_7_respF$DEQ, + wci_7_respF$EMPTY_N, + wci_7_respF$ENQ, + wci_7_respF$FULL_N; + + // ports of submodule wci_8_mReset + wire wci_8_mReset$ASSERT_IN, wci_8_mReset$OUT_RST; + + // ports of submodule wci_8_respF + reg [33 : 0] wci_8_respF$D_IN; + wire [33 : 0] wci_8_respF$D_OUT; + wire wci_8_respF$CLR, + wci_8_respF$DEQ, + wci_8_respF$EMPTY_N, + wci_8_respF$ENQ, + wci_8_respF$FULL_N; + + // ports of submodule wci_9_mReset + wire wci_9_mReset$ASSERT_IN, wci_9_mReset$OUT_RST; + + // ports of submodule wci_9_respF + reg [33 : 0] wci_9_respF$D_IN; + wire [33 : 0] wci_9_respF$D_OUT; + wire wci_9_respF$CLR, + wci_9_respF$DEQ, + wci_9_respF$EMPTY_N, + wci_9_respF$ENQ, + wci_9_respF$FULL_N; // rule scheduling signals wire CAN_FIRE_RL_cpDispatch_F_T_F_F, @@ -3508,279 +3533,279 @@ module mkOCCP(pciDevice, CAN_FIRE_RL_cpDispatch_F_T_T_T, WILL_FIRE_RL_completeWorkerRead, WILL_FIRE_RL_completeWorkerWrite, - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F, - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F, - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T, - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T, - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T, - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T, - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F, - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T, - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F, - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T, - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F, - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T, - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T, - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T, - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T, - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F, - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T, - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F, - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T, - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F, - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T, - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T, - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T, - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T, - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F, - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T, - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F, - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T, - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F, - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T, - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T, - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T, - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T, - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F, - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T, - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F, - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T, - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F, - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T, - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T, - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T, - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T, - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F, - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T, - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F, - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T, - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F, - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T, - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T, - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T, - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T, - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F, - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T, - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F, - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T, - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F, - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T, - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T, - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T, - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T, - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F, - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T, - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F, - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T, - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F, - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T, - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T, - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T, - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T, - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F, - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T, - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_T_F, - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_T_T, - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F, - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T, - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T, - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T, - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_F_F_T, - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_F_T_F, - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_F_T_T, - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_T_F, - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_T_T, - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F, - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T, - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T, - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_F_F_T, - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_F_T, - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_T_F, - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_T_T, - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_T_F, - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_T_T, - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F, - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T, - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_F_F_F_T, - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_F_F_T, - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_F_T, - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_T_F, - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_T_T, - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_T_F, - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_T_T, - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_F_F_F_F_F_F, - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_F_F_F_F_F_T, - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_F_F_F_F_T, - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_F_F_F_T, - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_F_F_T, - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_F_T_F, - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_F_T_T, - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_T_F, - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_T_T, - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_F_F_F_F_F_F, - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_F_F_F_F_F_T, - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_F_F_F_F_T, - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_F_F_F_T, - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_F_F_T, - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_F_T_F, - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_F_T_T, - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_T_F, - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_T_T, - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_F_F_F_F_F_F, - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_F_F_F_F_F_T, - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_F_F_F_F_T, - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_F_F_F_T, - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_F_F_T, - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_F_T_F, - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_F_T_T, - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_T_F, - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_T_T, - WILL_FIRE_RL_cpDispatch_F_F_F_F_T_F_F_F_F_F_F, - WILL_FIRE_RL_cpDispatch_F_F_F_F_T_F_F_F_F_F_T, - WILL_FIRE_RL_cpDispatch_F_F_F_F_T_F_F_F_F_T, - WILL_FIRE_RL_cpDispatch_F_F_F_F_T_F_F_F_T, - WILL_FIRE_RL_cpDispatch_F_F_F_F_T_F_F_T, - WILL_FIRE_RL_cpDispatch_F_F_F_F_T_F_T_F, - WILL_FIRE_RL_cpDispatch_F_F_F_F_T_F_T_T, - WILL_FIRE_RL_cpDispatch_F_F_F_F_T_T_F, - WILL_FIRE_RL_cpDispatch_F_F_F_F_T_T_T, + WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_F_F_F_F_F, + WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_F_F_F_F_T, + WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_F_F_F_T, + WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_F_F_T, + WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_F_T, + WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_T_F, + WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_T_T, + WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_T_F, + WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_T_T, + WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_F_F_F_F_F_F, + WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_F_F_F_F_F_T, + WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_F_F_F_F_T, + WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_F_F_F_T, + WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_F_F_T, + WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_F_T_F, + WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_F_T_T, + WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_T_F, + WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_T_T, + WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_F_F_F_F_F_F, + WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_F_F_F_F_F_T, + WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_F_F_F_F_T, + WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_F_F_F_T, + WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_F_F_T, + WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_F_T_F, + WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_F_T_T, + WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_T_F, + WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_T_T, + WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_F_F_F_F_F_F, + WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_F_F_F_F_F_T, + WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_F_F_F_F_T, + WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_F_F_F_T, + WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_F_F_T, + WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_F_T_F, + WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_F_T_T, + WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_T_F, + WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_T_T, + WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_F_F_F_F_F_F, + WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_F_F_F_F_F_T, + WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_F_F_F_F_T, + WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_F_F_F_T, + WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_F_F_T, + WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_F_T_F, + WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_F_T_T, + WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_T_F, + WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_T_T, + WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_F_F_F_F_F_F, + WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_F_F_F_F_F_T, + WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_F_F_F_F_T, + WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_F_F_F_T, + WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_F_F_T, + WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_F_T_F, + WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_F_T_T, + WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_T_F, + WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_T_T, + WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_F_F_F_F_F, + WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_F_F_F_F_T, + WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_F_F_F_T, + WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_F_F_T, + WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_F_T, + WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_T_F, + WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_T_T, + WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_T_F, + WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_T_T, + WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_F_F_F_F_F_F, + WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_F_F_F_F_F_T, + WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_F_F_F_F_T, + WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_F_F_F_T, + WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_F_F_T, + WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_F_T_F, + WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_F_T_T, + WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_T_F, + WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_T_T, + WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_F_F_F_F_F_F, + WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_F_F_F_F_F_T, + WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_F_F_F_F_T, + WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_F_F_F_T, + WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_F_F_T, + WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_F_T_F, + WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_F_T_T, + WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_T_F, + WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_T_T, + WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_F_F_F_F_F_F, + WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_F_F_F_F_F_T, + WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_F_F_F_F_T, + WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_F_F_F_T, + WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_F_F_T, + WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_F_T_F, + WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_F_T_T, + WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_T_F, + WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_T_T, + WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_F_F_F_F_F, + WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_F_F_F_F_T, + WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_F_F_F_T, + WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_F_F_T, + WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_F_T, + WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_T_F, + WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_T_T, + WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_T_F, + WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_T_T, + WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_F_F_F_F_F_F, + WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_F_F_F_F_F_T, + WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_F_F_F_F_T, + WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_F_F_F_T, + WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_F_F_T, + WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_F_T_F, + WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_F_T_T, + WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_T_F, + WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_T_T, + WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_F_F_F_F_F, + WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_F_F_F_F_T, + WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_F_F_F_T, + WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_F_F_T, + WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_F_T, + WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_T_F, + WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_T_T, + WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_T_F, + WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_T_T, + WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_F_F_F_F_F, + WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_F_F_F_F_T, + WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_F_F_F_T, + WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_F_F_T, + WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_F_T, + WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_T_F, + WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_T_T, + WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_T_F, + WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_T_T, + WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_F_F_F_F_F_F, + WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_F_F_F_F_F_T, + WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_F_F_F_F_T, + WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_F_F_F_T, + WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_F_F_T, + WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_F_T_F, + WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_F_T_T, + WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_T_F, + WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_T_T, + WILL_FIRE_RL_cpDispatch_F_F_F_F_OOB, WILL_FIRE_RL_cpDispatch_F_F_F_T, - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F, - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F, - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T, - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_F, - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_T, - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_F, - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_T, - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T, - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F, - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T, - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F, - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T, - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_F, - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_T, - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_F, - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_T, - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T, - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F, - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T, - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F, - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T, - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_F, - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_T, - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_F, - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_T, - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T, - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F, - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T, - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F, - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T, - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_F, - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_T, - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_F, - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_T, - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_F_T, - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_T_F, - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_T_T, - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F, - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T, - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_F, - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_T, - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_F, - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_T, - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_T, - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_T_F, - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_T_T, - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_F_F_F_F, - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_F_F_F_T, - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_F_F_T_F_F, - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_F_F_T_F_T, - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_F_F_T_T_F, - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_F_F_T_T_T, - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_F_T, - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_T_F, - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_T_T, - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_F_F_F_F, - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_F_F_F_T, - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_F_F_T_F_F, - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_F_F_T_F_T, - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_F_F_T_T_F, - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_F_F_T_T_T, - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_F_T, - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_T_F, - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_T_T, - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_F_F_F_F, - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_F_F_F_T, - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_F_F_T_F_F, - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_F_F_T_F_T, - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_F_F_T_T_F, - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_F_F_T_T_T, - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_F_T, - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_T_F, - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_T_T, - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_F_F_F_F, - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_F_F_F_T, - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_F_F_T_F_F, - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_F_F_T_F_T, - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_F_F_T_T_F, - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_F_F_T_T_T, - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_F_T, - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_T_F, - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_T_T, - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_F_F_F, - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_F_F_T, - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_F_T_F_F, - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_F_T_F_T, - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_F_T_T_F, - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_F_T_T_T, - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_T, - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_T_F, - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_T_T, - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_F_F_F_F, - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_F_F_F_T, - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_F_F_T_F_F, - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_F_F_T_F_T, - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_F_F_T_T_F, - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_F_F_T_T_T, - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_F_T, - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_T_F, - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_T_T, - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_F_F_F_F, - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_F_F_F_T, - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_F_F_T_F_F, - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_F_F_T_F_T, - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_F_F_T_T_F, - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_F_F_T_T_T, - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_F_T, - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_T_F, - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_T_T, - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_F_F_F_F, - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_F_F_F_T, - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_F_F_T_F_F, - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_F_F_T_F_T, - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_F_F_T_T_F, - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_F_F_T_T_T, - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_F_T, - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_T_F, - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_T_T, - WILL_FIRE_RL_cpDispatch_F_F_T_F_T_F_F_F_F, - WILL_FIRE_RL_cpDispatch_F_F_T_F_T_F_F_F_T, - WILL_FIRE_RL_cpDispatch_F_F_T_F_T_F_F_T_F_F, - WILL_FIRE_RL_cpDispatch_F_F_T_F_T_F_F_T_F_T, - WILL_FIRE_RL_cpDispatch_F_F_T_F_T_F_F_T_T_F, - WILL_FIRE_RL_cpDispatch_F_F_T_F_T_F_F_T_T_T, - WILL_FIRE_RL_cpDispatch_F_F_T_F_T_F_T, - WILL_FIRE_RL_cpDispatch_F_F_T_F_T_T_F, - WILL_FIRE_RL_cpDispatch_F_F_T_F_T_T_T, - WILL_FIRE_RL_cpDispatch_F_F_T_T_F_F_F_F, - WILL_FIRE_RL_cpDispatch_F_F_T_T_F_F_F_T, - WILL_FIRE_RL_cpDispatch_F_F_T_T_F_F_T_F_F, - WILL_FIRE_RL_cpDispatch_F_F_T_T_F_F_T_F_T, - WILL_FIRE_RL_cpDispatch_F_F_T_T_F_F_T_T_F, - WILL_FIRE_RL_cpDispatch_F_F_T_T_F_F_T_T_T, - WILL_FIRE_RL_cpDispatch_F_F_T_T_F_T, - WILL_FIRE_RL_cpDispatch_F_F_T_T_T_F, - WILL_FIRE_RL_cpDispatch_F_F_T_T_T_T, + WILL_FIRE_RL_cpDispatch_F_F_T_E0_F_F_F_F, + WILL_FIRE_RL_cpDispatch_F_F_T_E0_F_F_F_T, + WILL_FIRE_RL_cpDispatch_F_F_T_E0_F_F_T_F_F, + WILL_FIRE_RL_cpDispatch_F_F_T_E0_F_F_T_F_T, + WILL_FIRE_RL_cpDispatch_F_F_T_E0_F_F_T_T_F, + WILL_FIRE_RL_cpDispatch_F_F_T_E0_F_F_T_T_T, + WILL_FIRE_RL_cpDispatch_F_F_T_E0_F_T, + WILL_FIRE_RL_cpDispatch_F_F_T_E0_T_F, + WILL_FIRE_RL_cpDispatch_F_F_T_E0_T_T, + WILL_FIRE_RL_cpDispatch_F_F_T_E10_F_F_F_F, + WILL_FIRE_RL_cpDispatch_F_F_T_E10_F_F_F_T, + WILL_FIRE_RL_cpDispatch_F_F_T_E10_F_F_T_F_F, + WILL_FIRE_RL_cpDispatch_F_F_T_E10_F_F_T_F_T, + WILL_FIRE_RL_cpDispatch_F_F_T_E10_F_F_T_T_F, + WILL_FIRE_RL_cpDispatch_F_F_T_E10_F_F_T_T_T, + WILL_FIRE_RL_cpDispatch_F_F_T_E10_F_T, + WILL_FIRE_RL_cpDispatch_F_F_T_E10_T_F, + WILL_FIRE_RL_cpDispatch_F_F_T_E10_T_T, + WILL_FIRE_RL_cpDispatch_F_F_T_E11_F_F_F_F, + WILL_FIRE_RL_cpDispatch_F_F_T_E11_F_F_F_T, + WILL_FIRE_RL_cpDispatch_F_F_T_E11_F_F_T_F_F, + WILL_FIRE_RL_cpDispatch_F_F_T_E11_F_F_T_F_T, + WILL_FIRE_RL_cpDispatch_F_F_T_E11_F_F_T_T_F, + WILL_FIRE_RL_cpDispatch_F_F_T_E11_F_F_T_T_T, + WILL_FIRE_RL_cpDispatch_F_F_T_E11_F_T, + WILL_FIRE_RL_cpDispatch_F_F_T_E11_T_F, + WILL_FIRE_RL_cpDispatch_F_F_T_E11_T_T, + WILL_FIRE_RL_cpDispatch_F_F_T_E12_F_F_F_F, + WILL_FIRE_RL_cpDispatch_F_F_T_E12_F_F_F_T, + WILL_FIRE_RL_cpDispatch_F_F_T_E12_F_F_T_F_F, + WILL_FIRE_RL_cpDispatch_F_F_T_E12_F_F_T_F_T, + WILL_FIRE_RL_cpDispatch_F_F_T_E12_F_F_T_T_F, + WILL_FIRE_RL_cpDispatch_F_F_T_E12_F_F_T_T_T, + WILL_FIRE_RL_cpDispatch_F_F_T_E12_F_T, + WILL_FIRE_RL_cpDispatch_F_F_T_E12_T_F, + WILL_FIRE_RL_cpDispatch_F_F_T_E12_T_T, + WILL_FIRE_RL_cpDispatch_F_F_T_E13_F_F_F_F, + WILL_FIRE_RL_cpDispatch_F_F_T_E13_F_F_F_T, + WILL_FIRE_RL_cpDispatch_F_F_T_E13_F_F_T_F_F, + WILL_FIRE_RL_cpDispatch_F_F_T_E13_F_F_T_F_T, + WILL_FIRE_RL_cpDispatch_F_F_T_E13_F_F_T_T_F, + WILL_FIRE_RL_cpDispatch_F_F_T_E13_F_F_T_T_T, + WILL_FIRE_RL_cpDispatch_F_F_T_E13_F_T, + WILL_FIRE_RL_cpDispatch_F_F_T_E13_T_F, + WILL_FIRE_RL_cpDispatch_F_F_T_E13_T_T, + WILL_FIRE_RL_cpDispatch_F_F_T_E14_F_F_F_F, + WILL_FIRE_RL_cpDispatch_F_F_T_E14_F_F_F_T, + WILL_FIRE_RL_cpDispatch_F_F_T_E14_F_F_T_F_F, + WILL_FIRE_RL_cpDispatch_F_F_T_E14_F_F_T_F_T, + WILL_FIRE_RL_cpDispatch_F_F_T_E14_F_F_T_T_F, + WILL_FIRE_RL_cpDispatch_F_F_T_E14_F_F_T_T_T, + WILL_FIRE_RL_cpDispatch_F_F_T_E14_F_T, + WILL_FIRE_RL_cpDispatch_F_F_T_E14_T_F, + WILL_FIRE_RL_cpDispatch_F_F_T_E14_T_T, + WILL_FIRE_RL_cpDispatch_F_F_T_E1_F_F_F_F, + WILL_FIRE_RL_cpDispatch_F_F_T_E1_F_F_F_T, + WILL_FIRE_RL_cpDispatch_F_F_T_E1_F_F_T_F_F, + WILL_FIRE_RL_cpDispatch_F_F_T_E1_F_F_T_F_T, + WILL_FIRE_RL_cpDispatch_F_F_T_E1_F_F_T_T_F, + WILL_FIRE_RL_cpDispatch_F_F_T_E1_F_F_T_T_T, + WILL_FIRE_RL_cpDispatch_F_F_T_E1_F_T, + WILL_FIRE_RL_cpDispatch_F_F_T_E1_T_F, + WILL_FIRE_RL_cpDispatch_F_F_T_E1_T_T, + WILL_FIRE_RL_cpDispatch_F_F_T_E2_F_F_F_F, + WILL_FIRE_RL_cpDispatch_F_F_T_E2_F_F_F_T, + WILL_FIRE_RL_cpDispatch_F_F_T_E2_F_F_T_F_F, + WILL_FIRE_RL_cpDispatch_F_F_T_E2_F_F_T_F_T, + WILL_FIRE_RL_cpDispatch_F_F_T_E2_F_F_T_T_F, + WILL_FIRE_RL_cpDispatch_F_F_T_E2_F_F_T_T_T, + WILL_FIRE_RL_cpDispatch_F_F_T_E2_F_T, + WILL_FIRE_RL_cpDispatch_F_F_T_E2_T_F, + WILL_FIRE_RL_cpDispatch_F_F_T_E2_T_T, + WILL_FIRE_RL_cpDispatch_F_F_T_E3_F_F_F_F, + WILL_FIRE_RL_cpDispatch_F_F_T_E3_F_F_F_T, + WILL_FIRE_RL_cpDispatch_F_F_T_E3_F_F_T_F_F, + WILL_FIRE_RL_cpDispatch_F_F_T_E3_F_F_T_F_T, + WILL_FIRE_RL_cpDispatch_F_F_T_E3_F_F_T_T_F, + WILL_FIRE_RL_cpDispatch_F_F_T_E3_F_F_T_T_T, + WILL_FIRE_RL_cpDispatch_F_F_T_E3_F_T, + WILL_FIRE_RL_cpDispatch_F_F_T_E3_T_F, + WILL_FIRE_RL_cpDispatch_F_F_T_E3_T_T, + WILL_FIRE_RL_cpDispatch_F_F_T_E4_F_F_F_F, + WILL_FIRE_RL_cpDispatch_F_F_T_E4_F_F_F_T, + WILL_FIRE_RL_cpDispatch_F_F_T_E4_F_F_T_F_F, + WILL_FIRE_RL_cpDispatch_F_F_T_E4_F_F_T_F_T, + WILL_FIRE_RL_cpDispatch_F_F_T_E4_F_F_T_T_F, + WILL_FIRE_RL_cpDispatch_F_F_T_E4_F_F_T_T_T, + WILL_FIRE_RL_cpDispatch_F_F_T_E4_F_T, + WILL_FIRE_RL_cpDispatch_F_F_T_E4_T_F, + WILL_FIRE_RL_cpDispatch_F_F_T_E4_T_T, + WILL_FIRE_RL_cpDispatch_F_F_T_E5_F_F_F_F, + WILL_FIRE_RL_cpDispatch_F_F_T_E5_F_F_F_T, + WILL_FIRE_RL_cpDispatch_F_F_T_E5_F_F_T_F_F, + WILL_FIRE_RL_cpDispatch_F_F_T_E5_F_F_T_F_T, + WILL_FIRE_RL_cpDispatch_F_F_T_E5_F_F_T_T_F, + WILL_FIRE_RL_cpDispatch_F_F_T_E5_F_F_T_T_T, + WILL_FIRE_RL_cpDispatch_F_F_T_E5_F_T, + WILL_FIRE_RL_cpDispatch_F_F_T_E5_T_F, + WILL_FIRE_RL_cpDispatch_F_F_T_E5_T_T, + WILL_FIRE_RL_cpDispatch_F_F_T_E6_F_F_F_F, + WILL_FIRE_RL_cpDispatch_F_F_T_E6_F_F_F_T, + WILL_FIRE_RL_cpDispatch_F_F_T_E6_F_F_T_F_F, + WILL_FIRE_RL_cpDispatch_F_F_T_E6_F_F_T_F_T, + WILL_FIRE_RL_cpDispatch_F_F_T_E6_F_F_T_T_F, + WILL_FIRE_RL_cpDispatch_F_F_T_E6_F_F_T_T_T, + WILL_FIRE_RL_cpDispatch_F_F_T_E6_F_T, + WILL_FIRE_RL_cpDispatch_F_F_T_E6_T_F, + WILL_FIRE_RL_cpDispatch_F_F_T_E6_T_T, + WILL_FIRE_RL_cpDispatch_F_F_T_E7_F_F_F_F, + WILL_FIRE_RL_cpDispatch_F_F_T_E7_F_F_F_T, + WILL_FIRE_RL_cpDispatch_F_F_T_E7_F_F_T_F_F, + WILL_FIRE_RL_cpDispatch_F_F_T_E7_F_F_T_F_T, + WILL_FIRE_RL_cpDispatch_F_F_T_E7_F_F_T_T_F, + WILL_FIRE_RL_cpDispatch_F_F_T_E7_F_F_T_T_T, + WILL_FIRE_RL_cpDispatch_F_F_T_E7_F_T, + WILL_FIRE_RL_cpDispatch_F_F_T_E7_T_F, + WILL_FIRE_RL_cpDispatch_F_F_T_E7_T_T, + WILL_FIRE_RL_cpDispatch_F_F_T_E8_F_F_F_F, + WILL_FIRE_RL_cpDispatch_F_F_T_E8_F_F_F_T, + WILL_FIRE_RL_cpDispatch_F_F_T_E8_F_F_T_F_F, + WILL_FIRE_RL_cpDispatch_F_F_T_E8_F_F_T_F_T, + WILL_FIRE_RL_cpDispatch_F_F_T_E8_F_F_T_T_F, + WILL_FIRE_RL_cpDispatch_F_F_T_E8_F_F_T_T_T, + WILL_FIRE_RL_cpDispatch_F_F_T_E8_F_T, + WILL_FIRE_RL_cpDispatch_F_F_T_E8_T_F, + WILL_FIRE_RL_cpDispatch_F_F_T_E8_T_T, + WILL_FIRE_RL_cpDispatch_F_F_T_E9_F_F_F_F, + WILL_FIRE_RL_cpDispatch_F_F_T_E9_F_F_F_T, + WILL_FIRE_RL_cpDispatch_F_F_T_E9_F_F_T_F_F, + WILL_FIRE_RL_cpDispatch_F_F_T_E9_F_F_T_F_T, + WILL_FIRE_RL_cpDispatch_F_F_T_E9_F_F_T_T_F, + WILL_FIRE_RL_cpDispatch_F_F_T_E9_F_F_T_T_T, + WILL_FIRE_RL_cpDispatch_F_F_T_E9_F_T, + WILL_FIRE_RL_cpDispatch_F_F_T_E9_T_F, + WILL_FIRE_RL_cpDispatch_F_F_T_E9_T_T, + WILL_FIRE_RL_cpDispatch_F_F_T_OOB, WILL_FIRE_RL_cpDispatch_F_T_F_T, WILL_FIRE_RL_cpDispatch_F_T_T_F_F, WILL_FIRE_RL_cpDispatch_F_T_T_F_T_F_F, @@ -3804,945 +3829,1037 @@ module mkOCCP(pciDevice, WILL_FIRE_RL_responseAdminRd, WILL_FIRE_RL_rom_serverAdapter_outData_enqAndDeq, WILL_FIRE_RL_rom_serverAdapter_stageReadResponseAlways, - WILL_FIRE_RL_wci_reqF_10_both, - WILL_FIRE_RL_wci_reqF_10_decCtr, - WILL_FIRE_RL_wci_reqF_10_incCtr, - WILL_FIRE_RL_wci_reqF_11_both, - WILL_FIRE_RL_wci_reqF_11_decCtr, - WILL_FIRE_RL_wci_reqF_11_incCtr, - WILL_FIRE_RL_wci_reqF_12_both, - WILL_FIRE_RL_wci_reqF_12_decCtr, - WILL_FIRE_RL_wci_reqF_12_incCtr, - WILL_FIRE_RL_wci_reqF_13_both, - WILL_FIRE_RL_wci_reqF_13_decCtr, - WILL_FIRE_RL_wci_reqF_13_incCtr, - WILL_FIRE_RL_wci_reqF_14_both, - WILL_FIRE_RL_wci_reqF_14_decCtr, - WILL_FIRE_RL_wci_reqF_14_incCtr, - WILL_FIRE_RL_wci_reqF_1_both, - WILL_FIRE_RL_wci_reqF_1_decCtr, - WILL_FIRE_RL_wci_reqF_1_incCtr, - WILL_FIRE_RL_wci_reqF_2_both, - WILL_FIRE_RL_wci_reqF_2_decCtr, - WILL_FIRE_RL_wci_reqF_2_incCtr, - WILL_FIRE_RL_wci_reqF_3_both, - WILL_FIRE_RL_wci_reqF_3_decCtr, - WILL_FIRE_RL_wci_reqF_3_incCtr, - WILL_FIRE_RL_wci_reqF_4_both, - WILL_FIRE_RL_wci_reqF_4_decCtr, - WILL_FIRE_RL_wci_reqF_4_incCtr, - WILL_FIRE_RL_wci_reqF_5_both, - WILL_FIRE_RL_wci_reqF_5_decCtr, - WILL_FIRE_RL_wci_reqF_5_incCtr, - WILL_FIRE_RL_wci_reqF_6_both, - WILL_FIRE_RL_wci_reqF_6_decCtr, - WILL_FIRE_RL_wci_reqF_6_incCtr, - WILL_FIRE_RL_wci_reqF_7_both, - WILL_FIRE_RL_wci_reqF_7_decCtr, - WILL_FIRE_RL_wci_reqF_7_incCtr, - WILL_FIRE_RL_wci_reqF_8_both, - WILL_FIRE_RL_wci_reqF_8_decCtr, - WILL_FIRE_RL_wci_reqF_8_incCtr, - WILL_FIRE_RL_wci_reqF_9_both, - WILL_FIRE_RL_wci_reqF_9_decCtr, - WILL_FIRE_RL_wci_reqF_9_incCtr, - WILL_FIRE_RL_wci_reqF_both, - WILL_FIRE_RL_wci_reqF_decCtr, - WILL_FIRE_RL_wci_reqF_incCtr, - WILL_FIRE_RL_wci_wrkBusy, - WILL_FIRE_RL_wci_wrkBusy_1, - WILL_FIRE_RL_wci_wrkBusy_10, - WILL_FIRE_RL_wci_wrkBusy_11, - WILL_FIRE_RL_wci_wrkBusy_12, - WILL_FIRE_RL_wci_wrkBusy_13, - WILL_FIRE_RL_wci_wrkBusy_14, - WILL_FIRE_RL_wci_wrkBusy_2, - WILL_FIRE_RL_wci_wrkBusy_3, - WILL_FIRE_RL_wci_wrkBusy_4, - WILL_FIRE_RL_wci_wrkBusy_5, - WILL_FIRE_RL_wci_wrkBusy_6, - WILL_FIRE_RL_wci_wrkBusy_7, - WILL_FIRE_RL_wci_wrkBusy_8, - WILL_FIRE_RL_wci_wrkBusy_9; + WILL_FIRE_RL_wci_0_reqF_both, + WILL_FIRE_RL_wci_0_reqF_decCtr, + WILL_FIRE_RL_wci_0_reqF_incCtr, + WILL_FIRE_RL_wci_0_wrkBusy, + WILL_FIRE_RL_wci_10_reqF_both, + WILL_FIRE_RL_wci_10_reqF_decCtr, + WILL_FIRE_RL_wci_10_reqF_incCtr, + WILL_FIRE_RL_wci_10_wrkBusy, + WILL_FIRE_RL_wci_11_reqF_both, + WILL_FIRE_RL_wci_11_reqF_decCtr, + WILL_FIRE_RL_wci_11_reqF_incCtr, + WILL_FIRE_RL_wci_11_wrkBusy, + WILL_FIRE_RL_wci_12_reqF_both, + WILL_FIRE_RL_wci_12_reqF_decCtr, + WILL_FIRE_RL_wci_12_reqF_incCtr, + WILL_FIRE_RL_wci_12_wrkBusy, + WILL_FIRE_RL_wci_13_reqF_both, + WILL_FIRE_RL_wci_13_reqF_decCtr, + WILL_FIRE_RL_wci_13_reqF_incCtr, + WILL_FIRE_RL_wci_13_wrkBusy, + WILL_FIRE_RL_wci_14_reqF_both, + WILL_FIRE_RL_wci_14_reqF_decCtr, + WILL_FIRE_RL_wci_14_reqF_incCtr, + WILL_FIRE_RL_wci_14_wrkBusy, + WILL_FIRE_RL_wci_1_reqF_both, + WILL_FIRE_RL_wci_1_reqF_decCtr, + WILL_FIRE_RL_wci_1_reqF_incCtr, + WILL_FIRE_RL_wci_1_wrkBusy, + WILL_FIRE_RL_wci_2_reqF_both, + WILL_FIRE_RL_wci_2_reqF_decCtr, + WILL_FIRE_RL_wci_2_reqF_incCtr, + WILL_FIRE_RL_wci_2_wrkBusy, + WILL_FIRE_RL_wci_3_reqF_both, + WILL_FIRE_RL_wci_3_reqF_decCtr, + WILL_FIRE_RL_wci_3_reqF_incCtr, + WILL_FIRE_RL_wci_3_wrkBusy, + WILL_FIRE_RL_wci_4_reqF_both, + WILL_FIRE_RL_wci_4_reqF_decCtr, + WILL_FIRE_RL_wci_4_reqF_incCtr, + WILL_FIRE_RL_wci_4_wrkBusy, + WILL_FIRE_RL_wci_5_reqF_both, + WILL_FIRE_RL_wci_5_reqF_decCtr, + WILL_FIRE_RL_wci_5_reqF_incCtr, + WILL_FIRE_RL_wci_5_wrkBusy, + WILL_FIRE_RL_wci_6_reqF_both, + WILL_FIRE_RL_wci_6_reqF_decCtr, + WILL_FIRE_RL_wci_6_reqF_incCtr, + WILL_FIRE_RL_wci_6_wrkBusy, + WILL_FIRE_RL_wci_7_reqF_both, + WILL_FIRE_RL_wci_7_reqF_decCtr, + WILL_FIRE_RL_wci_7_reqF_incCtr, + WILL_FIRE_RL_wci_7_wrkBusy, + WILL_FIRE_RL_wci_8_reqF_both, + WILL_FIRE_RL_wci_8_reqF_decCtr, + WILL_FIRE_RL_wci_8_reqF_incCtr, + WILL_FIRE_RL_wci_8_wrkBusy, + WILL_FIRE_RL_wci_9_reqF_both, + WILL_FIRE_RL_wci_9_reqF_decCtr, + WILL_FIRE_RL_wci_9_reqF_incCtr, + WILL_FIRE_RL_wci_9_wrkBusy; // inputs to muxes for submodule ports - reg [71 : 0] MUX_wci_reqF_10_q_0$write_1__VAL_1, - MUX_wci_reqF_11_q_0$write_1__VAL_1, - MUX_wci_reqF_12_q_0$write_1__VAL_1, - MUX_wci_reqF_13_q_0$write_1__VAL_1, - MUX_wci_reqF_14_q_0$write_1__VAL_1, - MUX_wci_reqF_1_q_0$write_1__VAL_2, - MUX_wci_reqF_2_q_0$write_1__VAL_1, - MUX_wci_reqF_3_q_0$write_1__VAL_1, - MUX_wci_reqF_4_q_0$write_1__VAL_1, - MUX_wci_reqF_5_q_0$write_1__VAL_1, - MUX_wci_reqF_6_q_0$write_1__VAL_1, - MUX_wci_reqF_7_q_0$write_1__VAL_1, - MUX_wci_reqF_8_q_0$write_1__VAL_1, - MUX_wci_reqF_9_q_0$write_1__VAL_1, - MUX_wci_reqF_q_0$write_1__VAL_2; - reg [2 : 0] MUX_wci_reqERR$write_1__VAL_1, - MUX_wci_reqERR_1$write_1__VAL_1, - MUX_wci_reqERR_10$write_1__VAL_1, - MUX_wci_reqERR_11$write_1__VAL_1, - MUX_wci_reqERR_12$write_1__VAL_1, - MUX_wci_reqERR_13$write_1__VAL_1, - MUX_wci_reqERR_14$write_1__VAL_1, - MUX_wci_reqERR_2$write_1__VAL_1, - MUX_wci_reqERR_3$write_1__VAL_1, - MUX_wci_reqERR_4$write_1__VAL_1, - MUX_wci_reqERR_5$write_1__VAL_1, - MUX_wci_reqERR_6$write_1__VAL_1, - MUX_wci_reqERR_7$write_1__VAL_1, - MUX_wci_reqERR_8$write_1__VAL_1, - MUX_wci_reqERR_9$write_1__VAL_1, - MUX_wci_reqFAIL$write_1__VAL_1, - MUX_wci_reqFAIL_1$write_1__VAL_1, - MUX_wci_reqFAIL_10$write_1__VAL_1, - MUX_wci_reqFAIL_11$write_1__VAL_1, - MUX_wci_reqFAIL_12$write_1__VAL_1, - MUX_wci_reqFAIL_13$write_1__VAL_1, - MUX_wci_reqFAIL_14$write_1__VAL_1, - MUX_wci_reqFAIL_2$write_1__VAL_1, - MUX_wci_reqFAIL_3$write_1__VAL_1, - MUX_wci_reqFAIL_4$write_1__VAL_1, - MUX_wci_reqFAIL_5$write_1__VAL_1, - MUX_wci_reqFAIL_6$write_1__VAL_1, - MUX_wci_reqFAIL_7$write_1__VAL_1, - MUX_wci_reqFAIL_8$write_1__VAL_1, - MUX_wci_reqFAIL_9$write_1__VAL_1, - MUX_wci_reqTO$write_1__VAL_1, - MUX_wci_reqTO_1$write_1__VAL_1, - MUX_wci_reqTO_10$write_1__VAL_1, - MUX_wci_reqTO_11$write_1__VAL_1, - MUX_wci_reqTO_12$write_1__VAL_1, - MUX_wci_reqTO_13$write_1__VAL_1, - MUX_wci_reqTO_14$write_1__VAL_1, - MUX_wci_reqTO_2$write_1__VAL_1, - MUX_wci_reqTO_3$write_1__VAL_1, - MUX_wci_reqTO_4$write_1__VAL_1, - MUX_wci_reqTO_5$write_1__VAL_1, - MUX_wci_reqTO_6$write_1__VAL_1, - MUX_wci_reqTO_7$write_1__VAL_1, - MUX_wci_reqTO_8$write_1__VAL_1, - MUX_wci_reqTO_9$write_1__VAL_1; - wire [71 : 0] MUX_wci_reqF_10_q_0$write_1__VAL_2, - MUX_wci_reqF_10_x_wire$wset_1__VAL_1, - MUX_wci_reqF_10_x_wire$wset_1__VAL_2, - MUX_wci_reqF_10_x_wire$wset_1__VAL_3, - MUX_wci_reqF_11_q_0$write_1__VAL_2, - MUX_wci_reqF_11_x_wire$wset_1__VAL_1, - MUX_wci_reqF_11_x_wire$wset_1__VAL_2, - MUX_wci_reqF_12_q_0$write_1__VAL_2, - MUX_wci_reqF_12_x_wire$wset_1__VAL_1, - MUX_wci_reqF_12_x_wire$wset_1__VAL_2, - MUX_wci_reqF_13_q_0$write_1__VAL_2, - MUX_wci_reqF_13_x_wire$wset_1__VAL_1, - MUX_wci_reqF_13_x_wire$wset_1__VAL_2, - MUX_wci_reqF_14_q_0$write_1__VAL_2, - MUX_wci_reqF_14_x_wire$wset_1__VAL_1, - MUX_wci_reqF_14_x_wire$wset_1__VAL_2, - MUX_wci_reqF_1_q_0$write_1__VAL_1, - MUX_wci_reqF_1_x_wire$wset_1__VAL_1, - MUX_wci_reqF_1_x_wire$wset_1__VAL_2, - MUX_wci_reqF_2_q_0$write_1__VAL_2, - MUX_wci_reqF_2_x_wire$wset_1__VAL_1, - MUX_wci_reqF_2_x_wire$wset_1__VAL_2, - MUX_wci_reqF_3_q_0$write_1__VAL_2, - MUX_wci_reqF_3_x_wire$wset_1__VAL_1, - MUX_wci_reqF_3_x_wire$wset_1__VAL_2, - MUX_wci_reqF_4_q_0$write_1__VAL_2, - MUX_wci_reqF_4_x_wire$wset_1__VAL_1, - MUX_wci_reqF_4_x_wire$wset_1__VAL_2, - MUX_wci_reqF_5_q_0$write_1__VAL_2, - MUX_wci_reqF_5_x_wire$wset_1__VAL_1, - MUX_wci_reqF_5_x_wire$wset_1__VAL_2, - MUX_wci_reqF_6_q_0$write_1__VAL_2, - MUX_wci_reqF_6_x_wire$wset_1__VAL_1, - MUX_wci_reqF_6_x_wire$wset_1__VAL_2, - MUX_wci_reqF_7_q_0$write_1__VAL_2, - MUX_wci_reqF_7_x_wire$wset_1__VAL_1, - MUX_wci_reqF_7_x_wire$wset_1__VAL_2, - MUX_wci_reqF_8_q_0$write_1__VAL_2, - MUX_wci_reqF_8_x_wire$wset_1__VAL_1, - MUX_wci_reqF_8_x_wire$wset_1__VAL_2, - MUX_wci_reqF_9_q_0$write_1__VAL_2, - MUX_wci_reqF_9_x_wire$wset_1__VAL_1, - MUX_wci_reqF_9_x_wire$wset_1__VAL_2, - MUX_wci_reqF_q_0$write_1__VAL_1, - MUX_wci_reqF_x_wire$wset_1__VAL_1, - MUX_wci_reqF_x_wire$wset_1__VAL_2; + reg [71 : 0] MUX_wci_0_reqF_q_0$write_1__VAL_2, + MUX_wci_10_reqF_q_0$write_1__VAL_1, + MUX_wci_11_reqF_q_0$write_1__VAL_1, + MUX_wci_12_reqF_q_0$write_1__VAL_1, + MUX_wci_13_reqF_q_0$write_1__VAL_1, + MUX_wci_14_reqF_q_0$write_1__VAL_1, + MUX_wci_1_reqF_q_0$write_1__VAL_2, + MUX_wci_2_reqF_q_0$write_1__VAL_2, + MUX_wci_3_reqF_q_0$write_1__VAL_2, + MUX_wci_4_reqF_q_0$write_1__VAL_2, + MUX_wci_5_reqF_q_0$write_1__VAL_2, + MUX_wci_6_reqF_q_0$write_1__VAL_2, + MUX_wci_7_reqF_q_0$write_1__VAL_2, + MUX_wci_8_reqF_q_0$write_1__VAL_2, + MUX_wci_9_reqF_q_0$write_1__VAL_2; + reg [2 : 0] MUX_wci_0_reqERR$write_1__VAL_1, + MUX_wci_0_reqFAIL$write_1__VAL_1, + MUX_wci_0_reqTO$write_1__VAL_1, + MUX_wci_10_reqERR$write_1__VAL_1, + MUX_wci_10_reqFAIL$write_1__VAL_1, + MUX_wci_10_reqTO$write_1__VAL_1, + MUX_wci_11_reqERR$write_1__VAL_1, + MUX_wci_11_reqFAIL$write_1__VAL_1, + MUX_wci_11_reqTO$write_1__VAL_1, + MUX_wci_12_reqERR$write_1__VAL_1, + MUX_wci_12_reqFAIL$write_1__VAL_1, + MUX_wci_12_reqTO$write_1__VAL_1, + MUX_wci_13_reqERR$write_1__VAL_1, + MUX_wci_13_reqFAIL$write_1__VAL_1, + MUX_wci_13_reqTO$write_1__VAL_1, + MUX_wci_14_reqERR$write_1__VAL_1, + MUX_wci_14_reqFAIL$write_1__VAL_1, + MUX_wci_14_reqTO$write_1__VAL_1, + MUX_wci_1_reqERR$write_1__VAL_1, + MUX_wci_1_reqFAIL$write_1__VAL_1, + MUX_wci_1_reqTO$write_1__VAL_1, + MUX_wci_2_reqERR$write_1__VAL_1, + MUX_wci_2_reqFAIL$write_1__VAL_1, + MUX_wci_2_reqTO$write_1__VAL_1, + MUX_wci_3_reqERR$write_1__VAL_1, + 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MUX_wci_reqF_1_c_r$write_1__VAL_2, - MUX_wci_reqF_1_q_0$write_1__SEL_2, - MUX_wci_reqF_2_c_r$write_1__VAL_1, - MUX_wci_reqF_2_c_r$write_1__VAL_2, - MUX_wci_reqF_2_q_0$write_1__SEL_1, - MUX_wci_reqF_3_c_r$write_1__VAL_1, - MUX_wci_reqF_3_c_r$write_1__VAL_2, - MUX_wci_reqF_3_q_0$write_1__SEL_1, - MUX_wci_reqF_4_c_r$write_1__VAL_1, - MUX_wci_reqF_4_c_r$write_1__VAL_2, - MUX_wci_reqF_4_q_0$write_1__SEL_1, - MUX_wci_reqF_5_c_r$write_1__VAL_1, - MUX_wci_reqF_5_c_r$write_1__VAL_2, - MUX_wci_reqF_5_q_0$write_1__SEL_1, - MUX_wci_reqF_6_c_r$write_1__VAL_1, - MUX_wci_reqF_6_c_r$write_1__VAL_2, - MUX_wci_reqF_6_q_0$write_1__SEL_1, - MUX_wci_reqF_7_c_r$write_1__VAL_1, - MUX_wci_reqF_7_c_r$write_1__VAL_2, - MUX_wci_reqF_7_q_0$write_1__SEL_1, - MUX_wci_reqF_8_c_r$write_1__VAL_1, - MUX_wci_reqF_8_c_r$write_1__VAL_2, - MUX_wci_reqF_8_q_0$write_1__SEL_1, - MUX_wci_reqF_9_c_r$write_1__VAL_1, - MUX_wci_reqF_9_c_r$write_1__VAL_2, - MUX_wci_reqF_9_q_0$write_1__SEL_1, - MUX_wci_reqF_c_r$write_1__VAL_1, - MUX_wci_reqF_c_r$write_1__VAL_2, - MUX_wci_reqF_q_0$write_1__SEL_2, - MUX_wci_reqPend$write_1__SEL_1, - MUX_wci_reqPend_1$write_1__SEL_1, - MUX_wci_reqPend_10$write_1__SEL_1, - MUX_wci_reqPend_11$write_1__SEL_1, - MUX_wci_reqPend_12$write_1__SEL_1, - MUX_wci_reqPend_13$write_1__SEL_1, - MUX_wci_reqPend_14$write_1__SEL_1, - MUX_wci_reqPend_2$write_1__SEL_1, - MUX_wci_reqPend_3$write_1__SEL_1, - MUX_wci_reqPend_4$write_1__SEL_1, - MUX_wci_reqPend_5$write_1__SEL_1, - MUX_wci_reqPend_6$write_1__SEL_1, - MUX_wci_reqPend_7$write_1__SEL_1, - MUX_wci_reqPend_8$write_1__SEL_1, - MUX_wci_reqPend_9$write_1__SEL_1, - MUX_wci_reqTO$write_1__SEL_1, - MUX_wci_reqTO_1$write_1__SEL_1, - MUX_wci_reqTO_10$write_1__SEL_1, - MUX_wci_reqTO_11$write_1__SEL_1, - MUX_wci_reqTO_12$write_1__SEL_1, - MUX_wci_reqTO_13$write_1__SEL_1, - MUX_wci_reqTO_14$write_1__SEL_1, - MUX_wci_reqTO_2$write_1__SEL_1, - MUX_wci_reqTO_3$write_1__SEL_1, - MUX_wci_reqTO_4$write_1__SEL_1, - MUX_wci_reqTO_5$write_1__SEL_1, - MUX_wci_reqTO_6$write_1__SEL_1, - MUX_wci_reqTO_7$write_1__SEL_1, - MUX_wci_reqTO_8$write_1__SEL_1, - MUX_wci_reqTO_9$write_1__SEL_1, - MUX_wci_respF$enq_1__SEL_6, - MUX_wci_respF$enq_1__SEL_7, - MUX_wci_respF_1$enq_1__SEL_6, - MUX_wci_respF_1$enq_1__SEL_7, - MUX_wci_respF_10$enq_1__SEL_6, - MUX_wci_respF_10$enq_1__SEL_7, - MUX_wci_respF_11$enq_1__SEL_6, - MUX_wci_respF_11$enq_1__SEL_7, - MUX_wci_respF_12$enq_1__SEL_6, - MUX_wci_respF_12$enq_1__SEL_7, - MUX_wci_respF_13$enq_1__SEL_6, - MUX_wci_respF_13$enq_1__SEL_7, - MUX_wci_respF_14$enq_1__SEL_6, - MUX_wci_respF_14$enq_1__SEL_7, - MUX_wci_respF_2$enq_1__SEL_6, - MUX_wci_respF_2$enq_1__SEL_7, - MUX_wci_respF_3$enq_1__SEL_6, - MUX_wci_respF_3$enq_1__SEL_7, - MUX_wci_respF_4$enq_1__SEL_6, - MUX_wci_respF_4$enq_1__SEL_7, - MUX_wci_respF_5$enq_1__SEL_6, - MUX_wci_respF_5$enq_1__SEL_7, - MUX_wci_respF_6$enq_1__SEL_6, - MUX_wci_respF_6$enq_1__SEL_7, - MUX_wci_respF_7$enq_1__SEL_6, - MUX_wci_respF_7$enq_1__SEL_7, - MUX_wci_respF_8$enq_1__SEL_6, - MUX_wci_respF_8$enq_1__SEL_7, - MUX_wci_respF_9$enq_1__SEL_6, - MUX_wci_respF_9$enq_1__SEL_7, + MUX_wci_0_respTimr$write_1__VAL_2, + MUX_wci_10_respTimr$write_1__VAL_2, + MUX_wci_11_respTimr$write_1__VAL_2, + MUX_wci_12_respTimr$write_1__VAL_2, + MUX_wci_13_respTimr$write_1__VAL_2, + MUX_wci_14_respTimr$write_1__VAL_2, + MUX_wci_1_respTimr$write_1__VAL_2, + MUX_wci_2_respTimr$write_1__VAL_2, + MUX_wci_3_respTimr$write_1__VAL_2, + MUX_wci_4_respTimr$write_1__VAL_2, + MUX_wci_5_respTimr$write_1__VAL_2, + MUX_wci_6_respTimr$write_1__VAL_2, + MUX_wci_7_respTimr$write_1__VAL_2, + MUX_wci_8_respTimr$write_1__VAL_2, + MUX_wci_9_respTimr$write_1__VAL_2; + wire MUX_wci_0_busy$write_1__SEL_1, + MUX_wci_0_busy$write_1__SEL_2, + MUX_wci_0_reqERR$write_1__SEL_1, + MUX_wci_0_reqFAIL$write_1__SEL_1, + MUX_wci_0_reqF_cntr_r$write_1__VAL_1, + MUX_wci_0_reqF_cntr_r$write_1__VAL_2, + MUX_wci_0_reqF_q_0$write_1__SEL_2, + MUX_wci_0_reqPend$write_1__SEL_1, + MUX_wci_0_reqTO$write_1__SEL_1, + MUX_wci_0_respF$enq_1__SEL_6, + MUX_wci_0_respF$enq_1__SEL_7, + MUX_wci_10_busy$write_1__SEL_1, + MUX_wci_10_busy$write_1__SEL_2, + MUX_wci_10_reqERR$write_1__SEL_1, + MUX_wci_10_reqFAIL$write_1__SEL_1, + MUX_wci_10_reqF_cntr_r$write_1__VAL_1, + MUX_wci_10_reqF_cntr_r$write_1__VAL_2, + MUX_wci_10_reqF_q_0$write_1__SEL_1, + MUX_wci_10_reqPend$write_1__SEL_1, + MUX_wci_10_reqTO$write_1__SEL_1, + MUX_wci_10_respF$enq_1__SEL_6, + MUX_wci_10_respF$enq_1__SEL_7, + MUX_wci_11_busy$write_1__SEL_1, + MUX_wci_11_busy$write_1__SEL_2, + MUX_wci_11_reqERR$write_1__SEL_1, + MUX_wci_11_reqFAIL$write_1__SEL_1, + MUX_wci_11_reqF_cntr_r$write_1__VAL_1, + MUX_wci_11_reqF_cntr_r$write_1__VAL_2, + MUX_wci_11_reqF_q_0$write_1__SEL_1, + MUX_wci_11_reqPend$write_1__SEL_1, + MUX_wci_11_reqTO$write_1__SEL_1, + MUX_wci_11_respF$enq_1__SEL_6, + MUX_wci_11_respF$enq_1__SEL_7, + MUX_wci_12_busy$write_1__SEL_1, + MUX_wci_12_busy$write_1__SEL_2, + MUX_wci_12_reqERR$write_1__SEL_1, + MUX_wci_12_reqFAIL$write_1__SEL_1, + MUX_wci_12_reqF_cntr_r$write_1__VAL_1, + MUX_wci_12_reqF_cntr_r$write_1__VAL_2, + MUX_wci_12_reqF_q_0$write_1__SEL_1, + MUX_wci_12_reqPend$write_1__SEL_1, + MUX_wci_12_reqTO$write_1__SEL_1, + MUX_wci_12_respF$enq_1__SEL_6, + MUX_wci_12_respF$enq_1__SEL_7, + MUX_wci_13_busy$write_1__SEL_1, + MUX_wci_13_busy$write_1__SEL_2, + MUX_wci_13_reqERR$write_1__SEL_1, + MUX_wci_13_reqFAIL$write_1__SEL_1, + MUX_wci_13_reqF_cntr_r$write_1__VAL_1, + MUX_wci_13_reqF_cntr_r$write_1__VAL_2, + MUX_wci_13_reqF_q_0$write_1__SEL_1, + MUX_wci_13_reqPend$write_1__SEL_1, + MUX_wci_13_reqTO$write_1__SEL_1, + MUX_wci_13_respF$enq_1__SEL_6, + MUX_wci_13_respF$enq_1__SEL_7, + MUX_wci_14_busy$write_1__SEL_1, + MUX_wci_14_busy$write_1__SEL_2, + MUX_wci_14_reqERR$write_1__SEL_1, + MUX_wci_14_reqFAIL$write_1__SEL_1, + MUX_wci_14_reqF_cntr_r$write_1__VAL_1, + MUX_wci_14_reqF_cntr_r$write_1__VAL_2, + MUX_wci_14_reqF_q_0$write_1__SEL_1, + MUX_wci_14_reqPend$write_1__SEL_1, + MUX_wci_14_reqTO$write_1__SEL_1, + MUX_wci_14_respF$enq_1__SEL_6, + MUX_wci_14_respF$enq_1__SEL_7, + MUX_wci_1_busy$write_1__SEL_1, + MUX_wci_1_busy$write_1__SEL_2, + MUX_wci_1_reqERR$write_1__SEL_1, + MUX_wci_1_reqFAIL$write_1__SEL_1, + MUX_wci_1_reqF_cntr_r$write_1__VAL_1, + MUX_wci_1_reqF_cntr_r$write_1__VAL_2, + MUX_wci_1_reqF_q_0$write_1__SEL_2, + MUX_wci_1_reqPend$write_1__SEL_1, + MUX_wci_1_reqTO$write_1__SEL_1, + MUX_wci_1_respF$enq_1__SEL_6, + MUX_wci_1_respF$enq_1__SEL_7, + MUX_wci_2_busy$write_1__SEL_1, + MUX_wci_2_busy$write_1__SEL_2, + MUX_wci_2_reqERR$write_1__SEL_1, + MUX_wci_2_reqFAIL$write_1__SEL_1, + MUX_wci_2_reqF_cntr_r$write_1__VAL_1, + MUX_wci_2_reqF_cntr_r$write_1__VAL_2, + MUX_wci_2_reqF_q_0$write_1__SEL_2, + MUX_wci_2_reqPend$write_1__SEL_1, + MUX_wci_2_reqTO$write_1__SEL_1, + MUX_wci_2_respF$enq_1__SEL_6, + MUX_wci_2_respF$enq_1__SEL_7, + MUX_wci_3_busy$write_1__SEL_1, + MUX_wci_3_busy$write_1__SEL_2, + MUX_wci_3_reqERR$write_1__SEL_1, + MUX_wci_3_reqFAIL$write_1__SEL_1, + MUX_wci_3_reqF_cntr_r$write_1__VAL_1, + MUX_wci_3_reqF_cntr_r$write_1__VAL_2, + MUX_wci_3_reqF_q_0$write_1__SEL_2, + MUX_wci_3_reqPend$write_1__SEL_1, + MUX_wci_3_reqTO$write_1__SEL_1, + MUX_wci_3_respF$enq_1__SEL_6, + MUX_wci_3_respF$enq_1__SEL_7, + MUX_wci_4_busy$write_1__SEL_1, + MUX_wci_4_busy$write_1__SEL_2, + MUX_wci_4_reqERR$write_1__SEL_1, + MUX_wci_4_reqFAIL$write_1__SEL_1, + MUX_wci_4_reqF_cntr_r$write_1__VAL_1, + MUX_wci_4_reqF_cntr_r$write_1__VAL_2, + MUX_wci_4_reqF_q_0$write_1__SEL_2, + MUX_wci_4_reqPend$write_1__SEL_1, + MUX_wci_4_reqTO$write_1__SEL_1, + MUX_wci_4_respF$enq_1__SEL_6, + MUX_wci_4_respF$enq_1__SEL_7, + MUX_wci_5_busy$write_1__SEL_1, + MUX_wci_5_busy$write_1__SEL_2, + MUX_wci_5_reqERR$write_1__SEL_1, + MUX_wci_5_reqFAIL$write_1__SEL_1, + MUX_wci_5_reqF_cntr_r$write_1__VAL_1, + MUX_wci_5_reqF_cntr_r$write_1__VAL_2, + MUX_wci_5_reqF_q_0$write_1__SEL_2, + MUX_wci_5_reqPend$write_1__SEL_1, + MUX_wci_5_reqTO$write_1__SEL_1, + MUX_wci_5_respF$enq_1__SEL_6, + MUX_wci_5_respF$enq_1__SEL_7, + MUX_wci_6_busy$write_1__SEL_1, + MUX_wci_6_busy$write_1__SEL_2, + MUX_wci_6_reqERR$write_1__SEL_1, + MUX_wci_6_reqFAIL$write_1__SEL_1, + MUX_wci_6_reqF_cntr_r$write_1__VAL_1, + MUX_wci_6_reqF_cntr_r$write_1__VAL_2, + MUX_wci_6_reqF_q_0$write_1__SEL_2, + MUX_wci_6_reqPend$write_1__SEL_1, + MUX_wci_6_reqTO$write_1__SEL_1, + MUX_wci_6_respF$enq_1__SEL_6, + MUX_wci_6_respF$enq_1__SEL_7, + MUX_wci_7_busy$write_1__SEL_1, + MUX_wci_7_busy$write_1__SEL_2, + MUX_wci_7_reqERR$write_1__SEL_1, + MUX_wci_7_reqFAIL$write_1__SEL_1, + MUX_wci_7_reqF_cntr_r$write_1__VAL_1, + MUX_wci_7_reqF_cntr_r$write_1__VAL_2, + MUX_wci_7_reqF_q_0$write_1__SEL_2, + MUX_wci_7_reqPend$write_1__SEL_1, + MUX_wci_7_reqTO$write_1__SEL_1, + MUX_wci_7_respF$enq_1__SEL_6, + MUX_wci_7_respF$enq_1__SEL_7, + MUX_wci_8_busy$write_1__SEL_1, + MUX_wci_8_busy$write_1__SEL_2, + MUX_wci_8_reqERR$write_1__SEL_1, + MUX_wci_8_reqFAIL$write_1__SEL_1, + MUX_wci_8_reqF_cntr_r$write_1__VAL_1, + MUX_wci_8_reqF_cntr_r$write_1__VAL_2, + MUX_wci_8_reqF_q_0$write_1__SEL_2, + MUX_wci_8_reqPend$write_1__SEL_1, + MUX_wci_8_reqTO$write_1__SEL_1, + MUX_wci_8_respF$enq_1__SEL_6, + MUX_wci_8_respF$enq_1__SEL_7, + MUX_wci_9_busy$write_1__SEL_1, + MUX_wci_9_busy$write_1__SEL_2, + MUX_wci_9_reqERR$write_1__SEL_1, + MUX_wci_9_reqFAIL$write_1__SEL_1, + MUX_wci_9_reqF_cntr_r$write_1__VAL_1, + MUX_wci_9_reqF_cntr_r$write_1__VAL_2, + MUX_wci_9_reqF_q_0$write_1__SEL_2, + MUX_wci_9_reqPend$write_1__SEL_1, + MUX_wci_9_reqTO$write_1__SEL_1, + MUX_wci_9_respF$enq_1__SEL_6, + MUX_wci_9_respF$enq_1__SEL_7, MUX_wrkAct$write_1__SEL_1, MUX_wrkAct$write_1__SEL_2, MUX_wrkAct$write_1__SEL_3; // remaining internal signals - reg [63 : 0] v__h105179, - v__h105232, - v__h11118, - v__h11208, - v__h11297, - v__h11521, - v__h11611, - v__h11700, - v__h11929, - v__h12019, - v__h12108, - v__h15558, - v__h15648, - v__h15737, - v__h15961, - v__h16051, - v__h16140, - v__h16369, - v__h16459, - v__h16548, - v__h19998, - v__h20088, - v__h20177, - v__h20401, - v__h20491, - v__h20580, - v__h20809, - v__h20899, - v__h20988, - v__h24438, - v__h24528, - v__h24617, - v__h24841, - v__h24931, - v__h25020, - v__h25249, - v__h25339, - v__h25428, - v__h28878, - v__h28968, - v__h29057, - v__h29281, - v__h29371, - v__h29460, - v__h29689, - v__h29779, - v__h29868, - v__h33318, - v__h33408, - v__h33497, - v__h33721, - v__h33811, - v__h33900, - v__h34129, - v__h34219, - v__h34308, - v__h37758, - v__h37848, - v__h37937, - v__h38161, - v__h38251, - v__h38340, - v__h38569, - v__h38659, - v__h38748, - v__h42198, - v__h42288, - v__h42377, - v__h42601, - v__h42691, - v__h42780, - v__h43009, - v__h43099, - v__h43188, - v__h46638, - v__h46728, - v__h46817, - v__h47041, - v__h47131, - v__h47220, - v__h47449, - v__h47539, - v__h47628, - v__h51078, - v__h51168, - v__h51257, - v__h51481, - v__h51571, - v__h51660, - v__h51889, - v__h51979, - v__h52068, - v__h55518, - v__h55608, - v__h55697, - v__h55921, - v__h56011, - v__h56100, - v__h56329, - v__h56419, - v__h56508, - v__h59958, - v__h60048, - v__h60137, - v__h60361, - v__h60451, - v__h60540, - v__h60769, - v__h60859, - v__h60948, - v__h64398, - v__h64488, - v__h64577, - v__h64801, - v__h64891, - v__h64980, - v__h65209, - v__h65299, - v__h65388, - v__h68838, - v__h68928, - v__h69017, - v__h69241, - v__h69331, - v__h69420, - v__h69649, - v__h69739, - v__h69828, - v__h73278, - v__h73368, - v__h73457, - v__h73681, - v__h73771, - v__h73860, - v__h74089, - v__h74179, - v__h74268, - v__h78563, - v__h79155, - v__h79264, - v__h79843, - v__h79952, - v__h80531, - v__h80640, - v__h81219, - v__h81328, - v__h81907, - v__h82016, - v__h82595, - v__h82704, - v__h83283, - v__h83392, - v__h83971, - v__h84080, - v__h84659, - v__h84768, - v__h85347, - v__h85456, - v__h86035, - v__h86144, - v__h86723, - v__h86832, - v__h87411, - v__h87520, - v__h88099, - v__h88208, - v__h88787, - v__h96191, - v__h96263, - v__h96335, - v__h96407, - v__h96479, - v__h96551, - v__h96623, - v__h96695, - v__h96767, - v__h96839, - v__h96911, - v__h96983, - v__h97055, - v__h97127, - v__h97199; - reg [31 : 0] CASE_cpReq_BITS_9_TO_6_uuid_arg_BITS_31_TO_0_0_ETC__q3, - IF_cpReq_337_BITS_11_TO_4_340_EQ_0x0_419_THEN__ETC___d6152, - IF_cpReq_337_BITS_11_TO_4_340_EQ_0x30_569_THEN_ETC___d6151, - rtnData__h112395; - reg IF_wrkAct_051_EQ_0_052_THEN_wci_respF_i_notEmp_ETC___d6101; + reg [63 : 0] v__h104109, + v__h104162, + v__h11985, + v__h12075, + v__h12164, + v__h12388, + v__h12478, + v__h12567, + v__h12796, + v__h12886, + v__h12975, + v__h16354, + v__h16444, + v__h16533, + v__h16757, + v__h16847, + v__h16936, + v__h17165, + v__h17255, + v__h17344, + v__h20723, + v__h20813, + v__h20902, + v__h21126, + v__h21216, + v__h21305, + v__h21534, + v__h21624, + v__h21713, + v__h25092, + v__h25182, + v__h25271, + v__h25495, + v__h25585, + v__h25674, + v__h25903, + v__h25993, + v__h26082, + v__h29461, + v__h29551, + v__h29640, + v__h29864, + v__h29954, + v__h30043, + v__h30272, + v__h30362, + v__h30451, + v__h33830, + v__h33920, + v__h34009, + v__h34233, + v__h34323, + v__h34412, + v__h34641, + v__h34731, + v__h34820, + v__h38199, + v__h38289, + v__h38378, + v__h38602, + v__h38692, + v__h38781, + v__h39010, + v__h39100, + v__h39189, + v__h42568, + v__h42658, + v__h42747, + v__h42971, + v__h43061, + v__h43150, + v__h43379, + v__h43469, + v__h43558, + v__h46937, + v__h47027, + v__h47116, + v__h47340, + v__h47430, + v__h47519, + v__h47748, + v__h47838, + v__h47927, + v__h51306, + v__h51396, + v__h51485, + v__h51709, + v__h51799, + v__h51888, + v__h52117, + v__h52207, + v__h52296, + v__h55675, + v__h55765, + v__h55854, + v__h56078, + v__h56168, + v__h56257, + v__h56486, + v__h56576, + v__h56665, + v__h60044, + v__h60134, + v__h60223, + v__h60447, + v__h60537, + v__h60626, + v__h60855, + v__h60945, + v__h61034, + v__h64413, + v__h64503, + v__h64592, + v__h64816, + v__h64906, + v__h64995, + v__h65224, + v__h65314, + v__h65403, + v__h68782, + v__h68872, + v__h68961, + v__h69185, + v__h69275, + v__h69364, + v__h69593, + v__h69683, + v__h69772, + v__h73151, + v__h73241, + v__h73330, + v__h73554, + v__h73644, + v__h73733, + v__h73962, + v__h74052, + v__h74141, + v__h78104, + v__h78692, + v__h78800, + v__h79379, + v__h79487, + v__h80066, + v__h80174, + v__h80753, + v__h80861, + v__h81440, + v__h81548, + v__h82127, + v__h82235, + v__h82814, + v__h82922, + v__h83501, + v__h83609, + v__h84188, + v__h84296, + v__h84875, + v__h84983, + v__h85562, + v__h85670, + v__h86249, + v__h86357, + v__h86936, + v__h87044, + v__h87623, + v__h87731, + v__h88310, + v__h95208, + v__h95279, + v__h95350, + v__h95421, + v__h95492, + v__h95563, + v__h95634, + v__h95705, + v__h95776, + v__h95847, + v__h95918, + v__h95989, + v__h96060, + v__h96131, + v__h96202; + reg [31 : 0] CASE_cpReq_BITS_9_TO_6_0_uuid_arg_BITS_511_TO__ETC__q3, + IF_cpReq_363_BITS_11_TO_4_366_EQ_0x0_445_THEN__ETC___d2590, + IF_cpReq_363_BITS_11_TO_4_366_EQ_0x30_595_THEN_ETC___d2691, + rtnData__h110501; + reg CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3681, + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3694, + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3735, + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3750, + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793, + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3851, + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3863, + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3876, + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3886, + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3928, + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3940, + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3951, + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3961, + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4003, + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4015, + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4026, + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4036, + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4078, + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4090, + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4101, + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4111, + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4153, + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4165, + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4176, + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4186, + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4228, + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4240, + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4251, + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4261, + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4303, + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4315, + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4326, + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4336, + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4378, + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4390, + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4401, + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4411, + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4453, + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4465, + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4476, + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4486, + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4528, + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4540, + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4551, + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4561, + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4603, + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4615, + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4626, + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4636, + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4678, + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4690, + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4701, + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4711, + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4753, + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4765, + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4776, + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4786, + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4828, + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4840, + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4851, + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4861, + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d5021, + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d2943, + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d2961, + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d2986, + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3049, + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3060, + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3085, + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3096, + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3121, + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3132, + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3157, + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3168, + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3193, + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3204, + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3229, + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3240, + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3265, + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3276, + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3301, + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3312, + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3337, + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3348, + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3373, + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3384, + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3409, + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3420, + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3445, + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3456, + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3481, + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3492, + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3517, + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3528, + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3639, + CASE_wrkAct_028_0_wci_0_respF_i_notEmpty__029__ETC___d5044; + wire [63 : 0] x_wget__h5213; wire [49 : 0] _281474976710656_MINUS_timeServ_delSecond__q1, - x__h3700, - x__h4421, - x__h4649; - wire [47 : 0] x_f__h4848; - wire [32 : 0] IF_adminResp2F_notEmpty__278_THEN_adminResp2F__ETC___d2316; - wire [31 : 0] cpStatus__h74993, - crr_data__h75663, - toCount__h10825, - toCount__h15271, - toCount__h19711, - toCount__h24151, - toCount__h28591, - toCount__h33031, - toCount__h37471, - toCount__h41911, - toCount__h46351, - toCount__h50791, - toCount__h55231, - toCount__h59671, - toCount__h64111, - toCount__h68551, - toCount__h72991, - wciAddr__h77388, - wciAddr__h77456, - wciAddr__h77522, - wciAddr__h77588, - wciAddr__h77654, - wciAddr__h77720, - wciAddr__h77786, - wciAddr__h77852, - wciAddr__h77918, - wciAddr__h77984, - wciAddr__h78050, - wciAddr__h78116, - wciAddr__h78182, - wciAddr__h78248, - wciAddr__h78314, - x__h10985, - x__h15428, - x__h19868, - x__h24308, - x__h28748, - x__h33188, - x__h37628, - x__h42068, - x__h46508, - x__h4715, - x__h50948, - x__h55388, - x__h59828, - x__h64268, - x__h68708, - x__h73148, - x_addr__h97612, - x_data__h103818, - x_data__h103824, - x_data__h103871, - x_data__h103877, - x_data__h103924, - x_data__h103930, - x_data__h103977, - x_data__h103983, - x_data__h104030, - x_data__h104036, - x_data__h104083, - x_data__h104089, - x_data__h104136, - x_data__h104142, - x_data__h104189, - x_data__h104195, - x_data__h104242, - x_data__h104248, - x_data__h104295, - x_data__h104301, - x_data__h104348, - x_data__h104354, - x_data__h104401, - x_data__h104407, - x_data__h104454, - x_data__h104460, - x_data__h104507, - x_data__h104513, - x_data__h104560, - x_data__h104566; - wire [26 : 0] IF_wci_lastControlOp_10_687_BIT_3_688_THEN_wci_ETC___d1702, - IF_wci_lastControlOp_11_827_BIT_3_828_THEN_wci_ETC___d1842, - IF_wci_lastControlOp_12_967_BIT_3_968_THEN_wci_ETC___d1982, - IF_wci_lastControlOp_13_107_BIT_3_108_THEN_wci_ETC___d2122, - IF_wci_lastControlOp_14_247_BIT_3_248_THEN_wci_ETC___d2262, - IF_wci_lastControlOp_1_27_BIT_3_28_THEN_wci_la_ETC___d442, - IF_wci_lastControlOp_2_67_BIT_3_68_THEN_wci_la_ETC___d582, - IF_wci_lastControlOp_3_07_BIT_3_08_THEN_wci_la_ETC___d722, - IF_wci_lastControlOp_4_47_BIT_3_48_THEN_wci_la_ETC___d862, - IF_wci_lastControlOp_5_87_BIT_3_88_THEN_wci_la_ETC___d1002, - IF_wci_lastControlOp_6_127_BIT_3_128_THEN_wci__ETC___d1142, - IF_wci_lastControlOp_7_267_BIT_3_268_THEN_wci__ETC___d1282, - IF_wci_lastControlOp_87_BIT_3_88_THEN_wci_last_ETC___d302, - IF_wci_lastControlOp_8_407_BIT_3_408_THEN_wci__ETC___d1422, - IF_wci_lastControlOp_9_547_BIT_3_548_THEN_wci__ETC___d1562; - wire [23 : 0] bAddr__h112904, bAddr__h113364; + x__h3688, + x__h4408, + x__h4636; + wire [47 : 0] x_f__h4835; + wire [32 : 0] IF_adminResp2F_notEmpty__304_THEN_adminResp2F__ETC___d2342; + wire [31 : 0] cpStatus__h74863, + crr_data__h75533, + toCount__h11692, + toCount__h16067, + toCount__h20436, + toCount__h24805, + toCount__h29174, + toCount__h33543, + toCount__h37912, + toCount__h42281, + toCount__h46650, + toCount__h51019, + toCount__h55388, + toCount__h59757, + toCount__h64126, + toCount__h68495, + toCount__h72864, + wciAddr__h77037, + wciAddr__h77105, + wciAddr__h77173, + wciAddr__h77241, + wciAddr__h77309, + wciAddr__h77377, + wciAddr__h77445, + wciAddr__h77513, + wciAddr__h77581, + wciAddr__h77649, + wciAddr__h77717, + wciAddr__h77785, + wciAddr__h77853, + wciAddr__h77921, + wciAddr__h77989, + x__h11852, + x__h16224, + x__h20593, + x__h24962, + x__h29331, + x__h33700, + x__h38069, + x__h42438, + x__h46807, + x__h4702, + x__h51176, + x__h55545, + x__h59914, + x__h64283, + x__h68652, + x__h73021, + x_addr__h96606, + x_data__h102795, + x_data__h102801, + x_data__h102846, + x_data__h102852, + x_data__h102897, + x_data__h102903, + x_data__h102948, + x_data__h102954, + x_data__h102999, + x_data__h103005, + x_data__h103050, + x_data__h103056, + x_data__h103101, + x_data__h103107, + x_data__h103152, + x_data__h103158, + x_data__h103203, + x_data__h103209, + x_data__h103254, + x_data__h103260, + x_data__h103305, + x_data__h103311, + x_data__h103356, + x_data__h103362, + x_data__h103407, + x_data__h103413, + x_data__h103458, + x_data__h103464, + x_data__h103509, + x_data__h103515; + wire [26 : 0] IF_wci_0_lastControlOp_13_BIT_3_14_THEN_wci_0__ETC___d328, + IF_wci_10_lastControlOp_713_BIT_3_714_THEN_wci_ETC___d1728, + IF_wci_11_lastControlOp_853_BIT_3_854_THEN_wci_ETC___d1868, + IF_wci_12_lastControlOp_993_BIT_3_994_THEN_wci_ETC___d2008, + IF_wci_13_lastControlOp_133_BIT_3_134_THEN_wci_ETC___d2148, + IF_wci_14_lastControlOp_273_BIT_3_274_THEN_wci_ETC___d2288, + IF_wci_1_lastControlOp_53_BIT_3_54_THEN_wci_1__ETC___d468, + IF_wci_2_lastControlOp_93_BIT_3_94_THEN_wci_2__ETC___d608, + IF_wci_3_lastControlOp_33_BIT_3_34_THEN_wci_3__ETC___d748, + IF_wci_4_lastControlOp_73_BIT_3_74_THEN_wci_4__ETC___d888, + IF_wci_5_lastControlOp_013_BIT_3_014_THEN_wci__ETC___d1028, + IF_wci_6_lastControlOp_153_BIT_3_154_THEN_wci__ETC___d1168, + IF_wci_7_lastControlOp_293_BIT_3_294_THEN_wci__ETC___d1308, + IF_wci_8_lastControlOp_433_BIT_3_434_THEN_wci__ETC___d1448, + IF_wci_9_lastControlOp_573_BIT_3_574_THEN_wci__ETC___d1588; + wire [23 : 0] bAddr__h110990, bAddr__h111449; wire [21 : 0] _281474976710656_MINUS_timeServ_delSecond_BITS__ETC__q2; - wire [14 : 0] x__h105402, x__h105951; - wire [4 : 0] x__h97614; - wire [3 : 0] _theResult_____1__h75857, - _theResult_____1__h75875, - wn___1__h76646, - wn__h75856; + wire [14 : 0] x__h104311, x__h104860; + wire [4 : 0] x__h96608; + wire [3 : 0] _theResult_____1__h75724, + _theResult_____1__h75739, + wn___1__h76499, + wn__h75723; wire [2 : 0] rom_serverAdapter_cnt_29_PLUS_IF_rom_serverAda_ETC___d135; - wire IF_cpReq_337_BITS_37_TO_36_861_EQ_2_862_THEN_c_ETC___d3906, - IF_cpReq_337_BITS_37_TO_36_861_EQ_2_862_THEN_c_ETC___d3915, - IF_cpReq_337_BITS_37_TO_36_861_EQ_2_862_THEN_c_ETC___d3925, - IF_cpReq_337_BITS_37_TO_36_861_EQ_2_862_THEN_c_ETC___d3984, - IF_cpReq_337_BITS_37_TO_36_861_EQ_2_862_THEN_c_ETC___d3993, - IF_cpReq_337_BITS_37_TO_36_861_EQ_2_862_THEN_c_ETC___d4003, - IF_cpReq_337_BITS_37_TO_36_861_EQ_2_862_THEN_c_ETC___d4060, - IF_cpReq_337_BITS_37_TO_36_861_EQ_2_862_THEN_c_ETC___d4069, - IF_cpReq_337_BITS_37_TO_36_861_EQ_2_862_THEN_c_ETC___d4079, - IF_cpReq_337_BITS_37_TO_36_861_EQ_2_862_THEN_c_ETC___d4136, - IF_cpReq_337_BITS_37_TO_36_861_EQ_2_862_THEN_c_ETC___d4145, - IF_cpReq_337_BITS_37_TO_36_861_EQ_2_862_THEN_c_ETC___d4155, - IF_cpReq_337_BITS_37_TO_36_861_EQ_2_862_THEN_c_ETC___d4212, - IF_cpReq_337_BITS_37_TO_36_861_EQ_2_862_THEN_c_ETC___d4221, - IF_cpReq_337_BITS_37_TO_36_861_EQ_2_862_THEN_c_ETC___d4231, - IF_cpReq_337_BITS_37_TO_36_861_EQ_2_862_THEN_c_ETC___d4288, - IF_cpReq_337_BITS_37_TO_36_861_EQ_2_862_THEN_c_ETC___d4297, - IF_cpReq_337_BITS_37_TO_36_861_EQ_2_862_THEN_c_ETC___d4307, - IF_cpReq_337_BITS_37_TO_36_861_EQ_2_862_THEN_c_ETC___d4364, - IF_cpReq_337_BITS_37_TO_36_861_EQ_2_862_THEN_c_ETC___d4373, - IF_cpReq_337_BITS_37_TO_36_861_EQ_2_862_THEN_c_ETC___d4383, - IF_cpReq_337_BITS_37_TO_36_861_EQ_2_862_THEN_c_ETC___d4440, - IF_cpReq_337_BITS_37_TO_36_861_EQ_2_862_THEN_c_ETC___d4449, - IF_cpReq_337_BITS_37_TO_36_861_EQ_2_862_THEN_c_ETC___d4459, - IF_cpReq_337_BITS_37_TO_36_861_EQ_2_862_THEN_c_ETC___d4516, - IF_cpReq_337_BITS_37_TO_36_861_EQ_2_862_THEN_c_ETC___d4525, - IF_cpReq_337_BITS_37_TO_36_861_EQ_2_862_THEN_c_ETC___d4535, - IF_cpReq_337_BITS_37_TO_36_861_EQ_2_862_THEN_c_ETC___d4592, - IF_cpReq_337_BITS_37_TO_36_861_EQ_2_862_THEN_c_ETC___d4601, - IF_cpReq_337_BITS_37_TO_36_861_EQ_2_862_THEN_c_ETC___d4611, - IF_cpReq_337_BITS_37_TO_36_861_EQ_2_862_THEN_c_ETC___d4668, - IF_cpReq_337_BITS_37_TO_36_861_EQ_2_862_THEN_c_ETC___d4677, - IF_cpReq_337_BITS_37_TO_36_861_EQ_2_862_THEN_c_ETC___d4687, - IF_cpReq_337_BITS_37_TO_36_861_EQ_2_862_THEN_c_ETC___d4744, - IF_cpReq_337_BITS_37_TO_36_861_EQ_2_862_THEN_c_ETC___d4753, - IF_cpReq_337_BITS_37_TO_36_861_EQ_2_862_THEN_c_ETC___d4763, - IF_cpReq_337_BITS_37_TO_36_861_EQ_2_862_THEN_c_ETC___d4820, - IF_cpReq_337_BITS_37_TO_36_861_EQ_2_862_THEN_c_ETC___d4829, - IF_cpReq_337_BITS_37_TO_36_861_EQ_2_862_THEN_c_ETC___d4839, - IF_cpReq_337_BITS_37_TO_36_861_EQ_2_862_THEN_c_ETC___d4896, - IF_cpReq_337_BITS_37_TO_36_861_EQ_2_862_THEN_c_ETC___d4905, - IF_cpReq_337_BITS_37_TO_36_861_EQ_2_862_THEN_c_ETC___d4915, - IF_cpReq_337_BITS_37_TO_36_861_EQ_2_862_THEN_c_ETC___d4972, - IF_cpReq_337_BITS_37_TO_36_861_EQ_2_862_THEN_c_ETC___d4981, - IF_cpReq_337_BITS_37_TO_36_861_EQ_2_862_THEN_c_ETC___d4991, - IF_timeServ_ppsOK_7_THEN_timeServ_ppsExtSync_d_ETC___d6035, - NOT_cpReq_337_BITS_11_TO_4_340_EQ_0x30_569_623_ETC___d2686, - NOT_cpReq_337_BITS_64_TO_62_338_EQ_0_855_860_A_ETC___d5047, - NOT_cpReq_337_BITS_64_TO_62_338_EQ_3_851_859_A_ETC___d3950, - NOT_cpReq_337_BITS_64_TO_62_338_EQ_3_851_859_A_ETC___d4026, - NOT_cpReq_337_BITS_64_TO_62_338_EQ_3_851_859_A_ETC___d4102, - NOT_cpReq_337_BITS_64_TO_62_338_EQ_3_851_859_A_ETC___d4178, - NOT_cpReq_337_BITS_64_TO_62_338_EQ_3_851_859_A_ETC___d4254, - NOT_cpReq_337_BITS_64_TO_62_338_EQ_3_851_859_A_ETC___d4330, - NOT_cpReq_337_BITS_64_TO_62_338_EQ_3_851_859_A_ETC___d4406, - NOT_cpReq_337_BITS_64_TO_62_338_EQ_3_851_859_A_ETC___d4482, - NOT_cpReq_337_BITS_64_TO_62_338_EQ_3_851_859_A_ETC___d4558, - NOT_cpReq_337_BITS_64_TO_62_338_EQ_3_851_859_A_ETC___d4634, - NOT_cpReq_337_BITS_64_TO_62_338_EQ_3_851_859_A_ETC___d4710, - NOT_cpReq_337_BITS_64_TO_62_338_EQ_3_851_859_A_ETC___d4786, - NOT_cpReq_337_BITS_64_TO_62_338_EQ_3_851_859_A_ETC___d4862, - NOT_cpReq_337_BITS_64_TO_62_338_EQ_3_851_859_A_ETC___d4938, - NOT_cpReq_337_BITS_64_TO_62_338_EQ_3_851_859_A_ETC___d5014, - NOT_cpReq_337_BITS_9_TO_6_770_EQ_0xC_809_935_A_ETC___d2936, - NOT_cpReq_337_BITS_9_TO_6_770_EQ_0xC_809_935_A_ETC___d2999, - NOT_cpReq_337_BITS_9_TO_6_770_EQ_0xC_809_935_A_ETC___d3062, - NOT_cpReq_337_BITS_9_TO_6_770_EQ_0xC_809_935_A_ETC___d3125, - NOT_cpReq_337_BITS_9_TO_6_770_EQ_0xC_809_935_A_ETC___d3188, - NOT_cpReq_337_BITS_9_TO_6_770_EQ_0xC_809_935_A_ETC___d3251, - NOT_cpReq_337_BITS_9_TO_6_770_EQ_0xC_809_935_A_ETC___d3314, - NOT_cpReq_337_BITS_9_TO_6_770_EQ_0xC_809_935_A_ETC___d3377, - NOT_cpReq_337_BITS_9_TO_6_770_EQ_0xC_809_935_A_ETC___d3440, - NOT_cpReq_337_BITS_9_TO_6_770_EQ_0xC_809_935_A_ETC___d3503, - NOT_cpReq_337_BITS_9_TO_6_770_EQ_0xC_809_935_A_ETC___d3566, - NOT_cpReq_337_BITS_9_TO_6_770_EQ_0xC_809_935_A_ETC___d3629, - NOT_cpReq_337_BITS_9_TO_6_770_EQ_0xC_809_935_A_ETC___d3692, - NOT_cpReq_337_BITS_9_TO_6_770_EQ_0xC_809_935_A_ETC___d3755, - NOT_cpReq_337_BITS_9_TO_6_770_EQ_0xC_809_935_A_ETC___d3818, - NOT_cpReq_337_BIT_36_898_906_AND_NOT_wci_busy__ETC___d2907, - NOT_cpReq_337_BIT_36_898_906_AND_NOT_wci_busy__ETC___d2974, - NOT_cpReq_337_BIT_36_898_906_AND_NOT_wci_busy__ETC___d3037, - NOT_cpReq_337_BIT_36_898_906_AND_NOT_wci_busy__ETC___d3100, - NOT_cpReq_337_BIT_36_898_906_AND_NOT_wci_busy__ETC___d3163, - NOT_cpReq_337_BIT_36_898_906_AND_NOT_wci_busy__ETC___d3226, - NOT_cpReq_337_BIT_36_898_906_AND_NOT_wci_busy__ETC___d3289, - NOT_cpReq_337_BIT_36_898_906_AND_NOT_wci_busy__ETC___d3352, - NOT_cpReq_337_BIT_36_898_906_AND_NOT_wci_busy__ETC___d3415, - NOT_cpReq_337_BIT_36_898_906_AND_NOT_wci_busy__ETC___d3478, - NOT_cpReq_337_BIT_36_898_906_AND_NOT_wci_busy__ETC___d3541, - NOT_cpReq_337_BIT_36_898_906_AND_NOT_wci_busy__ETC___d3604, - NOT_cpReq_337_BIT_36_898_906_AND_NOT_wci_busy__ETC___d3667, - NOT_cpReq_337_BIT_36_898_906_AND_NOT_wci_busy__ETC___d3730, - NOT_cpReq_337_BIT_36_898_906_AND_NOT_wci_busy__ETC___d3793, - NOT_wci_busy_10_610_510_AND_wci_wReset_n_10_59_ETC___d3523, - NOT_wci_busy_10_860_AND_wci_wReset_n_90_OR_wci_ETC___d2878, - NOT_wci_busy_11_750_573_AND_wci_wReset_n_11_73_ETC___d3586, - NOT_wci_busy_12_890_636_AND_wci_wReset_n_12_87_ETC___d3649, - NOT_wci_busy_13_030_699_AND_wci_wReset_n_13_01_ETC___d3712, - NOT_wci_busy_14_170_762_AND_wci_wReset_n_14_15_ETC___d3775, - NOT_wci_busy_1_50_943_AND_wci_wReset_n_1_30_OR_ETC___d2956, - NOT_wci_busy_2_90_006_AND_wci_wReset_n_2_70_OR_ETC___d3019, - NOT_wci_busy_3_30_069_AND_wci_wReset_n_3_10_OR_ETC___d3082, - NOT_wci_busy_4_70_132_AND_wci_wReset_n_4_50_OR_ETC___d3145, - NOT_wci_busy_5_10_195_AND_wci_wReset_n_5_90_OR_ETC___d3208, - NOT_wci_busy_6_050_258_AND_wci_wReset_n_6_030__ETC___d3271, - NOT_wci_busy_7_190_321_AND_wci_wReset_n_7_170__ETC___d3334, - NOT_wci_busy_8_330_384_AND_wci_wReset_n_8_310__ETC___d3397, - NOT_wci_busy_9_470_447_AND_wci_wReset_n_9_450__ETC___d3460, - cpReq_337_BITS_11_TO_4_340_EQ_0x30_569_OR_cpRe_ETC___d2606, - cpReq_337_BITS_11_TO_4_340_ULT_0x30___d2412, - cpReq_337_BITS_11_TO_4_340_ULT_0xC0___d2568, - cpReq_337_BITS_27_TO_4_410_ULT_0x1000___d2840, - cpReq_337_BITS_27_TO_4_410_ULT_0x100___d2411, - cpReq_337_BITS_9_TO_6_770_EQ_0xC_809_AND_NOT_w_ETC___d2927, - cpReq_337_BITS_9_TO_6_770_EQ_0xC_809_AND_NOT_w_ETC___d2993, - cpReq_337_BITS_9_TO_6_770_EQ_0xC_809_AND_NOT_w_ETC___d3056, - cpReq_337_BITS_9_TO_6_770_EQ_0xC_809_AND_NOT_w_ETC___d3119, - cpReq_337_BITS_9_TO_6_770_EQ_0xC_809_AND_NOT_w_ETC___d3182, - cpReq_337_BITS_9_TO_6_770_EQ_0xC_809_AND_NOT_w_ETC___d3245, - cpReq_337_BITS_9_TO_6_770_EQ_0xC_809_AND_NOT_w_ETC___d3308, - cpReq_337_BITS_9_TO_6_770_EQ_0xC_809_AND_NOT_w_ETC___d3371, - cpReq_337_BITS_9_TO_6_770_EQ_0xC_809_AND_NOT_w_ETC___d3434, - cpReq_337_BITS_9_TO_6_770_EQ_0xC_809_AND_NOT_w_ETC___d3497, - cpReq_337_BITS_9_TO_6_770_EQ_0xC_809_AND_NOT_w_ETC___d3560, - cpReq_337_BITS_9_TO_6_770_EQ_0xC_809_AND_NOT_w_ETC___d3623, - cpReq_337_BITS_9_TO_6_770_EQ_0xC_809_AND_NOT_w_ETC___d3686, - cpReq_337_BITS_9_TO_6_770_EQ_0xC_809_AND_NOT_w_ETC___d3749, - cpReq_337_BITS_9_TO_6_770_EQ_0xC_809_AND_NOT_w_ETC___d3812, - cpReq_337_BIT_36_898_AND_NOT_wci_busy_10_610_5_ETC___d3534, - cpReq_337_BIT_36_898_AND_NOT_wci_busy_10_860_A_ETC___d2899, - cpReq_337_BIT_36_898_AND_NOT_wci_busy_11_750_5_ETC___d3597, - cpReq_337_BIT_36_898_AND_NOT_wci_busy_12_890_6_ETC___d3660, - cpReq_337_BIT_36_898_AND_NOT_wci_busy_13_030_6_ETC___d3723, - cpReq_337_BIT_36_898_AND_NOT_wci_busy_14_170_7_ETC___d3786, - cpReq_337_BIT_36_898_AND_NOT_wci_busy_1_50_943_ETC___d2967, - cpReq_337_BIT_36_898_AND_NOT_wci_busy_2_90_006_ETC___d3030, - cpReq_337_BIT_36_898_AND_NOT_wci_busy_3_30_069_ETC___d3093, - cpReq_337_BIT_36_898_AND_NOT_wci_busy_4_70_132_ETC___d3156, - cpReq_337_BIT_36_898_AND_NOT_wci_busy_5_10_195_ETC___d3219, - cpReq_337_BIT_36_898_AND_NOT_wci_busy_6_050_25_ETC___d3282, - cpReq_337_BIT_36_898_AND_NOT_wci_busy_7_190_32_ETC___d3345, - cpReq_337_BIT_36_898_AND_NOT_wci_busy_8_330_38_ETC___d3408, - cpReq_337_BIT_36_898_AND_NOT_wci_busy_9_470_44_ETC___d3471, + wire IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_N_ETC___d4934, + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_N_ETC___d4940, + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_N_ETC___d4946, + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_N_ETC___d4952, + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_N_ETC___d4958, + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_N_ETC___d4964, + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_N_ETC___d4970, + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_N_ETC___d4976, + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_N_ETC___d4982, + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_N_ETC___d4988, + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_N_ETC___d4994, + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_N_ETC___d5000, + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_N_ETC___d5006, + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_N_ETC___d5012, + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_N_ETC___d5018, + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_w_ETC___d4932, + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_w_ETC___d4938, + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_w_ETC___d4944, + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_w_ETC___d4950, + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_w_ETC___d4956, + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_w_ETC___d4962, + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_w_ETC___d4968, + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_w_ETC___d4974, + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_w_ETC___d4980, + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_w_ETC___d4986, + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_w_ETC___d4992, + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_w_ETC___d4998, + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_w_ETC___d5004, + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_w_ETC___d5010, + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_w_ETC___d5016, + IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_THEN_N_ETC___d3580, + IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_THEN_N_ETC___d3584, + IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_THEN_N_ETC___d3588, + IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_THEN_N_ETC___d3592, + IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_THEN_N_ETC___d3596, + IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_THEN_N_ETC___d3600, + IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_THEN_N_ETC___d3604, + IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_THEN_N_ETC___d3608, + IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_THEN_N_ETC___d3612, + IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_THEN_N_ETC___d3616, + IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_THEN_N_ETC___d3620, + IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_THEN_N_ETC___d3624, + IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_THEN_N_ETC___d3628, + IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_THEN_N_ETC___d3632, + IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_THEN_N_ETC___d3636, + IF_timeServ_ppsOK_7_THEN_timeServ_ppsExtSync_d_ETC___d39, + NOT_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_TH_ETC___d5023, + NOT_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_TH_ETC___d3641, + NOT_cpReq_363_BITS_11_TO_4_366_EQ_0x30_595_649_ETC___d2712, + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d3796, + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d3805, + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d3816, + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d3827, + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d4933, + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d4939, + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d4945, + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d4951, + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d4957, + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d4963, + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d4969, + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d4975, + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d4981, + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d4987, + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d4993, + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d4999, + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d5005, + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d5011, + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d5017, + NOT_cpReq_363_BITS_61_TO_60_848_EQ_1_967_993_O_ETC___d3029, + NOT_cpReq_363_BITS_61_TO_60_848_EQ_1_967_993_O_ETC___d3039, + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d3688, + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d3701, + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d3742, + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d3757, + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d3858, + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d3870, + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d3883, + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d3893, + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d3935, + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d3947, + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d3958, + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d3968, + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4010, + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4022, + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4033, + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4043, + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4085, + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4097, + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4108, + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4118, + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4160, + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4172, + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4183, + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4193, + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4235, + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4247, + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4258, + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4268, + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4310, + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4322, + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4333, + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4343, + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4385, + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4397, + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4408, + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4418, + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4460, + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4472, + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4483, + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4493, + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4535, + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4547, + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4558, + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4568, + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4610, + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4622, + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4633, + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4643, + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4685, + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4697, + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4708, + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4718, + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4760, + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4772, + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4783, + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4793, + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4835, + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4847, + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4858, + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4868, + NOT_cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_035_A_ETC___d3839, + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046, + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918, + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924, + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930, + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936, + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942, + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864, + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870, + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876, + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882, + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888, + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894, + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900, + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906, + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912, + cpReq_363_BITS_11_TO_4_366_EQ_0x30_595_OR_cpRe_ETC___d2632, + cpReq_363_BITS_11_TO_4_366_ULT_0x30___d2438, + cpReq_363_BITS_11_TO_4_366_ULT_0xC0___d2594, + cpReq_363_BITS_27_TO_4_436_ULT_0x1000___d2836, + cpReq_363_BITS_27_TO_4_436_ULT_0x100___d2437, + cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_AND_NOT_c_ETC___d3016, + cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_AND_NOT_c_ETC___d3022, + cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_AND_cpReq_ETC___d3001, + cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_AND_cpReq_ETC___d3009, timeServ_ppsExtSync_d2_2_AND_NOT_timeServ_ppsE_ETC___d61, timeServ_ppsExtSync_d2_2_AND_NOT_timeServ_ppsE_ETC___d70, - timeServ_refFromRise_3_ULE_199800000___d6126, - timeServ_refFromRise_3_ULT_200200000___d5828, - wci_respTimr_02_ULT_1_SL_wci_wTimeout_03_04___d5829, - wci_respTimr_10_602_ULT_1_SL_wci_wTimeout_10_6_ETC___d5839, - wci_respTimr_11_742_ULT_1_SL_wci_wTimeout_11_7_ETC___d5840, - wci_respTimr_12_882_ULT_1_SL_wci_wTimeout_12_8_ETC___d5841, - wci_respTimr_13_022_ULT_1_SL_wci_wTimeout_13_0_ETC___d5842, - wci_respTimr_14_162_ULT_1_SL_wci_wTimeout_14_1_ETC___d5843, - wci_respTimr_1_42_ULT_1_SL_wci_wTimeout_1_43_44___d5830, - wci_respTimr_2_82_ULT_1_SL_wci_wTimeout_2_83_84___d5831, - wci_respTimr_3_22_ULT_1_SL_wci_wTimeout_3_23_24___d5832, - wci_respTimr_4_62_ULT_1_SL_wci_wTimeout_4_63_64___d5833, - wci_respTimr_5_02_ULT_1_SL_wci_wTimeout_5_03_04___d5834, - wci_respTimr_6_042_ULT_1_SL_wci_wTimeout_6_043_ETC___d5835, - wci_respTimr_7_182_ULT_1_SL_wci_wTimeout_7_183_ETC___d5836, - wci_respTimr_8_322_ULT_1_SL_wci_wTimeout_8_323_ETC___d5837, - wci_respTimr_9_462_ULT_1_SL_wci_wTimeout_9_463_ETC___d5838, - wci_wReset_n_10_590_AND_NOT_wci_busy_10_610_51_ETC___d3513, - wci_wReset_n_11_730_AND_NOT_wci_busy_11_750_57_ETC___d3576, - wci_wReset_n_12_870_AND_NOT_wci_busy_12_890_63_ETC___d3639, - wci_wReset_n_13_010_AND_NOT_wci_busy_13_030_69_ETC___d3702, - wci_wReset_n_14_150_AND_NOT_wci_busy_14_170_76_ETC___d3765, - wci_wReset_n_1_30_AND_NOT_wci_busy_1_50_943_AN_ETC___d2946, - wci_wReset_n_2_70_AND_NOT_wci_busy_2_90_006_AN_ETC___d3009, - wci_wReset_n_3_10_AND_NOT_wci_busy_3_30_069_AN_ETC___d3072, - wci_wReset_n_4_50_AND_NOT_wci_busy_4_70_132_AN_ETC___d3135, - wci_wReset_n_5_90_AND_NOT_wci_busy_5_10_195_AN_ETC___d3198, - wci_wReset_n_6_030_AND_NOT_wci_busy_6_050_258__ETC___d3261, - wci_wReset_n_7_170_AND_NOT_wci_busy_7_190_321__ETC___d3324, - wci_wReset_n_8_310_AND_NOT_wci_busy_8_330_384__ETC___d3387, - wci_wReset_n_90_AND_NOT_wci_busy_10_860_AND_NO_ETC___d2863, - wci_wReset_n_9_450_AND_NOT_wci_busy_9_470_447__ETC___d3450, - wci_wciResponse_10_wget__597_BITS_33_TO_32_598_ETC___d1626, - wci_wciResponse_11_wget__737_BITS_33_TO_32_738_ETC___d1766, - wci_wciResponse_12_wget__877_BITS_33_TO_32_878_ETC___d1906, - wci_wciResponse_13_wget__017_BITS_33_TO_32_018_ETC___d2046, - wci_wciResponse_14_wget__157_BITS_33_TO_32_158_ETC___d2186, - wci_wciResponse_1_wget__37_BITS_33_TO_32_38_EQ_ETC___d366, - wci_wciResponse_2_wget__77_BITS_33_TO_32_78_EQ_ETC___d506, - wci_wciResponse_3_wget__17_BITS_33_TO_32_18_EQ_ETC___d646, - wci_wciResponse_4_wget__57_BITS_33_TO_32_58_EQ_ETC___d786, - wci_wciResponse_5_wget__97_BITS_33_TO_32_98_EQ_ETC___d926, - wci_wciResponse_6_wget__037_BITS_33_TO_32_038__ETC___d1066, - wci_wciResponse_7_wget__177_BITS_33_TO_32_178__ETC___d1206, - wci_wciResponse_8_wget__317_BITS_33_TO_32_318__ETC___d1346, - wci_wciResponse_9_wget__457_BITS_33_TO_32_458__ETC___d1486, - wci_wciResponse_wget__97_BITS_33_TO_32_98_EQ_0_ETC___d226; + timeServ_refFromRise_3_ULE_199800000___d48, + timeServ_refFromRise_3_ULT_200200000___d50, + wci_0_respTimr_28_ULT_1_SL_wci_0_wTimeout_29_30___d231, + wci_0_wciResponse_wget__23_BITS_33_TO_32_24_EQ_ETC___d252, + wci_10_respTimr_628_ULT_1_SL_wci_10_wTimeout_6_ETC___d1631, + wci_10_wciResponse_wget__623_BITS_33_TO_32_624_ETC___d1652, + wci_11_respTimr_768_ULT_1_SL_wci_11_wTimeout_7_ETC___d1771, + wci_11_wciResponse_wget__763_BITS_33_TO_32_764_ETC___d1792, + wci_12_respTimr_908_ULT_1_SL_wci_12_wTimeout_9_ETC___d1911, + wci_12_wciResponse_wget__903_BITS_33_TO_32_904_ETC___d1932, + wci_13_respTimr_048_ULT_1_SL_wci_13_wTimeout_0_ETC___d2051, + wci_13_wciResponse_wget__043_BITS_33_TO_32_044_ETC___d2072, + wci_14_respTimr_188_ULT_1_SL_wci_14_wTimeout_1_ETC___d2191, + wci_14_wciResponse_wget__183_BITS_33_TO_32_184_ETC___d2212, + wci_1_respTimr_68_ULT_1_SL_wci_1_wTimeout_69_70___d371, + wci_1_wciResponse_wget__63_BITS_33_TO_32_64_EQ_ETC___d392, + wci_2_respTimr_08_ULT_1_SL_wci_2_wTimeout_09_10___d511, + wci_2_wciResponse_wget__03_BITS_33_TO_32_04_EQ_ETC___d532, + wci_3_respTimr_48_ULT_1_SL_wci_3_wTimeout_49_50___d651, + wci_3_wciResponse_wget__43_BITS_33_TO_32_44_EQ_ETC___d672, + wci_4_respTimr_88_ULT_1_SL_wci_4_wTimeout_89_90___d791, + wci_4_wciResponse_wget__83_BITS_33_TO_32_84_EQ_ETC___d812, + wci_5_respTimr_28_ULT_1_SL_wci_5_wTimeout_29_30___d931, + wci_5_wciResponse_wget__23_BITS_33_TO_32_24_EQ_ETC___d952, + wci_6_respTimr_068_ULT_1_SL_wci_6_wTimeout_069_ETC___d1071, + wci_6_wciResponse_wget__063_BITS_33_TO_32_064__ETC___d1092, + wci_7_respTimr_208_ULT_1_SL_wci_7_wTimeout_209_ETC___d1211, + wci_7_wciResponse_wget__203_BITS_33_TO_32_204__ETC___d1232, + wci_8_respTimr_348_ULT_1_SL_wci_8_wTimeout_349_ETC___d1351, + wci_8_wciResponse_wget__343_BITS_33_TO_32_344__ETC___d1372, + wci_9_respTimr_488_ULT_1_SL_wci_9_wTimeout_489_ETC___d1491, + wci_9_wciResponse_wget__483_BITS_33_TO_32_484__ETC___d1512; // output resets - assign RST_N_wci_Vm_0 = wci_mReset$OUT_RST ; - assign RST_N_wci_Vm_1 = wci_mReset_1$OUT_RST ; - assign RST_N_wci_Vm_2 = wci_mReset_2$OUT_RST ; - assign RST_N_wci_Vm_3 = wci_mReset_3$OUT_RST ; - assign RST_N_wci_Vm_4 = wci_mReset_4$OUT_RST ; - assign RST_N_wci_Vm_5 = wci_mReset_5$OUT_RST ; - assign RST_N_wci_Vm_6 = wci_mReset_6$OUT_RST ; - assign RST_N_wci_Vm_7 = wci_mReset_7$OUT_RST ; - assign RST_N_wci_Vm_8 = wci_mReset_8$OUT_RST ; - assign RST_N_wci_Vm_9 = wci_mReset_9$OUT_RST ; - assign RST_N_wci_Vm_10 = wci_mReset_10$OUT_RST ; - assign RST_N_wci_Vm_11 = wci_mReset_11$OUT_RST ; - assign RST_N_wci_Vm_12 = wci_mReset_12$OUT_RST ; - assign RST_N_wci_Vm_13 = wci_mReset_13$OUT_RST ; - assign RST_N_wci_Vm_14 = wci_mReset_14$OUT_RST ; + assign RST_N_wci_Vm_0 = wci_0_mReset$OUT_RST ; + assign RST_N_wci_Vm_1 = wci_1_mReset$OUT_RST ; + assign RST_N_wci_Vm_2 = wci_2_mReset$OUT_RST ; + assign RST_N_wci_Vm_3 = wci_3_mReset$OUT_RST ; + assign RST_N_wci_Vm_4 = wci_4_mReset$OUT_RST ; + assign RST_N_wci_Vm_5 = wci_5_mReset$OUT_RST ; + assign RST_N_wci_Vm_6 = wci_6_mReset$OUT_RST ; + assign RST_N_wci_Vm_7 = wci_7_mReset$OUT_RST ; + assign RST_N_wci_Vm_8 = wci_8_mReset$OUT_RST ; + assign RST_N_wci_Vm_9 = wci_9_mReset$OUT_RST ; + assign RST_N_wci_Vm_10 = wci_10_mReset$OUT_RST ; + assign RST_N_wci_Vm_11 = wci_11_mReset$OUT_RST ; + assign RST_N_wci_Vm_12 = wci_12_mReset$OUT_RST ; + assign RST_N_wci_Vm_13 = wci_13_mReset$OUT_RST ; + assign RST_N_wci_Vm_14 = wci_14_mReset$OUT_RST ; // action method server_request_put assign RDY_server_request_put = cpReqF$FULL_N ; @@ -4752,307 +4869,309 @@ module mkOCCP(pciDevice, assign RDY_server_response_get = cpRespF$EMPTY_N ; // value method wci_Vm_0_mCmd - assign wci_Vm_0_MCmd = wci_sThreadBusy_d ? 3'd0 : wci_reqF_q_0[71:69] ; + assign wci_Vm_0_MCmd = wci_0_sThreadBusy_d ? 3'd0 : wci_0_reqF_q_0[71:69] ; // value method wci_Vm_0_mAddrSpace - assign wci_Vm_0_MAddrSpace = !wci_sThreadBusy_d && wci_reqF_q_0[68] ; + assign wci_Vm_0_MAddrSpace = !wci_0_sThreadBusy_d && wci_0_reqF_q_0[68] ; // value method wci_Vm_0_mByteEn - assign wci_Vm_0_MByteEn = wci_sThreadBusy_d ? 4'd0 : wci_reqF_q_0[67:64] ; + assign wci_Vm_0_MByteEn = + wci_0_sThreadBusy_d ? 4'd0 : wci_0_reqF_q_0[67:64] ; // value method wci_Vm_0_mAddr - assign wci_Vm_0_MAddr = wci_sThreadBusy_d ? 32'd0 : wci_reqF_q_0[63:32] ; + assign wci_Vm_0_MAddr = + wci_0_sThreadBusy_d ? 32'd0 : wci_0_reqF_q_0[63:32] ; // value method wci_Vm_0_mData - assign wci_Vm_0_MData = wci_reqF_q_0[31:0] ; + assign wci_Vm_0_MData = wci_0_reqF_q_0[31:0] ; // value method wci_Vm_0_mFlag - assign wci_Vm_0_MFlag = wci_mFlagReg ; + assign wci_Vm_0_MFlag = wci_0_mFlagReg ; // value method wci_Vm_1_mCmd - assign wci_Vm_1_MCmd = wci_sThreadBusy_d_1 ? 3'd0 : wci_reqF_1_q_0[71:69] ; + assign wci_Vm_1_MCmd = wci_1_sThreadBusy_d ? 3'd0 : wci_1_reqF_q_0[71:69] ; // value method wci_Vm_1_mAddrSpace - assign wci_Vm_1_MAddrSpace = !wci_sThreadBusy_d_1 && wci_reqF_1_q_0[68] ; + assign wci_Vm_1_MAddrSpace = !wci_1_sThreadBusy_d && wci_1_reqF_q_0[68] ; // value method wci_Vm_1_mByteEn assign wci_Vm_1_MByteEn = - wci_sThreadBusy_d_1 ? 4'd0 : wci_reqF_1_q_0[67:64] ; + wci_1_sThreadBusy_d ? 4'd0 : wci_1_reqF_q_0[67:64] ; // value method wci_Vm_1_mAddr assign wci_Vm_1_MAddr = - wci_sThreadBusy_d_1 ? 32'd0 : wci_reqF_1_q_0[63:32] ; + wci_1_sThreadBusy_d ? 32'd0 : wci_1_reqF_q_0[63:32] ; // value method wci_Vm_1_mData - assign wci_Vm_1_MData = wci_reqF_1_q_0[31:0] ; + assign wci_Vm_1_MData = wci_1_reqF_q_0[31:0] ; // value method wci_Vm_1_mFlag - assign wci_Vm_1_MFlag = wci_mFlagReg_1 ; + assign wci_Vm_1_MFlag = wci_1_mFlagReg ; // value method wci_Vm_2_mCmd - assign wci_Vm_2_MCmd = wci_sThreadBusy_d_2 ? 3'd0 : wci_reqF_2_q_0[71:69] ; + assign wci_Vm_2_MCmd = wci_2_sThreadBusy_d ? 3'd0 : wci_2_reqF_q_0[71:69] ; // value method wci_Vm_2_mAddrSpace - assign wci_Vm_2_MAddrSpace = !wci_sThreadBusy_d_2 && wci_reqF_2_q_0[68] ; + assign wci_Vm_2_MAddrSpace = !wci_2_sThreadBusy_d && wci_2_reqF_q_0[68] ; // value method wci_Vm_2_mByteEn assign wci_Vm_2_MByteEn = - wci_sThreadBusy_d_2 ? 4'd0 : wci_reqF_2_q_0[67:64] ; + wci_2_sThreadBusy_d ? 4'd0 : wci_2_reqF_q_0[67:64] ; // value method wci_Vm_2_mAddr assign wci_Vm_2_MAddr = - wci_sThreadBusy_d_2 ? 32'd0 : wci_reqF_2_q_0[63:32] ; + wci_2_sThreadBusy_d ? 32'd0 : wci_2_reqF_q_0[63:32] ; // value method wci_Vm_2_mData - assign wci_Vm_2_MData = wci_reqF_2_q_0[31:0] ; + assign wci_Vm_2_MData = wci_2_reqF_q_0[31:0] ; // value method wci_Vm_2_mFlag - assign wci_Vm_2_MFlag = wci_mFlagReg_2 ; + assign wci_Vm_2_MFlag = wci_2_mFlagReg ; // value method wci_Vm_3_mCmd - assign wci_Vm_3_MCmd = wci_sThreadBusy_d_3 ? 3'd0 : wci_reqF_3_q_0[71:69] ; + assign wci_Vm_3_MCmd = wci_3_sThreadBusy_d ? 3'd0 : wci_3_reqF_q_0[71:69] ; // value method wci_Vm_3_mAddrSpace - assign wci_Vm_3_MAddrSpace = !wci_sThreadBusy_d_3 && wci_reqF_3_q_0[68] ; + assign wci_Vm_3_MAddrSpace = !wci_3_sThreadBusy_d && wci_3_reqF_q_0[68] ; // value method wci_Vm_3_mByteEn assign wci_Vm_3_MByteEn = - wci_sThreadBusy_d_3 ? 4'd0 : wci_reqF_3_q_0[67:64] ; + wci_3_sThreadBusy_d ? 4'd0 : wci_3_reqF_q_0[67:64] ; // value method wci_Vm_3_mAddr assign wci_Vm_3_MAddr = - wci_sThreadBusy_d_3 ? 32'd0 : wci_reqF_3_q_0[63:32] ; + wci_3_sThreadBusy_d ? 32'd0 : wci_3_reqF_q_0[63:32] ; // value method wci_Vm_3_mData - assign wci_Vm_3_MData = wci_reqF_3_q_0[31:0] ; + assign wci_Vm_3_MData = wci_3_reqF_q_0[31:0] ; // value method wci_Vm_3_mFlag - assign wci_Vm_3_MFlag = wci_mFlagReg_3 ; + assign wci_Vm_3_MFlag = wci_3_mFlagReg ; // value method wci_Vm_4_mCmd - assign wci_Vm_4_MCmd = wci_sThreadBusy_d_4 ? 3'd0 : wci_reqF_4_q_0[71:69] ; + assign wci_Vm_4_MCmd = wci_4_sThreadBusy_d ? 3'd0 : wci_4_reqF_q_0[71:69] ; // value method wci_Vm_4_mAddrSpace - assign wci_Vm_4_MAddrSpace = !wci_sThreadBusy_d_4 && wci_reqF_4_q_0[68] ; + assign wci_Vm_4_MAddrSpace = !wci_4_sThreadBusy_d && wci_4_reqF_q_0[68] ; // value method wci_Vm_4_mByteEn assign wci_Vm_4_MByteEn = - wci_sThreadBusy_d_4 ? 4'd0 : wci_reqF_4_q_0[67:64] ; + wci_4_sThreadBusy_d ? 4'd0 : wci_4_reqF_q_0[67:64] ; // value method wci_Vm_4_mAddr assign wci_Vm_4_MAddr = - wci_sThreadBusy_d_4 ? 32'd0 : wci_reqF_4_q_0[63:32] ; + wci_4_sThreadBusy_d ? 32'd0 : wci_4_reqF_q_0[63:32] ; // value method wci_Vm_4_mData - assign wci_Vm_4_MData = wci_reqF_4_q_0[31:0] ; + assign wci_Vm_4_MData = wci_4_reqF_q_0[31:0] ; // value method wci_Vm_4_mFlag - assign wci_Vm_4_MFlag = wci_mFlagReg_4 ; + assign wci_Vm_4_MFlag = wci_4_mFlagReg ; // value method wci_Vm_5_mCmd - assign wci_Vm_5_MCmd = wci_sThreadBusy_d_5 ? 3'd0 : wci_reqF_5_q_0[71:69] ; + assign wci_Vm_5_MCmd = wci_5_sThreadBusy_d ? 3'd0 : wci_5_reqF_q_0[71:69] ; // value method wci_Vm_5_mAddrSpace - assign wci_Vm_5_MAddrSpace = !wci_sThreadBusy_d_5 && wci_reqF_5_q_0[68] ; + assign wci_Vm_5_MAddrSpace = !wci_5_sThreadBusy_d && wci_5_reqF_q_0[68] ; // value method wci_Vm_5_mByteEn assign wci_Vm_5_MByteEn = - wci_sThreadBusy_d_5 ? 4'd0 : wci_reqF_5_q_0[67:64] ; + wci_5_sThreadBusy_d ? 4'd0 : wci_5_reqF_q_0[67:64] ; // value method wci_Vm_5_mAddr assign wci_Vm_5_MAddr = - wci_sThreadBusy_d_5 ? 32'd0 : wci_reqF_5_q_0[63:32] ; + wci_5_sThreadBusy_d ? 32'd0 : wci_5_reqF_q_0[63:32] ; // value method wci_Vm_5_mData - assign wci_Vm_5_MData = wci_reqF_5_q_0[31:0] ; + assign wci_Vm_5_MData = wci_5_reqF_q_0[31:0] ; // value method wci_Vm_5_mFlag - assign wci_Vm_5_MFlag = wci_mFlagReg_5 ; + assign wci_Vm_5_MFlag = wci_5_mFlagReg ; // value method wci_Vm_6_mCmd - assign wci_Vm_6_MCmd = wci_sThreadBusy_d_6 ? 3'd0 : wci_reqF_6_q_0[71:69] ; + assign wci_Vm_6_MCmd = wci_6_sThreadBusy_d ? 3'd0 : wci_6_reqF_q_0[71:69] ; // value method wci_Vm_6_mAddrSpace - assign wci_Vm_6_MAddrSpace = !wci_sThreadBusy_d_6 && wci_reqF_6_q_0[68] ; + assign wci_Vm_6_MAddrSpace = !wci_6_sThreadBusy_d && wci_6_reqF_q_0[68] ; // value method wci_Vm_6_mByteEn assign wci_Vm_6_MByteEn = - wci_sThreadBusy_d_6 ? 4'd0 : wci_reqF_6_q_0[67:64] ; + wci_6_sThreadBusy_d ? 4'd0 : wci_6_reqF_q_0[67:64] ; // value method wci_Vm_6_mAddr assign wci_Vm_6_MAddr = - wci_sThreadBusy_d_6 ? 32'd0 : wci_reqF_6_q_0[63:32] ; + wci_6_sThreadBusy_d ? 32'd0 : wci_6_reqF_q_0[63:32] ; // value method wci_Vm_6_mData - assign wci_Vm_6_MData = wci_reqF_6_q_0[31:0] ; + assign wci_Vm_6_MData = wci_6_reqF_q_0[31:0] ; // value method wci_Vm_6_mFlag - assign wci_Vm_6_MFlag = wci_mFlagReg_6 ; + assign wci_Vm_6_MFlag = wci_6_mFlagReg ; // value method wci_Vm_7_mCmd - assign wci_Vm_7_MCmd = wci_sThreadBusy_d_7 ? 3'd0 : wci_reqF_7_q_0[71:69] ; + assign wci_Vm_7_MCmd = wci_7_sThreadBusy_d ? 3'd0 : wci_7_reqF_q_0[71:69] ; // value method wci_Vm_7_mAddrSpace - assign wci_Vm_7_MAddrSpace = !wci_sThreadBusy_d_7 && wci_reqF_7_q_0[68] ; + assign wci_Vm_7_MAddrSpace = !wci_7_sThreadBusy_d && wci_7_reqF_q_0[68] ; // value method wci_Vm_7_mByteEn assign wci_Vm_7_MByteEn = - wci_sThreadBusy_d_7 ? 4'd0 : wci_reqF_7_q_0[67:64] ; + wci_7_sThreadBusy_d ? 4'd0 : wci_7_reqF_q_0[67:64] ; // value method wci_Vm_7_mAddr assign wci_Vm_7_MAddr = - wci_sThreadBusy_d_7 ? 32'd0 : wci_reqF_7_q_0[63:32] ; + wci_7_sThreadBusy_d ? 32'd0 : wci_7_reqF_q_0[63:32] ; // value method wci_Vm_7_mData - assign wci_Vm_7_MData = wci_reqF_7_q_0[31:0] ; + assign wci_Vm_7_MData = wci_7_reqF_q_0[31:0] ; // value method wci_Vm_7_mFlag - assign wci_Vm_7_MFlag = wci_mFlagReg_7 ; + assign wci_Vm_7_MFlag = wci_7_mFlagReg ; // value method wci_Vm_8_mCmd - assign wci_Vm_8_MCmd = wci_sThreadBusy_d_8 ? 3'd0 : wci_reqF_8_q_0[71:69] ; + assign wci_Vm_8_MCmd = wci_8_sThreadBusy_d ? 3'd0 : wci_8_reqF_q_0[71:69] ; // value method wci_Vm_8_mAddrSpace - assign wci_Vm_8_MAddrSpace = !wci_sThreadBusy_d_8 && wci_reqF_8_q_0[68] ; + assign wci_Vm_8_MAddrSpace = !wci_8_sThreadBusy_d && wci_8_reqF_q_0[68] ; // value method wci_Vm_8_mByteEn assign wci_Vm_8_MByteEn = - wci_sThreadBusy_d_8 ? 4'd0 : wci_reqF_8_q_0[67:64] ; + wci_8_sThreadBusy_d ? 4'd0 : wci_8_reqF_q_0[67:64] ; // value method wci_Vm_8_mAddr assign wci_Vm_8_MAddr = - wci_sThreadBusy_d_8 ? 32'd0 : wci_reqF_8_q_0[63:32] ; + wci_8_sThreadBusy_d ? 32'd0 : wci_8_reqF_q_0[63:32] ; // value method wci_Vm_8_mData - assign wci_Vm_8_MData = wci_reqF_8_q_0[31:0] ; + assign wci_Vm_8_MData = wci_8_reqF_q_0[31:0] ; // value method wci_Vm_8_mFlag - assign wci_Vm_8_MFlag = wci_mFlagReg_8 ; + assign wci_Vm_8_MFlag = wci_8_mFlagReg ; // value method wci_Vm_9_mCmd - assign wci_Vm_9_MCmd = wci_sThreadBusy_d_9 ? 3'd0 : wci_reqF_9_q_0[71:69] ; + assign wci_Vm_9_MCmd = wci_9_sThreadBusy_d ? 3'd0 : wci_9_reqF_q_0[71:69] ; // value method wci_Vm_9_mAddrSpace - assign wci_Vm_9_MAddrSpace = !wci_sThreadBusy_d_9 && wci_reqF_9_q_0[68] ; + assign wci_Vm_9_MAddrSpace = !wci_9_sThreadBusy_d && wci_9_reqF_q_0[68] ; // value method wci_Vm_9_mByteEn assign wci_Vm_9_MByteEn = - wci_sThreadBusy_d_9 ? 4'd0 : wci_reqF_9_q_0[67:64] ; + wci_9_sThreadBusy_d ? 4'd0 : wci_9_reqF_q_0[67:64] ; // value method wci_Vm_9_mAddr assign wci_Vm_9_MAddr = - wci_sThreadBusy_d_9 ? 32'd0 : wci_reqF_9_q_0[63:32] ; + wci_9_sThreadBusy_d ? 32'd0 : wci_9_reqF_q_0[63:32] ; // value method wci_Vm_9_mData - assign wci_Vm_9_MData = wci_reqF_9_q_0[31:0] ; + assign wci_Vm_9_MData = wci_9_reqF_q_0[31:0] ; // value method wci_Vm_9_mFlag - assign wci_Vm_9_MFlag = wci_mFlagReg_9 ; + assign wci_Vm_9_MFlag = wci_9_mFlagReg ; // value method wci_Vm_10_mCmd assign wci_Vm_10_MCmd = - wci_sThreadBusy_d_10 ? 3'd0 : wci_reqF_10_q_0[71:69] ; + wci_10_sThreadBusy_d ? 3'd0 : wci_10_reqF_q_0[71:69] ; // value method wci_Vm_10_mAddrSpace - assign wci_Vm_10_MAddrSpace = !wci_sThreadBusy_d_10 && wci_reqF_10_q_0[68] ; + assign wci_Vm_10_MAddrSpace = !wci_10_sThreadBusy_d && wci_10_reqF_q_0[68] ; // value method wci_Vm_10_mByteEn assign wci_Vm_10_MByteEn = - wci_sThreadBusy_d_10 ? 4'd0 : wci_reqF_10_q_0[67:64] ; + wci_10_sThreadBusy_d ? 4'd0 : wci_10_reqF_q_0[67:64] ; // value method wci_Vm_10_mAddr assign wci_Vm_10_MAddr = - wci_sThreadBusy_d_10 ? 32'd0 : wci_reqF_10_q_0[63:32] ; + wci_10_sThreadBusy_d ? 32'd0 : wci_10_reqF_q_0[63:32] ; // value method wci_Vm_10_mData - assign wci_Vm_10_MData = wci_reqF_10_q_0[31:0] ; + assign wci_Vm_10_MData = wci_10_reqF_q_0[31:0] ; // value method wci_Vm_10_mFlag - assign wci_Vm_10_MFlag = wci_mFlagReg_10 ; + assign wci_Vm_10_MFlag = wci_10_mFlagReg ; // value method wci_Vm_11_mCmd assign wci_Vm_11_MCmd = - wci_sThreadBusy_d_11 ? 3'd0 : wci_reqF_11_q_0[71:69] ; + wci_11_sThreadBusy_d ? 3'd0 : wci_11_reqF_q_0[71:69] ; // value method wci_Vm_11_mAddrSpace - assign wci_Vm_11_MAddrSpace = !wci_sThreadBusy_d_11 && wci_reqF_11_q_0[68] ; + assign wci_Vm_11_MAddrSpace = !wci_11_sThreadBusy_d && wci_11_reqF_q_0[68] ; // value method wci_Vm_11_mByteEn assign wci_Vm_11_MByteEn = - wci_sThreadBusy_d_11 ? 4'd0 : wci_reqF_11_q_0[67:64] ; + wci_11_sThreadBusy_d ? 4'd0 : wci_11_reqF_q_0[67:64] ; // value method wci_Vm_11_mAddr assign wci_Vm_11_MAddr = - wci_sThreadBusy_d_11 ? 32'd0 : wci_reqF_11_q_0[63:32] ; + wci_11_sThreadBusy_d ? 32'd0 : wci_11_reqF_q_0[63:32] ; // value method wci_Vm_11_mData - assign wci_Vm_11_MData = wci_reqF_11_q_0[31:0] ; + assign wci_Vm_11_MData = wci_11_reqF_q_0[31:0] ; // value method wci_Vm_11_mFlag - assign wci_Vm_11_MFlag = wci_mFlagReg_11 ; + assign wci_Vm_11_MFlag = wci_11_mFlagReg ; // value method wci_Vm_12_mCmd assign wci_Vm_12_MCmd = - wci_sThreadBusy_d_12 ? 3'd0 : wci_reqF_12_q_0[71:69] ; + wci_12_sThreadBusy_d ? 3'd0 : wci_12_reqF_q_0[71:69] ; // value method wci_Vm_12_mAddrSpace - assign wci_Vm_12_MAddrSpace = !wci_sThreadBusy_d_12 && wci_reqF_12_q_0[68] ; + assign wci_Vm_12_MAddrSpace = !wci_12_sThreadBusy_d && wci_12_reqF_q_0[68] ; // value method wci_Vm_12_mByteEn assign wci_Vm_12_MByteEn = - wci_sThreadBusy_d_12 ? 4'd0 : wci_reqF_12_q_0[67:64] ; + wci_12_sThreadBusy_d ? 4'd0 : wci_12_reqF_q_0[67:64] ; // value method wci_Vm_12_mAddr assign wci_Vm_12_MAddr = - wci_sThreadBusy_d_12 ? 32'd0 : wci_reqF_12_q_0[63:32] ; + wci_12_sThreadBusy_d ? 32'd0 : wci_12_reqF_q_0[63:32] ; // value method wci_Vm_12_mData - assign wci_Vm_12_MData = wci_reqF_12_q_0[31:0] ; + assign wci_Vm_12_MData = wci_12_reqF_q_0[31:0] ; // value method wci_Vm_12_mFlag - assign wci_Vm_12_MFlag = wci_mFlagReg_12 ; + assign wci_Vm_12_MFlag = wci_12_mFlagReg ; // value method wci_Vm_13_mCmd assign wci_Vm_13_MCmd = - wci_sThreadBusy_d_13 ? 3'd0 : wci_reqF_13_q_0[71:69] ; + wci_13_sThreadBusy_d ? 3'd0 : wci_13_reqF_q_0[71:69] ; // value method wci_Vm_13_mAddrSpace - assign wci_Vm_13_MAddrSpace = !wci_sThreadBusy_d_13 && wci_reqF_13_q_0[68] ; + assign wci_Vm_13_MAddrSpace = !wci_13_sThreadBusy_d && wci_13_reqF_q_0[68] ; // value method wci_Vm_13_mByteEn assign wci_Vm_13_MByteEn = - wci_sThreadBusy_d_13 ? 4'd0 : wci_reqF_13_q_0[67:64] ; + wci_13_sThreadBusy_d ? 4'd0 : wci_13_reqF_q_0[67:64] ; // value method wci_Vm_13_mAddr assign wci_Vm_13_MAddr = - wci_sThreadBusy_d_13 ? 32'd0 : wci_reqF_13_q_0[63:32] ; + wci_13_sThreadBusy_d ? 32'd0 : wci_13_reqF_q_0[63:32] ; // value method wci_Vm_13_mData - assign wci_Vm_13_MData = wci_reqF_13_q_0[31:0] ; + assign wci_Vm_13_MData = wci_13_reqF_q_0[31:0] ; // value method wci_Vm_13_mFlag - assign wci_Vm_13_MFlag = wci_mFlagReg_13 ; + assign wci_Vm_13_MFlag = wci_13_mFlagReg ; // value method wci_Vm_14_mCmd assign wci_Vm_14_MCmd = - wci_sThreadBusy_d_14 ? 3'd0 : wci_reqF_14_q_0[71:69] ; + wci_14_sThreadBusy_d ? 3'd0 : wci_14_reqF_q_0[71:69] ; // value method wci_Vm_14_mAddrSpace - assign wci_Vm_14_MAddrSpace = !wci_sThreadBusy_d_14 && wci_reqF_14_q_0[68] ; + assign wci_Vm_14_MAddrSpace = !wci_14_sThreadBusy_d && wci_14_reqF_q_0[68] ; // value method wci_Vm_14_mByteEn assign wci_Vm_14_MByteEn = - wci_sThreadBusy_d_14 ? 4'd0 : wci_reqF_14_q_0[67:64] ; + wci_14_sThreadBusy_d ? 4'd0 : wci_14_reqF_q_0[67:64] ; // value method wci_Vm_14_mAddr assign wci_Vm_14_MAddr = - wci_sThreadBusy_d_14 ? 32'd0 : wci_reqF_14_q_0[63:32] ; + wci_14_sThreadBusy_d ? 32'd0 : wci_14_reqF_q_0[63:32] ; // value method wci_Vm_14_mData - assign wci_Vm_14_MData = wci_reqF_14_q_0[31:0] ; + assign wci_Vm_14_MData = wci_14_reqF_q_0[31:0] ; // value method wci_Vm_14_mFlag - assign wci_Vm_14_MFlag = wci_mFlagReg_14 ; + assign wci_Vm_14_MFlag = wci_14_mFlagReg ; // value method cpNow assign cpNow = timeServ_now ; @@ -5150,6 +5269,13 @@ module mkOCCP(pciDevice, .FULL_N(cpRespF$FULL_N), .EMPTY_N(cpRespF$EMPTY_N)); + // submodule dna_dna + DNA_PORT dna_dna(.CLK(dna_dna$CLK), + .DIN(dna_dna$DIN), + .READ(dna_dna$READ), + .SHIFT(dna_dna$SHIFT), + .DOUT(dna_dna$DOUT)); + // submodule rom_memory BRAM1Load #(.FILENAME("ramprom.data"), .PIPELINED(1'd0), @@ -5268,290 +5394,290 @@ module mkOCCP(pciDevice, .sFULL_N(timeServ_setRefF$sFULL_N), .dEMPTY_N(timeServ_setRefF$dEMPTY_N)); - // submodule wci_mReset - MakeResetA #(.RSTDELAY(32'd16), .init(1'd0)) wci_mReset(.CLK(CLK), - .RST(RST_N), - .DST_CLK(CLK), - .ASSERT_IN(wci_mReset$ASSERT_IN), - .ASSERT_OUT(), - .OUT_RST(wci_mReset$OUT_RST)); - - // submodule wci_mReset_1 - MakeResetA #(.RSTDELAY(32'd16), .init(1'd0)) wci_mReset_1(.CLK(CLK), + // submodule wci_0_mReset + MakeResetA #(.RSTDELAY(32'd16), .init(1'd0)) wci_0_mReset(.CLK(CLK), .RST(RST_N), .DST_CLK(CLK), - .ASSERT_IN(wci_mReset_1$ASSERT_IN), + .ASSERT_IN(wci_0_mReset$ASSERT_IN), .ASSERT_OUT(), - .OUT_RST(wci_mReset_1$OUT_RST)); + .OUT_RST(wci_0_mReset$OUT_RST)); - // submodule wci_mReset_10 - MakeResetA #(.RSTDELAY(32'd16), .init(1'd0)) wci_mReset_10(.CLK(CLK), + // submodule wci_0_respF + FIFO1 #(.width(32'd34), .guarded(32'd1)) wci_0_respF(.RST(RST_N), + .CLK(CLK), + .D_IN(wci_0_respF$D_IN), + .ENQ(wci_0_respF$ENQ), + .DEQ(wci_0_respF$DEQ), + .CLR(wci_0_respF$CLR), + .D_OUT(wci_0_respF$D_OUT), + .FULL_N(wci_0_respF$FULL_N), + .EMPTY_N(wci_0_respF$EMPTY_N)); + + // submodule wci_10_mReset + MakeResetA #(.RSTDELAY(32'd16), .init(1'd0)) wci_10_mReset(.CLK(CLK), .RST(RST_N), .DST_CLK(CLK), - .ASSERT_IN(wci_mReset_10$ASSERT_IN), + .ASSERT_IN(wci_10_mReset$ASSERT_IN), .ASSERT_OUT(), - .OUT_RST(wci_mReset_10$OUT_RST)); + .OUT_RST(wci_10_mReset$OUT_RST)); - // submodule wci_mReset_11 - MakeResetA #(.RSTDELAY(32'd16), .init(1'd0)) wci_mReset_11(.CLK(CLK), + // submodule wci_10_respF + FIFO1 #(.width(32'd34), .guarded(32'd1)) wci_10_respF(.RST(RST_N), + .CLK(CLK), + .D_IN(wci_10_respF$D_IN), + .ENQ(wci_10_respF$ENQ), + .DEQ(wci_10_respF$DEQ), + .CLR(wci_10_respF$CLR), + .D_OUT(wci_10_respF$D_OUT), + .FULL_N(wci_10_respF$FULL_N), + .EMPTY_N(wci_10_respF$EMPTY_N)); + + // submodule wci_11_mReset + MakeResetA #(.RSTDELAY(32'd16), .init(1'd0)) wci_11_mReset(.CLK(CLK), .RST(RST_N), .DST_CLK(CLK), - .ASSERT_IN(wci_mReset_11$ASSERT_IN), + .ASSERT_IN(wci_11_mReset$ASSERT_IN), .ASSERT_OUT(), - .OUT_RST(wci_mReset_11$OUT_RST)); + .OUT_RST(wci_11_mReset$OUT_RST)); - // submodule wci_mReset_12 - MakeResetA #(.RSTDELAY(32'd16), .init(1'd0)) wci_mReset_12(.CLK(CLK), + // submodule wci_11_respF + FIFO1 #(.width(32'd34), .guarded(32'd1)) wci_11_respF(.RST(RST_N), + .CLK(CLK), + .D_IN(wci_11_respF$D_IN), + .ENQ(wci_11_respF$ENQ), + .DEQ(wci_11_respF$DEQ), + .CLR(wci_11_respF$CLR), + .D_OUT(wci_11_respF$D_OUT), + .FULL_N(wci_11_respF$FULL_N), + .EMPTY_N(wci_11_respF$EMPTY_N)); + + // submodule wci_12_mReset + MakeResetA #(.RSTDELAY(32'd16), .init(1'd0)) wci_12_mReset(.CLK(CLK), .RST(RST_N), .DST_CLK(CLK), - .ASSERT_IN(wci_mReset_12$ASSERT_IN), + .ASSERT_IN(wci_12_mReset$ASSERT_IN), .ASSERT_OUT(), - .OUT_RST(wci_mReset_12$OUT_RST)); + .OUT_RST(wci_12_mReset$OUT_RST)); - // submodule wci_mReset_13 - MakeResetA #(.RSTDELAY(32'd16), .init(1'd0)) wci_mReset_13(.CLK(CLK), + // submodule wci_12_respF + FIFO1 #(.width(32'd34), .guarded(32'd1)) wci_12_respF(.RST(RST_N), + .CLK(CLK), + .D_IN(wci_12_respF$D_IN), + .ENQ(wci_12_respF$ENQ), + .DEQ(wci_12_respF$DEQ), + .CLR(wci_12_respF$CLR), + .D_OUT(wci_12_respF$D_OUT), + .FULL_N(wci_12_respF$FULL_N), + .EMPTY_N(wci_12_respF$EMPTY_N)); + + // submodule wci_13_mReset + MakeResetA #(.RSTDELAY(32'd16), .init(1'd0)) wci_13_mReset(.CLK(CLK), .RST(RST_N), .DST_CLK(CLK), - .ASSERT_IN(wci_mReset_13$ASSERT_IN), + .ASSERT_IN(wci_13_mReset$ASSERT_IN), .ASSERT_OUT(), - .OUT_RST(wci_mReset_13$OUT_RST)); + .OUT_RST(wci_13_mReset$OUT_RST)); - // submodule wci_mReset_14 - MakeResetA #(.RSTDELAY(32'd16), .init(1'd0)) wci_mReset_14(.CLK(CLK), + // submodule wci_13_respF + FIFO1 #(.width(32'd34), .guarded(32'd1)) wci_13_respF(.RST(RST_N), + .CLK(CLK), + .D_IN(wci_13_respF$D_IN), + .ENQ(wci_13_respF$ENQ), + .DEQ(wci_13_respF$DEQ), + .CLR(wci_13_respF$CLR), + .D_OUT(wci_13_respF$D_OUT), + .FULL_N(wci_13_respF$FULL_N), + .EMPTY_N(wci_13_respF$EMPTY_N)); + + // submodule wci_14_mReset + MakeResetA #(.RSTDELAY(32'd16), .init(1'd0)) wci_14_mReset(.CLK(CLK), .RST(RST_N), .DST_CLK(CLK), - .ASSERT_IN(wci_mReset_14$ASSERT_IN), + .ASSERT_IN(wci_14_mReset$ASSERT_IN), .ASSERT_OUT(), - .OUT_RST(wci_mReset_14$OUT_RST)); + .OUT_RST(wci_14_mReset$OUT_RST)); - // submodule wci_mReset_2 - MakeResetA #(.RSTDELAY(32'd16), .init(1'd0)) wci_mReset_2(.CLK(CLK), + // submodule wci_14_respF + FIFO1 #(.width(32'd34), .guarded(32'd1)) wci_14_respF(.RST(RST_N), + .CLK(CLK), + .D_IN(wci_14_respF$D_IN), + .ENQ(wci_14_respF$ENQ), + .DEQ(wci_14_respF$DEQ), + .CLR(wci_14_respF$CLR), + .D_OUT(wci_14_respF$D_OUT), + .FULL_N(wci_14_respF$FULL_N), + .EMPTY_N(wci_14_respF$EMPTY_N)); + + // submodule wci_1_mReset + MakeResetA #(.RSTDELAY(32'd16), .init(1'd0)) wci_1_mReset(.CLK(CLK), .RST(RST_N), .DST_CLK(CLK), - .ASSERT_IN(wci_mReset_2$ASSERT_IN), + .ASSERT_IN(wci_1_mReset$ASSERT_IN), .ASSERT_OUT(), - .OUT_RST(wci_mReset_2$OUT_RST)); + .OUT_RST(wci_1_mReset$OUT_RST)); - // submodule wci_mReset_3 - MakeResetA #(.RSTDELAY(32'd16), .init(1'd0)) wci_mReset_3(.CLK(CLK), + // submodule wci_1_respF + FIFO1 #(.width(32'd34), .guarded(32'd1)) wci_1_respF(.RST(RST_N), + .CLK(CLK), + .D_IN(wci_1_respF$D_IN), + .ENQ(wci_1_respF$ENQ), + .DEQ(wci_1_respF$DEQ), + .CLR(wci_1_respF$CLR), + .D_OUT(wci_1_respF$D_OUT), + .FULL_N(wci_1_respF$FULL_N), + .EMPTY_N(wci_1_respF$EMPTY_N)); + + // submodule wci_2_mReset + MakeResetA #(.RSTDELAY(32'd16), .init(1'd0)) wci_2_mReset(.CLK(CLK), .RST(RST_N), .DST_CLK(CLK), - .ASSERT_IN(wci_mReset_3$ASSERT_IN), + .ASSERT_IN(wci_2_mReset$ASSERT_IN), .ASSERT_OUT(), - .OUT_RST(wci_mReset_3$OUT_RST)); + .OUT_RST(wci_2_mReset$OUT_RST)); - // submodule wci_mReset_4 - MakeResetA #(.RSTDELAY(32'd16), .init(1'd0)) wci_mReset_4(.CLK(CLK), + // submodule wci_2_respF + FIFO1 #(.width(32'd34), .guarded(32'd1)) wci_2_respF(.RST(RST_N), + .CLK(CLK), + .D_IN(wci_2_respF$D_IN), + .ENQ(wci_2_respF$ENQ), + .DEQ(wci_2_respF$DEQ), + .CLR(wci_2_respF$CLR), + .D_OUT(wci_2_respF$D_OUT), + .FULL_N(wci_2_respF$FULL_N), + .EMPTY_N(wci_2_respF$EMPTY_N)); + + // submodule wci_3_mReset + MakeResetA #(.RSTDELAY(32'd16), .init(1'd0)) wci_3_mReset(.CLK(CLK), .RST(RST_N), .DST_CLK(CLK), - .ASSERT_IN(wci_mReset_4$ASSERT_IN), + .ASSERT_IN(wci_3_mReset$ASSERT_IN), .ASSERT_OUT(), - .OUT_RST(wci_mReset_4$OUT_RST)); + .OUT_RST(wci_3_mReset$OUT_RST)); - // submodule wci_mReset_5 - MakeResetA #(.RSTDELAY(32'd16), .init(1'd0)) wci_mReset_5(.CLK(CLK), + // submodule wci_3_respF + FIFO1 #(.width(32'd34), .guarded(32'd1)) wci_3_respF(.RST(RST_N), + .CLK(CLK), + .D_IN(wci_3_respF$D_IN), + .ENQ(wci_3_respF$ENQ), + .DEQ(wci_3_respF$DEQ), + .CLR(wci_3_respF$CLR), + .D_OUT(wci_3_respF$D_OUT), + .FULL_N(wci_3_respF$FULL_N), + .EMPTY_N(wci_3_respF$EMPTY_N)); + + // submodule wci_4_mReset + MakeResetA #(.RSTDELAY(32'd16), .init(1'd0)) wci_4_mReset(.CLK(CLK), .RST(RST_N), .DST_CLK(CLK), - .ASSERT_IN(wci_mReset_5$ASSERT_IN), + .ASSERT_IN(wci_4_mReset$ASSERT_IN), .ASSERT_OUT(), - .OUT_RST(wci_mReset_5$OUT_RST)); + .OUT_RST(wci_4_mReset$OUT_RST)); - // submodule wci_mReset_6 - MakeResetA #(.RSTDELAY(32'd16), .init(1'd0)) wci_mReset_6(.CLK(CLK), + // submodule wci_4_respF + FIFO1 #(.width(32'd34), .guarded(32'd1)) wci_4_respF(.RST(RST_N), + .CLK(CLK), + .D_IN(wci_4_respF$D_IN), + .ENQ(wci_4_respF$ENQ), + .DEQ(wci_4_respF$DEQ), + .CLR(wci_4_respF$CLR), + .D_OUT(wci_4_respF$D_OUT), + .FULL_N(wci_4_respF$FULL_N), + .EMPTY_N(wci_4_respF$EMPTY_N)); + + // submodule wci_5_mReset + MakeResetA #(.RSTDELAY(32'd16), .init(1'd0)) wci_5_mReset(.CLK(CLK), .RST(RST_N), .DST_CLK(CLK), - .ASSERT_IN(wci_mReset_6$ASSERT_IN), + .ASSERT_IN(wci_5_mReset$ASSERT_IN), .ASSERT_OUT(), - .OUT_RST(wci_mReset_6$OUT_RST)); + .OUT_RST(wci_5_mReset$OUT_RST)); - // submodule wci_mReset_7 - MakeResetA #(.RSTDELAY(32'd16), .init(1'd0)) wci_mReset_7(.CLK(CLK), + // submodule wci_5_respF + FIFO1 #(.width(32'd34), .guarded(32'd1)) wci_5_respF(.RST(RST_N), + .CLK(CLK), + .D_IN(wci_5_respF$D_IN), + .ENQ(wci_5_respF$ENQ), + .DEQ(wci_5_respF$DEQ), + .CLR(wci_5_respF$CLR), + .D_OUT(wci_5_respF$D_OUT), + .FULL_N(wci_5_respF$FULL_N), + .EMPTY_N(wci_5_respF$EMPTY_N)); + + // submodule wci_6_mReset + MakeResetA #(.RSTDELAY(32'd16), .init(1'd0)) wci_6_mReset(.CLK(CLK), .RST(RST_N), .DST_CLK(CLK), - .ASSERT_IN(wci_mReset_7$ASSERT_IN), + .ASSERT_IN(wci_6_mReset$ASSERT_IN), .ASSERT_OUT(), - .OUT_RST(wci_mReset_7$OUT_RST)); + .OUT_RST(wci_6_mReset$OUT_RST)); - // submodule wci_mReset_8 - MakeResetA #(.RSTDELAY(32'd16), .init(1'd0)) wci_mReset_8(.CLK(CLK), + // submodule wci_6_respF + FIFO1 #(.width(32'd34), .guarded(32'd1)) wci_6_respF(.RST(RST_N), + .CLK(CLK), + .D_IN(wci_6_respF$D_IN), + .ENQ(wci_6_respF$ENQ), + .DEQ(wci_6_respF$DEQ), + .CLR(wci_6_respF$CLR), + .D_OUT(wci_6_respF$D_OUT), + .FULL_N(wci_6_respF$FULL_N), + .EMPTY_N(wci_6_respF$EMPTY_N)); + + // submodule wci_7_mReset + MakeResetA #(.RSTDELAY(32'd16), .init(1'd0)) wci_7_mReset(.CLK(CLK), .RST(RST_N), .DST_CLK(CLK), - .ASSERT_IN(wci_mReset_8$ASSERT_IN), + .ASSERT_IN(wci_7_mReset$ASSERT_IN), .ASSERT_OUT(), - .OUT_RST(wci_mReset_8$OUT_RST)); + .OUT_RST(wci_7_mReset$OUT_RST)); - // submodule wci_mReset_9 - MakeResetA #(.RSTDELAY(32'd16), .init(1'd0)) wci_mReset_9(.CLK(CLK), + // submodule wci_7_respF + FIFO1 #(.width(32'd34), .guarded(32'd1)) wci_7_respF(.RST(RST_N), + .CLK(CLK), + .D_IN(wci_7_respF$D_IN), + .ENQ(wci_7_respF$ENQ), + .DEQ(wci_7_respF$DEQ), + .CLR(wci_7_respF$CLR), + .D_OUT(wci_7_respF$D_OUT), + .FULL_N(wci_7_respF$FULL_N), + .EMPTY_N(wci_7_respF$EMPTY_N)); + + // submodule wci_8_mReset + MakeResetA #(.RSTDELAY(32'd16), .init(1'd0)) wci_8_mReset(.CLK(CLK), .RST(RST_N), .DST_CLK(CLK), - .ASSERT_IN(wci_mReset_9$ASSERT_IN), + .ASSERT_IN(wci_8_mReset$ASSERT_IN), .ASSERT_OUT(), - .OUT_RST(wci_mReset_9$OUT_RST)); - - // submodule wci_respF - FIFO1 #(.width(32'd34), .guarded(32'd1)) wci_respF(.RST(RST_N), - .CLK(CLK), - .D_IN(wci_respF$D_IN), - .ENQ(wci_respF$ENQ), - .DEQ(wci_respF$DEQ), - .CLR(wci_respF$CLR), - .D_OUT(wci_respF$D_OUT), - .FULL_N(wci_respF$FULL_N), - .EMPTY_N(wci_respF$EMPTY_N)); - - // submodule wci_respF_1 - FIFO1 #(.width(32'd34), .guarded(32'd1)) wci_respF_1(.RST(RST_N), - .CLK(CLK), - .D_IN(wci_respF_1$D_IN), - .ENQ(wci_respF_1$ENQ), - .DEQ(wci_respF_1$DEQ), - .CLR(wci_respF_1$CLR), - .D_OUT(wci_respF_1$D_OUT), - .FULL_N(wci_respF_1$FULL_N), - .EMPTY_N(wci_respF_1$EMPTY_N)); - - // submodule wci_respF_10 - FIFO1 #(.width(32'd34), .guarded(32'd1)) wci_respF_10(.RST(RST_N), - .CLK(CLK), - .D_IN(wci_respF_10$D_IN), - .ENQ(wci_respF_10$ENQ), - .DEQ(wci_respF_10$DEQ), - .CLR(wci_respF_10$CLR), - .D_OUT(wci_respF_10$D_OUT), - .FULL_N(wci_respF_10$FULL_N), - .EMPTY_N(wci_respF_10$EMPTY_N)); - - // submodule wci_respF_11 - FIFO1 #(.width(32'd34), .guarded(32'd1)) wci_respF_11(.RST(RST_N), - .CLK(CLK), - .D_IN(wci_respF_11$D_IN), - .ENQ(wci_respF_11$ENQ), - .DEQ(wci_respF_11$DEQ), - .CLR(wci_respF_11$CLR), - .D_OUT(wci_respF_11$D_OUT), - .FULL_N(wci_respF_11$FULL_N), - .EMPTY_N(wci_respF_11$EMPTY_N)); - - // submodule wci_respF_12 - FIFO1 #(.width(32'd34), .guarded(32'd1)) wci_respF_12(.RST(RST_N), - .CLK(CLK), - .D_IN(wci_respF_12$D_IN), - .ENQ(wci_respF_12$ENQ), - .DEQ(wci_respF_12$DEQ), - .CLR(wci_respF_12$CLR), - .D_OUT(wci_respF_12$D_OUT), - .FULL_N(wci_respF_12$FULL_N), - .EMPTY_N(wci_respF_12$EMPTY_N)); - - // submodule wci_respF_13 - FIFO1 #(.width(32'd34), .guarded(32'd1)) wci_respF_13(.RST(RST_N), - .CLK(CLK), - .D_IN(wci_respF_13$D_IN), - .ENQ(wci_respF_13$ENQ), - .DEQ(wci_respF_13$DEQ), - .CLR(wci_respF_13$CLR), - .D_OUT(wci_respF_13$D_OUT), - .FULL_N(wci_respF_13$FULL_N), - .EMPTY_N(wci_respF_13$EMPTY_N)); - - // submodule wci_respF_14 - FIFO1 #(.width(32'd34), .guarded(32'd1)) wci_respF_14(.RST(RST_N), - .CLK(CLK), - .D_IN(wci_respF_14$D_IN), - .ENQ(wci_respF_14$ENQ), - .DEQ(wci_respF_14$DEQ), - .CLR(wci_respF_14$CLR), - .D_OUT(wci_respF_14$D_OUT), - .FULL_N(wci_respF_14$FULL_N), - .EMPTY_N(wci_respF_14$EMPTY_N)); - - // submodule wci_respF_2 - FIFO1 #(.width(32'd34), .guarded(32'd1)) wci_respF_2(.RST(RST_N), - .CLK(CLK), - .D_IN(wci_respF_2$D_IN), - .ENQ(wci_respF_2$ENQ), - .DEQ(wci_respF_2$DEQ), - .CLR(wci_respF_2$CLR), - .D_OUT(wci_respF_2$D_OUT), - .FULL_N(wci_respF_2$FULL_N), - .EMPTY_N(wci_respF_2$EMPTY_N)); - - // submodule wci_respF_3 - FIFO1 #(.width(32'd34), .guarded(32'd1)) wci_respF_3(.RST(RST_N), - .CLK(CLK), - .D_IN(wci_respF_3$D_IN), - .ENQ(wci_respF_3$ENQ), - .DEQ(wci_respF_3$DEQ), - .CLR(wci_respF_3$CLR), - .D_OUT(wci_respF_3$D_OUT), - .FULL_N(wci_respF_3$FULL_N), - .EMPTY_N(wci_respF_3$EMPTY_N)); - - // submodule wci_respF_4 - FIFO1 #(.width(32'd34), .guarded(32'd1)) wci_respF_4(.RST(RST_N), - .CLK(CLK), - .D_IN(wci_respF_4$D_IN), - .ENQ(wci_respF_4$ENQ), - .DEQ(wci_respF_4$DEQ), - .CLR(wci_respF_4$CLR), - .D_OUT(wci_respF_4$D_OUT), - .FULL_N(wci_respF_4$FULL_N), - .EMPTY_N(wci_respF_4$EMPTY_N)); - - // submodule wci_respF_5 - FIFO1 #(.width(32'd34), .guarded(32'd1)) wci_respF_5(.RST(RST_N), - .CLK(CLK), - .D_IN(wci_respF_5$D_IN), - .ENQ(wci_respF_5$ENQ), - .DEQ(wci_respF_5$DEQ), - .CLR(wci_respF_5$CLR), - .D_OUT(wci_respF_5$D_OUT), - .FULL_N(wci_respF_5$FULL_N), - .EMPTY_N(wci_respF_5$EMPTY_N)); - - // submodule wci_respF_6 - FIFO1 #(.width(32'd34), .guarded(32'd1)) wci_respF_6(.RST(RST_N), - .CLK(CLK), - .D_IN(wci_respF_6$D_IN), - .ENQ(wci_respF_6$ENQ), - .DEQ(wci_respF_6$DEQ), - .CLR(wci_respF_6$CLR), - .D_OUT(wci_respF_6$D_OUT), - .FULL_N(wci_respF_6$FULL_N), - .EMPTY_N(wci_respF_6$EMPTY_N)); - - // submodule wci_respF_7 - FIFO1 #(.width(32'd34), .guarded(32'd1)) wci_respF_7(.RST(RST_N), - .CLK(CLK), - .D_IN(wci_respF_7$D_IN), - .ENQ(wci_respF_7$ENQ), - .DEQ(wci_respF_7$DEQ), - .CLR(wci_respF_7$CLR), - .D_OUT(wci_respF_7$D_OUT), - .FULL_N(wci_respF_7$FULL_N), - .EMPTY_N(wci_respF_7$EMPTY_N)); - - // submodule wci_respF_8 - FIFO1 #(.width(32'd34), .guarded(32'd1)) wci_respF_8(.RST(RST_N), + .OUT_RST(wci_8_mReset$OUT_RST)); + + // submodule wci_8_respF + FIFO1 #(.width(32'd34), .guarded(32'd1)) wci_8_respF(.RST(RST_N), .CLK(CLK), - .D_IN(wci_respF_8$D_IN), - .ENQ(wci_respF_8$ENQ), - .DEQ(wci_respF_8$DEQ), - .CLR(wci_respF_8$CLR), - .D_OUT(wci_respF_8$D_OUT), - .FULL_N(wci_respF_8$FULL_N), - .EMPTY_N(wci_respF_8$EMPTY_N)); - - // submodule wci_respF_9 - FIFO1 #(.width(32'd34), .guarded(32'd1)) wci_respF_9(.RST(RST_N), + .D_IN(wci_8_respF$D_IN), + .ENQ(wci_8_respF$ENQ), + .DEQ(wci_8_respF$DEQ), + .CLR(wci_8_respF$CLR), + .D_OUT(wci_8_respF$D_OUT), + .FULL_N(wci_8_respF$FULL_N), + .EMPTY_N(wci_8_respF$EMPTY_N)); + + // submodule wci_9_mReset + MakeResetA #(.RSTDELAY(32'd16), .init(1'd0)) wci_9_mReset(.CLK(CLK), + .RST(RST_N), + .DST_CLK(CLK), + .ASSERT_IN(wci_9_mReset$ASSERT_IN), + .ASSERT_OUT(), + .OUT_RST(wci_9_mReset$OUT_RST)); + + // submodule wci_9_respF + FIFO1 #(.width(32'd34), .guarded(32'd1)) wci_9_respF(.RST(RST_N), .CLK(CLK), - .D_IN(wci_respF_9$D_IN), - .ENQ(wci_respF_9$ENQ), - .DEQ(wci_respF_9$DEQ), - .CLR(wci_respF_9$CLR), - .D_OUT(wci_respF_9$D_OUT), - .FULL_N(wci_respF_9$FULL_N), - .EMPTY_N(wci_respF_9$EMPTY_N)); + .D_IN(wci_9_respF$D_IN), + .ENQ(wci_9_respF$ENQ), + .DEQ(wci_9_respF$DEQ), + .CLR(wci_9_respF$CLR), + .D_OUT(wci_9_respF$D_OUT), + .FULL_N(wci_9_respF$FULL_N), + .EMPTY_N(wci_9_respF$EMPTY_N)); // rule RL_readAdminResponseCollect assign WILL_FIRE_RL_readAdminResponseCollect = @@ -5618,8 +5744,8 @@ module mkOCCP(pciDevice, // rule RL_cpDispatch_F_T_T_T assign CAN_FIRE_RL_cpDispatch_F_T_T_T = cpReq[64:62] == 3'd2 && - cpReq_337_BITS_27_TO_4_410_ULT_0x100___d2411 && - cpReq_337_BITS_11_TO_4_340_ULT_0x30___d2412 && + cpReq_363_BITS_27_TO_4_436_ULT_0x100___d2437 && + cpReq_363_BITS_11_TO_4_366_ULT_0x30___d2438 && adminResp1F$FULL_N && !dispatched ; assign WILL_FIRE_RL_cpDispatch_F_T_T_T = @@ -5628,10 +5754,10 @@ module mkOCCP(pciDevice, // rule RL_cpDispatch_F_T_T_F_T_T assign CAN_FIRE_RL_cpDispatch_F_T_T_F_T_T = cpReq[64:62] == 3'd2 && - cpReq_337_BITS_27_TO_4_410_ULT_0x100___d2411 && - !cpReq_337_BITS_11_TO_4_340_ULT_0x30___d2412 && - cpReq_337_BITS_11_TO_4_340_ULT_0xC0___d2568 && - cpReq_337_BITS_11_TO_4_340_EQ_0x30_569_OR_cpRe_ETC___d2606 ; + cpReq_363_BITS_27_TO_4_436_ULT_0x100___d2437 && + !cpReq_363_BITS_11_TO_4_366_ULT_0x30___d2438 && + cpReq_363_BITS_11_TO_4_366_ULT_0xC0___d2594 && + cpReq_363_BITS_11_TO_4_366_EQ_0x30_595_OR_cpRe_ETC___d2632 ; assign WILL_FIRE_RL_cpDispatch_F_T_T_F_T_T = CAN_FIRE_RL_cpDispatch_F_T_T_F_T_T && !WILL_FIRE_RL_responseAdminRd ; @@ -5639,9 +5765,9 @@ module mkOCCP(pciDevice, // rule RL_cpDispatch_F_T_T_F_T_F_T assign CAN_FIRE_RL_cpDispatch_F_T_T_F_T_F_T = cpReq[64:62] == 3'd2 && - cpReq_337_BITS_27_TO_4_410_ULT_0x100___d2411 && - !cpReq_337_BITS_11_TO_4_340_ULT_0x30___d2412 && - cpReq_337_BITS_11_TO_4_340_ULT_0xC0___d2568 && + cpReq_363_BITS_27_TO_4_436_ULT_0x100___d2437 && + !cpReq_363_BITS_11_TO_4_366_ULT_0x30___d2438 && + cpReq_363_BITS_11_TO_4_366_ULT_0xC0___d2594 && cpReq[11:4] == 8'h4C && adminResp2F$FULL_N && !dispatched ; @@ -5652,10 +5778,10 @@ module mkOCCP(pciDevice, // rule RL_cpDispatch_F_T_T_F_T_F_F assign CAN_FIRE_RL_cpDispatch_F_T_T_F_T_F_F = cpReq[64:62] == 3'd2 && - cpReq_337_BITS_27_TO_4_410_ULT_0x100___d2411 && - !cpReq_337_BITS_11_TO_4_340_ULT_0x30___d2412 && - cpReq_337_BITS_11_TO_4_340_ULT_0xC0___d2568 && - NOT_cpReq_337_BITS_11_TO_4_340_EQ_0x30_569_623_ETC___d2686 ; + cpReq_363_BITS_27_TO_4_436_ULT_0x100___d2437 && + !cpReq_363_BITS_11_TO_4_366_ULT_0x30___d2438 && + cpReq_363_BITS_11_TO_4_366_ULT_0xC0___d2594 && + NOT_cpReq_363_BITS_11_TO_4_366_EQ_0x30_595_649_ETC___d2712 ; assign WILL_FIRE_RL_cpDispatch_F_T_T_F_T_F_F = CAN_FIRE_RL_cpDispatch_F_T_T_F_T_F_F && !WILL_FIRE_RL_responseAdminRd ; @@ -5663,9 +5789,9 @@ module mkOCCP(pciDevice, // rule RL_cpDispatch_F_T_T_F_F assign CAN_FIRE_RL_cpDispatch_F_T_T_F_F = cpReq[64:62] == 3'd2 && - cpReq_337_BITS_27_TO_4_410_ULT_0x100___d2411 && - !cpReq_337_BITS_11_TO_4_340_ULT_0x30___d2412 && - !cpReq_337_BITS_11_TO_4_340_ULT_0xC0___d2568 && + cpReq_363_BITS_27_TO_4_436_ULT_0x100___d2437 && + !cpReq_363_BITS_11_TO_4_366_ULT_0x30___d2438 && + !cpReq_363_BITS_11_TO_4_366_ULT_0xC0___d2594 && adminResp3F$FULL_N && !dispatched ; assign WILL_FIRE_RL_cpDispatch_F_T_T_F_F = @@ -5675,1653 +5801,1595 @@ module mkOCCP(pciDevice, // rule RL_cpDispatch_F_T_F_T assign WILL_FIRE_RL_cpDispatch_F_T_F_T = cpReq[64:62] == 3'd2 && - !cpReq_337_BITS_27_TO_4_410_ULT_0x100___d2411 && - cpReq_337_BITS_27_TO_4_410_ULT_0x1000___d2840 && + !cpReq_363_BITS_27_TO_4_436_ULT_0x100___d2437 && + cpReq_363_BITS_27_TO_4_436_ULT_0x1000___d2836 && !dispatched && !WILL_FIRE_RL_responseAdminRd ; // rule RL_cpDispatch_F_T_F_F assign CAN_FIRE_RL_cpDispatch_F_T_F_F = cpReq[64:62] == 3'd2 && - !cpReq_337_BITS_27_TO_4_410_ULT_0x100___d2411 && - !cpReq_337_BITS_27_TO_4_410_ULT_0x1000___d2840 && + !cpReq_363_BITS_27_TO_4_436_ULT_0x100___d2437 && + !cpReq_363_BITS_27_TO_4_436_ULT_0x1000___d2836 && (rom_serverAdapter_cnt ^ 3'h4) < 3'd7 && !dispatched ; - // rule RL_cpDispatch_F_F_T_T_T_F - assign WILL_FIRE_RL_cpDispatch_F_F_T_T_T_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h75857 == 4'd0 && + // rule RL_cpDispatch_F_F_T_E0_T_F + assign WILL_FIRE_RL_cpDispatch_F_F_T_E0_T_F = + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd0 && cpReq[61:60] == 2'd2 && - !wci_wReset_n && - NOT_wci_busy_10_860_AND_wci_wReset_n_90_OR_wci_ETC___d2878 ; + !wci_0_wReset_n && + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d2961 && + !dispatched ; - // rule RL_cpDispatch_F_F_T_T_F_T - assign WILL_FIRE_RL_cpDispatch_F_F_T_T_F_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h75857 == 4'd0 && + // rule RL_cpDispatch_F_F_T_E0_F_T + assign WILL_FIRE_RL_cpDispatch_F_F_T_E0_F_T = + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd0 && cpReq[61:60] == 2'd1 && cpReq[19:9] == 11'd0 && - !wci_busy && - wci_respF$FULL_N && + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d2986 && !dispatched ; - // rule RL_cpDispatch_F_F_T_T_F_F_F_T - assign WILL_FIRE_RL_cpDispatch_F_F_T_T_F_F_F_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h75857 == 4'd0 && + // rule RL_cpDispatch_F_F_T_E0_F_F_F_T + assign WILL_FIRE_RL_cpDispatch_F_F_T_E0_F_F_F_T = + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd0 && cpReq[61:60] != 2'd2 && - (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && - cpReq_337_BITS_9_TO_6_770_EQ_0xC_809_AND_NOT_w_ETC___d2927 ; + NOT_cpReq_363_BITS_61_TO_60_848_EQ_1_967_993_O_ETC___d3029 ; - // rule RL_cpDispatch_F_F_T_T_F_F_F_F - assign WILL_FIRE_RL_cpDispatch_F_F_T_T_F_F_F_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h75857 == 4'd0 && + // rule RL_cpDispatch_F_F_T_E0_F_F_F_F + assign WILL_FIRE_RL_cpDispatch_F_F_T_E0_F_F_F_F = + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd0 && cpReq[61:60] != 2'd2 && - (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && - cpReq[9:6] != 4'h9 && - NOT_cpReq_337_BITS_9_TO_6_770_EQ_0xC_809_935_A_ETC___d2936 ; + NOT_cpReq_363_BITS_61_TO_60_848_EQ_1_967_993_O_ETC___d3039 ; - // rule RL_cpDispatch_F_F_T_F_T_T_F - assign WILL_FIRE_RL_cpDispatch_F_F_T_F_T_T_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h75857 == 4'd1 && + // rule RL_cpDispatch_F_F_T_E1_T_F + assign WILL_FIRE_RL_cpDispatch_F_F_T_E1_T_F = + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd1 && cpReq[61:60] == 2'd2 && - !wci_wReset_n_1 && - NOT_wci_busy_1_50_943_AND_wci_wReset_n_1_30_OR_ETC___d2956 ; + !wci_1_wReset_n && + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3060 && + !dispatched ; - // rule RL_cpDispatch_F_F_T_F_T_F_T - assign WILL_FIRE_RL_cpDispatch_F_F_T_F_T_F_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h75857 == 4'd1 && + // rule RL_cpDispatch_F_F_T_E1_F_T + assign WILL_FIRE_RL_cpDispatch_F_F_T_E1_F_T = + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd1 && cpReq[61:60] == 2'd1 && cpReq[19:9] == 11'd0 && - !wci_busy_1 && - wci_respF_1$FULL_N && + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d2986 && !dispatched ; - // rule RL_cpDispatch_F_F_T_F_T_F_F_F_T - assign WILL_FIRE_RL_cpDispatch_F_F_T_F_T_F_F_F_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h75857 == 4'd1 && + // rule RL_cpDispatch_F_F_T_E1_F_F_F_T + assign WILL_FIRE_RL_cpDispatch_F_F_T_E1_F_F_F_T = + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd1 && cpReq[61:60] != 2'd2 && - (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && - cpReq_337_BITS_9_TO_6_770_EQ_0xC_809_AND_NOT_w_ETC___d2993 ; + NOT_cpReq_363_BITS_61_TO_60_848_EQ_1_967_993_O_ETC___d3029 ; - // rule RL_cpDispatch_F_F_T_F_T_F_F_F_F - assign WILL_FIRE_RL_cpDispatch_F_F_T_F_T_F_F_F_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h75857 == 4'd1 && + // rule RL_cpDispatch_F_F_T_E1_F_F_F_F + assign WILL_FIRE_RL_cpDispatch_F_F_T_E1_F_F_F_F = + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd1 && cpReq[61:60] != 2'd2 && - (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && - cpReq[9:6] != 4'h9 && - NOT_cpReq_337_BITS_9_TO_6_770_EQ_0xC_809_935_A_ETC___d2999 ; + NOT_cpReq_363_BITS_61_TO_60_848_EQ_1_967_993_O_ETC___d3039 ; - // rule RL_cpDispatch_F_F_T_F_F_T_T_F - assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_T_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h75857 == 4'd2 && + // rule RL_cpDispatch_F_F_T_E2_T_F + assign WILL_FIRE_RL_cpDispatch_F_F_T_E2_T_F = + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd2 && cpReq[61:60] == 2'd2 && - !wci_wReset_n_2 && - NOT_wci_busy_2_90_006_AND_wci_wReset_n_2_70_OR_ETC___d3019 ; + !wci_2_wReset_n && + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3096 && + !dispatched ; - // rule RL_cpDispatch_F_F_T_F_F_T_F_T - assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_F_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h75857 == 4'd2 && + // rule RL_cpDispatch_F_F_T_E2_F_T + assign WILL_FIRE_RL_cpDispatch_F_F_T_E2_F_T = + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd2 && cpReq[61:60] == 2'd1 && cpReq[19:9] == 11'd0 && - !wci_busy_2 && - wci_respF_2$FULL_N && + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d2986 && !dispatched ; - // rule RL_cpDispatch_F_F_T_F_F_T_F_F_F_T - assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_F_F_F_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h75857 == 4'd2 && + // rule RL_cpDispatch_F_F_T_E2_F_F_F_T + assign WILL_FIRE_RL_cpDispatch_F_F_T_E2_F_F_F_T = + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd2 && cpReq[61:60] != 2'd2 && - (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && - cpReq_337_BITS_9_TO_6_770_EQ_0xC_809_AND_NOT_w_ETC___d3056 ; + NOT_cpReq_363_BITS_61_TO_60_848_EQ_1_967_993_O_ETC___d3029 ; - // rule RL_cpDispatch_F_F_T_F_F_T_F_F_F_F - assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_F_F_F_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h75857 == 4'd2 && + // rule RL_cpDispatch_F_F_T_E2_F_F_F_F + assign WILL_FIRE_RL_cpDispatch_F_F_T_E2_F_F_F_F = + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd2 && cpReq[61:60] != 2'd2 && - (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && - cpReq[9:6] != 4'h9 && - NOT_cpReq_337_BITS_9_TO_6_770_EQ_0xC_809_935_A_ETC___d3062 ; + NOT_cpReq_363_BITS_61_TO_60_848_EQ_1_967_993_O_ETC___d3039 ; - // rule RL_cpDispatch_F_F_T_F_F_F_T_T_F - assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_T_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h75857 == 4'd3 && + // rule RL_cpDispatch_F_F_T_E3_T_F + assign WILL_FIRE_RL_cpDispatch_F_F_T_E3_T_F = + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd3 && cpReq[61:60] == 2'd2 && - !wci_wReset_n_3 && - NOT_wci_busy_3_30_069_AND_wci_wReset_n_3_10_OR_ETC___d3082 ; + !wci_3_wReset_n && + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3132 && + !dispatched ; - // rule RL_cpDispatch_F_F_T_F_F_F_T_F_T - assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_F_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h75857 == 4'd3 && + // rule RL_cpDispatch_F_F_T_E3_F_T + assign WILL_FIRE_RL_cpDispatch_F_F_T_E3_F_T = + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd3 && cpReq[61:60] == 2'd1 && cpReq[19:9] == 11'd0 && - !wci_busy_3 && - wci_respF_3$FULL_N && + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d2986 && !dispatched ; - // rule RL_cpDispatch_F_F_T_F_F_F_T_F_F_F_T - assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_F_F_F_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h75857 == 4'd3 && + // rule RL_cpDispatch_F_F_T_E3_F_F_F_T + assign WILL_FIRE_RL_cpDispatch_F_F_T_E3_F_F_F_T = + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd3 && cpReq[61:60] != 2'd2 && - (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && - cpReq_337_BITS_9_TO_6_770_EQ_0xC_809_AND_NOT_w_ETC___d3119 ; + NOT_cpReq_363_BITS_61_TO_60_848_EQ_1_967_993_O_ETC___d3029 ; - // rule RL_cpDispatch_F_F_T_F_F_F_T_F_F_F_F - assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_F_F_F_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h75857 == 4'd3 && + // rule RL_cpDispatch_F_F_T_E3_F_F_F_F + assign WILL_FIRE_RL_cpDispatch_F_F_T_E3_F_F_F_F = + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd3 && cpReq[61:60] != 2'd2 && - (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && - cpReq[9:6] != 4'h9 && - NOT_cpReq_337_BITS_9_TO_6_770_EQ_0xC_809_935_A_ETC___d3125 ; + NOT_cpReq_363_BITS_61_TO_60_848_EQ_1_967_993_O_ETC___d3039 ; - // rule RL_cpDispatch_F_F_T_F_F_F_F_T_T_F - assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_T_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h75857 == 4'd4 && + // rule RL_cpDispatch_F_F_T_E4_T_F + assign WILL_FIRE_RL_cpDispatch_F_F_T_E4_T_F = + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd4 && cpReq[61:60] == 2'd2 && - !wci_wReset_n_4 && - NOT_wci_busy_4_70_132_AND_wci_wReset_n_4_50_OR_ETC___d3145 ; + !wci_4_wReset_n && + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3168 && + !dispatched ; - // rule RL_cpDispatch_F_F_T_F_F_F_F_T_F_T - assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_F_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h75857 == 4'd4 && + // rule RL_cpDispatch_F_F_T_E4_F_T + assign WILL_FIRE_RL_cpDispatch_F_F_T_E4_F_T = + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd4 && cpReq[61:60] == 2'd1 && cpReq[19:9] == 11'd0 && - !wci_busy_4 && - wci_respF_4$FULL_N && + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d2986 && !dispatched ; - // rule RL_cpDispatch_F_F_T_F_F_F_F_T_F_F_F_T - assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_F_F_F_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h75857 == 4'd4 && + // rule RL_cpDispatch_F_F_T_E4_F_F_F_T + assign WILL_FIRE_RL_cpDispatch_F_F_T_E4_F_F_F_T = + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd4 && cpReq[61:60] != 2'd2 && - (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && - cpReq_337_BITS_9_TO_6_770_EQ_0xC_809_AND_NOT_w_ETC___d3182 ; + NOT_cpReq_363_BITS_61_TO_60_848_EQ_1_967_993_O_ETC___d3029 ; - // rule RL_cpDispatch_F_F_T_F_F_F_F_T_F_F_F_F - assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_F_F_F_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h75857 == 4'd4 && + // rule RL_cpDispatch_F_F_T_E4_F_F_F_F + assign WILL_FIRE_RL_cpDispatch_F_F_T_E4_F_F_F_F = + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd4 && cpReq[61:60] != 2'd2 && - (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && - cpReq[9:6] != 4'h9 && - NOT_cpReq_337_BITS_9_TO_6_770_EQ_0xC_809_935_A_ETC___d3188 ; + NOT_cpReq_363_BITS_61_TO_60_848_EQ_1_967_993_O_ETC___d3039 ; - // rule RL_cpDispatch_F_F_T_F_F_F_F_F_T_T_F - assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_T_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h75857 == 4'd5 && + // rule RL_cpDispatch_F_F_T_E5_T_F + assign WILL_FIRE_RL_cpDispatch_F_F_T_E5_T_F = + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd5 && cpReq[61:60] == 2'd2 && - !wci_wReset_n_5 && - NOT_wci_busy_5_10_195_AND_wci_wReset_n_5_90_OR_ETC___d3208 ; + !wci_5_wReset_n && + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3204 && + !dispatched ; - // rule RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_T - assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h75857 == 4'd5 && + // rule RL_cpDispatch_F_F_T_E5_F_T + assign WILL_FIRE_RL_cpDispatch_F_F_T_E5_F_T = + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd5 && cpReq[61:60] == 2'd1 && cpReq[19:9] == 11'd0 && - !wci_busy_5 && - wci_respF_5$FULL_N && + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d2986 && !dispatched ; - // rule RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_F_F_T - assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_F_F_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h75857 == 4'd5 && + // rule RL_cpDispatch_F_F_T_E5_F_F_F_T + assign WILL_FIRE_RL_cpDispatch_F_F_T_E5_F_F_F_T = + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd5 && cpReq[61:60] != 2'd2 && - (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && - cpReq_337_BITS_9_TO_6_770_EQ_0xC_809_AND_NOT_w_ETC___d3245 ; + NOT_cpReq_363_BITS_61_TO_60_848_EQ_1_967_993_O_ETC___d3029 ; - // rule RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_F_F_F - assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_F_F_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h75857 == 4'd5 && + // rule RL_cpDispatch_F_F_T_E5_F_F_F_F + assign WILL_FIRE_RL_cpDispatch_F_F_T_E5_F_F_F_F = + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd5 && cpReq[61:60] != 2'd2 && - (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && - cpReq[9:6] != 4'h9 && - NOT_cpReq_337_BITS_9_TO_6_770_EQ_0xC_809_935_A_ETC___d3251 ; + NOT_cpReq_363_BITS_61_TO_60_848_EQ_1_967_993_O_ETC___d3039 ; - // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_T_F - assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_T_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h75857 == 4'd6 && + // rule RL_cpDispatch_F_F_T_E6_T_F + assign WILL_FIRE_RL_cpDispatch_F_F_T_E6_T_F = + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd6 && cpReq[61:60] == 2'd2 && - !wci_wReset_n_6 && - NOT_wci_busy_6_050_258_AND_wci_wReset_n_6_030__ETC___d3271 ; + !wci_6_wReset_n && + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3240 && + !dispatched ; - // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_F_T - assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_F_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h75857 == 4'd6 && + // rule RL_cpDispatch_F_F_T_E6_F_T + assign WILL_FIRE_RL_cpDispatch_F_F_T_E6_F_T = + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd6 && cpReq[61:60] == 2'd1 && cpReq[19:9] == 11'd0 && - !wci_busy_6 && - wci_respF_6$FULL_N && + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d2986 && !dispatched ; - // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_F_F_F_T - assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_F_F_F_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h75857 == 4'd6 && + // rule RL_cpDispatch_F_F_T_E6_F_F_F_T + assign WILL_FIRE_RL_cpDispatch_F_F_T_E6_F_F_F_T = + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd6 && cpReq[61:60] != 2'd2 && - (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && - cpReq_337_BITS_9_TO_6_770_EQ_0xC_809_AND_NOT_w_ETC___d3308 ; + NOT_cpReq_363_BITS_61_TO_60_848_EQ_1_967_993_O_ETC___d3029 ; - // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_F_F_F_F - assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_F_F_F_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h75857 == 4'd6 && + // rule RL_cpDispatch_F_F_T_E6_F_F_F_F + assign WILL_FIRE_RL_cpDispatch_F_F_T_E6_F_F_F_F = + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd6 && cpReq[61:60] != 2'd2 && - (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && - cpReq[9:6] != 4'h9 && - NOT_cpReq_337_BITS_9_TO_6_770_EQ_0xC_809_935_A_ETC___d3314 ; + NOT_cpReq_363_BITS_61_TO_60_848_EQ_1_967_993_O_ETC___d3039 ; - // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_T_F - assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_T_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h75857 == 4'd7 && + // rule RL_cpDispatch_F_F_T_E7_T_F + assign WILL_FIRE_RL_cpDispatch_F_F_T_E7_T_F = + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd7 && cpReq[61:60] == 2'd2 && - !wci_wReset_n_7 && - NOT_wci_busy_7_190_321_AND_wci_wReset_n_7_170__ETC___d3334 ; + !wci_7_wReset_n && + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3276 && + !dispatched ; - // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_F_T - assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_F_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h75857 == 4'd7 && + // rule RL_cpDispatch_F_F_T_E7_F_T + assign WILL_FIRE_RL_cpDispatch_F_F_T_E7_F_T = + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd7 && cpReq[61:60] == 2'd1 && cpReq[19:9] == 11'd0 && - !wci_busy_7 && - wci_respF_7$FULL_N && + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d2986 && !dispatched ; - // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_F_F_F_T - assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_F_F_F_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h75857 == 4'd7 && + // rule RL_cpDispatch_F_F_T_E7_F_F_F_T + assign WILL_FIRE_RL_cpDispatch_F_F_T_E7_F_F_F_T = + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd7 && cpReq[61:60] != 2'd2 && - (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && - cpReq_337_BITS_9_TO_6_770_EQ_0xC_809_AND_NOT_w_ETC___d3371 ; + NOT_cpReq_363_BITS_61_TO_60_848_EQ_1_967_993_O_ETC___d3029 ; - // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_F_F_F_F - assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_F_F_F_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h75857 == 4'd7 && + // rule RL_cpDispatch_F_F_T_E7_F_F_F_F + assign WILL_FIRE_RL_cpDispatch_F_F_T_E7_F_F_F_F = + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd7 && cpReq[61:60] != 2'd2 && - (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && - cpReq[9:6] != 4'h9 && - NOT_cpReq_337_BITS_9_TO_6_770_EQ_0xC_809_935_A_ETC___d3377 ; + NOT_cpReq_363_BITS_61_TO_60_848_EQ_1_967_993_O_ETC___d3039 ; - // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_T_F - assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_T_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h75857 == 4'd8 && + // rule RL_cpDispatch_F_F_T_E8_T_F + assign WILL_FIRE_RL_cpDispatch_F_F_T_E8_T_F = + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd8 && cpReq[61:60] == 2'd2 && - !wci_wReset_n_8 && - NOT_wci_busy_8_330_384_AND_wci_wReset_n_8_310__ETC___d3397 ; + !wci_8_wReset_n && + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3312 && + !dispatched ; - // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_F_T - assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_F_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h75857 == 4'd8 && + // rule RL_cpDispatch_F_F_T_E8_F_T + assign WILL_FIRE_RL_cpDispatch_F_F_T_E8_F_T = + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd8 && cpReq[61:60] == 2'd1 && cpReq[19:9] == 11'd0 && - !wci_busy_8 && - wci_respF_8$FULL_N && + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d2986 && !dispatched ; - // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_F_F_F_T - assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_F_F_F_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h75857 == 4'd8 && + // rule RL_cpDispatch_F_F_T_E8_F_F_F_T + assign WILL_FIRE_RL_cpDispatch_F_F_T_E8_F_F_F_T = + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd8 && cpReq[61:60] != 2'd2 && - (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && - cpReq_337_BITS_9_TO_6_770_EQ_0xC_809_AND_NOT_w_ETC___d3434 ; + NOT_cpReq_363_BITS_61_TO_60_848_EQ_1_967_993_O_ETC___d3029 ; - // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_F_F_F_F - assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_F_F_F_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h75857 == 4'd8 && + // rule RL_cpDispatch_F_F_T_E8_F_F_F_F + assign WILL_FIRE_RL_cpDispatch_F_F_T_E8_F_F_F_F = + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd8 && cpReq[61:60] != 2'd2 && - (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && - cpReq[9:6] != 4'h9 && - NOT_cpReq_337_BITS_9_TO_6_770_EQ_0xC_809_935_A_ETC___d3440 ; + NOT_cpReq_363_BITS_61_TO_60_848_EQ_1_967_993_O_ETC___d3039 ; - // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_T_F - assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_T_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h75857 == 4'd9 && + // rule RL_cpDispatch_F_F_T_E9_T_F + assign WILL_FIRE_RL_cpDispatch_F_F_T_E9_T_F = + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd9 && cpReq[61:60] == 2'd2 && - !wci_wReset_n_9 && - NOT_wci_busy_9_470_447_AND_wci_wReset_n_9_450__ETC___d3460 ; + !wci_9_wReset_n && + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3348 && + !dispatched ; - // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_F_T - assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_F_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h75857 == 4'd9 && + // rule RL_cpDispatch_F_F_T_E9_F_T + assign WILL_FIRE_RL_cpDispatch_F_F_T_E9_F_T = + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd9 && cpReq[61:60] == 2'd1 && cpReq[19:9] == 11'd0 && - !wci_busy_9 && - wci_respF_9$FULL_N && + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d2986 && !dispatched ; - // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_F_F_F_T - assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_F_F_F_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h75857 == 4'd9 && + // rule RL_cpDispatch_F_F_T_E9_F_F_F_T + assign WILL_FIRE_RL_cpDispatch_F_F_T_E9_F_F_F_T = + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd9 && cpReq[61:60] != 2'd2 && - (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && - cpReq_337_BITS_9_TO_6_770_EQ_0xC_809_AND_NOT_w_ETC___d3497 ; + NOT_cpReq_363_BITS_61_TO_60_848_EQ_1_967_993_O_ETC___d3029 ; - // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_F_F_F_F - assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_F_F_F_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h75857 == 4'd9 && + // rule RL_cpDispatch_F_F_T_E9_F_F_F_F + assign WILL_FIRE_RL_cpDispatch_F_F_T_E9_F_F_F_F = + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd9 && cpReq[61:60] != 2'd2 && - (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && - cpReq[9:6] != 4'h9 && - NOT_cpReq_337_BITS_9_TO_6_770_EQ_0xC_809_935_A_ETC___d3503 ; + NOT_cpReq_363_BITS_61_TO_60_848_EQ_1_967_993_O_ETC___d3039 ; - // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_T_F - assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_T_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h75857 == 4'd10 && + // rule RL_cpDispatch_F_F_T_E10_T_F + assign WILL_FIRE_RL_cpDispatch_F_F_T_E10_T_F = + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd10 && cpReq[61:60] == 2'd2 && - !wci_wReset_n_10 && - NOT_wci_busy_10_610_510_AND_wci_wReset_n_10_59_ETC___d3523 ; + !wci_10_wReset_n && + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3384 && + !dispatched ; - // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_T - assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h75857 == 4'd10 && + // rule RL_cpDispatch_F_F_T_E10_F_T + assign WILL_FIRE_RL_cpDispatch_F_F_T_E10_F_T = + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd10 && cpReq[61:60] == 2'd1 && cpReq[19:9] == 11'd0 && - !wci_busy_10 && - wci_respF_10$FULL_N && + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d2986 && !dispatched ; - // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T - assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h75857 == 4'd10 && + // rule RL_cpDispatch_F_F_T_E10_F_F_F_T + assign WILL_FIRE_RL_cpDispatch_F_F_T_E10_F_F_F_T = + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd10 && cpReq[61:60] != 2'd2 && - (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && - cpReq_337_BITS_9_TO_6_770_EQ_0xC_809_AND_NOT_w_ETC___d3560 ; + NOT_cpReq_363_BITS_61_TO_60_848_EQ_1_967_993_O_ETC___d3029 ; - // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F - assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h75857 == 4'd10 && + // rule RL_cpDispatch_F_F_T_E10_F_F_F_F + assign WILL_FIRE_RL_cpDispatch_F_F_T_E10_F_F_F_F = + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd10 && cpReq[61:60] != 2'd2 && - (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && - cpReq[9:6] != 4'h9 && - NOT_cpReq_337_BITS_9_TO_6_770_EQ_0xC_809_935_A_ETC___d3566 ; + NOT_cpReq_363_BITS_61_TO_60_848_EQ_1_967_993_O_ETC___d3039 ; - // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_T_F - assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_T_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h75857 == 4'd11 && + // rule RL_cpDispatch_F_F_T_E11_T_F + assign WILL_FIRE_RL_cpDispatch_F_F_T_E11_T_F = + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd11 && cpReq[61:60] == 2'd2 && - !wci_wReset_n_11 && - NOT_wci_busy_11_750_573_AND_wci_wReset_n_11_73_ETC___d3586 ; + !wci_11_wReset_n && + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3420 && + !dispatched ; - // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_F_T - assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_F_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h75857 == 4'd11 && + // rule RL_cpDispatch_F_F_T_E11_F_T + assign WILL_FIRE_RL_cpDispatch_F_F_T_E11_F_T = + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd11 && cpReq[61:60] == 2'd1 && cpReq[19:9] == 11'd0 && - !wci_busy_11 && - wci_respF_11$FULL_N && + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d2986 && !dispatched ; - // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T - assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h75857 == 4'd11 && + // rule RL_cpDispatch_F_F_T_E11_F_F_F_T + assign WILL_FIRE_RL_cpDispatch_F_F_T_E11_F_F_F_T = + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd11 && cpReq[61:60] != 2'd2 && - (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && - cpReq_337_BITS_9_TO_6_770_EQ_0xC_809_AND_NOT_w_ETC___d3623 ; + NOT_cpReq_363_BITS_61_TO_60_848_EQ_1_967_993_O_ETC___d3029 ; - // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F - assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h75857 == 4'd11 && + // rule RL_cpDispatch_F_F_T_E11_F_F_F_F + assign WILL_FIRE_RL_cpDispatch_F_F_T_E11_F_F_F_F = + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd11 && cpReq[61:60] != 2'd2 && - (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && - cpReq[9:6] != 4'h9 && - NOT_cpReq_337_BITS_9_TO_6_770_EQ_0xC_809_935_A_ETC___d3629 ; + NOT_cpReq_363_BITS_61_TO_60_848_EQ_1_967_993_O_ETC___d3039 ; - // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F - assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h75857 == 4'd12 && + // rule RL_cpDispatch_F_F_T_E12_T_F + assign WILL_FIRE_RL_cpDispatch_F_F_T_E12_T_F = + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd12 && cpReq[61:60] == 2'd2 && - !wci_wReset_n_12 && - NOT_wci_busy_12_890_636_AND_wci_wReset_n_12_87_ETC___d3649 ; + !wci_12_wReset_n && + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3456 && + !dispatched ; - // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T - assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h75857 == 4'd12 && + // rule RL_cpDispatch_F_F_T_E12_F_T + assign WILL_FIRE_RL_cpDispatch_F_F_T_E12_F_T = + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd12 && cpReq[61:60] == 2'd1 && cpReq[19:9] == 11'd0 && - !wci_busy_12 && - wci_respF_12$FULL_N && + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d2986 && !dispatched ; - // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T - assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h75857 == 4'd12 && + // rule RL_cpDispatch_F_F_T_E12_F_F_F_T + assign WILL_FIRE_RL_cpDispatch_F_F_T_E12_F_F_F_T = + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd12 && cpReq[61:60] != 2'd2 && - (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && - cpReq_337_BITS_9_TO_6_770_EQ_0xC_809_AND_NOT_w_ETC___d3686 ; + NOT_cpReq_363_BITS_61_TO_60_848_EQ_1_967_993_O_ETC___d3029 ; - // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F - assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h75857 == 4'd12 && + // rule RL_cpDispatch_F_F_T_E12_F_F_F_F + assign WILL_FIRE_RL_cpDispatch_F_F_T_E12_F_F_F_F = + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd12 && cpReq[61:60] != 2'd2 && - (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && - cpReq[9:6] != 4'h9 && - NOT_cpReq_337_BITS_9_TO_6_770_EQ_0xC_809_935_A_ETC___d3692 ; + NOT_cpReq_363_BITS_61_TO_60_848_EQ_1_967_993_O_ETC___d3039 ; - // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F - assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h75857 == 4'd13 && + // rule RL_cpDispatch_F_F_T_E13_T_F + assign WILL_FIRE_RL_cpDispatch_F_F_T_E13_T_F = + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd13 && cpReq[61:60] == 2'd2 && - !wci_wReset_n_13 && - NOT_wci_busy_13_030_699_AND_wci_wReset_n_13_01_ETC___d3712 ; + !wci_13_wReset_n && + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3492 && + !dispatched ; - // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T - assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h75857 == 4'd13 && + // rule RL_cpDispatch_F_F_T_E13_F_T + assign WILL_FIRE_RL_cpDispatch_F_F_T_E13_F_T = + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd13 && cpReq[61:60] == 2'd1 && cpReq[19:9] == 11'd0 && - !wci_busy_13 && - wci_respF_13$FULL_N && + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d2986 && !dispatched ; - // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T - assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h75857 == 4'd13 && + // rule RL_cpDispatch_F_F_T_E13_F_F_F_T + assign WILL_FIRE_RL_cpDispatch_F_F_T_E13_F_F_F_T = + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd13 && cpReq[61:60] != 2'd2 && - (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && - cpReq_337_BITS_9_TO_6_770_EQ_0xC_809_AND_NOT_w_ETC___d3749 ; + NOT_cpReq_363_BITS_61_TO_60_848_EQ_1_967_993_O_ETC___d3029 ; - // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F - assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h75857 == 4'd13 && + // rule RL_cpDispatch_F_F_T_E13_F_F_F_F + assign WILL_FIRE_RL_cpDispatch_F_F_T_E13_F_F_F_F = + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd13 && cpReq[61:60] != 2'd2 && - (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && - cpReq[9:6] != 4'h9 && - NOT_cpReq_337_BITS_9_TO_6_770_EQ_0xC_809_935_A_ETC___d3755 ; + NOT_cpReq_363_BITS_61_TO_60_848_EQ_1_967_993_O_ETC___d3039 ; - // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F - assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h75857 == 4'd14 && + // rule RL_cpDispatch_F_F_T_E14_T_F + assign WILL_FIRE_RL_cpDispatch_F_F_T_E14_T_F = + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd14 && cpReq[61:60] == 2'd2 && - !wci_wReset_n_14 && - NOT_wci_busy_14_170_762_AND_wci_wReset_n_14_15_ETC___d3775 ; + !wci_14_wReset_n && + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3528 && + !dispatched ; - // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T - assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h75857 == 4'd14 && + // rule RL_cpDispatch_F_F_T_E14_F_T + assign WILL_FIRE_RL_cpDispatch_F_F_T_E14_F_T = + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd14 && cpReq[61:60] == 2'd1 && cpReq[19:9] == 11'd0 && - !wci_busy_14 && - wci_respF_14$FULL_N && + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d2986 && !dispatched ; - // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T - assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h75857 == 4'd14 && + // rule RL_cpDispatch_F_F_T_E14_F_F_F_T + assign WILL_FIRE_RL_cpDispatch_F_F_T_E14_F_F_F_T = + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd14 && cpReq[61:60] != 2'd2 && - (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && - cpReq_337_BITS_9_TO_6_770_EQ_0xC_809_AND_NOT_w_ETC___d3812 ; + NOT_cpReq_363_BITS_61_TO_60_848_EQ_1_967_993_O_ETC___d3029 ; - // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F - assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h75857 == 4'd14 && + // rule RL_cpDispatch_F_F_T_E14_F_F_F_F + assign WILL_FIRE_RL_cpDispatch_F_F_T_E14_F_F_F_F = + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd14 && cpReq[61:60] != 2'd2 && - (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && - cpReq[9:6] != 4'h9 && - NOT_cpReq_337_BITS_9_TO_6_770_EQ_0xC_809_935_A_ETC___d3818 ; - - // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F - assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h75857 != 4'd0 && - _theResult_____1__h75857 != 4'd1 && - _theResult_____1__h75857 != 4'd2 && - _theResult_____1__h75857 != 4'd3 && - _theResult_____1__h75857 != 4'd4 && - _theResult_____1__h75857 != 4'd5 && - _theResult_____1__h75857 != 4'd6 && - _theResult_____1__h75857 != 4'd7 && - _theResult_____1__h75857 != 4'd8 && - _theResult_____1__h75857 != 4'd9 && - _theResult_____1__h75857 != 4'd10 && - _theResult_____1__h75857 != 4'd11 && - _theResult_____1__h75857 != 4'd12 && - _theResult_____1__h75857 != 4'd13 && - _theResult_____1__h75857 != 4'd14 && - !dispatched ; + NOT_cpReq_363_BITS_61_TO_60_848_EQ_1_967_993_O_ETC___d3039 ; + + // rule RL_cpDispatch_F_F_T_OOB + assign WILL_FIRE_RL_cpDispatch_F_F_T_OOB = + cpReq[64:62] == 3'd3 && + NOT_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_TH_ETC___d3641 ; // rule RL_cpDispatch_F_F_F_T assign WILL_FIRE_RL_cpDispatch_F_F_F_T = cpReq[64:62] == 3'd0 && !dispatched ; - // rule RL_cpDispatch_F_F_F_F_T_T_F - assign WILL_FIRE_RL_cpDispatch_F_F_F_F_T_T_F = - cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && - cpReq[64:62] != 3'd3 && - cpReq[64:62] != 3'd0 && - _theResult_____1__h75875 == 4'd0 && - cpReq[37:36] == 2'd2 && - !wci_wReset_n && - NOT_wci_busy_10_860_AND_wci_wReset_n_90_OR_wci_ETC___d2878 ; + // rule RL_cpDispatch_F_F_F_F_E0_T_F + assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_T_F = + cpReq[64:62] != 3'd1 && + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d3701 ; - // rule RL_cpDispatch_F_F_F_F_T_F_T_F - assign WILL_FIRE_RL_cpDispatch_F_F_F_F_T_F_T_F = + // rule RL_cpDispatch_F_F_F_F_E0_F_T_F + assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_T_F = + cpReq[64:62] != 3'd1 && + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d3757 ; + + // rule RL_cpDispatch_F_F_F_F_E0_F_F_T + assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_F_T = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h75875 == 4'd0 && - cpReq[37:36] == 2'd1 && - cpReq[19:9] == 11'd0 && - !wci_wReset_n && - NOT_wci_busy_10_860_AND_wci_wReset_n_90_OR_wci_ETC___d2878 ; + _theResult_____1__h75739 == 4'd0 && + cpReq[37:36] != 2'd2 && + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d3796 ; - // rule RL_cpDispatch_F_F_F_F_T_F_F_T - assign WILL_FIRE_RL_cpDispatch_F_F_F_F_T_F_F_T = + // rule RL_cpDispatch_F_F_F_F_E0_F_F_F_T + assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_F_F_T = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - IF_cpReq_337_BITS_37_TO_36_861_EQ_2_862_THEN_c_ETC___d3906 ; + _theResult_____1__h75739 == 4'd0 && + cpReq[37:36] != 2'd2 && + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d3805 ; - // rule RL_cpDispatch_F_F_F_F_T_F_F_F_T - assign WILL_FIRE_RL_cpDispatch_F_F_F_F_T_F_F_F_T = + // rule RL_cpDispatch_F_F_F_F_E0_F_F_F_F_T + assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_F_F_F_T = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - IF_cpReq_337_BITS_37_TO_36_861_EQ_2_862_THEN_c_ETC___d3915 ; + _theResult_____1__h75739 == 4'd0 && + cpReq[37:36] != 2'd2 && + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d3816 ; - // rule RL_cpDispatch_F_F_F_F_T_F_F_F_F_T - assign WILL_FIRE_RL_cpDispatch_F_F_F_F_T_F_F_F_F_T = + // rule RL_cpDispatch_F_F_F_F_E0_F_F_F_F_F_T + assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_F_F_F_F_T = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - IF_cpReq_337_BITS_37_TO_36_861_EQ_2_862_THEN_c_ETC___d3925 ; + _theResult_____1__h75739 == 4'd0 && + cpReq[37:36] != 2'd2 && + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d3827 ; - // rule RL_cpDispatch_F_F_F_F_T_F_F_F_F_F_T - assign WILL_FIRE_RL_cpDispatch_F_F_F_F_T_F_F_F_F_F_T = + // rule RL_cpDispatch_F_F_F_F_E0_F_F_F_F_F_F + assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_F_F_F_F_F = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h75875 == 4'd0 && + _theResult_____1__h75739 == 4'd0 && cpReq[37:36] != 2'd2 && (cpReq[37:36] != 2'd1 || cpReq[19:9] != 11'd0) && - cpReq_337_BITS_9_TO_6_770_EQ_0xC_809_AND_NOT_w_ETC___d2927 ; + cpReq[9:6] != 4'h8 && + NOT_cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_035_A_ETC___d3839 ; - // rule RL_cpDispatch_F_F_F_F_T_F_F_F_F_F_F - assign WILL_FIRE_RL_cpDispatch_F_F_F_F_T_F_F_F_F_F_F = - cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && - NOT_cpReq_337_BITS_64_TO_62_338_EQ_3_851_859_A_ETC___d3950 ; + // rule RL_cpDispatch_F_F_F_F_E1_T_F + assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_T_F = + cpReq[64:62] != 3'd1 && + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d3870 ; - // rule RL_cpDispatch_F_F_F_F_F_T_T_F - assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_T_F = - cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && - cpReq[64:62] != 3'd3 && - cpReq[64:62] != 3'd0 && - _theResult_____1__h75875 == 4'd1 && - cpReq[37:36] == 2'd2 && - !wci_wReset_n_1 && - NOT_wci_busy_1_50_943_AND_wci_wReset_n_1_30_OR_ETC___d2956 ; + // rule RL_cpDispatch_F_F_F_F_E1_F_T_F + assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_T_F = + cpReq[64:62] != 3'd1 && + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d3893 ; - // rule RL_cpDispatch_F_F_F_F_F_T_F_T_F - assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_F_T_F = + // rule RL_cpDispatch_F_F_F_F_E1_F_F_T + assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_F_T = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h75875 == 4'd1 && - cpReq[37:36] == 2'd1 && - cpReq[19:9] == 11'd0 && - !wci_wReset_n_1 && - NOT_wci_busy_1_50_943_AND_wci_wReset_n_1_30_OR_ETC___d2956 ; + _theResult_____1__h75739 == 4'd1 && + cpReq[37:36] != 2'd2 && + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d3796 ; - // rule RL_cpDispatch_F_F_F_F_F_T_F_F_T - assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_F_F_T = + // rule RL_cpDispatch_F_F_F_F_E1_F_F_F_T + assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_F_F_T = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - IF_cpReq_337_BITS_37_TO_36_861_EQ_2_862_THEN_c_ETC___d3984 ; + _theResult_____1__h75739 == 4'd1 && + cpReq[37:36] != 2'd2 && + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d3805 ; - // rule RL_cpDispatch_F_F_F_F_F_T_F_F_F_T - assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_F_F_F_T = + // rule RL_cpDispatch_F_F_F_F_E1_F_F_F_F_T + assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_F_F_F_T = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - IF_cpReq_337_BITS_37_TO_36_861_EQ_2_862_THEN_c_ETC___d3993 ; + _theResult_____1__h75739 == 4'd1 && + cpReq[37:36] != 2'd2 && + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d3816 ; - // rule RL_cpDispatch_F_F_F_F_F_T_F_F_F_F_T - assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_F_F_F_F_T = + // rule RL_cpDispatch_F_F_F_F_E1_F_F_F_F_F_T + assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_F_F_F_F_T = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - IF_cpReq_337_BITS_37_TO_36_861_EQ_2_862_THEN_c_ETC___d4003 ; + _theResult_____1__h75739 == 4'd1 && + cpReq[37:36] != 2'd2 && + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d3827 ; - // rule RL_cpDispatch_F_F_F_F_F_T_F_F_F_F_F_T - assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_F_F_F_F_F_T = + // rule RL_cpDispatch_F_F_F_F_E1_F_F_F_F_F_F + assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_F_F_F_F_F = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h75875 == 4'd1 && + _theResult_____1__h75739 == 4'd1 && cpReq[37:36] != 2'd2 && (cpReq[37:36] != 2'd1 || cpReq[19:9] != 11'd0) && - cpReq_337_BITS_9_TO_6_770_EQ_0xC_809_AND_NOT_w_ETC___d2993 ; + cpReq[9:6] != 4'h8 && + NOT_cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_035_A_ETC___d3839 ; - // rule RL_cpDispatch_F_F_F_F_F_T_F_F_F_F_F_F - assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_F_F_F_F_F_F = - cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && - NOT_cpReq_337_BITS_64_TO_62_338_EQ_3_851_859_A_ETC___d4026 ; + // rule RL_cpDispatch_F_F_F_F_E2_T_F + assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_T_F = + cpReq[64:62] != 3'd1 && + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d3947 ; - // rule RL_cpDispatch_F_F_F_F_F_F_T_T_F - assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_T_F = - cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && - cpReq[64:62] != 3'd3 && - cpReq[64:62] != 3'd0 && - _theResult_____1__h75875 == 4'd2 && - cpReq[37:36] == 2'd2 && - !wci_wReset_n_2 && - NOT_wci_busy_2_90_006_AND_wci_wReset_n_2_70_OR_ETC___d3019 ; + // rule RL_cpDispatch_F_F_F_F_E2_F_T_F + assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_F_T_F = + cpReq[64:62] != 3'd1 && + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d3968 ; - // rule RL_cpDispatch_F_F_F_F_F_F_T_F_T_F - assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_F_T_F = + // rule RL_cpDispatch_F_F_F_F_E2_F_F_T + assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_F_F_T = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h75875 == 4'd2 && - cpReq[37:36] == 2'd1 && - cpReq[19:9] == 11'd0 && - !wci_wReset_n_2 && - NOT_wci_busy_2_90_006_AND_wci_wReset_n_2_70_OR_ETC___d3019 ; + _theResult_____1__h75739 == 4'd2 && + cpReq[37:36] != 2'd2 && + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d3796 ; - // rule RL_cpDispatch_F_F_F_F_F_F_T_F_F_T - assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_F_F_T = + // rule RL_cpDispatch_F_F_F_F_E2_F_F_F_T + assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_F_F_F_T = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - IF_cpReq_337_BITS_37_TO_36_861_EQ_2_862_THEN_c_ETC___d4060 ; + _theResult_____1__h75739 == 4'd2 && + cpReq[37:36] != 2'd2 && + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d3805 ; - // rule RL_cpDispatch_F_F_F_F_F_F_T_F_F_F_T - assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_F_F_F_T = + // rule RL_cpDispatch_F_F_F_F_E2_F_F_F_F_T + assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_F_F_F_F_T = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - IF_cpReq_337_BITS_37_TO_36_861_EQ_2_862_THEN_c_ETC___d4069 ; + _theResult_____1__h75739 == 4'd2 && + cpReq[37:36] != 2'd2 && + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d3816 ; - // rule RL_cpDispatch_F_F_F_F_F_F_T_F_F_F_F_T - assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_F_F_F_F_T = + // rule RL_cpDispatch_F_F_F_F_E2_F_F_F_F_F_T + assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_F_F_F_F_F_T = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - IF_cpReq_337_BITS_37_TO_36_861_EQ_2_862_THEN_c_ETC___d4079 ; + _theResult_____1__h75739 == 4'd2 && + cpReq[37:36] != 2'd2 && + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d3827 ; - // rule RL_cpDispatch_F_F_F_F_F_F_T_F_F_F_F_F_T - assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_F_F_F_F_F_T = + // rule RL_cpDispatch_F_F_F_F_E2_F_F_F_F_F_F + assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_F_F_F_F_F_F = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h75875 == 4'd2 && + _theResult_____1__h75739 == 4'd2 && cpReq[37:36] != 2'd2 && (cpReq[37:36] != 2'd1 || cpReq[19:9] != 11'd0) && - cpReq_337_BITS_9_TO_6_770_EQ_0xC_809_AND_NOT_w_ETC___d3056 ; + cpReq[9:6] != 4'h8 && + NOT_cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_035_A_ETC___d3839 ; - // rule RL_cpDispatch_F_F_F_F_F_F_T_F_F_F_F_F_F - assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_F_F_F_F_F_F = - cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && - NOT_cpReq_337_BITS_64_TO_62_338_EQ_3_851_859_A_ETC___d4102 ; + // rule RL_cpDispatch_F_F_F_F_E3_T_F + assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_T_F = + cpReq[64:62] != 3'd1 && + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4022 ; - // rule RL_cpDispatch_F_F_F_F_F_F_F_T_T_F - assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_T_F = - cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && - cpReq[64:62] != 3'd3 && - cpReq[64:62] != 3'd0 && - _theResult_____1__h75875 == 4'd3 && - cpReq[37:36] == 2'd2 && - !wci_wReset_n_3 && - NOT_wci_busy_3_30_069_AND_wci_wReset_n_3_10_OR_ETC___d3082 ; + // rule RL_cpDispatch_F_F_F_F_E3_F_T_F + assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_F_T_F = + cpReq[64:62] != 3'd1 && + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4043 ; - // rule RL_cpDispatch_F_F_F_F_F_F_F_T_F_T_F - assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_F_T_F = + // rule RL_cpDispatch_F_F_F_F_E3_F_F_T + assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_F_F_T = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h75875 == 4'd3 && - cpReq[37:36] == 2'd1 && - cpReq[19:9] == 11'd0 && - !wci_wReset_n_3 && - NOT_wci_busy_3_30_069_AND_wci_wReset_n_3_10_OR_ETC___d3082 ; + _theResult_____1__h75739 == 4'd3 && + cpReq[37:36] != 2'd2 && + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d3796 ; - // rule RL_cpDispatch_F_F_F_F_F_F_F_T_F_F_T - assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_F_F_T = + // rule RL_cpDispatch_F_F_F_F_E3_F_F_F_T + assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_F_F_F_T = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - IF_cpReq_337_BITS_37_TO_36_861_EQ_2_862_THEN_c_ETC___d4136 ; + _theResult_____1__h75739 == 4'd3 && + cpReq[37:36] != 2'd2 && + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d3805 ; - // rule RL_cpDispatch_F_F_F_F_F_F_F_T_F_F_F_T - assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_F_F_F_T = + // rule RL_cpDispatch_F_F_F_F_E3_F_F_F_F_T + assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_F_F_F_F_T = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - IF_cpReq_337_BITS_37_TO_36_861_EQ_2_862_THEN_c_ETC___d4145 ; + _theResult_____1__h75739 == 4'd3 && + cpReq[37:36] != 2'd2 && + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d3816 ; - // rule RL_cpDispatch_F_F_F_F_F_F_F_T_F_F_F_F_T - assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_F_F_F_F_T = + // rule RL_cpDispatch_F_F_F_F_E3_F_F_F_F_F_T + assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_F_F_F_F_F_T = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - IF_cpReq_337_BITS_37_TO_36_861_EQ_2_862_THEN_c_ETC___d4155 ; + _theResult_____1__h75739 == 4'd3 && + cpReq[37:36] != 2'd2 && + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d3827 ; - // rule RL_cpDispatch_F_F_F_F_F_F_F_T_F_F_F_F_F_T - assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_F_F_F_F_F_T = + // rule RL_cpDispatch_F_F_F_F_E3_F_F_F_F_F_F + assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_F_F_F_F_F_F = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h75875 == 4'd3 && + _theResult_____1__h75739 == 4'd3 && cpReq[37:36] != 2'd2 && (cpReq[37:36] != 2'd1 || cpReq[19:9] != 11'd0) && - cpReq_337_BITS_9_TO_6_770_EQ_0xC_809_AND_NOT_w_ETC___d3119 ; + cpReq[9:6] != 4'h8 && + NOT_cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_035_A_ETC___d3839 ; - // rule RL_cpDispatch_F_F_F_F_F_F_F_T_F_F_F_F_F_F - assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_F_F_F_F_F_F = - cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && - NOT_cpReq_337_BITS_64_TO_62_338_EQ_3_851_859_A_ETC___d4178 ; + // rule RL_cpDispatch_F_F_F_F_E4_T_F + assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_T_F = + cpReq[64:62] != 3'd1 && + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4097 ; - // rule RL_cpDispatch_F_F_F_F_F_F_F_F_T_T_F - assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_T_F = - cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && - cpReq[64:62] != 3'd3 && - cpReq[64:62] != 3'd0 && - _theResult_____1__h75875 == 4'd4 && - cpReq[37:36] == 2'd2 && - !wci_wReset_n_4 && - NOT_wci_busy_4_70_132_AND_wci_wReset_n_4_50_OR_ETC___d3145 ; + // rule RL_cpDispatch_F_F_F_F_E4_F_T_F + assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_F_T_F = + cpReq[64:62] != 3'd1 && + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4118 ; - // rule RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_T_F - assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_T_F = + // rule RL_cpDispatch_F_F_F_F_E4_F_F_T + assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_F_F_T = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h75875 == 4'd4 && - cpReq[37:36] == 2'd1 && - cpReq[19:9] == 11'd0 && - !wci_wReset_n_4 && - NOT_wci_busy_4_70_132_AND_wci_wReset_n_4_50_OR_ETC___d3145 ; + _theResult_____1__h75739 == 4'd4 && + cpReq[37:36] != 2'd2 && + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d3796 ; - // rule RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_F_T - assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_F_T = + // rule RL_cpDispatch_F_F_F_F_E4_F_F_F_T + assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_F_F_F_T = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - IF_cpReq_337_BITS_37_TO_36_861_EQ_2_862_THEN_c_ETC___d4212 ; + _theResult_____1__h75739 == 4'd4 && + cpReq[37:36] != 2'd2 && + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d3805 ; - // rule RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_F_F_T - assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_F_F_T = + // rule RL_cpDispatch_F_F_F_F_E4_F_F_F_F_T + assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_F_F_F_F_T = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - IF_cpReq_337_BITS_37_TO_36_861_EQ_2_862_THEN_c_ETC___d4221 ; + _theResult_____1__h75739 == 4'd4 && + cpReq[37:36] != 2'd2 && + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d3816 ; - // rule RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_F_F_F_T - assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_F_F_F_T = + // rule RL_cpDispatch_F_F_F_F_E4_F_F_F_F_F_T + assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_F_F_F_F_F_T = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - IF_cpReq_337_BITS_37_TO_36_861_EQ_2_862_THEN_c_ETC___d4231 ; + _theResult_____1__h75739 == 4'd4 && + cpReq[37:36] != 2'd2 && + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d3827 ; - // rule RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T - assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T = + // rule RL_cpDispatch_F_F_F_F_E4_F_F_F_F_F_F + assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_F_F_F_F_F_F = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h75875 == 4'd4 && + _theResult_____1__h75739 == 4'd4 && cpReq[37:36] != 2'd2 && (cpReq[37:36] != 2'd1 || cpReq[19:9] != 11'd0) && - cpReq_337_BITS_9_TO_6_770_EQ_0xC_809_AND_NOT_w_ETC___d3182 ; + cpReq[9:6] != 4'h8 && + NOT_cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_035_A_ETC___d3839 ; - // rule RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F - assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F = - cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && - NOT_cpReq_337_BITS_64_TO_62_338_EQ_3_851_859_A_ETC___d4254 ; + // rule RL_cpDispatch_F_F_F_F_E5_T_F + assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_T_F = + cpReq[64:62] != 3'd1 && + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4172 ; - // rule RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_T_F - assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_T_F = - cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && - cpReq[64:62] != 3'd3 && - cpReq[64:62] != 3'd0 && - _theResult_____1__h75875 == 4'd5 && - cpReq[37:36] == 2'd2 && - !wci_wReset_n_5 && - NOT_wci_busy_5_10_195_AND_wci_wReset_n_5_90_OR_ETC___d3208 ; + // rule RL_cpDispatch_F_F_F_F_E5_F_T_F + assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_T_F = + cpReq[64:62] != 3'd1 && + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4193 ; - // rule RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_T_F - assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_T_F = + // rule RL_cpDispatch_F_F_F_F_E5_F_F_T + assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_F_T = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h75875 == 4'd5 && - cpReq[37:36] == 2'd1 && - cpReq[19:9] == 11'd0 && - !wci_wReset_n_5 && - NOT_wci_busy_5_10_195_AND_wci_wReset_n_5_90_OR_ETC___d3208 ; + _theResult_____1__h75739 == 4'd5 && + cpReq[37:36] != 2'd2 && + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d3796 ; - // rule RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_F_T - assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_F_T = + // rule RL_cpDispatch_F_F_F_F_E5_F_F_F_T + assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_F_F_T = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - IF_cpReq_337_BITS_37_TO_36_861_EQ_2_862_THEN_c_ETC___d4288 ; + _theResult_____1__h75739 == 4'd5 && + cpReq[37:36] != 2'd2 && + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d3805 ; - // rule RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_F_F_T - assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_F_F_T = + // rule RL_cpDispatch_F_F_F_F_E5_F_F_F_F_T + assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_F_F_F_T = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - IF_cpReq_337_BITS_37_TO_36_861_EQ_2_862_THEN_c_ETC___d4297 ; + _theResult_____1__h75739 == 4'd5 && + cpReq[37:36] != 2'd2 && + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d3816 ; - // rule RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T - assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T = + // rule RL_cpDispatch_F_F_F_F_E5_F_F_F_F_F_T + assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_F_F_F_F_T = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - IF_cpReq_337_BITS_37_TO_36_861_EQ_2_862_THEN_c_ETC___d4307 ; + _theResult_____1__h75739 == 4'd5 && + cpReq[37:36] != 2'd2 && + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d3827 ; - // rule RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T - assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T = + // rule RL_cpDispatch_F_F_F_F_E5_F_F_F_F_F_F + assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_F_F_F_F_F = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h75875 == 4'd5 && + _theResult_____1__h75739 == 4'd5 && cpReq[37:36] != 2'd2 && (cpReq[37:36] != 2'd1 || cpReq[19:9] != 11'd0) && - cpReq_337_BITS_9_TO_6_770_EQ_0xC_809_AND_NOT_w_ETC___d3245 ; + cpReq[9:6] != 4'h8 && + NOT_cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_035_A_ETC___d3839 ; - // rule RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F - assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F = - cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && - NOT_cpReq_337_BITS_64_TO_62_338_EQ_3_851_859_A_ETC___d4330 ; + // rule RL_cpDispatch_F_F_F_F_E6_T_F + assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_T_F = + cpReq[64:62] != 3'd1 && + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4247 ; - // rule RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_T_F - assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_T_F = - cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && - cpReq[64:62] != 3'd3 && - cpReq[64:62] != 3'd0 && - _theResult_____1__h75875 == 4'd6 && - cpReq[37:36] == 2'd2 && - !wci_wReset_n_6 && - NOT_wci_busy_6_050_258_AND_wci_wReset_n_6_030__ETC___d3271 ; + // rule RL_cpDispatch_F_F_F_F_E6_F_T_F + assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_F_T_F = + cpReq[64:62] != 3'd1 && + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4268 ; - // rule RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_F_T_F - assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_F_T_F = + // rule RL_cpDispatch_F_F_F_F_E6_F_F_T + assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_F_F_T = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h75875 == 4'd6 && - cpReq[37:36] == 2'd1 && - cpReq[19:9] == 11'd0 && - !wci_wReset_n_6 && - NOT_wci_busy_6_050_258_AND_wci_wReset_n_6_030__ETC___d3271 ; + _theResult_____1__h75739 == 4'd6 && + cpReq[37:36] != 2'd2 && + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d3796 ; - // rule RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_F_F_T - assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_F_F_T = + // rule RL_cpDispatch_F_F_F_F_E6_F_F_F_T + assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_F_F_F_T = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - IF_cpReq_337_BITS_37_TO_36_861_EQ_2_862_THEN_c_ETC___d4364 ; + _theResult_____1__h75739 == 4'd6 && + cpReq[37:36] != 2'd2 && + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d3805 ; - // rule RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T - assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T = + // rule RL_cpDispatch_F_F_F_F_E6_F_F_F_F_T + assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_F_F_F_F_T = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - IF_cpReq_337_BITS_37_TO_36_861_EQ_2_862_THEN_c_ETC___d4373 ; + _theResult_____1__h75739 == 4'd6 && + cpReq[37:36] != 2'd2 && + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d3816 ; - // rule RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T - assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T = + // rule RL_cpDispatch_F_F_F_F_E6_F_F_F_F_F_T + assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_F_F_F_F_F_T = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - IF_cpReq_337_BITS_37_TO_36_861_EQ_2_862_THEN_c_ETC___d4383 ; + _theResult_____1__h75739 == 4'd6 && + cpReq[37:36] != 2'd2 && + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d3827 ; - // rule RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T - assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T = + // rule RL_cpDispatch_F_F_F_F_E6_F_F_F_F_F_F + assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_F_F_F_F_F_F = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h75875 == 4'd6 && + _theResult_____1__h75739 == 4'd6 && cpReq[37:36] != 2'd2 && (cpReq[37:36] != 2'd1 || cpReq[19:9] != 11'd0) && - cpReq_337_BITS_9_TO_6_770_EQ_0xC_809_AND_NOT_w_ETC___d3308 ; + cpReq[9:6] != 4'h8 && + NOT_cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_035_A_ETC___d3839 ; - // rule RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F - assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F = - cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && - NOT_cpReq_337_BITS_64_TO_62_338_EQ_3_851_859_A_ETC___d4406 ; + // rule RL_cpDispatch_F_F_F_F_E7_T_F + assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_T_F = + cpReq[64:62] != 3'd1 && + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4322 ; + + // rule RL_cpDispatch_F_F_F_F_E7_F_T_F + assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_T_F = + cpReq[64:62] != 3'd1 && + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4343 ; - // rule RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_T_F - assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_T_F = + // rule RL_cpDispatch_F_F_F_F_E7_F_F_T + assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_F_T = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h75875 == 4'd7 && - cpReq[37:36] == 2'd2 && - !wci_wReset_n_7 && - NOT_wci_busy_7_190_321_AND_wci_wReset_n_7_170__ETC___d3334 ; + _theResult_____1__h75739 == 4'd7 && + cpReq[37:36] != 2'd2 && + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d3796 ; - // rule RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F - assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F = + // rule RL_cpDispatch_F_F_F_F_E7_F_F_F_T + assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_F_F_T = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h75875 == 4'd7 && - cpReq[37:36] == 2'd1 && - cpReq[19:9] == 11'd0 && - !wci_wReset_n_7 && - NOT_wci_busy_7_190_321_AND_wci_wReset_n_7_170__ETC___d3334 ; - - // rule RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T - assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T = - cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && - cpReq[64:62] != 3'd3 && - cpReq[64:62] != 3'd0 && - IF_cpReq_337_BITS_37_TO_36_861_EQ_2_862_THEN_c_ETC___d4440 ; + _theResult_____1__h75739 == 4'd7 && + cpReq[37:36] != 2'd2 && + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d3805 ; - // rule RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T - assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T = + // rule RL_cpDispatch_F_F_F_F_E7_F_F_F_F_T + assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_F_F_F_T = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - IF_cpReq_337_BITS_37_TO_36_861_EQ_2_862_THEN_c_ETC___d4449 ; + _theResult_____1__h75739 == 4'd7 && + cpReq[37:36] != 2'd2 && + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d3816 ; - // rule RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T - assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T = + // rule RL_cpDispatch_F_F_F_F_E7_F_F_F_F_F_T + assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_F_F_F_F_T = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - IF_cpReq_337_BITS_37_TO_36_861_EQ_2_862_THEN_c_ETC___d4459 ; + _theResult_____1__h75739 == 4'd7 && + cpReq[37:36] != 2'd2 && + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d3827 ; - // rule RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T - assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T = + // rule RL_cpDispatch_F_F_F_F_E7_F_F_F_F_F_F + assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_F_F_F_F_F = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h75875 == 4'd7 && + _theResult_____1__h75739 == 4'd7 && cpReq[37:36] != 2'd2 && (cpReq[37:36] != 2'd1 || cpReq[19:9] != 11'd0) && - cpReq_337_BITS_9_TO_6_770_EQ_0xC_809_AND_NOT_w_ETC___d3371 ; + cpReq[9:6] != 4'h8 && + NOT_cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_035_A_ETC___d3839 ; - // rule RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F - assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F = - cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && - NOT_cpReq_337_BITS_64_TO_62_338_EQ_3_851_859_A_ETC___d4482 ; + // rule RL_cpDispatch_F_F_F_F_E8_T_F + assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_T_F = + cpReq[64:62] != 3'd1 && + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4397 ; - // rule RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F - assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F = - cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && - cpReq[64:62] != 3'd3 && - cpReq[64:62] != 3'd0 && - _theResult_____1__h75875 == 4'd8 && - cpReq[37:36] == 2'd2 && - !wci_wReset_n_8 && - NOT_wci_busy_8_330_384_AND_wci_wReset_n_8_310__ETC___d3397 ; + // rule RL_cpDispatch_F_F_F_F_E8_F_T_F + assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_T_F = + cpReq[64:62] != 3'd1 && + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4418 ; - // rule RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F - assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F = + // rule RL_cpDispatch_F_F_F_F_E8_F_F_T + assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_F_T = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h75875 == 4'd8 && - cpReq[37:36] == 2'd1 && - cpReq[19:9] == 11'd0 && - !wci_wReset_n_8 && - NOT_wci_busy_8_330_384_AND_wci_wReset_n_8_310__ETC___d3397 ; + _theResult_____1__h75739 == 4'd8 && + cpReq[37:36] != 2'd2 && + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d3796 ; - // rule RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T - assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T = + // rule RL_cpDispatch_F_F_F_F_E8_F_F_F_T + assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_F_F_T = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - IF_cpReq_337_BITS_37_TO_36_861_EQ_2_862_THEN_c_ETC___d4516 ; + _theResult_____1__h75739 == 4'd8 && + cpReq[37:36] != 2'd2 && + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d3805 ; - // rule RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T - assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T = + // rule RL_cpDispatch_F_F_F_F_E8_F_F_F_F_T + assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_F_F_F_T = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - IF_cpReq_337_BITS_37_TO_36_861_EQ_2_862_THEN_c_ETC___d4525 ; + _theResult_____1__h75739 == 4'd8 && + cpReq[37:36] != 2'd2 && + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d3816 ; - // rule RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T - assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T = + // rule RL_cpDispatch_F_F_F_F_E8_F_F_F_F_F_T + assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_F_F_F_F_T = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - IF_cpReq_337_BITS_37_TO_36_861_EQ_2_862_THEN_c_ETC___d4535 ; + _theResult_____1__h75739 == 4'd8 && + cpReq[37:36] != 2'd2 && + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d3827 ; - // rule RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T - assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T = + // rule RL_cpDispatch_F_F_F_F_E8_F_F_F_F_F_F + assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_F_F_F_F_F = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h75875 == 4'd8 && + _theResult_____1__h75739 == 4'd8 && cpReq[37:36] != 2'd2 && (cpReq[37:36] != 2'd1 || cpReq[19:9] != 11'd0) && - cpReq_337_BITS_9_TO_6_770_EQ_0xC_809_AND_NOT_w_ETC___d3434 ; + cpReq[9:6] != 4'h8 && + NOT_cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_035_A_ETC___d3839 ; - // rule RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F - assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F = - cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && - NOT_cpReq_337_BITS_64_TO_62_338_EQ_3_851_859_A_ETC___d4558 ; + // rule RL_cpDispatch_F_F_F_F_E9_T_F + assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_T_F = + cpReq[64:62] != 3'd1 && + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4472 ; - // rule RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F - assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F = - cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && - cpReq[64:62] != 3'd3 && - cpReq[64:62] != 3'd0 && - _theResult_____1__h75875 == 4'd9 && - cpReq[37:36] == 2'd2 && - !wci_wReset_n_9 && - NOT_wci_busy_9_470_447_AND_wci_wReset_n_9_450__ETC___d3460 ; + // rule RL_cpDispatch_F_F_F_F_E9_F_T_F + assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_F_T_F = + cpReq[64:62] != 3'd1 && + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4493 ; - // rule RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F - assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F = + // rule RL_cpDispatch_F_F_F_F_E9_F_F_T + assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_F_F_T = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h75875 == 4'd9 && - cpReq[37:36] == 2'd1 && - cpReq[19:9] == 11'd0 && - !wci_wReset_n_9 && - NOT_wci_busy_9_470_447_AND_wci_wReset_n_9_450__ETC___d3460 ; + _theResult_____1__h75739 == 4'd9 && + cpReq[37:36] != 2'd2 && + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d3796 ; - // rule RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T - assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T = + // rule RL_cpDispatch_F_F_F_F_E9_F_F_F_T + assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_F_F_F_T = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - IF_cpReq_337_BITS_37_TO_36_861_EQ_2_862_THEN_c_ETC___d4592 ; + _theResult_____1__h75739 == 4'd9 && + cpReq[37:36] != 2'd2 && + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d3805 ; - // rule RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T - assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T = + // rule RL_cpDispatch_F_F_F_F_E9_F_F_F_F_T + assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_F_F_F_F_T = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - IF_cpReq_337_BITS_37_TO_36_861_EQ_2_862_THEN_c_ETC___d4601 ; + _theResult_____1__h75739 == 4'd9 && + cpReq[37:36] != 2'd2 && + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d3816 ; - // rule RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T - assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T = + // rule RL_cpDispatch_F_F_F_F_E9_F_F_F_F_F_T + assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_F_F_F_F_F_T = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - IF_cpReq_337_BITS_37_TO_36_861_EQ_2_862_THEN_c_ETC___d4611 ; + _theResult_____1__h75739 == 4'd9 && + cpReq[37:36] != 2'd2 && + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d3827 ; - // rule RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T - assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T = + // rule RL_cpDispatch_F_F_F_F_E9_F_F_F_F_F_F + assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_F_F_F_F_F_F = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h75875 == 4'd9 && + _theResult_____1__h75739 == 4'd9 && cpReq[37:36] != 2'd2 && (cpReq[37:36] != 2'd1 || cpReq[19:9] != 11'd0) && - cpReq_337_BITS_9_TO_6_770_EQ_0xC_809_AND_NOT_w_ETC___d3497 ; + cpReq[9:6] != 4'h8 && + NOT_cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_035_A_ETC___d3839 ; - // rule RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F - assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F = - cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && - NOT_cpReq_337_BITS_64_TO_62_338_EQ_3_851_859_A_ETC___d4634 ; + // rule RL_cpDispatch_F_F_F_F_E10_T_F + assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_T_F = + cpReq[64:62] != 3'd1 && + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4547 ; - // rule RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F - assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F = - cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && - cpReq[64:62] != 3'd3 && - cpReq[64:62] != 3'd0 && - _theResult_____1__h75875 == 4'd10 && - cpReq[37:36] == 2'd2 && - !wci_wReset_n_10 && - NOT_wci_busy_10_610_510_AND_wci_wReset_n_10_59_ETC___d3523 ; + // rule RL_cpDispatch_F_F_F_F_E10_F_T_F + assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_F_T_F = + cpReq[64:62] != 3'd1 && + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4568 ; - // rule RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F - assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F = + // rule RL_cpDispatch_F_F_F_F_E10_F_F_T + assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_F_F_T = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h75875 == 4'd10 && - cpReq[37:36] == 2'd1 && - cpReq[19:9] == 11'd0 && - !wci_wReset_n_10 && - NOT_wci_busy_10_610_510_AND_wci_wReset_n_10_59_ETC___d3523 ; + _theResult_____1__h75739 == 4'd10 && + cpReq[37:36] != 2'd2 && + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d3796 ; - // rule RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T - assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T = + // rule RL_cpDispatch_F_F_F_F_E10_F_F_F_T + assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_F_F_F_T = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - IF_cpReq_337_BITS_37_TO_36_861_EQ_2_862_THEN_c_ETC___d4668 ; + _theResult_____1__h75739 == 4'd10 && + cpReq[37:36] != 2'd2 && + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d3805 ; - // rule RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T - assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T = + // rule RL_cpDispatch_F_F_F_F_E10_F_F_F_F_T + assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_F_F_F_F_T = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - IF_cpReq_337_BITS_37_TO_36_861_EQ_2_862_THEN_c_ETC___d4677 ; + _theResult_____1__h75739 == 4'd10 && + cpReq[37:36] != 2'd2 && + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d3816 ; - // rule RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T - assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T = + // rule RL_cpDispatch_F_F_F_F_E10_F_F_F_F_F_T + assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_F_F_F_F_F_T = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - IF_cpReq_337_BITS_37_TO_36_861_EQ_2_862_THEN_c_ETC___d4687 ; + _theResult_____1__h75739 == 4'd10 && + cpReq[37:36] != 2'd2 && + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d3827 ; - // rule RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T - assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T = + // rule RL_cpDispatch_F_F_F_F_E10_F_F_F_F_F_F + assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_F_F_F_F_F_F = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h75875 == 4'd10 && + _theResult_____1__h75739 == 4'd10 && cpReq[37:36] != 2'd2 && (cpReq[37:36] != 2'd1 || cpReq[19:9] != 11'd0) && - cpReq_337_BITS_9_TO_6_770_EQ_0xC_809_AND_NOT_w_ETC___d3560 ; + cpReq[9:6] != 4'h8 && + NOT_cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_035_A_ETC___d3839 ; - // rule RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F - assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F = - cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && - NOT_cpReq_337_BITS_64_TO_62_338_EQ_3_851_859_A_ETC___d4710 ; + // rule RL_cpDispatch_F_F_F_F_E11_T_F + assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_T_F = + cpReq[64:62] != 3'd1 && + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4622 ; - // rule RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F - assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F = - cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && - cpReq[64:62] != 3'd3 && - cpReq[64:62] != 3'd0 && - _theResult_____1__h75875 == 4'd11 && - cpReq[37:36] == 2'd2 && - !wci_wReset_n_11 && - NOT_wci_busy_11_750_573_AND_wci_wReset_n_11_73_ETC___d3586 ; + // rule RL_cpDispatch_F_F_F_F_E11_F_T_F + assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_F_T_F = + cpReq[64:62] != 3'd1 && + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4643 ; - // rule RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F - assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F = + // rule RL_cpDispatch_F_F_F_F_E11_F_F_T + assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_F_F_T = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h75875 == 4'd11 && - cpReq[37:36] == 2'd1 && - cpReq[19:9] == 11'd0 && - !wci_wReset_n_11 && - NOT_wci_busy_11_750_573_AND_wci_wReset_n_11_73_ETC___d3586 ; + _theResult_____1__h75739 == 4'd11 && + cpReq[37:36] != 2'd2 && + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d3796 ; - // rule RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T - assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T = + // rule RL_cpDispatch_F_F_F_F_E11_F_F_F_T + assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_F_F_F_T = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - IF_cpReq_337_BITS_37_TO_36_861_EQ_2_862_THEN_c_ETC___d4744 ; + _theResult_____1__h75739 == 4'd11 && + cpReq[37:36] != 2'd2 && + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d3805 ; - // rule RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T - assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T = + // rule RL_cpDispatch_F_F_F_F_E11_F_F_F_F_T + assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_F_F_F_F_T = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - IF_cpReq_337_BITS_37_TO_36_861_EQ_2_862_THEN_c_ETC___d4753 ; + _theResult_____1__h75739 == 4'd11 && + cpReq[37:36] != 2'd2 && + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d3816 ; - // rule RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T - assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T = + // rule RL_cpDispatch_F_F_F_F_E11_F_F_F_F_F_T + assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_F_F_F_F_F_T = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - IF_cpReq_337_BITS_37_TO_36_861_EQ_2_862_THEN_c_ETC___d4763 ; + _theResult_____1__h75739 == 4'd11 && + cpReq[37:36] != 2'd2 && + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d3827 ; - // rule RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T - assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T = + // rule RL_cpDispatch_F_F_F_F_E11_F_F_F_F_F_F + assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_F_F_F_F_F_F = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h75875 == 4'd11 && + _theResult_____1__h75739 == 4'd11 && cpReq[37:36] != 2'd2 && (cpReq[37:36] != 2'd1 || cpReq[19:9] != 11'd0) && - cpReq_337_BITS_9_TO_6_770_EQ_0xC_809_AND_NOT_w_ETC___d3623 ; + cpReq[9:6] != 4'h8 && + NOT_cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_035_A_ETC___d3839 ; - // rule RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F - assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F = - cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && - NOT_cpReq_337_BITS_64_TO_62_338_EQ_3_851_859_A_ETC___d4786 ; + // rule RL_cpDispatch_F_F_F_F_E12_T_F + assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_T_F = + cpReq[64:62] != 3'd1 && + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4697 ; - // rule RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F - assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F = - cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && - cpReq[64:62] != 3'd3 && - cpReq[64:62] != 3'd0 && - _theResult_____1__h75875 == 4'd12 && - cpReq[37:36] == 2'd2 && - !wci_wReset_n_12 && - NOT_wci_busy_12_890_636_AND_wci_wReset_n_12_87_ETC___d3649 ; + // rule RL_cpDispatch_F_F_F_F_E12_F_T_F + assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_F_T_F = + cpReq[64:62] != 3'd1 && + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4718 ; - // rule RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F - assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F = + // rule RL_cpDispatch_F_F_F_F_E12_F_F_T + assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_F_F_T = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h75875 == 4'd12 && - cpReq[37:36] == 2'd1 && - cpReq[19:9] == 11'd0 && - !wci_wReset_n_12 && - NOT_wci_busy_12_890_636_AND_wci_wReset_n_12_87_ETC___d3649 ; + _theResult_____1__h75739 == 4'd12 && + cpReq[37:36] != 2'd2 && + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d3796 ; - // rule RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T - assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T = + // rule RL_cpDispatch_F_F_F_F_E12_F_F_F_T + assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_F_F_F_T = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - IF_cpReq_337_BITS_37_TO_36_861_EQ_2_862_THEN_c_ETC___d4820 ; + _theResult_____1__h75739 == 4'd12 && + cpReq[37:36] != 2'd2 && + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d3805 ; - // rule RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T - assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T = + // rule RL_cpDispatch_F_F_F_F_E12_F_F_F_F_T + assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_F_F_F_F_T = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - IF_cpReq_337_BITS_37_TO_36_861_EQ_2_862_THEN_c_ETC___d4829 ; + _theResult_____1__h75739 == 4'd12 && + cpReq[37:36] != 2'd2 && + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d3816 ; - // rule RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T - assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T = + // rule RL_cpDispatch_F_F_F_F_E12_F_F_F_F_F_T + assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_F_F_F_F_F_T = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - IF_cpReq_337_BITS_37_TO_36_861_EQ_2_862_THEN_c_ETC___d4839 ; + _theResult_____1__h75739 == 4'd12 && + cpReq[37:36] != 2'd2 && + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d3827 ; - // rule RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T - assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T = + // rule RL_cpDispatch_F_F_F_F_E12_F_F_F_F_F_F + assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_F_F_F_F_F_F = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h75875 == 4'd12 && + _theResult_____1__h75739 == 4'd12 && cpReq[37:36] != 2'd2 && (cpReq[37:36] != 2'd1 || cpReq[19:9] != 11'd0) && - cpReq_337_BITS_9_TO_6_770_EQ_0xC_809_AND_NOT_w_ETC___d3686 ; + cpReq[9:6] != 4'h8 && + NOT_cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_035_A_ETC___d3839 ; - // rule RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F - assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F = - cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && - NOT_cpReq_337_BITS_64_TO_62_338_EQ_3_851_859_A_ETC___d4862 ; + // rule RL_cpDispatch_F_F_F_F_E13_T_F + assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_T_F = + cpReq[64:62] != 3'd1 && + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4772 ; - // rule RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F - assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F = - cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && - cpReq[64:62] != 3'd3 && - cpReq[64:62] != 3'd0 && - _theResult_____1__h75875 == 4'd13 && - cpReq[37:36] == 2'd2 && - !wci_wReset_n_13 && - NOT_wci_busy_13_030_699_AND_wci_wReset_n_13_01_ETC___d3712 ; + // rule RL_cpDispatch_F_F_F_F_E13_F_T_F + assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_F_T_F = + cpReq[64:62] != 3'd1 && + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4793 ; - // rule RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F - assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F = + // rule RL_cpDispatch_F_F_F_F_E13_F_F_T + assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_F_F_T = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h75875 == 4'd13 && - cpReq[37:36] == 2'd1 && - cpReq[19:9] == 11'd0 && - !wci_wReset_n_13 && - NOT_wci_busy_13_030_699_AND_wci_wReset_n_13_01_ETC___d3712 ; + _theResult_____1__h75739 == 4'd13 && + cpReq[37:36] != 2'd2 && + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d3796 ; - // rule RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T - assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T = + // rule RL_cpDispatch_F_F_F_F_E13_F_F_F_T + assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_F_F_F_T = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - IF_cpReq_337_BITS_37_TO_36_861_EQ_2_862_THEN_c_ETC___d4896 ; + _theResult_____1__h75739 == 4'd13 && + cpReq[37:36] != 2'd2 && + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d3805 ; - // rule RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T - assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T = + // rule RL_cpDispatch_F_F_F_F_E13_F_F_F_F_T + assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_F_F_F_F_T = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - IF_cpReq_337_BITS_37_TO_36_861_EQ_2_862_THEN_c_ETC___d4905 ; + _theResult_____1__h75739 == 4'd13 && + cpReq[37:36] != 2'd2 && + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d3816 ; - // rule RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T - assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T = + // rule RL_cpDispatch_F_F_F_F_E13_F_F_F_F_F_T + assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_F_F_F_F_F_T = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - IF_cpReq_337_BITS_37_TO_36_861_EQ_2_862_THEN_c_ETC___d4915 ; + _theResult_____1__h75739 == 4'd13 && + cpReq[37:36] != 2'd2 && + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d3827 ; - // rule RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T - assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T = + // rule RL_cpDispatch_F_F_F_F_E13_F_F_F_F_F_F + assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_F_F_F_F_F_F = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h75875 == 4'd13 && + _theResult_____1__h75739 == 4'd13 && cpReq[37:36] != 2'd2 && (cpReq[37:36] != 2'd1 || cpReq[19:9] != 11'd0) && - cpReq_337_BITS_9_TO_6_770_EQ_0xC_809_AND_NOT_w_ETC___d3749 ; + cpReq[9:6] != 4'h8 && + NOT_cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_035_A_ETC___d3839 ; - // rule RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F - assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F = - cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && - NOT_cpReq_337_BITS_64_TO_62_338_EQ_3_851_859_A_ETC___d4938 ; + // rule RL_cpDispatch_F_F_F_F_E14_T_F + assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_T_F = + cpReq[64:62] != 3'd1 && + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4847 ; - // rule RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F - assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F = - cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && - cpReq[64:62] != 3'd3 && - cpReq[64:62] != 3'd0 && - _theResult_____1__h75875 == 4'd14 && - cpReq[37:36] == 2'd2 && - !wci_wReset_n_14 && - NOT_wci_busy_14_170_762_AND_wci_wReset_n_14_15_ETC___d3775 ; + // rule RL_cpDispatch_F_F_F_F_E14_F_T_F + assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_F_T_F = + cpReq[64:62] != 3'd1 && + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4868 ; - // rule RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F - assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F = + // rule RL_cpDispatch_F_F_F_F_E14_F_F_T + assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_F_F_T = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h75875 == 4'd14 && - cpReq[37:36] == 2'd1 && - cpReq[19:9] == 11'd0 && - !wci_wReset_n_14 && - NOT_wci_busy_14_170_762_AND_wci_wReset_n_14_15_ETC___d3775 ; + _theResult_____1__h75739 == 4'd14 && + cpReq[37:36] != 2'd2 && + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d3796 ; - // rule RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T - assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T = + // rule RL_cpDispatch_F_F_F_F_E14_F_F_F_T + assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_F_F_F_T = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - IF_cpReq_337_BITS_37_TO_36_861_EQ_2_862_THEN_c_ETC___d4972 ; + _theResult_____1__h75739 == 4'd14 && + cpReq[37:36] != 2'd2 && + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d3805 ; - // rule RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T - assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T = + // rule RL_cpDispatch_F_F_F_F_E14_F_F_F_F_T + assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_F_F_F_F_T = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - IF_cpReq_337_BITS_37_TO_36_861_EQ_2_862_THEN_c_ETC___d4981 ; + _theResult_____1__h75739 == 4'd14 && + cpReq[37:36] != 2'd2 && + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d3816 ; - // rule RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T - assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T = + // rule RL_cpDispatch_F_F_F_F_E14_F_F_F_F_F_T + assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_F_F_F_F_F_T = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - IF_cpReq_337_BITS_37_TO_36_861_EQ_2_862_THEN_c_ETC___d4991 ; + _theResult_____1__h75739 == 4'd14 && + cpReq[37:36] != 2'd2 && + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d3827 ; - // rule RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T - assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T = + // rule RL_cpDispatch_F_F_F_F_E14_F_F_F_F_F_F + assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_F_F_F_F_F_F = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h75875 == 4'd14 && + _theResult_____1__h75739 == 4'd14 && cpReq[37:36] != 2'd2 && (cpReq[37:36] != 2'd1 || cpReq[19:9] != 11'd0) && - cpReq_337_BITS_9_TO_6_770_EQ_0xC_809_AND_NOT_w_ETC___d3812 ; - - // rule RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F - assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F = - cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && - NOT_cpReq_337_BITS_64_TO_62_338_EQ_3_851_859_A_ETC___d5014 ; + cpReq[9:6] != 4'h8 && + NOT_cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_035_A_ETC___d3839 ; - // rule RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F - assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F = + // rule RL_cpDispatch_F_F_F_F_OOB + assign WILL_FIRE_RL_cpDispatch_F_F_F_F_OOB = cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && - NOT_cpReq_337_BITS_64_TO_62_338_EQ_0_855_860_A_ETC___d5047 ; + cpReq[64:62] != 3'd0 && + NOT_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_TH_ETC___d5023 ; // rule RL_completeWorkerWrite assign WILL_FIRE_RL_completeWorkerWrite = - IF_wrkAct_051_EQ_0_052_THEN_wci_respF_i_notEmp_ETC___d6101 && + CASE_wrkAct_028_0_wci_0_respF_i_notEmpty__029__ETC___d5044 && cpReq[64:62] == 3'd3 && - !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F && - !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F && - !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T && - !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_F && - !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_T && - !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_F && - !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_T && - !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T && - !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F && - !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T && - !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F && - !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T && - !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_F && - !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_T && - !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_F && - !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_T && - !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T && - !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F && - !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T && - !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F && - !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T && - !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_F && - !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_T && - !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_T && - !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T && - !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F && - !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_F && - !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T && - !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F && - !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T && - !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_F && - !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_T && - !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_F && - !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_T && - !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_F_T && - !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_T_F && - !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_T_T && - !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F && - !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T && - !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_F && - !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_F && - !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_T && - !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_T && - !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_T && - !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_T_T && - !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_F_F_F_F && - !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_F_F_F_T && - !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_T_F && - !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_F_F_T_F_F && - !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_F_F_T_F_T && - !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_F_F_T_T_F && - !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_F_F_T_T_T && - !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_T_F && - !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_T_T && - !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_F_T && - !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_F_F_F_F && - !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_F_F_T_F_F && - !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_F_F_F_T && - !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_F_F_T_F_T && - !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_F_F_T_T_F && - !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_F_F_T_T_T && - !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_F_T && - !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_T_F && - !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_T_T && - !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_F_F_F_F && - !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_F_F_F_T && - !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_F_F_T_F_F && - !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_F_F_T_F_T && - !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_F_F_T_T_F && - !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_F_F_T_T_T && - !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_F_T && - !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_T_F && - !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_T_T && - !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_F_F_F_F && - !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_F_F_T_F_F && - !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_F_F_F_T && - !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_F_F_T_F_T && - !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_F_F_T_T_T && - !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_F_F_T_T_F && - !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_F_T && - !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_T_F && - !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_T_T && - !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_F_F_F && - !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_F_F_T && - !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_F_T_F_F && - !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_F_T_F_T && - !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_F_T_T_F && - !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_F_T_T_T && - !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_T && - !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_T_F && - !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_T_T && - !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_F_F_F_F && - !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_F_F_F_T && - !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_F_F_T_F_F && - !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_F_F_T_F_T && - !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_F_F_T_T_F && - !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_F_F_T_T_T && - !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_F_T && - !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_T_F && - !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_T_T && - !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_F_F_F_F && - !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_F_F_F_T && - !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_F_F_T_F_F && - !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_F_F_T_F_T && - !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_F_F_T_T_F && - !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_F_F_T_T_T && - !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_T_F && - !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_F_T && - !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_T_T && - !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_F_F_F_F && - !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_F_F_F_T && - !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_F_F_T_F_F && - !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_F_F_T_F_T && - !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_F_F_T_T_F && - !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_F_T && - !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_T_F && - !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_T_T && - !WILL_FIRE_RL_cpDispatch_F_F_T_F_T_F_F_F_F && - !WILL_FIRE_RL_cpDispatch_F_F_T_F_T_F_F_F_T && - !WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_F_F_T_T_T && - !WILL_FIRE_RL_cpDispatch_F_F_T_F_T_F_F_T_F_F && - !WILL_FIRE_RL_cpDispatch_F_F_T_F_T_F_F_T_F_T && - !WILL_FIRE_RL_cpDispatch_F_F_T_F_T_F_F_T_T_F && - !WILL_FIRE_RL_cpDispatch_F_F_T_F_T_F_F_T_T_T && - !WILL_FIRE_RL_cpDispatch_F_F_T_F_T_F_T && - !WILL_FIRE_RL_cpDispatch_F_F_T_F_T_T_T && - !WILL_FIRE_RL_cpDispatch_F_F_T_F_T_T_F && - !WILL_FIRE_RL_cpDispatch_F_F_T_T_F_F_F_F && - !WILL_FIRE_RL_cpDispatch_F_F_T_T_F_F_F_T && - !WILL_FIRE_RL_cpDispatch_F_F_T_T_F_F_T_F_F && - !WILL_FIRE_RL_cpDispatch_F_F_T_T_F_F_T_F_T && - !WILL_FIRE_RL_cpDispatch_F_F_T_T_F_F_T_T_F && - !WILL_FIRE_RL_cpDispatch_F_F_T_T_F_F_T_T_T && - !WILL_FIRE_RL_cpDispatch_F_F_T_T_F_T && - !WILL_FIRE_RL_cpDispatch_F_F_T_T_T_F && - !WILL_FIRE_RL_cpDispatch_F_F_T_T_T_T ; + !WILL_FIRE_RL_cpDispatch_F_F_T_OOB && + !WILL_FIRE_RL_cpDispatch_F_F_T_E14_F_F_F_F && + !WILL_FIRE_RL_cpDispatch_F_F_T_E14_F_F_F_T && + !WILL_FIRE_RL_cpDispatch_F_F_T_E14_F_F_T_F_F && + !WILL_FIRE_RL_cpDispatch_F_F_T_E14_F_F_T_F_T && + !WILL_FIRE_RL_cpDispatch_F_F_T_E14_F_F_T_T_F && + !WILL_FIRE_RL_cpDispatch_F_F_T_E14_F_F_T_T_T && + !WILL_FIRE_RL_cpDispatch_F_F_T_E14_T_F && + !WILL_FIRE_RL_cpDispatch_F_F_T_E14_T_T && + !WILL_FIRE_RL_cpDispatch_F_F_T_E14_F_T && + !WILL_FIRE_RL_cpDispatch_F_F_T_E13_F_F_F_F && + !WILL_FIRE_RL_cpDispatch_F_F_T_E13_F_F_T_F_F && + !WILL_FIRE_RL_cpDispatch_F_F_T_E13_F_F_F_T && + !WILL_FIRE_RL_cpDispatch_F_F_T_E13_F_F_T_F_T && + !WILL_FIRE_RL_cpDispatch_F_F_T_E13_F_F_T_T_F && + !WILL_FIRE_RL_cpDispatch_F_F_T_E13_F_F_T_T_T && + !WILL_FIRE_RL_cpDispatch_F_F_T_E13_F_T && + !WILL_FIRE_RL_cpDispatch_F_F_T_E13_T_F && + !WILL_FIRE_RL_cpDispatch_F_F_T_E13_T_T && + !WILL_FIRE_RL_cpDispatch_F_F_T_E12_F_F_F_F && + !WILL_FIRE_RL_cpDispatch_F_F_T_E12_F_F_F_T && + !WILL_FIRE_RL_cpDispatch_F_F_T_E12_F_F_T_F_F && + !WILL_FIRE_RL_cpDispatch_F_F_T_E12_F_F_T_F_T && + !WILL_FIRE_RL_cpDispatch_F_F_T_E12_F_F_T_T_F && + !WILL_FIRE_RL_cpDispatch_F_F_T_E12_F_F_T_T_T && + !WILL_FIRE_RL_cpDispatch_F_F_T_E12_F_T && + !WILL_FIRE_RL_cpDispatch_F_F_T_E12_T_F && + !WILL_FIRE_RL_cpDispatch_F_F_T_E12_T_T && + !WILL_FIRE_RL_cpDispatch_F_F_T_E11_F_F_F_F && + !WILL_FIRE_RL_cpDispatch_F_F_T_E11_F_F_F_T && + !WILL_FIRE_RL_cpDispatch_F_F_T_E11_F_F_T_F_F && + !WILL_FIRE_RL_cpDispatch_F_F_T_E11_F_F_T_F_T && + !WILL_FIRE_RL_cpDispatch_F_F_T_E11_F_F_T_T_F && + !WILL_FIRE_RL_cpDispatch_F_F_T_E11_F_F_T_T_T && + !WILL_FIRE_RL_cpDispatch_F_F_T_E11_F_T && + !WILL_FIRE_RL_cpDispatch_F_F_T_E11_T_F && + !WILL_FIRE_RL_cpDispatch_F_F_T_E11_T_T && + !WILL_FIRE_RL_cpDispatch_F_F_T_E10_F_F_F_F && + !WILL_FIRE_RL_cpDispatch_F_F_T_E10_F_F_F_T && + !WILL_FIRE_RL_cpDispatch_F_F_T_E10_F_F_T_F_F && + !WILL_FIRE_RL_cpDispatch_F_F_T_E10_F_F_T_F_T && + !WILL_FIRE_RL_cpDispatch_F_F_T_E10_F_F_T_T_F && + !WILL_FIRE_RL_cpDispatch_F_F_T_E10_F_T && + !WILL_FIRE_RL_cpDispatch_F_F_T_E10_T_F && + !WILL_FIRE_RL_cpDispatch_F_F_T_E10_T_T && + !WILL_FIRE_RL_cpDispatch_F_F_T_E10_F_F_T_T_T && + !WILL_FIRE_RL_cpDispatch_F_F_T_E9_F_F_F_F && + !WILL_FIRE_RL_cpDispatch_F_F_T_E9_F_F_F_T && + !WILL_FIRE_RL_cpDispatch_F_F_T_E9_F_F_T_F_F && + !WILL_FIRE_RL_cpDispatch_F_F_T_E9_F_F_T_F_T && + !WILL_FIRE_RL_cpDispatch_F_F_T_E9_F_F_T_T_T && + !WILL_FIRE_RL_cpDispatch_F_F_T_E9_F_T && + !WILL_FIRE_RL_cpDispatch_F_F_T_E9_F_F_T_T_F && + !WILL_FIRE_RL_cpDispatch_F_F_T_E9_T_F && + !WILL_FIRE_RL_cpDispatch_F_F_T_E9_T_T && + !WILL_FIRE_RL_cpDispatch_F_F_T_E8_F_F_F_F && + !WILL_FIRE_RL_cpDispatch_F_F_T_E8_F_F_F_T && + !WILL_FIRE_RL_cpDispatch_F_F_T_E8_F_F_T_F_F && + !WILL_FIRE_RL_cpDispatch_F_F_T_E8_F_F_T_F_T && + !WILL_FIRE_RL_cpDispatch_F_F_T_E8_F_F_T_T_F && + !WILL_FIRE_RL_cpDispatch_F_F_T_E8_F_F_T_T_T && + !WILL_FIRE_RL_cpDispatch_F_F_T_E8_F_T && + !WILL_FIRE_RL_cpDispatch_F_F_T_E8_T_F && + !WILL_FIRE_RL_cpDispatch_F_F_T_E8_T_T && + !WILL_FIRE_RL_cpDispatch_F_F_T_E7_F_F_F_F && + !WILL_FIRE_RL_cpDispatch_F_F_T_E7_F_F_F_T && + !WILL_FIRE_RL_cpDispatch_F_F_T_E7_F_F_T_F_F && + !WILL_FIRE_RL_cpDispatch_F_F_T_E7_F_F_T_F_T && + !WILL_FIRE_RL_cpDispatch_F_F_T_E7_F_F_T_T_F && + !WILL_FIRE_RL_cpDispatch_F_F_T_E7_F_F_T_T_T && + !WILL_FIRE_RL_cpDispatch_F_F_T_E7_F_T && + !WILL_FIRE_RL_cpDispatch_F_F_T_E7_T_F && + !WILL_FIRE_RL_cpDispatch_F_F_T_E7_T_T && + !WILL_FIRE_RL_cpDispatch_F_F_T_E6_F_F_F_F && + !WILL_FIRE_RL_cpDispatch_F_F_T_E6_F_F_F_T && + !WILL_FIRE_RL_cpDispatch_F_F_T_E6_F_F_T_F_F && + !WILL_FIRE_RL_cpDispatch_F_F_T_E6_F_F_T_F_T && + !WILL_FIRE_RL_cpDispatch_F_F_T_E6_F_F_T_T_F && + !WILL_FIRE_RL_cpDispatch_F_F_T_E6_F_F_T_T_T && + !WILL_FIRE_RL_cpDispatch_F_F_T_E6_F_T && + !WILL_FIRE_RL_cpDispatch_F_F_T_E6_T_F && + !WILL_FIRE_RL_cpDispatch_F_F_T_E6_T_T && + !WILL_FIRE_RL_cpDispatch_F_F_T_E5_F_F_F_F && + !WILL_FIRE_RL_cpDispatch_F_F_T_E5_F_F_T_F_F && + !WILL_FIRE_RL_cpDispatch_F_F_T_E5_F_F_F_T && + !WILL_FIRE_RL_cpDispatch_F_F_T_E5_F_F_T_F_T && + !WILL_FIRE_RL_cpDispatch_F_F_T_E5_F_F_T_T_T && + !WILL_FIRE_RL_cpDispatch_F_F_T_E5_F_F_T_T_F && + !WILL_FIRE_RL_cpDispatch_F_F_T_E5_F_T && + !WILL_FIRE_RL_cpDispatch_F_F_T_E5_T_F && + !WILL_FIRE_RL_cpDispatch_F_F_T_E5_T_T && + !WILL_FIRE_RL_cpDispatch_F_F_T_E4_F_F_F_F && + !WILL_FIRE_RL_cpDispatch_F_F_T_E4_F_F_F_T && + !WILL_FIRE_RL_cpDispatch_F_F_T_E4_F_F_T_F_F && + !WILL_FIRE_RL_cpDispatch_F_F_T_E4_F_F_T_F_T && + !WILL_FIRE_RL_cpDispatch_F_F_T_E4_F_F_T_T_F && + !WILL_FIRE_RL_cpDispatch_F_F_T_E4_F_F_T_T_T && + !WILL_FIRE_RL_cpDispatch_F_F_T_E4_T_F && + !WILL_FIRE_RL_cpDispatch_F_F_T_E4_F_T && + !WILL_FIRE_RL_cpDispatch_F_F_T_E4_T_T && + !WILL_FIRE_RL_cpDispatch_F_F_T_E3_F_F_F_F && + !WILL_FIRE_RL_cpDispatch_F_F_T_E3_F_F_F_T && + !WILL_FIRE_RL_cpDispatch_F_F_T_E3_F_F_T_F_F && + !WILL_FIRE_RL_cpDispatch_F_F_T_E3_F_F_T_F_T && + !WILL_FIRE_RL_cpDispatch_F_F_T_E3_F_F_T_T_F && + !WILL_FIRE_RL_cpDispatch_F_F_T_E3_F_F_T_T_T && + !WILL_FIRE_RL_cpDispatch_F_F_T_E3_F_T && + !WILL_FIRE_RL_cpDispatch_F_F_T_E3_T_F && + !WILL_FIRE_RL_cpDispatch_F_F_T_E3_T_T && + !WILL_FIRE_RL_cpDispatch_F_F_T_E2_F_F_F_F && + !WILL_FIRE_RL_cpDispatch_F_F_T_E2_F_F_F_T && + !WILL_FIRE_RL_cpDispatch_F_F_T_E2_F_F_T_F_F && + !WILL_FIRE_RL_cpDispatch_F_F_T_E2_F_F_T_F_T && + !WILL_FIRE_RL_cpDispatch_F_F_T_E2_F_F_T_T_F && + !WILL_FIRE_RL_cpDispatch_F_F_T_E2_F_F_T_T_T && + !WILL_FIRE_RL_cpDispatch_F_F_T_E2_F_T && + !WILL_FIRE_RL_cpDispatch_F_F_T_E2_T_F && + !WILL_FIRE_RL_cpDispatch_F_F_T_E2_T_T && + !WILL_FIRE_RL_cpDispatch_F_F_T_E1_F_F_F_F && + !WILL_FIRE_RL_cpDispatch_F_F_T_E1_F_F_F_T && + !WILL_FIRE_RL_cpDispatch_F_F_T_E1_F_F_T_F_F && + !WILL_FIRE_RL_cpDispatch_F_F_T_E1_F_F_T_F_T && + !WILL_FIRE_RL_cpDispatch_F_F_T_E1_F_F_T_T_F && + !WILL_FIRE_RL_cpDispatch_F_F_T_E1_F_F_T_T_T && + !WILL_FIRE_RL_cpDispatch_F_F_T_E1_F_T && + !WILL_FIRE_RL_cpDispatch_F_F_T_E1_T_F && + !WILL_FIRE_RL_cpDispatch_F_F_T_E1_T_T && + !WILL_FIRE_RL_cpDispatch_F_F_T_E0_F_F_F_F && + !WILL_FIRE_RL_cpDispatch_F_F_T_E0_F_F_T_F_F && + !WILL_FIRE_RL_cpDispatch_F_F_T_E0_F_F_T_F_T && + !WILL_FIRE_RL_cpDispatch_F_F_T_E0_F_F_T_T_F && + !WILL_FIRE_RL_cpDispatch_F_F_T_E0_F_F_F_T && + !WILL_FIRE_RL_cpDispatch_F_F_T_E0_F_F_T_T_T && + !WILL_FIRE_RL_cpDispatch_F_F_T_E0_F_T && + !WILL_FIRE_RL_cpDispatch_F_F_T_E0_T_F && + !WILL_FIRE_RL_cpDispatch_F_F_T_E0_T_T ; // rule RL_completeWorkerRead assign WILL_FIRE_RL_completeWorkerRead = cpRespF$FULL_N && - IF_wrkAct_051_EQ_0_052_THEN_wci_respF_i_notEmp_ETC___d6101 && + CASE_wrkAct_028_0_wci_0_respF_i_notEmpty__029__ETC___d5044 && cpReq[64:62] != 3'd0 && cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_T_F && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_T_T && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_F_F_T && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_F_T_F && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_F_T_T && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_T_F && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_T_T && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_F_F_T && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_F_T && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_T_F && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_T_F && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_T_T && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_T_T && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_F_F_F_T && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_F_T && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_F_F_T && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_T_F && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_T_F && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_T_T && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_T_T && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_F_F_F_F_F_T && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_F_F_F_F_F_F && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_F_F_F_F_T && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_F_F_F_T && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_F_F_T && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_F_T_F && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_F_T_T && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_T_F && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_T_T && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_F_F_F_F_F_F && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_F_F_F_F_F_T && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_F_F_F_F_T && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_F_F_F_T && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_F_F_T && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_F_T_F && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_F_T_T && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_T_F && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_T_T && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_F_F_F_F_F_F && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_F_F_F_F_F_T && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_F_F_F_F_T && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_F_F_F_T && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_F_F_T && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_F_T_F && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_F_T_T && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_T_F && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_T_T && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_T_F_F_F_F_F_F && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_T_F_F_F_F_F_T && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_T_F_F_F_T && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_T_F_F_F_F_T && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_T_F_F_T && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_T_F_T_F && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_T_F_T_T && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_T_T_F && - !WILL_FIRE_RL_cpDispatch_F_F_F_F_T_T_T && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_OOB && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_F_F_F_F_F_F && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_F_F_F_F_F_T && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_F_F_F_F_T && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_F_F_F_T && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_F_F_T && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_F_T_F && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_F_T_T && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_T_F && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_T_T && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_F_F_F_F_F_F && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_F_F_F_F_F_T && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_F_F_F_F_T && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_F_F_F_T && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_F_T_F && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_F_F_T && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_F_T_T && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_T_F && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_T_T && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_F_F_F_F_F_F && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_F_F_F_F_F_T && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_F_F_F_F_T && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_F_F_F_T && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_F_F_T && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_F_T_F && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_T_F && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_F_T_T && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_T_T && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_F_F_F_F_F_F && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_F_F_F_F_F_T && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_F_F_F_T && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_F_F_F_F_T && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_F_F_T && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_F_T_F && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_F_T_T && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_T_F && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_T_T && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_F_F_F_F_F_F && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_F_F_F_F_F_T && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_F_F_F_F_T && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_F_F_F_T && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_F_T_F && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_F_F_T && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_F_T_T && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_T_F && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_T_T && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_F_F_F_F_F_F && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_F_F_F_F_F_T && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_F_F_F_F_T && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_F_F_F_T && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_F_F_T && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_F_T_F && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_F_T_T && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_T_F && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_T_T && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_F_F_F_F_F && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_F_F_F_F_T && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_F_F_T && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_F_F_F_T && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_F_T && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_T_F && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_T_T && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_T_F && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_T_T && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_F_F_F_F_F && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_F_F_F_F_T && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_F_F_F_T && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_F_F_T && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_T_F && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_F_T && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_T_T && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_T_F && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_F_F_F_F_F_F && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_F_F_F_F_F_T && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_F_F_F_F_T && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_T_T && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_F_F_F_T && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_F_F_T && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_F_T_F && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_F_T_T && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_T_F && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_T_T && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_F_F_F_F_F && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_F_F_F_F_T && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_F_F_T && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_F_F_F_T && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_F_T && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_T_F && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_T_T && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_T_F && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_T_T && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_F_F_F_F_F_F && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_F_F_F_F_F_T && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_F_F_F_F_T && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_F_F_F_T && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_F_F_T && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_F_T_F && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_F_T_T && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_T_F && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_T_T && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_F_F_F_F_F_T && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_F_F_F_F_F_F && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_F_F_F_F_T && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_F_F_F_T && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_F_F_T && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_F_T_F && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_F_T_T && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_T_F && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_T_T && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_F_F_F_F_F_F && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_F_F_F_F_F_T && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_F_F_F_T && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_F_F_F_F_T && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_F_F_T && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_F_T_F && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_F_T_T && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_T_F && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_T_T && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_F_F_F_F_F && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_F_F_F_F_T && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_F_F_F_T && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_F_F_T && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_F_T && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_T_F && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_T_T && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_T_F && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_T_T && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_F_F_F_F_F && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_F_F_F_F_T && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_F_F_F_T && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_F_F_T && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_F_T && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_T_T && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_T_F && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_T_F && + !WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_T_T && !WILL_FIRE_RL_responseAdminRd ; // rule RL_reqRcv @@ -7348,2068 +7416,1904 @@ module mkOCCP(pciDevice, rom_serverAdapter_outData_deqCalled$whas && rom_serverAdapter_outData_enqData$whas ; - // rule RL_cpDispatch_F_F_T_T_F_F_T_T_F - assign WILL_FIRE_RL_cpDispatch_F_F_T_T_F_F_T_T_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h75857 == 4'd0 && + // rule RL_cpDispatch_F_F_T_E0_F_F_T_T_F + assign WILL_FIRE_RL_cpDispatch_F_F_T_E0_F_F_T_T_F = + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd0 && cpReq[61:60] != 2'd2 && - cpReq[9:6] == 4'h9 && - cpReq[37] && - NOT_cpReq_337_BIT_36_898_906_AND_NOT_wci_busy__ETC___d2907 ; + (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && + cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_AND_cpReq_ETC___d3009 ; - // rule RL_cpDispatch_F_F_T_T_F_F_T_F_F - assign WILL_FIRE_RL_cpDispatch_F_F_T_T_F_F_T_F_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h75857 == 4'd0 && + // rule RL_cpDispatch_F_F_T_E0_F_F_T_F_F + assign WILL_FIRE_RL_cpDispatch_F_F_T_E0_F_F_T_F_F = + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd0 && cpReq[61:60] != 2'd2 && - cpReq[9:6] == 4'h9 && - !cpReq[37] && - NOT_cpReq_337_BIT_36_898_906_AND_NOT_wci_busy__ETC___d2907 ; + (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && + cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_AND_NOT_c_ETC___d3022 ; - // rule RL_cpDispatch_F_F_T_T_T_T - assign WILL_FIRE_RL_cpDispatch_F_F_T_T_T_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h75857 == 4'd0 && + // rule RL_cpDispatch_F_F_T_E0_T_T + assign WILL_FIRE_RL_cpDispatch_F_F_T_E0_T_T = + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd0 && cpReq[61:60] == 2'd2 && - wci_wReset_n_90_AND_NOT_wci_busy_10_860_AND_NO_ETC___d2863 ; + wci_0_wReset_n && + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d2943 && + !dispatched ; - // rule RL_cpDispatch_F_F_T_T_F_F_T_T_T - assign WILL_FIRE_RL_cpDispatch_F_F_T_T_F_F_T_T_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h75857 == 4'd0 && + // rule RL_cpDispatch_F_F_T_E0_F_F_T_T_T + assign WILL_FIRE_RL_cpDispatch_F_F_T_E0_F_F_T_T_T = + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd0 && cpReq[61:60] != 2'd2 && - cpReq[9:6] == 4'h9 && - cpReq[37] && - cpReq_337_BIT_36_898_AND_NOT_wci_busy_10_860_A_ETC___d2899 ; + (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && + cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_AND_cpReq_ETC___d3001 ; - // rule RL_cpDispatch_F_F_T_T_F_F_T_F_T - assign WILL_FIRE_RL_cpDispatch_F_F_T_T_F_F_T_F_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h75857 == 4'd0 && + // rule RL_cpDispatch_F_F_T_E0_F_F_T_F_T + assign WILL_FIRE_RL_cpDispatch_F_F_T_E0_F_F_T_F_T = + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd0 && cpReq[61:60] != 2'd2 && - cpReq[9:6] == 4'h9 && - !cpReq[37] && - cpReq_337_BIT_36_898_AND_NOT_wci_busy_10_860_A_ETC___d2899 ; + (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && + cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_AND_NOT_c_ETC___d3016 ; - // rule RL_cpDispatch_F_F_F_F_T_T_T - assign WILL_FIRE_RL_cpDispatch_F_F_F_F_T_T_T = - cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && - cpReq[64:62] != 3'd3 && - cpReq[64:62] != 3'd0 && - _theResult_____1__h75875 == 4'd0 && - cpReq[37:36] == 2'd2 && - wci_wReset_n_90_AND_NOT_wci_busy_10_860_AND_NO_ETC___d2863 ; + // rule RL_cpDispatch_F_F_F_F_E0_T_T + assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_T_T = + cpReq[64:62] != 3'd1 && + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d3688 ; - // rule RL_cpDispatch_F_F_F_F_T_F_T_T - assign WILL_FIRE_RL_cpDispatch_F_F_F_F_T_F_T_T = - cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && - cpReq[64:62] != 3'd3 && - cpReq[64:62] != 3'd0 && - _theResult_____1__h75875 == 4'd0 && - cpReq[37:36] == 2'd1 && - cpReq[19:9] == 11'd0 && - wci_wReset_n_90_AND_NOT_wci_busy_10_860_AND_NO_ETC___d2863 ; + // rule RL_cpDispatch_F_F_F_F_E0_F_T_T + assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_T_T = + cpReq[64:62] != 3'd1 && + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d3742 ; - // rule RL_cpDispatch_F_F_T_F_T_F_F_T_T_F - assign WILL_FIRE_RL_cpDispatch_F_F_T_F_T_F_F_T_T_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h75857 == 4'd1 && + // rule RL_cpDispatch_F_F_T_E1_F_F_T_T_F + assign WILL_FIRE_RL_cpDispatch_F_F_T_E1_F_F_T_T_F = + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd1 && cpReq[61:60] != 2'd2 && - cpReq[9:6] == 4'h9 && - cpReq[37] && - NOT_cpReq_337_BIT_36_898_906_AND_NOT_wci_busy__ETC___d2974 ; + (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && + cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_AND_cpReq_ETC___d3009 ; - // rule RL_cpDispatch_F_F_T_F_T_F_F_T_F_F - assign WILL_FIRE_RL_cpDispatch_F_F_T_F_T_F_F_T_F_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h75857 == 4'd1 && + // rule RL_cpDispatch_F_F_T_E1_F_F_T_F_F + assign WILL_FIRE_RL_cpDispatch_F_F_T_E1_F_F_T_F_F = + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd1 && cpReq[61:60] != 2'd2 && - cpReq[9:6] == 4'h9 && - !cpReq[37] && - NOT_cpReq_337_BIT_36_898_906_AND_NOT_wci_busy__ETC___d2974 ; + (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && + cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_AND_NOT_c_ETC___d3022 ; - // rule RL_cpDispatch_F_F_T_F_T_T_T - assign WILL_FIRE_RL_cpDispatch_F_F_T_F_T_T_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h75857 == 4'd1 && + // rule RL_cpDispatch_F_F_T_E1_T_T + assign WILL_FIRE_RL_cpDispatch_F_F_T_E1_T_T = + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd1 && cpReq[61:60] == 2'd2 && - wci_wReset_n_1_30_AND_NOT_wci_busy_1_50_943_AN_ETC___d2946 ; + wci_1_wReset_n && + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3049 && + !dispatched ; - // rule RL_cpDispatch_F_F_T_F_T_F_F_T_T_T - assign WILL_FIRE_RL_cpDispatch_F_F_T_F_T_F_F_T_T_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h75857 == 4'd1 && + // rule RL_cpDispatch_F_F_T_E1_F_F_T_T_T + assign WILL_FIRE_RL_cpDispatch_F_F_T_E1_F_F_T_T_T = + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd1 && cpReq[61:60] != 2'd2 && - cpReq[9:6] == 4'h9 && - cpReq[37] && - cpReq_337_BIT_36_898_AND_NOT_wci_busy_1_50_943_ETC___d2967 ; + (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && + cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_AND_cpReq_ETC___d3001 ; - // rule RL_cpDispatch_F_F_T_F_T_F_F_T_F_T - assign WILL_FIRE_RL_cpDispatch_F_F_T_F_T_F_F_T_F_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h75857 == 4'd1 && + // rule RL_cpDispatch_F_F_T_E1_F_F_T_F_T + assign WILL_FIRE_RL_cpDispatch_F_F_T_E1_F_F_T_F_T = + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd1 && cpReq[61:60] != 2'd2 && - cpReq[9:6] == 4'h9 && - !cpReq[37] && - cpReq_337_BIT_36_898_AND_NOT_wci_busy_1_50_943_ETC___d2967 ; + (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && + cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_AND_NOT_c_ETC___d3016 ; - // rule RL_cpDispatch_F_F_F_F_F_T_T_T - assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_T_T = - cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && - cpReq[64:62] != 3'd3 && - cpReq[64:62] != 3'd0 && - _theResult_____1__h75875 == 4'd1 && - cpReq[37:36] == 2'd2 && - wci_wReset_n_1_30_AND_NOT_wci_busy_1_50_943_AN_ETC___d2946 ; + // rule RL_cpDispatch_F_F_F_F_E1_T_T + assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_T_T = + cpReq[64:62] != 3'd1 && + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d3858 ; - // rule RL_cpDispatch_F_F_F_F_F_T_F_T_T - assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_F_T_T = - cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && - cpReq[64:62] != 3'd3 && - cpReq[64:62] != 3'd0 && - _theResult_____1__h75875 == 4'd1 && - cpReq[37:36] == 2'd1 && - cpReq[19:9] == 11'd0 && - wci_wReset_n_1_30_AND_NOT_wci_busy_1_50_943_AN_ETC___d2946 ; + // rule RL_cpDispatch_F_F_F_F_E1_F_T_T + assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_T_T = + cpReq[64:62] != 3'd1 && + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d3883 ; - // rule RL_cpDispatch_F_F_T_F_F_T_F_F_T_T_F - assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_F_F_T_T_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h75857 == 4'd2 && + // rule RL_cpDispatch_F_F_T_E2_F_F_T_T_F + assign WILL_FIRE_RL_cpDispatch_F_F_T_E2_F_F_T_T_F = + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd2 && cpReq[61:60] != 2'd2 && - cpReq[9:6] == 4'h9 && - cpReq[37] && - NOT_cpReq_337_BIT_36_898_906_AND_NOT_wci_busy__ETC___d3037 ; + (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && + cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_AND_cpReq_ETC___d3009 ; - // rule RL_cpDispatch_F_F_T_F_F_T_F_F_T_F_F - assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_F_F_T_F_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h75857 == 4'd2 && + // rule RL_cpDispatch_F_F_T_E2_F_F_T_F_F + assign WILL_FIRE_RL_cpDispatch_F_F_T_E2_F_F_T_F_F = + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd2 && cpReq[61:60] != 2'd2 && - cpReq[9:6] == 4'h9 && - !cpReq[37] && - NOT_cpReq_337_BIT_36_898_906_AND_NOT_wci_busy__ETC___d3037 ; + (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && + cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_AND_NOT_c_ETC___d3022 ; - // rule RL_cpDispatch_F_F_T_F_F_T_T_T - assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_T_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h75857 == 4'd2 && + // rule RL_cpDispatch_F_F_T_E2_T_T + assign WILL_FIRE_RL_cpDispatch_F_F_T_E2_T_T = + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd2 && cpReq[61:60] == 2'd2 && - wci_wReset_n_2_70_AND_NOT_wci_busy_2_90_006_AN_ETC___d3009 ; + wci_2_wReset_n && + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3085 && + !dispatched ; - // rule RL_cpDispatch_F_F_T_F_F_T_F_F_T_T_T - assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_F_F_T_T_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h75857 == 4'd2 && + // rule RL_cpDispatch_F_F_T_E2_F_F_T_T_T + assign WILL_FIRE_RL_cpDispatch_F_F_T_E2_F_F_T_T_T = + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd2 && cpReq[61:60] != 2'd2 && - cpReq[9:6] == 4'h9 && - cpReq[37] && - cpReq_337_BIT_36_898_AND_NOT_wci_busy_2_90_006_ETC___d3030 ; + (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && + cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_AND_cpReq_ETC___d3001 ; - // rule RL_cpDispatch_F_F_T_F_F_T_F_F_T_F_T - assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_F_F_T_F_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h75857 == 4'd2 && + // rule RL_cpDispatch_F_F_T_E2_F_F_T_F_T + assign WILL_FIRE_RL_cpDispatch_F_F_T_E2_F_F_T_F_T = + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd2 && cpReq[61:60] != 2'd2 && - cpReq[9:6] == 4'h9 && - !cpReq[37] && - cpReq_337_BIT_36_898_AND_NOT_wci_busy_2_90_006_ETC___d3030 ; + (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && + cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_AND_NOT_c_ETC___d3016 ; - // rule RL_cpDispatch_F_F_F_F_F_F_T_T_T - assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_T_T = - cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && - cpReq[64:62] != 3'd3 && - cpReq[64:62] != 3'd0 && - _theResult_____1__h75875 == 4'd2 && - cpReq[37:36] == 2'd2 && - wci_wReset_n_2_70_AND_NOT_wci_busy_2_90_006_AN_ETC___d3009 ; + // rule RL_cpDispatch_F_F_F_F_E2_T_T + assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_T_T = + cpReq[64:62] != 3'd1 && + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d3935 ; - // rule RL_cpDispatch_F_F_F_F_F_F_T_F_T_T - assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_F_T_T = - cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && - cpReq[64:62] != 3'd3 && - cpReq[64:62] != 3'd0 && - _theResult_____1__h75875 == 4'd2 && - cpReq[37:36] == 2'd1 && - cpReq[19:9] == 11'd0 && - wci_wReset_n_2_70_AND_NOT_wci_busy_2_90_006_AN_ETC___d3009 ; + // rule RL_cpDispatch_F_F_F_F_E2_F_T_T + assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_F_T_T = + cpReq[64:62] != 3'd1 && + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d3958 ; - // rule RL_cpDispatch_F_F_T_F_F_F_T_F_F_T_T_F - assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_F_F_T_T_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h75857 == 4'd3 && + // rule RL_cpDispatch_F_F_T_E3_F_F_T_T_F + assign WILL_FIRE_RL_cpDispatch_F_F_T_E3_F_F_T_T_F = + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd3 && cpReq[61:60] != 2'd2 && - cpReq[9:6] == 4'h9 && - cpReq[37] && - NOT_cpReq_337_BIT_36_898_906_AND_NOT_wci_busy__ETC___d3100 ; + (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && + cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_AND_cpReq_ETC___d3009 ; - // rule RL_cpDispatch_F_F_T_F_F_F_T_F_F_T_F_F - assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_F_F_T_F_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h75857 == 4'd3 && + // rule RL_cpDispatch_F_F_T_E3_F_F_T_F_F + assign WILL_FIRE_RL_cpDispatch_F_F_T_E3_F_F_T_F_F = + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd3 && cpReq[61:60] != 2'd2 && - cpReq[9:6] == 4'h9 && - !cpReq[37] && - NOT_cpReq_337_BIT_36_898_906_AND_NOT_wci_busy__ETC___d3100 ; + (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && + cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_AND_NOT_c_ETC___d3022 ; - // rule RL_cpDispatch_F_F_T_F_F_F_T_T_T - assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_T_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h75857 == 4'd3 && + // rule RL_cpDispatch_F_F_T_E3_T_T + assign WILL_FIRE_RL_cpDispatch_F_F_T_E3_T_T = + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd3 && cpReq[61:60] == 2'd2 && - wci_wReset_n_3_10_AND_NOT_wci_busy_3_30_069_AN_ETC___d3072 ; + wci_3_wReset_n && + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3121 && + !dispatched ; - // rule RL_cpDispatch_F_F_T_F_F_F_T_F_F_T_T_T - assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_F_F_T_T_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h75857 == 4'd3 && + // rule RL_cpDispatch_F_F_T_E3_F_F_T_T_T + assign WILL_FIRE_RL_cpDispatch_F_F_T_E3_F_F_T_T_T = + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd3 && cpReq[61:60] != 2'd2 && - cpReq[9:6] == 4'h9 && - cpReq[37] && - cpReq_337_BIT_36_898_AND_NOT_wci_busy_3_30_069_ETC___d3093 ; + (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && + cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_AND_cpReq_ETC___d3001 ; - // rule RL_cpDispatch_F_F_T_F_F_F_T_F_F_T_F_T - assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_F_F_T_F_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h75857 == 4'd3 && + // rule RL_cpDispatch_F_F_T_E3_F_F_T_F_T + assign WILL_FIRE_RL_cpDispatch_F_F_T_E3_F_F_T_F_T = + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd3 && cpReq[61:60] != 2'd2 && - cpReq[9:6] == 4'h9 && - !cpReq[37] && - cpReq_337_BIT_36_898_AND_NOT_wci_busy_3_30_069_ETC___d3093 ; + (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && + cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_AND_NOT_c_ETC___d3016 ; - // rule RL_cpDispatch_F_F_F_F_F_F_F_T_T_T - assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_T_T = - cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && - cpReq[64:62] != 3'd3 && - cpReq[64:62] != 3'd0 && - _theResult_____1__h75875 == 4'd3 && - cpReq[37:36] == 2'd2 && - wci_wReset_n_3_10_AND_NOT_wci_busy_3_30_069_AN_ETC___d3072 ; + // rule RL_cpDispatch_F_F_F_F_E3_T_T + assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_T_T = + cpReq[64:62] != 3'd1 && + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4010 ; - // rule RL_cpDispatch_F_F_F_F_F_F_F_T_F_T_T - assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_F_T_T = - cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && - cpReq[64:62] != 3'd3 && - cpReq[64:62] != 3'd0 && - _theResult_____1__h75875 == 4'd3 && - cpReq[37:36] == 2'd1 && - cpReq[19:9] == 11'd0 && - wci_wReset_n_3_10_AND_NOT_wci_busy_3_30_069_AN_ETC___d3072 ; + // rule RL_cpDispatch_F_F_F_F_E3_F_T_T + assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_F_T_T = + cpReq[64:62] != 3'd1 && + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4033 ; - // rule RL_cpDispatch_F_F_T_F_F_F_F_T_F_F_T_T_F - assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_F_F_T_T_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h75857 == 4'd4 && + // rule RL_cpDispatch_F_F_T_E4_F_F_T_T_F + assign WILL_FIRE_RL_cpDispatch_F_F_T_E4_F_F_T_T_F = + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd4 && cpReq[61:60] != 2'd2 && - cpReq[9:6] == 4'h9 && - cpReq[37] && - NOT_cpReq_337_BIT_36_898_906_AND_NOT_wci_busy__ETC___d3163 ; + (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && + cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_AND_cpReq_ETC___d3009 ; - // rule RL_cpDispatch_F_F_T_F_F_F_F_T_F_F_T_F_F - assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_F_F_T_F_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h75857 == 4'd4 && + // rule RL_cpDispatch_F_F_T_E4_F_F_T_F_F + assign WILL_FIRE_RL_cpDispatch_F_F_T_E4_F_F_T_F_F = + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd4 && cpReq[61:60] != 2'd2 && - cpReq[9:6] == 4'h9 && - !cpReq[37] && - NOT_cpReq_337_BIT_36_898_906_AND_NOT_wci_busy__ETC___d3163 ; + (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && + cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_AND_NOT_c_ETC___d3022 ; - // rule RL_cpDispatch_F_F_T_F_F_F_F_T_T_T - assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_T_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h75857 == 4'd4 && + // rule RL_cpDispatch_F_F_T_E4_T_T + assign WILL_FIRE_RL_cpDispatch_F_F_T_E4_T_T = + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd4 && cpReq[61:60] == 2'd2 && - wci_wReset_n_4_50_AND_NOT_wci_busy_4_70_132_AN_ETC___d3135 ; + wci_4_wReset_n && + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3157 && + !dispatched ; - // rule RL_cpDispatch_F_F_T_F_F_F_F_T_F_F_T_T_T - assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_F_F_T_T_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h75857 == 4'd4 && + // rule RL_cpDispatch_F_F_T_E4_F_F_T_T_T + assign WILL_FIRE_RL_cpDispatch_F_F_T_E4_F_F_T_T_T = + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd4 && cpReq[61:60] != 2'd2 && - cpReq[9:6] == 4'h9 && - cpReq[37] && - cpReq_337_BIT_36_898_AND_NOT_wci_busy_4_70_132_ETC___d3156 ; + (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && + cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_AND_cpReq_ETC___d3001 ; - // rule RL_cpDispatch_F_F_T_F_F_F_F_T_F_F_T_F_T - assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_F_F_T_F_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h75857 == 4'd4 && + // rule RL_cpDispatch_F_F_T_E4_F_F_T_F_T + assign WILL_FIRE_RL_cpDispatch_F_F_T_E4_F_F_T_F_T = + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd4 && cpReq[61:60] != 2'd2 && - cpReq[9:6] == 4'h9 && - !cpReq[37] && - cpReq_337_BIT_36_898_AND_NOT_wci_busy_4_70_132_ETC___d3156 ; + (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && + cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_AND_NOT_c_ETC___d3016 ; - // rule RL_cpDispatch_F_F_F_F_F_F_F_F_T_T_T - assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_T_T = - cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && - cpReq[64:62] != 3'd3 && - cpReq[64:62] != 3'd0 && - _theResult_____1__h75875 == 4'd4 && - cpReq[37:36] == 2'd2 && - wci_wReset_n_4_50_AND_NOT_wci_busy_4_70_132_AN_ETC___d3135 ; + // rule RL_cpDispatch_F_F_F_F_E4_T_T + assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_T_T = + cpReq[64:62] != 3'd1 && + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4085 ; - // rule RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_T_T - assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_T_T = - cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && - cpReq[64:62] != 3'd3 && - cpReq[64:62] != 3'd0 && - _theResult_____1__h75875 == 4'd4 && - cpReq[37:36] == 2'd1 && - cpReq[19:9] == 11'd0 && - wci_wReset_n_4_50_AND_NOT_wci_busy_4_70_132_AN_ETC___d3135 ; + // rule RL_cpDispatch_F_F_F_F_E4_F_T_T + assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_F_T_T = + cpReq[64:62] != 3'd1 && + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4108 ; - // rule RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_F_T_T_F - assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_F_T_T_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h75857 == 4'd5 && + // rule RL_cpDispatch_F_F_T_E5_F_F_T_T_F + assign WILL_FIRE_RL_cpDispatch_F_F_T_E5_F_F_T_T_F = + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd5 && cpReq[61:60] != 2'd2 && - cpReq[9:6] == 4'h9 && - cpReq[37] && - NOT_cpReq_337_BIT_36_898_906_AND_NOT_wci_busy__ETC___d3226 ; + (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && + cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_AND_cpReq_ETC___d3009 ; - // rule RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_F_T_F_F - assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_F_T_F_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h75857 == 4'd5 && + // rule RL_cpDispatch_F_F_T_E5_F_F_T_F_F + assign WILL_FIRE_RL_cpDispatch_F_F_T_E5_F_F_T_F_F = + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd5 && cpReq[61:60] != 2'd2 && - cpReq[9:6] == 4'h9 && - !cpReq[37] && - NOT_cpReq_337_BIT_36_898_906_AND_NOT_wci_busy__ETC___d3226 ; + (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && + cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_AND_NOT_c_ETC___d3022 ; - // rule RL_cpDispatch_F_F_T_F_F_F_F_F_T_T_T - assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_T_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h75857 == 4'd5 && + // rule RL_cpDispatch_F_F_T_E5_T_T + assign WILL_FIRE_RL_cpDispatch_F_F_T_E5_T_T = + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd5 && cpReq[61:60] == 2'd2 && - wci_wReset_n_5_90_AND_NOT_wci_busy_5_10_195_AN_ETC___d3198 ; + wci_5_wReset_n && + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3193 && + !dispatched ; - // rule RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_F_T_T_T - assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_F_T_T_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h75857 == 4'd5 && + // rule RL_cpDispatch_F_F_T_E5_F_F_T_T_T + assign WILL_FIRE_RL_cpDispatch_F_F_T_E5_F_F_T_T_T = + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd5 && cpReq[61:60] != 2'd2 && - cpReq[9:6] == 4'h9 && - cpReq[37] && - cpReq_337_BIT_36_898_AND_NOT_wci_busy_5_10_195_ETC___d3219 ; + (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && + cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_AND_cpReq_ETC___d3001 ; - // rule RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_F_T_F_T - assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_F_T_F_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h75857 == 4'd5 && + // rule RL_cpDispatch_F_F_T_E5_F_F_T_F_T + assign WILL_FIRE_RL_cpDispatch_F_F_T_E5_F_F_T_F_T = + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd5 && cpReq[61:60] != 2'd2 && - cpReq[9:6] == 4'h9 && - !cpReq[37] && - cpReq_337_BIT_36_898_AND_NOT_wci_busy_5_10_195_ETC___d3219 ; + (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && + cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_AND_NOT_c_ETC___d3016 ; - // rule RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_T_T - assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_T_T = - cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && - cpReq[64:62] != 3'd3 && - cpReq[64:62] != 3'd0 && - _theResult_____1__h75875 == 4'd5 && - cpReq[37:36] == 2'd2 && - wci_wReset_n_5_90_AND_NOT_wci_busy_5_10_195_AN_ETC___d3198 ; + // rule RL_cpDispatch_F_F_F_F_E5_T_T + assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_T_T = + cpReq[64:62] != 3'd1 && + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4160 ; - // rule RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_T_T - assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_T_T = - cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && - cpReq[64:62] != 3'd3 && - cpReq[64:62] != 3'd0 && - _theResult_____1__h75875 == 4'd5 && - cpReq[37:36] == 2'd1 && - cpReq[19:9] == 11'd0 && - wci_wReset_n_5_90_AND_NOT_wci_busy_5_10_195_AN_ETC___d3198 ; + // rule RL_cpDispatch_F_F_F_F_E5_F_T_T + assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_T_T = + cpReq[64:62] != 3'd1 && + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4183 ; - // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_F_F_T_T_F - assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_F_F_T_T_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h75857 == 4'd6 && + // rule RL_cpDispatch_F_F_T_E6_F_F_T_T_F + assign WILL_FIRE_RL_cpDispatch_F_F_T_E6_F_F_T_T_F = + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd6 && cpReq[61:60] != 2'd2 && - cpReq[9:6] == 4'h9 && - cpReq[37] && - NOT_cpReq_337_BIT_36_898_906_AND_NOT_wci_busy__ETC___d3289 ; + (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && + cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_AND_cpReq_ETC___d3009 ; - // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_F_F_T_F_F - assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_F_F_T_F_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h75857 == 4'd6 && + // rule RL_cpDispatch_F_F_T_E6_F_F_T_F_F + assign WILL_FIRE_RL_cpDispatch_F_F_T_E6_F_F_T_F_F = + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd6 && cpReq[61:60] != 2'd2 && - cpReq[9:6] == 4'h9 && - !cpReq[37] && - NOT_cpReq_337_BIT_36_898_906_AND_NOT_wci_busy__ETC___d3289 ; + (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && + cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_AND_NOT_c_ETC___d3022 ; - // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_T_T - assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_T_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h75857 == 4'd6 && + // rule RL_cpDispatch_F_F_T_E6_T_T + assign WILL_FIRE_RL_cpDispatch_F_F_T_E6_T_T = + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd6 && cpReq[61:60] == 2'd2 && - wci_wReset_n_6_030_AND_NOT_wci_busy_6_050_258__ETC___d3261 ; + wci_6_wReset_n && + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3229 && + !dispatched ; - // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_F_F_T_T_T - assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_F_F_T_T_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h75857 == 4'd6 && + // rule RL_cpDispatch_F_F_T_E6_F_F_T_T_T + assign WILL_FIRE_RL_cpDispatch_F_F_T_E6_F_F_T_T_T = + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd6 && cpReq[61:60] != 2'd2 && - cpReq[9:6] == 4'h9 && - cpReq[37] && - cpReq_337_BIT_36_898_AND_NOT_wci_busy_6_050_25_ETC___d3282 ; + (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && + cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_AND_cpReq_ETC___d3001 ; - // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_F_F_T_F_T - assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_F_F_T_F_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h75857 == 4'd6 && + // rule RL_cpDispatch_F_F_T_E6_F_F_T_F_T + assign WILL_FIRE_RL_cpDispatch_F_F_T_E6_F_F_T_F_T = + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd6 && cpReq[61:60] != 2'd2 && - cpReq[9:6] == 4'h9 && - !cpReq[37] && - cpReq_337_BIT_36_898_AND_NOT_wci_busy_6_050_25_ETC___d3282 ; + (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && + cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_AND_NOT_c_ETC___d3016 ; - // rule RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_T_T - assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_T_T = - cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && - cpReq[64:62] != 3'd3 && - cpReq[64:62] != 3'd0 && - _theResult_____1__h75875 == 4'd6 && - cpReq[37:36] == 2'd2 && - wci_wReset_n_6_030_AND_NOT_wci_busy_6_050_258__ETC___d3261 ; + // rule RL_cpDispatch_F_F_F_F_E6_T_T + assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_T_T = + cpReq[64:62] != 3'd1 && + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4235 ; - // rule RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_F_T_T - assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_F_T_T = - cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && - cpReq[64:62] != 3'd3 && - cpReq[64:62] != 3'd0 && - _theResult_____1__h75875 == 4'd6 && - cpReq[37:36] == 2'd1 && - cpReq[19:9] == 11'd0 && - wci_wReset_n_6_030_AND_NOT_wci_busy_6_050_258__ETC___d3261 ; + // rule RL_cpDispatch_F_F_F_F_E6_F_T_T + assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_F_T_T = + cpReq[64:62] != 3'd1 && + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4258 ; - // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_F_F_T_T_F - assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_F_F_T_T_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h75857 == 4'd7 && + // rule RL_cpDispatch_F_F_T_E7_F_F_T_T_F + assign WILL_FIRE_RL_cpDispatch_F_F_T_E7_F_F_T_T_F = + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd7 && cpReq[61:60] != 2'd2 && - cpReq[9:6] == 4'h9 && - cpReq[37] && - NOT_cpReq_337_BIT_36_898_906_AND_NOT_wci_busy__ETC___d3352 ; + (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && + cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_AND_cpReq_ETC___d3009 ; - // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_F_F_T_F_F - assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_F_F_T_F_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h75857 == 4'd7 && + // rule RL_cpDispatch_F_F_T_E7_F_F_T_F_F + assign WILL_FIRE_RL_cpDispatch_F_F_T_E7_F_F_T_F_F = + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd7 && cpReq[61:60] != 2'd2 && - cpReq[9:6] == 4'h9 && - !cpReq[37] && - NOT_cpReq_337_BIT_36_898_906_AND_NOT_wci_busy__ETC___d3352 ; + (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && + cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_AND_NOT_c_ETC___d3022 ; - // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_T_T - assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_T_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h75857 == 4'd7 && + // rule RL_cpDispatch_F_F_T_E7_T_T + assign WILL_FIRE_RL_cpDispatch_F_F_T_E7_T_T = + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd7 && cpReq[61:60] == 2'd2 && - wci_wReset_n_7_170_AND_NOT_wci_busy_7_190_321__ETC___d3324 ; + wci_7_wReset_n && + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3265 && + !dispatched ; - // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_F_F_T_T_T - assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_F_F_T_T_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h75857 == 4'd7 && + // rule RL_cpDispatch_F_F_T_E7_F_F_T_T_T + assign WILL_FIRE_RL_cpDispatch_F_F_T_E7_F_F_T_T_T = + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd7 && cpReq[61:60] != 2'd2 && - cpReq[9:6] == 4'h9 && - cpReq[37] && - cpReq_337_BIT_36_898_AND_NOT_wci_busy_7_190_32_ETC___d3345 ; + (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && + cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_AND_cpReq_ETC___d3001 ; - // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_F_F_T_F_T - assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_F_F_T_F_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h75857 == 4'd7 && + // rule RL_cpDispatch_F_F_T_E7_F_F_T_F_T + assign WILL_FIRE_RL_cpDispatch_F_F_T_E7_F_F_T_F_T = + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd7 && cpReq[61:60] != 2'd2 && - cpReq[9:6] == 4'h9 && - !cpReq[37] && - cpReq_337_BIT_36_898_AND_NOT_wci_busy_7_190_32_ETC___d3345 ; + (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && + cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_AND_NOT_c_ETC___d3016 ; - // rule RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_T_T - assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_T_T = - cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && - cpReq[64:62] != 3'd3 && - cpReq[64:62] != 3'd0 && - _theResult_____1__h75875 == 4'd7 && - cpReq[37:36] == 2'd2 && - wci_wReset_n_7_170_AND_NOT_wci_busy_7_190_321__ETC___d3324 ; + // rule RL_cpDispatch_F_F_F_F_E7_T_T + assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_T_T = + cpReq[64:62] != 3'd1 && + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4310 ; - // rule RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T - assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T = - cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && - cpReq[64:62] != 3'd3 && - cpReq[64:62] != 3'd0 && - _theResult_____1__h75875 == 4'd7 && - cpReq[37:36] == 2'd1 && - cpReq[19:9] == 11'd0 && - wci_wReset_n_7_170_AND_NOT_wci_busy_7_190_321__ETC___d3324 ; + // rule RL_cpDispatch_F_F_F_F_E7_F_T_T + assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_T_T = + cpReq[64:62] != 3'd1 && + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4333 ; - // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_F_F_T_T_F - assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_F_F_T_T_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h75857 == 4'd8 && + // rule RL_cpDispatch_F_F_T_E8_F_F_T_T_F + assign WILL_FIRE_RL_cpDispatch_F_F_T_E8_F_F_T_T_F = + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd8 && cpReq[61:60] != 2'd2 && - cpReq[9:6] == 4'h9 && - cpReq[37] && - NOT_cpReq_337_BIT_36_898_906_AND_NOT_wci_busy__ETC___d3415 ; + (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && + cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_AND_cpReq_ETC___d3009 ; - // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_F_F_T_F_F - assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_F_F_T_F_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h75857 == 4'd8 && + // rule RL_cpDispatch_F_F_T_E8_F_F_T_F_F + assign WILL_FIRE_RL_cpDispatch_F_F_T_E8_F_F_T_F_F = + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd8 && cpReq[61:60] != 2'd2 && - cpReq[9:6] == 4'h9 && - !cpReq[37] && - NOT_cpReq_337_BIT_36_898_906_AND_NOT_wci_busy__ETC___d3415 ; + (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && + cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_AND_NOT_c_ETC___d3022 ; - // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_T_T - assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_T_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h75857 == 4'd8 && + // rule RL_cpDispatch_F_F_T_E8_T_T + assign WILL_FIRE_RL_cpDispatch_F_F_T_E8_T_T = + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd8 && cpReq[61:60] == 2'd2 && - wci_wReset_n_8_310_AND_NOT_wci_busy_8_330_384__ETC___d3387 ; + wci_8_wReset_n && + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3301 && + !dispatched ; - // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_F_F_T_T_T - assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_F_F_T_T_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h75857 == 4'd8 && + // rule RL_cpDispatch_F_F_T_E8_F_F_T_T_T + assign WILL_FIRE_RL_cpDispatch_F_F_T_E8_F_F_T_T_T = + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd8 && cpReq[61:60] != 2'd2 && - cpReq[9:6] == 4'h9 && - cpReq[37] && - cpReq_337_BIT_36_898_AND_NOT_wci_busy_8_330_38_ETC___d3408 ; + (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && + cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_AND_cpReq_ETC___d3001 ; - // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_F_F_T_F_T - assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_F_F_T_F_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h75857 == 4'd8 && + // rule RL_cpDispatch_F_F_T_E8_F_F_T_F_T + assign WILL_FIRE_RL_cpDispatch_F_F_T_E8_F_F_T_F_T = + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd8 && cpReq[61:60] != 2'd2 && - cpReq[9:6] == 4'h9 && - !cpReq[37] && - cpReq_337_BIT_36_898_AND_NOT_wci_busy_8_330_38_ETC___d3408 ; + (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && + cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_AND_NOT_c_ETC___d3016 ; - // rule RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T - assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T = - cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && - cpReq[64:62] != 3'd3 && - cpReq[64:62] != 3'd0 && - _theResult_____1__h75875 == 4'd8 && - cpReq[37:36] == 2'd2 && - wci_wReset_n_8_310_AND_NOT_wci_busy_8_330_384__ETC___d3387 ; + // rule RL_cpDispatch_F_F_F_F_E8_T_T + assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_T_T = + cpReq[64:62] != 3'd1 && + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4385 ; - // rule RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T - assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T = - cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && - cpReq[64:62] != 3'd3 && - cpReq[64:62] != 3'd0 && - _theResult_____1__h75875 == 4'd8 && - cpReq[37:36] == 2'd1 && - cpReq[19:9] == 11'd0 && - wci_wReset_n_8_310_AND_NOT_wci_busy_8_330_384__ETC___d3387 ; + // rule RL_cpDispatch_F_F_F_F_E8_F_T_T + assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_T_T = + cpReq[64:62] != 3'd1 && + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4408 ; - // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_F_F_T_T_F - assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_F_F_T_T_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h75857 == 4'd9 && + // rule RL_cpDispatch_F_F_T_E9_F_F_T_T_F + assign WILL_FIRE_RL_cpDispatch_F_F_T_E9_F_F_T_T_F = + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd9 && cpReq[61:60] != 2'd2 && - cpReq[9:6] == 4'h9 && - cpReq[37] && - NOT_cpReq_337_BIT_36_898_906_AND_NOT_wci_busy__ETC___d3478 ; + (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && + cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_AND_cpReq_ETC___d3009 ; - // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_F_F_T_F_F - assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_F_F_T_F_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h75857 == 4'd9 && + // rule RL_cpDispatch_F_F_T_E9_F_F_T_F_F + assign WILL_FIRE_RL_cpDispatch_F_F_T_E9_F_F_T_F_F = + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd9 && cpReq[61:60] != 2'd2 && - cpReq[9:6] == 4'h9 && - !cpReq[37] && - NOT_cpReq_337_BIT_36_898_906_AND_NOT_wci_busy__ETC___d3478 ; + (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && + cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_AND_NOT_c_ETC___d3022 ; - // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_T_T - assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_T_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h75857 == 4'd9 && + // rule RL_cpDispatch_F_F_T_E9_T_T + assign WILL_FIRE_RL_cpDispatch_F_F_T_E9_T_T = + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd9 && cpReq[61:60] == 2'd2 && - wci_wReset_n_9_450_AND_NOT_wci_busy_9_470_447__ETC___d3450 ; + wci_9_wReset_n && + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3337 && + !dispatched ; - // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_F_F_T_T_T - assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_F_F_T_T_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h75857 == 4'd9 && + // rule RL_cpDispatch_F_F_T_E9_F_F_T_T_T + assign WILL_FIRE_RL_cpDispatch_F_F_T_E9_F_F_T_T_T = + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd9 && cpReq[61:60] != 2'd2 && - cpReq[9:6] == 4'h9 && - cpReq[37] && - cpReq_337_BIT_36_898_AND_NOT_wci_busy_9_470_44_ETC___d3471 ; + (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && + cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_AND_cpReq_ETC___d3001 ; - // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_F_F_T_F_T - assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_F_F_T_F_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h75857 == 4'd9 && + // rule RL_cpDispatch_F_F_T_E9_F_F_T_F_T + assign WILL_FIRE_RL_cpDispatch_F_F_T_E9_F_F_T_F_T = + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd9 && cpReq[61:60] != 2'd2 && - cpReq[9:6] == 4'h9 && - !cpReq[37] && - cpReq_337_BIT_36_898_AND_NOT_wci_busy_9_470_44_ETC___d3471 ; + (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && + cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_AND_NOT_c_ETC___d3016 ; - // rule RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T - assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T = - cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && - cpReq[64:62] != 3'd3 && - cpReq[64:62] != 3'd0 && - _theResult_____1__h75875 == 4'd9 && - cpReq[37:36] == 2'd2 && - wci_wReset_n_9_450_AND_NOT_wci_busy_9_470_447__ETC___d3450 ; + // rule RL_cpDispatch_F_F_F_F_E9_T_T + assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_T_T = + cpReq[64:62] != 3'd1 && + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4460 ; - // rule RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T - assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T = - cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && - cpReq[64:62] != 3'd3 && - cpReq[64:62] != 3'd0 && - _theResult_____1__h75875 == 4'd9 && - cpReq[37:36] == 2'd1 && - cpReq[19:9] == 11'd0 && - wci_wReset_n_9_450_AND_NOT_wci_busy_9_470_447__ETC___d3450 ; + // rule RL_cpDispatch_F_F_F_F_E9_F_T_T + assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_F_T_T = + cpReq[64:62] != 3'd1 && + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4483 ; - // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_F - assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h75857 == 4'd10 && + // rule RL_cpDispatch_F_F_T_E10_F_F_T_T_F + assign WILL_FIRE_RL_cpDispatch_F_F_T_E10_F_F_T_T_F = + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd10 && cpReq[61:60] != 2'd2 && - cpReq[9:6] == 4'h9 && - cpReq[37] && - NOT_cpReq_337_BIT_36_898_906_AND_NOT_wci_busy__ETC___d3541 ; + (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && + cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_AND_cpReq_ETC___d3009 ; - // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_F - assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h75857 == 4'd10 && + // rule RL_cpDispatch_F_F_T_E10_F_F_T_F_F + assign WILL_FIRE_RL_cpDispatch_F_F_T_E10_F_F_T_F_F = + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd10 && cpReq[61:60] != 2'd2 && - cpReq[9:6] == 4'h9 && - !cpReq[37] && - NOT_cpReq_337_BIT_36_898_906_AND_NOT_wci_busy__ETC___d3541 ; + (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && + cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_AND_NOT_c_ETC___d3022 ; - // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_T_T - assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_T_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h75857 == 4'd10 && + // rule RL_cpDispatch_F_F_T_E10_T_T + assign WILL_FIRE_RL_cpDispatch_F_F_T_E10_T_T = + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd10 && cpReq[61:60] == 2'd2 && - wci_wReset_n_10_590_AND_NOT_wci_busy_10_610_51_ETC___d3513 ; + wci_10_wReset_n && + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3373 && + !dispatched ; - // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_T - assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h75857 == 4'd10 && + // rule RL_cpDispatch_F_F_T_E10_F_F_T_T_T + assign WILL_FIRE_RL_cpDispatch_F_F_T_E10_F_F_T_T_T = + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd10 && cpReq[61:60] != 2'd2 && - cpReq[9:6] == 4'h9 && - cpReq[37] && - cpReq_337_BIT_36_898_AND_NOT_wci_busy_10_610_5_ETC___d3534 ; + (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && + cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_AND_cpReq_ETC___d3001 ; - // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_T - assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h75857 == 4'd10 && + // rule RL_cpDispatch_F_F_T_E10_F_F_T_F_T + assign WILL_FIRE_RL_cpDispatch_F_F_T_E10_F_F_T_F_T = + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd10 && cpReq[61:60] != 2'd2 && - cpReq[9:6] == 4'h9 && - !cpReq[37] && - cpReq_337_BIT_36_898_AND_NOT_wci_busy_10_610_5_ETC___d3534 ; + (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && + cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_AND_NOT_c_ETC___d3016 ; - // rule RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T - assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T = - cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && - cpReq[64:62] != 3'd3 && - cpReq[64:62] != 3'd0 && - _theResult_____1__h75875 == 4'd10 && - cpReq[37:36] == 2'd2 && - wci_wReset_n_10_590_AND_NOT_wci_busy_10_610_51_ETC___d3513 ; + // rule RL_cpDispatch_F_F_F_F_E10_T_T + assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_T_T = + cpReq[64:62] != 3'd1 && + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4535 ; - // rule RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T - assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T = - cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && - cpReq[64:62] != 3'd3 && - cpReq[64:62] != 3'd0 && - _theResult_____1__h75875 == 4'd10 && - cpReq[37:36] == 2'd1 && - cpReq[19:9] == 11'd0 && - wci_wReset_n_10_590_AND_NOT_wci_busy_10_610_51_ETC___d3513 ; + // rule RL_cpDispatch_F_F_F_F_E10_F_T_T + assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_F_T_T = + cpReq[64:62] != 3'd1 && + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4558 ; - // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_F - assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h75857 == 4'd11 && + // rule RL_cpDispatch_F_F_T_E11_F_F_T_T_F + assign WILL_FIRE_RL_cpDispatch_F_F_T_E11_F_F_T_T_F = + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd11 && cpReq[61:60] != 2'd2 && - cpReq[9:6] == 4'h9 && - cpReq[37] && - NOT_cpReq_337_BIT_36_898_906_AND_NOT_wci_busy__ETC___d3604 ; + (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && + cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_AND_cpReq_ETC___d3009 ; - // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_F - assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h75857 == 4'd11 && + // rule RL_cpDispatch_F_F_T_E11_F_F_T_F_F + assign WILL_FIRE_RL_cpDispatch_F_F_T_E11_F_F_T_F_F = + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd11 && cpReq[61:60] != 2'd2 && - cpReq[9:6] == 4'h9 && - !cpReq[37] && - NOT_cpReq_337_BIT_36_898_906_AND_NOT_wci_busy__ETC___d3604 ; + (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && + cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_AND_NOT_c_ETC___d3022 ; - // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_T_T - assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_T_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h75857 == 4'd11 && + // rule RL_cpDispatch_F_F_T_E11_T_T + assign WILL_FIRE_RL_cpDispatch_F_F_T_E11_T_T = + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd11 && cpReq[61:60] == 2'd2 && - wci_wReset_n_11_730_AND_NOT_wci_busy_11_750_57_ETC___d3576 ; + wci_11_wReset_n && + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3409 && + !dispatched ; - // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_T - assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h75857 == 4'd11 && + // rule RL_cpDispatch_F_F_T_E11_F_F_T_T_T + assign WILL_FIRE_RL_cpDispatch_F_F_T_E11_F_F_T_T_T = + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd11 && cpReq[61:60] != 2'd2 && - cpReq[9:6] == 4'h9 && - cpReq[37] && - cpReq_337_BIT_36_898_AND_NOT_wci_busy_11_750_5_ETC___d3597 ; + (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && + cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_AND_cpReq_ETC___d3001 ; - // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_T - assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h75857 == 4'd11 && + // rule RL_cpDispatch_F_F_T_E11_F_F_T_F_T + assign WILL_FIRE_RL_cpDispatch_F_F_T_E11_F_F_T_F_T = + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd11 && cpReq[61:60] != 2'd2 && - cpReq[9:6] == 4'h9 && - !cpReq[37] && - cpReq_337_BIT_36_898_AND_NOT_wci_busy_11_750_5_ETC___d3597 ; + (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && + cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_AND_NOT_c_ETC___d3016 ; - // rule RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T - assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T = - cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && - cpReq[64:62] != 3'd3 && - cpReq[64:62] != 3'd0 && - _theResult_____1__h75875 == 4'd11 && - cpReq[37:36] == 2'd2 && - wci_wReset_n_11_730_AND_NOT_wci_busy_11_750_57_ETC___d3576 ; + // rule RL_cpDispatch_F_F_F_F_E11_T_T + assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_T_T = + cpReq[64:62] != 3'd1 && + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4610 ; - // rule RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T - assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T = - cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && - cpReq[64:62] != 3'd3 && - cpReq[64:62] != 3'd0 && - _theResult_____1__h75875 == 4'd11 && - cpReq[37:36] == 2'd1 && - cpReq[19:9] == 11'd0 && - wci_wReset_n_11_730_AND_NOT_wci_busy_11_750_57_ETC___d3576 ; + // rule RL_cpDispatch_F_F_F_F_E11_F_T_T + assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_F_T_T = + cpReq[64:62] != 3'd1 && + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4633 ; - // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_F - assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h75857 == 4'd12 && + // rule RL_cpDispatch_F_F_T_E12_F_F_T_T_F + assign WILL_FIRE_RL_cpDispatch_F_F_T_E12_F_F_T_T_F = + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd12 && cpReq[61:60] != 2'd2 && - cpReq[9:6] == 4'h9 && - cpReq[37] && - NOT_cpReq_337_BIT_36_898_906_AND_NOT_wci_busy__ETC___d3667 ; + (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && + cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_AND_cpReq_ETC___d3009 ; - // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_F - assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h75857 == 4'd12 && + // rule RL_cpDispatch_F_F_T_E12_F_F_T_F_F + assign WILL_FIRE_RL_cpDispatch_F_F_T_E12_F_F_T_F_F = + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd12 && cpReq[61:60] != 2'd2 && - cpReq[9:6] == 4'h9 && - !cpReq[37] && - NOT_cpReq_337_BIT_36_898_906_AND_NOT_wci_busy__ETC___d3667 ; + (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && + cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_AND_NOT_c_ETC___d3022 ; - // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T - assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h75857 == 4'd12 && + // rule RL_cpDispatch_F_F_T_E12_T_T + assign WILL_FIRE_RL_cpDispatch_F_F_T_E12_T_T = + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd12 && cpReq[61:60] == 2'd2 && - wci_wReset_n_12_870_AND_NOT_wci_busy_12_890_63_ETC___d3639 ; + wci_12_wReset_n && + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3445 && + !dispatched ; - // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_T - assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h75857 == 4'd12 && + // rule RL_cpDispatch_F_F_T_E12_F_F_T_T_T + assign WILL_FIRE_RL_cpDispatch_F_F_T_E12_F_F_T_T_T = + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd12 && cpReq[61:60] != 2'd2 && - cpReq[9:6] == 4'h9 && - cpReq[37] && - cpReq_337_BIT_36_898_AND_NOT_wci_busy_12_890_6_ETC___d3660 ; + (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && + cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_AND_cpReq_ETC___d3001 ; - // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_T - assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h75857 == 4'd12 && + // rule RL_cpDispatch_F_F_T_E12_F_F_T_F_T + assign WILL_FIRE_RL_cpDispatch_F_F_T_E12_F_F_T_F_T = + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd12 && cpReq[61:60] != 2'd2 && - cpReq[9:6] == 4'h9 && - !cpReq[37] && - cpReq_337_BIT_36_898_AND_NOT_wci_busy_12_890_6_ETC___d3660 ; + (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && + cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_AND_NOT_c_ETC___d3016 ; - // rule RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T - assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T = - cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && - cpReq[64:62] != 3'd3 && - cpReq[64:62] != 3'd0 && - _theResult_____1__h75875 == 4'd12 && - cpReq[37:36] == 2'd2 && - wci_wReset_n_12_870_AND_NOT_wci_busy_12_890_63_ETC___d3639 ; + // rule RL_cpDispatch_F_F_F_F_E12_T_T + assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_T_T = + cpReq[64:62] != 3'd1 && + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4685 ; - // rule RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T - assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T = - cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && - cpReq[64:62] != 3'd3 && - cpReq[64:62] != 3'd0 && - _theResult_____1__h75875 == 4'd12 && - cpReq[37:36] == 2'd1 && - cpReq[19:9] == 11'd0 && - wci_wReset_n_12_870_AND_NOT_wci_busy_12_890_63_ETC___d3639 ; + // rule RL_cpDispatch_F_F_F_F_E12_F_T_T + assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_F_T_T = + cpReq[64:62] != 3'd1 && + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4708 ; - // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_F - assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h75857 == 4'd13 && + // rule RL_cpDispatch_F_F_T_E13_F_F_T_T_F + assign WILL_FIRE_RL_cpDispatch_F_F_T_E13_F_F_T_T_F = + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd13 && cpReq[61:60] != 2'd2 && - cpReq[9:6] == 4'h9 && - cpReq[37] && - NOT_cpReq_337_BIT_36_898_906_AND_NOT_wci_busy__ETC___d3730 ; + (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && + cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_AND_cpReq_ETC___d3009 ; - // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_F - assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h75857 == 4'd13 && + // rule RL_cpDispatch_F_F_T_E13_F_F_T_F_F + assign WILL_FIRE_RL_cpDispatch_F_F_T_E13_F_F_T_F_F = + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd13 && cpReq[61:60] != 2'd2 && - cpReq[9:6] == 4'h9 && - !cpReq[37] && - NOT_cpReq_337_BIT_36_898_906_AND_NOT_wci_busy__ETC___d3730 ; + (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && + cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_AND_NOT_c_ETC___d3022 ; - // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T - assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h75857 == 4'd13 && + // rule RL_cpDispatch_F_F_T_E13_T_T + assign WILL_FIRE_RL_cpDispatch_F_F_T_E13_T_T = + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd13 && cpReq[61:60] == 2'd2 && - wci_wReset_n_13_010_AND_NOT_wci_busy_13_030_69_ETC___d3702 ; + wci_13_wReset_n && + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3481 && + !dispatched ; - // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_T - assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h75857 == 4'd13 && + // rule RL_cpDispatch_F_F_T_E13_F_F_T_T_T + assign WILL_FIRE_RL_cpDispatch_F_F_T_E13_F_F_T_T_T = + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd13 && cpReq[61:60] != 2'd2 && - cpReq[9:6] == 4'h9 && - cpReq[37] && - cpReq_337_BIT_36_898_AND_NOT_wci_busy_13_030_6_ETC___d3723 ; + (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && + cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_AND_cpReq_ETC___d3001 ; - // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_T - assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h75857 == 4'd13 && + // rule RL_cpDispatch_F_F_T_E13_F_F_T_F_T + assign WILL_FIRE_RL_cpDispatch_F_F_T_E13_F_F_T_F_T = + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd13 && cpReq[61:60] != 2'd2 && - cpReq[9:6] == 4'h9 && - !cpReq[37] && - cpReq_337_BIT_36_898_AND_NOT_wci_busy_13_030_6_ETC___d3723 ; + (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && + cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_AND_NOT_c_ETC___d3016 ; - // rule RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T - assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T = - cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && - cpReq[64:62] != 3'd3 && - cpReq[64:62] != 3'd0 && - _theResult_____1__h75875 == 4'd13 && - cpReq[37:36] == 2'd2 && - wci_wReset_n_13_010_AND_NOT_wci_busy_13_030_69_ETC___d3702 ; + // rule RL_cpDispatch_F_F_F_F_E13_T_T + assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_T_T = + cpReq[64:62] != 3'd1 && + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4760 ; - // rule RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T - assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T = - cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && - cpReq[64:62] != 3'd3 && - cpReq[64:62] != 3'd0 && - _theResult_____1__h75875 == 4'd13 && - cpReq[37:36] == 2'd1 && - cpReq[19:9] == 11'd0 && - wci_wReset_n_13_010_AND_NOT_wci_busy_13_030_69_ETC___d3702 ; + // rule RL_cpDispatch_F_F_F_F_E13_F_T_T + assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_F_T_T = + cpReq[64:62] != 3'd1 && + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4783 ; - // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_F - assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h75857 == 4'd14 && + // rule RL_cpDispatch_F_F_T_E14_F_F_T_T_F + assign WILL_FIRE_RL_cpDispatch_F_F_T_E14_F_F_T_T_F = + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd14 && cpReq[61:60] != 2'd2 && - cpReq[9:6] == 4'h9 && - cpReq[37] && - NOT_cpReq_337_BIT_36_898_906_AND_NOT_wci_busy__ETC___d3793 ; + (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && + cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_AND_cpReq_ETC___d3009 ; - // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_F - assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_F = - cpReq[64:62] == 3'd3 && _theResult_____1__h75857 == 4'd14 && + // rule RL_cpDispatch_F_F_T_E14_F_F_T_F_F + assign WILL_FIRE_RL_cpDispatch_F_F_T_E14_F_F_T_F_F = + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd14 && cpReq[61:60] != 2'd2 && - cpReq[9:6] == 4'h9 && - !cpReq[37] && - NOT_cpReq_337_BIT_36_898_906_AND_NOT_wci_busy__ETC___d3793 ; + (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && + cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_AND_NOT_c_ETC___d3022 ; - // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T - assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h75857 == 4'd14 && + // rule RL_cpDispatch_F_F_T_E14_T_T + assign WILL_FIRE_RL_cpDispatch_F_F_T_E14_T_T = + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd14 && cpReq[61:60] == 2'd2 && - wci_wReset_n_14_150_AND_NOT_wci_busy_14_170_76_ETC___d3765 ; + wci_14_wReset_n && + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3517 && + !dispatched ; - // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_T - assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h75857 == 4'd14 && + // rule RL_cpDispatch_F_F_T_E14_F_F_T_T_T + assign WILL_FIRE_RL_cpDispatch_F_F_T_E14_F_F_T_T_T = + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd14 && cpReq[61:60] != 2'd2 && - cpReq[9:6] == 4'h9 && - cpReq[37] && - cpReq_337_BIT_36_898_AND_NOT_wci_busy_14_170_7_ETC___d3786 ; + (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && + cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_AND_cpReq_ETC___d3001 ; - // rule RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_T - assign WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_T = - cpReq[64:62] == 3'd3 && _theResult_____1__h75857 == 4'd14 && + // rule RL_cpDispatch_F_F_T_E14_F_F_T_F_T + assign WILL_FIRE_RL_cpDispatch_F_F_T_E14_F_F_T_F_T = + cpReq[64:62] == 3'd3 && _theResult_____1__h75724 == 4'd14 && cpReq[61:60] != 2'd2 && - cpReq[9:6] == 4'h9 && - !cpReq[37] && - cpReq_337_BIT_36_898_AND_NOT_wci_busy_14_170_7_ETC___d3786 ; + (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && + cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_AND_NOT_c_ETC___d3016 ; - // rule RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T - assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T = - cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && - cpReq[64:62] != 3'd3 && - cpReq[64:62] != 3'd0 && - _theResult_____1__h75875 == 4'd14 && - cpReq[37:36] == 2'd2 && - wci_wReset_n_14_150_AND_NOT_wci_busy_14_170_76_ETC___d3765 ; + // rule RL_cpDispatch_F_F_F_F_E14_T_T + assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_T_T = + cpReq[64:62] != 3'd1 && + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4835 ; - // rule RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T - assign WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T = - cpReq[64:62] != 3'd1 && cpReq[64:62] != 3'd2 && - cpReq[64:62] != 3'd3 && - cpReq[64:62] != 3'd0 && - _theResult_____1__h75875 == 4'd14 && - cpReq[37:36] == 2'd1 && - cpReq[19:9] == 11'd0 && - wci_wReset_n_14_150_AND_NOT_wci_busy_14_170_76_ETC___d3765 ; + // rule RL_cpDispatch_F_F_F_F_E14_F_T_T + assign WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_F_T_T = + cpReq[64:62] != 3'd1 && + NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4858 ; // rule RL_responseAdminRd assign WILL_FIRE_RL_responseAdminRd = adminRespF$EMPTY_N && cpRespF$FULL_N ; - // rule RL_wci_wrkBusy - assign WILL_FIRE_RL_wci_wrkBusy = - ((wci_wciResponse$wget[33:32] == 2'd0) ? - wci_respTimr_02_ULT_1_SL_wci_wTimeout_03_04___d5829 || - wci_respF$FULL_N : - wci_respF$FULL_N) && - wci_busy ; - - // rule RL_wci_reqF_incCtr - assign WILL_FIRE_RL_wci_reqF_incCtr = - (wci_reqF_c_r || wci_reqF_x_wire$whas) && - MUX_wci_busy$write_1__SEL_2 && - !wci_reqF_dequeueing$whas ; - - // rule RL_wci_reqF_decCtr - assign WILL_FIRE_RL_wci_reqF_decCtr = - wci_reqF_dequeueing$whas && !MUX_wci_busy$write_1__SEL_2 ; - - // rule RL_wci_reqF_both - assign WILL_FIRE_RL_wci_reqF_both = - (!wci_reqF_c_r || wci_reqF_x_wire$whas) && - wci_reqF_dequeueing$whas && - MUX_wci_busy$write_1__SEL_2 ; - - // rule RL_wci_wrkBusy_1 - assign WILL_FIRE_RL_wci_wrkBusy_1 = - ((wci_wciResponse_1$wget[33:32] == 2'd0) ? - wci_respTimr_1_42_ULT_1_SL_wci_wTimeout_1_43_44___d5830 || - wci_respF_1$FULL_N : - wci_respF_1$FULL_N) && - wci_busy_1 ; - - // rule RL_wci_reqF_1_incCtr - assign WILL_FIRE_RL_wci_reqF_1_incCtr = - (wci_reqF_1_c_r || wci_reqF_1_x_wire$whas) && - MUX_wci_busy_1$write_1__SEL_2 && - !wci_reqF_1_dequeueing$whas ; - - // rule RL_wci_reqF_1_decCtr - assign WILL_FIRE_RL_wci_reqF_1_decCtr = - wci_reqF_1_dequeueing$whas && !MUX_wci_busy_1$write_1__SEL_2 ; - - // rule RL_wci_reqF_1_both - assign WILL_FIRE_RL_wci_reqF_1_both = - (!wci_reqF_1_c_r || wci_reqF_1_x_wire$whas) && - wci_reqF_1_dequeueing$whas && - MUX_wci_busy_1$write_1__SEL_2 ; - - // rule RL_wci_wrkBusy_2 - assign WILL_FIRE_RL_wci_wrkBusy_2 = - ((wci_wciResponse_2$wget[33:32] == 2'd0) ? - wci_respTimr_2_82_ULT_1_SL_wci_wTimeout_2_83_84___d5831 || - wci_respF_2$FULL_N : - wci_respF_2$FULL_N) && - wci_busy_2 ; - - // rule RL_wci_reqF_2_incCtr - assign WILL_FIRE_RL_wci_reqF_2_incCtr = - (wci_reqF_2_c_r || wci_reqF_2_x_wire$whas) && - MUX_wci_busy_2$write_1__SEL_2 && - !wci_reqF_2_dequeueing$whas ; - - // rule RL_wci_reqF_2_decCtr - assign WILL_FIRE_RL_wci_reqF_2_decCtr = - wci_reqF_2_dequeueing$whas && !MUX_wci_busy_2$write_1__SEL_2 ; - - // rule RL_wci_reqF_2_both - assign WILL_FIRE_RL_wci_reqF_2_both = - (!wci_reqF_2_c_r || wci_reqF_2_x_wire$whas) && - wci_reqF_2_dequeueing$whas && - MUX_wci_busy_2$write_1__SEL_2 ; - - // rule RL_wci_wrkBusy_3 - assign WILL_FIRE_RL_wci_wrkBusy_3 = - ((wci_wciResponse_3$wget[33:32] == 2'd0) ? - wci_respTimr_3_22_ULT_1_SL_wci_wTimeout_3_23_24___d5832 || - wci_respF_3$FULL_N : - wci_respF_3$FULL_N) && - wci_busy_3 ; - - // rule RL_wci_reqF_3_incCtr - assign WILL_FIRE_RL_wci_reqF_3_incCtr = - (wci_reqF_3_c_r || wci_reqF_3_x_wire$whas) && - MUX_wci_busy_3$write_1__SEL_2 && - !wci_reqF_3_dequeueing$whas ; - - // rule RL_wci_reqF_3_decCtr - assign WILL_FIRE_RL_wci_reqF_3_decCtr = - wci_reqF_3_dequeueing$whas && !MUX_wci_busy_3$write_1__SEL_2 ; - - // rule RL_wci_reqF_3_both - assign WILL_FIRE_RL_wci_reqF_3_both = - (!wci_reqF_3_c_r || wci_reqF_3_x_wire$whas) && - wci_reqF_3_dequeueing$whas && - MUX_wci_busy_3$write_1__SEL_2 ; - - // rule RL_wci_wrkBusy_4 - assign WILL_FIRE_RL_wci_wrkBusy_4 = - ((wci_wciResponse_4$wget[33:32] == 2'd0) ? - wci_respTimr_4_62_ULT_1_SL_wci_wTimeout_4_63_64___d5833 || - wci_respF_4$FULL_N : - wci_respF_4$FULL_N) && - wci_busy_4 ; - - // rule RL_wci_reqF_4_incCtr - assign WILL_FIRE_RL_wci_reqF_4_incCtr = - (wci_reqF_4_c_r || wci_reqF_4_x_wire$whas) && - MUX_wci_busy_4$write_1__SEL_2 && - !wci_reqF_4_dequeueing$whas ; - - // rule RL_wci_reqF_4_decCtr - assign WILL_FIRE_RL_wci_reqF_4_decCtr = - wci_reqF_4_dequeueing$whas && !MUX_wci_busy_4$write_1__SEL_2 ; - - // rule RL_wci_reqF_4_both - assign WILL_FIRE_RL_wci_reqF_4_both = - (!wci_reqF_4_c_r || wci_reqF_4_x_wire$whas) && - wci_reqF_4_dequeueing$whas && - MUX_wci_busy_4$write_1__SEL_2 ; - - // rule RL_wci_wrkBusy_5 - assign WILL_FIRE_RL_wci_wrkBusy_5 = - ((wci_wciResponse_5$wget[33:32] == 2'd0) ? - wci_respTimr_5_02_ULT_1_SL_wci_wTimeout_5_03_04___d5834 || - wci_respF_5$FULL_N : - wci_respF_5$FULL_N) && - wci_busy_5 ; - - // rule RL_wci_reqF_5_incCtr - assign WILL_FIRE_RL_wci_reqF_5_incCtr = - (wci_reqF_5_c_r || wci_reqF_5_x_wire$whas) && - MUX_wci_busy_5$write_1__SEL_2 && - !wci_reqF_5_dequeueing$whas ; - - // rule RL_wci_reqF_5_decCtr - assign WILL_FIRE_RL_wci_reqF_5_decCtr = - wci_reqF_5_dequeueing$whas && !MUX_wci_busy_5$write_1__SEL_2 ; - - // rule RL_wci_reqF_5_both - assign WILL_FIRE_RL_wci_reqF_5_both = - (!wci_reqF_5_c_r || wci_reqF_5_x_wire$whas) && - wci_reqF_5_dequeueing$whas && - MUX_wci_busy_5$write_1__SEL_2 ; - - // rule RL_wci_wrkBusy_6 - assign WILL_FIRE_RL_wci_wrkBusy_6 = - ((wci_wciResponse_6$wget[33:32] == 2'd0) ? - wci_respTimr_6_042_ULT_1_SL_wci_wTimeout_6_043_ETC___d5835 || - wci_respF_6$FULL_N : - wci_respF_6$FULL_N) && - wci_busy_6 ; - - // rule RL_wci_reqF_6_incCtr - assign WILL_FIRE_RL_wci_reqF_6_incCtr = - (wci_reqF_6_c_r || wci_reqF_6_x_wire$whas) && - MUX_wci_busy_6$write_1__SEL_2 && - !wci_reqF_6_dequeueing$whas ; - - // rule RL_wci_reqF_6_decCtr - assign WILL_FIRE_RL_wci_reqF_6_decCtr = - wci_reqF_6_dequeueing$whas && !MUX_wci_busy_6$write_1__SEL_2 ; - - // rule RL_wci_reqF_6_both - assign WILL_FIRE_RL_wci_reqF_6_both = - (!wci_reqF_6_c_r || wci_reqF_6_x_wire$whas) && - wci_reqF_6_dequeueing$whas && - MUX_wci_busy_6$write_1__SEL_2 ; - - // rule RL_wci_wrkBusy_7 - assign WILL_FIRE_RL_wci_wrkBusy_7 = - ((wci_wciResponse_7$wget[33:32] == 2'd0) ? - wci_respTimr_7_182_ULT_1_SL_wci_wTimeout_7_183_ETC___d5836 || - wci_respF_7$FULL_N : - wci_respF_7$FULL_N) && - wci_busy_7 ; - - // rule RL_wci_reqF_7_incCtr - assign WILL_FIRE_RL_wci_reqF_7_incCtr = - (wci_reqF_7_c_r || wci_reqF_7_x_wire$whas) && - MUX_wci_busy_7$write_1__SEL_2 && - !wci_reqF_7_dequeueing$whas ; - - // rule RL_wci_reqF_7_decCtr - assign WILL_FIRE_RL_wci_reqF_7_decCtr = - wci_reqF_7_dequeueing$whas && !MUX_wci_busy_7$write_1__SEL_2 ; - - // rule RL_wci_reqF_7_both - assign WILL_FIRE_RL_wci_reqF_7_both = - (!wci_reqF_7_c_r || wci_reqF_7_x_wire$whas) && - wci_reqF_7_dequeueing$whas && - MUX_wci_busy_7$write_1__SEL_2 ; - - // rule RL_wci_wrkBusy_8 - assign WILL_FIRE_RL_wci_wrkBusy_8 = - ((wci_wciResponse_8$wget[33:32] == 2'd0) ? - wci_respTimr_8_322_ULT_1_SL_wci_wTimeout_8_323_ETC___d5837 || - wci_respF_8$FULL_N : - wci_respF_8$FULL_N) && - wci_busy_8 ; - - // rule RL_wci_reqF_8_incCtr - assign WILL_FIRE_RL_wci_reqF_8_incCtr = - (wci_reqF_8_c_r || wci_reqF_8_x_wire$whas) && - MUX_wci_busy_8$write_1__SEL_2 && - !wci_reqF_8_dequeueing$whas ; - - // rule RL_wci_reqF_8_decCtr - assign WILL_FIRE_RL_wci_reqF_8_decCtr = - wci_reqF_8_dequeueing$whas && !MUX_wci_busy_8$write_1__SEL_2 ; - - // rule RL_wci_reqF_8_both - assign WILL_FIRE_RL_wci_reqF_8_both = - (!wci_reqF_8_c_r || wci_reqF_8_x_wire$whas) && - wci_reqF_8_dequeueing$whas && - MUX_wci_busy_8$write_1__SEL_2 ; - - // rule RL_wci_wrkBusy_9 - assign WILL_FIRE_RL_wci_wrkBusy_9 = - ((wci_wciResponse_9$wget[33:32] == 2'd0) ? - wci_respTimr_9_462_ULT_1_SL_wci_wTimeout_9_463_ETC___d5838 || - wci_respF_9$FULL_N : - wci_respF_9$FULL_N) && - wci_busy_9 ; - - // rule RL_wci_reqF_9_incCtr - assign WILL_FIRE_RL_wci_reqF_9_incCtr = - (wci_reqF_9_c_r || wci_reqF_9_x_wire$whas) && - MUX_wci_busy_9$write_1__SEL_2 && - !wci_reqF_9_dequeueing$whas ; - - // rule RL_wci_reqF_9_decCtr - assign WILL_FIRE_RL_wci_reqF_9_decCtr = - wci_reqF_9_dequeueing$whas && !MUX_wci_busy_9$write_1__SEL_2 ; - - // rule RL_wci_reqF_9_both - assign WILL_FIRE_RL_wci_reqF_9_both = - (!wci_reqF_9_c_r || wci_reqF_9_x_wire$whas) && - wci_reqF_9_dequeueing$whas && - MUX_wci_busy_9$write_1__SEL_2 ; - - // rule RL_wci_wrkBusy_10 - assign WILL_FIRE_RL_wci_wrkBusy_10 = - ((wci_wciResponse_10$wget[33:32] == 2'd0) ? - wci_respTimr_10_602_ULT_1_SL_wci_wTimeout_10_6_ETC___d5839 || - wci_respF_10$FULL_N : - wci_respF_10$FULL_N) && - wci_busy_10 ; - - // rule RL_wci_reqF_10_incCtr - assign WILL_FIRE_RL_wci_reqF_10_incCtr = - (wci_reqF_10_c_r || wci_reqF_10_x_wire$whas) && - MUX_wci_busy_10$write_1__SEL_2 && - !wci_reqF_10_dequeueing$whas ; - - // rule RL_wci_reqF_10_decCtr - assign WILL_FIRE_RL_wci_reqF_10_decCtr = - wci_reqF_10_dequeueing$whas && !MUX_wci_busy_10$write_1__SEL_2 ; - - // rule RL_wci_reqF_10_both - assign WILL_FIRE_RL_wci_reqF_10_both = - (!wci_reqF_10_c_r || wci_reqF_10_x_wire$whas) && - wci_reqF_10_dequeueing$whas && - MUX_wci_busy_10$write_1__SEL_2 ; - - // rule RL_wci_wrkBusy_11 - assign WILL_FIRE_RL_wci_wrkBusy_11 = - ((wci_wciResponse_11$wget[33:32] == 2'd0) ? - wci_respTimr_11_742_ULT_1_SL_wci_wTimeout_11_7_ETC___d5840 || - wci_respF_11$FULL_N : - wci_respF_11$FULL_N) && - wci_busy_11 ; - - // rule RL_wci_reqF_11_incCtr - assign WILL_FIRE_RL_wci_reqF_11_incCtr = - (wci_reqF_11_c_r || wci_reqF_11_x_wire$whas) && - MUX_wci_busy_11$write_1__SEL_2 && - !wci_reqF_11_dequeueing$whas ; - - // rule RL_wci_reqF_11_decCtr - assign WILL_FIRE_RL_wci_reqF_11_decCtr = - wci_reqF_11_dequeueing$whas && !MUX_wci_busy_11$write_1__SEL_2 ; - - // rule RL_wci_reqF_11_both - assign WILL_FIRE_RL_wci_reqF_11_both = - (!wci_reqF_11_c_r || wci_reqF_11_x_wire$whas) && - wci_reqF_11_dequeueing$whas && - MUX_wci_busy_11$write_1__SEL_2 ; - - // rule RL_wci_wrkBusy_12 - assign WILL_FIRE_RL_wci_wrkBusy_12 = - ((wci_wciResponse_12$wget[33:32] == 2'd0) ? - wci_respTimr_12_882_ULT_1_SL_wci_wTimeout_12_8_ETC___d5841 || - wci_respF_12$FULL_N : - wci_respF_12$FULL_N) && - wci_busy_12 ; - - // rule RL_wci_reqF_12_incCtr - assign WILL_FIRE_RL_wci_reqF_12_incCtr = - (wci_reqF_12_c_r || wci_reqF_12_x_wire$whas) && - MUX_wci_busy_12$write_1__SEL_2 && - !wci_reqF_12_dequeueing$whas ; - - // rule RL_wci_reqF_12_decCtr - assign WILL_FIRE_RL_wci_reqF_12_decCtr = - wci_reqF_12_dequeueing$whas && !MUX_wci_busy_12$write_1__SEL_2 ; - - // rule RL_wci_reqF_12_both - assign WILL_FIRE_RL_wci_reqF_12_both = - (!wci_reqF_12_c_r || wci_reqF_12_x_wire$whas) && - wci_reqF_12_dequeueing$whas && - MUX_wci_busy_12$write_1__SEL_2 ; - - // rule RL_wci_wrkBusy_13 - assign WILL_FIRE_RL_wci_wrkBusy_13 = - ((wci_wciResponse_13$wget[33:32] == 2'd0) ? - wci_respTimr_13_022_ULT_1_SL_wci_wTimeout_13_0_ETC___d5842 || - wci_respF_13$FULL_N : - wci_respF_13$FULL_N) && - wci_busy_13 ; - - // rule RL_wci_reqF_13_incCtr - assign WILL_FIRE_RL_wci_reqF_13_incCtr = - (wci_reqF_13_c_r || wci_reqF_13_x_wire$whas) && - MUX_wci_busy_13$write_1__SEL_2 && - !wci_reqF_13_dequeueing$whas ; - - // rule RL_wci_reqF_13_decCtr - assign WILL_FIRE_RL_wci_reqF_13_decCtr = - wci_reqF_13_dequeueing$whas && !MUX_wci_busy_13$write_1__SEL_2 ; - - // rule RL_wci_reqF_13_both - assign WILL_FIRE_RL_wci_reqF_13_both = - (!wci_reqF_13_c_r || wci_reqF_13_x_wire$whas) && - wci_reqF_13_dequeueing$whas && - MUX_wci_busy_13$write_1__SEL_2 ; - - // rule RL_wci_wrkBusy_14 - assign WILL_FIRE_RL_wci_wrkBusy_14 = - ((wci_wciResponse_14$wget[33:32] == 2'd0) ? - wci_respTimr_14_162_ULT_1_SL_wci_wTimeout_14_1_ETC___d5843 || - wci_respF_14$FULL_N : - wci_respF_14$FULL_N) && - wci_busy_14 ; - - // rule RL_wci_reqF_14_incCtr - assign WILL_FIRE_RL_wci_reqF_14_incCtr = - (wci_reqF_14_c_r || wci_reqF_14_x_wire$whas) && - MUX_wci_busy_14$write_1__SEL_2 && - !wci_reqF_14_dequeueing$whas ; - - // rule RL_wci_reqF_14_decCtr - assign WILL_FIRE_RL_wci_reqF_14_decCtr = - wci_reqF_14_dequeueing$whas && !MUX_wci_busy_14$write_1__SEL_2 ; - - // rule RL_wci_reqF_14_both - assign WILL_FIRE_RL_wci_reqF_14_both = - (!wci_reqF_14_c_r || wci_reqF_14_x_wire$whas) && - wci_reqF_14_dequeueing$whas && - MUX_wci_busy_14$write_1__SEL_2 ; + // rule RL_wci_0_wrkBusy + assign WILL_FIRE_RL_wci_0_wrkBusy = + ((wci_0_wciResponse$wget[33:32] == 2'd0) ? + wci_0_respTimr_28_ULT_1_SL_wci_0_wTimeout_29_30___d231 || + wci_0_respF$FULL_N : + wci_0_respF$FULL_N) && + wci_0_busy ; + + // rule RL_wci_0_reqF_incCtr + assign WILL_FIRE_RL_wci_0_reqF_incCtr = + (wci_0_reqF_cntr_r || wci_0_reqF_x_wire$whas) && + MUX_wci_0_busy$write_1__SEL_2 && + !wci_0_reqF_dequeueing$whas ; + + // rule RL_wci_0_reqF_decCtr + assign WILL_FIRE_RL_wci_0_reqF_decCtr = + wci_0_reqF_dequeueing$whas && !MUX_wci_0_busy$write_1__SEL_2 ; + + // rule RL_wci_0_reqF_both + assign WILL_FIRE_RL_wci_0_reqF_both = + (!wci_0_reqF_cntr_r || wci_0_reqF_x_wire$whas) && + wci_0_reqF_dequeueing$whas && + MUX_wci_0_busy$write_1__SEL_2 ; + + // rule RL_wci_1_wrkBusy + assign WILL_FIRE_RL_wci_1_wrkBusy = + ((wci_1_wciResponse$wget[33:32] == 2'd0) ? + wci_1_respTimr_68_ULT_1_SL_wci_1_wTimeout_69_70___d371 || + wci_1_respF$FULL_N : + wci_1_respF$FULL_N) && + wci_1_busy ; + + // rule RL_wci_1_reqF_incCtr + assign WILL_FIRE_RL_wci_1_reqF_incCtr = + (wci_1_reqF_cntr_r || wci_1_reqF_x_wire$whas) && + MUX_wci_1_busy$write_1__SEL_2 && + !wci_1_reqF_dequeueing$whas ; + + // rule RL_wci_1_reqF_decCtr + assign WILL_FIRE_RL_wci_1_reqF_decCtr = + wci_1_reqF_dequeueing$whas && !MUX_wci_1_busy$write_1__SEL_2 ; + + // rule RL_wci_1_reqF_both + assign WILL_FIRE_RL_wci_1_reqF_both = + (!wci_1_reqF_cntr_r || wci_1_reqF_x_wire$whas) && + wci_1_reqF_dequeueing$whas && + MUX_wci_1_busy$write_1__SEL_2 ; + + // rule RL_wci_2_wrkBusy + assign WILL_FIRE_RL_wci_2_wrkBusy = + ((wci_2_wciResponse$wget[33:32] == 2'd0) ? + wci_2_respTimr_08_ULT_1_SL_wci_2_wTimeout_09_10___d511 || + wci_2_respF$FULL_N : + wci_2_respF$FULL_N) && + wci_2_busy ; + + // rule RL_wci_2_reqF_incCtr + assign WILL_FIRE_RL_wci_2_reqF_incCtr = + (wci_2_reqF_cntr_r || wci_2_reqF_x_wire$whas) && + MUX_wci_2_busy$write_1__SEL_2 && + !wci_2_reqF_dequeueing$whas ; + + // rule RL_wci_2_reqF_decCtr + assign WILL_FIRE_RL_wci_2_reqF_decCtr = + wci_2_reqF_dequeueing$whas && !MUX_wci_2_busy$write_1__SEL_2 ; + + // rule RL_wci_2_reqF_both + assign WILL_FIRE_RL_wci_2_reqF_both = + (!wci_2_reqF_cntr_r || wci_2_reqF_x_wire$whas) && + wci_2_reqF_dequeueing$whas && + MUX_wci_2_busy$write_1__SEL_2 ; + + // rule RL_wci_3_wrkBusy + assign WILL_FIRE_RL_wci_3_wrkBusy = + ((wci_3_wciResponse$wget[33:32] == 2'd0) ? + wci_3_respTimr_48_ULT_1_SL_wci_3_wTimeout_49_50___d651 || + wci_3_respF$FULL_N : + wci_3_respF$FULL_N) && + wci_3_busy ; + + // rule RL_wci_3_reqF_incCtr + assign WILL_FIRE_RL_wci_3_reqF_incCtr = + (wci_3_reqF_cntr_r || wci_3_reqF_x_wire$whas) && + MUX_wci_3_busy$write_1__SEL_2 && + !wci_3_reqF_dequeueing$whas ; + + // rule RL_wci_3_reqF_decCtr + assign WILL_FIRE_RL_wci_3_reqF_decCtr = + wci_3_reqF_dequeueing$whas && !MUX_wci_3_busy$write_1__SEL_2 ; + + // rule RL_wci_3_reqF_both + assign WILL_FIRE_RL_wci_3_reqF_both = + (!wci_3_reqF_cntr_r || wci_3_reqF_x_wire$whas) && + wci_3_reqF_dequeueing$whas && + MUX_wci_3_busy$write_1__SEL_2 ; + + // rule RL_wci_4_wrkBusy + assign WILL_FIRE_RL_wci_4_wrkBusy = + ((wci_4_wciResponse$wget[33:32] == 2'd0) ? + wci_4_respTimr_88_ULT_1_SL_wci_4_wTimeout_89_90___d791 || + wci_4_respF$FULL_N : + wci_4_respF$FULL_N) && + wci_4_busy ; + + // rule RL_wci_4_reqF_incCtr + assign WILL_FIRE_RL_wci_4_reqF_incCtr = + (wci_4_reqF_cntr_r || wci_4_reqF_x_wire$whas) && + MUX_wci_4_busy$write_1__SEL_2 && + !wci_4_reqF_dequeueing$whas ; + + // rule RL_wci_4_reqF_decCtr + assign WILL_FIRE_RL_wci_4_reqF_decCtr = + wci_4_reqF_dequeueing$whas && !MUX_wci_4_busy$write_1__SEL_2 ; + + // rule RL_wci_4_reqF_both + assign WILL_FIRE_RL_wci_4_reqF_both = + (!wci_4_reqF_cntr_r || wci_4_reqF_x_wire$whas) && + wci_4_reqF_dequeueing$whas && + MUX_wci_4_busy$write_1__SEL_2 ; + + // rule RL_wci_5_wrkBusy + assign WILL_FIRE_RL_wci_5_wrkBusy = + ((wci_5_wciResponse$wget[33:32] == 2'd0) ? + wci_5_respTimr_28_ULT_1_SL_wci_5_wTimeout_29_30___d931 || + wci_5_respF$FULL_N : + wci_5_respF$FULL_N) && + wci_5_busy ; + + // rule RL_wci_5_reqF_incCtr + assign WILL_FIRE_RL_wci_5_reqF_incCtr = + (wci_5_reqF_cntr_r || wci_5_reqF_x_wire$whas) && + MUX_wci_5_busy$write_1__SEL_2 && + !wci_5_reqF_dequeueing$whas ; + + // rule RL_wci_5_reqF_decCtr + assign WILL_FIRE_RL_wci_5_reqF_decCtr = + wci_5_reqF_dequeueing$whas && !MUX_wci_5_busy$write_1__SEL_2 ; + + // rule RL_wci_5_reqF_both + assign WILL_FIRE_RL_wci_5_reqF_both = + (!wci_5_reqF_cntr_r || wci_5_reqF_x_wire$whas) && + wci_5_reqF_dequeueing$whas && + MUX_wci_5_busy$write_1__SEL_2 ; + + // rule RL_wci_6_wrkBusy + assign WILL_FIRE_RL_wci_6_wrkBusy = + ((wci_6_wciResponse$wget[33:32] == 2'd0) ? + wci_6_respTimr_068_ULT_1_SL_wci_6_wTimeout_069_ETC___d1071 || + wci_6_respF$FULL_N : + wci_6_respF$FULL_N) && + wci_6_busy ; + + // rule RL_wci_6_reqF_incCtr + assign WILL_FIRE_RL_wci_6_reqF_incCtr = + (wci_6_reqF_cntr_r || wci_6_reqF_x_wire$whas) && + MUX_wci_6_busy$write_1__SEL_2 && + !wci_6_reqF_dequeueing$whas ; + + // rule RL_wci_6_reqF_decCtr + assign WILL_FIRE_RL_wci_6_reqF_decCtr = + wci_6_reqF_dequeueing$whas && !MUX_wci_6_busy$write_1__SEL_2 ; + + // rule RL_wci_6_reqF_both + assign WILL_FIRE_RL_wci_6_reqF_both = + (!wci_6_reqF_cntr_r || wci_6_reqF_x_wire$whas) && + wci_6_reqF_dequeueing$whas && + MUX_wci_6_busy$write_1__SEL_2 ; + + // rule RL_wci_7_wrkBusy + assign WILL_FIRE_RL_wci_7_wrkBusy = + ((wci_7_wciResponse$wget[33:32] == 2'd0) ? + wci_7_respTimr_208_ULT_1_SL_wci_7_wTimeout_209_ETC___d1211 || + wci_7_respF$FULL_N : + wci_7_respF$FULL_N) && + wci_7_busy ; + + // rule RL_wci_7_reqF_incCtr + assign WILL_FIRE_RL_wci_7_reqF_incCtr = + (wci_7_reqF_cntr_r || wci_7_reqF_x_wire$whas) && + MUX_wci_7_busy$write_1__SEL_2 && + !wci_7_reqF_dequeueing$whas ; + + // rule RL_wci_7_reqF_decCtr + assign WILL_FIRE_RL_wci_7_reqF_decCtr = + wci_7_reqF_dequeueing$whas && !MUX_wci_7_busy$write_1__SEL_2 ; + + // rule RL_wci_7_reqF_both + assign WILL_FIRE_RL_wci_7_reqF_both = + (!wci_7_reqF_cntr_r || wci_7_reqF_x_wire$whas) && + wci_7_reqF_dequeueing$whas && + MUX_wci_7_busy$write_1__SEL_2 ; + + // rule RL_wci_8_wrkBusy + assign WILL_FIRE_RL_wci_8_wrkBusy = + ((wci_8_wciResponse$wget[33:32] == 2'd0) ? + wci_8_respTimr_348_ULT_1_SL_wci_8_wTimeout_349_ETC___d1351 || + wci_8_respF$FULL_N : + wci_8_respF$FULL_N) && + wci_8_busy ; + + // rule RL_wci_8_reqF_incCtr + assign WILL_FIRE_RL_wci_8_reqF_incCtr = + (wci_8_reqF_cntr_r || wci_8_reqF_x_wire$whas) && + MUX_wci_8_busy$write_1__SEL_2 && + !wci_8_reqF_dequeueing$whas ; + + // rule RL_wci_8_reqF_decCtr + assign WILL_FIRE_RL_wci_8_reqF_decCtr = + wci_8_reqF_dequeueing$whas && !MUX_wci_8_busy$write_1__SEL_2 ; + + // rule RL_wci_8_reqF_both + assign WILL_FIRE_RL_wci_8_reqF_both = + (!wci_8_reqF_cntr_r || wci_8_reqF_x_wire$whas) && + wci_8_reqF_dequeueing$whas && + MUX_wci_8_busy$write_1__SEL_2 ; + + // rule RL_wci_9_wrkBusy + assign WILL_FIRE_RL_wci_9_wrkBusy = + ((wci_9_wciResponse$wget[33:32] == 2'd0) ? + wci_9_respTimr_488_ULT_1_SL_wci_9_wTimeout_489_ETC___d1491 || + wci_9_respF$FULL_N : + wci_9_respF$FULL_N) && + wci_9_busy ; + + // rule RL_wci_9_reqF_incCtr + assign WILL_FIRE_RL_wci_9_reqF_incCtr = + (wci_9_reqF_cntr_r || wci_9_reqF_x_wire$whas) && + MUX_wci_9_busy$write_1__SEL_2 && + !wci_9_reqF_dequeueing$whas ; + + // rule RL_wci_9_reqF_decCtr + assign WILL_FIRE_RL_wci_9_reqF_decCtr = + wci_9_reqF_dequeueing$whas && !MUX_wci_9_busy$write_1__SEL_2 ; + + // rule RL_wci_9_reqF_both + assign WILL_FIRE_RL_wci_9_reqF_both = + (!wci_9_reqF_cntr_r || wci_9_reqF_x_wire$whas) && + wci_9_reqF_dequeueing$whas && + MUX_wci_9_busy$write_1__SEL_2 ; + + // rule RL_wci_10_wrkBusy + assign WILL_FIRE_RL_wci_10_wrkBusy = + ((wci_10_wciResponse$wget[33:32] == 2'd0) ? + wci_10_respTimr_628_ULT_1_SL_wci_10_wTimeout_6_ETC___d1631 || + wci_10_respF$FULL_N : + wci_10_respF$FULL_N) && + wci_10_busy ; + + // rule RL_wci_10_reqF_incCtr + assign WILL_FIRE_RL_wci_10_reqF_incCtr = + (wci_10_reqF_cntr_r || wci_10_reqF_x_wire$whas) && + MUX_wci_10_busy$write_1__SEL_2 && + !wci_10_reqF_dequeueing$whas ; + + // rule RL_wci_10_reqF_decCtr + assign WILL_FIRE_RL_wci_10_reqF_decCtr = + wci_10_reqF_dequeueing$whas && !MUX_wci_10_busy$write_1__SEL_2 ; + + // rule RL_wci_10_reqF_both + assign WILL_FIRE_RL_wci_10_reqF_both = + (!wci_10_reqF_cntr_r || wci_10_reqF_x_wire$whas) && + wci_10_reqF_dequeueing$whas && + MUX_wci_10_busy$write_1__SEL_2 ; + + // rule RL_wci_11_wrkBusy + assign WILL_FIRE_RL_wci_11_wrkBusy = + ((wci_11_wciResponse$wget[33:32] == 2'd0) ? + wci_11_respTimr_768_ULT_1_SL_wci_11_wTimeout_7_ETC___d1771 || + wci_11_respF$FULL_N : + wci_11_respF$FULL_N) && + wci_11_busy ; + + // rule RL_wci_11_reqF_incCtr + assign WILL_FIRE_RL_wci_11_reqF_incCtr = + (wci_11_reqF_cntr_r || wci_11_reqF_x_wire$whas) && + MUX_wci_11_busy$write_1__SEL_2 && + !wci_11_reqF_dequeueing$whas ; + + // rule RL_wci_11_reqF_decCtr + assign WILL_FIRE_RL_wci_11_reqF_decCtr = + wci_11_reqF_dequeueing$whas && !MUX_wci_11_busy$write_1__SEL_2 ; + + // rule RL_wci_11_reqF_both + assign WILL_FIRE_RL_wci_11_reqF_both = + (!wci_11_reqF_cntr_r || wci_11_reqF_x_wire$whas) && + wci_11_reqF_dequeueing$whas && + MUX_wci_11_busy$write_1__SEL_2 ; + + // rule RL_wci_12_wrkBusy + assign WILL_FIRE_RL_wci_12_wrkBusy = + ((wci_12_wciResponse$wget[33:32] == 2'd0) ? + wci_12_respTimr_908_ULT_1_SL_wci_12_wTimeout_9_ETC___d1911 || + wci_12_respF$FULL_N : + wci_12_respF$FULL_N) && + wci_12_busy ; + + // rule RL_wci_12_reqF_incCtr + assign WILL_FIRE_RL_wci_12_reqF_incCtr = + (wci_12_reqF_cntr_r || wci_12_reqF_x_wire$whas) && + MUX_wci_12_busy$write_1__SEL_2 && + !wci_12_reqF_dequeueing$whas ; + + // rule RL_wci_12_reqF_decCtr + assign WILL_FIRE_RL_wci_12_reqF_decCtr = + wci_12_reqF_dequeueing$whas && !MUX_wci_12_busy$write_1__SEL_2 ; + + // rule RL_wci_12_reqF_both + assign WILL_FIRE_RL_wci_12_reqF_both = + (!wci_12_reqF_cntr_r || wci_12_reqF_x_wire$whas) && + wci_12_reqF_dequeueing$whas && + MUX_wci_12_busy$write_1__SEL_2 ; + + // rule RL_wci_13_wrkBusy + assign WILL_FIRE_RL_wci_13_wrkBusy = + ((wci_13_wciResponse$wget[33:32] == 2'd0) ? + wci_13_respTimr_048_ULT_1_SL_wci_13_wTimeout_0_ETC___d2051 || + wci_13_respF$FULL_N : + wci_13_respF$FULL_N) && + wci_13_busy ; + + // rule RL_wci_13_reqF_incCtr + assign WILL_FIRE_RL_wci_13_reqF_incCtr = + (wci_13_reqF_cntr_r || wci_13_reqF_x_wire$whas) && + MUX_wci_13_busy$write_1__SEL_2 && + !wci_13_reqF_dequeueing$whas ; + + // rule RL_wci_13_reqF_decCtr + assign WILL_FIRE_RL_wci_13_reqF_decCtr = + wci_13_reqF_dequeueing$whas && !MUX_wci_13_busy$write_1__SEL_2 ; + + // rule RL_wci_13_reqF_both + assign WILL_FIRE_RL_wci_13_reqF_both = + (!wci_13_reqF_cntr_r || wci_13_reqF_x_wire$whas) && + wci_13_reqF_dequeueing$whas && + MUX_wci_13_busy$write_1__SEL_2 ; + + // rule RL_wci_14_wrkBusy + assign WILL_FIRE_RL_wci_14_wrkBusy = + ((wci_14_wciResponse$wget[33:32] == 2'd0) ? + wci_14_respTimr_188_ULT_1_SL_wci_14_wTimeout_1_ETC___d2191 || + wci_14_respF$FULL_N : + wci_14_respF$FULL_N) && + wci_14_busy ; + + // rule RL_wci_14_reqF_incCtr + assign WILL_FIRE_RL_wci_14_reqF_incCtr = + (wci_14_reqF_cntr_r || wci_14_reqF_x_wire$whas) && + MUX_wci_14_busy$write_1__SEL_2 && + !wci_14_reqF_dequeueing$whas ; + + // rule RL_wci_14_reqF_decCtr + assign WILL_FIRE_RL_wci_14_reqF_decCtr = + wci_14_reqF_dequeueing$whas && !MUX_wci_14_busy$write_1__SEL_2 ; + + // rule RL_wci_14_reqF_both + assign WILL_FIRE_RL_wci_14_reqF_both = + (!wci_14_reqF_cntr_r || wci_14_reqF_x_wire$whas) && + wci_14_reqF_dequeueing$whas && + MUX_wci_14_busy$write_1__SEL_2 ; // inputs to muxes for submodule ports - assign MUX_wci_busy$write_1__SEL_1 = - WILL_FIRE_RL_wci_wrkBusy && - (!wci_respTimr_02_ULT_1_SL_wci_wTimeout_03_04___d5829 || - wci_wciResponse$wget[33:32] != 2'd0) ; - assign MUX_wci_busy$write_1__SEL_2 = - WILL_FIRE_RL_cpDispatch_F_F_F_F_T_F_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_T_T_T ; - assign MUX_wci_busy_1$write_1__SEL_1 = - WILL_FIRE_RL_wci_wrkBusy_1 && - (!wci_respTimr_1_42_ULT_1_SL_wci_wTimeout_1_43_44___d5830 || - wci_wciResponse_1$wget[33:32] != 2'd0) ; - assign MUX_wci_busy_1$write_1__SEL_2 = - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_F_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_T_T_T ; - assign MUX_wci_busy_10$write_1__SEL_1 = - WILL_FIRE_RL_wci_wrkBusy_10 && - (!wci_respTimr_10_602_ULT_1_SL_wci_wTimeout_10_6_ETC___d5839 || - wci_wciResponse_10$wget[33:32] != 2'd0) ; - assign MUX_wci_busy_10$write_1__SEL_2 = - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_T_T ; - assign MUX_wci_busy_11$write_1__SEL_1 = - WILL_FIRE_RL_wci_wrkBusy_11 && - (!wci_respTimr_11_742_ULT_1_SL_wci_wTimeout_11_7_ETC___d5840 || - wci_wciResponse_11$wget[33:32] != 2'd0) ; - assign MUX_wci_busy_11$write_1__SEL_2 = - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_T_T ; - assign MUX_wci_busy_12$write_1__SEL_1 = - WILL_FIRE_RL_wci_wrkBusy_12 && - (!wci_respTimr_12_882_ULT_1_SL_wci_wTimeout_12_8_ETC___d5841 || - wci_wciResponse_12$wget[33:32] != 2'd0) ; - assign MUX_wci_busy_12$write_1__SEL_2 = - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T ; - assign MUX_wci_busy_13$write_1__SEL_1 = - WILL_FIRE_RL_wci_wrkBusy_13 && - (!wci_respTimr_13_022_ULT_1_SL_wci_wTimeout_13_0_ETC___d5842 || - wci_wciResponse_13$wget[33:32] != 2'd0) ; - assign MUX_wci_busy_13$write_1__SEL_2 = - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T ; - assign MUX_wci_busy_14$write_1__SEL_1 = - WILL_FIRE_RL_wci_wrkBusy_14 && - (!wci_respTimr_14_162_ULT_1_SL_wci_wTimeout_14_1_ETC___d5843 || - wci_wciResponse_14$wget[33:32] != 2'd0) ; - assign MUX_wci_busy_14$write_1__SEL_2 = - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T ; - assign MUX_wci_busy_2$write_1__SEL_1 = - WILL_FIRE_RL_wci_wrkBusy_2 && - (!wci_respTimr_2_82_ULT_1_SL_wci_wTimeout_2_83_84___d5831 || - wci_wciResponse_2$wget[33:32] != 2'd0) ; - assign MUX_wci_busy_2$write_1__SEL_2 = - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_F_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_T_T ; - assign MUX_wci_busy_3$write_1__SEL_1 = - WILL_FIRE_RL_wci_wrkBusy_3 && - (!wci_respTimr_3_22_ULT_1_SL_wci_wTimeout_3_23_24___d5832 || - wci_wciResponse_3$wget[33:32] != 2'd0) ; - assign MUX_wci_busy_3$write_1__SEL_2 = - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_F_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_T_T ; - assign MUX_wci_busy_4$write_1__SEL_1 = - WILL_FIRE_RL_wci_wrkBusy_4 && - (!wci_respTimr_4_62_ULT_1_SL_wci_wTimeout_4_63_64___d5833 || - wci_wciResponse_4$wget[33:32] != 2'd0) ; - assign MUX_wci_busy_4$write_1__SEL_2 = - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_T_T ; - assign MUX_wci_busy_5$write_1__SEL_1 = - WILL_FIRE_RL_wci_wrkBusy_5 && - (!wci_respTimr_5_02_ULT_1_SL_wci_wTimeout_5_03_04___d5834 || - wci_wciResponse_5$wget[33:32] != 2'd0) ; - assign MUX_wci_busy_5$write_1__SEL_2 = - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_T_T ; - assign MUX_wci_busy_6$write_1__SEL_1 = - WILL_FIRE_RL_wci_wrkBusy_6 && - (!wci_respTimr_6_042_ULT_1_SL_wci_wTimeout_6_043_ETC___d5835 || - wci_wciResponse_6$wget[33:32] != 2'd0) ; - assign MUX_wci_busy_6$write_1__SEL_2 = - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_F_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_T_T ; - assign MUX_wci_busy_7$write_1__SEL_1 = - WILL_FIRE_RL_wci_wrkBusy_7 && - (!wci_respTimr_7_182_ULT_1_SL_wci_wTimeout_7_183_ETC___d5836 || - wci_wciResponse_7$wget[33:32] != 2'd0) ; - assign MUX_wci_busy_7$write_1__SEL_2 = - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_T_T ; - assign MUX_wci_busy_8$write_1__SEL_1 = - WILL_FIRE_RL_wci_wrkBusy_8 && - (!wci_respTimr_8_322_ULT_1_SL_wci_wTimeout_8_323_ETC___d5837 || - wci_wciResponse_8$wget[33:32] != 2'd0) ; - assign MUX_wci_busy_8$write_1__SEL_2 = - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_T_T ; - assign MUX_wci_busy_9$write_1__SEL_1 = - WILL_FIRE_RL_wci_wrkBusy_9 && - (!wci_respTimr_9_462_ULT_1_SL_wci_wTimeout_9_463_ETC___d5838 || - wci_wciResponse_9$wget[33:32] != 2'd0) ; - assign MUX_wci_busy_9$write_1__SEL_2 = - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_T_T ; - assign MUX_wci_reqERR$write_1__SEL_1 = - WILL_FIRE_RL_wci_wrkBusy && - wci_wciResponse$wget[33:32] == 2'd3 && - (wci_reqPend == 2'd1 || wci_reqPend == 2'd2 || - wci_reqPend == 2'd3) ; - assign MUX_wci_reqERR_1$write_1__SEL_1 = - WILL_FIRE_RL_wci_wrkBusy_1 && - wci_wciResponse_1$wget[33:32] == 2'd3 && - (wci_reqPend_1 == 2'd1 || wci_reqPend_1 == 2'd2 || - wci_reqPend_1 == 2'd3) ; - assign MUX_wci_reqERR_10$write_1__SEL_1 = - WILL_FIRE_RL_wci_wrkBusy_10 && - wci_wciResponse_10$wget[33:32] == 2'd3 && - (wci_reqPend_10 == 2'd1 || wci_reqPend_10 == 2'd2 || - wci_reqPend_10 == 2'd3) ; - assign MUX_wci_reqERR_11$write_1__SEL_1 = - WILL_FIRE_RL_wci_wrkBusy_11 && - wci_wciResponse_11$wget[33:32] == 2'd3 && - (wci_reqPend_11 == 2'd1 || wci_reqPend_11 == 2'd2 || - wci_reqPend_11 == 2'd3) ; - assign MUX_wci_reqERR_12$write_1__SEL_1 = - WILL_FIRE_RL_wci_wrkBusy_12 && - wci_wciResponse_12$wget[33:32] == 2'd3 && - (wci_reqPend_12 == 2'd1 || wci_reqPend_12 == 2'd2 || - wci_reqPend_12 == 2'd3) ; - assign MUX_wci_reqERR_13$write_1__SEL_1 = - WILL_FIRE_RL_wci_wrkBusy_13 && - wci_wciResponse_13$wget[33:32] == 2'd3 && - (wci_reqPend_13 == 2'd1 || wci_reqPend_13 == 2'd2 || - wci_reqPend_13 == 2'd3) ; - assign MUX_wci_reqERR_14$write_1__SEL_1 = - WILL_FIRE_RL_wci_wrkBusy_14 && - wci_wciResponse_14$wget[33:32] == 2'd3 && - (wci_reqPend_14 == 2'd1 || wci_reqPend_14 == 2'd2 || - wci_reqPend_14 == 2'd3) ; - assign MUX_wci_reqERR_2$write_1__SEL_1 = - WILL_FIRE_RL_wci_wrkBusy_2 && - wci_wciResponse_2$wget[33:32] == 2'd3 && - (wci_reqPend_2 == 2'd1 || wci_reqPend_2 == 2'd2 || - wci_reqPend_2 == 2'd3) ; - assign MUX_wci_reqERR_3$write_1__SEL_1 = - WILL_FIRE_RL_wci_wrkBusy_3 && - wci_wciResponse_3$wget[33:32] == 2'd3 && - (wci_reqPend_3 == 2'd1 || wci_reqPend_3 == 2'd2 || - wci_reqPend_3 == 2'd3) ; - assign MUX_wci_reqERR_4$write_1__SEL_1 = - WILL_FIRE_RL_wci_wrkBusy_4 && - wci_wciResponse_4$wget[33:32] == 2'd3 && - (wci_reqPend_4 == 2'd1 || wci_reqPend_4 == 2'd2 || - wci_reqPend_4 == 2'd3) ; - assign MUX_wci_reqERR_5$write_1__SEL_1 = - WILL_FIRE_RL_wci_wrkBusy_5 && - wci_wciResponse_5$wget[33:32] == 2'd3 && - (wci_reqPend_5 == 2'd1 || wci_reqPend_5 == 2'd2 || - wci_reqPend_5 == 2'd3) ; - assign MUX_wci_reqERR_6$write_1__SEL_1 = - WILL_FIRE_RL_wci_wrkBusy_6 && - wci_wciResponse_6$wget[33:32] == 2'd3 && - (wci_reqPend_6 == 2'd1 || wci_reqPend_6 == 2'd2 || - wci_reqPend_6 == 2'd3) ; - assign MUX_wci_reqERR_7$write_1__SEL_1 = - WILL_FIRE_RL_wci_wrkBusy_7 && - wci_wciResponse_7$wget[33:32] == 2'd3 && - (wci_reqPend_7 == 2'd1 || wci_reqPend_7 == 2'd2 || - wci_reqPend_7 == 2'd3) ; - assign MUX_wci_reqERR_8$write_1__SEL_1 = - WILL_FIRE_RL_wci_wrkBusy_8 && - wci_wciResponse_8$wget[33:32] == 2'd3 && - (wci_reqPend_8 == 2'd1 || wci_reqPend_8 == 2'd2 || - wci_reqPend_8 == 2'd3) ; - assign MUX_wci_reqERR_9$write_1__SEL_1 = - WILL_FIRE_RL_wci_wrkBusy_9 && - wci_wciResponse_9$wget[33:32] == 2'd3 && - (wci_reqPend_9 == 2'd1 || wci_reqPend_9 == 2'd2 || - wci_reqPend_9 == 2'd3) ; - assign MUX_wci_reqFAIL$write_1__SEL_1 = - WILL_FIRE_RL_wci_wrkBusy && - wci_wciResponse$wget[33:32] == 2'd2 && - (wci_reqPend == 2'd1 || wci_reqPend == 2'd2 || - wci_reqPend == 2'd3) ; - assign MUX_wci_reqFAIL_1$write_1__SEL_1 = - WILL_FIRE_RL_wci_wrkBusy_1 && - wci_wciResponse_1$wget[33:32] == 2'd2 && - (wci_reqPend_1 == 2'd1 || wci_reqPend_1 == 2'd2 || - wci_reqPend_1 == 2'd3) ; - assign MUX_wci_reqFAIL_10$write_1__SEL_1 = - WILL_FIRE_RL_wci_wrkBusy_10 && - wci_wciResponse_10$wget[33:32] == 2'd2 && - (wci_reqPend_10 == 2'd1 || wci_reqPend_10 == 2'd2 || - wci_reqPend_10 == 2'd3) ; - assign MUX_wci_reqFAIL_11$write_1__SEL_1 = - WILL_FIRE_RL_wci_wrkBusy_11 && - wci_wciResponse_11$wget[33:32] == 2'd2 && - (wci_reqPend_11 == 2'd1 || wci_reqPend_11 == 2'd2 || - wci_reqPend_11 == 2'd3) ; - assign MUX_wci_reqFAIL_12$write_1__SEL_1 = - WILL_FIRE_RL_wci_wrkBusy_12 && - wci_wciResponse_12$wget[33:32] == 2'd2 && - (wci_reqPend_12 == 2'd1 || wci_reqPend_12 == 2'd2 || - wci_reqPend_12 == 2'd3) ; - assign MUX_wci_reqFAIL_13$write_1__SEL_1 = - WILL_FIRE_RL_wci_wrkBusy_13 && - wci_wciResponse_13$wget[33:32] == 2'd2 && - (wci_reqPend_13 == 2'd1 || wci_reqPend_13 == 2'd2 || - wci_reqPend_13 == 2'd3) ; - assign MUX_wci_reqFAIL_14$write_1__SEL_1 = - WILL_FIRE_RL_wci_wrkBusy_14 && - wci_wciResponse_14$wget[33:32] == 2'd2 && - (wci_reqPend_14 == 2'd1 || wci_reqPend_14 == 2'd2 || - wci_reqPend_14 == 2'd3) ; - assign MUX_wci_reqFAIL_2$write_1__SEL_1 = - WILL_FIRE_RL_wci_wrkBusy_2 && - wci_wciResponse_2$wget[33:32] == 2'd2 && - (wci_reqPend_2 == 2'd1 || wci_reqPend_2 == 2'd2 || - wci_reqPend_2 == 2'd3) ; - assign MUX_wci_reqFAIL_3$write_1__SEL_1 = - WILL_FIRE_RL_wci_wrkBusy_3 && - wci_wciResponse_3$wget[33:32] == 2'd2 && - (wci_reqPend_3 == 2'd1 || wci_reqPend_3 == 2'd2 || - wci_reqPend_3 == 2'd3) ; - assign MUX_wci_reqFAIL_4$write_1__SEL_1 = - WILL_FIRE_RL_wci_wrkBusy_4 && - wci_wciResponse_4$wget[33:32] == 2'd2 && - (wci_reqPend_4 == 2'd1 || wci_reqPend_4 == 2'd2 || - wci_reqPend_4 == 2'd3) ; - assign MUX_wci_reqFAIL_5$write_1__SEL_1 = - WILL_FIRE_RL_wci_wrkBusy_5 && - wci_wciResponse_5$wget[33:32] == 2'd2 && - (wci_reqPend_5 == 2'd1 || wci_reqPend_5 == 2'd2 || - wci_reqPend_5 == 2'd3) ; - assign MUX_wci_reqFAIL_6$write_1__SEL_1 = - WILL_FIRE_RL_wci_wrkBusy_6 && - wci_wciResponse_6$wget[33:32] == 2'd2 && - (wci_reqPend_6 == 2'd1 || wci_reqPend_6 == 2'd2 || - wci_reqPend_6 == 2'd3) ; - assign MUX_wci_reqFAIL_7$write_1__SEL_1 = - WILL_FIRE_RL_wci_wrkBusy_7 && - wci_wciResponse_7$wget[33:32] == 2'd2 && - (wci_reqPend_7 == 2'd1 || wci_reqPend_7 == 2'd2 || - wci_reqPend_7 == 2'd3) ; - assign MUX_wci_reqFAIL_8$write_1__SEL_1 = - WILL_FIRE_RL_wci_wrkBusy_8 && - wci_wciResponse_8$wget[33:32] == 2'd2 && - (wci_reqPend_8 == 2'd1 || wci_reqPend_8 == 2'd2 || - wci_reqPend_8 == 2'd3) ; - assign MUX_wci_reqFAIL_9$write_1__SEL_1 = - WILL_FIRE_RL_wci_wrkBusy_9 && - wci_wciResponse_9$wget[33:32] == 2'd2 && - (wci_reqPend_9 == 2'd1 || wci_reqPend_9 == 2'd2 || - wci_reqPend_9 == 2'd3) ; - assign MUX_wci_reqF_10_q_0$write_1__SEL_1 = - WILL_FIRE_RL_wci_reqF_10_incCtr && !wci_reqF_10_c_r ; - assign MUX_wci_reqF_11_q_0$write_1__SEL_1 = - WILL_FIRE_RL_wci_reqF_11_incCtr && !wci_reqF_11_c_r ; - assign MUX_wci_reqF_12_q_0$write_1__SEL_1 = - WILL_FIRE_RL_wci_reqF_12_incCtr && !wci_reqF_12_c_r ; - assign MUX_wci_reqF_13_q_0$write_1__SEL_1 = - WILL_FIRE_RL_wci_reqF_13_incCtr && !wci_reqF_13_c_r ; - assign MUX_wci_reqF_14_q_0$write_1__SEL_1 = - WILL_FIRE_RL_wci_reqF_14_incCtr && !wci_reqF_14_c_r ; - assign MUX_wci_reqF_1_q_0$write_1__SEL_2 = - WILL_FIRE_RL_wci_reqF_1_incCtr && !wci_reqF_1_c_r ; - assign MUX_wci_reqF_2_q_0$write_1__SEL_1 = - WILL_FIRE_RL_wci_reqF_2_incCtr && !wci_reqF_2_c_r ; - assign MUX_wci_reqF_3_q_0$write_1__SEL_1 = - WILL_FIRE_RL_wci_reqF_3_incCtr && !wci_reqF_3_c_r ; - assign MUX_wci_reqF_4_q_0$write_1__SEL_1 = - WILL_FIRE_RL_wci_reqF_4_incCtr && !wci_reqF_4_c_r ; - assign MUX_wci_reqF_5_q_0$write_1__SEL_1 = - WILL_FIRE_RL_wci_reqF_5_incCtr && !wci_reqF_5_c_r ; - assign MUX_wci_reqF_6_q_0$write_1__SEL_1 = - WILL_FIRE_RL_wci_reqF_6_incCtr && !wci_reqF_6_c_r ; - assign MUX_wci_reqF_7_q_0$write_1__SEL_1 = - WILL_FIRE_RL_wci_reqF_7_incCtr && !wci_reqF_7_c_r ; - assign MUX_wci_reqF_8_q_0$write_1__SEL_1 = - WILL_FIRE_RL_wci_reqF_8_incCtr && !wci_reqF_8_c_r ; - assign MUX_wci_reqF_9_q_0$write_1__SEL_1 = - WILL_FIRE_RL_wci_reqF_9_incCtr && !wci_reqF_9_c_r ; - assign MUX_wci_reqF_q_0$write_1__SEL_2 = - WILL_FIRE_RL_wci_reqF_incCtr && !wci_reqF_c_r ; - assign MUX_wci_reqPend$write_1__SEL_1 = - WILL_FIRE_RL_wci_wrkBusy && wci_wciResponse$wget[33:32] != 2'd0 ; - assign MUX_wci_reqPend_1$write_1__SEL_1 = - WILL_FIRE_RL_wci_wrkBusy_1 && - wci_wciResponse_1$wget[33:32] != 2'd0 ; - assign MUX_wci_reqPend_10$write_1__SEL_1 = - WILL_FIRE_RL_wci_wrkBusy_10 && - wci_wciResponse_10$wget[33:32] != 2'd0 ; - assign MUX_wci_reqPend_11$write_1__SEL_1 = - WILL_FIRE_RL_wci_wrkBusy_11 && - wci_wciResponse_11$wget[33:32] != 2'd0 ; - assign MUX_wci_reqPend_12$write_1__SEL_1 = - WILL_FIRE_RL_wci_wrkBusy_12 && - wci_wciResponse_12$wget[33:32] != 2'd0 ; - assign MUX_wci_reqPend_13$write_1__SEL_1 = - WILL_FIRE_RL_wci_wrkBusy_13 && - wci_wciResponse_13$wget[33:32] != 2'd0 ; - assign MUX_wci_reqPend_14$write_1__SEL_1 = - WILL_FIRE_RL_wci_wrkBusy_14 && - wci_wciResponse_14$wget[33:32] != 2'd0 ; - assign MUX_wci_reqPend_2$write_1__SEL_1 = - WILL_FIRE_RL_wci_wrkBusy_2 && - wci_wciResponse_2$wget[33:32] != 2'd0 ; - assign MUX_wci_reqPend_3$write_1__SEL_1 = - WILL_FIRE_RL_wci_wrkBusy_3 && - wci_wciResponse_3$wget[33:32] != 2'd0 ; - assign MUX_wci_reqPend_4$write_1__SEL_1 = - WILL_FIRE_RL_wci_wrkBusy_4 && - wci_wciResponse_4$wget[33:32] != 2'd0 ; - assign MUX_wci_reqPend_5$write_1__SEL_1 = - WILL_FIRE_RL_wci_wrkBusy_5 && - wci_wciResponse_5$wget[33:32] != 2'd0 ; - assign MUX_wci_reqPend_6$write_1__SEL_1 = - WILL_FIRE_RL_wci_wrkBusy_6 && - wci_wciResponse_6$wget[33:32] != 2'd0 ; - assign MUX_wci_reqPend_7$write_1__SEL_1 = - WILL_FIRE_RL_wci_wrkBusy_7 && - wci_wciResponse_7$wget[33:32] != 2'd0 ; - assign MUX_wci_reqPend_8$write_1__SEL_1 = - WILL_FIRE_RL_wci_wrkBusy_8 && - wci_wciResponse_8$wget[33:32] != 2'd0 ; - assign MUX_wci_reqPend_9$write_1__SEL_1 = - WILL_FIRE_RL_wci_wrkBusy_9 && - wci_wciResponse_9$wget[33:32] != 2'd0 ; - assign MUX_wci_reqTO$write_1__SEL_1 = - WILL_FIRE_RL_wci_wrkBusy && - wci_wciResponse_wget__97_BITS_33_TO_32_98_EQ_0_ETC___d226 ; - assign MUX_wci_reqTO_1$write_1__SEL_1 = - WILL_FIRE_RL_wci_wrkBusy_1 && - wci_wciResponse_1_wget__37_BITS_33_TO_32_38_EQ_ETC___d366 ; - assign MUX_wci_reqTO_10$write_1__SEL_1 = - WILL_FIRE_RL_wci_wrkBusy_10 && - wci_wciResponse_10_wget__597_BITS_33_TO_32_598_ETC___d1626 ; - assign MUX_wci_reqTO_11$write_1__SEL_1 = - WILL_FIRE_RL_wci_wrkBusy_11 && - wci_wciResponse_11_wget__737_BITS_33_TO_32_738_ETC___d1766 ; - assign MUX_wci_reqTO_12$write_1__SEL_1 = - WILL_FIRE_RL_wci_wrkBusy_12 && - wci_wciResponse_12_wget__877_BITS_33_TO_32_878_ETC___d1906 ; - assign MUX_wci_reqTO_13$write_1__SEL_1 = - WILL_FIRE_RL_wci_wrkBusy_13 && - wci_wciResponse_13_wget__017_BITS_33_TO_32_018_ETC___d2046 ; - assign MUX_wci_reqTO_14$write_1__SEL_1 = - WILL_FIRE_RL_wci_wrkBusy_14 && - wci_wciResponse_14_wget__157_BITS_33_TO_32_158_ETC___d2186 ; - assign MUX_wci_reqTO_2$write_1__SEL_1 = - WILL_FIRE_RL_wci_wrkBusy_2 && - wci_wciResponse_2_wget__77_BITS_33_TO_32_78_EQ_ETC___d506 ; - assign MUX_wci_reqTO_3$write_1__SEL_1 = - WILL_FIRE_RL_wci_wrkBusy_3 && - wci_wciResponse_3_wget__17_BITS_33_TO_32_18_EQ_ETC___d646 ; - assign MUX_wci_reqTO_4$write_1__SEL_1 = - WILL_FIRE_RL_wci_wrkBusy_4 && - wci_wciResponse_4_wget__57_BITS_33_TO_32_58_EQ_ETC___d786 ; - assign MUX_wci_reqTO_5$write_1__SEL_1 = - WILL_FIRE_RL_wci_wrkBusy_5 && - wci_wciResponse_5_wget__97_BITS_33_TO_32_98_EQ_ETC___d926 ; - assign MUX_wci_reqTO_6$write_1__SEL_1 = - WILL_FIRE_RL_wci_wrkBusy_6 && - wci_wciResponse_6_wget__037_BITS_33_TO_32_038__ETC___d1066 ; - assign MUX_wci_reqTO_7$write_1__SEL_1 = - WILL_FIRE_RL_wci_wrkBusy_7 && - wci_wciResponse_7_wget__177_BITS_33_TO_32_178__ETC___d1206 ; - assign MUX_wci_reqTO_8$write_1__SEL_1 = - WILL_FIRE_RL_wci_wrkBusy_8 && - wci_wciResponse_8_wget__317_BITS_33_TO_32_318__ETC___d1346 ; - assign MUX_wci_reqTO_9$write_1__SEL_1 = - WILL_FIRE_RL_wci_wrkBusy_9 && - wci_wciResponse_9_wget__457_BITS_33_TO_32_458__ETC___d1486 ; - assign MUX_wci_respF$enq_1__SEL_6 = - WILL_FIRE_RL_cpDispatch_F_F_F_F_T_F_F_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_T_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_T_F_F_T_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_T_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_T_F_F_T_T_T ; - assign MUX_wci_respF$enq_1__SEL_7 = - WILL_FIRE_RL_cpDispatch_F_F_F_F_T_F_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_T_T_F ; - assign MUX_wci_respF_1$enq_1__SEL_6 = - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_F_F_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_T_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_T_F_F_T_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_T_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_T_F_F_T_T_T ; - assign MUX_wci_respF_1$enq_1__SEL_7 = - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_F_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_T_T_F ; - assign MUX_wci_respF_10$enq_1__SEL_6 = - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_T ; - assign MUX_wci_respF_10$enq_1__SEL_7 = - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_T_F ; - assign MUX_wci_respF_11$enq_1__SEL_6 = - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_T ; - assign MUX_wci_respF_11$enq_1__SEL_7 = - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_T_F ; - assign MUX_wci_respF_12$enq_1__SEL_6 = - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_T ; - assign MUX_wci_respF_12$enq_1__SEL_7 = - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F ; - assign MUX_wci_respF_13$enq_1__SEL_6 = - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_T ; - assign MUX_wci_respF_13$enq_1__SEL_7 = - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F ; - assign MUX_wci_respF_14$enq_1__SEL_6 = - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_T ; - assign MUX_wci_respF_14$enq_1__SEL_7 = - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F ; - assign MUX_wci_respF_2$enq_1__SEL_6 = - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_F_F_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_F_F_T_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_F_F_T_T_T ; - assign MUX_wci_respF_2$enq_1__SEL_7 = - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_F_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_T_F ; - assign MUX_wci_respF_3$enq_1__SEL_6 = - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_F_F_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_F_F_T_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_F_F_T_T_T ; - assign MUX_wci_respF_3$enq_1__SEL_7 = - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_F_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_T_F ; - assign MUX_wci_respF_4$enq_1__SEL_6 = - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_F_F_T_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_F_F_T_T_T ; - assign MUX_wci_respF_4$enq_1__SEL_7 = - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_T_F ; - assign MUX_wci_respF_5$enq_1__SEL_6 = - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_F_T_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_F_T_T_T ; - assign MUX_wci_respF_5$enq_1__SEL_7 = - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_T_F ; - assign MUX_wci_respF_6$enq_1__SEL_6 = - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_F_F_T_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_F_F_T_T_T ; - assign MUX_wci_respF_6$enq_1__SEL_7 = - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_F_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_T_F ; - assign MUX_wci_respF_7$enq_1__SEL_6 = - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_F_F_T_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_F_F_T_T_T ; - assign MUX_wci_respF_7$enq_1__SEL_7 = - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_T_F ; - assign MUX_wci_respF_8$enq_1__SEL_6 = - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_F_F_T_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_F_F_T_T_T ; - assign MUX_wci_respF_8$enq_1__SEL_7 = - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_T_F ; - assign MUX_wci_respF_9$enq_1__SEL_6 = - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_F_F_T_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_F_F_T_T_T ; - assign MUX_wci_respF_9$enq_1__SEL_7 = - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_T_F ; + assign MUX_wci_0_busy$write_1__SEL_1 = + WILL_FIRE_RL_wci_0_wrkBusy && + (!wci_0_respTimr_28_ULT_1_SL_wci_0_wTimeout_29_30___d231 || + wci_0_wciResponse$wget[33:32] != 2'd0) ; + assign MUX_wci_0_busy$write_1__SEL_2 = + WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E0_T_T ; + assign MUX_wci_0_reqERR$write_1__SEL_1 = + WILL_FIRE_RL_wci_0_wrkBusy && + wci_0_wciResponse$wget[33:32] == 2'd3 && + (wci_0_reqPend == 2'd1 || wci_0_reqPend == 2'd2 || + wci_0_reqPend == 2'd3) ; + assign MUX_wci_0_reqFAIL$write_1__SEL_1 = + WILL_FIRE_RL_wci_0_wrkBusy && + wci_0_wciResponse$wget[33:32] == 2'd2 && + (wci_0_reqPend == 2'd1 || wci_0_reqPend == 2'd2 || + wci_0_reqPend == 2'd3) ; + assign MUX_wci_0_reqF_q_0$write_1__SEL_2 = + WILL_FIRE_RL_wci_0_reqF_incCtr && !wci_0_reqF_cntr_r ; + assign MUX_wci_0_reqPend$write_1__SEL_1 = + WILL_FIRE_RL_wci_0_wrkBusy && + wci_0_wciResponse$wget[33:32] != 2'd0 ; + assign MUX_wci_0_reqTO$write_1__SEL_1 = + WILL_FIRE_RL_wci_0_wrkBusy && + wci_0_wciResponse_wget__23_BITS_33_TO_32_24_EQ_ETC___d252 ; + assign MUX_wci_0_respF$enq_1__SEL_6 = + WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_F_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E0_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E0_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E0_F_F_T_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E0_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E0_F_F_T_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E0_F_F_T_T_T ; + assign MUX_wci_0_respF$enq_1__SEL_7 = + WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E0_T_F ; + assign MUX_wci_10_busy$write_1__SEL_1 = + WILL_FIRE_RL_wci_10_wrkBusy && + (!wci_10_respTimr_628_ULT_1_SL_wci_10_wTimeout_6_ETC___d1631 || + wci_10_wciResponse$wget[33:32] != 2'd0) ; + assign MUX_wci_10_busy$write_1__SEL_2 = + WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_F_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E10_T_T ; + assign MUX_wci_10_reqERR$write_1__SEL_1 = + WILL_FIRE_RL_wci_10_wrkBusy && + wci_10_wciResponse$wget[33:32] == 2'd3 && + (wci_10_reqPend == 2'd1 || wci_10_reqPend == 2'd2 || + wci_10_reqPend == 2'd3) ; + assign MUX_wci_10_reqFAIL$write_1__SEL_1 = + WILL_FIRE_RL_wci_10_wrkBusy && + wci_10_wciResponse$wget[33:32] == 2'd2 && + (wci_10_reqPend == 2'd1 || wci_10_reqPend == 2'd2 || + wci_10_reqPend == 2'd3) ; + assign MUX_wci_10_reqF_q_0$write_1__SEL_1 = + WILL_FIRE_RL_wci_10_reqF_incCtr && !wci_10_reqF_cntr_r ; + assign MUX_wci_10_reqPend$write_1__SEL_1 = + WILL_FIRE_RL_wci_10_wrkBusy && + wci_10_wciResponse$wget[33:32] != 2'd0 ; + assign MUX_wci_10_reqTO$write_1__SEL_1 = + WILL_FIRE_RL_wci_10_wrkBusy && + wci_10_wciResponse_wget__623_BITS_33_TO_32_624_ETC___d1652 ; + assign MUX_wci_10_respF$enq_1__SEL_6 = + WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_F_F_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E10_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E10_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E10_F_F_T_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E10_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E10_F_F_T_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E10_F_F_T_T_T ; + assign MUX_wci_10_respF$enq_1__SEL_7 = + WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_F_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E10_T_F ; + assign MUX_wci_11_busy$write_1__SEL_1 = + WILL_FIRE_RL_wci_11_wrkBusy && + (!wci_11_respTimr_768_ULT_1_SL_wci_11_wTimeout_7_ETC___d1771 || + wci_11_wciResponse$wget[33:32] != 2'd0) ; + assign MUX_wci_11_busy$write_1__SEL_2 = + WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_F_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E11_T_T ; + assign MUX_wci_11_reqERR$write_1__SEL_1 = + WILL_FIRE_RL_wci_11_wrkBusy && + wci_11_wciResponse$wget[33:32] == 2'd3 && + (wci_11_reqPend == 2'd1 || wci_11_reqPend == 2'd2 || + wci_11_reqPend == 2'd3) ; + assign MUX_wci_11_reqFAIL$write_1__SEL_1 = + WILL_FIRE_RL_wci_11_wrkBusy && + wci_11_wciResponse$wget[33:32] == 2'd2 && + (wci_11_reqPend == 2'd1 || wci_11_reqPend == 2'd2 || + wci_11_reqPend == 2'd3) ; + assign MUX_wci_11_reqF_q_0$write_1__SEL_1 = + WILL_FIRE_RL_wci_11_reqF_incCtr && !wci_11_reqF_cntr_r ; + assign MUX_wci_11_reqPend$write_1__SEL_1 = + WILL_FIRE_RL_wci_11_wrkBusy && + wci_11_wciResponse$wget[33:32] != 2'd0 ; + assign MUX_wci_11_reqTO$write_1__SEL_1 = + WILL_FIRE_RL_wci_11_wrkBusy && + wci_11_wciResponse_wget__763_BITS_33_TO_32_764_ETC___d1792 ; + assign MUX_wci_11_respF$enq_1__SEL_6 = + WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_F_F_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E11_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E11_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E11_F_F_T_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E11_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E11_F_F_T_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E11_F_F_T_T_T ; + assign MUX_wci_11_respF$enq_1__SEL_7 = + WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_F_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E11_T_F ; + assign MUX_wci_12_busy$write_1__SEL_1 = + WILL_FIRE_RL_wci_12_wrkBusy && + (!wci_12_respTimr_908_ULT_1_SL_wci_12_wTimeout_9_ETC___d1911 || + wci_12_wciResponse$wget[33:32] != 2'd0) ; + assign MUX_wci_12_busy$write_1__SEL_2 = + WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_F_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E12_T_T ; + assign MUX_wci_12_reqERR$write_1__SEL_1 = + WILL_FIRE_RL_wci_12_wrkBusy && + wci_12_wciResponse$wget[33:32] == 2'd3 && + (wci_12_reqPend == 2'd1 || wci_12_reqPend == 2'd2 || + wci_12_reqPend == 2'd3) ; + assign MUX_wci_12_reqFAIL$write_1__SEL_1 = + WILL_FIRE_RL_wci_12_wrkBusy && + wci_12_wciResponse$wget[33:32] == 2'd2 && + (wci_12_reqPend == 2'd1 || wci_12_reqPend == 2'd2 || + wci_12_reqPend == 2'd3) ; + assign MUX_wci_12_reqF_q_0$write_1__SEL_1 = + WILL_FIRE_RL_wci_12_reqF_incCtr && !wci_12_reqF_cntr_r ; + assign MUX_wci_12_reqPend$write_1__SEL_1 = + WILL_FIRE_RL_wci_12_wrkBusy && + wci_12_wciResponse$wget[33:32] != 2'd0 ; + assign MUX_wci_12_reqTO$write_1__SEL_1 = + WILL_FIRE_RL_wci_12_wrkBusy && + wci_12_wciResponse_wget__903_BITS_33_TO_32_904_ETC___d1932 ; + assign MUX_wci_12_respF$enq_1__SEL_6 = + WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_F_F_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E12_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E12_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E12_F_F_T_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E12_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E12_F_F_T_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E12_F_F_T_T_T ; + assign MUX_wci_12_respF$enq_1__SEL_7 = + WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_F_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E12_T_F ; + assign MUX_wci_13_busy$write_1__SEL_1 = + WILL_FIRE_RL_wci_13_wrkBusy && + (!wci_13_respTimr_048_ULT_1_SL_wci_13_wTimeout_0_ETC___d2051 || + wci_13_wciResponse$wget[33:32] != 2'd0) ; + assign MUX_wci_13_busy$write_1__SEL_2 = + WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_F_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E13_T_T ; + assign MUX_wci_13_reqERR$write_1__SEL_1 = + WILL_FIRE_RL_wci_13_wrkBusy && + wci_13_wciResponse$wget[33:32] == 2'd3 && + (wci_13_reqPend == 2'd1 || wci_13_reqPend == 2'd2 || + wci_13_reqPend == 2'd3) ; + assign MUX_wci_13_reqFAIL$write_1__SEL_1 = + WILL_FIRE_RL_wci_13_wrkBusy && + wci_13_wciResponse$wget[33:32] == 2'd2 && + (wci_13_reqPend == 2'd1 || wci_13_reqPend == 2'd2 || + wci_13_reqPend == 2'd3) ; + assign MUX_wci_13_reqF_q_0$write_1__SEL_1 = + WILL_FIRE_RL_wci_13_reqF_incCtr && !wci_13_reqF_cntr_r ; + assign MUX_wci_13_reqPend$write_1__SEL_1 = + WILL_FIRE_RL_wci_13_wrkBusy && + wci_13_wciResponse$wget[33:32] != 2'd0 ; + assign MUX_wci_13_reqTO$write_1__SEL_1 = + WILL_FIRE_RL_wci_13_wrkBusy && + wci_13_wciResponse_wget__043_BITS_33_TO_32_044_ETC___d2072 ; + assign MUX_wci_13_respF$enq_1__SEL_6 = + WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_F_F_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E13_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E13_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E13_F_F_T_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E13_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E13_F_F_T_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E13_F_F_T_T_T ; + assign MUX_wci_13_respF$enq_1__SEL_7 = + WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_F_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E13_T_F ; + assign MUX_wci_14_busy$write_1__SEL_1 = + WILL_FIRE_RL_wci_14_wrkBusy && + (!wci_14_respTimr_188_ULT_1_SL_wci_14_wTimeout_1_ETC___d2191 || + wci_14_wciResponse$wget[33:32] != 2'd0) ; + assign MUX_wci_14_busy$write_1__SEL_2 = + WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_F_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E14_T_T ; + assign MUX_wci_14_reqERR$write_1__SEL_1 = + WILL_FIRE_RL_wci_14_wrkBusy && + wci_14_wciResponse$wget[33:32] == 2'd3 && + (wci_14_reqPend == 2'd1 || wci_14_reqPend == 2'd2 || + wci_14_reqPend == 2'd3) ; + assign MUX_wci_14_reqFAIL$write_1__SEL_1 = + WILL_FIRE_RL_wci_14_wrkBusy && + wci_14_wciResponse$wget[33:32] == 2'd2 && + (wci_14_reqPend == 2'd1 || wci_14_reqPend == 2'd2 || + wci_14_reqPend == 2'd3) ; + assign MUX_wci_14_reqF_q_0$write_1__SEL_1 = + WILL_FIRE_RL_wci_14_reqF_incCtr && !wci_14_reqF_cntr_r ; + assign MUX_wci_14_reqPend$write_1__SEL_1 = + WILL_FIRE_RL_wci_14_wrkBusy && + wci_14_wciResponse$wget[33:32] != 2'd0 ; + assign MUX_wci_14_reqTO$write_1__SEL_1 = + WILL_FIRE_RL_wci_14_wrkBusy && + wci_14_wciResponse_wget__183_BITS_33_TO_32_184_ETC___d2212 ; + assign MUX_wci_14_respF$enq_1__SEL_6 = + WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_F_F_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E14_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E14_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E14_F_F_T_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E14_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E14_F_F_T_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E14_F_F_T_T_T ; + assign MUX_wci_14_respF$enq_1__SEL_7 = + WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_F_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E14_T_F ; + assign MUX_wci_1_busy$write_1__SEL_1 = + WILL_FIRE_RL_wci_1_wrkBusy && + (!wci_1_respTimr_68_ULT_1_SL_wci_1_wTimeout_69_70___d371 || + wci_1_wciResponse$wget[33:32] != 2'd0) ; + assign MUX_wci_1_busy$write_1__SEL_2 = + WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E1_T_T ; + assign MUX_wci_1_reqERR$write_1__SEL_1 = + WILL_FIRE_RL_wci_1_wrkBusy && + wci_1_wciResponse$wget[33:32] == 2'd3 && + (wci_1_reqPend == 2'd1 || wci_1_reqPend == 2'd2 || + wci_1_reqPend == 2'd3) ; + assign MUX_wci_1_reqFAIL$write_1__SEL_1 = + WILL_FIRE_RL_wci_1_wrkBusy && + wci_1_wciResponse$wget[33:32] == 2'd2 && + (wci_1_reqPend == 2'd1 || wci_1_reqPend == 2'd2 || + wci_1_reqPend == 2'd3) ; + assign MUX_wci_1_reqF_q_0$write_1__SEL_2 = + WILL_FIRE_RL_wci_1_reqF_incCtr && !wci_1_reqF_cntr_r ; + assign MUX_wci_1_reqPend$write_1__SEL_1 = + WILL_FIRE_RL_wci_1_wrkBusy && + wci_1_wciResponse$wget[33:32] != 2'd0 ; + assign MUX_wci_1_reqTO$write_1__SEL_1 = + WILL_FIRE_RL_wci_1_wrkBusy && + wci_1_wciResponse_wget__63_BITS_33_TO_32_64_EQ_ETC___d392 ; + assign MUX_wci_1_respF$enq_1__SEL_6 = + WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_F_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E1_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E1_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E1_F_F_T_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E1_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E1_F_F_T_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E1_F_F_T_T_T ; + assign MUX_wci_1_respF$enq_1__SEL_7 = + WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E1_T_F ; + assign MUX_wci_2_busy$write_1__SEL_1 = + WILL_FIRE_RL_wci_2_wrkBusy && + (!wci_2_respTimr_08_ULT_1_SL_wci_2_wTimeout_09_10___d511 || + wci_2_wciResponse$wget[33:32] != 2'd0) ; + assign MUX_wci_2_busy$write_1__SEL_2 = + WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_F_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E2_T_T ; + assign MUX_wci_2_reqERR$write_1__SEL_1 = + WILL_FIRE_RL_wci_2_wrkBusy && + wci_2_wciResponse$wget[33:32] == 2'd3 && + (wci_2_reqPend == 2'd1 || wci_2_reqPend == 2'd2 || + wci_2_reqPend == 2'd3) ; + assign MUX_wci_2_reqFAIL$write_1__SEL_1 = + WILL_FIRE_RL_wci_2_wrkBusy && + wci_2_wciResponse$wget[33:32] == 2'd2 && + (wci_2_reqPend == 2'd1 || wci_2_reqPend == 2'd2 || + wci_2_reqPend == 2'd3) ; + assign MUX_wci_2_reqF_q_0$write_1__SEL_2 = + WILL_FIRE_RL_wci_2_reqF_incCtr && !wci_2_reqF_cntr_r ; + assign MUX_wci_2_reqPend$write_1__SEL_1 = + WILL_FIRE_RL_wci_2_wrkBusy && + wci_2_wciResponse$wget[33:32] != 2'd0 ; + assign MUX_wci_2_reqTO$write_1__SEL_1 = + WILL_FIRE_RL_wci_2_wrkBusy && + wci_2_wciResponse_wget__03_BITS_33_TO_32_04_EQ_ETC___d532 ; + assign MUX_wci_2_respF$enq_1__SEL_6 = + WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_F_F_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E2_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E2_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E2_F_F_T_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E2_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E2_F_F_T_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E2_F_F_T_T_T ; + assign MUX_wci_2_respF$enq_1__SEL_7 = + WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_F_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E2_T_F ; + assign MUX_wci_3_busy$write_1__SEL_1 = + WILL_FIRE_RL_wci_3_wrkBusy && + (!wci_3_respTimr_48_ULT_1_SL_wci_3_wTimeout_49_50___d651 || + wci_3_wciResponse$wget[33:32] != 2'd0) ; + assign MUX_wci_3_busy$write_1__SEL_2 = + WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_F_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E3_T_T ; + assign MUX_wci_3_reqERR$write_1__SEL_1 = + WILL_FIRE_RL_wci_3_wrkBusy && + wci_3_wciResponse$wget[33:32] == 2'd3 && + (wci_3_reqPend == 2'd1 || wci_3_reqPend == 2'd2 || + wci_3_reqPend == 2'd3) ; + assign MUX_wci_3_reqFAIL$write_1__SEL_1 = + WILL_FIRE_RL_wci_3_wrkBusy && + wci_3_wciResponse$wget[33:32] == 2'd2 && + (wci_3_reqPend == 2'd1 || wci_3_reqPend == 2'd2 || + wci_3_reqPend == 2'd3) ; + assign MUX_wci_3_reqF_q_0$write_1__SEL_2 = + WILL_FIRE_RL_wci_3_reqF_incCtr && !wci_3_reqF_cntr_r ; + assign MUX_wci_3_reqPend$write_1__SEL_1 = + WILL_FIRE_RL_wci_3_wrkBusy && + wci_3_wciResponse$wget[33:32] != 2'd0 ; + assign MUX_wci_3_reqTO$write_1__SEL_1 = + WILL_FIRE_RL_wci_3_wrkBusy && + wci_3_wciResponse_wget__43_BITS_33_TO_32_44_EQ_ETC___d672 ; + assign MUX_wci_3_respF$enq_1__SEL_6 = + WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_F_F_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E3_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E3_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E3_F_F_T_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E3_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E3_F_F_T_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E3_F_F_T_T_T ; + assign MUX_wci_3_respF$enq_1__SEL_7 = + WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_F_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E3_T_F ; + assign MUX_wci_4_busy$write_1__SEL_1 = + WILL_FIRE_RL_wci_4_wrkBusy && + (!wci_4_respTimr_88_ULT_1_SL_wci_4_wTimeout_89_90___d791 || + wci_4_wciResponse$wget[33:32] != 2'd0) ; + assign MUX_wci_4_busy$write_1__SEL_2 = + WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_F_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E4_T_T ; + assign MUX_wci_4_reqERR$write_1__SEL_1 = + WILL_FIRE_RL_wci_4_wrkBusy && + wci_4_wciResponse$wget[33:32] == 2'd3 && + (wci_4_reqPend == 2'd1 || wci_4_reqPend == 2'd2 || + wci_4_reqPend == 2'd3) ; + assign MUX_wci_4_reqFAIL$write_1__SEL_1 = + WILL_FIRE_RL_wci_4_wrkBusy && + wci_4_wciResponse$wget[33:32] == 2'd2 && + (wci_4_reqPend == 2'd1 || wci_4_reqPend == 2'd2 || + wci_4_reqPend == 2'd3) ; + assign MUX_wci_4_reqF_q_0$write_1__SEL_2 = + WILL_FIRE_RL_wci_4_reqF_incCtr && !wci_4_reqF_cntr_r ; + assign MUX_wci_4_reqPend$write_1__SEL_1 = + WILL_FIRE_RL_wci_4_wrkBusy && + wci_4_wciResponse$wget[33:32] != 2'd0 ; + assign MUX_wci_4_reqTO$write_1__SEL_1 = + WILL_FIRE_RL_wci_4_wrkBusy && + wci_4_wciResponse_wget__83_BITS_33_TO_32_84_EQ_ETC___d812 ; + assign MUX_wci_4_respF$enq_1__SEL_6 = + WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_F_F_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E4_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E4_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E4_F_F_T_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E4_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E4_F_F_T_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E4_F_F_T_T_T ; + assign MUX_wci_4_respF$enq_1__SEL_7 = + WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_F_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E4_T_F ; + assign MUX_wci_5_busy$write_1__SEL_1 = + WILL_FIRE_RL_wci_5_wrkBusy && + (!wci_5_respTimr_28_ULT_1_SL_wci_5_wTimeout_29_30___d931 || + wci_5_wciResponse$wget[33:32] != 2'd0) ; + assign MUX_wci_5_busy$write_1__SEL_2 = + WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E5_T_T ; + assign MUX_wci_5_reqERR$write_1__SEL_1 = + WILL_FIRE_RL_wci_5_wrkBusy && + wci_5_wciResponse$wget[33:32] == 2'd3 && + (wci_5_reqPend == 2'd1 || wci_5_reqPend == 2'd2 || + wci_5_reqPend == 2'd3) ; + assign MUX_wci_5_reqFAIL$write_1__SEL_1 = + WILL_FIRE_RL_wci_5_wrkBusy && + wci_5_wciResponse$wget[33:32] == 2'd2 && + (wci_5_reqPend == 2'd1 || wci_5_reqPend == 2'd2 || + wci_5_reqPend == 2'd3) ; + assign MUX_wci_5_reqF_q_0$write_1__SEL_2 = + WILL_FIRE_RL_wci_5_reqF_incCtr && !wci_5_reqF_cntr_r ; + assign MUX_wci_5_reqPend$write_1__SEL_1 = + WILL_FIRE_RL_wci_5_wrkBusy && + wci_5_wciResponse$wget[33:32] != 2'd0 ; + assign MUX_wci_5_reqTO$write_1__SEL_1 = + WILL_FIRE_RL_wci_5_wrkBusy && + wci_5_wciResponse_wget__23_BITS_33_TO_32_24_EQ_ETC___d952 ; + assign MUX_wci_5_respF$enq_1__SEL_6 = + WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_F_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E5_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E5_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E5_F_F_T_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E5_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E5_F_F_T_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E5_F_F_T_T_T ; + assign MUX_wci_5_respF$enq_1__SEL_7 = + WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E5_T_F ; + assign MUX_wci_6_busy$write_1__SEL_1 = + WILL_FIRE_RL_wci_6_wrkBusy && + (!wci_6_respTimr_068_ULT_1_SL_wci_6_wTimeout_069_ETC___d1071 || + wci_6_wciResponse$wget[33:32] != 2'd0) ; + assign MUX_wci_6_busy$write_1__SEL_2 = + WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_F_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E6_T_T ; + assign MUX_wci_6_reqERR$write_1__SEL_1 = + WILL_FIRE_RL_wci_6_wrkBusy && + wci_6_wciResponse$wget[33:32] == 2'd3 && + (wci_6_reqPend == 2'd1 || wci_6_reqPend == 2'd2 || + wci_6_reqPend == 2'd3) ; + assign MUX_wci_6_reqFAIL$write_1__SEL_1 = + WILL_FIRE_RL_wci_6_wrkBusy && + wci_6_wciResponse$wget[33:32] == 2'd2 && + (wci_6_reqPend == 2'd1 || wci_6_reqPend == 2'd2 || + wci_6_reqPend == 2'd3) ; + assign MUX_wci_6_reqF_q_0$write_1__SEL_2 = + WILL_FIRE_RL_wci_6_reqF_incCtr && !wci_6_reqF_cntr_r ; + assign MUX_wci_6_reqPend$write_1__SEL_1 = + WILL_FIRE_RL_wci_6_wrkBusy && + wci_6_wciResponse$wget[33:32] != 2'd0 ; + assign MUX_wci_6_reqTO$write_1__SEL_1 = + WILL_FIRE_RL_wci_6_wrkBusy && + wci_6_wciResponse_wget__063_BITS_33_TO_32_064__ETC___d1092 ; + assign MUX_wci_6_respF$enq_1__SEL_6 = + WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_F_F_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E6_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E6_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E6_F_F_T_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E6_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E6_F_F_T_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E6_F_F_T_T_T ; + assign MUX_wci_6_respF$enq_1__SEL_7 = + WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_F_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E6_T_F ; + assign MUX_wci_7_busy$write_1__SEL_1 = + WILL_FIRE_RL_wci_7_wrkBusy && + (!wci_7_respTimr_208_ULT_1_SL_wci_7_wTimeout_209_ETC___d1211 || + wci_7_wciResponse$wget[33:32] != 2'd0) ; + assign MUX_wci_7_busy$write_1__SEL_2 = + WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E7_T_T ; + assign MUX_wci_7_reqERR$write_1__SEL_1 = + WILL_FIRE_RL_wci_7_wrkBusy && + wci_7_wciResponse$wget[33:32] == 2'd3 && + (wci_7_reqPend == 2'd1 || wci_7_reqPend == 2'd2 || + wci_7_reqPend == 2'd3) ; + assign MUX_wci_7_reqFAIL$write_1__SEL_1 = + WILL_FIRE_RL_wci_7_wrkBusy && + wci_7_wciResponse$wget[33:32] == 2'd2 && + (wci_7_reqPend == 2'd1 || wci_7_reqPend == 2'd2 || + wci_7_reqPend == 2'd3) ; + assign MUX_wci_7_reqF_q_0$write_1__SEL_2 = + WILL_FIRE_RL_wci_7_reqF_incCtr && !wci_7_reqF_cntr_r ; + assign MUX_wci_7_reqPend$write_1__SEL_1 = + WILL_FIRE_RL_wci_7_wrkBusy && + wci_7_wciResponse$wget[33:32] != 2'd0 ; + assign MUX_wci_7_reqTO$write_1__SEL_1 = + WILL_FIRE_RL_wci_7_wrkBusy && + wci_7_wciResponse_wget__203_BITS_33_TO_32_204__ETC___d1232 ; + assign MUX_wci_7_respF$enq_1__SEL_6 = + WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_F_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E7_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E7_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E7_F_F_T_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E7_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E7_F_F_T_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E7_F_F_T_T_T ; + assign MUX_wci_7_respF$enq_1__SEL_7 = + WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E7_T_F ; + assign MUX_wci_8_busy$write_1__SEL_1 = + WILL_FIRE_RL_wci_8_wrkBusy && + (!wci_8_respTimr_348_ULT_1_SL_wci_8_wTimeout_349_ETC___d1351 || + wci_8_wciResponse$wget[33:32] != 2'd0) ; + assign MUX_wci_8_busy$write_1__SEL_2 = + WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E8_T_T ; + assign MUX_wci_8_reqERR$write_1__SEL_1 = + WILL_FIRE_RL_wci_8_wrkBusy && + wci_8_wciResponse$wget[33:32] == 2'd3 && + (wci_8_reqPend == 2'd1 || wci_8_reqPend == 2'd2 || + wci_8_reqPend == 2'd3) ; + assign MUX_wci_8_reqFAIL$write_1__SEL_1 = + WILL_FIRE_RL_wci_8_wrkBusy && + wci_8_wciResponse$wget[33:32] == 2'd2 && + (wci_8_reqPend == 2'd1 || wci_8_reqPend == 2'd2 || + wci_8_reqPend == 2'd3) ; + assign MUX_wci_8_reqF_q_0$write_1__SEL_2 = + WILL_FIRE_RL_wci_8_reqF_incCtr && !wci_8_reqF_cntr_r ; + assign MUX_wci_8_reqPend$write_1__SEL_1 = + WILL_FIRE_RL_wci_8_wrkBusy && + wci_8_wciResponse$wget[33:32] != 2'd0 ; + assign MUX_wci_8_reqTO$write_1__SEL_1 = + WILL_FIRE_RL_wci_8_wrkBusy && + wci_8_wciResponse_wget__343_BITS_33_TO_32_344__ETC___d1372 ; + assign MUX_wci_8_respF$enq_1__SEL_6 = + WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_F_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E8_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E8_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E8_F_F_T_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E8_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E8_F_F_T_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E8_F_F_T_T_T ; + assign MUX_wci_8_respF$enq_1__SEL_7 = + WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E8_T_F ; + assign MUX_wci_9_busy$write_1__SEL_1 = + WILL_FIRE_RL_wci_9_wrkBusy && + (!wci_9_respTimr_488_ULT_1_SL_wci_9_wTimeout_489_ETC___d1491 || + wci_9_wciResponse$wget[33:32] != 2'd0) ; + assign MUX_wci_9_busy$write_1__SEL_2 = + WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_F_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E9_T_T ; + assign MUX_wci_9_reqERR$write_1__SEL_1 = + WILL_FIRE_RL_wci_9_wrkBusy && + wci_9_wciResponse$wget[33:32] == 2'd3 && + (wci_9_reqPend == 2'd1 || wci_9_reqPend == 2'd2 || + wci_9_reqPend == 2'd3) ; + assign MUX_wci_9_reqFAIL$write_1__SEL_1 = + WILL_FIRE_RL_wci_9_wrkBusy && + wci_9_wciResponse$wget[33:32] == 2'd2 && + (wci_9_reqPend == 2'd1 || wci_9_reqPend == 2'd2 || + wci_9_reqPend == 2'd3) ; + assign MUX_wci_9_reqF_q_0$write_1__SEL_2 = + WILL_FIRE_RL_wci_9_reqF_incCtr && !wci_9_reqF_cntr_r ; + assign MUX_wci_9_reqPend$write_1__SEL_1 = + WILL_FIRE_RL_wci_9_wrkBusy && + wci_9_wciResponse$wget[33:32] != 2'd0 ; + assign MUX_wci_9_reqTO$write_1__SEL_1 = + WILL_FIRE_RL_wci_9_wrkBusy && + wci_9_wciResponse_wget__483_BITS_33_TO_32_484__ETC___d1512 ; + assign MUX_wci_9_respF$enq_1__SEL_6 = + WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_F_F_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E9_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E9_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E9_F_F_T_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E9_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E9_F_F_T_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E9_F_F_T_T_T ; + assign MUX_wci_9_respF$enq_1__SEL_7 = + WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_F_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E9_T_F ; assign MUX_wrkAct$write_1__SEL_1 = - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_F_F_T_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_F_F_T_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_F_F_T_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_F_F_T_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_F_T_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_F_F_T_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_F_F_T_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_F_F_T_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_T_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_T_F_F_T_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_T_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_T_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_T_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_T_F_F_T_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_T_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_T_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_T_T_T ; + WILL_FIRE_RL_cpDispatch_F_F_T_OOB || + WILL_FIRE_RL_cpDispatch_F_F_T_E14_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E14_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E14_F_F_T_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E14_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E14_F_F_T_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E14_F_F_T_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E14_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E14_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E14_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E13_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E13_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E13_F_F_T_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E13_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E13_F_F_T_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E13_F_F_T_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E13_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E13_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E13_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E12_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E12_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E12_F_F_T_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E12_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E12_F_F_T_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E12_F_F_T_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E12_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E12_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E12_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E11_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E11_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E11_F_F_T_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E11_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E11_F_F_T_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E11_F_F_T_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E11_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E11_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E11_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E10_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E10_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E10_F_F_T_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E10_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E10_F_F_T_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E10_F_F_T_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E10_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E10_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E10_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E9_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E9_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E9_F_F_T_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E9_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E9_F_F_T_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E9_F_F_T_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E9_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E9_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E9_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E8_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E8_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E8_F_F_T_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E8_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E8_F_F_T_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E8_F_F_T_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E8_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E8_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E8_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E7_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E7_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E7_F_F_T_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E7_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E7_F_F_T_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E7_F_F_T_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E7_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E7_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E7_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E6_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E6_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E6_F_F_T_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E6_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E6_F_F_T_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E6_F_F_T_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E6_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E6_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E6_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E5_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E5_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E5_F_F_T_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E5_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E5_F_F_T_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E5_F_F_T_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E5_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E5_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E5_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E4_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E4_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E4_F_F_T_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E4_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E4_F_F_T_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E4_F_F_T_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E4_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E4_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E4_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E3_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E3_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E3_F_F_T_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E3_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E3_F_F_T_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E3_F_F_T_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E3_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E3_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E3_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E2_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E2_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E2_F_F_T_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E2_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E2_F_F_T_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E2_F_F_T_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E2_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E2_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E2_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E1_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E1_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E1_F_F_T_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E1_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E1_F_F_T_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E1_F_F_T_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E1_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E1_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E1_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E0_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E0_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E0_F_F_T_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E0_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E0_F_F_T_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E0_F_F_T_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E0_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E0_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E0_T_T ; assign MUX_wrkAct$write_1__SEL_2 = - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_F_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_F_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_F_F_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_F_F_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_F_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_F_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_F_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_F_F_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_F_F_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_F_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_F_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_F_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_F_F_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_F_F_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_F_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_F_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_F_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_T_F_F_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_T_F_F_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_T_F_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_T_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_T_F_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_T_F_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_T_T_T ; + WILL_FIRE_RL_cpDispatch_F_F_F_F_OOB || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_F_F_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_F_F_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_F_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_F_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_F_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_F_F_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_F_F_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_F_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_F_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_F_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_F_F_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_F_F_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_F_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_F_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_F_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_F_F_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_F_F_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_F_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_F_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_F_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_F_F_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_F_F_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_F_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_F_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_F_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_F_F_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_F_F_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_F_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_F_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_F_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_F_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_F_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_F_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_F_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_F_F_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_F_F_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_F_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_F_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_F_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_F_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_F_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_F_F_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_F_F_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_F_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_F_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_F_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_F_F_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_F_F_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_F_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_F_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_F_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_F_F_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_F_F_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_F_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_F_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_F_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_F_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_F_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_F_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_F_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_T_T ; assign MUX_wrkAct$write_1__SEL_3 = WILL_FIRE_RL_completeWorkerRead || WILL_FIRE_RL_completeWorkerWrite ; @@ -9426,16 +9330,16 @@ module mkOCCP(pciDevice, cpReq[11:4] == 8'h7C || cpReq[11:4] == 8'h80 || cpReq[11:4] == 8'h84, - IF_cpReq_337_BITS_11_TO_4_340_EQ_0x30_569_THEN_ETC___d6151 } ; + IF_cpReq_363_BITS_11_TO_4_366_EQ_0x30_595_THEN_ETC___d2691 } ; assign MUX_adminResp2F$enq_1__VAL_2 = { 1'd1, - IF_cpReq_337_BITS_11_TO_4_340_EQ_0x30_569_THEN_ETC___d6151 } ; + IF_cpReq_363_BITS_11_TO_4_366_EQ_0x30_595_THEN_ETC___d2691 } ; assign MUX_adminResp2F$enq_1__VAL_3 = { cpReq[11:4] == 8'h50 || cpReq[11:4] == 8'h54 || cpReq[11:4] == 8'h7C || cpReq[11:4] == 8'h80 || cpReq[11:4] == 8'h84, - IF_cpReq_337_BITS_11_TO_4_340_EQ_0x30_569_THEN_ETC___d6151 } ; + IF_cpReq_363_BITS_11_TO_4_366_EQ_0x30_595_THEN_ETC___d2691 } ; assign MUX_cpReq$write_1__VAL_4 = cpReqF$D_OUT[58] ? { (cpReqF$D_OUT[25:18] == 8'd0) ? 3'd2 : 3'd4, @@ -9444,1158 +9348,1162 @@ module mkOCCP(pciDevice, 2'd0 : ((cpReqF$D_OUT[25:22] == 4'd0) ? 2'd1 : 2'd2), cpReqF$D_OUT[33:26], - bAddr__h113364, + bAddr__h111449, cpReqF$D_OUT[3:0] } : { (cpReqF$D_OUT[57:50] == 8'd0) ? 5'd4 : ((cpReqF$D_OUT[57:54] == 4'd0) ? 5'd13 : 5'd14), cpReqF$D_OUT[31:0], - bAddr__h112904, + bAddr__h110990, cpReqF$D_OUT[35:32] } ; - assign MUX_cpRespF$enq_1__VAL_1 = { seqTag, crr_data__h75663 } ; - assign MUX_cpRespF$enq_1__VAL_2 = { cpReq[35:28], rtnData__h112395 } ; + assign MUX_cpRespF$enq_1__VAL_1 = { seqTag, crr_data__h75533 } ; + assign MUX_cpRespF$enq_1__VAL_2 = { cpReq[35:28], rtnData__h110501 } ; assign MUX_readCntReg$write_1__VAL_2 = readCntReg + 32'd1 ; - always@(wci_reqPend or wci_reqERR) + always@(wci_0_reqPend or wci_0_reqERR) begin - case (wci_reqPend) - 2'd1: MUX_wci_reqERR$write_1__VAL_1 = { 1'd1, wci_reqERR[1:0] }; + case (wci_0_reqPend) + 2'd1: MUX_wci_0_reqERR$write_1__VAL_1 = { 1'd1, wci_0_reqERR[1:0] }; 2'd2: - MUX_wci_reqERR$write_1__VAL_1 = - { wci_reqERR[2], 1'd1, wci_reqERR[0] }; - default: MUX_wci_reqERR$write_1__VAL_1 = { wci_reqERR[2:1], 1'd1 }; + MUX_wci_0_reqERR$write_1__VAL_1 = + { wci_0_reqERR[2], 1'd1, wci_0_reqERR[0] }; + default: MUX_wci_0_reqERR$write_1__VAL_1 = { wci_0_reqERR[2:1], 1'd1 }; endcase end - always@(wci_reqPend_1 or wci_reqERR_1) + always@(wci_0_reqPend or wci_0_reqFAIL) begin - case (wci_reqPend_1) - 2'd1: MUX_wci_reqERR_1$write_1__VAL_1 = { 1'd1, wci_reqERR_1[1:0] }; + case (wci_0_reqPend) + 2'd1: MUX_wci_0_reqFAIL$write_1__VAL_1 = { 1'd1, wci_0_reqFAIL[1:0] }; 2'd2: - MUX_wci_reqERR_1$write_1__VAL_1 = - { wci_reqERR_1[2], 1'd1, wci_reqERR_1[0] }; - default: MUX_wci_reqERR_1$write_1__VAL_1 = { wci_reqERR_1[2:1], 1'd1 }; + MUX_wci_0_reqFAIL$write_1__VAL_1 = + { wci_0_reqFAIL[2], 1'd1, wci_0_reqFAIL[0] }; + default: MUX_wci_0_reqFAIL$write_1__VAL_1 = + { wci_0_reqFAIL[2:1], 1'd1 }; endcase end - always@(wci_reqPend_10 or wci_reqERR_10) + assign MUX_wci_0_reqF_cntr_r$write_1__VAL_1 = wci_0_reqF_cntr_r + 1'd1 ; + assign MUX_wci_0_reqF_cntr_r$write_1__VAL_2 = wci_0_reqF_cntr_r - 1'd1 ; + assign MUX_wci_0_reqF_q_0$write_1__VAL_1 = + wci_0_reqF_cntr_r ? + MUX_wci_0_reqF_q_0$write_1__VAL_2 : + 72'h0000000000AAAAAAAA ; + always@(WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_T_T or + MUX_wci_0_reqF_x_wire$wset_1__VAL_1 or + WILL_FIRE_RL_cpDispatch_F_F_T_E0_T_T or + MUX_wci_0_reqF_x_wire$wset_1__VAL_2 or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_T_T or + MUX_wci_0_reqF_x_wire$wset_1__VAL_3) begin - case (wci_reqPend_10) - 2'd1: MUX_wci_reqERR_10$write_1__VAL_1 = { 1'd1, wci_reqERR_10[1:0] }; - 2'd2: - MUX_wci_reqERR_10$write_1__VAL_1 = - { wci_reqERR_10[2], 1'd1, wci_reqERR_10[0] }; - default: MUX_wci_reqERR_10$write_1__VAL_1 = - { wci_reqERR_10[2:1], 1'd1 }; + case (1'b1) // synopsys parallel_case + WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_T_T: + MUX_wci_0_reqF_q_0$write_1__VAL_2 = + MUX_wci_0_reqF_x_wire$wset_1__VAL_1; + WILL_FIRE_RL_cpDispatch_F_F_T_E0_T_T: + MUX_wci_0_reqF_q_0$write_1__VAL_2 = + MUX_wci_0_reqF_x_wire$wset_1__VAL_2; + WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_T_T: + MUX_wci_0_reqF_q_0$write_1__VAL_2 = + MUX_wci_0_reqF_x_wire$wset_1__VAL_3; + default: MUX_wci_0_reqF_q_0$write_1__VAL_2 = + 72'hAAAAAAAAAAAAAAAAAA /* unspecified value */ ; endcase end - always@(wci_reqPend_11 or wci_reqERR_11) + assign MUX_wci_0_reqF_x_wire$wset_1__VAL_1 = + { 8'd79, x_addr__h96606, 32'hAAAAAAAA } ; + assign MUX_wci_0_reqF_x_wire$wset_1__VAL_2 = + { 4'd3, cpReq[3:0], wciAddr__h77037, cpReq[59:28] } ; + assign MUX_wci_0_reqF_x_wire$wset_1__VAL_3 = + { 4'd5, cpReq[3:0], wciAddr__h77037, 32'hAAAAAAAA } ; + always@(wci_0_reqPend or wci_0_reqTO) begin - case (wci_reqPend_11) - 2'd1: MUX_wci_reqERR_11$write_1__VAL_1 = { 1'd1, wci_reqERR_11[1:0] }; + case (wci_0_reqPend) + 2'd1: MUX_wci_0_reqTO$write_1__VAL_1 = { 1'd1, wci_0_reqTO[1:0] }; 2'd2: - MUX_wci_reqERR_11$write_1__VAL_1 = - { wci_reqERR_11[2], 1'd1, wci_reqERR_11[0] }; - default: MUX_wci_reqERR_11$write_1__VAL_1 = - { wci_reqERR_11[2:1], 1'd1 }; + MUX_wci_0_reqTO$write_1__VAL_1 = + { wci_0_reqTO[2], 1'd1, wci_0_reqTO[0] }; + default: MUX_wci_0_reqTO$write_1__VAL_1 = { wci_0_reqTO[2:1], 1'd1 }; endcase end - always@(wci_reqPend_12 or wci_reqERR_12) + assign MUX_wci_0_respF$enq_1__VAL_1 = + (wci_0_wciResponse$wget[33:32] == 2'd0) ? + 34'h1C0DE4203 : + wci_0_wciResponse$wget ; + assign MUX_wci_0_respF$enq_1__VAL_2 = { 2'd1, wci_0_wStatus } ; + assign MUX_wci_0_respF$enq_1__VAL_3 = { 2'd1, x_data__h102795 } ; + assign MUX_wci_0_respF$enq_1__VAL_4 = { 2'd1, x_data__h102801 } ; + assign MUX_wci_0_respF$enq_1__VAL_5 = { 22'd1048576, wci_0_pageWindow } ; + assign MUX_wci_0_respTimr$write_1__VAL_2 = + (wci_0_wciResponse$wget[33:32] == 2'd0) ? + (wci_0_respTimr_28_ULT_1_SL_wci_0_wTimeout_29_30___d231 ? + x__h11852 : + 32'd0) : + 32'd0 ; + always@(wci_10_reqPend or wci_10_reqERR) begin - case (wci_reqPend_12) - 2'd1: MUX_wci_reqERR_12$write_1__VAL_1 = { 1'd1, wci_reqERR_12[1:0] }; + case (wci_10_reqPend) + 2'd1: MUX_wci_10_reqERR$write_1__VAL_1 = { 1'd1, wci_10_reqERR[1:0] }; 2'd2: - MUX_wci_reqERR_12$write_1__VAL_1 = - { wci_reqERR_12[2], 1'd1, wci_reqERR_12[0] }; - default: MUX_wci_reqERR_12$write_1__VAL_1 = - { wci_reqERR_12[2:1], 1'd1 }; + MUX_wci_10_reqERR$write_1__VAL_1 = + { wci_10_reqERR[2], 1'd1, wci_10_reqERR[0] }; + default: MUX_wci_10_reqERR$write_1__VAL_1 = + { wci_10_reqERR[2:1], 1'd1 }; endcase end - always@(wci_reqPend_13 or wci_reqERR_13) + always@(wci_10_reqPend or wci_10_reqFAIL) begin - case (wci_reqPend_13) - 2'd1: MUX_wci_reqERR_13$write_1__VAL_1 = { 1'd1, wci_reqERR_13[1:0] }; + case (wci_10_reqPend) + 2'd1: MUX_wci_10_reqFAIL$write_1__VAL_1 = { 1'd1, wci_10_reqFAIL[1:0] }; 2'd2: - MUX_wci_reqERR_13$write_1__VAL_1 = - { wci_reqERR_13[2], 1'd1, wci_reqERR_13[0] }; - default: MUX_wci_reqERR_13$write_1__VAL_1 = - { wci_reqERR_13[2:1], 1'd1 }; + MUX_wci_10_reqFAIL$write_1__VAL_1 = + { wci_10_reqFAIL[2], 1'd1, wci_10_reqFAIL[0] }; + default: MUX_wci_10_reqFAIL$write_1__VAL_1 = + { wci_10_reqFAIL[2:1], 1'd1 }; endcase end - always@(wci_reqPend_14 or wci_reqERR_14) + assign MUX_wci_10_reqF_cntr_r$write_1__VAL_1 = wci_10_reqF_cntr_r + 1'd1 ; + assign MUX_wci_10_reqF_cntr_r$write_1__VAL_2 = wci_10_reqF_cntr_r - 1'd1 ; + always@(WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_F_T_T or + MUX_wci_0_reqF_x_wire$wset_1__VAL_1 or + WILL_FIRE_RL_cpDispatch_F_F_T_E10_T_T or + MUX_wci_10_reqF_x_wire$wset_1__VAL_2 or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_T_T or + MUX_wci_10_reqF_x_wire$wset_1__VAL_3) begin - case (wci_reqPend_14) - 2'd1: MUX_wci_reqERR_14$write_1__VAL_1 = { 1'd1, wci_reqERR_14[1:0] }; - 2'd2: - MUX_wci_reqERR_14$write_1__VAL_1 = - { wci_reqERR_14[2], 1'd1, wci_reqERR_14[0] }; - default: MUX_wci_reqERR_14$write_1__VAL_1 = - { wci_reqERR_14[2:1], 1'd1 }; + case (1'b1) // synopsys parallel_case + WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_F_T_T: + MUX_wci_10_reqF_q_0$write_1__VAL_1 = + MUX_wci_0_reqF_x_wire$wset_1__VAL_1; + WILL_FIRE_RL_cpDispatch_F_F_T_E10_T_T: + MUX_wci_10_reqF_q_0$write_1__VAL_1 = + MUX_wci_10_reqF_x_wire$wset_1__VAL_2; + WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_T_T: + MUX_wci_10_reqF_q_0$write_1__VAL_1 = + MUX_wci_10_reqF_x_wire$wset_1__VAL_3; + default: MUX_wci_10_reqF_q_0$write_1__VAL_1 = + 72'hAAAAAAAAAAAAAAAAAA /* unspecified value */ ; endcase end - always@(wci_reqPend_2 or wci_reqERR_2) + assign MUX_wci_10_reqF_q_0$write_1__VAL_2 = + wci_10_reqF_cntr_r ? + MUX_wci_10_reqF_q_0$write_1__VAL_1 : + 72'h0000000000AAAAAAAA ; + assign MUX_wci_10_reqF_x_wire$wset_1__VAL_2 = + { 4'd3, cpReq[3:0], wciAddr__h77717, cpReq[59:28] } ; + assign MUX_wci_10_reqF_x_wire$wset_1__VAL_3 = + { 4'd5, cpReq[3:0], wciAddr__h77717, 32'hAAAAAAAA } ; + always@(wci_10_reqPend or wci_10_reqTO) begin - case (wci_reqPend_2) - 2'd1: MUX_wci_reqERR_2$write_1__VAL_1 = { 1'd1, wci_reqERR_2[1:0] }; + case (wci_10_reqPend) + 2'd1: MUX_wci_10_reqTO$write_1__VAL_1 = { 1'd1, wci_10_reqTO[1:0] }; 2'd2: - MUX_wci_reqERR_2$write_1__VAL_1 = - { wci_reqERR_2[2], 1'd1, wci_reqERR_2[0] }; - default: MUX_wci_reqERR_2$write_1__VAL_1 = { wci_reqERR_2[2:1], 1'd1 }; + MUX_wci_10_reqTO$write_1__VAL_1 = + { wci_10_reqTO[2], 1'd1, wci_10_reqTO[0] }; + default: MUX_wci_10_reqTO$write_1__VAL_1 = { wci_10_reqTO[2:1], 1'd1 }; endcase end - always@(wci_reqPend_3 or wci_reqERR_3) + assign MUX_wci_10_respF$enq_1__VAL_1 = + (wci_10_wciResponse$wget[33:32] == 2'd0) ? + 34'h1C0DE4203 : + wci_10_wciResponse$wget ; + assign MUX_wci_10_respF$enq_1__VAL_2 = { 2'd1, wci_10_wStatus } ; + assign MUX_wci_10_respF$enq_1__VAL_3 = { 2'd1, x_data__h103305 } ; + assign MUX_wci_10_respF$enq_1__VAL_4 = { 2'd1, x_data__h103311 } ; + assign MUX_wci_10_respF$enq_1__VAL_5 = { 22'd1048576, wci_10_pageWindow } ; + assign MUX_wci_10_respTimr$write_1__VAL_2 = + (wci_10_wciResponse$wget[33:32] == 2'd0) ? + (wci_10_respTimr_628_ULT_1_SL_wci_10_wTimeout_6_ETC___d1631 ? + x__h55545 : + 32'd0) : + 32'd0 ; + always@(wci_11_reqPend or wci_11_reqERR) begin - case (wci_reqPend_3) - 2'd1: MUX_wci_reqERR_3$write_1__VAL_1 = { 1'd1, wci_reqERR_3[1:0] }; + case (wci_11_reqPend) + 2'd1: MUX_wci_11_reqERR$write_1__VAL_1 = { 1'd1, wci_11_reqERR[1:0] }; 2'd2: - MUX_wci_reqERR_3$write_1__VAL_1 = - { wci_reqERR_3[2], 1'd1, wci_reqERR_3[0] }; - default: MUX_wci_reqERR_3$write_1__VAL_1 = { wci_reqERR_3[2:1], 1'd1 }; + MUX_wci_11_reqERR$write_1__VAL_1 = + { wci_11_reqERR[2], 1'd1, wci_11_reqERR[0] }; + default: MUX_wci_11_reqERR$write_1__VAL_1 = + { wci_11_reqERR[2:1], 1'd1 }; endcase end - always@(wci_reqPend_4 or wci_reqERR_4) + always@(wci_11_reqPend or wci_11_reqFAIL) begin - case (wci_reqPend_4) - 2'd1: MUX_wci_reqERR_4$write_1__VAL_1 = { 1'd1, wci_reqERR_4[1:0] }; + case (wci_11_reqPend) + 2'd1: MUX_wci_11_reqFAIL$write_1__VAL_1 = { 1'd1, wci_11_reqFAIL[1:0] }; 2'd2: - MUX_wci_reqERR_4$write_1__VAL_1 = - { wci_reqERR_4[2], 1'd1, wci_reqERR_4[0] }; - default: MUX_wci_reqERR_4$write_1__VAL_1 = { wci_reqERR_4[2:1], 1'd1 }; + MUX_wci_11_reqFAIL$write_1__VAL_1 = + { wci_11_reqFAIL[2], 1'd1, wci_11_reqFAIL[0] }; + default: MUX_wci_11_reqFAIL$write_1__VAL_1 = + { wci_11_reqFAIL[2:1], 1'd1 }; endcase end - always@(wci_reqPend_5 or wci_reqERR_5) + assign MUX_wci_11_reqF_cntr_r$write_1__VAL_1 = wci_11_reqF_cntr_r + 1'd1 ; + assign MUX_wci_11_reqF_cntr_r$write_1__VAL_2 = wci_11_reqF_cntr_r - 1'd1 ; + always@(WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_F_T_T or + MUX_wci_0_reqF_x_wire$wset_1__VAL_1 or + WILL_FIRE_RL_cpDispatch_F_F_T_E11_T_T or + MUX_wci_11_reqF_x_wire$wset_1__VAL_2 or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_T_T or + MUX_wci_11_reqF_x_wire$wset_1__VAL_3) begin - case (wci_reqPend_5) - 2'd1: MUX_wci_reqERR_5$write_1__VAL_1 = { 1'd1, wci_reqERR_5[1:0] }; - 2'd2: - MUX_wci_reqERR_5$write_1__VAL_1 = - { wci_reqERR_5[2], 1'd1, wci_reqERR_5[0] }; - default: MUX_wci_reqERR_5$write_1__VAL_1 = { wci_reqERR_5[2:1], 1'd1 }; + case (1'b1) // synopsys parallel_case + WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_F_T_T: + MUX_wci_11_reqF_q_0$write_1__VAL_1 = + MUX_wci_0_reqF_x_wire$wset_1__VAL_1; + WILL_FIRE_RL_cpDispatch_F_F_T_E11_T_T: + MUX_wci_11_reqF_q_0$write_1__VAL_1 = + MUX_wci_11_reqF_x_wire$wset_1__VAL_2; + WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_T_T: + MUX_wci_11_reqF_q_0$write_1__VAL_1 = + MUX_wci_11_reqF_x_wire$wset_1__VAL_3; + default: MUX_wci_11_reqF_q_0$write_1__VAL_1 = + 72'hAAAAAAAAAAAAAAAAAA /* unspecified value */ ; endcase end - always@(wci_reqPend_6 or wci_reqERR_6) + assign MUX_wci_11_reqF_q_0$write_1__VAL_2 = + wci_11_reqF_cntr_r ? + MUX_wci_11_reqF_q_0$write_1__VAL_1 : + 72'h0000000000AAAAAAAA ; + assign MUX_wci_11_reqF_x_wire$wset_1__VAL_2 = + { 4'd3, cpReq[3:0], wciAddr__h77785, cpReq[59:28] } ; + assign MUX_wci_11_reqF_x_wire$wset_1__VAL_3 = + { 4'd5, cpReq[3:0], wciAddr__h77785, 32'hAAAAAAAA } ; + always@(wci_11_reqPend or wci_11_reqTO) begin - case (wci_reqPend_6) - 2'd1: MUX_wci_reqERR_6$write_1__VAL_1 = { 1'd1, wci_reqERR_6[1:0] }; + case (wci_11_reqPend) + 2'd1: MUX_wci_11_reqTO$write_1__VAL_1 = { 1'd1, wci_11_reqTO[1:0] }; 2'd2: - MUX_wci_reqERR_6$write_1__VAL_1 = - { wci_reqERR_6[2], 1'd1, wci_reqERR_6[0] }; - default: MUX_wci_reqERR_6$write_1__VAL_1 = { wci_reqERR_6[2:1], 1'd1 }; + MUX_wci_11_reqTO$write_1__VAL_1 = + { wci_11_reqTO[2], 1'd1, wci_11_reqTO[0] }; + default: MUX_wci_11_reqTO$write_1__VAL_1 = { wci_11_reqTO[2:1], 1'd1 }; endcase end - always@(wci_reqPend_7 or wci_reqERR_7) + assign MUX_wci_11_respF$enq_1__VAL_1 = + (wci_11_wciResponse$wget[33:32] == 2'd0) ? + 34'h1C0DE4203 : + wci_11_wciResponse$wget ; + assign MUX_wci_11_respF$enq_1__VAL_2 = { 2'd1, wci_11_wStatus } ; + assign MUX_wci_11_respF$enq_1__VAL_3 = { 2'd1, x_data__h103356 } ; + assign MUX_wci_11_respF$enq_1__VAL_4 = { 2'd1, x_data__h103362 } ; + assign MUX_wci_11_respF$enq_1__VAL_5 = { 22'd1048576, wci_11_pageWindow } ; + assign MUX_wci_11_respTimr$write_1__VAL_2 = + (wci_11_wciResponse$wget[33:32] == 2'd0) ? + (wci_11_respTimr_768_ULT_1_SL_wci_11_wTimeout_7_ETC___d1771 ? + x__h59914 : + 32'd0) : + 32'd0 ; + always@(wci_12_reqPend or wci_12_reqERR) begin - case (wci_reqPend_7) - 2'd1: MUX_wci_reqERR_7$write_1__VAL_1 = { 1'd1, wci_reqERR_7[1:0] }; + case (wci_12_reqPend) + 2'd1: MUX_wci_12_reqERR$write_1__VAL_1 = { 1'd1, wci_12_reqERR[1:0] }; 2'd2: - MUX_wci_reqERR_7$write_1__VAL_1 = - { wci_reqERR_7[2], 1'd1, wci_reqERR_7[0] }; - default: MUX_wci_reqERR_7$write_1__VAL_1 = { wci_reqERR_7[2:1], 1'd1 }; + MUX_wci_12_reqERR$write_1__VAL_1 = + { wci_12_reqERR[2], 1'd1, wci_12_reqERR[0] }; + default: MUX_wci_12_reqERR$write_1__VAL_1 = + { wci_12_reqERR[2:1], 1'd1 }; endcase end - always@(wci_reqPend_8 or wci_reqERR_8) + always@(wci_12_reqPend or wci_12_reqFAIL) begin - case (wci_reqPend_8) - 2'd1: MUX_wci_reqERR_8$write_1__VAL_1 = { 1'd1, wci_reqERR_8[1:0] }; + case (wci_12_reqPend) + 2'd1: MUX_wci_12_reqFAIL$write_1__VAL_1 = { 1'd1, wci_12_reqFAIL[1:0] }; 2'd2: - MUX_wci_reqERR_8$write_1__VAL_1 = - { wci_reqERR_8[2], 1'd1, wci_reqERR_8[0] }; - default: MUX_wci_reqERR_8$write_1__VAL_1 = { wci_reqERR_8[2:1], 1'd1 }; + MUX_wci_12_reqFAIL$write_1__VAL_1 = + { wci_12_reqFAIL[2], 1'd1, wci_12_reqFAIL[0] }; + default: MUX_wci_12_reqFAIL$write_1__VAL_1 = + { wci_12_reqFAIL[2:1], 1'd1 }; endcase end - always@(wci_reqPend_9 or wci_reqERR_9) + assign MUX_wci_12_reqF_cntr_r$write_1__VAL_1 = wci_12_reqF_cntr_r + 1'd1 ; + assign MUX_wci_12_reqF_cntr_r$write_1__VAL_2 = wci_12_reqF_cntr_r - 1'd1 ; + always@(WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_F_T_T or + MUX_wci_0_reqF_x_wire$wset_1__VAL_1 or + WILL_FIRE_RL_cpDispatch_F_F_T_E12_T_T or + MUX_wci_12_reqF_x_wire$wset_1__VAL_2 or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_T_T or + MUX_wci_12_reqF_x_wire$wset_1__VAL_3) begin - case (wci_reqPend_9) - 2'd1: MUX_wci_reqERR_9$write_1__VAL_1 = { 1'd1, wci_reqERR_9[1:0] }; - 2'd2: - MUX_wci_reqERR_9$write_1__VAL_1 = - { wci_reqERR_9[2], 1'd1, wci_reqERR_9[0] }; - default: MUX_wci_reqERR_9$write_1__VAL_1 = { wci_reqERR_9[2:1], 1'd1 }; + case (1'b1) // synopsys parallel_case + WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_F_T_T: + MUX_wci_12_reqF_q_0$write_1__VAL_1 = + MUX_wci_0_reqF_x_wire$wset_1__VAL_1; + WILL_FIRE_RL_cpDispatch_F_F_T_E12_T_T: + MUX_wci_12_reqF_q_0$write_1__VAL_1 = + MUX_wci_12_reqF_x_wire$wset_1__VAL_2; + WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_T_T: + MUX_wci_12_reqF_q_0$write_1__VAL_1 = + MUX_wci_12_reqF_x_wire$wset_1__VAL_3; + default: MUX_wci_12_reqF_q_0$write_1__VAL_1 = + 72'hAAAAAAAAAAAAAAAAAA /* unspecified value */ ; endcase end - always@(wci_reqPend or wci_reqFAIL) + assign MUX_wci_12_reqF_q_0$write_1__VAL_2 = + wci_12_reqF_cntr_r ? + MUX_wci_12_reqF_q_0$write_1__VAL_1 : + 72'h0000000000AAAAAAAA ; + assign MUX_wci_12_reqF_x_wire$wset_1__VAL_2 = + { 4'd3, cpReq[3:0], wciAddr__h77853, cpReq[59:28] } ; + assign MUX_wci_12_reqF_x_wire$wset_1__VAL_3 = + { 4'd5, cpReq[3:0], wciAddr__h77853, 32'hAAAAAAAA } ; + always@(wci_12_reqPend or wci_12_reqTO) begin - case (wci_reqPend) - 2'd1: MUX_wci_reqFAIL$write_1__VAL_1 = { 1'd1, wci_reqFAIL[1:0] }; + case (wci_12_reqPend) + 2'd1: MUX_wci_12_reqTO$write_1__VAL_1 = { 1'd1, wci_12_reqTO[1:0] }; 2'd2: - MUX_wci_reqFAIL$write_1__VAL_1 = - { wci_reqFAIL[2], 1'd1, wci_reqFAIL[0] }; - default: MUX_wci_reqFAIL$write_1__VAL_1 = { wci_reqFAIL[2:1], 1'd1 }; + MUX_wci_12_reqTO$write_1__VAL_1 = + { wci_12_reqTO[2], 1'd1, wci_12_reqTO[0] }; + default: MUX_wci_12_reqTO$write_1__VAL_1 = { wci_12_reqTO[2:1], 1'd1 }; endcase end - always@(wci_reqPend_1 or wci_reqFAIL_1) + assign MUX_wci_12_respF$enq_1__VAL_1 = + (wci_12_wciResponse$wget[33:32] == 2'd0) ? + 34'h1C0DE4203 : + wci_12_wciResponse$wget ; + assign MUX_wci_12_respF$enq_1__VAL_2 = { 2'd1, wci_12_wStatus } ; + assign MUX_wci_12_respF$enq_1__VAL_3 = { 2'd1, x_data__h103407 } ; + assign MUX_wci_12_respF$enq_1__VAL_4 = { 2'd1, x_data__h103413 } ; + assign MUX_wci_12_respF$enq_1__VAL_5 = { 22'd1048576, wci_12_pageWindow } ; + assign MUX_wci_12_respTimr$write_1__VAL_2 = + (wci_12_wciResponse$wget[33:32] == 2'd0) ? + (wci_12_respTimr_908_ULT_1_SL_wci_12_wTimeout_9_ETC___d1911 ? + x__h64283 : + 32'd0) : + 32'd0 ; + always@(wci_13_reqPend or wci_13_reqERR) begin - case (wci_reqPend_1) - 2'd1: MUX_wci_reqFAIL_1$write_1__VAL_1 = { 1'd1, wci_reqFAIL_1[1:0] }; + case (wci_13_reqPend) + 2'd1: MUX_wci_13_reqERR$write_1__VAL_1 = { 1'd1, wci_13_reqERR[1:0] }; 2'd2: - MUX_wci_reqFAIL_1$write_1__VAL_1 = - { wci_reqFAIL_1[2], 1'd1, wci_reqFAIL_1[0] }; - default: MUX_wci_reqFAIL_1$write_1__VAL_1 = - { wci_reqFAIL_1[2:1], 1'd1 }; + MUX_wci_13_reqERR$write_1__VAL_1 = + { wci_13_reqERR[2], 1'd1, wci_13_reqERR[0] }; + default: MUX_wci_13_reqERR$write_1__VAL_1 = + { wci_13_reqERR[2:1], 1'd1 }; endcase end - always@(wci_reqPend_10 or wci_reqFAIL_10) + always@(wci_13_reqPend or wci_13_reqFAIL) begin - case (wci_reqPend_10) - 2'd1: MUX_wci_reqFAIL_10$write_1__VAL_1 = { 1'd1, wci_reqFAIL_10[1:0] }; + case (wci_13_reqPend) + 2'd1: MUX_wci_13_reqFAIL$write_1__VAL_1 = { 1'd1, wci_13_reqFAIL[1:0] }; 2'd2: - MUX_wci_reqFAIL_10$write_1__VAL_1 = - { wci_reqFAIL_10[2], 1'd1, wci_reqFAIL_10[0] }; - default: MUX_wci_reqFAIL_10$write_1__VAL_1 = - { wci_reqFAIL_10[2:1], 1'd1 }; + MUX_wci_13_reqFAIL$write_1__VAL_1 = + { wci_13_reqFAIL[2], 1'd1, wci_13_reqFAIL[0] }; + default: MUX_wci_13_reqFAIL$write_1__VAL_1 = + { wci_13_reqFAIL[2:1], 1'd1 }; endcase end - always@(wci_reqPend_11 or wci_reqFAIL_11) + assign MUX_wci_13_reqF_cntr_r$write_1__VAL_1 = wci_13_reqF_cntr_r + 1'd1 ; + assign MUX_wci_13_reqF_cntr_r$write_1__VAL_2 = wci_13_reqF_cntr_r - 1'd1 ; + always@(WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_F_T_T or + MUX_wci_0_reqF_x_wire$wset_1__VAL_1 or + WILL_FIRE_RL_cpDispatch_F_F_T_E13_T_T or + MUX_wci_13_reqF_x_wire$wset_1__VAL_2 or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_T_T or + MUX_wci_13_reqF_x_wire$wset_1__VAL_3) begin - case (wci_reqPend_11) - 2'd1: MUX_wci_reqFAIL_11$write_1__VAL_1 = { 1'd1, wci_reqFAIL_11[1:0] }; - 2'd2: - MUX_wci_reqFAIL_11$write_1__VAL_1 = - { wci_reqFAIL_11[2], 1'd1, wci_reqFAIL_11[0] }; - default: MUX_wci_reqFAIL_11$write_1__VAL_1 = - { wci_reqFAIL_11[2:1], 1'd1 }; + case (1'b1) // synopsys parallel_case + WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_F_T_T: + MUX_wci_13_reqF_q_0$write_1__VAL_1 = + MUX_wci_0_reqF_x_wire$wset_1__VAL_1; + WILL_FIRE_RL_cpDispatch_F_F_T_E13_T_T: + MUX_wci_13_reqF_q_0$write_1__VAL_1 = + MUX_wci_13_reqF_x_wire$wset_1__VAL_2; + WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_T_T: + MUX_wci_13_reqF_q_0$write_1__VAL_1 = + MUX_wci_13_reqF_x_wire$wset_1__VAL_3; + default: MUX_wci_13_reqF_q_0$write_1__VAL_1 = + 72'hAAAAAAAAAAAAAAAAAA /* unspecified value */ ; endcase end - always@(wci_reqPend_12 or wci_reqFAIL_12) + assign MUX_wci_13_reqF_q_0$write_1__VAL_2 = + wci_13_reqF_cntr_r ? + MUX_wci_13_reqF_q_0$write_1__VAL_1 : + 72'h0000000000AAAAAAAA ; + assign MUX_wci_13_reqF_x_wire$wset_1__VAL_2 = + { 4'd3, cpReq[3:0], wciAddr__h77921, cpReq[59:28] } ; + assign MUX_wci_13_reqF_x_wire$wset_1__VAL_3 = + { 4'd5, cpReq[3:0], wciAddr__h77921, 32'hAAAAAAAA } ; + always@(wci_13_reqPend or wci_13_reqTO) begin - case (wci_reqPend_12) - 2'd1: MUX_wci_reqFAIL_12$write_1__VAL_1 = { 1'd1, wci_reqFAIL_12[1:0] }; + case (wci_13_reqPend) + 2'd1: MUX_wci_13_reqTO$write_1__VAL_1 = { 1'd1, wci_13_reqTO[1:0] }; 2'd2: - MUX_wci_reqFAIL_12$write_1__VAL_1 = - { wci_reqFAIL_12[2], 1'd1, wci_reqFAIL_12[0] }; - default: MUX_wci_reqFAIL_12$write_1__VAL_1 = - { wci_reqFAIL_12[2:1], 1'd1 }; + MUX_wci_13_reqTO$write_1__VAL_1 = + { wci_13_reqTO[2], 1'd1, wci_13_reqTO[0] }; + default: MUX_wci_13_reqTO$write_1__VAL_1 = { wci_13_reqTO[2:1], 1'd1 }; endcase end - always@(wci_reqPend_13 or wci_reqFAIL_13) + assign MUX_wci_13_respF$enq_1__VAL_1 = + (wci_13_wciResponse$wget[33:32] == 2'd0) ? + 34'h1C0DE4203 : + wci_13_wciResponse$wget ; + assign MUX_wci_13_respF$enq_1__VAL_2 = { 2'd1, wci_13_wStatus } ; + assign MUX_wci_13_respF$enq_1__VAL_3 = { 2'd1, x_data__h103458 } ; + assign MUX_wci_13_respF$enq_1__VAL_4 = { 2'd1, x_data__h103464 } ; + assign MUX_wci_13_respF$enq_1__VAL_5 = { 22'd1048576, wci_13_pageWindow } ; + assign MUX_wci_13_respTimr$write_1__VAL_2 = + (wci_13_wciResponse$wget[33:32] == 2'd0) ? + (wci_13_respTimr_048_ULT_1_SL_wci_13_wTimeout_0_ETC___d2051 ? + x__h68652 : + 32'd0) : + 32'd0 ; + always@(wci_14_reqPend or wci_14_reqERR) begin - case (wci_reqPend_13) - 2'd1: MUX_wci_reqFAIL_13$write_1__VAL_1 = { 1'd1, wci_reqFAIL_13[1:0] }; + case (wci_14_reqPend) + 2'd1: MUX_wci_14_reqERR$write_1__VAL_1 = { 1'd1, wci_14_reqERR[1:0] }; 2'd2: - MUX_wci_reqFAIL_13$write_1__VAL_1 = - { wci_reqFAIL_13[2], 1'd1, wci_reqFAIL_13[0] }; - default: MUX_wci_reqFAIL_13$write_1__VAL_1 = - { wci_reqFAIL_13[2:1], 1'd1 }; + MUX_wci_14_reqERR$write_1__VAL_1 = + { wci_14_reqERR[2], 1'd1, wci_14_reqERR[0] }; + default: MUX_wci_14_reqERR$write_1__VAL_1 = + { wci_14_reqERR[2:1], 1'd1 }; endcase end - always@(wci_reqPend_14 or wci_reqFAIL_14) + always@(wci_14_reqPend or wci_14_reqFAIL) begin - case (wci_reqPend_14) - 2'd1: MUX_wci_reqFAIL_14$write_1__VAL_1 = { 1'd1, wci_reqFAIL_14[1:0] }; + case (wci_14_reqPend) + 2'd1: MUX_wci_14_reqFAIL$write_1__VAL_1 = { 1'd1, wci_14_reqFAIL[1:0] }; 2'd2: - MUX_wci_reqFAIL_14$write_1__VAL_1 = - { wci_reqFAIL_14[2], 1'd1, wci_reqFAIL_14[0] }; - default: MUX_wci_reqFAIL_14$write_1__VAL_1 = - { wci_reqFAIL_14[2:1], 1'd1 }; + MUX_wci_14_reqFAIL$write_1__VAL_1 = + { wci_14_reqFAIL[2], 1'd1, wci_14_reqFAIL[0] }; + default: MUX_wci_14_reqFAIL$write_1__VAL_1 = + { wci_14_reqFAIL[2:1], 1'd1 }; endcase end - always@(wci_reqPend_2 or wci_reqFAIL_2) + assign MUX_wci_14_reqF_cntr_r$write_1__VAL_1 = wci_14_reqF_cntr_r + 1'd1 ; + assign MUX_wci_14_reqF_cntr_r$write_1__VAL_2 = wci_14_reqF_cntr_r - 1'd1 ; + always@(WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_F_T_T or + MUX_wci_0_reqF_x_wire$wset_1__VAL_1 or + WILL_FIRE_RL_cpDispatch_F_F_T_E14_T_T or + MUX_wci_14_reqF_x_wire$wset_1__VAL_2 or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_T_T or + MUX_wci_14_reqF_x_wire$wset_1__VAL_3) begin - case (wci_reqPend_2) - 2'd1: MUX_wci_reqFAIL_2$write_1__VAL_1 = { 1'd1, wci_reqFAIL_2[1:0] }; - 2'd2: - MUX_wci_reqFAIL_2$write_1__VAL_1 = - { wci_reqFAIL_2[2], 1'd1, wci_reqFAIL_2[0] }; - default: MUX_wci_reqFAIL_2$write_1__VAL_1 = - { wci_reqFAIL_2[2:1], 1'd1 }; + case (1'b1) // synopsys parallel_case + WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_F_T_T: + MUX_wci_14_reqF_q_0$write_1__VAL_1 = + MUX_wci_0_reqF_x_wire$wset_1__VAL_1; + WILL_FIRE_RL_cpDispatch_F_F_T_E14_T_T: + MUX_wci_14_reqF_q_0$write_1__VAL_1 = + MUX_wci_14_reqF_x_wire$wset_1__VAL_2; + WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_T_T: + MUX_wci_14_reqF_q_0$write_1__VAL_1 = + MUX_wci_14_reqF_x_wire$wset_1__VAL_3; + default: MUX_wci_14_reqF_q_0$write_1__VAL_1 = + 72'hAAAAAAAAAAAAAAAAAA /* unspecified value */ ; endcase end - always@(wci_reqPend_3 or wci_reqFAIL_3) + assign MUX_wci_14_reqF_q_0$write_1__VAL_2 = + wci_14_reqF_cntr_r ? + MUX_wci_14_reqF_q_0$write_1__VAL_1 : + 72'h0000000000AAAAAAAA ; + assign MUX_wci_14_reqF_x_wire$wset_1__VAL_2 = + { 4'd3, cpReq[3:0], wciAddr__h77989, cpReq[59:28] } ; + assign MUX_wci_14_reqF_x_wire$wset_1__VAL_3 = + { 4'd5, cpReq[3:0], wciAddr__h77989, 32'hAAAAAAAA } ; + always@(wci_14_reqPend or wci_14_reqTO) begin - case (wci_reqPend_3) - 2'd1: MUX_wci_reqFAIL_3$write_1__VAL_1 = { 1'd1, wci_reqFAIL_3[1:0] }; + case (wci_14_reqPend) + 2'd1: MUX_wci_14_reqTO$write_1__VAL_1 = { 1'd1, wci_14_reqTO[1:0] }; 2'd2: - MUX_wci_reqFAIL_3$write_1__VAL_1 = - { wci_reqFAIL_3[2], 1'd1, wci_reqFAIL_3[0] }; - default: MUX_wci_reqFAIL_3$write_1__VAL_1 = - { wci_reqFAIL_3[2:1], 1'd1 }; + MUX_wci_14_reqTO$write_1__VAL_1 = + { wci_14_reqTO[2], 1'd1, wci_14_reqTO[0] }; + default: MUX_wci_14_reqTO$write_1__VAL_1 = { wci_14_reqTO[2:1], 1'd1 }; endcase end - always@(wci_reqPend_4 or wci_reqFAIL_4) + assign MUX_wci_14_respF$enq_1__VAL_1 = + (wci_14_wciResponse$wget[33:32] == 2'd0) ? + 34'h1C0DE4203 : + wci_14_wciResponse$wget ; + assign MUX_wci_14_respF$enq_1__VAL_2 = { 2'd1, wci_14_wStatus } ; + assign MUX_wci_14_respF$enq_1__VAL_3 = { 2'd1, x_data__h103509 } ; + assign MUX_wci_14_respF$enq_1__VAL_4 = { 2'd1, x_data__h103515 } ; + assign MUX_wci_14_respF$enq_1__VAL_5 = { 22'd1048576, wci_14_pageWindow } ; + assign MUX_wci_14_respTimr$write_1__VAL_2 = + (wci_14_wciResponse$wget[33:32] == 2'd0) ? + (wci_14_respTimr_188_ULT_1_SL_wci_14_wTimeout_1_ETC___d2191 ? + x__h73021 : + 32'd0) : + 32'd0 ; + always@(wci_1_reqPend or wci_1_reqERR) begin - case (wci_reqPend_4) - 2'd1: MUX_wci_reqFAIL_4$write_1__VAL_1 = { 1'd1, wci_reqFAIL_4[1:0] }; + case (wci_1_reqPend) + 2'd1: MUX_wci_1_reqERR$write_1__VAL_1 = { 1'd1, wci_1_reqERR[1:0] }; 2'd2: - MUX_wci_reqFAIL_4$write_1__VAL_1 = - { wci_reqFAIL_4[2], 1'd1, wci_reqFAIL_4[0] }; - default: MUX_wci_reqFAIL_4$write_1__VAL_1 = - { wci_reqFAIL_4[2:1], 1'd1 }; + MUX_wci_1_reqERR$write_1__VAL_1 = + { wci_1_reqERR[2], 1'd1, wci_1_reqERR[0] }; + default: MUX_wci_1_reqERR$write_1__VAL_1 = { wci_1_reqERR[2:1], 1'd1 }; endcase end - always@(wci_reqPend_5 or wci_reqFAIL_5) + always@(wci_1_reqPend or wci_1_reqFAIL) begin - case (wci_reqPend_5) - 2'd1: MUX_wci_reqFAIL_5$write_1__VAL_1 = { 1'd1, wci_reqFAIL_5[1:0] }; + case (wci_1_reqPend) + 2'd1: MUX_wci_1_reqFAIL$write_1__VAL_1 = { 1'd1, wci_1_reqFAIL[1:0] }; 2'd2: - MUX_wci_reqFAIL_5$write_1__VAL_1 = - { wci_reqFAIL_5[2], 1'd1, wci_reqFAIL_5[0] }; - default: MUX_wci_reqFAIL_5$write_1__VAL_1 = - { wci_reqFAIL_5[2:1], 1'd1 }; + MUX_wci_1_reqFAIL$write_1__VAL_1 = + { wci_1_reqFAIL[2], 1'd1, wci_1_reqFAIL[0] }; + default: MUX_wci_1_reqFAIL$write_1__VAL_1 = + { wci_1_reqFAIL[2:1], 1'd1 }; endcase end - always@(wci_reqPend_6 or wci_reqFAIL_6) + assign MUX_wci_1_reqF_cntr_r$write_1__VAL_1 = wci_1_reqF_cntr_r + 1'd1 ; + assign MUX_wci_1_reqF_cntr_r$write_1__VAL_2 = wci_1_reqF_cntr_r - 1'd1 ; + assign MUX_wci_1_reqF_q_0$write_1__VAL_1 = + wci_1_reqF_cntr_r ? + MUX_wci_1_reqF_q_0$write_1__VAL_2 : + 72'h0000000000AAAAAAAA ; + always@(WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_T_T or + MUX_wci_0_reqF_x_wire$wset_1__VAL_1 or + WILL_FIRE_RL_cpDispatch_F_F_T_E1_T_T or + MUX_wci_1_reqF_x_wire$wset_1__VAL_2 or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_T_T or + MUX_wci_1_reqF_x_wire$wset_1__VAL_3) begin - case (wci_reqPend_6) - 2'd1: MUX_wci_reqFAIL_6$write_1__VAL_1 = { 1'd1, wci_reqFAIL_6[1:0] }; - 2'd2: - MUX_wci_reqFAIL_6$write_1__VAL_1 = - { wci_reqFAIL_6[2], 1'd1, wci_reqFAIL_6[0] }; - default: MUX_wci_reqFAIL_6$write_1__VAL_1 = - { wci_reqFAIL_6[2:1], 1'd1 }; + case (1'b1) // synopsys parallel_case + WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_T_T: + MUX_wci_1_reqF_q_0$write_1__VAL_2 = + MUX_wci_0_reqF_x_wire$wset_1__VAL_1; + WILL_FIRE_RL_cpDispatch_F_F_T_E1_T_T: + MUX_wci_1_reqF_q_0$write_1__VAL_2 = + MUX_wci_1_reqF_x_wire$wset_1__VAL_2; + WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_T_T: + MUX_wci_1_reqF_q_0$write_1__VAL_2 = + MUX_wci_1_reqF_x_wire$wset_1__VAL_3; + default: MUX_wci_1_reqF_q_0$write_1__VAL_2 = + 72'hAAAAAAAAAAAAAAAAAA /* unspecified value */ ; endcase end - always@(wci_reqPend_7 or wci_reqFAIL_7) + assign MUX_wci_1_reqF_x_wire$wset_1__VAL_2 = + { 4'd3, cpReq[3:0], wciAddr__h77105, cpReq[59:28] } ; + assign MUX_wci_1_reqF_x_wire$wset_1__VAL_3 = + { 4'd5, cpReq[3:0], wciAddr__h77105, 32'hAAAAAAAA } ; + always@(wci_1_reqPend or wci_1_reqTO) begin - case (wci_reqPend_7) - 2'd1: MUX_wci_reqFAIL_7$write_1__VAL_1 = { 1'd1, wci_reqFAIL_7[1:0] }; + case (wci_1_reqPend) + 2'd1: MUX_wci_1_reqTO$write_1__VAL_1 = { 1'd1, wci_1_reqTO[1:0] }; 2'd2: - MUX_wci_reqFAIL_7$write_1__VAL_1 = - { wci_reqFAIL_7[2], 1'd1, wci_reqFAIL_7[0] }; - default: MUX_wci_reqFAIL_7$write_1__VAL_1 = - { wci_reqFAIL_7[2:1], 1'd1 }; + MUX_wci_1_reqTO$write_1__VAL_1 = + { wci_1_reqTO[2], 1'd1, wci_1_reqTO[0] }; + default: MUX_wci_1_reqTO$write_1__VAL_1 = { wci_1_reqTO[2:1], 1'd1 }; endcase end - always@(wci_reqPend_8 or wci_reqFAIL_8) + assign MUX_wci_1_respF$enq_1__VAL_1 = + (wci_1_wciResponse$wget[33:32] == 2'd0) ? + 34'h1C0DE4203 : + wci_1_wciResponse$wget ; + assign MUX_wci_1_respF$enq_1__VAL_2 = { 2'd1, wci_1_wStatus } ; + assign MUX_wci_1_respF$enq_1__VAL_3 = { 2'd1, x_data__h102846 } ; + assign MUX_wci_1_respF$enq_1__VAL_4 = { 2'd1, x_data__h102852 } ; + assign MUX_wci_1_respF$enq_1__VAL_5 = { 22'd1048576, wci_1_pageWindow } ; + assign MUX_wci_1_respTimr$write_1__VAL_2 = + (wci_1_wciResponse$wget[33:32] == 2'd0) ? + (wci_1_respTimr_68_ULT_1_SL_wci_1_wTimeout_69_70___d371 ? + x__h16224 : + 32'd0) : + 32'd0 ; + always@(wci_2_reqPend or wci_2_reqERR) begin - case (wci_reqPend_8) - 2'd1: MUX_wci_reqFAIL_8$write_1__VAL_1 = { 1'd1, wci_reqFAIL_8[1:0] }; + case (wci_2_reqPend) + 2'd1: MUX_wci_2_reqERR$write_1__VAL_1 = { 1'd1, wci_2_reqERR[1:0] }; 2'd2: - MUX_wci_reqFAIL_8$write_1__VAL_1 = - { wci_reqFAIL_8[2], 1'd1, wci_reqFAIL_8[0] }; - default: MUX_wci_reqFAIL_8$write_1__VAL_1 = - { wci_reqFAIL_8[2:1], 1'd1 }; + MUX_wci_2_reqERR$write_1__VAL_1 = + { wci_2_reqERR[2], 1'd1, wci_2_reqERR[0] }; + default: MUX_wci_2_reqERR$write_1__VAL_1 = { wci_2_reqERR[2:1], 1'd1 }; endcase end - always@(wci_reqPend_9 or wci_reqFAIL_9) + always@(wci_2_reqPend or wci_2_reqFAIL) begin - case (wci_reqPend_9) - 2'd1: MUX_wci_reqFAIL_9$write_1__VAL_1 = { 1'd1, wci_reqFAIL_9[1:0] }; + case (wci_2_reqPend) + 2'd1: MUX_wci_2_reqFAIL$write_1__VAL_1 = { 1'd1, wci_2_reqFAIL[1:0] }; 2'd2: - MUX_wci_reqFAIL_9$write_1__VAL_1 = - { wci_reqFAIL_9[2], 1'd1, wci_reqFAIL_9[0] }; - default: MUX_wci_reqFAIL_9$write_1__VAL_1 = - { wci_reqFAIL_9[2:1], 1'd1 }; + MUX_wci_2_reqFAIL$write_1__VAL_1 = + { wci_2_reqFAIL[2], 1'd1, wci_2_reqFAIL[0] }; + default: MUX_wci_2_reqFAIL$write_1__VAL_1 = + { wci_2_reqFAIL[2:1], 1'd1 }; endcase end - assign MUX_wci_reqF_10_c_r$write_1__VAL_1 = wci_reqF_10_c_r + 1'd1 ; - assign MUX_wci_reqF_10_c_r$write_1__VAL_2 = wci_reqF_10_c_r - 1'd1 ; - always@(WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_T_T or - MUX_wci_reqF_10_x_wire$wset_1__VAL_1 or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T or - MUX_wci_reqF_10_x_wire$wset_1__VAL_2 or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T or - MUX_wci_reqF_10_x_wire$wset_1__VAL_3) + assign MUX_wci_2_reqF_cntr_r$write_1__VAL_1 = wci_2_reqF_cntr_r + 1'd1 ; + assign MUX_wci_2_reqF_cntr_r$write_1__VAL_2 = wci_2_reqF_cntr_r - 1'd1 ; + assign MUX_wci_2_reqF_q_0$write_1__VAL_1 = + wci_2_reqF_cntr_r ? + MUX_wci_2_reqF_q_0$write_1__VAL_2 : + 72'h0000000000AAAAAAAA ; + always@(WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_F_T_T or + MUX_wci_0_reqF_x_wire$wset_1__VAL_1 or + WILL_FIRE_RL_cpDispatch_F_F_T_E2_T_T or + MUX_wci_2_reqF_x_wire$wset_1__VAL_2 or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_T_T or + MUX_wci_2_reqF_x_wire$wset_1__VAL_3) begin case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_T_T: - MUX_wci_reqF_10_q_0$write_1__VAL_1 = - MUX_wci_reqF_10_x_wire$wset_1__VAL_1; - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T: - MUX_wci_reqF_10_q_0$write_1__VAL_1 = - MUX_wci_reqF_10_x_wire$wset_1__VAL_2; - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T: - MUX_wci_reqF_10_q_0$write_1__VAL_1 = - MUX_wci_reqF_10_x_wire$wset_1__VAL_3; - default: MUX_wci_reqF_10_q_0$write_1__VAL_1 = + WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_F_T_T: + MUX_wci_2_reqF_q_0$write_1__VAL_2 = + MUX_wci_0_reqF_x_wire$wset_1__VAL_1; + WILL_FIRE_RL_cpDispatch_F_F_T_E2_T_T: + MUX_wci_2_reqF_q_0$write_1__VAL_2 = + MUX_wci_2_reqF_x_wire$wset_1__VAL_2; + WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_T_T: + MUX_wci_2_reqF_q_0$write_1__VAL_2 = + MUX_wci_2_reqF_x_wire$wset_1__VAL_3; + default: MUX_wci_2_reqF_q_0$write_1__VAL_2 = 72'hAAAAAAAAAAAAAAAAAA /* unspecified value */ ; endcase end - assign MUX_wci_reqF_10_q_0$write_1__VAL_2 = - wci_reqF_10_c_r ? - MUX_wci_reqF_10_q_0$write_1__VAL_1 : - 72'h0000000000AAAAAAAA ; - assign MUX_wci_reqF_10_x_wire$wset_1__VAL_1 = - { 4'd3, cpReq[3:0], wciAddr__h78050, cpReq[59:28] } ; - assign MUX_wci_reqF_10_x_wire$wset_1__VAL_2 = - { 4'd5, cpReq[3:0], wciAddr__h78050, 32'hAAAAAAAA } ; - assign MUX_wci_reqF_10_x_wire$wset_1__VAL_3 = - { 8'd79, x_addr__h97612, 32'hAAAAAAAA } ; - assign MUX_wci_reqF_11_c_r$write_1__VAL_1 = wci_reqF_11_c_r + 1'd1 ; - assign MUX_wci_reqF_11_c_r$write_1__VAL_2 = wci_reqF_11_c_r - 1'd1 ; - always@(WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_T_T or - MUX_wci_reqF_11_x_wire$wset_1__VAL_1 or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T or - MUX_wci_reqF_11_x_wire$wset_1__VAL_2 or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T or - MUX_wci_reqF_10_x_wire$wset_1__VAL_3) + assign MUX_wci_2_reqF_x_wire$wset_1__VAL_2 = + { 4'd3, cpReq[3:0], wciAddr__h77173, cpReq[59:28] } ; + assign MUX_wci_2_reqF_x_wire$wset_1__VAL_3 = + { 4'd5, cpReq[3:0], wciAddr__h77173, 32'hAAAAAAAA } ; + always@(wci_2_reqPend or wci_2_reqTO) begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_T_T: - MUX_wci_reqF_11_q_0$write_1__VAL_1 = - MUX_wci_reqF_11_x_wire$wset_1__VAL_1; - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T: - MUX_wci_reqF_11_q_0$write_1__VAL_1 = - MUX_wci_reqF_11_x_wire$wset_1__VAL_2; - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T: - MUX_wci_reqF_11_q_0$write_1__VAL_1 = - MUX_wci_reqF_10_x_wire$wset_1__VAL_3; - default: MUX_wci_reqF_11_q_0$write_1__VAL_1 = - 72'hAAAAAAAAAAAAAAAAAA /* unspecified value */ ; + case (wci_2_reqPend) + 2'd1: MUX_wci_2_reqTO$write_1__VAL_1 = { 1'd1, wci_2_reqTO[1:0] }; + 2'd2: + MUX_wci_2_reqTO$write_1__VAL_1 = + { wci_2_reqTO[2], 1'd1, wci_2_reqTO[0] }; + default: MUX_wci_2_reqTO$write_1__VAL_1 = { wci_2_reqTO[2:1], 1'd1 }; endcase end - assign MUX_wci_reqF_11_q_0$write_1__VAL_2 = - wci_reqF_11_c_r ? - MUX_wci_reqF_11_q_0$write_1__VAL_1 : - 72'h0000000000AAAAAAAA ; - assign MUX_wci_reqF_11_x_wire$wset_1__VAL_1 = - { 4'd3, cpReq[3:0], wciAddr__h78116, cpReq[59:28] } ; - assign MUX_wci_reqF_11_x_wire$wset_1__VAL_2 = - { 4'd5, cpReq[3:0], wciAddr__h78116, 32'hAAAAAAAA } ; - assign MUX_wci_reqF_12_c_r$write_1__VAL_1 = wci_reqF_12_c_r + 1'd1 ; - assign MUX_wci_reqF_12_c_r$write_1__VAL_2 = wci_reqF_12_c_r - 1'd1 ; - always@(WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T or - MUX_wci_reqF_12_x_wire$wset_1__VAL_1 or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T or - MUX_wci_reqF_12_x_wire$wset_1__VAL_2 or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T or - MUX_wci_reqF_10_x_wire$wset_1__VAL_3) + assign MUX_wci_2_respF$enq_1__VAL_1 = + (wci_2_wciResponse$wget[33:32] == 2'd0) ? + 34'h1C0DE4203 : + wci_2_wciResponse$wget ; + assign MUX_wci_2_respF$enq_1__VAL_2 = { 2'd1, wci_2_wStatus } ; + assign MUX_wci_2_respF$enq_1__VAL_3 = { 2'd1, x_data__h102897 } ; + assign MUX_wci_2_respF$enq_1__VAL_4 = { 2'd1, x_data__h102903 } ; + assign MUX_wci_2_respF$enq_1__VAL_5 = { 22'd1048576, wci_2_pageWindow } ; + assign MUX_wci_2_respTimr$write_1__VAL_2 = + (wci_2_wciResponse$wget[33:32] == 2'd0) ? + (wci_2_respTimr_08_ULT_1_SL_wci_2_wTimeout_09_10___d511 ? + x__h20593 : + 32'd0) : + 32'd0 ; + always@(wci_3_reqPend or wci_3_reqERR) begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T: - MUX_wci_reqF_12_q_0$write_1__VAL_1 = - MUX_wci_reqF_12_x_wire$wset_1__VAL_1; - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T: - MUX_wci_reqF_12_q_0$write_1__VAL_1 = - MUX_wci_reqF_12_x_wire$wset_1__VAL_2; - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T: - MUX_wci_reqF_12_q_0$write_1__VAL_1 = - MUX_wci_reqF_10_x_wire$wset_1__VAL_3; - default: MUX_wci_reqF_12_q_0$write_1__VAL_1 = - 72'hAAAAAAAAAAAAAAAAAA /* unspecified value */ ; + case (wci_3_reqPend) + 2'd1: MUX_wci_3_reqERR$write_1__VAL_1 = { 1'd1, wci_3_reqERR[1:0] }; + 2'd2: + MUX_wci_3_reqERR$write_1__VAL_1 = + { wci_3_reqERR[2], 1'd1, wci_3_reqERR[0] }; + default: MUX_wci_3_reqERR$write_1__VAL_1 = { wci_3_reqERR[2:1], 1'd1 }; endcase end - assign MUX_wci_reqF_12_q_0$write_1__VAL_2 = - wci_reqF_12_c_r ? - MUX_wci_reqF_12_q_0$write_1__VAL_1 : - 72'h0000000000AAAAAAAA ; - assign MUX_wci_reqF_12_x_wire$wset_1__VAL_1 = - { 4'd3, cpReq[3:0], wciAddr__h78182, cpReq[59:28] } ; - assign MUX_wci_reqF_12_x_wire$wset_1__VAL_2 = - { 4'd5, cpReq[3:0], wciAddr__h78182, 32'hAAAAAAAA } ; - assign MUX_wci_reqF_13_c_r$write_1__VAL_1 = wci_reqF_13_c_r + 1'd1 ; - assign MUX_wci_reqF_13_c_r$write_1__VAL_2 = wci_reqF_13_c_r - 1'd1 ; - always@(WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T or - MUX_wci_reqF_13_x_wire$wset_1__VAL_1 or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T or - MUX_wci_reqF_13_x_wire$wset_1__VAL_2 or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T or - MUX_wci_reqF_10_x_wire$wset_1__VAL_3) + always@(wci_3_reqPend or wci_3_reqFAIL) begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T: - MUX_wci_reqF_13_q_0$write_1__VAL_1 = - MUX_wci_reqF_13_x_wire$wset_1__VAL_1; - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T: - MUX_wci_reqF_13_q_0$write_1__VAL_1 = - MUX_wci_reqF_13_x_wire$wset_1__VAL_2; - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T: - MUX_wci_reqF_13_q_0$write_1__VAL_1 = - MUX_wci_reqF_10_x_wire$wset_1__VAL_3; - default: MUX_wci_reqF_13_q_0$write_1__VAL_1 = - 72'hAAAAAAAAAAAAAAAAAA /* unspecified value */ ; + case (wci_3_reqPend) + 2'd1: MUX_wci_3_reqFAIL$write_1__VAL_1 = { 1'd1, wci_3_reqFAIL[1:0] }; + 2'd2: + MUX_wci_3_reqFAIL$write_1__VAL_1 = + { wci_3_reqFAIL[2], 1'd1, wci_3_reqFAIL[0] }; + default: MUX_wci_3_reqFAIL$write_1__VAL_1 = + { wci_3_reqFAIL[2:1], 1'd1 }; endcase end - assign MUX_wci_reqF_13_q_0$write_1__VAL_2 = - wci_reqF_13_c_r ? - MUX_wci_reqF_13_q_0$write_1__VAL_1 : + assign MUX_wci_3_reqF_cntr_r$write_1__VAL_1 = wci_3_reqF_cntr_r + 1'd1 ; + assign MUX_wci_3_reqF_cntr_r$write_1__VAL_2 = wci_3_reqF_cntr_r - 1'd1 ; + assign MUX_wci_3_reqF_q_0$write_1__VAL_1 = + wci_3_reqF_cntr_r ? + MUX_wci_3_reqF_q_0$write_1__VAL_2 : 72'h0000000000AAAAAAAA ; - assign MUX_wci_reqF_13_x_wire$wset_1__VAL_1 = - { 4'd3, cpReq[3:0], wciAddr__h78248, cpReq[59:28] } ; - assign MUX_wci_reqF_13_x_wire$wset_1__VAL_2 = - { 4'd5, cpReq[3:0], wciAddr__h78248, 32'hAAAAAAAA } ; - assign MUX_wci_reqF_14_c_r$write_1__VAL_1 = wci_reqF_14_c_r + 1'd1 ; - assign MUX_wci_reqF_14_c_r$write_1__VAL_2 = wci_reqF_14_c_r - 1'd1 ; - always@(WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T or - MUX_wci_reqF_14_x_wire$wset_1__VAL_1 or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T or - MUX_wci_reqF_14_x_wire$wset_1__VAL_2 or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T or - MUX_wci_reqF_10_x_wire$wset_1__VAL_3) + always@(WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_F_T_T or + MUX_wci_0_reqF_x_wire$wset_1__VAL_1 or + WILL_FIRE_RL_cpDispatch_F_F_T_E3_T_T or + MUX_wci_3_reqF_x_wire$wset_1__VAL_2 or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_T_T or + MUX_wci_3_reqF_x_wire$wset_1__VAL_3) begin case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T: - MUX_wci_reqF_14_q_0$write_1__VAL_1 = - MUX_wci_reqF_14_x_wire$wset_1__VAL_1; - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T: - MUX_wci_reqF_14_q_0$write_1__VAL_1 = - MUX_wci_reqF_14_x_wire$wset_1__VAL_2; - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T: - MUX_wci_reqF_14_q_0$write_1__VAL_1 = - MUX_wci_reqF_10_x_wire$wset_1__VAL_3; - default: MUX_wci_reqF_14_q_0$write_1__VAL_1 = + WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_F_T_T: + MUX_wci_3_reqF_q_0$write_1__VAL_2 = + MUX_wci_0_reqF_x_wire$wset_1__VAL_1; + WILL_FIRE_RL_cpDispatch_F_F_T_E3_T_T: + MUX_wci_3_reqF_q_0$write_1__VAL_2 = + MUX_wci_3_reqF_x_wire$wset_1__VAL_2; + WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_T_T: + MUX_wci_3_reqF_q_0$write_1__VAL_2 = + MUX_wci_3_reqF_x_wire$wset_1__VAL_3; + default: MUX_wci_3_reqF_q_0$write_1__VAL_2 = 72'hAAAAAAAAAAAAAAAAAA /* unspecified value */ ; endcase end - assign MUX_wci_reqF_14_q_0$write_1__VAL_2 = - wci_reqF_14_c_r ? - MUX_wci_reqF_14_q_0$write_1__VAL_1 : - 72'h0000000000AAAAAAAA ; - assign MUX_wci_reqF_14_x_wire$wset_1__VAL_1 = - { 4'd3, cpReq[3:0], wciAddr__h78314, cpReq[59:28] } ; - assign MUX_wci_reqF_14_x_wire$wset_1__VAL_2 = - { 4'd5, cpReq[3:0], wciAddr__h78314, 32'hAAAAAAAA } ; - assign MUX_wci_reqF_1_c_r$write_1__VAL_1 = wci_reqF_1_c_r + 1'd1 ; - assign MUX_wci_reqF_1_c_r$write_1__VAL_2 = wci_reqF_1_c_r - 1'd1 ; - assign MUX_wci_reqF_1_q_0$write_1__VAL_1 = - wci_reqF_1_c_r ? - MUX_wci_reqF_1_q_0$write_1__VAL_2 : - 72'h0000000000AAAAAAAA ; - always@(WILL_FIRE_RL_cpDispatch_F_F_T_F_T_T_T or - MUX_wci_reqF_1_x_wire$wset_1__VAL_1 or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_T_T or - MUX_wci_reqF_1_x_wire$wset_1__VAL_2 or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_F_T_T or - MUX_wci_reqF_10_x_wire$wset_1__VAL_3) + assign MUX_wci_3_reqF_x_wire$wset_1__VAL_2 = + { 4'd3, cpReq[3:0], wciAddr__h77241, cpReq[59:28] } ; + assign MUX_wci_3_reqF_x_wire$wset_1__VAL_3 = + { 4'd5, cpReq[3:0], wciAddr__h77241, 32'hAAAAAAAA } ; + always@(wci_3_reqPend or wci_3_reqTO) begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_cpDispatch_F_F_T_F_T_T_T: - MUX_wci_reqF_1_q_0$write_1__VAL_2 = - MUX_wci_reqF_1_x_wire$wset_1__VAL_1; - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_T_T: - MUX_wci_reqF_1_q_0$write_1__VAL_2 = - MUX_wci_reqF_1_x_wire$wset_1__VAL_2; - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_F_T_T: - MUX_wci_reqF_1_q_0$write_1__VAL_2 = - MUX_wci_reqF_10_x_wire$wset_1__VAL_3; - default: MUX_wci_reqF_1_q_0$write_1__VAL_2 = - 72'hAAAAAAAAAAAAAAAAAA /* unspecified value */ ; + case (wci_3_reqPend) + 2'd1: MUX_wci_3_reqTO$write_1__VAL_1 = { 1'd1, wci_3_reqTO[1:0] }; + 2'd2: + MUX_wci_3_reqTO$write_1__VAL_1 = + { wci_3_reqTO[2], 1'd1, wci_3_reqTO[0] }; + default: MUX_wci_3_reqTO$write_1__VAL_1 = { wci_3_reqTO[2:1], 1'd1 }; endcase end - assign MUX_wci_reqF_1_x_wire$wset_1__VAL_1 = - { 4'd3, cpReq[3:0], wciAddr__h77456, cpReq[59:28] } ; - assign MUX_wci_reqF_1_x_wire$wset_1__VAL_2 = - { 4'd5, cpReq[3:0], wciAddr__h77456, 32'hAAAAAAAA } ; - assign MUX_wci_reqF_2_c_r$write_1__VAL_1 = wci_reqF_2_c_r + 1'd1 ; - assign MUX_wci_reqF_2_c_r$write_1__VAL_2 = wci_reqF_2_c_r - 1'd1 ; - always@(WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_T_T or - MUX_wci_reqF_2_x_wire$wset_1__VAL_1 or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_T_T or - MUX_wci_reqF_2_x_wire$wset_1__VAL_2 or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_F_T_T or - MUX_wci_reqF_10_x_wire$wset_1__VAL_3) + assign MUX_wci_3_respF$enq_1__VAL_1 = + (wci_3_wciResponse$wget[33:32] == 2'd0) ? + 34'h1C0DE4203 : + wci_3_wciResponse$wget ; + assign MUX_wci_3_respF$enq_1__VAL_2 = { 2'd1, wci_3_wStatus } ; + assign MUX_wci_3_respF$enq_1__VAL_3 = { 2'd1, x_data__h102948 } ; + assign MUX_wci_3_respF$enq_1__VAL_4 = { 2'd1, x_data__h102954 } ; + assign MUX_wci_3_respF$enq_1__VAL_5 = { 22'd1048576, wci_3_pageWindow } ; + assign MUX_wci_3_respTimr$write_1__VAL_2 = + (wci_3_wciResponse$wget[33:32] == 2'd0) ? + (wci_3_respTimr_48_ULT_1_SL_wci_3_wTimeout_49_50___d651 ? + x__h24962 : + 32'd0) : + 32'd0 ; + always@(wci_4_reqPend or wci_4_reqERR) begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_T_T: - MUX_wci_reqF_2_q_0$write_1__VAL_1 = - MUX_wci_reqF_2_x_wire$wset_1__VAL_1; - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_T_T: - MUX_wci_reqF_2_q_0$write_1__VAL_1 = - MUX_wci_reqF_2_x_wire$wset_1__VAL_2; - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_F_T_T: - MUX_wci_reqF_2_q_0$write_1__VAL_1 = - MUX_wci_reqF_10_x_wire$wset_1__VAL_3; - default: MUX_wci_reqF_2_q_0$write_1__VAL_1 = - 72'hAAAAAAAAAAAAAAAAAA /* unspecified value */ ; + case (wci_4_reqPend) + 2'd1: MUX_wci_4_reqERR$write_1__VAL_1 = { 1'd1, wci_4_reqERR[1:0] }; + 2'd2: + MUX_wci_4_reqERR$write_1__VAL_1 = + { wci_4_reqERR[2], 1'd1, wci_4_reqERR[0] }; + default: MUX_wci_4_reqERR$write_1__VAL_1 = { wci_4_reqERR[2:1], 1'd1 }; endcase end - assign MUX_wci_reqF_2_q_0$write_1__VAL_2 = - wci_reqF_2_c_r ? - MUX_wci_reqF_2_q_0$write_1__VAL_1 : - 72'h0000000000AAAAAAAA ; - assign MUX_wci_reqF_2_x_wire$wset_1__VAL_1 = - { 4'd3, cpReq[3:0], wciAddr__h77522, cpReq[59:28] } ; - assign MUX_wci_reqF_2_x_wire$wset_1__VAL_2 = - { 4'd5, cpReq[3:0], wciAddr__h77522, 32'hAAAAAAAA } ; - assign MUX_wci_reqF_3_c_r$write_1__VAL_1 = wci_reqF_3_c_r + 1'd1 ; - assign MUX_wci_reqF_3_c_r$write_1__VAL_2 = wci_reqF_3_c_r - 1'd1 ; - always@(WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_T_T or - MUX_wci_reqF_3_x_wire$wset_1__VAL_1 or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_T_T or - MUX_wci_reqF_3_x_wire$wset_1__VAL_2 or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_F_T_T or - MUX_wci_reqF_10_x_wire$wset_1__VAL_3) + always@(wci_4_reqPend or wci_4_reqFAIL) begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_T_T: - MUX_wci_reqF_3_q_0$write_1__VAL_1 = - MUX_wci_reqF_3_x_wire$wset_1__VAL_1; - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_T_T: - MUX_wci_reqF_3_q_0$write_1__VAL_1 = - MUX_wci_reqF_3_x_wire$wset_1__VAL_2; - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_F_T_T: - MUX_wci_reqF_3_q_0$write_1__VAL_1 = - MUX_wci_reqF_10_x_wire$wset_1__VAL_3; - default: MUX_wci_reqF_3_q_0$write_1__VAL_1 = - 72'hAAAAAAAAAAAAAAAAAA /* unspecified value */ ; + case (wci_4_reqPend) + 2'd1: MUX_wci_4_reqFAIL$write_1__VAL_1 = { 1'd1, wci_4_reqFAIL[1:0] }; + 2'd2: + MUX_wci_4_reqFAIL$write_1__VAL_1 = + { wci_4_reqFAIL[2], 1'd1, wci_4_reqFAIL[0] }; + default: MUX_wci_4_reqFAIL$write_1__VAL_1 = + { wci_4_reqFAIL[2:1], 1'd1 }; endcase end - assign MUX_wci_reqF_3_q_0$write_1__VAL_2 = - wci_reqF_3_c_r ? - MUX_wci_reqF_3_q_0$write_1__VAL_1 : + assign MUX_wci_4_reqF_cntr_r$write_1__VAL_1 = wci_4_reqF_cntr_r + 1'd1 ; + assign MUX_wci_4_reqF_cntr_r$write_1__VAL_2 = wci_4_reqF_cntr_r - 1'd1 ; + assign MUX_wci_4_reqF_q_0$write_1__VAL_1 = + wci_4_reqF_cntr_r ? + MUX_wci_4_reqF_q_0$write_1__VAL_2 : 72'h0000000000AAAAAAAA ; - assign MUX_wci_reqF_3_x_wire$wset_1__VAL_1 = - { 4'd3, cpReq[3:0], wciAddr__h77588, cpReq[59:28] } ; - assign MUX_wci_reqF_3_x_wire$wset_1__VAL_2 = - { 4'd5, cpReq[3:0], wciAddr__h77588, 32'hAAAAAAAA } ; - assign MUX_wci_reqF_4_c_r$write_1__VAL_1 = wci_reqF_4_c_r + 1'd1 ; - assign MUX_wci_reqF_4_c_r$write_1__VAL_2 = wci_reqF_4_c_r - 1'd1 ; - always@(WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_T_T or - MUX_wci_reqF_4_x_wire$wset_1__VAL_1 or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_T_T or - MUX_wci_reqF_4_x_wire$wset_1__VAL_2 or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_T_T or - MUX_wci_reqF_10_x_wire$wset_1__VAL_3) + always@(WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_F_T_T or + MUX_wci_0_reqF_x_wire$wset_1__VAL_1 or + WILL_FIRE_RL_cpDispatch_F_F_T_E4_T_T or + MUX_wci_4_reqF_x_wire$wset_1__VAL_2 or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_T_T or + MUX_wci_4_reqF_x_wire$wset_1__VAL_3) begin case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_T_T: - MUX_wci_reqF_4_q_0$write_1__VAL_1 = - MUX_wci_reqF_4_x_wire$wset_1__VAL_1; - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_T_T: - MUX_wci_reqF_4_q_0$write_1__VAL_1 = - MUX_wci_reqF_4_x_wire$wset_1__VAL_2; - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_T_T: - MUX_wci_reqF_4_q_0$write_1__VAL_1 = - MUX_wci_reqF_10_x_wire$wset_1__VAL_3; - default: MUX_wci_reqF_4_q_0$write_1__VAL_1 = + WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_F_T_T: + MUX_wci_4_reqF_q_0$write_1__VAL_2 = + MUX_wci_0_reqF_x_wire$wset_1__VAL_1; + WILL_FIRE_RL_cpDispatch_F_F_T_E4_T_T: + MUX_wci_4_reqF_q_0$write_1__VAL_2 = + MUX_wci_4_reqF_x_wire$wset_1__VAL_2; + WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_T_T: + MUX_wci_4_reqF_q_0$write_1__VAL_2 = + MUX_wci_4_reqF_x_wire$wset_1__VAL_3; + default: MUX_wci_4_reqF_q_0$write_1__VAL_2 = 72'hAAAAAAAAAAAAAAAAAA /* unspecified value */ ; endcase end - assign MUX_wci_reqF_4_q_0$write_1__VAL_2 = - wci_reqF_4_c_r ? - MUX_wci_reqF_4_q_0$write_1__VAL_1 : - 72'h0000000000AAAAAAAA ; - assign MUX_wci_reqF_4_x_wire$wset_1__VAL_1 = - { 4'd3, cpReq[3:0], wciAddr__h77654, cpReq[59:28] } ; - assign MUX_wci_reqF_4_x_wire$wset_1__VAL_2 = - { 4'd5, cpReq[3:0], wciAddr__h77654, 32'hAAAAAAAA } ; - assign MUX_wci_reqF_5_c_r$write_1__VAL_1 = wci_reqF_5_c_r + 1'd1 ; - assign MUX_wci_reqF_5_c_r$write_1__VAL_2 = wci_reqF_5_c_r - 1'd1 ; - always@(WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_T_T or - MUX_wci_reqF_5_x_wire$wset_1__VAL_1 or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_T_T or - MUX_wci_reqF_5_x_wire$wset_1__VAL_2 or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_T_T or - MUX_wci_reqF_10_x_wire$wset_1__VAL_3) + assign MUX_wci_4_reqF_x_wire$wset_1__VAL_2 = + { 4'd3, cpReq[3:0], wciAddr__h77309, cpReq[59:28] } ; + assign MUX_wci_4_reqF_x_wire$wset_1__VAL_3 = + { 4'd5, cpReq[3:0], wciAddr__h77309, 32'hAAAAAAAA } ; + always@(wci_4_reqPend or wci_4_reqTO) begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_T_T: - MUX_wci_reqF_5_q_0$write_1__VAL_1 = - MUX_wci_reqF_5_x_wire$wset_1__VAL_1; - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_T_T: - MUX_wci_reqF_5_q_0$write_1__VAL_1 = - MUX_wci_reqF_5_x_wire$wset_1__VAL_2; - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_T_T: - MUX_wci_reqF_5_q_0$write_1__VAL_1 = - MUX_wci_reqF_10_x_wire$wset_1__VAL_3; - default: MUX_wci_reqF_5_q_0$write_1__VAL_1 = - 72'hAAAAAAAAAAAAAAAAAA /* unspecified value */ ; + case (wci_4_reqPend) + 2'd1: MUX_wci_4_reqTO$write_1__VAL_1 = { 1'd1, wci_4_reqTO[1:0] }; + 2'd2: + MUX_wci_4_reqTO$write_1__VAL_1 = + { wci_4_reqTO[2], 1'd1, wci_4_reqTO[0] }; + default: MUX_wci_4_reqTO$write_1__VAL_1 = { wci_4_reqTO[2:1], 1'd1 }; endcase end - assign MUX_wci_reqF_5_q_0$write_1__VAL_2 = - wci_reqF_5_c_r ? - MUX_wci_reqF_5_q_0$write_1__VAL_1 : - 72'h0000000000AAAAAAAA ; - assign MUX_wci_reqF_5_x_wire$wset_1__VAL_1 = - { 4'd3, cpReq[3:0], wciAddr__h77720, cpReq[59:28] } ; - assign MUX_wci_reqF_5_x_wire$wset_1__VAL_2 = - { 4'd5, cpReq[3:0], wciAddr__h77720, 32'hAAAAAAAA } ; - assign MUX_wci_reqF_6_c_r$write_1__VAL_1 = wci_reqF_6_c_r + 1'd1 ; - assign MUX_wci_reqF_6_c_r$write_1__VAL_2 = wci_reqF_6_c_r - 1'd1 ; - always@(WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_T_T or - MUX_wci_reqF_6_x_wire$wset_1__VAL_1 or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_T_T or - MUX_wci_reqF_6_x_wire$wset_1__VAL_2 or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_F_T_T or - MUX_wci_reqF_10_x_wire$wset_1__VAL_3) + assign MUX_wci_4_respF$enq_1__VAL_1 = + (wci_4_wciResponse$wget[33:32] == 2'd0) ? + 34'h1C0DE4203 : + wci_4_wciResponse$wget ; + assign MUX_wci_4_respF$enq_1__VAL_2 = { 2'd1, wci_4_wStatus } ; + assign MUX_wci_4_respF$enq_1__VAL_3 = { 2'd1, x_data__h102999 } ; + assign MUX_wci_4_respF$enq_1__VAL_4 = { 2'd1, x_data__h103005 } ; + assign MUX_wci_4_respF$enq_1__VAL_5 = { 22'd1048576, wci_4_pageWindow } ; + assign MUX_wci_4_respTimr$write_1__VAL_2 = + (wci_4_wciResponse$wget[33:32] == 2'd0) ? + (wci_4_respTimr_88_ULT_1_SL_wci_4_wTimeout_89_90___d791 ? + x__h29331 : + 32'd0) : + 32'd0 ; + always@(wci_5_reqPend or wci_5_reqERR) begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_T_T: - MUX_wci_reqF_6_q_0$write_1__VAL_1 = - MUX_wci_reqF_6_x_wire$wset_1__VAL_1; - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_T_T: - MUX_wci_reqF_6_q_0$write_1__VAL_1 = - MUX_wci_reqF_6_x_wire$wset_1__VAL_2; - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_F_T_T: - MUX_wci_reqF_6_q_0$write_1__VAL_1 = - MUX_wci_reqF_10_x_wire$wset_1__VAL_3; - default: MUX_wci_reqF_6_q_0$write_1__VAL_1 = - 72'hAAAAAAAAAAAAAAAAAA /* unspecified value */ ; + case (wci_5_reqPend) + 2'd1: MUX_wci_5_reqERR$write_1__VAL_1 = { 1'd1, wci_5_reqERR[1:0] }; + 2'd2: + MUX_wci_5_reqERR$write_1__VAL_1 = + { wci_5_reqERR[2], 1'd1, wci_5_reqERR[0] }; + default: MUX_wci_5_reqERR$write_1__VAL_1 = { wci_5_reqERR[2:1], 1'd1 }; endcase end - assign MUX_wci_reqF_6_q_0$write_1__VAL_2 = - wci_reqF_6_c_r ? - MUX_wci_reqF_6_q_0$write_1__VAL_1 : - 72'h0000000000AAAAAAAA ; - assign MUX_wci_reqF_6_x_wire$wset_1__VAL_1 = - { 4'd3, cpReq[3:0], wciAddr__h77786, cpReq[59:28] } ; - assign MUX_wci_reqF_6_x_wire$wset_1__VAL_2 = - { 4'd5, cpReq[3:0], wciAddr__h77786, 32'hAAAAAAAA } ; - assign MUX_wci_reqF_7_c_r$write_1__VAL_1 = wci_reqF_7_c_r + 1'd1 ; - assign MUX_wci_reqF_7_c_r$write_1__VAL_2 = wci_reqF_7_c_r - 1'd1 ; - always@(WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_T_T or - MUX_wci_reqF_7_x_wire$wset_1__VAL_1 or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_T_T or - MUX_wci_reqF_7_x_wire$wset_1__VAL_2 or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T or - MUX_wci_reqF_10_x_wire$wset_1__VAL_3) + always@(wci_5_reqPend or wci_5_reqFAIL) begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_T_T: - MUX_wci_reqF_7_q_0$write_1__VAL_1 = - MUX_wci_reqF_7_x_wire$wset_1__VAL_1; - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_T_T: - MUX_wci_reqF_7_q_0$write_1__VAL_1 = - MUX_wci_reqF_7_x_wire$wset_1__VAL_2; - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T: - MUX_wci_reqF_7_q_0$write_1__VAL_1 = - MUX_wci_reqF_10_x_wire$wset_1__VAL_3; - default: MUX_wci_reqF_7_q_0$write_1__VAL_1 = - 72'hAAAAAAAAAAAAAAAAAA /* unspecified value */ ; + case (wci_5_reqPend) + 2'd1: MUX_wci_5_reqFAIL$write_1__VAL_1 = { 1'd1, wci_5_reqFAIL[1:0] }; + 2'd2: + MUX_wci_5_reqFAIL$write_1__VAL_1 = + { wci_5_reqFAIL[2], 1'd1, wci_5_reqFAIL[0] }; + default: MUX_wci_5_reqFAIL$write_1__VAL_1 = + { wci_5_reqFAIL[2:1], 1'd1 }; endcase end - assign MUX_wci_reqF_7_q_0$write_1__VAL_2 = - wci_reqF_7_c_r ? - MUX_wci_reqF_7_q_0$write_1__VAL_1 : + assign MUX_wci_5_reqF_cntr_r$write_1__VAL_1 = wci_5_reqF_cntr_r + 1'd1 ; + assign MUX_wci_5_reqF_cntr_r$write_1__VAL_2 = wci_5_reqF_cntr_r - 1'd1 ; + assign MUX_wci_5_reqF_q_0$write_1__VAL_1 = + wci_5_reqF_cntr_r ? + MUX_wci_5_reqF_q_0$write_1__VAL_2 : 72'h0000000000AAAAAAAA ; - assign MUX_wci_reqF_7_x_wire$wset_1__VAL_1 = - { 4'd3, cpReq[3:0], wciAddr__h77852, cpReq[59:28] } ; - assign MUX_wci_reqF_7_x_wire$wset_1__VAL_2 = - { 4'd5, cpReq[3:0], wciAddr__h77852, 32'hAAAAAAAA } ; - assign MUX_wci_reqF_8_c_r$write_1__VAL_1 = wci_reqF_8_c_r + 1'd1 ; - assign MUX_wci_reqF_8_c_r$write_1__VAL_2 = wci_reqF_8_c_r - 1'd1 ; - always@(WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_T_T or - MUX_wci_reqF_8_x_wire$wset_1__VAL_1 or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T or - MUX_wci_reqF_8_x_wire$wset_1__VAL_2 or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T or - MUX_wci_reqF_10_x_wire$wset_1__VAL_3) + always@(WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_T_T or + MUX_wci_0_reqF_x_wire$wset_1__VAL_1 or + WILL_FIRE_RL_cpDispatch_F_F_T_E5_T_T or + MUX_wci_5_reqF_x_wire$wset_1__VAL_2 or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_T_T or + MUX_wci_5_reqF_x_wire$wset_1__VAL_3) begin case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_T_T: - MUX_wci_reqF_8_q_0$write_1__VAL_1 = - MUX_wci_reqF_8_x_wire$wset_1__VAL_1; - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T: - MUX_wci_reqF_8_q_0$write_1__VAL_1 = - MUX_wci_reqF_8_x_wire$wset_1__VAL_2; - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T: - MUX_wci_reqF_8_q_0$write_1__VAL_1 = - MUX_wci_reqF_10_x_wire$wset_1__VAL_3; - default: MUX_wci_reqF_8_q_0$write_1__VAL_1 = + WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_T_T: + MUX_wci_5_reqF_q_0$write_1__VAL_2 = + MUX_wci_0_reqF_x_wire$wset_1__VAL_1; + WILL_FIRE_RL_cpDispatch_F_F_T_E5_T_T: + MUX_wci_5_reqF_q_0$write_1__VAL_2 = + MUX_wci_5_reqF_x_wire$wset_1__VAL_2; + WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_T_T: + MUX_wci_5_reqF_q_0$write_1__VAL_2 = + MUX_wci_5_reqF_x_wire$wset_1__VAL_3; + default: MUX_wci_5_reqF_q_0$write_1__VAL_2 = 72'hAAAAAAAAAAAAAAAAAA /* unspecified value */ ; endcase end - assign MUX_wci_reqF_8_q_0$write_1__VAL_2 = - wci_reqF_8_c_r ? - MUX_wci_reqF_8_q_0$write_1__VAL_1 : - 72'h0000000000AAAAAAAA ; - assign MUX_wci_reqF_8_x_wire$wset_1__VAL_1 = - { 4'd3, cpReq[3:0], wciAddr__h77918, cpReq[59:28] } ; - assign MUX_wci_reqF_8_x_wire$wset_1__VAL_2 = - { 4'd5, cpReq[3:0], wciAddr__h77918, 32'hAAAAAAAA } ; - assign MUX_wci_reqF_9_c_r$write_1__VAL_1 = wci_reqF_9_c_r + 1'd1 ; - assign MUX_wci_reqF_9_c_r$write_1__VAL_2 = wci_reqF_9_c_r - 1'd1 ; - always@(WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_T_T or - MUX_wci_reqF_9_x_wire$wset_1__VAL_1 or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T or - MUX_wci_reqF_9_x_wire$wset_1__VAL_2 or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T or - MUX_wci_reqF_10_x_wire$wset_1__VAL_3) + assign MUX_wci_5_reqF_x_wire$wset_1__VAL_2 = + { 4'd3, cpReq[3:0], wciAddr__h77377, cpReq[59:28] } ; + assign MUX_wci_5_reqF_x_wire$wset_1__VAL_3 = + { 4'd5, cpReq[3:0], wciAddr__h77377, 32'hAAAAAAAA } ; + always@(wci_5_reqPend or wci_5_reqTO) begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_T_T: - MUX_wci_reqF_9_q_0$write_1__VAL_1 = - MUX_wci_reqF_9_x_wire$wset_1__VAL_1; - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T: - MUX_wci_reqF_9_q_0$write_1__VAL_1 = - MUX_wci_reqF_9_x_wire$wset_1__VAL_2; - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T: - MUX_wci_reqF_9_q_0$write_1__VAL_1 = - MUX_wci_reqF_10_x_wire$wset_1__VAL_3; - default: MUX_wci_reqF_9_q_0$write_1__VAL_1 = - 72'hAAAAAAAAAAAAAAAAAA /* unspecified value */ ; + case (wci_5_reqPend) + 2'd1: MUX_wci_5_reqTO$write_1__VAL_1 = { 1'd1, wci_5_reqTO[1:0] }; + 2'd2: + MUX_wci_5_reqTO$write_1__VAL_1 = + { wci_5_reqTO[2], 1'd1, wci_5_reqTO[0] }; + default: MUX_wci_5_reqTO$write_1__VAL_1 = { wci_5_reqTO[2:1], 1'd1 }; endcase end - assign MUX_wci_reqF_9_q_0$write_1__VAL_2 = - wci_reqF_9_c_r ? - MUX_wci_reqF_9_q_0$write_1__VAL_1 : - 72'h0000000000AAAAAAAA ; - assign MUX_wci_reqF_9_x_wire$wset_1__VAL_1 = - { 4'd3, cpReq[3:0], wciAddr__h77984, cpReq[59:28] } ; - assign MUX_wci_reqF_9_x_wire$wset_1__VAL_2 = - { 4'd5, cpReq[3:0], wciAddr__h77984, 32'hAAAAAAAA } ; - assign MUX_wci_reqF_c_r$write_1__VAL_1 = wci_reqF_c_r + 1'd1 ; - assign MUX_wci_reqF_c_r$write_1__VAL_2 = wci_reqF_c_r - 1'd1 ; - assign MUX_wci_reqF_q_0$write_1__VAL_1 = - wci_reqF_c_r ? - MUX_wci_reqF_q_0$write_1__VAL_2 : - 72'h0000000000AAAAAAAA ; - always@(WILL_FIRE_RL_cpDispatch_F_F_T_T_T_T or - MUX_wci_reqF_x_wire$wset_1__VAL_1 or - WILL_FIRE_RL_cpDispatch_F_F_F_F_T_T_T or - MUX_wci_reqF_x_wire$wset_1__VAL_2 or - WILL_FIRE_RL_cpDispatch_F_F_F_F_T_F_T_T or - MUX_wci_reqF_10_x_wire$wset_1__VAL_3) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_cpDispatch_F_F_T_T_T_T: - MUX_wci_reqF_q_0$write_1__VAL_2 = MUX_wci_reqF_x_wire$wset_1__VAL_1; - WILL_FIRE_RL_cpDispatch_F_F_F_F_T_T_T: - MUX_wci_reqF_q_0$write_1__VAL_2 = MUX_wci_reqF_x_wire$wset_1__VAL_2; - WILL_FIRE_RL_cpDispatch_F_F_F_F_T_F_T_T: - MUX_wci_reqF_q_0$write_1__VAL_2 = - MUX_wci_reqF_10_x_wire$wset_1__VAL_3; - default: MUX_wci_reqF_q_0$write_1__VAL_2 = - 72'hAAAAAAAAAAAAAAAAAA /* unspecified value */ ; + assign MUX_wci_5_respF$enq_1__VAL_1 = + (wci_5_wciResponse$wget[33:32] == 2'd0) ? + 34'h1C0DE4203 : + wci_5_wciResponse$wget ; + assign MUX_wci_5_respF$enq_1__VAL_2 = { 2'd1, wci_5_wStatus } ; + assign MUX_wci_5_respF$enq_1__VAL_3 = { 2'd1, x_data__h103050 } ; + assign MUX_wci_5_respF$enq_1__VAL_4 = { 2'd1, x_data__h103056 } ; + assign MUX_wci_5_respF$enq_1__VAL_5 = { 22'd1048576, wci_5_pageWindow } ; + assign MUX_wci_5_respTimr$write_1__VAL_2 = + (wci_5_wciResponse$wget[33:32] == 2'd0) ? + (wci_5_respTimr_28_ULT_1_SL_wci_5_wTimeout_29_30___d931 ? + x__h33700 : + 32'd0) : + 32'd0 ; + always@(wci_6_reqPend or wci_6_reqERR) + begin + case (wci_6_reqPend) + 2'd1: MUX_wci_6_reqERR$write_1__VAL_1 = { 1'd1, wci_6_reqERR[1:0] }; + 2'd2: + MUX_wci_6_reqERR$write_1__VAL_1 = + { wci_6_reqERR[2], 1'd1, wci_6_reqERR[0] }; + default: MUX_wci_6_reqERR$write_1__VAL_1 = { wci_6_reqERR[2:1], 1'd1 }; endcase end - assign MUX_wci_reqF_x_wire$wset_1__VAL_1 = - { 4'd3, cpReq[3:0], wciAddr__h77388, cpReq[59:28] } ; - assign MUX_wci_reqF_x_wire$wset_1__VAL_2 = - { 4'd5, cpReq[3:0], wciAddr__h77388, 32'hAAAAAAAA } ; - always@(wci_reqPend or wci_reqTO) + always@(wci_6_reqPend or wci_6_reqFAIL) begin - case (wci_reqPend) - 2'd1: MUX_wci_reqTO$write_1__VAL_1 = { 1'd1, wci_reqTO[1:0] }; + case (wci_6_reqPend) + 2'd1: MUX_wci_6_reqFAIL$write_1__VAL_1 = { 1'd1, wci_6_reqFAIL[1:0] }; 2'd2: - MUX_wci_reqTO$write_1__VAL_1 = { wci_reqTO[2], 1'd1, wci_reqTO[0] }; - default: MUX_wci_reqTO$write_1__VAL_1 = { wci_reqTO[2:1], 1'd1 }; + MUX_wci_6_reqFAIL$write_1__VAL_1 = + { wci_6_reqFAIL[2], 1'd1, wci_6_reqFAIL[0] }; + default: MUX_wci_6_reqFAIL$write_1__VAL_1 = + { wci_6_reqFAIL[2:1], 1'd1 }; endcase end - always@(wci_reqPend_1 or wci_reqTO_1) + assign MUX_wci_6_reqF_cntr_r$write_1__VAL_1 = wci_6_reqF_cntr_r + 1'd1 ; + assign MUX_wci_6_reqF_cntr_r$write_1__VAL_2 = wci_6_reqF_cntr_r - 1'd1 ; + assign MUX_wci_6_reqF_q_0$write_1__VAL_1 = + wci_6_reqF_cntr_r ? + MUX_wci_6_reqF_q_0$write_1__VAL_2 : + 72'h0000000000AAAAAAAA ; + always@(WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_F_T_T or + MUX_wci_0_reqF_x_wire$wset_1__VAL_1 or + WILL_FIRE_RL_cpDispatch_F_F_T_E6_T_T or + MUX_wci_6_reqF_x_wire$wset_1__VAL_2 or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_T_T or + MUX_wci_6_reqF_x_wire$wset_1__VAL_3) begin - case (wci_reqPend_1) - 2'd1: MUX_wci_reqTO_1$write_1__VAL_1 = { 1'd1, wci_reqTO_1[1:0] }; - 2'd2: - MUX_wci_reqTO_1$write_1__VAL_1 = - { wci_reqTO_1[2], 1'd1, wci_reqTO_1[0] }; - default: MUX_wci_reqTO_1$write_1__VAL_1 = { wci_reqTO_1[2:1], 1'd1 }; + case (1'b1) // synopsys parallel_case + WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_F_T_T: + MUX_wci_6_reqF_q_0$write_1__VAL_2 = + MUX_wci_0_reqF_x_wire$wset_1__VAL_1; + WILL_FIRE_RL_cpDispatch_F_F_T_E6_T_T: + MUX_wci_6_reqF_q_0$write_1__VAL_2 = + MUX_wci_6_reqF_x_wire$wset_1__VAL_2; + WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_T_T: + MUX_wci_6_reqF_q_0$write_1__VAL_2 = + MUX_wci_6_reqF_x_wire$wset_1__VAL_3; + default: MUX_wci_6_reqF_q_0$write_1__VAL_2 = + 72'hAAAAAAAAAAAAAAAAAA /* unspecified value */ ; endcase end - always@(wci_reqPend_10 or wci_reqTO_10) + assign MUX_wci_6_reqF_x_wire$wset_1__VAL_2 = + { 4'd3, cpReq[3:0], wciAddr__h77445, cpReq[59:28] } ; + assign MUX_wci_6_reqF_x_wire$wset_1__VAL_3 = + { 4'd5, cpReq[3:0], wciAddr__h77445, 32'hAAAAAAAA } ; + always@(wci_6_reqPend or wci_6_reqTO) begin - case (wci_reqPend_10) - 2'd1: MUX_wci_reqTO_10$write_1__VAL_1 = { 1'd1, wci_reqTO_10[1:0] }; + case (wci_6_reqPend) + 2'd1: MUX_wci_6_reqTO$write_1__VAL_1 = { 1'd1, wci_6_reqTO[1:0] }; 2'd2: - MUX_wci_reqTO_10$write_1__VAL_1 = - { wci_reqTO_10[2], 1'd1, wci_reqTO_10[0] }; - default: MUX_wci_reqTO_10$write_1__VAL_1 = { wci_reqTO_10[2:1], 1'd1 }; + MUX_wci_6_reqTO$write_1__VAL_1 = + { wci_6_reqTO[2], 1'd1, wci_6_reqTO[0] }; + default: MUX_wci_6_reqTO$write_1__VAL_1 = { wci_6_reqTO[2:1], 1'd1 }; endcase end - always@(wci_reqPend_11 or wci_reqTO_11) + assign MUX_wci_6_respF$enq_1__VAL_1 = + (wci_6_wciResponse$wget[33:32] == 2'd0) ? + 34'h1C0DE4203 : + wci_6_wciResponse$wget ; + assign MUX_wci_6_respF$enq_1__VAL_2 = { 2'd1, wci_6_wStatus } ; + assign MUX_wci_6_respF$enq_1__VAL_3 = { 2'd1, x_data__h103101 } ; + assign MUX_wci_6_respF$enq_1__VAL_4 = { 2'd1, x_data__h103107 } ; + assign MUX_wci_6_respF$enq_1__VAL_5 = { 22'd1048576, wci_6_pageWindow } ; + assign MUX_wci_6_respTimr$write_1__VAL_2 = + (wci_6_wciResponse$wget[33:32] == 2'd0) ? + (wci_6_respTimr_068_ULT_1_SL_wci_6_wTimeout_069_ETC___d1071 ? + x__h38069 : + 32'd0) : + 32'd0 ; + always@(wci_7_reqPend or wci_7_reqERR) begin - case (wci_reqPend_11) - 2'd1: MUX_wci_reqTO_11$write_1__VAL_1 = { 1'd1, wci_reqTO_11[1:0] }; + case (wci_7_reqPend) + 2'd1: MUX_wci_7_reqERR$write_1__VAL_1 = { 1'd1, wci_7_reqERR[1:0] }; 2'd2: - MUX_wci_reqTO_11$write_1__VAL_1 = - { wci_reqTO_11[2], 1'd1, wci_reqTO_11[0] }; - default: MUX_wci_reqTO_11$write_1__VAL_1 = { wci_reqTO_11[2:1], 1'd1 }; + MUX_wci_7_reqERR$write_1__VAL_1 = + { wci_7_reqERR[2], 1'd1, wci_7_reqERR[0] }; + default: MUX_wci_7_reqERR$write_1__VAL_1 = { wci_7_reqERR[2:1], 1'd1 }; endcase end - always@(wci_reqPend_12 or wci_reqTO_12) + always@(wci_7_reqPend or wci_7_reqFAIL) begin - case (wci_reqPend_12) - 2'd1: MUX_wci_reqTO_12$write_1__VAL_1 = { 1'd1, wci_reqTO_12[1:0] }; + case (wci_7_reqPend) + 2'd1: MUX_wci_7_reqFAIL$write_1__VAL_1 = { 1'd1, wci_7_reqFAIL[1:0] }; 2'd2: - MUX_wci_reqTO_12$write_1__VAL_1 = - { wci_reqTO_12[2], 1'd1, wci_reqTO_12[0] }; - default: MUX_wci_reqTO_12$write_1__VAL_1 = { wci_reqTO_12[2:1], 1'd1 }; + MUX_wci_7_reqFAIL$write_1__VAL_1 = + { wci_7_reqFAIL[2], 1'd1, wci_7_reqFAIL[0] }; + default: MUX_wci_7_reqFAIL$write_1__VAL_1 = + { wci_7_reqFAIL[2:1], 1'd1 }; endcase end - always@(wci_reqPend_13 or wci_reqTO_13) + assign MUX_wci_7_reqF_cntr_r$write_1__VAL_1 = wci_7_reqF_cntr_r + 1'd1 ; + assign MUX_wci_7_reqF_cntr_r$write_1__VAL_2 = wci_7_reqF_cntr_r - 1'd1 ; + assign MUX_wci_7_reqF_q_0$write_1__VAL_1 = + wci_7_reqF_cntr_r ? + MUX_wci_7_reqF_q_0$write_1__VAL_2 : + 72'h0000000000AAAAAAAA ; + always@(WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_T_T or + MUX_wci_0_reqF_x_wire$wset_1__VAL_1 or + WILL_FIRE_RL_cpDispatch_F_F_T_E7_T_T or + MUX_wci_7_reqF_x_wire$wset_1__VAL_2 or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_T_T or + MUX_wci_7_reqF_x_wire$wset_1__VAL_3) begin - case (wci_reqPend_13) - 2'd1: MUX_wci_reqTO_13$write_1__VAL_1 = { 1'd1, wci_reqTO_13[1:0] }; - 2'd2: - MUX_wci_reqTO_13$write_1__VAL_1 = - { wci_reqTO_13[2], 1'd1, wci_reqTO_13[0] }; - default: MUX_wci_reqTO_13$write_1__VAL_1 = { wci_reqTO_13[2:1], 1'd1 }; + case (1'b1) // synopsys parallel_case + WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_T_T: + MUX_wci_7_reqF_q_0$write_1__VAL_2 = + MUX_wci_0_reqF_x_wire$wset_1__VAL_1; + WILL_FIRE_RL_cpDispatch_F_F_T_E7_T_T: + MUX_wci_7_reqF_q_0$write_1__VAL_2 = + MUX_wci_7_reqF_x_wire$wset_1__VAL_2; + WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_T_T: + MUX_wci_7_reqF_q_0$write_1__VAL_2 = + MUX_wci_7_reqF_x_wire$wset_1__VAL_3; + default: MUX_wci_7_reqF_q_0$write_1__VAL_2 = + 72'hAAAAAAAAAAAAAAAAAA /* unspecified value */ ; endcase end - always@(wci_reqPend_14 or wci_reqTO_14) + assign MUX_wci_7_reqF_x_wire$wset_1__VAL_2 = + { 4'd3, cpReq[3:0], wciAddr__h77513, cpReq[59:28] } ; + assign MUX_wci_7_reqF_x_wire$wset_1__VAL_3 = + { 4'd5, cpReq[3:0], wciAddr__h77513, 32'hAAAAAAAA } ; + always@(wci_7_reqPend or wci_7_reqTO) begin - case (wci_reqPend_14) - 2'd1: MUX_wci_reqTO_14$write_1__VAL_1 = { 1'd1, wci_reqTO_14[1:0] }; + case (wci_7_reqPend) + 2'd1: MUX_wci_7_reqTO$write_1__VAL_1 = { 1'd1, wci_7_reqTO[1:0] }; 2'd2: - MUX_wci_reqTO_14$write_1__VAL_1 = - { wci_reqTO_14[2], 1'd1, wci_reqTO_14[0] }; - default: MUX_wci_reqTO_14$write_1__VAL_1 = { wci_reqTO_14[2:1], 1'd1 }; + MUX_wci_7_reqTO$write_1__VAL_1 = + { wci_7_reqTO[2], 1'd1, wci_7_reqTO[0] }; + default: MUX_wci_7_reqTO$write_1__VAL_1 = { wci_7_reqTO[2:1], 1'd1 }; endcase end - always@(wci_reqPend_2 or wci_reqTO_2) + assign MUX_wci_7_respF$enq_1__VAL_1 = + (wci_7_wciResponse$wget[33:32] == 2'd0) ? + 34'h1C0DE4203 : + wci_7_wciResponse$wget ; + assign MUX_wci_7_respF$enq_1__VAL_2 = { 2'd1, wci_7_wStatus } ; + assign MUX_wci_7_respF$enq_1__VAL_3 = { 2'd1, x_data__h103152 } ; + assign MUX_wci_7_respF$enq_1__VAL_4 = { 2'd1, x_data__h103158 } ; + assign MUX_wci_7_respF$enq_1__VAL_5 = { 22'd1048576, wci_7_pageWindow } ; + assign MUX_wci_7_respTimr$write_1__VAL_2 = + (wci_7_wciResponse$wget[33:32] == 2'd0) ? + (wci_7_respTimr_208_ULT_1_SL_wci_7_wTimeout_209_ETC___d1211 ? + x__h42438 : + 32'd0) : + 32'd0 ; + always@(wci_8_reqPend or wci_8_reqERR) begin - case (wci_reqPend_2) - 2'd1: MUX_wci_reqTO_2$write_1__VAL_1 = { 1'd1, wci_reqTO_2[1:0] }; + case (wci_8_reqPend) + 2'd1: MUX_wci_8_reqERR$write_1__VAL_1 = { 1'd1, wci_8_reqERR[1:0] }; 2'd2: - MUX_wci_reqTO_2$write_1__VAL_1 = - { wci_reqTO_2[2], 1'd1, wci_reqTO_2[0] }; - default: MUX_wci_reqTO_2$write_1__VAL_1 = { wci_reqTO_2[2:1], 1'd1 }; + MUX_wci_8_reqERR$write_1__VAL_1 = + { wci_8_reqERR[2], 1'd1, wci_8_reqERR[0] }; + default: MUX_wci_8_reqERR$write_1__VAL_1 = { wci_8_reqERR[2:1], 1'd1 }; endcase end - always@(wci_reqPend_3 or wci_reqTO_3) + always@(wci_8_reqPend or wci_8_reqFAIL) begin - case (wci_reqPend_3) - 2'd1: MUX_wci_reqTO_3$write_1__VAL_1 = { 1'd1, wci_reqTO_3[1:0] }; + case (wci_8_reqPend) + 2'd1: MUX_wci_8_reqFAIL$write_1__VAL_1 = { 1'd1, wci_8_reqFAIL[1:0] }; 2'd2: - MUX_wci_reqTO_3$write_1__VAL_1 = - { wci_reqTO_3[2], 1'd1, wci_reqTO_3[0] }; - default: MUX_wci_reqTO_3$write_1__VAL_1 = { wci_reqTO_3[2:1], 1'd1 }; + MUX_wci_8_reqFAIL$write_1__VAL_1 = + { wci_8_reqFAIL[2], 1'd1, wci_8_reqFAIL[0] }; + default: MUX_wci_8_reqFAIL$write_1__VAL_1 = + { wci_8_reqFAIL[2:1], 1'd1 }; endcase end - always@(wci_reqPend_4 or wci_reqTO_4) + assign MUX_wci_8_reqF_cntr_r$write_1__VAL_1 = wci_8_reqF_cntr_r + 1'd1 ; + assign MUX_wci_8_reqF_cntr_r$write_1__VAL_2 = wci_8_reqF_cntr_r - 1'd1 ; + assign MUX_wci_8_reqF_q_0$write_1__VAL_1 = + wci_8_reqF_cntr_r ? + MUX_wci_8_reqF_q_0$write_1__VAL_2 : + 72'h0000000000AAAAAAAA ; + always@(WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_T_T or + MUX_wci_0_reqF_x_wire$wset_1__VAL_1 or + WILL_FIRE_RL_cpDispatch_F_F_T_E8_T_T or + MUX_wci_8_reqF_x_wire$wset_1__VAL_2 or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_T_T or + MUX_wci_8_reqF_x_wire$wset_1__VAL_3) begin - case (wci_reqPend_4) - 2'd1: MUX_wci_reqTO_4$write_1__VAL_1 = { 1'd1, wci_reqTO_4[1:0] }; - 2'd2: - MUX_wci_reqTO_4$write_1__VAL_1 = - { wci_reqTO_4[2], 1'd1, wci_reqTO_4[0] }; - default: MUX_wci_reqTO_4$write_1__VAL_1 = { wci_reqTO_4[2:1], 1'd1 }; + case (1'b1) // synopsys parallel_case + WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_T_T: + MUX_wci_8_reqF_q_0$write_1__VAL_2 = + MUX_wci_0_reqF_x_wire$wset_1__VAL_1; + WILL_FIRE_RL_cpDispatch_F_F_T_E8_T_T: + MUX_wci_8_reqF_q_0$write_1__VAL_2 = + MUX_wci_8_reqF_x_wire$wset_1__VAL_2; + WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_T_T: + MUX_wci_8_reqF_q_0$write_1__VAL_2 = + MUX_wci_8_reqF_x_wire$wset_1__VAL_3; + default: MUX_wci_8_reqF_q_0$write_1__VAL_2 = + 72'hAAAAAAAAAAAAAAAAAA /* unspecified value */ ; endcase end - always@(wci_reqPend_5 or wci_reqTO_5) + assign MUX_wci_8_reqF_x_wire$wset_1__VAL_2 = + { 4'd3, cpReq[3:0], wciAddr__h77581, cpReq[59:28] } ; + assign MUX_wci_8_reqF_x_wire$wset_1__VAL_3 = + { 4'd5, cpReq[3:0], wciAddr__h77581, 32'hAAAAAAAA } ; + always@(wci_8_reqPend or wci_8_reqTO) begin - case (wci_reqPend_5) - 2'd1: MUX_wci_reqTO_5$write_1__VAL_1 = { 1'd1, wci_reqTO_5[1:0] }; + case (wci_8_reqPend) + 2'd1: MUX_wci_8_reqTO$write_1__VAL_1 = { 1'd1, wci_8_reqTO[1:0] }; 2'd2: - MUX_wci_reqTO_5$write_1__VAL_1 = - { wci_reqTO_5[2], 1'd1, wci_reqTO_5[0] }; - default: MUX_wci_reqTO_5$write_1__VAL_1 = { wci_reqTO_5[2:1], 1'd1 }; + MUX_wci_8_reqTO$write_1__VAL_1 = + { wci_8_reqTO[2], 1'd1, wci_8_reqTO[0] }; + default: MUX_wci_8_reqTO$write_1__VAL_1 = { wci_8_reqTO[2:1], 1'd1 }; endcase end - always@(wci_reqPend_6 or wci_reqTO_6) + assign MUX_wci_8_respF$enq_1__VAL_1 = + (wci_8_wciResponse$wget[33:32] == 2'd0) ? + 34'h1C0DE4203 : + wci_8_wciResponse$wget ; + assign MUX_wci_8_respF$enq_1__VAL_2 = { 2'd1, wci_8_wStatus } ; + assign MUX_wci_8_respF$enq_1__VAL_3 = { 2'd1, x_data__h103203 } ; + assign MUX_wci_8_respF$enq_1__VAL_4 = { 2'd1, x_data__h103209 } ; + assign MUX_wci_8_respF$enq_1__VAL_5 = { 22'd1048576, wci_8_pageWindow } ; + assign MUX_wci_8_respTimr$write_1__VAL_2 = + (wci_8_wciResponse$wget[33:32] == 2'd0) ? + (wci_8_respTimr_348_ULT_1_SL_wci_8_wTimeout_349_ETC___d1351 ? + x__h46807 : + 32'd0) : + 32'd0 ; + always@(wci_9_reqPend or wci_9_reqERR) begin - case (wci_reqPend_6) - 2'd1: MUX_wci_reqTO_6$write_1__VAL_1 = { 1'd1, wci_reqTO_6[1:0] }; + case (wci_9_reqPend) + 2'd1: MUX_wci_9_reqERR$write_1__VAL_1 = { 1'd1, wci_9_reqERR[1:0] }; 2'd2: - MUX_wci_reqTO_6$write_1__VAL_1 = - { wci_reqTO_6[2], 1'd1, wci_reqTO_6[0] }; - default: MUX_wci_reqTO_6$write_1__VAL_1 = { wci_reqTO_6[2:1], 1'd1 }; + MUX_wci_9_reqERR$write_1__VAL_1 = + { wci_9_reqERR[2], 1'd1, wci_9_reqERR[0] }; + default: MUX_wci_9_reqERR$write_1__VAL_1 = { wci_9_reqERR[2:1], 1'd1 }; endcase end - always@(wci_reqPend_7 or wci_reqTO_7) + always@(wci_9_reqPend or wci_9_reqFAIL) begin - case (wci_reqPend_7) - 2'd1: MUX_wci_reqTO_7$write_1__VAL_1 = { 1'd1, wci_reqTO_7[1:0] }; + case (wci_9_reqPend) + 2'd1: MUX_wci_9_reqFAIL$write_1__VAL_1 = { 1'd1, wci_9_reqFAIL[1:0] }; 2'd2: - MUX_wci_reqTO_7$write_1__VAL_1 = - { wci_reqTO_7[2], 1'd1, wci_reqTO_7[0] }; - default: MUX_wci_reqTO_7$write_1__VAL_1 = { wci_reqTO_7[2:1], 1'd1 }; + MUX_wci_9_reqFAIL$write_1__VAL_1 = + { wci_9_reqFAIL[2], 1'd1, wci_9_reqFAIL[0] }; + default: MUX_wci_9_reqFAIL$write_1__VAL_1 = + { wci_9_reqFAIL[2:1], 1'd1 }; endcase end - always@(wci_reqPend_8 or wci_reqTO_8) + assign MUX_wci_9_reqF_cntr_r$write_1__VAL_1 = wci_9_reqF_cntr_r + 1'd1 ; + assign MUX_wci_9_reqF_cntr_r$write_1__VAL_2 = wci_9_reqF_cntr_r - 1'd1 ; + assign MUX_wci_9_reqF_q_0$write_1__VAL_1 = + wci_9_reqF_cntr_r ? + MUX_wci_9_reqF_q_0$write_1__VAL_2 : + 72'h0000000000AAAAAAAA ; + always@(WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_F_T_T or + MUX_wci_0_reqF_x_wire$wset_1__VAL_1 or + WILL_FIRE_RL_cpDispatch_F_F_T_E9_T_T or + MUX_wci_9_reqF_x_wire$wset_1__VAL_2 or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_T_T or + MUX_wci_9_reqF_x_wire$wset_1__VAL_3) begin - case (wci_reqPend_8) - 2'd1: MUX_wci_reqTO_8$write_1__VAL_1 = { 1'd1, wci_reqTO_8[1:0] }; - 2'd2: - MUX_wci_reqTO_8$write_1__VAL_1 = - { wci_reqTO_8[2], 1'd1, wci_reqTO_8[0] }; - default: MUX_wci_reqTO_8$write_1__VAL_1 = { wci_reqTO_8[2:1], 1'd1 }; + case (1'b1) // synopsys parallel_case + WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_F_T_T: + MUX_wci_9_reqF_q_0$write_1__VAL_2 = + MUX_wci_0_reqF_x_wire$wset_1__VAL_1; + WILL_FIRE_RL_cpDispatch_F_F_T_E9_T_T: + MUX_wci_9_reqF_q_0$write_1__VAL_2 = + MUX_wci_9_reqF_x_wire$wset_1__VAL_2; + WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_T_T: + MUX_wci_9_reqF_q_0$write_1__VAL_2 = + MUX_wci_9_reqF_x_wire$wset_1__VAL_3; + default: MUX_wci_9_reqF_q_0$write_1__VAL_2 = + 72'hAAAAAAAAAAAAAAAAAA /* unspecified value */ ; endcase end - always@(wci_reqPend_9 or wci_reqTO_9) + assign MUX_wci_9_reqF_x_wire$wset_1__VAL_2 = + { 4'd3, cpReq[3:0], wciAddr__h77649, cpReq[59:28] } ; + assign MUX_wci_9_reqF_x_wire$wset_1__VAL_3 = + { 4'd5, cpReq[3:0], wciAddr__h77649, 32'hAAAAAAAA } ; + always@(wci_9_reqPend or wci_9_reqTO) begin - case (wci_reqPend_9) - 2'd1: MUX_wci_reqTO_9$write_1__VAL_1 = { 1'd1, wci_reqTO_9[1:0] }; + case (wci_9_reqPend) + 2'd1: MUX_wci_9_reqTO$write_1__VAL_1 = { 1'd1, wci_9_reqTO[1:0] }; 2'd2: - MUX_wci_reqTO_9$write_1__VAL_1 = - { wci_reqTO_9[2], 1'd1, wci_reqTO_9[0] }; - default: MUX_wci_reqTO_9$write_1__VAL_1 = { wci_reqTO_9[2:1], 1'd1 }; + MUX_wci_9_reqTO$write_1__VAL_1 = + { wci_9_reqTO[2], 1'd1, wci_9_reqTO[0] }; + default: MUX_wci_9_reqTO$write_1__VAL_1 = { wci_9_reqTO[2:1], 1'd1 }; endcase end - assign MUX_wci_respF$enq_1__VAL_1 = - (wci_wciResponse$wget[33:32] == 2'd0) ? + assign MUX_wci_9_respF$enq_1__VAL_1 = + (wci_9_wciResponse$wget[33:32] == 2'd0) ? 34'h1C0DE4203 : - wci_wciResponse$wget ; - assign MUX_wci_respF$enq_1__VAL_2 = { 2'd1, wci_wStatus } ; - assign MUX_wci_respF$enq_1__VAL_3 = { 2'd1, x_data__h103818 } ; - assign MUX_wci_respF$enq_1__VAL_4 = { 2'd1, x_data__h103824 } ; - assign MUX_wci_respF$enq_1__VAL_5 = { 22'd1048576, wci_pageWindow } ; - assign MUX_wci_respF_1$enq_1__VAL_1 = - (wci_wciResponse_1$wget[33:32] == 2'd0) ? - 34'h1C0DE4203 : - wci_wciResponse_1$wget ; - assign MUX_wci_respF_1$enq_1__VAL_2 = { 2'd1, wci_wStatus_1 } ; - assign MUX_wci_respF_1$enq_1__VAL_3 = { 2'd1, x_data__h103871 } ; - assign MUX_wci_respF_1$enq_1__VAL_4 = { 2'd1, x_data__h103877 } ; - assign MUX_wci_respF_1$enq_1__VAL_5 = { 22'd1048576, wci_pageWindow_1 } ; - assign MUX_wci_respF_10$enq_1__VAL_1 = - (wci_wciResponse_10$wget[33:32] == 2'd0) ? - 34'h1C0DE4203 : - wci_wciResponse_10$wget ; - assign MUX_wci_respF_10$enq_1__VAL_2 = { 2'd1, wci_wStatus_10 } ; - assign MUX_wci_respF_10$enq_1__VAL_3 = { 2'd1, x_data__h104348 } ; - assign MUX_wci_respF_10$enq_1__VAL_4 = { 2'd1, x_data__h104354 } ; - assign MUX_wci_respF_10$enq_1__VAL_5 = { 22'd1048576, wci_pageWindow_10 } ; - assign MUX_wci_respF_11$enq_1__VAL_1 = - (wci_wciResponse_11$wget[33:32] == 2'd0) ? - 34'h1C0DE4203 : - wci_wciResponse_11$wget ; - assign MUX_wci_respF_11$enq_1__VAL_2 = { 2'd1, wci_wStatus_11 } ; - assign MUX_wci_respF_11$enq_1__VAL_3 = { 2'd1, x_data__h104401 } ; - assign MUX_wci_respF_11$enq_1__VAL_4 = { 2'd1, x_data__h104407 } ; - assign MUX_wci_respF_11$enq_1__VAL_5 = { 22'd1048576, wci_pageWindow_11 } ; - assign MUX_wci_respF_12$enq_1__VAL_1 = - (wci_wciResponse_12$wget[33:32] == 2'd0) ? - 34'h1C0DE4203 : - wci_wciResponse_12$wget ; - assign MUX_wci_respF_12$enq_1__VAL_2 = { 2'd1, wci_wStatus_12 } ; - assign MUX_wci_respF_12$enq_1__VAL_3 = { 2'd1, x_data__h104454 } ; - assign MUX_wci_respF_12$enq_1__VAL_4 = { 2'd1, x_data__h104460 } ; - assign MUX_wci_respF_12$enq_1__VAL_5 = { 22'd1048576, wci_pageWindow_12 } ; - assign MUX_wci_respF_13$enq_1__VAL_1 = - (wci_wciResponse_13$wget[33:32] == 2'd0) ? - 34'h1C0DE4203 : - wci_wciResponse_13$wget ; - assign MUX_wci_respF_13$enq_1__VAL_2 = { 2'd1, wci_wStatus_13 } ; - assign MUX_wci_respF_13$enq_1__VAL_3 = { 2'd1, x_data__h104507 } ; - assign MUX_wci_respF_13$enq_1__VAL_4 = { 2'd1, x_data__h104513 } ; - assign MUX_wci_respF_13$enq_1__VAL_5 = { 22'd1048576, wci_pageWindow_13 } ; - assign MUX_wci_respF_14$enq_1__VAL_1 = - (wci_wciResponse_14$wget[33:32] == 2'd0) ? - 34'h1C0DE4203 : - wci_wciResponse_14$wget ; - assign MUX_wci_respF_14$enq_1__VAL_2 = { 2'd1, wci_wStatus_14 } ; - assign MUX_wci_respF_14$enq_1__VAL_3 = { 2'd1, x_data__h104560 } ; - assign MUX_wci_respF_14$enq_1__VAL_4 = { 2'd1, x_data__h104566 } ; - assign MUX_wci_respF_14$enq_1__VAL_5 = { 22'd1048576, wci_pageWindow_14 } ; - assign MUX_wci_respF_2$enq_1__VAL_1 = - (wci_wciResponse_2$wget[33:32] == 2'd0) ? - 34'h1C0DE4203 : - wci_wciResponse_2$wget ; - assign MUX_wci_respF_2$enq_1__VAL_2 = { 2'd1, wci_wStatus_2 } ; - assign MUX_wci_respF_2$enq_1__VAL_3 = { 2'd1, x_data__h103924 } ; - assign MUX_wci_respF_2$enq_1__VAL_4 = { 2'd1, x_data__h103930 } ; - assign MUX_wci_respF_2$enq_1__VAL_5 = { 22'd1048576, wci_pageWindow_2 } ; - assign MUX_wci_respF_3$enq_1__VAL_1 = - (wci_wciResponse_3$wget[33:32] == 2'd0) ? - 34'h1C0DE4203 : - wci_wciResponse_3$wget ; - assign MUX_wci_respF_3$enq_1__VAL_2 = { 2'd1, wci_wStatus_3 } ; - assign MUX_wci_respF_3$enq_1__VAL_3 = { 2'd1, x_data__h103977 } ; - assign MUX_wci_respF_3$enq_1__VAL_4 = { 2'd1, x_data__h103983 } ; - assign MUX_wci_respF_3$enq_1__VAL_5 = { 22'd1048576, wci_pageWindow_3 } ; - assign MUX_wci_respF_4$enq_1__VAL_1 = - (wci_wciResponse_4$wget[33:32] == 2'd0) ? - 34'h1C0DE4203 : - wci_wciResponse_4$wget ; - assign MUX_wci_respF_4$enq_1__VAL_2 = { 2'd1, wci_wStatus_4 } ; - assign MUX_wci_respF_4$enq_1__VAL_3 = { 2'd1, x_data__h104030 } ; - assign MUX_wci_respF_4$enq_1__VAL_4 = { 2'd1, x_data__h104036 } ; - assign MUX_wci_respF_4$enq_1__VAL_5 = { 22'd1048576, wci_pageWindow_4 } ; - assign MUX_wci_respF_5$enq_1__VAL_1 = - (wci_wciResponse_5$wget[33:32] == 2'd0) ? - 34'h1C0DE4203 : - wci_wciResponse_5$wget ; - assign MUX_wci_respF_5$enq_1__VAL_2 = { 2'd1, wci_wStatus_5 } ; - assign MUX_wci_respF_5$enq_1__VAL_3 = { 2'd1, x_data__h104083 } ; - assign MUX_wci_respF_5$enq_1__VAL_4 = { 2'd1, x_data__h104089 } ; - assign MUX_wci_respF_5$enq_1__VAL_5 = { 22'd1048576, wci_pageWindow_5 } ; - assign MUX_wci_respF_6$enq_1__VAL_1 = - (wci_wciResponse_6$wget[33:32] == 2'd0) ? - 34'h1C0DE4203 : - wci_wciResponse_6$wget ; - assign MUX_wci_respF_6$enq_1__VAL_2 = { 2'd1, wci_wStatus_6 } ; - assign MUX_wci_respF_6$enq_1__VAL_3 = { 2'd1, x_data__h104136 } ; - assign MUX_wci_respF_6$enq_1__VAL_4 = { 2'd1, x_data__h104142 } ; - assign MUX_wci_respF_6$enq_1__VAL_5 = { 22'd1048576, wci_pageWindow_6 } ; - assign MUX_wci_respF_7$enq_1__VAL_1 = - (wci_wciResponse_7$wget[33:32] == 2'd0) ? - 34'h1C0DE4203 : - wci_wciResponse_7$wget ; - assign MUX_wci_respF_7$enq_1__VAL_2 = { 2'd1, wci_wStatus_7 } ; - assign MUX_wci_respF_7$enq_1__VAL_3 = { 2'd1, x_data__h104189 } ; - assign MUX_wci_respF_7$enq_1__VAL_4 = { 2'd1, x_data__h104195 } ; - assign MUX_wci_respF_7$enq_1__VAL_5 = { 22'd1048576, wci_pageWindow_7 } ; - assign MUX_wci_respF_8$enq_1__VAL_1 = - (wci_wciResponse_8$wget[33:32] == 2'd0) ? - 34'h1C0DE4203 : - wci_wciResponse_8$wget ; - assign MUX_wci_respF_8$enq_1__VAL_2 = { 2'd1, wci_wStatus_8 } ; - assign MUX_wci_respF_8$enq_1__VAL_3 = { 2'd1, x_data__h104242 } ; - assign MUX_wci_respF_8$enq_1__VAL_4 = { 2'd1, x_data__h104248 } ; - assign MUX_wci_respF_8$enq_1__VAL_5 = { 22'd1048576, wci_pageWindow_8 } ; - assign MUX_wci_respF_9$enq_1__VAL_1 = - (wci_wciResponse_9$wget[33:32] == 2'd0) ? - 34'h1C0DE4203 : - wci_wciResponse_9$wget ; - assign MUX_wci_respF_9$enq_1__VAL_2 = { 2'd1, wci_wStatus_9 } ; - assign MUX_wci_respF_9$enq_1__VAL_3 = { 2'd1, x_data__h104295 } ; - assign MUX_wci_respF_9$enq_1__VAL_4 = { 2'd1, x_data__h104301 } ; - assign MUX_wci_respF_9$enq_1__VAL_5 = { 22'd1048576, wci_pageWindow_9 } ; - assign MUX_wci_respTimr$write_1__VAL_2 = - (wci_wciResponse$wget[33:32] == 2'd0) ? - (wci_respTimr_02_ULT_1_SL_wci_wTimeout_03_04___d5829 ? - x__h10985 : - 32'd0) : - 32'd0 ; - assign MUX_wci_respTimr_1$write_1__VAL_2 = - (wci_wciResponse_1$wget[33:32] == 2'd0) ? - (wci_respTimr_1_42_ULT_1_SL_wci_wTimeout_1_43_44___d5830 ? - x__h15428 : - 32'd0) : - 32'd0 ; - assign MUX_wci_respTimr_10$write_1__VAL_2 = - (wci_wciResponse_10$wget[33:32] == 2'd0) ? - (wci_respTimr_10_602_ULT_1_SL_wci_wTimeout_10_6_ETC___d5839 ? - x__h55388 : - 32'd0) : - 32'd0 ; - assign MUX_wci_respTimr_11$write_1__VAL_2 = - (wci_wciResponse_11$wget[33:32] == 2'd0) ? - (wci_respTimr_11_742_ULT_1_SL_wci_wTimeout_11_7_ETC___d5840 ? - x__h59828 : - 32'd0) : - 32'd0 ; - assign MUX_wci_respTimr_12$write_1__VAL_2 = - (wci_wciResponse_12$wget[33:32] == 2'd0) ? - (wci_respTimr_12_882_ULT_1_SL_wci_wTimeout_12_8_ETC___d5841 ? - x__h64268 : - 32'd0) : - 32'd0 ; - assign MUX_wci_respTimr_13$write_1__VAL_2 = - (wci_wciResponse_13$wget[33:32] == 2'd0) ? - (wci_respTimr_13_022_ULT_1_SL_wci_wTimeout_13_0_ETC___d5842 ? - x__h68708 : - 32'd0) : - 32'd0 ; - assign MUX_wci_respTimr_14$write_1__VAL_2 = - (wci_wciResponse_14$wget[33:32] == 2'd0) ? - (wci_respTimr_14_162_ULT_1_SL_wci_wTimeout_14_1_ETC___d5843 ? - x__h73148 : - 32'd0) : - 32'd0 ; - assign MUX_wci_respTimr_2$write_1__VAL_2 = - (wci_wciResponse_2$wget[33:32] == 2'd0) ? - (wci_respTimr_2_82_ULT_1_SL_wci_wTimeout_2_83_84___d5831 ? - x__h19868 : - 32'd0) : - 32'd0 ; - assign MUX_wci_respTimr_3$write_1__VAL_2 = - (wci_wciResponse_3$wget[33:32] == 2'd0) ? - (wci_respTimr_3_22_ULT_1_SL_wci_wTimeout_3_23_24___d5832 ? - x__h24308 : - 32'd0) : - 32'd0 ; - assign MUX_wci_respTimr_4$write_1__VAL_2 = - (wci_wciResponse_4$wget[33:32] == 2'd0) ? - (wci_respTimr_4_62_ULT_1_SL_wci_wTimeout_4_63_64___d5833 ? - x__h28748 : - 32'd0) : - 32'd0 ; - assign MUX_wci_respTimr_5$write_1__VAL_2 = - (wci_wciResponse_5$wget[33:32] == 2'd0) ? - (wci_respTimr_5_02_ULT_1_SL_wci_wTimeout_5_03_04___d5834 ? - x__h33188 : - 32'd0) : - 32'd0 ; - assign MUX_wci_respTimr_6$write_1__VAL_2 = - (wci_wciResponse_6$wget[33:32] == 2'd0) ? - (wci_respTimr_6_042_ULT_1_SL_wci_wTimeout_6_043_ETC___d5835 ? - x__h37628 : - 32'd0) : - 32'd0 ; - assign MUX_wci_respTimr_7$write_1__VAL_2 = - (wci_wciResponse_7$wget[33:32] == 2'd0) ? - (wci_respTimr_7_182_ULT_1_SL_wci_wTimeout_7_183_ETC___d5836 ? - x__h42068 : - 32'd0) : - 32'd0 ; - assign MUX_wci_respTimr_8$write_1__VAL_2 = - (wci_wciResponse_8$wget[33:32] == 2'd0) ? - (wci_respTimr_8_322_ULT_1_SL_wci_wTimeout_8_323_ETC___d5837 ? - x__h46508 : - 32'd0) : - 32'd0 ; - assign MUX_wci_respTimr_9$write_1__VAL_2 = - (wci_wciResponse_9$wget[33:32] == 2'd0) ? - (wci_respTimr_9_462_ULT_1_SL_wci_wTimeout_9_463_ETC___d5838 ? - x__h50948 : + wci_9_wciResponse$wget ; + assign MUX_wci_9_respF$enq_1__VAL_2 = { 2'd1, wci_9_wStatus } ; + assign MUX_wci_9_respF$enq_1__VAL_3 = { 2'd1, x_data__h103254 } ; + assign MUX_wci_9_respF$enq_1__VAL_4 = { 2'd1, x_data__h103260 } ; + assign MUX_wci_9_respF$enq_1__VAL_5 = { 22'd1048576, wci_9_pageWindow } ; + assign MUX_wci_9_respTimr$write_1__VAL_2 = + (wci_9_wciResponse$wget[33:32] == 2'd0) ? + (wci_9_respTimr_488_ULT_1_SL_wci_9_wTimeout_489_ETC___d1491 ? + x__h51176 : 32'd0) : 32'd0 ; @@ -10605,11 +10513,12 @@ module mkOCCP(pciDevice, assign timeServ_jamFrac_1$wget = 1'd1 ; assign timeServ_jamFrac_1$whas = timeServ_setRefF$dEMPTY_N && !timeServ_ppsOK ; - assign timeServ_jamFracVal_1$wget = x__h3700 ; + assign timeServ_jamFracVal_1$wget = x__h3688 ; assign timeServ_jamFracVal_1$whas = timeServ_jamFrac_1$whas ; - assign deviceDNA$wget = 64'h0 ; - assign deviceDNA$whas = 1'b0 ; - assign devDNAV$wget = 64'h0BADC0DE0BADC0DE ; + assign deviceDNA$wget = x_wget__h5213 ; + assign deviceDNA$whas = dna_cnt == 7'd127 ; + assign devDNAV$wget = + (dna_cnt == 7'd127) ? x_wget__h5213 : 64'h0BADC0DE0BADC0DE ; assign devDNAV$whas = 1'd1 ; assign rom_serverAdapter_outData_enqData$wget = rom_memory$DO ; assign rom_serverAdapter_outData_enqData$whas = @@ -10639,348 +10548,352 @@ module mkOCCP(pciDevice, assign rom_serverAdapter_s1_1$wget = 2'd3 ; assign rom_serverAdapter_s1_1$whas = WILL_FIRE_RL_rom_serverAdapter_stageReadResponseAlways ; + assign dna_rdReg_1$wget = 1'd1 ; + assign dna_rdReg_1$whas = dna_cnt == 7'd1 || dna_cnt == 7'd2 ; + assign dna_shftReg_1$wget = 1'd1 ; + assign dna_shftReg_1$whas = dna_cnt >= 7'd3 && dna_cnt <= 7'd116 ; assign uuidV$wget = uuid_arg ; assign uuidV$whas = 1'd1 ; - assign wci_reqF_x_wire$wget = MUX_wci_reqF_q_0$write_1__VAL_2 ; - assign wci_reqF_x_wire$whas = - WILL_FIRE_RL_cpDispatch_F_F_T_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_T_F_T_T ; - assign wci_wciResponse$wget = { wci_Vm_0_SResp, wci_Vm_0_SData } ; - assign wci_wciResponse$whas = 1'd1 ; - assign wci_sfCapSet_1$wget = wci_Vm_0_SFlag[0] ; - assign wci_sfCapSet_1$whas = 1'd1 ; - assign wci_sfCapClear_1$wget = 1'd1 ; - assign wci_sfCapClear_1$whas = - WILL_FIRE_RL_cpDispatch_F_F_T_T_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_T_F_F_T_T_T ; - assign wci_reqF_1_x_wire$wget = MUX_wci_reqF_1_q_0$write_1__VAL_2 ; - assign wci_reqF_1_x_wire$whas = - WILL_FIRE_RL_cpDispatch_F_F_T_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_F_T_T ; - assign wci_wciResponse_1$wget = { wci_Vm_1_SResp, wci_Vm_1_SData } ; - assign wci_wciResponse_1$whas = 1'd1 ; - assign wci_sfCapSet_1_2$wget = wci_Vm_1_SFlag[0] ; - assign wci_sfCapSet_1_2$whas = 1'd1 ; - assign wci_sfCapClear_1_2$wget = 1'd1 ; - assign wci_sfCapClear_1_2$whas = - WILL_FIRE_RL_cpDispatch_F_F_T_F_T_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_T_F_F_T_T_T ; - assign wci_reqF_2_x_wire$wget = MUX_wci_reqF_2_q_0$write_1__VAL_1 ; - assign wci_reqF_2_x_wire$whas = - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_F_T_T ; - assign wci_wciResponse_2$wget = { wci_Vm_2_SResp, wci_Vm_2_SData } ; - assign wci_wciResponse_2$whas = 1'd1 ; - assign wci_sfCapSet_2_1$wget = wci_Vm_2_SFlag[0] ; - assign wci_sfCapSet_2_1$whas = 1'd1 ; - assign wci_sfCapClear_2_1$wget = 1'd1 ; - assign wci_sfCapClear_2_1$whas = - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_F_F_T_T_T ; - assign wci_reqF_3_x_wire$wget = MUX_wci_reqF_3_q_0$write_1__VAL_1 ; - assign wci_reqF_3_x_wire$whas = - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_F_T_T ; - assign wci_wciResponse_3$wget = { wci_Vm_3_SResp, wci_Vm_3_SData } ; - assign wci_wciResponse_3$whas = 1'd1 ; - assign wci_sfCapSet_3_1$wget = wci_Vm_3_SFlag[0] ; - assign wci_sfCapSet_3_1$whas = 1'd1 ; - assign wci_sfCapClear_3_1$wget = 1'd1 ; - assign wci_sfCapClear_3_1$whas = - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_F_F_T_T_T ; - assign wci_reqF_4_x_wire$wget = MUX_wci_reqF_4_q_0$write_1__VAL_1 ; - assign wci_reqF_4_x_wire$whas = - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_T_T ; - assign wci_wciResponse_4$wget = { wci_Vm_4_SResp, wci_Vm_4_SData } ; - assign wci_wciResponse_4$whas = 1'd1 ; - assign wci_sfCapSet_4_1$wget = wci_Vm_4_SFlag[0] ; - assign wci_sfCapSet_4_1$whas = 1'd1 ; - assign wci_sfCapClear_4_1$wget = 1'd1 ; - assign wci_sfCapClear_4_1$whas = - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_F_F_T_T_T ; - assign wci_reqF_5_x_wire$wget = MUX_wci_reqF_5_q_0$write_1__VAL_1 ; - assign wci_reqF_5_x_wire$whas = - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_T_T ; - assign wci_wciResponse_5$wget = { wci_Vm_5_SResp, wci_Vm_5_SData } ; - assign wci_wciResponse_5$whas = 1'd1 ; - assign wci_sfCapSet_5_1$wget = wci_Vm_5_SFlag[0] ; - assign wci_sfCapSet_5_1$whas = 1'd1 ; - assign wci_sfCapClear_5_1$wget = 1'd1 ; - assign wci_sfCapClear_5_1$whas = - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_F_T_T_T ; - assign wci_reqF_6_x_wire$wget = MUX_wci_reqF_6_q_0$write_1__VAL_1 ; - assign wci_reqF_6_x_wire$whas = - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_F_T_T ; - assign wci_wciResponse_6$wget = { wci_Vm_6_SResp, wci_Vm_6_SData } ; - assign wci_wciResponse_6$whas = 1'd1 ; - assign wci_sfCapSet_6_1$wget = wci_Vm_6_SFlag[0] ; - assign wci_sfCapSet_6_1$whas = 1'd1 ; - assign wci_sfCapClear_6_1$wget = 1'd1 ; - assign wci_sfCapClear_6_1$whas = - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_F_F_T_T_T ; - assign wci_reqF_7_x_wire$wget = MUX_wci_reqF_7_q_0$write_1__VAL_1 ; - assign wci_reqF_7_x_wire$whas = - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T ; - assign wci_wciResponse_7$wget = { wci_Vm_7_SResp, wci_Vm_7_SData } ; - assign wci_wciResponse_7$whas = 1'd1 ; - assign wci_sfCapSet_7_1$wget = wci_Vm_7_SFlag[0] ; - assign wci_sfCapSet_7_1$whas = 1'd1 ; - assign wci_sfCapClear_7_1$wget = 1'd1 ; - assign wci_sfCapClear_7_1$whas = - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_F_F_T_T_T ; - assign wci_reqF_8_x_wire$wget = MUX_wci_reqF_8_q_0$write_1__VAL_1 ; - assign wci_reqF_8_x_wire$whas = - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T ; - assign wci_wciResponse_8$wget = { wci_Vm_8_SResp, wci_Vm_8_SData } ; - assign wci_wciResponse_8$whas = 1'd1 ; - assign wci_sfCapSet_8_1$wget = wci_Vm_8_SFlag[0] ; - assign wci_sfCapSet_8_1$whas = 1'd1 ; - assign wci_sfCapClear_8_1$wget = 1'd1 ; - assign wci_sfCapClear_8_1$whas = - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_F_F_T_T_T ; - assign wci_reqF_9_x_wire$wget = MUX_wci_reqF_9_q_0$write_1__VAL_1 ; - assign wci_reqF_9_x_wire$whas = - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T ; - assign wci_wciResponse_9$wget = { wci_Vm_9_SResp, wci_Vm_9_SData } ; - assign wci_wciResponse_9$whas = 1'd1 ; - assign wci_sfCapSet_9_1$wget = wci_Vm_9_SFlag[0] ; - assign wci_sfCapSet_9_1$whas = 1'd1 ; - assign wci_sfCapClear_9_1$wget = 1'd1 ; - assign wci_sfCapClear_9_1$whas = - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_F_F_T_T_T ; - assign wci_reqF_10_x_wire$wget = MUX_wci_reqF_10_q_0$write_1__VAL_1 ; - assign wci_reqF_10_x_wire$whas = - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T ; - assign wci_wciResponse_10$wget = { wci_Vm_10_SResp, wci_Vm_10_SData } ; - assign wci_wciResponse_10$whas = 1'd1 ; - assign wci_sfCapSet_10_1$wget = wci_Vm_10_SFlag[0] ; - assign wci_sfCapSet_10_1$whas = 1'd1 ; - assign wci_sfCapClear_10_1$wget = 1'd1 ; - assign wci_sfCapClear_10_1$whas = - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_T ; - assign wci_reqF_11_x_wire$wget = MUX_wci_reqF_11_q_0$write_1__VAL_1 ; - assign wci_reqF_11_x_wire$whas = - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T ; - assign wci_wciResponse_11$wget = { wci_Vm_11_SResp, wci_Vm_11_SData } ; - assign wci_wciResponse_11$whas = 1'd1 ; - assign wci_sfCapSet_11_1$wget = wci_Vm_11_SFlag[0] ; - assign wci_sfCapSet_11_1$whas = 1'd1 ; - assign wci_sfCapClear_11_1$wget = 1'd1 ; - assign wci_sfCapClear_11_1$whas = - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_T ; - assign wci_reqF_12_x_wire$wget = MUX_wci_reqF_12_q_0$write_1__VAL_1 ; - assign wci_reqF_12_x_wire$whas = - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T ; - assign wci_wciResponse_12$wget = { wci_Vm_12_SResp, wci_Vm_12_SData } ; - assign wci_wciResponse_12$whas = 1'd1 ; - assign wci_sfCapSet_12_1$wget = wci_Vm_12_SFlag[0] ; - assign wci_sfCapSet_12_1$whas = 1'd1 ; - assign wci_sfCapClear_12_1$wget = 1'd1 ; - assign wci_sfCapClear_12_1$whas = - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_T ; - assign wci_reqF_13_x_wire$wget = MUX_wci_reqF_13_q_0$write_1__VAL_1 ; - assign wci_reqF_13_x_wire$whas = - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T ; - assign wci_wciResponse_13$wget = { wci_Vm_13_SResp, wci_Vm_13_SData } ; - assign wci_wciResponse_13$whas = 1'd1 ; - assign wci_sfCapSet_13_1$wget = wci_Vm_13_SFlag[0] ; - assign wci_sfCapSet_13_1$whas = 1'd1 ; - assign wci_sfCapClear_13_1$wget = 1'd1 ; - assign wci_sfCapClear_13_1$whas = - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_T ; - assign wci_reqF_14_x_wire$wget = MUX_wci_reqF_14_q_0$write_1__VAL_1 ; - assign wci_reqF_14_x_wire$whas = - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T ; - assign wci_wciResponse_14$wget = { wci_Vm_14_SResp, wci_Vm_14_SData } ; - assign wci_wciResponse_14$whas = 1'd1 ; - assign wci_sfCapSet_14_1$wget = wci_Vm_14_SFlag[0] ; - assign wci_sfCapSet_14_1$whas = 1'd1 ; - assign wci_sfCapClear_14_1$wget = 1'd1 ; - assign wci_sfCapClear_14_1$whas = - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_T ; - assign wci_Emv_resp_w$wget = wci_Vm_0_SResp ; - assign wci_Emv_resp_w$whas = 1'd1 ; - assign wci_Emv_respData_w$wget = wci_Vm_0_SData ; - assign wci_Emv_respData_w$whas = 1'd1 ; - assign wci_Emv_resp_w_1$wget = wci_Vm_1_SResp ; - assign wci_Emv_resp_w_1$whas = 1'd1 ; - assign wci_Emv_respData_w_1$wget = wci_Vm_1_SData ; - assign wci_Emv_respData_w_1$whas = 1'd1 ; - assign wci_Emv_resp_w_2$wget = wci_Vm_2_SResp ; - assign wci_Emv_resp_w_2$whas = 1'd1 ; - assign wci_Emv_respData_w_2$wget = wci_Vm_2_SData ; - assign wci_Emv_respData_w_2$whas = 1'd1 ; - assign wci_Emv_resp_w_3$wget = wci_Vm_3_SResp ; - assign wci_Emv_resp_w_3$whas = 1'd1 ; - assign wci_Emv_respData_w_3$wget = wci_Vm_3_SData ; - assign wci_Emv_respData_w_3$whas = 1'd1 ; - assign wci_Emv_resp_w_4$wget = wci_Vm_4_SResp ; - assign wci_Emv_resp_w_4$whas = 1'd1 ; - assign wci_Emv_respData_w_4$wget = wci_Vm_4_SData ; - assign wci_Emv_respData_w_4$whas = 1'd1 ; - assign wci_Emv_resp_w_5$wget = wci_Vm_5_SResp ; - assign wci_Emv_resp_w_5$whas = 1'd1 ; - assign wci_Emv_respData_w_5$wget = wci_Vm_5_SData ; - assign wci_Emv_respData_w_5$whas = 1'd1 ; - assign wci_Emv_resp_w_6$wget = wci_Vm_6_SResp ; - assign wci_Emv_resp_w_6$whas = 1'd1 ; - assign wci_Emv_respData_w_6$wget = wci_Vm_6_SData ; - assign wci_Emv_respData_w_6$whas = 1'd1 ; - assign wci_Emv_resp_w_7$wget = wci_Vm_7_SResp ; - assign wci_Emv_resp_w_7$whas = 1'd1 ; - assign wci_Emv_respData_w_7$wget = wci_Vm_7_SData ; - assign wci_Emv_respData_w_7$whas = 1'd1 ; - assign wci_Emv_resp_w_8$wget = wci_Vm_8_SResp ; - assign wci_Emv_resp_w_8$whas = 1'd1 ; - assign wci_Emv_respData_w_8$wget = wci_Vm_8_SData ; - assign wci_Emv_respData_w_8$whas = 1'd1 ; - assign wci_Emv_resp_w_9$wget = wci_Vm_9_SResp ; - assign wci_Emv_resp_w_9$whas = 1'd1 ; - assign wci_Emv_respData_w_9$wget = wci_Vm_9_SData ; - assign wci_Emv_respData_w_9$whas = 1'd1 ; - assign wci_Emv_resp_w_10$wget = wci_Vm_10_SResp ; - assign wci_Emv_resp_w_10$whas = 1'd1 ; - assign wci_Emv_respData_w_10$wget = wci_Vm_10_SData ; - assign wci_Emv_respData_w_10$whas = 1'd1 ; - assign wci_Emv_resp_w_11$wget = wci_Vm_11_SResp ; - assign wci_Emv_resp_w_11$whas = 1'd1 ; - assign wci_Emv_respData_w_11$wget = wci_Vm_11_SData ; - assign wci_Emv_respData_w_11$whas = 1'd1 ; - assign wci_Emv_resp_w_12$wget = wci_Vm_12_SResp ; - assign wci_Emv_resp_w_12$whas = 1'd1 ; - assign wci_Emv_respData_w_12$wget = wci_Vm_12_SData ; - assign wci_Emv_respData_w_12$whas = 1'd1 ; - assign wci_Emv_resp_w_13$wget = wci_Vm_13_SResp ; - assign wci_Emv_resp_w_13$whas = 1'd1 ; - assign wci_Emv_respData_w_13$wget = wci_Vm_13_SData ; - assign wci_Emv_respData_w_13$whas = 1'd1 ; - assign wci_Emv_resp_w_14$wget = wci_Vm_14_SResp ; - assign wci_Emv_resp_w_14$whas = 1'd1 ; - assign wci_Emv_respData_w_14$wget = wci_Vm_14_SData ; - assign wci_Emv_respData_w_14$whas = 1'd1 ; + assign wci_0_reqF_x_wire$wget = MUX_wci_0_reqF_q_0$write_1__VAL_2 ; + assign wci_0_reqF_x_wire$whas = + WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E0_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_T_T ; + assign wci_0_wciResponse$wget = { wci_Vm_0_SResp, wci_Vm_0_SData } ; + assign wci_0_wciResponse$whas = 1'd1 ; + assign wci_0_sfCapSet_1$wget = wci_Vm_0_SFlag[0] ; + assign wci_0_sfCapSet_1$whas = 1'd1 ; + assign wci_0_sfCapClear_1$wget = 1'd1 ; + assign wci_0_sfCapClear_1$whas = + WILL_FIRE_RL_cpDispatch_F_F_T_E0_F_F_T_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E0_F_F_T_T_T ; + assign wci_1_reqF_x_wire$wget = MUX_wci_1_reqF_q_0$write_1__VAL_2 ; + assign wci_1_reqF_x_wire$whas = + WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E1_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_T_T ; + assign wci_1_wciResponse$wget = { wci_Vm_1_SResp, wci_Vm_1_SData } ; + assign wci_1_wciResponse$whas = 1'd1 ; + assign wci_1_sfCapSet_1$wget = wci_Vm_1_SFlag[0] ; + assign wci_1_sfCapSet_1$whas = 1'd1 ; + assign wci_1_sfCapClear_1$wget = 1'd1 ; + assign wci_1_sfCapClear_1$whas = + WILL_FIRE_RL_cpDispatch_F_F_T_E1_F_F_T_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E1_F_F_T_T_T ; + assign wci_2_reqF_x_wire$wget = MUX_wci_2_reqF_q_0$write_1__VAL_2 ; + assign wci_2_reqF_x_wire$whas = + WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_F_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E2_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_T_T ; + assign wci_2_wciResponse$wget = { wci_Vm_2_SResp, wci_Vm_2_SData } ; + assign wci_2_wciResponse$whas = 1'd1 ; + assign wci_2_sfCapSet_1$wget = wci_Vm_2_SFlag[0] ; + assign wci_2_sfCapSet_1$whas = 1'd1 ; + assign wci_2_sfCapClear_1$wget = 1'd1 ; + assign wci_2_sfCapClear_1$whas = + WILL_FIRE_RL_cpDispatch_F_F_T_E2_F_F_T_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E2_F_F_T_T_T ; + assign wci_3_reqF_x_wire$wget = MUX_wci_3_reqF_q_0$write_1__VAL_2 ; + assign wci_3_reqF_x_wire$whas = + WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_F_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E3_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_T_T ; + assign wci_3_wciResponse$wget = { wci_Vm_3_SResp, wci_Vm_3_SData } ; + assign wci_3_wciResponse$whas = 1'd1 ; + assign wci_3_sfCapSet_1$wget = wci_Vm_3_SFlag[0] ; + assign wci_3_sfCapSet_1$whas = 1'd1 ; + assign wci_3_sfCapClear_1$wget = 1'd1 ; + assign wci_3_sfCapClear_1$whas = + WILL_FIRE_RL_cpDispatch_F_F_T_E3_F_F_T_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E3_F_F_T_T_T ; + assign wci_4_reqF_x_wire$wget = MUX_wci_4_reqF_q_0$write_1__VAL_2 ; + assign wci_4_reqF_x_wire$whas = + WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_F_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E4_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_T_T ; + assign wci_4_wciResponse$wget = { wci_Vm_4_SResp, wci_Vm_4_SData } ; + assign wci_4_wciResponse$whas = 1'd1 ; + assign wci_4_sfCapSet_1$wget = wci_Vm_4_SFlag[0] ; + assign wci_4_sfCapSet_1$whas = 1'd1 ; + assign wci_4_sfCapClear_1$wget = 1'd1 ; + assign wci_4_sfCapClear_1$whas = + WILL_FIRE_RL_cpDispatch_F_F_T_E4_F_F_T_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E4_F_F_T_T_T ; + assign wci_5_reqF_x_wire$wget = MUX_wci_5_reqF_q_0$write_1__VAL_2 ; + assign wci_5_reqF_x_wire$whas = + WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E5_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_T_T ; + assign wci_5_wciResponse$wget = { wci_Vm_5_SResp, wci_Vm_5_SData } ; + assign wci_5_wciResponse$whas = 1'd1 ; + assign wci_5_sfCapSet_1$wget = wci_Vm_5_SFlag[0] ; + assign wci_5_sfCapSet_1$whas = 1'd1 ; + assign wci_5_sfCapClear_1$wget = 1'd1 ; + assign wci_5_sfCapClear_1$whas = + WILL_FIRE_RL_cpDispatch_F_F_T_E5_F_F_T_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E5_F_F_T_T_T ; + assign wci_6_reqF_x_wire$wget = MUX_wci_6_reqF_q_0$write_1__VAL_2 ; + assign wci_6_reqF_x_wire$whas = + WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_F_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E6_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_T_T ; + assign wci_6_wciResponse$wget = { wci_Vm_6_SResp, wci_Vm_6_SData } ; + assign wci_6_wciResponse$whas = 1'd1 ; + assign wci_6_sfCapSet_1$wget = wci_Vm_6_SFlag[0] ; + assign wci_6_sfCapSet_1$whas = 1'd1 ; + assign wci_6_sfCapClear_1$wget = 1'd1 ; + assign wci_6_sfCapClear_1$whas = + WILL_FIRE_RL_cpDispatch_F_F_T_E6_F_F_T_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E6_F_F_T_T_T ; + assign wci_7_reqF_x_wire$wget = MUX_wci_7_reqF_q_0$write_1__VAL_2 ; + assign wci_7_reqF_x_wire$whas = + WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E7_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_T_T ; + assign wci_7_wciResponse$wget = { wci_Vm_7_SResp, wci_Vm_7_SData } ; + assign wci_7_wciResponse$whas = 1'd1 ; + assign wci_7_sfCapSet_1$wget = wci_Vm_7_SFlag[0] ; + assign wci_7_sfCapSet_1$whas = 1'd1 ; + assign wci_7_sfCapClear_1$wget = 1'd1 ; + assign wci_7_sfCapClear_1$whas = + WILL_FIRE_RL_cpDispatch_F_F_T_E7_F_F_T_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E7_F_F_T_T_T ; + assign wci_8_reqF_x_wire$wget = MUX_wci_8_reqF_q_0$write_1__VAL_2 ; + assign wci_8_reqF_x_wire$whas = + WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E8_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_T_T ; + assign wci_8_wciResponse$wget = { wci_Vm_8_SResp, wci_Vm_8_SData } ; + assign wci_8_wciResponse$whas = 1'd1 ; + assign wci_8_sfCapSet_1$wget = wci_Vm_8_SFlag[0] ; + assign wci_8_sfCapSet_1$whas = 1'd1 ; + assign wci_8_sfCapClear_1$wget = 1'd1 ; + assign wci_8_sfCapClear_1$whas = + WILL_FIRE_RL_cpDispatch_F_F_T_E8_F_F_T_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E8_F_F_T_T_T ; + assign wci_9_reqF_x_wire$wget = MUX_wci_9_reqF_q_0$write_1__VAL_2 ; + assign wci_9_reqF_x_wire$whas = + WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_F_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E9_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_T_T ; + assign wci_9_wciResponse$wget = { wci_Vm_9_SResp, wci_Vm_9_SData } ; + assign wci_9_wciResponse$whas = 1'd1 ; + assign wci_9_sfCapSet_1$wget = wci_Vm_9_SFlag[0] ; + assign wci_9_sfCapSet_1$whas = 1'd1 ; + assign wci_9_sfCapClear_1$wget = 1'd1 ; + assign wci_9_sfCapClear_1$whas = + WILL_FIRE_RL_cpDispatch_F_F_T_E9_F_F_T_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E9_F_F_T_T_T ; + assign wci_10_reqF_x_wire$wget = MUX_wci_10_reqF_q_0$write_1__VAL_1 ; + assign wci_10_reqF_x_wire$whas = + WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_F_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E10_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_T_T ; + assign wci_10_wciResponse$wget = { wci_Vm_10_SResp, wci_Vm_10_SData } ; + assign wci_10_wciResponse$whas = 1'd1 ; + assign wci_10_sfCapSet_1$wget = wci_Vm_10_SFlag[0] ; + assign wci_10_sfCapSet_1$whas = 1'd1 ; + assign wci_10_sfCapClear_1$wget = 1'd1 ; + assign wci_10_sfCapClear_1$whas = + WILL_FIRE_RL_cpDispatch_F_F_T_E10_F_F_T_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E10_F_F_T_T_T ; + assign wci_11_reqF_x_wire$wget = MUX_wci_11_reqF_q_0$write_1__VAL_1 ; + assign wci_11_reqF_x_wire$whas = + WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_F_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E11_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_T_T ; + assign wci_11_wciResponse$wget = { wci_Vm_11_SResp, wci_Vm_11_SData } ; + assign wci_11_wciResponse$whas = 1'd1 ; + assign wci_11_sfCapSet_1$wget = wci_Vm_11_SFlag[0] ; + assign wci_11_sfCapSet_1$whas = 1'd1 ; + assign wci_11_sfCapClear_1$wget = 1'd1 ; + assign wci_11_sfCapClear_1$whas = + WILL_FIRE_RL_cpDispatch_F_F_T_E11_F_F_T_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E11_F_F_T_T_T ; + assign wci_12_reqF_x_wire$wget = MUX_wci_12_reqF_q_0$write_1__VAL_1 ; + assign wci_12_reqF_x_wire$whas = + WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_F_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E12_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_T_T ; + assign wci_12_wciResponse$wget = { wci_Vm_12_SResp, wci_Vm_12_SData } ; + assign wci_12_wciResponse$whas = 1'd1 ; + assign wci_12_sfCapSet_1$wget = wci_Vm_12_SFlag[0] ; + assign wci_12_sfCapSet_1$whas = 1'd1 ; + assign wci_12_sfCapClear_1$wget = 1'd1 ; + assign wci_12_sfCapClear_1$whas = + WILL_FIRE_RL_cpDispatch_F_F_T_E12_F_F_T_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E12_F_F_T_T_T ; + assign wci_13_reqF_x_wire$wget = MUX_wci_13_reqF_q_0$write_1__VAL_1 ; + assign wci_13_reqF_x_wire$whas = + WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_F_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E13_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_T_T ; + assign wci_13_wciResponse$wget = { wci_Vm_13_SResp, wci_Vm_13_SData } ; + assign wci_13_wciResponse$whas = 1'd1 ; + assign wci_13_sfCapSet_1$wget = wci_Vm_13_SFlag[0] ; + assign wci_13_sfCapSet_1$whas = 1'd1 ; + assign wci_13_sfCapClear_1$wget = 1'd1 ; + assign wci_13_sfCapClear_1$whas = + WILL_FIRE_RL_cpDispatch_F_F_T_E13_F_F_T_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E13_F_F_T_T_T ; + assign wci_14_reqF_x_wire$wget = MUX_wci_14_reqF_q_0$write_1__VAL_1 ; + assign wci_14_reqF_x_wire$whas = + WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_F_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E14_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_T_T ; + assign wci_14_wciResponse$wget = { wci_Vm_14_SResp, wci_Vm_14_SData } ; + assign wci_14_wciResponse$whas = 1'd1 ; + assign wci_14_sfCapSet_1$wget = wci_Vm_14_SFlag[0] ; + assign wci_14_sfCapSet_1$whas = 1'd1 ; + assign wci_14_sfCapClear_1$wget = 1'd1 ; + assign wci_14_sfCapClear_1$whas = + WILL_FIRE_RL_cpDispatch_F_F_T_E14_F_F_T_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E14_F_F_T_T_T ; + assign wci_Emv_0_resp_w$wget = wci_Vm_0_SResp ; + assign wci_Emv_0_resp_w$whas = 1'd1 ; + assign wci_Emv_0_respData_w$wget = wci_Vm_0_SData ; + assign wci_Emv_0_respData_w$whas = 1'd1 ; + assign wci_Emv_1_resp_w$wget = wci_Vm_1_SResp ; + assign wci_Emv_1_resp_w$whas = 1'd1 ; + assign wci_Emv_1_respData_w$wget = wci_Vm_1_SData ; + assign wci_Emv_1_respData_w$whas = 1'd1 ; + assign wci_Emv_2_resp_w$wget = wci_Vm_2_SResp ; + assign wci_Emv_2_resp_w$whas = 1'd1 ; + assign wci_Emv_2_respData_w$wget = wci_Vm_2_SData ; + assign wci_Emv_2_respData_w$whas = 1'd1 ; + assign wci_Emv_3_resp_w$wget = wci_Vm_3_SResp ; + assign wci_Emv_3_resp_w$whas = 1'd1 ; + assign wci_Emv_3_respData_w$wget = wci_Vm_3_SData ; + assign wci_Emv_3_respData_w$whas = 1'd1 ; + assign wci_Emv_4_resp_w$wget = wci_Vm_4_SResp ; + assign wci_Emv_4_resp_w$whas = 1'd1 ; + assign wci_Emv_4_respData_w$wget = wci_Vm_4_SData ; + assign wci_Emv_4_respData_w$whas = 1'd1 ; + assign wci_Emv_5_resp_w$wget = wci_Vm_5_SResp ; + assign wci_Emv_5_resp_w$whas = 1'd1 ; + assign wci_Emv_5_respData_w$wget = wci_Vm_5_SData ; + assign wci_Emv_5_respData_w$whas = 1'd1 ; + assign wci_Emv_6_resp_w$wget = wci_Vm_6_SResp ; + assign wci_Emv_6_resp_w$whas = 1'd1 ; + assign wci_Emv_6_respData_w$wget = wci_Vm_6_SData ; + assign wci_Emv_6_respData_w$whas = 1'd1 ; + assign wci_Emv_7_resp_w$wget = wci_Vm_7_SResp ; + assign wci_Emv_7_resp_w$whas = 1'd1 ; + assign wci_Emv_7_respData_w$wget = wci_Vm_7_SData ; + assign wci_Emv_7_respData_w$whas = 1'd1 ; + assign wci_Emv_8_resp_w$wget = wci_Vm_8_SResp ; + assign wci_Emv_8_resp_w$whas = 1'd1 ; + assign wci_Emv_8_respData_w$wget = wci_Vm_8_SData ; + assign wci_Emv_8_respData_w$whas = 1'd1 ; + assign wci_Emv_9_resp_w$wget = wci_Vm_9_SResp ; + assign wci_Emv_9_resp_w$whas = 1'd1 ; + assign wci_Emv_9_respData_w$wget = wci_Vm_9_SData ; + assign wci_Emv_9_respData_w$whas = 1'd1 ; + assign wci_Emv_10_resp_w$wget = wci_Vm_10_SResp ; + assign wci_Emv_10_resp_w$whas = 1'd1 ; + assign wci_Emv_10_respData_w$wget = wci_Vm_10_SData ; + assign wci_Emv_10_respData_w$whas = 1'd1 ; + assign wci_Emv_11_resp_w$wget = wci_Vm_11_SResp ; + assign wci_Emv_11_resp_w$whas = 1'd1 ; + assign wci_Emv_11_respData_w$wget = wci_Vm_11_SData ; + assign wci_Emv_11_respData_w$whas = 1'd1 ; + assign wci_Emv_12_resp_w$wget = wci_Vm_12_SResp ; + assign wci_Emv_12_resp_w$whas = 1'd1 ; + assign wci_Emv_12_respData_w$wget = wci_Vm_12_SData ; + assign wci_Emv_12_respData_w$whas = 1'd1 ; + assign wci_Emv_13_resp_w$wget = wci_Vm_13_SResp ; + assign wci_Emv_13_resp_w$whas = 1'd1 ; + assign wci_Emv_13_respData_w$wget = wci_Vm_13_SData ; + assign wci_Emv_13_respData_w$whas = 1'd1 ; + assign wci_Emv_14_resp_w$wget = wci_Vm_14_SResp ; + assign wci_Emv_14_resp_w$whas = 1'd1 ; + assign wci_Emv_14_respData_w$wget = wci_Vm_14_SData ; + assign wci_Emv_14_respData_w$whas = 1'd1 ; assign rom_serverAdapter_outData_deqCalled$whas = (rom_serverAdapter_outDataCore$EMPTY_N || rom_serverAdapter_outData_enqData$whas) && rom_serverAdapter_outData_outData$whas && adminResp4F$FULL_N ; - assign wci_reqF_enqueueing$whas = MUX_wci_busy$write_1__SEL_2 ; - assign wci_reqF_dequeueing$whas = - !wci_sThreadBusy_d && wci_wciResponse$wget[33:32] == 2'd0 && - wci_reqF_c_r ; - assign wci_sThreadBusy_pw$whas = wci_Vm_0_SThreadBusy ; - assign wci_reqF_1_enqueueing$whas = MUX_wci_busy_1$write_1__SEL_2 ; - assign wci_reqF_1_dequeueing$whas = - !wci_sThreadBusy_d_1 && wci_wciResponse_1$wget[33:32] == 2'd0 && - wci_reqF_1_c_r ; - assign wci_sThreadBusy_pw_1$whas = wci_Vm_1_SThreadBusy ; - assign wci_reqF_2_enqueueing$whas = MUX_wci_busy_2$write_1__SEL_2 ; - assign wci_reqF_2_dequeueing$whas = - !wci_sThreadBusy_d_2 && wci_wciResponse_2$wget[33:32] == 2'd0 && - wci_reqF_2_c_r ; - assign wci_sThreadBusy_pw_2$whas = wci_Vm_2_SThreadBusy ; - assign wci_reqF_3_enqueueing$whas = MUX_wci_busy_3$write_1__SEL_2 ; - assign wci_reqF_3_dequeueing$whas = - !wci_sThreadBusy_d_3 && wci_wciResponse_3$wget[33:32] == 2'd0 && - wci_reqF_3_c_r ; - assign wci_sThreadBusy_pw_3$whas = wci_Vm_3_SThreadBusy ; - assign wci_reqF_4_enqueueing$whas = MUX_wci_busy_4$write_1__SEL_2 ; - assign wci_reqF_4_dequeueing$whas = - !wci_sThreadBusy_d_4 && wci_wciResponse_4$wget[33:32] == 2'd0 && - wci_reqF_4_c_r ; - assign wci_sThreadBusy_pw_4$whas = wci_Vm_4_SThreadBusy ; - assign wci_reqF_5_enqueueing$whas = MUX_wci_busy_5$write_1__SEL_2 ; - assign wci_reqF_5_dequeueing$whas = - !wci_sThreadBusy_d_5 && wci_wciResponse_5$wget[33:32] == 2'd0 && - wci_reqF_5_c_r ; - assign wci_sThreadBusy_pw_5$whas = wci_Vm_5_SThreadBusy ; - assign wci_reqF_6_enqueueing$whas = MUX_wci_busy_6$write_1__SEL_2 ; - assign wci_reqF_6_dequeueing$whas = - !wci_sThreadBusy_d_6 && wci_wciResponse_6$wget[33:32] == 2'd0 && - wci_reqF_6_c_r ; - assign wci_sThreadBusy_pw_6$whas = wci_Vm_6_SThreadBusy ; - assign wci_reqF_7_enqueueing$whas = MUX_wci_busy_7$write_1__SEL_2 ; - assign wci_reqF_7_dequeueing$whas = - !wci_sThreadBusy_d_7 && wci_wciResponse_7$wget[33:32] == 2'd0 && - wci_reqF_7_c_r ; - assign wci_sThreadBusy_pw_7$whas = wci_Vm_7_SThreadBusy ; - assign wci_reqF_8_enqueueing$whas = MUX_wci_busy_8$write_1__SEL_2 ; - assign wci_reqF_8_dequeueing$whas = - !wci_sThreadBusy_d_8 && wci_wciResponse_8$wget[33:32] == 2'd0 && - wci_reqF_8_c_r ; - assign wci_sThreadBusy_pw_8$whas = wci_Vm_8_SThreadBusy ; - assign wci_reqF_9_enqueueing$whas = MUX_wci_busy_9$write_1__SEL_2 ; - assign wci_reqF_9_dequeueing$whas = - !wci_sThreadBusy_d_9 && wci_wciResponse_9$wget[33:32] == 2'd0 && - wci_reqF_9_c_r ; - assign wci_sThreadBusy_pw_9$whas = wci_Vm_9_SThreadBusy ; - assign wci_reqF_10_enqueueing$whas = MUX_wci_busy_10$write_1__SEL_2 ; - assign wci_reqF_10_dequeueing$whas = - !wci_sThreadBusy_d_10 && - wci_wciResponse_10$wget[33:32] == 2'd0 && - wci_reqF_10_c_r ; - assign wci_sThreadBusy_pw_10$whas = wci_Vm_10_SThreadBusy ; - assign wci_reqF_11_enqueueing$whas = MUX_wci_busy_11$write_1__SEL_2 ; - assign wci_reqF_11_dequeueing$whas = - !wci_sThreadBusy_d_11 && - wci_wciResponse_11$wget[33:32] == 2'd0 && - wci_reqF_11_c_r ; - assign wci_sThreadBusy_pw_11$whas = wci_Vm_11_SThreadBusy ; - assign wci_reqF_12_enqueueing$whas = MUX_wci_busy_12$write_1__SEL_2 ; - assign wci_reqF_12_dequeueing$whas = - !wci_sThreadBusy_d_12 && - wci_wciResponse_12$wget[33:32] == 2'd0 && - wci_reqF_12_c_r ; - assign wci_sThreadBusy_pw_12$whas = wci_Vm_12_SThreadBusy ; - assign wci_reqF_13_enqueueing$whas = MUX_wci_busy_13$write_1__SEL_2 ; - assign wci_reqF_13_dequeueing$whas = - !wci_sThreadBusy_d_13 && - wci_wciResponse_13$wget[33:32] == 2'd0 && - wci_reqF_13_c_r ; - assign wci_sThreadBusy_pw_13$whas = wci_Vm_13_SThreadBusy ; - assign wci_reqF_14_enqueueing$whas = MUX_wci_busy_14$write_1__SEL_2 ; - assign wci_reqF_14_dequeueing$whas = - !wci_sThreadBusy_d_14 && - wci_wciResponse_14$wget[33:32] == 2'd0 && - wci_reqF_14_c_r ; - assign wci_sThreadBusy_pw_14$whas = wci_Vm_14_SThreadBusy ; + assign wci_0_reqF_enqueueing$whas = MUX_wci_0_busy$write_1__SEL_2 ; + assign wci_0_reqF_dequeueing$whas = + !wci_0_sThreadBusy_d && wci_0_wciResponse$wget[33:32] == 2'd0 && + wci_0_reqF_cntr_r ; + assign wci_0_sThreadBusy_pw$whas = wci_Vm_0_SThreadBusy ; + assign wci_1_reqF_enqueueing$whas = MUX_wci_1_busy$write_1__SEL_2 ; + assign wci_1_reqF_dequeueing$whas = + !wci_1_sThreadBusy_d && wci_1_wciResponse$wget[33:32] == 2'd0 && + wci_1_reqF_cntr_r ; + assign wci_1_sThreadBusy_pw$whas = wci_Vm_1_SThreadBusy ; + assign wci_2_reqF_enqueueing$whas = MUX_wci_2_busy$write_1__SEL_2 ; + assign wci_2_reqF_dequeueing$whas = + !wci_2_sThreadBusy_d && wci_2_wciResponse$wget[33:32] == 2'd0 && + wci_2_reqF_cntr_r ; + assign wci_2_sThreadBusy_pw$whas = wci_Vm_2_SThreadBusy ; + assign wci_3_reqF_enqueueing$whas = MUX_wci_3_busy$write_1__SEL_2 ; + assign wci_3_reqF_dequeueing$whas = + !wci_3_sThreadBusy_d && wci_3_wciResponse$wget[33:32] == 2'd0 && + wci_3_reqF_cntr_r ; + assign wci_3_sThreadBusy_pw$whas = wci_Vm_3_SThreadBusy ; + assign wci_4_reqF_enqueueing$whas = MUX_wci_4_busy$write_1__SEL_2 ; + assign wci_4_reqF_dequeueing$whas = + !wci_4_sThreadBusy_d && wci_4_wciResponse$wget[33:32] == 2'd0 && + wci_4_reqF_cntr_r ; + assign wci_4_sThreadBusy_pw$whas = wci_Vm_4_SThreadBusy ; + assign wci_5_reqF_enqueueing$whas = MUX_wci_5_busy$write_1__SEL_2 ; + assign wci_5_reqF_dequeueing$whas = + !wci_5_sThreadBusy_d && wci_5_wciResponse$wget[33:32] == 2'd0 && + wci_5_reqF_cntr_r ; + assign wci_5_sThreadBusy_pw$whas = wci_Vm_5_SThreadBusy ; + assign wci_6_reqF_enqueueing$whas = MUX_wci_6_busy$write_1__SEL_2 ; + assign wci_6_reqF_dequeueing$whas = + !wci_6_sThreadBusy_d && wci_6_wciResponse$wget[33:32] == 2'd0 && + wci_6_reqF_cntr_r ; + assign wci_6_sThreadBusy_pw$whas = wci_Vm_6_SThreadBusy ; + assign wci_7_reqF_enqueueing$whas = MUX_wci_7_busy$write_1__SEL_2 ; + assign wci_7_reqF_dequeueing$whas = + !wci_7_sThreadBusy_d && wci_7_wciResponse$wget[33:32] == 2'd0 && + wci_7_reqF_cntr_r ; + assign wci_7_sThreadBusy_pw$whas = wci_Vm_7_SThreadBusy ; + assign wci_8_reqF_enqueueing$whas = MUX_wci_8_busy$write_1__SEL_2 ; + assign wci_8_reqF_dequeueing$whas = + !wci_8_sThreadBusy_d && wci_8_wciResponse$wget[33:32] == 2'd0 && + wci_8_reqF_cntr_r ; + assign wci_8_sThreadBusy_pw$whas = wci_Vm_8_SThreadBusy ; + assign wci_9_reqF_enqueueing$whas = MUX_wci_9_busy$write_1__SEL_2 ; + assign wci_9_reqF_dequeueing$whas = + !wci_9_sThreadBusy_d && wci_9_wciResponse$wget[33:32] == 2'd0 && + wci_9_reqF_cntr_r ; + assign wci_9_sThreadBusy_pw$whas = wci_Vm_9_SThreadBusy ; + assign wci_10_reqF_enqueueing$whas = MUX_wci_10_busy$write_1__SEL_2 ; + assign wci_10_reqF_dequeueing$whas = + !wci_10_sThreadBusy_d && + wci_10_wciResponse$wget[33:32] == 2'd0 && + wci_10_reqF_cntr_r ; + assign wci_10_sThreadBusy_pw$whas = wci_Vm_10_SThreadBusy ; + assign wci_11_reqF_enqueueing$whas = MUX_wci_11_busy$write_1__SEL_2 ; + assign wci_11_reqF_dequeueing$whas = + !wci_11_sThreadBusy_d && + wci_11_wciResponse$wget[33:32] == 2'd0 && + wci_11_reqF_cntr_r ; + assign wci_11_sThreadBusy_pw$whas = wci_Vm_11_SThreadBusy ; + assign wci_12_reqF_enqueueing$whas = MUX_wci_12_busy$write_1__SEL_2 ; + assign wci_12_reqF_dequeueing$whas = + !wci_12_sThreadBusy_d && + wci_12_wciResponse$wget[33:32] == 2'd0 && + wci_12_reqF_cntr_r ; + assign wci_12_sThreadBusy_pw$whas = wci_Vm_12_SThreadBusy ; + assign wci_13_reqF_enqueueing$whas = MUX_wci_13_busy$write_1__SEL_2 ; + assign wci_13_reqF_dequeueing$whas = + !wci_13_sThreadBusy_d && + wci_13_wciResponse$wget[33:32] == 2'd0 && + wci_13_reqF_cntr_r ; + assign wci_13_sThreadBusy_pw$whas = wci_Vm_13_SThreadBusy ; + assign wci_14_reqF_enqueueing$whas = MUX_wci_14_busy$write_1__SEL_2 ; + assign wci_14_reqF_dequeueing$whas = + !wci_14_sThreadBusy_d && + wci_14_wciResponse$wget[33:32] == 2'd0 && + wci_14_reqF_cntr_r ; + assign wci_14_sThreadBusy_pw$whas = wci_Vm_14_SThreadBusy ; // register cpControl assign cpControl$D_IN = cpReq[59:28] ; @@ -11045,282 +10958,282 @@ module mkOCCP(pciDevice, assign deltaTime$EN = WILL_FIRE_RL_cpDispatch_T_F_F_F_F_F_F_F_F_T ; // register dispatched - always@(WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T or - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_T or - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_T or - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T or - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_F or - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_F or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T or - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_T or - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_T or - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T or - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_F or - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_F or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T or - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_T or - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_T or - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T or - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_F or - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_F or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T or - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_T or - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_T or - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_T_T or - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_F or - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_F or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T or - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_T or - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_T or - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_T_T or - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_F or - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_F or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T or - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_F_F_T_F_T or - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_F_F_T_T_T or - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_T_T or - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_F_F_T_F_F or - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_F_F_T_T_F or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T or - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_F_F_T_F_T or - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_F_F_T_T_T or - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_T_T or - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_F_F_T_F_F or - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_F_F_T_T_F or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_T_T or - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_F_F_T_F_T or - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_F_F_T_T_T or - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_T_T or - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_F_F_T_F_F or - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_F_F_T_T_F or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_F_T_T or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_T_T or - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_F_F_T_F_T or - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_F_F_T_T_T or - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_T_T or - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_F_F_T_F_F or - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_F_F_T_T_F or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_T_T or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_T_T or - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_F_T_F_T or - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_F_T_T_T or - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_T_T or - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_F_T_F_F or - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_F_T_T_F or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_T_T or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_T_T or - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_F_F_T_F_T or - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_F_F_T_T_T or - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_T_T or - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_F_F_T_F_F or - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_F_F_T_T_F or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_F_T_T or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_T_T or - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_F_F_T_F_T or - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_F_F_T_T_T or - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_T_T or - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_F_F_T_F_F or - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_F_F_T_T_F or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_F_T_T or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_T_T or - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_F_F_T_F_T or - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_F_F_T_T_T or - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_T_T or - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_F_F_T_F_F or - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_F_F_T_T_F or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_F_T_T or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_T_T or - WILL_FIRE_RL_cpDispatch_F_F_T_F_T_F_F_T_F_T or - WILL_FIRE_RL_cpDispatch_F_F_T_F_T_F_F_T_T_T or - WILL_FIRE_RL_cpDispatch_F_F_T_F_T_T_T or - WILL_FIRE_RL_cpDispatch_F_F_T_F_T_F_F_T_F_F or - WILL_FIRE_RL_cpDispatch_F_F_T_F_T_F_F_T_T_F or - WILL_FIRE_RL_cpDispatch_F_F_F_F_T_F_T_T or - WILL_FIRE_RL_cpDispatch_F_F_F_F_T_T_T or - WILL_FIRE_RL_cpDispatch_F_F_T_T_F_F_T_F_T or - WILL_FIRE_RL_cpDispatch_F_F_T_T_F_F_T_T_T or - WILL_FIRE_RL_cpDispatch_F_F_T_T_T_T or - WILL_FIRE_RL_cpDispatch_F_F_T_T_F_F_T_F_F or - WILL_FIRE_RL_cpDispatch_F_F_T_T_F_F_T_T_F or + always@(WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_F_T_T or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_T_T or + WILL_FIRE_RL_cpDispatch_F_F_T_E14_F_F_T_F_T or + WILL_FIRE_RL_cpDispatch_F_F_T_E14_F_F_T_T_T or + WILL_FIRE_RL_cpDispatch_F_F_T_E14_T_T or + WILL_FIRE_RL_cpDispatch_F_F_T_E14_F_F_T_F_F or + WILL_FIRE_RL_cpDispatch_F_F_T_E14_F_F_T_T_F or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_F_T_T or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_T_T or + WILL_FIRE_RL_cpDispatch_F_F_T_E13_F_F_T_F_T or + WILL_FIRE_RL_cpDispatch_F_F_T_E13_F_F_T_T_T or + WILL_FIRE_RL_cpDispatch_F_F_T_E13_T_T or + WILL_FIRE_RL_cpDispatch_F_F_T_E13_F_F_T_F_F or + WILL_FIRE_RL_cpDispatch_F_F_T_E13_F_F_T_T_F or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_F_T_T or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_T_T or + WILL_FIRE_RL_cpDispatch_F_F_T_E12_F_F_T_F_T or + WILL_FIRE_RL_cpDispatch_F_F_T_E12_F_F_T_T_T or + WILL_FIRE_RL_cpDispatch_F_F_T_E12_T_T or + WILL_FIRE_RL_cpDispatch_F_F_T_E12_F_F_T_F_F or + WILL_FIRE_RL_cpDispatch_F_F_T_E12_F_F_T_T_F or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_F_T_T or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_T_T or + WILL_FIRE_RL_cpDispatch_F_F_T_E11_F_F_T_F_T or + WILL_FIRE_RL_cpDispatch_F_F_T_E11_F_F_T_T_T or + WILL_FIRE_RL_cpDispatch_F_F_T_E11_T_T or + WILL_FIRE_RL_cpDispatch_F_F_T_E11_F_F_T_F_F or + WILL_FIRE_RL_cpDispatch_F_F_T_E11_F_F_T_T_F or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_F_T_T or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_T_T or + WILL_FIRE_RL_cpDispatch_F_F_T_E10_F_F_T_F_T or + WILL_FIRE_RL_cpDispatch_F_F_T_E10_F_F_T_T_T or + WILL_FIRE_RL_cpDispatch_F_F_T_E10_T_T or + WILL_FIRE_RL_cpDispatch_F_F_T_E10_F_F_T_F_F or + WILL_FIRE_RL_cpDispatch_F_F_T_E10_F_F_T_T_F or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_F_T_T or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_T_T or + WILL_FIRE_RL_cpDispatch_F_F_T_E9_F_F_T_F_T or + WILL_FIRE_RL_cpDispatch_F_F_T_E9_F_F_T_T_T or + WILL_FIRE_RL_cpDispatch_F_F_T_E9_T_T or + WILL_FIRE_RL_cpDispatch_F_F_T_E9_F_F_T_F_F or + WILL_FIRE_RL_cpDispatch_F_F_T_E9_F_F_T_T_F or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_T_T or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_T_T or + WILL_FIRE_RL_cpDispatch_F_F_T_E8_F_F_T_F_T or + WILL_FIRE_RL_cpDispatch_F_F_T_E8_F_F_T_T_T or + WILL_FIRE_RL_cpDispatch_F_F_T_E8_T_T or + WILL_FIRE_RL_cpDispatch_F_F_T_E8_F_F_T_F_F or + WILL_FIRE_RL_cpDispatch_F_F_T_E8_F_F_T_T_F or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_T_T or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_T_T or + WILL_FIRE_RL_cpDispatch_F_F_T_E7_F_F_T_F_T or + WILL_FIRE_RL_cpDispatch_F_F_T_E7_F_F_T_T_T or + WILL_FIRE_RL_cpDispatch_F_F_T_E7_T_T or + WILL_FIRE_RL_cpDispatch_F_F_T_E7_F_F_T_F_F or + WILL_FIRE_RL_cpDispatch_F_F_T_E7_F_F_T_T_F or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_F_T_T or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_T_T or + WILL_FIRE_RL_cpDispatch_F_F_T_E6_F_F_T_F_T or + WILL_FIRE_RL_cpDispatch_F_F_T_E6_F_F_T_T_T or + WILL_FIRE_RL_cpDispatch_F_F_T_E6_T_T or + WILL_FIRE_RL_cpDispatch_F_F_T_E6_F_F_T_F_F or + WILL_FIRE_RL_cpDispatch_F_F_T_E6_F_F_T_T_F or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_T_T or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_T_T or + WILL_FIRE_RL_cpDispatch_F_F_T_E5_F_F_T_F_T or + WILL_FIRE_RL_cpDispatch_F_F_T_E5_F_F_T_T_T or + WILL_FIRE_RL_cpDispatch_F_F_T_E5_T_T or + WILL_FIRE_RL_cpDispatch_F_F_T_E5_F_F_T_F_F or + WILL_FIRE_RL_cpDispatch_F_F_T_E5_F_F_T_T_F or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_F_T_T or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_T_T or + WILL_FIRE_RL_cpDispatch_F_F_T_E4_F_F_T_F_T or + WILL_FIRE_RL_cpDispatch_F_F_T_E4_F_F_T_T_T or + WILL_FIRE_RL_cpDispatch_F_F_T_E4_T_T or + WILL_FIRE_RL_cpDispatch_F_F_T_E4_F_F_T_F_F or + WILL_FIRE_RL_cpDispatch_F_F_T_E4_F_F_T_T_F or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_F_T_T or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_T_T or + WILL_FIRE_RL_cpDispatch_F_F_T_E3_F_F_T_F_T or + WILL_FIRE_RL_cpDispatch_F_F_T_E3_F_F_T_T_T or + WILL_FIRE_RL_cpDispatch_F_F_T_E3_T_T or + WILL_FIRE_RL_cpDispatch_F_F_T_E3_F_F_T_F_F or + WILL_FIRE_RL_cpDispatch_F_F_T_E3_F_F_T_T_F or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_F_T_T or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_T_T or + WILL_FIRE_RL_cpDispatch_F_F_T_E2_F_F_T_F_T or + WILL_FIRE_RL_cpDispatch_F_F_T_E2_F_F_T_T_T or + WILL_FIRE_RL_cpDispatch_F_F_T_E2_T_T or + WILL_FIRE_RL_cpDispatch_F_F_T_E2_F_F_T_F_F or + WILL_FIRE_RL_cpDispatch_F_F_T_E2_F_F_T_T_F or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_T_T or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_T_T or + WILL_FIRE_RL_cpDispatch_F_F_T_E1_F_F_T_F_T or + WILL_FIRE_RL_cpDispatch_F_F_T_E1_F_F_T_T_T or + WILL_FIRE_RL_cpDispatch_F_F_T_E1_T_T or + WILL_FIRE_RL_cpDispatch_F_F_T_E1_F_F_T_F_F or + WILL_FIRE_RL_cpDispatch_F_F_T_E1_F_F_T_T_F or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_T_T or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_T_T or + WILL_FIRE_RL_cpDispatch_F_F_T_E0_F_F_T_F_T or + WILL_FIRE_RL_cpDispatch_F_F_T_E0_F_F_T_T_T or + WILL_FIRE_RL_cpDispatch_F_F_T_E0_T_T or + WILL_FIRE_RL_cpDispatch_F_F_T_E0_F_F_T_F_F or + WILL_FIRE_RL_cpDispatch_F_F_T_E0_F_F_T_T_F or WILL_FIRE_RL_cpDispatch_T_F_F_F_F_T_F or WILL_FIRE_RL_cpDispatch_T_F_F_F_F_T_T or WILL_FIRE_RL_reqRcv or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_T_F or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_F_F_T or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_F_T_F or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_T_F or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_F_F_T or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_F_T or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_T_F or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_T_F or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_F_F_F_T or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_F_F_T or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_F_T or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_T_F or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_T_F or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_F_F_F_F_F_F or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_F_F_F_F_F_T or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_F_F_F_F_T or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_F_F_F_T or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_F_F_T or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_F_T_F or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_T_F or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_F_F_F_F_F_F or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_F_F_F_F_F_T or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_F_F_F_F_T or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_F_F_F_T or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_F_F_T or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_F_T_F or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_T_F or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_F_F_F_F_F_F or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_F_F_F_F_F_T or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_F_F_F_F_T or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_F_F_F_T or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_F_F_T or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_F_T_F or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_T_F or - WILL_FIRE_RL_cpDispatch_F_F_F_F_T_F_F_F_F_F_F or - WILL_FIRE_RL_cpDispatch_F_F_F_F_T_F_F_F_F_F_T or - WILL_FIRE_RL_cpDispatch_F_F_F_F_T_F_F_F_F_T or - WILL_FIRE_RL_cpDispatch_F_F_F_F_T_F_F_F_T or - WILL_FIRE_RL_cpDispatch_F_F_F_F_T_F_F_T or - WILL_FIRE_RL_cpDispatch_F_F_F_F_T_F_T_F or - WILL_FIRE_RL_cpDispatch_F_F_F_F_T_T_F or + WILL_FIRE_RL_cpDispatch_F_F_F_F_OOB or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_F_F_F_F_F_F or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_F_F_F_F_F_T or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_F_F_F_F_T or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_F_F_F_T or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_F_F_T or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_F_T_F or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_T_F or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_F_F_F_F_F_F or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_F_F_F_F_F_T or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_F_F_F_F_T or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_F_F_F_T or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_F_F_T or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_F_T_F or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_T_F or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_F_F_F_F_F_F or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_F_F_F_F_F_T or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_F_F_F_F_T or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_F_F_F_T or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_F_F_T or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_F_T_F or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_T_F or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_F_F_F_F_F_F or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_F_F_F_F_F_T or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_F_F_F_F_T or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_F_F_F_T or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_F_F_T or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_F_T_F or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_T_F or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_F_F_F_F_F_F or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_F_F_F_F_F_T or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_F_F_F_F_T or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_F_F_F_T or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_F_F_T or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_F_T_F or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_T_F or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_F_F_F_F_F_F or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_F_F_F_F_F_T or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_F_F_F_F_T or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_F_F_F_T or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_F_F_T or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_F_T_F or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_T_F or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_F_F_F_F_F or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_F_F_F_F_T or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_F_F_F_T or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_F_F_T or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_F_T or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_T_F or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_T_F or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_F_F_F_F_F or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_F_F_F_F_T or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_F_F_F_T or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_F_F_T or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_F_T or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_T_F or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_T_F or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_F_F_F_F_F_F or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_F_F_F_F_F_T or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_F_F_F_F_T or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_F_F_F_T or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_F_F_T or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_F_T_F or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_T_F or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_F_F_F_F_F or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_F_F_F_F_T or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_F_F_F_T or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_F_F_T or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_F_T or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_T_F or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_T_F or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_F_F_F_F_F_F or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_F_F_F_F_F_T or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_F_F_F_F_T or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_F_F_F_T or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_F_F_T or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_F_T_F or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_T_F or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_F_F_F_F_F_F or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_F_F_F_F_F_T or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_F_F_F_F_T or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_F_F_F_T or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_F_F_T or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_F_T_F or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_T_F or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_F_F_F_F_F_F or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_F_F_F_F_F_T or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_F_F_F_F_T or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_F_F_F_T or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_F_F_T or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_F_T_F or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_T_F or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_F_F_F_F_F or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_F_F_F_F_T or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_F_F_F_T or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_F_F_T or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_F_T or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_T_F or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_T_F or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_F_F_F_F_F or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_F_F_F_F_T or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_F_F_F_T or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_F_F_T or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_F_T or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_T_F or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_T_F or WILL_FIRE_RL_cpDispatch_F_F_F_T or - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F or - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F or - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T or - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T or - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F or - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F or - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T or - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T or - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F or - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F or - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T or - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T or - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F or - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F or - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T or - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_F_T or - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_T_F or - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F or - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T or - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_T or - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_T_F or - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_F_F_F_F or - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_F_F_F_T or - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_F_T or - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_T_F or - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_F_F_F_F or - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_F_F_F_T or - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_F_T or - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_T_F or - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_F_F_F_F or - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_F_F_F_T or - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_F_T or - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_T_F or - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_F_F_F_F or - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_F_F_F_T or - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_F_T or - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_T_F or - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_F_F_F or - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_F_F_T or - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_T or - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_T_F or - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_F_F_F_F or - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_F_F_F_T or - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_F_T or - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_T_F or - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_F_F_F_F or - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_F_F_F_T or - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_F_T or - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_T_F or - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_F_F_F_F or - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_F_F_F_T or - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_F_T or - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_T_F or - WILL_FIRE_RL_cpDispatch_F_F_T_F_T_F_F_F_F or - WILL_FIRE_RL_cpDispatch_F_F_T_F_T_F_F_F_T or - WILL_FIRE_RL_cpDispatch_F_F_T_F_T_F_T or - WILL_FIRE_RL_cpDispatch_F_F_T_F_T_T_F or - WILL_FIRE_RL_cpDispatch_F_F_T_T_F_F_F_F or - WILL_FIRE_RL_cpDispatch_F_F_T_T_F_F_F_T or - WILL_FIRE_RL_cpDispatch_F_F_T_T_F_T or - WILL_FIRE_RL_cpDispatch_F_F_T_T_T_F or + WILL_FIRE_RL_cpDispatch_F_F_T_OOB or + WILL_FIRE_RL_cpDispatch_F_F_T_E14_F_F_F_F or + WILL_FIRE_RL_cpDispatch_F_F_T_E14_F_F_F_T or + WILL_FIRE_RL_cpDispatch_F_F_T_E14_F_T or + WILL_FIRE_RL_cpDispatch_F_F_T_E14_T_F or + WILL_FIRE_RL_cpDispatch_F_F_T_E13_F_F_F_F or + WILL_FIRE_RL_cpDispatch_F_F_T_E13_F_F_F_T or + WILL_FIRE_RL_cpDispatch_F_F_T_E13_F_T or + WILL_FIRE_RL_cpDispatch_F_F_T_E13_T_F or + WILL_FIRE_RL_cpDispatch_F_F_T_E12_F_F_F_F or + WILL_FIRE_RL_cpDispatch_F_F_T_E12_F_F_F_T or + WILL_FIRE_RL_cpDispatch_F_F_T_E12_F_T or + WILL_FIRE_RL_cpDispatch_F_F_T_E12_T_F or + WILL_FIRE_RL_cpDispatch_F_F_T_E11_F_F_F_F or + WILL_FIRE_RL_cpDispatch_F_F_T_E11_F_F_F_T or + WILL_FIRE_RL_cpDispatch_F_F_T_E11_F_T or + WILL_FIRE_RL_cpDispatch_F_F_T_E11_T_F or + WILL_FIRE_RL_cpDispatch_F_F_T_E10_F_F_F_F or + WILL_FIRE_RL_cpDispatch_F_F_T_E10_F_F_F_T or + WILL_FIRE_RL_cpDispatch_F_F_T_E10_F_T or + WILL_FIRE_RL_cpDispatch_F_F_T_E10_T_F or + WILL_FIRE_RL_cpDispatch_F_F_T_E9_F_F_F_F or + WILL_FIRE_RL_cpDispatch_F_F_T_E9_F_F_F_T or + WILL_FIRE_RL_cpDispatch_F_F_T_E9_F_T or + WILL_FIRE_RL_cpDispatch_F_F_T_E9_T_F or + WILL_FIRE_RL_cpDispatch_F_F_T_E8_F_F_F_F or + WILL_FIRE_RL_cpDispatch_F_F_T_E8_F_F_F_T or + WILL_FIRE_RL_cpDispatch_F_F_T_E8_F_T or + WILL_FIRE_RL_cpDispatch_F_F_T_E8_T_F or + WILL_FIRE_RL_cpDispatch_F_F_T_E7_F_F_F_F or + WILL_FIRE_RL_cpDispatch_F_F_T_E7_F_F_F_T or + WILL_FIRE_RL_cpDispatch_F_F_T_E7_F_T or + WILL_FIRE_RL_cpDispatch_F_F_T_E7_T_F or + WILL_FIRE_RL_cpDispatch_F_F_T_E6_F_F_F_F or + WILL_FIRE_RL_cpDispatch_F_F_T_E6_F_F_F_T or + WILL_FIRE_RL_cpDispatch_F_F_T_E6_F_T or + WILL_FIRE_RL_cpDispatch_F_F_T_E6_T_F or + WILL_FIRE_RL_cpDispatch_F_F_T_E5_F_F_F_F or + WILL_FIRE_RL_cpDispatch_F_F_T_E5_F_F_F_T or + WILL_FIRE_RL_cpDispatch_F_F_T_E5_F_T or + WILL_FIRE_RL_cpDispatch_F_F_T_E5_T_F or + WILL_FIRE_RL_cpDispatch_F_F_T_E4_F_F_F_F or + WILL_FIRE_RL_cpDispatch_F_F_T_E4_F_F_F_T or + WILL_FIRE_RL_cpDispatch_F_F_T_E4_F_T or + WILL_FIRE_RL_cpDispatch_F_F_T_E4_T_F or + WILL_FIRE_RL_cpDispatch_F_F_T_E3_F_F_F_F or + WILL_FIRE_RL_cpDispatch_F_F_T_E3_F_F_F_T or + WILL_FIRE_RL_cpDispatch_F_F_T_E3_F_T or + WILL_FIRE_RL_cpDispatch_F_F_T_E3_T_F or + WILL_FIRE_RL_cpDispatch_F_F_T_E2_F_F_F_F or + WILL_FIRE_RL_cpDispatch_F_F_T_E2_F_F_F_T or + WILL_FIRE_RL_cpDispatch_F_F_T_E2_F_T or + WILL_FIRE_RL_cpDispatch_F_F_T_E2_T_F or + WILL_FIRE_RL_cpDispatch_F_F_T_E1_F_F_F_F or + WILL_FIRE_RL_cpDispatch_F_F_T_E1_F_F_F_T or + WILL_FIRE_RL_cpDispatch_F_F_T_E1_F_T or + WILL_FIRE_RL_cpDispatch_F_F_T_E1_T_F or + WILL_FIRE_RL_cpDispatch_F_F_T_E0_F_F_F_F or + WILL_FIRE_RL_cpDispatch_F_F_T_E0_F_F_F_T or + WILL_FIRE_RL_cpDispatch_F_F_T_E0_F_T or + WILL_FIRE_RL_cpDispatch_F_F_T_E0_T_F or WILL_FIRE_RL_rom_serverAdapter_stageReadResponseAlways or WILL_FIRE_RL_cpDispatch_F_T_F_T or WILL_FIRE_RL_cpDispatch_F_T_T_F_F or @@ -11338,283 +11251,283 @@ module mkOCCP(pciDevice, WILL_FIRE_RL_cpDispatch_T_F_F_T or WILL_FIRE_RL_cpDispatch_T_F_T or WILL_FIRE_RL_cpDispatch_T_T) case (1'b1) - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_F_F_T_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_F_F_T_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_F_F_T_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_F_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_F_F_T_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_F_T_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_F_F_T_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_F_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_F_F_T_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_F_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_F_F_T_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_F_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_T_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_T_F_F_T_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_T_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_T_F_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_T_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_T_F_F_T_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_T_F_F_T_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_F_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E14_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E14_F_F_T_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E14_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E14_F_F_T_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E14_F_F_T_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_F_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E13_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E13_F_F_T_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E13_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E13_F_F_T_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E13_F_F_T_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_F_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E12_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E12_F_F_T_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E12_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E12_F_F_T_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E12_F_F_T_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_F_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E11_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E11_F_F_T_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E11_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E11_F_F_T_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E11_F_F_T_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_F_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E10_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E10_F_F_T_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E10_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E10_F_F_T_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E10_F_F_T_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_F_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E9_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E9_F_F_T_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E9_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E9_F_F_T_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E9_F_F_T_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E8_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E8_F_F_T_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E8_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E8_F_F_T_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E8_F_F_T_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E7_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E7_F_F_T_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E7_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E7_F_F_T_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E7_F_F_T_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_F_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E6_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E6_F_F_T_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E6_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E6_F_F_T_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E6_F_F_T_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E5_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E5_F_F_T_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E5_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E5_F_F_T_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E5_F_F_T_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_F_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E4_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E4_F_F_T_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E4_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E4_F_F_T_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E4_F_F_T_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_F_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E3_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E3_F_F_T_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E3_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E3_F_F_T_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E3_F_F_T_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_F_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E2_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E2_F_F_T_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E2_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E2_F_F_T_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E2_F_F_T_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E1_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E1_F_F_T_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E1_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E1_F_F_T_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E1_F_F_T_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E0_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E0_F_F_T_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E0_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E0_F_F_T_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E0_F_F_T_T_F || WILL_FIRE_RL_cpDispatch_T_F_F_F_F_T_F || WILL_FIRE_RL_cpDispatch_T_F_F_F_F_T_T: dispatched$D_IN = 1'd1; WILL_FIRE_RL_reqRcv: dispatched$D_IN = 1'd0; - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_F_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_F_F_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_F_F_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_F_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_F_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_F_F_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_F_F_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_F_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_F_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_F_F_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_F_F_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_F_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_F_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_T_F_F_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_T_F_F_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_T_F_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_T_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_T_F_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_T_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_OOB || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_F_F_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_F_F_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_F_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_F_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_F_F_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_F_F_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_F_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_F_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_F_F_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_F_F_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_F_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_F_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_F_F_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_F_F_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_F_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_F_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_F_F_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_F_F_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_F_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_F_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_F_F_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_F_F_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_F_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_F_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_F_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_F_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_F_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_F_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_F_F_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_F_F_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_F_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_F_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_F_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_F_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_F_F_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_F_F_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_F_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_F_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_F_F_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_F_F_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_F_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_F_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_F_F_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_F_F_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_F_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_F_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_F_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_F_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_F_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_F_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_T_F || WILL_FIRE_RL_cpDispatch_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_T_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_T_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_T_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_OOB || + WILL_FIRE_RL_cpDispatch_F_F_T_E14_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E14_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E14_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E14_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E13_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E13_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E13_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E13_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E12_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E12_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E12_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E12_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E11_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E11_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E11_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E11_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E10_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E10_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E10_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E10_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E9_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E9_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E9_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E9_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E8_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E8_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E8_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E8_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E7_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E7_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E7_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E7_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E6_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E6_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E6_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E6_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E5_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E5_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E5_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E5_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E4_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E4_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E4_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E4_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E3_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E3_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E3_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E3_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E2_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E2_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E2_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E2_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E1_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E1_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E1_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E1_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E0_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E0_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E0_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E0_T_F || WILL_FIRE_RL_rom_serverAdapter_stageReadResponseAlways || WILL_FIRE_RL_cpDispatch_F_T_F_T || WILL_FIRE_RL_cpDispatch_F_T_T_F_F || @@ -11636,280 +11549,279 @@ module mkOCCP(pciDevice, default: dispatched$D_IN = 1'b0 /* unspecified value */ ; endcase assign dispatched$EN = - WILL_FIRE_RL_reqRcv || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_F_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_F_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_F_F_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_F_F_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_F_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_F_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_F_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_F_F_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_F_F_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_F_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_F_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_F_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_F_F_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_F_F_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_F_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_F_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_F_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_T_F_F_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_T_F_F_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_T_F_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_T_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_T_F_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_T_F_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_T_T_T || + WILL_FIRE_RL_reqRcv || WILL_FIRE_RL_cpDispatch_F_F_F_F_OOB || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_F_F_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_F_F_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_F_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_F_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_F_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_F_F_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_F_F_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_F_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_F_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_F_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_F_F_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_F_F_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_F_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_F_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_F_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_F_F_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_F_F_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_F_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_F_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_F_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_F_F_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_F_F_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_F_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_F_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_F_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_F_F_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_F_F_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_F_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_F_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_F_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_F_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_F_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_F_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_F_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_F_F_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_F_F_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_F_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_F_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_F_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_F_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_F_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_F_F_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_F_F_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_F_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_F_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_F_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_F_F_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_F_F_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_F_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_F_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_F_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_F_F_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_F_F_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_F_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_F_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_F_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_F_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_F_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_F_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_F_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_T_T || WILL_FIRE_RL_cpDispatch_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_F_F_T_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_F_F_T_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_F_F_T_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_F_F_T_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_F_T_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_F_F_T_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_F_F_T_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_F_F_T_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_T_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_T_F_F_T_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_T_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_T_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_T_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_T_F_F_T_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_T_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_T_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_T_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_OOB || + WILL_FIRE_RL_cpDispatch_F_F_T_E14_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E14_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E14_F_F_T_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E14_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E14_F_F_T_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E14_F_F_T_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E14_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E14_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E14_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E13_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E13_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E13_F_F_T_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E13_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E13_F_F_T_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E13_F_F_T_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E13_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E13_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E13_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E12_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E12_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E12_F_F_T_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E12_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E12_F_F_T_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E12_F_F_T_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E12_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E12_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E12_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E11_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E11_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E11_F_F_T_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E11_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E11_F_F_T_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E11_F_F_T_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E11_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E11_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E11_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E10_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E10_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E10_F_F_T_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E10_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E10_F_F_T_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E10_F_F_T_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E10_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E10_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E10_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E9_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E9_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E9_F_F_T_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E9_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E9_F_F_T_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E9_F_F_T_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E9_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E9_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E9_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E8_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E8_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E8_F_F_T_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E8_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E8_F_F_T_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E8_F_F_T_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E8_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E8_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E8_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E7_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E7_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E7_F_F_T_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E7_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E7_F_F_T_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E7_F_F_T_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E7_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E7_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E7_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E6_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E6_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E6_F_F_T_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E6_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E6_F_F_T_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E6_F_F_T_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E6_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E6_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E6_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E5_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E5_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E5_F_F_T_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E5_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E5_F_F_T_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E5_F_F_T_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E5_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E5_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E5_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E4_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E4_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E4_F_F_T_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E4_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E4_F_F_T_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E4_F_F_T_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E4_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E4_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E4_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E3_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E3_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E3_F_F_T_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E3_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E3_F_F_T_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E3_F_F_T_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E3_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E3_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E3_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E2_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E2_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E2_F_F_T_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E2_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E2_F_F_T_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E2_F_F_T_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E2_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E2_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E2_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E1_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E1_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E1_F_F_T_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E1_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E1_F_F_T_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E1_F_F_T_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E1_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E1_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E1_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E0_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E0_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E0_F_F_T_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E0_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E0_F_F_T_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E0_F_F_T_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E0_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E0_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E0_T_T || WILL_FIRE_RL_rom_serverAdapter_stageReadResponseAlways || WILL_FIRE_RL_cpDispatch_F_T_F_T || WILL_FIRE_RL_cpDispatch_F_T_T_F_F || @@ -11930,6 +11842,22 @@ module mkOCCP(pciDevice, WILL_FIRE_RL_cpDispatch_T_F_T || WILL_FIRE_RL_cpDispatch_T_T ; + // register dna_cnt + assign dna_cnt$D_IN = dna_cnt + 7'd1 ; + assign dna_cnt$EN = dna_cnt != 7'd127 ; + + // register dna_rdReg + assign dna_rdReg$D_IN = dna_rdReg_1$whas ; + assign dna_rdReg$EN = 1'd1 ; + + // register dna_shftReg + assign dna_shftReg$D_IN = dna_shftReg_1$whas ; + assign dna_shftReg$EN = 1'd1 ; + + // register dna_sr + assign dna_sr$D_IN = { dna_sr[55:0], dna_dna$DOUT } ; + assign dna_sr$EN = dna_cnt >= 7'd3 && dna_cnt <= 7'd116 && !dna_cnt[0] ; + // register readCntReg assign readCntReg$D_IN = WILL_FIRE_RL_cpDispatch_T_F_F_F_F_F_F_F_F_F_T ? @@ -11994,17 +11922,17 @@ module mkOCCP(pciDevice, timeServ_fracSeconds - timeServ_lastSecond ; assign timeServ_delSecond$EN = timeServ_ppsExtSync_d2 && !timeServ_ppsExtSyncD && - !timeServ_refFromRise_3_ULE_199800000___d6126 && - timeServ_refFromRise_3_ULT_200200000___d5828 ; + !timeServ_refFromRise_3_ULE_199800000___d48 && + timeServ_refFromRise_3_ULT_200200000___d50 ; // register timeServ_fracInc - assign timeServ_fracInc$D_IN = timeServ_fracInc + x__h4421 ; + assign timeServ_fracInc$D_IN = timeServ_fracInc + x__h4408 ; assign timeServ_fracInc$EN = timeServ_ppsExtSync_d2_2_AND_NOT_timeServ_ppsE_ETC___d70 ; // register timeServ_fracSeconds assign timeServ_fracSeconds$D_IN = - timeServ_jamFrac ? timeServ_jamFracVal : x__h4649 ; + timeServ_jamFrac ? timeServ_jamFracVal : x__h4636 ; assign timeServ_fracSeconds$EN = 1'd1 ; // register timeServ_gpsInSticky @@ -12017,15 +11945,15 @@ module mkOCCP(pciDevice, // register timeServ_jamFracVal assign timeServ_jamFracVal$D_IN = - timeServ_jamFrac_1$whas ? x__h3700 : 50'd0 ; + timeServ_jamFrac_1$whas ? x__h3688 : 50'd0 ; assign timeServ_jamFracVal$EN = 1'd1 ; // register timeServ_lastSecond assign timeServ_lastSecond$D_IN = timeServ_fracSeconds ; assign timeServ_lastSecond$EN = timeServ_ppsExtSync_d2 && !timeServ_ppsExtSyncD && - !timeServ_refFromRise_3_ULE_199800000___d6126 && - timeServ_refFromRise_3_ULT_200200000___d5828 ; + !timeServ_refFromRise_3_ULE_199800000___d48 && + timeServ_refFromRise_3_ULT_200200000___d50 ; // register timeServ_now assign timeServ_now$D_IN = @@ -12078,8 +12006,8 @@ module mkOCCP(pciDevice, // register timeServ_ppsOK assign timeServ_ppsOK$D_IN = timeServ_ppsExtSync_d2 && !timeServ_ppsExtSyncD && - !timeServ_refFromRise_3_ULE_199800000___d6126 && - timeServ_refFromRise_3_ULT_200200000___d5828 || + !timeServ_refFromRise_3_ULE_199800000___d48 && + timeServ_refFromRise_3_ULT_200200000___d50 || timeServ_ppsOK && !timeServ_ppsLost ; assign timeServ_ppsOK$EN = 1'd1 ; @@ -12091,16 +12019,16 @@ module mkOCCP(pciDevice, assign timeServ_refFreeSamp$D_IN = timeServ_refFreeCount ; assign timeServ_refFreeSamp$EN = timeServ_ppsExtSync_d2 && !timeServ_ppsExtSyncD && - !timeServ_refFromRise_3_ULE_199800000___d6126 && - timeServ_refFromRise_3_ULT_200200000___d5828 ; + !timeServ_refFromRise_3_ULE_199800000___d48 && + timeServ_refFromRise_3_ULT_200200000___d50 ; // register timeServ_refFreeSpan assign timeServ_refFreeSpan$D_IN = timeServ_refFreeCount - timeServ_refFreeSamp ; assign timeServ_refFreeSpan$EN = timeServ_ppsExtSync_d2 && !timeServ_ppsExtSyncD && - !timeServ_refFromRise_3_ULE_199800000___d6126 && - timeServ_refFromRise_3_ULT_200200000___d5828 ; + !timeServ_refFromRise_3_ULE_199800000___d48 && + timeServ_refFromRise_3_ULT_200200000___d50 ; // register timeServ_refFromRise assign timeServ_refFromRise$D_IN = @@ -12111,7 +12039,7 @@ module mkOCCP(pciDevice, // register timeServ_refPerCount assign timeServ_refPerCount$D_IN = - IF_timeServ_ppsOK_7_THEN_timeServ_ppsExtSync_d_ETC___d6035 ? + IF_timeServ_ppsOK_7_THEN_timeServ_ppsExtSync_d_ETC___d39 ? 28'd0 : timeServ_refPerCount + 28'd1 ; assign timeServ_refPerCount$EN = 1'd1 ; @@ -12120,10 +12048,10 @@ module mkOCCP(pciDevice, assign timeServ_refSecCount$D_IN = timeServ_setRefF$dEMPTY_N ? timeServ_setRefF$dD_OUT[63:32] : - x__h4715 ; + x__h4702 ; assign timeServ_refSecCount$EN = timeServ_setRefF$dEMPTY_N || - IF_timeServ_ppsOK_7_THEN_timeServ_ppsExtSync_d_ETC___d6035 ; + IF_timeServ_ppsOK_7_THEN_timeServ_ppsExtSync_d_ETC___d39 ; // register timeServ_rplTimeControl assign timeServ_rplTimeControl$D_IN = cpReq[32:28] ; @@ -12148,3159 +12076,3092 @@ module mkOCCP(pciDevice, cpReq[59:28] == 32'hC0DEFFFF ; assign warmResetP$EN = 1'd1 ; - // register wci_busy - assign wci_busy$D_IN = !MUX_wci_busy$write_1__SEL_1 ; - assign wci_busy$EN = - WILL_FIRE_RL_wci_wrkBusy && - (!wci_respTimr_02_ULT_1_SL_wci_wTimeout_03_04___d5829 || - wci_wciResponse$wget[33:32] != 2'd0) || - WILL_FIRE_RL_cpDispatch_F_F_F_F_T_F_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_T_T_T ; - - // register wci_busy_1 - assign wci_busy_1$D_IN = !MUX_wci_busy_1$write_1__SEL_1 ; - assign wci_busy_1$EN = - WILL_FIRE_RL_wci_wrkBusy_1 && - (!wci_respTimr_1_42_ULT_1_SL_wci_wTimeout_1_43_44___d5830 || - wci_wciResponse_1$wget[33:32] != 2'd0) || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_F_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_T_T_T ; - - // register wci_busy_10 - assign wci_busy_10$D_IN = !MUX_wci_busy_10$write_1__SEL_1 ; - assign wci_busy_10$EN = - WILL_FIRE_RL_wci_wrkBusy_10 && - (!wci_respTimr_10_602_ULT_1_SL_wci_wTimeout_10_6_ETC___d5839 || - wci_wciResponse_10$wget[33:32] != 2'd0) || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_T_T ; - - // register wci_busy_11 - assign wci_busy_11$D_IN = !MUX_wci_busy_11$write_1__SEL_1 ; - assign wci_busy_11$EN = - WILL_FIRE_RL_wci_wrkBusy_11 && - (!wci_respTimr_11_742_ULT_1_SL_wci_wTimeout_11_7_ETC___d5840 || - wci_wciResponse_11$wget[33:32] != 2'd0) || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_T_T ; - - // register wci_busy_12 - assign wci_busy_12$D_IN = !MUX_wci_busy_12$write_1__SEL_1 ; - assign wci_busy_12$EN = - WILL_FIRE_RL_wci_wrkBusy_12 && - (!wci_respTimr_12_882_ULT_1_SL_wci_wTimeout_12_8_ETC___d5841 || - wci_wciResponse_12$wget[33:32] != 2'd0) || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T ; - - // register wci_busy_13 - assign wci_busy_13$D_IN = !MUX_wci_busy_13$write_1__SEL_1 ; - assign wci_busy_13$EN = - WILL_FIRE_RL_wci_wrkBusy_13 && - (!wci_respTimr_13_022_ULT_1_SL_wci_wTimeout_13_0_ETC___d5842 || - wci_wciResponse_13$wget[33:32] != 2'd0) || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T ; - - // register wci_busy_14 - assign wci_busy_14$D_IN = !MUX_wci_busy_14$write_1__SEL_1 ; - assign wci_busy_14$EN = - WILL_FIRE_RL_wci_wrkBusy_14 && - (!wci_respTimr_14_162_ULT_1_SL_wci_wTimeout_14_1_ETC___d5843 || - wci_wciResponse_14$wget[33:32] != 2'd0) || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T ; - - // register wci_busy_2 - assign wci_busy_2$D_IN = !MUX_wci_busy_2$write_1__SEL_1 ; - assign wci_busy_2$EN = - WILL_FIRE_RL_wci_wrkBusy_2 && - (!wci_respTimr_2_82_ULT_1_SL_wci_wTimeout_2_83_84___d5831 || - wci_wciResponse_2$wget[33:32] != 2'd0) || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_F_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_T_T ; - - // register wci_busy_3 - assign wci_busy_3$D_IN = !MUX_wci_busy_3$write_1__SEL_1 ; - assign wci_busy_3$EN = - WILL_FIRE_RL_wci_wrkBusy_3 && - (!wci_respTimr_3_22_ULT_1_SL_wci_wTimeout_3_23_24___d5832 || - wci_wciResponse_3$wget[33:32] != 2'd0) || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_F_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_T_T ; - - // register wci_busy_4 - assign wci_busy_4$D_IN = !MUX_wci_busy_4$write_1__SEL_1 ; - assign wci_busy_4$EN = - WILL_FIRE_RL_wci_wrkBusy_4 && - (!wci_respTimr_4_62_ULT_1_SL_wci_wTimeout_4_63_64___d5833 || - wci_wciResponse_4$wget[33:32] != 2'd0) || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_T_T ; - - // register wci_busy_5 - assign wci_busy_5$D_IN = !MUX_wci_busy_5$write_1__SEL_1 ; - assign wci_busy_5$EN = - WILL_FIRE_RL_wci_wrkBusy_5 && - (!wci_respTimr_5_02_ULT_1_SL_wci_wTimeout_5_03_04___d5834 || - wci_wciResponse_5$wget[33:32] != 2'd0) || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_T_T ; - - // register wci_busy_6 - assign wci_busy_6$D_IN = !MUX_wci_busy_6$write_1__SEL_1 ; - assign wci_busy_6$EN = - WILL_FIRE_RL_wci_wrkBusy_6 && - (!wci_respTimr_6_042_ULT_1_SL_wci_wTimeout_6_043_ETC___d5835 || - wci_wciResponse_6$wget[33:32] != 2'd0) || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_F_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_T_T ; - - // register wci_busy_7 - assign wci_busy_7$D_IN = !MUX_wci_busy_7$write_1__SEL_1 ; - assign wci_busy_7$EN = - WILL_FIRE_RL_wci_wrkBusy_7 && - (!wci_respTimr_7_182_ULT_1_SL_wci_wTimeout_7_183_ETC___d5836 || - wci_wciResponse_7$wget[33:32] != 2'd0) || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_T_T ; - - // register wci_busy_8 - assign wci_busy_8$D_IN = !MUX_wci_busy_8$write_1__SEL_1 ; - assign wci_busy_8$EN = - WILL_FIRE_RL_wci_wrkBusy_8 && - (!wci_respTimr_8_322_ULT_1_SL_wci_wTimeout_8_323_ETC___d5837 || - wci_wciResponse_8$wget[33:32] != 2'd0) || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_T_T ; - - // register wci_busy_9 - assign wci_busy_9$D_IN = !MUX_wci_busy_9$write_1__SEL_1 ; - assign wci_busy_9$EN = - WILL_FIRE_RL_wci_wrkBusy_9 && - (!wci_respTimr_9_462_ULT_1_SL_wci_wTimeout_9_463_ETC___d5838 || - wci_wciResponse_9$wget[33:32] != 2'd0) || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_T_T ; - - // register wci_lastConfigAddr - assign wci_lastConfigAddr$D_IN = { 13'd4096, cpReq[23:4] } ; - assign wci_lastConfigAddr$EN = - WILL_FIRE_RL_cpDispatch_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_T_T_T ; - - // register wci_lastConfigAddr_1 - assign wci_lastConfigAddr_1$D_IN = wci_lastConfigAddr$D_IN ; - assign wci_lastConfigAddr_1$EN = - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_T_T_T ; - - // register wci_lastConfigAddr_10 - assign wci_lastConfigAddr_10$D_IN = wci_lastConfigAddr$D_IN ; - assign wci_lastConfigAddr_10$EN = - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_T_T ; - - // register wci_lastConfigAddr_11 - assign wci_lastConfigAddr_11$D_IN = wci_lastConfigAddr$D_IN ; - assign wci_lastConfigAddr_11$EN = - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_T_T ; - - // register wci_lastConfigAddr_12 - assign wci_lastConfigAddr_12$D_IN = wci_lastConfigAddr$D_IN ; - assign wci_lastConfigAddr_12$EN = - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T ; - - // register wci_lastConfigAddr_13 - assign wci_lastConfigAddr_13$D_IN = wci_lastConfigAddr$D_IN ; - assign wci_lastConfigAddr_13$EN = - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T ; - - // register wci_lastConfigAddr_14 - assign wci_lastConfigAddr_14$D_IN = wci_lastConfigAddr$D_IN ; - assign wci_lastConfigAddr_14$EN = - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T ; - - // register wci_lastConfigAddr_2 - assign wci_lastConfigAddr_2$D_IN = wci_lastConfigAddr$D_IN ; - assign wci_lastConfigAddr_2$EN = - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_T_T ; - - // register wci_lastConfigAddr_3 - assign wci_lastConfigAddr_3$D_IN = wci_lastConfigAddr$D_IN ; - assign wci_lastConfigAddr_3$EN = - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_T_T ; - - // register wci_lastConfigAddr_4 - assign wci_lastConfigAddr_4$D_IN = wci_lastConfigAddr$D_IN ; - assign wci_lastConfigAddr_4$EN = - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_T_T ; - - // register wci_lastConfigAddr_5 - assign wci_lastConfigAddr_5$D_IN = wci_lastConfigAddr$D_IN ; - assign wci_lastConfigAddr_5$EN = - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_T_T ; - - // register wci_lastConfigAddr_6 - assign wci_lastConfigAddr_6$D_IN = wci_lastConfigAddr$D_IN ; - assign wci_lastConfigAddr_6$EN = - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_T_T ; - - // register wci_lastConfigAddr_7 - assign wci_lastConfigAddr_7$D_IN = wci_lastConfigAddr$D_IN ; - assign wci_lastConfigAddr_7$EN = - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_T_T ; - - // register wci_lastConfigAddr_8 - assign wci_lastConfigAddr_8$D_IN = wci_lastConfigAddr$D_IN ; - assign wci_lastConfigAddr_8$EN = - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_T_T ; - - // register wci_lastConfigAddr_9 - assign wci_lastConfigAddr_9$D_IN = wci_lastConfigAddr$D_IN ; - assign wci_lastConfigAddr_9$EN = - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_T_T ; - - // register wci_lastConfigBE - assign wci_lastConfigBE$D_IN = { 1'd1, cpReq[3:0] } ; - assign wci_lastConfigBE$EN = - WILL_FIRE_RL_cpDispatch_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_T_T_T ; - - // register wci_lastConfigBE_1 - assign wci_lastConfigBE_1$D_IN = wci_lastConfigBE$D_IN ; - assign wci_lastConfigBE_1$EN = - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_T_T_T ; - - // register wci_lastConfigBE_10 - assign wci_lastConfigBE_10$D_IN = wci_lastConfigBE$D_IN ; - assign wci_lastConfigBE_10$EN = - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_T_T ; - - // register wci_lastConfigBE_11 - assign wci_lastConfigBE_11$D_IN = wci_lastConfigBE$D_IN ; - assign wci_lastConfigBE_11$EN = - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_T_T ; - - // register wci_lastConfigBE_12 - assign wci_lastConfigBE_12$D_IN = wci_lastConfigBE$D_IN ; - assign wci_lastConfigBE_12$EN = - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T ; - - // register wci_lastConfigBE_13 - assign wci_lastConfigBE_13$D_IN = wci_lastConfigBE$D_IN ; - assign wci_lastConfigBE_13$EN = - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T ; - - // register wci_lastConfigBE_14 - assign wci_lastConfigBE_14$D_IN = wci_lastConfigBE$D_IN ; - assign wci_lastConfigBE_14$EN = - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T ; - - // register wci_lastConfigBE_2 - assign wci_lastConfigBE_2$D_IN = wci_lastConfigBE$D_IN ; - assign wci_lastConfigBE_2$EN = - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_T_T ; - - // register wci_lastConfigBE_3 - assign wci_lastConfigBE_3$D_IN = wci_lastConfigBE$D_IN ; - assign wci_lastConfigBE_3$EN = - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_T_T ; - - // register wci_lastConfigBE_4 - assign wci_lastConfigBE_4$D_IN = wci_lastConfigBE$D_IN ; - assign wci_lastConfigBE_4$EN = - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_T_T ; - - // register wci_lastConfigBE_5 - assign wci_lastConfigBE_5$D_IN = wci_lastConfigBE$D_IN ; - assign wci_lastConfigBE_5$EN = - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_T_T ; - - // register wci_lastConfigBE_6 - assign wci_lastConfigBE_6$D_IN = wci_lastConfigBE$D_IN ; - assign wci_lastConfigBE_6$EN = - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_T_T ; - - // register wci_lastConfigBE_7 - assign wci_lastConfigBE_7$D_IN = wci_lastConfigBE$D_IN ; - assign wci_lastConfigBE_7$EN = - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_T_T ; - - // register wci_lastConfigBE_8 - assign wci_lastConfigBE_8$D_IN = wci_lastConfigBE$D_IN ; - assign wci_lastConfigBE_8$EN = - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_T_T ; - - // register wci_lastConfigBE_9 - assign wci_lastConfigBE_9$D_IN = wci_lastConfigBE$D_IN ; - assign wci_lastConfigBE_9$EN = - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_T_T ; - - // register wci_lastControlOp - assign wci_lastControlOp$D_IN = { 1'd1, cpReq[8:6] } ; - assign wci_lastControlOp$EN = WILL_FIRE_RL_cpDispatch_F_F_F_F_T_F_T_T ; - - // register wci_lastControlOp_1 - assign wci_lastControlOp_1$D_IN = wci_lastControlOp$D_IN ; - assign wci_lastControlOp_1$EN = WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_F_T_T ; - - // register wci_lastControlOp_10 - assign wci_lastControlOp_10$D_IN = wci_lastControlOp$D_IN ; - assign wci_lastControlOp_10$EN = - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T ; - - // register wci_lastControlOp_11 - assign wci_lastControlOp_11$D_IN = wci_lastControlOp$D_IN ; - assign wci_lastControlOp_11$EN = - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T ; - - // register wci_lastControlOp_12 - assign wci_lastControlOp_12$D_IN = wci_lastControlOp$D_IN ; - assign wci_lastControlOp_12$EN = - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T ; - - // register wci_lastControlOp_13 - assign wci_lastControlOp_13$D_IN = wci_lastControlOp$D_IN ; - assign wci_lastControlOp_13$EN = - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T ; - - // register wci_lastControlOp_14 - assign wci_lastControlOp_14$D_IN = wci_lastControlOp$D_IN ; - assign wci_lastControlOp_14$EN = - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T ; - - // register wci_lastControlOp_2 - assign wci_lastControlOp_2$D_IN = wci_lastControlOp$D_IN ; - assign wci_lastControlOp_2$EN = - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_F_T_T ; - - // register wci_lastControlOp_3 - assign wci_lastControlOp_3$D_IN = wci_lastControlOp$D_IN ; - assign wci_lastControlOp_3$EN = - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_F_T_T ; - - // register wci_lastControlOp_4 - assign wci_lastControlOp_4$D_IN = wci_lastControlOp$D_IN ; - assign wci_lastControlOp_4$EN = - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_T_T ; - - // register wci_lastControlOp_5 - assign wci_lastControlOp_5$D_IN = wci_lastControlOp$D_IN ; - assign wci_lastControlOp_5$EN = - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_T_T ; - - // register wci_lastControlOp_6 - assign wci_lastControlOp_6$D_IN = wci_lastControlOp$D_IN ; - assign wci_lastControlOp_6$EN = - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_F_T_T ; - - // register wci_lastControlOp_7 - assign wci_lastControlOp_7$D_IN = wci_lastControlOp$D_IN ; - assign wci_lastControlOp_7$EN = - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T ; - - // register wci_lastControlOp_8 - assign wci_lastControlOp_8$D_IN = wci_lastControlOp$D_IN ; - assign wci_lastControlOp_8$EN = - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T ; - - // register wci_lastControlOp_9 - assign wci_lastControlOp_9$D_IN = wci_lastControlOp$D_IN ; - assign wci_lastControlOp_9$EN = - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T ; - - // register wci_lastOpWrite - assign wci_lastOpWrite$D_IN = - WILL_FIRE_RL_cpDispatch_F_F_F_F_T_T_T ? 2'd2 : 2'd3 ; - assign wci_lastOpWrite$EN = - WILL_FIRE_RL_cpDispatch_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_T_T_T ; - - // register wci_lastOpWrite_1 - assign wci_lastOpWrite_1$D_IN = - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_T_T ? 2'd2 : 2'd3 ; - assign wci_lastOpWrite_1$EN = - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_T_T_T ; - - // register wci_lastOpWrite_10 - assign wci_lastOpWrite_10$D_IN = - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T ? - 2'd2 : - 2'd3 ; - assign wci_lastOpWrite_10$EN = - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_T_T ; - - // register wci_lastOpWrite_11 - assign wci_lastOpWrite_11$D_IN = - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T ? - 2'd2 : - 2'd3 ; - assign wci_lastOpWrite_11$EN = - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_T_T ; - - // register wci_lastOpWrite_12 - assign wci_lastOpWrite_12$D_IN = - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T ? - 2'd2 : - 2'd3 ; - assign wci_lastOpWrite_12$EN = - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T ; - - // register wci_lastOpWrite_13 - assign wci_lastOpWrite_13$D_IN = - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T ? - 2'd2 : - 2'd3 ; - assign wci_lastOpWrite_13$EN = - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T ; - - // register wci_lastOpWrite_14 - assign wci_lastOpWrite_14$D_IN = - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T ? - 2'd2 : - 2'd3 ; - assign wci_lastOpWrite_14$EN = - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T ; - - // register wci_lastOpWrite_2 - assign wci_lastOpWrite_2$D_IN = - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_T_T ? 2'd2 : 2'd3 ; - assign wci_lastOpWrite_2$EN = - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_T_T ; - - // register wci_lastOpWrite_3 - assign wci_lastOpWrite_3$D_IN = - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_T_T ? 2'd2 : 2'd3 ; - assign wci_lastOpWrite_3$EN = - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_T_T ; - - // register wci_lastOpWrite_4 - assign wci_lastOpWrite_4$D_IN = - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_T_T ? 2'd2 : 2'd3 ; - assign wci_lastOpWrite_4$EN = - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_T_T ; - - // register wci_lastOpWrite_5 - assign wci_lastOpWrite_5$D_IN = - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_T_T ? 2'd2 : 2'd3 ; - assign wci_lastOpWrite_5$EN = - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_T_T ; - - // register wci_lastOpWrite_6 - assign wci_lastOpWrite_6$D_IN = - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_T_T ? 2'd2 : 2'd3 ; - assign wci_lastOpWrite_6$EN = - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_T_T ; - - // register wci_lastOpWrite_7 - assign wci_lastOpWrite_7$D_IN = - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_T_T ? - 2'd2 : - 2'd3 ; - assign wci_lastOpWrite_7$EN = - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_T_T ; - - // register wci_lastOpWrite_8 - assign wci_lastOpWrite_8$D_IN = - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T ? - 2'd2 : - 2'd3 ; - assign wci_lastOpWrite_8$EN = - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_T_T ; - - // register wci_lastOpWrite_9 - assign wci_lastOpWrite_9$D_IN = - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T ? - 2'd2 : - 2'd3 ; - assign wci_lastOpWrite_9$EN = - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_T_T ; - - // register wci_mFlagReg - assign wci_mFlagReg$D_IN = 2'h0 ; - assign wci_mFlagReg$EN = 1'b0 ; - - // register wci_mFlagReg_1 - assign wci_mFlagReg_1$D_IN = 2'h0 ; - assign wci_mFlagReg_1$EN = 1'b0 ; - - // register wci_mFlagReg_10 - assign wci_mFlagReg_10$D_IN = 2'h0 ; - assign wci_mFlagReg_10$EN = 1'b0 ; - - // register wci_mFlagReg_11 - assign wci_mFlagReg_11$D_IN = 2'h0 ; - assign wci_mFlagReg_11$EN = 1'b0 ; - - // register wci_mFlagReg_12 - assign wci_mFlagReg_12$D_IN = 2'h0 ; - assign wci_mFlagReg_12$EN = 1'b0 ; - - // register wci_mFlagReg_13 - assign wci_mFlagReg_13$D_IN = 2'h0 ; - assign wci_mFlagReg_13$EN = 1'b0 ; - - // register wci_mFlagReg_14 - assign wci_mFlagReg_14$D_IN = 2'h0 ; - assign wci_mFlagReg_14$EN = 1'b0 ; - - // register wci_mFlagReg_2 - assign wci_mFlagReg_2$D_IN = 2'h0 ; - assign wci_mFlagReg_2$EN = 1'b0 ; - - // register wci_mFlagReg_3 - assign wci_mFlagReg_3$D_IN = 2'h0 ; - assign wci_mFlagReg_3$EN = 1'b0 ; - - // register wci_mFlagReg_4 - assign wci_mFlagReg_4$D_IN = 2'h0 ; - assign wci_mFlagReg_4$EN = 1'b0 ; - - // register wci_mFlagReg_5 - assign wci_mFlagReg_5$D_IN = 2'h0 ; - assign wci_mFlagReg_5$EN = 1'b0 ; - - // register wci_mFlagReg_6 - assign wci_mFlagReg_6$D_IN = 2'h0 ; - assign wci_mFlagReg_6$EN = 1'b0 ; - - // register wci_mFlagReg_7 - assign wci_mFlagReg_7$D_IN = 2'h0 ; - assign wci_mFlagReg_7$EN = 1'b0 ; - - // register wci_mFlagReg_8 - assign wci_mFlagReg_8$D_IN = 2'h0 ; - assign wci_mFlagReg_8$EN = 1'b0 ; - - // register wci_mFlagReg_9 - assign wci_mFlagReg_9$D_IN = 2'h0 ; - assign wci_mFlagReg_9$EN = 1'b0 ; - - // register wci_pageWindow - assign wci_pageWindow$D_IN = cpReq[39:28] ; - assign wci_pageWindow$EN = WILL_FIRE_RL_cpDispatch_F_F_T_T_F_F_F_T ; - - // register wci_pageWindow_1 - assign wci_pageWindow_1$D_IN = cpReq[39:28] ; - assign wci_pageWindow_1$EN = WILL_FIRE_RL_cpDispatch_F_F_T_F_T_F_F_F_T ; - - // register wci_pageWindow_10 - assign wci_pageWindow_10$D_IN = cpReq[39:28] ; - assign wci_pageWindow_10$EN = - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T ; - - // register wci_pageWindow_11 - assign wci_pageWindow_11$D_IN = cpReq[39:28] ; - assign wci_pageWindow_11$EN = - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T ; - - // register wci_pageWindow_12 - assign wci_pageWindow_12$D_IN = cpReq[39:28] ; - assign wci_pageWindow_12$EN = - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T ; - - // register wci_pageWindow_13 - assign wci_pageWindow_13$D_IN = cpReq[39:28] ; - assign wci_pageWindow_13$EN = - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T ; - - // register wci_pageWindow_14 - assign wci_pageWindow_14$D_IN = cpReq[39:28] ; - assign wci_pageWindow_14$EN = - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T ; - - // register wci_pageWindow_2 - assign wci_pageWindow_2$D_IN = cpReq[39:28] ; - assign wci_pageWindow_2$EN = WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_F_F_F_T ; - - // register wci_pageWindow_3 - assign wci_pageWindow_3$D_IN = cpReq[39:28] ; - assign wci_pageWindow_3$EN = WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_F_F_F_T ; - - // register wci_pageWindow_4 - assign wci_pageWindow_4$D_IN = cpReq[39:28] ; - assign wci_pageWindow_4$EN = - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_F_F_F_T ; - - // register wci_pageWindow_5 - assign wci_pageWindow_5$D_IN = cpReq[39:28] ; - assign wci_pageWindow_5$EN = - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_F_F_T ; - - // register wci_pageWindow_6 - assign wci_pageWindow_6$D_IN = cpReq[39:28] ; - assign wci_pageWindow_6$EN = - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_F_F_F_T ; - - // register wci_pageWindow_7 - assign wci_pageWindow_7$D_IN = cpReq[39:28] ; - assign wci_pageWindow_7$EN = - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_F_F_F_T ; - - // register wci_pageWindow_8 - assign wci_pageWindow_8$D_IN = cpReq[39:28] ; - assign wci_pageWindow_8$EN = - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_F_F_F_T ; - - // register wci_pageWindow_9 - assign wci_pageWindow_9$D_IN = cpReq[39:28] ; - assign wci_pageWindow_9$EN = - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_F_F_F_T ; - - // register wci_reqERR - assign wci_reqERR$D_IN = - MUX_wci_reqERR$write_1__SEL_1 ? - MUX_wci_reqERR$write_1__VAL_1 : - 3'd0 ; - assign wci_reqERR$EN = - WILL_FIRE_RL_wci_wrkBusy && - wci_wciResponse$wget[33:32] == 2'd3 && - (wci_reqPend == 2'd1 || wci_reqPend == 2'd2 || - wci_reqPend == 2'd3) || - WILL_FIRE_RL_cpDispatch_F_F_T_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_T_F_F_T_T_T ; - - // register wci_reqERR_1 - assign wci_reqERR_1$D_IN = - MUX_wci_reqERR_1$write_1__SEL_1 ? - MUX_wci_reqERR_1$write_1__VAL_1 : - 3'd0 ; - assign wci_reqERR_1$EN = - WILL_FIRE_RL_wci_wrkBusy_1 && - wci_wciResponse_1$wget[33:32] == 2'd3 && - (wci_reqPend_1 == 2'd1 || wci_reqPend_1 == 2'd2 || - wci_reqPend_1 == 2'd3) || - WILL_FIRE_RL_cpDispatch_F_F_T_F_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_T_F_F_T_T_T ; - - // register wci_reqERR_10 - assign wci_reqERR_10$D_IN = - MUX_wci_reqERR_10$write_1__SEL_1 ? - MUX_wci_reqERR_10$write_1__VAL_1 : - 3'd0 ; - assign wci_reqERR_10$EN = - WILL_FIRE_RL_wci_wrkBusy_10 && - wci_wciResponse_10$wget[33:32] == 2'd3 && - (wci_reqPend_10 == 2'd1 || wci_reqPend_10 == 2'd2 || - wci_reqPend_10 == 2'd3) || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_T ; - - // register wci_reqERR_11 - assign wci_reqERR_11$D_IN = - MUX_wci_reqERR_11$write_1__SEL_1 ? - MUX_wci_reqERR_11$write_1__VAL_1 : - 3'd0 ; - assign wci_reqERR_11$EN = - WILL_FIRE_RL_wci_wrkBusy_11 && - wci_wciResponse_11$wget[33:32] == 2'd3 && - (wci_reqPend_11 == 2'd1 || wci_reqPend_11 == 2'd2 || - wci_reqPend_11 == 2'd3) || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_T ; - - // register wci_reqERR_12 - assign wci_reqERR_12$D_IN = - MUX_wci_reqERR_12$write_1__SEL_1 ? - MUX_wci_reqERR_12$write_1__VAL_1 : - 3'd0 ; - assign wci_reqERR_12$EN = - WILL_FIRE_RL_wci_wrkBusy_12 && - wci_wciResponse_12$wget[33:32] == 2'd3 && - (wci_reqPend_12 == 2'd1 || wci_reqPend_12 == 2'd2 || - wci_reqPend_12 == 2'd3) || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_T ; - - // register wci_reqERR_13 - assign wci_reqERR_13$D_IN = - MUX_wci_reqERR_13$write_1__SEL_1 ? - MUX_wci_reqERR_13$write_1__VAL_1 : - 3'd0 ; - assign wci_reqERR_13$EN = - WILL_FIRE_RL_wci_wrkBusy_13 && - wci_wciResponse_13$wget[33:32] == 2'd3 && - (wci_reqPend_13 == 2'd1 || wci_reqPend_13 == 2'd2 || - wci_reqPend_13 == 2'd3) || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_T ; - - // register wci_reqERR_14 - assign wci_reqERR_14$D_IN = - MUX_wci_reqERR_14$write_1__SEL_1 ? - MUX_wci_reqERR_14$write_1__VAL_1 : - 3'd0 ; - assign wci_reqERR_14$EN = - WILL_FIRE_RL_wci_wrkBusy_14 && - wci_wciResponse_14$wget[33:32] == 2'd3 && - (wci_reqPend_14 == 2'd1 || wci_reqPend_14 == 2'd2 || - wci_reqPend_14 == 2'd3) || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_T ; - - // register wci_reqERR_2 - assign wci_reqERR_2$D_IN = - MUX_wci_reqERR_2$write_1__SEL_1 ? - MUX_wci_reqERR_2$write_1__VAL_1 : - 3'd0 ; - assign wci_reqERR_2$EN = - WILL_FIRE_RL_wci_wrkBusy_2 && - wci_wciResponse_2$wget[33:32] == 2'd3 && - (wci_reqPend_2 == 2'd1 || wci_reqPend_2 == 2'd2 || - wci_reqPend_2 == 2'd3) || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_F_F_T_T_T ; - - // register wci_reqERR_3 - assign wci_reqERR_3$D_IN = - MUX_wci_reqERR_3$write_1__SEL_1 ? - MUX_wci_reqERR_3$write_1__VAL_1 : - 3'd0 ; - assign wci_reqERR_3$EN = - WILL_FIRE_RL_wci_wrkBusy_3 && - wci_wciResponse_3$wget[33:32] == 2'd3 && - (wci_reqPend_3 == 2'd1 || wci_reqPend_3 == 2'd2 || - wci_reqPend_3 == 2'd3) || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_F_F_T_T_T ; - - // register wci_reqERR_4 - assign wci_reqERR_4$D_IN = - MUX_wci_reqERR_4$write_1__SEL_1 ? - MUX_wci_reqERR_4$write_1__VAL_1 : - 3'd0 ; - assign wci_reqERR_4$EN = - WILL_FIRE_RL_wci_wrkBusy_4 && - wci_wciResponse_4$wget[33:32] == 2'd3 && - (wci_reqPend_4 == 2'd1 || wci_reqPend_4 == 2'd2 || - wci_reqPend_4 == 2'd3) || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_F_F_T_T_T ; - - // register wci_reqERR_5 - assign wci_reqERR_5$D_IN = - MUX_wci_reqERR_5$write_1__SEL_1 ? - MUX_wci_reqERR_5$write_1__VAL_1 : - 3'd0 ; - assign wci_reqERR_5$EN = - WILL_FIRE_RL_wci_wrkBusy_5 && - wci_wciResponse_5$wget[33:32] == 2'd3 && - (wci_reqPend_5 == 2'd1 || wci_reqPend_5 == 2'd2 || - wci_reqPend_5 == 2'd3) || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_F_T_T_T ; - - // register wci_reqERR_6 - assign wci_reqERR_6$D_IN = - MUX_wci_reqERR_6$write_1__SEL_1 ? - MUX_wci_reqERR_6$write_1__VAL_1 : - 3'd0 ; - assign wci_reqERR_6$EN = - WILL_FIRE_RL_wci_wrkBusy_6 && - wci_wciResponse_6$wget[33:32] == 2'd3 && - (wci_reqPend_6 == 2'd1 || wci_reqPend_6 == 2'd2 || - wci_reqPend_6 == 2'd3) || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_F_F_T_T_T ; - - // register wci_reqERR_7 - assign wci_reqERR_7$D_IN = - MUX_wci_reqERR_7$write_1__SEL_1 ? - MUX_wci_reqERR_7$write_1__VAL_1 : - 3'd0 ; - assign wci_reqERR_7$EN = - WILL_FIRE_RL_wci_wrkBusy_7 && - wci_wciResponse_7$wget[33:32] == 2'd3 && - (wci_reqPend_7 == 2'd1 || wci_reqPend_7 == 2'd2 || - wci_reqPend_7 == 2'd3) || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_F_F_T_T_T ; - - // register wci_reqERR_8 - assign wci_reqERR_8$D_IN = - MUX_wci_reqERR_8$write_1__SEL_1 ? - MUX_wci_reqERR_8$write_1__VAL_1 : - 3'd0 ; - assign wci_reqERR_8$EN = - WILL_FIRE_RL_wci_wrkBusy_8 && - wci_wciResponse_8$wget[33:32] == 2'd3 && - (wci_reqPend_8 == 2'd1 || wci_reqPend_8 == 2'd2 || - wci_reqPend_8 == 2'd3) || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_F_F_T_T_T ; - - // register wci_reqERR_9 - assign wci_reqERR_9$D_IN = - MUX_wci_reqERR_9$write_1__SEL_1 ? - MUX_wci_reqERR_9$write_1__VAL_1 : - 3'd0 ; - assign wci_reqERR_9$EN = - WILL_FIRE_RL_wci_wrkBusy_9 && - wci_wciResponse_9$wget[33:32] == 2'd3 && - (wci_reqPend_9 == 2'd1 || wci_reqPend_9 == 2'd2 || - wci_reqPend_9 == 2'd3) || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_F_F_T_T_T ; - - // register wci_reqFAIL - assign wci_reqFAIL$D_IN = - MUX_wci_reqFAIL$write_1__SEL_1 ? - MUX_wci_reqFAIL$write_1__VAL_1 : - 3'd0 ; - assign wci_reqFAIL$EN = - WILL_FIRE_RL_wci_wrkBusy && - wci_wciResponse$wget[33:32] == 2'd2 && - (wci_reqPend == 2'd1 || wci_reqPend == 2'd2 || - wci_reqPend == 2'd3) || - WILL_FIRE_RL_cpDispatch_F_F_T_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_T_F_F_T_T_T ; - - // register wci_reqFAIL_1 - assign wci_reqFAIL_1$D_IN = - MUX_wci_reqFAIL_1$write_1__SEL_1 ? - MUX_wci_reqFAIL_1$write_1__VAL_1 : - 3'd0 ; - assign wci_reqFAIL_1$EN = - WILL_FIRE_RL_wci_wrkBusy_1 && - wci_wciResponse_1$wget[33:32] == 2'd2 && - (wci_reqPend_1 == 2'd1 || wci_reqPend_1 == 2'd2 || - wci_reqPend_1 == 2'd3) || - WILL_FIRE_RL_cpDispatch_F_F_T_F_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_T_F_F_T_T_T ; - - // register wci_reqFAIL_10 - assign wci_reqFAIL_10$D_IN = - MUX_wci_reqFAIL_10$write_1__SEL_1 ? - MUX_wci_reqFAIL_10$write_1__VAL_1 : + // register wci_0_busy + assign wci_0_busy$D_IN = !MUX_wci_0_busy$write_1__SEL_1 ; + assign wci_0_busy$EN = + WILL_FIRE_RL_wci_0_wrkBusy && + (!wci_0_respTimr_28_ULT_1_SL_wci_0_wTimeout_29_30___d231 || + wci_0_wciResponse$wget[33:32] != 2'd0) || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E0_T_T ; + + // register wci_0_lastConfigAddr + assign wci_0_lastConfigAddr$D_IN = { 13'd4096, cpReq[23:4] } ; + assign wci_0_lastConfigAddr$EN = + WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E0_T_T ; + + // register wci_0_lastConfigBE + assign wci_0_lastConfigBE$D_IN = { 1'd1, cpReq[3:0] } ; + assign wci_0_lastConfigBE$EN = + WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E0_T_T ; + + // register wci_0_lastControlOp + assign wci_0_lastControlOp$D_IN = { 1'd1, cpReq[8:6] } ; + assign wci_0_lastControlOp$EN = WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_T_T ; + + // register wci_0_lastOpWrite + assign wci_0_lastOpWrite$D_IN = + WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_T_T ? 2'd2 : 2'd3 ; + assign wci_0_lastOpWrite$EN = + WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E0_T_T ; + + // register wci_0_mFlagReg + assign wci_0_mFlagReg$D_IN = 2'h0 ; + assign wci_0_mFlagReg$EN = 1'b0 ; + + // register wci_0_pageWindow + assign wci_0_pageWindow$D_IN = cpReq[39:28] ; + assign wci_0_pageWindow$EN = WILL_FIRE_RL_cpDispatch_F_F_T_E0_F_F_F_T ; + + // register wci_0_reqERR + assign wci_0_reqERR$D_IN = + MUX_wci_0_reqERR$write_1__SEL_1 ? + MUX_wci_0_reqERR$write_1__VAL_1 : 3'd0 ; - assign wci_reqFAIL_10$EN = - WILL_FIRE_RL_wci_wrkBusy_10 && - wci_wciResponse_10$wget[33:32] == 2'd2 && - (wci_reqPend_10 == 2'd1 || wci_reqPend_10 == 2'd2 || - wci_reqPend_10 == 2'd3) || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_T ; - - // register wci_reqFAIL_11 - assign wci_reqFAIL_11$D_IN = - MUX_wci_reqFAIL_11$write_1__SEL_1 ? - MUX_wci_reqFAIL_11$write_1__VAL_1 : + assign wci_0_reqERR$EN = + WILL_FIRE_RL_wci_0_wrkBusy && + wci_0_wciResponse$wget[33:32] == 2'd3 && + (wci_0_reqPend == 2'd1 || wci_0_reqPend == 2'd2 || + wci_0_reqPend == 2'd3) || + WILL_FIRE_RL_cpDispatch_F_F_T_E0_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E0_F_F_T_T_T ; + + // register wci_0_reqFAIL + assign wci_0_reqFAIL$D_IN = + MUX_wci_0_reqFAIL$write_1__SEL_1 ? + MUX_wci_0_reqFAIL$write_1__VAL_1 : 3'd0 ; - assign wci_reqFAIL_11$EN = - WILL_FIRE_RL_wci_wrkBusy_11 && - wci_wciResponse_11$wget[33:32] == 2'd2 && - (wci_reqPend_11 == 2'd1 || wci_reqPend_11 == 2'd2 || - wci_reqPend_11 == 2'd3) || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_T ; - - // register wci_reqFAIL_12 - assign wci_reqFAIL_12$D_IN = - MUX_wci_reqFAIL_12$write_1__SEL_1 ? - MUX_wci_reqFAIL_12$write_1__VAL_1 : - 3'd0 ; - assign wci_reqFAIL_12$EN = - WILL_FIRE_RL_wci_wrkBusy_12 && - wci_wciResponse_12$wget[33:32] == 2'd2 && - (wci_reqPend_12 == 2'd1 || wci_reqPend_12 == 2'd2 || - wci_reqPend_12 == 2'd3) || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_T ; - - // register wci_reqFAIL_13 - assign wci_reqFAIL_13$D_IN = - MUX_wci_reqFAIL_13$write_1__SEL_1 ? - MUX_wci_reqFAIL_13$write_1__VAL_1 : - 3'd0 ; - assign wci_reqFAIL_13$EN = - WILL_FIRE_RL_wci_wrkBusy_13 && - wci_wciResponse_13$wget[33:32] == 2'd2 && - (wci_reqPend_13 == 2'd1 || wci_reqPend_13 == 2'd2 || - wci_reqPend_13 == 2'd3) || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_T ; - - // register wci_reqFAIL_14 - assign wci_reqFAIL_14$D_IN = - MUX_wci_reqFAIL_14$write_1__SEL_1 ? - MUX_wci_reqFAIL_14$write_1__VAL_1 : - 3'd0 ; - assign wci_reqFAIL_14$EN = - WILL_FIRE_RL_wci_wrkBusy_14 && - wci_wciResponse_14$wget[33:32] == 2'd2 && - (wci_reqPend_14 == 2'd1 || wci_reqPend_14 == 2'd2 || - wci_reqPend_14 == 2'd3) || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_T ; - - // register wci_reqFAIL_2 - assign wci_reqFAIL_2$D_IN = - MUX_wci_reqFAIL_2$write_1__SEL_1 ? - MUX_wci_reqFAIL_2$write_1__VAL_1 : - 3'd0 ; - assign wci_reqFAIL_2$EN = - WILL_FIRE_RL_wci_wrkBusy_2 && - wci_wciResponse_2$wget[33:32] == 2'd2 && - (wci_reqPend_2 == 2'd1 || wci_reqPend_2 == 2'd2 || - wci_reqPend_2 == 2'd3) || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_F_F_T_T_T ; - - // register wci_reqFAIL_3 - assign wci_reqFAIL_3$D_IN = - MUX_wci_reqFAIL_3$write_1__SEL_1 ? - MUX_wci_reqFAIL_3$write_1__VAL_1 : - 3'd0 ; - assign wci_reqFAIL_3$EN = - WILL_FIRE_RL_wci_wrkBusy_3 && - wci_wciResponse_3$wget[33:32] == 2'd2 && - (wci_reqPend_3 == 2'd1 || wci_reqPend_3 == 2'd2 || - wci_reqPend_3 == 2'd3) || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_F_F_T_T_T ; - - // register wci_reqFAIL_4 - assign wci_reqFAIL_4$D_IN = - MUX_wci_reqFAIL_4$write_1__SEL_1 ? - MUX_wci_reqFAIL_4$write_1__VAL_1 : - 3'd0 ; - assign wci_reqFAIL_4$EN = - WILL_FIRE_RL_wci_wrkBusy_4 && - wci_wciResponse_4$wget[33:32] == 2'd2 && - (wci_reqPend_4 == 2'd1 || wci_reqPend_4 == 2'd2 || - wci_reqPend_4 == 2'd3) || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_F_F_T_T_T ; - - // register wci_reqFAIL_5 - assign wci_reqFAIL_5$D_IN = - MUX_wci_reqFAIL_5$write_1__SEL_1 ? - MUX_wci_reqFAIL_5$write_1__VAL_1 : - 3'd0 ; - assign wci_reqFAIL_5$EN = - WILL_FIRE_RL_wci_wrkBusy_5 && - wci_wciResponse_5$wget[33:32] == 2'd2 && - (wci_reqPend_5 == 2'd1 || wci_reqPend_5 == 2'd2 || - wci_reqPend_5 == 2'd3) || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_F_T_T_T ; - - // register wci_reqFAIL_6 - assign wci_reqFAIL_6$D_IN = - MUX_wci_reqFAIL_6$write_1__SEL_1 ? - MUX_wci_reqFAIL_6$write_1__VAL_1 : - 3'd0 ; - assign wci_reqFAIL_6$EN = - WILL_FIRE_RL_wci_wrkBusy_6 && - wci_wciResponse_6$wget[33:32] == 2'd2 && - (wci_reqPend_6 == 2'd1 || wci_reqPend_6 == 2'd2 || - wci_reqPend_6 == 2'd3) || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_F_F_T_T_T ; - - // register wci_reqFAIL_7 - assign wci_reqFAIL_7$D_IN = - MUX_wci_reqFAIL_7$write_1__SEL_1 ? - MUX_wci_reqFAIL_7$write_1__VAL_1 : - 3'd0 ; - assign wci_reqFAIL_7$EN = - WILL_FIRE_RL_wci_wrkBusy_7 && - wci_wciResponse_7$wget[33:32] == 2'd2 && - (wci_reqPend_7 == 2'd1 || wci_reqPend_7 == 2'd2 || - wci_reqPend_7 == 2'd3) || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_F_F_T_T_T ; - - // register wci_reqFAIL_8 - assign wci_reqFAIL_8$D_IN = - MUX_wci_reqFAIL_8$write_1__SEL_1 ? - MUX_wci_reqFAIL_8$write_1__VAL_1 : - 3'd0 ; - assign wci_reqFAIL_8$EN = - WILL_FIRE_RL_wci_wrkBusy_8 && - wci_wciResponse_8$wget[33:32] == 2'd2 && - (wci_reqPend_8 == 2'd1 || wci_reqPend_8 == 2'd2 || - wci_reqPend_8 == 2'd3) || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_F_F_T_T_T ; - - // register wci_reqFAIL_9 - assign wci_reqFAIL_9$D_IN = - MUX_wci_reqFAIL_9$write_1__SEL_1 ? - MUX_wci_reqFAIL_9$write_1__VAL_1 : - 3'd0 ; - assign wci_reqFAIL_9$EN = - WILL_FIRE_RL_wci_wrkBusy_9 && - wci_wciResponse_9$wget[33:32] == 2'd2 && - (wci_reqPend_9 == 2'd1 || wci_reqPend_9 == 2'd2 || - wci_reqPend_9 == 2'd3) || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_F_F_T_T_T ; - - // register wci_reqF_10_c_r - assign wci_reqF_10_c_r$D_IN = - WILL_FIRE_RL_wci_reqF_10_incCtr ? - MUX_wci_reqF_10_c_r$write_1__VAL_1 : - MUX_wci_reqF_10_c_r$write_1__VAL_2 ; - assign wci_reqF_10_c_r$EN = - WILL_FIRE_RL_wci_reqF_10_incCtr || - WILL_FIRE_RL_wci_reqF_10_decCtr ; - - // register wci_reqF_10_q_0 - always@(MUX_wci_reqF_10_q_0$write_1__SEL_1 or - MUX_wci_reqF_10_q_0$write_1__VAL_1 or - WILL_FIRE_RL_wci_reqF_10_both or - MUX_wci_reqF_10_q_0$write_1__VAL_2 or - WILL_FIRE_RL_wci_reqF_10_decCtr) + assign wci_0_reqFAIL$EN = + WILL_FIRE_RL_wci_0_wrkBusy && + wci_0_wciResponse$wget[33:32] == 2'd2 && + (wci_0_reqPend == 2'd1 || wci_0_reqPend == 2'd2 || + wci_0_reqPend == 2'd3) || + WILL_FIRE_RL_cpDispatch_F_F_T_E0_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E0_F_F_T_T_T ; + + // register wci_0_reqF_cntr_r + assign wci_0_reqF_cntr_r$D_IN = + WILL_FIRE_RL_wci_0_reqF_incCtr ? + MUX_wci_0_reqF_cntr_r$write_1__VAL_1 : + MUX_wci_0_reqF_cntr_r$write_1__VAL_2 ; + assign wci_0_reqF_cntr_r$EN = + WILL_FIRE_RL_wci_0_reqF_incCtr || + WILL_FIRE_RL_wci_0_reqF_decCtr ; + + // register wci_0_reqF_q_0 + always@(WILL_FIRE_RL_wci_0_reqF_both or + MUX_wci_0_reqF_q_0$write_1__VAL_1 or + MUX_wci_0_reqF_q_0$write_1__SEL_2 or + MUX_wci_0_reqF_q_0$write_1__VAL_2 or WILL_FIRE_RL_wci_0_reqF_decCtr) begin case (1'b1) // synopsys parallel_case - MUX_wci_reqF_10_q_0$write_1__SEL_1: - wci_reqF_10_q_0$D_IN = MUX_wci_reqF_10_q_0$write_1__VAL_1; - WILL_FIRE_RL_wci_reqF_10_both: - wci_reqF_10_q_0$D_IN = MUX_wci_reqF_10_q_0$write_1__VAL_2; - WILL_FIRE_RL_wci_reqF_10_decCtr: - wci_reqF_10_q_0$D_IN = 72'h0000000000AAAAAAAA; - default: wci_reqF_10_q_0$D_IN = + WILL_FIRE_RL_wci_0_reqF_both: + wci_0_reqF_q_0$D_IN = MUX_wci_0_reqF_q_0$write_1__VAL_1; + MUX_wci_0_reqF_q_0$write_1__SEL_2: + wci_0_reqF_q_0$D_IN = MUX_wci_0_reqF_q_0$write_1__VAL_2; + WILL_FIRE_RL_wci_0_reqF_decCtr: + wci_0_reqF_q_0$D_IN = 72'h0000000000AAAAAAAA; + default: wci_0_reqF_q_0$D_IN = 72'hAAAAAAAAAAAAAAAAAA /* unspecified value */ ; endcase end - assign wci_reqF_10_q_0$EN = - WILL_FIRE_RL_wci_reqF_10_incCtr && !wci_reqF_10_c_r || - WILL_FIRE_RL_wci_reqF_10_both || - WILL_FIRE_RL_wci_reqF_10_decCtr ; - - // register wci_reqF_11_c_r - assign wci_reqF_11_c_r$D_IN = - WILL_FIRE_RL_wci_reqF_11_incCtr ? - MUX_wci_reqF_11_c_r$write_1__VAL_1 : - MUX_wci_reqF_11_c_r$write_1__VAL_2 ; - assign wci_reqF_11_c_r$EN = - WILL_FIRE_RL_wci_reqF_11_incCtr || - WILL_FIRE_RL_wci_reqF_11_decCtr ; - - // register wci_reqF_11_q_0 - always@(MUX_wci_reqF_11_q_0$write_1__SEL_1 or - MUX_wci_reqF_11_q_0$write_1__VAL_1 or - WILL_FIRE_RL_wci_reqF_11_both or - MUX_wci_reqF_11_q_0$write_1__VAL_2 or - WILL_FIRE_RL_wci_reqF_11_decCtr) + assign wci_0_reqF_q_0$EN = + WILL_FIRE_RL_wci_0_reqF_both || + WILL_FIRE_RL_wci_0_reqF_incCtr && !wci_0_reqF_cntr_r || + WILL_FIRE_RL_wci_0_reqF_decCtr ; + + // register wci_0_reqPend + always@(MUX_wci_0_reqPend$write_1__SEL_1 or + WILL_FIRE_RL_cpDispatch_F_F_T_E0_T_T or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_T_T or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_T_T) begin case (1'b1) // synopsys parallel_case - MUX_wci_reqF_11_q_0$write_1__SEL_1: - wci_reqF_11_q_0$D_IN = MUX_wci_reqF_11_q_0$write_1__VAL_1; - WILL_FIRE_RL_wci_reqF_11_both: - wci_reqF_11_q_0$D_IN = MUX_wci_reqF_11_q_0$write_1__VAL_2; - WILL_FIRE_RL_wci_reqF_11_decCtr: - wci_reqF_11_q_0$D_IN = 72'h0000000000AAAAAAAA; - default: wci_reqF_11_q_0$D_IN = - 72'hAAAAAAAAAAAAAAAAAA /* unspecified value */ ; + MUX_wci_0_reqPend$write_1__SEL_1: wci_0_reqPend$D_IN = 2'd0; + WILL_FIRE_RL_cpDispatch_F_F_T_E0_T_T: wci_0_reqPend$D_IN = 2'd1; + WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_T_T: wci_0_reqPend$D_IN = 2'd2; + WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_T_T: wci_0_reqPend$D_IN = 2'd3; + default: wci_0_reqPend$D_IN = 2'b10 /* unspecified value */ ; endcase end - assign wci_reqF_11_q_0$EN = - WILL_FIRE_RL_wci_reqF_11_incCtr && !wci_reqF_11_c_r || - WILL_FIRE_RL_wci_reqF_11_both || - WILL_FIRE_RL_wci_reqF_11_decCtr ; - - // register wci_reqF_12_c_r - assign wci_reqF_12_c_r$D_IN = - WILL_FIRE_RL_wci_reqF_12_incCtr ? - MUX_wci_reqF_12_c_r$write_1__VAL_1 : - MUX_wci_reqF_12_c_r$write_1__VAL_2 ; - assign wci_reqF_12_c_r$EN = - WILL_FIRE_RL_wci_reqF_12_incCtr || - WILL_FIRE_RL_wci_reqF_12_decCtr ; - - // register wci_reqF_12_q_0 - always@(MUX_wci_reqF_12_q_0$write_1__SEL_1 or - MUX_wci_reqF_12_q_0$write_1__VAL_1 or - WILL_FIRE_RL_wci_reqF_12_both or - MUX_wci_reqF_12_q_0$write_1__VAL_2 or - WILL_FIRE_RL_wci_reqF_12_decCtr) + assign wci_0_reqPend$EN = + WILL_FIRE_RL_wci_0_wrkBusy && + wci_0_wciResponse$wget[33:32] != 2'd0 || + WILL_FIRE_RL_cpDispatch_F_F_T_E0_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_T_T ; + + // register wci_0_reqTO + assign wci_0_reqTO$D_IN = + MUX_wci_0_reqTO$write_1__SEL_1 ? + MUX_wci_0_reqTO$write_1__VAL_1 : + 3'd0 ; + assign wci_0_reqTO$EN = + WILL_FIRE_RL_wci_0_wrkBusy && + wci_0_wciResponse_wget__23_BITS_33_TO_32_24_EQ_ETC___d252 || + WILL_FIRE_RL_cpDispatch_F_F_T_E0_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E0_F_F_T_T_T ; + + // register wci_0_respTimr + assign wci_0_respTimr$D_IN = + wci_0_reqF_cntr_r ? 32'd0 : MUX_wci_0_respTimr$write_1__VAL_2 ; + assign wci_0_respTimr$EN = WILL_FIRE_RL_wci_0_wrkBusy || wci_0_reqF_cntr_r ; + + // register wci_0_respTimrAct + assign wci_0_respTimrAct$D_IN = wci_0_reqF_cntr_r ; + assign wci_0_respTimrAct$EN = + WILL_FIRE_RL_wci_0_wrkBusy && + (!wci_0_respTimr_28_ULT_1_SL_wci_0_wTimeout_29_30___d231 || + wci_0_wciResponse$wget[33:32] != 2'd0) || + wci_0_reqF_cntr_r ; + + // register wci_0_sThreadBusy_d + assign wci_0_sThreadBusy_d$D_IN = wci_Vm_0_SThreadBusy ; + assign wci_0_sThreadBusy_d$EN = 1'd1 ; + + // register wci_0_sfCap + assign wci_0_sfCap$D_IN = wci_0_sfCapSet ; + assign wci_0_sfCap$EN = wci_0_sfCapSet || wci_0_sfCapClear ; + + // register wci_0_sfCapClear + assign wci_0_sfCapClear$D_IN = wci_0_sfCapClear_1$whas ; + assign wci_0_sfCapClear$EN = 1'd1 ; + + // register wci_0_sfCapSet + assign wci_0_sfCapSet$D_IN = wci_Vm_0_SFlag[0] ; + assign wci_0_sfCapSet$EN = 1'd1 ; + + // register wci_0_slvPresent + assign wci_0_slvPresent$D_IN = wci_Vm_0_SFlag[1] ; + assign wci_0_slvPresent$EN = 1'd1 ; + + // register wci_0_wReset_n + assign wci_0_wReset_n$D_IN = cpReq[59] ; + assign wci_0_wReset_n$EN = + WILL_FIRE_RL_cpDispatch_F_F_T_E0_F_F_T_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E0_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E0_F_F_T_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E0_F_F_T_T_T ; + + // register wci_0_wStatus + assign wci_0_wStatus$D_IN = + { 4'b0, + !wci_0_lastOpWrite[1] || wci_0_lastOpWrite[0], + IF_wci_0_lastControlOp_13_BIT_3_14_THEN_wci_0__ETC___d328 } ; + assign wci_0_wStatus$EN = 1'd1 ; + + // register wci_0_wTimeout + assign wci_0_wTimeout$D_IN = cpReq[32:28] ; + assign wci_0_wTimeout$EN = + WILL_FIRE_RL_cpDispatch_F_F_T_E0_F_F_T_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E0_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E0_F_F_T_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E0_F_F_T_T_T ; + + // register wci_10_busy + assign wci_10_busy$D_IN = !MUX_wci_10_busy$write_1__SEL_1 ; + assign wci_10_busy$EN = + WILL_FIRE_RL_wci_10_wrkBusy && + (!wci_10_respTimr_628_ULT_1_SL_wci_10_wTimeout_6_ETC___d1631 || + wci_10_wciResponse$wget[33:32] != 2'd0) || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_F_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E10_T_T ; + + // register wci_10_lastConfigAddr + assign wci_10_lastConfigAddr$D_IN = wci_0_lastConfigAddr$D_IN ; + assign wci_10_lastConfigAddr$EN = + WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E10_T_T ; + + // register wci_10_lastConfigBE + assign wci_10_lastConfigBE$D_IN = wci_0_lastConfigBE$D_IN ; + assign wci_10_lastConfigBE$EN = + WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E10_T_T ; + + // register wci_10_lastControlOp + assign wci_10_lastControlOp$D_IN = wci_0_lastControlOp$D_IN ; + assign wci_10_lastControlOp$EN = WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_F_T_T ; + + // register wci_10_lastOpWrite + assign wci_10_lastOpWrite$D_IN = + WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_T_T ? 2'd2 : 2'd3 ; + assign wci_10_lastOpWrite$EN = + WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E10_T_T ; + + // register wci_10_mFlagReg + assign wci_10_mFlagReg$D_IN = 2'h0 ; + assign wci_10_mFlagReg$EN = 1'b0 ; + + // register wci_10_pageWindow + assign wci_10_pageWindow$D_IN = cpReq[39:28] ; + assign wci_10_pageWindow$EN = WILL_FIRE_RL_cpDispatch_F_F_T_E10_F_F_F_T ; + + // register wci_10_reqERR + assign wci_10_reqERR$D_IN = + MUX_wci_10_reqERR$write_1__SEL_1 ? + MUX_wci_10_reqERR$write_1__VAL_1 : + 3'd0 ; + assign wci_10_reqERR$EN = + WILL_FIRE_RL_wci_10_wrkBusy && + wci_10_wciResponse$wget[33:32] == 2'd3 && + (wci_10_reqPend == 2'd1 || wci_10_reqPend == 2'd2 || + wci_10_reqPend == 2'd3) || + WILL_FIRE_RL_cpDispatch_F_F_T_E10_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E10_F_F_T_T_T ; + + // register wci_10_reqFAIL + assign wci_10_reqFAIL$D_IN = + MUX_wci_10_reqFAIL$write_1__SEL_1 ? + MUX_wci_10_reqFAIL$write_1__VAL_1 : + 3'd0 ; + assign wci_10_reqFAIL$EN = + WILL_FIRE_RL_wci_10_wrkBusy && + wci_10_wciResponse$wget[33:32] == 2'd2 && + (wci_10_reqPend == 2'd1 || wci_10_reqPend == 2'd2 || + wci_10_reqPend == 2'd3) || + WILL_FIRE_RL_cpDispatch_F_F_T_E10_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E10_F_F_T_T_T ; + + // register wci_10_reqF_cntr_r + assign wci_10_reqF_cntr_r$D_IN = + WILL_FIRE_RL_wci_10_reqF_incCtr ? + MUX_wci_10_reqF_cntr_r$write_1__VAL_1 : + MUX_wci_10_reqF_cntr_r$write_1__VAL_2 ; + assign wci_10_reqF_cntr_r$EN = + WILL_FIRE_RL_wci_10_reqF_incCtr || + WILL_FIRE_RL_wci_10_reqF_decCtr ; + + // register wci_10_reqF_q_0 + always@(MUX_wci_10_reqF_q_0$write_1__SEL_1 or + MUX_wci_10_reqF_q_0$write_1__VAL_1 or + WILL_FIRE_RL_wci_10_reqF_both or + MUX_wci_10_reqF_q_0$write_1__VAL_2 or + WILL_FIRE_RL_wci_10_reqF_decCtr) begin case (1'b1) // synopsys parallel_case - MUX_wci_reqF_12_q_0$write_1__SEL_1: - wci_reqF_12_q_0$D_IN = MUX_wci_reqF_12_q_0$write_1__VAL_1; - WILL_FIRE_RL_wci_reqF_12_both: - wci_reqF_12_q_0$D_IN = MUX_wci_reqF_12_q_0$write_1__VAL_2; - WILL_FIRE_RL_wci_reqF_12_decCtr: - wci_reqF_12_q_0$D_IN = 72'h0000000000AAAAAAAA; - default: wci_reqF_12_q_0$D_IN = + MUX_wci_10_reqF_q_0$write_1__SEL_1: + wci_10_reqF_q_0$D_IN = MUX_wci_10_reqF_q_0$write_1__VAL_1; + WILL_FIRE_RL_wci_10_reqF_both: + wci_10_reqF_q_0$D_IN = MUX_wci_10_reqF_q_0$write_1__VAL_2; + WILL_FIRE_RL_wci_10_reqF_decCtr: + wci_10_reqF_q_0$D_IN = 72'h0000000000AAAAAAAA; + default: wci_10_reqF_q_0$D_IN = 72'hAAAAAAAAAAAAAAAAAA /* unspecified value */ ; endcase end - assign wci_reqF_12_q_0$EN = - WILL_FIRE_RL_wci_reqF_12_incCtr && !wci_reqF_12_c_r || - WILL_FIRE_RL_wci_reqF_12_both || - WILL_FIRE_RL_wci_reqF_12_decCtr ; - - // register wci_reqF_13_c_r - assign wci_reqF_13_c_r$D_IN = - WILL_FIRE_RL_wci_reqF_13_incCtr ? - MUX_wci_reqF_13_c_r$write_1__VAL_1 : - MUX_wci_reqF_13_c_r$write_1__VAL_2 ; - assign wci_reqF_13_c_r$EN = - WILL_FIRE_RL_wci_reqF_13_incCtr || - WILL_FIRE_RL_wci_reqF_13_decCtr ; - - // register wci_reqF_13_q_0 - always@(MUX_wci_reqF_13_q_0$write_1__SEL_1 or - MUX_wci_reqF_13_q_0$write_1__VAL_1 or - WILL_FIRE_RL_wci_reqF_13_both or - MUX_wci_reqF_13_q_0$write_1__VAL_2 or - WILL_FIRE_RL_wci_reqF_13_decCtr) + assign wci_10_reqF_q_0$EN = + WILL_FIRE_RL_wci_10_reqF_incCtr && !wci_10_reqF_cntr_r || + WILL_FIRE_RL_wci_10_reqF_both || + WILL_FIRE_RL_wci_10_reqF_decCtr ; + + // register wci_10_reqPend + always@(MUX_wci_10_reqPend$write_1__SEL_1 or + WILL_FIRE_RL_cpDispatch_F_F_T_E10_T_T or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_T_T or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_F_T_T) begin case (1'b1) // synopsys parallel_case - MUX_wci_reqF_13_q_0$write_1__SEL_1: - wci_reqF_13_q_0$D_IN = MUX_wci_reqF_13_q_0$write_1__VAL_1; - WILL_FIRE_RL_wci_reqF_13_both: - wci_reqF_13_q_0$D_IN = MUX_wci_reqF_13_q_0$write_1__VAL_2; - WILL_FIRE_RL_wci_reqF_13_decCtr: - wci_reqF_13_q_0$D_IN = 72'h0000000000AAAAAAAA; - default: wci_reqF_13_q_0$D_IN = - 72'hAAAAAAAAAAAAAAAAAA /* unspecified value */ ; + MUX_wci_10_reqPend$write_1__SEL_1: wci_10_reqPend$D_IN = 2'd0; + WILL_FIRE_RL_cpDispatch_F_F_T_E10_T_T: wci_10_reqPend$D_IN = 2'd1; + WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_T_T: wci_10_reqPend$D_IN = 2'd2; + WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_F_T_T: wci_10_reqPend$D_IN = 2'd3; + default: wci_10_reqPend$D_IN = 2'b10 /* unspecified value */ ; endcase end - assign wci_reqF_13_q_0$EN = - WILL_FIRE_RL_wci_reqF_13_incCtr && !wci_reqF_13_c_r || - WILL_FIRE_RL_wci_reqF_13_both || - WILL_FIRE_RL_wci_reqF_13_decCtr ; - - // register wci_reqF_14_c_r - assign wci_reqF_14_c_r$D_IN = - WILL_FIRE_RL_wci_reqF_14_incCtr ? - MUX_wci_reqF_14_c_r$write_1__VAL_1 : - MUX_wci_reqF_14_c_r$write_1__VAL_2 ; - assign wci_reqF_14_c_r$EN = - WILL_FIRE_RL_wci_reqF_14_incCtr || - WILL_FIRE_RL_wci_reqF_14_decCtr ; - - // register wci_reqF_14_q_0 - always@(MUX_wci_reqF_14_q_0$write_1__SEL_1 or - MUX_wci_reqF_14_q_0$write_1__VAL_1 or - WILL_FIRE_RL_wci_reqF_14_both or - MUX_wci_reqF_14_q_0$write_1__VAL_2 or - WILL_FIRE_RL_wci_reqF_14_decCtr) + assign wci_10_reqPend$EN = + WILL_FIRE_RL_wci_10_wrkBusy && + wci_10_wciResponse$wget[33:32] != 2'd0 || + WILL_FIRE_RL_cpDispatch_F_F_T_E10_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_F_T_T ; + + // register wci_10_reqTO + assign wci_10_reqTO$D_IN = + MUX_wci_10_reqTO$write_1__SEL_1 ? + MUX_wci_10_reqTO$write_1__VAL_1 : + 3'd0 ; + assign wci_10_reqTO$EN = + WILL_FIRE_RL_wci_10_wrkBusy && + wci_10_wciResponse_wget__623_BITS_33_TO_32_624_ETC___d1652 || + WILL_FIRE_RL_cpDispatch_F_F_T_E10_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E10_F_F_T_T_T ; + + // register wci_10_respTimr + assign wci_10_respTimr$D_IN = + wci_10_reqF_cntr_r ? 32'd0 : MUX_wci_10_respTimr$write_1__VAL_2 ; + assign wci_10_respTimr$EN = + WILL_FIRE_RL_wci_10_wrkBusy || wci_10_reqF_cntr_r ; + + // register wci_10_respTimrAct + assign wci_10_respTimrAct$D_IN = wci_10_reqF_cntr_r ; + assign wci_10_respTimrAct$EN = + WILL_FIRE_RL_wci_10_wrkBusy && + (!wci_10_respTimr_628_ULT_1_SL_wci_10_wTimeout_6_ETC___d1631 || + wci_10_wciResponse$wget[33:32] != 2'd0) || + wci_10_reqF_cntr_r ; + + // register wci_10_sThreadBusy_d + assign wci_10_sThreadBusy_d$D_IN = wci_Vm_10_SThreadBusy ; + assign wci_10_sThreadBusy_d$EN = 1'd1 ; + + // register wci_10_sfCap + assign wci_10_sfCap$D_IN = wci_10_sfCapSet ; + assign wci_10_sfCap$EN = wci_10_sfCapSet || wci_10_sfCapClear ; + + // register wci_10_sfCapClear + assign wci_10_sfCapClear$D_IN = wci_10_sfCapClear_1$whas ; + assign wci_10_sfCapClear$EN = 1'd1 ; + + // register wci_10_sfCapSet + assign wci_10_sfCapSet$D_IN = wci_Vm_10_SFlag[0] ; + assign wci_10_sfCapSet$EN = 1'd1 ; + + // register wci_10_slvPresent + assign wci_10_slvPresent$D_IN = wci_Vm_10_SFlag[1] ; + assign wci_10_slvPresent$EN = 1'd1 ; + + // register wci_10_wReset_n + assign wci_10_wReset_n$D_IN = cpReq[59] ; + assign wci_10_wReset_n$EN = + WILL_FIRE_RL_cpDispatch_F_F_T_E10_F_F_T_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E10_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E10_F_F_T_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E10_F_F_T_T_T ; + + // register wci_10_wStatus + assign wci_10_wStatus$D_IN = + { 4'b0, + !wci_10_lastOpWrite[1] || wci_10_lastOpWrite[0], + IF_wci_10_lastControlOp_713_BIT_3_714_THEN_wci_ETC___d1728 } ; + assign wci_10_wStatus$EN = 1'd1 ; + + // register wci_10_wTimeout + assign wci_10_wTimeout$D_IN = cpReq[32:28] ; + assign wci_10_wTimeout$EN = + WILL_FIRE_RL_cpDispatch_F_F_T_E10_F_F_T_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E10_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E10_F_F_T_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E10_F_F_T_T_T ; + + // register wci_11_busy + assign wci_11_busy$D_IN = !MUX_wci_11_busy$write_1__SEL_1 ; + assign wci_11_busy$EN = + WILL_FIRE_RL_wci_11_wrkBusy && + (!wci_11_respTimr_768_ULT_1_SL_wci_11_wTimeout_7_ETC___d1771 || + wci_11_wciResponse$wget[33:32] != 2'd0) || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_F_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E11_T_T ; + + // register wci_11_lastConfigAddr + assign wci_11_lastConfigAddr$D_IN = wci_0_lastConfigAddr$D_IN ; + assign wci_11_lastConfigAddr$EN = + WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E11_T_T ; + + // register wci_11_lastConfigBE + assign wci_11_lastConfigBE$D_IN = wci_0_lastConfigBE$D_IN ; + assign wci_11_lastConfigBE$EN = + WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E11_T_T ; + + // register wci_11_lastControlOp + assign wci_11_lastControlOp$D_IN = wci_0_lastControlOp$D_IN ; + assign wci_11_lastControlOp$EN = WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_F_T_T ; + + // register wci_11_lastOpWrite + assign wci_11_lastOpWrite$D_IN = + WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_T_T ? 2'd2 : 2'd3 ; + assign wci_11_lastOpWrite$EN = + WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E11_T_T ; + + // register wci_11_mFlagReg + assign wci_11_mFlagReg$D_IN = 2'h0 ; + assign wci_11_mFlagReg$EN = 1'b0 ; + + // register wci_11_pageWindow + assign wci_11_pageWindow$D_IN = cpReq[39:28] ; + assign wci_11_pageWindow$EN = WILL_FIRE_RL_cpDispatch_F_F_T_E11_F_F_F_T ; + + // register wci_11_reqERR + assign wci_11_reqERR$D_IN = + MUX_wci_11_reqERR$write_1__SEL_1 ? + MUX_wci_11_reqERR$write_1__VAL_1 : + 3'd0 ; + assign wci_11_reqERR$EN = + WILL_FIRE_RL_wci_11_wrkBusy && + wci_11_wciResponse$wget[33:32] == 2'd3 && + (wci_11_reqPend == 2'd1 || wci_11_reqPend == 2'd2 || + wci_11_reqPend == 2'd3) || + WILL_FIRE_RL_cpDispatch_F_F_T_E11_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E11_F_F_T_T_T ; + + // register wci_11_reqFAIL + assign wci_11_reqFAIL$D_IN = + MUX_wci_11_reqFAIL$write_1__SEL_1 ? + MUX_wci_11_reqFAIL$write_1__VAL_1 : + 3'd0 ; + assign wci_11_reqFAIL$EN = + WILL_FIRE_RL_wci_11_wrkBusy && + wci_11_wciResponse$wget[33:32] == 2'd2 && + (wci_11_reqPend == 2'd1 || wci_11_reqPend == 2'd2 || + wci_11_reqPend == 2'd3) || + WILL_FIRE_RL_cpDispatch_F_F_T_E11_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E11_F_F_T_T_T ; + + // register wci_11_reqF_cntr_r + assign wci_11_reqF_cntr_r$D_IN = + WILL_FIRE_RL_wci_11_reqF_incCtr ? + MUX_wci_11_reqF_cntr_r$write_1__VAL_1 : + MUX_wci_11_reqF_cntr_r$write_1__VAL_2 ; + assign wci_11_reqF_cntr_r$EN = + WILL_FIRE_RL_wci_11_reqF_incCtr || + WILL_FIRE_RL_wci_11_reqF_decCtr ; + + // register wci_11_reqF_q_0 + always@(MUX_wci_11_reqF_q_0$write_1__SEL_1 or + MUX_wci_11_reqF_q_0$write_1__VAL_1 or + WILL_FIRE_RL_wci_11_reqF_both or + MUX_wci_11_reqF_q_0$write_1__VAL_2 or + WILL_FIRE_RL_wci_11_reqF_decCtr) begin case (1'b1) // synopsys parallel_case - MUX_wci_reqF_14_q_0$write_1__SEL_1: - wci_reqF_14_q_0$D_IN = MUX_wci_reqF_14_q_0$write_1__VAL_1; - WILL_FIRE_RL_wci_reqF_14_both: - wci_reqF_14_q_0$D_IN = MUX_wci_reqF_14_q_0$write_1__VAL_2; - WILL_FIRE_RL_wci_reqF_14_decCtr: - wci_reqF_14_q_0$D_IN = 72'h0000000000AAAAAAAA; - default: wci_reqF_14_q_0$D_IN = + MUX_wci_11_reqF_q_0$write_1__SEL_1: + wci_11_reqF_q_0$D_IN = MUX_wci_11_reqF_q_0$write_1__VAL_1; + WILL_FIRE_RL_wci_11_reqF_both: + wci_11_reqF_q_0$D_IN = MUX_wci_11_reqF_q_0$write_1__VAL_2; + WILL_FIRE_RL_wci_11_reqF_decCtr: + wci_11_reqF_q_0$D_IN = 72'h0000000000AAAAAAAA; + default: wci_11_reqF_q_0$D_IN = 72'hAAAAAAAAAAAAAAAAAA /* unspecified value */ ; endcase end - assign wci_reqF_14_q_0$EN = - WILL_FIRE_RL_wci_reqF_14_incCtr && !wci_reqF_14_c_r || - WILL_FIRE_RL_wci_reqF_14_both || - WILL_FIRE_RL_wci_reqF_14_decCtr ; - - // register wci_reqF_1_c_r - assign wci_reqF_1_c_r$D_IN = - WILL_FIRE_RL_wci_reqF_1_incCtr ? - MUX_wci_reqF_1_c_r$write_1__VAL_1 : - MUX_wci_reqF_1_c_r$write_1__VAL_2 ; - assign wci_reqF_1_c_r$EN = - WILL_FIRE_RL_wci_reqF_1_incCtr || - WILL_FIRE_RL_wci_reqF_1_decCtr ; - - // register wci_reqF_1_q_0 - always@(WILL_FIRE_RL_wci_reqF_1_both or - MUX_wci_reqF_1_q_0$write_1__VAL_1 or - MUX_wci_reqF_1_q_0$write_1__SEL_2 or - MUX_wci_reqF_1_q_0$write_1__VAL_2 or WILL_FIRE_RL_wci_reqF_1_decCtr) + assign wci_11_reqF_q_0$EN = + WILL_FIRE_RL_wci_11_reqF_incCtr && !wci_11_reqF_cntr_r || + WILL_FIRE_RL_wci_11_reqF_both || + WILL_FIRE_RL_wci_11_reqF_decCtr ; + + // register wci_11_reqPend + always@(MUX_wci_11_reqPend$write_1__SEL_1 or + WILL_FIRE_RL_cpDispatch_F_F_T_E11_T_T or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_T_T or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_F_T_T) begin case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_wci_reqF_1_both: - wci_reqF_1_q_0$D_IN = MUX_wci_reqF_1_q_0$write_1__VAL_1; - MUX_wci_reqF_1_q_0$write_1__SEL_2: - wci_reqF_1_q_0$D_IN = MUX_wci_reqF_1_q_0$write_1__VAL_2; - WILL_FIRE_RL_wci_reqF_1_decCtr: - wci_reqF_1_q_0$D_IN = 72'h0000000000AAAAAAAA; - default: wci_reqF_1_q_0$D_IN = - 72'hAAAAAAAAAAAAAAAAAA /* unspecified value */ ; + MUX_wci_11_reqPend$write_1__SEL_1: wci_11_reqPend$D_IN = 2'd0; + WILL_FIRE_RL_cpDispatch_F_F_T_E11_T_T: wci_11_reqPend$D_IN = 2'd1; + WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_T_T: wci_11_reqPend$D_IN = 2'd2; + WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_F_T_T: wci_11_reqPend$D_IN = 2'd3; + default: wci_11_reqPend$D_IN = 2'b10 /* unspecified value */ ; endcase end - assign wci_reqF_1_q_0$EN = - WILL_FIRE_RL_wci_reqF_1_both || - WILL_FIRE_RL_wci_reqF_1_incCtr && !wci_reqF_1_c_r || - WILL_FIRE_RL_wci_reqF_1_decCtr ; - - // register wci_reqF_2_c_r - assign wci_reqF_2_c_r$D_IN = - WILL_FIRE_RL_wci_reqF_2_incCtr ? - MUX_wci_reqF_2_c_r$write_1__VAL_1 : - MUX_wci_reqF_2_c_r$write_1__VAL_2 ; - assign wci_reqF_2_c_r$EN = - WILL_FIRE_RL_wci_reqF_2_incCtr || - WILL_FIRE_RL_wci_reqF_2_decCtr ; - - // register wci_reqF_2_q_0 - always@(MUX_wci_reqF_2_q_0$write_1__SEL_1 or - MUX_wci_reqF_2_q_0$write_1__VAL_1 or - WILL_FIRE_RL_wci_reqF_2_both or - MUX_wci_reqF_2_q_0$write_1__VAL_2 or WILL_FIRE_RL_wci_reqF_2_decCtr) + assign wci_11_reqPend$EN = + WILL_FIRE_RL_wci_11_wrkBusy && + wci_11_wciResponse$wget[33:32] != 2'd0 || + WILL_FIRE_RL_cpDispatch_F_F_T_E11_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_F_T_T ; + + // register wci_11_reqTO + assign wci_11_reqTO$D_IN = + MUX_wci_11_reqTO$write_1__SEL_1 ? + MUX_wci_11_reqTO$write_1__VAL_1 : + 3'd0 ; + assign wci_11_reqTO$EN = + WILL_FIRE_RL_wci_11_wrkBusy && + wci_11_wciResponse_wget__763_BITS_33_TO_32_764_ETC___d1792 || + WILL_FIRE_RL_cpDispatch_F_F_T_E11_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E11_F_F_T_T_T ; + + // register wci_11_respTimr + assign wci_11_respTimr$D_IN = + wci_11_reqF_cntr_r ? 32'd0 : MUX_wci_11_respTimr$write_1__VAL_2 ; + assign wci_11_respTimr$EN = + WILL_FIRE_RL_wci_11_wrkBusy || wci_11_reqF_cntr_r ; + + // register wci_11_respTimrAct + assign wci_11_respTimrAct$D_IN = wci_11_reqF_cntr_r ; + assign wci_11_respTimrAct$EN = + WILL_FIRE_RL_wci_11_wrkBusy && + (!wci_11_respTimr_768_ULT_1_SL_wci_11_wTimeout_7_ETC___d1771 || + wci_11_wciResponse$wget[33:32] != 2'd0) || + wci_11_reqF_cntr_r ; + + // register wci_11_sThreadBusy_d + assign wci_11_sThreadBusy_d$D_IN = wci_Vm_11_SThreadBusy ; + assign wci_11_sThreadBusy_d$EN = 1'd1 ; + + // register wci_11_sfCap + assign wci_11_sfCap$D_IN = wci_11_sfCapSet ; + assign wci_11_sfCap$EN = wci_11_sfCapSet || wci_11_sfCapClear ; + + // register wci_11_sfCapClear + assign wci_11_sfCapClear$D_IN = wci_11_sfCapClear_1$whas ; + assign wci_11_sfCapClear$EN = 1'd1 ; + + // register wci_11_sfCapSet + assign wci_11_sfCapSet$D_IN = wci_Vm_11_SFlag[0] ; + assign wci_11_sfCapSet$EN = 1'd1 ; + + // register wci_11_slvPresent + assign wci_11_slvPresent$D_IN = wci_Vm_11_SFlag[1] ; + assign wci_11_slvPresent$EN = 1'd1 ; + + // register wci_11_wReset_n + assign wci_11_wReset_n$D_IN = cpReq[59] ; + assign wci_11_wReset_n$EN = + WILL_FIRE_RL_cpDispatch_F_F_T_E11_F_F_T_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E11_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E11_F_F_T_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E11_F_F_T_T_T ; + + // register wci_11_wStatus + assign wci_11_wStatus$D_IN = + { 4'b0, + !wci_11_lastOpWrite[1] || wci_11_lastOpWrite[0], + IF_wci_11_lastControlOp_853_BIT_3_854_THEN_wci_ETC___d1868 } ; + assign wci_11_wStatus$EN = 1'd1 ; + + // register wci_11_wTimeout + assign wci_11_wTimeout$D_IN = cpReq[32:28] ; + assign wci_11_wTimeout$EN = + WILL_FIRE_RL_cpDispatch_F_F_T_E11_F_F_T_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E11_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E11_F_F_T_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E11_F_F_T_T_T ; + + // register wci_12_busy + assign wci_12_busy$D_IN = !MUX_wci_12_busy$write_1__SEL_1 ; + assign wci_12_busy$EN = + WILL_FIRE_RL_wci_12_wrkBusy && + (!wci_12_respTimr_908_ULT_1_SL_wci_12_wTimeout_9_ETC___d1911 || + wci_12_wciResponse$wget[33:32] != 2'd0) || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_F_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E12_T_T ; + + // register wci_12_lastConfigAddr + assign wci_12_lastConfigAddr$D_IN = wci_0_lastConfigAddr$D_IN ; + assign wci_12_lastConfigAddr$EN = + WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E12_T_T ; + + // register wci_12_lastConfigBE + assign wci_12_lastConfigBE$D_IN = wci_0_lastConfigBE$D_IN ; + assign wci_12_lastConfigBE$EN = + WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E12_T_T ; + + // register wci_12_lastControlOp + assign wci_12_lastControlOp$D_IN = wci_0_lastControlOp$D_IN ; + assign wci_12_lastControlOp$EN = WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_F_T_T ; + + // register wci_12_lastOpWrite + assign wci_12_lastOpWrite$D_IN = + WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_T_T ? 2'd2 : 2'd3 ; + assign wci_12_lastOpWrite$EN = + WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E12_T_T ; + + // register wci_12_mFlagReg + assign wci_12_mFlagReg$D_IN = 2'h0 ; + assign wci_12_mFlagReg$EN = 1'b0 ; + + // register wci_12_pageWindow + assign wci_12_pageWindow$D_IN = cpReq[39:28] ; + assign wci_12_pageWindow$EN = WILL_FIRE_RL_cpDispatch_F_F_T_E12_F_F_F_T ; + + // register wci_12_reqERR + assign wci_12_reqERR$D_IN = + MUX_wci_12_reqERR$write_1__SEL_1 ? + MUX_wci_12_reqERR$write_1__VAL_1 : + 3'd0 ; + assign wci_12_reqERR$EN = + WILL_FIRE_RL_wci_12_wrkBusy && + wci_12_wciResponse$wget[33:32] == 2'd3 && + (wci_12_reqPend == 2'd1 || wci_12_reqPend == 2'd2 || + wci_12_reqPend == 2'd3) || + WILL_FIRE_RL_cpDispatch_F_F_T_E12_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E12_F_F_T_T_T ; + + // register wci_12_reqFAIL + assign wci_12_reqFAIL$D_IN = + MUX_wci_12_reqFAIL$write_1__SEL_1 ? + MUX_wci_12_reqFAIL$write_1__VAL_1 : + 3'd0 ; + assign wci_12_reqFAIL$EN = + WILL_FIRE_RL_wci_12_wrkBusy && + wci_12_wciResponse$wget[33:32] == 2'd2 && + (wci_12_reqPend == 2'd1 || wci_12_reqPend == 2'd2 || + wci_12_reqPend == 2'd3) || + WILL_FIRE_RL_cpDispatch_F_F_T_E12_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E12_F_F_T_T_T ; + + // register wci_12_reqF_cntr_r + assign wci_12_reqF_cntr_r$D_IN = + WILL_FIRE_RL_wci_12_reqF_incCtr ? + MUX_wci_12_reqF_cntr_r$write_1__VAL_1 : + MUX_wci_12_reqF_cntr_r$write_1__VAL_2 ; + assign wci_12_reqF_cntr_r$EN = + WILL_FIRE_RL_wci_12_reqF_incCtr || + WILL_FIRE_RL_wci_12_reqF_decCtr ; + + // register wci_12_reqF_q_0 + always@(MUX_wci_12_reqF_q_0$write_1__SEL_1 or + MUX_wci_12_reqF_q_0$write_1__VAL_1 or + WILL_FIRE_RL_wci_12_reqF_both or + MUX_wci_12_reqF_q_0$write_1__VAL_2 or + WILL_FIRE_RL_wci_12_reqF_decCtr) begin case (1'b1) // synopsys parallel_case - MUX_wci_reqF_2_q_0$write_1__SEL_1: - wci_reqF_2_q_0$D_IN = MUX_wci_reqF_2_q_0$write_1__VAL_1; - WILL_FIRE_RL_wci_reqF_2_both: - wci_reqF_2_q_0$D_IN = MUX_wci_reqF_2_q_0$write_1__VAL_2; - WILL_FIRE_RL_wci_reqF_2_decCtr: - wci_reqF_2_q_0$D_IN = 72'h0000000000AAAAAAAA; - default: wci_reqF_2_q_0$D_IN = + MUX_wci_12_reqF_q_0$write_1__SEL_1: + wci_12_reqF_q_0$D_IN = MUX_wci_12_reqF_q_0$write_1__VAL_1; + WILL_FIRE_RL_wci_12_reqF_both: + wci_12_reqF_q_0$D_IN = MUX_wci_12_reqF_q_0$write_1__VAL_2; + WILL_FIRE_RL_wci_12_reqF_decCtr: + wci_12_reqF_q_0$D_IN = 72'h0000000000AAAAAAAA; + default: wci_12_reqF_q_0$D_IN = 72'hAAAAAAAAAAAAAAAAAA /* unspecified value */ ; endcase end - assign wci_reqF_2_q_0$EN = - WILL_FIRE_RL_wci_reqF_2_incCtr && !wci_reqF_2_c_r || - WILL_FIRE_RL_wci_reqF_2_both || - WILL_FIRE_RL_wci_reqF_2_decCtr ; - - // register wci_reqF_3_c_r - assign wci_reqF_3_c_r$D_IN = - WILL_FIRE_RL_wci_reqF_3_incCtr ? - MUX_wci_reqF_3_c_r$write_1__VAL_1 : - MUX_wci_reqF_3_c_r$write_1__VAL_2 ; - assign wci_reqF_3_c_r$EN = - WILL_FIRE_RL_wci_reqF_3_incCtr || - WILL_FIRE_RL_wci_reqF_3_decCtr ; - - // register wci_reqF_3_q_0 - always@(MUX_wci_reqF_3_q_0$write_1__SEL_1 or - MUX_wci_reqF_3_q_0$write_1__VAL_1 or - WILL_FIRE_RL_wci_reqF_3_both or - MUX_wci_reqF_3_q_0$write_1__VAL_2 or WILL_FIRE_RL_wci_reqF_3_decCtr) + assign wci_12_reqF_q_0$EN = + WILL_FIRE_RL_wci_12_reqF_incCtr && !wci_12_reqF_cntr_r || + WILL_FIRE_RL_wci_12_reqF_both || + WILL_FIRE_RL_wci_12_reqF_decCtr ; + + // register wci_12_reqPend + always@(MUX_wci_12_reqPend$write_1__SEL_1 or + WILL_FIRE_RL_cpDispatch_F_F_T_E12_T_T or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_T_T or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_F_T_T) begin case (1'b1) // synopsys parallel_case - MUX_wci_reqF_3_q_0$write_1__SEL_1: - wci_reqF_3_q_0$D_IN = MUX_wci_reqF_3_q_0$write_1__VAL_1; - WILL_FIRE_RL_wci_reqF_3_both: - wci_reqF_3_q_0$D_IN = MUX_wci_reqF_3_q_0$write_1__VAL_2; - WILL_FIRE_RL_wci_reqF_3_decCtr: - wci_reqF_3_q_0$D_IN = 72'h0000000000AAAAAAAA; - default: wci_reqF_3_q_0$D_IN = - 72'hAAAAAAAAAAAAAAAAAA /* unspecified value */ ; + MUX_wci_12_reqPend$write_1__SEL_1: wci_12_reqPend$D_IN = 2'd0; + WILL_FIRE_RL_cpDispatch_F_F_T_E12_T_T: wci_12_reqPend$D_IN = 2'd1; + WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_T_T: wci_12_reqPend$D_IN = 2'd2; + WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_F_T_T: wci_12_reqPend$D_IN = 2'd3; + default: wci_12_reqPend$D_IN = 2'b10 /* unspecified value */ ; endcase end - assign wci_reqF_3_q_0$EN = - WILL_FIRE_RL_wci_reqF_3_incCtr && !wci_reqF_3_c_r || - WILL_FIRE_RL_wci_reqF_3_both || - WILL_FIRE_RL_wci_reqF_3_decCtr ; - - // register wci_reqF_4_c_r - assign wci_reqF_4_c_r$D_IN = - WILL_FIRE_RL_wci_reqF_4_incCtr ? - MUX_wci_reqF_4_c_r$write_1__VAL_1 : - MUX_wci_reqF_4_c_r$write_1__VAL_2 ; - assign wci_reqF_4_c_r$EN = - WILL_FIRE_RL_wci_reqF_4_incCtr || - WILL_FIRE_RL_wci_reqF_4_decCtr ; - - // register wci_reqF_4_q_0 - always@(MUX_wci_reqF_4_q_0$write_1__SEL_1 or - MUX_wci_reqF_4_q_0$write_1__VAL_1 or - WILL_FIRE_RL_wci_reqF_4_both or - MUX_wci_reqF_4_q_0$write_1__VAL_2 or WILL_FIRE_RL_wci_reqF_4_decCtr) + assign wci_12_reqPend$EN = + WILL_FIRE_RL_wci_12_wrkBusy && + wci_12_wciResponse$wget[33:32] != 2'd0 || + WILL_FIRE_RL_cpDispatch_F_F_T_E12_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_F_T_T ; + + // register wci_12_reqTO + assign wci_12_reqTO$D_IN = + MUX_wci_12_reqTO$write_1__SEL_1 ? + MUX_wci_12_reqTO$write_1__VAL_1 : + 3'd0 ; + assign wci_12_reqTO$EN = + WILL_FIRE_RL_wci_12_wrkBusy && + wci_12_wciResponse_wget__903_BITS_33_TO_32_904_ETC___d1932 || + WILL_FIRE_RL_cpDispatch_F_F_T_E12_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E12_F_F_T_T_T ; + + // register wci_12_respTimr + assign wci_12_respTimr$D_IN = + wci_12_reqF_cntr_r ? 32'd0 : MUX_wci_12_respTimr$write_1__VAL_2 ; + assign wci_12_respTimr$EN = + WILL_FIRE_RL_wci_12_wrkBusy || wci_12_reqF_cntr_r ; + + // register wci_12_respTimrAct + assign wci_12_respTimrAct$D_IN = wci_12_reqF_cntr_r ; + assign wci_12_respTimrAct$EN = + WILL_FIRE_RL_wci_12_wrkBusy && + (!wci_12_respTimr_908_ULT_1_SL_wci_12_wTimeout_9_ETC___d1911 || + wci_12_wciResponse$wget[33:32] != 2'd0) || + wci_12_reqF_cntr_r ; + + // register wci_12_sThreadBusy_d + assign wci_12_sThreadBusy_d$D_IN = wci_Vm_12_SThreadBusy ; + assign wci_12_sThreadBusy_d$EN = 1'd1 ; + + // register wci_12_sfCap + assign wci_12_sfCap$D_IN = wci_12_sfCapSet ; + assign wci_12_sfCap$EN = wci_12_sfCapSet || wci_12_sfCapClear ; + + // register wci_12_sfCapClear + assign wci_12_sfCapClear$D_IN = wci_12_sfCapClear_1$whas ; + assign wci_12_sfCapClear$EN = 1'd1 ; + + // register wci_12_sfCapSet + assign wci_12_sfCapSet$D_IN = wci_Vm_12_SFlag[0] ; + assign wci_12_sfCapSet$EN = 1'd1 ; + + // register wci_12_slvPresent + assign wci_12_slvPresent$D_IN = wci_Vm_12_SFlag[1] ; + assign wci_12_slvPresent$EN = 1'd1 ; + + // register wci_12_wReset_n + assign wci_12_wReset_n$D_IN = cpReq[59] ; + assign wci_12_wReset_n$EN = + WILL_FIRE_RL_cpDispatch_F_F_T_E12_F_F_T_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E12_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E12_F_F_T_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E12_F_F_T_T_T ; + + // register wci_12_wStatus + assign wci_12_wStatus$D_IN = + { 4'b0, + !wci_12_lastOpWrite[1] || wci_12_lastOpWrite[0], + IF_wci_12_lastControlOp_993_BIT_3_994_THEN_wci_ETC___d2008 } ; + assign wci_12_wStatus$EN = 1'd1 ; + + // register wci_12_wTimeout + assign wci_12_wTimeout$D_IN = cpReq[32:28] ; + assign wci_12_wTimeout$EN = + WILL_FIRE_RL_cpDispatch_F_F_T_E12_F_F_T_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E12_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E12_F_F_T_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E12_F_F_T_T_T ; + + // register wci_13_busy + assign wci_13_busy$D_IN = !MUX_wci_13_busy$write_1__SEL_1 ; + assign wci_13_busy$EN = + WILL_FIRE_RL_wci_13_wrkBusy && + (!wci_13_respTimr_048_ULT_1_SL_wci_13_wTimeout_0_ETC___d2051 || + wci_13_wciResponse$wget[33:32] != 2'd0) || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_F_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E13_T_T ; + + // register wci_13_lastConfigAddr + assign wci_13_lastConfigAddr$D_IN = wci_0_lastConfigAddr$D_IN ; + assign wci_13_lastConfigAddr$EN = + WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E13_T_T ; + + // register wci_13_lastConfigBE + assign wci_13_lastConfigBE$D_IN = wci_0_lastConfigBE$D_IN ; + assign wci_13_lastConfigBE$EN = + WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E13_T_T ; + + // register wci_13_lastControlOp + assign wci_13_lastControlOp$D_IN = wci_0_lastControlOp$D_IN ; + assign wci_13_lastControlOp$EN = WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_F_T_T ; + + // register wci_13_lastOpWrite + assign wci_13_lastOpWrite$D_IN = + WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_T_T ? 2'd2 : 2'd3 ; + assign wci_13_lastOpWrite$EN = + WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E13_T_T ; + + // register wci_13_mFlagReg + assign wci_13_mFlagReg$D_IN = 2'h0 ; + assign wci_13_mFlagReg$EN = 1'b0 ; + + // register wci_13_pageWindow + assign wci_13_pageWindow$D_IN = cpReq[39:28] ; + assign wci_13_pageWindow$EN = WILL_FIRE_RL_cpDispatch_F_F_T_E13_F_F_F_T ; + + // register wci_13_reqERR + assign wci_13_reqERR$D_IN = + MUX_wci_13_reqERR$write_1__SEL_1 ? + MUX_wci_13_reqERR$write_1__VAL_1 : + 3'd0 ; + assign wci_13_reqERR$EN = + WILL_FIRE_RL_wci_13_wrkBusy && + wci_13_wciResponse$wget[33:32] == 2'd3 && + (wci_13_reqPend == 2'd1 || wci_13_reqPend == 2'd2 || + wci_13_reqPend == 2'd3) || + WILL_FIRE_RL_cpDispatch_F_F_T_E13_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E13_F_F_T_T_T ; + + // register wci_13_reqFAIL + assign wci_13_reqFAIL$D_IN = + MUX_wci_13_reqFAIL$write_1__SEL_1 ? + MUX_wci_13_reqFAIL$write_1__VAL_1 : + 3'd0 ; + assign wci_13_reqFAIL$EN = + WILL_FIRE_RL_wci_13_wrkBusy && + wci_13_wciResponse$wget[33:32] == 2'd2 && + (wci_13_reqPend == 2'd1 || wci_13_reqPend == 2'd2 || + wci_13_reqPend == 2'd3) || + WILL_FIRE_RL_cpDispatch_F_F_T_E13_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E13_F_F_T_T_T ; + + // register wci_13_reqF_cntr_r + assign wci_13_reqF_cntr_r$D_IN = + WILL_FIRE_RL_wci_13_reqF_incCtr ? + MUX_wci_13_reqF_cntr_r$write_1__VAL_1 : + MUX_wci_13_reqF_cntr_r$write_1__VAL_2 ; + assign wci_13_reqF_cntr_r$EN = + WILL_FIRE_RL_wci_13_reqF_incCtr || + WILL_FIRE_RL_wci_13_reqF_decCtr ; + + // register wci_13_reqF_q_0 + always@(MUX_wci_13_reqF_q_0$write_1__SEL_1 or + MUX_wci_13_reqF_q_0$write_1__VAL_1 or + WILL_FIRE_RL_wci_13_reqF_both or + MUX_wci_13_reqF_q_0$write_1__VAL_2 or + WILL_FIRE_RL_wci_13_reqF_decCtr) begin case (1'b1) // synopsys parallel_case - MUX_wci_reqF_4_q_0$write_1__SEL_1: - wci_reqF_4_q_0$D_IN = MUX_wci_reqF_4_q_0$write_1__VAL_1; - WILL_FIRE_RL_wci_reqF_4_both: - wci_reqF_4_q_0$D_IN = MUX_wci_reqF_4_q_0$write_1__VAL_2; - WILL_FIRE_RL_wci_reqF_4_decCtr: - wci_reqF_4_q_0$D_IN = 72'h0000000000AAAAAAAA; - default: wci_reqF_4_q_0$D_IN = + MUX_wci_13_reqF_q_0$write_1__SEL_1: + wci_13_reqF_q_0$D_IN = MUX_wci_13_reqF_q_0$write_1__VAL_1; + WILL_FIRE_RL_wci_13_reqF_both: + wci_13_reqF_q_0$D_IN = MUX_wci_13_reqF_q_0$write_1__VAL_2; + WILL_FIRE_RL_wci_13_reqF_decCtr: + wci_13_reqF_q_0$D_IN = 72'h0000000000AAAAAAAA; + default: wci_13_reqF_q_0$D_IN = 72'hAAAAAAAAAAAAAAAAAA /* unspecified value */ ; endcase end - assign wci_reqF_4_q_0$EN = - WILL_FIRE_RL_wci_reqF_4_incCtr && !wci_reqF_4_c_r || - WILL_FIRE_RL_wci_reqF_4_both || - WILL_FIRE_RL_wci_reqF_4_decCtr ; - - // register wci_reqF_5_c_r - assign wci_reqF_5_c_r$D_IN = - WILL_FIRE_RL_wci_reqF_5_incCtr ? - MUX_wci_reqF_5_c_r$write_1__VAL_1 : - MUX_wci_reqF_5_c_r$write_1__VAL_2 ; - assign wci_reqF_5_c_r$EN = - WILL_FIRE_RL_wci_reqF_5_incCtr || - WILL_FIRE_RL_wci_reqF_5_decCtr ; - - // register wci_reqF_5_q_0 - always@(MUX_wci_reqF_5_q_0$write_1__SEL_1 or - MUX_wci_reqF_5_q_0$write_1__VAL_1 or - WILL_FIRE_RL_wci_reqF_5_both or - MUX_wci_reqF_5_q_0$write_1__VAL_2 or WILL_FIRE_RL_wci_reqF_5_decCtr) + assign wci_13_reqF_q_0$EN = + WILL_FIRE_RL_wci_13_reqF_incCtr && !wci_13_reqF_cntr_r || + WILL_FIRE_RL_wci_13_reqF_both || + WILL_FIRE_RL_wci_13_reqF_decCtr ; + + // register wci_13_reqPend + always@(MUX_wci_13_reqPend$write_1__SEL_1 or + WILL_FIRE_RL_cpDispatch_F_F_T_E13_T_T or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_T_T or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_F_T_T) begin case (1'b1) // synopsys parallel_case - MUX_wci_reqF_5_q_0$write_1__SEL_1: - wci_reqF_5_q_0$D_IN = MUX_wci_reqF_5_q_0$write_1__VAL_1; - WILL_FIRE_RL_wci_reqF_5_both: - wci_reqF_5_q_0$D_IN = MUX_wci_reqF_5_q_0$write_1__VAL_2; - WILL_FIRE_RL_wci_reqF_5_decCtr: - wci_reqF_5_q_0$D_IN = 72'h0000000000AAAAAAAA; - default: wci_reqF_5_q_0$D_IN = - 72'hAAAAAAAAAAAAAAAAAA /* unspecified value */ ; + MUX_wci_13_reqPend$write_1__SEL_1: wci_13_reqPend$D_IN = 2'd0; + WILL_FIRE_RL_cpDispatch_F_F_T_E13_T_T: wci_13_reqPend$D_IN = 2'd1; + WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_T_T: wci_13_reqPend$D_IN = 2'd2; + WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_F_T_T: wci_13_reqPend$D_IN = 2'd3; + default: wci_13_reqPend$D_IN = 2'b10 /* unspecified value */ ; endcase end - assign wci_reqF_5_q_0$EN = - WILL_FIRE_RL_wci_reqF_5_incCtr && !wci_reqF_5_c_r || - WILL_FIRE_RL_wci_reqF_5_both || - WILL_FIRE_RL_wci_reqF_5_decCtr ; - - // register wci_reqF_6_c_r - assign wci_reqF_6_c_r$D_IN = - WILL_FIRE_RL_wci_reqF_6_incCtr ? - MUX_wci_reqF_6_c_r$write_1__VAL_1 : - MUX_wci_reqF_6_c_r$write_1__VAL_2 ; - assign wci_reqF_6_c_r$EN = - WILL_FIRE_RL_wci_reqF_6_incCtr || - WILL_FIRE_RL_wci_reqF_6_decCtr ; - - // register wci_reqF_6_q_0 - always@(MUX_wci_reqF_6_q_0$write_1__SEL_1 or - MUX_wci_reqF_6_q_0$write_1__VAL_1 or - WILL_FIRE_RL_wci_reqF_6_both or - MUX_wci_reqF_6_q_0$write_1__VAL_2 or WILL_FIRE_RL_wci_reqF_6_decCtr) + assign wci_13_reqPend$EN = + WILL_FIRE_RL_wci_13_wrkBusy && + wci_13_wciResponse$wget[33:32] != 2'd0 || + WILL_FIRE_RL_cpDispatch_F_F_T_E13_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_F_T_T ; + + // register wci_13_reqTO + assign wci_13_reqTO$D_IN = + MUX_wci_13_reqTO$write_1__SEL_1 ? + MUX_wci_13_reqTO$write_1__VAL_1 : + 3'd0 ; + assign wci_13_reqTO$EN = + WILL_FIRE_RL_wci_13_wrkBusy && + wci_13_wciResponse_wget__043_BITS_33_TO_32_044_ETC___d2072 || + WILL_FIRE_RL_cpDispatch_F_F_T_E13_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E13_F_F_T_T_T ; + + // register wci_13_respTimr + assign wci_13_respTimr$D_IN = + wci_13_reqF_cntr_r ? 32'd0 : MUX_wci_13_respTimr$write_1__VAL_2 ; + assign wci_13_respTimr$EN = + WILL_FIRE_RL_wci_13_wrkBusy || wci_13_reqF_cntr_r ; + + // register wci_13_respTimrAct + assign wci_13_respTimrAct$D_IN = wci_13_reqF_cntr_r ; + assign wci_13_respTimrAct$EN = + WILL_FIRE_RL_wci_13_wrkBusy && + (!wci_13_respTimr_048_ULT_1_SL_wci_13_wTimeout_0_ETC___d2051 || + wci_13_wciResponse$wget[33:32] != 2'd0) || + wci_13_reqF_cntr_r ; + + // register wci_13_sThreadBusy_d + assign wci_13_sThreadBusy_d$D_IN = wci_Vm_13_SThreadBusy ; + assign wci_13_sThreadBusy_d$EN = 1'd1 ; + + // register wci_13_sfCap + assign wci_13_sfCap$D_IN = wci_13_sfCapSet ; + assign wci_13_sfCap$EN = wci_13_sfCapSet || wci_13_sfCapClear ; + + // register wci_13_sfCapClear + assign wci_13_sfCapClear$D_IN = wci_13_sfCapClear_1$whas ; + assign wci_13_sfCapClear$EN = 1'd1 ; + + // register wci_13_sfCapSet + assign wci_13_sfCapSet$D_IN = wci_Vm_13_SFlag[0] ; + assign wci_13_sfCapSet$EN = 1'd1 ; + + // register wci_13_slvPresent + assign wci_13_slvPresent$D_IN = wci_Vm_13_SFlag[1] ; + assign wci_13_slvPresent$EN = 1'd1 ; + + // register wci_13_wReset_n + assign wci_13_wReset_n$D_IN = cpReq[59] ; + assign wci_13_wReset_n$EN = + WILL_FIRE_RL_cpDispatch_F_F_T_E13_F_F_T_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E13_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E13_F_F_T_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E13_F_F_T_T_T ; + + // register wci_13_wStatus + assign wci_13_wStatus$D_IN = + { 4'b0, + !wci_13_lastOpWrite[1] || wci_13_lastOpWrite[0], + IF_wci_13_lastControlOp_133_BIT_3_134_THEN_wci_ETC___d2148 } ; + assign wci_13_wStatus$EN = 1'd1 ; + + // register wci_13_wTimeout + assign wci_13_wTimeout$D_IN = cpReq[32:28] ; + assign wci_13_wTimeout$EN = + WILL_FIRE_RL_cpDispatch_F_F_T_E13_F_F_T_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E13_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E13_F_F_T_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E13_F_F_T_T_T ; + + // register wci_14_busy + assign wci_14_busy$D_IN = !MUX_wci_14_busy$write_1__SEL_1 ; + assign wci_14_busy$EN = + WILL_FIRE_RL_wci_14_wrkBusy && + (!wci_14_respTimr_188_ULT_1_SL_wci_14_wTimeout_1_ETC___d2191 || + wci_14_wciResponse$wget[33:32] != 2'd0) || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_F_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E14_T_T ; + + // register wci_14_lastConfigAddr + assign wci_14_lastConfigAddr$D_IN = wci_0_lastConfigAddr$D_IN ; + assign wci_14_lastConfigAddr$EN = + WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E14_T_T ; + + // register wci_14_lastConfigBE + assign wci_14_lastConfigBE$D_IN = wci_0_lastConfigBE$D_IN ; + assign wci_14_lastConfigBE$EN = + WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E14_T_T ; + + // register wci_14_lastControlOp + assign wci_14_lastControlOp$D_IN = wci_0_lastControlOp$D_IN ; + assign wci_14_lastControlOp$EN = WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_F_T_T ; + + // register wci_14_lastOpWrite + assign wci_14_lastOpWrite$D_IN = + WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_T_T ? 2'd2 : 2'd3 ; + assign wci_14_lastOpWrite$EN = + WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E14_T_T ; + + // register wci_14_mFlagReg + assign wci_14_mFlagReg$D_IN = 2'h0 ; + assign wci_14_mFlagReg$EN = 1'b0 ; + + // register wci_14_pageWindow + assign wci_14_pageWindow$D_IN = cpReq[39:28] ; + assign wci_14_pageWindow$EN = WILL_FIRE_RL_cpDispatch_F_F_T_E14_F_F_F_T ; + + // register wci_14_reqERR + assign wci_14_reqERR$D_IN = + MUX_wci_14_reqERR$write_1__SEL_1 ? + MUX_wci_14_reqERR$write_1__VAL_1 : + 3'd0 ; + assign wci_14_reqERR$EN = + WILL_FIRE_RL_wci_14_wrkBusy && + wci_14_wciResponse$wget[33:32] == 2'd3 && + (wci_14_reqPend == 2'd1 || wci_14_reqPend == 2'd2 || + wci_14_reqPend == 2'd3) || + WILL_FIRE_RL_cpDispatch_F_F_T_E14_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E14_F_F_T_T_T ; + + // register wci_14_reqFAIL + assign wci_14_reqFAIL$D_IN = + MUX_wci_14_reqFAIL$write_1__SEL_1 ? + MUX_wci_14_reqFAIL$write_1__VAL_1 : + 3'd0 ; + assign wci_14_reqFAIL$EN = + WILL_FIRE_RL_wci_14_wrkBusy && + wci_14_wciResponse$wget[33:32] == 2'd2 && + (wci_14_reqPend == 2'd1 || wci_14_reqPend == 2'd2 || + wci_14_reqPend == 2'd3) || + WILL_FIRE_RL_cpDispatch_F_F_T_E14_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E14_F_F_T_T_T ; + + // register wci_14_reqF_cntr_r + assign wci_14_reqF_cntr_r$D_IN = + WILL_FIRE_RL_wci_14_reqF_incCtr ? + MUX_wci_14_reqF_cntr_r$write_1__VAL_1 : + MUX_wci_14_reqF_cntr_r$write_1__VAL_2 ; + assign wci_14_reqF_cntr_r$EN = + WILL_FIRE_RL_wci_14_reqF_incCtr || + WILL_FIRE_RL_wci_14_reqF_decCtr ; + + // register wci_14_reqF_q_0 + always@(MUX_wci_14_reqF_q_0$write_1__SEL_1 or + MUX_wci_14_reqF_q_0$write_1__VAL_1 or + WILL_FIRE_RL_wci_14_reqF_both or + MUX_wci_14_reqF_q_0$write_1__VAL_2 or + WILL_FIRE_RL_wci_14_reqF_decCtr) begin case (1'b1) // synopsys parallel_case - MUX_wci_reqF_6_q_0$write_1__SEL_1: - wci_reqF_6_q_0$D_IN = MUX_wci_reqF_6_q_0$write_1__VAL_1; - WILL_FIRE_RL_wci_reqF_6_both: - wci_reqF_6_q_0$D_IN = MUX_wci_reqF_6_q_0$write_1__VAL_2; - WILL_FIRE_RL_wci_reqF_6_decCtr: - wci_reqF_6_q_0$D_IN = 72'h0000000000AAAAAAAA; - default: wci_reqF_6_q_0$D_IN = + MUX_wci_14_reqF_q_0$write_1__SEL_1: + wci_14_reqF_q_0$D_IN = MUX_wci_14_reqF_q_0$write_1__VAL_1; + WILL_FIRE_RL_wci_14_reqF_both: + wci_14_reqF_q_0$D_IN = MUX_wci_14_reqF_q_0$write_1__VAL_2; + WILL_FIRE_RL_wci_14_reqF_decCtr: + wci_14_reqF_q_0$D_IN = 72'h0000000000AAAAAAAA; + default: wci_14_reqF_q_0$D_IN = 72'hAAAAAAAAAAAAAAAAAA /* unspecified value */ ; endcase end - assign wci_reqF_6_q_0$EN = - WILL_FIRE_RL_wci_reqF_6_incCtr && !wci_reqF_6_c_r || - WILL_FIRE_RL_wci_reqF_6_both || - WILL_FIRE_RL_wci_reqF_6_decCtr ; - - // register wci_reqF_7_c_r - assign wci_reqF_7_c_r$D_IN = - WILL_FIRE_RL_wci_reqF_7_incCtr ? - MUX_wci_reqF_7_c_r$write_1__VAL_1 : - MUX_wci_reqF_7_c_r$write_1__VAL_2 ; - assign wci_reqF_7_c_r$EN = - WILL_FIRE_RL_wci_reqF_7_incCtr || - WILL_FIRE_RL_wci_reqF_7_decCtr ; - - // register wci_reqF_7_q_0 - always@(MUX_wci_reqF_7_q_0$write_1__SEL_1 or - MUX_wci_reqF_7_q_0$write_1__VAL_1 or - WILL_FIRE_RL_wci_reqF_7_both or - MUX_wci_reqF_7_q_0$write_1__VAL_2 or WILL_FIRE_RL_wci_reqF_7_decCtr) + assign wci_14_reqF_q_0$EN = + WILL_FIRE_RL_wci_14_reqF_incCtr && !wci_14_reqF_cntr_r || + WILL_FIRE_RL_wci_14_reqF_both || + WILL_FIRE_RL_wci_14_reqF_decCtr ; + + // register wci_14_reqPend + always@(MUX_wci_14_reqPend$write_1__SEL_1 or + WILL_FIRE_RL_cpDispatch_F_F_T_E14_T_T or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_T_T or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_F_T_T) begin case (1'b1) // synopsys parallel_case - MUX_wci_reqF_7_q_0$write_1__SEL_1: - wci_reqF_7_q_0$D_IN = MUX_wci_reqF_7_q_0$write_1__VAL_1; - WILL_FIRE_RL_wci_reqF_7_both: - wci_reqF_7_q_0$D_IN = MUX_wci_reqF_7_q_0$write_1__VAL_2; - WILL_FIRE_RL_wci_reqF_7_decCtr: - wci_reqF_7_q_0$D_IN = 72'h0000000000AAAAAAAA; - default: wci_reqF_7_q_0$D_IN = - 72'hAAAAAAAAAAAAAAAAAA /* unspecified value */ ; + MUX_wci_14_reqPend$write_1__SEL_1: wci_14_reqPend$D_IN = 2'd0; + WILL_FIRE_RL_cpDispatch_F_F_T_E14_T_T: wci_14_reqPend$D_IN = 2'd1; + WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_T_T: wci_14_reqPend$D_IN = 2'd2; + WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_F_T_T: wci_14_reqPend$D_IN = 2'd3; + default: wci_14_reqPend$D_IN = 2'b10 /* unspecified value */ ; endcase end - assign wci_reqF_7_q_0$EN = - WILL_FIRE_RL_wci_reqF_7_incCtr && !wci_reqF_7_c_r || - WILL_FIRE_RL_wci_reqF_7_both || - WILL_FIRE_RL_wci_reqF_7_decCtr ; - - // register wci_reqF_8_c_r - assign wci_reqF_8_c_r$D_IN = - WILL_FIRE_RL_wci_reqF_8_incCtr ? - MUX_wci_reqF_8_c_r$write_1__VAL_1 : - MUX_wci_reqF_8_c_r$write_1__VAL_2 ; - assign wci_reqF_8_c_r$EN = - WILL_FIRE_RL_wci_reqF_8_incCtr || - WILL_FIRE_RL_wci_reqF_8_decCtr ; - - // register wci_reqF_8_q_0 - always@(MUX_wci_reqF_8_q_0$write_1__SEL_1 or - MUX_wci_reqF_8_q_0$write_1__VAL_1 or - WILL_FIRE_RL_wci_reqF_8_both or - MUX_wci_reqF_8_q_0$write_1__VAL_2 or WILL_FIRE_RL_wci_reqF_8_decCtr) + assign wci_14_reqPend$EN = + WILL_FIRE_RL_wci_14_wrkBusy && + wci_14_wciResponse$wget[33:32] != 2'd0 || + WILL_FIRE_RL_cpDispatch_F_F_T_E14_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_F_T_T ; + + // register wci_14_reqTO + assign wci_14_reqTO$D_IN = + MUX_wci_14_reqTO$write_1__SEL_1 ? + MUX_wci_14_reqTO$write_1__VAL_1 : + 3'd0 ; + assign wci_14_reqTO$EN = + WILL_FIRE_RL_wci_14_wrkBusy && + wci_14_wciResponse_wget__183_BITS_33_TO_32_184_ETC___d2212 || + WILL_FIRE_RL_cpDispatch_F_F_T_E14_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E14_F_F_T_T_T ; + + // register wci_14_respTimr + assign wci_14_respTimr$D_IN = + wci_14_reqF_cntr_r ? 32'd0 : MUX_wci_14_respTimr$write_1__VAL_2 ; + assign wci_14_respTimr$EN = + WILL_FIRE_RL_wci_14_wrkBusy || wci_14_reqF_cntr_r ; + + // register wci_14_respTimrAct + assign wci_14_respTimrAct$D_IN = wci_14_reqF_cntr_r ; + assign wci_14_respTimrAct$EN = + WILL_FIRE_RL_wci_14_wrkBusy && + (!wci_14_respTimr_188_ULT_1_SL_wci_14_wTimeout_1_ETC___d2191 || + wci_14_wciResponse$wget[33:32] != 2'd0) || + wci_14_reqF_cntr_r ; + + // register wci_14_sThreadBusy_d + assign wci_14_sThreadBusy_d$D_IN = wci_Vm_14_SThreadBusy ; + assign wci_14_sThreadBusy_d$EN = 1'd1 ; + + // register wci_14_sfCap + assign wci_14_sfCap$D_IN = wci_14_sfCapSet ; + assign wci_14_sfCap$EN = wci_14_sfCapSet || wci_14_sfCapClear ; + + // register wci_14_sfCapClear + assign wci_14_sfCapClear$D_IN = wci_14_sfCapClear_1$whas ; + assign wci_14_sfCapClear$EN = 1'd1 ; + + // register wci_14_sfCapSet + assign wci_14_sfCapSet$D_IN = wci_Vm_14_SFlag[0] ; + assign wci_14_sfCapSet$EN = 1'd1 ; + + // register wci_14_slvPresent + assign wci_14_slvPresent$D_IN = wci_Vm_14_SFlag[1] ; + assign wci_14_slvPresent$EN = 1'd1 ; + + // register wci_14_wReset_n + assign wci_14_wReset_n$D_IN = cpReq[59] ; + assign wci_14_wReset_n$EN = + WILL_FIRE_RL_cpDispatch_F_F_T_E14_F_F_T_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E14_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E14_F_F_T_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E14_F_F_T_T_T ; + + // register wci_14_wStatus + assign wci_14_wStatus$D_IN = + { 4'b0, + !wci_14_lastOpWrite[1] || wci_14_lastOpWrite[0], + IF_wci_14_lastControlOp_273_BIT_3_274_THEN_wci_ETC___d2288 } ; + assign wci_14_wStatus$EN = 1'd1 ; + + // register wci_14_wTimeout + assign wci_14_wTimeout$D_IN = cpReq[32:28] ; + assign wci_14_wTimeout$EN = + WILL_FIRE_RL_cpDispatch_F_F_T_E14_F_F_T_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E14_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E14_F_F_T_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E14_F_F_T_T_T ; + + // register wci_1_busy + assign wci_1_busy$D_IN = !MUX_wci_1_busy$write_1__SEL_1 ; + assign wci_1_busy$EN = + WILL_FIRE_RL_wci_1_wrkBusy && + (!wci_1_respTimr_68_ULT_1_SL_wci_1_wTimeout_69_70___d371 || + wci_1_wciResponse$wget[33:32] != 2'd0) || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E1_T_T ; + + // register wci_1_lastConfigAddr + assign wci_1_lastConfigAddr$D_IN = wci_0_lastConfigAddr$D_IN ; + assign wci_1_lastConfigAddr$EN = + WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E1_T_T ; + + // register wci_1_lastConfigBE + assign wci_1_lastConfigBE$D_IN = wci_0_lastConfigBE$D_IN ; + assign wci_1_lastConfigBE$EN = + WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E1_T_T ; + + // register wci_1_lastControlOp + assign wci_1_lastControlOp$D_IN = wci_0_lastControlOp$D_IN ; + assign wci_1_lastControlOp$EN = WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_T_T ; + + // register wci_1_lastOpWrite + assign wci_1_lastOpWrite$D_IN = + WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_T_T ? 2'd2 : 2'd3 ; + assign wci_1_lastOpWrite$EN = + WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E1_T_T ; + + // register wci_1_mFlagReg + assign wci_1_mFlagReg$D_IN = 2'h0 ; + assign wci_1_mFlagReg$EN = 1'b0 ; + + // register wci_1_pageWindow + assign wci_1_pageWindow$D_IN = cpReq[39:28] ; + assign wci_1_pageWindow$EN = WILL_FIRE_RL_cpDispatch_F_F_T_E1_F_F_F_T ; + + // register wci_1_reqERR + assign wci_1_reqERR$D_IN = + MUX_wci_1_reqERR$write_1__SEL_1 ? + MUX_wci_1_reqERR$write_1__VAL_1 : + 3'd0 ; + assign wci_1_reqERR$EN = + WILL_FIRE_RL_wci_1_wrkBusy && + wci_1_wciResponse$wget[33:32] == 2'd3 && + (wci_1_reqPend == 2'd1 || wci_1_reqPend == 2'd2 || + wci_1_reqPend == 2'd3) || + WILL_FIRE_RL_cpDispatch_F_F_T_E1_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E1_F_F_T_T_T ; + + // register wci_1_reqFAIL + assign wci_1_reqFAIL$D_IN = + MUX_wci_1_reqFAIL$write_1__SEL_1 ? + MUX_wci_1_reqFAIL$write_1__VAL_1 : + 3'd0 ; + assign wci_1_reqFAIL$EN = + WILL_FIRE_RL_wci_1_wrkBusy && + wci_1_wciResponse$wget[33:32] == 2'd2 && + (wci_1_reqPend == 2'd1 || wci_1_reqPend == 2'd2 || + wci_1_reqPend == 2'd3) || + WILL_FIRE_RL_cpDispatch_F_F_T_E1_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E1_F_F_T_T_T ; + + // register wci_1_reqF_cntr_r + assign wci_1_reqF_cntr_r$D_IN = + WILL_FIRE_RL_wci_1_reqF_incCtr ? + MUX_wci_1_reqF_cntr_r$write_1__VAL_1 : + MUX_wci_1_reqF_cntr_r$write_1__VAL_2 ; + assign wci_1_reqF_cntr_r$EN = + WILL_FIRE_RL_wci_1_reqF_incCtr || + WILL_FIRE_RL_wci_1_reqF_decCtr ; + + // register wci_1_reqF_q_0 + always@(WILL_FIRE_RL_wci_1_reqF_both or + MUX_wci_1_reqF_q_0$write_1__VAL_1 or + MUX_wci_1_reqF_q_0$write_1__SEL_2 or + MUX_wci_1_reqF_q_0$write_1__VAL_2 or WILL_FIRE_RL_wci_1_reqF_decCtr) begin case (1'b1) // synopsys parallel_case - MUX_wci_reqF_8_q_0$write_1__SEL_1: - wci_reqF_8_q_0$D_IN = MUX_wci_reqF_8_q_0$write_1__VAL_1; - WILL_FIRE_RL_wci_reqF_8_both: - wci_reqF_8_q_0$D_IN = MUX_wci_reqF_8_q_0$write_1__VAL_2; - WILL_FIRE_RL_wci_reqF_8_decCtr: - wci_reqF_8_q_0$D_IN = 72'h0000000000AAAAAAAA; - default: wci_reqF_8_q_0$D_IN = + WILL_FIRE_RL_wci_1_reqF_both: + wci_1_reqF_q_0$D_IN = MUX_wci_1_reqF_q_0$write_1__VAL_1; + MUX_wci_1_reqF_q_0$write_1__SEL_2: + wci_1_reqF_q_0$D_IN = MUX_wci_1_reqF_q_0$write_1__VAL_2; + WILL_FIRE_RL_wci_1_reqF_decCtr: + wci_1_reqF_q_0$D_IN = 72'h0000000000AAAAAAAA; + default: wci_1_reqF_q_0$D_IN = 72'hAAAAAAAAAAAAAAAAAA /* unspecified value */ ; endcase end - assign wci_reqF_8_q_0$EN = - WILL_FIRE_RL_wci_reqF_8_incCtr && !wci_reqF_8_c_r || - WILL_FIRE_RL_wci_reqF_8_both || - WILL_FIRE_RL_wci_reqF_8_decCtr ; - - // register wci_reqF_9_c_r - assign wci_reqF_9_c_r$D_IN = - WILL_FIRE_RL_wci_reqF_9_incCtr ? - MUX_wci_reqF_9_c_r$write_1__VAL_1 : - MUX_wci_reqF_9_c_r$write_1__VAL_2 ; - assign wci_reqF_9_c_r$EN = - WILL_FIRE_RL_wci_reqF_9_incCtr || - WILL_FIRE_RL_wci_reqF_9_decCtr ; - - // register wci_reqF_9_q_0 - always@(MUX_wci_reqF_9_q_0$write_1__SEL_1 or - MUX_wci_reqF_9_q_0$write_1__VAL_1 or - WILL_FIRE_RL_wci_reqF_9_both or - MUX_wci_reqF_9_q_0$write_1__VAL_2 or WILL_FIRE_RL_wci_reqF_9_decCtr) + assign wci_1_reqF_q_0$EN = + WILL_FIRE_RL_wci_1_reqF_both || + WILL_FIRE_RL_wci_1_reqF_incCtr && !wci_1_reqF_cntr_r || + WILL_FIRE_RL_wci_1_reqF_decCtr ; + + // register wci_1_reqPend + always@(MUX_wci_1_reqPend$write_1__SEL_1 or + WILL_FIRE_RL_cpDispatch_F_F_T_E1_T_T or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_T_T or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_T_T) begin case (1'b1) // synopsys parallel_case - MUX_wci_reqF_9_q_0$write_1__SEL_1: - wci_reqF_9_q_0$D_IN = MUX_wci_reqF_9_q_0$write_1__VAL_1; - WILL_FIRE_RL_wci_reqF_9_both: - wci_reqF_9_q_0$D_IN = MUX_wci_reqF_9_q_0$write_1__VAL_2; - WILL_FIRE_RL_wci_reqF_9_decCtr: - wci_reqF_9_q_0$D_IN = 72'h0000000000AAAAAAAA; - default: wci_reqF_9_q_0$D_IN = - 72'hAAAAAAAAAAAAAAAAAA /* unspecified value */ ; + MUX_wci_1_reqPend$write_1__SEL_1: wci_1_reqPend$D_IN = 2'd0; + WILL_FIRE_RL_cpDispatch_F_F_T_E1_T_T: wci_1_reqPend$D_IN = 2'd1; + WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_T_T: wci_1_reqPend$D_IN = 2'd2; + WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_T_T: wci_1_reqPend$D_IN = 2'd3; + default: wci_1_reqPend$D_IN = 2'b10 /* unspecified value */ ; endcase end - assign wci_reqF_9_q_0$EN = - WILL_FIRE_RL_wci_reqF_9_incCtr && !wci_reqF_9_c_r || - WILL_FIRE_RL_wci_reqF_9_both || - WILL_FIRE_RL_wci_reqF_9_decCtr ; - - // register wci_reqF_c_r - assign wci_reqF_c_r$D_IN = - WILL_FIRE_RL_wci_reqF_incCtr ? - MUX_wci_reqF_c_r$write_1__VAL_1 : - MUX_wci_reqF_c_r$write_1__VAL_2 ; - assign wci_reqF_c_r$EN = - WILL_FIRE_RL_wci_reqF_incCtr || WILL_FIRE_RL_wci_reqF_decCtr ; - - // register wci_reqF_q_0 - always@(WILL_FIRE_RL_wci_reqF_both or - MUX_wci_reqF_q_0$write_1__VAL_1 or - MUX_wci_reqF_q_0$write_1__SEL_2 or - MUX_wci_reqF_q_0$write_1__VAL_2 or WILL_FIRE_RL_wci_reqF_decCtr) + assign wci_1_reqPend$EN = + WILL_FIRE_RL_wci_1_wrkBusy && + wci_1_wciResponse$wget[33:32] != 2'd0 || + WILL_FIRE_RL_cpDispatch_F_F_T_E1_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_T_T ; + + // register wci_1_reqTO + assign wci_1_reqTO$D_IN = + MUX_wci_1_reqTO$write_1__SEL_1 ? + MUX_wci_1_reqTO$write_1__VAL_1 : + 3'd0 ; + assign wci_1_reqTO$EN = + WILL_FIRE_RL_wci_1_wrkBusy && + wci_1_wciResponse_wget__63_BITS_33_TO_32_64_EQ_ETC___d392 || + WILL_FIRE_RL_cpDispatch_F_F_T_E1_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E1_F_F_T_T_T ; + + // register wci_1_respTimr + assign wci_1_respTimr$D_IN = + wci_1_reqF_cntr_r ? 32'd0 : MUX_wci_1_respTimr$write_1__VAL_2 ; + assign wci_1_respTimr$EN = WILL_FIRE_RL_wci_1_wrkBusy || wci_1_reqF_cntr_r ; + + // register wci_1_respTimrAct + assign wci_1_respTimrAct$D_IN = wci_1_reqF_cntr_r ; + assign wci_1_respTimrAct$EN = + WILL_FIRE_RL_wci_1_wrkBusy && + (!wci_1_respTimr_68_ULT_1_SL_wci_1_wTimeout_69_70___d371 || + wci_1_wciResponse$wget[33:32] != 2'd0) || + wci_1_reqF_cntr_r ; + + // register wci_1_sThreadBusy_d + assign wci_1_sThreadBusy_d$D_IN = wci_Vm_1_SThreadBusy ; + assign wci_1_sThreadBusy_d$EN = 1'd1 ; + + // register wci_1_sfCap + assign wci_1_sfCap$D_IN = wci_1_sfCapSet ; + assign wci_1_sfCap$EN = wci_1_sfCapSet || wci_1_sfCapClear ; + + // register wci_1_sfCapClear + assign wci_1_sfCapClear$D_IN = wci_1_sfCapClear_1$whas ; + assign wci_1_sfCapClear$EN = 1'd1 ; + + // register wci_1_sfCapSet + assign wci_1_sfCapSet$D_IN = wci_Vm_1_SFlag[0] ; + assign wci_1_sfCapSet$EN = 1'd1 ; + + // register wci_1_slvPresent + assign wci_1_slvPresent$D_IN = wci_Vm_1_SFlag[1] ; + assign wci_1_slvPresent$EN = 1'd1 ; + + // register wci_1_wReset_n + assign wci_1_wReset_n$D_IN = cpReq[59] ; + assign wci_1_wReset_n$EN = + WILL_FIRE_RL_cpDispatch_F_F_T_E1_F_F_T_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E1_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E1_F_F_T_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E1_F_F_T_T_T ; + + // register wci_1_wStatus + assign wci_1_wStatus$D_IN = + { 4'b0, + !wci_1_lastOpWrite[1] || wci_1_lastOpWrite[0], + IF_wci_1_lastControlOp_53_BIT_3_54_THEN_wci_1__ETC___d468 } ; + assign wci_1_wStatus$EN = 1'd1 ; + + // register wci_1_wTimeout + assign wci_1_wTimeout$D_IN = cpReq[32:28] ; + assign wci_1_wTimeout$EN = + WILL_FIRE_RL_cpDispatch_F_F_T_E1_F_F_T_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E1_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E1_F_F_T_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E1_F_F_T_T_T ; + + // register wci_2_busy + assign wci_2_busy$D_IN = !MUX_wci_2_busy$write_1__SEL_1 ; + assign wci_2_busy$EN = + WILL_FIRE_RL_wci_2_wrkBusy && + (!wci_2_respTimr_08_ULT_1_SL_wci_2_wTimeout_09_10___d511 || + wci_2_wciResponse$wget[33:32] != 2'd0) || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_F_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E2_T_T ; + + // register wci_2_lastConfigAddr + assign wci_2_lastConfigAddr$D_IN = wci_0_lastConfigAddr$D_IN ; + assign wci_2_lastConfigAddr$EN = + WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E2_T_T ; + + // register wci_2_lastConfigBE + assign wci_2_lastConfigBE$D_IN = wci_0_lastConfigBE$D_IN ; + assign wci_2_lastConfigBE$EN = + WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E2_T_T ; + + // register wci_2_lastControlOp + assign wci_2_lastControlOp$D_IN = wci_0_lastControlOp$D_IN ; + assign wci_2_lastControlOp$EN = WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_F_T_T ; + + // register wci_2_lastOpWrite + assign wci_2_lastOpWrite$D_IN = + WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_T_T ? 2'd2 : 2'd3 ; + assign wci_2_lastOpWrite$EN = + WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E2_T_T ; + + // register wci_2_mFlagReg + assign wci_2_mFlagReg$D_IN = 2'h0 ; + assign wci_2_mFlagReg$EN = 1'b0 ; + + // register wci_2_pageWindow + assign wci_2_pageWindow$D_IN = cpReq[39:28] ; + assign wci_2_pageWindow$EN = WILL_FIRE_RL_cpDispatch_F_F_T_E2_F_F_F_T ; + + // register wci_2_reqERR + assign wci_2_reqERR$D_IN = + MUX_wci_2_reqERR$write_1__SEL_1 ? + MUX_wci_2_reqERR$write_1__VAL_1 : + 3'd0 ; + assign wci_2_reqERR$EN = + WILL_FIRE_RL_wci_2_wrkBusy && + wci_2_wciResponse$wget[33:32] == 2'd3 && + (wci_2_reqPend == 2'd1 || wci_2_reqPend == 2'd2 || + wci_2_reqPend == 2'd3) || + WILL_FIRE_RL_cpDispatch_F_F_T_E2_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E2_F_F_T_T_T ; + + // register wci_2_reqFAIL + assign wci_2_reqFAIL$D_IN = + MUX_wci_2_reqFAIL$write_1__SEL_1 ? + MUX_wci_2_reqFAIL$write_1__VAL_1 : + 3'd0 ; + assign wci_2_reqFAIL$EN = + WILL_FIRE_RL_wci_2_wrkBusy && + wci_2_wciResponse$wget[33:32] == 2'd2 && + (wci_2_reqPend == 2'd1 || wci_2_reqPend == 2'd2 || + wci_2_reqPend == 2'd3) || + WILL_FIRE_RL_cpDispatch_F_F_T_E2_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E2_F_F_T_T_T ; + + // register wci_2_reqF_cntr_r + assign wci_2_reqF_cntr_r$D_IN = + WILL_FIRE_RL_wci_2_reqF_incCtr ? + MUX_wci_2_reqF_cntr_r$write_1__VAL_1 : + MUX_wci_2_reqF_cntr_r$write_1__VAL_2 ; + assign wci_2_reqF_cntr_r$EN = + WILL_FIRE_RL_wci_2_reqF_incCtr || + WILL_FIRE_RL_wci_2_reqF_decCtr ; + + // register wci_2_reqF_q_0 + always@(WILL_FIRE_RL_wci_2_reqF_both or + MUX_wci_2_reqF_q_0$write_1__VAL_1 or + MUX_wci_2_reqF_q_0$write_1__SEL_2 or + MUX_wci_2_reqF_q_0$write_1__VAL_2 or WILL_FIRE_RL_wci_2_reqF_decCtr) begin case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_wci_reqF_both: - wci_reqF_q_0$D_IN = MUX_wci_reqF_q_0$write_1__VAL_1; - MUX_wci_reqF_q_0$write_1__SEL_2: - wci_reqF_q_0$D_IN = MUX_wci_reqF_q_0$write_1__VAL_2; - WILL_FIRE_RL_wci_reqF_decCtr: - wci_reqF_q_0$D_IN = 72'h0000000000AAAAAAAA; - default: wci_reqF_q_0$D_IN = + WILL_FIRE_RL_wci_2_reqF_both: + wci_2_reqF_q_0$D_IN = MUX_wci_2_reqF_q_0$write_1__VAL_1; + MUX_wci_2_reqF_q_0$write_1__SEL_2: + wci_2_reqF_q_0$D_IN = MUX_wci_2_reqF_q_0$write_1__VAL_2; + WILL_FIRE_RL_wci_2_reqF_decCtr: + wci_2_reqF_q_0$D_IN = 72'h0000000000AAAAAAAA; + default: wci_2_reqF_q_0$D_IN = 72'hAAAAAAAAAAAAAAAAAA /* unspecified value */ ; endcase end - assign wci_reqF_q_0$EN = - WILL_FIRE_RL_wci_reqF_both || - WILL_FIRE_RL_wci_reqF_incCtr && !wci_reqF_c_r || - WILL_FIRE_RL_wci_reqF_decCtr ; - - // register wci_reqPend - always@(MUX_wci_reqPend$write_1__SEL_1 or - WILL_FIRE_RL_cpDispatch_F_F_T_T_T_T or - WILL_FIRE_RL_cpDispatch_F_F_F_F_T_T_T or - WILL_FIRE_RL_cpDispatch_F_F_F_F_T_F_T_T) + assign wci_2_reqF_q_0$EN = + WILL_FIRE_RL_wci_2_reqF_both || + WILL_FIRE_RL_wci_2_reqF_incCtr && !wci_2_reqF_cntr_r || + WILL_FIRE_RL_wci_2_reqF_decCtr ; + + // register wci_2_reqPend + always@(MUX_wci_2_reqPend$write_1__SEL_1 or + WILL_FIRE_RL_cpDispatch_F_F_T_E2_T_T or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_T_T or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_F_T_T) begin case (1'b1) // synopsys parallel_case - MUX_wci_reqPend$write_1__SEL_1: wci_reqPend$D_IN = 2'd0; - WILL_FIRE_RL_cpDispatch_F_F_T_T_T_T: wci_reqPend$D_IN = 2'd1; - WILL_FIRE_RL_cpDispatch_F_F_F_F_T_T_T: wci_reqPend$D_IN = 2'd2; - WILL_FIRE_RL_cpDispatch_F_F_F_F_T_F_T_T: wci_reqPend$D_IN = 2'd3; - default: wci_reqPend$D_IN = 2'b10 /* unspecified value */ ; + MUX_wci_2_reqPend$write_1__SEL_1: wci_2_reqPend$D_IN = 2'd0; + WILL_FIRE_RL_cpDispatch_F_F_T_E2_T_T: wci_2_reqPend$D_IN = 2'd1; + WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_T_T: wci_2_reqPend$D_IN = 2'd2; + WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_F_T_T: wci_2_reqPend$D_IN = 2'd3; + default: wci_2_reqPend$D_IN = 2'b10 /* unspecified value */ ; endcase end - assign wci_reqPend$EN = - WILL_FIRE_RL_wci_wrkBusy && - wci_wciResponse$wget[33:32] != 2'd0 || - WILL_FIRE_RL_cpDispatch_F_F_T_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_T_F_T_T ; - - // register wci_reqPend_1 - always@(MUX_wci_reqPend_1$write_1__SEL_1 or - WILL_FIRE_RL_cpDispatch_F_F_T_F_T_T_T or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_T_T or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_F_T_T) + assign wci_2_reqPend$EN = + WILL_FIRE_RL_wci_2_wrkBusy && + wci_2_wciResponse$wget[33:32] != 2'd0 || + WILL_FIRE_RL_cpDispatch_F_F_T_E2_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_F_T_T ; + + // register wci_2_reqTO + assign wci_2_reqTO$D_IN = + MUX_wci_2_reqTO$write_1__SEL_1 ? + MUX_wci_2_reqTO$write_1__VAL_1 : + 3'd0 ; + assign wci_2_reqTO$EN = + WILL_FIRE_RL_wci_2_wrkBusy && + wci_2_wciResponse_wget__03_BITS_33_TO_32_04_EQ_ETC___d532 || + WILL_FIRE_RL_cpDispatch_F_F_T_E2_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E2_F_F_T_T_T ; + + // register wci_2_respTimr + assign wci_2_respTimr$D_IN = + wci_2_reqF_cntr_r ? 32'd0 : MUX_wci_2_respTimr$write_1__VAL_2 ; + assign wci_2_respTimr$EN = WILL_FIRE_RL_wci_2_wrkBusy || wci_2_reqF_cntr_r ; + + // register wci_2_respTimrAct + assign wci_2_respTimrAct$D_IN = wci_2_reqF_cntr_r ; + assign wci_2_respTimrAct$EN = + WILL_FIRE_RL_wci_2_wrkBusy && + (!wci_2_respTimr_08_ULT_1_SL_wci_2_wTimeout_09_10___d511 || + wci_2_wciResponse$wget[33:32] != 2'd0) || + wci_2_reqF_cntr_r ; + + // register wci_2_sThreadBusy_d + assign wci_2_sThreadBusy_d$D_IN = wci_Vm_2_SThreadBusy ; + assign wci_2_sThreadBusy_d$EN = 1'd1 ; + + // register wci_2_sfCap + assign wci_2_sfCap$D_IN = wci_2_sfCapSet ; + assign wci_2_sfCap$EN = wci_2_sfCapSet || wci_2_sfCapClear ; + + // register wci_2_sfCapClear + assign wci_2_sfCapClear$D_IN = wci_2_sfCapClear_1$whas ; + assign wci_2_sfCapClear$EN = 1'd1 ; + + // register wci_2_sfCapSet + assign wci_2_sfCapSet$D_IN = wci_Vm_2_SFlag[0] ; + assign wci_2_sfCapSet$EN = 1'd1 ; + + // register wci_2_slvPresent + assign wci_2_slvPresent$D_IN = wci_Vm_2_SFlag[1] ; + assign wci_2_slvPresent$EN = 1'd1 ; + + // register wci_2_wReset_n + assign wci_2_wReset_n$D_IN = cpReq[59] ; + assign wci_2_wReset_n$EN = + WILL_FIRE_RL_cpDispatch_F_F_T_E2_F_F_T_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E2_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E2_F_F_T_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E2_F_F_T_T_T ; + + // register wci_2_wStatus + assign wci_2_wStatus$D_IN = + { 4'b0, + !wci_2_lastOpWrite[1] || wci_2_lastOpWrite[0], + IF_wci_2_lastControlOp_93_BIT_3_94_THEN_wci_2__ETC___d608 } ; + assign wci_2_wStatus$EN = 1'd1 ; + + // register wci_2_wTimeout + assign wci_2_wTimeout$D_IN = cpReq[32:28] ; + assign wci_2_wTimeout$EN = + WILL_FIRE_RL_cpDispatch_F_F_T_E2_F_F_T_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E2_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E2_F_F_T_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E2_F_F_T_T_T ; + + // register wci_3_busy + assign wci_3_busy$D_IN = !MUX_wci_3_busy$write_1__SEL_1 ; + assign wci_3_busy$EN = + WILL_FIRE_RL_wci_3_wrkBusy && + (!wci_3_respTimr_48_ULT_1_SL_wci_3_wTimeout_49_50___d651 || + wci_3_wciResponse$wget[33:32] != 2'd0) || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_F_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E3_T_T ; + + // register wci_3_lastConfigAddr + assign wci_3_lastConfigAddr$D_IN = wci_0_lastConfigAddr$D_IN ; + assign wci_3_lastConfigAddr$EN = + WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E3_T_T ; + + // register wci_3_lastConfigBE + assign wci_3_lastConfigBE$D_IN = wci_0_lastConfigBE$D_IN ; + assign wci_3_lastConfigBE$EN = + WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E3_T_T ; + + // register wci_3_lastControlOp + assign wci_3_lastControlOp$D_IN = wci_0_lastControlOp$D_IN ; + assign wci_3_lastControlOp$EN = WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_F_T_T ; + + // register wci_3_lastOpWrite + assign wci_3_lastOpWrite$D_IN = + WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_T_T ? 2'd2 : 2'd3 ; + assign wci_3_lastOpWrite$EN = + WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E3_T_T ; + + // register wci_3_mFlagReg + assign wci_3_mFlagReg$D_IN = 2'h0 ; + assign wci_3_mFlagReg$EN = 1'b0 ; + + // register wci_3_pageWindow + assign wci_3_pageWindow$D_IN = cpReq[39:28] ; + assign wci_3_pageWindow$EN = WILL_FIRE_RL_cpDispatch_F_F_T_E3_F_F_F_T ; + + // register wci_3_reqERR + assign wci_3_reqERR$D_IN = + MUX_wci_3_reqERR$write_1__SEL_1 ? + MUX_wci_3_reqERR$write_1__VAL_1 : + 3'd0 ; + assign wci_3_reqERR$EN = + WILL_FIRE_RL_wci_3_wrkBusy && + wci_3_wciResponse$wget[33:32] == 2'd3 && + (wci_3_reqPend == 2'd1 || wci_3_reqPend == 2'd2 || + wci_3_reqPend == 2'd3) || + WILL_FIRE_RL_cpDispatch_F_F_T_E3_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E3_F_F_T_T_T ; + + // register wci_3_reqFAIL + assign wci_3_reqFAIL$D_IN = + MUX_wci_3_reqFAIL$write_1__SEL_1 ? + MUX_wci_3_reqFAIL$write_1__VAL_1 : + 3'd0 ; + assign wci_3_reqFAIL$EN = + WILL_FIRE_RL_wci_3_wrkBusy && + wci_3_wciResponse$wget[33:32] == 2'd2 && + (wci_3_reqPend == 2'd1 || wci_3_reqPend == 2'd2 || + wci_3_reqPend == 2'd3) || + WILL_FIRE_RL_cpDispatch_F_F_T_E3_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E3_F_F_T_T_T ; + + // register wci_3_reqF_cntr_r + assign wci_3_reqF_cntr_r$D_IN = + WILL_FIRE_RL_wci_3_reqF_incCtr ? + MUX_wci_3_reqF_cntr_r$write_1__VAL_1 : + MUX_wci_3_reqF_cntr_r$write_1__VAL_2 ; + assign wci_3_reqF_cntr_r$EN = + WILL_FIRE_RL_wci_3_reqF_incCtr || + WILL_FIRE_RL_wci_3_reqF_decCtr ; + + // register wci_3_reqF_q_0 + always@(WILL_FIRE_RL_wci_3_reqF_both or + MUX_wci_3_reqF_q_0$write_1__VAL_1 or + MUX_wci_3_reqF_q_0$write_1__SEL_2 or + MUX_wci_3_reqF_q_0$write_1__VAL_2 or WILL_FIRE_RL_wci_3_reqF_decCtr) begin case (1'b1) // synopsys parallel_case - MUX_wci_reqPend_1$write_1__SEL_1: wci_reqPend_1$D_IN = 2'd0; - WILL_FIRE_RL_cpDispatch_F_F_T_F_T_T_T: wci_reqPend_1$D_IN = 2'd1; - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_T_T: wci_reqPend_1$D_IN = 2'd2; - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_F_T_T: wci_reqPend_1$D_IN = 2'd3; - default: wci_reqPend_1$D_IN = 2'b10 /* unspecified value */ ; + WILL_FIRE_RL_wci_3_reqF_both: + wci_3_reqF_q_0$D_IN = MUX_wci_3_reqF_q_0$write_1__VAL_1; + MUX_wci_3_reqF_q_0$write_1__SEL_2: + wci_3_reqF_q_0$D_IN = MUX_wci_3_reqF_q_0$write_1__VAL_2; + WILL_FIRE_RL_wci_3_reqF_decCtr: + wci_3_reqF_q_0$D_IN = 72'h0000000000AAAAAAAA; + default: wci_3_reqF_q_0$D_IN = + 72'hAAAAAAAAAAAAAAAAAA /* unspecified value */ ; endcase end - assign wci_reqPend_1$EN = - WILL_FIRE_RL_wci_wrkBusy_1 && - wci_wciResponse_1$wget[33:32] != 2'd0 || - WILL_FIRE_RL_cpDispatch_F_F_T_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_F_T_T ; - - // register wci_reqPend_10 - always@(MUX_wci_reqPend_10$write_1__SEL_1 or - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_T_T or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T) + assign wci_3_reqF_q_0$EN = + WILL_FIRE_RL_wci_3_reqF_both || + WILL_FIRE_RL_wci_3_reqF_incCtr && !wci_3_reqF_cntr_r || + WILL_FIRE_RL_wci_3_reqF_decCtr ; + + // register wci_3_reqPend + always@(MUX_wci_3_reqPend$write_1__SEL_1 or + WILL_FIRE_RL_cpDispatch_F_F_T_E3_T_T or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_T_T or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_F_T_T) begin case (1'b1) // synopsys parallel_case - MUX_wci_reqPend_10$write_1__SEL_1: wci_reqPend_10$D_IN = 2'd0; - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_T_T: - wci_reqPend_10$D_IN = 2'd1; - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T: - wci_reqPend_10$D_IN = 2'd2; - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T: - wci_reqPend_10$D_IN = 2'd3; - default: wci_reqPend_10$D_IN = 2'b10 /* unspecified value */ ; + MUX_wci_3_reqPend$write_1__SEL_1: wci_3_reqPend$D_IN = 2'd0; + WILL_FIRE_RL_cpDispatch_F_F_T_E3_T_T: wci_3_reqPend$D_IN = 2'd1; + WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_T_T: wci_3_reqPend$D_IN = 2'd2; + WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_F_T_T: wci_3_reqPend$D_IN = 2'd3; + default: wci_3_reqPend$D_IN = 2'b10 /* unspecified value */ ; endcase end - assign wci_reqPend_10$EN = - WILL_FIRE_RL_wci_wrkBusy_10 && - wci_wciResponse_10$wget[33:32] != 2'd0 || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T ; - - // register wci_reqPend_11 - always@(MUX_wci_reqPend_11$write_1__SEL_1 or - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_T_T or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T) + assign wci_3_reqPend$EN = + WILL_FIRE_RL_wci_3_wrkBusy && + wci_3_wciResponse$wget[33:32] != 2'd0 || + WILL_FIRE_RL_cpDispatch_F_F_T_E3_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_F_T_T ; + + // register wci_3_reqTO + assign wci_3_reqTO$D_IN = + MUX_wci_3_reqTO$write_1__SEL_1 ? + MUX_wci_3_reqTO$write_1__VAL_1 : + 3'd0 ; + assign wci_3_reqTO$EN = + WILL_FIRE_RL_wci_3_wrkBusy && + wci_3_wciResponse_wget__43_BITS_33_TO_32_44_EQ_ETC___d672 || + WILL_FIRE_RL_cpDispatch_F_F_T_E3_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E3_F_F_T_T_T ; + + // register wci_3_respTimr + assign wci_3_respTimr$D_IN = + wci_3_reqF_cntr_r ? 32'd0 : MUX_wci_3_respTimr$write_1__VAL_2 ; + assign wci_3_respTimr$EN = WILL_FIRE_RL_wci_3_wrkBusy || wci_3_reqF_cntr_r ; + + // register wci_3_respTimrAct + assign wci_3_respTimrAct$D_IN = wci_3_reqF_cntr_r ; + assign wci_3_respTimrAct$EN = + WILL_FIRE_RL_wci_3_wrkBusy && + (!wci_3_respTimr_48_ULT_1_SL_wci_3_wTimeout_49_50___d651 || + wci_3_wciResponse$wget[33:32] != 2'd0) || + wci_3_reqF_cntr_r ; + + // register wci_3_sThreadBusy_d + assign wci_3_sThreadBusy_d$D_IN = wci_Vm_3_SThreadBusy ; + assign wci_3_sThreadBusy_d$EN = 1'd1 ; + + // register wci_3_sfCap + assign wci_3_sfCap$D_IN = wci_3_sfCapSet ; + assign wci_3_sfCap$EN = wci_3_sfCapSet || wci_3_sfCapClear ; + + // register wci_3_sfCapClear + assign wci_3_sfCapClear$D_IN = wci_3_sfCapClear_1$whas ; + assign wci_3_sfCapClear$EN = 1'd1 ; + + // register wci_3_sfCapSet + assign wci_3_sfCapSet$D_IN = wci_Vm_3_SFlag[0] ; + assign wci_3_sfCapSet$EN = 1'd1 ; + + // register wci_3_slvPresent + assign wci_3_slvPresent$D_IN = wci_Vm_3_SFlag[1] ; + assign wci_3_slvPresent$EN = 1'd1 ; + + // register wci_3_wReset_n + assign wci_3_wReset_n$D_IN = cpReq[59] ; + assign wci_3_wReset_n$EN = + WILL_FIRE_RL_cpDispatch_F_F_T_E3_F_F_T_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E3_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E3_F_F_T_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E3_F_F_T_T_T ; + + // register wci_3_wStatus + assign wci_3_wStatus$D_IN = + { 4'b0, + !wci_3_lastOpWrite[1] || wci_3_lastOpWrite[0], + IF_wci_3_lastControlOp_33_BIT_3_34_THEN_wci_3__ETC___d748 } ; + assign wci_3_wStatus$EN = 1'd1 ; + + // register wci_3_wTimeout + assign wci_3_wTimeout$D_IN = cpReq[32:28] ; + assign wci_3_wTimeout$EN = + WILL_FIRE_RL_cpDispatch_F_F_T_E3_F_F_T_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E3_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E3_F_F_T_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E3_F_F_T_T_T ; + + // register wci_4_busy + assign wci_4_busy$D_IN = !MUX_wci_4_busy$write_1__SEL_1 ; + assign wci_4_busy$EN = + WILL_FIRE_RL_wci_4_wrkBusy && + (!wci_4_respTimr_88_ULT_1_SL_wci_4_wTimeout_89_90___d791 || + wci_4_wciResponse$wget[33:32] != 2'd0) || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_F_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E4_T_T ; + + // register wci_4_lastConfigAddr + assign wci_4_lastConfigAddr$D_IN = wci_0_lastConfigAddr$D_IN ; + assign wci_4_lastConfigAddr$EN = + WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E4_T_T ; + + // register wci_4_lastConfigBE + assign wci_4_lastConfigBE$D_IN = wci_0_lastConfigBE$D_IN ; + assign wci_4_lastConfigBE$EN = + WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E4_T_T ; + + // register wci_4_lastControlOp + assign wci_4_lastControlOp$D_IN = wci_0_lastControlOp$D_IN ; + assign wci_4_lastControlOp$EN = WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_F_T_T ; + + // register wci_4_lastOpWrite + assign wci_4_lastOpWrite$D_IN = + WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_T_T ? 2'd2 : 2'd3 ; + assign wci_4_lastOpWrite$EN = + WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E4_T_T ; + + // register wci_4_mFlagReg + assign wci_4_mFlagReg$D_IN = 2'h0 ; + assign wci_4_mFlagReg$EN = 1'b0 ; + + // register wci_4_pageWindow + assign wci_4_pageWindow$D_IN = cpReq[39:28] ; + assign wci_4_pageWindow$EN = WILL_FIRE_RL_cpDispatch_F_F_T_E4_F_F_F_T ; + + // register wci_4_reqERR + assign wci_4_reqERR$D_IN = + MUX_wci_4_reqERR$write_1__SEL_1 ? + MUX_wci_4_reqERR$write_1__VAL_1 : + 3'd0 ; + assign wci_4_reqERR$EN = + WILL_FIRE_RL_wci_4_wrkBusy && + wci_4_wciResponse$wget[33:32] == 2'd3 && + (wci_4_reqPend == 2'd1 || wci_4_reqPend == 2'd2 || + wci_4_reqPend == 2'd3) || + WILL_FIRE_RL_cpDispatch_F_F_T_E4_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E4_F_F_T_T_T ; + + // register wci_4_reqFAIL + assign wci_4_reqFAIL$D_IN = + MUX_wci_4_reqFAIL$write_1__SEL_1 ? + MUX_wci_4_reqFAIL$write_1__VAL_1 : + 3'd0 ; + assign wci_4_reqFAIL$EN = + WILL_FIRE_RL_wci_4_wrkBusy && + wci_4_wciResponse$wget[33:32] == 2'd2 && + (wci_4_reqPend == 2'd1 || wci_4_reqPend == 2'd2 || + wci_4_reqPend == 2'd3) || + WILL_FIRE_RL_cpDispatch_F_F_T_E4_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E4_F_F_T_T_T ; + + // register wci_4_reqF_cntr_r + assign wci_4_reqF_cntr_r$D_IN = + WILL_FIRE_RL_wci_4_reqF_incCtr ? + MUX_wci_4_reqF_cntr_r$write_1__VAL_1 : + MUX_wci_4_reqF_cntr_r$write_1__VAL_2 ; + assign wci_4_reqF_cntr_r$EN = + WILL_FIRE_RL_wci_4_reqF_incCtr || + WILL_FIRE_RL_wci_4_reqF_decCtr ; + + // register wci_4_reqF_q_0 + always@(WILL_FIRE_RL_wci_4_reqF_both or + MUX_wci_4_reqF_q_0$write_1__VAL_1 or + MUX_wci_4_reqF_q_0$write_1__SEL_2 or + MUX_wci_4_reqF_q_0$write_1__VAL_2 or WILL_FIRE_RL_wci_4_reqF_decCtr) begin case (1'b1) // synopsys parallel_case - MUX_wci_reqPend_11$write_1__SEL_1: wci_reqPend_11$D_IN = 2'd0; - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_T_T: - wci_reqPend_11$D_IN = 2'd1; - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T: - wci_reqPend_11$D_IN = 2'd2; - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T: - wci_reqPend_11$D_IN = 2'd3; - default: wci_reqPend_11$D_IN = 2'b10 /* unspecified value */ ; + WILL_FIRE_RL_wci_4_reqF_both: + wci_4_reqF_q_0$D_IN = MUX_wci_4_reqF_q_0$write_1__VAL_1; + MUX_wci_4_reqF_q_0$write_1__SEL_2: + wci_4_reqF_q_0$D_IN = MUX_wci_4_reqF_q_0$write_1__VAL_2; + WILL_FIRE_RL_wci_4_reqF_decCtr: + wci_4_reqF_q_0$D_IN = 72'h0000000000AAAAAAAA; + default: wci_4_reqF_q_0$D_IN = + 72'hAAAAAAAAAAAAAAAAAA /* unspecified value */ ; endcase end - assign wci_reqPend_11$EN = - WILL_FIRE_RL_wci_wrkBusy_11 && - wci_wciResponse_11$wget[33:32] != 2'd0 || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T ; - - // register wci_reqPend_12 - always@(MUX_wci_reqPend_12$write_1__SEL_1 or - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T) + assign wci_4_reqF_q_0$EN = + WILL_FIRE_RL_wci_4_reqF_both || + WILL_FIRE_RL_wci_4_reqF_incCtr && !wci_4_reqF_cntr_r || + WILL_FIRE_RL_wci_4_reqF_decCtr ; + + // register wci_4_reqPend + always@(MUX_wci_4_reqPend$write_1__SEL_1 or + WILL_FIRE_RL_cpDispatch_F_F_T_E4_T_T or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_T_T or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_F_T_T) begin case (1'b1) // synopsys parallel_case - MUX_wci_reqPend_12$write_1__SEL_1: wci_reqPend_12$D_IN = 2'd0; - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T: - wci_reqPend_12$D_IN = 2'd1; - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T: - wci_reqPend_12$D_IN = 2'd2; - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T: - wci_reqPend_12$D_IN = 2'd3; - default: wci_reqPend_12$D_IN = 2'b10 /* unspecified value */ ; + MUX_wci_4_reqPend$write_1__SEL_1: wci_4_reqPend$D_IN = 2'd0; + WILL_FIRE_RL_cpDispatch_F_F_T_E4_T_T: wci_4_reqPend$D_IN = 2'd1; + WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_T_T: wci_4_reqPend$D_IN = 2'd2; + WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_F_T_T: wci_4_reqPend$D_IN = 2'd3; + default: wci_4_reqPend$D_IN = 2'b10 /* unspecified value */ ; endcase end - assign wci_reqPend_12$EN = - WILL_FIRE_RL_wci_wrkBusy_12 && - wci_wciResponse_12$wget[33:32] != 2'd0 || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T ; - - // register wci_reqPend_13 - always@(MUX_wci_reqPend_13$write_1__SEL_1 or - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T) + assign wci_4_reqPend$EN = + WILL_FIRE_RL_wci_4_wrkBusy && + wci_4_wciResponse$wget[33:32] != 2'd0 || + WILL_FIRE_RL_cpDispatch_F_F_T_E4_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_F_T_T ; + + // register wci_4_reqTO + assign wci_4_reqTO$D_IN = + MUX_wci_4_reqTO$write_1__SEL_1 ? + MUX_wci_4_reqTO$write_1__VAL_1 : + 3'd0 ; + assign wci_4_reqTO$EN = + WILL_FIRE_RL_wci_4_wrkBusy && + wci_4_wciResponse_wget__83_BITS_33_TO_32_84_EQ_ETC___d812 || + WILL_FIRE_RL_cpDispatch_F_F_T_E4_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E4_F_F_T_T_T ; + + // register wci_4_respTimr + assign wci_4_respTimr$D_IN = + wci_4_reqF_cntr_r ? 32'd0 : MUX_wci_4_respTimr$write_1__VAL_2 ; + assign wci_4_respTimr$EN = WILL_FIRE_RL_wci_4_wrkBusy || wci_4_reqF_cntr_r ; + + // register wci_4_respTimrAct + assign wci_4_respTimrAct$D_IN = wci_4_reqF_cntr_r ; + assign wci_4_respTimrAct$EN = + WILL_FIRE_RL_wci_4_wrkBusy && + (!wci_4_respTimr_88_ULT_1_SL_wci_4_wTimeout_89_90___d791 || + wci_4_wciResponse$wget[33:32] != 2'd0) || + wci_4_reqF_cntr_r ; + + // register wci_4_sThreadBusy_d + assign wci_4_sThreadBusy_d$D_IN = wci_Vm_4_SThreadBusy ; + assign wci_4_sThreadBusy_d$EN = 1'd1 ; + + // register wci_4_sfCap + assign wci_4_sfCap$D_IN = wci_4_sfCapSet ; + assign wci_4_sfCap$EN = wci_4_sfCapSet || wci_4_sfCapClear ; + + // register wci_4_sfCapClear + assign wci_4_sfCapClear$D_IN = wci_4_sfCapClear_1$whas ; + assign wci_4_sfCapClear$EN = 1'd1 ; + + // register wci_4_sfCapSet + assign wci_4_sfCapSet$D_IN = wci_Vm_4_SFlag[0] ; + assign wci_4_sfCapSet$EN = 1'd1 ; + + // register wci_4_slvPresent + assign wci_4_slvPresent$D_IN = wci_Vm_4_SFlag[1] ; + assign wci_4_slvPresent$EN = 1'd1 ; + + // register wci_4_wReset_n + assign wci_4_wReset_n$D_IN = cpReq[59] ; + assign wci_4_wReset_n$EN = + WILL_FIRE_RL_cpDispatch_F_F_T_E4_F_F_T_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E4_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E4_F_F_T_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E4_F_F_T_T_T ; + + // register wci_4_wStatus + assign wci_4_wStatus$D_IN = + { 4'b0, + !wci_4_lastOpWrite[1] || wci_4_lastOpWrite[0], + IF_wci_4_lastControlOp_73_BIT_3_74_THEN_wci_4__ETC___d888 } ; + assign wci_4_wStatus$EN = 1'd1 ; + + // register wci_4_wTimeout + assign wci_4_wTimeout$D_IN = cpReq[32:28] ; + assign wci_4_wTimeout$EN = + WILL_FIRE_RL_cpDispatch_F_F_T_E4_F_F_T_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E4_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E4_F_F_T_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E4_F_F_T_T_T ; + + // register wci_5_busy + assign wci_5_busy$D_IN = !MUX_wci_5_busy$write_1__SEL_1 ; + assign wci_5_busy$EN = + WILL_FIRE_RL_wci_5_wrkBusy && + (!wci_5_respTimr_28_ULT_1_SL_wci_5_wTimeout_29_30___d931 || + wci_5_wciResponse$wget[33:32] != 2'd0) || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E5_T_T ; + + // register wci_5_lastConfigAddr + assign wci_5_lastConfigAddr$D_IN = wci_0_lastConfigAddr$D_IN ; + assign wci_5_lastConfigAddr$EN = + WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E5_T_T ; + + // register wci_5_lastConfigBE + assign wci_5_lastConfigBE$D_IN = wci_0_lastConfigBE$D_IN ; + assign wci_5_lastConfigBE$EN = + WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E5_T_T ; + + // register wci_5_lastControlOp + assign wci_5_lastControlOp$D_IN = wci_0_lastControlOp$D_IN ; + assign wci_5_lastControlOp$EN = WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_T_T ; + + // register wci_5_lastOpWrite + assign wci_5_lastOpWrite$D_IN = + WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_T_T ? 2'd2 : 2'd3 ; + assign wci_5_lastOpWrite$EN = + WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E5_T_T ; + + // register wci_5_mFlagReg + assign wci_5_mFlagReg$D_IN = 2'h0 ; + assign wci_5_mFlagReg$EN = 1'b0 ; + + // register wci_5_pageWindow + assign wci_5_pageWindow$D_IN = cpReq[39:28] ; + assign wci_5_pageWindow$EN = WILL_FIRE_RL_cpDispatch_F_F_T_E5_F_F_F_T ; + + // register wci_5_reqERR + assign wci_5_reqERR$D_IN = + MUX_wci_5_reqERR$write_1__SEL_1 ? + MUX_wci_5_reqERR$write_1__VAL_1 : + 3'd0 ; + assign wci_5_reqERR$EN = + WILL_FIRE_RL_wci_5_wrkBusy && + wci_5_wciResponse$wget[33:32] == 2'd3 && + (wci_5_reqPend == 2'd1 || wci_5_reqPend == 2'd2 || + wci_5_reqPend == 2'd3) || + WILL_FIRE_RL_cpDispatch_F_F_T_E5_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E5_F_F_T_T_T ; + + // register wci_5_reqFAIL + assign wci_5_reqFAIL$D_IN = + MUX_wci_5_reqFAIL$write_1__SEL_1 ? + MUX_wci_5_reqFAIL$write_1__VAL_1 : + 3'd0 ; + assign wci_5_reqFAIL$EN = + WILL_FIRE_RL_wci_5_wrkBusy && + wci_5_wciResponse$wget[33:32] == 2'd2 && + (wci_5_reqPend == 2'd1 || wci_5_reqPend == 2'd2 || + wci_5_reqPend == 2'd3) || + WILL_FIRE_RL_cpDispatch_F_F_T_E5_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E5_F_F_T_T_T ; + + // register wci_5_reqF_cntr_r + assign wci_5_reqF_cntr_r$D_IN = + WILL_FIRE_RL_wci_5_reqF_incCtr ? + MUX_wci_5_reqF_cntr_r$write_1__VAL_1 : + MUX_wci_5_reqF_cntr_r$write_1__VAL_2 ; + assign wci_5_reqF_cntr_r$EN = + WILL_FIRE_RL_wci_5_reqF_incCtr || + WILL_FIRE_RL_wci_5_reqF_decCtr ; + + // register wci_5_reqF_q_0 + always@(WILL_FIRE_RL_wci_5_reqF_both or + MUX_wci_5_reqF_q_0$write_1__VAL_1 or + MUX_wci_5_reqF_q_0$write_1__SEL_2 or + MUX_wci_5_reqF_q_0$write_1__VAL_2 or WILL_FIRE_RL_wci_5_reqF_decCtr) begin case (1'b1) // synopsys parallel_case - MUX_wci_reqPend_13$write_1__SEL_1: wci_reqPend_13$D_IN = 2'd0; - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T: - wci_reqPend_13$D_IN = 2'd1; - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T: - wci_reqPend_13$D_IN = 2'd2; - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T: - wci_reqPend_13$D_IN = 2'd3; - default: wci_reqPend_13$D_IN = 2'b10 /* unspecified value */ ; + WILL_FIRE_RL_wci_5_reqF_both: + wci_5_reqF_q_0$D_IN = MUX_wci_5_reqF_q_0$write_1__VAL_1; + MUX_wci_5_reqF_q_0$write_1__SEL_2: + wci_5_reqF_q_0$D_IN = MUX_wci_5_reqF_q_0$write_1__VAL_2; + WILL_FIRE_RL_wci_5_reqF_decCtr: + wci_5_reqF_q_0$D_IN = 72'h0000000000AAAAAAAA; + default: wci_5_reqF_q_0$D_IN = + 72'hAAAAAAAAAAAAAAAAAA /* unspecified value */ ; endcase end - assign wci_reqPend_13$EN = - WILL_FIRE_RL_wci_wrkBusy_13 && - wci_wciResponse_13$wget[33:32] != 2'd0 || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T ; - - // register wci_reqPend_14 - always@(MUX_wci_reqPend_14$write_1__SEL_1 or - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T) + assign wci_5_reqF_q_0$EN = + WILL_FIRE_RL_wci_5_reqF_both || + WILL_FIRE_RL_wci_5_reqF_incCtr && !wci_5_reqF_cntr_r || + WILL_FIRE_RL_wci_5_reqF_decCtr ; + + // register wci_5_reqPend + always@(MUX_wci_5_reqPend$write_1__SEL_1 or + WILL_FIRE_RL_cpDispatch_F_F_T_E5_T_T or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_T_T or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_T_T) begin case (1'b1) // synopsys parallel_case - MUX_wci_reqPend_14$write_1__SEL_1: wci_reqPend_14$D_IN = 2'd0; - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T: - wci_reqPend_14$D_IN = 2'd1; - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T: - wci_reqPend_14$D_IN = 2'd2; - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T: - wci_reqPend_14$D_IN = 2'd3; - default: wci_reqPend_14$D_IN = 2'b10 /* unspecified value */ ; + MUX_wci_5_reqPend$write_1__SEL_1: wci_5_reqPend$D_IN = 2'd0; + WILL_FIRE_RL_cpDispatch_F_F_T_E5_T_T: wci_5_reqPend$D_IN = 2'd1; + WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_T_T: wci_5_reqPend$D_IN = 2'd2; + WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_T_T: wci_5_reqPend$D_IN = 2'd3; + default: wci_5_reqPend$D_IN = 2'b10 /* unspecified value */ ; endcase end - assign wci_reqPend_14$EN = - WILL_FIRE_RL_wci_wrkBusy_14 && - wci_wciResponse_14$wget[33:32] != 2'd0 || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T ; - - // register wci_reqPend_2 - always@(MUX_wci_reqPend_2$write_1__SEL_1 or - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_T_T or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_T_T or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_F_T_T) + assign wci_5_reqPend$EN = + WILL_FIRE_RL_wci_5_wrkBusy && + wci_5_wciResponse$wget[33:32] != 2'd0 || + WILL_FIRE_RL_cpDispatch_F_F_T_E5_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_T_T ; + + // register wci_5_reqTO + assign wci_5_reqTO$D_IN = + MUX_wci_5_reqTO$write_1__SEL_1 ? + MUX_wci_5_reqTO$write_1__VAL_1 : + 3'd0 ; + assign wci_5_reqTO$EN = + WILL_FIRE_RL_wci_5_wrkBusy && + wci_5_wciResponse_wget__23_BITS_33_TO_32_24_EQ_ETC___d952 || + WILL_FIRE_RL_cpDispatch_F_F_T_E5_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E5_F_F_T_T_T ; + + // register wci_5_respTimr + assign wci_5_respTimr$D_IN = + wci_5_reqF_cntr_r ? 32'd0 : MUX_wci_5_respTimr$write_1__VAL_2 ; + assign wci_5_respTimr$EN = WILL_FIRE_RL_wci_5_wrkBusy || wci_5_reqF_cntr_r ; + + // register wci_5_respTimrAct + assign wci_5_respTimrAct$D_IN = wci_5_reqF_cntr_r ; + assign wci_5_respTimrAct$EN = + WILL_FIRE_RL_wci_5_wrkBusy && + (!wci_5_respTimr_28_ULT_1_SL_wci_5_wTimeout_29_30___d931 || + wci_5_wciResponse$wget[33:32] != 2'd0) || + wci_5_reqF_cntr_r ; + + // register wci_5_sThreadBusy_d + assign wci_5_sThreadBusy_d$D_IN = wci_Vm_5_SThreadBusy ; + assign wci_5_sThreadBusy_d$EN = 1'd1 ; + + // register wci_5_sfCap + assign wci_5_sfCap$D_IN = wci_5_sfCapSet ; + assign wci_5_sfCap$EN = wci_5_sfCapSet || wci_5_sfCapClear ; + + // register wci_5_sfCapClear + assign wci_5_sfCapClear$D_IN = wci_5_sfCapClear_1$whas ; + assign wci_5_sfCapClear$EN = 1'd1 ; + + // register wci_5_sfCapSet + assign wci_5_sfCapSet$D_IN = wci_Vm_5_SFlag[0] ; + assign wci_5_sfCapSet$EN = 1'd1 ; + + // register wci_5_slvPresent + assign wci_5_slvPresent$D_IN = wci_Vm_5_SFlag[1] ; + assign wci_5_slvPresent$EN = 1'd1 ; + + // register wci_5_wReset_n + assign wci_5_wReset_n$D_IN = cpReq[59] ; + assign wci_5_wReset_n$EN = + WILL_FIRE_RL_cpDispatch_F_F_T_E5_F_F_T_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E5_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E5_F_F_T_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E5_F_F_T_T_T ; + + // register wci_5_wStatus + assign wci_5_wStatus$D_IN = + { 4'b0, + !wci_5_lastOpWrite[1] || wci_5_lastOpWrite[0], + IF_wci_5_lastControlOp_013_BIT_3_014_THEN_wci__ETC___d1028 } ; + assign wci_5_wStatus$EN = 1'd1 ; + + // register wci_5_wTimeout + assign wci_5_wTimeout$D_IN = cpReq[32:28] ; + assign wci_5_wTimeout$EN = + WILL_FIRE_RL_cpDispatch_F_F_T_E5_F_F_T_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E5_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E5_F_F_T_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E5_F_F_T_T_T ; + + // register wci_6_busy + assign wci_6_busy$D_IN = !MUX_wci_6_busy$write_1__SEL_1 ; + assign wci_6_busy$EN = + WILL_FIRE_RL_wci_6_wrkBusy && + (!wci_6_respTimr_068_ULT_1_SL_wci_6_wTimeout_069_ETC___d1071 || + wci_6_wciResponse$wget[33:32] != 2'd0) || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_F_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E6_T_T ; + + // register wci_6_lastConfigAddr + assign wci_6_lastConfigAddr$D_IN = wci_0_lastConfigAddr$D_IN ; + assign wci_6_lastConfigAddr$EN = + WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E6_T_T ; + + // register wci_6_lastConfigBE + assign wci_6_lastConfigBE$D_IN = wci_0_lastConfigBE$D_IN ; + assign wci_6_lastConfigBE$EN = + WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E6_T_T ; + + // register wci_6_lastControlOp + assign wci_6_lastControlOp$D_IN = wci_0_lastControlOp$D_IN ; + assign wci_6_lastControlOp$EN = WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_F_T_T ; + + // register wci_6_lastOpWrite + assign wci_6_lastOpWrite$D_IN = + WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_T_T ? 2'd2 : 2'd3 ; + assign wci_6_lastOpWrite$EN = + WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E6_T_T ; + + // register wci_6_mFlagReg + assign wci_6_mFlagReg$D_IN = 2'h0 ; + assign wci_6_mFlagReg$EN = 1'b0 ; + + // register wci_6_pageWindow + assign wci_6_pageWindow$D_IN = cpReq[39:28] ; + assign wci_6_pageWindow$EN = WILL_FIRE_RL_cpDispatch_F_F_T_E6_F_F_F_T ; + + // register wci_6_reqERR + assign wci_6_reqERR$D_IN = + MUX_wci_6_reqERR$write_1__SEL_1 ? + MUX_wci_6_reqERR$write_1__VAL_1 : + 3'd0 ; + assign wci_6_reqERR$EN = + WILL_FIRE_RL_wci_6_wrkBusy && + wci_6_wciResponse$wget[33:32] == 2'd3 && + (wci_6_reqPend == 2'd1 || wci_6_reqPend == 2'd2 || + wci_6_reqPend == 2'd3) || + WILL_FIRE_RL_cpDispatch_F_F_T_E6_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E6_F_F_T_T_T ; + + // register wci_6_reqFAIL + assign wci_6_reqFAIL$D_IN = + MUX_wci_6_reqFAIL$write_1__SEL_1 ? + MUX_wci_6_reqFAIL$write_1__VAL_1 : + 3'd0 ; + assign wci_6_reqFAIL$EN = + WILL_FIRE_RL_wci_6_wrkBusy && + wci_6_wciResponse$wget[33:32] == 2'd2 && + (wci_6_reqPend == 2'd1 || wci_6_reqPend == 2'd2 || + wci_6_reqPend == 2'd3) || + WILL_FIRE_RL_cpDispatch_F_F_T_E6_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E6_F_F_T_T_T ; + + // register wci_6_reqF_cntr_r + assign wci_6_reqF_cntr_r$D_IN = + WILL_FIRE_RL_wci_6_reqF_incCtr ? + MUX_wci_6_reqF_cntr_r$write_1__VAL_1 : + MUX_wci_6_reqF_cntr_r$write_1__VAL_2 ; + assign wci_6_reqF_cntr_r$EN = + WILL_FIRE_RL_wci_6_reqF_incCtr || + WILL_FIRE_RL_wci_6_reqF_decCtr ; + + // register wci_6_reqF_q_0 + always@(WILL_FIRE_RL_wci_6_reqF_both or + MUX_wci_6_reqF_q_0$write_1__VAL_1 or + MUX_wci_6_reqF_q_0$write_1__SEL_2 or + MUX_wci_6_reqF_q_0$write_1__VAL_2 or WILL_FIRE_RL_wci_6_reqF_decCtr) begin case (1'b1) // synopsys parallel_case - MUX_wci_reqPend_2$write_1__SEL_1: wci_reqPend_2$D_IN = 2'd0; - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_T_T: wci_reqPend_2$D_IN = 2'd1; - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_T_T: wci_reqPend_2$D_IN = 2'd2; - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_F_T_T: wci_reqPend_2$D_IN = 2'd3; - default: wci_reqPend_2$D_IN = 2'b10 /* unspecified value */ ; + WILL_FIRE_RL_wci_6_reqF_both: + wci_6_reqF_q_0$D_IN = MUX_wci_6_reqF_q_0$write_1__VAL_1; + MUX_wci_6_reqF_q_0$write_1__SEL_2: + wci_6_reqF_q_0$D_IN = MUX_wci_6_reqF_q_0$write_1__VAL_2; + WILL_FIRE_RL_wci_6_reqF_decCtr: + wci_6_reqF_q_0$D_IN = 72'h0000000000AAAAAAAA; + default: wci_6_reqF_q_0$D_IN = + 72'hAAAAAAAAAAAAAAAAAA /* unspecified value */ ; endcase end - assign wci_reqPend_2$EN = - WILL_FIRE_RL_wci_wrkBusy_2 && - wci_wciResponse_2$wget[33:32] != 2'd0 || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_F_T_T ; - - // register wci_reqPend_3 - always@(MUX_wci_reqPend_3$write_1__SEL_1 or - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_T_T or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_T_T or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_F_T_T) + assign wci_6_reqF_q_0$EN = + WILL_FIRE_RL_wci_6_reqF_both || + WILL_FIRE_RL_wci_6_reqF_incCtr && !wci_6_reqF_cntr_r || + WILL_FIRE_RL_wci_6_reqF_decCtr ; + + // register wci_6_reqPend + always@(MUX_wci_6_reqPend$write_1__SEL_1 or + WILL_FIRE_RL_cpDispatch_F_F_T_E6_T_T or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_T_T or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_F_T_T) begin case (1'b1) // synopsys parallel_case - MUX_wci_reqPend_3$write_1__SEL_1: wci_reqPend_3$D_IN = 2'd0; - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_T_T: wci_reqPend_3$D_IN = 2'd1; - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_T_T: wci_reqPend_3$D_IN = 2'd2; - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_F_T_T: - wci_reqPend_3$D_IN = 2'd3; - default: wci_reqPend_3$D_IN = 2'b10 /* unspecified value */ ; + MUX_wci_6_reqPend$write_1__SEL_1: wci_6_reqPend$D_IN = 2'd0; + WILL_FIRE_RL_cpDispatch_F_F_T_E6_T_T: wci_6_reqPend$D_IN = 2'd1; + WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_T_T: wci_6_reqPend$D_IN = 2'd2; + WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_F_T_T: wci_6_reqPend$D_IN = 2'd3; + default: wci_6_reqPend$D_IN = 2'b10 /* unspecified value */ ; endcase end - assign wci_reqPend_3$EN = - WILL_FIRE_RL_wci_wrkBusy_3 && - wci_wciResponse_3$wget[33:32] != 2'd0 || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_F_T_T ; - - // register wci_reqPend_4 - always@(MUX_wci_reqPend_4$write_1__SEL_1 or - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_T_T or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_T_T or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_T_T) + assign wci_6_reqPend$EN = + WILL_FIRE_RL_wci_6_wrkBusy && + wci_6_wciResponse$wget[33:32] != 2'd0 || + WILL_FIRE_RL_cpDispatch_F_F_T_E6_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_F_T_T ; + + // register wci_6_reqTO + assign wci_6_reqTO$D_IN = + MUX_wci_6_reqTO$write_1__SEL_1 ? + MUX_wci_6_reqTO$write_1__VAL_1 : + 3'd0 ; + assign wci_6_reqTO$EN = + WILL_FIRE_RL_wci_6_wrkBusy && + wci_6_wciResponse_wget__063_BITS_33_TO_32_064__ETC___d1092 || + WILL_FIRE_RL_cpDispatch_F_F_T_E6_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E6_F_F_T_T_T ; + + // register wci_6_respTimr + assign wci_6_respTimr$D_IN = + wci_6_reqF_cntr_r ? 32'd0 : MUX_wci_6_respTimr$write_1__VAL_2 ; + assign wci_6_respTimr$EN = WILL_FIRE_RL_wci_6_wrkBusy || wci_6_reqF_cntr_r ; + + // register wci_6_respTimrAct + assign wci_6_respTimrAct$D_IN = wci_6_reqF_cntr_r ; + assign wci_6_respTimrAct$EN = + WILL_FIRE_RL_wci_6_wrkBusy && + (!wci_6_respTimr_068_ULT_1_SL_wci_6_wTimeout_069_ETC___d1071 || + wci_6_wciResponse$wget[33:32] != 2'd0) || + wci_6_reqF_cntr_r ; + + // register wci_6_sThreadBusy_d + assign wci_6_sThreadBusy_d$D_IN = wci_Vm_6_SThreadBusy ; + assign wci_6_sThreadBusy_d$EN = 1'd1 ; + + // register wci_6_sfCap + assign wci_6_sfCap$D_IN = wci_6_sfCapSet ; + assign wci_6_sfCap$EN = wci_6_sfCapSet || wci_6_sfCapClear ; + + // register wci_6_sfCapClear + assign wci_6_sfCapClear$D_IN = wci_6_sfCapClear_1$whas ; + assign wci_6_sfCapClear$EN = 1'd1 ; + + // register wci_6_sfCapSet + assign wci_6_sfCapSet$D_IN = wci_Vm_6_SFlag[0] ; + assign wci_6_sfCapSet$EN = 1'd1 ; + + // register wci_6_slvPresent + assign wci_6_slvPresent$D_IN = wci_Vm_6_SFlag[1] ; + assign wci_6_slvPresent$EN = 1'd1 ; + + // register wci_6_wReset_n + assign wci_6_wReset_n$D_IN = cpReq[59] ; + assign wci_6_wReset_n$EN = + WILL_FIRE_RL_cpDispatch_F_F_T_E6_F_F_T_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E6_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E6_F_F_T_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E6_F_F_T_T_T ; + + // register wci_6_wStatus + assign wci_6_wStatus$D_IN = + { 4'b0, + !wci_6_lastOpWrite[1] || wci_6_lastOpWrite[0], + IF_wci_6_lastControlOp_153_BIT_3_154_THEN_wci__ETC___d1168 } ; + assign wci_6_wStatus$EN = 1'd1 ; + + // register wci_6_wTimeout + assign wci_6_wTimeout$D_IN = cpReq[32:28] ; + assign wci_6_wTimeout$EN = + WILL_FIRE_RL_cpDispatch_F_F_T_E6_F_F_T_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E6_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E6_F_F_T_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E6_F_F_T_T_T ; + + // register wci_7_busy + assign wci_7_busy$D_IN = !MUX_wci_7_busy$write_1__SEL_1 ; + assign wci_7_busy$EN = + WILL_FIRE_RL_wci_7_wrkBusy && + (!wci_7_respTimr_208_ULT_1_SL_wci_7_wTimeout_209_ETC___d1211 || + wci_7_wciResponse$wget[33:32] != 2'd0) || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E7_T_T ; + + // register wci_7_lastConfigAddr + assign wci_7_lastConfigAddr$D_IN = wci_0_lastConfigAddr$D_IN ; + assign wci_7_lastConfigAddr$EN = + WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E7_T_T ; + + // register wci_7_lastConfigBE + assign wci_7_lastConfigBE$D_IN = wci_0_lastConfigBE$D_IN ; + assign wci_7_lastConfigBE$EN = + WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E7_T_T ; + + // register wci_7_lastControlOp + assign wci_7_lastControlOp$D_IN = wci_0_lastControlOp$D_IN ; + assign wci_7_lastControlOp$EN = WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_T_T ; + + // register wci_7_lastOpWrite + assign wci_7_lastOpWrite$D_IN = + WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_T_T ? 2'd2 : 2'd3 ; + assign wci_7_lastOpWrite$EN = + WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E7_T_T ; + + // register wci_7_mFlagReg + assign wci_7_mFlagReg$D_IN = 2'h0 ; + assign wci_7_mFlagReg$EN = 1'b0 ; + + // register wci_7_pageWindow + assign wci_7_pageWindow$D_IN = cpReq[39:28] ; + assign wci_7_pageWindow$EN = WILL_FIRE_RL_cpDispatch_F_F_T_E7_F_F_F_T ; + + // register wci_7_reqERR + assign wci_7_reqERR$D_IN = + MUX_wci_7_reqERR$write_1__SEL_1 ? + MUX_wci_7_reqERR$write_1__VAL_1 : + 3'd0 ; + assign wci_7_reqERR$EN = + WILL_FIRE_RL_wci_7_wrkBusy && + wci_7_wciResponse$wget[33:32] == 2'd3 && + (wci_7_reqPend == 2'd1 || wci_7_reqPend == 2'd2 || + wci_7_reqPend == 2'd3) || + WILL_FIRE_RL_cpDispatch_F_F_T_E7_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E7_F_F_T_T_T ; + + // register wci_7_reqFAIL + assign wci_7_reqFAIL$D_IN = + MUX_wci_7_reqFAIL$write_1__SEL_1 ? + MUX_wci_7_reqFAIL$write_1__VAL_1 : + 3'd0 ; + assign wci_7_reqFAIL$EN = + WILL_FIRE_RL_wci_7_wrkBusy && + wci_7_wciResponse$wget[33:32] == 2'd2 && + (wci_7_reqPend == 2'd1 || wci_7_reqPend == 2'd2 || + wci_7_reqPend == 2'd3) || + WILL_FIRE_RL_cpDispatch_F_F_T_E7_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E7_F_F_T_T_T ; + + // register wci_7_reqF_cntr_r + assign wci_7_reqF_cntr_r$D_IN = + WILL_FIRE_RL_wci_7_reqF_incCtr ? + MUX_wci_7_reqF_cntr_r$write_1__VAL_1 : + MUX_wci_7_reqF_cntr_r$write_1__VAL_2 ; + assign wci_7_reqF_cntr_r$EN = + WILL_FIRE_RL_wci_7_reqF_incCtr || + WILL_FIRE_RL_wci_7_reqF_decCtr ; + + // register wci_7_reqF_q_0 + always@(WILL_FIRE_RL_wci_7_reqF_both or + MUX_wci_7_reqF_q_0$write_1__VAL_1 or + MUX_wci_7_reqF_q_0$write_1__SEL_2 or + MUX_wci_7_reqF_q_0$write_1__VAL_2 or WILL_FIRE_RL_wci_7_reqF_decCtr) begin case (1'b1) // synopsys parallel_case - MUX_wci_reqPend_4$write_1__SEL_1: wci_reqPend_4$D_IN = 2'd0; - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_T_T: wci_reqPend_4$D_IN = 2'd1; - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_T_T: - wci_reqPend_4$D_IN = 2'd2; - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_T_T: - wci_reqPend_4$D_IN = 2'd3; - default: wci_reqPend_4$D_IN = 2'b10 /* unspecified value */ ; + WILL_FIRE_RL_wci_7_reqF_both: + wci_7_reqF_q_0$D_IN = MUX_wci_7_reqF_q_0$write_1__VAL_1; + MUX_wci_7_reqF_q_0$write_1__SEL_2: + wci_7_reqF_q_0$D_IN = MUX_wci_7_reqF_q_0$write_1__VAL_2; + WILL_FIRE_RL_wci_7_reqF_decCtr: + wci_7_reqF_q_0$D_IN = 72'h0000000000AAAAAAAA; + default: wci_7_reqF_q_0$D_IN = + 72'hAAAAAAAAAAAAAAAAAA /* unspecified value */ ; endcase end - assign wci_reqPend_4$EN = - WILL_FIRE_RL_wci_wrkBusy_4 && - wci_wciResponse_4$wget[33:32] != 2'd0 || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_T_T ; - - // register wci_reqPend_5 - always@(MUX_wci_reqPend_5$write_1__SEL_1 or - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_T_T or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_T_T or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_T_T) + assign wci_7_reqF_q_0$EN = + WILL_FIRE_RL_wci_7_reqF_both || + WILL_FIRE_RL_wci_7_reqF_incCtr && !wci_7_reqF_cntr_r || + WILL_FIRE_RL_wci_7_reqF_decCtr ; + + // register wci_7_reqPend + always@(MUX_wci_7_reqPend$write_1__SEL_1 or + WILL_FIRE_RL_cpDispatch_F_F_T_E7_T_T or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_T_T or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_T_T) begin case (1'b1) // synopsys parallel_case - MUX_wci_reqPend_5$write_1__SEL_1: wci_reqPend_5$D_IN = 2'd0; - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_T_T: - wci_reqPend_5$D_IN = 2'd1; - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_T_T: - wci_reqPend_5$D_IN = 2'd2; - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_T_T: - wci_reqPend_5$D_IN = 2'd3; - default: wci_reqPend_5$D_IN = 2'b10 /* unspecified value */ ; + MUX_wci_7_reqPend$write_1__SEL_1: wci_7_reqPend$D_IN = 2'd0; + WILL_FIRE_RL_cpDispatch_F_F_T_E7_T_T: wci_7_reqPend$D_IN = 2'd1; + WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_T_T: wci_7_reqPend$D_IN = 2'd2; + WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_T_T: wci_7_reqPend$D_IN = 2'd3; + default: wci_7_reqPend$D_IN = 2'b10 /* unspecified value */ ; endcase end - assign wci_reqPend_5$EN = - WILL_FIRE_RL_wci_wrkBusy_5 && - wci_wciResponse_5$wget[33:32] != 2'd0 || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_T_T ; - - // register wci_reqPend_6 - always@(MUX_wci_reqPend_6$write_1__SEL_1 or - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_T_T or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_T_T or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_F_T_T) + assign wci_7_reqPend$EN = + WILL_FIRE_RL_wci_7_wrkBusy && + wci_7_wciResponse$wget[33:32] != 2'd0 || + WILL_FIRE_RL_cpDispatch_F_F_T_E7_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_T_T ; + + // register wci_7_reqTO + assign wci_7_reqTO$D_IN = + MUX_wci_7_reqTO$write_1__SEL_1 ? + MUX_wci_7_reqTO$write_1__VAL_1 : + 3'd0 ; + assign wci_7_reqTO$EN = + WILL_FIRE_RL_wci_7_wrkBusy && + wci_7_wciResponse_wget__203_BITS_33_TO_32_204__ETC___d1232 || + WILL_FIRE_RL_cpDispatch_F_F_T_E7_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E7_F_F_T_T_T ; + + // register wci_7_respTimr + assign wci_7_respTimr$D_IN = + wci_7_reqF_cntr_r ? 32'd0 : MUX_wci_7_respTimr$write_1__VAL_2 ; + assign wci_7_respTimr$EN = WILL_FIRE_RL_wci_7_wrkBusy || wci_7_reqF_cntr_r ; + + // register wci_7_respTimrAct + assign wci_7_respTimrAct$D_IN = wci_7_reqF_cntr_r ; + assign wci_7_respTimrAct$EN = + WILL_FIRE_RL_wci_7_wrkBusy && + (!wci_7_respTimr_208_ULT_1_SL_wci_7_wTimeout_209_ETC___d1211 || + wci_7_wciResponse$wget[33:32] != 2'd0) || + wci_7_reqF_cntr_r ; + + // register wci_7_sThreadBusy_d + assign wci_7_sThreadBusy_d$D_IN = wci_Vm_7_SThreadBusy ; + assign wci_7_sThreadBusy_d$EN = 1'd1 ; + + // register wci_7_sfCap + assign wci_7_sfCap$D_IN = wci_7_sfCapSet ; + assign wci_7_sfCap$EN = wci_7_sfCapSet || wci_7_sfCapClear ; + + // register wci_7_sfCapClear + assign wci_7_sfCapClear$D_IN = wci_7_sfCapClear_1$whas ; + assign wci_7_sfCapClear$EN = 1'd1 ; + + // register wci_7_sfCapSet + assign wci_7_sfCapSet$D_IN = wci_Vm_7_SFlag[0] ; + assign wci_7_sfCapSet$EN = 1'd1 ; + + // register wci_7_slvPresent + assign wci_7_slvPresent$D_IN = wci_Vm_7_SFlag[1] ; + assign wci_7_slvPresent$EN = 1'd1 ; + + // register wci_7_wReset_n + assign wci_7_wReset_n$D_IN = cpReq[59] ; + assign wci_7_wReset_n$EN = + WILL_FIRE_RL_cpDispatch_F_F_T_E7_F_F_T_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E7_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E7_F_F_T_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E7_F_F_T_T_T ; + + // register wci_7_wStatus + assign wci_7_wStatus$D_IN = + { 4'b0, + !wci_7_lastOpWrite[1] || wci_7_lastOpWrite[0], + IF_wci_7_lastControlOp_293_BIT_3_294_THEN_wci__ETC___d1308 } ; + assign wci_7_wStatus$EN = 1'd1 ; + + // register wci_7_wTimeout + assign wci_7_wTimeout$D_IN = cpReq[32:28] ; + assign wci_7_wTimeout$EN = + WILL_FIRE_RL_cpDispatch_F_F_T_E7_F_F_T_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E7_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E7_F_F_T_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E7_F_F_T_T_T ; + + // register wci_8_busy + assign wci_8_busy$D_IN = !MUX_wci_8_busy$write_1__SEL_1 ; + assign wci_8_busy$EN = + WILL_FIRE_RL_wci_8_wrkBusy && + (!wci_8_respTimr_348_ULT_1_SL_wci_8_wTimeout_349_ETC___d1351 || + wci_8_wciResponse$wget[33:32] != 2'd0) || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E8_T_T ; + + // register wci_8_lastConfigAddr + assign wci_8_lastConfigAddr$D_IN = wci_0_lastConfigAddr$D_IN ; + assign wci_8_lastConfigAddr$EN = + WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E8_T_T ; + + // register wci_8_lastConfigBE + assign wci_8_lastConfigBE$D_IN = wci_0_lastConfigBE$D_IN ; + assign wci_8_lastConfigBE$EN = + WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E8_T_T ; + + // register wci_8_lastControlOp + assign wci_8_lastControlOp$D_IN = wci_0_lastControlOp$D_IN ; + assign wci_8_lastControlOp$EN = WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_T_T ; + + // register wci_8_lastOpWrite + assign wci_8_lastOpWrite$D_IN = + WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_T_T ? 2'd2 : 2'd3 ; + assign wci_8_lastOpWrite$EN = + WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E8_T_T ; + + // register wci_8_mFlagReg + assign wci_8_mFlagReg$D_IN = 2'h0 ; + assign wci_8_mFlagReg$EN = 1'b0 ; + + // register wci_8_pageWindow + assign wci_8_pageWindow$D_IN = cpReq[39:28] ; + assign wci_8_pageWindow$EN = WILL_FIRE_RL_cpDispatch_F_F_T_E8_F_F_F_T ; + + // register wci_8_reqERR + assign wci_8_reqERR$D_IN = + MUX_wci_8_reqERR$write_1__SEL_1 ? + MUX_wci_8_reqERR$write_1__VAL_1 : + 3'd0 ; + assign wci_8_reqERR$EN = + WILL_FIRE_RL_wci_8_wrkBusy && + wci_8_wciResponse$wget[33:32] == 2'd3 && + (wci_8_reqPend == 2'd1 || wci_8_reqPend == 2'd2 || + wci_8_reqPend == 2'd3) || + WILL_FIRE_RL_cpDispatch_F_F_T_E8_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E8_F_F_T_T_T ; + + // register wci_8_reqFAIL + assign wci_8_reqFAIL$D_IN = + MUX_wci_8_reqFAIL$write_1__SEL_1 ? + MUX_wci_8_reqFAIL$write_1__VAL_1 : + 3'd0 ; + assign wci_8_reqFAIL$EN = + WILL_FIRE_RL_wci_8_wrkBusy && + wci_8_wciResponse$wget[33:32] == 2'd2 && + (wci_8_reqPend == 2'd1 || wci_8_reqPend == 2'd2 || + wci_8_reqPend == 2'd3) || + WILL_FIRE_RL_cpDispatch_F_F_T_E8_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E8_F_F_T_T_T ; + + // register wci_8_reqF_cntr_r + assign wci_8_reqF_cntr_r$D_IN = + WILL_FIRE_RL_wci_8_reqF_incCtr ? + MUX_wci_8_reqF_cntr_r$write_1__VAL_1 : + MUX_wci_8_reqF_cntr_r$write_1__VAL_2 ; + assign wci_8_reqF_cntr_r$EN = + WILL_FIRE_RL_wci_8_reqF_incCtr || + WILL_FIRE_RL_wci_8_reqF_decCtr ; + + // register wci_8_reqF_q_0 + always@(WILL_FIRE_RL_wci_8_reqF_both or + MUX_wci_8_reqF_q_0$write_1__VAL_1 or + MUX_wci_8_reqF_q_0$write_1__SEL_2 or + MUX_wci_8_reqF_q_0$write_1__VAL_2 or WILL_FIRE_RL_wci_8_reqF_decCtr) begin case (1'b1) // synopsys parallel_case - MUX_wci_reqPend_6$write_1__SEL_1: wci_reqPend_6$D_IN = 2'd0; - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_T_T: - wci_reqPend_6$D_IN = 2'd1; - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_T_T: - wci_reqPend_6$D_IN = 2'd2; - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_F_T_T: - wci_reqPend_6$D_IN = 2'd3; - default: wci_reqPend_6$D_IN = 2'b10 /* unspecified value */ ; + WILL_FIRE_RL_wci_8_reqF_both: + wci_8_reqF_q_0$D_IN = MUX_wci_8_reqF_q_0$write_1__VAL_1; + MUX_wci_8_reqF_q_0$write_1__SEL_2: + wci_8_reqF_q_0$D_IN = MUX_wci_8_reqF_q_0$write_1__VAL_2; + WILL_FIRE_RL_wci_8_reqF_decCtr: + wci_8_reqF_q_0$D_IN = 72'h0000000000AAAAAAAA; + default: wci_8_reqF_q_0$D_IN = + 72'hAAAAAAAAAAAAAAAAAA /* unspecified value */ ; endcase end - assign wci_reqPend_6$EN = - WILL_FIRE_RL_wci_wrkBusy_6 && - wci_wciResponse_6$wget[33:32] != 2'd0 || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_F_T_T ; - - // register wci_reqPend_7 - always@(MUX_wci_reqPend_7$write_1__SEL_1 or - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_T_T or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_T_T or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T) + assign wci_8_reqF_q_0$EN = + WILL_FIRE_RL_wci_8_reqF_both || + WILL_FIRE_RL_wci_8_reqF_incCtr && !wci_8_reqF_cntr_r || + WILL_FIRE_RL_wci_8_reqF_decCtr ; + + // register wci_8_reqPend + always@(MUX_wci_8_reqPend$write_1__SEL_1 or + WILL_FIRE_RL_cpDispatch_F_F_T_E8_T_T or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_T_T or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_T_T) begin case (1'b1) // synopsys parallel_case - MUX_wci_reqPend_7$write_1__SEL_1: wci_reqPend_7$D_IN = 2'd0; - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_T_T: - wci_reqPend_7$D_IN = 2'd1; - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_T_T: - wci_reqPend_7$D_IN = 2'd2; - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T: - wci_reqPend_7$D_IN = 2'd3; - default: wci_reqPend_7$D_IN = 2'b10 /* unspecified value */ ; + MUX_wci_8_reqPend$write_1__SEL_1: wci_8_reqPend$D_IN = 2'd0; + WILL_FIRE_RL_cpDispatch_F_F_T_E8_T_T: wci_8_reqPend$D_IN = 2'd1; + WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_T_T: wci_8_reqPend$D_IN = 2'd2; + WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_T_T: wci_8_reqPend$D_IN = 2'd3; + default: wci_8_reqPend$D_IN = 2'b10 /* unspecified value */ ; endcase end - assign wci_reqPend_7$EN = - WILL_FIRE_RL_wci_wrkBusy_7 && - wci_wciResponse_7$wget[33:32] != 2'd0 || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T ; - - // register wci_reqPend_8 - always@(MUX_wci_reqPend_8$write_1__SEL_1 or - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_T_T or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T) + assign wci_8_reqPend$EN = + WILL_FIRE_RL_wci_8_wrkBusy && + wci_8_wciResponse$wget[33:32] != 2'd0 || + WILL_FIRE_RL_cpDispatch_F_F_T_E8_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_T_T ; + + // register wci_8_reqTO + assign wci_8_reqTO$D_IN = + MUX_wci_8_reqTO$write_1__SEL_1 ? + MUX_wci_8_reqTO$write_1__VAL_1 : + 3'd0 ; + assign wci_8_reqTO$EN = + WILL_FIRE_RL_wci_8_wrkBusy && + wci_8_wciResponse_wget__343_BITS_33_TO_32_344__ETC___d1372 || + WILL_FIRE_RL_cpDispatch_F_F_T_E8_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E8_F_F_T_T_T ; + + // register wci_8_respTimr + assign wci_8_respTimr$D_IN = + wci_8_reqF_cntr_r ? 32'd0 : MUX_wci_8_respTimr$write_1__VAL_2 ; + assign wci_8_respTimr$EN = WILL_FIRE_RL_wci_8_wrkBusy || wci_8_reqF_cntr_r ; + + // register wci_8_respTimrAct + assign wci_8_respTimrAct$D_IN = wci_8_reqF_cntr_r ; + assign wci_8_respTimrAct$EN = + WILL_FIRE_RL_wci_8_wrkBusy && + (!wci_8_respTimr_348_ULT_1_SL_wci_8_wTimeout_349_ETC___d1351 || + wci_8_wciResponse$wget[33:32] != 2'd0) || + wci_8_reqF_cntr_r ; + + // register wci_8_sThreadBusy_d + assign wci_8_sThreadBusy_d$D_IN = wci_Vm_8_SThreadBusy ; + assign wci_8_sThreadBusy_d$EN = 1'd1 ; + + // register wci_8_sfCap + assign wci_8_sfCap$D_IN = wci_8_sfCapSet ; + assign wci_8_sfCap$EN = wci_8_sfCapSet || wci_8_sfCapClear ; + + // register wci_8_sfCapClear + assign wci_8_sfCapClear$D_IN = wci_8_sfCapClear_1$whas ; + assign wci_8_sfCapClear$EN = 1'd1 ; + + // register wci_8_sfCapSet + assign wci_8_sfCapSet$D_IN = wci_Vm_8_SFlag[0] ; + assign wci_8_sfCapSet$EN = 1'd1 ; + + // register wci_8_slvPresent + assign wci_8_slvPresent$D_IN = wci_Vm_8_SFlag[1] ; + assign wci_8_slvPresent$EN = 1'd1 ; + + // register wci_8_wReset_n + assign wci_8_wReset_n$D_IN = cpReq[59] ; + assign wci_8_wReset_n$EN = + WILL_FIRE_RL_cpDispatch_F_F_T_E8_F_F_T_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E8_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E8_F_F_T_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E8_F_F_T_T_T ; + + // register wci_8_wStatus + assign wci_8_wStatus$D_IN = + { 4'b0, + !wci_8_lastOpWrite[1] || wci_8_lastOpWrite[0], + IF_wci_8_lastControlOp_433_BIT_3_434_THEN_wci__ETC___d1448 } ; + assign wci_8_wStatus$EN = 1'd1 ; + + // register wci_8_wTimeout + assign wci_8_wTimeout$D_IN = cpReq[32:28] ; + assign wci_8_wTimeout$EN = + WILL_FIRE_RL_cpDispatch_F_F_T_E8_F_F_T_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E8_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E8_F_F_T_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E8_F_F_T_T_T ; + + // register wci_9_busy + assign wci_9_busy$D_IN = !MUX_wci_9_busy$write_1__SEL_1 ; + assign wci_9_busy$EN = + WILL_FIRE_RL_wci_9_wrkBusy && + (!wci_9_respTimr_488_ULT_1_SL_wci_9_wTimeout_489_ETC___d1491 || + wci_9_wciResponse$wget[33:32] != 2'd0) || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_F_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E9_T_T ; + + // register wci_9_lastConfigAddr + assign wci_9_lastConfigAddr$D_IN = wci_0_lastConfigAddr$D_IN ; + assign wci_9_lastConfigAddr$EN = + WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E9_T_T ; + + // register wci_9_lastConfigBE + assign wci_9_lastConfigBE$D_IN = wci_0_lastConfigBE$D_IN ; + assign wci_9_lastConfigBE$EN = + WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E9_T_T ; + + // register wci_9_lastControlOp + assign wci_9_lastControlOp$D_IN = wci_0_lastControlOp$D_IN ; + assign wci_9_lastControlOp$EN = WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_F_T_T ; + + // register wci_9_lastOpWrite + assign wci_9_lastOpWrite$D_IN = + WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_T_T ? 2'd2 : 2'd3 ; + assign wci_9_lastOpWrite$EN = + WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E9_T_T ; + + // register wci_9_mFlagReg + assign wci_9_mFlagReg$D_IN = 2'h0 ; + assign wci_9_mFlagReg$EN = 1'b0 ; + + // register wci_9_pageWindow + assign wci_9_pageWindow$D_IN = cpReq[39:28] ; + assign wci_9_pageWindow$EN = WILL_FIRE_RL_cpDispatch_F_F_T_E9_F_F_F_T ; + + // register wci_9_reqERR + assign wci_9_reqERR$D_IN = + MUX_wci_9_reqERR$write_1__SEL_1 ? + MUX_wci_9_reqERR$write_1__VAL_1 : + 3'd0 ; + assign wci_9_reqERR$EN = + WILL_FIRE_RL_wci_9_wrkBusy && + wci_9_wciResponse$wget[33:32] == 2'd3 && + (wci_9_reqPend == 2'd1 || wci_9_reqPend == 2'd2 || + wci_9_reqPend == 2'd3) || + WILL_FIRE_RL_cpDispatch_F_F_T_E9_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E9_F_F_T_T_T ; + + // register wci_9_reqFAIL + assign wci_9_reqFAIL$D_IN = + MUX_wci_9_reqFAIL$write_1__SEL_1 ? + MUX_wci_9_reqFAIL$write_1__VAL_1 : + 3'd0 ; + assign wci_9_reqFAIL$EN = + WILL_FIRE_RL_wci_9_wrkBusy && + wci_9_wciResponse$wget[33:32] == 2'd2 && + (wci_9_reqPend == 2'd1 || wci_9_reqPend == 2'd2 || + wci_9_reqPend == 2'd3) || + WILL_FIRE_RL_cpDispatch_F_F_T_E9_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E9_F_F_T_T_T ; + + // register wci_9_reqF_cntr_r + assign wci_9_reqF_cntr_r$D_IN = + WILL_FIRE_RL_wci_9_reqF_incCtr ? + MUX_wci_9_reqF_cntr_r$write_1__VAL_1 : + MUX_wci_9_reqF_cntr_r$write_1__VAL_2 ; + assign wci_9_reqF_cntr_r$EN = + WILL_FIRE_RL_wci_9_reqF_incCtr || + WILL_FIRE_RL_wci_9_reqF_decCtr ; + + // register wci_9_reqF_q_0 + always@(WILL_FIRE_RL_wci_9_reqF_both or + MUX_wci_9_reqF_q_0$write_1__VAL_1 or + MUX_wci_9_reqF_q_0$write_1__SEL_2 or + MUX_wci_9_reqF_q_0$write_1__VAL_2 or WILL_FIRE_RL_wci_9_reqF_decCtr) begin case (1'b1) // synopsys parallel_case - MUX_wci_reqPend_8$write_1__SEL_1: wci_reqPend_8$D_IN = 2'd0; - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_T_T: - wci_reqPend_8$D_IN = 2'd1; - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T: - wci_reqPend_8$D_IN = 2'd2; - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T: - wci_reqPend_8$D_IN = 2'd3; - default: wci_reqPend_8$D_IN = 2'b10 /* unspecified value */ ; + WILL_FIRE_RL_wci_9_reqF_both: + wci_9_reqF_q_0$D_IN = MUX_wci_9_reqF_q_0$write_1__VAL_1; + MUX_wci_9_reqF_q_0$write_1__SEL_2: + wci_9_reqF_q_0$D_IN = MUX_wci_9_reqF_q_0$write_1__VAL_2; + WILL_FIRE_RL_wci_9_reqF_decCtr: + wci_9_reqF_q_0$D_IN = 72'h0000000000AAAAAAAA; + default: wci_9_reqF_q_0$D_IN = + 72'hAAAAAAAAAAAAAAAAAA /* unspecified value */ ; endcase end - assign wci_reqPend_8$EN = - WILL_FIRE_RL_wci_wrkBusy_8 && - wci_wciResponse_8$wget[33:32] != 2'd0 || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T ; - - // register wci_reqPend_9 - always@(MUX_wci_reqPend_9$write_1__SEL_1 or - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_T_T or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T) + assign wci_9_reqF_q_0$EN = + WILL_FIRE_RL_wci_9_reqF_both || + WILL_FIRE_RL_wci_9_reqF_incCtr && !wci_9_reqF_cntr_r || + WILL_FIRE_RL_wci_9_reqF_decCtr ; + + // register wci_9_reqPend + always@(MUX_wci_9_reqPend$write_1__SEL_1 or + WILL_FIRE_RL_cpDispatch_F_F_T_E9_T_T or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_T_T or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_F_T_T) begin case (1'b1) // synopsys parallel_case - MUX_wci_reqPend_9$write_1__SEL_1: wci_reqPend_9$D_IN = 2'd0; - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_T_T: - wci_reqPend_9$D_IN = 2'd1; - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T: - wci_reqPend_9$D_IN = 2'd2; - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T: - wci_reqPend_9$D_IN = 2'd3; - default: wci_reqPend_9$D_IN = 2'b10 /* unspecified value */ ; + MUX_wci_9_reqPend$write_1__SEL_1: wci_9_reqPend$D_IN = 2'd0; + WILL_FIRE_RL_cpDispatch_F_F_T_E9_T_T: wci_9_reqPend$D_IN = 2'd1; + WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_T_T: wci_9_reqPend$D_IN = 2'd2; + WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_F_T_T: wci_9_reqPend$D_IN = 2'd3; + default: wci_9_reqPend$D_IN = 2'b10 /* unspecified value */ ; endcase end - assign wci_reqPend_9$EN = - WILL_FIRE_RL_wci_wrkBusy_9 && - wci_wciResponse_9$wget[33:32] != 2'd0 || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T ; - - // register wci_reqTO - assign wci_reqTO$D_IN = - MUX_wci_reqTO$write_1__SEL_1 ? - MUX_wci_reqTO$write_1__VAL_1 : - 3'd0 ; - assign wci_reqTO$EN = - WILL_FIRE_RL_wci_wrkBusy && - wci_wciResponse_wget__97_BITS_33_TO_32_98_EQ_0_ETC___d226 || - WILL_FIRE_RL_cpDispatch_F_F_T_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_T_F_F_T_T_T ; - - // register wci_reqTO_1 - assign wci_reqTO_1$D_IN = - MUX_wci_reqTO_1$write_1__SEL_1 ? - MUX_wci_reqTO_1$write_1__VAL_1 : - 3'd0 ; - assign wci_reqTO_1$EN = - WILL_FIRE_RL_wci_wrkBusy_1 && - wci_wciResponse_1_wget__37_BITS_33_TO_32_38_EQ_ETC___d366 || - WILL_FIRE_RL_cpDispatch_F_F_T_F_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_T_F_F_T_T_T ; - - // register wci_reqTO_10 - assign wci_reqTO_10$D_IN = - MUX_wci_reqTO_10$write_1__SEL_1 ? - MUX_wci_reqTO_10$write_1__VAL_1 : - 3'd0 ; - assign wci_reqTO_10$EN = - WILL_FIRE_RL_wci_wrkBusy_10 && - wci_wciResponse_10_wget__597_BITS_33_TO_32_598_ETC___d1626 || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_T ; - - // register wci_reqTO_11 - assign wci_reqTO_11$D_IN = - MUX_wci_reqTO_11$write_1__SEL_1 ? - MUX_wci_reqTO_11$write_1__VAL_1 : - 3'd0 ; - assign wci_reqTO_11$EN = - WILL_FIRE_RL_wci_wrkBusy_11 && - wci_wciResponse_11_wget__737_BITS_33_TO_32_738_ETC___d1766 || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_T ; - - // register wci_reqTO_12 - assign wci_reqTO_12$D_IN = - MUX_wci_reqTO_12$write_1__SEL_1 ? - MUX_wci_reqTO_12$write_1__VAL_1 : - 3'd0 ; - assign wci_reqTO_12$EN = - WILL_FIRE_RL_wci_wrkBusy_12 && - wci_wciResponse_12_wget__877_BITS_33_TO_32_878_ETC___d1906 || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_T ; - - // register wci_reqTO_13 - assign wci_reqTO_13$D_IN = - MUX_wci_reqTO_13$write_1__SEL_1 ? - MUX_wci_reqTO_13$write_1__VAL_1 : - 3'd0 ; - assign wci_reqTO_13$EN = - WILL_FIRE_RL_wci_wrkBusy_13 && - wci_wciResponse_13_wget__017_BITS_33_TO_32_018_ETC___d2046 || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_T ; - - // register wci_reqTO_14 - assign wci_reqTO_14$D_IN = - MUX_wci_reqTO_14$write_1__SEL_1 ? - MUX_wci_reqTO_14$write_1__VAL_1 : - 3'd0 ; - assign wci_reqTO_14$EN = - WILL_FIRE_RL_wci_wrkBusy_14 && - wci_wciResponse_14_wget__157_BITS_33_TO_32_158_ETC___d2186 || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_T ; - - // register wci_reqTO_2 - assign wci_reqTO_2$D_IN = - MUX_wci_reqTO_2$write_1__SEL_1 ? - MUX_wci_reqTO_2$write_1__VAL_1 : + assign wci_9_reqPend$EN = + WILL_FIRE_RL_wci_9_wrkBusy && + wci_9_wciResponse$wget[33:32] != 2'd0 || + WILL_FIRE_RL_cpDispatch_F_F_T_E9_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_F_T_T ; + + // register wci_9_reqTO + assign wci_9_reqTO$D_IN = + MUX_wci_9_reqTO$write_1__SEL_1 ? + MUX_wci_9_reqTO$write_1__VAL_1 : 3'd0 ; - assign wci_reqTO_2$EN = - WILL_FIRE_RL_wci_wrkBusy_2 && - wci_wciResponse_2_wget__77_BITS_33_TO_32_78_EQ_ETC___d506 || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_F_F_T_T_T ; - - // register wci_reqTO_3 - assign wci_reqTO_3$D_IN = - MUX_wci_reqTO_3$write_1__SEL_1 ? - MUX_wci_reqTO_3$write_1__VAL_1 : - 3'd0 ; - assign wci_reqTO_3$EN = - WILL_FIRE_RL_wci_wrkBusy_3 && - wci_wciResponse_3_wget__17_BITS_33_TO_32_18_EQ_ETC___d646 || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_F_F_T_T_T ; - - // register wci_reqTO_4 - assign wci_reqTO_4$D_IN = - MUX_wci_reqTO_4$write_1__SEL_1 ? - MUX_wci_reqTO_4$write_1__VAL_1 : - 3'd0 ; - assign wci_reqTO_4$EN = - WILL_FIRE_RL_wci_wrkBusy_4 && - wci_wciResponse_4_wget__57_BITS_33_TO_32_58_EQ_ETC___d786 || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_F_F_T_T_T ; - - // register wci_reqTO_5 - assign wci_reqTO_5$D_IN = - MUX_wci_reqTO_5$write_1__SEL_1 ? - MUX_wci_reqTO_5$write_1__VAL_1 : - 3'd0 ; - assign wci_reqTO_5$EN = - WILL_FIRE_RL_wci_wrkBusy_5 && - wci_wciResponse_5_wget__97_BITS_33_TO_32_98_EQ_ETC___d926 || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_F_T_T_T ; - - // register wci_reqTO_6 - assign wci_reqTO_6$D_IN = - MUX_wci_reqTO_6$write_1__SEL_1 ? - MUX_wci_reqTO_6$write_1__VAL_1 : - 3'd0 ; - assign wci_reqTO_6$EN = - WILL_FIRE_RL_wci_wrkBusy_6 && - wci_wciResponse_6_wget__037_BITS_33_TO_32_038__ETC___d1066 || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_F_F_T_T_T ; - - // register wci_reqTO_7 - assign wci_reqTO_7$D_IN = - MUX_wci_reqTO_7$write_1__SEL_1 ? - MUX_wci_reqTO_7$write_1__VAL_1 : - 3'd0 ; - assign wci_reqTO_7$EN = - WILL_FIRE_RL_wci_wrkBusy_7 && - wci_wciResponse_7_wget__177_BITS_33_TO_32_178__ETC___d1206 || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_F_F_T_T_T ; - - // register wci_reqTO_8 - assign wci_reqTO_8$D_IN = - MUX_wci_reqTO_8$write_1__SEL_1 ? - MUX_wci_reqTO_8$write_1__VAL_1 : - 3'd0 ; - assign wci_reqTO_8$EN = - WILL_FIRE_RL_wci_wrkBusy_8 && - wci_wciResponse_8_wget__317_BITS_33_TO_32_318__ETC___d1346 || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_F_F_T_T_T ; - - // register wci_reqTO_9 - assign wci_reqTO_9$D_IN = - MUX_wci_reqTO_9$write_1__SEL_1 ? - MUX_wci_reqTO_9$write_1__VAL_1 : - 3'd0 ; - assign wci_reqTO_9$EN = - WILL_FIRE_RL_wci_wrkBusy_9 && - wci_wciResponse_9_wget__457_BITS_33_TO_32_458__ETC___d1486 || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_F_F_T_T_T ; - - // register wci_respTimr - assign wci_respTimr$D_IN = - wci_reqF_c_r ? 32'd0 : MUX_wci_respTimr$write_1__VAL_2 ; - assign wci_respTimr$EN = WILL_FIRE_RL_wci_wrkBusy || wci_reqF_c_r ; - - // register wci_respTimrAct - assign wci_respTimrAct$D_IN = wci_reqF_c_r ; - assign wci_respTimrAct$EN = - WILL_FIRE_RL_wci_wrkBusy && - (!wci_respTimr_02_ULT_1_SL_wci_wTimeout_03_04___d5829 || - wci_wciResponse$wget[33:32] != 2'd0) || - wci_reqF_c_r ; - - // register wci_respTimrAct_1 - assign wci_respTimrAct_1$D_IN = wci_reqF_1_c_r ; - assign wci_respTimrAct_1$EN = - WILL_FIRE_RL_wci_wrkBusy_1 && - (!wci_respTimr_1_42_ULT_1_SL_wci_wTimeout_1_43_44___d5830 || - wci_wciResponse_1$wget[33:32] != 2'd0) || - wci_reqF_1_c_r ; - - // register wci_respTimrAct_10 - assign wci_respTimrAct_10$D_IN = wci_reqF_10_c_r ; - assign wci_respTimrAct_10$EN = - WILL_FIRE_RL_wci_wrkBusy_10 && - (!wci_respTimr_10_602_ULT_1_SL_wci_wTimeout_10_6_ETC___d5839 || - wci_wciResponse_10$wget[33:32] != 2'd0) || - wci_reqF_10_c_r ; - - // register wci_respTimrAct_11 - assign wci_respTimrAct_11$D_IN = wci_reqF_11_c_r ; - assign wci_respTimrAct_11$EN = - WILL_FIRE_RL_wci_wrkBusy_11 && - (!wci_respTimr_11_742_ULT_1_SL_wci_wTimeout_11_7_ETC___d5840 || - wci_wciResponse_11$wget[33:32] != 2'd0) || - wci_reqF_11_c_r ; - - // register wci_respTimrAct_12 - assign wci_respTimrAct_12$D_IN = wci_reqF_12_c_r ; - assign wci_respTimrAct_12$EN = - WILL_FIRE_RL_wci_wrkBusy_12 && - (!wci_respTimr_12_882_ULT_1_SL_wci_wTimeout_12_8_ETC___d5841 || - wci_wciResponse_12$wget[33:32] != 2'd0) || - wci_reqF_12_c_r ; - - // register wci_respTimrAct_13 - assign wci_respTimrAct_13$D_IN = wci_reqF_13_c_r ; - assign wci_respTimrAct_13$EN = - WILL_FIRE_RL_wci_wrkBusy_13 && - (!wci_respTimr_13_022_ULT_1_SL_wci_wTimeout_13_0_ETC___d5842 || - wci_wciResponse_13$wget[33:32] != 2'd0) || - wci_reqF_13_c_r ; - - // register wci_respTimrAct_14 - assign wci_respTimrAct_14$D_IN = wci_reqF_14_c_r ; - assign wci_respTimrAct_14$EN = - WILL_FIRE_RL_wci_wrkBusy_14 && - (!wci_respTimr_14_162_ULT_1_SL_wci_wTimeout_14_1_ETC___d5843 || - wci_wciResponse_14$wget[33:32] != 2'd0) || - wci_reqF_14_c_r ; - - // register wci_respTimrAct_2 - assign wci_respTimrAct_2$D_IN = wci_reqF_2_c_r ; - assign wci_respTimrAct_2$EN = - WILL_FIRE_RL_wci_wrkBusy_2 && - (!wci_respTimr_2_82_ULT_1_SL_wci_wTimeout_2_83_84___d5831 || - wci_wciResponse_2$wget[33:32] != 2'd0) || - wci_reqF_2_c_r ; - - // register wci_respTimrAct_3 - assign wci_respTimrAct_3$D_IN = wci_reqF_3_c_r ; - assign wci_respTimrAct_3$EN = - WILL_FIRE_RL_wci_wrkBusy_3 && - (!wci_respTimr_3_22_ULT_1_SL_wci_wTimeout_3_23_24___d5832 || - wci_wciResponse_3$wget[33:32] != 2'd0) || - wci_reqF_3_c_r ; - - // register wci_respTimrAct_4 - assign wci_respTimrAct_4$D_IN = wci_reqF_4_c_r ; - assign wci_respTimrAct_4$EN = - WILL_FIRE_RL_wci_wrkBusy_4 && - (!wci_respTimr_4_62_ULT_1_SL_wci_wTimeout_4_63_64___d5833 || - wci_wciResponse_4$wget[33:32] != 2'd0) || - wci_reqF_4_c_r ; - - // register wci_respTimrAct_5 - assign wci_respTimrAct_5$D_IN = wci_reqF_5_c_r ; - assign wci_respTimrAct_5$EN = - WILL_FIRE_RL_wci_wrkBusy_5 && - (!wci_respTimr_5_02_ULT_1_SL_wci_wTimeout_5_03_04___d5834 || - wci_wciResponse_5$wget[33:32] != 2'd0) || - wci_reqF_5_c_r ; - - // register wci_respTimrAct_6 - assign wci_respTimrAct_6$D_IN = wci_reqF_6_c_r ; - assign wci_respTimrAct_6$EN = - WILL_FIRE_RL_wci_wrkBusy_6 && - (!wci_respTimr_6_042_ULT_1_SL_wci_wTimeout_6_043_ETC___d5835 || - wci_wciResponse_6$wget[33:32] != 2'd0) || - wci_reqF_6_c_r ; - - // register wci_respTimrAct_7 - assign wci_respTimrAct_7$D_IN = wci_reqF_7_c_r ; - assign wci_respTimrAct_7$EN = - WILL_FIRE_RL_wci_wrkBusy_7 && - (!wci_respTimr_7_182_ULT_1_SL_wci_wTimeout_7_183_ETC___d5836 || - wci_wciResponse_7$wget[33:32] != 2'd0) || - wci_reqF_7_c_r ; - - // register wci_respTimrAct_8 - assign wci_respTimrAct_8$D_IN = wci_reqF_8_c_r ; - assign wci_respTimrAct_8$EN = - WILL_FIRE_RL_wci_wrkBusy_8 && - (!wci_respTimr_8_322_ULT_1_SL_wci_wTimeout_8_323_ETC___d5837 || - wci_wciResponse_8$wget[33:32] != 2'd0) || - wci_reqF_8_c_r ; - - // register wci_respTimrAct_9 - assign wci_respTimrAct_9$D_IN = wci_reqF_9_c_r ; - assign wci_respTimrAct_9$EN = - WILL_FIRE_RL_wci_wrkBusy_9 && - (!wci_respTimr_9_462_ULT_1_SL_wci_wTimeout_9_463_ETC___d5838 || - wci_wciResponse_9$wget[33:32] != 2'd0) || - wci_reqF_9_c_r ; - - // register wci_respTimr_1 - assign wci_respTimr_1$D_IN = - wci_reqF_1_c_r ? 32'd0 : MUX_wci_respTimr_1$write_1__VAL_2 ; - assign wci_respTimr_1$EN = WILL_FIRE_RL_wci_wrkBusy_1 || wci_reqF_1_c_r ; - - // register wci_respTimr_10 - assign wci_respTimr_10$D_IN = - wci_reqF_10_c_r ? 32'd0 : MUX_wci_respTimr_10$write_1__VAL_2 ; - assign wci_respTimr_10$EN = WILL_FIRE_RL_wci_wrkBusy_10 || wci_reqF_10_c_r ; - - // register wci_respTimr_11 - assign wci_respTimr_11$D_IN = - wci_reqF_11_c_r ? 32'd0 : MUX_wci_respTimr_11$write_1__VAL_2 ; - assign wci_respTimr_11$EN = WILL_FIRE_RL_wci_wrkBusy_11 || wci_reqF_11_c_r ; - - // register wci_respTimr_12 - assign wci_respTimr_12$D_IN = - wci_reqF_12_c_r ? 32'd0 : MUX_wci_respTimr_12$write_1__VAL_2 ; - assign wci_respTimr_12$EN = WILL_FIRE_RL_wci_wrkBusy_12 || wci_reqF_12_c_r ; - - // register wci_respTimr_13 - assign wci_respTimr_13$D_IN = - wci_reqF_13_c_r ? 32'd0 : MUX_wci_respTimr_13$write_1__VAL_2 ; - assign wci_respTimr_13$EN = WILL_FIRE_RL_wci_wrkBusy_13 || wci_reqF_13_c_r ; - - // register wci_respTimr_14 - assign wci_respTimr_14$D_IN = - wci_reqF_14_c_r ? 32'd0 : MUX_wci_respTimr_14$write_1__VAL_2 ; - assign wci_respTimr_14$EN = WILL_FIRE_RL_wci_wrkBusy_14 || wci_reqF_14_c_r ; - - // register wci_respTimr_2 - assign wci_respTimr_2$D_IN = - wci_reqF_2_c_r ? 32'd0 : MUX_wci_respTimr_2$write_1__VAL_2 ; - assign wci_respTimr_2$EN = WILL_FIRE_RL_wci_wrkBusy_2 || wci_reqF_2_c_r ; - - // register wci_respTimr_3 - assign wci_respTimr_3$D_IN = - wci_reqF_3_c_r ? 32'd0 : MUX_wci_respTimr_3$write_1__VAL_2 ; - assign wci_respTimr_3$EN = WILL_FIRE_RL_wci_wrkBusy_3 || wci_reqF_3_c_r ; - - // register wci_respTimr_4 - assign wci_respTimr_4$D_IN = - wci_reqF_4_c_r ? 32'd0 : MUX_wci_respTimr_4$write_1__VAL_2 ; - assign wci_respTimr_4$EN = WILL_FIRE_RL_wci_wrkBusy_4 || wci_reqF_4_c_r ; - - // register wci_respTimr_5 - assign wci_respTimr_5$D_IN = - wci_reqF_5_c_r ? 32'd0 : MUX_wci_respTimr_5$write_1__VAL_2 ; - assign wci_respTimr_5$EN = WILL_FIRE_RL_wci_wrkBusy_5 || wci_reqF_5_c_r ; - - // register wci_respTimr_6 - assign wci_respTimr_6$D_IN = - wci_reqF_6_c_r ? 32'd0 : MUX_wci_respTimr_6$write_1__VAL_2 ; - assign wci_respTimr_6$EN = WILL_FIRE_RL_wci_wrkBusy_6 || wci_reqF_6_c_r ; - - // register wci_respTimr_7 - assign wci_respTimr_7$D_IN = - wci_reqF_7_c_r ? 32'd0 : MUX_wci_respTimr_7$write_1__VAL_2 ; - assign wci_respTimr_7$EN = WILL_FIRE_RL_wci_wrkBusy_7 || wci_reqF_7_c_r ; - - // register wci_respTimr_8 - assign wci_respTimr_8$D_IN = - wci_reqF_8_c_r ? 32'd0 : MUX_wci_respTimr_8$write_1__VAL_2 ; - assign wci_respTimr_8$EN = WILL_FIRE_RL_wci_wrkBusy_8 || wci_reqF_8_c_r ; - - // register wci_respTimr_9 - assign wci_respTimr_9$D_IN = - wci_reqF_9_c_r ? 32'd0 : MUX_wci_respTimr_9$write_1__VAL_2 ; - assign wci_respTimr_9$EN = WILL_FIRE_RL_wci_wrkBusy_9 || wci_reqF_9_c_r ; - - // register wci_sThreadBusy_d - assign wci_sThreadBusy_d$D_IN = wci_Vm_0_SThreadBusy ; - assign wci_sThreadBusy_d$EN = 1'd1 ; - - // register wci_sThreadBusy_d_1 - assign wci_sThreadBusy_d_1$D_IN = wci_Vm_1_SThreadBusy ; - assign wci_sThreadBusy_d_1$EN = 1'd1 ; - - // register wci_sThreadBusy_d_10 - assign wci_sThreadBusy_d_10$D_IN = wci_Vm_10_SThreadBusy ; - assign wci_sThreadBusy_d_10$EN = 1'd1 ; - - // register wci_sThreadBusy_d_11 - assign wci_sThreadBusy_d_11$D_IN = wci_Vm_11_SThreadBusy ; - assign wci_sThreadBusy_d_11$EN = 1'd1 ; - - // register wci_sThreadBusy_d_12 - assign wci_sThreadBusy_d_12$D_IN = wci_Vm_12_SThreadBusy ; - assign wci_sThreadBusy_d_12$EN = 1'd1 ; - - // register wci_sThreadBusy_d_13 - assign wci_sThreadBusy_d_13$D_IN = wci_Vm_13_SThreadBusy ; - assign wci_sThreadBusy_d_13$EN = 1'd1 ; - - // register wci_sThreadBusy_d_14 - assign wci_sThreadBusy_d_14$D_IN = wci_Vm_14_SThreadBusy ; - assign wci_sThreadBusy_d_14$EN = 1'd1 ; - - // register wci_sThreadBusy_d_2 - assign wci_sThreadBusy_d_2$D_IN = wci_Vm_2_SThreadBusy ; - assign wci_sThreadBusy_d_2$EN = 1'd1 ; - - // register wci_sThreadBusy_d_3 - assign wci_sThreadBusy_d_3$D_IN = wci_Vm_3_SThreadBusy ; - assign wci_sThreadBusy_d_3$EN = 1'd1 ; - - // register wci_sThreadBusy_d_4 - assign wci_sThreadBusy_d_4$D_IN = wci_Vm_4_SThreadBusy ; - assign wci_sThreadBusy_d_4$EN = 1'd1 ; - - // register wci_sThreadBusy_d_5 - assign wci_sThreadBusy_d_5$D_IN = wci_Vm_5_SThreadBusy ; - assign wci_sThreadBusy_d_5$EN = 1'd1 ; - - // register wci_sThreadBusy_d_6 - assign wci_sThreadBusy_d_6$D_IN = wci_Vm_6_SThreadBusy ; - assign wci_sThreadBusy_d_6$EN = 1'd1 ; - - // register wci_sThreadBusy_d_7 - assign wci_sThreadBusy_d_7$D_IN = wci_Vm_7_SThreadBusy ; - assign wci_sThreadBusy_d_7$EN = 1'd1 ; - - // register wci_sThreadBusy_d_8 - assign wci_sThreadBusy_d_8$D_IN = wci_Vm_8_SThreadBusy ; - assign wci_sThreadBusy_d_8$EN = 1'd1 ; - - // register wci_sThreadBusy_d_9 - assign wci_sThreadBusy_d_9$D_IN = wci_Vm_9_SThreadBusy ; - assign wci_sThreadBusy_d_9$EN = 1'd1 ; - - // register wci_sfCap - assign wci_sfCap$D_IN = wci_sfCapSet ; - assign wci_sfCap$EN = wci_sfCapSet || wci_sfCapClear ; - - // register wci_sfCapClear - assign wci_sfCapClear$D_IN = wci_sfCapClear_1$whas ; - assign wci_sfCapClear$EN = 1'd1 ; - - // register wci_sfCapClear_10 - assign wci_sfCapClear_10$D_IN = wci_sfCapClear_10_1$whas ; - assign wci_sfCapClear_10$EN = 1'd1 ; - - // register wci_sfCapClear_11 - assign wci_sfCapClear_11$D_IN = wci_sfCapClear_11_1$whas ; - assign wci_sfCapClear_11$EN = 1'd1 ; - - // register wci_sfCapClear_12 - assign wci_sfCapClear_12$D_IN = wci_sfCapClear_12_1$whas ; - assign wci_sfCapClear_12$EN = 1'd1 ; - - // register wci_sfCapClear_13 - assign wci_sfCapClear_13$D_IN = wci_sfCapClear_13_1$whas ; - assign wci_sfCapClear_13$EN = 1'd1 ; - - // register wci_sfCapClear_14 - assign wci_sfCapClear_14$D_IN = wci_sfCapClear_14_1$whas ; - assign wci_sfCapClear_14$EN = 1'd1 ; - - // register wci_sfCapClear_1_1 - assign wci_sfCapClear_1_1$D_IN = wci_sfCapClear_1_2$whas ; - assign wci_sfCapClear_1_1$EN = 1'd1 ; - - // register wci_sfCapClear_2 - assign wci_sfCapClear_2$D_IN = wci_sfCapClear_2_1$whas ; - assign wci_sfCapClear_2$EN = 1'd1 ; - - // register wci_sfCapClear_3 - assign wci_sfCapClear_3$D_IN = wci_sfCapClear_3_1$whas ; - assign wci_sfCapClear_3$EN = 1'd1 ; - - // register wci_sfCapClear_4 - assign wci_sfCapClear_4$D_IN = wci_sfCapClear_4_1$whas ; - assign wci_sfCapClear_4$EN = 1'd1 ; - - // register wci_sfCapClear_5 - assign wci_sfCapClear_5$D_IN = wci_sfCapClear_5_1$whas ; - assign wci_sfCapClear_5$EN = 1'd1 ; - - // register wci_sfCapClear_6 - assign wci_sfCapClear_6$D_IN = wci_sfCapClear_6_1$whas ; - assign wci_sfCapClear_6$EN = 1'd1 ; - - // register wci_sfCapClear_7 - assign wci_sfCapClear_7$D_IN = wci_sfCapClear_7_1$whas ; - assign wci_sfCapClear_7$EN = 1'd1 ; - - // register wci_sfCapClear_8 - assign wci_sfCapClear_8$D_IN = wci_sfCapClear_8_1$whas ; - assign wci_sfCapClear_8$EN = 1'd1 ; - - // register wci_sfCapClear_9 - assign wci_sfCapClear_9$D_IN = wci_sfCapClear_9_1$whas ; - assign wci_sfCapClear_9$EN = 1'd1 ; - - // register wci_sfCapSet - assign wci_sfCapSet$D_IN = wci_Vm_0_SFlag[0] ; - assign wci_sfCapSet$EN = 1'd1 ; - - // register wci_sfCapSet_10 - assign wci_sfCapSet_10$D_IN = wci_Vm_10_SFlag[0] ; - assign wci_sfCapSet_10$EN = 1'd1 ; - - // register wci_sfCapSet_11 - assign wci_sfCapSet_11$D_IN = wci_Vm_11_SFlag[0] ; - assign wci_sfCapSet_11$EN = 1'd1 ; - - // register wci_sfCapSet_12 - assign wci_sfCapSet_12$D_IN = wci_Vm_12_SFlag[0] ; - assign wci_sfCapSet_12$EN = 1'd1 ; - - // register wci_sfCapSet_13 - assign wci_sfCapSet_13$D_IN = wci_Vm_13_SFlag[0] ; - assign wci_sfCapSet_13$EN = 1'd1 ; - - // register wci_sfCapSet_14 - assign wci_sfCapSet_14$D_IN = wci_Vm_14_SFlag[0] ; - assign wci_sfCapSet_14$EN = 1'd1 ; - - // register wci_sfCapSet_1_1 - assign wci_sfCapSet_1_1$D_IN = wci_Vm_1_SFlag[0] ; - assign wci_sfCapSet_1_1$EN = 1'd1 ; - - // register wci_sfCapSet_2 - assign wci_sfCapSet_2$D_IN = wci_Vm_2_SFlag[0] ; - assign wci_sfCapSet_2$EN = 1'd1 ; - - // register wci_sfCapSet_3 - assign wci_sfCapSet_3$D_IN = wci_Vm_3_SFlag[0] ; - assign wci_sfCapSet_3$EN = 1'd1 ; - - // register wci_sfCapSet_4 - assign wci_sfCapSet_4$D_IN = wci_Vm_4_SFlag[0] ; - assign wci_sfCapSet_4$EN = 1'd1 ; - - // register wci_sfCapSet_5 - assign wci_sfCapSet_5$D_IN = wci_Vm_5_SFlag[0] ; - assign wci_sfCapSet_5$EN = 1'd1 ; - - // register wci_sfCapSet_6 - assign wci_sfCapSet_6$D_IN = wci_Vm_6_SFlag[0] ; - assign wci_sfCapSet_6$EN = 1'd1 ; - - // register wci_sfCapSet_7 - assign wci_sfCapSet_7$D_IN = wci_Vm_7_SFlag[0] ; - assign wci_sfCapSet_7$EN = 1'd1 ; - - // register wci_sfCapSet_8 - assign wci_sfCapSet_8$D_IN = wci_Vm_8_SFlag[0] ; - assign wci_sfCapSet_8$EN = 1'd1 ; - - // register wci_sfCapSet_9 - assign wci_sfCapSet_9$D_IN = wci_Vm_9_SFlag[0] ; - assign wci_sfCapSet_9$EN = 1'd1 ; - - // register wci_sfCap_1 - assign wci_sfCap_1$D_IN = wci_sfCapSet_1_1 ; - assign wci_sfCap_1$EN = wci_sfCapSet_1_1 || wci_sfCapClear_1_1 ; - - // register wci_sfCap_10 - assign wci_sfCap_10$D_IN = wci_sfCapSet_10 ; - assign wci_sfCap_10$EN = wci_sfCapSet_10 || wci_sfCapClear_10 ; - - // register wci_sfCap_11 - assign wci_sfCap_11$D_IN = wci_sfCapSet_11 ; - assign wci_sfCap_11$EN = wci_sfCapSet_11 || wci_sfCapClear_11 ; - - // register wci_sfCap_12 - assign wci_sfCap_12$D_IN = wci_sfCapSet_12 ; - assign wci_sfCap_12$EN = wci_sfCapSet_12 || wci_sfCapClear_12 ; - - // register wci_sfCap_13 - assign wci_sfCap_13$D_IN = wci_sfCapSet_13 ; - assign wci_sfCap_13$EN = wci_sfCapSet_13 || wci_sfCapClear_13 ; - - // register wci_sfCap_14 - assign wci_sfCap_14$D_IN = wci_sfCapSet_14 ; - assign wci_sfCap_14$EN = wci_sfCapSet_14 || wci_sfCapClear_14 ; - - // register wci_sfCap_2 - assign wci_sfCap_2$D_IN = wci_sfCapSet_2 ; - assign wci_sfCap_2$EN = wci_sfCapSet_2 || wci_sfCapClear_2 ; - - // register wci_sfCap_3 - assign wci_sfCap_3$D_IN = wci_sfCapSet_3 ; - assign wci_sfCap_3$EN = wci_sfCapSet_3 || wci_sfCapClear_3 ; - - // register wci_sfCap_4 - assign wci_sfCap_4$D_IN = wci_sfCapSet_4 ; - assign wci_sfCap_4$EN = wci_sfCapSet_4 || wci_sfCapClear_4 ; - - // register wci_sfCap_5 - assign wci_sfCap_5$D_IN = wci_sfCapSet_5 ; - assign wci_sfCap_5$EN = wci_sfCapSet_5 || wci_sfCapClear_5 ; - - // register wci_sfCap_6 - assign wci_sfCap_6$D_IN = wci_sfCapSet_6 ; - assign wci_sfCap_6$EN = wci_sfCapSet_6 || wci_sfCapClear_6 ; - - // register wci_sfCap_7 - assign wci_sfCap_7$D_IN = wci_sfCapSet_7 ; - assign wci_sfCap_7$EN = wci_sfCapSet_7 || wci_sfCapClear_7 ; - - // register wci_sfCap_8 - assign wci_sfCap_8$D_IN = wci_sfCapSet_8 ; - assign wci_sfCap_8$EN = wci_sfCapSet_8 || wci_sfCapClear_8 ; - - // register wci_sfCap_9 - assign wci_sfCap_9$D_IN = wci_sfCapSet_9 ; - assign wci_sfCap_9$EN = wci_sfCapSet_9 || wci_sfCapClear_9 ; - - // register wci_slvPresent - assign wci_slvPresent$D_IN = wci_Vm_0_SFlag[1] ; - assign wci_slvPresent$EN = 1'd1 ; - - // register wci_slvPresent_1 - assign wci_slvPresent_1$D_IN = wci_Vm_1_SFlag[1] ; - assign wci_slvPresent_1$EN = 1'd1 ; - - // register wci_slvPresent_10 - assign wci_slvPresent_10$D_IN = wci_Vm_10_SFlag[1] ; - assign wci_slvPresent_10$EN = 1'd1 ; - - // register wci_slvPresent_11 - assign wci_slvPresent_11$D_IN = wci_Vm_11_SFlag[1] ; - assign wci_slvPresent_11$EN = 1'd1 ; - - // register wci_slvPresent_12 - assign wci_slvPresent_12$D_IN = wci_Vm_12_SFlag[1] ; - assign wci_slvPresent_12$EN = 1'd1 ; - - // register wci_slvPresent_13 - assign wci_slvPresent_13$D_IN = wci_Vm_13_SFlag[1] ; - assign wci_slvPresent_13$EN = 1'd1 ; - - // register wci_slvPresent_14 - assign wci_slvPresent_14$D_IN = wci_Vm_14_SFlag[1] ; - assign wci_slvPresent_14$EN = 1'd1 ; - - // register wci_slvPresent_2 - assign wci_slvPresent_2$D_IN = wci_Vm_2_SFlag[1] ; - assign wci_slvPresent_2$EN = 1'd1 ; - - // register wci_slvPresent_3 - assign wci_slvPresent_3$D_IN = wci_Vm_3_SFlag[1] ; - assign wci_slvPresent_3$EN = 1'd1 ; - - // register wci_slvPresent_4 - assign wci_slvPresent_4$D_IN = wci_Vm_4_SFlag[1] ; - assign wci_slvPresent_4$EN = 1'd1 ; - - // register wci_slvPresent_5 - assign wci_slvPresent_5$D_IN = wci_Vm_5_SFlag[1] ; - assign wci_slvPresent_5$EN = 1'd1 ; - - // register wci_slvPresent_6 - assign wci_slvPresent_6$D_IN = wci_Vm_6_SFlag[1] ; - assign wci_slvPresent_6$EN = 1'd1 ; - - // register wci_slvPresent_7 - assign wci_slvPresent_7$D_IN = wci_Vm_7_SFlag[1] ; - assign wci_slvPresent_7$EN = 1'd1 ; - - // register wci_slvPresent_8 - assign wci_slvPresent_8$D_IN = wci_Vm_8_SFlag[1] ; - assign wci_slvPresent_8$EN = 1'd1 ; - - // register wci_slvPresent_9 - assign wci_slvPresent_9$D_IN = wci_Vm_9_SFlag[1] ; - assign wci_slvPresent_9$EN = 1'd1 ; - - // register wci_wReset_n - assign wci_wReset_n$D_IN = cpReq[59] ; - assign wci_wReset_n$EN = - WILL_FIRE_RL_cpDispatch_F_F_T_T_F_F_T_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_T_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_T_F_F_T_T_T ; - - // register wci_wReset_n_1 - assign wci_wReset_n_1$D_IN = cpReq[59] ; - assign wci_wReset_n_1$EN = - WILL_FIRE_RL_cpDispatch_F_F_T_F_T_F_F_T_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_T_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_T_F_F_T_T_T ; - - // register wci_wReset_n_10 - assign wci_wReset_n_10$D_IN = cpReq[59] ; - assign wci_wReset_n_10$EN = - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_T ; - - // register wci_wReset_n_11 - assign wci_wReset_n_11$D_IN = cpReq[59] ; - assign wci_wReset_n_11$EN = - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_T ; - - // register wci_wReset_n_12 - assign wci_wReset_n_12$D_IN = cpReq[59] ; - assign wci_wReset_n_12$EN = - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_T ; - - // register wci_wReset_n_13 - assign wci_wReset_n_13$D_IN = cpReq[59] ; - assign wci_wReset_n_13$EN = - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_T ; - - // register wci_wReset_n_14 - assign wci_wReset_n_14$D_IN = cpReq[59] ; - assign wci_wReset_n_14$EN = - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_T ; - - // register wci_wReset_n_2 - assign wci_wReset_n_2$D_IN = cpReq[59] ; - assign wci_wReset_n_2$EN = - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_F_F_T_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_F_F_T_T_T ; - - // register wci_wReset_n_3 - assign wci_wReset_n_3$D_IN = cpReq[59] ; - assign wci_wReset_n_3$EN = - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_F_F_T_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_F_F_T_T_T ; - - // register wci_wReset_n_4 - assign wci_wReset_n_4$D_IN = cpReq[59] ; - assign wci_wReset_n_4$EN = - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_F_F_T_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_F_F_T_T_T ; - - // register wci_wReset_n_5 - assign wci_wReset_n_5$D_IN = cpReq[59] ; - assign wci_wReset_n_5$EN = - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_F_T_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_F_T_T_T ; - - // register wci_wReset_n_6 - assign wci_wReset_n_6$D_IN = cpReq[59] ; - assign wci_wReset_n_6$EN = - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_F_F_T_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_F_F_T_T_T ; - - // register wci_wReset_n_7 - assign wci_wReset_n_7$D_IN = cpReq[59] ; - assign wci_wReset_n_7$EN = - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_F_F_T_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_F_F_T_T_T ; - - // register wci_wReset_n_8 - assign wci_wReset_n_8$D_IN = cpReq[59] ; - assign wci_wReset_n_8$EN = - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_F_F_T_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_F_F_T_T_T ; - - // register wci_wReset_n_9 - assign wci_wReset_n_9$D_IN = cpReq[59] ; - assign wci_wReset_n_9$EN = - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_F_F_T_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_F_F_T_T_T ; - - // register wci_wStatus - assign wci_wStatus$D_IN = + assign wci_9_reqTO$EN = + WILL_FIRE_RL_wci_9_wrkBusy && + wci_9_wciResponse_wget__483_BITS_33_TO_32_484__ETC___d1512 || + WILL_FIRE_RL_cpDispatch_F_F_T_E9_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E9_F_F_T_T_T ; + + // register wci_9_respTimr + assign wci_9_respTimr$D_IN = + wci_9_reqF_cntr_r ? 32'd0 : MUX_wci_9_respTimr$write_1__VAL_2 ; + assign wci_9_respTimr$EN = WILL_FIRE_RL_wci_9_wrkBusy || wci_9_reqF_cntr_r ; + + // register wci_9_respTimrAct + assign wci_9_respTimrAct$D_IN = wci_9_reqF_cntr_r ; + assign wci_9_respTimrAct$EN = + WILL_FIRE_RL_wci_9_wrkBusy && + (!wci_9_respTimr_488_ULT_1_SL_wci_9_wTimeout_489_ETC___d1491 || + wci_9_wciResponse$wget[33:32] != 2'd0) || + wci_9_reqF_cntr_r ; + + // register wci_9_sThreadBusy_d + assign wci_9_sThreadBusy_d$D_IN = wci_Vm_9_SThreadBusy ; + assign wci_9_sThreadBusy_d$EN = 1'd1 ; + + // register wci_9_sfCap + assign wci_9_sfCap$D_IN = wci_9_sfCapSet ; + assign wci_9_sfCap$EN = wci_9_sfCapSet || wci_9_sfCapClear ; + + // register wci_9_sfCapClear + assign wci_9_sfCapClear$D_IN = wci_9_sfCapClear_1$whas ; + assign wci_9_sfCapClear$EN = 1'd1 ; + + // register wci_9_sfCapSet + assign wci_9_sfCapSet$D_IN = wci_Vm_9_SFlag[0] ; + assign wci_9_sfCapSet$EN = 1'd1 ; + + // register wci_9_slvPresent + assign wci_9_slvPresent$D_IN = wci_Vm_9_SFlag[1] ; + assign wci_9_slvPresent$EN = 1'd1 ; + + // register wci_9_wReset_n + assign wci_9_wReset_n$D_IN = cpReq[59] ; + assign wci_9_wReset_n$EN = + WILL_FIRE_RL_cpDispatch_F_F_T_E9_F_F_T_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E9_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E9_F_F_T_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E9_F_F_T_T_T ; + + // register wci_9_wStatus + assign wci_9_wStatus$D_IN = { 4'b0, - !wci_lastOpWrite[1] || wci_lastOpWrite[0], - IF_wci_lastControlOp_87_BIT_3_88_THEN_wci_last_ETC___d302 } ; - assign wci_wStatus$EN = 1'd1 ; - - // register wci_wStatus_1 - assign wci_wStatus_1$D_IN = - { 4'b0, - !wci_lastOpWrite_1[1] || wci_lastOpWrite_1[0], - IF_wci_lastControlOp_1_27_BIT_3_28_THEN_wci_la_ETC___d442 } ; - assign wci_wStatus_1$EN = 1'd1 ; - - // register wci_wStatus_10 - assign wci_wStatus_10$D_IN = - { 4'b0, - !wci_lastOpWrite_10[1] || wci_lastOpWrite_10[0], - IF_wci_lastControlOp_10_687_BIT_3_688_THEN_wci_ETC___d1702 } ; - assign wci_wStatus_10$EN = 1'd1 ; - - // register wci_wStatus_11 - assign wci_wStatus_11$D_IN = - { 4'b0, - !wci_lastOpWrite_11[1] || wci_lastOpWrite_11[0], - IF_wci_lastControlOp_11_827_BIT_3_828_THEN_wci_ETC___d1842 } ; - assign wci_wStatus_11$EN = 1'd1 ; - - // register wci_wStatus_12 - assign wci_wStatus_12$D_IN = - { 4'b0, - !wci_lastOpWrite_12[1] || wci_lastOpWrite_12[0], - IF_wci_lastControlOp_12_967_BIT_3_968_THEN_wci_ETC___d1982 } ; - assign wci_wStatus_12$EN = 1'd1 ; - - // register wci_wStatus_13 - assign wci_wStatus_13$D_IN = - { 4'b0, - !wci_lastOpWrite_13[1] || wci_lastOpWrite_13[0], - IF_wci_lastControlOp_13_107_BIT_3_108_THEN_wci_ETC___d2122 } ; - assign wci_wStatus_13$EN = 1'd1 ; - - // register wci_wStatus_14 - assign wci_wStatus_14$D_IN = - { 4'b0, - !wci_lastOpWrite_14[1] || wci_lastOpWrite_14[0], - IF_wci_lastControlOp_14_247_BIT_3_248_THEN_wci_ETC___d2262 } ; - assign wci_wStatus_14$EN = 1'd1 ; - - // register wci_wStatus_2 - assign wci_wStatus_2$D_IN = - { 4'b0, - !wci_lastOpWrite_2[1] || wci_lastOpWrite_2[0], - IF_wci_lastControlOp_2_67_BIT_3_68_THEN_wci_la_ETC___d582 } ; - assign wci_wStatus_2$EN = 1'd1 ; - - // register wci_wStatus_3 - assign wci_wStatus_3$D_IN = - { 4'b0, - !wci_lastOpWrite_3[1] || wci_lastOpWrite_3[0], - IF_wci_lastControlOp_3_07_BIT_3_08_THEN_wci_la_ETC___d722 } ; - assign wci_wStatus_3$EN = 1'd1 ; - - // register wci_wStatus_4 - assign wci_wStatus_4$D_IN = - { 4'b0, - !wci_lastOpWrite_4[1] || wci_lastOpWrite_4[0], - IF_wci_lastControlOp_4_47_BIT_3_48_THEN_wci_la_ETC___d862 } ; - assign wci_wStatus_4$EN = 1'd1 ; - - // register wci_wStatus_5 - assign wci_wStatus_5$D_IN = - { 4'b0, - !wci_lastOpWrite_5[1] || wci_lastOpWrite_5[0], - IF_wci_lastControlOp_5_87_BIT_3_88_THEN_wci_la_ETC___d1002 } ; - assign wci_wStatus_5$EN = 1'd1 ; - - // register wci_wStatus_6 - assign wci_wStatus_6$D_IN = - { 4'b0, - !wci_lastOpWrite_6[1] || wci_lastOpWrite_6[0], - IF_wci_lastControlOp_6_127_BIT_3_128_THEN_wci__ETC___d1142 } ; - assign wci_wStatus_6$EN = 1'd1 ; - - // register wci_wStatus_7 - assign wci_wStatus_7$D_IN = - { 4'b0, - !wci_lastOpWrite_7[1] || wci_lastOpWrite_7[0], - IF_wci_lastControlOp_7_267_BIT_3_268_THEN_wci__ETC___d1282 } ; - assign wci_wStatus_7$EN = 1'd1 ; - - // register wci_wStatus_8 - assign wci_wStatus_8$D_IN = - { 4'b0, - !wci_lastOpWrite_8[1] || wci_lastOpWrite_8[0], - IF_wci_lastControlOp_8_407_BIT_3_408_THEN_wci__ETC___d1422 } ; - assign wci_wStatus_8$EN = 1'd1 ; - - // register wci_wStatus_9 - assign wci_wStatus_9$D_IN = - { 4'b0, - !wci_lastOpWrite_9[1] || wci_lastOpWrite_9[0], - IF_wci_lastControlOp_9_547_BIT_3_548_THEN_wci__ETC___d1562 } ; - assign wci_wStatus_9$EN = 1'd1 ; - - // register wci_wTimeout - assign wci_wTimeout$D_IN = cpReq[32:28] ; - assign wci_wTimeout$EN = - WILL_FIRE_RL_cpDispatch_F_F_T_T_F_F_T_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_T_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_T_F_F_T_T_T ; - - // register wci_wTimeout_1 - assign wci_wTimeout_1$D_IN = cpReq[32:28] ; - assign wci_wTimeout_1$EN = - WILL_FIRE_RL_cpDispatch_F_F_T_F_T_F_F_T_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_T_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_T_F_F_T_T_T ; - - // register wci_wTimeout_10 - assign wci_wTimeout_10$D_IN = cpReq[32:28] ; - assign wci_wTimeout_10$EN = - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_T ; - - // register wci_wTimeout_11 - assign wci_wTimeout_11$D_IN = cpReq[32:28] ; - assign wci_wTimeout_11$EN = - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_T ; - - // register wci_wTimeout_12 - assign wci_wTimeout_12$D_IN = cpReq[32:28] ; - assign wci_wTimeout_12$EN = - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_T ; - - // register wci_wTimeout_13 - assign wci_wTimeout_13$D_IN = cpReq[32:28] ; - assign wci_wTimeout_13$EN = - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_T ; - - // register wci_wTimeout_14 - assign wci_wTimeout_14$D_IN = cpReq[32:28] ; - assign wci_wTimeout_14$EN = - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_T ; - - // register wci_wTimeout_2 - assign wci_wTimeout_2$D_IN = cpReq[32:28] ; - assign wci_wTimeout_2$EN = - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_F_F_T_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_F_F_T_T_T ; - - // register wci_wTimeout_3 - assign wci_wTimeout_3$D_IN = cpReq[32:28] ; - assign wci_wTimeout_3$EN = - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_F_F_T_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_F_F_T_T_T ; - - // register wci_wTimeout_4 - assign wci_wTimeout_4$D_IN = cpReq[32:28] ; - assign wci_wTimeout_4$EN = - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_F_F_T_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_F_F_T_T_T ; - - // register wci_wTimeout_5 - assign wci_wTimeout_5$D_IN = cpReq[32:28] ; - assign wci_wTimeout_5$EN = - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_F_T_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_F_T_T_T ; - - // register wci_wTimeout_6 - assign wci_wTimeout_6$D_IN = cpReq[32:28] ; - assign wci_wTimeout_6$EN = - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_F_F_T_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_F_F_T_T_T ; - - // register wci_wTimeout_7 - assign wci_wTimeout_7$D_IN = cpReq[32:28] ; - assign wci_wTimeout_7$EN = - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_F_F_T_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_F_F_T_T_T ; - - // register wci_wTimeout_8 - assign wci_wTimeout_8$D_IN = cpReq[32:28] ; - assign wci_wTimeout_8$EN = - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_F_F_T_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_F_F_T_T_T ; - - // register wci_wTimeout_9 - assign wci_wTimeout_9$D_IN = cpReq[32:28] ; - assign wci_wTimeout_9$EN = - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_F_F_T_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_F_F_T_T_T ; + !wci_9_lastOpWrite[1] || wci_9_lastOpWrite[0], + IF_wci_9_lastControlOp_573_BIT_3_574_THEN_wci__ETC___d1588 } ; + assign wci_9_wStatus$EN = 1'd1 ; + + // register wci_9_wTimeout + assign wci_9_wTimeout$D_IN = cpReq[32:28] ; + assign wci_9_wTimeout$EN = + WILL_FIRE_RL_cpDispatch_F_F_T_E9_F_F_T_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E9_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E9_F_F_T_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E9_F_F_T_T_T ; // register wrkAct always@(MUX_wrkAct$write_1__SEL_1 or - _theResult_____1__h75857 or + _theResult_____1__h75724 or MUX_wrkAct$write_1__SEL_2 or - _theResult_____1__h75875 or MUX_wrkAct$write_1__SEL_3) + _theResult_____1__h75739 or MUX_wrkAct$write_1__SEL_3) begin case (1'b1) // synopsys parallel_case - MUX_wrkAct$write_1__SEL_1: wrkAct$D_IN = _theResult_____1__h75857; - MUX_wrkAct$write_1__SEL_2: wrkAct$D_IN = _theResult_____1__h75875; + MUX_wrkAct$write_1__SEL_1: wrkAct$D_IN = _theResult_____1__h75724; + MUX_wrkAct$write_1__SEL_2: wrkAct$D_IN = _theResult_____1__h75739; MUX_wrkAct$write_1__SEL_3: wrkAct$D_IN = 4'd0; default: wrkAct$D_IN = 4'b1010 /* unspecified value */ ; endcase end assign wrkAct$EN = - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_F_F_T_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_F_F_T_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_F_F_T_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_F_F_T_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_F_T_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_F_F_T_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_F_F_T_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_F_F_T_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_T_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_T_F_F_T_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_T_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_T_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_T_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_T_F_F_T_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_T_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_T_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_T_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_F_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_F_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_F_F_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_F_F_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_F_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_F_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_F_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_F_F_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_F_F_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_F_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_F_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_F_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_F_F_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_F_F_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_F_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_F_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_F_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_T_F_F_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_T_F_F_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_T_F_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_T_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_T_F_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_T_F_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_T_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_OOB || + WILL_FIRE_RL_cpDispatch_F_F_T_E14_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E14_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E14_F_F_T_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E14_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E14_F_F_T_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E14_F_F_T_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E14_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E14_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E14_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E13_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E13_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E13_F_F_T_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E13_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E13_F_F_T_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E13_F_F_T_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E13_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E13_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E13_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E12_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E12_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E12_F_F_T_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E12_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E12_F_F_T_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E12_F_F_T_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E12_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E12_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E12_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E11_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E11_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E11_F_F_T_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E11_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E11_F_F_T_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E11_F_F_T_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E11_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E11_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E11_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E10_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E10_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E10_F_F_T_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E10_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E10_F_F_T_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E10_F_F_T_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E10_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E10_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E10_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E9_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E9_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E9_F_F_T_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E9_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E9_F_F_T_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E9_F_F_T_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E9_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E9_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E9_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E8_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E8_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E8_F_F_T_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E8_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E8_F_F_T_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E8_F_F_T_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E8_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E8_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E8_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E7_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E7_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E7_F_F_T_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E7_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E7_F_F_T_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E7_F_F_T_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E7_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E7_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E7_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E6_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E6_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E6_F_F_T_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E6_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E6_F_F_T_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E6_F_F_T_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E6_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E6_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E6_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E5_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E5_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E5_F_F_T_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E5_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E5_F_F_T_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E5_F_F_T_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E5_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E5_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E5_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E4_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E4_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E4_F_F_T_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E4_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E4_F_F_T_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E4_F_F_T_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E4_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E4_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E4_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E3_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E3_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E3_F_F_T_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E3_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E3_F_F_T_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E3_F_F_T_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E3_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E3_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E3_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E2_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E2_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E2_F_F_T_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E2_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E2_F_F_T_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E2_F_F_T_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E2_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E2_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E2_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E1_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E1_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E1_F_F_T_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E1_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E1_F_F_T_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E1_F_F_T_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E1_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E1_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E1_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E0_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E0_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E0_F_F_T_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E0_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E0_F_F_T_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E0_F_F_T_T_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E0_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E0_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E0_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_OOB || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_F_F_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_F_F_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_F_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_F_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_F_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_F_F_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_F_F_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_F_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_F_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_F_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_F_F_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_F_F_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_F_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_F_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_F_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_F_F_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_F_F_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_F_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_F_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_F_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_F_F_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_F_F_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_F_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_F_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_F_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_F_F_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_F_F_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_F_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_F_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_F_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_F_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_F_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_F_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_F_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_F_F_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_F_F_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_F_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_F_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_F_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_F_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_F_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_F_F_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_F_F_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_F_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_F_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_F_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_F_F_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_F_F_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_F_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_F_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_F_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_F_F_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_F_F_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_F_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_F_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_F_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_F_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_F_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_F_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_F_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_T_T || WILL_FIRE_RL_completeWorkerRead || WILL_FIRE_RL_completeWorkerWrite ; @@ -15317,7 +15178,7 @@ module mkOCCP(pciDevice, cpReq[11:4] == 8'h24 || cpReq[11:4] == 8'h28 || cpReq[11:4] == 8'h2C, - IF_cpReq_337_BITS_11_TO_4_340_EQ_0x0_419_THEN__ETC___d6152 } ; + IF_cpReq_363_BITS_11_TO_4_366_EQ_0x0_445_THEN__ETC___d2590 } ; assign adminResp1F$ENQ = WILL_FIRE_RL_cpDispatch_F_T_T_T ; assign adminResp1F$DEQ = WILL_FIRE_RL_readAdminResponseCollect && adminResp1F$EMPTY_N ; @@ -15367,7 +15228,7 @@ module mkOCCP(pciDevice, cpReq[11:4] == 8'hF4 || cpReq[11:4] == 8'hF8 || cpReq[11:4] == 8'hFC, - CASE_cpReq_BITS_9_TO_6_uuid_arg_BITS_31_TO_0_0_ETC__q3 } ; + CASE_cpReq_BITS_9_TO_6_0_uuid_arg_BITS_511_TO__ETC__q3 } ; assign adminResp3F$ENQ = WILL_FIRE_RL_cpDispatch_F_T_T_F_F ; assign adminResp3F$DEQ = WILL_FIRE_RL_readAdminResponseCollect && !adminResp1F$EMPTY_N && @@ -15389,7 +15250,7 @@ module mkOCCP(pciDevice, assign adminRespF$D_IN = adminResp1F$EMPTY_N ? adminResp1F$D_OUT : - IF_adminResp2F_notEmpty__278_THEN_adminResp2F__ETC___d2316 ; + IF_adminResp2F_notEmpty__304_THEN_adminResp2F__ETC___d2342 ; assign adminRespF$ENQ = WILL_FIRE_RL_readAdminResponseCollect && (adminResp1F$EMPTY_N || adminResp2F$EMPTY_N || @@ -15414,6 +15275,12 @@ module mkOCCP(pciDevice, assign cpRespF$DEQ = EN_server_response_get ; assign cpRespF$CLR = 1'b0 ; + // submodule dna_dna + assign dna_dna$CLK = dna_cnt[0] ; + assign dna_dna$DIN = 1'd0 ; + assign dna_dna$READ = dna_rdReg ; + assign dna_dna$SHIFT = dna_shftReg ; + // submodule rom_memory assign rom_memory$ADDR = cpReq[15:6] ; assign rom_memory$DI = 32'd0 ; @@ -15475,1333 +15342,1287 @@ module mkOCCP(pciDevice, assign timeServ_setRefF$sENQ = WILL_FIRE_RL_cpDispatch_T_F_F_F_F_F_F_T ; assign timeServ_setRefF$dDEQ = timeServ_setRefF$dEMPTY_N ; - // submodule wci_mReset - assign wci_mReset$ASSERT_IN = !wci_wReset_n ; - - // submodule wci_mReset_1 - assign wci_mReset_1$ASSERT_IN = !wci_wReset_n_1 ; - - // submodule wci_mReset_10 - assign wci_mReset_10$ASSERT_IN = !wci_wReset_n_10 ; - - // submodule wci_mReset_11 - assign wci_mReset_11$ASSERT_IN = !wci_wReset_n_11 ; - - // submodule wci_mReset_12 - assign wci_mReset_12$ASSERT_IN = !wci_wReset_n_12 ; - - // submodule wci_mReset_13 - assign wci_mReset_13$ASSERT_IN = !wci_wReset_n_13 ; - - // submodule wci_mReset_14 - assign wci_mReset_14$ASSERT_IN = !wci_wReset_n_14 ; - - // submodule wci_mReset_2 - assign wci_mReset_2$ASSERT_IN = !wci_wReset_n_2 ; - - // submodule wci_mReset_3 - assign wci_mReset_3$ASSERT_IN = !wci_wReset_n_3 ; - - // submodule wci_mReset_4 - assign wci_mReset_4$ASSERT_IN = !wci_wReset_n_4 ; - - // submodule wci_mReset_5 - assign wci_mReset_5$ASSERT_IN = !wci_wReset_n_5 ; - - // submodule wci_mReset_6 - assign wci_mReset_6$ASSERT_IN = !wci_wReset_n_6 ; - - // submodule wci_mReset_7 - assign wci_mReset_7$ASSERT_IN = !wci_wReset_n_7 ; - - // submodule wci_mReset_8 - assign wci_mReset_8$ASSERT_IN = !wci_wReset_n_8 ; - - // submodule wci_mReset_9 - assign wci_mReset_9$ASSERT_IN = !wci_wReset_n_9 ; - - // submodule wci_respF - always@(MUX_wci_busy$write_1__SEL_1 or - MUX_wci_respF$enq_1__VAL_1 or - WILL_FIRE_RL_cpDispatch_F_F_F_F_T_F_F_T or - MUX_wci_respF$enq_1__VAL_2 or - WILL_FIRE_RL_cpDispatch_F_F_F_F_T_F_F_F_T or - MUX_wci_respF$enq_1__VAL_3 or - WILL_FIRE_RL_cpDispatch_F_F_F_F_T_F_F_F_F_T or - MUX_wci_respF$enq_1__VAL_4 or - WILL_FIRE_RL_cpDispatch_F_F_F_F_T_F_F_F_F_F_T or - MUX_wci_respF$enq_1__VAL_5 or - MUX_wci_respF$enq_1__SEL_6 or - MUX_wci_respF$enq_1__SEL_7 or WILL_FIRE_RL_cpDispatch_F_F_T_T_F_T) + // submodule wci_0_mReset + assign wci_0_mReset$ASSERT_IN = !wci_0_wReset_n ; + + // submodule wci_0_respF + always@(MUX_wci_0_busy$write_1__SEL_1 or + MUX_wci_0_respF$enq_1__VAL_1 or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_F_T or + MUX_wci_0_respF$enq_1__VAL_2 or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_F_F_T or + MUX_wci_0_respF$enq_1__VAL_3 or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_F_F_F_T or + MUX_wci_0_respF$enq_1__VAL_4 or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_F_F_F_F_T or + MUX_wci_0_respF$enq_1__VAL_5 or + MUX_wci_0_respF$enq_1__SEL_6 or + MUX_wci_0_respF$enq_1__SEL_7 or + WILL_FIRE_RL_cpDispatch_F_F_T_E0_F_T) begin case (1'b1) // synopsys parallel_case - MUX_wci_busy$write_1__SEL_1: - wci_respF$D_IN = MUX_wci_respF$enq_1__VAL_1; - WILL_FIRE_RL_cpDispatch_F_F_F_F_T_F_F_T: - wci_respF$D_IN = MUX_wci_respF$enq_1__VAL_2; - WILL_FIRE_RL_cpDispatch_F_F_F_F_T_F_F_F_T: - wci_respF$D_IN = MUX_wci_respF$enq_1__VAL_3; - WILL_FIRE_RL_cpDispatch_F_F_F_F_T_F_F_F_F_T: - wci_respF$D_IN = MUX_wci_respF$enq_1__VAL_4; - WILL_FIRE_RL_cpDispatch_F_F_F_F_T_F_F_F_F_F_T: - wci_respF$D_IN = MUX_wci_respF$enq_1__VAL_5; - MUX_wci_respF$enq_1__SEL_6: wci_respF$D_IN = 34'h100000000; - MUX_wci_respF$enq_1__SEL_7: wci_respF$D_IN = 34'h1C0DE4204; - WILL_FIRE_RL_cpDispatch_F_F_T_T_F_T: wci_respF$D_IN = 34'h3C0DE4202; - default: wci_respF$D_IN = 34'h2AAAAAAAA /* unspecified value */ ; + MUX_wci_0_busy$write_1__SEL_1: + wci_0_respF$D_IN = MUX_wci_0_respF$enq_1__VAL_1; + WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_F_T: + wci_0_respF$D_IN = MUX_wci_0_respF$enq_1__VAL_2; + WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_F_F_T: + wci_0_respF$D_IN = MUX_wci_0_respF$enq_1__VAL_3; + WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_F_F_F_T: + wci_0_respF$D_IN = MUX_wci_0_respF$enq_1__VAL_4; + WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_F_F_F_F_T: + wci_0_respF$D_IN = MUX_wci_0_respF$enq_1__VAL_5; + MUX_wci_0_respF$enq_1__SEL_6: wci_0_respF$D_IN = 34'h100000000; + MUX_wci_0_respF$enq_1__SEL_7: wci_0_respF$D_IN = 34'h1C0DE4204; + WILL_FIRE_RL_cpDispatch_F_F_T_E0_F_T: wci_0_respF$D_IN = 34'h3C0DE4202; + default: wci_0_respF$D_IN = 34'h2AAAAAAAA /* unspecified value */ ; endcase end - assign wci_respF$ENQ = - WILL_FIRE_RL_wci_wrkBusy && - (!wci_respTimr_02_ULT_1_SL_wci_wTimeout_03_04___d5829 || - wci_wciResponse$wget[33:32] != 2'd0) || - WILL_FIRE_RL_cpDispatch_F_F_F_F_T_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_T_F_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_T_F_F_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_T_F_F_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_T_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_T_F_F_T_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_T_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_T_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_T_F_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_T_F_T ; - assign wci_respF$DEQ = MUX_wrkAct$write_1__SEL_3 && wrkAct == 4'd0 ; - assign wci_respF$CLR = 1'b0 ; - - // submodule wci_respF_1 - always@(MUX_wci_busy_1$write_1__SEL_1 or - MUX_wci_respF_1$enq_1__VAL_1 or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_F_F_T or - MUX_wci_respF_1$enq_1__VAL_2 or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_F_F_F_T or - MUX_wci_respF_1$enq_1__VAL_3 or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_F_F_F_F_T or - MUX_wci_respF_1$enq_1__VAL_4 or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_F_F_F_F_F_T or - MUX_wci_respF_1$enq_1__VAL_5 or - MUX_wci_respF_1$enq_1__SEL_6 or - MUX_wci_respF_1$enq_1__SEL_7 or - WILL_FIRE_RL_cpDispatch_F_F_T_F_T_F_T) + assign wci_0_respF$ENQ = + WILL_FIRE_RL_wci_0_wrkBusy && + (!wci_0_respTimr_28_ULT_1_SL_wci_0_wTimeout_29_30___d231 || + wci_0_wciResponse$wget[33:32] != 2'd0) || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_F_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_F_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E0_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E0_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E0_F_F_T_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E0_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E0_F_F_T_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E0_F_F_T_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E0_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E0_F_T ; + assign wci_0_respF$DEQ = MUX_wrkAct$write_1__SEL_3 && wrkAct == 4'd0 ; + assign wci_0_respF$CLR = 1'b0 ; + + // submodule wci_10_mReset + assign wci_10_mReset$ASSERT_IN = !wci_10_wReset_n ; + + // submodule wci_10_respF + always@(MUX_wci_10_busy$write_1__SEL_1 or + MUX_wci_10_respF$enq_1__VAL_1 or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_F_F_T or + MUX_wci_10_respF$enq_1__VAL_2 or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_F_F_F_T or + MUX_wci_10_respF$enq_1__VAL_3 or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_F_F_F_F_T or + MUX_wci_10_respF$enq_1__VAL_4 or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_F_F_F_F_F_T or + MUX_wci_10_respF$enq_1__VAL_5 or + MUX_wci_10_respF$enq_1__SEL_6 or + MUX_wci_10_respF$enq_1__SEL_7 or + WILL_FIRE_RL_cpDispatch_F_F_T_E10_F_T) begin case (1'b1) // synopsys parallel_case - MUX_wci_busy_1$write_1__SEL_1: - wci_respF_1$D_IN = MUX_wci_respF_1$enq_1__VAL_1; - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_F_F_T: - wci_respF_1$D_IN = MUX_wci_respF_1$enq_1__VAL_2; - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_F_F_F_T: - wci_respF_1$D_IN = MUX_wci_respF_1$enq_1__VAL_3; - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_F_F_F_F_T: - wci_respF_1$D_IN = MUX_wci_respF_1$enq_1__VAL_4; - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_F_F_F_F_F_T: - wci_respF_1$D_IN = MUX_wci_respF_1$enq_1__VAL_5; - MUX_wci_respF_1$enq_1__SEL_6: wci_respF_1$D_IN = 34'h100000000; - MUX_wci_respF_1$enq_1__SEL_7: wci_respF_1$D_IN = 34'h1C0DE4204; - WILL_FIRE_RL_cpDispatch_F_F_T_F_T_F_T: wci_respF_1$D_IN = 34'h3C0DE4202; - default: wci_respF_1$D_IN = 34'h2AAAAAAAA /* unspecified value */ ; + MUX_wci_10_busy$write_1__SEL_1: + wci_10_respF$D_IN = MUX_wci_10_respF$enq_1__VAL_1; + WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_F_F_T: + wci_10_respF$D_IN = MUX_wci_10_respF$enq_1__VAL_2; + WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_F_F_F_T: + wci_10_respF$D_IN = MUX_wci_10_respF$enq_1__VAL_3; + WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_F_F_F_F_T: + wci_10_respF$D_IN = MUX_wci_10_respF$enq_1__VAL_4; + WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_F_F_F_F_F_T: + wci_10_respF$D_IN = MUX_wci_10_respF$enq_1__VAL_5; + MUX_wci_10_respF$enq_1__SEL_6: wci_10_respF$D_IN = 34'h100000000; + MUX_wci_10_respF$enq_1__SEL_7: wci_10_respF$D_IN = 34'h1C0DE4204; + WILL_FIRE_RL_cpDispatch_F_F_T_E10_F_T: + wci_10_respF$D_IN = 34'h3C0DE4202; + default: wci_10_respF$D_IN = 34'h2AAAAAAAA /* unspecified value */ ; endcase end - assign wci_respF_1$ENQ = - WILL_FIRE_RL_wci_wrkBusy_1 && - (!wci_respTimr_1_42_ULT_1_SL_wci_wTimeout_1_43_44___d5830 || - wci_wciResponse_1$wget[33:32] != 2'd0) || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_F_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_F_F_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_F_F_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_T_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_T_F_F_T_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_T_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_T_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_F_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_T_F_T ; - assign wci_respF_1$DEQ = MUX_wrkAct$write_1__SEL_3 && wrkAct == 4'd1 ; - assign wci_respF_1$CLR = 1'b0 ; - - // submodule wci_respF_10 - always@(MUX_wci_busy_10$write_1__SEL_1 or - MUX_wci_respF_10$enq_1__VAL_1 or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T or - MUX_wci_respF_10$enq_1__VAL_2 or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T or - MUX_wci_respF_10$enq_1__VAL_3 or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T or - MUX_wci_respF_10$enq_1__VAL_4 or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T or - MUX_wci_respF_10$enq_1__VAL_5 or - MUX_wci_respF_10$enq_1__SEL_6 or - MUX_wci_respF_10$enq_1__SEL_7 or - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_T) + assign wci_10_respF$ENQ = + WILL_FIRE_RL_wci_10_wrkBusy && + (!wci_10_respTimr_628_ULT_1_SL_wci_10_wTimeout_6_ETC___d1631 || + wci_10_wciResponse$wget[33:32] != 2'd0) || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_F_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_F_F_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_F_F_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E10_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E10_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E10_F_F_T_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E10_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E10_F_F_T_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E10_F_F_T_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_F_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E10_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E10_F_T ; + assign wci_10_respF$DEQ = MUX_wrkAct$write_1__SEL_3 && wrkAct == 4'd10 ; + assign wci_10_respF$CLR = 1'b0 ; + + // submodule wci_11_mReset + assign wci_11_mReset$ASSERT_IN = !wci_11_wReset_n ; + + // submodule wci_11_respF + always@(MUX_wci_11_busy$write_1__SEL_1 or + MUX_wci_11_respF$enq_1__VAL_1 or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_F_F_T or + MUX_wci_11_respF$enq_1__VAL_2 or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_F_F_F_T or + MUX_wci_11_respF$enq_1__VAL_3 or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_F_F_F_F_T or + MUX_wci_11_respF$enq_1__VAL_4 or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_F_F_F_F_F_T or + MUX_wci_11_respF$enq_1__VAL_5 or + MUX_wci_11_respF$enq_1__SEL_6 or + MUX_wci_11_respF$enq_1__SEL_7 or + WILL_FIRE_RL_cpDispatch_F_F_T_E11_F_T) begin case (1'b1) // synopsys parallel_case - MUX_wci_busy_10$write_1__SEL_1: - wci_respF_10$D_IN = MUX_wci_respF_10$enq_1__VAL_1; - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T: - wci_respF_10$D_IN = MUX_wci_respF_10$enq_1__VAL_2; - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T: - wci_respF_10$D_IN = MUX_wci_respF_10$enq_1__VAL_3; - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T: - wci_respF_10$D_IN = MUX_wci_respF_10$enq_1__VAL_4; - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T: - wci_respF_10$D_IN = MUX_wci_respF_10$enq_1__VAL_5; - MUX_wci_respF_10$enq_1__SEL_6: wci_respF_10$D_IN = 34'h100000000; - MUX_wci_respF_10$enq_1__SEL_7: wci_respF_10$D_IN = 34'h1C0DE4204; - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_T: - wci_respF_10$D_IN = 34'h3C0DE4202; - default: wci_respF_10$D_IN = 34'h2AAAAAAAA /* unspecified value */ ; + MUX_wci_11_busy$write_1__SEL_1: + wci_11_respF$D_IN = MUX_wci_11_respF$enq_1__VAL_1; + WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_F_F_T: + wci_11_respF$D_IN = MUX_wci_11_respF$enq_1__VAL_2; + WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_F_F_F_T: + wci_11_respF$D_IN = MUX_wci_11_respF$enq_1__VAL_3; + WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_F_F_F_F_T: + wci_11_respF$D_IN = MUX_wci_11_respF$enq_1__VAL_4; + WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_F_F_F_F_F_T: + wci_11_respF$D_IN = MUX_wci_11_respF$enq_1__VAL_5; + MUX_wci_11_respF$enq_1__SEL_6: wci_11_respF$D_IN = 34'h100000000; + MUX_wci_11_respF$enq_1__SEL_7: wci_11_respF$D_IN = 34'h1C0DE4204; + WILL_FIRE_RL_cpDispatch_F_F_T_E11_F_T: + wci_11_respF$D_IN = 34'h3C0DE4202; + default: wci_11_respF$D_IN = 34'h2AAAAAAAA /* unspecified value */ ; endcase end - assign wci_respF_10$ENQ = - WILL_FIRE_RL_wci_wrkBusy_10 && - (!wci_respTimr_10_602_ULT_1_SL_wci_wTimeout_10_6_ETC___d5839 || - wci_wciResponse_10$wget[33:32] != 2'd0) || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_T ; - assign wci_respF_10$DEQ = MUX_wrkAct$write_1__SEL_3 && wrkAct == 4'd10 ; - assign wci_respF_10$CLR = 1'b0 ; - - // submodule wci_respF_11 - always@(MUX_wci_busy_11$write_1__SEL_1 or - MUX_wci_respF_11$enq_1__VAL_1 or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T or - MUX_wci_respF_11$enq_1__VAL_2 or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T or - MUX_wci_respF_11$enq_1__VAL_3 or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T or - MUX_wci_respF_11$enq_1__VAL_4 or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T or - MUX_wci_respF_11$enq_1__VAL_5 or - MUX_wci_respF_11$enq_1__SEL_6 or - MUX_wci_respF_11$enq_1__SEL_7 or - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_F_T) + assign wci_11_respF$ENQ = + WILL_FIRE_RL_wci_11_wrkBusy && + (!wci_11_respTimr_768_ULT_1_SL_wci_11_wTimeout_7_ETC___d1771 || + wci_11_wciResponse$wget[33:32] != 2'd0) || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_F_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_F_F_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_F_F_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E11_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E11_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E11_F_F_T_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E11_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E11_F_F_T_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E11_F_F_T_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_F_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E11_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E11_F_T ; + assign wci_11_respF$DEQ = MUX_wrkAct$write_1__SEL_3 && wrkAct == 4'd11 ; + assign wci_11_respF$CLR = 1'b0 ; + + // submodule wci_12_mReset + assign wci_12_mReset$ASSERT_IN = !wci_12_wReset_n ; + + // submodule wci_12_respF + always@(MUX_wci_12_busy$write_1__SEL_1 or + MUX_wci_12_respF$enq_1__VAL_1 or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_F_F_T or + MUX_wci_12_respF$enq_1__VAL_2 or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_F_F_F_T or + MUX_wci_12_respF$enq_1__VAL_3 or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_F_F_F_F_T or + MUX_wci_12_respF$enq_1__VAL_4 or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_F_F_F_F_F_T or + MUX_wci_12_respF$enq_1__VAL_5 or + MUX_wci_12_respF$enq_1__SEL_6 or + MUX_wci_12_respF$enq_1__SEL_7 or + WILL_FIRE_RL_cpDispatch_F_F_T_E12_F_T) begin case (1'b1) // synopsys parallel_case - MUX_wci_busy_11$write_1__SEL_1: - wci_respF_11$D_IN = MUX_wci_respF_11$enq_1__VAL_1; - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T: - wci_respF_11$D_IN = MUX_wci_respF_11$enq_1__VAL_2; - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T: - wci_respF_11$D_IN = MUX_wci_respF_11$enq_1__VAL_3; - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T: - wci_respF_11$D_IN = MUX_wci_respF_11$enq_1__VAL_4; - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T: - wci_respF_11$D_IN = MUX_wci_respF_11$enq_1__VAL_5; - MUX_wci_respF_11$enq_1__SEL_6: wci_respF_11$D_IN = 34'h100000000; - MUX_wci_respF_11$enq_1__SEL_7: wci_respF_11$D_IN = 34'h1C0DE4204; - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_F_T: - wci_respF_11$D_IN = 34'h3C0DE4202; - default: wci_respF_11$D_IN = 34'h2AAAAAAAA /* unspecified value */ ; + MUX_wci_12_busy$write_1__SEL_1: + wci_12_respF$D_IN = MUX_wci_12_respF$enq_1__VAL_1; + WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_F_F_T: + wci_12_respF$D_IN = MUX_wci_12_respF$enq_1__VAL_2; + WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_F_F_F_T: + wci_12_respF$D_IN = MUX_wci_12_respF$enq_1__VAL_3; + WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_F_F_F_F_T: + wci_12_respF$D_IN = MUX_wci_12_respF$enq_1__VAL_4; + WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_F_F_F_F_F_T: + wci_12_respF$D_IN = MUX_wci_12_respF$enq_1__VAL_5; + MUX_wci_12_respF$enq_1__SEL_6: wci_12_respF$D_IN = 34'h100000000; + MUX_wci_12_respF$enq_1__SEL_7: wci_12_respF$D_IN = 34'h1C0DE4204; + WILL_FIRE_RL_cpDispatch_F_F_T_E12_F_T: + wci_12_respF$D_IN = 34'h3C0DE4202; + default: wci_12_respF$D_IN = 34'h2AAAAAAAA /* unspecified value */ ; endcase end - assign wci_respF_11$ENQ = - WILL_FIRE_RL_wci_wrkBusy_11 && - (!wci_respTimr_11_742_ULT_1_SL_wci_wTimeout_11_7_ETC___d5840 || - wci_wciResponse_11$wget[33:32] != 2'd0) || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_F_T ; - assign wci_respF_11$DEQ = MUX_wrkAct$write_1__SEL_3 && wrkAct == 4'd11 ; - assign wci_respF_11$CLR = 1'b0 ; - - // submodule wci_respF_12 - always@(MUX_wci_busy_12$write_1__SEL_1 or - MUX_wci_respF_12$enq_1__VAL_1 or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T or - MUX_wci_respF_12$enq_1__VAL_2 or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T or - MUX_wci_respF_12$enq_1__VAL_3 or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T or - MUX_wci_respF_12$enq_1__VAL_4 or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T or - MUX_wci_respF_12$enq_1__VAL_5 or - MUX_wci_respF_12$enq_1__SEL_6 or - MUX_wci_respF_12$enq_1__SEL_7 or - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T) + assign wci_12_respF$ENQ = + WILL_FIRE_RL_wci_12_wrkBusy && + (!wci_12_respTimr_908_ULT_1_SL_wci_12_wTimeout_9_ETC___d1911 || + wci_12_wciResponse$wget[33:32] != 2'd0) || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_F_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_F_F_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_F_F_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E12_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E12_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E12_F_F_T_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E12_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E12_F_F_T_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E12_F_F_T_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_F_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E12_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E12_F_T ; + assign wci_12_respF$DEQ = MUX_wrkAct$write_1__SEL_3 && wrkAct == 4'd12 ; + assign wci_12_respF$CLR = 1'b0 ; + + // submodule wci_13_mReset + assign wci_13_mReset$ASSERT_IN = !wci_13_wReset_n ; + + // submodule wci_13_respF + always@(MUX_wci_13_busy$write_1__SEL_1 or + MUX_wci_13_respF$enq_1__VAL_1 or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_F_F_T or + MUX_wci_13_respF$enq_1__VAL_2 or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_F_F_F_T or + MUX_wci_13_respF$enq_1__VAL_3 or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_F_F_F_F_T or + MUX_wci_13_respF$enq_1__VAL_4 or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_F_F_F_F_F_T or + MUX_wci_13_respF$enq_1__VAL_5 or + MUX_wci_13_respF$enq_1__SEL_6 or + MUX_wci_13_respF$enq_1__SEL_7 or + WILL_FIRE_RL_cpDispatch_F_F_T_E13_F_T) begin case (1'b1) // synopsys parallel_case - MUX_wci_busy_12$write_1__SEL_1: - wci_respF_12$D_IN = MUX_wci_respF_12$enq_1__VAL_1; - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T: - wci_respF_12$D_IN = MUX_wci_respF_12$enq_1__VAL_2; - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T: - wci_respF_12$D_IN = MUX_wci_respF_12$enq_1__VAL_3; - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T: - wci_respF_12$D_IN = MUX_wci_respF_12$enq_1__VAL_4; - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T: - wci_respF_12$D_IN = MUX_wci_respF_12$enq_1__VAL_5; - MUX_wci_respF_12$enq_1__SEL_6: wci_respF_12$D_IN = 34'h100000000; - MUX_wci_respF_12$enq_1__SEL_7: wci_respF_12$D_IN = 34'h1C0DE4204; - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T: - wci_respF_12$D_IN = 34'h3C0DE4202; - default: wci_respF_12$D_IN = 34'h2AAAAAAAA /* unspecified value */ ; + MUX_wci_13_busy$write_1__SEL_1: + wci_13_respF$D_IN = MUX_wci_13_respF$enq_1__VAL_1; + WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_F_F_T: + wci_13_respF$D_IN = MUX_wci_13_respF$enq_1__VAL_2; + WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_F_F_F_T: + wci_13_respF$D_IN = MUX_wci_13_respF$enq_1__VAL_3; + WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_F_F_F_F_T: + wci_13_respF$D_IN = MUX_wci_13_respF$enq_1__VAL_4; + WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_F_F_F_F_F_T: + wci_13_respF$D_IN = MUX_wci_13_respF$enq_1__VAL_5; + MUX_wci_13_respF$enq_1__SEL_6: wci_13_respF$D_IN = 34'h100000000; + MUX_wci_13_respF$enq_1__SEL_7: wci_13_respF$D_IN = 34'h1C0DE4204; + WILL_FIRE_RL_cpDispatch_F_F_T_E13_F_T: + wci_13_respF$D_IN = 34'h3C0DE4202; + default: wci_13_respF$D_IN = 34'h2AAAAAAAA /* unspecified value */ ; endcase end - assign wci_respF_12$ENQ = - WILL_FIRE_RL_wci_wrkBusy_12 && - (!wci_respTimr_12_882_ULT_1_SL_wci_wTimeout_12_8_ETC___d5841 || - wci_wciResponse_12$wget[33:32] != 2'd0) || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T ; - assign wci_respF_12$DEQ = MUX_wrkAct$write_1__SEL_3 && wrkAct == 4'd12 ; - assign wci_respF_12$CLR = 1'b0 ; - - // submodule wci_respF_13 - always@(MUX_wci_busy_13$write_1__SEL_1 or - MUX_wci_respF_13$enq_1__VAL_1 or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T or - MUX_wci_respF_13$enq_1__VAL_2 or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T or - MUX_wci_respF_13$enq_1__VAL_3 or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T or - MUX_wci_respF_13$enq_1__VAL_4 or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T or - MUX_wci_respF_13$enq_1__VAL_5 or - MUX_wci_respF_13$enq_1__SEL_6 or - MUX_wci_respF_13$enq_1__SEL_7 or - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T) + assign wci_13_respF$ENQ = + WILL_FIRE_RL_wci_13_wrkBusy && + (!wci_13_respTimr_048_ULT_1_SL_wci_13_wTimeout_0_ETC___d2051 || + wci_13_wciResponse$wget[33:32] != 2'd0) || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_F_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_F_F_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_F_F_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E13_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E13_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E13_F_F_T_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E13_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E13_F_F_T_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E13_F_F_T_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_F_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E13_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E13_F_T ; + assign wci_13_respF$DEQ = MUX_wrkAct$write_1__SEL_3 && wrkAct == 4'd13 ; + assign wci_13_respF$CLR = 1'b0 ; + + // submodule wci_14_mReset + assign wci_14_mReset$ASSERT_IN = !wci_14_wReset_n ; + + // submodule wci_14_respF + always@(MUX_wci_14_busy$write_1__SEL_1 or + MUX_wci_14_respF$enq_1__VAL_1 or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_F_F_T or + MUX_wci_14_respF$enq_1__VAL_2 or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_F_F_F_T or + MUX_wci_14_respF$enq_1__VAL_3 or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_F_F_F_F_T or + MUX_wci_14_respF$enq_1__VAL_4 or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_F_F_F_F_F_T or + MUX_wci_14_respF$enq_1__VAL_5 or + MUX_wci_14_respF$enq_1__SEL_6 or + MUX_wci_14_respF$enq_1__SEL_7 or + WILL_FIRE_RL_cpDispatch_F_F_T_E14_F_T) begin case (1'b1) // synopsys parallel_case - MUX_wci_busy_13$write_1__SEL_1: - wci_respF_13$D_IN = MUX_wci_respF_13$enq_1__VAL_1; - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T: - wci_respF_13$D_IN = MUX_wci_respF_13$enq_1__VAL_2; - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T: - wci_respF_13$D_IN = MUX_wci_respF_13$enq_1__VAL_3; - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T: - wci_respF_13$D_IN = MUX_wci_respF_13$enq_1__VAL_4; - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T: - wci_respF_13$D_IN = MUX_wci_respF_13$enq_1__VAL_5; - MUX_wci_respF_13$enq_1__SEL_6: wci_respF_13$D_IN = 34'h100000000; - MUX_wci_respF_13$enq_1__SEL_7: wci_respF_13$D_IN = 34'h1C0DE4204; - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T: - wci_respF_13$D_IN = 34'h3C0DE4202; - default: wci_respF_13$D_IN = 34'h2AAAAAAAA /* unspecified value */ ; + MUX_wci_14_busy$write_1__SEL_1: + wci_14_respF$D_IN = MUX_wci_14_respF$enq_1__VAL_1; + WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_F_F_T: + wci_14_respF$D_IN = MUX_wci_14_respF$enq_1__VAL_2; + WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_F_F_F_T: + wci_14_respF$D_IN = MUX_wci_14_respF$enq_1__VAL_3; + WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_F_F_F_F_T: + wci_14_respF$D_IN = MUX_wci_14_respF$enq_1__VAL_4; + WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_F_F_F_F_F_T: + wci_14_respF$D_IN = MUX_wci_14_respF$enq_1__VAL_5; + MUX_wci_14_respF$enq_1__SEL_6: wci_14_respF$D_IN = 34'h100000000; + MUX_wci_14_respF$enq_1__SEL_7: wci_14_respF$D_IN = 34'h1C0DE4204; + WILL_FIRE_RL_cpDispatch_F_F_T_E14_F_T: + wci_14_respF$D_IN = 34'h3C0DE4202; + default: wci_14_respF$D_IN = 34'h2AAAAAAAA /* unspecified value */ ; endcase end - assign wci_respF_13$ENQ = - WILL_FIRE_RL_wci_wrkBusy_13 && - (!wci_respTimr_13_022_ULT_1_SL_wci_wTimeout_13_0_ETC___d5842 || - wci_wciResponse_13$wget[33:32] != 2'd0) || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T ; - assign wci_respF_13$DEQ = MUX_wrkAct$write_1__SEL_3 && wrkAct == 4'd13 ; - assign wci_respF_13$CLR = 1'b0 ; - - // submodule wci_respF_14 - always@(MUX_wci_busy_14$write_1__SEL_1 or - MUX_wci_respF_14$enq_1__VAL_1 or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T or - MUX_wci_respF_14$enq_1__VAL_2 or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T or - MUX_wci_respF_14$enq_1__VAL_3 or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T or - MUX_wci_respF_14$enq_1__VAL_4 or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T or - MUX_wci_respF_14$enq_1__VAL_5 or - MUX_wci_respF_14$enq_1__SEL_6 or - MUX_wci_respF_14$enq_1__SEL_7 or - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T) + assign wci_14_respF$ENQ = + WILL_FIRE_RL_wci_14_wrkBusy && + (!wci_14_respTimr_188_ULT_1_SL_wci_14_wTimeout_1_ETC___d2191 || + wci_14_wciResponse$wget[33:32] != 2'd0) || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_F_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_F_F_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_F_F_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E14_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E14_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E14_F_F_T_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E14_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E14_F_F_T_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E14_F_F_T_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_F_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E14_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E14_F_T ; + assign wci_14_respF$DEQ = MUX_wrkAct$write_1__SEL_3 && wrkAct == 4'd14 ; + assign wci_14_respF$CLR = 1'b0 ; + + // submodule wci_1_mReset + assign wci_1_mReset$ASSERT_IN = !wci_1_wReset_n ; + + // submodule wci_1_respF + always@(MUX_wci_1_busy$write_1__SEL_1 or + MUX_wci_1_respF$enq_1__VAL_1 or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_F_T or + MUX_wci_1_respF$enq_1__VAL_2 or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_F_F_T or + MUX_wci_1_respF$enq_1__VAL_3 or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_F_F_F_T or + MUX_wci_1_respF$enq_1__VAL_4 or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_F_F_F_F_T or + MUX_wci_1_respF$enq_1__VAL_5 or + MUX_wci_1_respF$enq_1__SEL_6 or + MUX_wci_1_respF$enq_1__SEL_7 or + WILL_FIRE_RL_cpDispatch_F_F_T_E1_F_T) begin case (1'b1) // synopsys parallel_case - MUX_wci_busy_14$write_1__SEL_1: - wci_respF_14$D_IN = MUX_wci_respF_14$enq_1__VAL_1; - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T: - wci_respF_14$D_IN = MUX_wci_respF_14$enq_1__VAL_2; - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T: - wci_respF_14$D_IN = MUX_wci_respF_14$enq_1__VAL_3; - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T: - wci_respF_14$D_IN = MUX_wci_respF_14$enq_1__VAL_4; - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T: - wci_respF_14$D_IN = MUX_wci_respF_14$enq_1__VAL_5; - MUX_wci_respF_14$enq_1__SEL_6: wci_respF_14$D_IN = 34'h100000000; - MUX_wci_respF_14$enq_1__SEL_7: wci_respF_14$D_IN = 34'h1C0DE4204; - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T: - wci_respF_14$D_IN = 34'h3C0DE4202; - default: wci_respF_14$D_IN = 34'h2AAAAAAAA /* unspecified value */ ; + MUX_wci_1_busy$write_1__SEL_1: + wci_1_respF$D_IN = MUX_wci_1_respF$enq_1__VAL_1; + WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_F_T: + wci_1_respF$D_IN = MUX_wci_1_respF$enq_1__VAL_2; + WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_F_F_T: + wci_1_respF$D_IN = MUX_wci_1_respF$enq_1__VAL_3; + WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_F_F_F_T: + wci_1_respF$D_IN = MUX_wci_1_respF$enq_1__VAL_4; + WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_F_F_F_F_T: + wci_1_respF$D_IN = MUX_wci_1_respF$enq_1__VAL_5; + MUX_wci_1_respF$enq_1__SEL_6: wci_1_respF$D_IN = 34'h100000000; + MUX_wci_1_respF$enq_1__SEL_7: wci_1_respF$D_IN = 34'h1C0DE4204; + WILL_FIRE_RL_cpDispatch_F_F_T_E1_F_T: wci_1_respF$D_IN = 34'h3C0DE4202; + default: wci_1_respF$D_IN = 34'h2AAAAAAAA /* unspecified value */ ; endcase end - assign wci_respF_14$ENQ = - WILL_FIRE_RL_wci_wrkBusy_14 && - (!wci_respTimr_14_162_ULT_1_SL_wci_wTimeout_14_1_ETC___d5843 || - wci_wciResponse_14$wget[33:32] != 2'd0) || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T ; - assign wci_respF_14$DEQ = MUX_wrkAct$write_1__SEL_3 && wrkAct == 4'd14 ; - assign wci_respF_14$CLR = 1'b0 ; - - // submodule wci_respF_2 - always@(MUX_wci_busy_2$write_1__SEL_1 or - MUX_wci_respF_2$enq_1__VAL_1 or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_F_F_T or - MUX_wci_respF_2$enq_1__VAL_2 or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_F_F_F_T or - MUX_wci_respF_2$enq_1__VAL_3 or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_F_F_F_F_T or - MUX_wci_respF_2$enq_1__VAL_4 or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_F_F_F_F_F_T or - MUX_wci_respF_2$enq_1__VAL_5 or - MUX_wci_respF_2$enq_1__SEL_6 or - MUX_wci_respF_2$enq_1__SEL_7 or - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_F_T) + assign wci_1_respF$ENQ = + WILL_FIRE_RL_wci_1_wrkBusy && + (!wci_1_respTimr_68_ULT_1_SL_wci_1_wTimeout_69_70___d371 || + wci_1_wciResponse$wget[33:32] != 2'd0) || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_F_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_F_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E1_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E1_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E1_F_F_T_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E1_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E1_F_F_T_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E1_F_F_T_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E1_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E1_F_T ; + assign wci_1_respF$DEQ = MUX_wrkAct$write_1__SEL_3 && wrkAct == 4'd1 ; + assign wci_1_respF$CLR = 1'b0 ; + + // submodule wci_2_mReset + assign wci_2_mReset$ASSERT_IN = !wci_2_wReset_n ; + + // submodule wci_2_respF + always@(MUX_wci_2_busy$write_1__SEL_1 or + MUX_wci_2_respF$enq_1__VAL_1 or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_F_F_T or + MUX_wci_2_respF$enq_1__VAL_2 or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_F_F_F_T or + MUX_wci_2_respF$enq_1__VAL_3 or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_F_F_F_F_T or + MUX_wci_2_respF$enq_1__VAL_4 or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_F_F_F_F_F_T or + MUX_wci_2_respF$enq_1__VAL_5 or + MUX_wci_2_respF$enq_1__SEL_6 or + MUX_wci_2_respF$enq_1__SEL_7 or + WILL_FIRE_RL_cpDispatch_F_F_T_E2_F_T) begin case (1'b1) // synopsys parallel_case - MUX_wci_busy_2$write_1__SEL_1: - wci_respF_2$D_IN = MUX_wci_respF_2$enq_1__VAL_1; - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_F_F_T: - wci_respF_2$D_IN = MUX_wci_respF_2$enq_1__VAL_2; - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_F_F_F_T: - wci_respF_2$D_IN = MUX_wci_respF_2$enq_1__VAL_3; - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_F_F_F_F_T: - wci_respF_2$D_IN = MUX_wci_respF_2$enq_1__VAL_4; - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_F_F_F_F_F_T: - wci_respF_2$D_IN = MUX_wci_respF_2$enq_1__VAL_5; - MUX_wci_respF_2$enq_1__SEL_6: wci_respF_2$D_IN = 34'h100000000; - MUX_wci_respF_2$enq_1__SEL_7: wci_respF_2$D_IN = 34'h1C0DE4204; - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_F_T: - wci_respF_2$D_IN = 34'h3C0DE4202; - default: wci_respF_2$D_IN = 34'h2AAAAAAAA /* unspecified value */ ; + MUX_wci_2_busy$write_1__SEL_1: + wci_2_respF$D_IN = MUX_wci_2_respF$enq_1__VAL_1; + WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_F_F_T: + wci_2_respF$D_IN = MUX_wci_2_respF$enq_1__VAL_2; + WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_F_F_F_T: + wci_2_respF$D_IN = MUX_wci_2_respF$enq_1__VAL_3; + WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_F_F_F_F_T: + wci_2_respF$D_IN = MUX_wci_2_respF$enq_1__VAL_4; + WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_F_F_F_F_F_T: + wci_2_respF$D_IN = MUX_wci_2_respF$enq_1__VAL_5; + MUX_wci_2_respF$enq_1__SEL_6: wci_2_respF$D_IN = 34'h100000000; + MUX_wci_2_respF$enq_1__SEL_7: wci_2_respF$D_IN = 34'h1C0DE4204; + WILL_FIRE_RL_cpDispatch_F_F_T_E2_F_T: wci_2_respF$D_IN = 34'h3C0DE4202; + default: wci_2_respF$D_IN = 34'h2AAAAAAAA /* unspecified value */ ; endcase end - assign wci_respF_2$ENQ = - WILL_FIRE_RL_wci_wrkBusy_2 && - (!wci_respTimr_2_82_ULT_1_SL_wci_wTimeout_2_83_84___d5831 || - wci_wciResponse_2$wget[33:32] != 2'd0) || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_F_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_F_F_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_F_F_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_F_F_T_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_F_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_F_T ; - assign wci_respF_2$DEQ = MUX_wrkAct$write_1__SEL_3 && wrkAct == 4'd2 ; - assign wci_respF_2$CLR = 1'b0 ; - - // submodule wci_respF_3 - always@(MUX_wci_busy_3$write_1__SEL_1 or - MUX_wci_respF_3$enq_1__VAL_1 or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_F_F_T or - MUX_wci_respF_3$enq_1__VAL_2 or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_F_F_F_T or - MUX_wci_respF_3$enq_1__VAL_3 or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_F_F_F_F_T or - MUX_wci_respF_3$enq_1__VAL_4 or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_F_F_F_F_F_T or - MUX_wci_respF_3$enq_1__VAL_5 or - MUX_wci_respF_3$enq_1__SEL_6 or - MUX_wci_respF_3$enq_1__SEL_7 or - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_F_T) + assign wci_2_respF$ENQ = + WILL_FIRE_RL_wci_2_wrkBusy && + (!wci_2_respTimr_08_ULT_1_SL_wci_2_wTimeout_09_10___d511 || + wci_2_wciResponse$wget[33:32] != 2'd0) || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_F_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_F_F_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_F_F_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E2_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E2_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E2_F_F_T_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E2_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E2_F_F_T_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E2_F_F_T_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_F_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E2_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E2_F_T ; + assign wci_2_respF$DEQ = MUX_wrkAct$write_1__SEL_3 && wrkAct == 4'd2 ; + assign wci_2_respF$CLR = 1'b0 ; + + // submodule wci_3_mReset + assign wci_3_mReset$ASSERT_IN = !wci_3_wReset_n ; + + // submodule wci_3_respF + always@(MUX_wci_3_busy$write_1__SEL_1 or + MUX_wci_3_respF$enq_1__VAL_1 or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_F_F_T or + MUX_wci_3_respF$enq_1__VAL_2 or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_F_F_F_T or + MUX_wci_3_respF$enq_1__VAL_3 or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_F_F_F_F_T or + MUX_wci_3_respF$enq_1__VAL_4 or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_F_F_F_F_F_T or + MUX_wci_3_respF$enq_1__VAL_5 or + MUX_wci_3_respF$enq_1__SEL_6 or + MUX_wci_3_respF$enq_1__SEL_7 or + WILL_FIRE_RL_cpDispatch_F_F_T_E3_F_T) begin case (1'b1) // synopsys parallel_case - MUX_wci_busy_3$write_1__SEL_1: - wci_respF_3$D_IN = MUX_wci_respF_3$enq_1__VAL_1; - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_F_F_T: - wci_respF_3$D_IN = MUX_wci_respF_3$enq_1__VAL_2; - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_F_F_F_T: - wci_respF_3$D_IN = MUX_wci_respF_3$enq_1__VAL_3; - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_F_F_F_F_T: - wci_respF_3$D_IN = MUX_wci_respF_3$enq_1__VAL_4; - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_F_F_F_F_F_T: - wci_respF_3$D_IN = MUX_wci_respF_3$enq_1__VAL_5; - MUX_wci_respF_3$enq_1__SEL_6: wci_respF_3$D_IN = 34'h100000000; - MUX_wci_respF_3$enq_1__SEL_7: wci_respF_3$D_IN = 34'h1C0DE4204; - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_F_T: - wci_respF_3$D_IN = 34'h3C0DE4202; - default: wci_respF_3$D_IN = 34'h2AAAAAAAA /* unspecified value */ ; + MUX_wci_3_busy$write_1__SEL_1: + wci_3_respF$D_IN = MUX_wci_3_respF$enq_1__VAL_1; + WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_F_F_T: + wci_3_respF$D_IN = MUX_wci_3_respF$enq_1__VAL_2; + WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_F_F_F_T: + wci_3_respF$D_IN = MUX_wci_3_respF$enq_1__VAL_3; + WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_F_F_F_F_T: + wci_3_respF$D_IN = MUX_wci_3_respF$enq_1__VAL_4; + WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_F_F_F_F_F_T: + wci_3_respF$D_IN = MUX_wci_3_respF$enq_1__VAL_5; + MUX_wci_3_respF$enq_1__SEL_6: wci_3_respF$D_IN = 34'h100000000; + MUX_wci_3_respF$enq_1__SEL_7: wci_3_respF$D_IN = 34'h1C0DE4204; + WILL_FIRE_RL_cpDispatch_F_F_T_E3_F_T: wci_3_respF$D_IN = 34'h3C0DE4202; + default: wci_3_respF$D_IN = 34'h2AAAAAAAA /* unspecified value */ ; endcase end - assign wci_respF_3$ENQ = - WILL_FIRE_RL_wci_wrkBusy_3 && - (!wci_respTimr_3_22_ULT_1_SL_wci_wTimeout_3_23_24___d5832 || - wci_wciResponse_3$wget[33:32] != 2'd0) || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_F_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_F_F_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_F_F_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_F_F_T_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_F_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_F_T ; - assign wci_respF_3$DEQ = MUX_wrkAct$write_1__SEL_3 && wrkAct == 4'd3 ; - assign wci_respF_3$CLR = 1'b0 ; - - // submodule wci_respF_4 - always@(MUX_wci_busy_4$write_1__SEL_1 or - MUX_wci_respF_4$enq_1__VAL_1 or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_F_T or - MUX_wci_respF_4$enq_1__VAL_2 or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_F_F_T or - MUX_wci_respF_4$enq_1__VAL_3 or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_F_F_F_T or - MUX_wci_respF_4$enq_1__VAL_4 or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T or - MUX_wci_respF_4$enq_1__VAL_5 or - MUX_wci_respF_4$enq_1__SEL_6 or - MUX_wci_respF_4$enq_1__SEL_7 or - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_F_T) + assign wci_3_respF$ENQ = + WILL_FIRE_RL_wci_3_wrkBusy && + (!wci_3_respTimr_48_ULT_1_SL_wci_3_wTimeout_49_50___d651 || + wci_3_wciResponse$wget[33:32] != 2'd0) || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_F_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_F_F_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_F_F_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E3_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E3_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E3_F_F_T_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E3_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E3_F_F_T_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E3_F_F_T_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_F_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E3_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E3_F_T ; + assign wci_3_respF$DEQ = MUX_wrkAct$write_1__SEL_3 && wrkAct == 4'd3 ; + assign wci_3_respF$CLR = 1'b0 ; + + // submodule wci_4_mReset + assign wci_4_mReset$ASSERT_IN = !wci_4_wReset_n ; + + // submodule wci_4_respF + always@(MUX_wci_4_busy$write_1__SEL_1 or + MUX_wci_4_respF$enq_1__VAL_1 or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_F_F_T or + MUX_wci_4_respF$enq_1__VAL_2 or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_F_F_F_T or + MUX_wci_4_respF$enq_1__VAL_3 or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_F_F_F_F_T or + MUX_wci_4_respF$enq_1__VAL_4 or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_F_F_F_F_F_T or + MUX_wci_4_respF$enq_1__VAL_5 or + MUX_wci_4_respF$enq_1__SEL_6 or + MUX_wci_4_respF$enq_1__SEL_7 or + WILL_FIRE_RL_cpDispatch_F_F_T_E4_F_T) begin case (1'b1) // synopsys parallel_case - MUX_wci_busy_4$write_1__SEL_1: - wci_respF_4$D_IN = MUX_wci_respF_4$enq_1__VAL_1; - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_F_T: - wci_respF_4$D_IN = MUX_wci_respF_4$enq_1__VAL_2; - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_F_F_T: - wci_respF_4$D_IN = MUX_wci_respF_4$enq_1__VAL_3; - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_F_F_F_T: - wci_respF_4$D_IN = MUX_wci_respF_4$enq_1__VAL_4; - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T: - wci_respF_4$D_IN = MUX_wci_respF_4$enq_1__VAL_5; - MUX_wci_respF_4$enq_1__SEL_6: wci_respF_4$D_IN = 34'h100000000; - MUX_wci_respF_4$enq_1__SEL_7: wci_respF_4$D_IN = 34'h1C0DE4204; - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_F_T: - wci_respF_4$D_IN = 34'h3C0DE4202; - default: wci_respF_4$D_IN = 34'h2AAAAAAAA /* unspecified value */ ; + MUX_wci_4_busy$write_1__SEL_1: + wci_4_respF$D_IN = MUX_wci_4_respF$enq_1__VAL_1; + WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_F_F_T: + wci_4_respF$D_IN = MUX_wci_4_respF$enq_1__VAL_2; + WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_F_F_F_T: + wci_4_respF$D_IN = MUX_wci_4_respF$enq_1__VAL_3; + WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_F_F_F_F_T: + wci_4_respF$D_IN = MUX_wci_4_respF$enq_1__VAL_4; + WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_F_F_F_F_F_T: + wci_4_respF$D_IN = MUX_wci_4_respF$enq_1__VAL_5; + MUX_wci_4_respF$enq_1__SEL_6: wci_4_respF$D_IN = 34'h100000000; + MUX_wci_4_respF$enq_1__SEL_7: wci_4_respF$D_IN = 34'h1C0DE4204; + WILL_FIRE_RL_cpDispatch_F_F_T_E4_F_T: wci_4_respF$D_IN = 34'h3C0DE4202; + default: wci_4_respF$D_IN = 34'h2AAAAAAAA /* unspecified value */ ; endcase end - assign wci_respF_4$ENQ = - WILL_FIRE_RL_wci_wrkBusy_4 && - (!wci_respTimr_4_62_ULT_1_SL_wci_wTimeout_4_63_64___d5833 || - wci_wciResponse_4$wget[33:32] != 2'd0) || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_F_F_T_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_F_T ; - assign wci_respF_4$DEQ = MUX_wrkAct$write_1__SEL_3 && wrkAct == 4'd4 ; - assign wci_respF_4$CLR = 1'b0 ; - - // submodule wci_respF_5 - always@(MUX_wci_busy_5$write_1__SEL_1 or - MUX_wci_respF_5$enq_1__VAL_1 or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_F_T or - MUX_wci_respF_5$enq_1__VAL_2 or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_F_F_T or - MUX_wci_respF_5$enq_1__VAL_3 or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T or - MUX_wci_respF_5$enq_1__VAL_4 or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T or - MUX_wci_respF_5$enq_1__VAL_5 or - MUX_wci_respF_5$enq_1__SEL_6 or - MUX_wci_respF_5$enq_1__SEL_7 or - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_T) + assign wci_4_respF$ENQ = + WILL_FIRE_RL_wci_4_wrkBusy && + (!wci_4_respTimr_88_ULT_1_SL_wci_4_wTimeout_89_90___d791 || + wci_4_wciResponse$wget[33:32] != 2'd0) || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_F_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_F_F_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_F_F_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E4_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E4_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E4_F_F_T_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E4_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E4_F_F_T_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E4_F_F_T_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_F_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E4_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E4_F_T ; + assign wci_4_respF$DEQ = MUX_wrkAct$write_1__SEL_3 && wrkAct == 4'd4 ; + assign wci_4_respF$CLR = 1'b0 ; + + // submodule wci_5_mReset + assign wci_5_mReset$ASSERT_IN = !wci_5_wReset_n ; + + // submodule wci_5_respF + always@(MUX_wci_5_busy$write_1__SEL_1 or + MUX_wci_5_respF$enq_1__VAL_1 or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_F_T or + MUX_wci_5_respF$enq_1__VAL_2 or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_F_F_T or + MUX_wci_5_respF$enq_1__VAL_3 or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_F_F_F_T or + MUX_wci_5_respF$enq_1__VAL_4 or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_F_F_F_F_T or + MUX_wci_5_respF$enq_1__VAL_5 or + MUX_wci_5_respF$enq_1__SEL_6 or + MUX_wci_5_respF$enq_1__SEL_7 or + WILL_FIRE_RL_cpDispatch_F_F_T_E5_F_T) begin case (1'b1) // synopsys parallel_case - MUX_wci_busy_5$write_1__SEL_1: - wci_respF_5$D_IN = MUX_wci_respF_5$enq_1__VAL_1; - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_F_T: - wci_respF_5$D_IN = MUX_wci_respF_5$enq_1__VAL_2; - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_F_F_T: - wci_respF_5$D_IN = MUX_wci_respF_5$enq_1__VAL_3; - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T: - wci_respF_5$D_IN = MUX_wci_respF_5$enq_1__VAL_4; - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T: - wci_respF_5$D_IN = MUX_wci_respF_5$enq_1__VAL_5; - MUX_wci_respF_5$enq_1__SEL_6: wci_respF_5$D_IN = 34'h100000000; - MUX_wci_respF_5$enq_1__SEL_7: wci_respF_5$D_IN = 34'h1C0DE4204; - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_T: - wci_respF_5$D_IN = 34'h3C0DE4202; - default: wci_respF_5$D_IN = 34'h2AAAAAAAA /* unspecified value */ ; + MUX_wci_5_busy$write_1__SEL_1: + wci_5_respF$D_IN = MUX_wci_5_respF$enq_1__VAL_1; + WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_F_T: + wci_5_respF$D_IN = MUX_wci_5_respF$enq_1__VAL_2; + WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_F_F_T: + wci_5_respF$D_IN = MUX_wci_5_respF$enq_1__VAL_3; + WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_F_F_F_T: + wci_5_respF$D_IN = MUX_wci_5_respF$enq_1__VAL_4; + WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_F_F_F_F_T: + wci_5_respF$D_IN = MUX_wci_5_respF$enq_1__VAL_5; + MUX_wci_5_respF$enq_1__SEL_6: wci_5_respF$D_IN = 34'h100000000; + MUX_wci_5_respF$enq_1__SEL_7: wci_5_respF$D_IN = 34'h1C0DE4204; + WILL_FIRE_RL_cpDispatch_F_F_T_E5_F_T: wci_5_respF$D_IN = 34'h3C0DE4202; + default: wci_5_respF$D_IN = 34'h2AAAAAAAA /* unspecified value */ ; endcase end - assign wci_respF_5$ENQ = - WILL_FIRE_RL_wci_wrkBusy_5 && - (!wci_respTimr_5_02_ULT_1_SL_wci_wTimeout_5_03_04___d5834 || - wci_wciResponse_5$wget[33:32] != 2'd0) || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_F_T_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_T ; - assign wci_respF_5$DEQ = MUX_wrkAct$write_1__SEL_3 && wrkAct == 4'd5 ; - assign wci_respF_5$CLR = 1'b0 ; - - // submodule wci_respF_6 - always@(MUX_wci_busy_6$write_1__SEL_1 or - MUX_wci_respF_6$enq_1__VAL_1 or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_F_F_T or - MUX_wci_respF_6$enq_1__VAL_2 or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T or - MUX_wci_respF_6$enq_1__VAL_3 or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T or - MUX_wci_respF_6$enq_1__VAL_4 or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T or - MUX_wci_respF_6$enq_1__VAL_5 or - MUX_wci_respF_6$enq_1__SEL_6 or - MUX_wci_respF_6$enq_1__SEL_7 or - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_F_T) + assign wci_5_respF$ENQ = + WILL_FIRE_RL_wci_5_wrkBusy && + (!wci_5_respTimr_28_ULT_1_SL_wci_5_wTimeout_29_30___d931 || + wci_5_wciResponse$wget[33:32] != 2'd0) || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_F_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_F_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E5_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E5_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E5_F_F_T_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E5_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E5_F_F_T_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E5_F_F_T_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E5_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E5_F_T ; + assign wci_5_respF$DEQ = MUX_wrkAct$write_1__SEL_3 && wrkAct == 4'd5 ; + assign wci_5_respF$CLR = 1'b0 ; + + // submodule wci_6_mReset + assign wci_6_mReset$ASSERT_IN = !wci_6_wReset_n ; + + // submodule wci_6_respF + always@(MUX_wci_6_busy$write_1__SEL_1 or + MUX_wci_6_respF$enq_1__VAL_1 or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_F_F_T or + MUX_wci_6_respF$enq_1__VAL_2 or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_F_F_F_T or + MUX_wci_6_respF$enq_1__VAL_3 or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_F_F_F_F_T or + MUX_wci_6_respF$enq_1__VAL_4 or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_F_F_F_F_F_T or + MUX_wci_6_respF$enq_1__VAL_5 or + MUX_wci_6_respF$enq_1__SEL_6 or + MUX_wci_6_respF$enq_1__SEL_7 or + WILL_FIRE_RL_cpDispatch_F_F_T_E6_F_T) begin case (1'b1) // synopsys parallel_case - MUX_wci_busy_6$write_1__SEL_1: - wci_respF_6$D_IN = MUX_wci_respF_6$enq_1__VAL_1; - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_F_F_T: - wci_respF_6$D_IN = MUX_wci_respF_6$enq_1__VAL_2; - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T: - wci_respF_6$D_IN = MUX_wci_respF_6$enq_1__VAL_3; - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T: - wci_respF_6$D_IN = MUX_wci_respF_6$enq_1__VAL_4; - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T: - wci_respF_6$D_IN = MUX_wci_respF_6$enq_1__VAL_5; - MUX_wci_respF_6$enq_1__SEL_6: wci_respF_6$D_IN = 34'h100000000; - MUX_wci_respF_6$enq_1__SEL_7: wci_respF_6$D_IN = 34'h1C0DE4204; - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_F_T: - wci_respF_6$D_IN = 34'h3C0DE4202; - default: wci_respF_6$D_IN = 34'h2AAAAAAAA /* unspecified value */ ; + MUX_wci_6_busy$write_1__SEL_1: + wci_6_respF$D_IN = MUX_wci_6_respF$enq_1__VAL_1; + WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_F_F_T: + wci_6_respF$D_IN = MUX_wci_6_respF$enq_1__VAL_2; + WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_F_F_F_T: + wci_6_respF$D_IN = MUX_wci_6_respF$enq_1__VAL_3; + WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_F_F_F_F_T: + wci_6_respF$D_IN = MUX_wci_6_respF$enq_1__VAL_4; + WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_F_F_F_F_F_T: + wci_6_respF$D_IN = MUX_wci_6_respF$enq_1__VAL_5; + MUX_wci_6_respF$enq_1__SEL_6: wci_6_respF$D_IN = 34'h100000000; + MUX_wci_6_respF$enq_1__SEL_7: wci_6_respF$D_IN = 34'h1C0DE4204; + WILL_FIRE_RL_cpDispatch_F_F_T_E6_F_T: wci_6_respF$D_IN = 34'h3C0DE4202; + default: wci_6_respF$D_IN = 34'h2AAAAAAAA /* unspecified value */ ; endcase end - assign wci_respF_6$ENQ = - WILL_FIRE_RL_wci_wrkBusy_6 && - (!wci_respTimr_6_042_ULT_1_SL_wci_wTimeout_6_043_ETC___d5835 || - wci_wciResponse_6$wget[33:32] != 2'd0) || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_F_F_T_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_F_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_F_T ; - assign wci_respF_6$DEQ = MUX_wrkAct$write_1__SEL_3 && wrkAct == 4'd6 ; - assign wci_respF_6$CLR = 1'b0 ; - - // submodule wci_respF_7 - always@(MUX_wci_busy_7$write_1__SEL_1 or - MUX_wci_respF_7$enq_1__VAL_1 or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T or - MUX_wci_respF_7$enq_1__VAL_2 or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T or - MUX_wci_respF_7$enq_1__VAL_3 or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T or - MUX_wci_respF_7$enq_1__VAL_4 or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T or - MUX_wci_respF_7$enq_1__VAL_5 or - MUX_wci_respF_7$enq_1__SEL_6 or - MUX_wci_respF_7$enq_1__SEL_7 or - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_F_T) + assign wci_6_respF$ENQ = + WILL_FIRE_RL_wci_6_wrkBusy && + (!wci_6_respTimr_068_ULT_1_SL_wci_6_wTimeout_069_ETC___d1071 || + wci_6_wciResponse$wget[33:32] != 2'd0) || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_F_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_F_F_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_F_F_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E6_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E6_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E6_F_F_T_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E6_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E6_F_F_T_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E6_F_F_T_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_F_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E6_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E6_F_T ; + assign wci_6_respF$DEQ = MUX_wrkAct$write_1__SEL_3 && wrkAct == 4'd6 ; + assign wci_6_respF$CLR = 1'b0 ; + + // submodule wci_7_mReset + assign wci_7_mReset$ASSERT_IN = !wci_7_wReset_n ; + + // submodule wci_7_respF + always@(MUX_wci_7_busy$write_1__SEL_1 or + MUX_wci_7_respF$enq_1__VAL_1 or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_F_T or + MUX_wci_7_respF$enq_1__VAL_2 or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_F_F_T or + MUX_wci_7_respF$enq_1__VAL_3 or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_F_F_F_T or + MUX_wci_7_respF$enq_1__VAL_4 or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_F_F_F_F_T or + MUX_wci_7_respF$enq_1__VAL_5 or + MUX_wci_7_respF$enq_1__SEL_6 or + MUX_wci_7_respF$enq_1__SEL_7 or + WILL_FIRE_RL_cpDispatch_F_F_T_E7_F_T) begin case (1'b1) // synopsys parallel_case - MUX_wci_busy_7$write_1__SEL_1: - wci_respF_7$D_IN = MUX_wci_respF_7$enq_1__VAL_1; - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T: - wci_respF_7$D_IN = MUX_wci_respF_7$enq_1__VAL_2; - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T: - wci_respF_7$D_IN = MUX_wci_respF_7$enq_1__VAL_3; - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T: - wci_respF_7$D_IN = MUX_wci_respF_7$enq_1__VAL_4; - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T: - wci_respF_7$D_IN = MUX_wci_respF_7$enq_1__VAL_5; - MUX_wci_respF_7$enq_1__SEL_6: wci_respF_7$D_IN = 34'h100000000; - MUX_wci_respF_7$enq_1__SEL_7: wci_respF_7$D_IN = 34'h1C0DE4204; - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_F_T: - wci_respF_7$D_IN = 34'h3C0DE4202; - default: wci_respF_7$D_IN = 34'h2AAAAAAAA /* unspecified value */ ; + MUX_wci_7_busy$write_1__SEL_1: + wci_7_respF$D_IN = MUX_wci_7_respF$enq_1__VAL_1; + WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_F_T: + wci_7_respF$D_IN = MUX_wci_7_respF$enq_1__VAL_2; + WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_F_F_T: + wci_7_respF$D_IN = MUX_wci_7_respF$enq_1__VAL_3; + WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_F_F_F_T: + wci_7_respF$D_IN = MUX_wci_7_respF$enq_1__VAL_4; + WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_F_F_F_F_T: + wci_7_respF$D_IN = MUX_wci_7_respF$enq_1__VAL_5; + MUX_wci_7_respF$enq_1__SEL_6: wci_7_respF$D_IN = 34'h100000000; + MUX_wci_7_respF$enq_1__SEL_7: wci_7_respF$D_IN = 34'h1C0DE4204; + WILL_FIRE_RL_cpDispatch_F_F_T_E7_F_T: wci_7_respF$D_IN = 34'h3C0DE4202; + default: wci_7_respF$D_IN = 34'h2AAAAAAAA /* unspecified value */ ; endcase end - assign wci_respF_7$ENQ = - WILL_FIRE_RL_wci_wrkBusy_7 && - (!wci_respTimr_7_182_ULT_1_SL_wci_wTimeout_7_183_ETC___d5836 || - wci_wciResponse_7$wget[33:32] != 2'd0) || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_F_F_T_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_F_T ; - assign wci_respF_7$DEQ = MUX_wrkAct$write_1__SEL_3 && wrkAct == 4'd7 ; - assign wci_respF_7$CLR = 1'b0 ; - - // submodule wci_respF_8 - always@(MUX_wci_busy_8$write_1__SEL_1 or - MUX_wci_respF_8$enq_1__VAL_1 or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T or - MUX_wci_respF_8$enq_1__VAL_2 or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T or - MUX_wci_respF_8$enq_1__VAL_3 or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T or - MUX_wci_respF_8$enq_1__VAL_4 or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T or - MUX_wci_respF_8$enq_1__VAL_5 or - MUX_wci_respF_8$enq_1__SEL_6 or - MUX_wci_respF_8$enq_1__SEL_7 or - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_F_T) + assign wci_7_respF$ENQ = + WILL_FIRE_RL_wci_7_wrkBusy && + (!wci_7_respTimr_208_ULT_1_SL_wci_7_wTimeout_209_ETC___d1211 || + wci_7_wciResponse$wget[33:32] != 2'd0) || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_F_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_F_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E7_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E7_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E7_F_F_T_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E7_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E7_F_F_T_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E7_F_F_T_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E7_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E7_F_T ; + assign wci_7_respF$DEQ = MUX_wrkAct$write_1__SEL_3 && wrkAct == 4'd7 ; + assign wci_7_respF$CLR = 1'b0 ; + + // submodule wci_8_mReset + assign wci_8_mReset$ASSERT_IN = !wci_8_wReset_n ; + + // submodule wci_8_respF + always@(MUX_wci_8_busy$write_1__SEL_1 or + MUX_wci_8_respF$enq_1__VAL_1 or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_F_T or + MUX_wci_8_respF$enq_1__VAL_2 or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_F_F_T or + MUX_wci_8_respF$enq_1__VAL_3 or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_F_F_F_T or + MUX_wci_8_respF$enq_1__VAL_4 or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_F_F_F_F_T or + MUX_wci_8_respF$enq_1__VAL_5 or + MUX_wci_8_respF$enq_1__SEL_6 or + MUX_wci_8_respF$enq_1__SEL_7 or + WILL_FIRE_RL_cpDispatch_F_F_T_E8_F_T) begin case (1'b1) // synopsys parallel_case - MUX_wci_busy_8$write_1__SEL_1: - wci_respF_8$D_IN = MUX_wci_respF_8$enq_1__VAL_1; - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T: - wci_respF_8$D_IN = MUX_wci_respF_8$enq_1__VAL_2; - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T: - wci_respF_8$D_IN = MUX_wci_respF_8$enq_1__VAL_3; - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T: - wci_respF_8$D_IN = MUX_wci_respF_8$enq_1__VAL_4; - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T: - wci_respF_8$D_IN = MUX_wci_respF_8$enq_1__VAL_5; - MUX_wci_respF_8$enq_1__SEL_6: wci_respF_8$D_IN = 34'h100000000; - MUX_wci_respF_8$enq_1__SEL_7: wci_respF_8$D_IN = 34'h1C0DE4204; - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_F_T: - wci_respF_8$D_IN = 34'h3C0DE4202; - default: wci_respF_8$D_IN = 34'h2AAAAAAAA /* unspecified value */ ; + MUX_wci_8_busy$write_1__SEL_1: + wci_8_respF$D_IN = MUX_wci_8_respF$enq_1__VAL_1; + WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_F_T: + wci_8_respF$D_IN = MUX_wci_8_respF$enq_1__VAL_2; + WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_F_F_T: + wci_8_respF$D_IN = MUX_wci_8_respF$enq_1__VAL_3; + WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_F_F_F_T: + wci_8_respF$D_IN = MUX_wci_8_respF$enq_1__VAL_4; + WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_F_F_F_F_T: + wci_8_respF$D_IN = MUX_wci_8_respF$enq_1__VAL_5; + MUX_wci_8_respF$enq_1__SEL_6: wci_8_respF$D_IN = 34'h100000000; + MUX_wci_8_respF$enq_1__SEL_7: wci_8_respF$D_IN = 34'h1C0DE4204; + WILL_FIRE_RL_cpDispatch_F_F_T_E8_F_T: wci_8_respF$D_IN = 34'h3C0DE4202; + default: wci_8_respF$D_IN = 34'h2AAAAAAAA /* unspecified value */ ; endcase end - assign wci_respF_8$ENQ = - WILL_FIRE_RL_wci_wrkBusy_8 && - (!wci_respTimr_8_322_ULT_1_SL_wci_wTimeout_8_323_ETC___d5837 || - wci_wciResponse_8$wget[33:32] != 2'd0) || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_F_F_T_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_F_T ; - assign wci_respF_8$DEQ = MUX_wrkAct$write_1__SEL_3 && wrkAct == 4'd8 ; - assign wci_respF_8$CLR = 1'b0 ; - - // submodule wci_respF_9 - always@(MUX_wci_busy_9$write_1__SEL_1 or - MUX_wci_respF_9$enq_1__VAL_1 or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T or - MUX_wci_respF_9$enq_1__VAL_2 or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T or - MUX_wci_respF_9$enq_1__VAL_3 or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T or - MUX_wci_respF_9$enq_1__VAL_4 or - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T or - MUX_wci_respF_9$enq_1__VAL_5 or - MUX_wci_respF_9$enq_1__SEL_6 or - MUX_wci_respF_9$enq_1__SEL_7 or - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_F_T) + assign wci_8_respF$ENQ = + WILL_FIRE_RL_wci_8_wrkBusy && + (!wci_8_respTimr_348_ULT_1_SL_wci_8_wTimeout_349_ETC___d1351 || + wci_8_wciResponse$wget[33:32] != 2'd0) || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_F_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_F_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E8_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E8_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E8_F_F_T_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E8_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E8_F_F_T_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E8_F_F_T_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E8_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E8_F_T ; + assign wci_8_respF$DEQ = MUX_wrkAct$write_1__SEL_3 && wrkAct == 4'd8 ; + assign wci_8_respF$CLR = 1'b0 ; + + // submodule wci_9_mReset + assign wci_9_mReset$ASSERT_IN = !wci_9_wReset_n ; + + // submodule wci_9_respF + always@(MUX_wci_9_busy$write_1__SEL_1 or + MUX_wci_9_respF$enq_1__VAL_1 or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_F_F_T or + MUX_wci_9_respF$enq_1__VAL_2 or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_F_F_F_T or + MUX_wci_9_respF$enq_1__VAL_3 or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_F_F_F_F_T or + MUX_wci_9_respF$enq_1__VAL_4 or + WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_F_F_F_F_F_T or + MUX_wci_9_respF$enq_1__VAL_5 or + MUX_wci_9_respF$enq_1__SEL_6 or + MUX_wci_9_respF$enq_1__SEL_7 or + WILL_FIRE_RL_cpDispatch_F_F_T_E9_F_T) begin case (1'b1) // synopsys parallel_case - MUX_wci_busy_9$write_1__SEL_1: - wci_respF_9$D_IN = MUX_wci_respF_9$enq_1__VAL_1; - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T: - wci_respF_9$D_IN = MUX_wci_respF_9$enq_1__VAL_2; - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T: - wci_respF_9$D_IN = MUX_wci_respF_9$enq_1__VAL_3; - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T: - wci_respF_9$D_IN = MUX_wci_respF_9$enq_1__VAL_4; - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T: - wci_respF_9$D_IN = MUX_wci_respF_9$enq_1__VAL_5; - MUX_wci_respF_9$enq_1__SEL_6: wci_respF_9$D_IN = 34'h100000000; - MUX_wci_respF_9$enq_1__SEL_7: wci_respF_9$D_IN = 34'h1C0DE4204; - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_F_T: - wci_respF_9$D_IN = 34'h3C0DE4202; - default: wci_respF_9$D_IN = 34'h2AAAAAAAA /* unspecified value */ ; + MUX_wci_9_busy$write_1__SEL_1: + wci_9_respF$D_IN = MUX_wci_9_respF$enq_1__VAL_1; + WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_F_F_T: + wci_9_respF$D_IN = MUX_wci_9_respF$enq_1__VAL_2; + WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_F_F_F_T: + wci_9_respF$D_IN = MUX_wci_9_respF$enq_1__VAL_3; + WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_F_F_F_F_T: + wci_9_respF$D_IN = MUX_wci_9_respF$enq_1__VAL_4; + WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_F_F_F_F_F_T: + wci_9_respF$D_IN = MUX_wci_9_respF$enq_1__VAL_5; + MUX_wci_9_respF$enq_1__SEL_6: wci_9_respF$D_IN = 34'h100000000; + MUX_wci_9_respF$enq_1__SEL_7: wci_9_respF$D_IN = 34'h1C0DE4204; + WILL_FIRE_RL_cpDispatch_F_F_T_E9_F_T: wci_9_respF$D_IN = 34'h3C0DE4202; + default: wci_9_respF$D_IN = 34'h2AAAAAAAA /* unspecified value */ ; endcase end - assign wci_respF_9$ENQ = - WILL_FIRE_RL_wci_wrkBusy_9 && - (!wci_respTimr_9_462_ULT_1_SL_wci_wTimeout_9_463_ETC___d5838 || - wci_wciResponse_9$wget[33:32] != 2'd0) || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_F_F_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_F_F_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_F_F_T_F_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_F_F_T_F_T || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_F_F_T_T_T || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F || - WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_T_F || - WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_F_T ; - assign wci_respF_9$DEQ = MUX_wrkAct$write_1__SEL_3 && wrkAct == 4'd9 ; - assign wci_respF_9$CLR = 1'b0 ; + assign wci_9_respF$ENQ = + WILL_FIRE_RL_wci_9_wrkBusy && + (!wci_9_respTimr_488_ULT_1_SL_wci_9_wTimeout_489_ETC___d1491 || + wci_9_wciResponse$wget[33:32] != 2'd0) || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_F_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_F_F_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_F_F_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E9_F_F_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E9_F_F_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E9_F_F_T_F_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E9_F_F_T_F_T || + WILL_FIRE_RL_cpDispatch_F_F_T_E9_F_F_T_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E9_F_F_T_T_T || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_F_T_F || + WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E9_T_F || + WILL_FIRE_RL_cpDispatch_F_F_T_E9_F_T ; + assign wci_9_respF$DEQ = MUX_wrkAct$write_1__SEL_3 && wrkAct == 4'd9 ; + assign wci_9_respF$CLR = 1'b0 ; // remaining internal signals - assign IF_adminResp2F_notEmpty__278_THEN_adminResp2F__ETC___d2316 = + assign IF_adminResp2F_notEmpty__304_THEN_adminResp2F__ETC___d2342 = adminResp2F$EMPTY_N ? adminResp2F$D_OUT : (adminResp3F$EMPTY_N ? adminResp3F$D_OUT : adminResp4F$D_OUT) ; - assign IF_cpReq_337_BITS_37_TO_36_861_EQ_2_862_THEN_c_ETC___d3906 = - _theResult_____1__h75875 == 4'd0 && cpReq[37:36] != 2'd2 && - cpReq[9:6] == 4'h8 && - !wci_busy && - wci_respF$FULL_N && - !dispatched ; - assign IF_cpReq_337_BITS_37_TO_36_861_EQ_2_862_THEN_c_ETC___d3915 = - _theResult_____1__h75875 == 4'd0 && cpReq[37:36] != 2'd2 && - cpReq[9:6] == 4'h9 && - !wci_busy && - wci_respF$FULL_N && - !dispatched ; - assign IF_cpReq_337_BITS_37_TO_36_861_EQ_2_862_THEN_c_ETC___d3925 = - _theResult_____1__h75875 == 4'd0 && cpReq[37:36] != 2'd2 && - cpReq[9:6] == 4'hA && - !wci_busy && - wci_respF$FULL_N && - !dispatched ; - assign IF_cpReq_337_BITS_37_TO_36_861_EQ_2_862_THEN_c_ETC___d3984 = - _theResult_____1__h75875 == 4'd1 && cpReq[37:36] != 2'd2 && - cpReq[9:6] == 4'h8 && - !wci_busy_1 && - wci_respF_1$FULL_N && - !dispatched ; - assign IF_cpReq_337_BITS_37_TO_36_861_EQ_2_862_THEN_c_ETC___d3993 = - _theResult_____1__h75875 == 4'd1 && cpReq[37:36] != 2'd2 && - cpReq[9:6] == 4'h9 && - !wci_busy_1 && - wci_respF_1$FULL_N && - !dispatched ; - assign IF_cpReq_337_BITS_37_TO_36_861_EQ_2_862_THEN_c_ETC___d4003 = - _theResult_____1__h75875 == 4'd1 && cpReq[37:36] != 2'd2 && - cpReq[9:6] == 4'hA && - !wci_busy_1 && - wci_respF_1$FULL_N && - !dispatched ; - assign IF_cpReq_337_BITS_37_TO_36_861_EQ_2_862_THEN_c_ETC___d4060 = - _theResult_____1__h75875 == 4'd2 && cpReq[37:36] != 2'd2 && - cpReq[9:6] == 4'h8 && - !wci_busy_2 && - wci_respF_2$FULL_N && - !dispatched ; - assign IF_cpReq_337_BITS_37_TO_36_861_EQ_2_862_THEN_c_ETC___d4069 = - _theResult_____1__h75875 == 4'd2 && cpReq[37:36] != 2'd2 && - cpReq[9:6] == 4'h9 && - !wci_busy_2 && - wci_respF_2$FULL_N && - !dispatched ; - assign IF_cpReq_337_BITS_37_TO_36_861_EQ_2_862_THEN_c_ETC___d4079 = - _theResult_____1__h75875 == 4'd2 && cpReq[37:36] != 2'd2 && - cpReq[9:6] == 4'hA && - !wci_busy_2 && - wci_respF_2$FULL_N && - !dispatched ; - assign IF_cpReq_337_BITS_37_TO_36_861_EQ_2_862_THEN_c_ETC___d4136 = - _theResult_____1__h75875 == 4'd3 && cpReq[37:36] != 2'd2 && - cpReq[9:6] == 4'h8 && - !wci_busy_3 && - wci_respF_3$FULL_N && - !dispatched ; - assign IF_cpReq_337_BITS_37_TO_36_861_EQ_2_862_THEN_c_ETC___d4145 = - _theResult_____1__h75875 == 4'd3 && cpReq[37:36] != 2'd2 && - cpReq[9:6] == 4'h9 && - !wci_busy_3 && - wci_respF_3$FULL_N && - !dispatched ; - assign IF_cpReq_337_BITS_37_TO_36_861_EQ_2_862_THEN_c_ETC___d4155 = - _theResult_____1__h75875 == 4'd3 && cpReq[37:36] != 2'd2 && - cpReq[9:6] == 4'hA && - !wci_busy_3 && - wci_respF_3$FULL_N && - !dispatched ; - assign IF_cpReq_337_BITS_37_TO_36_861_EQ_2_862_THEN_c_ETC___d4212 = - _theResult_____1__h75875 == 4'd4 && cpReq[37:36] != 2'd2 && - cpReq[9:6] == 4'h8 && - !wci_busy_4 && - wci_respF_4$FULL_N && - !dispatched ; - assign IF_cpReq_337_BITS_37_TO_36_861_EQ_2_862_THEN_c_ETC___d4221 = - _theResult_____1__h75875 == 4'd4 && cpReq[37:36] != 2'd2 && - cpReq[9:6] == 4'h9 && - !wci_busy_4 && - wci_respF_4$FULL_N && - !dispatched ; - assign IF_cpReq_337_BITS_37_TO_36_861_EQ_2_862_THEN_c_ETC___d4231 = - _theResult_____1__h75875 == 4'd4 && cpReq[37:36] != 2'd2 && - cpReq[9:6] == 4'hA && - !wci_busy_4 && - wci_respF_4$FULL_N && - !dispatched ; - assign IF_cpReq_337_BITS_37_TO_36_861_EQ_2_862_THEN_c_ETC___d4288 = - _theResult_____1__h75875 == 4'd5 && cpReq[37:36] != 2'd2 && - cpReq[9:6] == 4'h8 && - !wci_busy_5 && - wci_respF_5$FULL_N && - !dispatched ; - assign IF_cpReq_337_BITS_37_TO_36_861_EQ_2_862_THEN_c_ETC___d4297 = - _theResult_____1__h75875 == 4'd5 && cpReq[37:36] != 2'd2 && - cpReq[9:6] == 4'h9 && - !wci_busy_5 && - wci_respF_5$FULL_N && - !dispatched ; - assign IF_cpReq_337_BITS_37_TO_36_861_EQ_2_862_THEN_c_ETC___d4307 = - _theResult_____1__h75875 == 4'd5 && cpReq[37:36] != 2'd2 && - cpReq[9:6] == 4'hA && - !wci_busy_5 && - wci_respF_5$FULL_N && - !dispatched ; - assign IF_cpReq_337_BITS_37_TO_36_861_EQ_2_862_THEN_c_ETC___d4364 = - _theResult_____1__h75875 == 4'd6 && cpReq[37:36] != 2'd2 && - cpReq[9:6] == 4'h8 && - !wci_busy_6 && - wci_respF_6$FULL_N && - !dispatched ; - assign IF_cpReq_337_BITS_37_TO_36_861_EQ_2_862_THEN_c_ETC___d4373 = - _theResult_____1__h75875 == 4'd6 && cpReq[37:36] != 2'd2 && - cpReq[9:6] == 4'h9 && - !wci_busy_6 && - wci_respF_6$FULL_N && - !dispatched ; - assign IF_cpReq_337_BITS_37_TO_36_861_EQ_2_862_THEN_c_ETC___d4383 = - _theResult_____1__h75875 == 4'd6 && cpReq[37:36] != 2'd2 && - cpReq[9:6] == 4'hA && - !wci_busy_6 && - wci_respF_6$FULL_N && - !dispatched ; - assign IF_cpReq_337_BITS_37_TO_36_861_EQ_2_862_THEN_c_ETC___d4440 = - _theResult_____1__h75875 == 4'd7 && cpReq[37:36] != 2'd2 && - cpReq[9:6] == 4'h8 && - !wci_busy_7 && - wci_respF_7$FULL_N && - !dispatched ; - assign IF_cpReq_337_BITS_37_TO_36_861_EQ_2_862_THEN_c_ETC___d4449 = - _theResult_____1__h75875 == 4'd7 && cpReq[37:36] != 2'd2 && - cpReq[9:6] == 4'h9 && - !wci_busy_7 && - wci_respF_7$FULL_N && - !dispatched ; - assign IF_cpReq_337_BITS_37_TO_36_861_EQ_2_862_THEN_c_ETC___d4459 = - _theResult_____1__h75875 == 4'd7 && cpReq[37:36] != 2'd2 && - cpReq[9:6] == 4'hA && - !wci_busy_7 && - wci_respF_7$FULL_N && - !dispatched ; - assign IF_cpReq_337_BITS_37_TO_36_861_EQ_2_862_THEN_c_ETC___d4516 = - _theResult_____1__h75875 == 4'd8 && cpReq[37:36] != 2'd2 && - cpReq[9:6] == 4'h8 && - !wci_busy_8 && - wci_respF_8$FULL_N && - !dispatched ; - assign IF_cpReq_337_BITS_37_TO_36_861_EQ_2_862_THEN_c_ETC___d4525 = - _theResult_____1__h75875 == 4'd8 && cpReq[37:36] != 2'd2 && - cpReq[9:6] == 4'h9 && - !wci_busy_8 && - wci_respF_8$FULL_N && - !dispatched ; - assign IF_cpReq_337_BITS_37_TO_36_861_EQ_2_862_THEN_c_ETC___d4535 = - _theResult_____1__h75875 == 4'd8 && cpReq[37:36] != 2'd2 && - cpReq[9:6] == 4'hA && - !wci_busy_8 && - wci_respF_8$FULL_N && - !dispatched ; - assign IF_cpReq_337_BITS_37_TO_36_861_EQ_2_862_THEN_c_ETC___d4592 = - _theResult_____1__h75875 == 4'd9 && cpReq[37:36] != 2'd2 && - cpReq[9:6] == 4'h8 && - !wci_busy_9 && - wci_respF_9$FULL_N && - !dispatched ; - assign IF_cpReq_337_BITS_37_TO_36_861_EQ_2_862_THEN_c_ETC___d4601 = - _theResult_____1__h75875 == 4'd9 && cpReq[37:36] != 2'd2 && - cpReq[9:6] == 4'h9 && - !wci_busy_9 && - wci_respF_9$FULL_N && - !dispatched ; - assign IF_cpReq_337_BITS_37_TO_36_861_EQ_2_862_THEN_c_ETC___d4611 = - _theResult_____1__h75875 == 4'd9 && cpReq[37:36] != 2'd2 && - cpReq[9:6] == 4'hA && - !wci_busy_9 && - wci_respF_9$FULL_N && - !dispatched ; - assign IF_cpReq_337_BITS_37_TO_36_861_EQ_2_862_THEN_c_ETC___d4668 = - _theResult_____1__h75875 == 4'd10 && cpReq[37:36] != 2'd2 && - cpReq[9:6] == 4'h8 && - !wci_busy_10 && - wci_respF_10$FULL_N && - !dispatched ; - assign IF_cpReq_337_BITS_37_TO_36_861_EQ_2_862_THEN_c_ETC___d4677 = - _theResult_____1__h75875 == 4'd10 && cpReq[37:36] != 2'd2 && - cpReq[9:6] == 4'h9 && - !wci_busy_10 && - wci_respF_10$FULL_N && - !dispatched ; - assign IF_cpReq_337_BITS_37_TO_36_861_EQ_2_862_THEN_c_ETC___d4687 = - _theResult_____1__h75875 == 4'd10 && cpReq[37:36] != 2'd2 && - cpReq[9:6] == 4'hA && - !wci_busy_10 && - wci_respF_10$FULL_N && - !dispatched ; - assign IF_cpReq_337_BITS_37_TO_36_861_EQ_2_862_THEN_c_ETC___d4744 = - _theResult_____1__h75875 == 4'd11 && cpReq[37:36] != 2'd2 && - cpReq[9:6] == 4'h8 && - !wci_busy_11 && - wci_respF_11$FULL_N && - !dispatched ; - assign IF_cpReq_337_BITS_37_TO_36_861_EQ_2_862_THEN_c_ETC___d4753 = - _theResult_____1__h75875 == 4'd11 && cpReq[37:36] != 2'd2 && - cpReq[9:6] == 4'h9 && - !wci_busy_11 && - wci_respF_11$FULL_N && - !dispatched ; - assign IF_cpReq_337_BITS_37_TO_36_861_EQ_2_862_THEN_c_ETC___d4763 = - _theResult_____1__h75875 == 4'd11 && cpReq[37:36] != 2'd2 && - cpReq[9:6] == 4'hA && - !wci_busy_11 && - wci_respF_11$FULL_N && - !dispatched ; - assign IF_cpReq_337_BITS_37_TO_36_861_EQ_2_862_THEN_c_ETC___d4820 = - _theResult_____1__h75875 == 4'd12 && cpReq[37:36] != 2'd2 && - cpReq[9:6] == 4'h8 && - !wci_busy_12 && - wci_respF_12$FULL_N && - !dispatched ; - assign IF_cpReq_337_BITS_37_TO_36_861_EQ_2_862_THEN_c_ETC___d4829 = - _theResult_____1__h75875 == 4'd12 && cpReq[37:36] != 2'd2 && - cpReq[9:6] == 4'h9 && - !wci_busy_12 && - wci_respF_12$FULL_N && - !dispatched ; - assign IF_cpReq_337_BITS_37_TO_36_861_EQ_2_862_THEN_c_ETC___d4839 = - _theResult_____1__h75875 == 4'd12 && cpReq[37:36] != 2'd2 && - cpReq[9:6] == 4'hA && - !wci_busy_12 && - wci_respF_12$FULL_N && - !dispatched ; - assign IF_cpReq_337_BITS_37_TO_36_861_EQ_2_862_THEN_c_ETC___d4896 = - _theResult_____1__h75875 == 4'd13 && cpReq[37:36] != 2'd2 && - cpReq[9:6] == 4'h8 && - !wci_busy_13 && - wci_respF_13$FULL_N && - !dispatched ; - assign IF_cpReq_337_BITS_37_TO_36_861_EQ_2_862_THEN_c_ETC___d4905 = - _theResult_____1__h75875 == 4'd13 && cpReq[37:36] != 2'd2 && - cpReq[9:6] == 4'h9 && - !wci_busy_13 && - wci_respF_13$FULL_N && - !dispatched ; - assign IF_cpReq_337_BITS_37_TO_36_861_EQ_2_862_THEN_c_ETC___d4915 = - _theResult_____1__h75875 == 4'd13 && cpReq[37:36] != 2'd2 && - cpReq[9:6] == 4'hA && - !wci_busy_13 && - wci_respF_13$FULL_N && - !dispatched ; - assign IF_cpReq_337_BITS_37_TO_36_861_EQ_2_862_THEN_c_ETC___d4972 = - _theResult_____1__h75875 == 4'd14 && cpReq[37:36] != 2'd2 && - cpReq[9:6] == 4'h8 && - !wci_busy_14 && - wci_respF_14$FULL_N && - !dispatched ; - assign IF_cpReq_337_BITS_37_TO_36_861_EQ_2_862_THEN_c_ETC___d4981 = - _theResult_____1__h75875 == 4'd14 && cpReq[37:36] != 2'd2 && - cpReq[9:6] == 4'h9 && - !wci_busy_14 && - wci_respF_14$FULL_N && - !dispatched ; - assign IF_cpReq_337_BITS_37_TO_36_861_EQ_2_862_THEN_c_ETC___d4991 = - _theResult_____1__h75875 == 4'd14 && cpReq[37:36] != 2'd2 && - cpReq[9:6] == 4'hA && - !wci_busy_14 && - wci_respF_14$FULL_N && - !dispatched ; - assign IF_timeServ_ppsOK_7_THEN_timeServ_ppsExtSync_d_ETC___d6035 = + assign IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_N_ETC___d4934 = + (cpReq[37:36] == 2'd2) ? + !wci_0_wReset_n || !wci_0_reqF_cntr_r : + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d4933 ; + assign IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_N_ETC___d4940 = + (cpReq[37:36] == 2'd2) ? + !wci_1_wReset_n || !wci_1_reqF_cntr_r : + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d4939 ; + assign IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_N_ETC___d4946 = + (cpReq[37:36] == 2'd2) ? + !wci_2_wReset_n || !wci_2_reqF_cntr_r : + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d4945 ; + assign IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_N_ETC___d4952 = + (cpReq[37:36] == 2'd2) ? + !wci_3_wReset_n || !wci_3_reqF_cntr_r : + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d4951 ; + assign IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_N_ETC___d4958 = + (cpReq[37:36] == 2'd2) ? + !wci_4_wReset_n || !wci_4_reqF_cntr_r : + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d4957 ; + assign IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_N_ETC___d4964 = + (cpReq[37:36] == 2'd2) ? + !wci_5_wReset_n || !wci_5_reqF_cntr_r : + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d4963 ; + assign IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_N_ETC___d4970 = + (cpReq[37:36] == 2'd2) ? + !wci_6_wReset_n || !wci_6_reqF_cntr_r : + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d4969 ; + assign IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_N_ETC___d4976 = + (cpReq[37:36] == 2'd2) ? + !wci_7_wReset_n || !wci_7_reqF_cntr_r : + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d4975 ; + assign IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_N_ETC___d4982 = + (cpReq[37:36] == 2'd2) ? + !wci_8_wReset_n || !wci_8_reqF_cntr_r : + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d4981 ; + assign IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_N_ETC___d4988 = + (cpReq[37:36] == 2'd2) ? + !wci_9_wReset_n || !wci_9_reqF_cntr_r : + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d4987 ; + assign IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_N_ETC___d4994 = + (cpReq[37:36] == 2'd2) ? + !wci_10_wReset_n || !wci_10_reqF_cntr_r : + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d4993 ; + assign IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_N_ETC___d5000 = + (cpReq[37:36] == 2'd2) ? + !wci_11_wReset_n || !wci_11_reqF_cntr_r : + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d4999 ; + assign IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_N_ETC___d5006 = + (cpReq[37:36] == 2'd2) ? + !wci_12_wReset_n || !wci_12_reqF_cntr_r : + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d5005 ; + assign IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_N_ETC___d5012 = + (cpReq[37:36] == 2'd2) ? + !wci_13_wReset_n || !wci_13_reqF_cntr_r : + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d5011 ; + assign IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_N_ETC___d5018 = + (cpReq[37:36] == 2'd2) ? + !wci_14_wReset_n || !wci_14_reqF_cntr_r : + NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d5017 ; + assign IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_w_ETC___d4932 = + (cpReq[37:36] == 2'd2) ? + wci_0_wReset_n || wci_0_respF$FULL_N : + cpReq[37:36] == 2'd1 && cpReq[19:9] == 11'd0 || + wci_0_respF$FULL_N ; + assign IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_w_ETC___d4938 = + (cpReq[37:36] == 2'd2) ? + wci_1_wReset_n || wci_1_respF$FULL_N : + cpReq[37:36] == 2'd1 && cpReq[19:9] == 11'd0 || + wci_1_respF$FULL_N ; + assign IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_w_ETC___d4944 = + (cpReq[37:36] == 2'd2) ? + wci_2_wReset_n || wci_2_respF$FULL_N : + cpReq[37:36] == 2'd1 && cpReq[19:9] == 11'd0 || + wci_2_respF$FULL_N ; + assign IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_w_ETC___d4950 = + (cpReq[37:36] == 2'd2) ? + wci_3_wReset_n || wci_3_respF$FULL_N : + cpReq[37:36] == 2'd1 && cpReq[19:9] == 11'd0 || + wci_3_respF$FULL_N ; + assign IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_w_ETC___d4956 = + (cpReq[37:36] == 2'd2) ? + wci_4_wReset_n || wci_4_respF$FULL_N : + cpReq[37:36] == 2'd1 && cpReq[19:9] == 11'd0 || + wci_4_respF$FULL_N ; + assign IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_w_ETC___d4962 = + (cpReq[37:36] == 2'd2) ? + wci_5_wReset_n || wci_5_respF$FULL_N : + cpReq[37:36] == 2'd1 && cpReq[19:9] == 11'd0 || + wci_5_respF$FULL_N ; + assign IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_w_ETC___d4968 = + (cpReq[37:36] == 2'd2) ? + wci_6_wReset_n || wci_6_respF$FULL_N : + cpReq[37:36] == 2'd1 && cpReq[19:9] == 11'd0 || + wci_6_respF$FULL_N ; + assign IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_w_ETC___d4974 = + (cpReq[37:36] == 2'd2) ? + wci_7_wReset_n || wci_7_respF$FULL_N : + cpReq[37:36] == 2'd1 && cpReq[19:9] == 11'd0 || + wci_7_respF$FULL_N ; + assign IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_w_ETC___d4980 = + (cpReq[37:36] == 2'd2) ? + wci_8_wReset_n || wci_8_respF$FULL_N : + cpReq[37:36] == 2'd1 && cpReq[19:9] == 11'd0 || + wci_8_respF$FULL_N ; + assign IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_w_ETC___d4986 = + (cpReq[37:36] == 2'd2) ? + wci_9_wReset_n || wci_9_respF$FULL_N : + cpReq[37:36] == 2'd1 && cpReq[19:9] == 11'd0 || + wci_9_respF$FULL_N ; + assign IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_w_ETC___d4992 = + (cpReq[37:36] == 2'd2) ? + wci_10_wReset_n || wci_10_respF$FULL_N : + cpReq[37:36] == 2'd1 && cpReq[19:9] == 11'd0 || + wci_10_respF$FULL_N ; + assign IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_w_ETC___d4998 = + (cpReq[37:36] == 2'd2) ? + wci_11_wReset_n || wci_11_respF$FULL_N : + cpReq[37:36] == 2'd1 && cpReq[19:9] == 11'd0 || + wci_11_respF$FULL_N ; + assign IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_w_ETC___d5004 = + (cpReq[37:36] == 2'd2) ? + wci_12_wReset_n || wci_12_respF$FULL_N : + cpReq[37:36] == 2'd1 && cpReq[19:9] == 11'd0 || + wci_12_respF$FULL_N ; + assign IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_w_ETC___d5010 = + (cpReq[37:36] == 2'd2) ? + wci_13_wReset_n || wci_13_respF$FULL_N : + cpReq[37:36] == 2'd1 && cpReq[19:9] == 11'd0 || + wci_13_respF$FULL_N ; + assign IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_w_ETC___d5016 = + (cpReq[37:36] == 2'd2) ? + wci_14_wReset_n || wci_14_respF$FULL_N : + cpReq[37:36] == 2'd1 && cpReq[19:9] == 11'd0 || + wci_14_respF$FULL_N ; + assign IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_THEN_N_ETC___d3580 = + (cpReq[61:60] == 2'd2) ? + !wci_0_wReset_n || !wci_0_reqF_cntr_r : + wci_0_respF$FULL_N ; + assign IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_THEN_N_ETC___d3584 = + (cpReq[61:60] == 2'd2) ? + !wci_1_wReset_n || !wci_1_reqF_cntr_r : + wci_1_respF$FULL_N ; + assign IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_THEN_N_ETC___d3588 = + (cpReq[61:60] == 2'd2) ? + !wci_2_wReset_n || !wci_2_reqF_cntr_r : + wci_2_respF$FULL_N ; + assign IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_THEN_N_ETC___d3592 = + (cpReq[61:60] == 2'd2) ? + !wci_3_wReset_n || !wci_3_reqF_cntr_r : + wci_3_respF$FULL_N ; + assign IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_THEN_N_ETC___d3596 = + (cpReq[61:60] == 2'd2) ? + !wci_4_wReset_n || !wci_4_reqF_cntr_r : + wci_4_respF$FULL_N ; + assign IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_THEN_N_ETC___d3600 = + (cpReq[61:60] == 2'd2) ? + !wci_5_wReset_n || !wci_5_reqF_cntr_r : + wci_5_respF$FULL_N ; + assign IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_THEN_N_ETC___d3604 = + (cpReq[61:60] == 2'd2) ? + !wci_6_wReset_n || !wci_6_reqF_cntr_r : + wci_6_respF$FULL_N ; + assign IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_THEN_N_ETC___d3608 = + (cpReq[61:60] == 2'd2) ? + !wci_7_wReset_n || !wci_7_reqF_cntr_r : + wci_7_respF$FULL_N ; + assign IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_THEN_N_ETC___d3612 = + (cpReq[61:60] == 2'd2) ? + !wci_8_wReset_n || !wci_8_reqF_cntr_r : + wci_8_respF$FULL_N ; + assign IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_THEN_N_ETC___d3616 = + (cpReq[61:60] == 2'd2) ? + !wci_9_wReset_n || !wci_9_reqF_cntr_r : + wci_9_respF$FULL_N ; + assign IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_THEN_N_ETC___d3620 = + (cpReq[61:60] == 2'd2) ? + !wci_10_wReset_n || !wci_10_reqF_cntr_r : + wci_10_respF$FULL_N ; + assign IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_THEN_N_ETC___d3624 = + (cpReq[61:60] == 2'd2) ? + !wci_11_wReset_n || !wci_11_reqF_cntr_r : + wci_11_respF$FULL_N ; + assign IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_THEN_N_ETC___d3628 = + (cpReq[61:60] == 2'd2) ? + !wci_12_wReset_n || !wci_12_reqF_cntr_r : + wci_12_respF$FULL_N ; + assign IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_THEN_N_ETC___d3632 = + (cpReq[61:60] == 2'd2) ? + !wci_13_wReset_n || !wci_13_reqF_cntr_r : + wci_13_respF$FULL_N ; + assign IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_THEN_N_ETC___d3636 = + (cpReq[61:60] == 2'd2) ? + !wci_14_wReset_n || !wci_14_reqF_cntr_r : + wci_14_respF$FULL_N ; + assign IF_timeServ_ppsOK_7_THEN_timeServ_ppsExtSync_d_ETC___d39 = timeServ_ppsOK ? timeServ_ppsExtSync_d2 && !timeServ_ppsExtSyncD : timeServ_delSec != timeServ_fracSeconds[49:48] ; - assign IF_wci_lastControlOp_10_687_BIT_3_688_THEN_wci_ETC___d1702 = - { wci_lastControlOp_10[3] ? wci_lastControlOp_10[2:0] : 3'b111, - wci_lastConfigBE_10[4] ? wci_lastConfigBE_10[3:0] : 4'hF, - wci_lastOpWrite_10[1], - wci_lastControlOp_10[3], - wci_lastConfigBE_10[4], - wci_lastConfigAddr_10[32], + assign IF_wci_0_lastControlOp_13_BIT_3_14_THEN_wci_0__ETC___d328 = + { wci_0_lastControlOp[3] ? wci_0_lastControlOp[2:0] : 3'b111, + wci_0_lastConfigBE[4] ? wci_0_lastConfigBE[3:0] : 4'hF, + wci_0_lastOpWrite[1], + wci_0_lastControlOp[3], + wci_0_lastConfigBE[4], + wci_0_lastConfigAddr[32], 6'b0, - wci_sfCap_10, - wci_reqTO_10, - wci_reqFAIL_10, - wci_reqERR_10 } ; - assign IF_wci_lastControlOp_11_827_BIT_3_828_THEN_wci_ETC___d1842 = - { wci_lastControlOp_11[3] ? wci_lastControlOp_11[2:0] : 3'b111, - wci_lastConfigBE_11[4] ? wci_lastConfigBE_11[3:0] : 4'hF, - wci_lastOpWrite_11[1], - wci_lastControlOp_11[3], - wci_lastConfigBE_11[4], - wci_lastConfigAddr_11[32], + wci_0_sfCap, + wci_0_reqTO, + wci_0_reqFAIL, + wci_0_reqERR } ; + assign IF_wci_10_lastControlOp_713_BIT_3_714_THEN_wci_ETC___d1728 = + { wci_10_lastControlOp[3] ? wci_10_lastControlOp[2:0] : 3'b111, + wci_10_lastConfigBE[4] ? wci_10_lastConfigBE[3:0] : 4'hF, + wci_10_lastOpWrite[1], + wci_10_lastControlOp[3], + wci_10_lastConfigBE[4], + wci_10_lastConfigAddr[32], 6'b0, - wci_sfCap_11, - wci_reqTO_11, - wci_reqFAIL_11, - wci_reqERR_11 } ; - assign IF_wci_lastControlOp_12_967_BIT_3_968_THEN_wci_ETC___d1982 = - { wci_lastControlOp_12[3] ? wci_lastControlOp_12[2:0] : 3'b111, - wci_lastConfigBE_12[4] ? wci_lastConfigBE_12[3:0] : 4'hF, - wci_lastOpWrite_12[1], - wci_lastControlOp_12[3], - wci_lastConfigBE_12[4], - wci_lastConfigAddr_12[32], + wci_10_sfCap, + wci_10_reqTO, + wci_10_reqFAIL, + wci_10_reqERR } ; + assign IF_wci_11_lastControlOp_853_BIT_3_854_THEN_wci_ETC___d1868 = + { wci_11_lastControlOp[3] ? wci_11_lastControlOp[2:0] : 3'b111, + wci_11_lastConfigBE[4] ? wci_11_lastConfigBE[3:0] : 4'hF, + wci_11_lastOpWrite[1], + wci_11_lastControlOp[3], + wci_11_lastConfigBE[4], + wci_11_lastConfigAddr[32], 6'b0, - wci_sfCap_12, - wci_reqTO_12, - wci_reqFAIL_12, - wci_reqERR_12 } ; - assign IF_wci_lastControlOp_13_107_BIT_3_108_THEN_wci_ETC___d2122 = - { wci_lastControlOp_13[3] ? wci_lastControlOp_13[2:0] : 3'b111, - wci_lastConfigBE_13[4] ? wci_lastConfigBE_13[3:0] : 4'hF, - wci_lastOpWrite_13[1], - wci_lastControlOp_13[3], - wci_lastConfigBE_13[4], - wci_lastConfigAddr_13[32], + wci_11_sfCap, + wci_11_reqTO, + wci_11_reqFAIL, + wci_11_reqERR } ; + assign IF_wci_12_lastControlOp_993_BIT_3_994_THEN_wci_ETC___d2008 = + { wci_12_lastControlOp[3] ? wci_12_lastControlOp[2:0] : 3'b111, + wci_12_lastConfigBE[4] ? wci_12_lastConfigBE[3:0] : 4'hF, + wci_12_lastOpWrite[1], + wci_12_lastControlOp[3], + wci_12_lastConfigBE[4], + wci_12_lastConfigAddr[32], 6'b0, - wci_sfCap_13, - wci_reqTO_13, - wci_reqFAIL_13, - wci_reqERR_13 } ; - assign IF_wci_lastControlOp_14_247_BIT_3_248_THEN_wci_ETC___d2262 = - { wci_lastControlOp_14[3] ? wci_lastControlOp_14[2:0] : 3'b111, - wci_lastConfigBE_14[4] ? wci_lastConfigBE_14[3:0] : 4'hF, - wci_lastOpWrite_14[1], - wci_lastControlOp_14[3], - wci_lastConfigBE_14[4], - wci_lastConfigAddr_14[32], + wci_12_sfCap, + wci_12_reqTO, + wci_12_reqFAIL, + wci_12_reqERR } ; + assign IF_wci_13_lastControlOp_133_BIT_3_134_THEN_wci_ETC___d2148 = + { wci_13_lastControlOp[3] ? wci_13_lastControlOp[2:0] : 3'b111, + wci_13_lastConfigBE[4] ? wci_13_lastConfigBE[3:0] : 4'hF, + wci_13_lastOpWrite[1], + wci_13_lastControlOp[3], + wci_13_lastConfigBE[4], + wci_13_lastConfigAddr[32], 6'b0, - wci_sfCap_14, - wci_reqTO_14, - wci_reqFAIL_14, - wci_reqERR_14 } ; - assign IF_wci_lastControlOp_1_27_BIT_3_28_THEN_wci_la_ETC___d442 = - { wci_lastControlOp_1[3] ? wci_lastControlOp_1[2:0] : 3'b111, - wci_lastConfigBE_1[4] ? wci_lastConfigBE_1[3:0] : 4'hF, - wci_lastOpWrite_1[1], - wci_lastControlOp_1[3], - wci_lastConfigBE_1[4], - wci_lastConfigAddr_1[32], + wci_13_sfCap, + wci_13_reqTO, + wci_13_reqFAIL, + wci_13_reqERR } ; + assign IF_wci_14_lastControlOp_273_BIT_3_274_THEN_wci_ETC___d2288 = + { wci_14_lastControlOp[3] ? wci_14_lastControlOp[2:0] : 3'b111, + wci_14_lastConfigBE[4] ? wci_14_lastConfigBE[3:0] : 4'hF, + wci_14_lastOpWrite[1], + wci_14_lastControlOp[3], + wci_14_lastConfigBE[4], + wci_14_lastConfigAddr[32], 6'b0, - wci_sfCap_1, - wci_reqTO_1, - wci_reqFAIL_1, - wci_reqERR_1 } ; - assign IF_wci_lastControlOp_2_67_BIT_3_68_THEN_wci_la_ETC___d582 = - { wci_lastControlOp_2[3] ? wci_lastControlOp_2[2:0] : 3'b111, - wci_lastConfigBE_2[4] ? wci_lastConfigBE_2[3:0] : 4'hF, - wci_lastOpWrite_2[1], - wci_lastControlOp_2[3], - wci_lastConfigBE_2[4], - wci_lastConfigAddr_2[32], + wci_14_sfCap, + wci_14_reqTO, + wci_14_reqFAIL, + wci_14_reqERR } ; + assign IF_wci_1_lastControlOp_53_BIT_3_54_THEN_wci_1__ETC___d468 = + { wci_1_lastControlOp[3] ? wci_1_lastControlOp[2:0] : 3'b111, + wci_1_lastConfigBE[4] ? wci_1_lastConfigBE[3:0] : 4'hF, + wci_1_lastOpWrite[1], + wci_1_lastControlOp[3], + wci_1_lastConfigBE[4], + wci_1_lastConfigAddr[32], 6'b0, - wci_sfCap_2, - wci_reqTO_2, - wci_reqFAIL_2, - wci_reqERR_2 } ; - assign IF_wci_lastControlOp_3_07_BIT_3_08_THEN_wci_la_ETC___d722 = - { wci_lastControlOp_3[3] ? wci_lastControlOp_3[2:0] : 3'b111, - wci_lastConfigBE_3[4] ? wci_lastConfigBE_3[3:0] : 4'hF, - wci_lastOpWrite_3[1], - wci_lastControlOp_3[3], - wci_lastConfigBE_3[4], - wci_lastConfigAddr_3[32], + wci_1_sfCap, + wci_1_reqTO, + wci_1_reqFAIL, + wci_1_reqERR } ; + assign IF_wci_2_lastControlOp_93_BIT_3_94_THEN_wci_2__ETC___d608 = + { wci_2_lastControlOp[3] ? wci_2_lastControlOp[2:0] : 3'b111, + wci_2_lastConfigBE[4] ? wci_2_lastConfigBE[3:0] : 4'hF, + wci_2_lastOpWrite[1], + wci_2_lastControlOp[3], + wci_2_lastConfigBE[4], + wci_2_lastConfigAddr[32], 6'b0, - wci_sfCap_3, - wci_reqTO_3, - wci_reqFAIL_3, - wci_reqERR_3 } ; - assign IF_wci_lastControlOp_4_47_BIT_3_48_THEN_wci_la_ETC___d862 = - { wci_lastControlOp_4[3] ? wci_lastControlOp_4[2:0] : 3'b111, - wci_lastConfigBE_4[4] ? wci_lastConfigBE_4[3:0] : 4'hF, - wci_lastOpWrite_4[1], - wci_lastControlOp_4[3], - wci_lastConfigBE_4[4], - wci_lastConfigAddr_4[32], + wci_2_sfCap, + wci_2_reqTO, + wci_2_reqFAIL, + wci_2_reqERR } ; + assign IF_wci_3_lastControlOp_33_BIT_3_34_THEN_wci_3__ETC___d748 = + { wci_3_lastControlOp[3] ? wci_3_lastControlOp[2:0] : 3'b111, + wci_3_lastConfigBE[4] ? wci_3_lastConfigBE[3:0] : 4'hF, + wci_3_lastOpWrite[1], + wci_3_lastControlOp[3], + wci_3_lastConfigBE[4], + wci_3_lastConfigAddr[32], 6'b0, - wci_sfCap_4, - wci_reqTO_4, - wci_reqFAIL_4, - wci_reqERR_4 } ; - assign IF_wci_lastControlOp_5_87_BIT_3_88_THEN_wci_la_ETC___d1002 = - { wci_lastControlOp_5[3] ? wci_lastControlOp_5[2:0] : 3'b111, - wci_lastConfigBE_5[4] ? wci_lastConfigBE_5[3:0] : 4'hF, - wci_lastOpWrite_5[1], - wci_lastControlOp_5[3], - wci_lastConfigBE_5[4], - wci_lastConfigAddr_5[32], + wci_3_sfCap, + wci_3_reqTO, + wci_3_reqFAIL, + wci_3_reqERR } ; + assign IF_wci_4_lastControlOp_73_BIT_3_74_THEN_wci_4__ETC___d888 = + { wci_4_lastControlOp[3] ? wci_4_lastControlOp[2:0] : 3'b111, + wci_4_lastConfigBE[4] ? wci_4_lastConfigBE[3:0] : 4'hF, + wci_4_lastOpWrite[1], + wci_4_lastControlOp[3], + wci_4_lastConfigBE[4], + wci_4_lastConfigAddr[32], 6'b0, - wci_sfCap_5, - wci_reqTO_5, - wci_reqFAIL_5, - wci_reqERR_5 } ; - assign IF_wci_lastControlOp_6_127_BIT_3_128_THEN_wci__ETC___d1142 = - { wci_lastControlOp_6[3] ? wci_lastControlOp_6[2:0] : 3'b111, - wci_lastConfigBE_6[4] ? wci_lastConfigBE_6[3:0] : 4'hF, - wci_lastOpWrite_6[1], - wci_lastControlOp_6[3], - wci_lastConfigBE_6[4], - wci_lastConfigAddr_6[32], + wci_4_sfCap, + wci_4_reqTO, + wci_4_reqFAIL, + wci_4_reqERR } ; + assign IF_wci_5_lastControlOp_013_BIT_3_014_THEN_wci__ETC___d1028 = + { wci_5_lastControlOp[3] ? wci_5_lastControlOp[2:0] : 3'b111, + wci_5_lastConfigBE[4] ? wci_5_lastConfigBE[3:0] : 4'hF, + wci_5_lastOpWrite[1], + wci_5_lastControlOp[3], + wci_5_lastConfigBE[4], + wci_5_lastConfigAddr[32], 6'b0, - wci_sfCap_6, - wci_reqTO_6, - wci_reqFAIL_6, - wci_reqERR_6 } ; - assign IF_wci_lastControlOp_7_267_BIT_3_268_THEN_wci__ETC___d1282 = - { wci_lastControlOp_7[3] ? wci_lastControlOp_7[2:0] : 3'b111, - wci_lastConfigBE_7[4] ? wci_lastConfigBE_7[3:0] : 4'hF, - wci_lastOpWrite_7[1], - wci_lastControlOp_7[3], - wci_lastConfigBE_7[4], - wci_lastConfigAddr_7[32], + wci_5_sfCap, + wci_5_reqTO, + wci_5_reqFAIL, + wci_5_reqERR } ; + assign IF_wci_6_lastControlOp_153_BIT_3_154_THEN_wci__ETC___d1168 = + { wci_6_lastControlOp[3] ? wci_6_lastControlOp[2:0] : 3'b111, + wci_6_lastConfigBE[4] ? wci_6_lastConfigBE[3:0] : 4'hF, + wci_6_lastOpWrite[1], + wci_6_lastControlOp[3], + wci_6_lastConfigBE[4], + wci_6_lastConfigAddr[32], 6'b0, - wci_sfCap_7, - wci_reqTO_7, - wci_reqFAIL_7, - wci_reqERR_7 } ; - assign IF_wci_lastControlOp_87_BIT_3_88_THEN_wci_last_ETC___d302 = - { wci_lastControlOp[3] ? wci_lastControlOp[2:0] : 3'b111, - wci_lastConfigBE[4] ? wci_lastConfigBE[3:0] : 4'hF, - wci_lastOpWrite[1], - wci_lastControlOp[3], - wci_lastConfigBE[4], - wci_lastConfigAddr[32], + wci_6_sfCap, + wci_6_reqTO, + wci_6_reqFAIL, + wci_6_reqERR } ; + assign IF_wci_7_lastControlOp_293_BIT_3_294_THEN_wci__ETC___d1308 = + { wci_7_lastControlOp[3] ? wci_7_lastControlOp[2:0] : 3'b111, + wci_7_lastConfigBE[4] ? wci_7_lastConfigBE[3:0] : 4'hF, + wci_7_lastOpWrite[1], + wci_7_lastControlOp[3], + wci_7_lastConfigBE[4], + wci_7_lastConfigAddr[32], 6'b0, - wci_sfCap, - wci_reqTO, - wci_reqFAIL, - wci_reqERR } ; - assign IF_wci_lastControlOp_8_407_BIT_3_408_THEN_wci__ETC___d1422 = - { wci_lastControlOp_8[3] ? wci_lastControlOp_8[2:0] : 3'b111, - wci_lastConfigBE_8[4] ? wci_lastConfigBE_8[3:0] : 4'hF, - wci_lastOpWrite_8[1], - wci_lastControlOp_8[3], - wci_lastConfigBE_8[4], - wci_lastConfigAddr_8[32], + wci_7_sfCap, + wci_7_reqTO, + wci_7_reqFAIL, + wci_7_reqERR } ; + assign IF_wci_8_lastControlOp_433_BIT_3_434_THEN_wci__ETC___d1448 = + { wci_8_lastControlOp[3] ? wci_8_lastControlOp[2:0] : 3'b111, + wci_8_lastConfigBE[4] ? wci_8_lastConfigBE[3:0] : 4'hF, + wci_8_lastOpWrite[1], + wci_8_lastControlOp[3], + wci_8_lastConfigBE[4], + wci_8_lastConfigAddr[32], 6'b0, - wci_sfCap_8, - wci_reqTO_8, - wci_reqFAIL_8, - wci_reqERR_8 } ; - assign IF_wci_lastControlOp_9_547_BIT_3_548_THEN_wci__ETC___d1562 = - { wci_lastControlOp_9[3] ? wci_lastControlOp_9[2:0] : 3'b111, - wci_lastConfigBE_9[4] ? wci_lastConfigBE_9[3:0] : 4'hF, - wci_lastOpWrite_9[1], - wci_lastControlOp_9[3], - wci_lastConfigBE_9[4], - wci_lastConfigAddr_9[32], + wci_8_sfCap, + wci_8_reqTO, + wci_8_reqFAIL, + wci_8_reqERR } ; + assign IF_wci_9_lastControlOp_573_BIT_3_574_THEN_wci__ETC___d1588 = + { wci_9_lastControlOp[3] ? wci_9_lastControlOp[2:0] : 3'b111, + wci_9_lastConfigBE[4] ? wci_9_lastConfigBE[3:0] : 4'hF, + wci_9_lastOpWrite[1], + wci_9_lastControlOp[3], + wci_9_lastConfigBE[4], + wci_9_lastConfigAddr[32], 6'b0, - wci_sfCap_9, - wci_reqTO_9, - wci_reqFAIL_9, - wci_reqERR_9 } ; - assign NOT_cpReq_337_BITS_11_TO_4_340_EQ_0x30_569_623_ETC___d2686 = + wci_9_sfCap, + wci_9_reqTO, + wci_9_reqFAIL, + wci_9_reqERR } ; + assign NOT_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_TH_ETC___d5023 = + _theResult_____1__h75739 != 4'd0 && + _theResult_____1__h75739 != 4'd1 && + _theResult_____1__h75739 != 4'd2 && + _theResult_____1__h75739 != 4'd3 && + _theResult_____1__h75739 != 4'd4 && + _theResult_____1__h75739 != 4'd5 && + _theResult_____1__h75739 != 4'd6 && + _theResult_____1__h75739 != 4'd7 && + _theResult_____1__h75739 != 4'd8 && + _theResult_____1__h75739 != 4'd9 && + _theResult_____1__h75739 != 4'd10 && + _theResult_____1__h75739 != 4'd11 && + _theResult_____1__h75739 != 4'd12 && + _theResult_____1__h75739 != 4'd13 && + _theResult_____1__h75739 != 4'd14 && + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d5021 && + !dispatched ; + assign NOT_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_TH_ETC___d3641 = + _theResult_____1__h75724 != 4'd0 && + _theResult_____1__h75724 != 4'd1 && + _theResult_____1__h75724 != 4'd2 && + _theResult_____1__h75724 != 4'd3 && + _theResult_____1__h75724 != 4'd4 && + _theResult_____1__h75724 != 4'd5 && + _theResult_____1__h75724 != 4'd6 && + _theResult_____1__h75724 != 4'd7 && + _theResult_____1__h75724 != 4'd8 && + _theResult_____1__h75724 != 4'd9 && + _theResult_____1__h75724 != 4'd10 && + _theResult_____1__h75724 != 4'd11 && + _theResult_____1__h75724 != 4'd12 && + _theResult_____1__h75724 != 4'd13 && + _theResult_____1__h75724 != 4'd14 && + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3639 && + !dispatched ; + assign NOT_cpReq_363_BITS_11_TO_4_366_EQ_0x30_595_649_ETC___d2712 = cpReq[11:4] != 8'h30 && cpReq[11:4] != 8'h34 && cpReq[11:4] != 8'h38 && cpReq[11:4] != 8'h3C && @@ -16811,384 +16632,694 @@ module mkOCCP(pciDevice, cpReq[11:4] != 8'h4C && adminResp2F$FULL_N && !dispatched ; - assign NOT_cpReq_337_BITS_64_TO_62_338_EQ_0_855_860_A_ETC___d5047 = - cpReq[64:62] != 3'd0 && _theResult_____1__h75875 != 4'd0 && - _theResult_____1__h75875 != 4'd1 && - _theResult_____1__h75875 != 4'd2 && - _theResult_____1__h75875 != 4'd3 && - _theResult_____1__h75875 != 4'd4 && - _theResult_____1__h75875 != 4'd5 && - _theResult_____1__h75875 != 4'd6 && - _theResult_____1__h75875 != 4'd7 && - _theResult_____1__h75875 != 4'd8 && - _theResult_____1__h75875 != 4'd9 && - _theResult_____1__h75875 != 4'd10 && - _theResult_____1__h75875 != 4'd11 && - _theResult_____1__h75875 != 4'd12 && - _theResult_____1__h75875 != 4'd13 && - _theResult_____1__h75875 != 4'd14 && + assign NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d3796 = + cpReq[9:6] == 4'h8 && + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793 && !dispatched ; - assign NOT_cpReq_337_BITS_64_TO_62_338_EQ_3_851_859_A_ETC___d3950 = - cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h75875 == 4'd0 && - cpReq[37:36] != 2'd2 && - (cpReq[37:36] != 2'd1 || cpReq[19:9] != 11'd0) && - cpReq[9:6] != 4'h8 && - cpReq[9:6] != 4'h9 && - cpReq[9:6] != 4'hA && - NOT_cpReq_337_BITS_9_TO_6_770_EQ_0xC_809_935_A_ETC___d2936 ; - assign NOT_cpReq_337_BITS_64_TO_62_338_EQ_3_851_859_A_ETC___d4026 = - cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h75875 == 4'd1 && - cpReq[37:36] != 2'd2 && - (cpReq[37:36] != 2'd1 || cpReq[19:9] != 11'd0) && - cpReq[9:6] != 4'h8 && - cpReq[9:6] != 4'h9 && - cpReq[9:6] != 4'hA && - NOT_cpReq_337_BITS_9_TO_6_770_EQ_0xC_809_935_A_ETC___d2999 ; - assign NOT_cpReq_337_BITS_64_TO_62_338_EQ_3_851_859_A_ETC___d4102 = - cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h75875 == 4'd2 && - cpReq[37:36] != 2'd2 && - (cpReq[37:36] != 2'd1 || cpReq[19:9] != 11'd0) && - cpReq[9:6] != 4'h8 && - cpReq[9:6] != 4'h9 && - cpReq[9:6] != 4'hA && - NOT_cpReq_337_BITS_9_TO_6_770_EQ_0xC_809_935_A_ETC___d3062 ; - assign NOT_cpReq_337_BITS_64_TO_62_338_EQ_3_851_859_A_ETC___d4178 = - cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h75875 == 4'd3 && - cpReq[37:36] != 2'd2 && - (cpReq[37:36] != 2'd1 || cpReq[19:9] != 11'd0) && - cpReq[9:6] != 4'h8 && - cpReq[9:6] != 4'h9 && - cpReq[9:6] != 4'hA && - NOT_cpReq_337_BITS_9_TO_6_770_EQ_0xC_809_935_A_ETC___d3125 ; - assign NOT_cpReq_337_BITS_64_TO_62_338_EQ_3_851_859_A_ETC___d4254 = - cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h75875 == 4'd4 && - cpReq[37:36] != 2'd2 && - (cpReq[37:36] != 2'd1 || cpReq[19:9] != 11'd0) && - cpReq[9:6] != 4'h8 && - cpReq[9:6] != 4'h9 && - cpReq[9:6] != 4'hA && - NOT_cpReq_337_BITS_9_TO_6_770_EQ_0xC_809_935_A_ETC___d3188 ; - assign NOT_cpReq_337_BITS_64_TO_62_338_EQ_3_851_859_A_ETC___d4330 = - cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h75875 == 4'd5 && - cpReq[37:36] != 2'd2 && - (cpReq[37:36] != 2'd1 || cpReq[19:9] != 11'd0) && - cpReq[9:6] != 4'h8 && - cpReq[9:6] != 4'h9 && - cpReq[9:6] != 4'hA && - NOT_cpReq_337_BITS_9_TO_6_770_EQ_0xC_809_935_A_ETC___d3251 ; - assign NOT_cpReq_337_BITS_64_TO_62_338_EQ_3_851_859_A_ETC___d4406 = - cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h75875 == 4'd6 && - cpReq[37:36] != 2'd2 && - (cpReq[37:36] != 2'd1 || cpReq[19:9] != 11'd0) && - cpReq[9:6] != 4'h8 && - cpReq[9:6] != 4'h9 && - cpReq[9:6] != 4'hA && - NOT_cpReq_337_BITS_9_TO_6_770_EQ_0xC_809_935_A_ETC___d3314 ; - assign NOT_cpReq_337_BITS_64_TO_62_338_EQ_3_851_859_A_ETC___d4482 = - cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h75875 == 4'd7 && - cpReq[37:36] != 2'd2 && - (cpReq[37:36] != 2'd1 || cpReq[19:9] != 11'd0) && - cpReq[9:6] != 4'h8 && - cpReq[9:6] != 4'h9 && - cpReq[9:6] != 4'hA && - NOT_cpReq_337_BITS_9_TO_6_770_EQ_0xC_809_935_A_ETC___d3377 ; - assign NOT_cpReq_337_BITS_64_TO_62_338_EQ_3_851_859_A_ETC___d4558 = - cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h75875 == 4'd8 && - cpReq[37:36] != 2'd2 && - (cpReq[37:36] != 2'd1 || cpReq[19:9] != 11'd0) && - cpReq[9:6] != 4'h8 && - cpReq[9:6] != 4'h9 && - cpReq[9:6] != 4'hA && - NOT_cpReq_337_BITS_9_TO_6_770_EQ_0xC_809_935_A_ETC___d3440 ; - assign NOT_cpReq_337_BITS_64_TO_62_338_EQ_3_851_859_A_ETC___d4634 = - cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h75875 == 4'd9 && - cpReq[37:36] != 2'd2 && - (cpReq[37:36] != 2'd1 || cpReq[19:9] != 11'd0) && - cpReq[9:6] != 4'h8 && - cpReq[9:6] != 4'h9 && - cpReq[9:6] != 4'hA && - NOT_cpReq_337_BITS_9_TO_6_770_EQ_0xC_809_935_A_ETC___d3503 ; - assign NOT_cpReq_337_BITS_64_TO_62_338_EQ_3_851_859_A_ETC___d4710 = - cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h75875 == 4'd10 && - cpReq[37:36] != 2'd2 && - (cpReq[37:36] != 2'd1 || cpReq[19:9] != 11'd0) && - cpReq[9:6] != 4'h8 && - cpReq[9:6] != 4'h9 && - cpReq[9:6] != 4'hA && - NOT_cpReq_337_BITS_9_TO_6_770_EQ_0xC_809_935_A_ETC___d3566 ; - assign NOT_cpReq_337_BITS_64_TO_62_338_EQ_3_851_859_A_ETC___d4786 = - cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h75875 == 4'd11 && - cpReq[37:36] != 2'd2 && - (cpReq[37:36] != 2'd1 || cpReq[19:9] != 11'd0) && - cpReq[9:6] != 4'h8 && - cpReq[9:6] != 4'h9 && - cpReq[9:6] != 4'hA && - NOT_cpReq_337_BITS_9_TO_6_770_EQ_0xC_809_935_A_ETC___d3629 ; - assign NOT_cpReq_337_BITS_64_TO_62_338_EQ_3_851_859_A_ETC___d4862 = - cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h75875 == 4'd12 && - cpReq[37:36] != 2'd2 && - (cpReq[37:36] != 2'd1 || cpReq[19:9] != 11'd0) && - cpReq[9:6] != 4'h8 && - cpReq[9:6] != 4'h9 && - cpReq[9:6] != 4'hA && - NOT_cpReq_337_BITS_9_TO_6_770_EQ_0xC_809_935_A_ETC___d3692 ; - assign NOT_cpReq_337_BITS_64_TO_62_338_EQ_3_851_859_A_ETC___d4938 = - cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h75875 == 4'd13 && - cpReq[37:36] != 2'd2 && - (cpReq[37:36] != 2'd1 || cpReq[19:9] != 11'd0) && - cpReq[9:6] != 4'h8 && - cpReq[9:6] != 4'h9 && - cpReq[9:6] != 4'hA && - NOT_cpReq_337_BITS_9_TO_6_770_EQ_0xC_809_935_A_ETC___d3755 ; - assign NOT_cpReq_337_BITS_64_TO_62_338_EQ_3_851_859_A_ETC___d5014 = - cpReq[64:62] != 3'd3 && cpReq[64:62] != 3'd0 && - _theResult_____1__h75875 == 4'd14 && - cpReq[37:36] != 2'd2 && - (cpReq[37:36] != 2'd1 || cpReq[19:9] != 11'd0) && - cpReq[9:6] != 4'h8 && - cpReq[9:6] != 4'h9 && - cpReq[9:6] != 4'hA && - NOT_cpReq_337_BITS_9_TO_6_770_EQ_0xC_809_935_A_ETC___d3818 ; - assign NOT_cpReq_337_BITS_9_TO_6_770_EQ_0xC_809_935_A_ETC___d2936 = - cpReq[9:6] != 4'hC && !wci_busy && wci_respF$FULL_N && + assign NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d3805 = + cpReq[9:6] == 4'h9 && + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793 && !dispatched ; - assign NOT_cpReq_337_BITS_9_TO_6_770_EQ_0xC_809_935_A_ETC___d2999 = - cpReq[9:6] != 4'hC && !wci_busy_1 && wci_respF_1$FULL_N && + assign NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d3816 = + cpReq[9:6] == 4'hA && + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793 && !dispatched ; - assign NOT_cpReq_337_BITS_9_TO_6_770_EQ_0xC_809_935_A_ETC___d3062 = - cpReq[9:6] != 4'hC && !wci_busy_2 && wci_respF_2$FULL_N && + assign NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d3827 = + cpReq[9:6] == 4'hC && + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793 && !dispatched ; - assign NOT_cpReq_337_BITS_9_TO_6_770_EQ_0xC_809_935_A_ETC___d3125 = - cpReq[9:6] != 4'hC && !wci_busy_3 && wci_respF_3$FULL_N && + assign NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d4933 = + cpReq[37:36] != 2'd1 || cpReq[19:9] != 11'd0 || + (wci_0_wReset_n || wci_0_respF$FULL_N) && + (!wci_0_wReset_n || !wci_0_reqF_cntr_r) ; + assign NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d4939 = + cpReq[37:36] != 2'd1 || cpReq[19:9] != 11'd0 || + (wci_1_wReset_n || wci_1_respF$FULL_N) && + (!wci_1_wReset_n || !wci_1_reqF_cntr_r) ; + assign NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d4945 = + cpReq[37:36] != 2'd1 || cpReq[19:9] != 11'd0 || + (wci_2_wReset_n || wci_2_respF$FULL_N) && + (!wci_2_wReset_n || !wci_2_reqF_cntr_r) ; + assign NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d4951 = + cpReq[37:36] != 2'd1 || cpReq[19:9] != 11'd0 || + (wci_3_wReset_n || wci_3_respF$FULL_N) && + (!wci_3_wReset_n || !wci_3_reqF_cntr_r) ; + assign NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d4957 = + cpReq[37:36] != 2'd1 || cpReq[19:9] != 11'd0 || + (wci_4_wReset_n || wci_4_respF$FULL_N) && + (!wci_4_wReset_n || !wci_4_reqF_cntr_r) ; + assign NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d4963 = + cpReq[37:36] != 2'd1 || cpReq[19:9] != 11'd0 || + (wci_5_wReset_n || wci_5_respF$FULL_N) && + (!wci_5_wReset_n || !wci_5_reqF_cntr_r) ; + assign NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d4969 = + cpReq[37:36] != 2'd1 || cpReq[19:9] != 11'd0 || + (wci_6_wReset_n || wci_6_respF$FULL_N) && + (!wci_6_wReset_n || !wci_6_reqF_cntr_r) ; + assign NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d4975 = + cpReq[37:36] != 2'd1 || cpReq[19:9] != 11'd0 || + (wci_7_wReset_n || wci_7_respF$FULL_N) && + (!wci_7_wReset_n || !wci_7_reqF_cntr_r) ; + assign NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d4981 = + cpReq[37:36] != 2'd1 || cpReq[19:9] != 11'd0 || + (wci_8_wReset_n || wci_8_respF$FULL_N) && + (!wci_8_wReset_n || !wci_8_reqF_cntr_r) ; + assign NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d4987 = + cpReq[37:36] != 2'd1 || cpReq[19:9] != 11'd0 || + (wci_9_wReset_n || wci_9_respF$FULL_N) && + (!wci_9_wReset_n || !wci_9_reqF_cntr_r) ; + assign NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d4993 = + cpReq[37:36] != 2'd1 || cpReq[19:9] != 11'd0 || + (wci_10_wReset_n || wci_10_respF$FULL_N) && + (!wci_10_wReset_n || !wci_10_reqF_cntr_r) ; + assign NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d4999 = + cpReq[37:36] != 2'd1 || cpReq[19:9] != 11'd0 || + (wci_11_wReset_n || wci_11_respF$FULL_N) && + (!wci_11_wReset_n || !wci_11_reqF_cntr_r) ; + assign NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d5005 = + cpReq[37:36] != 2'd1 || cpReq[19:9] != 11'd0 || + (wci_12_wReset_n || wci_12_respF$FULL_N) && + (!wci_12_wReset_n || !wci_12_reqF_cntr_r) ; + assign NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d5011 = + cpReq[37:36] != 2'd1 || cpReq[19:9] != 11'd0 || + (wci_13_wReset_n || wci_13_respF$FULL_N) && + (!wci_13_wReset_n || !wci_13_reqF_cntr_r) ; + assign NOT_cpReq_363_BITS_37_TO_36_649_EQ_1_703_760_O_ETC___d5017 = + cpReq[37:36] != 2'd1 || cpReq[19:9] != 11'd0 || + (wci_14_wReset_n || wci_14_respF$FULL_N) && + (!wci_14_wReset_n || !wci_14_reqF_cntr_r) ; + assign NOT_cpReq_363_BITS_61_TO_60_848_EQ_1_967_993_O_ETC___d3029 = + cpReq[9:6] == 4'hC && + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d2986 && !dispatched ; - assign NOT_cpReq_337_BITS_9_TO_6_770_EQ_0xC_809_935_A_ETC___d3188 = - cpReq[9:6] != 4'hC && !wci_busy_4 && wci_respF_4$FULL_N && + assign NOT_cpReq_363_BITS_61_TO_60_848_EQ_1_967_993_O_ETC___d3039 = + (cpReq[61:60] != 2'd1 || cpReq[19:9] != 11'd0) && + cpReq[9:6] != 4'h9 && + cpReq[9:6] != 4'hC && + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d2986 && !dispatched ; - assign NOT_cpReq_337_BITS_9_TO_6_770_EQ_0xC_809_935_A_ETC___d3251 = - cpReq[9:6] != 4'hC && !wci_busy_5 && wci_respF_5$FULL_N && + assign NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d3688 = + cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && + cpReq[64:62] != 3'd0 && + _theResult_____1__h75739 == 4'd0 && + cpReq[37:36] == 2'd2 && + wci_0_wReset_n && + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3681 && !dispatched ; - assign NOT_cpReq_337_BITS_9_TO_6_770_EQ_0xC_809_935_A_ETC___d3314 = - cpReq[9:6] != 4'hC && !wci_busy_6 && wci_respF_6$FULL_N && + assign NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d3701 = + cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && + cpReq[64:62] != 3'd0 && + _theResult_____1__h75739 == 4'd0 && + cpReq[37:36] == 2'd2 && + !wci_0_wReset_n && + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3694 && !dispatched ; - assign NOT_cpReq_337_BITS_9_TO_6_770_EQ_0xC_809_935_A_ETC___d3377 = - cpReq[9:6] != 4'hC && !wci_busy_7 && wci_respF_7$FULL_N && + assign NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d3742 = + cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && + cpReq[64:62] != 3'd0 && + _theResult_____1__h75739 == 4'd0 && + cpReq[37:36] == 2'd1 && + cpReq[19:9] == 11'd0 && + wci_0_wReset_n && + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3735 && !dispatched ; - assign NOT_cpReq_337_BITS_9_TO_6_770_EQ_0xC_809_935_A_ETC___d3440 = - cpReq[9:6] != 4'hC && !wci_busy_8 && wci_respF_8$FULL_N && + assign NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d3757 = + cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && + cpReq[64:62] != 3'd0 && + _theResult_____1__h75739 == 4'd0 && + cpReq[37:36] == 2'd1 && + cpReq[19:9] == 11'd0 && + !wci_0_wReset_n && + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3750 && !dispatched ; - assign NOT_cpReq_337_BITS_9_TO_6_770_EQ_0xC_809_935_A_ETC___d3503 = - cpReq[9:6] != 4'hC && !wci_busy_9 && wci_respF_9$FULL_N && + assign NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d3858 = + cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && + cpReq[64:62] != 3'd0 && + _theResult_____1__h75739 == 4'd1 && + cpReq[37:36] == 2'd2 && + wci_1_wReset_n && + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3851 && !dispatched ; - assign NOT_cpReq_337_BITS_9_TO_6_770_EQ_0xC_809_935_A_ETC___d3566 = - cpReq[9:6] != 4'hC && !wci_busy_10 && wci_respF_10$FULL_N && + assign NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d3870 = + cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && + cpReq[64:62] != 3'd0 && + _theResult_____1__h75739 == 4'd1 && + cpReq[37:36] == 2'd2 && + !wci_1_wReset_n && + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3863 && !dispatched ; - assign NOT_cpReq_337_BITS_9_TO_6_770_EQ_0xC_809_935_A_ETC___d3629 = - cpReq[9:6] != 4'hC && !wci_busy_11 && wci_respF_11$FULL_N && + assign NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d3883 = + cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && + cpReq[64:62] != 3'd0 && + _theResult_____1__h75739 == 4'd1 && + cpReq[37:36] == 2'd1 && + cpReq[19:9] == 11'd0 && + wci_1_wReset_n && + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3876 && !dispatched ; - assign NOT_cpReq_337_BITS_9_TO_6_770_EQ_0xC_809_935_A_ETC___d3692 = - cpReq[9:6] != 4'hC && !wci_busy_12 && wci_respF_12$FULL_N && + assign NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d3893 = + cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && + cpReq[64:62] != 3'd0 && + _theResult_____1__h75739 == 4'd1 && + cpReq[37:36] == 2'd1 && + cpReq[19:9] == 11'd0 && + !wci_1_wReset_n && + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3886 && !dispatched ; - assign NOT_cpReq_337_BITS_9_TO_6_770_EQ_0xC_809_935_A_ETC___d3755 = - cpReq[9:6] != 4'hC && !wci_busy_13 && wci_respF_13$FULL_N && + assign NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d3935 = + cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && + cpReq[64:62] != 3'd0 && + _theResult_____1__h75739 == 4'd2 && + cpReq[37:36] == 2'd2 && + wci_2_wReset_n && + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3928 && !dispatched ; - assign NOT_cpReq_337_BITS_9_TO_6_770_EQ_0xC_809_935_A_ETC___d3818 = - cpReq[9:6] != 4'hC && !wci_busy_14 && wci_respF_14$FULL_N && + assign NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d3947 = + cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && + cpReq[64:62] != 3'd0 && + _theResult_____1__h75739 == 4'd2 && + cpReq[37:36] == 2'd2 && + !wci_2_wReset_n && + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3940 && !dispatched ; - assign NOT_cpReq_337_BIT_36_898_906_AND_NOT_wci_busy__ETC___d2907 = - !cpReq[36] && !wci_busy && wci_respF$FULL_N && !dispatched ; - assign NOT_cpReq_337_BIT_36_898_906_AND_NOT_wci_busy__ETC___d2974 = - !cpReq[36] && !wci_busy_1 && wci_respF_1$FULL_N && !dispatched ; - assign NOT_cpReq_337_BIT_36_898_906_AND_NOT_wci_busy__ETC___d3037 = - !cpReq[36] && !wci_busy_2 && wci_respF_2$FULL_N && !dispatched ; - assign NOT_cpReq_337_BIT_36_898_906_AND_NOT_wci_busy__ETC___d3100 = - !cpReq[36] && !wci_busy_3 && wci_respF_3$FULL_N && !dispatched ; - assign NOT_cpReq_337_BIT_36_898_906_AND_NOT_wci_busy__ETC___d3163 = - !cpReq[36] && !wci_busy_4 && wci_respF_4$FULL_N && !dispatched ; - assign NOT_cpReq_337_BIT_36_898_906_AND_NOT_wci_busy__ETC___d3226 = - !cpReq[36] && !wci_busy_5 && wci_respF_5$FULL_N && !dispatched ; - assign NOT_cpReq_337_BIT_36_898_906_AND_NOT_wci_busy__ETC___d3289 = - !cpReq[36] && !wci_busy_6 && wci_respF_6$FULL_N && !dispatched ; - assign NOT_cpReq_337_BIT_36_898_906_AND_NOT_wci_busy__ETC___d3352 = - !cpReq[36] && !wci_busy_7 && wci_respF_7$FULL_N && !dispatched ; - assign NOT_cpReq_337_BIT_36_898_906_AND_NOT_wci_busy__ETC___d3415 = - !cpReq[36] && !wci_busy_8 && wci_respF_8$FULL_N && !dispatched ; - assign NOT_cpReq_337_BIT_36_898_906_AND_NOT_wci_busy__ETC___d3478 = - !cpReq[36] && !wci_busy_9 && wci_respF_9$FULL_N && !dispatched ; - assign NOT_cpReq_337_BIT_36_898_906_AND_NOT_wci_busy__ETC___d3541 = - !cpReq[36] && !wci_busy_10 && wci_respF_10$FULL_N && + assign NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d3958 = + cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && + cpReq[64:62] != 3'd0 && + _theResult_____1__h75739 == 4'd2 && + cpReq[37:36] == 2'd1 && + cpReq[19:9] == 11'd0 && + wci_2_wReset_n && + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3951 && !dispatched ; - assign NOT_cpReq_337_BIT_36_898_906_AND_NOT_wci_busy__ETC___d3604 = - !cpReq[36] && !wci_busy_11 && wci_respF_11$FULL_N && + assign NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d3968 = + cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && + cpReq[64:62] != 3'd0 && + _theResult_____1__h75739 == 4'd2 && + cpReq[37:36] == 2'd1 && + cpReq[19:9] == 11'd0 && + !wci_2_wReset_n && + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3961 && !dispatched ; - assign NOT_cpReq_337_BIT_36_898_906_AND_NOT_wci_busy__ETC___d3667 = - !cpReq[36] && !wci_busy_12 && wci_respF_12$FULL_N && + assign NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4010 = + cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && + cpReq[64:62] != 3'd0 && + _theResult_____1__h75739 == 4'd3 && + cpReq[37:36] == 2'd2 && + wci_3_wReset_n && + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4003 && !dispatched ; - assign NOT_cpReq_337_BIT_36_898_906_AND_NOT_wci_busy__ETC___d3730 = - !cpReq[36] && !wci_busy_13 && wci_respF_13$FULL_N && + assign NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4022 = + cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && + cpReq[64:62] != 3'd0 && + _theResult_____1__h75739 == 4'd3 && + cpReq[37:36] == 2'd2 && + !wci_3_wReset_n && + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4015 && !dispatched ; - assign NOT_cpReq_337_BIT_36_898_906_AND_NOT_wci_busy__ETC___d3793 = - !cpReq[36] && !wci_busy_14 && wci_respF_14$FULL_N && + assign NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4033 = + cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && + cpReq[64:62] != 3'd0 && + _theResult_____1__h75739 == 4'd3 && + cpReq[37:36] == 2'd1 && + cpReq[19:9] == 11'd0 && + wci_3_wReset_n && + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4026 && !dispatched ; - assign NOT_wci_busy_10_610_510_AND_wci_wReset_n_10_59_ETC___d3523 = - !wci_busy_10 && (wci_wReset_n_10 || wci_respF_10$FULL_N) && + assign NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4043 = + cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && + cpReq[64:62] != 3'd0 && + _theResult_____1__h75739 == 4'd3 && + cpReq[37:36] == 2'd1 && + cpReq[19:9] == 11'd0 && + !wci_3_wReset_n && + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4036 && !dispatched ; - assign NOT_wci_busy_10_860_AND_wci_wReset_n_90_OR_wci_ETC___d2878 = - !wci_busy && (wci_wReset_n || wci_respF$FULL_N) && !dispatched ; - assign NOT_wci_busy_11_750_573_AND_wci_wReset_n_11_73_ETC___d3586 = - !wci_busy_11 && (wci_wReset_n_11 || wci_respF_11$FULL_N) && + assign NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4085 = + cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && + cpReq[64:62] != 3'd0 && + _theResult_____1__h75739 == 4'd4 && + cpReq[37:36] == 2'd2 && + wci_4_wReset_n && + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4078 && !dispatched ; - assign NOT_wci_busy_12_890_636_AND_wci_wReset_n_12_87_ETC___d3649 = - !wci_busy_12 && (wci_wReset_n_12 || wci_respF_12$FULL_N) && + assign NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4097 = + cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && + cpReq[64:62] != 3'd0 && + _theResult_____1__h75739 == 4'd4 && + cpReq[37:36] == 2'd2 && + !wci_4_wReset_n && + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4090 && !dispatched ; - assign NOT_wci_busy_13_030_699_AND_wci_wReset_n_13_01_ETC___d3712 = - !wci_busy_13 && (wci_wReset_n_13 || wci_respF_13$FULL_N) && + assign NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4108 = + cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && + cpReq[64:62] != 3'd0 && + _theResult_____1__h75739 == 4'd4 && + cpReq[37:36] == 2'd1 && + cpReq[19:9] == 11'd0 && + wci_4_wReset_n && + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4101 && !dispatched ; - assign NOT_wci_busy_14_170_762_AND_wci_wReset_n_14_15_ETC___d3775 = - !wci_busy_14 && (wci_wReset_n_14 || wci_respF_14$FULL_N) && + assign NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4118 = + cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && + cpReq[64:62] != 3'd0 && + _theResult_____1__h75739 == 4'd4 && + cpReq[37:36] == 2'd1 && + cpReq[19:9] == 11'd0 && + !wci_4_wReset_n && + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4111 && !dispatched ; - assign NOT_wci_busy_1_50_943_AND_wci_wReset_n_1_30_OR_ETC___d2956 = - !wci_busy_1 && (wci_wReset_n_1 || wci_respF_1$FULL_N) && + assign NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4160 = + cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && + cpReq[64:62] != 3'd0 && + _theResult_____1__h75739 == 4'd5 && + cpReq[37:36] == 2'd2 && + wci_5_wReset_n && + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4153 && !dispatched ; - assign NOT_wci_busy_2_90_006_AND_wci_wReset_n_2_70_OR_ETC___d3019 = - !wci_busy_2 && (wci_wReset_n_2 || wci_respF_2$FULL_N) && + assign NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4172 = + cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && + cpReq[64:62] != 3'd0 && + _theResult_____1__h75739 == 4'd5 && + cpReq[37:36] == 2'd2 && + !wci_5_wReset_n && + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4165 && !dispatched ; - assign NOT_wci_busy_3_30_069_AND_wci_wReset_n_3_10_OR_ETC___d3082 = - !wci_busy_3 && (wci_wReset_n_3 || wci_respF_3$FULL_N) && + assign NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4183 = + cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && + cpReq[64:62] != 3'd0 && + _theResult_____1__h75739 == 4'd5 && + cpReq[37:36] == 2'd1 && + cpReq[19:9] == 11'd0 && + wci_5_wReset_n && + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4176 && !dispatched ; - assign NOT_wci_busy_4_70_132_AND_wci_wReset_n_4_50_OR_ETC___d3145 = - !wci_busy_4 && (wci_wReset_n_4 || wci_respF_4$FULL_N) && + assign NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4193 = + cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && + cpReq[64:62] != 3'd0 && + _theResult_____1__h75739 == 4'd5 && + cpReq[37:36] == 2'd1 && + cpReq[19:9] == 11'd0 && + !wci_5_wReset_n && + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4186 && !dispatched ; - assign NOT_wci_busy_5_10_195_AND_wci_wReset_n_5_90_OR_ETC___d3208 = - !wci_busy_5 && (wci_wReset_n_5 || wci_respF_5$FULL_N) && + assign NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4235 = + cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && + cpReq[64:62] != 3'd0 && + _theResult_____1__h75739 == 4'd6 && + cpReq[37:36] == 2'd2 && + wci_6_wReset_n && + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4228 && !dispatched ; - assign NOT_wci_busy_6_050_258_AND_wci_wReset_n_6_030__ETC___d3271 = - !wci_busy_6 && (wci_wReset_n_6 || wci_respF_6$FULL_N) && + assign NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4247 = + cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && + cpReq[64:62] != 3'd0 && + _theResult_____1__h75739 == 4'd6 && + cpReq[37:36] == 2'd2 && + !wci_6_wReset_n && + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4240 && !dispatched ; - assign NOT_wci_busy_7_190_321_AND_wci_wReset_n_7_170__ETC___d3334 = - !wci_busy_7 && (wci_wReset_n_7 || wci_respF_7$FULL_N) && + assign NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4258 = + cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && + cpReq[64:62] != 3'd0 && + _theResult_____1__h75739 == 4'd6 && + cpReq[37:36] == 2'd1 && + cpReq[19:9] == 11'd0 && + wci_6_wReset_n && + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4251 && !dispatched ; - assign NOT_wci_busy_8_330_384_AND_wci_wReset_n_8_310__ETC___d3397 = - !wci_busy_8 && (wci_wReset_n_8 || wci_respF_8$FULL_N) && + assign NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4268 = + cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && + cpReq[64:62] != 3'd0 && + _theResult_____1__h75739 == 4'd6 && + cpReq[37:36] == 2'd1 && + cpReq[19:9] == 11'd0 && + !wci_6_wReset_n && + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4261 && !dispatched ; - assign NOT_wci_busy_9_470_447_AND_wci_wReset_n_9_450__ETC___d3460 = - !wci_busy_9 && (wci_wReset_n_9 || wci_respF_9$FULL_N) && + assign NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4310 = + cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && + cpReq[64:62] != 3'd0 && + _theResult_____1__h75739 == 4'd7 && + cpReq[37:36] == 2'd2 && + wci_7_wReset_n && + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4303 && !dispatched ; - assign _281474976710656_MINUS_timeServ_delSecond_BITS__ETC__q2 = - _281474976710656_MINUS_timeServ_delSecond__q1[49:28] ; - assign _281474976710656_MINUS_timeServ_delSecond__q1 = - 50'h1000000000000 - timeServ_delSecond ; - assign _theResult_____1__h75857 = - (cpReq[61:60] == 2'd2) ? wn___1__h76646 : wn__h75856 ; - assign _theResult_____1__h75875 = - (cpReq[37:36] == 2'd2) ? wn___1__h76646 : wn__h75856 ; - assign bAddr__h112904 = { cpReqF$D_OUT[57:36], 2'b0 } ; - assign bAddr__h113364 = { cpReqF$D_OUT[25:4], 2'b0 } ; - assign cpReq_337_BITS_11_TO_4_340_EQ_0x30_569_OR_cpRe_ETC___d2606 = - (cpReq[11:4] == 8'h30 || cpReq[11:4] == 8'h34 || - cpReq[11:4] == 8'h38 || - cpReq[11:4] == 8'h3C || - cpReq[11:4] == 8'h40 || - cpReq[11:4] == 8'h44 || - cpReq[11:4] == 8'h48) && - adminResp2F$FULL_N && + assign NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4322 = + cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && + cpReq[64:62] != 3'd0 && + _theResult_____1__h75739 == 4'd7 && + cpReq[37:36] == 2'd2 && + !wci_7_wReset_n && + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4315 && !dispatched ; - assign cpReq_337_BITS_11_TO_4_340_ULT_0x30___d2412 = cpReq[11:4] < 8'h30 ; - assign cpReq_337_BITS_11_TO_4_340_ULT_0xC0___d2568 = cpReq[11:4] < 8'hC0 ; - assign cpReq_337_BITS_27_TO_4_410_ULT_0x1000___d2840 = - cpReq[27:4] < 24'h001000 ; - assign cpReq_337_BITS_27_TO_4_410_ULT_0x100___d2411 = - cpReq[27:4] < 24'h000100 ; - assign cpReq_337_BITS_9_TO_6_770_EQ_0xC_809_AND_NOT_w_ETC___d2927 = - cpReq[9:6] == 4'hC && !wci_busy && wci_respF$FULL_N && + assign NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4333 = + cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && + cpReq[64:62] != 3'd0 && + _theResult_____1__h75739 == 4'd7 && + cpReq[37:36] == 2'd1 && + cpReq[19:9] == 11'd0 && + wci_7_wReset_n && + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4326 && + !dispatched ; + assign NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4343 = + cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && + cpReq[64:62] != 3'd0 && + _theResult_____1__h75739 == 4'd7 && + cpReq[37:36] == 2'd1 && + cpReq[19:9] == 11'd0 && + !wci_7_wReset_n && + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4336 && + !dispatched ; + assign NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4385 = + cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && + cpReq[64:62] != 3'd0 && + _theResult_____1__h75739 == 4'd8 && + cpReq[37:36] == 2'd2 && + wci_8_wReset_n && + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4378 && + !dispatched ; + assign NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4397 = + cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && + cpReq[64:62] != 3'd0 && + _theResult_____1__h75739 == 4'd8 && + cpReq[37:36] == 2'd2 && + !wci_8_wReset_n && + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4390 && + !dispatched ; + assign NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4408 = + cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && + cpReq[64:62] != 3'd0 && + _theResult_____1__h75739 == 4'd8 && + cpReq[37:36] == 2'd1 && + cpReq[19:9] == 11'd0 && + wci_8_wReset_n && + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4401 && + !dispatched ; + assign NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4418 = + cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && + cpReq[64:62] != 3'd0 && + _theResult_____1__h75739 == 4'd8 && + cpReq[37:36] == 2'd1 && + cpReq[19:9] == 11'd0 && + !wci_8_wReset_n && + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4411 && + !dispatched ; + assign NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4460 = + cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && + cpReq[64:62] != 3'd0 && + _theResult_____1__h75739 == 4'd9 && + cpReq[37:36] == 2'd2 && + wci_9_wReset_n && + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4453 && + !dispatched ; + assign NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4472 = + cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && + cpReq[64:62] != 3'd0 && + _theResult_____1__h75739 == 4'd9 && + cpReq[37:36] == 2'd2 && + !wci_9_wReset_n && + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4465 && + !dispatched ; + assign NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4483 = + cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && + cpReq[64:62] != 3'd0 && + _theResult_____1__h75739 == 4'd9 && + cpReq[37:36] == 2'd1 && + cpReq[19:9] == 11'd0 && + wci_9_wReset_n && + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4476 && + !dispatched ; + assign NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4493 = + cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && + cpReq[64:62] != 3'd0 && + _theResult_____1__h75739 == 4'd9 && + cpReq[37:36] == 2'd1 && + cpReq[19:9] == 11'd0 && + !wci_9_wReset_n && + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4486 && + !dispatched ; + assign NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4535 = + cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && + cpReq[64:62] != 3'd0 && + _theResult_____1__h75739 == 4'd10 && + cpReq[37:36] == 2'd2 && + wci_10_wReset_n && + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4528 && + !dispatched ; + assign NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4547 = + cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && + cpReq[64:62] != 3'd0 && + _theResult_____1__h75739 == 4'd10 && + cpReq[37:36] == 2'd2 && + !wci_10_wReset_n && + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4540 && + !dispatched ; + assign NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4558 = + cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && + cpReq[64:62] != 3'd0 && + _theResult_____1__h75739 == 4'd10 && + cpReq[37:36] == 2'd1 && + cpReq[19:9] == 11'd0 && + wci_10_wReset_n && + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4551 && + !dispatched ; + assign NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4568 = + cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && + cpReq[64:62] != 3'd0 && + _theResult_____1__h75739 == 4'd10 && + cpReq[37:36] == 2'd1 && + cpReq[19:9] == 11'd0 && + !wci_10_wReset_n && + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4561 && + !dispatched ; + assign NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4610 = + cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && + cpReq[64:62] != 3'd0 && + _theResult_____1__h75739 == 4'd11 && + cpReq[37:36] == 2'd2 && + wci_11_wReset_n && + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4603 && + !dispatched ; + assign NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4622 = + cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && + cpReq[64:62] != 3'd0 && + _theResult_____1__h75739 == 4'd11 && + cpReq[37:36] == 2'd2 && + !wci_11_wReset_n && + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4615 && + !dispatched ; + assign NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4633 = + cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && + cpReq[64:62] != 3'd0 && + _theResult_____1__h75739 == 4'd11 && + cpReq[37:36] == 2'd1 && + cpReq[19:9] == 11'd0 && + wci_11_wReset_n && + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4626 && + !dispatched ; + assign NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4643 = + cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && + cpReq[64:62] != 3'd0 && + _theResult_____1__h75739 == 4'd11 && + cpReq[37:36] == 2'd1 && + cpReq[19:9] == 11'd0 && + !wci_11_wReset_n && + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4636 && + !dispatched ; + assign NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4685 = + cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && + cpReq[64:62] != 3'd0 && + _theResult_____1__h75739 == 4'd12 && + cpReq[37:36] == 2'd2 && + wci_12_wReset_n && + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4678 && + !dispatched ; + assign NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4697 = + cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && + cpReq[64:62] != 3'd0 && + _theResult_____1__h75739 == 4'd12 && + cpReq[37:36] == 2'd2 && + !wci_12_wReset_n && + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4690 && + !dispatched ; + assign NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4708 = + cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && + cpReq[64:62] != 3'd0 && + _theResult_____1__h75739 == 4'd12 && + cpReq[37:36] == 2'd1 && + cpReq[19:9] == 11'd0 && + wci_12_wReset_n && + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4701 && + !dispatched ; + assign NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4718 = + cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && + cpReq[64:62] != 3'd0 && + _theResult_____1__h75739 == 4'd12 && + cpReq[37:36] == 2'd1 && + cpReq[19:9] == 11'd0 && + !wci_12_wReset_n && + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4711 && !dispatched ; - assign cpReq_337_BITS_9_TO_6_770_EQ_0xC_809_AND_NOT_w_ETC___d2993 = - cpReq[9:6] == 4'hC && !wci_busy_1 && wci_respF_1$FULL_N && + assign NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4760 = + cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && + cpReq[64:62] != 3'd0 && + _theResult_____1__h75739 == 4'd13 && + cpReq[37:36] == 2'd2 && + wci_13_wReset_n && + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4753 && !dispatched ; - assign cpReq_337_BITS_9_TO_6_770_EQ_0xC_809_AND_NOT_w_ETC___d3056 = - cpReq[9:6] == 4'hC && !wci_busy_2 && wci_respF_2$FULL_N && + assign NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4772 = + cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && + cpReq[64:62] != 3'd0 && + _theResult_____1__h75739 == 4'd13 && + cpReq[37:36] == 2'd2 && + !wci_13_wReset_n && + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4765 && !dispatched ; - assign cpReq_337_BITS_9_TO_6_770_EQ_0xC_809_AND_NOT_w_ETC___d3119 = - cpReq[9:6] == 4'hC && !wci_busy_3 && wci_respF_3$FULL_N && + assign NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4783 = + cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && + cpReq[64:62] != 3'd0 && + _theResult_____1__h75739 == 4'd13 && + cpReq[37:36] == 2'd1 && + cpReq[19:9] == 11'd0 && + wci_13_wReset_n && + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4776 && !dispatched ; - assign cpReq_337_BITS_9_TO_6_770_EQ_0xC_809_AND_NOT_w_ETC___d3182 = - cpReq[9:6] == 4'hC && !wci_busy_4 && wci_respF_4$FULL_N && + assign NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4793 = + cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && + cpReq[64:62] != 3'd0 && + _theResult_____1__h75739 == 4'd13 && + cpReq[37:36] == 2'd1 && + cpReq[19:9] == 11'd0 && + !wci_13_wReset_n && + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4786 && !dispatched ; - assign cpReq_337_BITS_9_TO_6_770_EQ_0xC_809_AND_NOT_w_ETC___d3245 = - cpReq[9:6] == 4'hC && !wci_busy_5 && wci_respF_5$FULL_N && + assign NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4835 = + cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && + cpReq[64:62] != 3'd0 && + _theResult_____1__h75739 == 4'd14 && + cpReq[37:36] == 2'd2 && + wci_14_wReset_n && + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4828 && !dispatched ; - assign cpReq_337_BITS_9_TO_6_770_EQ_0xC_809_AND_NOT_w_ETC___d3308 = - cpReq[9:6] == 4'hC && !wci_busy_6 && wci_respF_6$FULL_N && + assign NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4847 = + cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && + cpReq[64:62] != 3'd0 && + _theResult_____1__h75739 == 4'd14 && + cpReq[37:36] == 2'd2 && + !wci_14_wReset_n && + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4840 && !dispatched ; - assign cpReq_337_BITS_9_TO_6_770_EQ_0xC_809_AND_NOT_w_ETC___d3371 = - cpReq[9:6] == 4'hC && !wci_busy_7 && wci_respF_7$FULL_N && + assign NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4858 = + cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && + cpReq[64:62] != 3'd0 && + _theResult_____1__h75739 == 4'd14 && + cpReq[37:36] == 2'd1 && + cpReq[19:9] == 11'd0 && + wci_14_wReset_n && + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4851 && !dispatched ; - assign cpReq_337_BITS_9_TO_6_770_EQ_0xC_809_AND_NOT_w_ETC___d3434 = - cpReq[9:6] == 4'hC && !wci_busy_8 && wci_respF_8$FULL_N && + assign NOT_cpReq_363_BITS_64_TO_62_364_EQ_2_435_646_A_ETC___d4868 = + cpReq[64:62] != 3'd2 && cpReq[64:62] != 3'd3 && + cpReq[64:62] != 3'd0 && + _theResult_____1__h75739 == 4'd14 && + cpReq[37:36] == 2'd1 && + cpReq[19:9] == 11'd0 && + !wci_14_wReset_n && + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4861 && !dispatched ; - assign cpReq_337_BITS_9_TO_6_770_EQ_0xC_809_AND_NOT_w_ETC___d3497 = - cpReq[9:6] == 4'hC && !wci_busy_9 && wci_respF_9$FULL_N && + assign NOT_cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_035_A_ETC___d3839 = + cpReq[9:6] != 4'h9 && cpReq[9:6] != 4'hA && cpReq[9:6] != 4'hC && + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793 && !dispatched ; - assign cpReq_337_BITS_9_TO_6_770_EQ_0xC_809_AND_NOT_w_ETC___d3560 = - cpReq[9:6] == 4'hC && !wci_busy_10 && wci_respF_10$FULL_N && + assign NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 = + !wci_0_busy && (wci_0_wReset_n || wci_0_respF$FULL_N) && + (!wci_0_wReset_n || !wci_0_reqF_cntr_r) ; + assign NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 = + !wci_10_busy && (wci_10_wReset_n || wci_10_respF$FULL_N) && + (!wci_10_wReset_n || !wci_10_reqF_cntr_r) ; + assign NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 = + !wci_11_busy && (wci_11_wReset_n || wci_11_respF$FULL_N) && + (!wci_11_wReset_n || !wci_11_reqF_cntr_r) ; + assign NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 = + !wci_12_busy && (wci_12_wReset_n || wci_12_respF$FULL_N) && + (!wci_12_wReset_n || !wci_12_reqF_cntr_r) ; + assign NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 = + !wci_13_busy && (wci_13_wReset_n || wci_13_respF$FULL_N) && + (!wci_13_wReset_n || !wci_13_reqF_cntr_r) ; + assign NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942 = + !wci_14_busy && (wci_14_wReset_n || wci_14_respF$FULL_N) && + (!wci_14_wReset_n || !wci_14_reqF_cntr_r) ; + assign NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 = + !wci_1_busy && (wci_1_wReset_n || wci_1_respF$FULL_N) && + (!wci_1_wReset_n || !wci_1_reqF_cntr_r) ; + assign NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 = + !wci_2_busy && (wci_2_wReset_n || wci_2_respF$FULL_N) && + (!wci_2_wReset_n || !wci_2_reqF_cntr_r) ; + assign NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 = + !wci_3_busy && (wci_3_wReset_n || wci_3_respF$FULL_N) && + (!wci_3_wReset_n || !wci_3_reqF_cntr_r) ; + assign NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 = + !wci_4_busy && (wci_4_wReset_n || wci_4_respF$FULL_N) && + (!wci_4_wReset_n || !wci_4_reqF_cntr_r) ; + assign NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 = + !wci_5_busy && (wci_5_wReset_n || wci_5_respF$FULL_N) && + (!wci_5_wReset_n || !wci_5_reqF_cntr_r) ; + assign NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 = + !wci_6_busy && (wci_6_wReset_n || wci_6_respF$FULL_N) && + (!wci_6_wReset_n || !wci_6_reqF_cntr_r) ; + assign NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 = + !wci_7_busy && (wci_7_wReset_n || wci_7_respF$FULL_N) && + (!wci_7_wReset_n || !wci_7_reqF_cntr_r) ; + assign NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 = + !wci_8_busy && (wci_8_wReset_n || wci_8_respF$FULL_N) && + (!wci_8_wReset_n || !wci_8_reqF_cntr_r) ; + assign NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 = + !wci_9_busy && (wci_9_wReset_n || wci_9_respF$FULL_N) && + (!wci_9_wReset_n || !wci_9_reqF_cntr_r) ; + assign _281474976710656_MINUS_timeServ_delSecond_BITS__ETC__q2 = + _281474976710656_MINUS_timeServ_delSecond__q1[49:28] ; + assign _281474976710656_MINUS_timeServ_delSecond__q1 = + 50'h1000000000000 - timeServ_delSecond ; + assign _theResult_____1__h75724 = + (cpReq[61:60] == 2'd2) ? wn___1__h76499 : wn__h75723 ; + assign _theResult_____1__h75739 = + (cpReq[37:36] == 2'd2) ? wn___1__h76499 : wn__h75723 ; + assign bAddr__h110990 = { cpReqF$D_OUT[57:36], 2'b0 } ; + assign bAddr__h111449 = { cpReqF$D_OUT[25:4], 2'b0 } ; + assign cpReq_363_BITS_11_TO_4_366_EQ_0x30_595_OR_cpRe_ETC___d2632 = + (cpReq[11:4] == 8'h30 || cpReq[11:4] == 8'h34 || + cpReq[11:4] == 8'h38 || + cpReq[11:4] == 8'h3C || + cpReq[11:4] == 8'h40 || + cpReq[11:4] == 8'h44 || + cpReq[11:4] == 8'h48) && + adminResp2F$FULL_N && !dispatched ; - assign cpReq_337_BITS_9_TO_6_770_EQ_0xC_809_AND_NOT_w_ETC___d3623 = - cpReq[9:6] == 4'hC && !wci_busy_11 && wci_respF_11$FULL_N && + assign cpReq_363_BITS_11_TO_4_366_ULT_0x30___d2438 = cpReq[11:4] < 8'h30 ; + assign cpReq_363_BITS_11_TO_4_366_ULT_0xC0___d2594 = cpReq[11:4] < 8'hC0 ; + assign cpReq_363_BITS_27_TO_4_436_ULT_0x1000___d2836 = + cpReq[27:4] < 24'h001000 ; + assign cpReq_363_BITS_27_TO_4_436_ULT_0x100___d2437 = + cpReq[27:4] < 24'h000100 ; + assign cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_AND_NOT_c_ETC___d3016 = + cpReq[9:6] == 4'h9 && !cpReq[37] && cpReq[36] && + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d2986 && !dispatched ; - assign cpReq_337_BITS_9_TO_6_770_EQ_0xC_809_AND_NOT_w_ETC___d3686 = - cpReq[9:6] == 4'hC && !wci_busy_12 && wci_respF_12$FULL_N && + assign cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_AND_NOT_c_ETC___d3022 = + cpReq[9:6] == 4'h9 && !cpReq[37] && !cpReq[36] && + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d2986 && !dispatched ; - assign cpReq_337_BITS_9_TO_6_770_EQ_0xC_809_AND_NOT_w_ETC___d3749 = - cpReq[9:6] == 4'hC && !wci_busy_13 && wci_respF_13$FULL_N && + assign cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_AND_cpReq_ETC___d3001 = + cpReq[9:6] == 4'h9 && cpReq[37] && cpReq[36] && + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d2986 && !dispatched ; - assign cpReq_337_BITS_9_TO_6_770_EQ_0xC_809_AND_NOT_w_ETC___d3812 = - cpReq[9:6] == 4'hC && !wci_busy_14 && wci_respF_14$FULL_N && + assign cpReq_363_BITS_9_TO_6_831_EQ_0x9_996_AND_cpReq_ETC___d3009 = + cpReq[9:6] == 4'h9 && cpReq[37] && !cpReq[36] && + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d2986 && !dispatched ; - assign cpReq_337_BIT_36_898_AND_NOT_wci_busy_10_610_5_ETC___d3534 = - cpReq[36] && !wci_busy_10 && wci_respF_10$FULL_N && !dispatched ; - assign cpReq_337_BIT_36_898_AND_NOT_wci_busy_10_860_A_ETC___d2899 = - cpReq[36] && !wci_busy && wci_respF$FULL_N && !dispatched ; - assign cpReq_337_BIT_36_898_AND_NOT_wci_busy_11_750_5_ETC___d3597 = - cpReq[36] && !wci_busy_11 && wci_respF_11$FULL_N && !dispatched ; - assign cpReq_337_BIT_36_898_AND_NOT_wci_busy_12_890_6_ETC___d3660 = - cpReq[36] && !wci_busy_12 && wci_respF_12$FULL_N && !dispatched ; - assign cpReq_337_BIT_36_898_AND_NOT_wci_busy_13_030_6_ETC___d3723 = - cpReq[36] && !wci_busy_13 && wci_respF_13$FULL_N && !dispatched ; - assign cpReq_337_BIT_36_898_AND_NOT_wci_busy_14_170_7_ETC___d3786 = - cpReq[36] && !wci_busy_14 && wci_respF_14$FULL_N && !dispatched ; - assign cpReq_337_BIT_36_898_AND_NOT_wci_busy_1_50_943_ETC___d2967 = - cpReq[36] && !wci_busy_1 && wci_respF_1$FULL_N && !dispatched ; - assign cpReq_337_BIT_36_898_AND_NOT_wci_busy_2_90_006_ETC___d3030 = - cpReq[36] && !wci_busy_2 && wci_respF_2$FULL_N && !dispatched ; - assign cpReq_337_BIT_36_898_AND_NOT_wci_busy_3_30_069_ETC___d3093 = - cpReq[36] && !wci_busy_3 && wci_respF_3$FULL_N && !dispatched ; - assign cpReq_337_BIT_36_898_AND_NOT_wci_busy_4_70_132_ETC___d3156 = - cpReq[36] && !wci_busy_4 && wci_respF_4$FULL_N && !dispatched ; - assign cpReq_337_BIT_36_898_AND_NOT_wci_busy_5_10_195_ETC___d3219 = - cpReq[36] && !wci_busy_5 && wci_respF_5$FULL_N && !dispatched ; - assign cpReq_337_BIT_36_898_AND_NOT_wci_busy_6_050_25_ETC___d3282 = - cpReq[36] && !wci_busy_6 && wci_respF_6$FULL_N && !dispatched ; - assign cpReq_337_BIT_36_898_AND_NOT_wci_busy_7_190_32_ETC___d3345 = - cpReq[36] && !wci_busy_7 && wci_respF_7$FULL_N && !dispatched ; - assign cpReq_337_BIT_36_898_AND_NOT_wci_busy_8_330_38_ETC___d3408 = - cpReq[36] && !wci_busy_8 && wci_respF_8$FULL_N && !dispatched ; - assign cpReq_337_BIT_36_898_AND_NOT_wci_busy_9_470_44_ETC___d3471 = - cpReq[36] && !wci_busy_9 && wci_respF_9$FULL_N && !dispatched ; - assign cpStatus__h74993 = { 28'd0, rogueTLP } ; - assign crr_data__h75663 = + assign cpStatus__h74863 = { 28'd0, rogueTLP } ; + assign crr_data__h75533 = adminRespF$D_OUT[32] ? adminRespF$D_OUT[31:0] : 32'hDEADC0DE ; assign rom_serverAdapter_cnt_29_PLUS_IF_rom_serverAda_ETC___d135 = rom_serverAdapter_cnt + @@ -17198,568 +17329,7143 @@ module mkOCCP(pciDevice, (rom_serverAdapter_outData_deqCalled$whas ? 3'd7 : 3'd0) ; assign timeServ_ppsExtSync_d2_2_AND_NOT_timeServ_ppsE_ETC___d61 = timeServ_ppsExtSync_d2 && !timeServ_ppsExtSyncD && - (timeServ_refFromRise_3_ULE_199800000___d6126 || - !timeServ_refFromRise_3_ULT_200200000___d5828) || + (timeServ_refFromRise_3_ULE_199800000___d48 || + !timeServ_refFromRise_3_ULT_200200000___d50) || timeServ_refFromRise > 28'd200200000 ; assign timeServ_ppsExtSync_d2_2_AND_NOT_timeServ_ppsE_ETC___d70 = timeServ_ppsExtSync_d2 && !timeServ_ppsExtSyncD && - !timeServ_refFromRise_3_ULE_199800000___d6126 && - timeServ_refFromRise_3_ULT_200200000___d5828 && + !timeServ_refFromRise_3_ULE_199800000___d48 && + timeServ_refFromRise_3_ULT_200200000___d50 && timeServ_ppsOK && !timeServ_disableServo$dD_OUT ; - assign timeServ_refFromRise_3_ULE_199800000___d6126 = + assign timeServ_refFromRise_3_ULE_199800000___d48 = timeServ_refFromRise <= 28'd199800000 ; - assign timeServ_refFromRise_3_ULT_200200000___d5828 = + assign timeServ_refFromRise_3_ULT_200200000___d50 = timeServ_refFromRise < 28'd200200000 ; - assign toCount__h10825 = 32'd1 << wci_wTimeout ; - assign toCount__h15271 = 32'd1 << wci_wTimeout_1 ; - assign toCount__h19711 = 32'd1 << wci_wTimeout_2 ; - assign toCount__h24151 = 32'd1 << wci_wTimeout_3 ; - assign toCount__h28591 = 32'd1 << wci_wTimeout_4 ; - assign toCount__h33031 = 32'd1 << wci_wTimeout_5 ; - assign toCount__h37471 = 32'd1 << wci_wTimeout_6 ; - assign toCount__h41911 = 32'd1 << wci_wTimeout_7 ; - assign toCount__h46351 = 32'd1 << wci_wTimeout_8 ; - assign toCount__h50791 = 32'd1 << wci_wTimeout_9 ; - assign toCount__h55231 = 32'd1 << wci_wTimeout_10 ; - assign toCount__h59671 = 32'd1 << wci_wTimeout_11 ; - assign toCount__h64111 = 32'd1 << wci_wTimeout_12 ; - assign toCount__h68551 = 32'd1 << wci_wTimeout_13 ; - assign toCount__h72991 = 32'd1 << wci_wTimeout_14 ; - assign wciAddr__h77388 = { wci_pageWindow, cpReq[23:4] } ; - assign wciAddr__h77456 = { wci_pageWindow_1, cpReq[23:4] } ; - assign wciAddr__h77522 = { wci_pageWindow_2, cpReq[23:4] } ; - assign wciAddr__h77588 = { wci_pageWindow_3, cpReq[23:4] } ; - assign wciAddr__h77654 = { wci_pageWindow_4, cpReq[23:4] } ; - assign wciAddr__h77720 = { wci_pageWindow_5, cpReq[23:4] } ; - assign wciAddr__h77786 = { wci_pageWindow_6, cpReq[23:4] } ; - assign wciAddr__h77852 = { wci_pageWindow_7, cpReq[23:4] } ; - assign wciAddr__h77918 = { wci_pageWindow_8, cpReq[23:4] } ; - assign wciAddr__h77984 = { wci_pageWindow_9, cpReq[23:4] } ; - assign wciAddr__h78050 = { wci_pageWindow_10, cpReq[23:4] } ; - assign wciAddr__h78116 = { wci_pageWindow_11, cpReq[23:4] } ; - assign wciAddr__h78182 = { wci_pageWindow_12, cpReq[23:4] } ; - assign wciAddr__h78248 = { wci_pageWindow_13, cpReq[23:4] } ; - assign wciAddr__h78314 = { wci_pageWindow_14, cpReq[23:4] } ; - assign wci_respTimr_02_ULT_1_SL_wci_wTimeout_03_04___d5829 = - wci_respTimr < toCount__h10825 ; - assign wci_respTimr_10_602_ULT_1_SL_wci_wTimeout_10_6_ETC___d5839 = - wci_respTimr_10 < toCount__h55231 ; - assign wci_respTimr_11_742_ULT_1_SL_wci_wTimeout_11_7_ETC___d5840 = - wci_respTimr_11 < toCount__h59671 ; - assign wci_respTimr_12_882_ULT_1_SL_wci_wTimeout_12_8_ETC___d5841 = - wci_respTimr_12 < toCount__h64111 ; - assign wci_respTimr_13_022_ULT_1_SL_wci_wTimeout_13_0_ETC___d5842 = - wci_respTimr_13 < toCount__h68551 ; - assign wci_respTimr_14_162_ULT_1_SL_wci_wTimeout_14_1_ETC___d5843 = - wci_respTimr_14 < toCount__h72991 ; - assign wci_respTimr_1_42_ULT_1_SL_wci_wTimeout_1_43_44___d5830 = - wci_respTimr_1 < toCount__h15271 ; - assign wci_respTimr_2_82_ULT_1_SL_wci_wTimeout_2_83_84___d5831 = - wci_respTimr_2 < toCount__h19711 ; - assign wci_respTimr_3_22_ULT_1_SL_wci_wTimeout_3_23_24___d5832 = - wci_respTimr_3 < toCount__h24151 ; - assign wci_respTimr_4_62_ULT_1_SL_wci_wTimeout_4_63_64___d5833 = - wci_respTimr_4 < toCount__h28591 ; - assign wci_respTimr_5_02_ULT_1_SL_wci_wTimeout_5_03_04___d5834 = - wci_respTimr_5 < toCount__h33031 ; - assign wci_respTimr_6_042_ULT_1_SL_wci_wTimeout_6_043_ETC___d5835 = - wci_respTimr_6 < toCount__h37471 ; - assign wci_respTimr_7_182_ULT_1_SL_wci_wTimeout_7_183_ETC___d5836 = - wci_respTimr_7 < toCount__h41911 ; - assign wci_respTimr_8_322_ULT_1_SL_wci_wTimeout_8_323_ETC___d5837 = - wci_respTimr_8 < toCount__h46351 ; - assign wci_respTimr_9_462_ULT_1_SL_wci_wTimeout_9_463_ETC___d5838 = - wci_respTimr_9 < toCount__h50791 ; - assign wci_wReset_n_10_590_AND_NOT_wci_busy_10_610_51_ETC___d3513 = - wci_wReset_n_10 && !wci_busy_10 && !wci_reqF_10_c_r && - !dispatched ; - assign wci_wReset_n_11_730_AND_NOT_wci_busy_11_750_57_ETC___d3576 = - wci_wReset_n_11 && !wci_busy_11 && !wci_reqF_11_c_r && - !dispatched ; - assign wci_wReset_n_12_870_AND_NOT_wci_busy_12_890_63_ETC___d3639 = - wci_wReset_n_12 && !wci_busy_12 && !wci_reqF_12_c_r && - !dispatched ; - assign wci_wReset_n_13_010_AND_NOT_wci_busy_13_030_69_ETC___d3702 = - wci_wReset_n_13 && !wci_busy_13 && !wci_reqF_13_c_r && - !dispatched ; - assign wci_wReset_n_14_150_AND_NOT_wci_busy_14_170_76_ETC___d3765 = - wci_wReset_n_14 && !wci_busy_14 && !wci_reqF_14_c_r && - !dispatched ; - assign wci_wReset_n_1_30_AND_NOT_wci_busy_1_50_943_AN_ETC___d2946 = - wci_wReset_n_1 && !wci_busy_1 && !wci_reqF_1_c_r && !dispatched ; - assign wci_wReset_n_2_70_AND_NOT_wci_busy_2_90_006_AN_ETC___d3009 = - wci_wReset_n_2 && !wci_busy_2 && !wci_reqF_2_c_r && !dispatched ; - assign wci_wReset_n_3_10_AND_NOT_wci_busy_3_30_069_AN_ETC___d3072 = - wci_wReset_n_3 && !wci_busy_3 && !wci_reqF_3_c_r && !dispatched ; - assign wci_wReset_n_4_50_AND_NOT_wci_busy_4_70_132_AN_ETC___d3135 = - wci_wReset_n_4 && !wci_busy_4 && !wci_reqF_4_c_r && !dispatched ; - assign wci_wReset_n_5_90_AND_NOT_wci_busy_5_10_195_AN_ETC___d3198 = - wci_wReset_n_5 && !wci_busy_5 && !wci_reqF_5_c_r && !dispatched ; - assign wci_wReset_n_6_030_AND_NOT_wci_busy_6_050_258__ETC___d3261 = - wci_wReset_n_6 && !wci_busy_6 && !wci_reqF_6_c_r && !dispatched ; - assign wci_wReset_n_7_170_AND_NOT_wci_busy_7_190_321__ETC___d3324 = - wci_wReset_n_7 && !wci_busy_7 && !wci_reqF_7_c_r && !dispatched ; - assign wci_wReset_n_8_310_AND_NOT_wci_busy_8_330_384__ETC___d3387 = - wci_wReset_n_8 && !wci_busy_8 && !wci_reqF_8_c_r && !dispatched ; - assign wci_wReset_n_90_AND_NOT_wci_busy_10_860_AND_NO_ETC___d2863 = - wci_wReset_n && !wci_busy && !wci_reqF_c_r && !dispatched ; - assign wci_wReset_n_9_450_AND_NOT_wci_busy_9_470_447__ETC___d3450 = - wci_wReset_n_9 && !wci_busy_9 && !wci_reqF_9_c_r && !dispatched ; - assign wci_wciResponse_10_wget__597_BITS_33_TO_32_598_ETC___d1626 = - wci_wciResponse_10$wget[33:32] == 2'd0 && - !wci_respTimr_10_602_ULT_1_SL_wci_wTimeout_10_6_ETC___d5839 && - (wci_reqPend_10 == 2'd1 || wci_reqPend_10 == 2'd2 || - wci_reqPend_10 == 2'd3) ; - assign wci_wciResponse_11_wget__737_BITS_33_TO_32_738_ETC___d1766 = - wci_wciResponse_11$wget[33:32] == 2'd0 && - !wci_respTimr_11_742_ULT_1_SL_wci_wTimeout_11_7_ETC___d5840 && - (wci_reqPend_11 == 2'd1 || wci_reqPend_11 == 2'd2 || - wci_reqPend_11 == 2'd3) ; - assign wci_wciResponse_12_wget__877_BITS_33_TO_32_878_ETC___d1906 = - wci_wciResponse_12$wget[33:32] == 2'd0 && - !wci_respTimr_12_882_ULT_1_SL_wci_wTimeout_12_8_ETC___d5841 && - (wci_reqPend_12 == 2'd1 || wci_reqPend_12 == 2'd2 || - wci_reqPend_12 == 2'd3) ; - assign wci_wciResponse_13_wget__017_BITS_33_TO_32_018_ETC___d2046 = - wci_wciResponse_13$wget[33:32] == 2'd0 && - !wci_respTimr_13_022_ULT_1_SL_wci_wTimeout_13_0_ETC___d5842 && - (wci_reqPend_13 == 2'd1 || wci_reqPend_13 == 2'd2 || - wci_reqPend_13 == 2'd3) ; - assign wci_wciResponse_14_wget__157_BITS_33_TO_32_158_ETC___d2186 = - wci_wciResponse_14$wget[33:32] == 2'd0 && - !wci_respTimr_14_162_ULT_1_SL_wci_wTimeout_14_1_ETC___d5843 && - (wci_reqPend_14 == 2'd1 || wci_reqPend_14 == 2'd2 || - wci_reqPend_14 == 2'd3) ; - assign wci_wciResponse_1_wget__37_BITS_33_TO_32_38_EQ_ETC___d366 = - wci_wciResponse_1$wget[33:32] == 2'd0 && - !wci_respTimr_1_42_ULT_1_SL_wci_wTimeout_1_43_44___d5830 && - (wci_reqPend_1 == 2'd1 || wci_reqPend_1 == 2'd2 || - wci_reqPend_1 == 2'd3) ; - assign wci_wciResponse_2_wget__77_BITS_33_TO_32_78_EQ_ETC___d506 = - wci_wciResponse_2$wget[33:32] == 2'd0 && - !wci_respTimr_2_82_ULT_1_SL_wci_wTimeout_2_83_84___d5831 && - (wci_reqPend_2 == 2'd1 || wci_reqPend_2 == 2'd2 || - wci_reqPend_2 == 2'd3) ; - assign wci_wciResponse_3_wget__17_BITS_33_TO_32_18_EQ_ETC___d646 = - wci_wciResponse_3$wget[33:32] == 2'd0 && - !wci_respTimr_3_22_ULT_1_SL_wci_wTimeout_3_23_24___d5832 && - (wci_reqPend_3 == 2'd1 || wci_reqPend_3 == 2'd2 || - wci_reqPend_3 == 2'd3) ; - assign wci_wciResponse_4_wget__57_BITS_33_TO_32_58_EQ_ETC___d786 = - wci_wciResponse_4$wget[33:32] == 2'd0 && - !wci_respTimr_4_62_ULT_1_SL_wci_wTimeout_4_63_64___d5833 && - (wci_reqPend_4 == 2'd1 || wci_reqPend_4 == 2'd2 || - wci_reqPend_4 == 2'd3) ; - assign wci_wciResponse_5_wget__97_BITS_33_TO_32_98_EQ_ETC___d926 = - wci_wciResponse_5$wget[33:32] == 2'd0 && - !wci_respTimr_5_02_ULT_1_SL_wci_wTimeout_5_03_04___d5834 && - (wci_reqPend_5 == 2'd1 || wci_reqPend_5 == 2'd2 || - wci_reqPend_5 == 2'd3) ; - assign wci_wciResponse_6_wget__037_BITS_33_TO_32_038__ETC___d1066 = - wci_wciResponse_6$wget[33:32] == 2'd0 && - !wci_respTimr_6_042_ULT_1_SL_wci_wTimeout_6_043_ETC___d5835 && - (wci_reqPend_6 == 2'd1 || wci_reqPend_6 == 2'd2 || - wci_reqPend_6 == 2'd3) ; - assign wci_wciResponse_7_wget__177_BITS_33_TO_32_178__ETC___d1206 = - wci_wciResponse_7$wget[33:32] == 2'd0 && - !wci_respTimr_7_182_ULT_1_SL_wci_wTimeout_7_183_ETC___d5836 && - (wci_reqPend_7 == 2'd1 || wci_reqPend_7 == 2'd2 || - wci_reqPend_7 == 2'd3) ; - assign wci_wciResponse_8_wget__317_BITS_33_TO_32_318__ETC___d1346 = - wci_wciResponse_8$wget[33:32] == 2'd0 && - !wci_respTimr_8_322_ULT_1_SL_wci_wTimeout_8_323_ETC___d5837 && - (wci_reqPend_8 == 2'd1 || wci_reqPend_8 == 2'd2 || - wci_reqPend_8 == 2'd3) ; - assign wci_wciResponse_9_wget__457_BITS_33_TO_32_458__ETC___d1486 = - wci_wciResponse_9$wget[33:32] == 2'd0 && - !wci_respTimr_9_462_ULT_1_SL_wci_wTimeout_9_463_ETC___d5838 && - (wci_reqPend_9 == 2'd1 || wci_reqPend_9 == 2'd2 || - wci_reqPend_9 == 2'd3) ; - assign wci_wciResponse_wget__97_BITS_33_TO_32_98_EQ_0_ETC___d226 = - wci_wciResponse$wget[33:32] == 2'd0 && - !wci_respTimr_02_ULT_1_SL_wci_wTimeout_03_04___d5829 && - (wci_reqPend == 2'd1 || wci_reqPend == 2'd2 || - wci_reqPend == 2'd3) ; - assign wn___1__h76646 = cpReq[27:24] - 4'd1 ; - assign wn__h75856 = cpReq[23:20] - 4'd1 ; - assign x__h105402 = - { wci_slvPresent_14, - wci_slvPresent_13, - wci_slvPresent_12, - wci_slvPresent_11, - wci_slvPresent_10, - wci_slvPresent_9, - wci_slvPresent_8, - wci_slvPresent_7, - wci_slvPresent_6, - wci_slvPresent_5, - wci_slvPresent_4, - wci_slvPresent_3, - wci_slvPresent_2, - wci_slvPresent_1, - wci_slvPresent } ; - assign x__h105951 = - { wci_wStatus_14[15:0] != 16'd0, - wci_wStatus_13[15:0] != 16'd0, - wci_wStatus_12[15:0] != 16'd0, - wci_wStatus_11[15:0] != 16'd0, - wci_wStatus_10[15:0] != 16'd0, - wci_wStatus_9[15:0] != 16'd0, - wci_wStatus_8[15:0] != 16'd0, - wci_wStatus_7[15:0] != 16'd0, - wci_wStatus_6[15:0] != 16'd0, - wci_wStatus_5[15:0] != 16'd0, - wci_wStatus_4[15:0] != 16'd0, - wci_wStatus_3[15:0] != 16'd0, - wci_wStatus_2[15:0] != 16'd0, - wci_wStatus_1[15:0] != 16'd0, - wci_wStatus[15:0] != 16'd0 } ; - assign x__h10985 = wci_respTimr + 32'd1 ; - assign x__h15428 = wci_respTimr_1 + 32'd1 ; - assign x__h19868 = wci_respTimr_2 + 32'd1 ; - assign x__h24308 = wci_respTimr_3 + 32'd1 ; - assign x__h28748 = wci_respTimr_4 + 32'd1 ; - assign x__h33188 = wci_respTimr_5 + 32'd1 ; - assign x__h3700 = { 2'b0, x_f__h4848 } ; - assign x__h37628 = wci_respTimr_6 + 32'd1 ; - assign x__h42068 = wci_respTimr_7 + 32'd1 ; - assign x__h4421 = + assign toCount__h11692 = 32'd1 << wci_0_wTimeout ; + assign toCount__h16067 = 32'd1 << wci_1_wTimeout ; + assign toCount__h20436 = 32'd1 << wci_2_wTimeout ; + assign toCount__h24805 = 32'd1 << wci_3_wTimeout ; + assign toCount__h29174 = 32'd1 << wci_4_wTimeout ; + assign toCount__h33543 = 32'd1 << wci_5_wTimeout ; + assign toCount__h37912 = 32'd1 << wci_6_wTimeout ; + assign toCount__h42281 = 32'd1 << wci_7_wTimeout ; + assign toCount__h46650 = 32'd1 << wci_8_wTimeout ; + assign toCount__h51019 = 32'd1 << wci_9_wTimeout ; + assign toCount__h55388 = 32'd1 << wci_10_wTimeout ; + assign toCount__h59757 = 32'd1 << wci_11_wTimeout ; + assign toCount__h64126 = 32'd1 << wci_12_wTimeout ; + assign toCount__h68495 = 32'd1 << wci_13_wTimeout ; + assign toCount__h72864 = 32'd1 << wci_14_wTimeout ; + assign wciAddr__h77037 = { wci_0_pageWindow, cpReq[23:4] } ; + assign wciAddr__h77105 = { wci_1_pageWindow, cpReq[23:4] } ; + assign wciAddr__h77173 = { wci_2_pageWindow, cpReq[23:4] } ; + assign wciAddr__h77241 = { wci_3_pageWindow, cpReq[23:4] } ; + assign wciAddr__h77309 = { wci_4_pageWindow, cpReq[23:4] } ; + assign wciAddr__h77377 = { wci_5_pageWindow, cpReq[23:4] } ; + assign wciAddr__h77445 = { wci_6_pageWindow, cpReq[23:4] } ; + assign wciAddr__h77513 = { wci_7_pageWindow, cpReq[23:4] } ; + assign wciAddr__h77581 = { wci_8_pageWindow, cpReq[23:4] } ; + assign wciAddr__h77649 = { wci_9_pageWindow, cpReq[23:4] } ; + assign wciAddr__h77717 = { wci_10_pageWindow, cpReq[23:4] } ; + assign wciAddr__h77785 = { wci_11_pageWindow, cpReq[23:4] } ; + assign wciAddr__h77853 = { wci_12_pageWindow, cpReq[23:4] } ; + assign wciAddr__h77921 = { wci_13_pageWindow, cpReq[23:4] } ; + assign wciAddr__h77989 = { wci_14_pageWindow, cpReq[23:4] } ; + assign wci_0_respTimr_28_ULT_1_SL_wci_0_wTimeout_29_30___d231 = + wci_0_respTimr < toCount__h11692 ; + assign wci_0_wciResponse_wget__23_BITS_33_TO_32_24_EQ_ETC___d252 = + wci_0_wciResponse$wget[33:32] == 2'd0 && + !wci_0_respTimr_28_ULT_1_SL_wci_0_wTimeout_29_30___d231 && + (wci_0_reqPend == 2'd1 || wci_0_reqPend == 2'd2 || + wci_0_reqPend == 2'd3) ; + assign wci_10_respTimr_628_ULT_1_SL_wci_10_wTimeout_6_ETC___d1631 = + wci_10_respTimr < toCount__h55388 ; + assign wci_10_wciResponse_wget__623_BITS_33_TO_32_624_ETC___d1652 = + wci_10_wciResponse$wget[33:32] == 2'd0 && + !wci_10_respTimr_628_ULT_1_SL_wci_10_wTimeout_6_ETC___d1631 && + (wci_10_reqPend == 2'd1 || wci_10_reqPend == 2'd2 || + wci_10_reqPend == 2'd3) ; + assign wci_11_respTimr_768_ULT_1_SL_wci_11_wTimeout_7_ETC___d1771 = + wci_11_respTimr < toCount__h59757 ; + assign wci_11_wciResponse_wget__763_BITS_33_TO_32_764_ETC___d1792 = + wci_11_wciResponse$wget[33:32] == 2'd0 && + !wci_11_respTimr_768_ULT_1_SL_wci_11_wTimeout_7_ETC___d1771 && + (wci_11_reqPend == 2'd1 || wci_11_reqPend == 2'd2 || + wci_11_reqPend == 2'd3) ; + assign wci_12_respTimr_908_ULT_1_SL_wci_12_wTimeout_9_ETC___d1911 = + wci_12_respTimr < toCount__h64126 ; + assign wci_12_wciResponse_wget__903_BITS_33_TO_32_904_ETC___d1932 = + wci_12_wciResponse$wget[33:32] == 2'd0 && + !wci_12_respTimr_908_ULT_1_SL_wci_12_wTimeout_9_ETC___d1911 && + (wci_12_reqPend == 2'd1 || wci_12_reqPend == 2'd2 || + wci_12_reqPend == 2'd3) ; + assign wci_13_respTimr_048_ULT_1_SL_wci_13_wTimeout_0_ETC___d2051 = + wci_13_respTimr < toCount__h68495 ; + assign wci_13_wciResponse_wget__043_BITS_33_TO_32_044_ETC___d2072 = + wci_13_wciResponse$wget[33:32] == 2'd0 && + !wci_13_respTimr_048_ULT_1_SL_wci_13_wTimeout_0_ETC___d2051 && + (wci_13_reqPend == 2'd1 || wci_13_reqPend == 2'd2 || + wci_13_reqPend == 2'd3) ; + assign wci_14_respTimr_188_ULT_1_SL_wci_14_wTimeout_1_ETC___d2191 = + wci_14_respTimr < toCount__h72864 ; + assign wci_14_wciResponse_wget__183_BITS_33_TO_32_184_ETC___d2212 = + wci_14_wciResponse$wget[33:32] == 2'd0 && + !wci_14_respTimr_188_ULT_1_SL_wci_14_wTimeout_1_ETC___d2191 && + (wci_14_reqPend == 2'd1 || wci_14_reqPend == 2'd2 || + wci_14_reqPend == 2'd3) ; + assign wci_1_respTimr_68_ULT_1_SL_wci_1_wTimeout_69_70___d371 = + wci_1_respTimr < toCount__h16067 ; + assign wci_1_wciResponse_wget__63_BITS_33_TO_32_64_EQ_ETC___d392 = + wci_1_wciResponse$wget[33:32] == 2'd0 && + !wci_1_respTimr_68_ULT_1_SL_wci_1_wTimeout_69_70___d371 && + (wci_1_reqPend == 2'd1 || wci_1_reqPend == 2'd2 || + wci_1_reqPend == 2'd3) ; + assign wci_2_respTimr_08_ULT_1_SL_wci_2_wTimeout_09_10___d511 = + wci_2_respTimr < toCount__h20436 ; + assign wci_2_wciResponse_wget__03_BITS_33_TO_32_04_EQ_ETC___d532 = + wci_2_wciResponse$wget[33:32] == 2'd0 && + !wci_2_respTimr_08_ULT_1_SL_wci_2_wTimeout_09_10___d511 && + (wci_2_reqPend == 2'd1 || wci_2_reqPend == 2'd2 || + wci_2_reqPend == 2'd3) ; + assign wci_3_respTimr_48_ULT_1_SL_wci_3_wTimeout_49_50___d651 = + wci_3_respTimr < toCount__h24805 ; + assign wci_3_wciResponse_wget__43_BITS_33_TO_32_44_EQ_ETC___d672 = + wci_3_wciResponse$wget[33:32] == 2'd0 && + !wci_3_respTimr_48_ULT_1_SL_wci_3_wTimeout_49_50___d651 && + (wci_3_reqPend == 2'd1 || wci_3_reqPend == 2'd2 || + wci_3_reqPend == 2'd3) ; + assign wci_4_respTimr_88_ULT_1_SL_wci_4_wTimeout_89_90___d791 = + wci_4_respTimr < toCount__h29174 ; + assign wci_4_wciResponse_wget__83_BITS_33_TO_32_84_EQ_ETC___d812 = + wci_4_wciResponse$wget[33:32] == 2'd0 && + !wci_4_respTimr_88_ULT_1_SL_wci_4_wTimeout_89_90___d791 && + (wci_4_reqPend == 2'd1 || wci_4_reqPend == 2'd2 || + wci_4_reqPend == 2'd3) ; + assign wci_5_respTimr_28_ULT_1_SL_wci_5_wTimeout_29_30___d931 = + wci_5_respTimr < toCount__h33543 ; + assign wci_5_wciResponse_wget__23_BITS_33_TO_32_24_EQ_ETC___d952 = + wci_5_wciResponse$wget[33:32] == 2'd0 && + !wci_5_respTimr_28_ULT_1_SL_wci_5_wTimeout_29_30___d931 && + (wci_5_reqPend == 2'd1 || wci_5_reqPend == 2'd2 || + wci_5_reqPend == 2'd3) ; + assign wci_6_respTimr_068_ULT_1_SL_wci_6_wTimeout_069_ETC___d1071 = + wci_6_respTimr < toCount__h37912 ; + assign wci_6_wciResponse_wget__063_BITS_33_TO_32_064__ETC___d1092 = + wci_6_wciResponse$wget[33:32] == 2'd0 && + !wci_6_respTimr_068_ULT_1_SL_wci_6_wTimeout_069_ETC___d1071 && + (wci_6_reqPend == 2'd1 || wci_6_reqPend == 2'd2 || + wci_6_reqPend == 2'd3) ; + assign wci_7_respTimr_208_ULT_1_SL_wci_7_wTimeout_209_ETC___d1211 = + wci_7_respTimr < toCount__h42281 ; + assign wci_7_wciResponse_wget__203_BITS_33_TO_32_204__ETC___d1232 = + wci_7_wciResponse$wget[33:32] == 2'd0 && + !wci_7_respTimr_208_ULT_1_SL_wci_7_wTimeout_209_ETC___d1211 && + (wci_7_reqPend == 2'd1 || wci_7_reqPend == 2'd2 || + wci_7_reqPend == 2'd3) ; + assign wci_8_respTimr_348_ULT_1_SL_wci_8_wTimeout_349_ETC___d1351 = + wci_8_respTimr < toCount__h46650 ; + assign wci_8_wciResponse_wget__343_BITS_33_TO_32_344__ETC___d1372 = + wci_8_wciResponse$wget[33:32] == 2'd0 && + !wci_8_respTimr_348_ULT_1_SL_wci_8_wTimeout_349_ETC___d1351 && + (wci_8_reqPend == 2'd1 || wci_8_reqPend == 2'd2 || + wci_8_reqPend == 2'd3) ; + assign wci_9_respTimr_488_ULT_1_SL_wci_9_wTimeout_489_ETC___d1491 = + wci_9_respTimr < toCount__h51019 ; + assign wci_9_wciResponse_wget__483_BITS_33_TO_32_484__ETC___d1512 = + wci_9_wciResponse$wget[33:32] == 2'd0 && + !wci_9_respTimr_488_ULT_1_SL_wci_9_wTimeout_489_ETC___d1491 && + (wci_9_reqPend == 2'd1 || wci_9_reqPend == 2'd2 || + wci_9_reqPend == 2'd3) ; + assign wn___1__h76499 = cpReq[27:24] - 4'd1 ; + assign wn__h75723 = cpReq[23:20] - 4'd1 ; + assign x__h104311 = + { wci_14_slvPresent, + wci_13_slvPresent, + wci_12_slvPresent, + wci_11_slvPresent, + wci_10_slvPresent, + wci_9_slvPresent, + wci_8_slvPresent, + wci_7_slvPresent, + wci_6_slvPresent, + wci_5_slvPresent, + wci_4_slvPresent, + wci_3_slvPresent, + wci_2_slvPresent, + wci_1_slvPresent, + wci_0_slvPresent } ; + assign x__h104860 = + { wci_14_wStatus[15:0] != 16'd0, + wci_13_wStatus[15:0] != 16'd0, + wci_12_wStatus[15:0] != 16'd0, + wci_11_wStatus[15:0] != 16'd0, + wci_10_wStatus[15:0] != 16'd0, + wci_9_wStatus[15:0] != 16'd0, + wci_8_wStatus[15:0] != 16'd0, + wci_7_wStatus[15:0] != 16'd0, + wci_6_wStatus[15:0] != 16'd0, + wci_5_wStatus[15:0] != 16'd0, + wci_4_wStatus[15:0] != 16'd0, + wci_3_wStatus[15:0] != 16'd0, + wci_2_wStatus[15:0] != 16'd0, + wci_1_wStatus[15:0] != 16'd0, + wci_0_wStatus[15:0] != 16'd0 } ; + assign x__h11852 = wci_0_respTimr + 32'd1 ; + assign x__h16224 = wci_1_respTimr + 32'd1 ; + assign x__h20593 = wci_2_respTimr + 32'd1 ; + assign x__h24962 = wci_3_respTimr + 32'd1 ; + assign x__h29331 = wci_4_respTimr + 32'd1 ; + assign x__h33700 = wci_5_respTimr + 32'd1 ; + assign x__h3688 = { 2'b0, x_f__h4835 } ; + assign x__h38069 = wci_6_respTimr + 32'd1 ; + assign x__h42438 = wci_7_respTimr + 32'd1 ; + assign x__h4408 = { {28{_281474976710656_MINUS_timeServ_delSecond_BITS__ETC__q2[21]}}, _281474976710656_MINUS_timeServ_delSecond_BITS__ETC__q2 } ; - assign x__h4649 = timeServ_fracSeconds + timeServ_fracInc ; - assign x__h46508 = wci_respTimr_8 + 32'd1 ; - assign x__h4715 = timeServ_refSecCount + 32'd1 ; - assign x__h50948 = wci_respTimr_9 + 32'd1 ; - assign x__h55388 = wci_respTimr_10 + 32'd1 ; - assign x__h59828 = wci_respTimr_11 + 32'd1 ; - assign x__h64268 = wci_respTimr_12 + 32'd1 ; - assign x__h68708 = wci_respTimr_13 + 32'd1 ; - assign x__h73148 = wci_respTimr_14 + 32'd1 ; - assign x__h97614 = { cpReq[8:6], 2'b0 } ; - assign x_addr__h97612 = { 27'd0, x__h97614 } ; - assign x_data__h103818 = { wci_wReset_n, 26'd0, wci_wTimeout } ; - assign x_data__h103824 = - wci_lastConfigAddr[32] ? - wci_lastConfigAddr[31:0] : + assign x__h4636 = timeServ_fracSeconds + timeServ_fracInc ; + assign x__h46807 = wci_8_respTimr + 32'd1 ; + assign x__h4702 = timeServ_refSecCount + 32'd1 ; + assign x__h51176 = wci_9_respTimr + 32'd1 ; + assign x__h55545 = wci_10_respTimr + 32'd1 ; + assign x__h59914 = wci_11_respTimr + 32'd1 ; + assign x__h64283 = wci_12_respTimr + 32'd1 ; + assign x__h68652 = wci_13_respTimr + 32'd1 ; + assign x__h73021 = wci_14_respTimr + 32'd1 ; + assign x__h96608 = { cpReq[8:6], 2'b0 } ; + assign x_addr__h96606 = { 27'd0, x__h96608 } ; + assign x_data__h102795 = { wci_0_wReset_n, 26'd0, wci_0_wTimeout } ; + assign x_data__h102801 = + wci_0_lastConfigAddr[32] ? + wci_0_lastConfigAddr[31:0] : 32'hFFFFFFFF ; - assign x_data__h103871 = { wci_wReset_n_1, 26'd0, wci_wTimeout_1 } ; - assign x_data__h103877 = - wci_lastConfigAddr_1[32] ? - wci_lastConfigAddr_1[31:0] : + assign x_data__h102846 = { wci_1_wReset_n, 26'd0, wci_1_wTimeout } ; + assign x_data__h102852 = + wci_1_lastConfigAddr[32] ? + wci_1_lastConfigAddr[31:0] : 32'hFFFFFFFF ; - assign x_data__h103924 = { wci_wReset_n_2, 26'd0, wci_wTimeout_2 } ; - assign x_data__h103930 = - wci_lastConfigAddr_2[32] ? - wci_lastConfigAddr_2[31:0] : + assign x_data__h102897 = { wci_2_wReset_n, 26'd0, wci_2_wTimeout } ; + assign x_data__h102903 = + wci_2_lastConfigAddr[32] ? + wci_2_lastConfigAddr[31:0] : 32'hFFFFFFFF ; - assign x_data__h103977 = { wci_wReset_n_3, 26'd0, wci_wTimeout_3 } ; - assign x_data__h103983 = - wci_lastConfigAddr_3[32] ? - wci_lastConfigAddr_3[31:0] : + assign x_data__h102948 = { wci_3_wReset_n, 26'd0, wci_3_wTimeout } ; + assign x_data__h102954 = + wci_3_lastConfigAddr[32] ? + wci_3_lastConfigAddr[31:0] : 32'hFFFFFFFF ; - assign x_data__h104030 = { wci_wReset_n_4, 26'd0, wci_wTimeout_4 } ; - assign x_data__h104036 = - wci_lastConfigAddr_4[32] ? - wci_lastConfigAddr_4[31:0] : + assign x_data__h102999 = { wci_4_wReset_n, 26'd0, wci_4_wTimeout } ; + assign x_data__h103005 = + wci_4_lastConfigAddr[32] ? + wci_4_lastConfigAddr[31:0] : 32'hFFFFFFFF ; - assign x_data__h104083 = { wci_wReset_n_5, 26'd0, wci_wTimeout_5 } ; - assign x_data__h104089 = - wci_lastConfigAddr_5[32] ? - wci_lastConfigAddr_5[31:0] : + assign x_data__h103050 = { wci_5_wReset_n, 26'd0, wci_5_wTimeout } ; + assign x_data__h103056 = + wci_5_lastConfigAddr[32] ? + wci_5_lastConfigAddr[31:0] : 32'hFFFFFFFF ; - assign x_data__h104136 = { wci_wReset_n_6, 26'd0, wci_wTimeout_6 } ; - assign x_data__h104142 = - wci_lastConfigAddr_6[32] ? - wci_lastConfigAddr_6[31:0] : + assign x_data__h103101 = { wci_6_wReset_n, 26'd0, wci_6_wTimeout } ; + assign x_data__h103107 = + wci_6_lastConfigAddr[32] ? + wci_6_lastConfigAddr[31:0] : 32'hFFFFFFFF ; - assign x_data__h104189 = { wci_wReset_n_7, 26'd0, wci_wTimeout_7 } ; - assign x_data__h104195 = - wci_lastConfigAddr_7[32] ? - wci_lastConfigAddr_7[31:0] : + assign x_data__h103152 = { wci_7_wReset_n, 26'd0, wci_7_wTimeout } ; + assign x_data__h103158 = + wci_7_lastConfigAddr[32] ? + wci_7_lastConfigAddr[31:0] : 32'hFFFFFFFF ; - assign x_data__h104242 = { wci_wReset_n_8, 26'd0, wci_wTimeout_8 } ; - assign x_data__h104248 = - wci_lastConfigAddr_8[32] ? - wci_lastConfigAddr_8[31:0] : + assign x_data__h103203 = { wci_8_wReset_n, 26'd0, wci_8_wTimeout } ; + assign x_data__h103209 = + wci_8_lastConfigAddr[32] ? + wci_8_lastConfigAddr[31:0] : 32'hFFFFFFFF ; - assign x_data__h104295 = { wci_wReset_n_9, 26'd0, wci_wTimeout_9 } ; - assign x_data__h104301 = - wci_lastConfigAddr_9[32] ? - wci_lastConfigAddr_9[31:0] : + assign x_data__h103254 = { wci_9_wReset_n, 26'd0, wci_9_wTimeout } ; + assign x_data__h103260 = + wci_9_lastConfigAddr[32] ? + wci_9_lastConfigAddr[31:0] : 32'hFFFFFFFF ; - assign x_data__h104348 = { wci_wReset_n_10, 26'd0, wci_wTimeout_10 } ; - assign x_data__h104354 = - wci_lastConfigAddr_10[32] ? - wci_lastConfigAddr_10[31:0] : + assign x_data__h103305 = { wci_10_wReset_n, 26'd0, wci_10_wTimeout } ; + assign x_data__h103311 = + wci_10_lastConfigAddr[32] ? + wci_10_lastConfigAddr[31:0] : 32'hFFFFFFFF ; - assign x_data__h104401 = { wci_wReset_n_11, 26'd0, wci_wTimeout_11 } ; - assign x_data__h104407 = - wci_lastConfigAddr_11[32] ? - wci_lastConfigAddr_11[31:0] : + assign x_data__h103356 = { wci_11_wReset_n, 26'd0, wci_11_wTimeout } ; + assign x_data__h103362 = + wci_11_lastConfigAddr[32] ? + wci_11_lastConfigAddr[31:0] : 32'hFFFFFFFF ; - assign x_data__h104454 = { wci_wReset_n_12, 26'd0, wci_wTimeout_12 } ; - assign x_data__h104460 = - wci_lastConfigAddr_12[32] ? - wci_lastConfigAddr_12[31:0] : + assign x_data__h103407 = { wci_12_wReset_n, 26'd0, wci_12_wTimeout } ; + assign x_data__h103413 = + wci_12_lastConfigAddr[32] ? + wci_12_lastConfigAddr[31:0] : 32'hFFFFFFFF ; - assign x_data__h104507 = { wci_wReset_n_13, 26'd0, wci_wTimeout_13 } ; - assign x_data__h104513 = - wci_lastConfigAddr_13[32] ? - wci_lastConfigAddr_13[31:0] : + assign x_data__h103458 = { wci_13_wReset_n, 26'd0, wci_13_wTimeout } ; + assign x_data__h103464 = + wci_13_lastConfigAddr[32] ? + wci_13_lastConfigAddr[31:0] : 32'hFFFFFFFF ; - assign x_data__h104560 = { wci_wReset_n_14, 26'd0, wci_wTimeout_14 } ; - assign x_data__h104566 = - wci_lastConfigAddr_14[32] ? - wci_lastConfigAddr_14[31:0] : + assign x_data__h103509 = { wci_14_wReset_n, 26'd0, wci_14_wTimeout } ; + assign x_data__h103515 = + wci_14_lastConfigAddr[32] ? + wci_14_lastConfigAddr[31:0] : 32'hFFFFFFFF ; - assign x_f__h4848 = { timeServ_setRefF$dD_OUT[31:0], 16'h0 } ; + assign x_f__h4835 = { timeServ_setRefF$dD_OUT[31:0], 16'h0 } ; + assign x_wget__h5213 = { 7'd0, dna_sr } ; always@(wrkAct or - wci_respF_14$D_OUT or - wci_respF$D_OUT or - wci_respF_1$D_OUT or - wci_respF_2$D_OUT or - wci_respF_3$D_OUT or - wci_respF_4$D_OUT or - wci_respF_5$D_OUT or - wci_respF_6$D_OUT or - wci_respF_7$D_OUT or - wci_respF_8$D_OUT or - wci_respF_9$D_OUT or - wci_respF_10$D_OUT or - wci_respF_11$D_OUT or wci_respF_12$D_OUT or wci_respF_13$D_OUT) + wci_0_respF$D_OUT or + wci_1_respF$D_OUT or + wci_2_respF$D_OUT or + wci_3_respF$D_OUT or + wci_4_respF$D_OUT or + wci_5_respF$D_OUT or + wci_6_respF$D_OUT or + wci_7_respF$D_OUT or + wci_8_respF$D_OUT or + wci_9_respF$D_OUT or + wci_10_respF$D_OUT or + wci_11_respF$D_OUT or + wci_12_respF$D_OUT or wci_13_respF$D_OUT or wci_14_respF$D_OUT) begin case (wrkAct) - 4'd0: rtnData__h112395 = wci_respF$D_OUT[31:0]; - 4'd1: rtnData__h112395 = wci_respF_1$D_OUT[31:0]; - 4'd2: rtnData__h112395 = wci_respF_2$D_OUT[31:0]; - 4'd3: rtnData__h112395 = wci_respF_3$D_OUT[31:0]; - 4'd4: rtnData__h112395 = wci_respF_4$D_OUT[31:0]; - 4'd5: rtnData__h112395 = wci_respF_5$D_OUT[31:0]; - 4'd6: rtnData__h112395 = wci_respF_6$D_OUT[31:0]; - 4'd7: rtnData__h112395 = wci_respF_7$D_OUT[31:0]; - 4'd8: rtnData__h112395 = wci_respF_8$D_OUT[31:0]; - 4'd9: rtnData__h112395 = wci_respF_9$D_OUT[31:0]; - 4'd10: rtnData__h112395 = wci_respF_10$D_OUT[31:0]; - 4'd11: rtnData__h112395 = wci_respF_11$D_OUT[31:0]; - 4'd12: rtnData__h112395 = wci_respF_12$D_OUT[31:0]; - 4'd13: rtnData__h112395 = wci_respF_13$D_OUT[31:0]; - default: rtnData__h112395 = wci_respF_14$D_OUT[31:0]; + 4'd0: rtnData__h110501 = wci_0_respF$D_OUT[31:0]; + 4'd1: rtnData__h110501 = wci_1_respF$D_OUT[31:0]; + 4'd2: rtnData__h110501 = wci_2_respF$D_OUT[31:0]; + 4'd3: rtnData__h110501 = wci_3_respF$D_OUT[31:0]; + 4'd4: rtnData__h110501 = wci_4_respF$D_OUT[31:0]; + 4'd5: rtnData__h110501 = wci_5_respF$D_OUT[31:0]; + 4'd6: rtnData__h110501 = wci_6_respF$D_OUT[31:0]; + 4'd7: rtnData__h110501 = wci_7_respF$D_OUT[31:0]; + 4'd8: rtnData__h110501 = wci_8_respF$D_OUT[31:0]; + 4'd9: rtnData__h110501 = wci_9_respF$D_OUT[31:0]; + 4'd10: rtnData__h110501 = wci_10_respF$D_OUT[31:0]; + 4'd11: rtnData__h110501 = wci_11_respF$D_OUT[31:0]; + 4'd12: rtnData__h110501 = wci_12_respF$D_OUT[31:0]; + 4'd13: rtnData__h110501 = wci_13_respF$D_OUT[31:0]; + 4'd14: rtnData__h110501 = wci_14_respF$D_OUT[31:0]; + 4'd15: rtnData__h110501 = 32'hAAAAAAAA /* unspecified value */ ; endcase end - always@(cpReq or - timeServ_ppsLostSticky or - timeServ_gpsInSticky or - timeServ_ppsInSticky or - timeServ_timeSetSticky or - timeServ_ppsOKCC$dD_OUT or - timeServ_ppsLostCC$dD_OUT or - timeServ_rollingPPSIn$dD_OUT or - timeServ_rplTimeControl or - timeServ_nowInCC$dD_OUT or - deltaTime or timeServ_refPerPPS$dD_OUT or readCntReg) + always@(_theResult_____1__h75724 or + wci_0_busy or + wci_0_reqF_cntr_r or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) begin - case (cpReq[11:4]) - 8'h30: - IF_cpReq_337_BITS_11_TO_4_340_EQ_0x30_569_THEN_ETC___d6151 = - { timeServ_ppsLostSticky, - timeServ_gpsInSticky, - timeServ_ppsInSticky, - timeServ_timeSetSticky, - timeServ_ppsOKCC$dD_OUT, - timeServ_ppsLostCC$dD_OUT, - 18'h0, - timeServ_rollingPPSIn$dD_OUT }; - 8'h34: - IF_cpReq_337_BITS_11_TO_4_340_EQ_0x30_569_THEN_ETC___d6151 = - { 27'd0, timeServ_rplTimeControl }; - 8'h38: - IF_cpReq_337_BITS_11_TO_4_340_EQ_0x30_569_THEN_ETC___d6151 = - timeServ_nowInCC$dD_OUT[63:32]; - 8'h3C: - IF_cpReq_337_BITS_11_TO_4_340_EQ_0x30_569_THEN_ETC___d6151 = - timeServ_nowInCC$dD_OUT[31:0]; - 8'h40: - IF_cpReq_337_BITS_11_TO_4_340_EQ_0x30_569_THEN_ETC___d6151 = - deltaTime[63:32]; - 8'h44: - IF_cpReq_337_BITS_11_TO_4_340_EQ_0x30_569_THEN_ETC___d6151 = - deltaTime[31:0]; - 8'h48: - IF_cpReq_337_BITS_11_TO_4_340_EQ_0x30_569_THEN_ETC___d6151 = - { 4'd0, timeServ_refPerPPS$dD_OUT }; - 8'h4C: - IF_cpReq_337_BITS_11_TO_4_340_EQ_0x30_569_THEN_ETC___d6151 = - readCntReg; - 8'h50, 8'h54: - IF_cpReq_337_BITS_11_TO_4_340_EQ_0x30_569_THEN_ETC___d6151 = - 32'b00001011101011011100000011011110; - 8'h7C: - IF_cpReq_337_BITS_11_TO_4_340_EQ_0x30_569_THEN_ETC___d6151 = 32'd2; - 8'h80: - IF_cpReq_337_BITS_11_TO_4_340_EQ_0x30_569_THEN_ETC___d6151 = - 32'd268435464; - default: IF_cpReq_337_BITS_11_TO_4_340_EQ_0x30_569_THEN_ETC___d6151 = - 32'd268566536; + case (_theResult_____1__h75724) + 4'd0: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d2943 = + !wci_0_busy && !wci_0_reqF_cntr_r; + 4'd1: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d2943 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; + 4'd2: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d2943 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; + 4'd3: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d2943 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; + 4'd4: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d2943 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; + 4'd5: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d2943 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; + 4'd6: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d2943 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; + 4'd7: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d2943 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; + 4'd8: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d2943 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; + 4'd9: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d2943 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; + 4'd10: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d2943 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; + 4'd11: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d2943 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; + 4'd12: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d2943 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; + 4'd13: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d2943 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; + 4'd14: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d2943 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; + 4'd15: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d2943 = 1'd1; endcase end - always@(wrkAct or - wci_respF_14$EMPTY_N or - wci_respF$EMPTY_N or - wci_respF_1$EMPTY_N or - wci_respF_2$EMPTY_N or - wci_respF_3$EMPTY_N or - wci_respF_4$EMPTY_N or - wci_respF_5$EMPTY_N or - wci_respF_6$EMPTY_N or - wci_respF_7$EMPTY_N or - wci_respF_8$EMPTY_N or - wci_respF_9$EMPTY_N or - wci_respF_10$EMPTY_N or - wci_respF_11$EMPTY_N or - wci_respF_12$EMPTY_N or wci_respF_13$EMPTY_N) + always@(_theResult_____1__h75724 or + wci_0_busy or + wci_0_wReset_n or + wci_0_respF$FULL_N or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) begin - case (wrkAct) + case (_theResult_____1__h75724) 4'd0: - IF_wrkAct_051_EQ_0_052_THEN_wci_respF_i_notEmp_ETC___d6101 = - wci_respF$EMPTY_N; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d2961 = + !wci_0_busy && (wci_0_wReset_n || wci_0_respF$FULL_N); 4'd1: - IF_wrkAct_051_EQ_0_052_THEN_wci_respF_i_notEmp_ETC___d6101 = - wci_respF_1$EMPTY_N; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d2961 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; 4'd2: - IF_wrkAct_051_EQ_0_052_THEN_wci_respF_i_notEmp_ETC___d6101 = - wci_respF_2$EMPTY_N; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d2961 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; 4'd3: - IF_wrkAct_051_EQ_0_052_THEN_wci_respF_i_notEmp_ETC___d6101 = - wci_respF_3$EMPTY_N; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d2961 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; 4'd4: - IF_wrkAct_051_EQ_0_052_THEN_wci_respF_i_notEmp_ETC___d6101 = - wci_respF_4$EMPTY_N; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d2961 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; 4'd5: - IF_wrkAct_051_EQ_0_052_THEN_wci_respF_i_notEmp_ETC___d6101 = - wci_respF_5$EMPTY_N; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d2961 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; 4'd6: - IF_wrkAct_051_EQ_0_052_THEN_wci_respF_i_notEmp_ETC___d6101 = - wci_respF_6$EMPTY_N; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d2961 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; 4'd7: - IF_wrkAct_051_EQ_0_052_THEN_wci_respF_i_notEmp_ETC___d6101 = - wci_respF_7$EMPTY_N; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d2961 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; 4'd8: - IF_wrkAct_051_EQ_0_052_THEN_wci_respF_i_notEmp_ETC___d6101 = - wci_respF_8$EMPTY_N; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d2961 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; 4'd9: - IF_wrkAct_051_EQ_0_052_THEN_wci_respF_i_notEmp_ETC___d6101 = - wci_respF_9$EMPTY_N; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d2961 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; 4'd10: - IF_wrkAct_051_EQ_0_052_THEN_wci_respF_i_notEmp_ETC___d6101 = - wci_respF_10$EMPTY_N; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d2961 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; 4'd11: - IF_wrkAct_051_EQ_0_052_THEN_wci_respF_i_notEmp_ETC___d6101 = - wci_respF_11$EMPTY_N; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d2961 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; 4'd12: - IF_wrkAct_051_EQ_0_052_THEN_wci_respF_i_notEmp_ETC___d6101 = - wci_respF_12$EMPTY_N; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d2961 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; 4'd13: - IF_wrkAct_051_EQ_0_052_THEN_wci_respF_i_notEmp_ETC___d6101 = - wci_respF_13$EMPTY_N; - default: IF_wrkAct_051_EQ_0_052_THEN_wci_respF_i_notEmp_ETC___d6101 = - wrkAct != 4'd14 || wci_respF_14$EMPTY_N; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d2961 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; + 4'd14: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d2961 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; + 4'd15: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d2961 = 1'd1; endcase end - always@(cpReq or - x__h105402 or - pciDevice or - x__h105951 or - cpStatus__h74993 or scratch20 or scratch24 or cpControl) + always@(_theResult_____1__h75724 or + wci_0_busy or + wci_0_respF$FULL_N or + wci_1_busy or + wci_1_respF$FULL_N or + wci_2_busy or + wci_2_respF$FULL_N or + wci_3_busy or + wci_3_respF$FULL_N or + wci_4_busy or + wci_4_respF$FULL_N or + wci_5_busy or + wci_5_respF$FULL_N or + wci_6_busy or + wci_6_respF$FULL_N or + wci_7_busy or + wci_7_respF$FULL_N or + wci_8_busy or + wci_8_respF$FULL_N or + wci_9_busy or + wci_9_respF$FULL_N or + wci_10_busy or + wci_10_respF$FULL_N or + wci_11_busy or + wci_11_respF$FULL_N or + wci_12_busy or + wci_12_respF$FULL_N or + wci_13_busy or + wci_13_respF$FULL_N or wci_14_busy or wci_14_respF$FULL_N) begin - case (cpReq[11:4]) - 8'h0: - IF_cpReq_337_BITS_11_TO_4_340_EQ_0x0_419_THEN__ETC___d6152 = - 32'h4F70656E; - 8'h04: - IF_cpReq_337_BITS_11_TO_4_340_EQ_0x0_419_THEN__ETC___d6152 = - 32'h43504900; - 8'h08: - IF_cpReq_337_BITS_11_TO_4_340_EQ_0x0_419_THEN__ETC___d6152 = - 32'h00000001; - 8'h0C: - IF_cpReq_337_BITS_11_TO_4_340_EQ_0x0_419_THEN__ETC___d6152 = - 32'd1355260760; - 8'h10: - IF_cpReq_337_BITS_11_TO_4_340_EQ_0x0_419_THEN__ETC___d6152 = - { 17'd0, x__h105402 }; - 8'h14: - IF_cpReq_337_BITS_11_TO_4_340_EQ_0x0_419_THEN__ETC___d6152 = - { 16'd0, pciDevice }; - 8'h18: - IF_cpReq_337_BITS_11_TO_4_340_EQ_0x0_419_THEN__ETC___d6152 = - { 17'd0, x__h105951 }; - 8'h1C: - IF_cpReq_337_BITS_11_TO_4_340_EQ_0x0_419_THEN__ETC___d6152 = - cpStatus__h74993; - 8'h20: - IF_cpReq_337_BITS_11_TO_4_340_EQ_0x0_419_THEN__ETC___d6152 = - scratch20; - 8'h24: - IF_cpReq_337_BITS_11_TO_4_340_EQ_0x0_419_THEN__ETC___d6152 = - scratch24; - 8'h28: - IF_cpReq_337_BITS_11_TO_4_340_EQ_0x0_419_THEN__ETC___d6152 = - cpControl; - default: IF_cpReq_337_BITS_11_TO_4_340_EQ_0x0_419_THEN__ETC___d6152 = - 32'd0; + case (_theResult_____1__h75724) + 4'd0: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d2986 = + !wci_0_busy && wci_0_respF$FULL_N; + 4'd1: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d2986 = + !wci_1_busy && wci_1_respF$FULL_N; + 4'd2: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d2986 = + !wci_2_busy && wci_2_respF$FULL_N; + 4'd3: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d2986 = + !wci_3_busy && wci_3_respF$FULL_N; + 4'd4: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d2986 = + !wci_4_busy && wci_4_respF$FULL_N; + 4'd5: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d2986 = + !wci_5_busy && wci_5_respF$FULL_N; + 4'd6: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d2986 = + !wci_6_busy && wci_6_respF$FULL_N; + 4'd7: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d2986 = + !wci_7_busy && wci_7_respF$FULL_N; + 4'd8: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d2986 = + !wci_8_busy && wci_8_respF$FULL_N; + 4'd9: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d2986 = + !wci_9_busy && wci_9_respF$FULL_N; + 4'd10: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d2986 = + !wci_10_busy && wci_10_respF$FULL_N; + 4'd11: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d2986 = + !wci_11_busy && wci_11_respF$FULL_N; + 4'd12: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d2986 = + !wci_12_busy && wci_12_respF$FULL_N; + 4'd13: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d2986 = + !wci_13_busy && wci_13_respF$FULL_N; + 4'd14: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d2986 = + !wci_14_busy && wci_14_respF$FULL_N; + 4'd15: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d2986 = 1'd1; endcase end - always@(cpReq or uuid_arg) + always@(_theResult_____1__h75724 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + wci_1_busy or + wci_1_reqF_cntr_r or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) begin - case (cpReq[9:6]) + case (_theResult_____1__h75724) 4'd0: - CASE_cpReq_BITS_9_TO_6_uuid_arg_BITS_31_TO_0_0_ETC__q3 = - uuid_arg[511:480]; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3049 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; 4'd1: - CASE_cpReq_BITS_9_TO_6_uuid_arg_BITS_31_TO_0_0_ETC__q3 = - uuid_arg[479:448]; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3049 = + !wci_1_busy && !wci_1_reqF_cntr_r; 4'd2: - CASE_cpReq_BITS_9_TO_6_uuid_arg_BITS_31_TO_0_0_ETC__q3 = - uuid_arg[447:416]; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3049 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; 4'd3: - CASE_cpReq_BITS_9_TO_6_uuid_arg_BITS_31_TO_0_0_ETC__q3 = - uuid_arg[415:384]; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3049 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; 4'd4: - CASE_cpReq_BITS_9_TO_6_uuid_arg_BITS_31_TO_0_0_ETC__q3 = - uuid_arg[383:352]; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3049 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; 4'd5: - CASE_cpReq_BITS_9_TO_6_uuid_arg_BITS_31_TO_0_0_ETC__q3 = - uuid_arg[351:320]; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3049 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; 4'd6: - CASE_cpReq_BITS_9_TO_6_uuid_arg_BITS_31_TO_0_0_ETC__q3 = - uuid_arg[319:288]; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3049 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; 4'd7: - CASE_cpReq_BITS_9_TO_6_uuid_arg_BITS_31_TO_0_0_ETC__q3 = - uuid_arg[287:256]; - 4'h8: - CASE_cpReq_BITS_9_TO_6_uuid_arg_BITS_31_TO_0_0_ETC__q3 = - uuid_arg[255:224]; - 4'h9: - CASE_cpReq_BITS_9_TO_6_uuid_arg_BITS_31_TO_0_0_ETC__q3 = - uuid_arg[223:192]; - 4'hA: - CASE_cpReq_BITS_9_TO_6_uuid_arg_BITS_31_TO_0_0_ETC__q3 = - uuid_arg[191:160]; + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3049 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; + 4'd8: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3049 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; + 4'd9: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3049 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; + 4'd10: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3049 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; 4'd11: - CASE_cpReq_BITS_9_TO_6_uuid_arg_BITS_31_TO_0_0_ETC__q3 = - uuid_arg[159:128]; - 4'hC: - CASE_cpReq_BITS_9_TO_6_uuid_arg_BITS_31_TO_0_0_ETC__q3 = + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3049 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; + 4'd12: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3049 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; + 4'd13: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3049 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; + 4'd14: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3049 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; + 4'd15: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3049 = 1'd1; + endcase + end + always@(_theResult_____1__h75724 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + wci_1_busy or + wci_1_wReset_n or + wci_1_respF$FULL_N or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) + begin + case (_theResult_____1__h75724) + 4'd0: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3060 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; + 4'd1: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3060 = + !wci_1_busy && (wci_1_wReset_n || wci_1_respF$FULL_N); + 4'd2: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3060 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; + 4'd3: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3060 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; + 4'd4: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3060 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; + 4'd5: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3060 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; + 4'd6: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3060 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; + 4'd7: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3060 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; + 4'd8: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3060 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; + 4'd9: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3060 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; + 4'd10: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3060 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; + 4'd11: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3060 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; + 4'd12: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3060 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; + 4'd13: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3060 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; + 4'd14: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3060 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; + 4'd15: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3060 = 1'd1; + endcase + end + always@(_theResult_____1__h75724 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + wci_2_busy or + wci_2_reqF_cntr_r or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) + begin + case (_theResult_____1__h75724) + 4'd0: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3085 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; + 4'd1: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3085 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; + 4'd2: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3085 = + !wci_2_busy && !wci_2_reqF_cntr_r; + 4'd3: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3085 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; + 4'd4: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3085 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; + 4'd5: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3085 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; + 4'd6: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3085 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; + 4'd7: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3085 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; + 4'd8: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3085 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; + 4'd9: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3085 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; + 4'd10: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3085 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; + 4'd11: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3085 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; + 4'd12: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3085 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; + 4'd13: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3085 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; + 4'd14: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3085 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; + 4'd15: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3085 = 1'd1; + endcase + end + always@(_theResult_____1__h75724 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + wci_2_busy or + wci_2_wReset_n or + wci_2_respF$FULL_N or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) + begin + case (_theResult_____1__h75724) + 4'd0: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3096 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; + 4'd1: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3096 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; + 4'd2: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3096 = + !wci_2_busy && (wci_2_wReset_n || wci_2_respF$FULL_N); + 4'd3: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3096 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; + 4'd4: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3096 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; + 4'd5: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3096 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; + 4'd6: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3096 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; + 4'd7: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3096 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; + 4'd8: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3096 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; + 4'd9: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3096 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; + 4'd10: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3096 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; + 4'd11: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3096 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; + 4'd12: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3096 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; + 4'd13: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3096 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; + 4'd14: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3096 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; + 4'd15: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3096 = 1'd1; + endcase + end + always@(_theResult_____1__h75724 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + wci_3_busy or + wci_3_reqF_cntr_r or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) + begin + case (_theResult_____1__h75724) + 4'd0: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3121 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; + 4'd1: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3121 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; + 4'd2: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3121 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; + 4'd3: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3121 = + !wci_3_busy && !wci_3_reqF_cntr_r; + 4'd4: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3121 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; + 4'd5: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3121 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; + 4'd6: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3121 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; + 4'd7: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3121 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; + 4'd8: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3121 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; + 4'd9: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3121 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; + 4'd10: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3121 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; + 4'd11: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3121 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; + 4'd12: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3121 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; + 4'd13: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3121 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; + 4'd14: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3121 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; + 4'd15: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3121 = 1'd1; + endcase + end + always@(_theResult_____1__h75724 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + wci_3_busy or + wci_3_wReset_n or + wci_3_respF$FULL_N or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) + begin + case (_theResult_____1__h75724) + 4'd0: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3132 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; + 4'd1: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3132 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; + 4'd2: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3132 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; + 4'd3: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3132 = + !wci_3_busy && (wci_3_wReset_n || wci_3_respF$FULL_N); + 4'd4: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3132 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; + 4'd5: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3132 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; + 4'd6: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3132 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; + 4'd7: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3132 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; + 4'd8: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3132 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; + 4'd9: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3132 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; + 4'd10: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3132 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; + 4'd11: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3132 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; + 4'd12: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3132 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; + 4'd13: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3132 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; + 4'd14: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3132 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; + 4'd15: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3132 = 1'd1; + endcase + end + always@(_theResult_____1__h75724 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + wci_4_busy or + wci_4_reqF_cntr_r or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) + begin + case (_theResult_____1__h75724) + 4'd0: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3157 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; + 4'd1: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3157 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; + 4'd2: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3157 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; + 4'd3: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3157 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; + 4'd4: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3157 = + !wci_4_busy && !wci_4_reqF_cntr_r; + 4'd5: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3157 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; + 4'd6: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3157 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; + 4'd7: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3157 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; + 4'd8: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3157 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; + 4'd9: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3157 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; + 4'd10: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3157 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; + 4'd11: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3157 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; + 4'd12: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3157 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; + 4'd13: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3157 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; + 4'd14: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3157 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; + 4'd15: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3157 = 1'd1; + endcase + end + always@(_theResult_____1__h75724 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + wci_4_busy or + wci_4_wReset_n or + wci_4_respF$FULL_N or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) + begin + case (_theResult_____1__h75724) + 4'd0: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3168 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; + 4'd1: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3168 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; + 4'd2: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3168 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; + 4'd3: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3168 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; + 4'd4: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3168 = + !wci_4_busy && (wci_4_wReset_n || wci_4_respF$FULL_N); + 4'd5: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3168 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; + 4'd6: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3168 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; + 4'd7: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3168 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; + 4'd8: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3168 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; + 4'd9: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3168 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; + 4'd10: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3168 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; + 4'd11: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3168 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; + 4'd12: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3168 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; + 4'd13: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3168 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; + 4'd14: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3168 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; + 4'd15: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3168 = 1'd1; + endcase + end + always@(_theResult_____1__h75724 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + wci_5_busy or + wci_5_reqF_cntr_r or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) + begin + case (_theResult_____1__h75724) + 4'd0: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3193 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; + 4'd1: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3193 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; + 4'd2: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3193 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; + 4'd3: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3193 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; + 4'd4: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3193 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; + 4'd5: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3193 = + !wci_5_busy && !wci_5_reqF_cntr_r; + 4'd6: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3193 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; + 4'd7: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3193 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; + 4'd8: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3193 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; + 4'd9: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3193 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; + 4'd10: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3193 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; + 4'd11: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3193 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; + 4'd12: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3193 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; + 4'd13: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3193 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; + 4'd14: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3193 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; + 4'd15: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3193 = 1'd1; + endcase + end + always@(_theResult_____1__h75724 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + wci_5_busy or + wci_5_wReset_n or + wci_5_respF$FULL_N or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) + begin + case (_theResult_____1__h75724) + 4'd0: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3204 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; + 4'd1: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3204 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; + 4'd2: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3204 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; + 4'd3: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3204 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; + 4'd4: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3204 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; + 4'd5: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3204 = + !wci_5_busy && (wci_5_wReset_n || wci_5_respF$FULL_N); + 4'd6: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3204 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; + 4'd7: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3204 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; + 4'd8: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3204 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; + 4'd9: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3204 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; + 4'd10: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3204 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; + 4'd11: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3204 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; + 4'd12: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3204 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; + 4'd13: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3204 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; + 4'd14: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3204 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; + 4'd15: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3204 = 1'd1; + endcase + end + always@(_theResult_____1__h75724 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + wci_6_busy or + wci_6_reqF_cntr_r or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) + begin + case (_theResult_____1__h75724) + 4'd0: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3229 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; + 4'd1: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3229 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; + 4'd2: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3229 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; + 4'd3: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3229 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; + 4'd4: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3229 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; + 4'd5: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3229 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; + 4'd6: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3229 = + !wci_6_busy && !wci_6_reqF_cntr_r; + 4'd7: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3229 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; + 4'd8: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3229 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; + 4'd9: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3229 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; + 4'd10: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3229 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; + 4'd11: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3229 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; + 4'd12: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3229 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; + 4'd13: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3229 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; + 4'd14: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3229 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; + 4'd15: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3229 = 1'd1; + endcase + end + always@(_theResult_____1__h75724 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + wci_6_busy or + wci_6_wReset_n or + wci_6_respF$FULL_N or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) + begin + case (_theResult_____1__h75724) + 4'd0: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3240 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; + 4'd1: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3240 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; + 4'd2: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3240 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; + 4'd3: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3240 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; + 4'd4: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3240 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; + 4'd5: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3240 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; + 4'd6: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3240 = + !wci_6_busy && (wci_6_wReset_n || wci_6_respF$FULL_N); + 4'd7: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3240 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; + 4'd8: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3240 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; + 4'd9: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3240 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; + 4'd10: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3240 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; + 4'd11: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3240 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; + 4'd12: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3240 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; + 4'd13: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3240 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; + 4'd14: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3240 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; + 4'd15: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3240 = 1'd1; + endcase + end + always@(_theResult_____1__h75724 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + wci_7_busy or + wci_7_reqF_cntr_r or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) + begin + case (_theResult_____1__h75724) + 4'd0: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3265 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; + 4'd1: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3265 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; + 4'd2: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3265 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; + 4'd3: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3265 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; + 4'd4: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3265 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; + 4'd5: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3265 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; + 4'd6: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3265 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; + 4'd7: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3265 = + !wci_7_busy && !wci_7_reqF_cntr_r; + 4'd8: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3265 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; + 4'd9: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3265 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; + 4'd10: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3265 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; + 4'd11: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3265 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; + 4'd12: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3265 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; + 4'd13: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3265 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; + 4'd14: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3265 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; + 4'd15: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3265 = 1'd1; + endcase + end + always@(_theResult_____1__h75724 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + wci_8_busy or + wci_8_wReset_n or + wci_8_respF$FULL_N or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) + begin + case (_theResult_____1__h75724) + 4'd0: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3312 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; + 4'd1: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3312 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; + 4'd2: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3312 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; + 4'd3: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3312 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; + 4'd4: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3312 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; + 4'd5: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3312 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; + 4'd6: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3312 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; + 4'd7: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3312 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; + 4'd8: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3312 = + !wci_8_busy && (wci_8_wReset_n || wci_8_respF$FULL_N); + 4'd9: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3312 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; + 4'd10: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3312 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; + 4'd11: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3312 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; + 4'd12: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3312 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; + 4'd13: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3312 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; + 4'd14: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3312 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; + 4'd15: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3312 = 1'd1; + endcase + end + always@(_theResult_____1__h75724 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + wci_7_busy or + wci_7_wReset_n or + wci_7_respF$FULL_N or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) + begin + case (_theResult_____1__h75724) + 4'd0: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3276 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; + 4'd1: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3276 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; + 4'd2: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3276 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; + 4'd3: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3276 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; + 4'd4: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3276 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; + 4'd5: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3276 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; + 4'd6: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3276 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; + 4'd7: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3276 = + !wci_7_busy && (wci_7_wReset_n || wci_7_respF$FULL_N); + 4'd8: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3276 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; + 4'd9: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3276 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; + 4'd10: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3276 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; + 4'd11: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3276 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; + 4'd12: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3276 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; + 4'd13: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3276 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; + 4'd14: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3276 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; + 4'd15: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3276 = 1'd1; + endcase + end + always@(_theResult_____1__h75724 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + wci_8_busy or + wci_8_reqF_cntr_r or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) + begin + case (_theResult_____1__h75724) + 4'd0: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3301 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; + 4'd1: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3301 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; + 4'd2: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3301 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; + 4'd3: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3301 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; + 4'd4: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3301 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; + 4'd5: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3301 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; + 4'd6: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3301 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; + 4'd7: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3301 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; + 4'd8: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3301 = + !wci_8_busy && !wci_8_reqF_cntr_r; + 4'd9: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3301 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; + 4'd10: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3301 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; + 4'd11: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3301 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; + 4'd12: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3301 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; + 4'd13: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3301 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; + 4'd14: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3301 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; + 4'd15: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3301 = 1'd1; + endcase + end + always@(_theResult_____1__h75724 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + wci_9_busy or + wci_9_reqF_cntr_r or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) + begin + case (_theResult_____1__h75724) + 4'd0: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3337 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; + 4'd1: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3337 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; + 4'd2: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3337 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; + 4'd3: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3337 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; + 4'd4: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3337 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; + 4'd5: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3337 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; + 4'd6: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3337 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; + 4'd7: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3337 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; + 4'd8: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3337 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; + 4'd9: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3337 = + !wci_9_busy && !wci_9_reqF_cntr_r; + 4'd10: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3337 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; + 4'd11: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3337 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; + 4'd12: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3337 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; + 4'd13: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3337 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; + 4'd14: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3337 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; + 4'd15: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3337 = 1'd1; + endcase + end + always@(_theResult_____1__h75724 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + wci_9_busy or + wci_9_wReset_n or + wci_9_respF$FULL_N or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) + begin + case (_theResult_____1__h75724) + 4'd0: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3348 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; + 4'd1: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3348 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; + 4'd2: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3348 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; + 4'd3: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3348 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; + 4'd4: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3348 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; + 4'd5: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3348 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; + 4'd6: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3348 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; + 4'd7: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3348 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; + 4'd8: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3348 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; + 4'd9: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3348 = + !wci_9_busy && (wci_9_wReset_n || wci_9_respF$FULL_N); + 4'd10: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3348 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; + 4'd11: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3348 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; + 4'd12: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3348 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; + 4'd13: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3348 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; + 4'd14: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3348 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; + 4'd15: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3348 = 1'd1; + endcase + end + always@(_theResult_____1__h75724 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + wci_10_busy or + wci_10_reqF_cntr_r or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) + begin + case (_theResult_____1__h75724) + 4'd0: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3373 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; + 4'd1: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3373 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; + 4'd2: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3373 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; + 4'd3: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3373 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; + 4'd4: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3373 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; + 4'd5: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3373 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; + 4'd6: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3373 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; + 4'd7: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3373 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; + 4'd8: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3373 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; + 4'd9: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3373 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; + 4'd10: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3373 = + !wci_10_busy && !wci_10_reqF_cntr_r; + 4'd11: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3373 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; + 4'd12: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3373 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; + 4'd13: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3373 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; + 4'd14: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3373 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; + 4'd15: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3373 = 1'd1; + endcase + end + always@(_theResult_____1__h75724 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + wci_10_busy or + wci_10_wReset_n or + wci_10_respF$FULL_N or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) + begin + case (_theResult_____1__h75724) + 4'd0: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3384 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; + 4'd1: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3384 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; + 4'd2: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3384 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; + 4'd3: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3384 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; + 4'd4: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3384 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; + 4'd5: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3384 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; + 4'd6: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3384 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; + 4'd7: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3384 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; + 4'd8: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3384 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; + 4'd9: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3384 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; + 4'd10: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3384 = + !wci_10_busy && (wci_10_wReset_n || wci_10_respF$FULL_N); + 4'd11: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3384 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; + 4'd12: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3384 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; + 4'd13: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3384 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; + 4'd14: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3384 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; + 4'd15: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3384 = 1'd1; + endcase + end + always@(_theResult_____1__h75724 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + wci_11_busy or + wci_11_reqF_cntr_r or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) + begin + case (_theResult_____1__h75724) + 4'd0: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3409 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; + 4'd1: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3409 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; + 4'd2: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3409 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; + 4'd3: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3409 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; + 4'd4: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3409 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; + 4'd5: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3409 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; + 4'd6: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3409 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; + 4'd7: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3409 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; + 4'd8: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3409 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; + 4'd9: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3409 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; + 4'd10: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3409 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; + 4'd11: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3409 = + !wci_11_busy && !wci_11_reqF_cntr_r; + 4'd12: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3409 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; + 4'd13: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3409 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; + 4'd14: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3409 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; + 4'd15: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3409 = 1'd1; + endcase + end + always@(_theResult_____1__h75724 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + wci_11_busy or + wci_11_wReset_n or + wci_11_respF$FULL_N or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) + begin + case (_theResult_____1__h75724) + 4'd0: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3420 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; + 4'd1: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3420 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; + 4'd2: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3420 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; + 4'd3: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3420 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; + 4'd4: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3420 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; + 4'd5: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3420 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; + 4'd6: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3420 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; + 4'd7: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3420 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; + 4'd8: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3420 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; + 4'd9: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3420 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; + 4'd10: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3420 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; + 4'd11: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3420 = + !wci_11_busy && (wci_11_wReset_n || wci_11_respF$FULL_N); + 4'd12: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3420 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; + 4'd13: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3420 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; + 4'd14: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3420 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; + 4'd15: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3420 = 1'd1; + endcase + end + always@(_theResult_____1__h75724 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + wci_12_busy or + wci_12_reqF_cntr_r or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) + begin + case (_theResult_____1__h75724) + 4'd0: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3445 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; + 4'd1: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3445 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; + 4'd2: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3445 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; + 4'd3: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3445 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; + 4'd4: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3445 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; + 4'd5: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3445 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; + 4'd6: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3445 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; + 4'd7: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3445 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; + 4'd8: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3445 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; + 4'd9: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3445 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; + 4'd10: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3445 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; + 4'd11: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3445 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; + 4'd12: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3445 = + !wci_12_busy && !wci_12_reqF_cntr_r; + 4'd13: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3445 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; + 4'd14: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3445 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; + 4'd15: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3445 = 1'd1; + endcase + end + always@(_theResult_____1__h75724 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + wci_12_busy or + wci_12_wReset_n or + wci_12_respF$FULL_N or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) + begin + case (_theResult_____1__h75724) + 4'd0: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3456 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; + 4'd1: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3456 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; + 4'd2: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3456 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; + 4'd3: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3456 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; + 4'd4: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3456 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; + 4'd5: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3456 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; + 4'd6: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3456 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; + 4'd7: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3456 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; + 4'd8: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3456 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; + 4'd9: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3456 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; + 4'd10: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3456 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; + 4'd11: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3456 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; + 4'd12: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3456 = + !wci_12_busy && (wci_12_wReset_n || wci_12_respF$FULL_N); + 4'd13: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3456 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; + 4'd14: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3456 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; + 4'd15: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3456 = 1'd1; + endcase + end + always@(_theResult_____1__h75724 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + wci_13_busy or + wci_13_reqF_cntr_r or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) + begin + case (_theResult_____1__h75724) + 4'd0: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3481 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; + 4'd1: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3481 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; + 4'd2: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3481 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; + 4'd3: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3481 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; + 4'd4: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3481 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; + 4'd5: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3481 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; + 4'd6: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3481 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; + 4'd7: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3481 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; + 4'd8: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3481 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; + 4'd9: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3481 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; + 4'd10: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3481 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; + 4'd11: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3481 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; + 4'd12: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3481 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; + 4'd13: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3481 = + !wci_13_busy && !wci_13_reqF_cntr_r; + 4'd14: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3481 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; + 4'd15: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3481 = 1'd1; + endcase + end + always@(_theResult_____1__h75724 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + wci_13_busy or + wci_13_wReset_n or + wci_13_respF$FULL_N or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) + begin + case (_theResult_____1__h75724) + 4'd0: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3492 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; + 4'd1: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3492 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; + 4'd2: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3492 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; + 4'd3: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3492 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; + 4'd4: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3492 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; + 4'd5: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3492 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; + 4'd6: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3492 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; + 4'd7: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3492 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; + 4'd8: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3492 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; + 4'd9: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3492 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; + 4'd10: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3492 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; + 4'd11: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3492 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; + 4'd12: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3492 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; + 4'd13: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3492 = + !wci_13_busy && (wci_13_wReset_n || wci_13_respF$FULL_N); + 4'd14: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3492 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; + 4'd15: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3492 = 1'd1; + endcase + end + always@(_theResult_____1__h75724 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + wci_14_busy or wci_14_reqF_cntr_r) + begin + case (_theResult_____1__h75724) + 4'd0: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3517 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; + 4'd1: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3517 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; + 4'd2: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3517 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; + 4'd3: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3517 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; + 4'd4: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3517 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; + 4'd5: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3517 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; + 4'd6: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3517 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; + 4'd7: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3517 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; + 4'd8: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3517 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; + 4'd9: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3517 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; + 4'd10: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3517 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; + 4'd11: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3517 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; + 4'd12: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3517 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; + 4'd13: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3517 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; + 4'd14: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3517 = + !wci_14_busy && !wci_14_reqF_cntr_r; + 4'd15: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3517 = 1'd1; + endcase + end + always@(_theResult_____1__h75724 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + wci_14_busy or wci_14_wReset_n or wci_14_respF$FULL_N) + begin + case (_theResult_____1__h75724) + 4'd0: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3528 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; + 4'd1: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3528 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; + 4'd2: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3528 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; + 4'd3: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3528 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; + 4'd4: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3528 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; + 4'd5: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3528 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; + 4'd6: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3528 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; + 4'd7: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3528 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; + 4'd8: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3528 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; + 4'd9: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3528 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; + 4'd10: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3528 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; + 4'd11: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3528 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; + 4'd12: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3528 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; + 4'd13: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3528 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; + 4'd14: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3528 = + !wci_14_busy && (wci_14_wReset_n || wci_14_respF$FULL_N); + 4'd15: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3528 = 1'd1; + endcase + end + always@(_theResult_____1__h75724 or + wci_0_busy or + cpReq or + wci_0_wReset_n or + wci_0_respF$FULL_N or + IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_THEN_N_ETC___d3580 or + wci_1_busy or + wci_1_wReset_n or + wci_1_respF$FULL_N or + IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_THEN_N_ETC___d3584 or + wci_2_busy or + wci_2_wReset_n or + wci_2_respF$FULL_N or + IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_THEN_N_ETC___d3588 or + wci_3_busy or + wci_3_wReset_n or + wci_3_respF$FULL_N or + IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_THEN_N_ETC___d3592 or + wci_4_busy or + wci_4_wReset_n or + wci_4_respF$FULL_N or + IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_THEN_N_ETC___d3596 or + wci_5_busy or + wci_5_wReset_n or + wci_5_respF$FULL_N or + IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_THEN_N_ETC___d3600 or + wci_6_busy or + wci_6_wReset_n or + wci_6_respF$FULL_N or + IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_THEN_N_ETC___d3604 or + wci_7_busy or + wci_7_wReset_n or + wci_7_respF$FULL_N or + IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_THEN_N_ETC___d3608 or + wci_8_busy or + wci_8_wReset_n or + wci_8_respF$FULL_N or + IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_THEN_N_ETC___d3612 or + wci_9_busy or + wci_9_wReset_n or + wci_9_respF$FULL_N or + IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_THEN_N_ETC___d3616 or + wci_10_busy or + wci_10_wReset_n or + wci_10_respF$FULL_N or + IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_THEN_N_ETC___d3620 or + wci_11_busy or + wci_11_wReset_n or + wci_11_respF$FULL_N or + IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_THEN_N_ETC___d3624 or + wci_12_busy or + wci_12_wReset_n or + wci_12_respF$FULL_N or + IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_THEN_N_ETC___d3628 or + wci_13_busy or + wci_13_wReset_n or + wci_13_respF$FULL_N or + IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_THEN_N_ETC___d3632 or + wci_14_busy or + wci_14_wReset_n or + wci_14_respF$FULL_N or + IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_THEN_N_ETC___d3636) + begin + case (_theResult_____1__h75724) + 4'd0: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3639 = + !wci_0_busy && + (cpReq[61:60] != 2'd2 || wci_0_wReset_n || + wci_0_respF$FULL_N) && + IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_THEN_N_ETC___d3580; + 4'd1: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3639 = + !wci_1_busy && + (cpReq[61:60] != 2'd2 || wci_1_wReset_n || + wci_1_respF$FULL_N) && + IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_THEN_N_ETC___d3584; + 4'd2: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3639 = + !wci_2_busy && + (cpReq[61:60] != 2'd2 || wci_2_wReset_n || + wci_2_respF$FULL_N) && + IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_THEN_N_ETC___d3588; + 4'd3: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3639 = + !wci_3_busy && + (cpReq[61:60] != 2'd2 || wci_3_wReset_n || + wci_3_respF$FULL_N) && + IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_THEN_N_ETC___d3592; + 4'd4: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3639 = + !wci_4_busy && + (cpReq[61:60] != 2'd2 || wci_4_wReset_n || + wci_4_respF$FULL_N) && + IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_THEN_N_ETC___d3596; + 4'd5: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3639 = + !wci_5_busy && + (cpReq[61:60] != 2'd2 || wci_5_wReset_n || + wci_5_respF$FULL_N) && + IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_THEN_N_ETC___d3600; + 4'd6: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3639 = + !wci_6_busy && + (cpReq[61:60] != 2'd2 || wci_6_wReset_n || + wci_6_respF$FULL_N) && + IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_THEN_N_ETC___d3604; + 4'd7: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3639 = + !wci_7_busy && + (cpReq[61:60] != 2'd2 || wci_7_wReset_n || + wci_7_respF$FULL_N) && + IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_THEN_N_ETC___d3608; + 4'd8: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3639 = + !wci_8_busy && + (cpReq[61:60] != 2'd2 || wci_8_wReset_n || + wci_8_respF$FULL_N) && + IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_THEN_N_ETC___d3612; + 4'd9: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3639 = + !wci_9_busy && + (cpReq[61:60] != 2'd2 || wci_9_wReset_n || + wci_9_respF$FULL_N) && + IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_THEN_N_ETC___d3616; + 4'd10: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3639 = + !wci_10_busy && + (cpReq[61:60] != 2'd2 || wci_10_wReset_n || + wci_10_respF$FULL_N) && + IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_THEN_N_ETC___d3620; + 4'd11: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3639 = + !wci_11_busy && + (cpReq[61:60] != 2'd2 || wci_11_wReset_n || + wci_11_respF$FULL_N) && + IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_THEN_N_ETC___d3624; + 4'd12: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3639 = + !wci_12_busy && + (cpReq[61:60] != 2'd2 || wci_12_wReset_n || + wci_12_respF$FULL_N) && + IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_THEN_N_ETC___d3628; + 4'd13: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3639 = + !wci_13_busy && + (cpReq[61:60] != 2'd2 || wci_13_wReset_n || + wci_13_respF$FULL_N) && + IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_THEN_N_ETC___d3632; + 4'd14: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3639 = + !wci_14_busy && + (cpReq[61:60] != 2'd2 || wci_14_wReset_n || + wci_14_respF$FULL_N) && + IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_THEN_N_ETC___d3636; + 4'd15: + CASE_IF_cpReq_363_BITS_61_TO_60_848_EQ_2_849_T_ETC___d3639 = 1'd1; + endcase + end + always@(_theResult_____1__h75739 or + wci_0_busy or + wci_0_reqF_cntr_r or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) + begin + case (_theResult_____1__h75739) + 4'd0: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3681 = + !wci_0_busy && !wci_0_reqF_cntr_r; + 4'd1: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3681 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; + 4'd2: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3681 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; + 4'd3: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3681 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; + 4'd4: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3681 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; + 4'd5: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3681 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; + 4'd6: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3681 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; + 4'd7: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3681 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; + 4'd8: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3681 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; + 4'd9: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3681 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; + 4'd10: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3681 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; + 4'd11: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3681 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; + 4'd12: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3681 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; + 4'd13: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3681 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; + 4'd14: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3681 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; + 4'd15: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3681 = 1'd1; + endcase + end + always@(_theResult_____1__h75739 or + wci_0_busy or + wci_0_wReset_n or + wci_0_respF$FULL_N or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) + begin + case (_theResult_____1__h75739) + 4'd0: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3694 = + !wci_0_busy && (wci_0_wReset_n || wci_0_respF$FULL_N); + 4'd1: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3694 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; + 4'd2: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3694 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; + 4'd3: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3694 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; + 4'd4: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3694 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; + 4'd5: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3694 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; + 4'd6: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3694 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; + 4'd7: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3694 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; + 4'd8: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3694 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; + 4'd9: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3694 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; + 4'd10: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3694 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; + 4'd11: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3694 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; + 4'd12: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3694 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; + 4'd13: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3694 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; + 4'd14: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3694 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; + 4'd15: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3694 = 1'd1; + endcase + end + always@(_theResult_____1__h75739 or + wci_0_busy or + wci_0_reqF_cntr_r or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) + begin + case (_theResult_____1__h75739) + 4'd0: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3735 = + !wci_0_busy && !wci_0_reqF_cntr_r; + 4'd1: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3735 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; + 4'd2: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3735 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; + 4'd3: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3735 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; + 4'd4: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3735 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; + 4'd5: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3735 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; + 4'd6: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3735 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; + 4'd7: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3735 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; + 4'd8: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3735 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; + 4'd9: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3735 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; + 4'd10: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3735 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; + 4'd11: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3735 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; + 4'd12: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3735 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; + 4'd13: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3735 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; + 4'd14: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3735 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; + 4'd15: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3735 = 1'd1; + endcase + end + always@(_theResult_____1__h75739 or + wci_0_busy or + wci_0_wReset_n or + wci_0_respF$FULL_N or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) + begin + case (_theResult_____1__h75739) + 4'd0: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3750 = + !wci_0_busy && (wci_0_wReset_n || wci_0_respF$FULL_N); + 4'd1: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3750 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; + 4'd2: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3750 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; + 4'd3: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3750 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; + 4'd4: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3750 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; + 4'd5: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3750 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; + 4'd6: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3750 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; + 4'd7: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3750 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; + 4'd8: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3750 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; + 4'd9: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3750 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; + 4'd10: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3750 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; + 4'd11: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3750 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; + 4'd12: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3750 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; + 4'd13: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3750 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; + 4'd14: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3750 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; + 4'd15: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3750 = 1'd1; + endcase + end + always@(_theResult_____1__h75739 or + wci_0_busy or + wci_0_respF$FULL_N or + wci_1_busy or + wci_1_respF$FULL_N or + wci_2_busy or + wci_2_respF$FULL_N or + wci_3_busy or + wci_3_respF$FULL_N or + wci_4_busy or + wci_4_respF$FULL_N or + wci_5_busy or + wci_5_respF$FULL_N or + wci_6_busy or + wci_6_respF$FULL_N or + wci_7_busy or + wci_7_respF$FULL_N or + wci_8_busy or + wci_8_respF$FULL_N or + wci_9_busy or + wci_9_respF$FULL_N or + wci_10_busy or + wci_10_respF$FULL_N or + wci_11_busy or + wci_11_respF$FULL_N or + wci_12_busy or + wci_12_respF$FULL_N or + wci_13_busy or + wci_13_respF$FULL_N or wci_14_busy or wci_14_respF$FULL_N) + begin + case (_theResult_____1__h75739) + 4'd0: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793 = + !wci_0_busy && wci_0_respF$FULL_N; + 4'd1: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793 = + !wci_1_busy && wci_1_respF$FULL_N; + 4'd2: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793 = + !wci_2_busy && wci_2_respF$FULL_N; + 4'd3: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793 = + !wci_3_busy && wci_3_respF$FULL_N; + 4'd4: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793 = + !wci_4_busy && wci_4_respF$FULL_N; + 4'd5: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793 = + !wci_5_busy && wci_5_respF$FULL_N; + 4'd6: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793 = + !wci_6_busy && wci_6_respF$FULL_N; + 4'd7: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793 = + !wci_7_busy && wci_7_respF$FULL_N; + 4'd8: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793 = + !wci_8_busy && wci_8_respF$FULL_N; + 4'd9: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793 = + !wci_9_busy && wci_9_respF$FULL_N; + 4'd10: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793 = + !wci_10_busy && wci_10_respF$FULL_N; + 4'd11: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793 = + !wci_11_busy && wci_11_respF$FULL_N; + 4'd12: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793 = + !wci_12_busy && wci_12_respF$FULL_N; + 4'd13: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793 = + !wci_13_busy && wci_13_respF$FULL_N; + 4'd14: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793 = + !wci_14_busy && wci_14_respF$FULL_N; + 4'd15: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3793 = 1'd1; + endcase + end + always@(_theResult_____1__h75739 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + wci_1_busy or + wci_1_reqF_cntr_r or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) + begin + case (_theResult_____1__h75739) + 4'd0: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3851 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; + 4'd1: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3851 = + !wci_1_busy && !wci_1_reqF_cntr_r; + 4'd2: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3851 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; + 4'd3: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3851 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; + 4'd4: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3851 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; + 4'd5: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3851 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; + 4'd6: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3851 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; + 4'd7: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3851 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; + 4'd8: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3851 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; + 4'd9: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3851 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; + 4'd10: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3851 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; + 4'd11: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3851 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; + 4'd12: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3851 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; + 4'd13: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3851 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; + 4'd14: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3851 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; + 4'd15: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3851 = 1'd1; + endcase + end + always@(_theResult_____1__h75739 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + wci_1_busy or + wci_1_wReset_n or + wci_1_respF$FULL_N or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) + begin + case (_theResult_____1__h75739) + 4'd0: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3863 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; + 4'd1: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3863 = + !wci_1_busy && (wci_1_wReset_n || wci_1_respF$FULL_N); + 4'd2: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3863 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; + 4'd3: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3863 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; + 4'd4: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3863 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; + 4'd5: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3863 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; + 4'd6: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3863 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; + 4'd7: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3863 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; + 4'd8: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3863 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; + 4'd9: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3863 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; + 4'd10: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3863 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; + 4'd11: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3863 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; + 4'd12: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3863 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; + 4'd13: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3863 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; + 4'd14: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3863 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; + 4'd15: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3863 = 1'd1; + endcase + end + always@(_theResult_____1__h75739 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + wci_1_busy or + wci_1_reqF_cntr_r or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) + begin + case (_theResult_____1__h75739) + 4'd0: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3876 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; + 4'd1: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3876 = + !wci_1_busy && !wci_1_reqF_cntr_r; + 4'd2: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3876 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; + 4'd3: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3876 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; + 4'd4: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3876 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; + 4'd5: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3876 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; + 4'd6: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3876 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; + 4'd7: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3876 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; + 4'd8: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3876 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; + 4'd9: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3876 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; + 4'd10: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3876 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; + 4'd11: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3876 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; + 4'd12: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3876 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; + 4'd13: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3876 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; + 4'd14: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3876 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; + 4'd15: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3876 = 1'd1; + endcase + end + always@(_theResult_____1__h75739 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + wci_1_busy or + wci_1_wReset_n or + wci_1_respF$FULL_N or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) + begin + case (_theResult_____1__h75739) + 4'd0: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3886 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; + 4'd1: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3886 = + !wci_1_busy && (wci_1_wReset_n || wci_1_respF$FULL_N); + 4'd2: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3886 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; + 4'd3: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3886 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; + 4'd4: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3886 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; + 4'd5: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3886 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; + 4'd6: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3886 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; + 4'd7: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3886 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; + 4'd8: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3886 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; + 4'd9: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3886 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; + 4'd10: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3886 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; + 4'd11: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3886 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; + 4'd12: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3886 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; + 4'd13: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3886 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; + 4'd14: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3886 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; + 4'd15: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3886 = 1'd1; + endcase + end + always@(_theResult_____1__h75739 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + wci_2_busy or + wci_2_reqF_cntr_r or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) + begin + case (_theResult_____1__h75739) + 4'd0: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3928 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; + 4'd1: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3928 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; + 4'd2: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3928 = + !wci_2_busy && !wci_2_reqF_cntr_r; + 4'd3: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3928 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; + 4'd4: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3928 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; + 4'd5: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3928 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; + 4'd6: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3928 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; + 4'd7: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3928 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; + 4'd8: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3928 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; + 4'd9: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3928 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; + 4'd10: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3928 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; + 4'd11: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3928 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; + 4'd12: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3928 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; + 4'd13: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3928 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; + 4'd14: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3928 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; + 4'd15: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3928 = 1'd1; + endcase + end + always@(_theResult_____1__h75739 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + wci_2_busy or + wci_2_wReset_n or + wci_2_respF$FULL_N or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) + begin + case (_theResult_____1__h75739) + 4'd0: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3940 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; + 4'd1: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3940 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; + 4'd2: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3940 = + !wci_2_busy && (wci_2_wReset_n || wci_2_respF$FULL_N); + 4'd3: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3940 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; + 4'd4: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3940 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; + 4'd5: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3940 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; + 4'd6: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3940 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; + 4'd7: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3940 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; + 4'd8: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3940 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; + 4'd9: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3940 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; + 4'd10: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3940 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; + 4'd11: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3940 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; + 4'd12: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3940 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; + 4'd13: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3940 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; + 4'd14: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3940 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; + 4'd15: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3940 = 1'd1; + endcase + end + always@(_theResult_____1__h75739 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + wci_2_busy or + wci_2_reqF_cntr_r or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) + begin + case (_theResult_____1__h75739) + 4'd0: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3951 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; + 4'd1: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3951 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; + 4'd2: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3951 = + !wci_2_busy && !wci_2_reqF_cntr_r; + 4'd3: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3951 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; + 4'd4: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3951 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; + 4'd5: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3951 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; + 4'd6: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3951 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; + 4'd7: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3951 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; + 4'd8: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3951 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; + 4'd9: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3951 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; + 4'd10: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3951 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; + 4'd11: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3951 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; + 4'd12: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3951 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; + 4'd13: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3951 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; + 4'd14: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3951 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; + 4'd15: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3951 = 1'd1; + endcase + end + always@(_theResult_____1__h75739 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + wci_2_busy or + wci_2_wReset_n or + wci_2_respF$FULL_N or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) + begin + case (_theResult_____1__h75739) + 4'd0: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3961 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; + 4'd1: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3961 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; + 4'd2: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3961 = + !wci_2_busy && (wci_2_wReset_n || wci_2_respF$FULL_N); + 4'd3: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3961 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; + 4'd4: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3961 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; + 4'd5: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3961 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; + 4'd6: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3961 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; + 4'd7: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3961 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; + 4'd8: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3961 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; + 4'd9: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3961 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; + 4'd10: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3961 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; + 4'd11: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3961 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; + 4'd12: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3961 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; + 4'd13: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3961 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; + 4'd14: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3961 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; + 4'd15: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d3961 = 1'd1; + endcase + end + always@(_theResult_____1__h75739 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + wci_3_busy or + wci_3_reqF_cntr_r or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) + begin + case (_theResult_____1__h75739) + 4'd0: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4003 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; + 4'd1: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4003 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; + 4'd2: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4003 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; + 4'd3: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4003 = + !wci_3_busy && !wci_3_reqF_cntr_r; + 4'd4: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4003 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; + 4'd5: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4003 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; + 4'd6: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4003 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; + 4'd7: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4003 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; + 4'd8: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4003 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; + 4'd9: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4003 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; + 4'd10: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4003 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; + 4'd11: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4003 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; + 4'd12: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4003 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; + 4'd13: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4003 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; + 4'd14: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4003 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; + 4'd15: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4003 = 1'd1; + endcase + end + always@(_theResult_____1__h75739 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + wci_3_busy or + wci_3_wReset_n or + wci_3_respF$FULL_N or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) + begin + case (_theResult_____1__h75739) + 4'd0: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4015 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; + 4'd1: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4015 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; + 4'd2: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4015 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; + 4'd3: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4015 = + !wci_3_busy && (wci_3_wReset_n || wci_3_respF$FULL_N); + 4'd4: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4015 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; + 4'd5: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4015 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; + 4'd6: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4015 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; + 4'd7: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4015 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; + 4'd8: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4015 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; + 4'd9: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4015 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; + 4'd10: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4015 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; + 4'd11: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4015 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; + 4'd12: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4015 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; + 4'd13: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4015 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; + 4'd14: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4015 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; + 4'd15: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4015 = 1'd1; + endcase + end + always@(_theResult_____1__h75739 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + wci_3_busy or + wci_3_reqF_cntr_r or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) + begin + case (_theResult_____1__h75739) + 4'd0: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4026 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; + 4'd1: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4026 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; + 4'd2: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4026 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; + 4'd3: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4026 = + !wci_3_busy && !wci_3_reqF_cntr_r; + 4'd4: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4026 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; + 4'd5: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4026 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; + 4'd6: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4026 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; + 4'd7: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4026 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; + 4'd8: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4026 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; + 4'd9: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4026 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; + 4'd10: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4026 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; + 4'd11: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4026 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; + 4'd12: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4026 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; + 4'd13: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4026 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; + 4'd14: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4026 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; + 4'd15: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4026 = 1'd1; + endcase + end + always@(_theResult_____1__h75739 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + wci_3_busy or + wci_3_wReset_n or + wci_3_respF$FULL_N or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) + begin + case (_theResult_____1__h75739) + 4'd0: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4036 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; + 4'd1: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4036 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; + 4'd2: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4036 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; + 4'd3: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4036 = + !wci_3_busy && (wci_3_wReset_n || wci_3_respF$FULL_N); + 4'd4: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4036 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; + 4'd5: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4036 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; + 4'd6: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4036 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; + 4'd7: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4036 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; + 4'd8: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4036 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; + 4'd9: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4036 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; + 4'd10: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4036 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; + 4'd11: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4036 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; + 4'd12: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4036 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; + 4'd13: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4036 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; + 4'd14: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4036 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; + 4'd15: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4036 = 1'd1; + endcase + end + always@(_theResult_____1__h75739 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + wci_4_busy or + wci_4_reqF_cntr_r or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) + begin + case (_theResult_____1__h75739) + 4'd0: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4078 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; + 4'd1: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4078 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; + 4'd2: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4078 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; + 4'd3: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4078 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; + 4'd4: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4078 = + !wci_4_busy && !wci_4_reqF_cntr_r; + 4'd5: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4078 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; + 4'd6: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4078 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; + 4'd7: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4078 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; + 4'd8: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4078 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; + 4'd9: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4078 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; + 4'd10: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4078 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; + 4'd11: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4078 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; + 4'd12: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4078 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; + 4'd13: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4078 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; + 4'd14: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4078 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; + 4'd15: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4078 = 1'd1; + endcase + end + always@(_theResult_____1__h75739 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + wci_4_busy or + wci_4_wReset_n or + wci_4_respF$FULL_N or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) + begin + case (_theResult_____1__h75739) + 4'd0: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4090 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; + 4'd1: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4090 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; + 4'd2: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4090 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; + 4'd3: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4090 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; + 4'd4: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4090 = + !wci_4_busy && (wci_4_wReset_n || wci_4_respF$FULL_N); + 4'd5: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4090 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; + 4'd6: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4090 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; + 4'd7: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4090 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; + 4'd8: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4090 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; + 4'd9: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4090 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; + 4'd10: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4090 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; + 4'd11: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4090 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; + 4'd12: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4090 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; + 4'd13: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4090 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; + 4'd14: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4090 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; + 4'd15: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4090 = 1'd1; + endcase + end + always@(_theResult_____1__h75739 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + wci_4_busy or + wci_4_reqF_cntr_r or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) + begin + case (_theResult_____1__h75739) + 4'd0: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4101 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; + 4'd1: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4101 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; + 4'd2: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4101 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; + 4'd3: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4101 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; + 4'd4: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4101 = + !wci_4_busy && !wci_4_reqF_cntr_r; + 4'd5: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4101 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; + 4'd6: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4101 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; + 4'd7: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4101 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; + 4'd8: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4101 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; + 4'd9: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4101 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; + 4'd10: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4101 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; + 4'd11: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4101 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; + 4'd12: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4101 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; + 4'd13: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4101 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; + 4'd14: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4101 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; + 4'd15: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4101 = 1'd1; + endcase + end + always@(_theResult_____1__h75739 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + wci_4_busy or + wci_4_wReset_n or + wci_4_respF$FULL_N or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) + begin + case (_theResult_____1__h75739) + 4'd0: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4111 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; + 4'd1: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4111 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; + 4'd2: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4111 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; + 4'd3: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4111 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; + 4'd4: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4111 = + !wci_4_busy && (wci_4_wReset_n || wci_4_respF$FULL_N); + 4'd5: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4111 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; + 4'd6: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4111 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; + 4'd7: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4111 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; + 4'd8: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4111 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; + 4'd9: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4111 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; + 4'd10: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4111 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; + 4'd11: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4111 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; + 4'd12: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4111 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; + 4'd13: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4111 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; + 4'd14: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4111 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; + 4'd15: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4111 = 1'd1; + endcase + end + always@(_theResult_____1__h75739 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + wci_5_busy or + wci_5_reqF_cntr_r or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) + begin + case (_theResult_____1__h75739) + 4'd0: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4153 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; + 4'd1: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4153 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; + 4'd2: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4153 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; + 4'd3: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4153 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; + 4'd4: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4153 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; + 4'd5: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4153 = + !wci_5_busy && !wci_5_reqF_cntr_r; + 4'd6: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4153 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; + 4'd7: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4153 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; + 4'd8: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4153 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; + 4'd9: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4153 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; + 4'd10: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4153 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; + 4'd11: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4153 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; + 4'd12: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4153 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; + 4'd13: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4153 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; + 4'd14: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4153 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; + 4'd15: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4153 = 1'd1; + endcase + end + always@(_theResult_____1__h75739 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + wci_5_busy or + wci_5_wReset_n or + wci_5_respF$FULL_N or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) + begin + case (_theResult_____1__h75739) + 4'd0: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4165 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; + 4'd1: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4165 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; + 4'd2: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4165 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; + 4'd3: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4165 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; + 4'd4: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4165 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; + 4'd5: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4165 = + !wci_5_busy && (wci_5_wReset_n || wci_5_respF$FULL_N); + 4'd6: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4165 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; + 4'd7: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4165 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; + 4'd8: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4165 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; + 4'd9: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4165 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; + 4'd10: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4165 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; + 4'd11: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4165 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; + 4'd12: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4165 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; + 4'd13: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4165 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; + 4'd14: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4165 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; + 4'd15: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4165 = 1'd1; + endcase + end + always@(_theResult_____1__h75739 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + wci_5_busy or + wci_5_reqF_cntr_r or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) + begin + case (_theResult_____1__h75739) + 4'd0: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4176 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; + 4'd1: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4176 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; + 4'd2: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4176 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; + 4'd3: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4176 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; + 4'd4: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4176 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; + 4'd5: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4176 = + !wci_5_busy && !wci_5_reqF_cntr_r; + 4'd6: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4176 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; + 4'd7: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4176 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; + 4'd8: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4176 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; + 4'd9: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4176 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; + 4'd10: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4176 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; + 4'd11: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4176 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; + 4'd12: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4176 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; + 4'd13: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4176 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; + 4'd14: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4176 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; + 4'd15: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4176 = 1'd1; + endcase + end + always@(_theResult_____1__h75739 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + wci_5_busy or + wci_5_wReset_n or + wci_5_respF$FULL_N or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) + begin + case (_theResult_____1__h75739) + 4'd0: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4186 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; + 4'd1: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4186 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; + 4'd2: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4186 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; + 4'd3: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4186 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; + 4'd4: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4186 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; + 4'd5: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4186 = + !wci_5_busy && (wci_5_wReset_n || wci_5_respF$FULL_N); + 4'd6: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4186 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; + 4'd7: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4186 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; + 4'd8: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4186 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; + 4'd9: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4186 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; + 4'd10: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4186 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; + 4'd11: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4186 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; + 4'd12: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4186 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; + 4'd13: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4186 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; + 4'd14: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4186 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; + 4'd15: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4186 = 1'd1; + endcase + end + always@(_theResult_____1__h75739 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + wci_6_busy or + wci_6_reqF_cntr_r or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) + begin + case (_theResult_____1__h75739) + 4'd0: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4228 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; + 4'd1: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4228 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; + 4'd2: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4228 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; + 4'd3: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4228 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; + 4'd4: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4228 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; + 4'd5: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4228 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; + 4'd6: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4228 = + !wci_6_busy && !wci_6_reqF_cntr_r; + 4'd7: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4228 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; + 4'd8: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4228 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; + 4'd9: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4228 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; + 4'd10: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4228 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; + 4'd11: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4228 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; + 4'd12: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4228 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; + 4'd13: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4228 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; + 4'd14: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4228 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; + 4'd15: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4228 = 1'd1; + endcase + end + always@(_theResult_____1__h75739 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + wci_6_busy or + wci_6_wReset_n or + wci_6_respF$FULL_N or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) + begin + case (_theResult_____1__h75739) + 4'd0: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4240 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; + 4'd1: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4240 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; + 4'd2: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4240 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; + 4'd3: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4240 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; + 4'd4: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4240 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; + 4'd5: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4240 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; + 4'd6: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4240 = + !wci_6_busy && (wci_6_wReset_n || wci_6_respF$FULL_N); + 4'd7: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4240 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; + 4'd8: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4240 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; + 4'd9: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4240 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; + 4'd10: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4240 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; + 4'd11: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4240 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; + 4'd12: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4240 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; + 4'd13: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4240 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; + 4'd14: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4240 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; + 4'd15: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4240 = 1'd1; + endcase + end + always@(_theResult_____1__h75739 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + wci_6_busy or + wci_6_reqF_cntr_r or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) + begin + case (_theResult_____1__h75739) + 4'd0: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4251 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; + 4'd1: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4251 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; + 4'd2: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4251 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; + 4'd3: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4251 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; + 4'd4: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4251 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; + 4'd5: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4251 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; + 4'd6: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4251 = + !wci_6_busy && !wci_6_reqF_cntr_r; + 4'd7: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4251 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; + 4'd8: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4251 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; + 4'd9: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4251 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; + 4'd10: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4251 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; + 4'd11: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4251 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; + 4'd12: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4251 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; + 4'd13: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4251 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; + 4'd14: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4251 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; + 4'd15: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4251 = 1'd1; + endcase + end + always@(_theResult_____1__h75739 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + wci_6_busy or + wci_6_wReset_n or + wci_6_respF$FULL_N or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) + begin + case (_theResult_____1__h75739) + 4'd0: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4261 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; + 4'd1: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4261 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; + 4'd2: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4261 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; + 4'd3: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4261 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; + 4'd4: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4261 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; + 4'd5: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4261 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; + 4'd6: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4261 = + !wci_6_busy && (wci_6_wReset_n || wci_6_respF$FULL_N); + 4'd7: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4261 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; + 4'd8: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4261 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; + 4'd9: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4261 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; + 4'd10: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4261 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; + 4'd11: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4261 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; + 4'd12: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4261 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; + 4'd13: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4261 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; + 4'd14: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4261 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; + 4'd15: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4261 = 1'd1; + endcase + end + always@(_theResult_____1__h75739 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + wci_7_busy or + wci_7_reqF_cntr_r or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) + begin + case (_theResult_____1__h75739) + 4'd0: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4303 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; + 4'd1: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4303 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; + 4'd2: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4303 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; + 4'd3: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4303 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; + 4'd4: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4303 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; + 4'd5: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4303 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; + 4'd6: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4303 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; + 4'd7: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4303 = + !wci_7_busy && !wci_7_reqF_cntr_r; + 4'd8: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4303 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; + 4'd9: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4303 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; + 4'd10: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4303 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; + 4'd11: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4303 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; + 4'd12: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4303 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; + 4'd13: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4303 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; + 4'd14: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4303 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; + 4'd15: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4303 = 1'd1; + endcase + end + always@(_theResult_____1__h75739 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + wci_7_busy or + wci_7_wReset_n or + wci_7_respF$FULL_N or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) + begin + case (_theResult_____1__h75739) + 4'd0: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4315 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; + 4'd1: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4315 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; + 4'd2: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4315 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; + 4'd3: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4315 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; + 4'd4: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4315 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; + 4'd5: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4315 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; + 4'd6: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4315 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; + 4'd7: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4315 = + !wci_7_busy && (wci_7_wReset_n || wci_7_respF$FULL_N); + 4'd8: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4315 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; + 4'd9: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4315 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; + 4'd10: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4315 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; + 4'd11: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4315 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; + 4'd12: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4315 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; + 4'd13: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4315 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; + 4'd14: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4315 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; + 4'd15: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4315 = 1'd1; + endcase + end + always@(_theResult_____1__h75739 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + wci_7_busy or + wci_7_reqF_cntr_r or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) + begin + case (_theResult_____1__h75739) + 4'd0: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4326 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; + 4'd1: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4326 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; + 4'd2: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4326 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; + 4'd3: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4326 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; + 4'd4: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4326 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; + 4'd5: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4326 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; + 4'd6: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4326 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; + 4'd7: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4326 = + !wci_7_busy && !wci_7_reqF_cntr_r; + 4'd8: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4326 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; + 4'd9: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4326 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; + 4'd10: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4326 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; + 4'd11: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4326 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; + 4'd12: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4326 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; + 4'd13: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4326 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; + 4'd14: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4326 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; + 4'd15: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4326 = 1'd1; + endcase + end + always@(_theResult_____1__h75739 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + wci_7_busy or + wci_7_wReset_n or + wci_7_respF$FULL_N or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) + begin + case (_theResult_____1__h75739) + 4'd0: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4336 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; + 4'd1: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4336 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; + 4'd2: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4336 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; + 4'd3: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4336 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; + 4'd4: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4336 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; + 4'd5: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4336 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; + 4'd6: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4336 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; + 4'd7: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4336 = + !wci_7_busy && (wci_7_wReset_n || wci_7_respF$FULL_N); + 4'd8: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4336 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; + 4'd9: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4336 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; + 4'd10: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4336 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; + 4'd11: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4336 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; + 4'd12: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4336 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; + 4'd13: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4336 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; + 4'd14: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4336 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; + 4'd15: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4336 = 1'd1; + endcase + end + always@(_theResult_____1__h75739 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + wci_8_busy or + wci_8_reqF_cntr_r or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) + begin + case (_theResult_____1__h75739) + 4'd0: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4378 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; + 4'd1: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4378 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; + 4'd2: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4378 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; + 4'd3: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4378 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; + 4'd4: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4378 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; + 4'd5: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4378 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; + 4'd6: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4378 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; + 4'd7: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4378 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; + 4'd8: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4378 = + !wci_8_busy && !wci_8_reqF_cntr_r; + 4'd9: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4378 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; + 4'd10: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4378 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; + 4'd11: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4378 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; + 4'd12: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4378 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; + 4'd13: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4378 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; + 4'd14: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4378 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; + 4'd15: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4378 = 1'd1; + endcase + end + always@(_theResult_____1__h75739 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + wci_8_busy or + wci_8_wReset_n or + wci_8_respF$FULL_N or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) + begin + case (_theResult_____1__h75739) + 4'd0: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4390 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; + 4'd1: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4390 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; + 4'd2: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4390 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; + 4'd3: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4390 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; + 4'd4: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4390 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; + 4'd5: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4390 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; + 4'd6: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4390 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; + 4'd7: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4390 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; + 4'd8: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4390 = + !wci_8_busy && (wci_8_wReset_n || wci_8_respF$FULL_N); + 4'd9: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4390 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; + 4'd10: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4390 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; + 4'd11: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4390 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; + 4'd12: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4390 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; + 4'd13: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4390 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; + 4'd14: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4390 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; + 4'd15: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4390 = 1'd1; + endcase + end + always@(_theResult_____1__h75739 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + wci_8_busy or + wci_8_reqF_cntr_r or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) + begin + case (_theResult_____1__h75739) + 4'd0: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4401 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; + 4'd1: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4401 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; + 4'd2: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4401 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; + 4'd3: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4401 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; + 4'd4: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4401 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; + 4'd5: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4401 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; + 4'd6: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4401 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; + 4'd7: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4401 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; + 4'd8: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4401 = + !wci_8_busy && !wci_8_reqF_cntr_r; + 4'd9: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4401 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; + 4'd10: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4401 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; + 4'd11: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4401 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; + 4'd12: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4401 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; + 4'd13: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4401 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; + 4'd14: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4401 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; + 4'd15: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4401 = 1'd1; + endcase + end + always@(_theResult_____1__h75739 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + wci_8_busy or + wci_8_wReset_n or + wci_8_respF$FULL_N or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) + begin + case (_theResult_____1__h75739) + 4'd0: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4411 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; + 4'd1: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4411 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; + 4'd2: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4411 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; + 4'd3: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4411 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; + 4'd4: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4411 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; + 4'd5: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4411 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; + 4'd6: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4411 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; + 4'd7: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4411 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; + 4'd8: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4411 = + !wci_8_busy && (wci_8_wReset_n || wci_8_respF$FULL_N); + 4'd9: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4411 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; + 4'd10: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4411 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; + 4'd11: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4411 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; + 4'd12: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4411 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; + 4'd13: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4411 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; + 4'd14: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4411 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; + 4'd15: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4411 = 1'd1; + endcase + end + always@(_theResult_____1__h75739 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + wci_9_busy or + wci_9_reqF_cntr_r or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) + begin + case (_theResult_____1__h75739) + 4'd0: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4453 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; + 4'd1: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4453 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; + 4'd2: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4453 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; + 4'd3: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4453 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; + 4'd4: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4453 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; + 4'd5: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4453 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; + 4'd6: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4453 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; + 4'd7: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4453 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; + 4'd8: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4453 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; + 4'd9: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4453 = + !wci_9_busy && !wci_9_reqF_cntr_r; + 4'd10: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4453 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; + 4'd11: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4453 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; + 4'd12: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4453 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; + 4'd13: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4453 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; + 4'd14: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4453 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; + 4'd15: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4453 = 1'd1; + endcase + end + always@(_theResult_____1__h75739 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + wci_9_busy or + wci_9_wReset_n or + wci_9_respF$FULL_N or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) + begin + case (_theResult_____1__h75739) + 4'd0: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4465 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; + 4'd1: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4465 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; + 4'd2: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4465 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; + 4'd3: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4465 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; + 4'd4: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4465 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; + 4'd5: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4465 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; + 4'd6: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4465 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; + 4'd7: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4465 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; + 4'd8: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4465 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; + 4'd9: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4465 = + !wci_9_busy && (wci_9_wReset_n || wci_9_respF$FULL_N); + 4'd10: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4465 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; + 4'd11: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4465 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; + 4'd12: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4465 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; + 4'd13: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4465 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; + 4'd14: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4465 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; + 4'd15: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4465 = 1'd1; + endcase + end + always@(_theResult_____1__h75739 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + wci_9_busy or + wci_9_reqF_cntr_r or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) + begin + case (_theResult_____1__h75739) + 4'd0: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4476 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; + 4'd1: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4476 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; + 4'd2: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4476 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; + 4'd3: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4476 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; + 4'd4: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4476 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; + 4'd5: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4476 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; + 4'd6: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4476 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; + 4'd7: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4476 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; + 4'd8: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4476 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; + 4'd9: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4476 = + !wci_9_busy && !wci_9_reqF_cntr_r; + 4'd10: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4476 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; + 4'd11: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4476 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; + 4'd12: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4476 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; + 4'd13: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4476 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; + 4'd14: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4476 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; + 4'd15: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4476 = 1'd1; + endcase + end + always@(_theResult_____1__h75739 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + wci_9_busy or + wci_9_wReset_n or + wci_9_respF$FULL_N or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) + begin + case (_theResult_____1__h75739) + 4'd0: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4486 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; + 4'd1: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4486 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; + 4'd2: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4486 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; + 4'd3: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4486 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; + 4'd4: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4486 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; + 4'd5: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4486 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; + 4'd6: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4486 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; + 4'd7: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4486 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; + 4'd8: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4486 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; + 4'd9: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4486 = + !wci_9_busy && (wci_9_wReset_n || wci_9_respF$FULL_N); + 4'd10: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4486 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; + 4'd11: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4486 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; + 4'd12: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4486 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; + 4'd13: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4486 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; + 4'd14: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4486 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; + 4'd15: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4486 = 1'd1; + endcase + end + always@(_theResult_____1__h75739 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + wci_10_busy or + wci_10_reqF_cntr_r or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) + begin + case (_theResult_____1__h75739) + 4'd0: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4528 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; + 4'd1: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4528 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; + 4'd2: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4528 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; + 4'd3: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4528 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; + 4'd4: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4528 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; + 4'd5: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4528 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; + 4'd6: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4528 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; + 4'd7: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4528 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; + 4'd8: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4528 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; + 4'd9: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4528 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; + 4'd10: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4528 = + !wci_10_busy && !wci_10_reqF_cntr_r; + 4'd11: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4528 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; + 4'd12: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4528 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; + 4'd13: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4528 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; + 4'd14: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4528 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; + 4'd15: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4528 = 1'd1; + endcase + end + always@(_theResult_____1__h75739 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + wci_10_busy or + wci_10_wReset_n or + wci_10_respF$FULL_N or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) + begin + case (_theResult_____1__h75739) + 4'd0: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4540 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; + 4'd1: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4540 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; + 4'd2: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4540 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; + 4'd3: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4540 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; + 4'd4: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4540 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; + 4'd5: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4540 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; + 4'd6: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4540 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; + 4'd7: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4540 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; + 4'd8: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4540 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; + 4'd9: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4540 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; + 4'd10: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4540 = + !wci_10_busy && (wci_10_wReset_n || wci_10_respF$FULL_N); + 4'd11: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4540 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; + 4'd12: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4540 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; + 4'd13: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4540 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; + 4'd14: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4540 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; + 4'd15: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4540 = 1'd1; + endcase + end + always@(_theResult_____1__h75739 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + wci_10_busy or + wci_10_reqF_cntr_r or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) + begin + case (_theResult_____1__h75739) + 4'd0: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4551 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; + 4'd1: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4551 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; + 4'd2: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4551 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; + 4'd3: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4551 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; + 4'd4: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4551 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; + 4'd5: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4551 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; + 4'd6: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4551 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; + 4'd7: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4551 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; + 4'd8: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4551 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; + 4'd9: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4551 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; + 4'd10: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4551 = + !wci_10_busy && !wci_10_reqF_cntr_r; + 4'd11: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4551 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; + 4'd12: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4551 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; + 4'd13: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4551 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; + 4'd14: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4551 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; + 4'd15: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4551 = 1'd1; + endcase + end + always@(_theResult_____1__h75739 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + wci_10_busy or + wci_10_wReset_n or + wci_10_respF$FULL_N or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) + begin + case (_theResult_____1__h75739) + 4'd0: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4561 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; + 4'd1: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4561 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; + 4'd2: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4561 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; + 4'd3: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4561 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; + 4'd4: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4561 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; + 4'd5: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4561 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; + 4'd6: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4561 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; + 4'd7: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4561 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; + 4'd8: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4561 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; + 4'd9: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4561 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; + 4'd10: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4561 = + !wci_10_busy && (wci_10_wReset_n || wci_10_respF$FULL_N); + 4'd11: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4561 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; + 4'd12: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4561 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; + 4'd13: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4561 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; + 4'd14: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4561 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; + 4'd15: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4561 = 1'd1; + endcase + end + always@(_theResult_____1__h75739 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + wci_11_busy or + wci_11_reqF_cntr_r or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) + begin + case (_theResult_____1__h75739) + 4'd0: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4603 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; + 4'd1: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4603 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; + 4'd2: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4603 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; + 4'd3: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4603 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; + 4'd4: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4603 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; + 4'd5: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4603 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; + 4'd6: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4603 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; + 4'd7: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4603 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; + 4'd8: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4603 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; + 4'd9: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4603 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; + 4'd10: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4603 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; + 4'd11: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4603 = + !wci_11_busy && !wci_11_reqF_cntr_r; + 4'd12: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4603 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; + 4'd13: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4603 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; + 4'd14: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4603 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; + 4'd15: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4603 = 1'd1; + endcase + end + always@(_theResult_____1__h75739 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + wci_11_busy or + wci_11_wReset_n or + wci_11_respF$FULL_N or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) + begin + case (_theResult_____1__h75739) + 4'd0: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4615 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; + 4'd1: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4615 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; + 4'd2: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4615 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; + 4'd3: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4615 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; + 4'd4: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4615 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; + 4'd5: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4615 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; + 4'd6: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4615 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; + 4'd7: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4615 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; + 4'd8: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4615 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; + 4'd9: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4615 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; + 4'd10: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4615 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; + 4'd11: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4615 = + !wci_11_busy && (wci_11_wReset_n || wci_11_respF$FULL_N); + 4'd12: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4615 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; + 4'd13: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4615 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; + 4'd14: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4615 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; + 4'd15: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4615 = 1'd1; + endcase + end + always@(_theResult_____1__h75739 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + wci_11_busy or + wci_11_reqF_cntr_r or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) + begin + case (_theResult_____1__h75739) + 4'd0: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4626 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; + 4'd1: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4626 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; + 4'd2: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4626 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; + 4'd3: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4626 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; + 4'd4: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4626 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; + 4'd5: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4626 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; + 4'd6: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4626 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; + 4'd7: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4626 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; + 4'd8: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4626 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; + 4'd9: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4626 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; + 4'd10: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4626 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; + 4'd11: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4626 = + !wci_11_busy && !wci_11_reqF_cntr_r; + 4'd12: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4626 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; + 4'd13: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4626 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; + 4'd14: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4626 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; + 4'd15: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4626 = 1'd1; + endcase + end + always@(_theResult_____1__h75739 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + wci_11_busy or + wci_11_wReset_n or + wci_11_respF$FULL_N or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) + begin + case (_theResult_____1__h75739) + 4'd0: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4636 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; + 4'd1: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4636 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; + 4'd2: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4636 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; + 4'd3: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4636 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; + 4'd4: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4636 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; + 4'd5: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4636 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; + 4'd6: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4636 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; + 4'd7: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4636 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; + 4'd8: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4636 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; + 4'd9: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4636 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; + 4'd10: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4636 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; + 4'd11: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4636 = + !wci_11_busy && (wci_11_wReset_n || wci_11_respF$FULL_N); + 4'd12: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4636 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; + 4'd13: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4636 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; + 4'd14: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4636 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; + 4'd15: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4636 = 1'd1; + endcase + end + always@(_theResult_____1__h75739 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + wci_12_busy or + wci_12_reqF_cntr_r or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) + begin + case (_theResult_____1__h75739) + 4'd0: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4678 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; + 4'd1: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4678 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; + 4'd2: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4678 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; + 4'd3: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4678 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; + 4'd4: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4678 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; + 4'd5: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4678 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; + 4'd6: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4678 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; + 4'd7: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4678 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; + 4'd8: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4678 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; + 4'd9: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4678 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; + 4'd10: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4678 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; + 4'd11: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4678 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; + 4'd12: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4678 = + !wci_12_busy && !wci_12_reqF_cntr_r; + 4'd13: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4678 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; + 4'd14: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4678 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; + 4'd15: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4678 = 1'd1; + endcase + end + always@(_theResult_____1__h75739 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + wci_12_busy or + wci_12_wReset_n or + wci_12_respF$FULL_N or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) + begin + case (_theResult_____1__h75739) + 4'd0: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4690 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; + 4'd1: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4690 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; + 4'd2: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4690 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; + 4'd3: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4690 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; + 4'd4: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4690 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; + 4'd5: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4690 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; + 4'd6: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4690 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; + 4'd7: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4690 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; + 4'd8: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4690 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; + 4'd9: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4690 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; + 4'd10: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4690 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; + 4'd11: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4690 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; + 4'd12: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4690 = + !wci_12_busy && (wci_12_wReset_n || wci_12_respF$FULL_N); + 4'd13: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4690 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; + 4'd14: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4690 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; + 4'd15: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4690 = 1'd1; + endcase + end + always@(_theResult_____1__h75739 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + wci_12_busy or + wci_12_reqF_cntr_r or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) + begin + case (_theResult_____1__h75739) + 4'd0: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4701 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; + 4'd1: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4701 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; + 4'd2: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4701 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; + 4'd3: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4701 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; + 4'd4: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4701 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; + 4'd5: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4701 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; + 4'd6: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4701 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; + 4'd7: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4701 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; + 4'd8: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4701 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; + 4'd9: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4701 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; + 4'd10: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4701 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; + 4'd11: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4701 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; + 4'd12: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4701 = + !wci_12_busy && !wci_12_reqF_cntr_r; + 4'd13: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4701 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; + 4'd14: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4701 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; + 4'd15: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4701 = 1'd1; + endcase + end + always@(_theResult_____1__h75739 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + wci_12_busy or + wci_12_wReset_n or + wci_12_respF$FULL_N or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) + begin + case (_theResult_____1__h75739) + 4'd0: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4711 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; + 4'd1: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4711 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; + 4'd2: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4711 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; + 4'd3: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4711 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; + 4'd4: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4711 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; + 4'd5: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4711 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; + 4'd6: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4711 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; + 4'd7: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4711 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; + 4'd8: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4711 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; + 4'd9: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4711 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; + 4'd10: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4711 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; + 4'd11: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4711 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; + 4'd12: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4711 = + !wci_12_busy && (wci_12_wReset_n || wci_12_respF$FULL_N); + 4'd13: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4711 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; + 4'd14: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4711 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; + 4'd15: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4711 = 1'd1; + endcase + end + always@(_theResult_____1__h75739 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + wci_13_busy or + wci_13_reqF_cntr_r or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) + begin + case (_theResult_____1__h75739) + 4'd0: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4753 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; + 4'd1: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4753 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; + 4'd2: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4753 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; + 4'd3: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4753 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; + 4'd4: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4753 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; + 4'd5: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4753 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; + 4'd6: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4753 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; + 4'd7: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4753 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; + 4'd8: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4753 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; + 4'd9: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4753 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; + 4'd10: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4753 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; + 4'd11: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4753 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; + 4'd12: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4753 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; + 4'd13: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4753 = + !wci_13_busy && !wci_13_reqF_cntr_r; + 4'd14: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4753 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; + 4'd15: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4753 = 1'd1; + endcase + end + always@(_theResult_____1__h75739 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + wci_13_busy or + wci_13_wReset_n or + wci_13_respF$FULL_N or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) + begin + case (_theResult_____1__h75739) + 4'd0: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4765 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; + 4'd1: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4765 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; + 4'd2: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4765 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; + 4'd3: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4765 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; + 4'd4: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4765 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; + 4'd5: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4765 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; + 4'd6: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4765 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; + 4'd7: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4765 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; + 4'd8: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4765 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; + 4'd9: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4765 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; + 4'd10: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4765 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; + 4'd11: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4765 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; + 4'd12: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4765 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; + 4'd13: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4765 = + !wci_13_busy && (wci_13_wReset_n || wci_13_respF$FULL_N); + 4'd14: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4765 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; + 4'd15: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4765 = 1'd1; + endcase + end + always@(_theResult_____1__h75739 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + wci_13_busy or + wci_13_reqF_cntr_r or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) + begin + case (_theResult_____1__h75739) + 4'd0: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4776 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; + 4'd1: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4776 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; + 4'd2: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4776 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; + 4'd3: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4776 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; + 4'd4: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4776 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; + 4'd5: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4776 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; + 4'd6: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4776 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; + 4'd7: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4776 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; + 4'd8: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4776 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; + 4'd9: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4776 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; + 4'd10: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4776 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; + 4'd11: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4776 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; + 4'd12: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4776 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; + 4'd13: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4776 = + !wci_13_busy && !wci_13_reqF_cntr_r; + 4'd14: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4776 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; + 4'd15: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4776 = 1'd1; + endcase + end + always@(_theResult_____1__h75739 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + wci_13_busy or + wci_13_wReset_n or + wci_13_respF$FULL_N or + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942) + begin + case (_theResult_____1__h75739) + 4'd0: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4786 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; + 4'd1: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4786 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; + 4'd2: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4786 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; + 4'd3: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4786 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; + 4'd4: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4786 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; + 4'd5: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4786 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; + 4'd6: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4786 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; + 4'd7: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4786 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; + 4'd8: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4786 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; + 4'd9: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4786 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; + 4'd10: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4786 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; + 4'd11: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4786 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; + 4'd12: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4786 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; + 4'd13: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4786 = + !wci_13_busy && (wci_13_wReset_n || wci_13_respF$FULL_N); + 4'd14: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4786 = + NOT_wci_14_busy_196_937_AND_0_OR_wci_14_wReset_ETC___d2942; + 4'd15: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4786 = 1'd1; + endcase + end + always@(_theResult_____1__h75739 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + wci_14_busy or wci_14_reqF_cntr_r) + begin + case (_theResult_____1__h75739) + 4'd0: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4828 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; + 4'd1: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4828 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; + 4'd2: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4828 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; + 4'd3: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4828 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; + 4'd4: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4828 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; + 4'd5: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4828 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; + 4'd6: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4828 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; + 4'd7: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4828 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; + 4'd8: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4828 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; + 4'd9: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4828 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; + 4'd10: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4828 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; + 4'd11: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4828 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; + 4'd12: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4828 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; + 4'd13: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4828 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; + 4'd14: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4828 = + !wci_14_busy && !wci_14_reqF_cntr_r; + 4'd15: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4828 = 1'd1; + endcase + end + always@(_theResult_____1__h75739 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + wci_14_busy or wci_14_wReset_n or wci_14_respF$FULL_N) + begin + case (_theResult_____1__h75739) + 4'd0: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4840 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; + 4'd1: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4840 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; + 4'd2: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4840 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; + 4'd3: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4840 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; + 4'd4: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4840 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; + 4'd5: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4840 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; + 4'd6: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4840 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; + 4'd7: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4840 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; + 4'd8: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4840 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; + 4'd9: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4840 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; + 4'd10: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4840 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; + 4'd11: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4840 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; + 4'd12: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4840 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; + 4'd13: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4840 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; + 4'd14: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4840 = + !wci_14_busy && (wci_14_wReset_n || wci_14_respF$FULL_N); + 4'd15: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4840 = 1'd1; + endcase + end + always@(_theResult_____1__h75739 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + wci_14_busy or wci_14_reqF_cntr_r) + begin + case (_theResult_____1__h75739) + 4'd0: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4851 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; + 4'd1: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4851 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; + 4'd2: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4851 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; + 4'd3: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4851 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; + 4'd4: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4851 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; + 4'd5: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4851 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; + 4'd6: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4851 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; + 4'd7: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4851 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; + 4'd8: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4851 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; + 4'd9: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4851 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; + 4'd10: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4851 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; + 4'd11: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4851 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; + 4'd12: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4851 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; + 4'd13: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4851 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; + 4'd14: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4851 = + !wci_14_busy && !wci_14_reqF_cntr_r; + 4'd15: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4851 = 1'd1; + endcase + end + always@(_theResult_____1__h75739 or + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046 or + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864 or + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870 or + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876 or + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882 or + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888 or + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894 or + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900 or + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906 or + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912 or + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918 or + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924 or + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930 or + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936 or + wci_14_busy or wci_14_wReset_n or wci_14_respF$FULL_N) + begin + case (_theResult_____1__h75739) + 4'd0: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4861 = + NOT_wci_0_busy_36_856_AND_0_OR_wci_0_wReset_n__ETC___d3046; + 4'd1: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4861 = + NOT_wci_1_busy_76_859_AND_0_OR_wci_1_wReset_n__ETC___d2864; + 4'd2: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4861 = + NOT_wci_2_busy_16_865_AND_0_OR_wci_2_wReset_n__ETC___d2870; + 4'd3: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4861 = + NOT_wci_3_busy_56_871_AND_0_OR_wci_3_wReset_n__ETC___d2876; + 4'd4: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4861 = + NOT_wci_4_busy_96_877_AND_0_OR_wci_4_wReset_n__ETC___d2882; + 4'd5: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4861 = + NOT_wci_5_busy_36_883_AND_0_OR_wci_5_wReset_n__ETC___d2888; + 4'd6: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4861 = + NOT_wci_6_busy_076_889_AND_0_OR_wci_6_wReset_n_ETC___d2894; + 4'd7: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4861 = + NOT_wci_7_busy_216_895_AND_0_OR_wci_7_wReset_n_ETC___d2900; + 4'd8: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4861 = + NOT_wci_8_busy_356_901_AND_0_OR_wci_8_wReset_n_ETC___d2906; + 4'd9: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4861 = + NOT_wci_9_busy_496_907_AND_0_OR_wci_9_wReset_n_ETC___d2912; + 4'd10: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4861 = + NOT_wci_10_busy_636_913_AND_0_OR_wci_10_wReset_ETC___d2918; + 4'd11: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4861 = + NOT_wci_11_busy_776_919_AND_0_OR_wci_11_wReset_ETC___d2924; + 4'd12: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4861 = + NOT_wci_12_busy_916_925_AND_0_OR_wci_12_wReset_ETC___d2930; + 4'd13: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4861 = + NOT_wci_13_busy_056_931_AND_0_OR_wci_13_wReset_ETC___d2936; + 4'd14: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4861 = + !wci_14_busy && (wci_14_wReset_n || wci_14_respF$FULL_N); + 4'd15: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d4861 = 1'd1; + endcase + end + always@(_theResult_____1__h75739 or + wci_0_busy or + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_w_ETC___d4932 or + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_N_ETC___d4934 or + wci_1_busy or + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_w_ETC___d4938 or + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_N_ETC___d4940 or + wci_2_busy or + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_w_ETC___d4944 or + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_N_ETC___d4946 or + wci_3_busy or + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_w_ETC___d4950 or + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_N_ETC___d4952 or + wci_4_busy or + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_w_ETC___d4956 or + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_N_ETC___d4958 or + wci_5_busy or + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_w_ETC___d4962 or + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_N_ETC___d4964 or + wci_6_busy or + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_w_ETC___d4968 or + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_N_ETC___d4970 or + wci_7_busy or + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_w_ETC___d4974 or + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_N_ETC___d4976 or + wci_8_busy or + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_w_ETC___d4980 or + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_N_ETC___d4982 or + wci_9_busy or + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_w_ETC___d4986 or + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_N_ETC___d4988 or + wci_10_busy or + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_w_ETC___d4992 or + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_N_ETC___d4994 or + wci_11_busy or + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_w_ETC___d4998 or + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_N_ETC___d5000 or + wci_12_busy or + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_w_ETC___d5004 or + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_N_ETC___d5006 or + wci_13_busy or + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_w_ETC___d5010 or + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_N_ETC___d5012 or + wci_14_busy or + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_w_ETC___d5016 or + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_N_ETC___d5018) + begin + case (_theResult_____1__h75739) + 4'd0: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d5021 = + !wci_0_busy && + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_w_ETC___d4932 && + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_N_ETC___d4934; + 4'd1: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d5021 = + !wci_1_busy && + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_w_ETC___d4938 && + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_N_ETC___d4940; + 4'd2: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d5021 = + !wci_2_busy && + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_w_ETC___d4944 && + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_N_ETC___d4946; + 4'd3: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d5021 = + !wci_3_busy && + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_w_ETC___d4950 && + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_N_ETC___d4952; + 4'd4: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d5021 = + !wci_4_busy && + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_w_ETC___d4956 && + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_N_ETC___d4958; + 4'd5: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d5021 = + !wci_5_busy && + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_w_ETC___d4962 && + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_N_ETC___d4964; + 4'd6: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d5021 = + !wci_6_busy && + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_w_ETC___d4968 && + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_N_ETC___d4970; + 4'd7: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d5021 = + !wci_7_busy && + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_w_ETC___d4974 && + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_N_ETC___d4976; + 4'd8: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d5021 = + !wci_8_busy && + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_w_ETC___d4980 && + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_N_ETC___d4982; + 4'd9: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d5021 = + !wci_9_busy && + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_w_ETC___d4986 && + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_N_ETC___d4988; + 4'd10: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d5021 = + !wci_10_busy && + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_w_ETC___d4992 && + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_N_ETC___d4994; + 4'd11: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d5021 = + !wci_11_busy && + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_w_ETC___d4998 && + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_N_ETC___d5000; + 4'd12: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d5021 = + !wci_12_busy && + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_w_ETC___d5004 && + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_N_ETC___d5006; + 4'd13: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d5021 = + !wci_13_busy && + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_w_ETC___d5010 && + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_N_ETC___d5012; + 4'd14: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d5021 = + !wci_14_busy && + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_w_ETC___d5016 && + IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_THEN_N_ETC___d5018; + 4'd15: + CASE_IF_cpReq_363_BITS_37_TO_36_649_EQ_2_650_T_ETC___d5021 = 1'd1; + endcase + end + always@(wrkAct or + wci_0_respF$EMPTY_N or + wci_1_respF$EMPTY_N or + wci_2_respF$EMPTY_N or + wci_3_respF$EMPTY_N or + wci_4_respF$EMPTY_N or + wci_5_respF$EMPTY_N or + wci_6_respF$EMPTY_N or + wci_7_respF$EMPTY_N or + wci_8_respF$EMPTY_N or + wci_9_respF$EMPTY_N or + wci_10_respF$EMPTY_N or + wci_11_respF$EMPTY_N or + wci_12_respF$EMPTY_N or + wci_13_respF$EMPTY_N or wci_14_respF$EMPTY_N) + begin + case (wrkAct) + 4'd0: + CASE_wrkAct_028_0_wci_0_respF_i_notEmpty__029__ETC___d5044 = + wci_0_respF$EMPTY_N; + 4'd1: + CASE_wrkAct_028_0_wci_0_respF_i_notEmpty__029__ETC___d5044 = + wci_1_respF$EMPTY_N; + 4'd2: + CASE_wrkAct_028_0_wci_0_respF_i_notEmpty__029__ETC___d5044 = + wci_2_respF$EMPTY_N; + 4'd3: + CASE_wrkAct_028_0_wci_0_respF_i_notEmpty__029__ETC___d5044 = + wci_3_respF$EMPTY_N; + 4'd4: + CASE_wrkAct_028_0_wci_0_respF_i_notEmpty__029__ETC___d5044 = + wci_4_respF$EMPTY_N; + 4'd5: + CASE_wrkAct_028_0_wci_0_respF_i_notEmpty__029__ETC___d5044 = + wci_5_respF$EMPTY_N; + 4'd6: + CASE_wrkAct_028_0_wci_0_respF_i_notEmpty__029__ETC___d5044 = + wci_6_respF$EMPTY_N; + 4'd7: + CASE_wrkAct_028_0_wci_0_respF_i_notEmpty__029__ETC___d5044 = + wci_7_respF$EMPTY_N; + 4'd8: + CASE_wrkAct_028_0_wci_0_respF_i_notEmpty__029__ETC___d5044 = + wci_8_respF$EMPTY_N; + 4'd9: + CASE_wrkAct_028_0_wci_0_respF_i_notEmpty__029__ETC___d5044 = + wci_9_respF$EMPTY_N; + 4'd10: + CASE_wrkAct_028_0_wci_0_respF_i_notEmpty__029__ETC___d5044 = + wci_10_respF$EMPTY_N; + 4'd11: + CASE_wrkAct_028_0_wci_0_respF_i_notEmpty__029__ETC___d5044 = + wci_11_respF$EMPTY_N; + 4'd12: + CASE_wrkAct_028_0_wci_0_respF_i_notEmpty__029__ETC___d5044 = + wci_12_respF$EMPTY_N; + 4'd13: + CASE_wrkAct_028_0_wci_0_respF_i_notEmpty__029__ETC___d5044 = + wci_13_respF$EMPTY_N; + 4'd14: + CASE_wrkAct_028_0_wci_0_respF_i_notEmpty__029__ETC___d5044 = + wci_14_respF$EMPTY_N; + 4'd15: + CASE_wrkAct_028_0_wci_0_respF_i_notEmpty__029__ETC___d5044 = 1'd1; + endcase + end + always@(cpReq or + x__h104311 or + pciDevice or + x__h104860 or + cpStatus__h74863 or scratch20 or scratch24 or cpControl) + begin + case (cpReq[11:4]) + 8'h0: + IF_cpReq_363_BITS_11_TO_4_366_EQ_0x0_445_THEN__ETC___d2590 = + 32'h4F70656E; + 8'h04: + IF_cpReq_363_BITS_11_TO_4_366_EQ_0x0_445_THEN__ETC___d2590 = + 32'h43504900; + 8'h08: + IF_cpReq_363_BITS_11_TO_4_366_EQ_0x0_445_THEN__ETC___d2590 = + 32'h00000001; + 8'h0C: + IF_cpReq_363_BITS_11_TO_4_366_EQ_0x0_445_THEN__ETC___d2590 = + 32'd1371848185; + 8'h10: + IF_cpReq_363_BITS_11_TO_4_366_EQ_0x0_445_THEN__ETC___d2590 = + { 17'd0, x__h104311 }; + 8'h14: + IF_cpReq_363_BITS_11_TO_4_366_EQ_0x0_445_THEN__ETC___d2590 = + { 16'd0, pciDevice }; + 8'h18: + IF_cpReq_363_BITS_11_TO_4_366_EQ_0x0_445_THEN__ETC___d2590 = + { 17'd0, x__h104860 }; + 8'h1C: + IF_cpReq_363_BITS_11_TO_4_366_EQ_0x0_445_THEN__ETC___d2590 = + cpStatus__h74863; + 8'h20: + IF_cpReq_363_BITS_11_TO_4_366_EQ_0x0_445_THEN__ETC___d2590 = + scratch20; + 8'h24: + IF_cpReq_363_BITS_11_TO_4_366_EQ_0x0_445_THEN__ETC___d2590 = + scratch24; + 8'h28: + IF_cpReq_363_BITS_11_TO_4_366_EQ_0x0_445_THEN__ETC___d2590 = + cpControl; + default: IF_cpReq_363_BITS_11_TO_4_366_EQ_0x0_445_THEN__ETC___d2590 = + 32'd0; + endcase + end + always@(cpReq or + timeServ_ppsLostSticky or + timeServ_gpsInSticky or + timeServ_ppsInSticky or + timeServ_timeSetSticky or + timeServ_ppsOKCC$dD_OUT or + timeServ_ppsLostCC$dD_OUT or + timeServ_rollingPPSIn$dD_OUT or + timeServ_rplTimeControl or + timeServ_nowInCC$dD_OUT or + deltaTime or + timeServ_refPerPPS$dD_OUT or readCntReg or devDNAV$wget) + begin + case (cpReq[11:4]) + 8'h30: + IF_cpReq_363_BITS_11_TO_4_366_EQ_0x30_595_THEN_ETC___d2691 = + { timeServ_ppsLostSticky, + timeServ_gpsInSticky, + timeServ_ppsInSticky, + timeServ_timeSetSticky, + timeServ_ppsOKCC$dD_OUT, + timeServ_ppsLostCC$dD_OUT, + 18'h0, + timeServ_rollingPPSIn$dD_OUT }; + 8'h34: + IF_cpReq_363_BITS_11_TO_4_366_EQ_0x30_595_THEN_ETC___d2691 = + { 27'd0, timeServ_rplTimeControl }; + 8'h38: + IF_cpReq_363_BITS_11_TO_4_366_EQ_0x30_595_THEN_ETC___d2691 = + timeServ_nowInCC$dD_OUT[63:32]; + 8'h3C: + IF_cpReq_363_BITS_11_TO_4_366_EQ_0x30_595_THEN_ETC___d2691 = + timeServ_nowInCC$dD_OUT[31:0]; + 8'h40: + IF_cpReq_363_BITS_11_TO_4_366_EQ_0x30_595_THEN_ETC___d2691 = + deltaTime[63:32]; + 8'h44: + IF_cpReq_363_BITS_11_TO_4_366_EQ_0x30_595_THEN_ETC___d2691 = + deltaTime[31:0]; + 8'h48: + IF_cpReq_363_BITS_11_TO_4_366_EQ_0x30_595_THEN_ETC___d2691 = + { 4'd0, timeServ_refPerPPS$dD_OUT }; + 8'h4C: + IF_cpReq_363_BITS_11_TO_4_366_EQ_0x30_595_THEN_ETC___d2691 = + readCntReg; + 8'h50: + IF_cpReq_363_BITS_11_TO_4_366_EQ_0x30_595_THEN_ETC___d2691 = + devDNAV$wget[31:0]; + 8'h54: + IF_cpReq_363_BITS_11_TO_4_366_EQ_0x30_595_THEN_ETC___d2691 = + devDNAV$wget[63:32]; + 8'h7C: + IF_cpReq_363_BITS_11_TO_4_366_EQ_0x30_595_THEN_ETC___d2691 = 32'd2; + 8'h80: + IF_cpReq_363_BITS_11_TO_4_366_EQ_0x30_595_THEN_ETC___d2691 = + 32'd268435464; + default: IF_cpReq_363_BITS_11_TO_4_366_EQ_0x30_595_THEN_ETC___d2691 = + 32'd268566536; + endcase + end + always@(cpReq or uuid_arg) + begin + case (cpReq[9:6]) + 4'd0: + CASE_cpReq_BITS_9_TO_6_0_uuid_arg_BITS_511_TO__ETC__q3 = + uuid_arg[511:480]; + 4'd1: + CASE_cpReq_BITS_9_TO_6_0_uuid_arg_BITS_511_TO__ETC__q3 = + uuid_arg[479:448]; + 4'd2: + CASE_cpReq_BITS_9_TO_6_0_uuid_arg_BITS_511_TO__ETC__q3 = + uuid_arg[447:416]; + 4'd3: + CASE_cpReq_BITS_9_TO_6_0_uuid_arg_BITS_511_TO__ETC__q3 = + uuid_arg[415:384]; + 4'd4: + CASE_cpReq_BITS_9_TO_6_0_uuid_arg_BITS_511_TO__ETC__q3 = + uuid_arg[383:352]; + 4'd5: + CASE_cpReq_BITS_9_TO_6_0_uuid_arg_BITS_511_TO__ETC__q3 = + uuid_arg[351:320]; + 4'd6: + CASE_cpReq_BITS_9_TO_6_0_uuid_arg_BITS_511_TO__ETC__q3 = + uuid_arg[319:288]; + 4'd7: + CASE_cpReq_BITS_9_TO_6_0_uuid_arg_BITS_511_TO__ETC__q3 = + uuid_arg[287:256]; + 4'd8: + CASE_cpReq_BITS_9_TO_6_0_uuid_arg_BITS_511_TO__ETC__q3 = + uuid_arg[255:224]; + 4'd9: + CASE_cpReq_BITS_9_TO_6_0_uuid_arg_BITS_511_TO__ETC__q3 = + uuid_arg[223:192]; + 4'd10: + CASE_cpReq_BITS_9_TO_6_0_uuid_arg_BITS_511_TO__ETC__q3 = + uuid_arg[191:160]; + 4'd11: + CASE_cpReq_BITS_9_TO_6_0_uuid_arg_BITS_511_TO__ETC__q3 = + uuid_arg[159:128]; + 4'd12: + CASE_cpReq_BITS_9_TO_6_0_uuid_arg_BITS_511_TO__ETC__q3 = uuid_arg[127:96]; 4'd13: - CASE_cpReq_BITS_9_TO_6_uuid_arg_BITS_31_TO_0_0_ETC__q3 = + CASE_cpReq_BITS_9_TO_6_0_uuid_arg_BITS_511_TO__ETC__q3 = uuid_arg[95:64]; 4'd14: - CASE_cpReq_BITS_9_TO_6_uuid_arg_BITS_31_TO_0_0_ETC__q3 = + CASE_cpReq_BITS_9_TO_6_0_uuid_arg_BITS_511_TO__ETC__q3 = uuid_arg[63:32]; 4'd15: - CASE_cpReq_BITS_9_TO_6_uuid_arg_BITS_31_TO_0_0_ETC__q3 = + CASE_cpReq_BITS_9_TO_6_0_uuid_arg_BITS_511_TO__ETC__q3 = uuid_arg[31:0]; endcase end @@ -17774,6 +24480,10 @@ module mkOCCP(pciDevice, cpReq <= `BSV_ASSIGNMENT_DELAY 65'h02AAAAAAAAAAAAAAA; deltaTime <= `BSV_ASSIGNMENT_DELAY 64'd0; dispatched <= `BSV_ASSIGNMENT_DELAY 1'd0; + dna_cnt <= `BSV_ASSIGNMENT_DELAY 7'd0; + dna_rdReg <= `BSV_ASSIGNMENT_DELAY 1'd0; + dna_shftReg <= `BSV_ASSIGNMENT_DELAY 1'd0; + dna_sr <= `BSV_ASSIGNMENT_DELAY 57'd0; readCntReg <= `BSV_ASSIGNMENT_DELAY 32'd0; rogueTLP <= `BSV_ASSIGNMENT_DELAY 4'd0; rom_serverAdapter_cnt <= `BSV_ASSIGNMENT_DELAY 3'd0; @@ -17786,336 +24496,336 @@ module mkOCCP(pciDevice, timeServ_rplTimeControl <= `BSV_ASSIGNMENT_DELAY 5'd0; timeServ_timeSetSticky <= `BSV_ASSIGNMENT_DELAY 1'd0; warmResetP <= `BSV_ASSIGNMENT_DELAY 1'd0; - wci_busy <= `BSV_ASSIGNMENT_DELAY 1'd0; - wci_busy_1 <= `BSV_ASSIGNMENT_DELAY 1'd0; - wci_busy_10 <= `BSV_ASSIGNMENT_DELAY 1'd0; - wci_busy_11 <= `BSV_ASSIGNMENT_DELAY 1'd0; - wci_busy_12 <= `BSV_ASSIGNMENT_DELAY 1'd0; - wci_busy_13 <= `BSV_ASSIGNMENT_DELAY 1'd0; - wci_busy_14 <= `BSV_ASSIGNMENT_DELAY 1'd0; - wci_busy_2 <= `BSV_ASSIGNMENT_DELAY 1'd0; - wci_busy_3 <= `BSV_ASSIGNMENT_DELAY 1'd0; - wci_busy_4 <= `BSV_ASSIGNMENT_DELAY 1'd0; - wci_busy_5 <= `BSV_ASSIGNMENT_DELAY 1'd0; - wci_busy_6 <= `BSV_ASSIGNMENT_DELAY 1'd0; - wci_busy_7 <= `BSV_ASSIGNMENT_DELAY 1'd0; - wci_busy_8 <= `BSV_ASSIGNMENT_DELAY 1'd0; - wci_busy_9 <= `BSV_ASSIGNMENT_DELAY 1'd0; - wci_lastConfigAddr <= `BSV_ASSIGNMENT_DELAY 33'h0AAAAAAAA; - wci_lastConfigAddr_1 <= `BSV_ASSIGNMENT_DELAY 33'h0AAAAAAAA; - wci_lastConfigAddr_10 <= `BSV_ASSIGNMENT_DELAY 33'h0AAAAAAAA; - wci_lastConfigAddr_11 <= `BSV_ASSIGNMENT_DELAY 33'h0AAAAAAAA; - wci_lastConfigAddr_12 <= `BSV_ASSIGNMENT_DELAY 33'h0AAAAAAAA; - wci_lastConfigAddr_13 <= `BSV_ASSIGNMENT_DELAY 33'h0AAAAAAAA; - wci_lastConfigAddr_14 <= `BSV_ASSIGNMENT_DELAY 33'h0AAAAAAAA; - wci_lastConfigAddr_2 <= `BSV_ASSIGNMENT_DELAY 33'h0AAAAAAAA; - wci_lastConfigAddr_3 <= `BSV_ASSIGNMENT_DELAY 33'h0AAAAAAAA; - wci_lastConfigAddr_4 <= `BSV_ASSIGNMENT_DELAY 33'h0AAAAAAAA; - wci_lastConfigAddr_5 <= `BSV_ASSIGNMENT_DELAY 33'h0AAAAAAAA; - wci_lastConfigAddr_6 <= `BSV_ASSIGNMENT_DELAY 33'h0AAAAAAAA; - wci_lastConfigAddr_7 <= `BSV_ASSIGNMENT_DELAY 33'h0AAAAAAAA; - wci_lastConfigAddr_8 <= `BSV_ASSIGNMENT_DELAY 33'h0AAAAAAAA; - wci_lastConfigAddr_9 <= `BSV_ASSIGNMENT_DELAY 33'h0AAAAAAAA; - wci_lastConfigBE <= `BSV_ASSIGNMENT_DELAY 5'd10; - wci_lastConfigBE_1 <= `BSV_ASSIGNMENT_DELAY 5'd10; - wci_lastConfigBE_10 <= `BSV_ASSIGNMENT_DELAY 5'd10; - wci_lastConfigBE_11 <= `BSV_ASSIGNMENT_DELAY 5'd10; - wci_lastConfigBE_12 <= `BSV_ASSIGNMENT_DELAY 5'd10; - wci_lastConfigBE_13 <= `BSV_ASSIGNMENT_DELAY 5'd10; - wci_lastConfigBE_14 <= `BSV_ASSIGNMENT_DELAY 5'd10; - wci_lastConfigBE_2 <= `BSV_ASSIGNMENT_DELAY 5'd10; - wci_lastConfigBE_3 <= `BSV_ASSIGNMENT_DELAY 5'd10; - wci_lastConfigBE_4 <= `BSV_ASSIGNMENT_DELAY 5'd10; - wci_lastConfigBE_5 <= `BSV_ASSIGNMENT_DELAY 5'd10; - wci_lastConfigBE_6 <= `BSV_ASSIGNMENT_DELAY 5'd10; - wci_lastConfigBE_7 <= `BSV_ASSIGNMENT_DELAY 5'd10; - wci_lastConfigBE_8 <= `BSV_ASSIGNMENT_DELAY 5'd10; - wci_lastConfigBE_9 <= `BSV_ASSIGNMENT_DELAY 5'd10; - wci_lastControlOp <= `BSV_ASSIGNMENT_DELAY 4'd2; - wci_lastControlOp_1 <= `BSV_ASSIGNMENT_DELAY 4'd2; - wci_lastControlOp_10 <= `BSV_ASSIGNMENT_DELAY 4'd2; - wci_lastControlOp_11 <= `BSV_ASSIGNMENT_DELAY 4'd2; - wci_lastControlOp_12 <= `BSV_ASSIGNMENT_DELAY 4'd2; - wci_lastControlOp_13 <= `BSV_ASSIGNMENT_DELAY 4'd2; - wci_lastControlOp_14 <= `BSV_ASSIGNMENT_DELAY 4'd2; - wci_lastControlOp_2 <= `BSV_ASSIGNMENT_DELAY 4'd2; - wci_lastControlOp_3 <= `BSV_ASSIGNMENT_DELAY 4'd2; - wci_lastControlOp_4 <= `BSV_ASSIGNMENT_DELAY 4'd2; - wci_lastControlOp_5 <= `BSV_ASSIGNMENT_DELAY 4'd2; - wci_lastControlOp_6 <= `BSV_ASSIGNMENT_DELAY 4'd2; - wci_lastControlOp_7 <= `BSV_ASSIGNMENT_DELAY 4'd2; - wci_lastControlOp_8 <= `BSV_ASSIGNMENT_DELAY 4'd2; - wci_lastControlOp_9 <= `BSV_ASSIGNMENT_DELAY 4'd2; - wci_lastOpWrite <= `BSV_ASSIGNMENT_DELAY 2'd0; - wci_lastOpWrite_1 <= `BSV_ASSIGNMENT_DELAY 2'd0; - wci_lastOpWrite_10 <= `BSV_ASSIGNMENT_DELAY 2'd0; - wci_lastOpWrite_11 <= `BSV_ASSIGNMENT_DELAY 2'd0; - wci_lastOpWrite_12 <= `BSV_ASSIGNMENT_DELAY 2'd0; - wci_lastOpWrite_13 <= `BSV_ASSIGNMENT_DELAY 2'd0; - wci_lastOpWrite_14 <= `BSV_ASSIGNMENT_DELAY 2'd0; - wci_lastOpWrite_2 <= `BSV_ASSIGNMENT_DELAY 2'd0; - wci_lastOpWrite_3 <= `BSV_ASSIGNMENT_DELAY 2'd0; - wci_lastOpWrite_4 <= `BSV_ASSIGNMENT_DELAY 2'd0; - wci_lastOpWrite_5 <= `BSV_ASSIGNMENT_DELAY 2'd0; - wci_lastOpWrite_6 <= `BSV_ASSIGNMENT_DELAY 2'd0; - wci_lastOpWrite_7 <= `BSV_ASSIGNMENT_DELAY 2'd0; - wci_lastOpWrite_8 <= `BSV_ASSIGNMENT_DELAY 2'd0; - wci_lastOpWrite_9 <= `BSV_ASSIGNMENT_DELAY 2'd0; - wci_mFlagReg <= `BSV_ASSIGNMENT_DELAY 2'b10; - wci_mFlagReg_1 <= `BSV_ASSIGNMENT_DELAY 2'b10; - wci_mFlagReg_10 <= `BSV_ASSIGNMENT_DELAY 2'b10; - wci_mFlagReg_11 <= `BSV_ASSIGNMENT_DELAY 2'b10; - wci_mFlagReg_12 <= `BSV_ASSIGNMENT_DELAY 2'b10; - wci_mFlagReg_13 <= `BSV_ASSIGNMENT_DELAY 2'b10; - wci_mFlagReg_14 <= `BSV_ASSIGNMENT_DELAY 2'b10; - wci_mFlagReg_2 <= `BSV_ASSIGNMENT_DELAY 2'b10; - wci_mFlagReg_3 <= `BSV_ASSIGNMENT_DELAY 2'b10; - wci_mFlagReg_4 <= `BSV_ASSIGNMENT_DELAY 2'b10; - wci_mFlagReg_5 <= `BSV_ASSIGNMENT_DELAY 2'b10; - wci_mFlagReg_6 <= `BSV_ASSIGNMENT_DELAY 2'b10; - wci_mFlagReg_7 <= `BSV_ASSIGNMENT_DELAY 2'b10; - wci_mFlagReg_8 <= `BSV_ASSIGNMENT_DELAY 2'b10; - wci_mFlagReg_9 <= `BSV_ASSIGNMENT_DELAY 2'b10; - wci_pageWindow <= `BSV_ASSIGNMENT_DELAY 12'd0; - wci_pageWindow_1 <= `BSV_ASSIGNMENT_DELAY 12'd0; - wci_pageWindow_10 <= `BSV_ASSIGNMENT_DELAY 12'd0; - wci_pageWindow_11 <= `BSV_ASSIGNMENT_DELAY 12'd0; - wci_pageWindow_12 <= `BSV_ASSIGNMENT_DELAY 12'd0; - wci_pageWindow_13 <= `BSV_ASSIGNMENT_DELAY 12'd0; - wci_pageWindow_14 <= `BSV_ASSIGNMENT_DELAY 12'd0; - wci_pageWindow_2 <= `BSV_ASSIGNMENT_DELAY 12'd0; - wci_pageWindow_3 <= `BSV_ASSIGNMENT_DELAY 12'd0; - wci_pageWindow_4 <= `BSV_ASSIGNMENT_DELAY 12'd0; - wci_pageWindow_5 <= `BSV_ASSIGNMENT_DELAY 12'd0; - wci_pageWindow_6 <= `BSV_ASSIGNMENT_DELAY 12'd0; - wci_pageWindow_7 <= `BSV_ASSIGNMENT_DELAY 12'd0; - wci_pageWindow_8 <= `BSV_ASSIGNMENT_DELAY 12'd0; - wci_pageWindow_9 <= `BSV_ASSIGNMENT_DELAY 12'd0; - wci_reqERR <= `BSV_ASSIGNMENT_DELAY 3'd0; - wci_reqERR_1 <= `BSV_ASSIGNMENT_DELAY 3'd0; - wci_reqERR_10 <= `BSV_ASSIGNMENT_DELAY 3'd0; - wci_reqERR_11 <= `BSV_ASSIGNMENT_DELAY 3'd0; - wci_reqERR_12 <= `BSV_ASSIGNMENT_DELAY 3'd0; - wci_reqERR_13 <= `BSV_ASSIGNMENT_DELAY 3'd0; - wci_reqERR_14 <= `BSV_ASSIGNMENT_DELAY 3'd0; - wci_reqERR_2 <= `BSV_ASSIGNMENT_DELAY 3'd0; - wci_reqERR_3 <= `BSV_ASSIGNMENT_DELAY 3'd0; - wci_reqERR_4 <= `BSV_ASSIGNMENT_DELAY 3'd0; - wci_reqERR_5 <= `BSV_ASSIGNMENT_DELAY 3'd0; - wci_reqERR_6 <= `BSV_ASSIGNMENT_DELAY 3'd0; - wci_reqERR_7 <= `BSV_ASSIGNMENT_DELAY 3'd0; - wci_reqERR_8 <= `BSV_ASSIGNMENT_DELAY 3'd0; - wci_reqERR_9 <= `BSV_ASSIGNMENT_DELAY 3'd0; - wci_reqFAIL <= `BSV_ASSIGNMENT_DELAY 3'd0; - wci_reqFAIL_1 <= `BSV_ASSIGNMENT_DELAY 3'd0; - wci_reqFAIL_10 <= `BSV_ASSIGNMENT_DELAY 3'd0; - wci_reqFAIL_11 <= `BSV_ASSIGNMENT_DELAY 3'd0; - wci_reqFAIL_12 <= `BSV_ASSIGNMENT_DELAY 3'd0; - wci_reqFAIL_13 <= `BSV_ASSIGNMENT_DELAY 3'd0; - wci_reqFAIL_14 <= `BSV_ASSIGNMENT_DELAY 3'd0; - wci_reqFAIL_2 <= `BSV_ASSIGNMENT_DELAY 3'd0; - wci_reqFAIL_3 <= `BSV_ASSIGNMENT_DELAY 3'd0; - wci_reqFAIL_4 <= `BSV_ASSIGNMENT_DELAY 3'd0; - wci_reqFAIL_5 <= `BSV_ASSIGNMENT_DELAY 3'd0; - wci_reqFAIL_6 <= `BSV_ASSIGNMENT_DELAY 3'd0; - wci_reqFAIL_7 <= `BSV_ASSIGNMENT_DELAY 3'd0; - wci_reqFAIL_8 <= `BSV_ASSIGNMENT_DELAY 3'd0; - wci_reqFAIL_9 <= `BSV_ASSIGNMENT_DELAY 3'd0; - wci_reqF_10_c_r <= `BSV_ASSIGNMENT_DELAY 1'd0; - wci_reqF_10_q_0 <= `BSV_ASSIGNMENT_DELAY 72'h0000000000AAAAAAAA; - wci_reqF_11_c_r <= `BSV_ASSIGNMENT_DELAY 1'd0; - wci_reqF_11_q_0 <= `BSV_ASSIGNMENT_DELAY 72'h0000000000AAAAAAAA; - wci_reqF_12_c_r <= `BSV_ASSIGNMENT_DELAY 1'd0; - wci_reqF_12_q_0 <= `BSV_ASSIGNMENT_DELAY 72'h0000000000AAAAAAAA; - wci_reqF_13_c_r <= `BSV_ASSIGNMENT_DELAY 1'd0; - wci_reqF_13_q_0 <= `BSV_ASSIGNMENT_DELAY 72'h0000000000AAAAAAAA; - wci_reqF_14_c_r <= `BSV_ASSIGNMENT_DELAY 1'd0; - wci_reqF_14_q_0 <= `BSV_ASSIGNMENT_DELAY 72'h0000000000AAAAAAAA; - wci_reqF_1_c_r <= `BSV_ASSIGNMENT_DELAY 1'd0; - wci_reqF_1_q_0 <= `BSV_ASSIGNMENT_DELAY 72'h0000000000AAAAAAAA; - wci_reqF_2_c_r <= `BSV_ASSIGNMENT_DELAY 1'd0; - wci_reqF_2_q_0 <= `BSV_ASSIGNMENT_DELAY 72'h0000000000AAAAAAAA; - wci_reqF_3_c_r <= `BSV_ASSIGNMENT_DELAY 1'd0; - wci_reqF_3_q_0 <= `BSV_ASSIGNMENT_DELAY 72'h0000000000AAAAAAAA; - wci_reqF_4_c_r <= `BSV_ASSIGNMENT_DELAY 1'd0; - wci_reqF_4_q_0 <= `BSV_ASSIGNMENT_DELAY 72'h0000000000AAAAAAAA; - wci_reqF_5_c_r <= `BSV_ASSIGNMENT_DELAY 1'd0; - wci_reqF_5_q_0 <= `BSV_ASSIGNMENT_DELAY 72'h0000000000AAAAAAAA; - wci_reqF_6_c_r <= `BSV_ASSIGNMENT_DELAY 1'd0; - wci_reqF_6_q_0 <= `BSV_ASSIGNMENT_DELAY 72'h0000000000AAAAAAAA; - wci_reqF_7_c_r <= `BSV_ASSIGNMENT_DELAY 1'd0; - wci_reqF_7_q_0 <= `BSV_ASSIGNMENT_DELAY 72'h0000000000AAAAAAAA; - wci_reqF_8_c_r <= `BSV_ASSIGNMENT_DELAY 1'd0; - wci_reqF_8_q_0 <= `BSV_ASSIGNMENT_DELAY 72'h0000000000AAAAAAAA; - wci_reqF_9_c_r <= `BSV_ASSIGNMENT_DELAY 1'd0; - wci_reqF_9_q_0 <= `BSV_ASSIGNMENT_DELAY 72'h0000000000AAAAAAAA; - wci_reqF_c_r <= `BSV_ASSIGNMENT_DELAY 1'd0; - wci_reqF_q_0 <= `BSV_ASSIGNMENT_DELAY 72'h0000000000AAAAAAAA; - wci_reqPend <= `BSV_ASSIGNMENT_DELAY 2'd0; - wci_reqPend_1 <= `BSV_ASSIGNMENT_DELAY 2'd0; - wci_reqPend_10 <= `BSV_ASSIGNMENT_DELAY 2'd0; - wci_reqPend_11 <= `BSV_ASSIGNMENT_DELAY 2'd0; - wci_reqPend_12 <= `BSV_ASSIGNMENT_DELAY 2'd0; - wci_reqPend_13 <= `BSV_ASSIGNMENT_DELAY 2'd0; - wci_reqPend_14 <= `BSV_ASSIGNMENT_DELAY 2'd0; - wci_reqPend_2 <= `BSV_ASSIGNMENT_DELAY 2'd0; - wci_reqPend_3 <= `BSV_ASSIGNMENT_DELAY 2'd0; - wci_reqPend_4 <= `BSV_ASSIGNMENT_DELAY 2'd0; - wci_reqPend_5 <= `BSV_ASSIGNMENT_DELAY 2'd0; - wci_reqPend_6 <= `BSV_ASSIGNMENT_DELAY 2'd0; - wci_reqPend_7 <= `BSV_ASSIGNMENT_DELAY 2'd0; - wci_reqPend_8 <= `BSV_ASSIGNMENT_DELAY 2'd0; - wci_reqPend_9 <= `BSV_ASSIGNMENT_DELAY 2'd0; - wci_reqTO <= `BSV_ASSIGNMENT_DELAY 3'd0; - wci_reqTO_1 <= `BSV_ASSIGNMENT_DELAY 3'd0; - wci_reqTO_10 <= `BSV_ASSIGNMENT_DELAY 3'd0; - wci_reqTO_11 <= `BSV_ASSIGNMENT_DELAY 3'd0; - wci_reqTO_12 <= `BSV_ASSIGNMENT_DELAY 3'd0; - wci_reqTO_13 <= `BSV_ASSIGNMENT_DELAY 3'd0; - wci_reqTO_14 <= `BSV_ASSIGNMENT_DELAY 3'd0; - wci_reqTO_2 <= `BSV_ASSIGNMENT_DELAY 3'd0; - wci_reqTO_3 <= `BSV_ASSIGNMENT_DELAY 3'd0; - wci_reqTO_4 <= `BSV_ASSIGNMENT_DELAY 3'd0; - wci_reqTO_5 <= `BSV_ASSIGNMENT_DELAY 3'd0; - wci_reqTO_6 <= `BSV_ASSIGNMENT_DELAY 3'd0; - wci_reqTO_7 <= `BSV_ASSIGNMENT_DELAY 3'd0; - wci_reqTO_8 <= `BSV_ASSIGNMENT_DELAY 3'd0; - wci_reqTO_9 <= `BSV_ASSIGNMENT_DELAY 3'd0; - wci_respTimr <= `BSV_ASSIGNMENT_DELAY 32'd0; - wci_respTimrAct <= `BSV_ASSIGNMENT_DELAY 1'd0; - wci_respTimrAct_1 <= `BSV_ASSIGNMENT_DELAY 1'd0; - wci_respTimrAct_10 <= `BSV_ASSIGNMENT_DELAY 1'd0; - wci_respTimrAct_11 <= `BSV_ASSIGNMENT_DELAY 1'd0; - wci_respTimrAct_12 <= `BSV_ASSIGNMENT_DELAY 1'd0; - wci_respTimrAct_13 <= `BSV_ASSIGNMENT_DELAY 1'd0; - wci_respTimrAct_14 <= `BSV_ASSIGNMENT_DELAY 1'd0; - wci_respTimrAct_2 <= `BSV_ASSIGNMENT_DELAY 1'd0; - wci_respTimrAct_3 <= `BSV_ASSIGNMENT_DELAY 1'd0; - wci_respTimrAct_4 <= `BSV_ASSIGNMENT_DELAY 1'd0; - wci_respTimrAct_5 <= `BSV_ASSIGNMENT_DELAY 1'd0; - wci_respTimrAct_6 <= `BSV_ASSIGNMENT_DELAY 1'd0; - wci_respTimrAct_7 <= `BSV_ASSIGNMENT_DELAY 1'd0; - wci_respTimrAct_8 <= `BSV_ASSIGNMENT_DELAY 1'd0; - wci_respTimrAct_9 <= `BSV_ASSIGNMENT_DELAY 1'd0; - wci_respTimr_1 <= `BSV_ASSIGNMENT_DELAY 32'd0; - wci_respTimr_10 <= `BSV_ASSIGNMENT_DELAY 32'd0; - wci_respTimr_11 <= `BSV_ASSIGNMENT_DELAY 32'd0; - wci_respTimr_12 <= `BSV_ASSIGNMENT_DELAY 32'd0; - wci_respTimr_13 <= `BSV_ASSIGNMENT_DELAY 32'd0; - wci_respTimr_14 <= `BSV_ASSIGNMENT_DELAY 32'd0; - wci_respTimr_2 <= `BSV_ASSIGNMENT_DELAY 32'd0; - wci_respTimr_3 <= `BSV_ASSIGNMENT_DELAY 32'd0; - wci_respTimr_4 <= `BSV_ASSIGNMENT_DELAY 32'd0; - wci_respTimr_5 <= `BSV_ASSIGNMENT_DELAY 32'd0; - wci_respTimr_6 <= `BSV_ASSIGNMENT_DELAY 32'd0; - wci_respTimr_7 <= `BSV_ASSIGNMENT_DELAY 32'd0; - wci_respTimr_8 <= `BSV_ASSIGNMENT_DELAY 32'd0; - wci_respTimr_9 <= `BSV_ASSIGNMENT_DELAY 32'd0; - wci_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY 1'd1; - wci_sThreadBusy_d_1 <= `BSV_ASSIGNMENT_DELAY 1'd1; - wci_sThreadBusy_d_10 <= `BSV_ASSIGNMENT_DELAY 1'd1; - wci_sThreadBusy_d_11 <= `BSV_ASSIGNMENT_DELAY 1'd1; - wci_sThreadBusy_d_12 <= `BSV_ASSIGNMENT_DELAY 1'd1; - wci_sThreadBusy_d_13 <= `BSV_ASSIGNMENT_DELAY 1'd1; - wci_sThreadBusy_d_14 <= `BSV_ASSIGNMENT_DELAY 1'd1; - wci_sThreadBusy_d_2 <= `BSV_ASSIGNMENT_DELAY 1'd1; - wci_sThreadBusy_d_3 <= `BSV_ASSIGNMENT_DELAY 1'd1; - wci_sThreadBusy_d_4 <= `BSV_ASSIGNMENT_DELAY 1'd1; - wci_sThreadBusy_d_5 <= `BSV_ASSIGNMENT_DELAY 1'd1; - wci_sThreadBusy_d_6 <= `BSV_ASSIGNMENT_DELAY 1'd1; - wci_sThreadBusy_d_7 <= `BSV_ASSIGNMENT_DELAY 1'd1; - wci_sThreadBusy_d_8 <= `BSV_ASSIGNMENT_DELAY 1'd1; - wci_sThreadBusy_d_9 <= `BSV_ASSIGNMENT_DELAY 1'd1; - wci_sfCap <= `BSV_ASSIGNMENT_DELAY 1'd0; - wci_sfCapClear <= `BSV_ASSIGNMENT_DELAY 1'd0; - wci_sfCapClear_10 <= `BSV_ASSIGNMENT_DELAY 1'd0; - wci_sfCapClear_11 <= `BSV_ASSIGNMENT_DELAY 1'd0; - wci_sfCapClear_12 <= `BSV_ASSIGNMENT_DELAY 1'd0; - wci_sfCapClear_13 <= `BSV_ASSIGNMENT_DELAY 1'd0; - wci_sfCapClear_14 <= `BSV_ASSIGNMENT_DELAY 1'd0; - wci_sfCapClear_1_1 <= `BSV_ASSIGNMENT_DELAY 1'd0; - wci_sfCapClear_2 <= `BSV_ASSIGNMENT_DELAY 1'd0; - wci_sfCapClear_3 <= `BSV_ASSIGNMENT_DELAY 1'd0; - wci_sfCapClear_4 <= `BSV_ASSIGNMENT_DELAY 1'd0; - wci_sfCapClear_5 <= `BSV_ASSIGNMENT_DELAY 1'd0; - wci_sfCapClear_6 <= `BSV_ASSIGNMENT_DELAY 1'd0; - wci_sfCapClear_7 <= `BSV_ASSIGNMENT_DELAY 1'd0; - wci_sfCapClear_8 <= `BSV_ASSIGNMENT_DELAY 1'd0; - wci_sfCapClear_9 <= `BSV_ASSIGNMENT_DELAY 1'd0; - wci_sfCapSet <= `BSV_ASSIGNMENT_DELAY 1'd0; - wci_sfCapSet_10 <= `BSV_ASSIGNMENT_DELAY 1'd0; - wci_sfCapSet_11 <= `BSV_ASSIGNMENT_DELAY 1'd0; - wci_sfCapSet_12 <= `BSV_ASSIGNMENT_DELAY 1'd0; - wci_sfCapSet_13 <= `BSV_ASSIGNMENT_DELAY 1'd0; - wci_sfCapSet_14 <= `BSV_ASSIGNMENT_DELAY 1'd0; - wci_sfCapSet_1_1 <= `BSV_ASSIGNMENT_DELAY 1'd0; - wci_sfCapSet_2 <= `BSV_ASSIGNMENT_DELAY 1'd0; - wci_sfCapSet_3 <= `BSV_ASSIGNMENT_DELAY 1'd0; - wci_sfCapSet_4 <= `BSV_ASSIGNMENT_DELAY 1'd0; - wci_sfCapSet_5 <= `BSV_ASSIGNMENT_DELAY 1'd0; - wci_sfCapSet_6 <= `BSV_ASSIGNMENT_DELAY 1'd0; - wci_sfCapSet_7 <= `BSV_ASSIGNMENT_DELAY 1'd0; - wci_sfCapSet_8 <= `BSV_ASSIGNMENT_DELAY 1'd0; - wci_sfCapSet_9 <= `BSV_ASSIGNMENT_DELAY 1'd0; - wci_sfCap_1 <= `BSV_ASSIGNMENT_DELAY 1'd0; - wci_sfCap_10 <= `BSV_ASSIGNMENT_DELAY 1'd0; - wci_sfCap_11 <= `BSV_ASSIGNMENT_DELAY 1'd0; - wci_sfCap_12 <= `BSV_ASSIGNMENT_DELAY 1'd0; - wci_sfCap_13 <= `BSV_ASSIGNMENT_DELAY 1'd0; - wci_sfCap_14 <= `BSV_ASSIGNMENT_DELAY 1'd0; - wci_sfCap_2 <= `BSV_ASSIGNMENT_DELAY 1'd0; - wci_sfCap_3 <= `BSV_ASSIGNMENT_DELAY 1'd0; - wci_sfCap_4 <= `BSV_ASSIGNMENT_DELAY 1'd0; - wci_sfCap_5 <= `BSV_ASSIGNMENT_DELAY 1'd0; - wci_sfCap_6 <= `BSV_ASSIGNMENT_DELAY 1'd0; - wci_sfCap_7 <= `BSV_ASSIGNMENT_DELAY 1'd0; - wci_sfCap_8 <= `BSV_ASSIGNMENT_DELAY 1'd0; - wci_sfCap_9 <= `BSV_ASSIGNMENT_DELAY 1'd0; - wci_slvPresent <= `BSV_ASSIGNMENT_DELAY 1'd0; - wci_slvPresent_1 <= `BSV_ASSIGNMENT_DELAY 1'd0; - wci_slvPresent_10 <= `BSV_ASSIGNMENT_DELAY 1'd0; - wci_slvPresent_11 <= `BSV_ASSIGNMENT_DELAY 1'd0; - wci_slvPresent_12 <= `BSV_ASSIGNMENT_DELAY 1'd0; - wci_slvPresent_13 <= `BSV_ASSIGNMENT_DELAY 1'd0; - wci_slvPresent_14 <= `BSV_ASSIGNMENT_DELAY 1'd0; - wci_slvPresent_2 <= `BSV_ASSIGNMENT_DELAY 1'd0; - wci_slvPresent_3 <= `BSV_ASSIGNMENT_DELAY 1'd0; - wci_slvPresent_4 <= `BSV_ASSIGNMENT_DELAY 1'd0; - wci_slvPresent_5 <= `BSV_ASSIGNMENT_DELAY 1'd0; - wci_slvPresent_6 <= `BSV_ASSIGNMENT_DELAY 1'd0; - wci_slvPresent_7 <= `BSV_ASSIGNMENT_DELAY 1'd0; - wci_slvPresent_8 <= `BSV_ASSIGNMENT_DELAY 1'd0; - wci_slvPresent_9 <= `BSV_ASSIGNMENT_DELAY 1'd0; - wci_wReset_n <= `BSV_ASSIGNMENT_DELAY 1'd0; - wci_wReset_n_1 <= `BSV_ASSIGNMENT_DELAY 1'd0; - wci_wReset_n_10 <= `BSV_ASSIGNMENT_DELAY 1'd0; - wci_wReset_n_11 <= `BSV_ASSIGNMENT_DELAY 1'd0; - wci_wReset_n_12 <= `BSV_ASSIGNMENT_DELAY 1'd0; - wci_wReset_n_13 <= `BSV_ASSIGNMENT_DELAY 1'd0; - wci_wReset_n_14 <= `BSV_ASSIGNMENT_DELAY 1'd0; - wci_wReset_n_2 <= `BSV_ASSIGNMENT_DELAY 1'd0; - wci_wReset_n_3 <= `BSV_ASSIGNMENT_DELAY 1'd0; - wci_wReset_n_4 <= `BSV_ASSIGNMENT_DELAY 1'd0; - wci_wReset_n_5 <= `BSV_ASSIGNMENT_DELAY 1'd0; - wci_wReset_n_6 <= `BSV_ASSIGNMENT_DELAY 1'd0; - wci_wReset_n_7 <= `BSV_ASSIGNMENT_DELAY 1'd0; - wci_wReset_n_8 <= `BSV_ASSIGNMENT_DELAY 1'd0; - wci_wReset_n_9 <= `BSV_ASSIGNMENT_DELAY 1'd0; - wci_wTimeout <= `BSV_ASSIGNMENT_DELAY 5'h04; - wci_wTimeout_1 <= `BSV_ASSIGNMENT_DELAY 5'h04; - wci_wTimeout_10 <= `BSV_ASSIGNMENT_DELAY 5'h04; - wci_wTimeout_11 <= `BSV_ASSIGNMENT_DELAY 5'h04; - wci_wTimeout_12 <= `BSV_ASSIGNMENT_DELAY 5'h04; - wci_wTimeout_13 <= `BSV_ASSIGNMENT_DELAY 5'h04; - wci_wTimeout_14 <= `BSV_ASSIGNMENT_DELAY 5'h04; - wci_wTimeout_2 <= `BSV_ASSIGNMENT_DELAY 5'h04; - wci_wTimeout_3 <= `BSV_ASSIGNMENT_DELAY 5'h04; - wci_wTimeout_4 <= `BSV_ASSIGNMENT_DELAY 5'h04; - wci_wTimeout_5 <= `BSV_ASSIGNMENT_DELAY 5'h04; - wci_wTimeout_6 <= `BSV_ASSIGNMENT_DELAY 5'h04; - wci_wTimeout_7 <= `BSV_ASSIGNMENT_DELAY 5'h04; - wci_wTimeout_8 <= `BSV_ASSIGNMENT_DELAY 5'h04; - wci_wTimeout_9 <= `BSV_ASSIGNMENT_DELAY 5'h04; + wci_0_busy <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_0_lastConfigAddr <= `BSV_ASSIGNMENT_DELAY 33'h0AAAAAAAA; + wci_0_lastConfigBE <= `BSV_ASSIGNMENT_DELAY 5'd10; + wci_0_lastControlOp <= `BSV_ASSIGNMENT_DELAY 4'd2; + wci_0_lastOpWrite <= `BSV_ASSIGNMENT_DELAY 2'd0; + wci_0_mFlagReg <= `BSV_ASSIGNMENT_DELAY 2'b10; + wci_0_pageWindow <= `BSV_ASSIGNMENT_DELAY 12'd0; + wci_0_reqERR <= `BSV_ASSIGNMENT_DELAY 3'd0; + wci_0_reqFAIL <= `BSV_ASSIGNMENT_DELAY 3'd0; + wci_0_reqF_cntr_r <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_0_reqF_q_0 <= `BSV_ASSIGNMENT_DELAY 72'h0000000000AAAAAAAA; + wci_0_reqPend <= `BSV_ASSIGNMENT_DELAY 2'd0; + wci_0_reqTO <= `BSV_ASSIGNMENT_DELAY 3'd0; + wci_0_respTimr <= `BSV_ASSIGNMENT_DELAY 32'd0; + wci_0_respTimrAct <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_0_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY 1'd1; + wci_0_sfCap <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_0_sfCapClear <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_0_sfCapSet <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_0_slvPresent <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_0_wReset_n <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_0_wTimeout <= `BSV_ASSIGNMENT_DELAY 5'h04; + wci_10_busy <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_10_lastConfigAddr <= `BSV_ASSIGNMENT_DELAY 33'h0AAAAAAAA; + wci_10_lastConfigBE <= `BSV_ASSIGNMENT_DELAY 5'd10; + wci_10_lastControlOp <= `BSV_ASSIGNMENT_DELAY 4'd2; + wci_10_lastOpWrite <= `BSV_ASSIGNMENT_DELAY 2'd0; + wci_10_mFlagReg <= `BSV_ASSIGNMENT_DELAY 2'b10; + wci_10_pageWindow <= `BSV_ASSIGNMENT_DELAY 12'd0; + wci_10_reqERR <= `BSV_ASSIGNMENT_DELAY 3'd0; + wci_10_reqFAIL <= `BSV_ASSIGNMENT_DELAY 3'd0; + wci_10_reqF_cntr_r <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_10_reqF_q_0 <= `BSV_ASSIGNMENT_DELAY 72'h0000000000AAAAAAAA; + wci_10_reqPend <= `BSV_ASSIGNMENT_DELAY 2'd0; + wci_10_reqTO <= `BSV_ASSIGNMENT_DELAY 3'd0; + wci_10_respTimr <= `BSV_ASSIGNMENT_DELAY 32'd0; + wci_10_respTimrAct <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_10_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY 1'd1; + wci_10_sfCap <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_10_sfCapClear <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_10_sfCapSet <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_10_slvPresent <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_10_wReset_n <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_10_wTimeout <= `BSV_ASSIGNMENT_DELAY 5'h04; + wci_11_busy <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_11_lastConfigAddr <= `BSV_ASSIGNMENT_DELAY 33'h0AAAAAAAA; + wci_11_lastConfigBE <= `BSV_ASSIGNMENT_DELAY 5'd10; + wci_11_lastControlOp <= `BSV_ASSIGNMENT_DELAY 4'd2; + wci_11_lastOpWrite <= `BSV_ASSIGNMENT_DELAY 2'd0; + wci_11_mFlagReg <= `BSV_ASSIGNMENT_DELAY 2'b10; + wci_11_pageWindow <= `BSV_ASSIGNMENT_DELAY 12'd0; + wci_11_reqERR <= `BSV_ASSIGNMENT_DELAY 3'd0; + wci_11_reqFAIL <= `BSV_ASSIGNMENT_DELAY 3'd0; + wci_11_reqF_cntr_r <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_11_reqF_q_0 <= `BSV_ASSIGNMENT_DELAY 72'h0000000000AAAAAAAA; + wci_11_reqPend <= `BSV_ASSIGNMENT_DELAY 2'd0; + wci_11_reqTO <= `BSV_ASSIGNMENT_DELAY 3'd0; + wci_11_respTimr <= `BSV_ASSIGNMENT_DELAY 32'd0; + wci_11_respTimrAct <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_11_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY 1'd1; + wci_11_sfCap <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_11_sfCapClear <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_11_sfCapSet <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_11_slvPresent <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_11_wReset_n <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_11_wTimeout <= `BSV_ASSIGNMENT_DELAY 5'h04; + wci_12_busy <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_12_lastConfigAddr <= `BSV_ASSIGNMENT_DELAY 33'h0AAAAAAAA; + wci_12_lastConfigBE <= `BSV_ASSIGNMENT_DELAY 5'd10; + wci_12_lastControlOp <= `BSV_ASSIGNMENT_DELAY 4'd2; + wci_12_lastOpWrite <= `BSV_ASSIGNMENT_DELAY 2'd0; + wci_12_mFlagReg <= `BSV_ASSIGNMENT_DELAY 2'b10; + wci_12_pageWindow <= `BSV_ASSIGNMENT_DELAY 12'd0; + wci_12_reqERR <= `BSV_ASSIGNMENT_DELAY 3'd0; + wci_12_reqFAIL <= `BSV_ASSIGNMENT_DELAY 3'd0; + wci_12_reqF_cntr_r <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_12_reqF_q_0 <= `BSV_ASSIGNMENT_DELAY 72'h0000000000AAAAAAAA; + wci_12_reqPend <= `BSV_ASSIGNMENT_DELAY 2'd0; + wci_12_reqTO <= `BSV_ASSIGNMENT_DELAY 3'd0; + wci_12_respTimr <= `BSV_ASSIGNMENT_DELAY 32'd0; + wci_12_respTimrAct <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_12_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY 1'd1; + wci_12_sfCap <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_12_sfCapClear <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_12_sfCapSet <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_12_slvPresent <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_12_wReset_n <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_12_wTimeout <= `BSV_ASSIGNMENT_DELAY 5'h04; + wci_13_busy <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_13_lastConfigAddr <= `BSV_ASSIGNMENT_DELAY 33'h0AAAAAAAA; + wci_13_lastConfigBE <= `BSV_ASSIGNMENT_DELAY 5'd10; + wci_13_lastControlOp <= `BSV_ASSIGNMENT_DELAY 4'd2; + wci_13_lastOpWrite <= `BSV_ASSIGNMENT_DELAY 2'd0; + wci_13_mFlagReg <= `BSV_ASSIGNMENT_DELAY 2'b10; + wci_13_pageWindow <= `BSV_ASSIGNMENT_DELAY 12'd0; + wci_13_reqERR <= `BSV_ASSIGNMENT_DELAY 3'd0; + wci_13_reqFAIL <= `BSV_ASSIGNMENT_DELAY 3'd0; + wci_13_reqF_cntr_r <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_13_reqF_q_0 <= `BSV_ASSIGNMENT_DELAY 72'h0000000000AAAAAAAA; + wci_13_reqPend <= `BSV_ASSIGNMENT_DELAY 2'd0; + wci_13_reqTO <= `BSV_ASSIGNMENT_DELAY 3'd0; + wci_13_respTimr <= `BSV_ASSIGNMENT_DELAY 32'd0; + wci_13_respTimrAct <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_13_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY 1'd1; + wci_13_sfCap <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_13_sfCapClear <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_13_sfCapSet <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_13_slvPresent <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_13_wReset_n <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_13_wTimeout <= `BSV_ASSIGNMENT_DELAY 5'h04; + wci_14_busy <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_14_lastConfigAddr <= `BSV_ASSIGNMENT_DELAY 33'h0AAAAAAAA; + wci_14_lastConfigBE <= `BSV_ASSIGNMENT_DELAY 5'd10; + wci_14_lastControlOp <= `BSV_ASSIGNMENT_DELAY 4'd2; + wci_14_lastOpWrite <= `BSV_ASSIGNMENT_DELAY 2'd0; + wci_14_mFlagReg <= `BSV_ASSIGNMENT_DELAY 2'b10; + wci_14_pageWindow <= `BSV_ASSIGNMENT_DELAY 12'd0; + wci_14_reqERR <= `BSV_ASSIGNMENT_DELAY 3'd0; + wci_14_reqFAIL <= `BSV_ASSIGNMENT_DELAY 3'd0; + wci_14_reqF_cntr_r <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_14_reqF_q_0 <= `BSV_ASSIGNMENT_DELAY 72'h0000000000AAAAAAAA; + wci_14_reqPend <= `BSV_ASSIGNMENT_DELAY 2'd0; + wci_14_reqTO <= `BSV_ASSIGNMENT_DELAY 3'd0; + wci_14_respTimr <= `BSV_ASSIGNMENT_DELAY 32'd0; + wci_14_respTimrAct <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_14_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY 1'd1; + wci_14_sfCap <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_14_sfCapClear <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_14_sfCapSet <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_14_slvPresent <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_14_wReset_n <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_14_wTimeout <= `BSV_ASSIGNMENT_DELAY 5'h04; + wci_1_busy <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_1_lastConfigAddr <= `BSV_ASSIGNMENT_DELAY 33'h0AAAAAAAA; + wci_1_lastConfigBE <= `BSV_ASSIGNMENT_DELAY 5'd10; + wci_1_lastControlOp <= `BSV_ASSIGNMENT_DELAY 4'd2; + wci_1_lastOpWrite <= `BSV_ASSIGNMENT_DELAY 2'd0; + wci_1_mFlagReg <= `BSV_ASSIGNMENT_DELAY 2'b10; + wci_1_pageWindow <= `BSV_ASSIGNMENT_DELAY 12'd0; + wci_1_reqERR <= `BSV_ASSIGNMENT_DELAY 3'd0; + wci_1_reqFAIL <= `BSV_ASSIGNMENT_DELAY 3'd0; + wci_1_reqF_cntr_r <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_1_reqF_q_0 <= `BSV_ASSIGNMENT_DELAY 72'h0000000000AAAAAAAA; + wci_1_reqPend <= `BSV_ASSIGNMENT_DELAY 2'd0; + wci_1_reqTO <= `BSV_ASSIGNMENT_DELAY 3'd0; + wci_1_respTimr <= `BSV_ASSIGNMENT_DELAY 32'd0; + wci_1_respTimrAct <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_1_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY 1'd1; + wci_1_sfCap <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_1_sfCapClear <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_1_sfCapSet <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_1_slvPresent <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_1_wReset_n <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_1_wTimeout <= `BSV_ASSIGNMENT_DELAY 5'h04; + wci_2_busy <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_2_lastConfigAddr <= `BSV_ASSIGNMENT_DELAY 33'h0AAAAAAAA; + wci_2_lastConfigBE <= `BSV_ASSIGNMENT_DELAY 5'd10; + wci_2_lastControlOp <= `BSV_ASSIGNMENT_DELAY 4'd2; + wci_2_lastOpWrite <= `BSV_ASSIGNMENT_DELAY 2'd0; + wci_2_mFlagReg <= `BSV_ASSIGNMENT_DELAY 2'b10; + wci_2_pageWindow <= `BSV_ASSIGNMENT_DELAY 12'd0; + wci_2_reqERR <= `BSV_ASSIGNMENT_DELAY 3'd0; + wci_2_reqFAIL <= `BSV_ASSIGNMENT_DELAY 3'd0; + wci_2_reqF_cntr_r <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_2_reqF_q_0 <= `BSV_ASSIGNMENT_DELAY 72'h0000000000AAAAAAAA; + wci_2_reqPend <= `BSV_ASSIGNMENT_DELAY 2'd0; + wci_2_reqTO <= `BSV_ASSIGNMENT_DELAY 3'd0; + wci_2_respTimr <= `BSV_ASSIGNMENT_DELAY 32'd0; + wci_2_respTimrAct <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_2_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY 1'd1; + wci_2_sfCap <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_2_sfCapClear <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_2_sfCapSet <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_2_slvPresent <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_2_wReset_n <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_2_wTimeout <= `BSV_ASSIGNMENT_DELAY 5'h04; + wci_3_busy <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_3_lastConfigAddr <= `BSV_ASSIGNMENT_DELAY 33'h0AAAAAAAA; + wci_3_lastConfigBE <= `BSV_ASSIGNMENT_DELAY 5'd10; + wci_3_lastControlOp <= `BSV_ASSIGNMENT_DELAY 4'd2; + wci_3_lastOpWrite <= `BSV_ASSIGNMENT_DELAY 2'd0; + wci_3_mFlagReg <= `BSV_ASSIGNMENT_DELAY 2'b10; + wci_3_pageWindow <= `BSV_ASSIGNMENT_DELAY 12'd0; + wci_3_reqERR <= `BSV_ASSIGNMENT_DELAY 3'd0; + wci_3_reqFAIL <= `BSV_ASSIGNMENT_DELAY 3'd0; + wci_3_reqF_cntr_r <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_3_reqF_q_0 <= `BSV_ASSIGNMENT_DELAY 72'h0000000000AAAAAAAA; + wci_3_reqPend <= `BSV_ASSIGNMENT_DELAY 2'd0; + wci_3_reqTO <= `BSV_ASSIGNMENT_DELAY 3'd0; + wci_3_respTimr <= `BSV_ASSIGNMENT_DELAY 32'd0; + wci_3_respTimrAct <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_3_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY 1'd1; + wci_3_sfCap <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_3_sfCapClear <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_3_sfCapSet <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_3_slvPresent <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_3_wReset_n <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_3_wTimeout <= `BSV_ASSIGNMENT_DELAY 5'h04; + wci_4_busy <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_4_lastConfigAddr <= `BSV_ASSIGNMENT_DELAY 33'h0AAAAAAAA; + wci_4_lastConfigBE <= `BSV_ASSIGNMENT_DELAY 5'd10; + wci_4_lastControlOp <= `BSV_ASSIGNMENT_DELAY 4'd2; + wci_4_lastOpWrite <= `BSV_ASSIGNMENT_DELAY 2'd0; + wci_4_mFlagReg <= `BSV_ASSIGNMENT_DELAY 2'b10; + wci_4_pageWindow <= `BSV_ASSIGNMENT_DELAY 12'd0; + wci_4_reqERR <= `BSV_ASSIGNMENT_DELAY 3'd0; + wci_4_reqFAIL <= `BSV_ASSIGNMENT_DELAY 3'd0; + wci_4_reqF_cntr_r <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_4_reqF_q_0 <= `BSV_ASSIGNMENT_DELAY 72'h0000000000AAAAAAAA; + wci_4_reqPend <= `BSV_ASSIGNMENT_DELAY 2'd0; + wci_4_reqTO <= `BSV_ASSIGNMENT_DELAY 3'd0; + wci_4_respTimr <= `BSV_ASSIGNMENT_DELAY 32'd0; + wci_4_respTimrAct <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_4_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY 1'd1; + wci_4_sfCap <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_4_sfCapClear <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_4_sfCapSet <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_4_slvPresent <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_4_wReset_n <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_4_wTimeout <= `BSV_ASSIGNMENT_DELAY 5'h04; + wci_5_busy <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_5_lastConfigAddr <= `BSV_ASSIGNMENT_DELAY 33'h0AAAAAAAA; + wci_5_lastConfigBE <= `BSV_ASSIGNMENT_DELAY 5'd10; + wci_5_lastControlOp <= `BSV_ASSIGNMENT_DELAY 4'd2; + wci_5_lastOpWrite <= `BSV_ASSIGNMENT_DELAY 2'd0; + wci_5_mFlagReg <= `BSV_ASSIGNMENT_DELAY 2'b10; + wci_5_pageWindow <= `BSV_ASSIGNMENT_DELAY 12'd0; + wci_5_reqERR <= `BSV_ASSIGNMENT_DELAY 3'd0; + wci_5_reqFAIL <= `BSV_ASSIGNMENT_DELAY 3'd0; + wci_5_reqF_cntr_r <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_5_reqF_q_0 <= `BSV_ASSIGNMENT_DELAY 72'h0000000000AAAAAAAA; + wci_5_reqPend <= `BSV_ASSIGNMENT_DELAY 2'd0; + wci_5_reqTO <= `BSV_ASSIGNMENT_DELAY 3'd0; + wci_5_respTimr <= `BSV_ASSIGNMENT_DELAY 32'd0; + wci_5_respTimrAct <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_5_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY 1'd1; + wci_5_sfCap <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_5_sfCapClear <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_5_sfCapSet <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_5_slvPresent <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_5_wReset_n <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_5_wTimeout <= `BSV_ASSIGNMENT_DELAY 5'h04; + wci_6_busy <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_6_lastConfigAddr <= `BSV_ASSIGNMENT_DELAY 33'h0AAAAAAAA; + wci_6_lastConfigBE <= `BSV_ASSIGNMENT_DELAY 5'd10; + wci_6_lastControlOp <= `BSV_ASSIGNMENT_DELAY 4'd2; + wci_6_lastOpWrite <= `BSV_ASSIGNMENT_DELAY 2'd0; + wci_6_mFlagReg <= `BSV_ASSIGNMENT_DELAY 2'b10; + wci_6_pageWindow <= `BSV_ASSIGNMENT_DELAY 12'd0; + wci_6_reqERR <= `BSV_ASSIGNMENT_DELAY 3'd0; + wci_6_reqFAIL <= `BSV_ASSIGNMENT_DELAY 3'd0; + wci_6_reqF_cntr_r <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_6_reqF_q_0 <= `BSV_ASSIGNMENT_DELAY 72'h0000000000AAAAAAAA; + wci_6_reqPend <= `BSV_ASSIGNMENT_DELAY 2'd0; + wci_6_reqTO <= `BSV_ASSIGNMENT_DELAY 3'd0; + wci_6_respTimr <= `BSV_ASSIGNMENT_DELAY 32'd0; + wci_6_respTimrAct <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_6_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY 1'd1; + wci_6_sfCap <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_6_sfCapClear <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_6_sfCapSet <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_6_slvPresent <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_6_wReset_n <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_6_wTimeout <= `BSV_ASSIGNMENT_DELAY 5'h04; + wci_7_busy <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_7_lastConfigAddr <= `BSV_ASSIGNMENT_DELAY 33'h0AAAAAAAA; + wci_7_lastConfigBE <= `BSV_ASSIGNMENT_DELAY 5'd10; + wci_7_lastControlOp <= `BSV_ASSIGNMENT_DELAY 4'd2; + wci_7_lastOpWrite <= `BSV_ASSIGNMENT_DELAY 2'd0; + wci_7_mFlagReg <= `BSV_ASSIGNMENT_DELAY 2'b10; + wci_7_pageWindow <= `BSV_ASSIGNMENT_DELAY 12'd0; + wci_7_reqERR <= `BSV_ASSIGNMENT_DELAY 3'd0; + wci_7_reqFAIL <= `BSV_ASSIGNMENT_DELAY 3'd0; + wci_7_reqF_cntr_r <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_7_reqF_q_0 <= `BSV_ASSIGNMENT_DELAY 72'h0000000000AAAAAAAA; + wci_7_reqPend <= `BSV_ASSIGNMENT_DELAY 2'd0; + wci_7_reqTO <= `BSV_ASSIGNMENT_DELAY 3'd0; + wci_7_respTimr <= `BSV_ASSIGNMENT_DELAY 32'd0; + wci_7_respTimrAct <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_7_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY 1'd1; + wci_7_sfCap <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_7_sfCapClear <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_7_sfCapSet <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_7_slvPresent <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_7_wReset_n <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_7_wTimeout <= `BSV_ASSIGNMENT_DELAY 5'h04; + wci_8_busy <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_8_lastConfigAddr <= `BSV_ASSIGNMENT_DELAY 33'h0AAAAAAAA; + wci_8_lastConfigBE <= `BSV_ASSIGNMENT_DELAY 5'd10; + wci_8_lastControlOp <= `BSV_ASSIGNMENT_DELAY 4'd2; + wci_8_lastOpWrite <= `BSV_ASSIGNMENT_DELAY 2'd0; + wci_8_mFlagReg <= `BSV_ASSIGNMENT_DELAY 2'b10; + wci_8_pageWindow <= `BSV_ASSIGNMENT_DELAY 12'd0; + wci_8_reqERR <= `BSV_ASSIGNMENT_DELAY 3'd0; + wci_8_reqFAIL <= `BSV_ASSIGNMENT_DELAY 3'd0; + wci_8_reqF_cntr_r <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_8_reqF_q_0 <= `BSV_ASSIGNMENT_DELAY 72'h0000000000AAAAAAAA; + wci_8_reqPend <= `BSV_ASSIGNMENT_DELAY 2'd0; + wci_8_reqTO <= `BSV_ASSIGNMENT_DELAY 3'd0; + wci_8_respTimr <= `BSV_ASSIGNMENT_DELAY 32'd0; + wci_8_respTimrAct <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_8_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY 1'd1; + wci_8_sfCap <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_8_sfCapClear <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_8_sfCapSet <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_8_slvPresent <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_8_wReset_n <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_8_wTimeout <= `BSV_ASSIGNMENT_DELAY 5'h04; + wci_9_busy <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_9_lastConfigAddr <= `BSV_ASSIGNMENT_DELAY 33'h0AAAAAAAA; + wci_9_lastConfigBE <= `BSV_ASSIGNMENT_DELAY 5'd10; + wci_9_lastControlOp <= `BSV_ASSIGNMENT_DELAY 4'd2; + wci_9_lastOpWrite <= `BSV_ASSIGNMENT_DELAY 2'd0; + wci_9_mFlagReg <= `BSV_ASSIGNMENT_DELAY 2'b10; + wci_9_pageWindow <= `BSV_ASSIGNMENT_DELAY 12'd0; + wci_9_reqERR <= `BSV_ASSIGNMENT_DELAY 3'd0; + wci_9_reqFAIL <= `BSV_ASSIGNMENT_DELAY 3'd0; + wci_9_reqF_cntr_r <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_9_reqF_q_0 <= `BSV_ASSIGNMENT_DELAY 72'h0000000000AAAAAAAA; + wci_9_reqPend <= `BSV_ASSIGNMENT_DELAY 2'd0; + wci_9_reqTO <= `BSV_ASSIGNMENT_DELAY 3'd0; + wci_9_respTimr <= `BSV_ASSIGNMENT_DELAY 32'd0; + wci_9_respTimrAct <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_9_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY 1'd1; + wci_9_sfCap <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_9_sfCapClear <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_9_sfCapSet <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_9_slvPresent <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_9_wReset_n <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_9_wTimeout <= `BSV_ASSIGNMENT_DELAY 5'h04; wrkAct <= `BSV_ASSIGNMENT_DELAY 4'd0; end else @@ -18125,6 +24835,11 @@ module mkOCCP(pciDevice, if (deltaTime$EN) deltaTime <= `BSV_ASSIGNMENT_DELAY deltaTime$D_IN; if (dispatched$EN) dispatched <= `BSV_ASSIGNMENT_DELAY dispatched$D_IN; + if (dna_cnt$EN) dna_cnt <= `BSV_ASSIGNMENT_DELAY dna_cnt$D_IN; + if (dna_rdReg$EN) dna_rdReg <= `BSV_ASSIGNMENT_DELAY dna_rdReg$D_IN; + if (dna_shftReg$EN) + dna_shftReg <= `BSV_ASSIGNMENT_DELAY dna_shftReg$D_IN; + if (dna_sr$EN) dna_sr <= `BSV_ASSIGNMENT_DELAY dna_sr$D_IN; if (readCntReg$EN) readCntReg <= `BSV_ASSIGNMENT_DELAY readCntReg$D_IN; if (rogueTLP$EN) rogueTLP <= `BSV_ASSIGNMENT_DELAY rogueTLP$D_IN; @@ -18153,744 +24868,751 @@ module mkOCCP(pciDevice, timeServ_timeSetSticky$D_IN; if (warmResetP$EN) warmResetP <= `BSV_ASSIGNMENT_DELAY warmResetP$D_IN; - if (wci_busy$EN) wci_busy <= `BSV_ASSIGNMENT_DELAY wci_busy$D_IN; - if (wci_busy_1$EN) - wci_busy_1 <= `BSV_ASSIGNMENT_DELAY wci_busy_1$D_IN; - if (wci_busy_10$EN) - wci_busy_10 <= `BSV_ASSIGNMENT_DELAY wci_busy_10$D_IN; - if (wci_busy_11$EN) - wci_busy_11 <= `BSV_ASSIGNMENT_DELAY wci_busy_11$D_IN; - if (wci_busy_12$EN) - wci_busy_12 <= `BSV_ASSIGNMENT_DELAY wci_busy_12$D_IN; - if (wci_busy_13$EN) - wci_busy_13 <= `BSV_ASSIGNMENT_DELAY wci_busy_13$D_IN; - if (wci_busy_14$EN) - wci_busy_14 <= `BSV_ASSIGNMENT_DELAY wci_busy_14$D_IN; - if (wci_busy_2$EN) - wci_busy_2 <= `BSV_ASSIGNMENT_DELAY wci_busy_2$D_IN; - if (wci_busy_3$EN) - wci_busy_3 <= `BSV_ASSIGNMENT_DELAY wci_busy_3$D_IN; - if (wci_busy_4$EN) - wci_busy_4 <= `BSV_ASSIGNMENT_DELAY wci_busy_4$D_IN; - if (wci_busy_5$EN) - wci_busy_5 <= `BSV_ASSIGNMENT_DELAY wci_busy_5$D_IN; - if (wci_busy_6$EN) - wci_busy_6 <= `BSV_ASSIGNMENT_DELAY wci_busy_6$D_IN; - if (wci_busy_7$EN) - wci_busy_7 <= `BSV_ASSIGNMENT_DELAY wci_busy_7$D_IN; - if (wci_busy_8$EN) - wci_busy_8 <= `BSV_ASSIGNMENT_DELAY wci_busy_8$D_IN; - if (wci_busy_9$EN) - wci_busy_9 <= `BSV_ASSIGNMENT_DELAY wci_busy_9$D_IN; - if (wci_lastConfigAddr$EN) - wci_lastConfigAddr <= `BSV_ASSIGNMENT_DELAY wci_lastConfigAddr$D_IN; - if (wci_lastConfigAddr_1$EN) - wci_lastConfigAddr_1 <= `BSV_ASSIGNMENT_DELAY - wci_lastConfigAddr_1$D_IN; - if (wci_lastConfigAddr_10$EN) - wci_lastConfigAddr_10 <= `BSV_ASSIGNMENT_DELAY - wci_lastConfigAddr_10$D_IN; - if (wci_lastConfigAddr_11$EN) - wci_lastConfigAddr_11 <= `BSV_ASSIGNMENT_DELAY - wci_lastConfigAddr_11$D_IN; - if (wci_lastConfigAddr_12$EN) - wci_lastConfigAddr_12 <= `BSV_ASSIGNMENT_DELAY - wci_lastConfigAddr_12$D_IN; - if (wci_lastConfigAddr_13$EN) - wci_lastConfigAddr_13 <= `BSV_ASSIGNMENT_DELAY - wci_lastConfigAddr_13$D_IN; - if (wci_lastConfigAddr_14$EN) - wci_lastConfigAddr_14 <= `BSV_ASSIGNMENT_DELAY - wci_lastConfigAddr_14$D_IN; - if (wci_lastConfigAddr_2$EN) - wci_lastConfigAddr_2 <= `BSV_ASSIGNMENT_DELAY - wci_lastConfigAddr_2$D_IN; - if (wci_lastConfigAddr_3$EN) - wci_lastConfigAddr_3 <= `BSV_ASSIGNMENT_DELAY - wci_lastConfigAddr_3$D_IN; - if (wci_lastConfigAddr_4$EN) - wci_lastConfigAddr_4 <= `BSV_ASSIGNMENT_DELAY - wci_lastConfigAddr_4$D_IN; - if (wci_lastConfigAddr_5$EN) - wci_lastConfigAddr_5 <= `BSV_ASSIGNMENT_DELAY - wci_lastConfigAddr_5$D_IN; - if (wci_lastConfigAddr_6$EN) - wci_lastConfigAddr_6 <= `BSV_ASSIGNMENT_DELAY - wci_lastConfigAddr_6$D_IN; - if (wci_lastConfigAddr_7$EN) - wci_lastConfigAddr_7 <= `BSV_ASSIGNMENT_DELAY - wci_lastConfigAddr_7$D_IN; - if (wci_lastConfigAddr_8$EN) - wci_lastConfigAddr_8 <= `BSV_ASSIGNMENT_DELAY - wci_lastConfigAddr_8$D_IN; - if (wci_lastConfigAddr_9$EN) - wci_lastConfigAddr_9 <= `BSV_ASSIGNMENT_DELAY - wci_lastConfigAddr_9$D_IN; - if (wci_lastConfigBE$EN) - wci_lastConfigBE <= `BSV_ASSIGNMENT_DELAY wci_lastConfigBE$D_IN; - if (wci_lastConfigBE_1$EN) - wci_lastConfigBE_1 <= `BSV_ASSIGNMENT_DELAY wci_lastConfigBE_1$D_IN; - if (wci_lastConfigBE_10$EN) - wci_lastConfigBE_10 <= `BSV_ASSIGNMENT_DELAY - wci_lastConfigBE_10$D_IN; - if (wci_lastConfigBE_11$EN) - wci_lastConfigBE_11 <= `BSV_ASSIGNMENT_DELAY - wci_lastConfigBE_11$D_IN; - if (wci_lastConfigBE_12$EN) - wci_lastConfigBE_12 <= `BSV_ASSIGNMENT_DELAY - wci_lastConfigBE_12$D_IN; - if (wci_lastConfigBE_13$EN) - wci_lastConfigBE_13 <= `BSV_ASSIGNMENT_DELAY - wci_lastConfigBE_13$D_IN; - if (wci_lastConfigBE_14$EN) - wci_lastConfigBE_14 <= `BSV_ASSIGNMENT_DELAY - wci_lastConfigBE_14$D_IN; - if (wci_lastConfigBE_2$EN) - wci_lastConfigBE_2 <= `BSV_ASSIGNMENT_DELAY wci_lastConfigBE_2$D_IN; - if (wci_lastConfigBE_3$EN) - wci_lastConfigBE_3 <= `BSV_ASSIGNMENT_DELAY wci_lastConfigBE_3$D_IN; - if (wci_lastConfigBE_4$EN) - wci_lastConfigBE_4 <= `BSV_ASSIGNMENT_DELAY wci_lastConfigBE_4$D_IN; - if (wci_lastConfigBE_5$EN) - wci_lastConfigBE_5 <= `BSV_ASSIGNMENT_DELAY wci_lastConfigBE_5$D_IN; - if (wci_lastConfigBE_6$EN) - wci_lastConfigBE_6 <= `BSV_ASSIGNMENT_DELAY wci_lastConfigBE_6$D_IN; - if (wci_lastConfigBE_7$EN) - wci_lastConfigBE_7 <= `BSV_ASSIGNMENT_DELAY wci_lastConfigBE_7$D_IN; - if (wci_lastConfigBE_8$EN) - wci_lastConfigBE_8 <= `BSV_ASSIGNMENT_DELAY wci_lastConfigBE_8$D_IN; - if (wci_lastConfigBE_9$EN) - wci_lastConfigBE_9 <= `BSV_ASSIGNMENT_DELAY wci_lastConfigBE_9$D_IN; - if (wci_lastControlOp$EN) - wci_lastControlOp <= `BSV_ASSIGNMENT_DELAY wci_lastControlOp$D_IN; - if (wci_lastControlOp_1$EN) - wci_lastControlOp_1 <= `BSV_ASSIGNMENT_DELAY - wci_lastControlOp_1$D_IN; - if (wci_lastControlOp_10$EN) - wci_lastControlOp_10 <= `BSV_ASSIGNMENT_DELAY - wci_lastControlOp_10$D_IN; - if (wci_lastControlOp_11$EN) - wci_lastControlOp_11 <= `BSV_ASSIGNMENT_DELAY - wci_lastControlOp_11$D_IN; - if (wci_lastControlOp_12$EN) - wci_lastControlOp_12 <= `BSV_ASSIGNMENT_DELAY - wci_lastControlOp_12$D_IN; - if (wci_lastControlOp_13$EN) - wci_lastControlOp_13 <= `BSV_ASSIGNMENT_DELAY - wci_lastControlOp_13$D_IN; - if (wci_lastControlOp_14$EN) - wci_lastControlOp_14 <= `BSV_ASSIGNMENT_DELAY - wci_lastControlOp_14$D_IN; - if (wci_lastControlOp_2$EN) - wci_lastControlOp_2 <= `BSV_ASSIGNMENT_DELAY - wci_lastControlOp_2$D_IN; - if (wci_lastControlOp_3$EN) - wci_lastControlOp_3 <= `BSV_ASSIGNMENT_DELAY - wci_lastControlOp_3$D_IN; - if (wci_lastControlOp_4$EN) - wci_lastControlOp_4 <= `BSV_ASSIGNMENT_DELAY - wci_lastControlOp_4$D_IN; - if (wci_lastControlOp_5$EN) - wci_lastControlOp_5 <= `BSV_ASSIGNMENT_DELAY - wci_lastControlOp_5$D_IN; - if (wci_lastControlOp_6$EN) - wci_lastControlOp_6 <= `BSV_ASSIGNMENT_DELAY - wci_lastControlOp_6$D_IN; - if (wci_lastControlOp_7$EN) - wci_lastControlOp_7 <= `BSV_ASSIGNMENT_DELAY - wci_lastControlOp_7$D_IN; - if (wci_lastControlOp_8$EN) - wci_lastControlOp_8 <= `BSV_ASSIGNMENT_DELAY - wci_lastControlOp_8$D_IN; - if (wci_lastControlOp_9$EN) - wci_lastControlOp_9 <= `BSV_ASSIGNMENT_DELAY - wci_lastControlOp_9$D_IN; - if (wci_lastOpWrite$EN) - wci_lastOpWrite <= `BSV_ASSIGNMENT_DELAY wci_lastOpWrite$D_IN; - if (wci_lastOpWrite_1$EN) - wci_lastOpWrite_1 <= `BSV_ASSIGNMENT_DELAY wci_lastOpWrite_1$D_IN; - if (wci_lastOpWrite_10$EN) - wci_lastOpWrite_10 <= `BSV_ASSIGNMENT_DELAY wci_lastOpWrite_10$D_IN; - if (wci_lastOpWrite_11$EN) - wci_lastOpWrite_11 <= `BSV_ASSIGNMENT_DELAY wci_lastOpWrite_11$D_IN; - if (wci_lastOpWrite_12$EN) - wci_lastOpWrite_12 <= `BSV_ASSIGNMENT_DELAY wci_lastOpWrite_12$D_IN; - if (wci_lastOpWrite_13$EN) - wci_lastOpWrite_13 <= `BSV_ASSIGNMENT_DELAY wci_lastOpWrite_13$D_IN; - if (wci_lastOpWrite_14$EN) - wci_lastOpWrite_14 <= `BSV_ASSIGNMENT_DELAY wci_lastOpWrite_14$D_IN; - if (wci_lastOpWrite_2$EN) - wci_lastOpWrite_2 <= `BSV_ASSIGNMENT_DELAY wci_lastOpWrite_2$D_IN; - if (wci_lastOpWrite_3$EN) - wci_lastOpWrite_3 <= `BSV_ASSIGNMENT_DELAY wci_lastOpWrite_3$D_IN; - if (wci_lastOpWrite_4$EN) - wci_lastOpWrite_4 <= `BSV_ASSIGNMENT_DELAY wci_lastOpWrite_4$D_IN; - if (wci_lastOpWrite_5$EN) - wci_lastOpWrite_5 <= `BSV_ASSIGNMENT_DELAY wci_lastOpWrite_5$D_IN; - if (wci_lastOpWrite_6$EN) - wci_lastOpWrite_6 <= `BSV_ASSIGNMENT_DELAY wci_lastOpWrite_6$D_IN; - if (wci_lastOpWrite_7$EN) - wci_lastOpWrite_7 <= `BSV_ASSIGNMENT_DELAY wci_lastOpWrite_7$D_IN; - if (wci_lastOpWrite_8$EN) - wci_lastOpWrite_8 <= `BSV_ASSIGNMENT_DELAY wci_lastOpWrite_8$D_IN; - if (wci_lastOpWrite_9$EN) - wci_lastOpWrite_9 <= `BSV_ASSIGNMENT_DELAY wci_lastOpWrite_9$D_IN; - if (wci_mFlagReg$EN) - wci_mFlagReg <= `BSV_ASSIGNMENT_DELAY wci_mFlagReg$D_IN; - if (wci_mFlagReg_1$EN) - wci_mFlagReg_1 <= `BSV_ASSIGNMENT_DELAY wci_mFlagReg_1$D_IN; - if (wci_mFlagReg_10$EN) - wci_mFlagReg_10 <= `BSV_ASSIGNMENT_DELAY wci_mFlagReg_10$D_IN; - if (wci_mFlagReg_11$EN) - wci_mFlagReg_11 <= `BSV_ASSIGNMENT_DELAY wci_mFlagReg_11$D_IN; - if (wci_mFlagReg_12$EN) - wci_mFlagReg_12 <= `BSV_ASSIGNMENT_DELAY wci_mFlagReg_12$D_IN; - if (wci_mFlagReg_13$EN) - wci_mFlagReg_13 <= `BSV_ASSIGNMENT_DELAY wci_mFlagReg_13$D_IN; - if (wci_mFlagReg_14$EN) - wci_mFlagReg_14 <= `BSV_ASSIGNMENT_DELAY wci_mFlagReg_14$D_IN; - if (wci_mFlagReg_2$EN) - wci_mFlagReg_2 <= `BSV_ASSIGNMENT_DELAY wci_mFlagReg_2$D_IN; - if (wci_mFlagReg_3$EN) - wci_mFlagReg_3 <= `BSV_ASSIGNMENT_DELAY wci_mFlagReg_3$D_IN; - if (wci_mFlagReg_4$EN) - wci_mFlagReg_4 <= `BSV_ASSIGNMENT_DELAY wci_mFlagReg_4$D_IN; - if (wci_mFlagReg_5$EN) - wci_mFlagReg_5 <= `BSV_ASSIGNMENT_DELAY wci_mFlagReg_5$D_IN; - if (wci_mFlagReg_6$EN) - wci_mFlagReg_6 <= `BSV_ASSIGNMENT_DELAY wci_mFlagReg_6$D_IN; - if (wci_mFlagReg_7$EN) - wci_mFlagReg_7 <= `BSV_ASSIGNMENT_DELAY wci_mFlagReg_7$D_IN; - if (wci_mFlagReg_8$EN) - wci_mFlagReg_8 <= `BSV_ASSIGNMENT_DELAY wci_mFlagReg_8$D_IN; - if (wci_mFlagReg_9$EN) - wci_mFlagReg_9 <= `BSV_ASSIGNMENT_DELAY wci_mFlagReg_9$D_IN; - if (wci_pageWindow$EN) - wci_pageWindow <= `BSV_ASSIGNMENT_DELAY wci_pageWindow$D_IN; - if (wci_pageWindow_1$EN) - wci_pageWindow_1 <= `BSV_ASSIGNMENT_DELAY wci_pageWindow_1$D_IN; - if (wci_pageWindow_10$EN) - wci_pageWindow_10 <= `BSV_ASSIGNMENT_DELAY wci_pageWindow_10$D_IN; - if (wci_pageWindow_11$EN) - wci_pageWindow_11 <= `BSV_ASSIGNMENT_DELAY wci_pageWindow_11$D_IN; - if (wci_pageWindow_12$EN) - wci_pageWindow_12 <= `BSV_ASSIGNMENT_DELAY wci_pageWindow_12$D_IN; - if (wci_pageWindow_13$EN) - wci_pageWindow_13 <= `BSV_ASSIGNMENT_DELAY wci_pageWindow_13$D_IN; - if (wci_pageWindow_14$EN) - wci_pageWindow_14 <= `BSV_ASSIGNMENT_DELAY wci_pageWindow_14$D_IN; - if (wci_pageWindow_2$EN) - wci_pageWindow_2 <= `BSV_ASSIGNMENT_DELAY wci_pageWindow_2$D_IN; - if (wci_pageWindow_3$EN) - wci_pageWindow_3 <= `BSV_ASSIGNMENT_DELAY wci_pageWindow_3$D_IN; - if (wci_pageWindow_4$EN) - wci_pageWindow_4 <= `BSV_ASSIGNMENT_DELAY wci_pageWindow_4$D_IN; - if (wci_pageWindow_5$EN) - wci_pageWindow_5 <= `BSV_ASSIGNMENT_DELAY wci_pageWindow_5$D_IN; - if (wci_pageWindow_6$EN) - wci_pageWindow_6 <= `BSV_ASSIGNMENT_DELAY wci_pageWindow_6$D_IN; - if (wci_pageWindow_7$EN) - wci_pageWindow_7 <= `BSV_ASSIGNMENT_DELAY wci_pageWindow_7$D_IN; - if (wci_pageWindow_8$EN) - wci_pageWindow_8 <= `BSV_ASSIGNMENT_DELAY wci_pageWindow_8$D_IN; - if (wci_pageWindow_9$EN) - wci_pageWindow_9 <= `BSV_ASSIGNMENT_DELAY wci_pageWindow_9$D_IN; - if (wci_reqERR$EN) - wci_reqERR <= `BSV_ASSIGNMENT_DELAY wci_reqERR$D_IN; - if (wci_reqERR_1$EN) - wci_reqERR_1 <= `BSV_ASSIGNMENT_DELAY wci_reqERR_1$D_IN; - if (wci_reqERR_10$EN) - wci_reqERR_10 <= `BSV_ASSIGNMENT_DELAY wci_reqERR_10$D_IN; - if (wci_reqERR_11$EN) - wci_reqERR_11 <= `BSV_ASSIGNMENT_DELAY wci_reqERR_11$D_IN; - if (wci_reqERR_12$EN) - wci_reqERR_12 <= `BSV_ASSIGNMENT_DELAY wci_reqERR_12$D_IN; - if (wci_reqERR_13$EN) - wci_reqERR_13 <= `BSV_ASSIGNMENT_DELAY wci_reqERR_13$D_IN; - if (wci_reqERR_14$EN) - wci_reqERR_14 <= `BSV_ASSIGNMENT_DELAY wci_reqERR_14$D_IN; - if (wci_reqERR_2$EN) - wci_reqERR_2 <= `BSV_ASSIGNMENT_DELAY wci_reqERR_2$D_IN; - if (wci_reqERR_3$EN) - wci_reqERR_3 <= `BSV_ASSIGNMENT_DELAY wci_reqERR_3$D_IN; - if (wci_reqERR_4$EN) - wci_reqERR_4 <= `BSV_ASSIGNMENT_DELAY wci_reqERR_4$D_IN; - if (wci_reqERR_5$EN) - wci_reqERR_5 <= `BSV_ASSIGNMENT_DELAY wci_reqERR_5$D_IN; - if (wci_reqERR_6$EN) - wci_reqERR_6 <= `BSV_ASSIGNMENT_DELAY wci_reqERR_6$D_IN; - if (wci_reqERR_7$EN) - wci_reqERR_7 <= `BSV_ASSIGNMENT_DELAY wci_reqERR_7$D_IN; - if (wci_reqERR_8$EN) - wci_reqERR_8 <= `BSV_ASSIGNMENT_DELAY wci_reqERR_8$D_IN; - if (wci_reqERR_9$EN) - wci_reqERR_9 <= `BSV_ASSIGNMENT_DELAY wci_reqERR_9$D_IN; - if (wci_reqFAIL$EN) - wci_reqFAIL <= `BSV_ASSIGNMENT_DELAY wci_reqFAIL$D_IN; - if (wci_reqFAIL_1$EN) - wci_reqFAIL_1 <= `BSV_ASSIGNMENT_DELAY wci_reqFAIL_1$D_IN; - if (wci_reqFAIL_10$EN) - wci_reqFAIL_10 <= `BSV_ASSIGNMENT_DELAY wci_reqFAIL_10$D_IN; - if (wci_reqFAIL_11$EN) - wci_reqFAIL_11 <= `BSV_ASSIGNMENT_DELAY wci_reqFAIL_11$D_IN; - if (wci_reqFAIL_12$EN) - wci_reqFAIL_12 <= `BSV_ASSIGNMENT_DELAY wci_reqFAIL_12$D_IN; - if (wci_reqFAIL_13$EN) - wci_reqFAIL_13 <= `BSV_ASSIGNMENT_DELAY wci_reqFAIL_13$D_IN; - if (wci_reqFAIL_14$EN) - wci_reqFAIL_14 <= `BSV_ASSIGNMENT_DELAY wci_reqFAIL_14$D_IN; - if (wci_reqFAIL_2$EN) - wci_reqFAIL_2 <= `BSV_ASSIGNMENT_DELAY wci_reqFAIL_2$D_IN; - if (wci_reqFAIL_3$EN) - wci_reqFAIL_3 <= `BSV_ASSIGNMENT_DELAY wci_reqFAIL_3$D_IN; - if (wci_reqFAIL_4$EN) - wci_reqFAIL_4 <= `BSV_ASSIGNMENT_DELAY wci_reqFAIL_4$D_IN; - if (wci_reqFAIL_5$EN) - wci_reqFAIL_5 <= `BSV_ASSIGNMENT_DELAY wci_reqFAIL_5$D_IN; - if (wci_reqFAIL_6$EN) - wci_reqFAIL_6 <= `BSV_ASSIGNMENT_DELAY wci_reqFAIL_6$D_IN; - if (wci_reqFAIL_7$EN) - wci_reqFAIL_7 <= `BSV_ASSIGNMENT_DELAY wci_reqFAIL_7$D_IN; - if (wci_reqFAIL_8$EN) - wci_reqFAIL_8 <= `BSV_ASSIGNMENT_DELAY wci_reqFAIL_8$D_IN; - if (wci_reqFAIL_9$EN) - wci_reqFAIL_9 <= `BSV_ASSIGNMENT_DELAY wci_reqFAIL_9$D_IN; - if (wci_reqF_10_c_r$EN) - wci_reqF_10_c_r <= `BSV_ASSIGNMENT_DELAY wci_reqF_10_c_r$D_IN; - if (wci_reqF_10_q_0$EN) - wci_reqF_10_q_0 <= `BSV_ASSIGNMENT_DELAY wci_reqF_10_q_0$D_IN; - if (wci_reqF_11_c_r$EN) - wci_reqF_11_c_r <= `BSV_ASSIGNMENT_DELAY wci_reqF_11_c_r$D_IN; - if (wci_reqF_11_q_0$EN) - wci_reqF_11_q_0 <= `BSV_ASSIGNMENT_DELAY wci_reqF_11_q_0$D_IN; - if (wci_reqF_12_c_r$EN) - wci_reqF_12_c_r <= `BSV_ASSIGNMENT_DELAY wci_reqF_12_c_r$D_IN; - if (wci_reqF_12_q_0$EN) - wci_reqF_12_q_0 <= `BSV_ASSIGNMENT_DELAY wci_reqF_12_q_0$D_IN; - if (wci_reqF_13_c_r$EN) - wci_reqF_13_c_r <= `BSV_ASSIGNMENT_DELAY wci_reqF_13_c_r$D_IN; - if (wci_reqF_13_q_0$EN) - wci_reqF_13_q_0 <= `BSV_ASSIGNMENT_DELAY wci_reqF_13_q_0$D_IN; - if (wci_reqF_14_c_r$EN) - wci_reqF_14_c_r <= `BSV_ASSIGNMENT_DELAY wci_reqF_14_c_r$D_IN; - if (wci_reqF_14_q_0$EN) - wci_reqF_14_q_0 <= `BSV_ASSIGNMENT_DELAY wci_reqF_14_q_0$D_IN; - if (wci_reqF_1_c_r$EN) - wci_reqF_1_c_r <= `BSV_ASSIGNMENT_DELAY wci_reqF_1_c_r$D_IN; - if (wci_reqF_1_q_0$EN) - wci_reqF_1_q_0 <= `BSV_ASSIGNMENT_DELAY wci_reqF_1_q_0$D_IN; - if (wci_reqF_2_c_r$EN) - wci_reqF_2_c_r <= `BSV_ASSIGNMENT_DELAY wci_reqF_2_c_r$D_IN; - if (wci_reqF_2_q_0$EN) - wci_reqF_2_q_0 <= `BSV_ASSIGNMENT_DELAY wci_reqF_2_q_0$D_IN; - if (wci_reqF_3_c_r$EN) - wci_reqF_3_c_r <= `BSV_ASSIGNMENT_DELAY wci_reqF_3_c_r$D_IN; - if (wci_reqF_3_q_0$EN) - wci_reqF_3_q_0 <= `BSV_ASSIGNMENT_DELAY wci_reqF_3_q_0$D_IN; - if (wci_reqF_4_c_r$EN) - wci_reqF_4_c_r <= `BSV_ASSIGNMENT_DELAY wci_reqF_4_c_r$D_IN; - if (wci_reqF_4_q_0$EN) - wci_reqF_4_q_0 <= `BSV_ASSIGNMENT_DELAY wci_reqF_4_q_0$D_IN; - if (wci_reqF_5_c_r$EN) - wci_reqF_5_c_r <= `BSV_ASSIGNMENT_DELAY wci_reqF_5_c_r$D_IN; - if (wci_reqF_5_q_0$EN) - wci_reqF_5_q_0 <= `BSV_ASSIGNMENT_DELAY wci_reqF_5_q_0$D_IN; - if (wci_reqF_6_c_r$EN) - wci_reqF_6_c_r <= `BSV_ASSIGNMENT_DELAY wci_reqF_6_c_r$D_IN; - if (wci_reqF_6_q_0$EN) - wci_reqF_6_q_0 <= `BSV_ASSIGNMENT_DELAY wci_reqF_6_q_0$D_IN; - if (wci_reqF_7_c_r$EN) - wci_reqF_7_c_r <= `BSV_ASSIGNMENT_DELAY wci_reqF_7_c_r$D_IN; - if (wci_reqF_7_q_0$EN) - wci_reqF_7_q_0 <= `BSV_ASSIGNMENT_DELAY wci_reqF_7_q_0$D_IN; - if (wci_reqF_8_c_r$EN) - wci_reqF_8_c_r <= `BSV_ASSIGNMENT_DELAY wci_reqF_8_c_r$D_IN; - if (wci_reqF_8_q_0$EN) - wci_reqF_8_q_0 <= `BSV_ASSIGNMENT_DELAY wci_reqF_8_q_0$D_IN; - if (wci_reqF_9_c_r$EN) - wci_reqF_9_c_r <= `BSV_ASSIGNMENT_DELAY wci_reqF_9_c_r$D_IN; - if (wci_reqF_9_q_0$EN) - wci_reqF_9_q_0 <= `BSV_ASSIGNMENT_DELAY wci_reqF_9_q_0$D_IN; - if (wci_reqF_c_r$EN) - wci_reqF_c_r <= `BSV_ASSIGNMENT_DELAY wci_reqF_c_r$D_IN; - if (wci_reqF_q_0$EN) - wci_reqF_q_0 <= `BSV_ASSIGNMENT_DELAY wci_reqF_q_0$D_IN; - if (wci_reqPend$EN) - wci_reqPend <= `BSV_ASSIGNMENT_DELAY wci_reqPend$D_IN; - if (wci_reqPend_1$EN) - wci_reqPend_1 <= `BSV_ASSIGNMENT_DELAY wci_reqPend_1$D_IN; - if (wci_reqPend_10$EN) - wci_reqPend_10 <= `BSV_ASSIGNMENT_DELAY wci_reqPend_10$D_IN; - if (wci_reqPend_11$EN) - wci_reqPend_11 <= `BSV_ASSIGNMENT_DELAY wci_reqPend_11$D_IN; - if (wci_reqPend_12$EN) - wci_reqPend_12 <= `BSV_ASSIGNMENT_DELAY wci_reqPend_12$D_IN; - if (wci_reqPend_13$EN) - wci_reqPend_13 <= `BSV_ASSIGNMENT_DELAY wci_reqPend_13$D_IN; - if (wci_reqPend_14$EN) - wci_reqPend_14 <= `BSV_ASSIGNMENT_DELAY wci_reqPend_14$D_IN; - if (wci_reqPend_2$EN) - wci_reqPend_2 <= `BSV_ASSIGNMENT_DELAY wci_reqPend_2$D_IN; - if (wci_reqPend_3$EN) - wci_reqPend_3 <= `BSV_ASSIGNMENT_DELAY wci_reqPend_3$D_IN; - if (wci_reqPend_4$EN) - wci_reqPend_4 <= `BSV_ASSIGNMENT_DELAY wci_reqPend_4$D_IN; - if (wci_reqPend_5$EN) - wci_reqPend_5 <= `BSV_ASSIGNMENT_DELAY wci_reqPend_5$D_IN; - if (wci_reqPend_6$EN) - wci_reqPend_6 <= `BSV_ASSIGNMENT_DELAY wci_reqPend_6$D_IN; - if (wci_reqPend_7$EN) - wci_reqPend_7 <= `BSV_ASSIGNMENT_DELAY wci_reqPend_7$D_IN; - if (wci_reqPend_8$EN) - wci_reqPend_8 <= `BSV_ASSIGNMENT_DELAY wci_reqPend_8$D_IN; - if (wci_reqPend_9$EN) - wci_reqPend_9 <= `BSV_ASSIGNMENT_DELAY wci_reqPend_9$D_IN; - if (wci_reqTO$EN) wci_reqTO <= `BSV_ASSIGNMENT_DELAY wci_reqTO$D_IN; - if (wci_reqTO_1$EN) - wci_reqTO_1 <= `BSV_ASSIGNMENT_DELAY wci_reqTO_1$D_IN; - if (wci_reqTO_10$EN) - wci_reqTO_10 <= `BSV_ASSIGNMENT_DELAY wci_reqTO_10$D_IN; - if (wci_reqTO_11$EN) - wci_reqTO_11 <= `BSV_ASSIGNMENT_DELAY wci_reqTO_11$D_IN; - if (wci_reqTO_12$EN) - wci_reqTO_12 <= `BSV_ASSIGNMENT_DELAY wci_reqTO_12$D_IN; - if (wci_reqTO_13$EN) - wci_reqTO_13 <= `BSV_ASSIGNMENT_DELAY wci_reqTO_13$D_IN; - if (wci_reqTO_14$EN) - wci_reqTO_14 <= `BSV_ASSIGNMENT_DELAY wci_reqTO_14$D_IN; - if (wci_reqTO_2$EN) - wci_reqTO_2 <= `BSV_ASSIGNMENT_DELAY wci_reqTO_2$D_IN; - if (wci_reqTO_3$EN) - wci_reqTO_3 <= `BSV_ASSIGNMENT_DELAY wci_reqTO_3$D_IN; - if (wci_reqTO_4$EN) - wci_reqTO_4 <= `BSV_ASSIGNMENT_DELAY wci_reqTO_4$D_IN; - if (wci_reqTO_5$EN) - wci_reqTO_5 <= `BSV_ASSIGNMENT_DELAY wci_reqTO_5$D_IN; - if (wci_reqTO_6$EN) - wci_reqTO_6 <= `BSV_ASSIGNMENT_DELAY wci_reqTO_6$D_IN; - if (wci_reqTO_7$EN) - wci_reqTO_7 <= `BSV_ASSIGNMENT_DELAY wci_reqTO_7$D_IN; - if (wci_reqTO_8$EN) - wci_reqTO_8 <= `BSV_ASSIGNMENT_DELAY wci_reqTO_8$D_IN; - if (wci_reqTO_9$EN) - wci_reqTO_9 <= `BSV_ASSIGNMENT_DELAY wci_reqTO_9$D_IN; - if (wci_respTimr$EN) - wci_respTimr <= `BSV_ASSIGNMENT_DELAY wci_respTimr$D_IN; - if (wci_respTimrAct$EN) - wci_respTimrAct <= `BSV_ASSIGNMENT_DELAY wci_respTimrAct$D_IN; - if (wci_respTimrAct_1$EN) - wci_respTimrAct_1 <= `BSV_ASSIGNMENT_DELAY wci_respTimrAct_1$D_IN; - if (wci_respTimrAct_10$EN) - wci_respTimrAct_10 <= `BSV_ASSIGNMENT_DELAY wci_respTimrAct_10$D_IN; - if (wci_respTimrAct_11$EN) - wci_respTimrAct_11 <= `BSV_ASSIGNMENT_DELAY wci_respTimrAct_11$D_IN; - if (wci_respTimrAct_12$EN) - wci_respTimrAct_12 <= `BSV_ASSIGNMENT_DELAY wci_respTimrAct_12$D_IN; - if (wci_respTimrAct_13$EN) - wci_respTimrAct_13 <= `BSV_ASSIGNMENT_DELAY wci_respTimrAct_13$D_IN; - if (wci_respTimrAct_14$EN) - wci_respTimrAct_14 <= `BSV_ASSIGNMENT_DELAY wci_respTimrAct_14$D_IN; - if (wci_respTimrAct_2$EN) - wci_respTimrAct_2 <= `BSV_ASSIGNMENT_DELAY wci_respTimrAct_2$D_IN; - if (wci_respTimrAct_3$EN) - wci_respTimrAct_3 <= `BSV_ASSIGNMENT_DELAY wci_respTimrAct_3$D_IN; - if (wci_respTimrAct_4$EN) - wci_respTimrAct_4 <= `BSV_ASSIGNMENT_DELAY wci_respTimrAct_4$D_IN; - if (wci_respTimrAct_5$EN) - wci_respTimrAct_5 <= `BSV_ASSIGNMENT_DELAY wci_respTimrAct_5$D_IN; - if (wci_respTimrAct_6$EN) - wci_respTimrAct_6 <= `BSV_ASSIGNMENT_DELAY wci_respTimrAct_6$D_IN; - if (wci_respTimrAct_7$EN) - wci_respTimrAct_7 <= `BSV_ASSIGNMENT_DELAY wci_respTimrAct_7$D_IN; - if (wci_respTimrAct_8$EN) - wci_respTimrAct_8 <= `BSV_ASSIGNMENT_DELAY wci_respTimrAct_8$D_IN; - if (wci_respTimrAct_9$EN) - wci_respTimrAct_9 <= `BSV_ASSIGNMENT_DELAY wci_respTimrAct_9$D_IN; - if (wci_respTimr_1$EN) - wci_respTimr_1 <= `BSV_ASSIGNMENT_DELAY wci_respTimr_1$D_IN; - if (wci_respTimr_10$EN) - wci_respTimr_10 <= `BSV_ASSIGNMENT_DELAY wci_respTimr_10$D_IN; - if (wci_respTimr_11$EN) - wci_respTimr_11 <= `BSV_ASSIGNMENT_DELAY wci_respTimr_11$D_IN; - if (wci_respTimr_12$EN) - wci_respTimr_12 <= `BSV_ASSIGNMENT_DELAY wci_respTimr_12$D_IN; - if (wci_respTimr_13$EN) - wci_respTimr_13 <= `BSV_ASSIGNMENT_DELAY wci_respTimr_13$D_IN; - if (wci_respTimr_14$EN) - wci_respTimr_14 <= `BSV_ASSIGNMENT_DELAY wci_respTimr_14$D_IN; - if (wci_respTimr_2$EN) - wci_respTimr_2 <= `BSV_ASSIGNMENT_DELAY wci_respTimr_2$D_IN; - if (wci_respTimr_3$EN) - wci_respTimr_3 <= `BSV_ASSIGNMENT_DELAY wci_respTimr_3$D_IN; - if (wci_respTimr_4$EN) - wci_respTimr_4 <= `BSV_ASSIGNMENT_DELAY wci_respTimr_4$D_IN; - if (wci_respTimr_5$EN) - wci_respTimr_5 <= `BSV_ASSIGNMENT_DELAY wci_respTimr_5$D_IN; - if (wci_respTimr_6$EN) - wci_respTimr_6 <= `BSV_ASSIGNMENT_DELAY wci_respTimr_6$D_IN; - if (wci_respTimr_7$EN) - wci_respTimr_7 <= `BSV_ASSIGNMENT_DELAY wci_respTimr_7$D_IN; - if (wci_respTimr_8$EN) - wci_respTimr_8 <= `BSV_ASSIGNMENT_DELAY wci_respTimr_8$D_IN; - if (wci_respTimr_9$EN) - wci_respTimr_9 <= `BSV_ASSIGNMENT_DELAY wci_respTimr_9$D_IN; - if (wci_sThreadBusy_d$EN) - wci_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY wci_sThreadBusy_d$D_IN; - if (wci_sThreadBusy_d_1$EN) - wci_sThreadBusy_d_1 <= `BSV_ASSIGNMENT_DELAY - wci_sThreadBusy_d_1$D_IN; - if (wci_sThreadBusy_d_10$EN) - wci_sThreadBusy_d_10 <= `BSV_ASSIGNMENT_DELAY - wci_sThreadBusy_d_10$D_IN; - if (wci_sThreadBusy_d_11$EN) - wci_sThreadBusy_d_11 <= `BSV_ASSIGNMENT_DELAY - wci_sThreadBusy_d_11$D_IN; - if (wci_sThreadBusy_d_12$EN) - wci_sThreadBusy_d_12 <= `BSV_ASSIGNMENT_DELAY - wci_sThreadBusy_d_12$D_IN; - if (wci_sThreadBusy_d_13$EN) - wci_sThreadBusy_d_13 <= `BSV_ASSIGNMENT_DELAY - wci_sThreadBusy_d_13$D_IN; - if (wci_sThreadBusy_d_14$EN) - wci_sThreadBusy_d_14 <= `BSV_ASSIGNMENT_DELAY - wci_sThreadBusy_d_14$D_IN; - if (wci_sThreadBusy_d_2$EN) - wci_sThreadBusy_d_2 <= `BSV_ASSIGNMENT_DELAY - wci_sThreadBusy_d_2$D_IN; - if (wci_sThreadBusy_d_3$EN) - wci_sThreadBusy_d_3 <= `BSV_ASSIGNMENT_DELAY - wci_sThreadBusy_d_3$D_IN; - if (wci_sThreadBusy_d_4$EN) - wci_sThreadBusy_d_4 <= `BSV_ASSIGNMENT_DELAY - wci_sThreadBusy_d_4$D_IN; - if (wci_sThreadBusy_d_5$EN) - wci_sThreadBusy_d_5 <= `BSV_ASSIGNMENT_DELAY - wci_sThreadBusy_d_5$D_IN; - if (wci_sThreadBusy_d_6$EN) - wci_sThreadBusy_d_6 <= `BSV_ASSIGNMENT_DELAY - wci_sThreadBusy_d_6$D_IN; - if (wci_sThreadBusy_d_7$EN) - wci_sThreadBusy_d_7 <= `BSV_ASSIGNMENT_DELAY - wci_sThreadBusy_d_7$D_IN; - if (wci_sThreadBusy_d_8$EN) - wci_sThreadBusy_d_8 <= `BSV_ASSIGNMENT_DELAY - wci_sThreadBusy_d_8$D_IN; - if (wci_sThreadBusy_d_9$EN) - wci_sThreadBusy_d_9 <= `BSV_ASSIGNMENT_DELAY - wci_sThreadBusy_d_9$D_IN; - if (wci_sfCap$EN) wci_sfCap <= `BSV_ASSIGNMENT_DELAY wci_sfCap$D_IN; - if (wci_sfCapClear$EN) - wci_sfCapClear <= `BSV_ASSIGNMENT_DELAY wci_sfCapClear$D_IN; - if (wci_sfCapClear_10$EN) - wci_sfCapClear_10 <= `BSV_ASSIGNMENT_DELAY wci_sfCapClear_10$D_IN; - if (wci_sfCapClear_11$EN) - wci_sfCapClear_11 <= `BSV_ASSIGNMENT_DELAY wci_sfCapClear_11$D_IN; - if (wci_sfCapClear_12$EN) - wci_sfCapClear_12 <= `BSV_ASSIGNMENT_DELAY wci_sfCapClear_12$D_IN; - if (wci_sfCapClear_13$EN) - wci_sfCapClear_13 <= `BSV_ASSIGNMENT_DELAY wci_sfCapClear_13$D_IN; - if (wci_sfCapClear_14$EN) - wci_sfCapClear_14 <= `BSV_ASSIGNMENT_DELAY wci_sfCapClear_14$D_IN; - if (wci_sfCapClear_1_1$EN) - wci_sfCapClear_1_1 <= `BSV_ASSIGNMENT_DELAY wci_sfCapClear_1_1$D_IN; - if (wci_sfCapClear_2$EN) - wci_sfCapClear_2 <= `BSV_ASSIGNMENT_DELAY wci_sfCapClear_2$D_IN; - if (wci_sfCapClear_3$EN) - wci_sfCapClear_3 <= `BSV_ASSIGNMENT_DELAY wci_sfCapClear_3$D_IN; - if (wci_sfCapClear_4$EN) - wci_sfCapClear_4 <= `BSV_ASSIGNMENT_DELAY wci_sfCapClear_4$D_IN; - if (wci_sfCapClear_5$EN) - wci_sfCapClear_5 <= `BSV_ASSIGNMENT_DELAY wci_sfCapClear_5$D_IN; - if (wci_sfCapClear_6$EN) - wci_sfCapClear_6 <= `BSV_ASSIGNMENT_DELAY wci_sfCapClear_6$D_IN; - if (wci_sfCapClear_7$EN) - wci_sfCapClear_7 <= `BSV_ASSIGNMENT_DELAY wci_sfCapClear_7$D_IN; - if (wci_sfCapClear_8$EN) - wci_sfCapClear_8 <= `BSV_ASSIGNMENT_DELAY wci_sfCapClear_8$D_IN; - if (wci_sfCapClear_9$EN) - wci_sfCapClear_9 <= `BSV_ASSIGNMENT_DELAY wci_sfCapClear_9$D_IN; - if (wci_sfCapSet$EN) - wci_sfCapSet <= `BSV_ASSIGNMENT_DELAY wci_sfCapSet$D_IN; - if (wci_sfCapSet_10$EN) - wci_sfCapSet_10 <= `BSV_ASSIGNMENT_DELAY wci_sfCapSet_10$D_IN; - if (wci_sfCapSet_11$EN) - wci_sfCapSet_11 <= `BSV_ASSIGNMENT_DELAY wci_sfCapSet_11$D_IN; - if (wci_sfCapSet_12$EN) - wci_sfCapSet_12 <= `BSV_ASSIGNMENT_DELAY wci_sfCapSet_12$D_IN; - if (wci_sfCapSet_13$EN) - wci_sfCapSet_13 <= `BSV_ASSIGNMENT_DELAY wci_sfCapSet_13$D_IN; - if (wci_sfCapSet_14$EN) - wci_sfCapSet_14 <= `BSV_ASSIGNMENT_DELAY wci_sfCapSet_14$D_IN; - if (wci_sfCapSet_1_1$EN) - wci_sfCapSet_1_1 <= `BSV_ASSIGNMENT_DELAY wci_sfCapSet_1_1$D_IN; - if (wci_sfCapSet_2$EN) - wci_sfCapSet_2 <= `BSV_ASSIGNMENT_DELAY wci_sfCapSet_2$D_IN; - if (wci_sfCapSet_3$EN) - wci_sfCapSet_3 <= `BSV_ASSIGNMENT_DELAY wci_sfCapSet_3$D_IN; - if (wci_sfCapSet_4$EN) - wci_sfCapSet_4 <= `BSV_ASSIGNMENT_DELAY wci_sfCapSet_4$D_IN; - if (wci_sfCapSet_5$EN) - wci_sfCapSet_5 <= `BSV_ASSIGNMENT_DELAY wci_sfCapSet_5$D_IN; - if (wci_sfCapSet_6$EN) - wci_sfCapSet_6 <= `BSV_ASSIGNMENT_DELAY wci_sfCapSet_6$D_IN; - if (wci_sfCapSet_7$EN) - wci_sfCapSet_7 <= `BSV_ASSIGNMENT_DELAY wci_sfCapSet_7$D_IN; - if (wci_sfCapSet_8$EN) - wci_sfCapSet_8 <= `BSV_ASSIGNMENT_DELAY wci_sfCapSet_8$D_IN; - if (wci_sfCapSet_9$EN) - wci_sfCapSet_9 <= `BSV_ASSIGNMENT_DELAY wci_sfCapSet_9$D_IN; - if (wci_sfCap_1$EN) - wci_sfCap_1 <= `BSV_ASSIGNMENT_DELAY wci_sfCap_1$D_IN; - if (wci_sfCap_10$EN) - wci_sfCap_10 <= `BSV_ASSIGNMENT_DELAY wci_sfCap_10$D_IN; - if (wci_sfCap_11$EN) - wci_sfCap_11 <= `BSV_ASSIGNMENT_DELAY wci_sfCap_11$D_IN; - if (wci_sfCap_12$EN) - wci_sfCap_12 <= `BSV_ASSIGNMENT_DELAY wci_sfCap_12$D_IN; - if (wci_sfCap_13$EN) - wci_sfCap_13 <= `BSV_ASSIGNMENT_DELAY wci_sfCap_13$D_IN; - if (wci_sfCap_14$EN) - wci_sfCap_14 <= `BSV_ASSIGNMENT_DELAY wci_sfCap_14$D_IN; - if (wci_sfCap_2$EN) - wci_sfCap_2 <= `BSV_ASSIGNMENT_DELAY wci_sfCap_2$D_IN; - if (wci_sfCap_3$EN) - wci_sfCap_3 <= `BSV_ASSIGNMENT_DELAY wci_sfCap_3$D_IN; - if (wci_sfCap_4$EN) - wci_sfCap_4 <= `BSV_ASSIGNMENT_DELAY wci_sfCap_4$D_IN; - if (wci_sfCap_5$EN) - wci_sfCap_5 <= `BSV_ASSIGNMENT_DELAY wci_sfCap_5$D_IN; - if (wci_sfCap_6$EN) - wci_sfCap_6 <= `BSV_ASSIGNMENT_DELAY wci_sfCap_6$D_IN; - if (wci_sfCap_7$EN) - wci_sfCap_7 <= `BSV_ASSIGNMENT_DELAY wci_sfCap_7$D_IN; - if (wci_sfCap_8$EN) - wci_sfCap_8 <= `BSV_ASSIGNMENT_DELAY wci_sfCap_8$D_IN; - if (wci_sfCap_9$EN) - wci_sfCap_9 <= `BSV_ASSIGNMENT_DELAY wci_sfCap_9$D_IN; - if (wci_slvPresent$EN) - wci_slvPresent <= `BSV_ASSIGNMENT_DELAY wci_slvPresent$D_IN; - if (wci_slvPresent_1$EN) - wci_slvPresent_1 <= `BSV_ASSIGNMENT_DELAY wci_slvPresent_1$D_IN; - if (wci_slvPresent_10$EN) - wci_slvPresent_10 <= `BSV_ASSIGNMENT_DELAY wci_slvPresent_10$D_IN; - if (wci_slvPresent_11$EN) - wci_slvPresent_11 <= `BSV_ASSIGNMENT_DELAY wci_slvPresent_11$D_IN; - if (wci_slvPresent_12$EN) - wci_slvPresent_12 <= `BSV_ASSIGNMENT_DELAY wci_slvPresent_12$D_IN; - if (wci_slvPresent_13$EN) - wci_slvPresent_13 <= `BSV_ASSIGNMENT_DELAY wci_slvPresent_13$D_IN; - if (wci_slvPresent_14$EN) - wci_slvPresent_14 <= `BSV_ASSIGNMENT_DELAY wci_slvPresent_14$D_IN; - if (wci_slvPresent_2$EN) - wci_slvPresent_2 <= `BSV_ASSIGNMENT_DELAY wci_slvPresent_2$D_IN; - if (wci_slvPresent_3$EN) - wci_slvPresent_3 <= `BSV_ASSIGNMENT_DELAY wci_slvPresent_3$D_IN; - if (wci_slvPresent_4$EN) - wci_slvPresent_4 <= `BSV_ASSIGNMENT_DELAY wci_slvPresent_4$D_IN; - if (wci_slvPresent_5$EN) - wci_slvPresent_5 <= `BSV_ASSIGNMENT_DELAY wci_slvPresent_5$D_IN; - if (wci_slvPresent_6$EN) - wci_slvPresent_6 <= `BSV_ASSIGNMENT_DELAY wci_slvPresent_6$D_IN; - if (wci_slvPresent_7$EN) - wci_slvPresent_7 <= `BSV_ASSIGNMENT_DELAY wci_slvPresent_7$D_IN; - if (wci_slvPresent_8$EN) - wci_slvPresent_8 <= `BSV_ASSIGNMENT_DELAY wci_slvPresent_8$D_IN; - if (wci_slvPresent_9$EN) - wci_slvPresent_9 <= `BSV_ASSIGNMENT_DELAY wci_slvPresent_9$D_IN; - if (wci_wReset_n$EN) - wci_wReset_n <= `BSV_ASSIGNMENT_DELAY wci_wReset_n$D_IN; - if (wci_wReset_n_1$EN) - wci_wReset_n_1 <= `BSV_ASSIGNMENT_DELAY wci_wReset_n_1$D_IN; - if (wci_wReset_n_10$EN) - wci_wReset_n_10 <= `BSV_ASSIGNMENT_DELAY wci_wReset_n_10$D_IN; - if (wci_wReset_n_11$EN) - wci_wReset_n_11 <= `BSV_ASSIGNMENT_DELAY wci_wReset_n_11$D_IN; - if (wci_wReset_n_12$EN) - wci_wReset_n_12 <= `BSV_ASSIGNMENT_DELAY wci_wReset_n_12$D_IN; - if (wci_wReset_n_13$EN) - wci_wReset_n_13 <= `BSV_ASSIGNMENT_DELAY wci_wReset_n_13$D_IN; - if (wci_wReset_n_14$EN) - wci_wReset_n_14 <= `BSV_ASSIGNMENT_DELAY wci_wReset_n_14$D_IN; - if (wci_wReset_n_2$EN) - wci_wReset_n_2 <= `BSV_ASSIGNMENT_DELAY wci_wReset_n_2$D_IN; - if (wci_wReset_n_3$EN) - wci_wReset_n_3 <= `BSV_ASSIGNMENT_DELAY wci_wReset_n_3$D_IN; - if (wci_wReset_n_4$EN) - wci_wReset_n_4 <= `BSV_ASSIGNMENT_DELAY wci_wReset_n_4$D_IN; - if (wci_wReset_n_5$EN) - wci_wReset_n_5 <= `BSV_ASSIGNMENT_DELAY wci_wReset_n_5$D_IN; - if (wci_wReset_n_6$EN) - wci_wReset_n_6 <= `BSV_ASSIGNMENT_DELAY wci_wReset_n_6$D_IN; - if (wci_wReset_n_7$EN) - wci_wReset_n_7 <= `BSV_ASSIGNMENT_DELAY wci_wReset_n_7$D_IN; - if (wci_wReset_n_8$EN) - wci_wReset_n_8 <= `BSV_ASSIGNMENT_DELAY wci_wReset_n_8$D_IN; - if (wci_wReset_n_9$EN) - wci_wReset_n_9 <= `BSV_ASSIGNMENT_DELAY wci_wReset_n_9$D_IN; - if (wci_wTimeout$EN) - wci_wTimeout <= `BSV_ASSIGNMENT_DELAY wci_wTimeout$D_IN; - if (wci_wTimeout_1$EN) - wci_wTimeout_1 <= `BSV_ASSIGNMENT_DELAY wci_wTimeout_1$D_IN; - if (wci_wTimeout_10$EN) - wci_wTimeout_10 <= `BSV_ASSIGNMENT_DELAY wci_wTimeout_10$D_IN; - if (wci_wTimeout_11$EN) - wci_wTimeout_11 <= `BSV_ASSIGNMENT_DELAY wci_wTimeout_11$D_IN; - if (wci_wTimeout_12$EN) - wci_wTimeout_12 <= `BSV_ASSIGNMENT_DELAY wci_wTimeout_12$D_IN; - if (wci_wTimeout_13$EN) - wci_wTimeout_13 <= `BSV_ASSIGNMENT_DELAY wci_wTimeout_13$D_IN; - if (wci_wTimeout_14$EN) - wci_wTimeout_14 <= `BSV_ASSIGNMENT_DELAY wci_wTimeout_14$D_IN; - if (wci_wTimeout_2$EN) - wci_wTimeout_2 <= `BSV_ASSIGNMENT_DELAY wci_wTimeout_2$D_IN; - if (wci_wTimeout_3$EN) - wci_wTimeout_3 <= `BSV_ASSIGNMENT_DELAY wci_wTimeout_3$D_IN; - if (wci_wTimeout_4$EN) - wci_wTimeout_4 <= `BSV_ASSIGNMENT_DELAY wci_wTimeout_4$D_IN; - if (wci_wTimeout_5$EN) - wci_wTimeout_5 <= `BSV_ASSIGNMENT_DELAY wci_wTimeout_5$D_IN; - if (wci_wTimeout_6$EN) - wci_wTimeout_6 <= `BSV_ASSIGNMENT_DELAY wci_wTimeout_6$D_IN; - if (wci_wTimeout_7$EN) - wci_wTimeout_7 <= `BSV_ASSIGNMENT_DELAY wci_wTimeout_7$D_IN; - if (wci_wTimeout_8$EN) - wci_wTimeout_8 <= `BSV_ASSIGNMENT_DELAY wci_wTimeout_8$D_IN; - if (wci_wTimeout_9$EN) - wci_wTimeout_9 <= `BSV_ASSIGNMENT_DELAY wci_wTimeout_9$D_IN; + if (wci_0_busy$EN) + wci_0_busy <= `BSV_ASSIGNMENT_DELAY wci_0_busy$D_IN; + if (wci_0_lastConfigAddr$EN) + wci_0_lastConfigAddr <= `BSV_ASSIGNMENT_DELAY + wci_0_lastConfigAddr$D_IN; + if (wci_0_lastConfigBE$EN) + wci_0_lastConfigBE <= `BSV_ASSIGNMENT_DELAY wci_0_lastConfigBE$D_IN; + if (wci_0_lastControlOp$EN) + wci_0_lastControlOp <= `BSV_ASSIGNMENT_DELAY + wci_0_lastControlOp$D_IN; + if (wci_0_lastOpWrite$EN) + wci_0_lastOpWrite <= `BSV_ASSIGNMENT_DELAY wci_0_lastOpWrite$D_IN; + if (wci_0_mFlagReg$EN) + wci_0_mFlagReg <= `BSV_ASSIGNMENT_DELAY wci_0_mFlagReg$D_IN; + if (wci_0_pageWindow$EN) + wci_0_pageWindow <= `BSV_ASSIGNMENT_DELAY wci_0_pageWindow$D_IN; + if (wci_0_reqERR$EN) + wci_0_reqERR <= `BSV_ASSIGNMENT_DELAY wci_0_reqERR$D_IN; + if (wci_0_reqFAIL$EN) + wci_0_reqFAIL <= `BSV_ASSIGNMENT_DELAY wci_0_reqFAIL$D_IN; + if (wci_0_reqF_cntr_r$EN) + wci_0_reqF_cntr_r <= `BSV_ASSIGNMENT_DELAY wci_0_reqF_cntr_r$D_IN; + if (wci_0_reqF_q_0$EN) + wci_0_reqF_q_0 <= `BSV_ASSIGNMENT_DELAY wci_0_reqF_q_0$D_IN; + if (wci_0_reqPend$EN) + wci_0_reqPend <= `BSV_ASSIGNMENT_DELAY wci_0_reqPend$D_IN; + if (wci_0_reqTO$EN) + wci_0_reqTO <= `BSV_ASSIGNMENT_DELAY wci_0_reqTO$D_IN; + if (wci_0_respTimr$EN) + wci_0_respTimr <= `BSV_ASSIGNMENT_DELAY wci_0_respTimr$D_IN; + if (wci_0_respTimrAct$EN) + wci_0_respTimrAct <= `BSV_ASSIGNMENT_DELAY wci_0_respTimrAct$D_IN; + if (wci_0_sThreadBusy_d$EN) + wci_0_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY + wci_0_sThreadBusy_d$D_IN; + if (wci_0_sfCap$EN) + wci_0_sfCap <= `BSV_ASSIGNMENT_DELAY wci_0_sfCap$D_IN; + if (wci_0_sfCapClear$EN) + wci_0_sfCapClear <= `BSV_ASSIGNMENT_DELAY wci_0_sfCapClear$D_IN; + if (wci_0_sfCapSet$EN) + wci_0_sfCapSet <= `BSV_ASSIGNMENT_DELAY wci_0_sfCapSet$D_IN; + if (wci_0_slvPresent$EN) + wci_0_slvPresent <= `BSV_ASSIGNMENT_DELAY wci_0_slvPresent$D_IN; + if (wci_0_wReset_n$EN) + wci_0_wReset_n <= `BSV_ASSIGNMENT_DELAY wci_0_wReset_n$D_IN; + if (wci_0_wTimeout$EN) + wci_0_wTimeout <= `BSV_ASSIGNMENT_DELAY wci_0_wTimeout$D_IN; + if (wci_10_busy$EN) + wci_10_busy <= `BSV_ASSIGNMENT_DELAY wci_10_busy$D_IN; + if (wci_10_lastConfigAddr$EN) + wci_10_lastConfigAddr <= `BSV_ASSIGNMENT_DELAY + wci_10_lastConfigAddr$D_IN; + if (wci_10_lastConfigBE$EN) + wci_10_lastConfigBE <= `BSV_ASSIGNMENT_DELAY + wci_10_lastConfigBE$D_IN; + if (wci_10_lastControlOp$EN) + wci_10_lastControlOp <= `BSV_ASSIGNMENT_DELAY + wci_10_lastControlOp$D_IN; + if (wci_10_lastOpWrite$EN) + wci_10_lastOpWrite <= `BSV_ASSIGNMENT_DELAY wci_10_lastOpWrite$D_IN; + if (wci_10_mFlagReg$EN) + wci_10_mFlagReg <= `BSV_ASSIGNMENT_DELAY wci_10_mFlagReg$D_IN; + if (wci_10_pageWindow$EN) + wci_10_pageWindow <= `BSV_ASSIGNMENT_DELAY wci_10_pageWindow$D_IN; + if (wci_10_reqERR$EN) + wci_10_reqERR <= `BSV_ASSIGNMENT_DELAY wci_10_reqERR$D_IN; + if (wci_10_reqFAIL$EN) + wci_10_reqFAIL <= `BSV_ASSIGNMENT_DELAY wci_10_reqFAIL$D_IN; + if (wci_10_reqF_cntr_r$EN) + wci_10_reqF_cntr_r <= `BSV_ASSIGNMENT_DELAY wci_10_reqF_cntr_r$D_IN; + if (wci_10_reqF_q_0$EN) + wci_10_reqF_q_0 <= `BSV_ASSIGNMENT_DELAY wci_10_reqF_q_0$D_IN; + if (wci_10_reqPend$EN) + wci_10_reqPend <= `BSV_ASSIGNMENT_DELAY wci_10_reqPend$D_IN; + if (wci_10_reqTO$EN) + wci_10_reqTO <= `BSV_ASSIGNMENT_DELAY wci_10_reqTO$D_IN; + if (wci_10_respTimr$EN) + wci_10_respTimr <= `BSV_ASSIGNMENT_DELAY wci_10_respTimr$D_IN; + if (wci_10_respTimrAct$EN) + wci_10_respTimrAct <= `BSV_ASSIGNMENT_DELAY wci_10_respTimrAct$D_IN; + if (wci_10_sThreadBusy_d$EN) + wci_10_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY + wci_10_sThreadBusy_d$D_IN; + if (wci_10_sfCap$EN) + wci_10_sfCap <= `BSV_ASSIGNMENT_DELAY wci_10_sfCap$D_IN; + if (wci_10_sfCapClear$EN) + wci_10_sfCapClear <= `BSV_ASSIGNMENT_DELAY wci_10_sfCapClear$D_IN; + if (wci_10_sfCapSet$EN) + wci_10_sfCapSet <= `BSV_ASSIGNMENT_DELAY wci_10_sfCapSet$D_IN; + if (wci_10_slvPresent$EN) + wci_10_slvPresent <= `BSV_ASSIGNMENT_DELAY wci_10_slvPresent$D_IN; + if (wci_10_wReset_n$EN) + wci_10_wReset_n <= `BSV_ASSIGNMENT_DELAY wci_10_wReset_n$D_IN; + if (wci_10_wTimeout$EN) + wci_10_wTimeout <= `BSV_ASSIGNMENT_DELAY wci_10_wTimeout$D_IN; + if (wci_11_busy$EN) + wci_11_busy <= `BSV_ASSIGNMENT_DELAY wci_11_busy$D_IN; + if (wci_11_lastConfigAddr$EN) + wci_11_lastConfigAddr <= `BSV_ASSIGNMENT_DELAY + wci_11_lastConfigAddr$D_IN; + if (wci_11_lastConfigBE$EN) + wci_11_lastConfigBE <= `BSV_ASSIGNMENT_DELAY + wci_11_lastConfigBE$D_IN; + if (wci_11_lastControlOp$EN) + wci_11_lastControlOp <= `BSV_ASSIGNMENT_DELAY + wci_11_lastControlOp$D_IN; + if (wci_11_lastOpWrite$EN) + wci_11_lastOpWrite <= `BSV_ASSIGNMENT_DELAY wci_11_lastOpWrite$D_IN; + if (wci_11_mFlagReg$EN) + wci_11_mFlagReg <= `BSV_ASSIGNMENT_DELAY wci_11_mFlagReg$D_IN; + if (wci_11_pageWindow$EN) + wci_11_pageWindow <= `BSV_ASSIGNMENT_DELAY wci_11_pageWindow$D_IN; + if (wci_11_reqERR$EN) + wci_11_reqERR <= `BSV_ASSIGNMENT_DELAY wci_11_reqERR$D_IN; + if (wci_11_reqFAIL$EN) + wci_11_reqFAIL <= `BSV_ASSIGNMENT_DELAY wci_11_reqFAIL$D_IN; + if (wci_11_reqF_cntr_r$EN) + wci_11_reqF_cntr_r <= `BSV_ASSIGNMENT_DELAY wci_11_reqF_cntr_r$D_IN; + if (wci_11_reqF_q_0$EN) + wci_11_reqF_q_0 <= `BSV_ASSIGNMENT_DELAY wci_11_reqF_q_0$D_IN; + if (wci_11_reqPend$EN) + wci_11_reqPend <= `BSV_ASSIGNMENT_DELAY wci_11_reqPend$D_IN; + if (wci_11_reqTO$EN) + wci_11_reqTO <= `BSV_ASSIGNMENT_DELAY wci_11_reqTO$D_IN; + if (wci_11_respTimr$EN) + wci_11_respTimr <= `BSV_ASSIGNMENT_DELAY wci_11_respTimr$D_IN; + if (wci_11_respTimrAct$EN) + wci_11_respTimrAct <= `BSV_ASSIGNMENT_DELAY wci_11_respTimrAct$D_IN; + if (wci_11_sThreadBusy_d$EN) + wci_11_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY + wci_11_sThreadBusy_d$D_IN; + if (wci_11_sfCap$EN) + wci_11_sfCap <= `BSV_ASSIGNMENT_DELAY wci_11_sfCap$D_IN; + if (wci_11_sfCapClear$EN) + wci_11_sfCapClear <= `BSV_ASSIGNMENT_DELAY wci_11_sfCapClear$D_IN; + if (wci_11_sfCapSet$EN) + wci_11_sfCapSet <= `BSV_ASSIGNMENT_DELAY wci_11_sfCapSet$D_IN; + if (wci_11_slvPresent$EN) + wci_11_slvPresent <= `BSV_ASSIGNMENT_DELAY wci_11_slvPresent$D_IN; + if (wci_11_wReset_n$EN) + wci_11_wReset_n <= `BSV_ASSIGNMENT_DELAY wci_11_wReset_n$D_IN; + if (wci_11_wTimeout$EN) + wci_11_wTimeout <= `BSV_ASSIGNMENT_DELAY wci_11_wTimeout$D_IN; + if (wci_12_busy$EN) + wci_12_busy <= `BSV_ASSIGNMENT_DELAY wci_12_busy$D_IN; + if (wci_12_lastConfigAddr$EN) + wci_12_lastConfigAddr <= `BSV_ASSIGNMENT_DELAY + wci_12_lastConfigAddr$D_IN; + if (wci_12_lastConfigBE$EN) + wci_12_lastConfigBE <= `BSV_ASSIGNMENT_DELAY + wci_12_lastConfigBE$D_IN; + if (wci_12_lastControlOp$EN) + wci_12_lastControlOp <= `BSV_ASSIGNMENT_DELAY + wci_12_lastControlOp$D_IN; + if (wci_12_lastOpWrite$EN) + wci_12_lastOpWrite <= `BSV_ASSIGNMENT_DELAY wci_12_lastOpWrite$D_IN; + if (wci_12_mFlagReg$EN) + wci_12_mFlagReg <= `BSV_ASSIGNMENT_DELAY wci_12_mFlagReg$D_IN; + if (wci_12_pageWindow$EN) + wci_12_pageWindow <= `BSV_ASSIGNMENT_DELAY wci_12_pageWindow$D_IN; + if (wci_12_reqERR$EN) + wci_12_reqERR <= `BSV_ASSIGNMENT_DELAY wci_12_reqERR$D_IN; + if (wci_12_reqFAIL$EN) + wci_12_reqFAIL <= `BSV_ASSIGNMENT_DELAY wci_12_reqFAIL$D_IN; + if (wci_12_reqF_cntr_r$EN) + wci_12_reqF_cntr_r <= `BSV_ASSIGNMENT_DELAY wci_12_reqF_cntr_r$D_IN; + if (wci_12_reqF_q_0$EN) + wci_12_reqF_q_0 <= `BSV_ASSIGNMENT_DELAY wci_12_reqF_q_0$D_IN; + if (wci_12_reqPend$EN) + wci_12_reqPend <= `BSV_ASSIGNMENT_DELAY wci_12_reqPend$D_IN; + if (wci_12_reqTO$EN) + wci_12_reqTO <= `BSV_ASSIGNMENT_DELAY wci_12_reqTO$D_IN; + if (wci_12_respTimr$EN) + wci_12_respTimr <= `BSV_ASSIGNMENT_DELAY wci_12_respTimr$D_IN; + if (wci_12_respTimrAct$EN) + wci_12_respTimrAct <= `BSV_ASSIGNMENT_DELAY wci_12_respTimrAct$D_IN; + if (wci_12_sThreadBusy_d$EN) + wci_12_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY + wci_12_sThreadBusy_d$D_IN; + if (wci_12_sfCap$EN) + wci_12_sfCap <= `BSV_ASSIGNMENT_DELAY wci_12_sfCap$D_IN; + if (wci_12_sfCapClear$EN) + wci_12_sfCapClear <= `BSV_ASSIGNMENT_DELAY wci_12_sfCapClear$D_IN; + if (wci_12_sfCapSet$EN) + wci_12_sfCapSet <= `BSV_ASSIGNMENT_DELAY wci_12_sfCapSet$D_IN; + if (wci_12_slvPresent$EN) + wci_12_slvPresent <= `BSV_ASSIGNMENT_DELAY wci_12_slvPresent$D_IN; + if (wci_12_wReset_n$EN) + wci_12_wReset_n <= `BSV_ASSIGNMENT_DELAY wci_12_wReset_n$D_IN; + if (wci_12_wTimeout$EN) + wci_12_wTimeout <= `BSV_ASSIGNMENT_DELAY wci_12_wTimeout$D_IN; + if (wci_13_busy$EN) + wci_13_busy <= `BSV_ASSIGNMENT_DELAY wci_13_busy$D_IN; + if (wci_13_lastConfigAddr$EN) + wci_13_lastConfigAddr <= `BSV_ASSIGNMENT_DELAY + wci_13_lastConfigAddr$D_IN; + if (wci_13_lastConfigBE$EN) + wci_13_lastConfigBE <= `BSV_ASSIGNMENT_DELAY + wci_13_lastConfigBE$D_IN; + if (wci_13_lastControlOp$EN) + wci_13_lastControlOp <= `BSV_ASSIGNMENT_DELAY + wci_13_lastControlOp$D_IN; + if (wci_13_lastOpWrite$EN) + wci_13_lastOpWrite <= `BSV_ASSIGNMENT_DELAY wci_13_lastOpWrite$D_IN; + if (wci_13_mFlagReg$EN) + wci_13_mFlagReg <= `BSV_ASSIGNMENT_DELAY wci_13_mFlagReg$D_IN; + if (wci_13_pageWindow$EN) + wci_13_pageWindow <= `BSV_ASSIGNMENT_DELAY wci_13_pageWindow$D_IN; + if (wci_13_reqERR$EN) + wci_13_reqERR <= `BSV_ASSIGNMENT_DELAY wci_13_reqERR$D_IN; + if (wci_13_reqFAIL$EN) + wci_13_reqFAIL <= `BSV_ASSIGNMENT_DELAY wci_13_reqFAIL$D_IN; + if (wci_13_reqF_cntr_r$EN) + wci_13_reqF_cntr_r <= `BSV_ASSIGNMENT_DELAY wci_13_reqF_cntr_r$D_IN; + if (wci_13_reqF_q_0$EN) + wci_13_reqF_q_0 <= `BSV_ASSIGNMENT_DELAY wci_13_reqF_q_0$D_IN; + if (wci_13_reqPend$EN) + wci_13_reqPend <= `BSV_ASSIGNMENT_DELAY wci_13_reqPend$D_IN; + if (wci_13_reqTO$EN) + wci_13_reqTO <= `BSV_ASSIGNMENT_DELAY wci_13_reqTO$D_IN; + if (wci_13_respTimr$EN) + wci_13_respTimr <= `BSV_ASSIGNMENT_DELAY wci_13_respTimr$D_IN; + if (wci_13_respTimrAct$EN) + wci_13_respTimrAct <= `BSV_ASSIGNMENT_DELAY wci_13_respTimrAct$D_IN; + if (wci_13_sThreadBusy_d$EN) + wci_13_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY + wci_13_sThreadBusy_d$D_IN; + if (wci_13_sfCap$EN) + wci_13_sfCap <= `BSV_ASSIGNMENT_DELAY wci_13_sfCap$D_IN; + if (wci_13_sfCapClear$EN) + wci_13_sfCapClear <= `BSV_ASSIGNMENT_DELAY wci_13_sfCapClear$D_IN; + if (wci_13_sfCapSet$EN) + wci_13_sfCapSet <= `BSV_ASSIGNMENT_DELAY wci_13_sfCapSet$D_IN; + if (wci_13_slvPresent$EN) + wci_13_slvPresent <= `BSV_ASSIGNMENT_DELAY wci_13_slvPresent$D_IN; + if (wci_13_wReset_n$EN) + wci_13_wReset_n <= `BSV_ASSIGNMENT_DELAY wci_13_wReset_n$D_IN; + if (wci_13_wTimeout$EN) + wci_13_wTimeout <= `BSV_ASSIGNMENT_DELAY wci_13_wTimeout$D_IN; + if (wci_14_busy$EN) + wci_14_busy <= `BSV_ASSIGNMENT_DELAY wci_14_busy$D_IN; + if (wci_14_lastConfigAddr$EN) + wci_14_lastConfigAddr <= `BSV_ASSIGNMENT_DELAY + wci_14_lastConfigAddr$D_IN; + if (wci_14_lastConfigBE$EN) + wci_14_lastConfigBE <= `BSV_ASSIGNMENT_DELAY + wci_14_lastConfigBE$D_IN; + if (wci_14_lastControlOp$EN) + wci_14_lastControlOp <= `BSV_ASSIGNMENT_DELAY + wci_14_lastControlOp$D_IN; + if (wci_14_lastOpWrite$EN) + wci_14_lastOpWrite <= `BSV_ASSIGNMENT_DELAY wci_14_lastOpWrite$D_IN; + if (wci_14_mFlagReg$EN) + wci_14_mFlagReg <= `BSV_ASSIGNMENT_DELAY wci_14_mFlagReg$D_IN; + if (wci_14_pageWindow$EN) + wci_14_pageWindow <= `BSV_ASSIGNMENT_DELAY wci_14_pageWindow$D_IN; + if (wci_14_reqERR$EN) + wci_14_reqERR <= `BSV_ASSIGNMENT_DELAY wci_14_reqERR$D_IN; + if (wci_14_reqFAIL$EN) + wci_14_reqFAIL <= `BSV_ASSIGNMENT_DELAY wci_14_reqFAIL$D_IN; + if (wci_14_reqF_cntr_r$EN) + wci_14_reqF_cntr_r <= `BSV_ASSIGNMENT_DELAY wci_14_reqF_cntr_r$D_IN; + if (wci_14_reqF_q_0$EN) + wci_14_reqF_q_0 <= `BSV_ASSIGNMENT_DELAY wci_14_reqF_q_0$D_IN; + if (wci_14_reqPend$EN) + wci_14_reqPend <= `BSV_ASSIGNMENT_DELAY wci_14_reqPend$D_IN; + if (wci_14_reqTO$EN) + wci_14_reqTO <= `BSV_ASSIGNMENT_DELAY wci_14_reqTO$D_IN; + if (wci_14_respTimr$EN) + wci_14_respTimr <= `BSV_ASSIGNMENT_DELAY wci_14_respTimr$D_IN; + if (wci_14_respTimrAct$EN) + wci_14_respTimrAct <= `BSV_ASSIGNMENT_DELAY wci_14_respTimrAct$D_IN; + if (wci_14_sThreadBusy_d$EN) + wci_14_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY + wci_14_sThreadBusy_d$D_IN; + if (wci_14_sfCap$EN) + wci_14_sfCap <= `BSV_ASSIGNMENT_DELAY wci_14_sfCap$D_IN; + if (wci_14_sfCapClear$EN) + wci_14_sfCapClear <= `BSV_ASSIGNMENT_DELAY wci_14_sfCapClear$D_IN; + if (wci_14_sfCapSet$EN) + wci_14_sfCapSet <= `BSV_ASSIGNMENT_DELAY wci_14_sfCapSet$D_IN; + if (wci_14_slvPresent$EN) + wci_14_slvPresent <= `BSV_ASSIGNMENT_DELAY wci_14_slvPresent$D_IN; + if (wci_14_wReset_n$EN) + wci_14_wReset_n <= `BSV_ASSIGNMENT_DELAY wci_14_wReset_n$D_IN; + if (wci_14_wTimeout$EN) + wci_14_wTimeout <= `BSV_ASSIGNMENT_DELAY wci_14_wTimeout$D_IN; + if (wci_1_busy$EN) + wci_1_busy <= `BSV_ASSIGNMENT_DELAY wci_1_busy$D_IN; + if (wci_1_lastConfigAddr$EN) + wci_1_lastConfigAddr <= `BSV_ASSIGNMENT_DELAY + wci_1_lastConfigAddr$D_IN; + if (wci_1_lastConfigBE$EN) + wci_1_lastConfigBE <= `BSV_ASSIGNMENT_DELAY wci_1_lastConfigBE$D_IN; + if (wci_1_lastControlOp$EN) + wci_1_lastControlOp <= `BSV_ASSIGNMENT_DELAY + wci_1_lastControlOp$D_IN; + if (wci_1_lastOpWrite$EN) + wci_1_lastOpWrite <= `BSV_ASSIGNMENT_DELAY wci_1_lastOpWrite$D_IN; + if (wci_1_mFlagReg$EN) + wci_1_mFlagReg <= `BSV_ASSIGNMENT_DELAY wci_1_mFlagReg$D_IN; + if (wci_1_pageWindow$EN) + wci_1_pageWindow <= `BSV_ASSIGNMENT_DELAY wci_1_pageWindow$D_IN; + if (wci_1_reqERR$EN) + wci_1_reqERR <= `BSV_ASSIGNMENT_DELAY wci_1_reqERR$D_IN; + if (wci_1_reqFAIL$EN) + wci_1_reqFAIL <= `BSV_ASSIGNMENT_DELAY wci_1_reqFAIL$D_IN; + if (wci_1_reqF_cntr_r$EN) + wci_1_reqF_cntr_r <= `BSV_ASSIGNMENT_DELAY wci_1_reqF_cntr_r$D_IN; + if (wci_1_reqF_q_0$EN) + wci_1_reqF_q_0 <= `BSV_ASSIGNMENT_DELAY wci_1_reqF_q_0$D_IN; + if (wci_1_reqPend$EN) + wci_1_reqPend <= `BSV_ASSIGNMENT_DELAY wci_1_reqPend$D_IN; + if (wci_1_reqTO$EN) + wci_1_reqTO <= `BSV_ASSIGNMENT_DELAY wci_1_reqTO$D_IN; + if (wci_1_respTimr$EN) + wci_1_respTimr <= `BSV_ASSIGNMENT_DELAY wci_1_respTimr$D_IN; + if (wci_1_respTimrAct$EN) + wci_1_respTimrAct <= `BSV_ASSIGNMENT_DELAY wci_1_respTimrAct$D_IN; + if (wci_1_sThreadBusy_d$EN) + wci_1_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY + wci_1_sThreadBusy_d$D_IN; + if (wci_1_sfCap$EN) + wci_1_sfCap <= `BSV_ASSIGNMENT_DELAY wci_1_sfCap$D_IN; + if (wci_1_sfCapClear$EN) + wci_1_sfCapClear <= `BSV_ASSIGNMENT_DELAY wci_1_sfCapClear$D_IN; + if (wci_1_sfCapSet$EN) + wci_1_sfCapSet <= `BSV_ASSIGNMENT_DELAY wci_1_sfCapSet$D_IN; + if (wci_1_slvPresent$EN) + wci_1_slvPresent <= `BSV_ASSIGNMENT_DELAY wci_1_slvPresent$D_IN; + if (wci_1_wReset_n$EN) + wci_1_wReset_n <= `BSV_ASSIGNMENT_DELAY wci_1_wReset_n$D_IN; + if (wci_1_wTimeout$EN) + wci_1_wTimeout <= `BSV_ASSIGNMENT_DELAY wci_1_wTimeout$D_IN; + if (wci_2_busy$EN) + wci_2_busy <= `BSV_ASSIGNMENT_DELAY wci_2_busy$D_IN; + if (wci_2_lastConfigAddr$EN) + wci_2_lastConfigAddr <= `BSV_ASSIGNMENT_DELAY + wci_2_lastConfigAddr$D_IN; + if (wci_2_lastConfigBE$EN) + wci_2_lastConfigBE <= `BSV_ASSIGNMENT_DELAY wci_2_lastConfigBE$D_IN; + if (wci_2_lastControlOp$EN) + wci_2_lastControlOp <= `BSV_ASSIGNMENT_DELAY + wci_2_lastControlOp$D_IN; + if (wci_2_lastOpWrite$EN) + wci_2_lastOpWrite <= `BSV_ASSIGNMENT_DELAY wci_2_lastOpWrite$D_IN; + if (wci_2_mFlagReg$EN) + wci_2_mFlagReg <= `BSV_ASSIGNMENT_DELAY wci_2_mFlagReg$D_IN; + if (wci_2_pageWindow$EN) + wci_2_pageWindow <= `BSV_ASSIGNMENT_DELAY wci_2_pageWindow$D_IN; + if (wci_2_reqERR$EN) + wci_2_reqERR <= `BSV_ASSIGNMENT_DELAY wci_2_reqERR$D_IN; + if (wci_2_reqFAIL$EN) + wci_2_reqFAIL <= `BSV_ASSIGNMENT_DELAY wci_2_reqFAIL$D_IN; + if (wci_2_reqF_cntr_r$EN) + wci_2_reqF_cntr_r <= `BSV_ASSIGNMENT_DELAY wci_2_reqF_cntr_r$D_IN; + if (wci_2_reqF_q_0$EN) + wci_2_reqF_q_0 <= `BSV_ASSIGNMENT_DELAY wci_2_reqF_q_0$D_IN; + if (wci_2_reqPend$EN) + wci_2_reqPend <= `BSV_ASSIGNMENT_DELAY wci_2_reqPend$D_IN; + if (wci_2_reqTO$EN) + wci_2_reqTO <= `BSV_ASSIGNMENT_DELAY wci_2_reqTO$D_IN; + if (wci_2_respTimr$EN) + wci_2_respTimr <= `BSV_ASSIGNMENT_DELAY wci_2_respTimr$D_IN; + if (wci_2_respTimrAct$EN) + wci_2_respTimrAct <= `BSV_ASSIGNMENT_DELAY wci_2_respTimrAct$D_IN; + if (wci_2_sThreadBusy_d$EN) + wci_2_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY + wci_2_sThreadBusy_d$D_IN; + if (wci_2_sfCap$EN) + wci_2_sfCap <= `BSV_ASSIGNMENT_DELAY wci_2_sfCap$D_IN; + if (wci_2_sfCapClear$EN) + wci_2_sfCapClear <= `BSV_ASSIGNMENT_DELAY wci_2_sfCapClear$D_IN; + if (wci_2_sfCapSet$EN) + wci_2_sfCapSet <= `BSV_ASSIGNMENT_DELAY wci_2_sfCapSet$D_IN; + if (wci_2_slvPresent$EN) + wci_2_slvPresent <= `BSV_ASSIGNMENT_DELAY wci_2_slvPresent$D_IN; + if (wci_2_wReset_n$EN) + wci_2_wReset_n <= `BSV_ASSIGNMENT_DELAY wci_2_wReset_n$D_IN; + if (wci_2_wTimeout$EN) + wci_2_wTimeout <= `BSV_ASSIGNMENT_DELAY wci_2_wTimeout$D_IN; + if (wci_3_busy$EN) + wci_3_busy <= `BSV_ASSIGNMENT_DELAY wci_3_busy$D_IN; + if (wci_3_lastConfigAddr$EN) + wci_3_lastConfigAddr <= `BSV_ASSIGNMENT_DELAY + wci_3_lastConfigAddr$D_IN; + if (wci_3_lastConfigBE$EN) + wci_3_lastConfigBE <= `BSV_ASSIGNMENT_DELAY wci_3_lastConfigBE$D_IN; + if (wci_3_lastControlOp$EN) + wci_3_lastControlOp <= `BSV_ASSIGNMENT_DELAY + wci_3_lastControlOp$D_IN; + if (wci_3_lastOpWrite$EN) + wci_3_lastOpWrite <= `BSV_ASSIGNMENT_DELAY wci_3_lastOpWrite$D_IN; + if (wci_3_mFlagReg$EN) + wci_3_mFlagReg <= `BSV_ASSIGNMENT_DELAY wci_3_mFlagReg$D_IN; + if (wci_3_pageWindow$EN) + wci_3_pageWindow <= `BSV_ASSIGNMENT_DELAY wci_3_pageWindow$D_IN; + if (wci_3_reqERR$EN) + wci_3_reqERR <= `BSV_ASSIGNMENT_DELAY wci_3_reqERR$D_IN; + if (wci_3_reqFAIL$EN) + wci_3_reqFAIL <= `BSV_ASSIGNMENT_DELAY wci_3_reqFAIL$D_IN; + if (wci_3_reqF_cntr_r$EN) + wci_3_reqF_cntr_r <= `BSV_ASSIGNMENT_DELAY wci_3_reqF_cntr_r$D_IN; + if (wci_3_reqF_q_0$EN) + wci_3_reqF_q_0 <= `BSV_ASSIGNMENT_DELAY wci_3_reqF_q_0$D_IN; + if (wci_3_reqPend$EN) + wci_3_reqPend <= `BSV_ASSIGNMENT_DELAY wci_3_reqPend$D_IN; + if (wci_3_reqTO$EN) + wci_3_reqTO <= `BSV_ASSIGNMENT_DELAY wci_3_reqTO$D_IN; + if (wci_3_respTimr$EN) + wci_3_respTimr <= `BSV_ASSIGNMENT_DELAY wci_3_respTimr$D_IN; + if (wci_3_respTimrAct$EN) + wci_3_respTimrAct <= `BSV_ASSIGNMENT_DELAY wci_3_respTimrAct$D_IN; + if (wci_3_sThreadBusy_d$EN) + wci_3_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY + wci_3_sThreadBusy_d$D_IN; + if (wci_3_sfCap$EN) + wci_3_sfCap <= `BSV_ASSIGNMENT_DELAY wci_3_sfCap$D_IN; + if (wci_3_sfCapClear$EN) + wci_3_sfCapClear <= `BSV_ASSIGNMENT_DELAY wci_3_sfCapClear$D_IN; + if (wci_3_sfCapSet$EN) + wci_3_sfCapSet <= `BSV_ASSIGNMENT_DELAY wci_3_sfCapSet$D_IN; + if (wci_3_slvPresent$EN) + wci_3_slvPresent <= `BSV_ASSIGNMENT_DELAY wci_3_slvPresent$D_IN; + if (wci_3_wReset_n$EN) + wci_3_wReset_n <= `BSV_ASSIGNMENT_DELAY wci_3_wReset_n$D_IN; + if (wci_3_wTimeout$EN) + wci_3_wTimeout <= `BSV_ASSIGNMENT_DELAY wci_3_wTimeout$D_IN; + if (wci_4_busy$EN) + wci_4_busy <= `BSV_ASSIGNMENT_DELAY wci_4_busy$D_IN; + if (wci_4_lastConfigAddr$EN) + wci_4_lastConfigAddr <= `BSV_ASSIGNMENT_DELAY + wci_4_lastConfigAddr$D_IN; + if (wci_4_lastConfigBE$EN) + wci_4_lastConfigBE <= `BSV_ASSIGNMENT_DELAY wci_4_lastConfigBE$D_IN; + if (wci_4_lastControlOp$EN) + wci_4_lastControlOp <= `BSV_ASSIGNMENT_DELAY + wci_4_lastControlOp$D_IN; + if (wci_4_lastOpWrite$EN) + wci_4_lastOpWrite <= `BSV_ASSIGNMENT_DELAY wci_4_lastOpWrite$D_IN; + if (wci_4_mFlagReg$EN) + wci_4_mFlagReg <= `BSV_ASSIGNMENT_DELAY wci_4_mFlagReg$D_IN; + if (wci_4_pageWindow$EN) + wci_4_pageWindow <= `BSV_ASSIGNMENT_DELAY wci_4_pageWindow$D_IN; + if (wci_4_reqERR$EN) + wci_4_reqERR <= `BSV_ASSIGNMENT_DELAY wci_4_reqERR$D_IN; + if (wci_4_reqFAIL$EN) + wci_4_reqFAIL <= `BSV_ASSIGNMENT_DELAY wci_4_reqFAIL$D_IN; + if (wci_4_reqF_cntr_r$EN) + wci_4_reqF_cntr_r <= `BSV_ASSIGNMENT_DELAY wci_4_reqF_cntr_r$D_IN; + if (wci_4_reqF_q_0$EN) + wci_4_reqF_q_0 <= `BSV_ASSIGNMENT_DELAY wci_4_reqF_q_0$D_IN; + if (wci_4_reqPend$EN) + wci_4_reqPend <= `BSV_ASSIGNMENT_DELAY wci_4_reqPend$D_IN; + if (wci_4_reqTO$EN) + wci_4_reqTO <= `BSV_ASSIGNMENT_DELAY wci_4_reqTO$D_IN; + if (wci_4_respTimr$EN) + wci_4_respTimr <= `BSV_ASSIGNMENT_DELAY wci_4_respTimr$D_IN; + if (wci_4_respTimrAct$EN) + wci_4_respTimrAct <= `BSV_ASSIGNMENT_DELAY wci_4_respTimrAct$D_IN; + if (wci_4_sThreadBusy_d$EN) + wci_4_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY + wci_4_sThreadBusy_d$D_IN; + if (wci_4_sfCap$EN) + wci_4_sfCap <= `BSV_ASSIGNMENT_DELAY wci_4_sfCap$D_IN; + if (wci_4_sfCapClear$EN) + wci_4_sfCapClear <= `BSV_ASSIGNMENT_DELAY wci_4_sfCapClear$D_IN; + if (wci_4_sfCapSet$EN) + wci_4_sfCapSet <= `BSV_ASSIGNMENT_DELAY wci_4_sfCapSet$D_IN; + if (wci_4_slvPresent$EN) + wci_4_slvPresent <= `BSV_ASSIGNMENT_DELAY wci_4_slvPresent$D_IN; + if (wci_4_wReset_n$EN) + wci_4_wReset_n <= `BSV_ASSIGNMENT_DELAY wci_4_wReset_n$D_IN; + if (wci_4_wTimeout$EN) + wci_4_wTimeout <= `BSV_ASSIGNMENT_DELAY wci_4_wTimeout$D_IN; + if (wci_5_busy$EN) + wci_5_busy <= `BSV_ASSIGNMENT_DELAY wci_5_busy$D_IN; + if (wci_5_lastConfigAddr$EN) + wci_5_lastConfigAddr <= `BSV_ASSIGNMENT_DELAY + wci_5_lastConfigAddr$D_IN; + if (wci_5_lastConfigBE$EN) + wci_5_lastConfigBE <= `BSV_ASSIGNMENT_DELAY wci_5_lastConfigBE$D_IN; + if (wci_5_lastControlOp$EN) + wci_5_lastControlOp <= `BSV_ASSIGNMENT_DELAY + wci_5_lastControlOp$D_IN; + if (wci_5_lastOpWrite$EN) + wci_5_lastOpWrite <= `BSV_ASSIGNMENT_DELAY wci_5_lastOpWrite$D_IN; + if (wci_5_mFlagReg$EN) + wci_5_mFlagReg <= `BSV_ASSIGNMENT_DELAY wci_5_mFlagReg$D_IN; + if (wci_5_pageWindow$EN) + wci_5_pageWindow <= `BSV_ASSIGNMENT_DELAY wci_5_pageWindow$D_IN; + if (wci_5_reqERR$EN) + wci_5_reqERR <= `BSV_ASSIGNMENT_DELAY wci_5_reqERR$D_IN; + if (wci_5_reqFAIL$EN) + wci_5_reqFAIL <= `BSV_ASSIGNMENT_DELAY wci_5_reqFAIL$D_IN; + if (wci_5_reqF_cntr_r$EN) + wci_5_reqF_cntr_r <= `BSV_ASSIGNMENT_DELAY wci_5_reqF_cntr_r$D_IN; + if (wci_5_reqF_q_0$EN) + wci_5_reqF_q_0 <= `BSV_ASSIGNMENT_DELAY wci_5_reqF_q_0$D_IN; + if (wci_5_reqPend$EN) + wci_5_reqPend <= `BSV_ASSIGNMENT_DELAY wci_5_reqPend$D_IN; + if (wci_5_reqTO$EN) + wci_5_reqTO <= `BSV_ASSIGNMENT_DELAY wci_5_reqTO$D_IN; + if (wci_5_respTimr$EN) + wci_5_respTimr <= `BSV_ASSIGNMENT_DELAY wci_5_respTimr$D_IN; + if (wci_5_respTimrAct$EN) + wci_5_respTimrAct <= `BSV_ASSIGNMENT_DELAY wci_5_respTimrAct$D_IN; + if (wci_5_sThreadBusy_d$EN) + wci_5_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY + wci_5_sThreadBusy_d$D_IN; + if (wci_5_sfCap$EN) + wci_5_sfCap <= `BSV_ASSIGNMENT_DELAY wci_5_sfCap$D_IN; + if (wci_5_sfCapClear$EN) + wci_5_sfCapClear <= `BSV_ASSIGNMENT_DELAY wci_5_sfCapClear$D_IN; + if (wci_5_sfCapSet$EN) + wci_5_sfCapSet <= `BSV_ASSIGNMENT_DELAY wci_5_sfCapSet$D_IN; + if (wci_5_slvPresent$EN) + wci_5_slvPresent <= `BSV_ASSIGNMENT_DELAY wci_5_slvPresent$D_IN; + if (wci_5_wReset_n$EN) + wci_5_wReset_n <= `BSV_ASSIGNMENT_DELAY wci_5_wReset_n$D_IN; + if (wci_5_wTimeout$EN) + wci_5_wTimeout <= `BSV_ASSIGNMENT_DELAY wci_5_wTimeout$D_IN; + if (wci_6_busy$EN) + wci_6_busy <= `BSV_ASSIGNMENT_DELAY wci_6_busy$D_IN; + if (wci_6_lastConfigAddr$EN) + wci_6_lastConfigAddr <= `BSV_ASSIGNMENT_DELAY + wci_6_lastConfigAddr$D_IN; + if (wci_6_lastConfigBE$EN) + wci_6_lastConfigBE <= `BSV_ASSIGNMENT_DELAY wci_6_lastConfigBE$D_IN; + if (wci_6_lastControlOp$EN) + wci_6_lastControlOp <= `BSV_ASSIGNMENT_DELAY + wci_6_lastControlOp$D_IN; + if (wci_6_lastOpWrite$EN) + wci_6_lastOpWrite <= `BSV_ASSIGNMENT_DELAY wci_6_lastOpWrite$D_IN; + if (wci_6_mFlagReg$EN) + wci_6_mFlagReg <= `BSV_ASSIGNMENT_DELAY wci_6_mFlagReg$D_IN; + if (wci_6_pageWindow$EN) + wci_6_pageWindow <= `BSV_ASSIGNMENT_DELAY wci_6_pageWindow$D_IN; + if (wci_6_reqERR$EN) + wci_6_reqERR <= `BSV_ASSIGNMENT_DELAY wci_6_reqERR$D_IN; + if (wci_6_reqFAIL$EN) + wci_6_reqFAIL <= `BSV_ASSIGNMENT_DELAY wci_6_reqFAIL$D_IN; + if (wci_6_reqF_cntr_r$EN) + wci_6_reqF_cntr_r <= `BSV_ASSIGNMENT_DELAY wci_6_reqF_cntr_r$D_IN; + if (wci_6_reqF_q_0$EN) + wci_6_reqF_q_0 <= `BSV_ASSIGNMENT_DELAY wci_6_reqF_q_0$D_IN; + if (wci_6_reqPend$EN) + wci_6_reqPend <= `BSV_ASSIGNMENT_DELAY wci_6_reqPend$D_IN; + if (wci_6_reqTO$EN) + wci_6_reqTO <= `BSV_ASSIGNMENT_DELAY wci_6_reqTO$D_IN; + if (wci_6_respTimr$EN) + wci_6_respTimr <= `BSV_ASSIGNMENT_DELAY wci_6_respTimr$D_IN; + if (wci_6_respTimrAct$EN) + wci_6_respTimrAct <= `BSV_ASSIGNMENT_DELAY wci_6_respTimrAct$D_IN; + if (wci_6_sThreadBusy_d$EN) + wci_6_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY + wci_6_sThreadBusy_d$D_IN; + if (wci_6_sfCap$EN) + wci_6_sfCap <= `BSV_ASSIGNMENT_DELAY wci_6_sfCap$D_IN; + if (wci_6_sfCapClear$EN) + wci_6_sfCapClear <= `BSV_ASSIGNMENT_DELAY wci_6_sfCapClear$D_IN; + if (wci_6_sfCapSet$EN) + wci_6_sfCapSet <= `BSV_ASSIGNMENT_DELAY wci_6_sfCapSet$D_IN; + if (wci_6_slvPresent$EN) + wci_6_slvPresent <= `BSV_ASSIGNMENT_DELAY wci_6_slvPresent$D_IN; + if (wci_6_wReset_n$EN) + wci_6_wReset_n <= `BSV_ASSIGNMENT_DELAY wci_6_wReset_n$D_IN; + if (wci_6_wTimeout$EN) + wci_6_wTimeout <= `BSV_ASSIGNMENT_DELAY wci_6_wTimeout$D_IN; + if (wci_7_busy$EN) + wci_7_busy <= `BSV_ASSIGNMENT_DELAY wci_7_busy$D_IN; + if (wci_7_lastConfigAddr$EN) + wci_7_lastConfigAddr <= `BSV_ASSIGNMENT_DELAY + wci_7_lastConfigAddr$D_IN; + if (wci_7_lastConfigBE$EN) + wci_7_lastConfigBE <= `BSV_ASSIGNMENT_DELAY wci_7_lastConfigBE$D_IN; + if (wci_7_lastControlOp$EN) + wci_7_lastControlOp <= `BSV_ASSIGNMENT_DELAY + wci_7_lastControlOp$D_IN; + if (wci_7_lastOpWrite$EN) + wci_7_lastOpWrite <= `BSV_ASSIGNMENT_DELAY wci_7_lastOpWrite$D_IN; + if (wci_7_mFlagReg$EN) + wci_7_mFlagReg <= `BSV_ASSIGNMENT_DELAY wci_7_mFlagReg$D_IN; + if (wci_7_pageWindow$EN) + wci_7_pageWindow <= `BSV_ASSIGNMENT_DELAY wci_7_pageWindow$D_IN; + if (wci_7_reqERR$EN) + wci_7_reqERR <= `BSV_ASSIGNMENT_DELAY wci_7_reqERR$D_IN; + if (wci_7_reqFAIL$EN) + wci_7_reqFAIL <= `BSV_ASSIGNMENT_DELAY wci_7_reqFAIL$D_IN; + if (wci_7_reqF_cntr_r$EN) + wci_7_reqF_cntr_r <= `BSV_ASSIGNMENT_DELAY wci_7_reqF_cntr_r$D_IN; + if (wci_7_reqF_q_0$EN) + wci_7_reqF_q_0 <= `BSV_ASSIGNMENT_DELAY wci_7_reqF_q_0$D_IN; + if (wci_7_reqPend$EN) + wci_7_reqPend <= `BSV_ASSIGNMENT_DELAY wci_7_reqPend$D_IN; + if (wci_7_reqTO$EN) + wci_7_reqTO <= `BSV_ASSIGNMENT_DELAY wci_7_reqTO$D_IN; + if (wci_7_respTimr$EN) + wci_7_respTimr <= `BSV_ASSIGNMENT_DELAY wci_7_respTimr$D_IN; + if (wci_7_respTimrAct$EN) + wci_7_respTimrAct <= `BSV_ASSIGNMENT_DELAY wci_7_respTimrAct$D_IN; + if (wci_7_sThreadBusy_d$EN) + wci_7_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY + wci_7_sThreadBusy_d$D_IN; + if (wci_7_sfCap$EN) + wci_7_sfCap <= `BSV_ASSIGNMENT_DELAY wci_7_sfCap$D_IN; + if (wci_7_sfCapClear$EN) + wci_7_sfCapClear <= `BSV_ASSIGNMENT_DELAY wci_7_sfCapClear$D_IN; + if (wci_7_sfCapSet$EN) + wci_7_sfCapSet <= `BSV_ASSIGNMENT_DELAY wci_7_sfCapSet$D_IN; + if (wci_7_slvPresent$EN) + wci_7_slvPresent <= `BSV_ASSIGNMENT_DELAY wci_7_slvPresent$D_IN; + if (wci_7_wReset_n$EN) + wci_7_wReset_n <= `BSV_ASSIGNMENT_DELAY wci_7_wReset_n$D_IN; + if (wci_7_wTimeout$EN) + wci_7_wTimeout <= `BSV_ASSIGNMENT_DELAY wci_7_wTimeout$D_IN; + if (wci_8_busy$EN) + wci_8_busy <= `BSV_ASSIGNMENT_DELAY wci_8_busy$D_IN; + if (wci_8_lastConfigAddr$EN) + wci_8_lastConfigAddr <= `BSV_ASSIGNMENT_DELAY + wci_8_lastConfigAddr$D_IN; + if (wci_8_lastConfigBE$EN) + wci_8_lastConfigBE <= `BSV_ASSIGNMENT_DELAY wci_8_lastConfigBE$D_IN; + if (wci_8_lastControlOp$EN) + wci_8_lastControlOp <= `BSV_ASSIGNMENT_DELAY + wci_8_lastControlOp$D_IN; + if (wci_8_lastOpWrite$EN) + wci_8_lastOpWrite <= `BSV_ASSIGNMENT_DELAY wci_8_lastOpWrite$D_IN; + if (wci_8_mFlagReg$EN) + wci_8_mFlagReg <= `BSV_ASSIGNMENT_DELAY wci_8_mFlagReg$D_IN; + if (wci_8_pageWindow$EN) + wci_8_pageWindow <= `BSV_ASSIGNMENT_DELAY wci_8_pageWindow$D_IN; + if (wci_8_reqERR$EN) + wci_8_reqERR <= `BSV_ASSIGNMENT_DELAY wci_8_reqERR$D_IN; + if (wci_8_reqFAIL$EN) + wci_8_reqFAIL <= `BSV_ASSIGNMENT_DELAY wci_8_reqFAIL$D_IN; + if (wci_8_reqF_cntr_r$EN) + wci_8_reqF_cntr_r <= `BSV_ASSIGNMENT_DELAY wci_8_reqF_cntr_r$D_IN; + if (wci_8_reqF_q_0$EN) + wci_8_reqF_q_0 <= `BSV_ASSIGNMENT_DELAY wci_8_reqF_q_0$D_IN; + if (wci_8_reqPend$EN) + wci_8_reqPend <= `BSV_ASSIGNMENT_DELAY wci_8_reqPend$D_IN; + if (wci_8_reqTO$EN) + wci_8_reqTO <= `BSV_ASSIGNMENT_DELAY wci_8_reqTO$D_IN; + if (wci_8_respTimr$EN) + wci_8_respTimr <= `BSV_ASSIGNMENT_DELAY wci_8_respTimr$D_IN; + if (wci_8_respTimrAct$EN) + wci_8_respTimrAct <= `BSV_ASSIGNMENT_DELAY wci_8_respTimrAct$D_IN; + if (wci_8_sThreadBusy_d$EN) + wci_8_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY + wci_8_sThreadBusy_d$D_IN; + if (wci_8_sfCap$EN) + wci_8_sfCap <= `BSV_ASSIGNMENT_DELAY wci_8_sfCap$D_IN; + if (wci_8_sfCapClear$EN) + wci_8_sfCapClear <= `BSV_ASSIGNMENT_DELAY wci_8_sfCapClear$D_IN; + if (wci_8_sfCapSet$EN) + wci_8_sfCapSet <= `BSV_ASSIGNMENT_DELAY wci_8_sfCapSet$D_IN; + if (wci_8_slvPresent$EN) + wci_8_slvPresent <= `BSV_ASSIGNMENT_DELAY wci_8_slvPresent$D_IN; + if (wci_8_wReset_n$EN) + wci_8_wReset_n <= `BSV_ASSIGNMENT_DELAY wci_8_wReset_n$D_IN; + if (wci_8_wTimeout$EN) + wci_8_wTimeout <= `BSV_ASSIGNMENT_DELAY wci_8_wTimeout$D_IN; + if (wci_9_busy$EN) + wci_9_busy <= `BSV_ASSIGNMENT_DELAY wci_9_busy$D_IN; + if (wci_9_lastConfigAddr$EN) + wci_9_lastConfigAddr <= `BSV_ASSIGNMENT_DELAY + wci_9_lastConfigAddr$D_IN; + if (wci_9_lastConfigBE$EN) + wci_9_lastConfigBE <= `BSV_ASSIGNMENT_DELAY wci_9_lastConfigBE$D_IN; + if (wci_9_lastControlOp$EN) + wci_9_lastControlOp <= `BSV_ASSIGNMENT_DELAY + wci_9_lastControlOp$D_IN; + if (wci_9_lastOpWrite$EN) + wci_9_lastOpWrite <= `BSV_ASSIGNMENT_DELAY wci_9_lastOpWrite$D_IN; + if (wci_9_mFlagReg$EN) + wci_9_mFlagReg <= `BSV_ASSIGNMENT_DELAY wci_9_mFlagReg$D_IN; + if (wci_9_pageWindow$EN) + wci_9_pageWindow <= `BSV_ASSIGNMENT_DELAY wci_9_pageWindow$D_IN; + if (wci_9_reqERR$EN) + wci_9_reqERR <= `BSV_ASSIGNMENT_DELAY wci_9_reqERR$D_IN; + if (wci_9_reqFAIL$EN) + wci_9_reqFAIL <= `BSV_ASSIGNMENT_DELAY wci_9_reqFAIL$D_IN; + if (wci_9_reqF_cntr_r$EN) + wci_9_reqF_cntr_r <= `BSV_ASSIGNMENT_DELAY wci_9_reqF_cntr_r$D_IN; + if (wci_9_reqF_q_0$EN) + wci_9_reqF_q_0 <= `BSV_ASSIGNMENT_DELAY wci_9_reqF_q_0$D_IN; + if (wci_9_reqPend$EN) + wci_9_reqPend <= `BSV_ASSIGNMENT_DELAY wci_9_reqPend$D_IN; + if (wci_9_reqTO$EN) + wci_9_reqTO <= `BSV_ASSIGNMENT_DELAY wci_9_reqTO$D_IN; + if (wci_9_respTimr$EN) + wci_9_respTimr <= `BSV_ASSIGNMENT_DELAY wci_9_respTimr$D_IN; + if (wci_9_respTimrAct$EN) + wci_9_respTimrAct <= `BSV_ASSIGNMENT_DELAY wci_9_respTimrAct$D_IN; + if (wci_9_sThreadBusy_d$EN) + wci_9_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY + wci_9_sThreadBusy_d$D_IN; + if (wci_9_sfCap$EN) + wci_9_sfCap <= `BSV_ASSIGNMENT_DELAY wci_9_sfCap$D_IN; + if (wci_9_sfCapClear$EN) + wci_9_sfCapClear <= `BSV_ASSIGNMENT_DELAY wci_9_sfCapClear$D_IN; + if (wci_9_sfCapSet$EN) + wci_9_sfCapSet <= `BSV_ASSIGNMENT_DELAY wci_9_sfCapSet$D_IN; + if (wci_9_slvPresent$EN) + wci_9_slvPresent <= `BSV_ASSIGNMENT_DELAY wci_9_slvPresent$D_IN; + if (wci_9_wReset_n$EN) + wci_9_wReset_n <= `BSV_ASSIGNMENT_DELAY wci_9_wReset_n$D_IN; + if (wci_9_wTimeout$EN) + wci_9_wTimeout <= `BSV_ASSIGNMENT_DELAY wci_9_wTimeout$D_IN; if (wrkAct$EN) wrkAct <= `BSV_ASSIGNMENT_DELAY wrkAct$D_IN; end if (seqTag$EN) seqTag <= `BSV_ASSIGNMENT_DELAY seqTag$D_IN; if (switch_d$EN) switch_d <= `BSV_ASSIGNMENT_DELAY switch_d$D_IN; if (td$EN) td <= `BSV_ASSIGNMENT_DELAY td$D_IN; - if (wci_wStatus$EN) wci_wStatus <= `BSV_ASSIGNMENT_DELAY wci_wStatus$D_IN; - if (wci_wStatus_1$EN) - wci_wStatus_1 <= `BSV_ASSIGNMENT_DELAY wci_wStatus_1$D_IN; - if (wci_wStatus_10$EN) - wci_wStatus_10 <= `BSV_ASSIGNMENT_DELAY wci_wStatus_10$D_IN; - if (wci_wStatus_11$EN) - wci_wStatus_11 <= `BSV_ASSIGNMENT_DELAY wci_wStatus_11$D_IN; - if (wci_wStatus_12$EN) - wci_wStatus_12 <= `BSV_ASSIGNMENT_DELAY wci_wStatus_12$D_IN; - if (wci_wStatus_13$EN) - wci_wStatus_13 <= `BSV_ASSIGNMENT_DELAY wci_wStatus_13$D_IN; - if (wci_wStatus_14$EN) - wci_wStatus_14 <= `BSV_ASSIGNMENT_DELAY wci_wStatus_14$D_IN; - if (wci_wStatus_2$EN) - wci_wStatus_2 <= `BSV_ASSIGNMENT_DELAY wci_wStatus_2$D_IN; - if (wci_wStatus_3$EN) - wci_wStatus_3 <= `BSV_ASSIGNMENT_DELAY wci_wStatus_3$D_IN; - if (wci_wStatus_4$EN) - wci_wStatus_4 <= `BSV_ASSIGNMENT_DELAY wci_wStatus_4$D_IN; - if (wci_wStatus_5$EN) - wci_wStatus_5 <= `BSV_ASSIGNMENT_DELAY wci_wStatus_5$D_IN; - if (wci_wStatus_6$EN) - wci_wStatus_6 <= `BSV_ASSIGNMENT_DELAY wci_wStatus_6$D_IN; - if (wci_wStatus_7$EN) - wci_wStatus_7 <= `BSV_ASSIGNMENT_DELAY wci_wStatus_7$D_IN; - if (wci_wStatus_8$EN) - wci_wStatus_8 <= `BSV_ASSIGNMENT_DELAY wci_wStatus_8$D_IN; - if (wci_wStatus_9$EN) - wci_wStatus_9 <= `BSV_ASSIGNMENT_DELAY wci_wStatus_9$D_IN; + if (wci_0_wStatus$EN) + wci_0_wStatus <= `BSV_ASSIGNMENT_DELAY wci_0_wStatus$D_IN; + if (wci_10_wStatus$EN) + wci_10_wStatus <= `BSV_ASSIGNMENT_DELAY wci_10_wStatus$D_IN; + if (wci_11_wStatus$EN) + wci_11_wStatus <= `BSV_ASSIGNMENT_DELAY wci_11_wStatus$D_IN; + if (wci_12_wStatus$EN) + wci_12_wStatus <= `BSV_ASSIGNMENT_DELAY wci_12_wStatus$D_IN; + if (wci_13_wStatus$EN) + wci_13_wStatus <= `BSV_ASSIGNMENT_DELAY wci_13_wStatus$D_IN; + if (wci_14_wStatus$EN) + wci_14_wStatus <= `BSV_ASSIGNMENT_DELAY wci_14_wStatus$D_IN; + if (wci_1_wStatus$EN) + wci_1_wStatus <= `BSV_ASSIGNMENT_DELAY wci_1_wStatus$D_IN; + if (wci_2_wStatus$EN) + wci_2_wStatus <= `BSV_ASSIGNMENT_DELAY wci_2_wStatus$D_IN; + if (wci_3_wStatus$EN) + wci_3_wStatus <= `BSV_ASSIGNMENT_DELAY wci_3_wStatus$D_IN; + if (wci_4_wStatus$EN) + wci_4_wStatus <= `BSV_ASSIGNMENT_DELAY wci_4_wStatus$D_IN; + if (wci_5_wStatus$EN) + wci_5_wStatus <= `BSV_ASSIGNMENT_DELAY wci_5_wStatus$D_IN; + if (wci_6_wStatus$EN) + wci_6_wStatus <= `BSV_ASSIGNMENT_DELAY wci_6_wStatus$D_IN; + if (wci_7_wStatus$EN) + wci_7_wStatus <= `BSV_ASSIGNMENT_DELAY wci_7_wStatus$D_IN; + if (wci_8_wStatus$EN) + wci_8_wStatus <= `BSV_ASSIGNMENT_DELAY wci_8_wStatus$D_IN; + if (wci_9_wStatus$EN) + wci_9_wStatus <= `BSV_ASSIGNMENT_DELAY wci_9_wStatus$D_IN; end always@(posedge CLK_time_clk) @@ -18995,6 +25717,10 @@ module mkOCCP(pciDevice, cpReq = 65'h0AAAAAAAAAAAAAAAA; deltaTime = 64'hAAAAAAAAAAAAAAAA; dispatched = 1'h0; + dna_cnt = 7'h2A; + dna_rdReg = 1'h0; + dna_shftReg = 1'h0; + dna_sr = 57'h0AAAAAAAAAAAAAA; readCntReg = 32'hAAAAAAAA; rogueTLP = 4'hA; rom_serverAdapter_cnt = 3'h2; @@ -19033,351 +25759,351 @@ module mkOCCP(pciDevice, timeServ_timeSetSticky = 1'h0; timeServ_xo2 = 1'h0; warmResetP = 1'h0; - wci_busy = 1'h0; - wci_busy_1 = 1'h0; - wci_busy_10 = 1'h0; - wci_busy_11 = 1'h0; - wci_busy_12 = 1'h0; - wci_busy_13 = 1'h0; - wci_busy_14 = 1'h0; - wci_busy_2 = 1'h0; - wci_busy_3 = 1'h0; - wci_busy_4 = 1'h0; - wci_busy_5 = 1'h0; - wci_busy_6 = 1'h0; - wci_busy_7 = 1'h0; - wci_busy_8 = 1'h0; - wci_busy_9 = 1'h0; - wci_lastConfigAddr = 33'h0AAAAAAAA; - wci_lastConfigAddr_1 = 33'h0AAAAAAAA; - wci_lastConfigAddr_10 = 33'h0AAAAAAAA; - wci_lastConfigAddr_11 = 33'h0AAAAAAAA; - wci_lastConfigAddr_12 = 33'h0AAAAAAAA; - wci_lastConfigAddr_13 = 33'h0AAAAAAAA; - wci_lastConfigAddr_14 = 33'h0AAAAAAAA; - wci_lastConfigAddr_2 = 33'h0AAAAAAAA; - wci_lastConfigAddr_3 = 33'h0AAAAAAAA; - wci_lastConfigAddr_4 = 33'h0AAAAAAAA; - wci_lastConfigAddr_5 = 33'h0AAAAAAAA; - wci_lastConfigAddr_6 = 33'h0AAAAAAAA; - wci_lastConfigAddr_7 = 33'h0AAAAAAAA; - wci_lastConfigAddr_8 = 33'h0AAAAAAAA; - wci_lastConfigAddr_9 = 33'h0AAAAAAAA; - wci_lastConfigBE = 5'h0A; - wci_lastConfigBE_1 = 5'h0A; - wci_lastConfigBE_10 = 5'h0A; - wci_lastConfigBE_11 = 5'h0A; - wci_lastConfigBE_12 = 5'h0A; - wci_lastConfigBE_13 = 5'h0A; - wci_lastConfigBE_14 = 5'h0A; - wci_lastConfigBE_2 = 5'h0A; - wci_lastConfigBE_3 = 5'h0A; - wci_lastConfigBE_4 = 5'h0A; - wci_lastConfigBE_5 = 5'h0A; - wci_lastConfigBE_6 = 5'h0A; - wci_lastConfigBE_7 = 5'h0A; - wci_lastConfigBE_8 = 5'h0A; - wci_lastConfigBE_9 = 5'h0A; - wci_lastControlOp = 4'hA; - wci_lastControlOp_1 = 4'hA; - wci_lastControlOp_10 = 4'hA; - wci_lastControlOp_11 = 4'hA; - wci_lastControlOp_12 = 4'hA; - wci_lastControlOp_13 = 4'hA; - wci_lastControlOp_14 = 4'hA; - wci_lastControlOp_2 = 4'hA; - wci_lastControlOp_3 = 4'hA; - wci_lastControlOp_4 = 4'hA; - wci_lastControlOp_5 = 4'hA; - wci_lastControlOp_6 = 4'hA; - wci_lastControlOp_7 = 4'hA; - wci_lastControlOp_8 = 4'hA; - wci_lastControlOp_9 = 4'hA; - wci_lastOpWrite = 2'h2; - wci_lastOpWrite_1 = 2'h2; - wci_lastOpWrite_10 = 2'h2; - wci_lastOpWrite_11 = 2'h2; - wci_lastOpWrite_12 = 2'h2; - wci_lastOpWrite_13 = 2'h2; - wci_lastOpWrite_14 = 2'h2; - wci_lastOpWrite_2 = 2'h2; - wci_lastOpWrite_3 = 2'h2; - wci_lastOpWrite_4 = 2'h2; - wci_lastOpWrite_5 = 2'h2; - wci_lastOpWrite_6 = 2'h2; - wci_lastOpWrite_7 = 2'h2; - wci_lastOpWrite_8 = 2'h2; - wci_lastOpWrite_9 = 2'h2; - wci_mFlagReg = 2'h2; - wci_mFlagReg_1 = 2'h2; - wci_mFlagReg_10 = 2'h2; - wci_mFlagReg_11 = 2'h2; - wci_mFlagReg_12 = 2'h2; - wci_mFlagReg_13 = 2'h2; - wci_mFlagReg_14 = 2'h2; - wci_mFlagReg_2 = 2'h2; - wci_mFlagReg_3 = 2'h2; - wci_mFlagReg_4 = 2'h2; - wci_mFlagReg_5 = 2'h2; - wci_mFlagReg_6 = 2'h2; - wci_mFlagReg_7 = 2'h2; - wci_mFlagReg_8 = 2'h2; - wci_mFlagReg_9 = 2'h2; - wci_pageWindow = 12'hAAA; - wci_pageWindow_1 = 12'hAAA; - wci_pageWindow_10 = 12'hAAA; - wci_pageWindow_11 = 12'hAAA; - wci_pageWindow_12 = 12'hAAA; - wci_pageWindow_13 = 12'hAAA; - wci_pageWindow_14 = 12'hAAA; - wci_pageWindow_2 = 12'hAAA; - wci_pageWindow_3 = 12'hAAA; - wci_pageWindow_4 = 12'hAAA; - wci_pageWindow_5 = 12'hAAA; - wci_pageWindow_6 = 12'hAAA; - wci_pageWindow_7 = 12'hAAA; - wci_pageWindow_8 = 12'hAAA; - wci_pageWindow_9 = 12'hAAA; - wci_reqERR = 3'h2; - wci_reqERR_1 = 3'h2; - wci_reqERR_10 = 3'h2; - wci_reqERR_11 = 3'h2; - wci_reqERR_12 = 3'h2; - wci_reqERR_13 = 3'h2; - wci_reqERR_14 = 3'h2; - wci_reqERR_2 = 3'h2; - wci_reqERR_3 = 3'h2; - wci_reqERR_4 = 3'h2; - wci_reqERR_5 = 3'h2; - wci_reqERR_6 = 3'h2; - wci_reqERR_7 = 3'h2; - wci_reqERR_8 = 3'h2; - wci_reqERR_9 = 3'h2; - wci_reqFAIL = 3'h2; - wci_reqFAIL_1 = 3'h2; - wci_reqFAIL_10 = 3'h2; - wci_reqFAIL_11 = 3'h2; - wci_reqFAIL_12 = 3'h2; - wci_reqFAIL_13 = 3'h2; - wci_reqFAIL_14 = 3'h2; - wci_reqFAIL_2 = 3'h2; - wci_reqFAIL_3 = 3'h2; - wci_reqFAIL_4 = 3'h2; - wci_reqFAIL_5 = 3'h2; - wci_reqFAIL_6 = 3'h2; - wci_reqFAIL_7 = 3'h2; - wci_reqFAIL_8 = 3'h2; - wci_reqFAIL_9 = 3'h2; - wci_reqF_10_c_r = 1'h0; - wci_reqF_10_q_0 = 72'hAAAAAAAAAAAAAAAAAA; - wci_reqF_11_c_r = 1'h0; - wci_reqF_11_q_0 = 72'hAAAAAAAAAAAAAAAAAA; - wci_reqF_12_c_r = 1'h0; - wci_reqF_12_q_0 = 72'hAAAAAAAAAAAAAAAAAA; - wci_reqF_13_c_r = 1'h0; - wci_reqF_13_q_0 = 72'hAAAAAAAAAAAAAAAAAA; - wci_reqF_14_c_r = 1'h0; - wci_reqF_14_q_0 = 72'hAAAAAAAAAAAAAAAAAA; - wci_reqF_1_c_r = 1'h0; - wci_reqF_1_q_0 = 72'hAAAAAAAAAAAAAAAAAA; - wci_reqF_2_c_r = 1'h0; - wci_reqF_2_q_0 = 72'hAAAAAAAAAAAAAAAAAA; - wci_reqF_3_c_r = 1'h0; - wci_reqF_3_q_0 = 72'hAAAAAAAAAAAAAAAAAA; - wci_reqF_4_c_r = 1'h0; - wci_reqF_4_q_0 = 72'hAAAAAAAAAAAAAAAAAA; - wci_reqF_5_c_r = 1'h0; - wci_reqF_5_q_0 = 72'hAAAAAAAAAAAAAAAAAA; - wci_reqF_6_c_r = 1'h0; - wci_reqF_6_q_0 = 72'hAAAAAAAAAAAAAAAAAA; - wci_reqF_7_c_r = 1'h0; - wci_reqF_7_q_0 = 72'hAAAAAAAAAAAAAAAAAA; - wci_reqF_8_c_r = 1'h0; - wci_reqF_8_q_0 = 72'hAAAAAAAAAAAAAAAAAA; - wci_reqF_9_c_r = 1'h0; - wci_reqF_9_q_0 = 72'hAAAAAAAAAAAAAAAAAA; - wci_reqF_c_r = 1'h0; - wci_reqF_q_0 = 72'hAAAAAAAAAAAAAAAAAA; - wci_reqPend = 2'h2; - wci_reqPend_1 = 2'h2; - wci_reqPend_10 = 2'h2; - wci_reqPend_11 = 2'h2; - wci_reqPend_12 = 2'h2; - wci_reqPend_13 = 2'h2; - wci_reqPend_14 = 2'h2; - wci_reqPend_2 = 2'h2; - wci_reqPend_3 = 2'h2; - wci_reqPend_4 = 2'h2; - wci_reqPend_5 = 2'h2; - wci_reqPend_6 = 2'h2; - wci_reqPend_7 = 2'h2; - wci_reqPend_8 = 2'h2; - wci_reqPend_9 = 2'h2; - wci_reqTO = 3'h2; - wci_reqTO_1 = 3'h2; - wci_reqTO_10 = 3'h2; - wci_reqTO_11 = 3'h2; - wci_reqTO_12 = 3'h2; - wci_reqTO_13 = 3'h2; - wci_reqTO_14 = 3'h2; - wci_reqTO_2 = 3'h2; - wci_reqTO_3 = 3'h2; - wci_reqTO_4 = 3'h2; - wci_reqTO_5 = 3'h2; - wci_reqTO_6 = 3'h2; - wci_reqTO_7 = 3'h2; - wci_reqTO_8 = 3'h2; - wci_reqTO_9 = 3'h2; - wci_respTimr = 32'hAAAAAAAA; - wci_respTimrAct = 1'h0; - wci_respTimrAct_1 = 1'h0; - wci_respTimrAct_10 = 1'h0; - wci_respTimrAct_11 = 1'h0; - wci_respTimrAct_12 = 1'h0; - wci_respTimrAct_13 = 1'h0; - wci_respTimrAct_14 = 1'h0; - wci_respTimrAct_2 = 1'h0; - wci_respTimrAct_3 = 1'h0; - wci_respTimrAct_4 = 1'h0; - wci_respTimrAct_5 = 1'h0; - wci_respTimrAct_6 = 1'h0; - wci_respTimrAct_7 = 1'h0; - wci_respTimrAct_8 = 1'h0; - wci_respTimrAct_9 = 1'h0; - wci_respTimr_1 = 32'hAAAAAAAA; - wci_respTimr_10 = 32'hAAAAAAAA; - wci_respTimr_11 = 32'hAAAAAAAA; - wci_respTimr_12 = 32'hAAAAAAAA; - wci_respTimr_13 = 32'hAAAAAAAA; - wci_respTimr_14 = 32'hAAAAAAAA; - wci_respTimr_2 = 32'hAAAAAAAA; - wci_respTimr_3 = 32'hAAAAAAAA; - wci_respTimr_4 = 32'hAAAAAAAA; - wci_respTimr_5 = 32'hAAAAAAAA; - wci_respTimr_6 = 32'hAAAAAAAA; - wci_respTimr_7 = 32'hAAAAAAAA; - wci_respTimr_8 = 32'hAAAAAAAA; - wci_respTimr_9 = 32'hAAAAAAAA; - wci_sThreadBusy_d = 1'h0; - wci_sThreadBusy_d_1 = 1'h0; - wci_sThreadBusy_d_10 = 1'h0; - wci_sThreadBusy_d_11 = 1'h0; - wci_sThreadBusy_d_12 = 1'h0; - wci_sThreadBusy_d_13 = 1'h0; - wci_sThreadBusy_d_14 = 1'h0; - wci_sThreadBusy_d_2 = 1'h0; - wci_sThreadBusy_d_3 = 1'h0; - wci_sThreadBusy_d_4 = 1'h0; - wci_sThreadBusy_d_5 = 1'h0; - wci_sThreadBusy_d_6 = 1'h0; - wci_sThreadBusy_d_7 = 1'h0; - wci_sThreadBusy_d_8 = 1'h0; - wci_sThreadBusy_d_9 = 1'h0; - wci_sfCap = 1'h0; - wci_sfCapClear = 1'h0; - wci_sfCapClear_10 = 1'h0; - wci_sfCapClear_11 = 1'h0; - wci_sfCapClear_12 = 1'h0; - wci_sfCapClear_13 = 1'h0; - wci_sfCapClear_14 = 1'h0; - wci_sfCapClear_1_1 = 1'h0; - wci_sfCapClear_2 = 1'h0; - wci_sfCapClear_3 = 1'h0; - wci_sfCapClear_4 = 1'h0; - wci_sfCapClear_5 = 1'h0; - wci_sfCapClear_6 = 1'h0; - wci_sfCapClear_7 = 1'h0; - wci_sfCapClear_8 = 1'h0; - wci_sfCapClear_9 = 1'h0; - wci_sfCapSet = 1'h0; - wci_sfCapSet_10 = 1'h0; - wci_sfCapSet_11 = 1'h0; - wci_sfCapSet_12 = 1'h0; - wci_sfCapSet_13 = 1'h0; - wci_sfCapSet_14 = 1'h0; - wci_sfCapSet_1_1 = 1'h0; - wci_sfCapSet_2 = 1'h0; - wci_sfCapSet_3 = 1'h0; - wci_sfCapSet_4 = 1'h0; - wci_sfCapSet_5 = 1'h0; - wci_sfCapSet_6 = 1'h0; - wci_sfCapSet_7 = 1'h0; - wci_sfCapSet_8 = 1'h0; - wci_sfCapSet_9 = 1'h0; - wci_sfCap_1 = 1'h0; - wci_sfCap_10 = 1'h0; - wci_sfCap_11 = 1'h0; - wci_sfCap_12 = 1'h0; - wci_sfCap_13 = 1'h0; - wci_sfCap_14 = 1'h0; - wci_sfCap_2 = 1'h0; - wci_sfCap_3 = 1'h0; - wci_sfCap_4 = 1'h0; - wci_sfCap_5 = 1'h0; - wci_sfCap_6 = 1'h0; - wci_sfCap_7 = 1'h0; - wci_sfCap_8 = 1'h0; - wci_sfCap_9 = 1'h0; - wci_slvPresent = 1'h0; - wci_slvPresent_1 = 1'h0; - wci_slvPresent_10 = 1'h0; - wci_slvPresent_11 = 1'h0; - wci_slvPresent_12 = 1'h0; - wci_slvPresent_13 = 1'h0; - wci_slvPresent_14 = 1'h0; - wci_slvPresent_2 = 1'h0; - wci_slvPresent_3 = 1'h0; - wci_slvPresent_4 = 1'h0; - wci_slvPresent_5 = 1'h0; - wci_slvPresent_6 = 1'h0; - wci_slvPresent_7 = 1'h0; - wci_slvPresent_8 = 1'h0; - wci_slvPresent_9 = 1'h0; - wci_wReset_n = 1'h0; - wci_wReset_n_1 = 1'h0; - wci_wReset_n_10 = 1'h0; - wci_wReset_n_11 = 1'h0; - wci_wReset_n_12 = 1'h0; - wci_wReset_n_13 = 1'h0; - wci_wReset_n_14 = 1'h0; - wci_wReset_n_2 = 1'h0; - wci_wReset_n_3 = 1'h0; - wci_wReset_n_4 = 1'h0; - wci_wReset_n_5 = 1'h0; - wci_wReset_n_6 = 1'h0; - wci_wReset_n_7 = 1'h0; - wci_wReset_n_8 = 1'h0; - wci_wReset_n_9 = 1'h0; - wci_wStatus = 32'hAAAAAAAA; - wci_wStatus_1 = 32'hAAAAAAAA; - wci_wStatus_10 = 32'hAAAAAAAA; - wci_wStatus_11 = 32'hAAAAAAAA; - wci_wStatus_12 = 32'hAAAAAAAA; - wci_wStatus_13 = 32'hAAAAAAAA; - wci_wStatus_14 = 32'hAAAAAAAA; - wci_wStatus_2 = 32'hAAAAAAAA; - wci_wStatus_3 = 32'hAAAAAAAA; - wci_wStatus_4 = 32'hAAAAAAAA; - wci_wStatus_5 = 32'hAAAAAAAA; - wci_wStatus_6 = 32'hAAAAAAAA; - wci_wStatus_7 = 32'hAAAAAAAA; - wci_wStatus_8 = 32'hAAAAAAAA; - wci_wStatus_9 = 32'hAAAAAAAA; - wci_wTimeout = 5'h0A; - wci_wTimeout_1 = 5'h0A; - wci_wTimeout_10 = 5'h0A; - wci_wTimeout_11 = 5'h0A; - wci_wTimeout_12 = 5'h0A; - wci_wTimeout_13 = 5'h0A; - wci_wTimeout_14 = 5'h0A; - wci_wTimeout_2 = 5'h0A; - wci_wTimeout_3 = 5'h0A; - wci_wTimeout_4 = 5'h0A; - wci_wTimeout_5 = 5'h0A; - wci_wTimeout_6 = 5'h0A; - wci_wTimeout_7 = 5'h0A; - wci_wTimeout_8 = 5'h0A; - wci_wTimeout_9 = 5'h0A; + wci_0_busy = 1'h0; + wci_0_lastConfigAddr = 33'h0AAAAAAAA; + wci_0_lastConfigBE = 5'h0A; + wci_0_lastControlOp = 4'hA; + wci_0_lastOpWrite = 2'h2; + wci_0_mFlagReg = 2'h2; + wci_0_pageWindow = 12'hAAA; + wci_0_reqERR = 3'h2; + wci_0_reqFAIL = 3'h2; + wci_0_reqF_cntr_r = 1'h0; + wci_0_reqF_q_0 = 72'hAAAAAAAAAAAAAAAAAA; + wci_0_reqPend = 2'h2; + wci_0_reqTO = 3'h2; + wci_0_respTimr = 32'hAAAAAAAA; + wci_0_respTimrAct = 1'h0; + wci_0_sThreadBusy_d = 1'h0; + wci_0_sfCap = 1'h0; + wci_0_sfCapClear = 1'h0; + wci_0_sfCapSet = 1'h0; + wci_0_slvPresent = 1'h0; + wci_0_wReset_n = 1'h0; + wci_0_wStatus = 32'hAAAAAAAA; + wci_0_wTimeout = 5'h0A; + wci_10_busy = 1'h0; + wci_10_lastConfigAddr = 33'h0AAAAAAAA; + wci_10_lastConfigBE = 5'h0A; + wci_10_lastControlOp = 4'hA; + wci_10_lastOpWrite = 2'h2; + wci_10_mFlagReg = 2'h2; + wci_10_pageWindow = 12'hAAA; + wci_10_reqERR = 3'h2; + wci_10_reqFAIL = 3'h2; + wci_10_reqF_cntr_r = 1'h0; + wci_10_reqF_q_0 = 72'hAAAAAAAAAAAAAAAAAA; + wci_10_reqPend = 2'h2; + wci_10_reqTO = 3'h2; + wci_10_respTimr = 32'hAAAAAAAA; + wci_10_respTimrAct = 1'h0; + wci_10_sThreadBusy_d = 1'h0; + wci_10_sfCap = 1'h0; + wci_10_sfCapClear = 1'h0; + wci_10_sfCapSet = 1'h0; + wci_10_slvPresent = 1'h0; + wci_10_wReset_n = 1'h0; + wci_10_wStatus = 32'hAAAAAAAA; + wci_10_wTimeout = 5'h0A; + wci_11_busy = 1'h0; + wci_11_lastConfigAddr = 33'h0AAAAAAAA; + wci_11_lastConfigBE = 5'h0A; + wci_11_lastControlOp = 4'hA; + wci_11_lastOpWrite = 2'h2; + wci_11_mFlagReg = 2'h2; + wci_11_pageWindow = 12'hAAA; + wci_11_reqERR = 3'h2; + wci_11_reqFAIL = 3'h2; + wci_11_reqF_cntr_r = 1'h0; + wci_11_reqF_q_0 = 72'hAAAAAAAAAAAAAAAAAA; + wci_11_reqPend = 2'h2; + wci_11_reqTO = 3'h2; + wci_11_respTimr = 32'hAAAAAAAA; + wci_11_respTimrAct = 1'h0; + wci_11_sThreadBusy_d = 1'h0; + wci_11_sfCap = 1'h0; + wci_11_sfCapClear = 1'h0; + wci_11_sfCapSet = 1'h0; + wci_11_slvPresent = 1'h0; + wci_11_wReset_n = 1'h0; + wci_11_wStatus = 32'hAAAAAAAA; + wci_11_wTimeout = 5'h0A; + wci_12_busy = 1'h0; + wci_12_lastConfigAddr = 33'h0AAAAAAAA; + wci_12_lastConfigBE = 5'h0A; + wci_12_lastControlOp = 4'hA; + wci_12_lastOpWrite = 2'h2; + wci_12_mFlagReg = 2'h2; + wci_12_pageWindow = 12'hAAA; + wci_12_reqERR = 3'h2; + wci_12_reqFAIL = 3'h2; + wci_12_reqF_cntr_r = 1'h0; + wci_12_reqF_q_0 = 72'hAAAAAAAAAAAAAAAAAA; + wci_12_reqPend = 2'h2; + wci_12_reqTO = 3'h2; + wci_12_respTimr = 32'hAAAAAAAA; + wci_12_respTimrAct = 1'h0; + wci_12_sThreadBusy_d = 1'h0; + wci_12_sfCap = 1'h0; + wci_12_sfCapClear = 1'h0; + wci_12_sfCapSet = 1'h0; + wci_12_slvPresent = 1'h0; + wci_12_wReset_n = 1'h0; + wci_12_wStatus = 32'hAAAAAAAA; + wci_12_wTimeout = 5'h0A; + wci_13_busy = 1'h0; + wci_13_lastConfigAddr = 33'h0AAAAAAAA; + wci_13_lastConfigBE = 5'h0A; + wci_13_lastControlOp = 4'hA; + wci_13_lastOpWrite = 2'h2; + wci_13_mFlagReg = 2'h2; + wci_13_pageWindow = 12'hAAA; + wci_13_reqERR = 3'h2; + wci_13_reqFAIL = 3'h2; + wci_13_reqF_cntr_r = 1'h0; + wci_13_reqF_q_0 = 72'hAAAAAAAAAAAAAAAAAA; + wci_13_reqPend = 2'h2; + wci_13_reqTO = 3'h2; + wci_13_respTimr = 32'hAAAAAAAA; + wci_13_respTimrAct = 1'h0; + wci_13_sThreadBusy_d = 1'h0; + wci_13_sfCap = 1'h0; + wci_13_sfCapClear = 1'h0; + wci_13_sfCapSet = 1'h0; + wci_13_slvPresent = 1'h0; + wci_13_wReset_n = 1'h0; + wci_13_wStatus = 32'hAAAAAAAA; + wci_13_wTimeout = 5'h0A; + wci_14_busy = 1'h0; + wci_14_lastConfigAddr = 33'h0AAAAAAAA; + wci_14_lastConfigBE = 5'h0A; + wci_14_lastControlOp = 4'hA; + wci_14_lastOpWrite = 2'h2; + wci_14_mFlagReg = 2'h2; + wci_14_pageWindow = 12'hAAA; + wci_14_reqERR = 3'h2; + wci_14_reqFAIL = 3'h2; + wci_14_reqF_cntr_r = 1'h0; + wci_14_reqF_q_0 = 72'hAAAAAAAAAAAAAAAAAA; + wci_14_reqPend = 2'h2; + wci_14_reqTO = 3'h2; + wci_14_respTimr = 32'hAAAAAAAA; + wci_14_respTimrAct = 1'h0; + wci_14_sThreadBusy_d = 1'h0; + wci_14_sfCap = 1'h0; + wci_14_sfCapClear = 1'h0; + wci_14_sfCapSet = 1'h0; + wci_14_slvPresent = 1'h0; + wci_14_wReset_n = 1'h0; + wci_14_wStatus = 32'hAAAAAAAA; + wci_14_wTimeout = 5'h0A; + wci_1_busy = 1'h0; + wci_1_lastConfigAddr = 33'h0AAAAAAAA; + wci_1_lastConfigBE = 5'h0A; + wci_1_lastControlOp = 4'hA; + wci_1_lastOpWrite = 2'h2; + wci_1_mFlagReg = 2'h2; + wci_1_pageWindow = 12'hAAA; + wci_1_reqERR = 3'h2; + wci_1_reqFAIL = 3'h2; + wci_1_reqF_cntr_r = 1'h0; + wci_1_reqF_q_0 = 72'hAAAAAAAAAAAAAAAAAA; + wci_1_reqPend = 2'h2; + wci_1_reqTO = 3'h2; + wci_1_respTimr = 32'hAAAAAAAA; + wci_1_respTimrAct = 1'h0; + wci_1_sThreadBusy_d = 1'h0; + wci_1_sfCap = 1'h0; + wci_1_sfCapClear = 1'h0; + wci_1_sfCapSet = 1'h0; + wci_1_slvPresent = 1'h0; + wci_1_wReset_n = 1'h0; + wci_1_wStatus = 32'hAAAAAAAA; + wci_1_wTimeout = 5'h0A; + wci_2_busy = 1'h0; + wci_2_lastConfigAddr = 33'h0AAAAAAAA; + wci_2_lastConfigBE = 5'h0A; + wci_2_lastControlOp = 4'hA; + wci_2_lastOpWrite = 2'h2; + wci_2_mFlagReg = 2'h2; + wci_2_pageWindow = 12'hAAA; + wci_2_reqERR = 3'h2; + wci_2_reqFAIL = 3'h2; + wci_2_reqF_cntr_r = 1'h0; + wci_2_reqF_q_0 = 72'hAAAAAAAAAAAAAAAAAA; + wci_2_reqPend = 2'h2; + wci_2_reqTO = 3'h2; + wci_2_respTimr = 32'hAAAAAAAA; + wci_2_respTimrAct = 1'h0; + wci_2_sThreadBusy_d = 1'h0; + wci_2_sfCap = 1'h0; + wci_2_sfCapClear = 1'h0; + wci_2_sfCapSet = 1'h0; + wci_2_slvPresent = 1'h0; + wci_2_wReset_n = 1'h0; + wci_2_wStatus = 32'hAAAAAAAA; + wci_2_wTimeout = 5'h0A; + wci_3_busy = 1'h0; + wci_3_lastConfigAddr = 33'h0AAAAAAAA; + wci_3_lastConfigBE = 5'h0A; + wci_3_lastControlOp = 4'hA; + wci_3_lastOpWrite = 2'h2; + wci_3_mFlagReg = 2'h2; + wci_3_pageWindow = 12'hAAA; + wci_3_reqERR = 3'h2; + wci_3_reqFAIL = 3'h2; + wci_3_reqF_cntr_r = 1'h0; + wci_3_reqF_q_0 = 72'hAAAAAAAAAAAAAAAAAA; + wci_3_reqPend = 2'h2; + wci_3_reqTO = 3'h2; + wci_3_respTimr = 32'hAAAAAAAA; + wci_3_respTimrAct = 1'h0; + wci_3_sThreadBusy_d = 1'h0; + wci_3_sfCap = 1'h0; + wci_3_sfCapClear = 1'h0; + wci_3_sfCapSet = 1'h0; + wci_3_slvPresent = 1'h0; + wci_3_wReset_n = 1'h0; + wci_3_wStatus = 32'hAAAAAAAA; + wci_3_wTimeout = 5'h0A; + wci_4_busy = 1'h0; + wci_4_lastConfigAddr = 33'h0AAAAAAAA; + wci_4_lastConfigBE = 5'h0A; + wci_4_lastControlOp = 4'hA; + wci_4_lastOpWrite = 2'h2; + wci_4_mFlagReg = 2'h2; + wci_4_pageWindow = 12'hAAA; + wci_4_reqERR = 3'h2; + wci_4_reqFAIL = 3'h2; + wci_4_reqF_cntr_r = 1'h0; + wci_4_reqF_q_0 = 72'hAAAAAAAAAAAAAAAAAA; + wci_4_reqPend = 2'h2; + wci_4_reqTO = 3'h2; + wci_4_respTimr = 32'hAAAAAAAA; + wci_4_respTimrAct = 1'h0; + wci_4_sThreadBusy_d = 1'h0; + wci_4_sfCap = 1'h0; + wci_4_sfCapClear = 1'h0; + wci_4_sfCapSet = 1'h0; + wci_4_slvPresent = 1'h0; + wci_4_wReset_n = 1'h0; + wci_4_wStatus = 32'hAAAAAAAA; + wci_4_wTimeout = 5'h0A; + wci_5_busy = 1'h0; + wci_5_lastConfigAddr = 33'h0AAAAAAAA; + wci_5_lastConfigBE = 5'h0A; + wci_5_lastControlOp = 4'hA; + wci_5_lastOpWrite = 2'h2; + wci_5_mFlagReg = 2'h2; + wci_5_pageWindow = 12'hAAA; + wci_5_reqERR = 3'h2; + wci_5_reqFAIL = 3'h2; + wci_5_reqF_cntr_r = 1'h0; + wci_5_reqF_q_0 = 72'hAAAAAAAAAAAAAAAAAA; + wci_5_reqPend = 2'h2; + wci_5_reqTO = 3'h2; + wci_5_respTimr = 32'hAAAAAAAA; + wci_5_respTimrAct = 1'h0; + wci_5_sThreadBusy_d = 1'h0; + wci_5_sfCap = 1'h0; + wci_5_sfCapClear = 1'h0; + wci_5_sfCapSet = 1'h0; + wci_5_slvPresent = 1'h0; + wci_5_wReset_n = 1'h0; + wci_5_wStatus = 32'hAAAAAAAA; + wci_5_wTimeout = 5'h0A; + wci_6_busy = 1'h0; + wci_6_lastConfigAddr = 33'h0AAAAAAAA; + wci_6_lastConfigBE = 5'h0A; + wci_6_lastControlOp = 4'hA; + wci_6_lastOpWrite = 2'h2; + wci_6_mFlagReg = 2'h2; + wci_6_pageWindow = 12'hAAA; + wci_6_reqERR = 3'h2; + wci_6_reqFAIL = 3'h2; + wci_6_reqF_cntr_r = 1'h0; + wci_6_reqF_q_0 = 72'hAAAAAAAAAAAAAAAAAA; + wci_6_reqPend = 2'h2; + wci_6_reqTO = 3'h2; + wci_6_respTimr = 32'hAAAAAAAA; + wci_6_respTimrAct = 1'h0; + wci_6_sThreadBusy_d = 1'h0; + wci_6_sfCap = 1'h0; + wci_6_sfCapClear = 1'h0; + wci_6_sfCapSet = 1'h0; + wci_6_slvPresent = 1'h0; + wci_6_wReset_n = 1'h0; + wci_6_wStatus = 32'hAAAAAAAA; + wci_6_wTimeout = 5'h0A; + wci_7_busy = 1'h0; + wci_7_lastConfigAddr = 33'h0AAAAAAAA; + wci_7_lastConfigBE = 5'h0A; + wci_7_lastControlOp = 4'hA; + wci_7_lastOpWrite = 2'h2; + wci_7_mFlagReg = 2'h2; + wci_7_pageWindow = 12'hAAA; + wci_7_reqERR = 3'h2; + wci_7_reqFAIL = 3'h2; + wci_7_reqF_cntr_r = 1'h0; + wci_7_reqF_q_0 = 72'hAAAAAAAAAAAAAAAAAA; + wci_7_reqPend = 2'h2; + wci_7_reqTO = 3'h2; + wci_7_respTimr = 32'hAAAAAAAA; + wci_7_respTimrAct = 1'h0; + wci_7_sThreadBusy_d = 1'h0; + wci_7_sfCap = 1'h0; + wci_7_sfCapClear = 1'h0; + wci_7_sfCapSet = 1'h0; + wci_7_slvPresent = 1'h0; + wci_7_wReset_n = 1'h0; + wci_7_wStatus = 32'hAAAAAAAA; + wci_7_wTimeout = 5'h0A; + wci_8_busy = 1'h0; + wci_8_lastConfigAddr = 33'h0AAAAAAAA; + wci_8_lastConfigBE = 5'h0A; + wci_8_lastControlOp = 4'hA; + wci_8_lastOpWrite = 2'h2; + wci_8_mFlagReg = 2'h2; + wci_8_pageWindow = 12'hAAA; + wci_8_reqERR = 3'h2; + wci_8_reqFAIL = 3'h2; + wci_8_reqF_cntr_r = 1'h0; + wci_8_reqF_q_0 = 72'hAAAAAAAAAAAAAAAAAA; + wci_8_reqPend = 2'h2; + wci_8_reqTO = 3'h2; + wci_8_respTimr = 32'hAAAAAAAA; + wci_8_respTimrAct = 1'h0; + wci_8_sThreadBusy_d = 1'h0; + wci_8_sfCap = 1'h0; + wci_8_sfCapClear = 1'h0; + wci_8_sfCapSet = 1'h0; + wci_8_slvPresent = 1'h0; + wci_8_wReset_n = 1'h0; + wci_8_wStatus = 32'hAAAAAAAA; + wci_8_wTimeout = 5'h0A; + wci_9_busy = 1'h0; + wci_9_lastConfigAddr = 33'h0AAAAAAAA; + wci_9_lastConfigBE = 5'h0A; + wci_9_lastControlOp = 4'hA; + wci_9_lastOpWrite = 2'h2; + wci_9_mFlagReg = 2'h2; + wci_9_pageWindow = 12'hAAA; + wci_9_reqERR = 3'h2; + wci_9_reqFAIL = 3'h2; + wci_9_reqF_cntr_r = 1'h0; + wci_9_reqF_q_0 = 72'hAAAAAAAAAAAAAAAAAA; + wci_9_reqPend = 2'h2; + wci_9_reqTO = 3'h2; + wci_9_respTimr = 32'hAAAAAAAA; + wci_9_respTimrAct = 1'h0; + wci_9_sThreadBusy_d = 1'h0; + wci_9_sfCap = 1'h0; + wci_9_sfCapClear = 1'h0; + wci_9_sfCapSet = 1'h0; + wci_9_slvPresent = 1'h0; + wci_9_wReset_n = 1'h0; + wci_9_wStatus = 32'hAAAAAAAA; + wci_9_wTimeout = 5'h0A; wrkAct = 4'hA; end `endif // BSV_NO_INITIAL_BLOCKS @@ -19390,2836 +26116,2836 @@ module mkOCCP(pciDevice, begin #0; if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_T_T_F) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E0_T_F) begin - v__h105179 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_T_T_F) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E0_T_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h105179, - _theResult_____1__h75857, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_T_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E0_F_T) begin - v__h78563 = $time; + v__h78104 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_T_F_T) - $display("[%0d]: %m: WORKER CONTROL ARM...", v__h78563); + if (WILL_FIRE_RL_cpDispatch_F_F_T_E0_F_T) + $display("[%0d]: %m: WORKER CONTROL ARM...", v__h78104); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_T_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E0_F_T) begin - v__h105179 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_T_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E0_F_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h105179, - _theResult_____1__h75857, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_T_F_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E0_F_F_F_T) begin - v__h79155 = $time; + v__h78692 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_T_F_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E0_F_F_F_T) $display("[%0d]: %m: pageWindow register written with %0x ", - v__h79155, + v__h78692, cpReq[59:28]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_T_F_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E0_F_F_F_T) begin - v__h105179 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_T_F_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E0_F_F_F_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h105179, - _theResult_____1__h75857, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_T_F_F_F_F) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E0_F_F_F_F) begin - v__h105179 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_T_F_F_F_F) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E0_F_F_F_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h105179, - _theResult_____1__h75857, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_T_T_F) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E1_T_F) begin - v__h105179 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_T_T_F) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E1_T_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h105179, - _theResult_____1__h75857, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_T_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E1_F_T) begin - v__h79264 = $time; + v__h78800 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_T_F_T) - $display("[%0d]: %m: WORKER CONTROL ARM...", v__h79264); + if (WILL_FIRE_RL_cpDispatch_F_F_T_E1_F_T) + $display("[%0d]: %m: WORKER CONTROL ARM...", v__h78800); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_T_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E1_F_T) begin - v__h105179 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_T_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E1_F_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h105179, - _theResult_____1__h75857, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_T_F_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E1_F_F_F_T) begin - v__h79843 = $time; + v__h79379 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_T_F_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E1_F_F_F_T) $display("[%0d]: %m: pageWindow register written with %0x ", - v__h79843, + v__h79379, cpReq[59:28]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_T_F_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E1_F_F_F_T) begin - v__h105179 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_T_F_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E1_F_F_F_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h105179, - _theResult_____1__h75857, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_T_F_F_F_F) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E1_F_F_F_F) begin - v__h105179 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_T_F_F_F_F) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E1_F_F_F_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h105179, - _theResult_____1__h75857, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_T_F) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E2_T_F) begin - v__h105179 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_T_F) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E2_T_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h105179, - _theResult_____1__h75857, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E2_F_T) begin - v__h79952 = $time; + v__h79487 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_F_T) - $display("[%0d]: %m: WORKER CONTROL ARM...", v__h79952); + if (WILL_FIRE_RL_cpDispatch_F_F_T_E2_F_T) + $display("[%0d]: %m: WORKER CONTROL ARM...", v__h79487); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E2_F_T) begin - v__h105179 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E2_F_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h105179, - _theResult_____1__h75857, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_F_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E2_F_F_F_T) begin - v__h80531 = $time; + v__h80066 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_F_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E2_F_F_F_T) $display("[%0d]: %m: pageWindow register written with %0x ", - v__h80531, + v__h80066, cpReq[59:28]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_F_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E2_F_F_F_T) begin - v__h105179 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_F_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E2_F_F_F_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h105179, - _theResult_____1__h75857, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_F_F_F_F) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E2_F_F_F_F) begin - v__h105179 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_F_F_F_F) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E2_F_F_F_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h105179, - _theResult_____1__h75857, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_T_F) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E3_T_F) begin - v__h105179 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_T_F) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E3_T_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h105179, - _theResult_____1__h75857, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E3_F_T) begin - v__h80640 = $time; + v__h80174 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_F_T) - $display("[%0d]: %m: WORKER CONTROL ARM...", v__h80640); + if (WILL_FIRE_RL_cpDispatch_F_F_T_E3_F_T) + $display("[%0d]: %m: WORKER CONTROL ARM...", v__h80174); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E3_F_T) begin - v__h105179 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E3_F_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h105179, - _theResult_____1__h75857, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_F_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E3_F_F_F_T) begin - v__h81219 = $time; + v__h80753 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_F_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E3_F_F_F_T) $display("[%0d]: %m: pageWindow register written with %0x ", - v__h81219, + v__h80753, cpReq[59:28]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_F_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E3_F_F_F_T) begin - v__h105179 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_F_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E3_F_F_F_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h105179, - _theResult_____1__h75857, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_F_F_F_F) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E3_F_F_F_F) begin - v__h105179 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_F_F_F_F) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E3_F_F_F_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h105179, - _theResult_____1__h75857, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_T_F) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E4_T_F) begin - v__h105179 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_T_F) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E4_T_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h105179, - _theResult_____1__h75857, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E4_F_T) begin - v__h81328 = $time; + v__h80861 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_F_T) - $display("[%0d]: %m: WORKER CONTROL ARM...", v__h81328); + if (WILL_FIRE_RL_cpDispatch_F_F_T_E4_F_T) + $display("[%0d]: %m: WORKER CONTROL ARM...", v__h80861); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E4_F_T) begin - v__h105179 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E4_F_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h105179, - _theResult_____1__h75857, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_F_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E4_F_F_F_T) begin - v__h81907 = $time; + v__h81440 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_F_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E4_F_F_F_T) $display("[%0d]: %m: pageWindow register written with %0x ", - v__h81907, + v__h81440, cpReq[59:28]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_F_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E4_F_F_F_T) begin - v__h105179 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_F_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E4_F_F_F_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h105179, - _theResult_____1__h75857, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_F_F_F_F) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E4_F_F_F_F) begin - v__h105179 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_F_F_F_F) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E4_F_F_F_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h105179, - _theResult_____1__h75857, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_T_F) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E5_T_F) begin - v__h105179 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_T_F) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E5_T_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h105179, - _theResult_____1__h75857, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E5_F_T) begin - v__h82016 = $time; + v__h81548 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_T) - $display("[%0d]: %m: WORKER CONTROL ARM...", v__h82016); + if (WILL_FIRE_RL_cpDispatch_F_F_T_E5_F_T) + $display("[%0d]: %m: WORKER CONTROL ARM...", v__h81548); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E5_F_T) begin - v__h105179 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E5_F_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h105179, - _theResult_____1__h75857, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E5_F_F_F_T) begin - v__h82595 = $time; + v__h82127 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E5_F_F_F_T) $display("[%0d]: %m: pageWindow register written with %0x ", - v__h82595, + v__h82127, cpReq[59:28]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E5_F_F_F_T) begin - v__h105179 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E5_F_F_F_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h105179, - _theResult_____1__h75857, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_F_F_F) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E5_F_F_F_F) begin - v__h105179 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_F_F_F) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E5_F_F_F_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h105179, - _theResult_____1__h75857, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_T_F) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E6_T_F) begin - v__h105179 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_T_F) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E6_T_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h105179, - _theResult_____1__h75857, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E6_F_T) begin - v__h82704 = $time; + v__h82235 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_F_T) - $display("[%0d]: %m: WORKER CONTROL ARM...", v__h82704); + if (WILL_FIRE_RL_cpDispatch_F_F_T_E6_F_T) + $display("[%0d]: %m: WORKER CONTROL ARM...", v__h82235); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E6_F_T) begin - v__h105179 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E6_F_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h105179, - _theResult_____1__h75857, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_F_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E6_F_F_F_T) begin - v__h83283 = $time; + v__h82814 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_F_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E6_F_F_F_T) $display("[%0d]: %m: pageWindow register written with %0x ", - v__h83283, + v__h82814, cpReq[59:28]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_F_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E6_F_F_F_T) begin - v__h105179 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_F_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E6_F_F_F_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h105179, - _theResult_____1__h75857, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_F_F_F_F) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E6_F_F_F_F) begin - v__h105179 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_F_F_F_F) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E6_F_F_F_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h105179, - _theResult_____1__h75857, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_T_F) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E7_T_F) begin - v__h105179 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_T_F) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E7_T_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h105179, - _theResult_____1__h75857, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E7_F_T) begin - v__h83392 = $time; + v__h82922 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_F_T) - $display("[%0d]: %m: WORKER CONTROL ARM...", v__h83392); + if (WILL_FIRE_RL_cpDispatch_F_F_T_E7_F_T) + $display("[%0d]: %m: WORKER CONTROL ARM...", v__h82922); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E7_F_T) begin - v__h105179 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E7_F_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h105179, - _theResult_____1__h75857, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_F_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E7_F_F_F_T) begin - v__h83971 = $time; + v__h83501 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_F_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E7_F_F_F_T) $display("[%0d]: %m: pageWindow register written with %0x ", - v__h83971, + v__h83501, cpReq[59:28]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_F_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E7_F_F_F_T) begin - v__h105179 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_F_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E7_F_F_F_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h105179, - _theResult_____1__h75857, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_F_F_F_F) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E7_F_F_F_F) begin - v__h105179 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_F_F_F_F) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E7_F_F_F_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h105179, - _theResult_____1__h75857, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_T_F) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E8_T_F) begin - v__h105179 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_T_F) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E8_T_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h105179, - _theResult_____1__h75857, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E8_F_T) begin - v__h84080 = $time; + v__h83609 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_F_T) - $display("[%0d]: %m: WORKER CONTROL ARM...", v__h84080); + if (WILL_FIRE_RL_cpDispatch_F_F_T_E8_F_T) + $display("[%0d]: %m: WORKER CONTROL ARM...", v__h83609); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E8_F_T) begin - v__h105179 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E8_F_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h105179, - _theResult_____1__h75857, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_F_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E8_F_F_F_T) begin - v__h84659 = $time; + v__h84188 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_F_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E8_F_F_F_T) $display("[%0d]: %m: pageWindow register written with %0x ", - v__h84659, + v__h84188, cpReq[59:28]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_F_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E8_F_F_F_T) begin - v__h105179 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_F_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E8_F_F_F_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h105179, - _theResult_____1__h75857, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_F_F_F_F) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E8_F_F_F_F) begin - v__h105179 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_F_F_F_F) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E8_F_F_F_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h105179, - _theResult_____1__h75857, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_T_F) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E9_T_F) begin - v__h105179 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_T_F) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E9_T_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h105179, - _theResult_____1__h75857, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E9_F_T) begin - v__h84768 = $time; + v__h84296 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_F_T) - $display("[%0d]: %m: WORKER CONTROL ARM...", v__h84768); + if (WILL_FIRE_RL_cpDispatch_F_F_T_E9_F_T) + $display("[%0d]: %m: WORKER CONTROL ARM...", v__h84296); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E9_F_T) begin - v__h105179 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E9_F_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h105179, - _theResult_____1__h75857, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_F_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E9_F_F_F_T) begin - v__h85347 = $time; + v__h84875 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_F_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E9_F_F_F_T) $display("[%0d]: %m: pageWindow register written with %0x ", - v__h85347, + v__h84875, cpReq[59:28]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_F_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E9_F_F_F_T) begin - v__h105179 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_F_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E9_F_F_F_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h105179, - _theResult_____1__h75857, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_F_F_F_F) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E9_F_F_F_F) begin - v__h105179 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_F_F_F_F) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E9_F_F_F_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h105179, - _theResult_____1__h75857, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_T_F) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E10_T_F) begin - v__h105179 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_T_F) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E10_T_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h105179, - _theResult_____1__h75857, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E10_F_T) begin - v__h85456 = $time; + v__h84983 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_T) - $display("[%0d]: %m: WORKER CONTROL ARM...", v__h85456); + if (WILL_FIRE_RL_cpDispatch_F_F_T_E10_F_T) + $display("[%0d]: %m: WORKER CONTROL ARM...", v__h84983); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E10_F_T) begin - v__h105179 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E10_F_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h105179, - _theResult_____1__h75857, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E10_F_F_F_T) begin - v__h86035 = $time; + v__h85562 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E10_F_F_F_T) $display("[%0d]: %m: pageWindow register written with %0x ", - v__h86035, + v__h85562, cpReq[59:28]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E10_F_F_F_T) begin - v__h105179 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E10_F_F_F_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h105179, - _theResult_____1__h75857, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E10_F_F_F_F) begin - v__h105179 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E10_F_F_F_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h105179, - _theResult_____1__h75857, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_T_F) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E11_T_F) begin - v__h105179 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_T_F) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E11_T_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h105179, - _theResult_____1__h75857, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E11_F_T) begin - v__h86144 = $time; + v__h85670 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_F_T) - $display("[%0d]: %m: WORKER CONTROL ARM...", v__h86144); + if (WILL_FIRE_RL_cpDispatch_F_F_T_E11_F_T) + $display("[%0d]: %m: WORKER CONTROL ARM...", v__h85670); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E11_F_T) begin - v__h105179 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E11_F_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h105179, - _theResult_____1__h75857, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E11_F_F_F_T) begin - v__h86723 = $time; + v__h86249 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E11_F_F_F_T) $display("[%0d]: %m: pageWindow register written with %0x ", - v__h86723, + v__h86249, cpReq[59:28]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E11_F_F_F_T) begin - v__h105179 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E11_F_F_F_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h105179, - _theResult_____1__h75857, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E11_F_F_F_F) begin - v__h105179 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E11_F_F_F_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h105179, - _theResult_____1__h75857, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E12_T_F) begin - v__h105179 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E12_T_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h105179, - _theResult_____1__h75857, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E12_F_T) begin - v__h86832 = $time; + v__h86357 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T) - $display("[%0d]: %m: WORKER CONTROL ARM...", v__h86832); + if (WILL_FIRE_RL_cpDispatch_F_F_T_E12_F_T) + $display("[%0d]: %m: WORKER CONTROL ARM...", v__h86357); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E12_F_T) begin - v__h105179 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E12_F_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h105179, - _theResult_____1__h75857, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E12_F_F_F_T) begin - v__h87411 = $time; + v__h86936 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E12_F_F_F_T) $display("[%0d]: %m: pageWindow register written with %0x ", - v__h87411, + v__h86936, cpReq[59:28]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E12_F_F_F_T) begin - v__h105179 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E12_F_F_F_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h105179, - _theResult_____1__h75857, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E12_F_F_F_F) begin - v__h105179 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E12_F_F_F_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h105179, - _theResult_____1__h75857, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E13_T_F) begin - v__h105179 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E13_T_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h105179, - _theResult_____1__h75857, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E13_F_T) begin - v__h87520 = $time; + v__h87044 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T) - $display("[%0d]: %m: WORKER CONTROL ARM...", v__h87520); + if (WILL_FIRE_RL_cpDispatch_F_F_T_E13_F_T) + $display("[%0d]: %m: WORKER CONTROL ARM...", v__h87044); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E13_F_T) begin - v__h105179 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E13_F_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h105179, - _theResult_____1__h75857, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E13_F_F_F_T) begin - v__h88099 = $time; + v__h87623 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E13_F_F_F_T) $display("[%0d]: %m: pageWindow register written with %0x ", - v__h88099, + v__h87623, cpReq[59:28]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E13_F_F_F_T) begin - v__h105179 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E13_F_F_F_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h105179, - _theResult_____1__h75857, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E13_F_F_F_F) begin - v__h105179 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E13_F_F_F_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h105179, - _theResult_____1__h75857, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E14_T_F) begin - v__h105179 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E14_T_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h105179, - _theResult_____1__h75857, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E14_F_T) begin - v__h88208 = $time; + v__h87731 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T) - $display("[%0d]: %m: WORKER CONTROL ARM...", v__h88208); + if (WILL_FIRE_RL_cpDispatch_F_F_T_E14_F_T) + $display("[%0d]: %m: WORKER CONTROL ARM...", v__h87731); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E14_F_T) begin - v__h105179 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E14_F_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h105179, - _theResult_____1__h75857, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E14_F_F_F_T) begin - v__h88787 = $time; + v__h88310 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E14_F_F_F_T) $display("[%0d]: %m: pageWindow register written with %0x ", - v__h88787, + v__h88310, cpReq[59:28]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E14_F_F_F_T) begin - v__h105179 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E14_F_F_F_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h105179, - _theResult_____1__h75857, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E14_F_F_F_F) begin - v__h105179 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E14_F_F_F_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h105179, - _theResult_____1__h75857, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F) + if (WILL_FIRE_RL_cpDispatch_F_F_T_OOB) begin - v__h105179 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F) + if (WILL_FIRE_RL_cpDispatch_F_F_T_OOB) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h105179, - _theResult_____1__h75857, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_T_T_F) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_T_F) begin - v__h105232 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_T_T_F) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_T_F) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h105232, - _theResult_____1__h75875, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_T_F_T_F) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_T_F) begin - v__h96191 = $time; + v__h95208 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_T_F_T_F) - $display("[%0d]: %m: WORKER CONTROL ARM...", v__h96191); + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_T_F) + $display("[%0d]: %m: WORKER CONTROL ARM...", v__h95208); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_T_F_T_F) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_T_F) begin - v__h105232 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_T_F_T_F) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_T_F) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h105232, - _theResult_____1__h75875, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_T_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_F_T) begin - v__h105232 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_T_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h105232, - _theResult_____1__h75875, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_T_F_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_F_F_T) begin - v__h105232 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_T_F_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h105232, - _theResult_____1__h75875, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_T_F_F_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_F_F_F_T) begin - v__h105232 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_T_F_F_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_F_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h105232, - _theResult_____1__h75875, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_T_F_F_F_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_F_F_F_F_T) begin - v__h105232 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_T_F_F_F_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_F_F_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h105232, - _theResult_____1__h75875, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_T_F_F_F_F_F_F) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_F_F_F_F_F) begin - v__h105232 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_T_F_F_F_F_F_F) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_F_F_F_F_F) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h105232, - _theResult_____1__h75875, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_T_F) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_T_F) begin - v__h105232 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_T_F) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_T_F) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h105232, - _theResult_____1__h75875, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_F_T_F) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_T_F) begin - v__h96263 = $time; + v__h95279 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_F_T_F) - $display("[%0d]: %m: WORKER CONTROL ARM...", v__h96263); + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_T_F) + $display("[%0d]: %m: WORKER CONTROL ARM...", v__h95279); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_F_T_F) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_T_F) begin - v__h105232 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_F_T_F) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_T_F) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h105232, - _theResult_____1__h75875, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_F_T) begin - v__h105232 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h105232, - _theResult_____1__h75875, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_F_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_F_F_T) begin - v__h105232 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_F_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h105232, - _theResult_____1__h75875, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_F_F_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_F_F_F_T) begin - v__h105232 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_F_F_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_F_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h105232, - _theResult_____1__h75875, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_F_F_F_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_F_F_F_F_T) begin - v__h105232 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_F_F_F_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_F_F_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h105232, - _theResult_____1__h75875, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_F_F_F_F_F_F) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_F_F_F_F_F) begin - v__h105232 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_F_F_F_F_F_F) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_F_F_F_F_F) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h105232, - _theResult_____1__h75875, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_T_F) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_T_F) begin - v__h105232 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_T_F) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_T_F) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h105232, - _theResult_____1__h75875, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_F_T_F) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_F_T_F) begin - v__h96335 = $time; + v__h95350 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_F_T_F) - $display("[%0d]: %m: WORKER CONTROL ARM...", v__h96335); + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_F_T_F) + $display("[%0d]: %m: WORKER CONTROL ARM...", v__h95350); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_F_T_F) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_F_T_F) begin - v__h105232 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_F_T_F) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_F_T_F) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h105232, - _theResult_____1__h75875, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_F_F_T) begin - v__h105232 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h105232, - _theResult_____1__h75875, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_F_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_F_F_F_T) begin - v__h105232 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_F_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_F_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h105232, - _theResult_____1__h75875, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_F_F_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_F_F_F_F_T) begin - v__h105232 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_F_F_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_F_F_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h105232, - _theResult_____1__h75875, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_F_F_F_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_F_F_F_F_F_T) begin - v__h105232 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_F_F_F_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_F_F_F_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h105232, - _theResult_____1__h75875, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_F_F_F_F_F_F) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_F_F_F_F_F_F) begin - v__h105232 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_F_F_F_F_F_F) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_F_F_F_F_F_F) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h105232, - _theResult_____1__h75875, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_T_F) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_T_F) begin - v__h105232 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_T_F) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_T_F) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h105232, - _theResult_____1__h75875, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_F_T_F) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_F_T_F) begin - v__h96407 = $time; + v__h95421 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_F_T_F) - $display("[%0d]: %m: WORKER CONTROL ARM...", v__h96407); + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_F_T_F) + $display("[%0d]: %m: WORKER CONTROL ARM...", v__h95421); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_F_T_F) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_F_T_F) begin - v__h105232 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_F_T_F) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_F_T_F) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h105232, - _theResult_____1__h75875, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_F_F_T) begin - v__h105232 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h105232, - _theResult_____1__h75875, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_F_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_F_F_F_T) begin - v__h105232 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_F_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_F_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h105232, - _theResult_____1__h75875, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_F_F_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_F_F_F_F_T) begin - v__h105232 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_F_F_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_F_F_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h105232, - _theResult_____1__h75875, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_F_F_F_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_F_F_F_F_F_T) begin - v__h105232 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_F_F_F_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_F_F_F_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h105232, - _theResult_____1__h75875, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_F_F_F_F_F_F) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_F_F_F_F_F_F) begin - v__h105232 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_F_F_F_F_F_F) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_F_F_F_F_F_F) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h105232, - _theResult_____1__h75875, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_T_F) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_T_F) begin - v__h105232 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_T_F) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_T_F) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h105232, - _theResult_____1__h75875, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_T_F) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_F_T_F) begin - v__h96479 = $time; + v__h95492 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_T_F) - $display("[%0d]: %m: WORKER CONTROL ARM...", v__h96479); + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_F_T_F) + $display("[%0d]: %m: WORKER CONTROL ARM...", v__h95492); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_T_F) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_F_T_F) begin - v__h105232 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_T_F) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_F_T_F) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h105232, - _theResult_____1__h75875, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_F_F_T) begin - v__h105232 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h105232, - _theResult_____1__h75875, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_F_F_F_T) begin - v__h105232 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_F_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h105232, - _theResult_____1__h75875, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_F_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_F_F_F_F_T) begin - v__h105232 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_F_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_F_F_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h105232, - _theResult_____1__h75875, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_F_F_F_F_F_T) begin - v__h105232 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_F_F_F_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h105232, - _theResult_____1__h75875, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_F_F_F_F_F_F) begin - v__h105232 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_F_F_F_F_F_F) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h105232, - _theResult_____1__h75875, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_T_F) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_T_F) begin - v__h105232 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_T_F) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_T_F) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h105232, - _theResult_____1__h75875, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_T_F) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_T_F) begin - v__h96551 = $time; + v__h95563 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_T_F) - $display("[%0d]: %m: WORKER CONTROL ARM...", v__h96551); + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_T_F) + $display("[%0d]: %m: WORKER CONTROL ARM...", v__h95563); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_T_F) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_T_F) begin - v__h105232 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_T_F) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_T_F) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h105232, - _theResult_____1__h75875, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_F_T) begin - v__h105232 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h105232, - _theResult_____1__h75875, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_F_F_T) begin - v__h105232 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h105232, - _theResult_____1__h75875, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_F_F_F_T) begin - v__h105232 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_F_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h105232, - _theResult_____1__h75875, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_F_F_F_F_T) begin - v__h105232 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_F_F_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h105232, - _theResult_____1__h75875, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_F_F_F_F_F) begin - v__h105232 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_F_F_F_F_F) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h105232, - _theResult_____1__h75875, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_T_F) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_T_F) begin - v__h105232 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_T_F) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_T_F) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h105232, - _theResult_____1__h75875, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_F_T_F) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_F_T_F) begin - v__h96623 = $time; + v__h95634 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_F_T_F) - $display("[%0d]: %m: WORKER CONTROL ARM...", v__h96623); + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_F_T_F) + $display("[%0d]: %m: WORKER CONTROL ARM...", v__h95634); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_F_T_F) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_F_T_F) begin - v__h105232 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_F_T_F) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_F_T_F) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h105232, - _theResult_____1__h75875, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_F_F_T) begin - v__h105232 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h105232, - _theResult_____1__h75875, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_F_F_F_T) begin - v__h105232 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_F_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h105232, - _theResult_____1__h75875, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_F_F_F_F_T) begin - v__h105232 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_F_F_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h105232, - _theResult_____1__h75875, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_F_F_F_F_F_T) begin - v__h105232 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_F_F_F_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h105232, - _theResult_____1__h75875, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_F_F_F_F_F_F) begin - v__h105232 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_F_F_F_F_F_F) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h105232, - _theResult_____1__h75875, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_T_F) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_T_F) begin - v__h105232 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_T_F) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_T_F) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h105232, - _theResult_____1__h75875, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_T_F) begin - v__h96695 = $time; + v__h95705 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F) - $display("[%0d]: %m: WORKER CONTROL ARM...", v__h96695); + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_T_F) + $display("[%0d]: %m: WORKER CONTROL ARM...", v__h95705); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_T_F) begin - v__h105232 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_T_F) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h105232, - _theResult_____1__h75875, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_F_T) begin - v__h105232 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h105232, - _theResult_____1__h75875, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_F_F_T) begin - v__h105232 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h105232, - _theResult_____1__h75875, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_F_F_F_T) begin - v__h105232 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_F_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h105232, - _theResult_____1__h75875, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_F_F_F_F_T) begin - v__h105232 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_F_F_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h105232, - _theResult_____1__h75875, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_F_F_F_F_F) begin - v__h105232 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_F_F_F_F_F) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h105232, - _theResult_____1__h75875, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_T_F) begin - v__h105232 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_T_F) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h105232, - _theResult_____1__h75875, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_T_F) begin - v__h96767 = $time; + v__h95776 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F) - $display("[%0d]: %m: WORKER CONTROL ARM...", v__h96767); + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_T_F) + $display("[%0d]: %m: WORKER CONTROL ARM...", v__h95776); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_T_F) begin - v__h105232 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_T_F) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h105232, - _theResult_____1__h75875, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_F_T) begin - v__h105232 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h105232, - _theResult_____1__h75875, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_F_F_T) begin - v__h105232 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h105232, - _theResult_____1__h75875, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_F_F_F_T) begin - v__h105232 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_F_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h105232, - _theResult_____1__h75875, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_F_F_F_F_T) begin - v__h105232 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_F_F_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h105232, - _theResult_____1__h75875, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_F_F_F_F_F) begin - v__h105232 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_F_F_F_F_F) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h105232, - _theResult_____1__h75875, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_T_F) begin - v__h105232 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_T_F) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h105232, - _theResult_____1__h75875, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_F_T_F) begin - v__h96839 = $time; + v__h95847 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F) - $display("[%0d]: %m: WORKER CONTROL ARM...", v__h96839); + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_F_T_F) + $display("[%0d]: %m: WORKER CONTROL ARM...", v__h95847); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_F_T_F) begin - v__h105232 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_F_T_F) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h105232, - _theResult_____1__h75875, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_F_F_T) begin - v__h105232 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h105232, - _theResult_____1__h75875, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_F_F_F_T) begin - v__h105232 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_F_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h105232, - _theResult_____1__h75875, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_F_F_F_F_T) begin - v__h105232 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_F_F_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h105232, - _theResult_____1__h75875, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_F_F_F_F_F_T) begin - v__h105232 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_F_F_F_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h105232, - _theResult_____1__h75875, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_F_F_F_F_F_F) begin - v__h105232 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_F_F_F_F_F_F) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h105232, - _theResult_____1__h75875, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_T_F) begin - v__h105232 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_T_F) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h105232, - _theResult_____1__h75875, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_F_T_F) begin - v__h96911 = $time; + v__h95918 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F) - $display("[%0d]: %m: WORKER CONTROL ARM...", v__h96911); + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_F_T_F) + $display("[%0d]: %m: WORKER CONTROL ARM...", v__h95918); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_F_T_F) begin - v__h105232 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_F_T_F) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h105232, - _theResult_____1__h75875, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_F_F_T) begin - v__h105232 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h105232, - _theResult_____1__h75875, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_F_F_F_T) begin - v__h105232 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_F_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h105232, - _theResult_____1__h75875, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_F_F_F_F_T) begin - v__h105232 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_F_F_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h105232, - _theResult_____1__h75875, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_F_F_F_F_F_T) begin - v__h105232 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_F_F_F_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h105232, - _theResult_____1__h75875, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_F_F_F_F_F_F) begin - v__h105232 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_F_F_F_F_F_F) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h105232, - _theResult_____1__h75875, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_T_F) begin - v__h105232 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_T_F) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h105232, - _theResult_____1__h75875, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_F_T_F) begin - v__h96983 = $time; + v__h95989 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F) - $display("[%0d]: %m: WORKER CONTROL ARM...", v__h96983); + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_F_T_F) + $display("[%0d]: %m: WORKER CONTROL ARM...", v__h95989); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_F_T_F) begin - v__h105232 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_F_T_F) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h105232, - _theResult_____1__h75875, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_F_F_T) begin - v__h105232 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h105232, - _theResult_____1__h75875, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_F_F_F_T) begin - v__h105232 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_F_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h105232, - _theResult_____1__h75875, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_F_F_F_F_T) begin - v__h105232 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_F_F_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h105232, - _theResult_____1__h75875, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_F_F_F_F_F_T) begin - v__h105232 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_F_F_F_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h105232, - _theResult_____1__h75875, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_F_F_F_F_F_F) begin - v__h105232 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_F_F_F_F_F_F) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h105232, - _theResult_____1__h75875, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_T_F) begin - v__h105232 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_T_F) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h105232, - _theResult_____1__h75875, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_F_T_F) begin - v__h97055 = $time; + v__h96060 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F) - $display("[%0d]: %m: WORKER CONTROL ARM...", v__h97055); + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_F_T_F) + $display("[%0d]: %m: WORKER CONTROL ARM...", v__h96060); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_F_T_F) begin - v__h105232 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_F_T_F) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h105232, - _theResult_____1__h75875, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_F_F_T) begin - v__h105232 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h105232, - _theResult_____1__h75875, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_F_F_F_T) begin - v__h105232 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_F_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h105232, - _theResult_____1__h75875, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_F_F_F_F_T) begin - v__h105232 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_F_F_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h105232, - _theResult_____1__h75875, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_F_F_F_F_F_T) begin - v__h105232 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_F_F_F_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h105232, - _theResult_____1__h75875, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_F_F_F_F_F_F) begin - v__h105232 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_F_F_F_F_F_F) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h105232, - _theResult_____1__h75875, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_T_F) begin - v__h105232 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_T_F) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h105232, - _theResult_____1__h75875, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_F_T_F) begin - v__h97127 = $time; + v__h96131 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F) - $display("[%0d]: %m: WORKER CONTROL ARM...", v__h97127); + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_F_T_F) + $display("[%0d]: %m: WORKER CONTROL ARM...", v__h96131); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_F_T_F) begin - v__h105232 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_F_T_F) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h105232, - _theResult_____1__h75875, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_F_F_T) begin - v__h105232 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h105232, - _theResult_____1__h75875, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_F_F_F_T) begin - v__h105232 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_F_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h105232, - _theResult_____1__h75875, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_F_F_F_F_T) begin - v__h105232 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_F_F_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h105232, - _theResult_____1__h75875, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_F_F_F_F_F_T) begin - v__h105232 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_F_F_F_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h105232, - _theResult_____1__h75875, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_F_F_F_F_F_F) begin - v__h105232 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_F_F_F_F_F_F) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h105232, - _theResult_____1__h75875, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_T_F) begin - v__h105232 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_F) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_T_F) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h105232, - _theResult_____1__h75875, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_F_T_F) begin - v__h97199 = $time; + v__h96202 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F) - $display("[%0d]: %m: WORKER CONTROL ARM...", v__h97199); + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_F_T_F) + $display("[%0d]: %m: WORKER CONTROL ARM...", v__h96202); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_F_T_F) begin - v__h105232 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_F) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_F_T_F) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h105232, - _theResult_____1__h75875, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_F_F_T) begin - v__h105232 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h105232, - _theResult_____1__h75875, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_F_F_F_T) begin - v__h105232 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_F_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h105232, - _theResult_____1__h75875, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_F_F_F_F_T) begin - v__h105232 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_F_F_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h105232, - _theResult_____1__h75875, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_F_F_F_F_F_T) begin - v__h105232 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_F_F_F_F_F_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h105232, - _theResult_____1__h75875, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_F_F_F_F_F_F) begin - v__h105232 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_F_F_F_F) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_F_F_F_F_F_F) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h105232, - _theResult_____1__h75875, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_OOB) begin - v__h105232 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_OOB) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h105232, - _theResult_____1__h75875, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); @@ -22227,3512 +28953,3530 @@ module mkOCCP(pciDevice, if (rom_serverAdapter_s1[1] && !rom_serverAdapter_outDataCore$FULL_N) $display("ERROR: %m: mkBRAMSeverAdapter overrun"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_T_F_F_T_T_F) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E0_F_F_T_T_F) begin - v__h105179 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_T_F_F_T_T_F) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E0_F_F_T_T_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h105179, - _theResult_____1__h75857, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_T_F_F_T_F_F) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E0_F_F_T_F_F) begin - v__h105179 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_T_F_F_T_F_F) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E0_F_F_T_F_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h105179, - _theResult_____1__h75857, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_T_T_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E0_T_T) begin - v__h105179 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_T_T_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E0_T_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h105179, - _theResult_____1__h75857, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_T_F_F_T_T_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E0_F_F_T_T_T) begin - v__h105179 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_T_F_F_T_T_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E0_F_F_T_T_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h105179, - _theResult_____1__h75857, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_T_F_F_T_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E0_F_F_T_F_T) begin - v__h105179 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_T_F_F_T_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E0_F_F_T_F_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h105179, - _theResult_____1__h75857, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_T_T_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_T_T) begin - v__h105232 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_T_T_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_T_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h105232, - _theResult_____1__h75875, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_T_F_T_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_T_T) begin - v__h96191 = $time; + v__h95208 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_T_F_T_T) - $display("[%0d]: %m: WORKER CONTROL ARM...", v__h96191); + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_T_T) + $display("[%0d]: %m: WORKER CONTROL ARM...", v__h95208); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_T_F_T_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_T_T) begin - v__h105232 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_T_F_T_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E0_F_T_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h105232, - _theResult_____1__h75875, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_T_F_F_T_T_F) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E1_F_F_T_T_F) begin - v__h105179 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_T_F_F_T_T_F) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E1_F_F_T_T_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h105179, - _theResult_____1__h75857, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_T_F_F_T_F_F) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E1_F_F_T_F_F) begin - v__h105179 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_T_F_F_T_F_F) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E1_F_F_T_F_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h105179, - _theResult_____1__h75857, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_T_T_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E1_T_T) begin - v__h105179 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_T_T_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E1_T_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h105179, - _theResult_____1__h75857, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_T_F_F_T_T_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E1_F_F_T_T_T) begin - v__h105179 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_T_F_F_T_T_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E1_F_F_T_T_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h105179, - _theResult_____1__h75857, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_T_F_F_T_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E1_F_F_T_F_T) begin - v__h105179 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_T_F_F_T_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E1_F_F_T_F_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h105179, - _theResult_____1__h75857, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_T_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_T_T) begin - v__h105232 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_T_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_T_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h105232, - _theResult_____1__h75875, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_F_T_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_T_T) begin - v__h96263 = $time; + v__h95279 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_F_T_T) - $display("[%0d]: %m: WORKER CONTROL ARM...", v__h96263); + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_T_T) + $display("[%0d]: %m: WORKER CONTROL ARM...", v__h95279); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_F_T_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_T_T) begin - v__h105232 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_T_F_T_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E1_F_T_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h105232, - _theResult_____1__h75875, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_F_F_T_T_F) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E2_F_F_T_T_F) begin - v__h105179 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_F_F_T_T_F) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E2_F_F_T_T_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h105179, - _theResult_____1__h75857, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_F_F_T_F_F) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E2_F_F_T_F_F) begin - v__h105179 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_F_F_T_F_F) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E2_F_F_T_F_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h105179, - _theResult_____1__h75857, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_T_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E2_T_T) begin - v__h105179 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_T_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E2_T_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h105179, - _theResult_____1__h75857, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_F_F_T_T_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E2_F_F_T_T_T) begin - v__h105179 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_F_F_T_T_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E2_F_F_T_T_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h105179, - _theResult_____1__h75857, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_F_F_T_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E2_F_F_T_F_T) begin - v__h105179 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_T_F_F_T_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E2_F_F_T_F_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h105179, - _theResult_____1__h75857, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_T_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_T_T) begin - v__h105232 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_T_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_T_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h105232, - _theResult_____1__h75875, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_F_T_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_F_T_T) begin - v__h96335 = $time; + v__h95350 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_F_T_T) - $display("[%0d]: %m: WORKER CONTROL ARM...", v__h96335); + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_F_T_T) + $display("[%0d]: %m: WORKER CONTROL ARM...", v__h95350); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_F_T_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_F_T_T) begin - v__h105232 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_T_F_T_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E2_F_T_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h105232, - _theResult_____1__h75875, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_F_F_T_T_F) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E3_F_F_T_T_F) begin - v__h105179 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_F_F_T_T_F) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E3_F_F_T_T_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h105179, - _theResult_____1__h75857, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_F_F_T_F_F) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E3_F_F_T_F_F) begin - v__h105179 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_F_F_T_F_F) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E3_F_F_T_F_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h105179, - _theResult_____1__h75857, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_T_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E3_T_T) begin - v__h105179 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_T_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E3_T_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h105179, - _theResult_____1__h75857, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_F_F_T_T_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E3_F_F_T_T_T) begin - v__h105179 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_F_F_T_T_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E3_F_F_T_T_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h105179, - _theResult_____1__h75857, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_F_F_T_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E3_F_F_T_F_T) begin - v__h105179 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_T_F_F_T_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E3_F_F_T_F_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h105179, - _theResult_____1__h75857, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_T_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_T_T) begin - v__h105232 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_T_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_T_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h105232, - _theResult_____1__h75875, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_F_T_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_F_T_T) begin - v__h96407 = $time; + v__h95421 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_F_T_T) - $display("[%0d]: %m: WORKER CONTROL ARM...", v__h96407); + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_F_T_T) + $display("[%0d]: %m: WORKER CONTROL ARM...", v__h95421); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_F_T_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_F_T_T) begin - v__h105232 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_T_F_T_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E3_F_T_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h105232, - _theResult_____1__h75875, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_F_F_T_T_F) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E4_F_F_T_T_F) begin - v__h105179 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_F_F_T_T_F) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E4_F_F_T_T_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h105179, - _theResult_____1__h75857, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_F_F_T_F_F) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E4_F_F_T_F_F) begin - v__h105179 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_F_F_T_F_F) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E4_F_F_T_F_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h105179, - _theResult_____1__h75857, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_T_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E4_T_T) begin - v__h105179 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_T_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E4_T_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h105179, - _theResult_____1__h75857, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_F_F_T_T_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E4_F_F_T_T_T) begin - v__h105179 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_F_F_T_T_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E4_F_F_T_T_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h105179, - _theResult_____1__h75857, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_F_F_T_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E4_F_F_T_F_T) begin - v__h105179 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_T_F_F_T_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E4_F_F_T_F_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h105179, - _theResult_____1__h75857, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_T_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_T_T) begin - v__h105232 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_T_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_T_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h105232, - _theResult_____1__h75875, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_T_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_F_T_T) begin - v__h96479 = $time; + v__h95492 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_T_T) - $display("[%0d]: %m: WORKER CONTROL ARM...", v__h96479); + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_F_T_T) + $display("[%0d]: %m: WORKER CONTROL ARM...", v__h95492); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_T_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_F_T_T) begin - v__h105232 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_T_F_T_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E4_F_T_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h105232, - _theResult_____1__h75875, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_F_T_T_F) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E5_F_F_T_T_F) begin - v__h105179 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_F_T_T_F) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E5_F_F_T_T_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h105179, - _theResult_____1__h75857, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_F_T_F_F) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E5_F_F_T_F_F) begin - v__h105179 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_F_T_F_F) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E5_F_F_T_F_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h105179, - _theResult_____1__h75857, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_T_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E5_T_T) begin - v__h105179 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_T_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E5_T_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h105179, - _theResult_____1__h75857, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_F_T_T_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E5_F_F_T_T_T) begin - v__h105179 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_F_T_T_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E5_F_F_T_T_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h105179, - _theResult_____1__h75857, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_F_T_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E5_F_F_T_F_T) begin - v__h105179 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_T_F_F_T_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E5_F_F_T_F_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h105179, - _theResult_____1__h75857, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_T_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_T_T) begin - v__h105232 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_T_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_T_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h105232, - _theResult_____1__h75875, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_T_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_T_T) begin - v__h96551 = $time; + v__h95563 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_T_T) - $display("[%0d]: %m: WORKER CONTROL ARM...", v__h96551); + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_T_T) + $display("[%0d]: %m: WORKER CONTROL ARM...", v__h95563); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_T_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_T_T) begin - v__h105232 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_T_F_T_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E5_F_T_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h105232, - _theResult_____1__h75875, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_F_F_T_T_F) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E6_F_F_T_T_F) begin - v__h105179 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_F_F_T_T_F) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E6_F_F_T_T_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h105179, - _theResult_____1__h75857, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_F_F_T_F_F) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E6_F_F_T_F_F) begin - v__h105179 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_F_F_T_F_F) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E6_F_F_T_F_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h105179, - _theResult_____1__h75857, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_T_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E6_T_T) begin - v__h105179 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_T_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E6_T_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h105179, - _theResult_____1__h75857, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_F_F_T_T_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E6_F_F_T_T_T) begin - v__h105179 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_F_F_T_T_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E6_F_F_T_T_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h105179, - _theResult_____1__h75857, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_F_F_T_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E6_F_F_T_F_T) begin - v__h105179 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_T_F_F_T_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E6_F_F_T_F_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h105179, - _theResult_____1__h75857, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_T_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_T_T) begin - v__h105232 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_T_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_T_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h105232, - _theResult_____1__h75875, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_F_T_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_F_T_T) begin - v__h96623 = $time; + v__h95634 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_F_T_T) - $display("[%0d]: %m: WORKER CONTROL ARM...", v__h96623); + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_F_T_T) + $display("[%0d]: %m: WORKER CONTROL ARM...", v__h95634); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_F_T_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_F_T_T) begin - v__h105232 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_T_F_T_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E6_F_T_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h105232, - _theResult_____1__h75875, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_F_F_T_T_F) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E7_F_F_T_T_F) begin - v__h105179 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_F_F_T_T_F) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E7_F_F_T_T_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h105179, - _theResult_____1__h75857, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_F_F_T_F_F) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E7_F_F_T_F_F) begin - v__h105179 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_F_F_T_F_F) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E7_F_F_T_F_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h105179, - _theResult_____1__h75857, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_T_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E7_T_T) begin - v__h105179 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_T_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E7_T_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h105179, - _theResult_____1__h75857, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_F_F_T_T_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E7_F_F_T_T_T) begin - v__h105179 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_F_F_T_T_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E7_F_F_T_T_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h105179, - _theResult_____1__h75857, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_F_F_T_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E7_F_F_T_F_T) begin - v__h105179 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_T_F_F_T_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E7_F_F_T_F_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h105179, - _theResult_____1__h75857, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_T_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_T_T) begin - v__h105232 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_T_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_T_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h105232, - _theResult_____1__h75875, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_T_T) begin - v__h96695 = $time; + v__h95705 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T) - $display("[%0d]: %m: WORKER CONTROL ARM...", v__h96695); + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_T_T) + $display("[%0d]: %m: WORKER CONTROL ARM...", v__h95705); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_T_T) begin - v__h105232 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E7_F_T_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h105232, - _theResult_____1__h75875, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_F_F_T_T_F) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E8_F_F_T_T_F) begin - v__h105179 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_F_F_T_T_F) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E8_F_F_T_T_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h105179, - _theResult_____1__h75857, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_F_F_T_F_F) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E8_F_F_T_F_F) begin - v__h105179 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_F_F_T_F_F) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E8_F_F_T_F_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h105179, - _theResult_____1__h75857, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_T_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E8_T_T) begin - v__h105179 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_T_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E8_T_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h105179, - _theResult_____1__h75857, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_F_F_T_T_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E8_F_F_T_T_T) begin - v__h105179 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_F_F_T_T_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E8_F_F_T_T_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h105179, - _theResult_____1__h75857, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_F_F_T_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E8_F_F_T_F_T) begin - v__h105179 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_T_F_F_T_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E8_F_F_T_F_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h105179, - _theResult_____1__h75857, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_T_T) begin - v__h105232 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_T_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h105232, - _theResult_____1__h75875, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_T_T) begin - v__h96767 = $time; + v__h95776 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T) - $display("[%0d]: %m: WORKER CONTROL ARM...", v__h96767); + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_T_T) + $display("[%0d]: %m: WORKER CONTROL ARM...", v__h95776); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_T_T) begin - v__h105232 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E8_F_T_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h105232, - _theResult_____1__h75875, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_F_F_T_T_F) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E9_F_F_T_T_F) begin - v__h105179 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_F_F_T_T_F) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E9_F_F_T_T_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h105179, - _theResult_____1__h75857, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_F_F_T_F_F) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E9_F_F_T_F_F) begin - v__h105179 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_F_F_T_F_F) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E9_F_F_T_F_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h105179, - _theResult_____1__h75857, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_T_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E9_T_T) begin - v__h105179 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_T_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E9_T_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h105179, - _theResult_____1__h75857, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_F_F_T_T_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E9_F_F_T_T_T) begin - v__h105179 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_F_F_T_T_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E9_F_F_T_T_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h105179, - _theResult_____1__h75857, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_F_F_T_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E9_F_F_T_F_T) begin - v__h105179 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_T_F_F_T_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E9_F_F_T_F_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h105179, - _theResult_____1__h75857, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_T_T) begin - v__h105232 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_T_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h105232, - _theResult_____1__h75875, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_F_T_T) begin - v__h96839 = $time; + v__h95847 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T) - $display("[%0d]: %m: WORKER CONTROL ARM...", v__h96839); + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_F_T_T) + $display("[%0d]: %m: WORKER CONTROL ARM...", v__h95847); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_F_T_T) begin - v__h105232 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E9_F_T_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h105232, - _theResult_____1__h75875, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_F) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E10_F_F_T_T_F) begin - v__h105179 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_F) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E10_F_F_T_T_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h105179, - _theResult_____1__h75857, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_F) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E10_F_F_T_F_F) begin - v__h105179 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_F) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E10_F_F_T_F_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h105179, - _theResult_____1__h75857, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_T_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E10_T_T) begin - v__h105179 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_T_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E10_T_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h105179, - _theResult_____1__h75857, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E10_F_F_T_T_T) begin - v__h105179 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E10_F_F_T_T_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h105179, - _theResult_____1__h75857, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E10_F_F_T_F_T) begin - v__h105179 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E10_F_F_T_F_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h105179, - _theResult_____1__h75857, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_T_T) begin - v__h105232 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_T_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h105232, - _theResult_____1__h75875, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_F_T_T) begin - v__h96911 = $time; + v__h95918 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T) - $display("[%0d]: %m: WORKER CONTROL ARM...", v__h96911); + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_F_T_T) + $display("[%0d]: %m: WORKER CONTROL ARM...", v__h95918); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_F_T_T) begin - v__h105232 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E10_F_T_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h105232, - _theResult_____1__h75875, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_F) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E11_F_F_T_T_F) begin - v__h105179 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_F) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E11_F_F_T_T_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h105179, - _theResult_____1__h75857, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_F) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E11_F_F_T_F_F) begin - v__h105179 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_F) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E11_F_F_T_F_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h105179, - _theResult_____1__h75857, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_T_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E11_T_T) begin - v__h105179 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_T_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E11_T_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h105179, - _theResult_____1__h75857, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E11_F_F_T_T_T) begin - v__h105179 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E11_F_F_T_T_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h105179, - _theResult_____1__h75857, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E11_F_F_T_F_T) begin - v__h105179 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E11_F_F_T_F_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h105179, - _theResult_____1__h75857, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_T_T) begin - v__h105232 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_T_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h105232, - _theResult_____1__h75875, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_F_T_T) begin - v__h96983 = $time; + v__h95989 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T) - $display("[%0d]: %m: WORKER CONTROL ARM...", v__h96983); + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_F_T_T) + $display("[%0d]: %m: WORKER CONTROL ARM...", v__h95989); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_F_T_T) begin - v__h105232 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E11_F_T_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h105232, - _theResult_____1__h75875, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_F) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E12_F_F_T_T_F) begin - v__h105179 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_F) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E12_F_F_T_T_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h105179, - _theResult_____1__h75857, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_F) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E12_F_F_T_F_F) begin - v__h105179 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_F) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E12_F_F_T_F_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h105179, - _theResult_____1__h75857, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E12_T_T) begin - v__h105179 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E12_T_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h105179, - _theResult_____1__h75857, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E12_F_F_T_T_T) begin - v__h105179 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E12_F_F_T_T_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h105179, - _theResult_____1__h75857, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E12_F_F_T_F_T) begin - v__h105179 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E12_F_F_T_F_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h105179, - _theResult_____1__h75857, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_T_T) begin - v__h105232 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_T_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h105232, - _theResult_____1__h75875, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_F_T_T) begin - v__h97055 = $time; + v__h96060 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T) - $display("[%0d]: %m: WORKER CONTROL ARM...", v__h97055); + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_F_T_T) + $display("[%0d]: %m: WORKER CONTROL ARM...", v__h96060); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_F_T_T) begin - v__h105232 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E12_F_T_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h105232, - _theResult_____1__h75875, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_F) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E13_F_F_T_T_F) begin - v__h105179 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_F) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E13_F_F_T_T_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h105179, - _theResult_____1__h75857, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_F) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E13_F_F_T_F_F) begin - v__h105179 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_F) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E13_F_F_T_F_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h105179, - _theResult_____1__h75857, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E13_T_T) begin - v__h105179 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E13_T_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h105179, - _theResult_____1__h75857, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E13_F_F_T_T_T) begin - v__h105179 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E13_F_F_T_T_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h105179, - _theResult_____1__h75857, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E13_F_F_T_F_T) begin - v__h105179 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E13_F_F_T_F_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h105179, - _theResult_____1__h75857, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_T_T) begin - v__h105232 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_T_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h105232, - _theResult_____1__h75875, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_F_T_T) begin - v__h97127 = $time; + v__h96131 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T) - $display("[%0d]: %m: WORKER CONTROL ARM...", v__h97127); + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_F_T_T) + $display("[%0d]: %m: WORKER CONTROL ARM...", v__h96131); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_F_T_T) begin - v__h105232 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E13_F_T_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h105232, - _theResult_____1__h75875, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_F) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E14_F_F_T_T_F) begin - v__h105179 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_F) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E14_F_F_T_T_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h105179, - _theResult_____1__h75857, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_F) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E14_F_F_T_F_F) begin - v__h105179 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_F) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E14_F_F_T_F_F) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h105179, - _theResult_____1__h75857, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E14_T_T) begin - v__h105179 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E14_T_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h105179, - _theResult_____1__h75857, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E14_F_F_T_T_T) begin - v__h105179 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_T_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E14_F_F_T_T_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h105179, - _theResult_____1__h75857, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E14_F_F_T_F_T) begin - v__h105179 = $time; + v__h104109 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_T_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_F_T_F_T) + if (WILL_FIRE_RL_cpDispatch_F_F_T_E14_F_F_T_F_T) $display("[%0d]: %m: reqWorker WRITE-POSTED Worker:%0d sp:%x Addr:%0x Data:%0x BE:%0x", - v__h105179, - _theResult_____1__h75857, + v__h104109, + _theResult_____1__h75724, cpReq[61:60], cpReq[27:4], cpReq[59:28], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_T_T) begin - v__h105232 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_T_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_T_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h105232, - _theResult_____1__h75875, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_F_T_T) begin - v__h97199 = $time; + v__h96202 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T) - $display("[%0d]: %m: WORKER CONTROL ARM...", v__h97199); + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_F_T_T) + $display("[%0d]: %m: WORKER CONTROL ARM...", v__h96202); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_F_T_T) begin - v__h105232 = $time; + v__h104162 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cpDispatch_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_F_T_F_T_T) + if (WILL_FIRE_RL_cpDispatch_F_F_F_F_E14_F_T_T) $display("[%0d]: %m: reqWorker READ-REQUESTED Worker:%0d sp:%x Addr:%0x BE:%0x", - v__h105232, - _theResult_____1__h75875, + v__h104162, + _theResult_____1__h75739, cpReq[37:36], cpReq[27:4], cpReq[3:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy && wci_wciResponse$wget[33:32] == 2'd0 && - !wci_respTimr_02_ULT_1_SL_wci_wTimeout_03_04___d5829 && - wci_reqPend == 2'd1) + if (WILL_FIRE_RL_wci_0_wrkBusy && + wci_0_wciResponse$wget[33:32] == 2'd0 && + !wci_0_respTimr_28_ULT_1_SL_wci_0_wTimeout_29_30___d231 && + wci_0_reqPend == 2'd1) begin - v__h11118 = $time; + v__h11985 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy && wci_wciResponse$wget[33:32] == 2'd0 && - !wci_respTimr_02_ULT_1_SL_wci_wTimeout_03_04___d5829 && - wci_reqPend == 2'd1) - $display("[%0d]: %m: WORKER CONFIG-WRITE TIMEOUT", v__h11118); + if (WILL_FIRE_RL_wci_0_wrkBusy && + wci_0_wciResponse$wget[33:32] == 2'd0 && + !wci_0_respTimr_28_ULT_1_SL_wci_0_wTimeout_29_30___d231 && + wci_0_reqPend == 2'd1) + $display("[%0d]: %m: WORKER CONFIG-WRITE TIMEOUT", v__h11985); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy && wci_wciResponse$wget[33:32] == 2'd0 && - !wci_respTimr_02_ULT_1_SL_wci_wTimeout_03_04___d5829 && - wci_reqPend == 2'd2) + if (WILL_FIRE_RL_wci_0_wrkBusy && + wci_0_wciResponse$wget[33:32] == 2'd0 && + !wci_0_respTimr_28_ULT_1_SL_wci_0_wTimeout_29_30___d231 && + wci_0_reqPend == 2'd2) begin - v__h11208 = $time; + v__h12075 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy && wci_wciResponse$wget[33:32] == 2'd0 && - !wci_respTimr_02_ULT_1_SL_wci_wTimeout_03_04___d5829 && - wci_reqPend == 2'd2) - $display("[%0d]: %m: WORKER CONFIG-READ TIMEOUT", v__h11208); + if (WILL_FIRE_RL_wci_0_wrkBusy && + wci_0_wciResponse$wget[33:32] == 2'd0 && + !wci_0_respTimr_28_ULT_1_SL_wci_0_wTimeout_29_30___d231 && + wci_0_reqPend == 2'd2) + $display("[%0d]: %m: WORKER CONFIG-READ TIMEOUT", v__h12075); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy && wci_wciResponse$wget[33:32] == 2'd0 && - !wci_respTimr_02_ULT_1_SL_wci_wTimeout_03_04___d5829 && - wci_reqPend == 2'd3) + if (WILL_FIRE_RL_wci_0_wrkBusy && + wci_0_wciResponse$wget[33:32] == 2'd0 && + !wci_0_respTimr_28_ULT_1_SL_wci_0_wTimeout_29_30___d231 && + wci_0_reqPend == 2'd3) begin - v__h11297 = $time; + v__h12164 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy && wci_wciResponse$wget[33:32] == 2'd0 && - !wci_respTimr_02_ULT_1_SL_wci_wTimeout_03_04___d5829 && - wci_reqPend == 2'd3) - $display("[%0d]: %m: WORKER CONTROL-OP TIMEOUT", v__h11297); + if (WILL_FIRE_RL_wci_0_wrkBusy && + wci_0_wciResponse$wget[33:32] == 2'd0 && + !wci_0_respTimr_28_ULT_1_SL_wci_0_wTimeout_29_30___d231 && + wci_0_reqPend == 2'd3) + $display("[%0d]: %m: WORKER CONTROL-OP TIMEOUT", v__h12164); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy && wci_wciResponse$wget[33:32] == 2'd2 && - wci_reqPend == 2'd1) + if (WILL_FIRE_RL_wci_0_wrkBusy && + wci_0_wciResponse$wget[33:32] == 2'd2 && + wci_0_reqPend == 2'd1) begin - v__h11521 = $time; + v__h12388 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy && wci_wciResponse$wget[33:32] == 2'd2 && - wci_reqPend == 2'd1) - $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-FAIL", v__h11521); + if (WILL_FIRE_RL_wci_0_wrkBusy && + wci_0_wciResponse$wget[33:32] == 2'd2 && + wci_0_reqPend == 2'd1) + $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-FAIL", v__h12388); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy && wci_wciResponse$wget[33:32] == 2'd2 && - wci_reqPend == 2'd2) + if (WILL_FIRE_RL_wci_0_wrkBusy && + wci_0_wciResponse$wget[33:32] == 2'd2 && + wci_0_reqPend == 2'd2) begin - v__h11611 = $time; + v__h12478 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy && wci_wciResponse$wget[33:32] == 2'd2 && - wci_reqPend == 2'd2) - $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-FAIL", v__h11611); + if (WILL_FIRE_RL_wci_0_wrkBusy && + wci_0_wciResponse$wget[33:32] == 2'd2 && + wci_0_reqPend == 2'd2) + $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-FAIL", v__h12478); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy && wci_wciResponse$wget[33:32] == 2'd2 && - wci_reqPend == 2'd3) + if (WILL_FIRE_RL_wci_0_wrkBusy && + wci_0_wciResponse$wget[33:32] == 2'd2 && + wci_0_reqPend == 2'd3) begin - v__h11700 = $time; + v__h12567 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy && wci_wciResponse$wget[33:32] == 2'd2 && - wci_reqPend == 2'd3) - $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-FAIL", v__h11700); + if (WILL_FIRE_RL_wci_0_wrkBusy && + wci_0_wciResponse$wget[33:32] == 2'd2 && + wci_0_reqPend == 2'd3) + $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-FAIL", v__h12567); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy && wci_wciResponse$wget[33:32] == 2'd3 && - wci_reqPend == 2'd1) + if (WILL_FIRE_RL_wci_0_wrkBusy && + wci_0_wciResponse$wget[33:32] == 2'd3 && + wci_0_reqPend == 2'd1) begin - v__h11929 = $time; + v__h12796 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy && wci_wciResponse$wget[33:32] == 2'd3 && - wci_reqPend == 2'd1) - $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-ERR", v__h11929); + if (WILL_FIRE_RL_wci_0_wrkBusy && + wci_0_wciResponse$wget[33:32] == 2'd3 && + wci_0_reqPend == 2'd1) + $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-ERR", v__h12796); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy && wci_wciResponse$wget[33:32] == 2'd3 && - wci_reqPend == 2'd2) + if (WILL_FIRE_RL_wci_0_wrkBusy && + wci_0_wciResponse$wget[33:32] == 2'd3 && + wci_0_reqPend == 2'd2) begin - v__h12019 = $time; + v__h12886 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy && wci_wciResponse$wget[33:32] == 2'd3 && - wci_reqPend == 2'd2) - $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-ERR", v__h12019); + if (WILL_FIRE_RL_wci_0_wrkBusy && + wci_0_wciResponse$wget[33:32] == 2'd3 && + wci_0_reqPend == 2'd2) + $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-ERR", v__h12886); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy && wci_wciResponse$wget[33:32] == 2'd3 && - wci_reqPend == 2'd3) + if (WILL_FIRE_RL_wci_0_wrkBusy && + wci_0_wciResponse$wget[33:32] == 2'd3 && + wci_0_reqPend == 2'd3) begin - v__h12108 = $time; + v__h12975 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy && wci_wciResponse$wget[33:32] == 2'd3 && - wci_reqPend == 2'd3) - $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-ERR", v__h12108); + if (WILL_FIRE_RL_wci_0_wrkBusy && + wci_0_wciResponse$wget[33:32] == 2'd3 && + wci_0_reqPend == 2'd3) + $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-ERR", v__h12975); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_1 && - wci_wciResponse_1$wget[33:32] == 2'd0 && - !wci_respTimr_1_42_ULT_1_SL_wci_wTimeout_1_43_44___d5830 && - wci_reqPend_1 == 2'd1) + if (WILL_FIRE_RL_wci_1_wrkBusy && + wci_1_wciResponse$wget[33:32] == 2'd0 && + !wci_1_respTimr_68_ULT_1_SL_wci_1_wTimeout_69_70___d371 && + wci_1_reqPend == 2'd1) begin - v__h15558 = $time; + v__h16354 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_1 && - wci_wciResponse_1$wget[33:32] == 2'd0 && - !wci_respTimr_1_42_ULT_1_SL_wci_wTimeout_1_43_44___d5830 && - wci_reqPend_1 == 2'd1) - $display("[%0d]: %m: WORKER CONFIG-WRITE TIMEOUT", v__h15558); + if (WILL_FIRE_RL_wci_1_wrkBusy && + wci_1_wciResponse$wget[33:32] == 2'd0 && + !wci_1_respTimr_68_ULT_1_SL_wci_1_wTimeout_69_70___d371 && + wci_1_reqPend == 2'd1) + $display("[%0d]: %m: WORKER CONFIG-WRITE TIMEOUT", v__h16354); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_1 && - wci_wciResponse_1$wget[33:32] == 2'd0 && - !wci_respTimr_1_42_ULT_1_SL_wci_wTimeout_1_43_44___d5830 && - wci_reqPend_1 == 2'd2) + if (WILL_FIRE_RL_wci_1_wrkBusy && + wci_1_wciResponse$wget[33:32] == 2'd0 && + !wci_1_respTimr_68_ULT_1_SL_wci_1_wTimeout_69_70___d371 && + wci_1_reqPend == 2'd2) begin - v__h15648 = $time; + v__h16444 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_1 && - wci_wciResponse_1$wget[33:32] == 2'd0 && - !wci_respTimr_1_42_ULT_1_SL_wci_wTimeout_1_43_44___d5830 && - wci_reqPend_1 == 2'd2) - $display("[%0d]: %m: WORKER CONFIG-READ TIMEOUT", v__h15648); + if (WILL_FIRE_RL_wci_1_wrkBusy && + wci_1_wciResponse$wget[33:32] == 2'd0 && + !wci_1_respTimr_68_ULT_1_SL_wci_1_wTimeout_69_70___d371 && + wci_1_reqPend == 2'd2) + $display("[%0d]: %m: WORKER CONFIG-READ TIMEOUT", v__h16444); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_1 && - wci_wciResponse_1$wget[33:32] == 2'd0 && - !wci_respTimr_1_42_ULT_1_SL_wci_wTimeout_1_43_44___d5830 && - wci_reqPend_1 == 2'd3) + if (WILL_FIRE_RL_wci_1_wrkBusy && + wci_1_wciResponse$wget[33:32] == 2'd0 && + !wci_1_respTimr_68_ULT_1_SL_wci_1_wTimeout_69_70___d371 && + wci_1_reqPend == 2'd3) begin - v__h15737 = $time; + v__h16533 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_1 && - wci_wciResponse_1$wget[33:32] == 2'd0 && - !wci_respTimr_1_42_ULT_1_SL_wci_wTimeout_1_43_44___d5830 && - wci_reqPend_1 == 2'd3) - $display("[%0d]: %m: WORKER CONTROL-OP TIMEOUT", v__h15737); + if (WILL_FIRE_RL_wci_1_wrkBusy && + wci_1_wciResponse$wget[33:32] == 2'd0 && + !wci_1_respTimr_68_ULT_1_SL_wci_1_wTimeout_69_70___d371 && + wci_1_reqPend == 2'd3) + $display("[%0d]: %m: WORKER CONTROL-OP TIMEOUT", v__h16533); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_1 && - wci_wciResponse_1$wget[33:32] == 2'd2 && - wci_reqPend_1 == 2'd1) + if (WILL_FIRE_RL_wci_1_wrkBusy && + wci_1_wciResponse$wget[33:32] == 2'd2 && + wci_1_reqPend == 2'd1) begin - v__h15961 = $time; + v__h16757 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_1 && - wci_wciResponse_1$wget[33:32] == 2'd2 && - wci_reqPend_1 == 2'd1) - $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-FAIL", v__h15961); + if (WILL_FIRE_RL_wci_1_wrkBusy && + wci_1_wciResponse$wget[33:32] == 2'd2 && + wci_1_reqPend == 2'd1) + $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-FAIL", v__h16757); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_1 && - wci_wciResponse_1$wget[33:32] == 2'd2 && - wci_reqPend_1 == 2'd2) + if (WILL_FIRE_RL_wci_1_wrkBusy && + wci_1_wciResponse$wget[33:32] == 2'd2 && + wci_1_reqPend == 2'd2) begin - v__h16051 = $time; + v__h16847 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_1 && - wci_wciResponse_1$wget[33:32] == 2'd2 && - wci_reqPend_1 == 2'd2) - $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-FAIL", v__h16051); + if (WILL_FIRE_RL_wci_1_wrkBusy && + wci_1_wciResponse$wget[33:32] == 2'd2 && + wci_1_reqPend == 2'd2) + $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-FAIL", v__h16847); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_1 && - wci_wciResponse_1$wget[33:32] == 2'd2 && - wci_reqPend_1 == 2'd3) + if (WILL_FIRE_RL_wci_1_wrkBusy && + wci_1_wciResponse$wget[33:32] == 2'd2 && + wci_1_reqPend == 2'd3) begin - v__h16140 = $time; + v__h16936 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_1 && - wci_wciResponse_1$wget[33:32] == 2'd2 && - wci_reqPend_1 == 2'd3) - $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-FAIL", v__h16140); + if (WILL_FIRE_RL_wci_1_wrkBusy && + wci_1_wciResponse$wget[33:32] == 2'd2 && + wci_1_reqPend == 2'd3) + $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-FAIL", v__h16936); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_1 && - wci_wciResponse_1$wget[33:32] == 2'd3 && - wci_reqPend_1 == 2'd1) + if (WILL_FIRE_RL_wci_1_wrkBusy && + wci_1_wciResponse$wget[33:32] == 2'd3 && + wci_1_reqPend == 2'd1) begin - v__h16369 = $time; + v__h17165 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_1 && - wci_wciResponse_1$wget[33:32] == 2'd3 && - wci_reqPend_1 == 2'd1) - $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-ERR", v__h16369); + if (WILL_FIRE_RL_wci_1_wrkBusy && + wci_1_wciResponse$wget[33:32] == 2'd3 && + wci_1_reqPend == 2'd1) + $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-ERR", v__h17165); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_1 && - wci_wciResponse_1$wget[33:32] == 2'd3 && - wci_reqPend_1 == 2'd2) + if (WILL_FIRE_RL_wci_1_wrkBusy && + wci_1_wciResponse$wget[33:32] == 2'd3 && + wci_1_reqPend == 2'd2) begin - v__h16459 = $time; + v__h17255 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_1 && - wci_wciResponse_1$wget[33:32] == 2'd3 && - wci_reqPend_1 == 2'd2) - $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-ERR", v__h16459); + if (WILL_FIRE_RL_wci_1_wrkBusy && + wci_1_wciResponse$wget[33:32] == 2'd3 && + wci_1_reqPend == 2'd2) + $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-ERR", v__h17255); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_1 && - wci_wciResponse_1$wget[33:32] == 2'd3 && - wci_reqPend_1 == 2'd3) + if (WILL_FIRE_RL_wci_1_wrkBusy && + wci_1_wciResponse$wget[33:32] == 2'd3 && + wci_1_reqPend == 2'd3) begin - v__h16548 = $time; + v__h17344 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_1 && - wci_wciResponse_1$wget[33:32] == 2'd3 && - wci_reqPend_1 == 2'd3) - $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-ERR", v__h16548); + if (WILL_FIRE_RL_wci_1_wrkBusy && + wci_1_wciResponse$wget[33:32] == 2'd3 && + wci_1_reqPend == 2'd3) + $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-ERR", v__h17344); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_2 && - wci_wciResponse_2$wget[33:32] == 2'd0 && - !wci_respTimr_2_82_ULT_1_SL_wci_wTimeout_2_83_84___d5831 && - wci_reqPend_2 == 2'd1) + if (WILL_FIRE_RL_wci_2_wrkBusy && + wci_2_wciResponse$wget[33:32] == 2'd0 && + !wci_2_respTimr_08_ULT_1_SL_wci_2_wTimeout_09_10___d511 && + wci_2_reqPend == 2'd1) begin - v__h19998 = $time; + v__h20723 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_2 && - wci_wciResponse_2$wget[33:32] == 2'd0 && - !wci_respTimr_2_82_ULT_1_SL_wci_wTimeout_2_83_84___d5831 && - wci_reqPend_2 == 2'd1) - $display("[%0d]: %m: WORKER CONFIG-WRITE TIMEOUT", v__h19998); + if (WILL_FIRE_RL_wci_2_wrkBusy && + wci_2_wciResponse$wget[33:32] == 2'd0 && + !wci_2_respTimr_08_ULT_1_SL_wci_2_wTimeout_09_10___d511 && + wci_2_reqPend == 2'd1) + $display("[%0d]: %m: WORKER CONFIG-WRITE TIMEOUT", v__h20723); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_2 && - wci_wciResponse_2$wget[33:32] == 2'd0 && - !wci_respTimr_2_82_ULT_1_SL_wci_wTimeout_2_83_84___d5831 && - wci_reqPend_2 == 2'd2) + if (WILL_FIRE_RL_wci_2_wrkBusy && + wci_2_wciResponse$wget[33:32] == 2'd0 && + !wci_2_respTimr_08_ULT_1_SL_wci_2_wTimeout_09_10___d511 && + wci_2_reqPend == 2'd2) begin - v__h20088 = $time; + v__h20813 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_2 && - wci_wciResponse_2$wget[33:32] == 2'd0 && - !wci_respTimr_2_82_ULT_1_SL_wci_wTimeout_2_83_84___d5831 && - wci_reqPend_2 == 2'd2) - $display("[%0d]: %m: WORKER CONFIG-READ TIMEOUT", v__h20088); + if (WILL_FIRE_RL_wci_2_wrkBusy && + wci_2_wciResponse$wget[33:32] == 2'd0 && + !wci_2_respTimr_08_ULT_1_SL_wci_2_wTimeout_09_10___d511 && + wci_2_reqPend == 2'd2) + $display("[%0d]: %m: WORKER CONFIG-READ TIMEOUT", v__h20813); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_2 && - wci_wciResponse_2$wget[33:32] == 2'd0 && - !wci_respTimr_2_82_ULT_1_SL_wci_wTimeout_2_83_84___d5831 && - wci_reqPend_2 == 2'd3) + if (WILL_FIRE_RL_wci_2_wrkBusy && + wci_2_wciResponse$wget[33:32] == 2'd0 && + !wci_2_respTimr_08_ULT_1_SL_wci_2_wTimeout_09_10___d511 && + wci_2_reqPend == 2'd3) begin - v__h20177 = $time; + v__h20902 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_2 && - wci_wciResponse_2$wget[33:32] == 2'd0 && - !wci_respTimr_2_82_ULT_1_SL_wci_wTimeout_2_83_84___d5831 && - wci_reqPend_2 == 2'd3) - $display("[%0d]: %m: WORKER CONTROL-OP TIMEOUT", v__h20177); + if (WILL_FIRE_RL_wci_2_wrkBusy && + wci_2_wciResponse$wget[33:32] == 2'd0 && + !wci_2_respTimr_08_ULT_1_SL_wci_2_wTimeout_09_10___d511 && + wci_2_reqPend == 2'd3) + $display("[%0d]: %m: WORKER CONTROL-OP TIMEOUT", v__h20902); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_2 && - wci_wciResponse_2$wget[33:32] == 2'd2 && - wci_reqPend_2 == 2'd1) + if (WILL_FIRE_RL_wci_2_wrkBusy && + wci_2_wciResponse$wget[33:32] == 2'd2 && + wci_2_reqPend == 2'd1) begin - v__h20401 = $time; + v__h21126 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_2 && - wci_wciResponse_2$wget[33:32] == 2'd2 && - wci_reqPend_2 == 2'd1) - $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-FAIL", v__h20401); + if (WILL_FIRE_RL_wci_2_wrkBusy && + wci_2_wciResponse$wget[33:32] == 2'd2 && + wci_2_reqPend == 2'd1) + $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-FAIL", v__h21126); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_2 && - wci_wciResponse_2$wget[33:32] == 2'd2 && - wci_reqPend_2 == 2'd2) + if (WILL_FIRE_RL_wci_2_wrkBusy && + wci_2_wciResponse$wget[33:32] == 2'd2 && + wci_2_reqPend == 2'd2) begin - v__h20491 = $time; + v__h21216 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_2 && - wci_wciResponse_2$wget[33:32] == 2'd2 && - wci_reqPend_2 == 2'd2) - $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-FAIL", v__h20491); + if (WILL_FIRE_RL_wci_2_wrkBusy && + wci_2_wciResponse$wget[33:32] == 2'd2 && + wci_2_reqPend == 2'd2) + $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-FAIL", v__h21216); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_2 && - wci_wciResponse_2$wget[33:32] == 2'd2 && - wci_reqPend_2 == 2'd3) + if (WILL_FIRE_RL_wci_2_wrkBusy && + wci_2_wciResponse$wget[33:32] == 2'd2 && + wci_2_reqPend == 2'd3) begin - v__h20580 = $time; + v__h21305 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_2 && - wci_wciResponse_2$wget[33:32] == 2'd2 && - wci_reqPend_2 == 2'd3) - $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-FAIL", v__h20580); + if (WILL_FIRE_RL_wci_2_wrkBusy && + wci_2_wciResponse$wget[33:32] == 2'd2 && + wci_2_reqPend == 2'd3) + $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-FAIL", v__h21305); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_2 && - wci_wciResponse_2$wget[33:32] == 2'd3 && - wci_reqPend_2 == 2'd1) + if (WILL_FIRE_RL_wci_2_wrkBusy && + wci_2_wciResponse$wget[33:32] == 2'd3 && + wci_2_reqPend == 2'd1) begin - v__h20809 = $time; + v__h21534 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_2 && - wci_wciResponse_2$wget[33:32] == 2'd3 && - wci_reqPend_2 == 2'd1) - $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-ERR", v__h20809); + if (WILL_FIRE_RL_wci_2_wrkBusy && + wci_2_wciResponse$wget[33:32] == 2'd3 && + wci_2_reqPend == 2'd1) + $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-ERR", v__h21534); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_2 && - wci_wciResponse_2$wget[33:32] == 2'd3 && - wci_reqPend_2 == 2'd2) + if (WILL_FIRE_RL_wci_2_wrkBusy && + wci_2_wciResponse$wget[33:32] == 2'd3 && + wci_2_reqPend == 2'd2) begin - v__h20899 = $time; + v__h21624 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_2 && - wci_wciResponse_2$wget[33:32] == 2'd3 && - wci_reqPend_2 == 2'd2) - $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-ERR", v__h20899); + if (WILL_FIRE_RL_wci_2_wrkBusy && + wci_2_wciResponse$wget[33:32] == 2'd3 && + wci_2_reqPend == 2'd2) + $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-ERR", v__h21624); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_2 && - wci_wciResponse_2$wget[33:32] == 2'd3 && - wci_reqPend_2 == 2'd3) + if (WILL_FIRE_RL_wci_2_wrkBusy && + wci_2_wciResponse$wget[33:32] == 2'd3 && + wci_2_reqPend == 2'd3) begin - v__h20988 = $time; + v__h21713 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_2 && - wci_wciResponse_2$wget[33:32] == 2'd3 && - wci_reqPend_2 == 2'd3) - $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-ERR", v__h20988); + if (WILL_FIRE_RL_wci_2_wrkBusy && + wci_2_wciResponse$wget[33:32] == 2'd3 && + wci_2_reqPend == 2'd3) + $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-ERR", v__h21713); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_3 && - wci_wciResponse_3$wget[33:32] == 2'd0 && - !wci_respTimr_3_22_ULT_1_SL_wci_wTimeout_3_23_24___d5832 && - wci_reqPend_3 == 2'd1) + if (WILL_FIRE_RL_wci_3_wrkBusy && + wci_3_wciResponse$wget[33:32] == 2'd0 && + !wci_3_respTimr_48_ULT_1_SL_wci_3_wTimeout_49_50___d651 && + wci_3_reqPend == 2'd1) begin - v__h24438 = $time; + v__h25092 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_3 && - wci_wciResponse_3$wget[33:32] == 2'd0 && - !wci_respTimr_3_22_ULT_1_SL_wci_wTimeout_3_23_24___d5832 && - wci_reqPend_3 == 2'd1) - $display("[%0d]: %m: WORKER CONFIG-WRITE TIMEOUT", v__h24438); + if (WILL_FIRE_RL_wci_3_wrkBusy && + wci_3_wciResponse$wget[33:32] == 2'd0 && + !wci_3_respTimr_48_ULT_1_SL_wci_3_wTimeout_49_50___d651 && + wci_3_reqPend == 2'd1) + $display("[%0d]: %m: WORKER CONFIG-WRITE TIMEOUT", v__h25092); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_3 && - wci_wciResponse_3$wget[33:32] == 2'd0 && - !wci_respTimr_3_22_ULT_1_SL_wci_wTimeout_3_23_24___d5832 && - wci_reqPend_3 == 2'd2) + if (WILL_FIRE_RL_wci_3_wrkBusy && + wci_3_wciResponse$wget[33:32] == 2'd0 && + !wci_3_respTimr_48_ULT_1_SL_wci_3_wTimeout_49_50___d651 && + wci_3_reqPend == 2'd2) begin - v__h24528 = $time; + v__h25182 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_3 && - wci_wciResponse_3$wget[33:32] == 2'd0 && - !wci_respTimr_3_22_ULT_1_SL_wci_wTimeout_3_23_24___d5832 && - wci_reqPend_3 == 2'd2) - $display("[%0d]: %m: WORKER CONFIG-READ TIMEOUT", v__h24528); + if (WILL_FIRE_RL_wci_3_wrkBusy && + wci_3_wciResponse$wget[33:32] == 2'd0 && + !wci_3_respTimr_48_ULT_1_SL_wci_3_wTimeout_49_50___d651 && + wci_3_reqPend == 2'd2) + $display("[%0d]: %m: WORKER CONFIG-READ TIMEOUT", v__h25182); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_3 && - wci_wciResponse_3$wget[33:32] == 2'd0 && - !wci_respTimr_3_22_ULT_1_SL_wci_wTimeout_3_23_24___d5832 && - wci_reqPend_3 == 2'd3) + if (WILL_FIRE_RL_wci_3_wrkBusy && + wci_3_wciResponse$wget[33:32] == 2'd0 && + !wci_3_respTimr_48_ULT_1_SL_wci_3_wTimeout_49_50___d651 && + wci_3_reqPend == 2'd3) begin - v__h24617 = $time; + v__h25271 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_3 && - wci_wciResponse_3$wget[33:32] == 2'd0 && - !wci_respTimr_3_22_ULT_1_SL_wci_wTimeout_3_23_24___d5832 && - wci_reqPend_3 == 2'd3) - $display("[%0d]: %m: WORKER CONTROL-OP TIMEOUT", v__h24617); + if (WILL_FIRE_RL_wci_3_wrkBusy && + wci_3_wciResponse$wget[33:32] == 2'd0 && + !wci_3_respTimr_48_ULT_1_SL_wci_3_wTimeout_49_50___d651 && + wci_3_reqPend == 2'd3) + $display("[%0d]: %m: WORKER CONTROL-OP TIMEOUT", v__h25271); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_3 && - wci_wciResponse_3$wget[33:32] == 2'd2 && - wci_reqPend_3 == 2'd1) + if (WILL_FIRE_RL_wci_3_wrkBusy && + wci_3_wciResponse$wget[33:32] == 2'd2 && + wci_3_reqPend == 2'd1) begin - v__h24841 = $time; + v__h25495 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_3 && - wci_wciResponse_3$wget[33:32] == 2'd2 && - wci_reqPend_3 == 2'd1) - $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-FAIL", v__h24841); + if (WILL_FIRE_RL_wci_3_wrkBusy && + wci_3_wciResponse$wget[33:32] == 2'd2 && + wci_3_reqPend == 2'd1) + $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-FAIL", v__h25495); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_3 && - wci_wciResponse_3$wget[33:32] == 2'd2 && - wci_reqPend_3 == 2'd2) + if (WILL_FIRE_RL_wci_3_wrkBusy && + wci_3_wciResponse$wget[33:32] == 2'd2 && + wci_3_reqPend == 2'd2) begin - v__h24931 = $time; + v__h25585 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_3 && - wci_wciResponse_3$wget[33:32] == 2'd2 && - wci_reqPend_3 == 2'd2) - $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-FAIL", v__h24931); + if (WILL_FIRE_RL_wci_3_wrkBusy && + wci_3_wciResponse$wget[33:32] == 2'd2 && + wci_3_reqPend == 2'd2) + $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-FAIL", v__h25585); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_3 && - wci_wciResponse_3$wget[33:32] == 2'd2 && - wci_reqPend_3 == 2'd3) + if (WILL_FIRE_RL_wci_3_wrkBusy && + wci_3_wciResponse$wget[33:32] == 2'd2 && + wci_3_reqPend == 2'd3) begin - v__h25020 = $time; + v__h25674 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_3 && - wci_wciResponse_3$wget[33:32] == 2'd2 && - wci_reqPend_3 == 2'd3) - $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-FAIL", v__h25020); + if (WILL_FIRE_RL_wci_3_wrkBusy && + wci_3_wciResponse$wget[33:32] == 2'd2 && + wci_3_reqPend == 2'd3) + $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-FAIL", v__h25674); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_3 && - wci_wciResponse_3$wget[33:32] == 2'd3 && - wci_reqPend_3 == 2'd1) + if (WILL_FIRE_RL_wci_3_wrkBusy && + wci_3_wciResponse$wget[33:32] == 2'd3 && + wci_3_reqPend == 2'd1) begin - v__h25249 = $time; + v__h25903 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_3 && - wci_wciResponse_3$wget[33:32] == 2'd3 && - wci_reqPend_3 == 2'd1) - $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-ERR", v__h25249); + if (WILL_FIRE_RL_wci_3_wrkBusy && + wci_3_wciResponse$wget[33:32] == 2'd3 && + wci_3_reqPend == 2'd1) + $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-ERR", v__h25903); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_3 && - wci_wciResponse_3$wget[33:32] == 2'd3 && - wci_reqPend_3 == 2'd2) + if (WILL_FIRE_RL_wci_3_wrkBusy && + wci_3_wciResponse$wget[33:32] == 2'd3 && + wci_3_reqPend == 2'd2) begin - v__h25339 = $time; + v__h25993 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_3 && - wci_wciResponse_3$wget[33:32] == 2'd3 && - wci_reqPend_3 == 2'd2) - $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-ERR", v__h25339); + if (WILL_FIRE_RL_wci_3_wrkBusy && + wci_3_wciResponse$wget[33:32] == 2'd3 && + wci_3_reqPend == 2'd2) + $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-ERR", v__h25993); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_3 && - wci_wciResponse_3$wget[33:32] == 2'd3 && - wci_reqPend_3 == 2'd3) + if (WILL_FIRE_RL_wci_3_wrkBusy && + wci_3_wciResponse$wget[33:32] == 2'd3 && + wci_3_reqPend == 2'd3) begin - v__h25428 = $time; + v__h26082 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_3 && - wci_wciResponse_3$wget[33:32] == 2'd3 && - wci_reqPend_3 == 2'd3) - $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-ERR", v__h25428); + if (WILL_FIRE_RL_wci_3_wrkBusy && + wci_3_wciResponse$wget[33:32] == 2'd3 && + wci_3_reqPend == 2'd3) + $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-ERR", v__h26082); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_4 && - wci_wciResponse_4$wget[33:32] == 2'd0 && - !wci_respTimr_4_62_ULT_1_SL_wci_wTimeout_4_63_64___d5833 && - wci_reqPend_4 == 2'd1) + if (WILL_FIRE_RL_wci_4_wrkBusy && + wci_4_wciResponse$wget[33:32] == 2'd0 && + !wci_4_respTimr_88_ULT_1_SL_wci_4_wTimeout_89_90___d791 && + wci_4_reqPend == 2'd1) begin - v__h28878 = $time; + v__h29461 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_4 && - wci_wciResponse_4$wget[33:32] == 2'd0 && - !wci_respTimr_4_62_ULT_1_SL_wci_wTimeout_4_63_64___d5833 && - wci_reqPend_4 == 2'd1) - $display("[%0d]: %m: WORKER CONFIG-WRITE TIMEOUT", v__h28878); + if (WILL_FIRE_RL_wci_4_wrkBusy && + wci_4_wciResponse$wget[33:32] == 2'd0 && + !wci_4_respTimr_88_ULT_1_SL_wci_4_wTimeout_89_90___d791 && + wci_4_reqPend == 2'd1) + $display("[%0d]: %m: WORKER CONFIG-WRITE TIMEOUT", v__h29461); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_4 && - wci_wciResponse_4$wget[33:32] == 2'd0 && - !wci_respTimr_4_62_ULT_1_SL_wci_wTimeout_4_63_64___d5833 && - wci_reqPend_4 == 2'd2) + if (WILL_FIRE_RL_wci_4_wrkBusy && + wci_4_wciResponse$wget[33:32] == 2'd0 && + !wci_4_respTimr_88_ULT_1_SL_wci_4_wTimeout_89_90___d791 && + wci_4_reqPend == 2'd2) begin - v__h28968 = $time; + v__h29551 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_4 && - wci_wciResponse_4$wget[33:32] == 2'd0 && - !wci_respTimr_4_62_ULT_1_SL_wci_wTimeout_4_63_64___d5833 && - wci_reqPend_4 == 2'd2) - $display("[%0d]: %m: WORKER CONFIG-READ TIMEOUT", v__h28968); + if (WILL_FIRE_RL_wci_4_wrkBusy && + wci_4_wciResponse$wget[33:32] == 2'd0 && + !wci_4_respTimr_88_ULT_1_SL_wci_4_wTimeout_89_90___d791 && + wci_4_reqPend == 2'd2) + $display("[%0d]: %m: WORKER CONFIG-READ TIMEOUT", v__h29551); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_4 && - wci_wciResponse_4$wget[33:32] == 2'd0 && - !wci_respTimr_4_62_ULT_1_SL_wci_wTimeout_4_63_64___d5833 && - wci_reqPend_4 == 2'd3) + if (WILL_FIRE_RL_wci_4_wrkBusy && + wci_4_wciResponse$wget[33:32] == 2'd0 && + !wci_4_respTimr_88_ULT_1_SL_wci_4_wTimeout_89_90___d791 && + wci_4_reqPend == 2'd3) begin - v__h29057 = $time; + v__h29640 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_4 && - wci_wciResponse_4$wget[33:32] == 2'd0 && - !wci_respTimr_4_62_ULT_1_SL_wci_wTimeout_4_63_64___d5833 && - wci_reqPend_4 == 2'd3) - $display("[%0d]: %m: WORKER CONTROL-OP TIMEOUT", v__h29057); + if (WILL_FIRE_RL_wci_4_wrkBusy && + wci_4_wciResponse$wget[33:32] == 2'd0 && + !wci_4_respTimr_88_ULT_1_SL_wci_4_wTimeout_89_90___d791 && + wci_4_reqPend == 2'd3) + $display("[%0d]: %m: WORKER CONTROL-OP TIMEOUT", v__h29640); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_4 && - wci_wciResponse_4$wget[33:32] == 2'd2 && - wci_reqPend_4 == 2'd1) + if (WILL_FIRE_RL_wci_4_wrkBusy && + wci_4_wciResponse$wget[33:32] == 2'd2 && + wci_4_reqPend == 2'd1) begin - v__h29281 = $time; + v__h29864 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_4 && - wci_wciResponse_4$wget[33:32] == 2'd2 && - wci_reqPend_4 == 2'd1) - $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-FAIL", v__h29281); + if (WILL_FIRE_RL_wci_4_wrkBusy && + wci_4_wciResponse$wget[33:32] == 2'd2 && + wci_4_reqPend == 2'd1) + $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-FAIL", v__h29864); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_4 && - wci_wciResponse_4$wget[33:32] == 2'd2 && - wci_reqPend_4 == 2'd2) + if (WILL_FIRE_RL_wci_4_wrkBusy && + wci_4_wciResponse$wget[33:32] == 2'd2 && + wci_4_reqPend == 2'd2) begin - v__h29371 = $time; + v__h29954 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_4 && - wci_wciResponse_4$wget[33:32] == 2'd2 && - wci_reqPend_4 == 2'd2) - $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-FAIL", v__h29371); + if (WILL_FIRE_RL_wci_4_wrkBusy && + wci_4_wciResponse$wget[33:32] == 2'd2 && + wci_4_reqPend == 2'd2) + $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-FAIL", v__h29954); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_4 && - wci_wciResponse_4$wget[33:32] == 2'd2 && - wci_reqPend_4 == 2'd3) + if (WILL_FIRE_RL_wci_4_wrkBusy && + wci_4_wciResponse$wget[33:32] == 2'd2 && + wci_4_reqPend == 2'd3) begin - v__h29460 = $time; + v__h30043 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_4 && - wci_wciResponse_4$wget[33:32] == 2'd2 && - wci_reqPend_4 == 2'd3) - $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-FAIL", v__h29460); + if (WILL_FIRE_RL_wci_4_wrkBusy && + wci_4_wciResponse$wget[33:32] == 2'd2 && + wci_4_reqPend == 2'd3) + $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-FAIL", v__h30043); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_4 && - wci_wciResponse_4$wget[33:32] == 2'd3 && - wci_reqPend_4 == 2'd1) + if (WILL_FIRE_RL_wci_4_wrkBusy && + wci_4_wciResponse$wget[33:32] == 2'd3 && + wci_4_reqPend == 2'd1) begin - v__h29689 = $time; + v__h30272 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_4 && - wci_wciResponse_4$wget[33:32] == 2'd3 && - wci_reqPend_4 == 2'd1) - $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-ERR", v__h29689); + if (WILL_FIRE_RL_wci_4_wrkBusy && + wci_4_wciResponse$wget[33:32] == 2'd3 && + wci_4_reqPend == 2'd1) + $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-ERR", v__h30272); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_4 && - wci_wciResponse_4$wget[33:32] == 2'd3 && - wci_reqPend_4 == 2'd2) + if (WILL_FIRE_RL_wci_4_wrkBusy && + wci_4_wciResponse$wget[33:32] == 2'd3 && + wci_4_reqPend == 2'd2) begin - v__h29779 = $time; + v__h30362 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_4 && - wci_wciResponse_4$wget[33:32] == 2'd3 && - wci_reqPend_4 == 2'd2) - $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-ERR", v__h29779); + if (WILL_FIRE_RL_wci_4_wrkBusy && + wci_4_wciResponse$wget[33:32] == 2'd3 && + wci_4_reqPend == 2'd2) + $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-ERR", v__h30362); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_4 && - wci_wciResponse_4$wget[33:32] == 2'd3 && - wci_reqPend_4 == 2'd3) + if (WILL_FIRE_RL_wci_4_wrkBusy && + wci_4_wciResponse$wget[33:32] == 2'd3 && + wci_4_reqPend == 2'd3) begin - v__h29868 = $time; + v__h30451 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_4 && - wci_wciResponse_4$wget[33:32] == 2'd3 && - wci_reqPend_4 == 2'd3) - $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-ERR", v__h29868); + if (WILL_FIRE_RL_wci_4_wrkBusy && + wci_4_wciResponse$wget[33:32] == 2'd3 && + wci_4_reqPend == 2'd3) + $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-ERR", v__h30451); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_5 && - wci_wciResponse_5$wget[33:32] == 2'd0 && - !wci_respTimr_5_02_ULT_1_SL_wci_wTimeout_5_03_04___d5834 && - wci_reqPend_5 == 2'd1) + if (WILL_FIRE_RL_wci_5_wrkBusy && + wci_5_wciResponse$wget[33:32] == 2'd0 && + !wci_5_respTimr_28_ULT_1_SL_wci_5_wTimeout_29_30___d931 && + wci_5_reqPend == 2'd1) begin - v__h33318 = $time; + v__h33830 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_5 && - wci_wciResponse_5$wget[33:32] == 2'd0 && - !wci_respTimr_5_02_ULT_1_SL_wci_wTimeout_5_03_04___d5834 && - wci_reqPend_5 == 2'd1) - $display("[%0d]: %m: WORKER CONFIG-WRITE TIMEOUT", v__h33318); + if (WILL_FIRE_RL_wci_5_wrkBusy && + wci_5_wciResponse$wget[33:32] == 2'd0 && + !wci_5_respTimr_28_ULT_1_SL_wci_5_wTimeout_29_30___d931 && + wci_5_reqPend == 2'd1) + $display("[%0d]: %m: WORKER CONFIG-WRITE TIMEOUT", v__h33830); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_5 && - wci_wciResponse_5$wget[33:32] == 2'd0 && - !wci_respTimr_5_02_ULT_1_SL_wci_wTimeout_5_03_04___d5834 && - wci_reqPend_5 == 2'd2) + if (WILL_FIRE_RL_wci_5_wrkBusy && + wci_5_wciResponse$wget[33:32] == 2'd0 && + !wci_5_respTimr_28_ULT_1_SL_wci_5_wTimeout_29_30___d931 && + wci_5_reqPend == 2'd2) begin - v__h33408 = $time; + v__h33920 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_5 && - wci_wciResponse_5$wget[33:32] == 2'd0 && - !wci_respTimr_5_02_ULT_1_SL_wci_wTimeout_5_03_04___d5834 && - wci_reqPend_5 == 2'd2) - $display("[%0d]: %m: WORKER CONFIG-READ TIMEOUT", v__h33408); + if (WILL_FIRE_RL_wci_5_wrkBusy && + wci_5_wciResponse$wget[33:32] == 2'd0 && + !wci_5_respTimr_28_ULT_1_SL_wci_5_wTimeout_29_30___d931 && + wci_5_reqPend == 2'd2) + $display("[%0d]: %m: WORKER CONFIG-READ TIMEOUT", v__h33920); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_5 && - wci_wciResponse_5$wget[33:32] == 2'd0 && - !wci_respTimr_5_02_ULT_1_SL_wci_wTimeout_5_03_04___d5834 && - wci_reqPend_5 == 2'd3) + if (WILL_FIRE_RL_wci_5_wrkBusy && + wci_5_wciResponse$wget[33:32] == 2'd0 && + !wci_5_respTimr_28_ULT_1_SL_wci_5_wTimeout_29_30___d931 && + wci_5_reqPend == 2'd3) begin - v__h33497 = $time; + v__h34009 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_5 && - wci_wciResponse_5$wget[33:32] == 2'd0 && - !wci_respTimr_5_02_ULT_1_SL_wci_wTimeout_5_03_04___d5834 && - wci_reqPend_5 == 2'd3) - $display("[%0d]: %m: WORKER CONTROL-OP TIMEOUT", v__h33497); + if (WILL_FIRE_RL_wci_5_wrkBusy && + wci_5_wciResponse$wget[33:32] == 2'd0 && + !wci_5_respTimr_28_ULT_1_SL_wci_5_wTimeout_29_30___d931 && + wci_5_reqPend == 2'd3) + $display("[%0d]: %m: WORKER CONTROL-OP TIMEOUT", v__h34009); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_5 && - wci_wciResponse_5$wget[33:32] == 2'd2 && - wci_reqPend_5 == 2'd1) + if (WILL_FIRE_RL_wci_5_wrkBusy && + wci_5_wciResponse$wget[33:32] == 2'd2 && + wci_5_reqPend == 2'd1) begin - v__h33721 = $time; + v__h34233 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_5 && - wci_wciResponse_5$wget[33:32] == 2'd2 && - wci_reqPend_5 == 2'd1) - $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-FAIL", v__h33721); + if (WILL_FIRE_RL_wci_5_wrkBusy && + wci_5_wciResponse$wget[33:32] == 2'd2 && + wci_5_reqPend == 2'd1) + $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-FAIL", v__h34233); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_5 && - wci_wciResponse_5$wget[33:32] == 2'd2 && - wci_reqPend_5 == 2'd2) + if (WILL_FIRE_RL_wci_5_wrkBusy && + wci_5_wciResponse$wget[33:32] == 2'd2 && + wci_5_reqPend == 2'd2) begin - v__h33811 = $time; + v__h34323 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_5 && - wci_wciResponse_5$wget[33:32] == 2'd2 && - wci_reqPend_5 == 2'd2) - $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-FAIL", v__h33811); + if (WILL_FIRE_RL_wci_5_wrkBusy && + wci_5_wciResponse$wget[33:32] == 2'd2 && + wci_5_reqPend == 2'd2) + $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-FAIL", v__h34323); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_5 && - wci_wciResponse_5$wget[33:32] == 2'd2 && - wci_reqPend_5 == 2'd3) + if (WILL_FIRE_RL_wci_5_wrkBusy && + wci_5_wciResponse$wget[33:32] == 2'd2 && + wci_5_reqPend == 2'd3) begin - v__h33900 = $time; + v__h34412 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_5 && - wci_wciResponse_5$wget[33:32] == 2'd2 && - wci_reqPend_5 == 2'd3) - $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-FAIL", v__h33900); + if (WILL_FIRE_RL_wci_5_wrkBusy && + wci_5_wciResponse$wget[33:32] == 2'd2 && + wci_5_reqPend == 2'd3) + $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-FAIL", v__h34412); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_5 && - wci_wciResponse_5$wget[33:32] == 2'd3 && - wci_reqPend_5 == 2'd1) + if (WILL_FIRE_RL_wci_5_wrkBusy && + wci_5_wciResponse$wget[33:32] == 2'd3 && + wci_5_reqPend == 2'd1) begin - v__h34129 = $time; + v__h34641 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_5 && - wci_wciResponse_5$wget[33:32] == 2'd3 && - wci_reqPend_5 == 2'd1) - $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-ERR", v__h34129); + if (WILL_FIRE_RL_wci_5_wrkBusy && + wci_5_wciResponse$wget[33:32] == 2'd3 && + wci_5_reqPend == 2'd1) + $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-ERR", v__h34641); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_5 && - wci_wciResponse_5$wget[33:32] == 2'd3 && - wci_reqPend_5 == 2'd2) + if (WILL_FIRE_RL_wci_5_wrkBusy && + wci_5_wciResponse$wget[33:32] == 2'd3 && + wci_5_reqPend == 2'd2) begin - v__h34219 = $time; + v__h34731 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_5 && - wci_wciResponse_5$wget[33:32] == 2'd3 && - wci_reqPend_5 == 2'd2) - $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-ERR", v__h34219); + if (WILL_FIRE_RL_wci_5_wrkBusy && + wci_5_wciResponse$wget[33:32] == 2'd3 && + wci_5_reqPend == 2'd2) + $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-ERR", v__h34731); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_5 && - wci_wciResponse_5$wget[33:32] == 2'd3 && - wci_reqPend_5 == 2'd3) + if (WILL_FIRE_RL_wci_5_wrkBusy && + wci_5_wciResponse$wget[33:32] == 2'd3 && + wci_5_reqPend == 2'd3) begin - v__h34308 = $time; + v__h34820 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_5 && - wci_wciResponse_5$wget[33:32] == 2'd3 && - wci_reqPend_5 == 2'd3) - $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-ERR", v__h34308); + if (WILL_FIRE_RL_wci_5_wrkBusy && + wci_5_wciResponse$wget[33:32] == 2'd3 && + wci_5_reqPend == 2'd3) + $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-ERR", v__h34820); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_6 && - wci_wciResponse_6$wget[33:32] == 2'd0 && - !wci_respTimr_6_042_ULT_1_SL_wci_wTimeout_6_043_ETC___d5835 && - wci_reqPend_6 == 2'd1) + if (WILL_FIRE_RL_wci_6_wrkBusy && + wci_6_wciResponse$wget[33:32] == 2'd0 && + !wci_6_respTimr_068_ULT_1_SL_wci_6_wTimeout_069_ETC___d1071 && + wci_6_reqPend == 2'd1) begin - v__h37758 = $time; + v__h38199 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_6 && - wci_wciResponse_6$wget[33:32] == 2'd0 && - !wci_respTimr_6_042_ULT_1_SL_wci_wTimeout_6_043_ETC___d5835 && - wci_reqPend_6 == 2'd1) - $display("[%0d]: %m: WORKER CONFIG-WRITE TIMEOUT", v__h37758); + if (WILL_FIRE_RL_wci_6_wrkBusy && + wci_6_wciResponse$wget[33:32] == 2'd0 && + !wci_6_respTimr_068_ULT_1_SL_wci_6_wTimeout_069_ETC___d1071 && + wci_6_reqPend == 2'd1) + $display("[%0d]: %m: WORKER CONFIG-WRITE TIMEOUT", v__h38199); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_6 && - wci_wciResponse_6$wget[33:32] == 2'd0 && - !wci_respTimr_6_042_ULT_1_SL_wci_wTimeout_6_043_ETC___d5835 && - wci_reqPend_6 == 2'd2) + if (WILL_FIRE_RL_wci_6_wrkBusy && + wci_6_wciResponse$wget[33:32] == 2'd0 && + !wci_6_respTimr_068_ULT_1_SL_wci_6_wTimeout_069_ETC___d1071 && + wci_6_reqPend == 2'd2) begin - v__h37848 = $time; + v__h38289 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_6 && - wci_wciResponse_6$wget[33:32] == 2'd0 && - !wci_respTimr_6_042_ULT_1_SL_wci_wTimeout_6_043_ETC___d5835 && - wci_reqPend_6 == 2'd2) - $display("[%0d]: %m: WORKER CONFIG-READ TIMEOUT", v__h37848); + if (WILL_FIRE_RL_wci_6_wrkBusy && + wci_6_wciResponse$wget[33:32] == 2'd0 && + !wci_6_respTimr_068_ULT_1_SL_wci_6_wTimeout_069_ETC___d1071 && + wci_6_reqPend == 2'd2) + $display("[%0d]: %m: WORKER CONFIG-READ TIMEOUT", v__h38289); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_6 && - wci_wciResponse_6$wget[33:32] == 2'd0 && - !wci_respTimr_6_042_ULT_1_SL_wci_wTimeout_6_043_ETC___d5835 && - wci_reqPend_6 == 2'd3) + if (WILL_FIRE_RL_wci_6_wrkBusy && + wci_6_wciResponse$wget[33:32] == 2'd0 && + !wci_6_respTimr_068_ULT_1_SL_wci_6_wTimeout_069_ETC___d1071 && + wci_6_reqPend == 2'd3) begin - v__h37937 = $time; + v__h38378 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_6 && - wci_wciResponse_6$wget[33:32] == 2'd0 && - !wci_respTimr_6_042_ULT_1_SL_wci_wTimeout_6_043_ETC___d5835 && - wci_reqPend_6 == 2'd3) - $display("[%0d]: %m: WORKER CONTROL-OP TIMEOUT", v__h37937); + if (WILL_FIRE_RL_wci_6_wrkBusy && + wci_6_wciResponse$wget[33:32] == 2'd0 && + !wci_6_respTimr_068_ULT_1_SL_wci_6_wTimeout_069_ETC___d1071 && + wci_6_reqPend == 2'd3) + $display("[%0d]: %m: WORKER CONTROL-OP TIMEOUT", v__h38378); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_6 && - wci_wciResponse_6$wget[33:32] == 2'd2 && - wci_reqPend_6 == 2'd1) + if (WILL_FIRE_RL_wci_6_wrkBusy && + wci_6_wciResponse$wget[33:32] == 2'd2 && + wci_6_reqPend == 2'd1) begin - v__h38161 = $time; + v__h38602 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_6 && - wci_wciResponse_6$wget[33:32] == 2'd2 && - wci_reqPend_6 == 2'd1) - $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-FAIL", v__h38161); + if (WILL_FIRE_RL_wci_6_wrkBusy && + wci_6_wciResponse$wget[33:32] == 2'd2 && + wci_6_reqPend == 2'd1) + $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-FAIL", v__h38602); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_6 && - wci_wciResponse_6$wget[33:32] == 2'd2 && - wci_reqPend_6 == 2'd2) + if (WILL_FIRE_RL_wci_6_wrkBusy && + wci_6_wciResponse$wget[33:32] == 2'd2 && + wci_6_reqPend == 2'd2) begin - v__h38251 = $time; + v__h38692 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_6 && - wci_wciResponse_6$wget[33:32] == 2'd2 && - wci_reqPend_6 == 2'd2) - $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-FAIL", v__h38251); + if (WILL_FIRE_RL_wci_6_wrkBusy && + wci_6_wciResponse$wget[33:32] == 2'd2 && + wci_6_reqPend == 2'd2) + $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-FAIL", v__h38692); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_6 && - wci_wciResponse_6$wget[33:32] == 2'd2 && - wci_reqPend_6 == 2'd3) + if (WILL_FIRE_RL_wci_6_wrkBusy && + wci_6_wciResponse$wget[33:32] == 2'd2 && + wci_6_reqPend == 2'd3) begin - v__h38340 = $time; + v__h38781 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_6 && - wci_wciResponse_6$wget[33:32] == 2'd2 && - wci_reqPend_6 == 2'd3) - $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-FAIL", v__h38340); + if (WILL_FIRE_RL_wci_6_wrkBusy && + wci_6_wciResponse$wget[33:32] == 2'd2 && + wci_6_reqPend == 2'd3) + $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-FAIL", v__h38781); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_6 && - wci_wciResponse_6$wget[33:32] == 2'd3 && - wci_reqPend_6 == 2'd1) + if (WILL_FIRE_RL_wci_6_wrkBusy && + wci_6_wciResponse$wget[33:32] == 2'd3 && + wci_6_reqPend == 2'd1) begin - v__h38569 = $time; + v__h39010 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_6 && - wci_wciResponse_6$wget[33:32] == 2'd3 && - wci_reqPend_6 == 2'd1) - $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-ERR", v__h38569); + if (WILL_FIRE_RL_wci_6_wrkBusy && + wci_6_wciResponse$wget[33:32] == 2'd3 && + wci_6_reqPend == 2'd1) + $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-ERR", v__h39010); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_6 && - wci_wciResponse_6$wget[33:32] == 2'd3 && - wci_reqPend_6 == 2'd2) + if (WILL_FIRE_RL_wci_6_wrkBusy && + wci_6_wciResponse$wget[33:32] == 2'd3 && + wci_6_reqPend == 2'd2) begin - v__h38659 = $time; + v__h39100 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_6 && - wci_wciResponse_6$wget[33:32] == 2'd3 && - wci_reqPend_6 == 2'd2) - $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-ERR", v__h38659); + if (WILL_FIRE_RL_wci_6_wrkBusy && + wci_6_wciResponse$wget[33:32] == 2'd3 && + wci_6_reqPend == 2'd2) + $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-ERR", v__h39100); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_6 && - wci_wciResponse_6$wget[33:32] == 2'd3 && - wci_reqPend_6 == 2'd3) + if (WILL_FIRE_RL_wci_6_wrkBusy && + wci_6_wciResponse$wget[33:32] == 2'd3 && + wci_6_reqPend == 2'd3) begin - v__h38748 = $time; + v__h39189 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_6 && - wci_wciResponse_6$wget[33:32] == 2'd3 && - wci_reqPend_6 == 2'd3) - $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-ERR", v__h38748); + if (WILL_FIRE_RL_wci_6_wrkBusy && + wci_6_wciResponse$wget[33:32] == 2'd3 && + wci_6_reqPend == 2'd3) + $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-ERR", v__h39189); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_7 && - wci_wciResponse_7$wget[33:32] == 2'd0 && - !wci_respTimr_7_182_ULT_1_SL_wci_wTimeout_7_183_ETC___d5836 && - wci_reqPend_7 == 2'd1) + if (WILL_FIRE_RL_wci_7_wrkBusy && + wci_7_wciResponse$wget[33:32] == 2'd0 && + !wci_7_respTimr_208_ULT_1_SL_wci_7_wTimeout_209_ETC___d1211 && + wci_7_reqPend == 2'd1) begin - v__h42198 = $time; + v__h42568 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_7 && - wci_wciResponse_7$wget[33:32] == 2'd0 && - !wci_respTimr_7_182_ULT_1_SL_wci_wTimeout_7_183_ETC___d5836 && - wci_reqPend_7 == 2'd1) - $display("[%0d]: %m: WORKER CONFIG-WRITE TIMEOUT", v__h42198); + if (WILL_FIRE_RL_wci_7_wrkBusy && + wci_7_wciResponse$wget[33:32] == 2'd0 && + !wci_7_respTimr_208_ULT_1_SL_wci_7_wTimeout_209_ETC___d1211 && + wci_7_reqPend == 2'd1) + $display("[%0d]: %m: WORKER CONFIG-WRITE TIMEOUT", v__h42568); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_7 && - wci_wciResponse_7$wget[33:32] == 2'd0 && - !wci_respTimr_7_182_ULT_1_SL_wci_wTimeout_7_183_ETC___d5836 && - wci_reqPend_7 == 2'd2) + if (WILL_FIRE_RL_wci_7_wrkBusy && + wci_7_wciResponse$wget[33:32] == 2'd0 && + !wci_7_respTimr_208_ULT_1_SL_wci_7_wTimeout_209_ETC___d1211 && + wci_7_reqPend == 2'd2) begin - v__h42288 = $time; + v__h42658 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_7 && - wci_wciResponse_7$wget[33:32] == 2'd0 && - !wci_respTimr_7_182_ULT_1_SL_wci_wTimeout_7_183_ETC___d5836 && - wci_reqPend_7 == 2'd2) - $display("[%0d]: %m: WORKER CONFIG-READ TIMEOUT", v__h42288); + if (WILL_FIRE_RL_wci_7_wrkBusy && + wci_7_wciResponse$wget[33:32] == 2'd0 && + !wci_7_respTimr_208_ULT_1_SL_wci_7_wTimeout_209_ETC___d1211 && + wci_7_reqPend == 2'd2) + $display("[%0d]: %m: WORKER CONFIG-READ TIMEOUT", v__h42658); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_7 && - wci_wciResponse_7$wget[33:32] == 2'd0 && - !wci_respTimr_7_182_ULT_1_SL_wci_wTimeout_7_183_ETC___d5836 && - wci_reqPend_7 == 2'd3) + if (WILL_FIRE_RL_wci_7_wrkBusy && + wci_7_wciResponse$wget[33:32] == 2'd0 && + !wci_7_respTimr_208_ULT_1_SL_wci_7_wTimeout_209_ETC___d1211 && + wci_7_reqPend == 2'd3) begin - v__h42377 = $time; + v__h42747 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_7 && - wci_wciResponse_7$wget[33:32] == 2'd0 && - !wci_respTimr_7_182_ULT_1_SL_wci_wTimeout_7_183_ETC___d5836 && - wci_reqPend_7 == 2'd3) - $display("[%0d]: %m: WORKER CONTROL-OP TIMEOUT", v__h42377); + if (WILL_FIRE_RL_wci_7_wrkBusy && + wci_7_wciResponse$wget[33:32] == 2'd0 && + !wci_7_respTimr_208_ULT_1_SL_wci_7_wTimeout_209_ETC___d1211 && + wci_7_reqPend == 2'd3) + $display("[%0d]: %m: WORKER CONTROL-OP TIMEOUT", v__h42747); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_7 && - wci_wciResponse_7$wget[33:32] == 2'd2 && - wci_reqPend_7 == 2'd1) + if (WILL_FIRE_RL_wci_7_wrkBusy && + wci_7_wciResponse$wget[33:32] == 2'd2 && + wci_7_reqPend == 2'd1) begin - v__h42601 = $time; + v__h42971 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_7 && - wci_wciResponse_7$wget[33:32] == 2'd2 && - wci_reqPend_7 == 2'd1) - $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-FAIL", v__h42601); + if (WILL_FIRE_RL_wci_7_wrkBusy && + wci_7_wciResponse$wget[33:32] == 2'd2 && + wci_7_reqPend == 2'd1) + $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-FAIL", v__h42971); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_7 && - wci_wciResponse_7$wget[33:32] == 2'd2 && - wci_reqPend_7 == 2'd2) + if (WILL_FIRE_RL_wci_7_wrkBusy && + wci_7_wciResponse$wget[33:32] == 2'd2 && + wci_7_reqPend == 2'd2) begin - v__h42691 = $time; + v__h43061 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_7 && - wci_wciResponse_7$wget[33:32] == 2'd2 && - wci_reqPend_7 == 2'd2) - $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-FAIL", v__h42691); + if (WILL_FIRE_RL_wci_7_wrkBusy && + wci_7_wciResponse$wget[33:32] == 2'd2 && + wci_7_reqPend == 2'd2) + $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-FAIL", v__h43061); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_7 && - wci_wciResponse_7$wget[33:32] == 2'd2 && - wci_reqPend_7 == 2'd3) + if (WILL_FIRE_RL_wci_7_wrkBusy && + wci_7_wciResponse$wget[33:32] == 2'd2 && + wci_7_reqPend == 2'd3) begin - v__h42780 = $time; + v__h43150 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_7 && - wci_wciResponse_7$wget[33:32] == 2'd2 && - wci_reqPend_7 == 2'd3) - $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-FAIL", v__h42780); + if (WILL_FIRE_RL_wci_7_wrkBusy && + wci_7_wciResponse$wget[33:32] == 2'd2 && + wci_7_reqPend == 2'd3) + $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-FAIL", v__h43150); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_7 && - wci_wciResponse_7$wget[33:32] == 2'd3 && - wci_reqPend_7 == 2'd1) + if (WILL_FIRE_RL_wci_7_wrkBusy && + wci_7_wciResponse$wget[33:32] == 2'd3 && + wci_7_reqPend == 2'd1) begin - v__h43009 = $time; + v__h43379 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_7 && - wci_wciResponse_7$wget[33:32] == 2'd3 && - wci_reqPend_7 == 2'd1) - $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-ERR", v__h43009); + if (WILL_FIRE_RL_wci_7_wrkBusy && + wci_7_wciResponse$wget[33:32] == 2'd3 && + wci_7_reqPend == 2'd1) + $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-ERR", v__h43379); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_7 && - wci_wciResponse_7$wget[33:32] == 2'd3 && - wci_reqPend_7 == 2'd2) + if (WILL_FIRE_RL_wci_7_wrkBusy && + wci_7_wciResponse$wget[33:32] == 2'd3 && + wci_7_reqPend == 2'd2) begin - v__h43099 = $time; + v__h43469 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_7 && - wci_wciResponse_7$wget[33:32] == 2'd3 && - wci_reqPend_7 == 2'd2) - $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-ERR", v__h43099); + if (WILL_FIRE_RL_wci_7_wrkBusy && + wci_7_wciResponse$wget[33:32] == 2'd3 && + wci_7_reqPend == 2'd2) + $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-ERR", v__h43469); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_7 && - wci_wciResponse_7$wget[33:32] == 2'd3 && - wci_reqPend_7 == 2'd3) + if (WILL_FIRE_RL_wci_7_wrkBusy && + wci_7_wciResponse$wget[33:32] == 2'd3 && + wci_7_reqPend == 2'd3) begin - v__h43188 = $time; + v__h43558 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_7 && - wci_wciResponse_7$wget[33:32] == 2'd3 && - wci_reqPend_7 == 2'd3) - $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-ERR", v__h43188); + if (WILL_FIRE_RL_wci_7_wrkBusy && + wci_7_wciResponse$wget[33:32] == 2'd3 && + wci_7_reqPend == 2'd3) + $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-ERR", v__h43558); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_8 && - wci_wciResponse_8$wget[33:32] == 2'd0 && - !wci_respTimr_8_322_ULT_1_SL_wci_wTimeout_8_323_ETC___d5837 && - wci_reqPend_8 == 2'd1) + if (WILL_FIRE_RL_wci_8_wrkBusy && + wci_8_wciResponse$wget[33:32] == 2'd0 && + !wci_8_respTimr_348_ULT_1_SL_wci_8_wTimeout_349_ETC___d1351 && + wci_8_reqPend == 2'd1) begin - v__h46638 = $time; + v__h46937 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_8 && - wci_wciResponse_8$wget[33:32] == 2'd0 && - !wci_respTimr_8_322_ULT_1_SL_wci_wTimeout_8_323_ETC___d5837 && - wci_reqPend_8 == 2'd1) - $display("[%0d]: %m: WORKER CONFIG-WRITE TIMEOUT", v__h46638); + if (WILL_FIRE_RL_wci_8_wrkBusy && + wci_8_wciResponse$wget[33:32] == 2'd0 && + !wci_8_respTimr_348_ULT_1_SL_wci_8_wTimeout_349_ETC___d1351 && + wci_8_reqPend == 2'd1) + $display("[%0d]: %m: WORKER CONFIG-WRITE TIMEOUT", v__h46937); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_8 && - wci_wciResponse_8$wget[33:32] == 2'd0 && - !wci_respTimr_8_322_ULT_1_SL_wci_wTimeout_8_323_ETC___d5837 && - wci_reqPend_8 == 2'd2) + if (WILL_FIRE_RL_wci_8_wrkBusy && + wci_8_wciResponse$wget[33:32] == 2'd0 && + !wci_8_respTimr_348_ULT_1_SL_wci_8_wTimeout_349_ETC___d1351 && + wci_8_reqPend == 2'd2) begin - v__h46728 = $time; + v__h47027 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_8 && - wci_wciResponse_8$wget[33:32] == 2'd0 && - !wci_respTimr_8_322_ULT_1_SL_wci_wTimeout_8_323_ETC___d5837 && - wci_reqPend_8 == 2'd2) - $display("[%0d]: %m: WORKER CONFIG-READ TIMEOUT", v__h46728); + if (WILL_FIRE_RL_wci_8_wrkBusy && + wci_8_wciResponse$wget[33:32] == 2'd0 && + !wci_8_respTimr_348_ULT_1_SL_wci_8_wTimeout_349_ETC___d1351 && + wci_8_reqPend == 2'd2) + $display("[%0d]: %m: WORKER CONFIG-READ TIMEOUT", v__h47027); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_8 && - wci_wciResponse_8$wget[33:32] == 2'd0 && - !wci_respTimr_8_322_ULT_1_SL_wci_wTimeout_8_323_ETC___d5837 && - wci_reqPend_8 == 2'd3) + if (WILL_FIRE_RL_wci_8_wrkBusy && + wci_8_wciResponse$wget[33:32] == 2'd0 && + !wci_8_respTimr_348_ULT_1_SL_wci_8_wTimeout_349_ETC___d1351 && + wci_8_reqPend == 2'd3) begin - v__h46817 = $time; + v__h47116 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_8 && - wci_wciResponse_8$wget[33:32] == 2'd0 && - !wci_respTimr_8_322_ULT_1_SL_wci_wTimeout_8_323_ETC___d5837 && - wci_reqPend_8 == 2'd3) - $display("[%0d]: %m: WORKER CONTROL-OP TIMEOUT", v__h46817); + if (WILL_FIRE_RL_wci_8_wrkBusy && + wci_8_wciResponse$wget[33:32] == 2'd0 && + !wci_8_respTimr_348_ULT_1_SL_wci_8_wTimeout_349_ETC___d1351 && + wci_8_reqPend == 2'd3) + $display("[%0d]: %m: WORKER CONTROL-OP TIMEOUT", v__h47116); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_8 && - wci_wciResponse_8$wget[33:32] == 2'd2 && - wci_reqPend_8 == 2'd1) + if (WILL_FIRE_RL_wci_8_wrkBusy && + wci_8_wciResponse$wget[33:32] == 2'd2 && + wci_8_reqPend == 2'd1) begin - v__h47041 = $time; + v__h47340 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_8 && - wci_wciResponse_8$wget[33:32] == 2'd2 && - wci_reqPend_8 == 2'd1) - $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-FAIL", v__h47041); + if (WILL_FIRE_RL_wci_8_wrkBusy && + wci_8_wciResponse$wget[33:32] == 2'd2 && + wci_8_reqPend == 2'd1) + $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-FAIL", v__h47340); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_8 && - wci_wciResponse_8$wget[33:32] == 2'd2 && - wci_reqPend_8 == 2'd2) + if (WILL_FIRE_RL_wci_8_wrkBusy && + wci_8_wciResponse$wget[33:32] == 2'd2 && + wci_8_reqPend == 2'd2) begin - v__h47131 = $time; + v__h47430 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_8 && - wci_wciResponse_8$wget[33:32] == 2'd2 && - wci_reqPend_8 == 2'd2) - $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-FAIL", v__h47131); + if (WILL_FIRE_RL_wci_8_wrkBusy && + wci_8_wciResponse$wget[33:32] == 2'd2 && + wci_8_reqPend == 2'd2) + $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-FAIL", v__h47430); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_8 && - wci_wciResponse_8$wget[33:32] == 2'd2 && - wci_reqPend_8 == 2'd3) + if (WILL_FIRE_RL_wci_8_wrkBusy && + wci_8_wciResponse$wget[33:32] == 2'd2 && + wci_8_reqPend == 2'd3) begin - v__h47220 = $time; + v__h47519 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_8 && - wci_wciResponse_8$wget[33:32] == 2'd2 && - wci_reqPend_8 == 2'd3) - $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-FAIL", v__h47220); + if (WILL_FIRE_RL_wci_8_wrkBusy && + wci_8_wciResponse$wget[33:32] == 2'd2 && + wci_8_reqPend == 2'd3) + $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-FAIL", v__h47519); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_8 && - wci_wciResponse_8$wget[33:32] == 2'd3 && - wci_reqPend_8 == 2'd1) + if (WILL_FIRE_RL_wci_8_wrkBusy && + wci_8_wciResponse$wget[33:32] == 2'd3 && + wci_8_reqPend == 2'd1) begin - v__h47449 = $time; + v__h47748 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_8 && - wci_wciResponse_8$wget[33:32] == 2'd3 && - wci_reqPend_8 == 2'd1) - $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-ERR", v__h47449); + if (WILL_FIRE_RL_wci_8_wrkBusy && + wci_8_wciResponse$wget[33:32] == 2'd3 && + wci_8_reqPend == 2'd1) + $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-ERR", v__h47748); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_8 && - wci_wciResponse_8$wget[33:32] == 2'd3 && - wci_reqPend_8 == 2'd2) + if (WILL_FIRE_RL_wci_8_wrkBusy && + wci_8_wciResponse$wget[33:32] == 2'd3 && + wci_8_reqPend == 2'd2) begin - v__h47539 = $time; + v__h47838 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_8 && - wci_wciResponse_8$wget[33:32] == 2'd3 && - wci_reqPend_8 == 2'd2) - $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-ERR", v__h47539); + if (WILL_FIRE_RL_wci_8_wrkBusy && + wci_8_wciResponse$wget[33:32] == 2'd3 && + wci_8_reqPend == 2'd2) + $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-ERR", v__h47838); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_8 && - wci_wciResponse_8$wget[33:32] == 2'd3 && - wci_reqPend_8 == 2'd3) + if (WILL_FIRE_RL_wci_8_wrkBusy && + wci_8_wciResponse$wget[33:32] == 2'd3 && + wci_8_reqPend == 2'd3) begin - v__h47628 = $time; + v__h47927 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_8 && - wci_wciResponse_8$wget[33:32] == 2'd3 && - wci_reqPend_8 == 2'd3) - $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-ERR", v__h47628); + if (WILL_FIRE_RL_wci_8_wrkBusy && + wci_8_wciResponse$wget[33:32] == 2'd3 && + wci_8_reqPend == 2'd3) + $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-ERR", v__h47927); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_9 && - wci_wciResponse_9$wget[33:32] == 2'd0 && - !wci_respTimr_9_462_ULT_1_SL_wci_wTimeout_9_463_ETC___d5838 && - wci_reqPend_9 == 2'd1) + if (WILL_FIRE_RL_wci_9_wrkBusy && + wci_9_wciResponse$wget[33:32] == 2'd0 && + !wci_9_respTimr_488_ULT_1_SL_wci_9_wTimeout_489_ETC___d1491 && + wci_9_reqPend == 2'd1) begin - v__h51078 = $time; + v__h51306 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_9 && - wci_wciResponse_9$wget[33:32] == 2'd0 && - !wci_respTimr_9_462_ULT_1_SL_wci_wTimeout_9_463_ETC___d5838 && - wci_reqPend_9 == 2'd1) - $display("[%0d]: %m: WORKER CONFIG-WRITE TIMEOUT", v__h51078); + if (WILL_FIRE_RL_wci_9_wrkBusy && + wci_9_wciResponse$wget[33:32] == 2'd0 && + !wci_9_respTimr_488_ULT_1_SL_wci_9_wTimeout_489_ETC___d1491 && + wci_9_reqPend == 2'd1) + $display("[%0d]: %m: WORKER CONFIG-WRITE TIMEOUT", v__h51306); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_9 && - wci_wciResponse_9$wget[33:32] == 2'd0 && - !wci_respTimr_9_462_ULT_1_SL_wci_wTimeout_9_463_ETC___d5838 && - wci_reqPend_9 == 2'd2) + if (WILL_FIRE_RL_wci_9_wrkBusy && + wci_9_wciResponse$wget[33:32] == 2'd0 && + !wci_9_respTimr_488_ULT_1_SL_wci_9_wTimeout_489_ETC___d1491 && + wci_9_reqPend == 2'd2) begin - v__h51168 = $time; + v__h51396 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_9 && - wci_wciResponse_9$wget[33:32] == 2'd0 && - !wci_respTimr_9_462_ULT_1_SL_wci_wTimeout_9_463_ETC___d5838 && - wci_reqPend_9 == 2'd2) - $display("[%0d]: %m: WORKER CONFIG-READ TIMEOUT", v__h51168); + if (WILL_FIRE_RL_wci_9_wrkBusy && + wci_9_wciResponse$wget[33:32] == 2'd0 && + !wci_9_respTimr_488_ULT_1_SL_wci_9_wTimeout_489_ETC___d1491 && + wci_9_reqPend == 2'd2) + $display("[%0d]: %m: WORKER CONFIG-READ TIMEOUT", v__h51396); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_9 && - wci_wciResponse_9$wget[33:32] == 2'd0 && - !wci_respTimr_9_462_ULT_1_SL_wci_wTimeout_9_463_ETC___d5838 && - wci_reqPend_9 == 2'd3) + if (WILL_FIRE_RL_wci_9_wrkBusy && + wci_9_wciResponse$wget[33:32] == 2'd0 && + !wci_9_respTimr_488_ULT_1_SL_wci_9_wTimeout_489_ETC___d1491 && + wci_9_reqPend == 2'd3) begin - v__h51257 = $time; + v__h51485 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_9 && - wci_wciResponse_9$wget[33:32] == 2'd0 && - !wci_respTimr_9_462_ULT_1_SL_wci_wTimeout_9_463_ETC___d5838 && - wci_reqPend_9 == 2'd3) - $display("[%0d]: %m: WORKER CONTROL-OP TIMEOUT", v__h51257); + if (WILL_FIRE_RL_wci_9_wrkBusy && + wci_9_wciResponse$wget[33:32] == 2'd0 && + !wci_9_respTimr_488_ULT_1_SL_wci_9_wTimeout_489_ETC___d1491 && + wci_9_reqPend == 2'd3) + $display("[%0d]: %m: WORKER CONTROL-OP TIMEOUT", v__h51485); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_9 && - wci_wciResponse_9$wget[33:32] == 2'd2 && - wci_reqPend_9 == 2'd1) + if (WILL_FIRE_RL_wci_9_wrkBusy && + wci_9_wciResponse$wget[33:32] == 2'd2 && + wci_9_reqPend == 2'd1) begin - v__h51481 = $time; + v__h51709 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_9 && - wci_wciResponse_9$wget[33:32] == 2'd2 && - wci_reqPend_9 == 2'd1) - $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-FAIL", v__h51481); + if (WILL_FIRE_RL_wci_9_wrkBusy && + wci_9_wciResponse$wget[33:32] == 2'd2 && + wci_9_reqPend == 2'd1) + $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-FAIL", v__h51709); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_9 && - wci_wciResponse_9$wget[33:32] == 2'd2 && - wci_reqPend_9 == 2'd2) + if (WILL_FIRE_RL_wci_9_wrkBusy && + wci_9_wciResponse$wget[33:32] == 2'd2 && + wci_9_reqPend == 2'd2) begin - v__h51571 = $time; + v__h51799 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_9 && - wci_wciResponse_9$wget[33:32] == 2'd2 && - wci_reqPend_9 == 2'd2) - $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-FAIL", v__h51571); + if (WILL_FIRE_RL_wci_9_wrkBusy && + wci_9_wciResponse$wget[33:32] == 2'd2 && + wci_9_reqPend == 2'd2) + $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-FAIL", v__h51799); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_9 && - wci_wciResponse_9$wget[33:32] == 2'd2 && - wci_reqPend_9 == 2'd3) + if (WILL_FIRE_RL_wci_9_wrkBusy && + wci_9_wciResponse$wget[33:32] == 2'd2 && + wci_9_reqPend == 2'd3) begin - v__h51660 = $time; + v__h51888 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_9 && - wci_wciResponse_9$wget[33:32] == 2'd2 && - wci_reqPend_9 == 2'd3) - $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-FAIL", v__h51660); + if (WILL_FIRE_RL_wci_9_wrkBusy && + wci_9_wciResponse$wget[33:32] == 2'd2 && + wci_9_reqPend == 2'd3) + $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-FAIL", v__h51888); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_9 && - wci_wciResponse_9$wget[33:32] == 2'd3 && - wci_reqPend_9 == 2'd1) + if (WILL_FIRE_RL_wci_9_wrkBusy && + wci_9_wciResponse$wget[33:32] == 2'd3 && + wci_9_reqPend == 2'd1) begin - v__h51889 = $time; + v__h52117 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_9 && - wci_wciResponse_9$wget[33:32] == 2'd3 && - wci_reqPend_9 == 2'd1) - $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-ERR", v__h51889); + if (WILL_FIRE_RL_wci_9_wrkBusy && + wci_9_wciResponse$wget[33:32] == 2'd3 && + wci_9_reqPend == 2'd1) + $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-ERR", v__h52117); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_9 && - wci_wciResponse_9$wget[33:32] == 2'd3 && - wci_reqPend_9 == 2'd2) + if (WILL_FIRE_RL_wci_9_wrkBusy && + wci_9_wciResponse$wget[33:32] == 2'd3 && + wci_9_reqPend == 2'd2) begin - v__h51979 = $time; + v__h52207 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_9 && - wci_wciResponse_9$wget[33:32] == 2'd3 && - wci_reqPend_9 == 2'd2) - $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-ERR", v__h51979); + if (WILL_FIRE_RL_wci_9_wrkBusy && + wci_9_wciResponse$wget[33:32] == 2'd3 && + wci_9_reqPend == 2'd2) + $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-ERR", v__h52207); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_9 && - wci_wciResponse_9$wget[33:32] == 2'd3 && - wci_reqPend_9 == 2'd3) + if (WILL_FIRE_RL_wci_9_wrkBusy && + wci_9_wciResponse$wget[33:32] == 2'd3 && + wci_9_reqPend == 2'd3) begin - v__h52068 = $time; + v__h52296 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_9 && - wci_wciResponse_9$wget[33:32] == 2'd3 && - wci_reqPend_9 == 2'd3) - $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-ERR", v__h52068); + if (WILL_FIRE_RL_wci_9_wrkBusy && + wci_9_wciResponse$wget[33:32] == 2'd3 && + wci_9_reqPend == 2'd3) + $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-ERR", v__h52296); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_10 && - wci_wciResponse_10$wget[33:32] == 2'd0 && - !wci_respTimr_10_602_ULT_1_SL_wci_wTimeout_10_6_ETC___d5839 && - wci_reqPend_10 == 2'd1) + if (WILL_FIRE_RL_wci_10_wrkBusy && + wci_10_wciResponse$wget[33:32] == 2'd0 && + !wci_10_respTimr_628_ULT_1_SL_wci_10_wTimeout_6_ETC___d1631 && + wci_10_reqPend == 2'd1) begin - v__h55518 = $time; + v__h55675 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_10 && - wci_wciResponse_10$wget[33:32] == 2'd0 && - !wci_respTimr_10_602_ULT_1_SL_wci_wTimeout_10_6_ETC___d5839 && - wci_reqPend_10 == 2'd1) - $display("[%0d]: %m: WORKER CONFIG-WRITE TIMEOUT", v__h55518); + if (WILL_FIRE_RL_wci_10_wrkBusy && + wci_10_wciResponse$wget[33:32] == 2'd0 && + !wci_10_respTimr_628_ULT_1_SL_wci_10_wTimeout_6_ETC___d1631 && + wci_10_reqPend == 2'd1) + $display("[%0d]: %m: WORKER CONFIG-WRITE TIMEOUT", v__h55675); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_10 && - wci_wciResponse_10$wget[33:32] == 2'd0 && - !wci_respTimr_10_602_ULT_1_SL_wci_wTimeout_10_6_ETC___d5839 && - wci_reqPend_10 == 2'd2) + if (WILL_FIRE_RL_wci_10_wrkBusy && + wci_10_wciResponse$wget[33:32] == 2'd0 && + !wci_10_respTimr_628_ULT_1_SL_wci_10_wTimeout_6_ETC___d1631 && + wci_10_reqPend == 2'd2) begin - v__h55608 = $time; + v__h55765 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_10 && - wci_wciResponse_10$wget[33:32] == 2'd0 && - !wci_respTimr_10_602_ULT_1_SL_wci_wTimeout_10_6_ETC___d5839 && - wci_reqPend_10 == 2'd2) - $display("[%0d]: %m: WORKER CONFIG-READ TIMEOUT", v__h55608); + if (WILL_FIRE_RL_wci_10_wrkBusy && + wci_10_wciResponse$wget[33:32] == 2'd0 && + !wci_10_respTimr_628_ULT_1_SL_wci_10_wTimeout_6_ETC___d1631 && + wci_10_reqPend == 2'd2) + $display("[%0d]: %m: WORKER CONFIG-READ TIMEOUT", v__h55765); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_10 && - wci_wciResponse_10$wget[33:32] == 2'd0 && - !wci_respTimr_10_602_ULT_1_SL_wci_wTimeout_10_6_ETC___d5839 && - wci_reqPend_10 == 2'd3) + if (WILL_FIRE_RL_wci_10_wrkBusy && + wci_10_wciResponse$wget[33:32] == 2'd0 && + !wci_10_respTimr_628_ULT_1_SL_wci_10_wTimeout_6_ETC___d1631 && + wci_10_reqPend == 2'd3) begin - v__h55697 = $time; + v__h55854 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_10 && - wci_wciResponse_10$wget[33:32] == 2'd0 && - !wci_respTimr_10_602_ULT_1_SL_wci_wTimeout_10_6_ETC___d5839 && - wci_reqPend_10 == 2'd3) - $display("[%0d]: %m: WORKER CONTROL-OP TIMEOUT", v__h55697); + if (WILL_FIRE_RL_wci_10_wrkBusy && + wci_10_wciResponse$wget[33:32] == 2'd0 && + !wci_10_respTimr_628_ULT_1_SL_wci_10_wTimeout_6_ETC___d1631 && + wci_10_reqPend == 2'd3) + $display("[%0d]: %m: WORKER CONTROL-OP TIMEOUT", v__h55854); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_10 && - wci_wciResponse_10$wget[33:32] == 2'd2 && - wci_reqPend_10 == 2'd1) + if (WILL_FIRE_RL_wci_10_wrkBusy && + wci_10_wciResponse$wget[33:32] == 2'd2 && + wci_10_reqPend == 2'd1) begin - v__h55921 = $time; + v__h56078 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_10 && - wci_wciResponse_10$wget[33:32] == 2'd2 && - wci_reqPend_10 == 2'd1) - $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-FAIL", v__h55921); + if (WILL_FIRE_RL_wci_10_wrkBusy && + wci_10_wciResponse$wget[33:32] == 2'd2 && + wci_10_reqPend == 2'd1) + $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-FAIL", v__h56078); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_10 && - wci_wciResponse_10$wget[33:32] == 2'd2 && - wci_reqPend_10 == 2'd2) + if (WILL_FIRE_RL_wci_10_wrkBusy && + wci_10_wciResponse$wget[33:32] == 2'd2 && + wci_10_reqPend == 2'd2) begin - v__h56011 = $time; + v__h56168 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_10 && - wci_wciResponse_10$wget[33:32] == 2'd2 && - wci_reqPend_10 == 2'd2) - $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-FAIL", v__h56011); + if (WILL_FIRE_RL_wci_10_wrkBusy && + wci_10_wciResponse$wget[33:32] == 2'd2 && + wci_10_reqPend == 2'd2) + $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-FAIL", v__h56168); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_10 && - wci_wciResponse_10$wget[33:32] == 2'd2 && - wci_reqPend_10 == 2'd3) + if (WILL_FIRE_RL_wci_10_wrkBusy && + wci_10_wciResponse$wget[33:32] == 2'd2 && + wci_10_reqPend == 2'd3) begin - v__h56100 = $time; + v__h56257 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_10 && - wci_wciResponse_10$wget[33:32] == 2'd2 && - wci_reqPend_10 == 2'd3) - $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-FAIL", v__h56100); + if (WILL_FIRE_RL_wci_10_wrkBusy && + wci_10_wciResponse$wget[33:32] == 2'd2 && + wci_10_reqPend == 2'd3) + $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-FAIL", v__h56257); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_10 && - wci_wciResponse_10$wget[33:32] == 2'd3 && - wci_reqPend_10 == 2'd1) + if (WILL_FIRE_RL_wci_10_wrkBusy && + wci_10_wciResponse$wget[33:32] == 2'd3 && + wci_10_reqPend == 2'd1) begin - v__h56329 = $time; + v__h56486 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_10 && - wci_wciResponse_10$wget[33:32] == 2'd3 && - wci_reqPend_10 == 2'd1) - $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-ERR", v__h56329); + if (WILL_FIRE_RL_wci_10_wrkBusy && + wci_10_wciResponse$wget[33:32] == 2'd3 && + wci_10_reqPend == 2'd1) + $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-ERR", v__h56486); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_10 && - wci_wciResponse_10$wget[33:32] == 2'd3 && - wci_reqPend_10 == 2'd2) + if (WILL_FIRE_RL_wci_10_wrkBusy && + wci_10_wciResponse$wget[33:32] == 2'd3 && + wci_10_reqPend == 2'd2) begin - v__h56419 = $time; + v__h56576 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_10 && - wci_wciResponse_10$wget[33:32] == 2'd3 && - wci_reqPend_10 == 2'd2) - $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-ERR", v__h56419); + if (WILL_FIRE_RL_wci_10_wrkBusy && + wci_10_wciResponse$wget[33:32] == 2'd3 && + wci_10_reqPend == 2'd2) + $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-ERR", v__h56576); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_10 && - wci_wciResponse_10$wget[33:32] == 2'd3 && - wci_reqPend_10 == 2'd3) + if (WILL_FIRE_RL_wci_10_wrkBusy && + wci_10_wciResponse$wget[33:32] == 2'd3 && + wci_10_reqPend == 2'd3) begin - v__h56508 = $time; + v__h56665 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_10 && - wci_wciResponse_10$wget[33:32] == 2'd3 && - wci_reqPend_10 == 2'd3) - $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-ERR", v__h56508); + if (WILL_FIRE_RL_wci_10_wrkBusy && + wci_10_wciResponse$wget[33:32] == 2'd3 && + wci_10_reqPend == 2'd3) + $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-ERR", v__h56665); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_11 && - wci_wciResponse_11$wget[33:32] == 2'd0 && - !wci_respTimr_11_742_ULT_1_SL_wci_wTimeout_11_7_ETC___d5840 && - wci_reqPend_11 == 2'd1) + if (WILL_FIRE_RL_wci_11_wrkBusy && + wci_11_wciResponse$wget[33:32] == 2'd0 && + !wci_11_respTimr_768_ULT_1_SL_wci_11_wTimeout_7_ETC___d1771 && + wci_11_reqPend == 2'd1) begin - v__h59958 = $time; + v__h60044 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_11 && - wci_wciResponse_11$wget[33:32] == 2'd0 && - !wci_respTimr_11_742_ULT_1_SL_wci_wTimeout_11_7_ETC___d5840 && - wci_reqPend_11 == 2'd1) - $display("[%0d]: %m: WORKER CONFIG-WRITE TIMEOUT", v__h59958); + if (WILL_FIRE_RL_wci_11_wrkBusy && + wci_11_wciResponse$wget[33:32] == 2'd0 && + !wci_11_respTimr_768_ULT_1_SL_wci_11_wTimeout_7_ETC___d1771 && + wci_11_reqPend == 2'd1) + $display("[%0d]: %m: WORKER CONFIG-WRITE TIMEOUT", v__h60044); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_11 && - wci_wciResponse_11$wget[33:32] == 2'd0 && - !wci_respTimr_11_742_ULT_1_SL_wci_wTimeout_11_7_ETC___d5840 && - wci_reqPend_11 == 2'd2) + if (WILL_FIRE_RL_wci_11_wrkBusy && + wci_11_wciResponse$wget[33:32] == 2'd0 && + !wci_11_respTimr_768_ULT_1_SL_wci_11_wTimeout_7_ETC___d1771 && + wci_11_reqPend == 2'd2) begin - v__h60048 = $time; + v__h60134 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_11 && - wci_wciResponse_11$wget[33:32] == 2'd0 && - !wci_respTimr_11_742_ULT_1_SL_wci_wTimeout_11_7_ETC___d5840 && - wci_reqPend_11 == 2'd2) - $display("[%0d]: %m: WORKER CONFIG-READ TIMEOUT", v__h60048); + if (WILL_FIRE_RL_wci_11_wrkBusy && + wci_11_wciResponse$wget[33:32] == 2'd0 && + !wci_11_respTimr_768_ULT_1_SL_wci_11_wTimeout_7_ETC___d1771 && + wci_11_reqPend == 2'd2) + $display("[%0d]: %m: WORKER CONFIG-READ TIMEOUT", v__h60134); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_11 && - wci_wciResponse_11$wget[33:32] == 2'd0 && - !wci_respTimr_11_742_ULT_1_SL_wci_wTimeout_11_7_ETC___d5840 && - wci_reqPend_11 == 2'd3) + if (WILL_FIRE_RL_wci_11_wrkBusy && + wci_11_wciResponse$wget[33:32] == 2'd0 && + !wci_11_respTimr_768_ULT_1_SL_wci_11_wTimeout_7_ETC___d1771 && + wci_11_reqPend == 2'd3) begin - v__h60137 = $time; + v__h60223 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_11 && - wci_wciResponse_11$wget[33:32] == 2'd0 && - !wci_respTimr_11_742_ULT_1_SL_wci_wTimeout_11_7_ETC___d5840 && - wci_reqPend_11 == 2'd3) - $display("[%0d]: %m: WORKER CONTROL-OP TIMEOUT", v__h60137); + if (WILL_FIRE_RL_wci_11_wrkBusy && + wci_11_wciResponse$wget[33:32] == 2'd0 && + !wci_11_respTimr_768_ULT_1_SL_wci_11_wTimeout_7_ETC___d1771 && + wci_11_reqPend == 2'd3) + $display("[%0d]: %m: WORKER CONTROL-OP TIMEOUT", v__h60223); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_11 && - wci_wciResponse_11$wget[33:32] == 2'd2 && - wci_reqPend_11 == 2'd1) + if (WILL_FIRE_RL_wci_11_wrkBusy && + wci_11_wciResponse$wget[33:32] == 2'd2 && + wci_11_reqPend == 2'd1) begin - v__h60361 = $time; + v__h60447 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_11 && - wci_wciResponse_11$wget[33:32] == 2'd2 && - wci_reqPend_11 == 2'd1) - $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-FAIL", v__h60361); + if (WILL_FIRE_RL_wci_11_wrkBusy && + wci_11_wciResponse$wget[33:32] == 2'd2 && + wci_11_reqPend == 2'd1) + $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-FAIL", v__h60447); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_11 && - wci_wciResponse_11$wget[33:32] == 2'd2 && - wci_reqPend_11 == 2'd2) + if (WILL_FIRE_RL_wci_11_wrkBusy && + wci_11_wciResponse$wget[33:32] == 2'd2 && + wci_11_reqPend == 2'd2) begin - v__h60451 = $time; + v__h60537 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_11 && - wci_wciResponse_11$wget[33:32] == 2'd2 && - wci_reqPend_11 == 2'd2) - $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-FAIL", v__h60451); + if (WILL_FIRE_RL_wci_11_wrkBusy && + wci_11_wciResponse$wget[33:32] == 2'd2 && + wci_11_reqPend == 2'd2) + $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-FAIL", v__h60537); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_11 && - wci_wciResponse_11$wget[33:32] == 2'd2 && - wci_reqPend_11 == 2'd3) + if (WILL_FIRE_RL_wci_11_wrkBusy && + wci_11_wciResponse$wget[33:32] == 2'd2 && + wci_11_reqPend == 2'd3) begin - v__h60540 = $time; + v__h60626 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_11 && - wci_wciResponse_11$wget[33:32] == 2'd2 && - wci_reqPend_11 == 2'd3) - $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-FAIL", v__h60540); + if (WILL_FIRE_RL_wci_11_wrkBusy && + wci_11_wciResponse$wget[33:32] == 2'd2 && + wci_11_reqPend == 2'd3) + $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-FAIL", v__h60626); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_11 && - wci_wciResponse_11$wget[33:32] == 2'd3 && - wci_reqPend_11 == 2'd1) + if (WILL_FIRE_RL_wci_11_wrkBusy && + wci_11_wciResponse$wget[33:32] == 2'd3 && + wci_11_reqPend == 2'd1) begin - v__h60769 = $time; + v__h60855 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_11 && - wci_wciResponse_11$wget[33:32] == 2'd3 && - wci_reqPend_11 == 2'd1) - $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-ERR", v__h60769); + if (WILL_FIRE_RL_wci_11_wrkBusy && + wci_11_wciResponse$wget[33:32] == 2'd3 && + wci_11_reqPend == 2'd1) + $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-ERR", v__h60855); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_11 && - wci_wciResponse_11$wget[33:32] == 2'd3 && - wci_reqPend_11 == 2'd2) + if (WILL_FIRE_RL_wci_11_wrkBusy && + wci_11_wciResponse$wget[33:32] == 2'd3 && + wci_11_reqPend == 2'd2) begin - v__h60859 = $time; + v__h60945 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_11 && - wci_wciResponse_11$wget[33:32] == 2'd3 && - wci_reqPend_11 == 2'd2) - $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-ERR", v__h60859); + if (WILL_FIRE_RL_wci_11_wrkBusy && + wci_11_wciResponse$wget[33:32] == 2'd3 && + wci_11_reqPend == 2'd2) + $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-ERR", v__h60945); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_11 && - wci_wciResponse_11$wget[33:32] == 2'd3 && - wci_reqPend_11 == 2'd3) + if (WILL_FIRE_RL_wci_11_wrkBusy && + wci_11_wciResponse$wget[33:32] == 2'd3 && + wci_11_reqPend == 2'd3) begin - v__h60948 = $time; + v__h61034 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_11 && - wci_wciResponse_11$wget[33:32] == 2'd3 && - wci_reqPend_11 == 2'd3) - $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-ERR", v__h60948); + if (WILL_FIRE_RL_wci_11_wrkBusy && + wci_11_wciResponse$wget[33:32] == 2'd3 && + wci_11_reqPend == 2'd3) + $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-ERR", v__h61034); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_12 && - wci_wciResponse_12$wget[33:32] == 2'd0 && - !wci_respTimr_12_882_ULT_1_SL_wci_wTimeout_12_8_ETC___d5841 && - wci_reqPend_12 == 2'd1) + if (WILL_FIRE_RL_wci_12_wrkBusy && + wci_12_wciResponse$wget[33:32] == 2'd0 && + !wci_12_respTimr_908_ULT_1_SL_wci_12_wTimeout_9_ETC___d1911 && + wci_12_reqPend == 2'd1) begin - v__h64398 = $time; + v__h64413 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_12 && - wci_wciResponse_12$wget[33:32] == 2'd0 && - !wci_respTimr_12_882_ULT_1_SL_wci_wTimeout_12_8_ETC___d5841 && - wci_reqPend_12 == 2'd1) - $display("[%0d]: %m: WORKER CONFIG-WRITE TIMEOUT", v__h64398); + if (WILL_FIRE_RL_wci_12_wrkBusy && + wci_12_wciResponse$wget[33:32] == 2'd0 && + !wci_12_respTimr_908_ULT_1_SL_wci_12_wTimeout_9_ETC___d1911 && + wci_12_reqPend == 2'd1) + $display("[%0d]: %m: WORKER CONFIG-WRITE TIMEOUT", v__h64413); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_12 && - wci_wciResponse_12$wget[33:32] == 2'd0 && - !wci_respTimr_12_882_ULT_1_SL_wci_wTimeout_12_8_ETC___d5841 && - wci_reqPend_12 == 2'd2) + if (WILL_FIRE_RL_wci_12_wrkBusy && + wci_12_wciResponse$wget[33:32] == 2'd0 && + !wci_12_respTimr_908_ULT_1_SL_wci_12_wTimeout_9_ETC___d1911 && + wci_12_reqPend == 2'd2) begin - v__h64488 = $time; + v__h64503 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_12 && - wci_wciResponse_12$wget[33:32] == 2'd0 && - !wci_respTimr_12_882_ULT_1_SL_wci_wTimeout_12_8_ETC___d5841 && - wci_reqPend_12 == 2'd2) - $display("[%0d]: %m: WORKER CONFIG-READ TIMEOUT", v__h64488); + if (WILL_FIRE_RL_wci_12_wrkBusy && + wci_12_wciResponse$wget[33:32] == 2'd0 && + !wci_12_respTimr_908_ULT_1_SL_wci_12_wTimeout_9_ETC___d1911 && + wci_12_reqPend == 2'd2) + $display("[%0d]: %m: WORKER CONFIG-READ TIMEOUT", v__h64503); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_12 && - wci_wciResponse_12$wget[33:32] == 2'd0 && - !wci_respTimr_12_882_ULT_1_SL_wci_wTimeout_12_8_ETC___d5841 && - wci_reqPend_12 == 2'd3) + if (WILL_FIRE_RL_wci_12_wrkBusy && + wci_12_wciResponse$wget[33:32] == 2'd0 && + !wci_12_respTimr_908_ULT_1_SL_wci_12_wTimeout_9_ETC___d1911 && + wci_12_reqPend == 2'd3) begin - v__h64577 = $time; + v__h64592 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_12 && - wci_wciResponse_12$wget[33:32] == 2'd0 && - !wci_respTimr_12_882_ULT_1_SL_wci_wTimeout_12_8_ETC___d5841 && - wci_reqPend_12 == 2'd3) - $display("[%0d]: %m: WORKER CONTROL-OP TIMEOUT", v__h64577); + if (WILL_FIRE_RL_wci_12_wrkBusy && + wci_12_wciResponse$wget[33:32] == 2'd0 && + !wci_12_respTimr_908_ULT_1_SL_wci_12_wTimeout_9_ETC___d1911 && + wci_12_reqPend == 2'd3) + $display("[%0d]: %m: WORKER CONTROL-OP TIMEOUT", v__h64592); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_12 && - wci_wciResponse_12$wget[33:32] == 2'd2 && - wci_reqPend_12 == 2'd1) + if (WILL_FIRE_RL_wci_12_wrkBusy && + wci_12_wciResponse$wget[33:32] == 2'd2 && + wci_12_reqPend == 2'd1) begin - v__h64801 = $time; + v__h64816 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_12 && - wci_wciResponse_12$wget[33:32] == 2'd2 && - wci_reqPend_12 == 2'd1) - $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-FAIL", v__h64801); + if (WILL_FIRE_RL_wci_12_wrkBusy && + wci_12_wciResponse$wget[33:32] == 2'd2 && + wci_12_reqPend == 2'd1) + $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-FAIL", v__h64816); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_12 && - wci_wciResponse_12$wget[33:32] == 2'd2 && - wci_reqPend_12 == 2'd2) + if (WILL_FIRE_RL_wci_12_wrkBusy && + wci_12_wciResponse$wget[33:32] == 2'd2 && + wci_12_reqPend == 2'd2) begin - v__h64891 = $time; + v__h64906 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_12 && - wci_wciResponse_12$wget[33:32] == 2'd2 && - wci_reqPend_12 == 2'd2) - $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-FAIL", v__h64891); + if (WILL_FIRE_RL_wci_12_wrkBusy && + wci_12_wciResponse$wget[33:32] == 2'd2 && + wci_12_reqPend == 2'd2) + $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-FAIL", v__h64906); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_12 && - wci_wciResponse_12$wget[33:32] == 2'd2 && - wci_reqPend_12 == 2'd3) + if (WILL_FIRE_RL_wci_12_wrkBusy && + wci_12_wciResponse$wget[33:32] == 2'd2 && + wci_12_reqPend == 2'd3) begin - v__h64980 = $time; + v__h64995 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_12 && - wci_wciResponse_12$wget[33:32] == 2'd2 && - wci_reqPend_12 == 2'd3) - $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-FAIL", v__h64980); + if (WILL_FIRE_RL_wci_12_wrkBusy && + wci_12_wciResponse$wget[33:32] == 2'd2 && + wci_12_reqPend == 2'd3) + $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-FAIL", v__h64995); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_12 && - wci_wciResponse_12$wget[33:32] == 2'd3 && - wci_reqPend_12 == 2'd1) + if (WILL_FIRE_RL_wci_12_wrkBusy && + wci_12_wciResponse$wget[33:32] == 2'd3 && + wci_12_reqPend == 2'd1) begin - v__h65209 = $time; + v__h65224 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_12 && - wci_wciResponse_12$wget[33:32] == 2'd3 && - wci_reqPend_12 == 2'd1) - $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-ERR", v__h65209); + if (WILL_FIRE_RL_wci_12_wrkBusy && + wci_12_wciResponse$wget[33:32] == 2'd3 && + wci_12_reqPend == 2'd1) + $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-ERR", v__h65224); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_12 && - wci_wciResponse_12$wget[33:32] == 2'd3 && - wci_reqPend_12 == 2'd2) + if (WILL_FIRE_RL_wci_12_wrkBusy && + wci_12_wciResponse$wget[33:32] == 2'd3 && + wci_12_reqPend == 2'd2) begin - v__h65299 = $time; + v__h65314 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_12 && - wci_wciResponse_12$wget[33:32] == 2'd3 && - wci_reqPend_12 == 2'd2) - $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-ERR", v__h65299); + if (WILL_FIRE_RL_wci_12_wrkBusy && + wci_12_wciResponse$wget[33:32] == 2'd3 && + wci_12_reqPend == 2'd2) + $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-ERR", v__h65314); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_12 && - wci_wciResponse_12$wget[33:32] == 2'd3 && - wci_reqPend_12 == 2'd3) + if (WILL_FIRE_RL_wci_12_wrkBusy && + wci_12_wciResponse$wget[33:32] == 2'd3 && + wci_12_reqPend == 2'd3) begin - v__h65388 = $time; + v__h65403 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_12 && - wci_wciResponse_12$wget[33:32] == 2'd3 && - wci_reqPend_12 == 2'd3) - $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-ERR", v__h65388); + if (WILL_FIRE_RL_wci_12_wrkBusy && + wci_12_wciResponse$wget[33:32] == 2'd3 && + wci_12_reqPend == 2'd3) + $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-ERR", v__h65403); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_13 && - wci_wciResponse_13$wget[33:32] == 2'd0 && - !wci_respTimr_13_022_ULT_1_SL_wci_wTimeout_13_0_ETC___d5842 && - wci_reqPend_13 == 2'd1) + if (WILL_FIRE_RL_wci_13_wrkBusy && + wci_13_wciResponse$wget[33:32] == 2'd0 && + !wci_13_respTimr_048_ULT_1_SL_wci_13_wTimeout_0_ETC___d2051 && + wci_13_reqPend == 2'd1) begin - v__h68838 = $time; + v__h68782 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_13 && - wci_wciResponse_13$wget[33:32] == 2'd0 && - !wci_respTimr_13_022_ULT_1_SL_wci_wTimeout_13_0_ETC___d5842 && - wci_reqPend_13 == 2'd1) - $display("[%0d]: %m: WORKER CONFIG-WRITE TIMEOUT", v__h68838); + if (WILL_FIRE_RL_wci_13_wrkBusy && + wci_13_wciResponse$wget[33:32] == 2'd0 && + !wci_13_respTimr_048_ULT_1_SL_wci_13_wTimeout_0_ETC___d2051 && + wci_13_reqPend == 2'd1) + $display("[%0d]: %m: WORKER CONFIG-WRITE TIMEOUT", v__h68782); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_13 && - wci_wciResponse_13$wget[33:32] == 2'd0 && - !wci_respTimr_13_022_ULT_1_SL_wci_wTimeout_13_0_ETC___d5842 && - wci_reqPend_13 == 2'd2) + if (WILL_FIRE_RL_wci_13_wrkBusy && + wci_13_wciResponse$wget[33:32] == 2'd0 && + !wci_13_respTimr_048_ULT_1_SL_wci_13_wTimeout_0_ETC___d2051 && + wci_13_reqPend == 2'd2) begin - v__h68928 = $time; + v__h68872 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_13 && - wci_wciResponse_13$wget[33:32] == 2'd0 && - !wci_respTimr_13_022_ULT_1_SL_wci_wTimeout_13_0_ETC___d5842 && - wci_reqPend_13 == 2'd2) - $display("[%0d]: %m: WORKER CONFIG-READ TIMEOUT", v__h68928); + if (WILL_FIRE_RL_wci_13_wrkBusy && + wci_13_wciResponse$wget[33:32] == 2'd0 && + !wci_13_respTimr_048_ULT_1_SL_wci_13_wTimeout_0_ETC___d2051 && + wci_13_reqPend == 2'd2) + $display("[%0d]: %m: WORKER CONFIG-READ TIMEOUT", v__h68872); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_13 && - wci_wciResponse_13$wget[33:32] == 2'd0 && - !wci_respTimr_13_022_ULT_1_SL_wci_wTimeout_13_0_ETC___d5842 && - wci_reqPend_13 == 2'd3) + if (WILL_FIRE_RL_wci_13_wrkBusy && + wci_13_wciResponse$wget[33:32] == 2'd0 && + !wci_13_respTimr_048_ULT_1_SL_wci_13_wTimeout_0_ETC___d2051 && + wci_13_reqPend == 2'd3) begin - v__h69017 = $time; + v__h68961 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_13 && - wci_wciResponse_13$wget[33:32] == 2'd0 && - !wci_respTimr_13_022_ULT_1_SL_wci_wTimeout_13_0_ETC___d5842 && - wci_reqPend_13 == 2'd3) - $display("[%0d]: %m: WORKER CONTROL-OP TIMEOUT", v__h69017); + if (WILL_FIRE_RL_wci_13_wrkBusy && + wci_13_wciResponse$wget[33:32] == 2'd0 && + !wci_13_respTimr_048_ULT_1_SL_wci_13_wTimeout_0_ETC___d2051 && + wci_13_reqPend == 2'd3) + $display("[%0d]: %m: WORKER CONTROL-OP TIMEOUT", v__h68961); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_13 && - wci_wciResponse_13$wget[33:32] == 2'd2 && - wci_reqPend_13 == 2'd1) + if (WILL_FIRE_RL_wci_13_wrkBusy && + wci_13_wciResponse$wget[33:32] == 2'd2 && + wci_13_reqPend == 2'd1) begin - v__h69241 = $time; + v__h69185 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_13 && - wci_wciResponse_13$wget[33:32] == 2'd2 && - wci_reqPend_13 == 2'd1) - $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-FAIL", v__h69241); + if (WILL_FIRE_RL_wci_13_wrkBusy && + wci_13_wciResponse$wget[33:32] == 2'd2 && + wci_13_reqPend == 2'd1) + $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-FAIL", v__h69185); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_13 && - wci_wciResponse_13$wget[33:32] == 2'd2 && - wci_reqPend_13 == 2'd2) + if (WILL_FIRE_RL_wci_13_wrkBusy && + wci_13_wciResponse$wget[33:32] == 2'd2 && + wci_13_reqPend == 2'd2) begin - v__h69331 = $time; + v__h69275 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_13 && - wci_wciResponse_13$wget[33:32] == 2'd2 && - wci_reqPend_13 == 2'd2) - $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-FAIL", v__h69331); + if (WILL_FIRE_RL_wci_13_wrkBusy && + wci_13_wciResponse$wget[33:32] == 2'd2 && + wci_13_reqPend == 2'd2) + $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-FAIL", v__h69275); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_13 && - wci_wciResponse_13$wget[33:32] == 2'd2 && - wci_reqPend_13 == 2'd3) + if (WILL_FIRE_RL_wci_13_wrkBusy && + wci_13_wciResponse$wget[33:32] == 2'd2 && + wci_13_reqPend == 2'd3) begin - v__h69420 = $time; + v__h69364 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_13 && - wci_wciResponse_13$wget[33:32] == 2'd2 && - wci_reqPend_13 == 2'd3) - $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-FAIL", v__h69420); + if (WILL_FIRE_RL_wci_13_wrkBusy && + wci_13_wciResponse$wget[33:32] == 2'd2 && + wci_13_reqPend == 2'd3) + $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-FAIL", v__h69364); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_13 && - wci_wciResponse_13$wget[33:32] == 2'd3 && - wci_reqPend_13 == 2'd1) + if (WILL_FIRE_RL_wci_13_wrkBusy && + wci_13_wciResponse$wget[33:32] == 2'd3 && + wci_13_reqPend == 2'd1) begin - v__h69649 = $time; + v__h69593 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_13 && - wci_wciResponse_13$wget[33:32] == 2'd3 && - wci_reqPend_13 == 2'd1) - $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-ERR", v__h69649); + if (WILL_FIRE_RL_wci_13_wrkBusy && + wci_13_wciResponse$wget[33:32] == 2'd3 && + wci_13_reqPend == 2'd1) + $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-ERR", v__h69593); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_13 && - wci_wciResponse_13$wget[33:32] == 2'd3 && - wci_reqPend_13 == 2'd2) + if (WILL_FIRE_RL_wci_13_wrkBusy && + wci_13_wciResponse$wget[33:32] == 2'd3 && + wci_13_reqPend == 2'd2) begin - v__h69739 = $time; + v__h69683 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_13 && - wci_wciResponse_13$wget[33:32] == 2'd3 && - wci_reqPend_13 == 2'd2) - $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-ERR", v__h69739); + if (WILL_FIRE_RL_wci_13_wrkBusy && + wci_13_wciResponse$wget[33:32] == 2'd3 && + wci_13_reqPend == 2'd2) + $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-ERR", v__h69683); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_13 && - wci_wciResponse_13$wget[33:32] == 2'd3 && - wci_reqPend_13 == 2'd3) + if (WILL_FIRE_RL_wci_13_wrkBusy && + wci_13_wciResponse$wget[33:32] == 2'd3 && + wci_13_reqPend == 2'd3) begin - v__h69828 = $time; + v__h69772 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_13 && - wci_wciResponse_13$wget[33:32] == 2'd3 && - wci_reqPend_13 == 2'd3) - $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-ERR", v__h69828); + if (WILL_FIRE_RL_wci_13_wrkBusy && + wci_13_wciResponse$wget[33:32] == 2'd3 && + wci_13_reqPend == 2'd3) + $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-ERR", v__h69772); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_14 && - wci_wciResponse_14$wget[33:32] == 2'd0 && - !wci_respTimr_14_162_ULT_1_SL_wci_wTimeout_14_1_ETC___d5843 && - wci_reqPend_14 == 2'd1) + if (WILL_FIRE_RL_wci_14_wrkBusy && + wci_14_wciResponse$wget[33:32] == 2'd0 && + !wci_14_respTimr_188_ULT_1_SL_wci_14_wTimeout_1_ETC___d2191 && + wci_14_reqPend == 2'd1) begin - v__h73278 = $time; + v__h73151 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_14 && - wci_wciResponse_14$wget[33:32] == 2'd0 && - !wci_respTimr_14_162_ULT_1_SL_wci_wTimeout_14_1_ETC___d5843 && - wci_reqPend_14 == 2'd1) - $display("[%0d]: %m: WORKER CONFIG-WRITE TIMEOUT", v__h73278); + if (WILL_FIRE_RL_wci_14_wrkBusy && + wci_14_wciResponse$wget[33:32] == 2'd0 && + !wci_14_respTimr_188_ULT_1_SL_wci_14_wTimeout_1_ETC___d2191 && + wci_14_reqPend == 2'd1) + $display("[%0d]: %m: WORKER CONFIG-WRITE TIMEOUT", v__h73151); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_14 && - wci_wciResponse_14$wget[33:32] == 2'd0 && - !wci_respTimr_14_162_ULT_1_SL_wci_wTimeout_14_1_ETC___d5843 && - wci_reqPend_14 == 2'd2) + if (WILL_FIRE_RL_wci_14_wrkBusy && + wci_14_wciResponse$wget[33:32] == 2'd0 && + !wci_14_respTimr_188_ULT_1_SL_wci_14_wTimeout_1_ETC___d2191 && + wci_14_reqPend == 2'd2) begin - v__h73368 = $time; + v__h73241 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_14 && - wci_wciResponse_14$wget[33:32] == 2'd0 && - !wci_respTimr_14_162_ULT_1_SL_wci_wTimeout_14_1_ETC___d5843 && - wci_reqPend_14 == 2'd2) - $display("[%0d]: %m: WORKER CONFIG-READ TIMEOUT", v__h73368); + if (WILL_FIRE_RL_wci_14_wrkBusy && + wci_14_wciResponse$wget[33:32] == 2'd0 && + !wci_14_respTimr_188_ULT_1_SL_wci_14_wTimeout_1_ETC___d2191 && + wci_14_reqPend == 2'd2) + $display("[%0d]: %m: WORKER CONFIG-READ TIMEOUT", v__h73241); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_14 && - wci_wciResponse_14$wget[33:32] == 2'd0 && - !wci_respTimr_14_162_ULT_1_SL_wci_wTimeout_14_1_ETC___d5843 && - wci_reqPend_14 == 2'd3) + if (WILL_FIRE_RL_wci_14_wrkBusy && + wci_14_wciResponse$wget[33:32] == 2'd0 && + !wci_14_respTimr_188_ULT_1_SL_wci_14_wTimeout_1_ETC___d2191 && + wci_14_reqPend == 2'd3) begin - v__h73457 = $time; + v__h73330 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_14 && - wci_wciResponse_14$wget[33:32] == 2'd0 && - !wci_respTimr_14_162_ULT_1_SL_wci_wTimeout_14_1_ETC___d5843 && - wci_reqPend_14 == 2'd3) - $display("[%0d]: %m: WORKER CONTROL-OP TIMEOUT", v__h73457); + if (WILL_FIRE_RL_wci_14_wrkBusy && + wci_14_wciResponse$wget[33:32] == 2'd0 && + !wci_14_respTimr_188_ULT_1_SL_wci_14_wTimeout_1_ETC___d2191 && + wci_14_reqPend == 2'd3) + $display("[%0d]: %m: WORKER CONTROL-OP TIMEOUT", v__h73330); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_14 && - wci_wciResponse_14$wget[33:32] == 2'd2 && - wci_reqPend_14 == 2'd1) + if (WILL_FIRE_RL_wci_14_wrkBusy && + wci_14_wciResponse$wget[33:32] == 2'd2 && + wci_14_reqPend == 2'd1) begin - v__h73681 = $time; + v__h73554 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_14 && - wci_wciResponse_14$wget[33:32] == 2'd2 && - wci_reqPend_14 == 2'd1) - $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-FAIL", v__h73681); + if (WILL_FIRE_RL_wci_14_wrkBusy && + wci_14_wciResponse$wget[33:32] == 2'd2 && + wci_14_reqPend == 2'd1) + $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-FAIL", v__h73554); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_14 && - wci_wciResponse_14$wget[33:32] == 2'd2 && - wci_reqPend_14 == 2'd2) + if (WILL_FIRE_RL_wci_14_wrkBusy && + wci_14_wciResponse$wget[33:32] == 2'd2 && + wci_14_reqPend == 2'd2) begin - v__h73771 = $time; + v__h73644 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_14 && - wci_wciResponse_14$wget[33:32] == 2'd2 && - wci_reqPend_14 == 2'd2) - $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-FAIL", v__h73771); + if (WILL_FIRE_RL_wci_14_wrkBusy && + wci_14_wciResponse$wget[33:32] == 2'd2 && + wci_14_reqPend == 2'd2) + $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-FAIL", v__h73644); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_14 && - wci_wciResponse_14$wget[33:32] == 2'd2 && - wci_reqPend_14 == 2'd3) + if (WILL_FIRE_RL_wci_14_wrkBusy && + wci_14_wciResponse$wget[33:32] == 2'd2 && + wci_14_reqPend == 2'd3) begin - v__h73860 = $time; + v__h73733 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_14 && - wci_wciResponse_14$wget[33:32] == 2'd2 && - wci_reqPend_14 == 2'd3) - $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-FAIL", v__h73860); + if (WILL_FIRE_RL_wci_14_wrkBusy && + wci_14_wciResponse$wget[33:32] == 2'd2 && + wci_14_reqPend == 2'd3) + $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-FAIL", v__h73733); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_14 && - wci_wciResponse_14$wget[33:32] == 2'd3 && - wci_reqPend_14 == 2'd1) + if (WILL_FIRE_RL_wci_14_wrkBusy && + wci_14_wciResponse$wget[33:32] == 2'd3 && + wci_14_reqPend == 2'd1) begin - v__h74089 = $time; + v__h73962 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_14 && - wci_wciResponse_14$wget[33:32] == 2'd3 && - wci_reqPend_14 == 2'd1) - $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-ERR", v__h74089); + if (WILL_FIRE_RL_wci_14_wrkBusy && + wci_14_wciResponse$wget[33:32] == 2'd3 && + wci_14_reqPend == 2'd1) + $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-ERR", v__h73962); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_14 && - wci_wciResponse_14$wget[33:32] == 2'd3 && - wci_reqPend_14 == 2'd2) + if (WILL_FIRE_RL_wci_14_wrkBusy && + wci_14_wciResponse$wget[33:32] == 2'd3 && + wci_14_reqPend == 2'd2) begin - v__h74179 = $time; + v__h74052 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_14 && - wci_wciResponse_14$wget[33:32] == 2'd3 && - wci_reqPend_14 == 2'd2) - $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-ERR", v__h74179); + if (WILL_FIRE_RL_wci_14_wrkBusy && + wci_14_wciResponse$wget[33:32] == 2'd3 && + wci_14_reqPend == 2'd2) + $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-ERR", v__h74052); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_14 && - wci_wciResponse_14$wget[33:32] == 2'd3 && - wci_reqPend_14 == 2'd3) + if (WILL_FIRE_RL_wci_14_wrkBusy && + wci_14_wciResponse$wget[33:32] == 2'd3 && + wci_14_reqPend == 2'd3) begin - v__h74268 = $time; + v__h74141 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_wrkBusy_14 && - wci_wciResponse_14$wget[33:32] == 2'd3 && - wci_reqPend_14 == 2'd3) - $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-ERR", v__h74268); + if (WILL_FIRE_RL_wci_14_wrkBusy && + wci_14_wciResponse$wget[33:32] == 2'd3 && + wci_14_reqPend == 2'd3) + $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-ERR", v__h74141); end // synopsys translate_on endmodule // mkOCCP diff --git a/rtl/mkOCDP16B.v b/rtl/mkOCDP16B.v index 58fcf6a2..947f01bb 100644 --- a/rtl/mkOCDP16B.v +++ b/rtl/mkOCDP16B.v @@ -1,7 +1,7 @@ // -// Generated by Bluespec Compiler, version 2012.09.beta1 (build 29570, 2012-09.11) +// Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Wed Nov 28 10:39:07 EST 2012 +// On Fri Jun 21 17:01:01 EDT 2013 // // // Ports: @@ -278,22 +278,22 @@ module mkOCDP16B(pciDevice, wire [66 : 0] wti_wtiReq$wget; wire [63 : 0] tlp_nowW$wget, wmi_nowW$wget; wire [33 : 0] wci_respF_x_wire$wget; - wire [31 : 0] bram_serverAdapterA_1_outData_enqData$wget, - bram_serverAdapterA_1_outData_outData$wget, - bram_serverAdapterA_2_outData_enqData$wget, - bram_serverAdapterA_2_outData_outData$wget, - bram_serverAdapterA_3_outData_enqData$wget, - bram_serverAdapterA_3_outData_outData$wget, - bram_serverAdapterA_outData_enqData$wget, - bram_serverAdapterA_outData_outData$wget, - bram_serverAdapterB_1_outData_enqData$wget, - bram_serverAdapterB_1_outData_outData$wget, - bram_serverAdapterB_2_outData_enqData$wget, - bram_serverAdapterB_2_outData_outData$wget, - bram_serverAdapterB_3_outData_enqData$wget, - bram_serverAdapterB_3_outData_outData$wget, - bram_serverAdapterB_outData_enqData$wget, - bram_serverAdapterB_outData_outData$wget, + wire [31 : 0] bram_0_serverAdapterA_outData_enqData$wget, + bram_0_serverAdapterA_outData_outData$wget, + bram_0_serverAdapterB_outData_enqData$wget, + bram_0_serverAdapterB_outData_outData$wget, + bram_1_serverAdapterA_outData_enqData$wget, + bram_1_serverAdapterA_outData_outData$wget, + bram_1_serverAdapterB_outData_enqData$wget, + bram_1_serverAdapterB_outData_outData$wget, + bram_2_serverAdapterA_outData_enqData$wget, + bram_2_serverAdapterA_outData_outData$wget, + bram_2_serverAdapterB_outData_enqData$wget, + bram_2_serverAdapterB_outData_outData$wget, + bram_3_serverAdapterA_outData_enqData$wget, + bram_3_serverAdapterA_outData_outData$wget, + bram_3_serverAdapterB_outData_enqData$wget, + bram_3_serverAdapterB_outData_outData$wget, wci_Es_mAddr_w$wget, wci_Es_mData_w$wget, wmi_wmi_wmiMFlag$wget, @@ -307,49 +307,49 @@ module mkOCDP16B(pciDevice, wire [11 : 0] wmi_Es_mBurstLength_w$wget; wire [7 : 0] bml_dpControl$wget, tlp_dpControl$wget, wmi_dpControl$wget; wire [3 : 0] wci_Es_mByteEn_w$wget; - wire [2 : 0] bram_serverAdapterA_1_cnt_1$wget, - bram_serverAdapterA_1_cnt_2$wget, - bram_serverAdapterA_1_cnt_3$wget, - bram_serverAdapterA_2_cnt_1$wget, - bram_serverAdapterA_2_cnt_2$wget, - bram_serverAdapterA_2_cnt_3$wget, - bram_serverAdapterA_3_cnt_1$wget, - bram_serverAdapterA_3_cnt_2$wget, - bram_serverAdapterA_3_cnt_3$wget, - bram_serverAdapterA_cnt_1$wget, - bram_serverAdapterA_cnt_2$wget, - bram_serverAdapterA_cnt_3$wget, - bram_serverAdapterB_1_cnt_1$wget, - bram_serverAdapterB_1_cnt_2$wget, - bram_serverAdapterB_1_cnt_3$wget, - bram_serverAdapterB_2_cnt_1$wget, - bram_serverAdapterB_2_cnt_2$wget, - bram_serverAdapterB_2_cnt_3$wget, - bram_serverAdapterB_3_cnt_1$wget, - bram_serverAdapterB_3_cnt_2$wget, - bram_serverAdapterB_3_cnt_3$wget, - bram_serverAdapterB_cnt_1$wget, - bram_serverAdapterB_cnt_2$wget, - bram_serverAdapterB_cnt_3$wget, + wire [2 : 0] bram_0_serverAdapterA_cnt_1$wget, + bram_0_serverAdapterA_cnt_2$wget, + bram_0_serverAdapterA_cnt_3$wget, + bram_0_serverAdapterB_cnt_1$wget, + bram_0_serverAdapterB_cnt_2$wget, + bram_0_serverAdapterB_cnt_3$wget, + bram_1_serverAdapterA_cnt_1$wget, + bram_1_serverAdapterA_cnt_2$wget, + bram_1_serverAdapterA_cnt_3$wget, + bram_1_serverAdapterB_cnt_1$wget, + bram_1_serverAdapterB_cnt_2$wget, + bram_1_serverAdapterB_cnt_3$wget, + bram_2_serverAdapterA_cnt_1$wget, + bram_2_serverAdapterA_cnt_2$wget, + bram_2_serverAdapterA_cnt_3$wget, + bram_2_serverAdapterB_cnt_1$wget, + bram_2_serverAdapterB_cnt_2$wget, + bram_2_serverAdapterB_cnt_3$wget, + bram_3_serverAdapterA_cnt_1$wget, + bram_3_serverAdapterA_cnt_2$wget, + bram_3_serverAdapterA_cnt_3$wget, + bram_3_serverAdapterB_cnt_1$wget, + bram_3_serverAdapterB_cnt_2$wget, + bram_3_serverAdapterB_cnt_3$wget, wci_Es_mCmd_w$wget, wci_wEdge$wget, wmi_Es_mCmd_w$wget; - wire [1 : 0] bram_serverAdapterA_1_s1_1$wget, - bram_serverAdapterA_1_writeWithResp$wget, - bram_serverAdapterA_2_s1_1$wget, - bram_serverAdapterA_2_writeWithResp$wget, - bram_serverAdapterA_3_s1_1$wget, - bram_serverAdapterA_3_writeWithResp$wget, - bram_serverAdapterA_s1_1$wget, - bram_serverAdapterA_writeWithResp$wget, - bram_serverAdapterB_1_s1_1$wget, - bram_serverAdapterB_1_writeWithResp$wget, - bram_serverAdapterB_2_s1_1$wget, - bram_serverAdapterB_2_writeWithResp$wget, - bram_serverAdapterB_3_s1_1$wget, - bram_serverAdapterB_3_writeWithResp$wget, - bram_serverAdapterB_s1_1$wget, - bram_serverAdapterB_writeWithResp$wget; + wire [1 : 0] bram_0_serverAdapterA_s1_1$wget, + bram_0_serverAdapterA_writeWithResp$wget, + bram_0_serverAdapterB_s1_1$wget, + bram_0_serverAdapterB_writeWithResp$wget, + bram_1_serverAdapterA_s1_1$wget, + bram_1_serverAdapterA_writeWithResp$wget, + bram_1_serverAdapterB_s1_1$wget, + bram_1_serverAdapterB_writeWithResp$wget, + bram_2_serverAdapterA_s1_1$wget, + bram_2_serverAdapterA_writeWithResp$wget, + bram_2_serverAdapterB_s1_1$wget, + bram_2_serverAdapterB_writeWithResp$wget, + bram_3_serverAdapterA_s1_1$wget, + bram_3_serverAdapterA_writeWithResp$wget, + bram_3_serverAdapterB_s1_1$wget, + bram_3_serverAdapterB_writeWithResp$wget; wire bml_crdBuf_decAction$whas, bml_crdBuf_incAction$whas, bml_datumAReg_1$wget, @@ -373,70 +373,70 @@ module mkOCDP16B(pciDevice, bml_remDone_1$whas, bml_remStart_1$wget, bml_remStart_1$whas, - bram_serverAdapterA_1_cnt_1$whas, - bram_serverAdapterA_1_cnt_2$whas, - bram_serverAdapterA_1_cnt_3$whas, - bram_serverAdapterA_1_outData_deqCalled$whas, - bram_serverAdapterA_1_outData_enqData$whas, - bram_serverAdapterA_1_outData_outData$whas, - bram_serverAdapterA_1_s1_1$whas, - bram_serverAdapterA_1_writeWithResp$whas, - bram_serverAdapterA_2_cnt_1$whas, - bram_serverAdapterA_2_cnt_2$whas, - bram_serverAdapterA_2_cnt_3$whas, - bram_serverAdapterA_2_outData_deqCalled$whas, - bram_serverAdapterA_2_outData_enqData$whas, - bram_serverAdapterA_2_outData_outData$whas, - bram_serverAdapterA_2_s1_1$whas, - bram_serverAdapterA_2_writeWithResp$whas, - bram_serverAdapterA_3_cnt_1$whas, - bram_serverAdapterA_3_cnt_2$whas, - bram_serverAdapterA_3_cnt_3$whas, - bram_serverAdapterA_3_outData_deqCalled$whas, - bram_serverAdapterA_3_outData_enqData$whas, - bram_serverAdapterA_3_outData_outData$whas, - bram_serverAdapterA_3_s1_1$whas, - bram_serverAdapterA_3_writeWithResp$whas, - bram_serverAdapterA_cnt_1$whas, - bram_serverAdapterA_cnt_2$whas, - bram_serverAdapterA_cnt_3$whas, - bram_serverAdapterA_outData_deqCalled$whas, - bram_serverAdapterA_outData_enqData$whas, - bram_serverAdapterA_outData_outData$whas, - bram_serverAdapterA_s1_1$whas, - bram_serverAdapterA_writeWithResp$whas, - bram_serverAdapterB_1_cnt_1$whas, - bram_serverAdapterB_1_cnt_2$whas, - bram_serverAdapterB_1_cnt_3$whas, - bram_serverAdapterB_1_outData_deqCalled$whas, - bram_serverAdapterB_1_outData_enqData$whas, - bram_serverAdapterB_1_outData_outData$whas, - bram_serverAdapterB_1_s1_1$whas, - bram_serverAdapterB_1_writeWithResp$whas, - bram_serverAdapterB_2_cnt_1$whas, - bram_serverAdapterB_2_cnt_2$whas, - bram_serverAdapterB_2_cnt_3$whas, - bram_serverAdapterB_2_outData_deqCalled$whas, - bram_serverAdapterB_2_outData_enqData$whas, - bram_serverAdapterB_2_outData_outData$whas, - bram_serverAdapterB_2_s1_1$whas, - bram_serverAdapterB_2_writeWithResp$whas, - bram_serverAdapterB_3_cnt_1$whas, - bram_serverAdapterB_3_cnt_2$whas, - bram_serverAdapterB_3_cnt_3$whas, - bram_serverAdapterB_3_outData_deqCalled$whas, - bram_serverAdapterB_3_outData_enqData$whas, - bram_serverAdapterB_3_outData_outData$whas, - bram_serverAdapterB_3_s1_1$whas, - bram_serverAdapterB_3_writeWithResp$whas, - bram_serverAdapterB_cnt_1$whas, - bram_serverAdapterB_cnt_2$whas, - bram_serverAdapterB_cnt_3$whas, - bram_serverAdapterB_outData_deqCalled$whas, - bram_serverAdapterB_outData_enqData$whas, - bram_serverAdapterB_outData_outData$whas, - bram_serverAdapterB_s1_1$whas, - bram_serverAdapterB_writeWithResp$whas, + bram_0_serverAdapterA_cnt_1$whas, + bram_0_serverAdapterA_cnt_2$whas, + bram_0_serverAdapterA_cnt_3$whas, + bram_0_serverAdapterA_outData_deqCalled$whas, + bram_0_serverAdapterA_outData_enqData$whas, + bram_0_serverAdapterA_outData_outData$whas, + bram_0_serverAdapterA_s1_1$whas, + bram_0_serverAdapterA_writeWithResp$whas, + bram_0_serverAdapterB_cnt_1$whas, + bram_0_serverAdapterB_cnt_2$whas, + bram_0_serverAdapterB_cnt_3$whas, + bram_0_serverAdapterB_outData_deqCalled$whas, + bram_0_serverAdapterB_outData_enqData$whas, + bram_0_serverAdapterB_outData_outData$whas, + bram_0_serverAdapterB_s1_1$whas, + bram_0_serverAdapterB_writeWithResp$whas, + bram_1_serverAdapterA_cnt_1$whas, + bram_1_serverAdapterA_cnt_2$whas, + bram_1_serverAdapterA_cnt_3$whas, + bram_1_serverAdapterA_outData_deqCalled$whas, + bram_1_serverAdapterA_outData_enqData$whas, + bram_1_serverAdapterA_outData_outData$whas, + bram_1_serverAdapterA_s1_1$whas, + bram_1_serverAdapterA_writeWithResp$whas, + bram_1_serverAdapterB_cnt_1$whas, + bram_1_serverAdapterB_cnt_2$whas, + bram_1_serverAdapterB_cnt_3$whas, + bram_1_serverAdapterB_outData_deqCalled$whas, + bram_1_serverAdapterB_outData_enqData$whas, + bram_1_serverAdapterB_outData_outData$whas, + bram_1_serverAdapterB_s1_1$whas, + bram_1_serverAdapterB_writeWithResp$whas, + bram_2_serverAdapterA_cnt_1$whas, + bram_2_serverAdapterA_cnt_2$whas, + bram_2_serverAdapterA_cnt_3$whas, + bram_2_serverAdapterA_outData_deqCalled$whas, + bram_2_serverAdapterA_outData_enqData$whas, + bram_2_serverAdapterA_outData_outData$whas, + bram_2_serverAdapterA_s1_1$whas, + bram_2_serverAdapterA_writeWithResp$whas, + bram_2_serverAdapterB_cnt_1$whas, + bram_2_serverAdapterB_cnt_2$whas, + bram_2_serverAdapterB_cnt_3$whas, + bram_2_serverAdapterB_outData_deqCalled$whas, + bram_2_serverAdapterB_outData_enqData$whas, + bram_2_serverAdapterB_outData_outData$whas, + bram_2_serverAdapterB_s1_1$whas, + bram_2_serverAdapterB_writeWithResp$whas, + bram_3_serverAdapterA_cnt_1$whas, + bram_3_serverAdapterA_cnt_2$whas, + bram_3_serverAdapterA_cnt_3$whas, + bram_3_serverAdapterA_outData_deqCalled$whas, + bram_3_serverAdapterA_outData_enqData$whas, + bram_3_serverAdapterA_outData_outData$whas, + bram_3_serverAdapterA_s1_1$whas, + bram_3_serverAdapterA_writeWithResp$whas, + bram_3_serverAdapterB_cnt_1$whas, + bram_3_serverAdapterB_cnt_2$whas, + bram_3_serverAdapterB_cnt_3$whas, + bram_3_serverAdapterB_outData_deqCalled$whas, + bram_3_serverAdapterB_outData_enqData$whas, + bram_3_serverAdapterB_outData_outData$whas, + bram_3_serverAdapterB_s1_1$whas, + bram_3_serverAdapterB_writeWithResp$whas, tlp_creditReady_1$wget, tlp_creditReady_1$whas, tlp_dmaDoneMark_1$wget, @@ -753,85 +753,85 @@ module mkOCDP16B(pciDevice, wire [15 : 0] bml_remStarts$D_IN; wire bml_remStarts$EN; - // register bram_serverAdapterA_1_cnt - reg [2 : 0] bram_serverAdapterA_1_cnt; - wire [2 : 0] bram_serverAdapterA_1_cnt$D_IN; - wire bram_serverAdapterA_1_cnt$EN; - - // register bram_serverAdapterA_1_s1 - reg [1 : 0] bram_serverAdapterA_1_s1; - wire [1 : 0] bram_serverAdapterA_1_s1$D_IN; - wire bram_serverAdapterA_1_s1$EN; - - // register bram_serverAdapterA_2_cnt - reg [2 : 0] bram_serverAdapterA_2_cnt; - wire [2 : 0] bram_serverAdapterA_2_cnt$D_IN; - wire bram_serverAdapterA_2_cnt$EN; - - // register bram_serverAdapterA_2_s1 - reg [1 : 0] bram_serverAdapterA_2_s1; - wire [1 : 0] bram_serverAdapterA_2_s1$D_IN; - wire bram_serverAdapterA_2_s1$EN; - - // register bram_serverAdapterA_3_cnt - reg [2 : 0] bram_serverAdapterA_3_cnt; - wire [2 : 0] bram_serverAdapterA_3_cnt$D_IN; - wire bram_serverAdapterA_3_cnt$EN; - - // register bram_serverAdapterA_3_s1 - reg [1 : 0] bram_serverAdapterA_3_s1; - wire [1 : 0] bram_serverAdapterA_3_s1$D_IN; - wire bram_serverAdapterA_3_s1$EN; - - // register bram_serverAdapterA_cnt - reg [2 : 0] bram_serverAdapterA_cnt; - wire [2 : 0] bram_serverAdapterA_cnt$D_IN; - wire bram_serverAdapterA_cnt$EN; - - // register bram_serverAdapterA_s1 - reg [1 : 0] bram_serverAdapterA_s1; - wire [1 : 0] bram_serverAdapterA_s1$D_IN; - wire bram_serverAdapterA_s1$EN; - - // register bram_serverAdapterB_1_cnt - reg [2 : 0] bram_serverAdapterB_1_cnt; - wire [2 : 0] bram_serverAdapterB_1_cnt$D_IN; - wire bram_serverAdapterB_1_cnt$EN; - - // register bram_serverAdapterB_1_s1 - reg [1 : 0] bram_serverAdapterB_1_s1; - wire [1 : 0] bram_serverAdapterB_1_s1$D_IN; - wire bram_serverAdapterB_1_s1$EN; - - // register bram_serverAdapterB_2_cnt - reg [2 : 0] bram_serverAdapterB_2_cnt; - wire [2 : 0] bram_serverAdapterB_2_cnt$D_IN; - wire bram_serverAdapterB_2_cnt$EN; - - // register bram_serverAdapterB_2_s1 - reg [1 : 0] bram_serverAdapterB_2_s1; - wire [1 : 0] bram_serverAdapterB_2_s1$D_IN; - wire bram_serverAdapterB_2_s1$EN; - - // register bram_serverAdapterB_3_cnt - reg [2 : 0] bram_serverAdapterB_3_cnt; - wire [2 : 0] bram_serverAdapterB_3_cnt$D_IN; - wire bram_serverAdapterB_3_cnt$EN; - - // register bram_serverAdapterB_3_s1 - reg [1 : 0] bram_serverAdapterB_3_s1; - wire [1 : 0] bram_serverAdapterB_3_s1$D_IN; - wire bram_serverAdapterB_3_s1$EN; - - // register bram_serverAdapterB_cnt - reg [2 : 0] bram_serverAdapterB_cnt; - wire [2 : 0] bram_serverAdapterB_cnt$D_IN; - wire bram_serverAdapterB_cnt$EN; - - // register bram_serverAdapterB_s1 - reg [1 : 0] bram_serverAdapterB_s1; - wire [1 : 0] bram_serverAdapterB_s1$D_IN; - wire bram_serverAdapterB_s1$EN; + // register bram_0_serverAdapterA_cnt + reg [2 : 0] bram_0_serverAdapterA_cnt; + wire [2 : 0] bram_0_serverAdapterA_cnt$D_IN; + wire bram_0_serverAdapterA_cnt$EN; + + // register bram_0_serverAdapterA_s1 + reg [1 : 0] bram_0_serverAdapterA_s1; + wire [1 : 0] bram_0_serverAdapterA_s1$D_IN; + wire bram_0_serverAdapterA_s1$EN; + + // register bram_0_serverAdapterB_cnt + reg [2 : 0] bram_0_serverAdapterB_cnt; + wire [2 : 0] bram_0_serverAdapterB_cnt$D_IN; + wire bram_0_serverAdapterB_cnt$EN; + + // register bram_0_serverAdapterB_s1 + reg [1 : 0] bram_0_serverAdapterB_s1; + wire [1 : 0] bram_0_serverAdapterB_s1$D_IN; + wire bram_0_serverAdapterB_s1$EN; + + // register bram_1_serverAdapterA_cnt + reg [2 : 0] bram_1_serverAdapterA_cnt; + wire [2 : 0] bram_1_serverAdapterA_cnt$D_IN; + wire bram_1_serverAdapterA_cnt$EN; + + // register bram_1_serverAdapterA_s1 + reg [1 : 0] bram_1_serverAdapterA_s1; + wire [1 : 0] bram_1_serverAdapterA_s1$D_IN; + wire bram_1_serverAdapterA_s1$EN; + + // register bram_1_serverAdapterB_cnt + reg [2 : 0] bram_1_serverAdapterB_cnt; + wire [2 : 0] bram_1_serverAdapterB_cnt$D_IN; + wire bram_1_serverAdapterB_cnt$EN; + + // register bram_1_serverAdapterB_s1 + reg [1 : 0] bram_1_serverAdapterB_s1; + wire [1 : 0] bram_1_serverAdapterB_s1$D_IN; + wire bram_1_serverAdapterB_s1$EN; + + // register bram_2_serverAdapterA_cnt + reg [2 : 0] bram_2_serverAdapterA_cnt; + wire [2 : 0] bram_2_serverAdapterA_cnt$D_IN; + wire bram_2_serverAdapterA_cnt$EN; + + // register bram_2_serverAdapterA_s1 + reg [1 : 0] bram_2_serverAdapterA_s1; + wire [1 : 0] bram_2_serverAdapterA_s1$D_IN; + wire bram_2_serverAdapterA_s1$EN; + + // register bram_2_serverAdapterB_cnt + reg [2 : 0] bram_2_serverAdapterB_cnt; + wire [2 : 0] bram_2_serverAdapterB_cnt$D_IN; + wire bram_2_serverAdapterB_cnt$EN; + + // register bram_2_serverAdapterB_s1 + reg [1 : 0] bram_2_serverAdapterB_s1; + wire [1 : 0] bram_2_serverAdapterB_s1$D_IN; + wire bram_2_serverAdapterB_s1$EN; + + // register bram_3_serverAdapterA_cnt + reg [2 : 0] bram_3_serverAdapterA_cnt; + wire [2 : 0] bram_3_serverAdapterA_cnt$D_IN; + wire bram_3_serverAdapterA_cnt$EN; + + // register bram_3_serverAdapterA_s1 + reg [1 : 0] bram_3_serverAdapterA_s1; + wire [1 : 0] bram_3_serverAdapterA_s1$D_IN; + wire bram_3_serverAdapterA_s1$EN; + + // register bram_3_serverAdapterB_cnt + reg [2 : 0] bram_3_serverAdapterB_cnt; + wire [2 : 0] bram_3_serverAdapterB_cnt$D_IN; + wire bram_3_serverAdapterB_cnt$EN; + + // register bram_3_serverAdapterB_s1 + reg [1 : 0] bram_3_serverAdapterB_s1; + wire [1 : 0] bram_3_serverAdapterB_s1$D_IN; + wire bram_3_serverAdapterB_s1$EN; // register dmaDoneTime reg [63 : 0] dmaDoneTime; @@ -961,10 +961,10 @@ module mkOCDP16B(pciDevice, reg tlp_inIgnorePkt; wire tlp_inIgnorePkt$D_IN, tlp_inIgnorePkt$EN; - // register tlp_lastMetaV - reg [31 : 0] tlp_lastMetaV; - wire [31 : 0] tlp_lastMetaV$D_IN; - wire tlp_lastMetaV$EN; + // register tlp_lastMetaV_0 + reg [31 : 0] tlp_lastMetaV_0; + wire [31 : 0] tlp_lastMetaV_0$D_IN; + wire tlp_lastMetaV_0$EN; // register tlp_lastMetaV_1 reg [31 : 0] tlp_lastMetaV_1; @@ -1177,10 +1177,10 @@ module mkOCDP16B(pciDevice, wire [1 : 0] wci_reqF_countReg$D_IN; wire wci_reqF_countReg$EN; - // register wci_respF_c_r - reg [1 : 0] wci_respF_c_r; - wire [1 : 0] wci_respF_c_r$D_IN; - wire wci_respF_c_r$EN; + // register wci_respF_cntr_r + reg [1 : 0] wci_respF_cntr_r; + wire [1 : 0] wci_respF_cntr_r$D_IN; + wire wci_respF_cntr_r$EN; // register wci_respF_q_0 reg [33 : 0] wci_respF_q_0; @@ -1335,10 +1335,10 @@ module mkOCDP16B(pciDevice, reg wmi_wmi_reqF_levelsValid; wire wmi_wmi_reqF_levelsValid$D_IN, wmi_wmi_reqF_levelsValid$EN; - // register wmi_wmi_respF_c_r - reg [1 : 0] wmi_wmi_respF_c_r; - wire [1 : 0] wmi_wmi_respF_c_r$D_IN; - wire wmi_wmi_respF_c_r$EN; + // register wmi_wmi_respF_cntr_r + reg [1 : 0] wmi_wmi_respF_cntr_r; + wire [1 : 0] wmi_wmi_respF_cntr_r$D_IN; + wire wmi_wmi_respF_cntr_r$EN; // register wmi_wmi_respF_q_0 reg [129 : 0] wmi_wmi_respF_q_0; @@ -1390,110 +1390,113 @@ module mkOCDP16B(pciDevice, reg wti_operateD; wire wti_operateD$D_IN, wti_operateD$EN; - // ports of submodule bram_memory - reg [31 : 0] bram_memory$DIA, bram_memory$DIB; - reg [10 : 0] bram_memory$ADDRA, bram_memory$ADDRB; - wire [31 : 0] bram_memory$DOA, bram_memory$DOB; - wire bram_memory$ENA, bram_memory$ENB, bram_memory$WEA, bram_memory$WEB; - - // ports of submodule bram_memory_1 - reg [31 : 0] bram_memory_1$DIA, bram_memory_1$DIB; - reg [10 : 0] bram_memory_1$ADDRA, bram_memory_1$ADDRB; - wire [31 : 0] bram_memory_1$DOA, bram_memory_1$DOB; - wire bram_memory_1$ENA, - bram_memory_1$ENB, - bram_memory_1$WEA, - bram_memory_1$WEB; - - // ports of submodule bram_memory_2 - reg [31 : 0] bram_memory_2$DIA, bram_memory_2$DIB; - reg [10 : 0] bram_memory_2$ADDRA, bram_memory_2$ADDRB; - wire [31 : 0] bram_memory_2$DOA, bram_memory_2$DOB; - wire bram_memory_2$ENA, - bram_memory_2$ENB, - bram_memory_2$WEA, - bram_memory_2$WEB; - - // ports of submodule bram_memory_3 - reg [31 : 0] bram_memory_3$DIA, bram_memory_3$DIB; - reg [10 : 0] bram_memory_3$ADDRA, bram_memory_3$ADDRB; - wire [31 : 0] bram_memory_3$DOA, bram_memory_3$DOB; - wire bram_memory_3$ENA, - bram_memory_3$ENB, - bram_memory_3$WEA, - bram_memory_3$WEB; - - // ports of submodule bram_serverAdapterA_1_outDataCore - wire [31 : 0] bram_serverAdapterA_1_outDataCore$D_IN, - bram_serverAdapterA_1_outDataCore$D_OUT; - wire bram_serverAdapterA_1_outDataCore$CLR, - bram_serverAdapterA_1_outDataCore$DEQ, - bram_serverAdapterA_1_outDataCore$EMPTY_N, - bram_serverAdapterA_1_outDataCore$ENQ, - bram_serverAdapterA_1_outDataCore$FULL_N; - - // ports of submodule bram_serverAdapterA_2_outDataCore - wire [31 : 0] bram_serverAdapterA_2_outDataCore$D_IN, - bram_serverAdapterA_2_outDataCore$D_OUT; - wire bram_serverAdapterA_2_outDataCore$CLR, - bram_serverAdapterA_2_outDataCore$DEQ, - bram_serverAdapterA_2_outDataCore$EMPTY_N, - bram_serverAdapterA_2_outDataCore$ENQ, - bram_serverAdapterA_2_outDataCore$FULL_N; - - // ports of submodule bram_serverAdapterA_3_outDataCore - wire [31 : 0] bram_serverAdapterA_3_outDataCore$D_IN, - bram_serverAdapterA_3_outDataCore$D_OUT; - wire bram_serverAdapterA_3_outDataCore$CLR, - bram_serverAdapterA_3_outDataCore$DEQ, - bram_serverAdapterA_3_outDataCore$EMPTY_N, - bram_serverAdapterA_3_outDataCore$ENQ, - bram_serverAdapterA_3_outDataCore$FULL_N; - - // ports of submodule bram_serverAdapterA_outDataCore - wire [31 : 0] bram_serverAdapterA_outDataCore$D_IN, - bram_serverAdapterA_outDataCore$D_OUT; - wire bram_serverAdapterA_outDataCore$CLR, - bram_serverAdapterA_outDataCore$DEQ, - bram_serverAdapterA_outDataCore$EMPTY_N, - bram_serverAdapterA_outDataCore$ENQ, - bram_serverAdapterA_outDataCore$FULL_N; - - // ports of submodule bram_serverAdapterB_1_outDataCore - wire [31 : 0] bram_serverAdapterB_1_outDataCore$D_IN, - bram_serverAdapterB_1_outDataCore$D_OUT; - wire bram_serverAdapterB_1_outDataCore$CLR, - bram_serverAdapterB_1_outDataCore$DEQ, - bram_serverAdapterB_1_outDataCore$EMPTY_N, - bram_serverAdapterB_1_outDataCore$ENQ, - bram_serverAdapterB_1_outDataCore$FULL_N; - - // ports of submodule bram_serverAdapterB_2_outDataCore - wire [31 : 0] bram_serverAdapterB_2_outDataCore$D_IN, - bram_serverAdapterB_2_outDataCore$D_OUT; - wire bram_serverAdapterB_2_outDataCore$CLR, - bram_serverAdapterB_2_outDataCore$DEQ, - bram_serverAdapterB_2_outDataCore$EMPTY_N, - bram_serverAdapterB_2_outDataCore$ENQ, - bram_serverAdapterB_2_outDataCore$FULL_N; - - // ports of submodule bram_serverAdapterB_3_outDataCore - wire [31 : 0] bram_serverAdapterB_3_outDataCore$D_IN, - bram_serverAdapterB_3_outDataCore$D_OUT; - wire bram_serverAdapterB_3_outDataCore$CLR, - bram_serverAdapterB_3_outDataCore$DEQ, - bram_serverAdapterB_3_outDataCore$EMPTY_N, - bram_serverAdapterB_3_outDataCore$ENQ, - bram_serverAdapterB_3_outDataCore$FULL_N; - - // ports of submodule bram_serverAdapterB_outDataCore - wire [31 : 0] bram_serverAdapterB_outDataCore$D_IN, - bram_serverAdapterB_outDataCore$D_OUT; - wire bram_serverAdapterB_outDataCore$CLR, - bram_serverAdapterB_outDataCore$DEQ, - bram_serverAdapterB_outDataCore$EMPTY_N, - bram_serverAdapterB_outDataCore$ENQ, - bram_serverAdapterB_outDataCore$FULL_N; + // ports of submodule bram_0_memory + reg [31 : 0] bram_0_memory$DIA, bram_0_memory$DIB; + reg [10 : 0] bram_0_memory$ADDRA, bram_0_memory$ADDRB; + wire [31 : 0] bram_0_memory$DOA, bram_0_memory$DOB; + wire bram_0_memory$ENA, + bram_0_memory$ENB, + bram_0_memory$WEA, + bram_0_memory$WEB; + + // ports of submodule bram_0_serverAdapterA_outDataCore + wire [31 : 0] bram_0_serverAdapterA_outDataCore$D_IN, + bram_0_serverAdapterA_outDataCore$D_OUT; + wire bram_0_serverAdapterA_outDataCore$CLR, + bram_0_serverAdapterA_outDataCore$DEQ, + bram_0_serverAdapterA_outDataCore$EMPTY_N, + bram_0_serverAdapterA_outDataCore$ENQ, + bram_0_serverAdapterA_outDataCore$FULL_N; + + // ports of submodule bram_0_serverAdapterB_outDataCore + wire [31 : 0] bram_0_serverAdapterB_outDataCore$D_IN, + bram_0_serverAdapterB_outDataCore$D_OUT; + wire bram_0_serverAdapterB_outDataCore$CLR, + bram_0_serverAdapterB_outDataCore$DEQ, + bram_0_serverAdapterB_outDataCore$EMPTY_N, + bram_0_serverAdapterB_outDataCore$ENQ, + bram_0_serverAdapterB_outDataCore$FULL_N; + + // ports of submodule bram_1_memory + reg [31 : 0] bram_1_memory$DIA, bram_1_memory$DIB; + reg [10 : 0] bram_1_memory$ADDRA, bram_1_memory$ADDRB; + wire [31 : 0] bram_1_memory$DOA, bram_1_memory$DOB; + wire bram_1_memory$ENA, + bram_1_memory$ENB, + bram_1_memory$WEA, + bram_1_memory$WEB; + + // ports of submodule bram_1_serverAdapterA_outDataCore + wire [31 : 0] bram_1_serverAdapterA_outDataCore$D_IN, + bram_1_serverAdapterA_outDataCore$D_OUT; + wire bram_1_serverAdapterA_outDataCore$CLR, + bram_1_serverAdapterA_outDataCore$DEQ, + bram_1_serverAdapterA_outDataCore$EMPTY_N, + bram_1_serverAdapterA_outDataCore$ENQ, + bram_1_serverAdapterA_outDataCore$FULL_N; + + // ports of submodule bram_1_serverAdapterB_outDataCore + wire [31 : 0] bram_1_serverAdapterB_outDataCore$D_IN, + bram_1_serverAdapterB_outDataCore$D_OUT; + wire bram_1_serverAdapterB_outDataCore$CLR, + bram_1_serverAdapterB_outDataCore$DEQ, + bram_1_serverAdapterB_outDataCore$EMPTY_N, + bram_1_serverAdapterB_outDataCore$ENQ, + bram_1_serverAdapterB_outDataCore$FULL_N; + + // ports of submodule bram_2_memory + reg [31 : 0] bram_2_memory$DIA, bram_2_memory$DIB; + reg [10 : 0] bram_2_memory$ADDRA, bram_2_memory$ADDRB; + wire [31 : 0] bram_2_memory$DOA, bram_2_memory$DOB; + wire bram_2_memory$ENA, + bram_2_memory$ENB, + bram_2_memory$WEA, + bram_2_memory$WEB; + + // ports of submodule bram_2_serverAdapterA_outDataCore + wire [31 : 0] bram_2_serverAdapterA_outDataCore$D_IN, + bram_2_serverAdapterA_outDataCore$D_OUT; + wire bram_2_serverAdapterA_outDataCore$CLR, + bram_2_serverAdapterA_outDataCore$DEQ, + bram_2_serverAdapterA_outDataCore$EMPTY_N, + bram_2_serverAdapterA_outDataCore$ENQ, + bram_2_serverAdapterA_outDataCore$FULL_N; + + // ports of submodule bram_2_serverAdapterB_outDataCore + wire [31 : 0] bram_2_serverAdapterB_outDataCore$D_IN, + bram_2_serverAdapterB_outDataCore$D_OUT; + wire bram_2_serverAdapterB_outDataCore$CLR, + bram_2_serverAdapterB_outDataCore$DEQ, + bram_2_serverAdapterB_outDataCore$EMPTY_N, + bram_2_serverAdapterB_outDataCore$ENQ, + bram_2_serverAdapterB_outDataCore$FULL_N; + + // ports of submodule bram_3_memory + reg [31 : 0] bram_3_memory$DIA, bram_3_memory$DIB; + reg [10 : 0] bram_3_memory$ADDRA, bram_3_memory$ADDRB; + wire [31 : 0] bram_3_memory$DOA, bram_3_memory$DOB; + wire bram_3_memory$ENA, + bram_3_memory$ENB, + bram_3_memory$WEA, + bram_3_memory$WEB; + + // ports of submodule bram_3_serverAdapterA_outDataCore + wire [31 : 0] bram_3_serverAdapterA_outDataCore$D_IN, + bram_3_serverAdapterA_outDataCore$D_OUT; + wire bram_3_serverAdapterA_outDataCore$CLR, + bram_3_serverAdapterA_outDataCore$DEQ, + bram_3_serverAdapterA_outDataCore$EMPTY_N, + bram_3_serverAdapterA_outDataCore$ENQ, + bram_3_serverAdapterA_outDataCore$FULL_N; + + // ports of submodule bram_3_serverAdapterB_outDataCore + wire [31 : 0] bram_3_serverAdapterB_outDataCore$D_IN, + bram_3_serverAdapterB_outDataCore$D_OUT; + wire bram_3_serverAdapterB_outDataCore$CLR, + bram_3_serverAdapterB_outDataCore$DEQ, + bram_3_serverAdapterB_outDataCore$EMPTY_N, + bram_3_serverAdapterB_outDataCore$ENQ, + bram_3_serverAdapterB_outDataCore$FULL_N; // ports of submodule tlp_inF wire [152 : 0] tlp_inF$D_IN, tlp_inF$D_OUT; @@ -1586,14 +1589,15 @@ module mkOCDP16B(pciDevice, WILL_FIRE_RL_bml_lclAdvance, WILL_FIRE_RL_bml_lcredit, WILL_FIRE_RL_bml_remAdvance, - WILL_FIRE_RL_bram_serverAdapterA_1_outData_enqAndDeq, - WILL_FIRE_RL_bram_serverAdapterA_2_outData_enqAndDeq, - WILL_FIRE_RL_bram_serverAdapterA_3_outData_enqAndDeq, - WILL_FIRE_RL_bram_serverAdapterA_outData_enqAndDeq, - WILL_FIRE_RL_bram_serverAdapterB_1_outData_enqAndDeq, - WILL_FIRE_RL_bram_serverAdapterB_2_outData_enqAndDeq, - WILL_FIRE_RL_bram_serverAdapterB_3_outData_enqAndDeq, - WILL_FIRE_RL_bram_serverAdapterB_outData_enqAndDeq, + WILL_FIRE_RL_bram_0_serverAdapterA_outData_enqAndDeq, + WILL_FIRE_RL_bram_0_serverAdapterB_outData_enqAndDeq, + WILL_FIRE_RL_bram_1_serverAdapterA_outData_enqAndDeq, + WILL_FIRE_RL_bram_1_serverAdapterB_outData_enqAndDeq, + WILL_FIRE_RL_bram_2_serverAdapterA_outData_enqAndDeq, + WILL_FIRE_RL_bram_2_serverAdapterA_outData_setFirstEnq, + WILL_FIRE_RL_bram_2_serverAdapterB_outData_enqAndDeq, + WILL_FIRE_RL_bram_3_serverAdapterA_outData_enqAndDeq, + WILL_FIRE_RL_bram_3_serverAdapterB_outData_enqAndDeq, WILL_FIRE_RL_tlp_dataXmt_Body, WILL_FIRE_RL_tlp_dataXmt_Header, WILL_FIRE_RL_tlp_dmaPullRequestFarMesg, @@ -1644,14 +1648,14 @@ module mkOCDP16B(pciDevice, // inputs to muxes for submodule ports reg [33 : 0] MUX_wci_respF_q_0$write_1__VAL_2; - reg [10 : 0] MUX_bram_memory$a_put_2__VAL_3, - MUX_bram_memory$a_put_2__VAL_4, - MUX_bram_memory_1$a_put_2__VAL_3, - MUX_bram_memory_1$a_put_2__VAL_4, - MUX_bram_memory_2$a_put_2__VAL_3, - MUX_bram_memory_2$a_put_2__VAL_4, - MUX_bram_memory_3$a_put_2__VAL_3, - MUX_bram_memory_3$a_put_2__VAL_4; + reg [10 : 0] MUX_bram_0_memory$a_put_2__VAL_1, + MUX_bram_0_memory$a_put_2__VAL_4, + MUX_bram_1_memory$a_put_2__VAL_1, + MUX_bram_1_memory$a_put_2__VAL_4, + MUX_bram_2_memory$a_put_2__VAL_1, + MUX_bram_2_memory$a_put_2__VAL_4, + MUX_bram_3_memory$a_put_2__VAL_1, + MUX_bram_3_memory$a_put_2__VAL_4; wire [152 : 0] MUX_tlp_outF$enq_1__VAL_1, MUX_tlp_outF$enq_1__VAL_2, MUX_tlp_outF$enq_1__VAL_3, @@ -1682,11 +1686,11 @@ module mkOCDP16B(pciDevice, MUX_bml_fabFlowAddr$write_1__VAL_3, MUX_bml_fabMesgAddr$write_1__VAL_1, MUX_bml_fabMetaAddr$write_1__VAL_1, - MUX_bram_memory$a_put_3__VAL_1, - MUX_bram_memory$a_put_3__VAL_3, - MUX_bram_memory_1$a_put_3__VAL_3, - MUX_bram_memory_2$a_put_3__VAL_3, - MUX_bram_memory_3$a_put_3__VAL_3, + MUX_bram_0_memory$a_put_3__VAL_1, + MUX_bram_0_memory$a_put_3__VAL_2, + MUX_bram_1_memory$a_put_3__VAL_1, + MUX_bram_2_memory$a_put_3__VAL_1, + MUX_bram_3_memory$a_put_3__VAL_1, MUX_tlp_fabMesgAccu$write_1__VAL_2, MUX_tlp_fabMesgAccu$write_1__VAL_3, MUX_tlp_srcMesgAccu$write_1__VAL_2, @@ -1724,7 +1728,7 @@ module mkOCDP16B(pciDevice, MUX_tlp_tlpBRAM_readNxtDWAddr$write_1__VAL_2, MUX_tlp_tlpBRAM_writeDWAddr$write_1__VAL_1, MUX_tlp_tlpBRAM_writeDWAddr$write_1__VAL_2; - wire [10 : 0] MUX_bram_memory$b_put_2__VAL_2; + wire [10 : 0] MUX_bram_0_memory$b_put_2__VAL_2; wire [9 : 0] MUX_tlp_dmaPullRemainDWLen$write_1__VAL_2, MUX_tlp_dmaPullRemainDWLen$write_1__VAL_3, MUX_tlp_dmaPullRemainDWSub$write_1__VAL_1, @@ -1742,29 +1746,27 @@ module mkOCDP16B(pciDevice, MUX_tlp_lastRuleFired$write_1__VAL_3, MUX_tlp_postSeqDwell$write_1__VAL_1, MUX_tlp_postSeqDwell$write_1__VAL_2; - wire [1 : 0] MUX_wci_respF_c_r$write_1__VAL_1, - MUX_wci_respF_c_r$write_1__VAL_2, + wire [1 : 0] MUX_wci_respF_cntr_r$write_1__VAL_2, MUX_wmi_bufDwell$write_1__VAL_3, - MUX_wmi_wmi_respF_c_r$write_1__VAL_1, - MUX_wmi_wmi_respF_c_r$write_1__VAL_2; + MUX_wmi_wmi_respF_cntr_r$write_1__VAL_2; wire MUX_bml_fabBufsAvail$write_1__SEL_1, MUX_bml_fabFlowAddr$write_1__SEL_1, MUX_bml_lclBufsAR$write_1__SEL_1, MUX_bml_lclBufsCF$write_1__SEL_1, MUX_bml_lclCredit$write_1__SEL_1, - MUX_bram_memory$a_put_1__SEL_1, - MUX_bram_memory$a_put_1__SEL_2, - MUX_bram_memory$a_put_1__SEL_3, - MUX_bram_memory_1$a_put_1__SEL_1, - MUX_bram_memory_1$a_put_1__SEL_2, - MUX_bram_memory_1$a_put_1__SEL_3, - MUX_bram_memory_2$a_put_1__SEL_1, - MUX_bram_memory_2$a_put_1__SEL_2, - MUX_bram_memory_2$a_put_1__SEL_3, - MUX_bram_memory_3$a_put_1__SEL_1, - MUX_bram_memory_3$a_put_1__SEL_2, - MUX_bram_memory_3$a_put_1__SEL_3, - MUX_bram_serverAdapterB_1_writeWithResp$wset_1__SEL_1, + MUX_bram_0_memory$a_put_1__SEL_1, + MUX_bram_0_memory$a_put_1__SEL_2, + MUX_bram_0_memory$a_put_1__SEL_3, + MUX_bram_0_serverAdapterB_writeWithResp$wset_1__SEL_1, + MUX_bram_1_memory$a_put_1__SEL_1, + MUX_bram_1_memory$a_put_1__SEL_2, + MUX_bram_1_memory$a_put_1__SEL_3, + MUX_bram_2_memory$a_put_1__SEL_1, + MUX_bram_2_memory$a_put_1__SEL_2, + MUX_bram_2_memory$a_put_1__SEL_3, + MUX_bram_3_memory$a_put_1__SEL_1, + MUX_bram_3_memory$a_put_1__SEL_2, + MUX_bram_3_memory$a_put_1__SEL_3, MUX_tlp_dmaDoTailEvent$write_1__VAL_1, MUX_tlp_fabMesgAccu$write_1__SEL_1, MUX_tlp_fabMeta$write_1__SEL_2, @@ -1772,10 +1774,10 @@ module mkOCDP16B(pciDevice, MUX_tlp_reqMesgInFlight$write_1__VAL_2, MUX_tlp_tailEventF$enq_1__SEL_1, MUX_tlp_tlpBRAM_mReqF$enq_1__SEL_1, - MUX_tlp_tlpBRAM_mReqF$enq_1__SEL_6, + MUX_tlp_tlpBRAM_mReqF$enq_1__SEL_2, MUX_tlp_tlpBRAM_readHeaderSent$write_1__SEL_1, MUX_tlp_tlpBRAM_readStarted$write_1__SEL_1, - MUX_tlp_tlpXmtBusy$write_1__PSEL_4, + MUX_tlp_tlpXmtBusy$write_1__PSEL_2, MUX_tlp_tlpXmtBusy$write_1__SEL_1, MUX_tlp_tlpXmtBusy$write_1__SEL_2, MUX_tlp_tlpXmtBusy$write_1__SEL_3, @@ -1786,7 +1788,9 @@ module mkOCDP16B(pciDevice, MUX_wci_illegalEdge$write_1__SEL_1, MUX_wci_illegalEdge$write_1__SEL_2, MUX_wci_illegalEdge$write_1__VAL_2, + MUX_wci_respF_q_0$write_1__SEL_1, MUX_wci_respF_q_0$write_1__SEL_2, + MUX_wci_respF_q_1$write_1__SEL_1, MUX_wci_respF_q_1$write_1__SEL_2, MUX_wmi_bufDwell$write_1__SEL_1, MUX_wmi_bytesRemainResp$write_1__SEL_1, @@ -1796,231 +1800,234 @@ module mkOCDP16B(pciDevice, MUX_wmi_wmi_dhF_levelsValid$write_1__SEL_2, MUX_wmi_wmi_mFlagF_levelsValid$write_1__SEL_2, MUX_wmi_wmi_reqF_levelsValid$write_1__SEL_2, + MUX_wmi_wmi_respF_q_0$write_1__SEL_1, MUX_wmi_wmi_respF_q_0$write_1__SEL_2, + MUX_wmi_wmi_respF_q_1$write_1__SEL_1, MUX_wmi_wmi_respF_q_1$write_1__SEL_2, MUX_wmi_wrActive$write_1__SEL_1, MUX_wmi_wrFinalize$write_1__SEL_1; // remaining internal signals - reg [63 : 0] v__h15697, - v__h15872, - v__h16016, - v__h39702, - v__h41753, - v__h46039, - v__h46380, - v__h47001, - v__h47351, - v__h48586, - v__h54850, - v__h54974, - v__h55182, - v__h55645, - v__h57878, - v__h62195, - v__h62717, - v__h63372, - v__h63720, - v__h63884, - v__h69047, - v__h80879, - v__h89794, - v__h90263, - v__h90426; - reg [31 : 0] IF_0_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2477, - IF_1_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2478, - IF_2_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2479, - IF_3_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2480, - IF_tlp_tlpBRAM_readReq_first__97_BITS_30_TO_29_ETC___d2397, - _theResult____h90410; - reg [15 : 0] CASE_tlp_outDwRemain_BITS_1_TO_0_0xFFF0_0b0_0x_ETC__q4; - reg [3 : 0] CASE_tlp_lastRuleFired_10_1_tlp_lastRuleFired__ETC__q1; - reg [1 : 0] lowAddr10__h28410, x__h28539, x__h28562; - reg CASE_dpControl_BITS_1_TO_0_NOT_bml_fabDone_0_N_ETC__q5, - CASE_dpControl_BITS_1_TO_0_NOT_bml_fabDone_0_N_ETC__q8, - CASE_dpControl_BITS_1_TO_0_bml_fabDone_0_bml_f_ETC__q3, - CASE_tlp_tlpBRAM_mReqFD_OUT_BITS_30_TO_29_NOT_ETC__q7, - CASE_tlp_tlpBRAM_mReqFD_OUT_BITS_51_TO_50_NOT_ETC__q6, - CASE_tlp_tlpBRAM_readReqD_OUT_BITS_30_TO_29_N_ETC__q17, - IF_0_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2431, - IF_0_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d675, - IF_1_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2432, - IF_1_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d685, - IF_2_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2433, - IF_2_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d695, - IF_3_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2434, - IF_3_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d705, - IF_bml_dpControl_wget__008_BITS_1_TO_0_014_EQ__ETC___d2085, - IF_tlp_tlpBRAM_readReq_first__97_BITS_30_TO_29_ETC___d912; - wire [127 : 0] IF_tlp_fabMesgAddrMS_186_EQ_0_187_THEN_0_ELSE__ETC___d1461, - IF_tlp_fabMetaAddrMS_265_EQ_0_266_THEN_4_ELSE__ETC___d1356, - IF_tlp_tlpBRAM_readReq_first__97_BITS_30_TO_29_ETC___d1037, - IF_tlp_tlpBRAM_readReq_first__97_BITS_30_TO_29_ETC___d1042, - pkt__h70068, - rdata__h33850, - rdata__h82127, - w_data__h46507, - w_data__h46644, - w_data__h51409, - w_data__h64198, - w_data__h65286, - w_data__h65532; + reg [63 : 0] v__h15577, + v__h15752, + v__h15896, + v__h41005, + v__h43090, + v__h47450, + v__h47790, + v__h48409, + v__h48757, + v__h50007, + v__h56382, + v__h56506, + v__h56714, + v__h57177, + v__h59442, + v__h63835, + v__h64356, + v__h65011, + v__h65359, + v__h65522, + v__h70765, + v__h82455, + v__h91331, + v__h91800, + v__h91963; + reg [31 : 0] SEL_ARR_bram_0_serverAdapterA_outData_outData__ETC___d863, + SEL_ARR_tlp_tlpBRAM_mReqF_first__16_BITS_127_T_ETC___d700, + SEL_ARR_tlp_tlpBRAM_mReqF_first__16_BITS_127_T_ETC___d708, + SEL_ARR_tlp_tlpBRAM_mReqF_first__16_BITS_127_T_ETC___d716, + SEL_ARR_tlp_tlpBRAM_mReqF_first__16_BITS_127_T_ETC___d724, + _theResult____h91947; + reg [15 : 0] CASE_tlp_outDwRemain_BITS_1_TO_0_0b0_0xFFFF_0b_ETC__q3; + reg [3 : 0] CASE_tlp_lastRuleFired_1_tlp_lastRuleFired_2_t_ETC__q1; + reg [1 : 0] lowAddr10__h29651, x__h29780, x__h29803; + reg CASE_dpControl_BITS_1_TO_0_0_NOT_bml_fabDone_1_ETC__q5, + CASE_dpControl_BITS_1_TO_0_0_NOT_bml_fabDone_1_ETC__q6, + CASE_dpControl_BITS_1_TO_0_0_bml_fabDone_1_IF__ETC__q7, + CASE_dpControl_BITS_1_TO_0_0_bml_fabDone_1_bml_ETC__q4, + CASE_tlp_tlpBRAM_mReqF_first__16_BITS_30_TO_29_ETC___d736, + CASE_tlp_tlpBRAM_mReqF_first__16_BITS_51_TO_50_ETC___d623, + CASE_tlp_tlpBRAM_readReq_first__98_BITS_30_TO__ETC___d805, + CASE_tlp_tlpBRAM_readReq_first__98_BITS_30_TO__ETC___d810, + SEL_ARR_NOT_tlp_tlpBRAM_writeRemainDWLen_52_EQ_ETC___d665, + SEL_ARR_NOT_tlp_tlpBRAM_writeRemainDWLen_52_EQ_ETC___d669, + SEL_ARR_NOT_tlp_tlpBRAM_writeRemainDWLen_52_EQ_ETC___d673, + SEL_ARR_NOT_tlp_tlpBRAM_writeRemainDWLen_52_EQ_ETC___d677; + wire [127 : 0] IF_tlp_fabMesgAddrMS_078_EQ_0_079_THEN_0_ELSE__ETC___d1353, + IF_tlp_fabMetaAddrMS_157_EQ_0_158_THEN_4_ELSE__ETC___d1248, + IF_tlp_tlpBRAM_readReq_first__98_BITS_30_TO_29_ETC___d929, + IF_tlp_tlpBRAM_readReq_first__98_BITS_30_TO_29_ETC___d934, + pkt__h71785, + rdata__h35173, + rdata__h83703, + w_data__h47916, + w_data__h48052, + w_data__h52877, + w_data__h65836, + w_data__h66940, + w_data__h67186; wire [63 : 0] wti_nowReq_BITS_63_TO_0__q2; - wire [31 : 0] bml_fabFlowAddr_047_PLUS_bml_fabFlowSize_048___d2624, - mesgMeta_opcode__h80277, - nowLS__h44844, - nowLS__h60998, - nowMS__h43901, - nowMS__h60057, - opcode__h42670, - opcode__h58837, - rdat__h90489, - rdat__h90497, - rdat__h90505, - rdat__h90513, - rdat__h90521, - rdat__h90529, - rdat__h90537, - rdat__h90558, - rdat__h90565, - rdat__h90578, - rdat__h90585, - rdat__h90592, - rdat__h90856, - rdat__h90906, - rdat__h91006, - rdat__h91064, - rdat__h91086, - rdat__h91096, - rdat__h91218, - rdat__h91339, - rdat__h91368, - rdat__h91397, - rdat__h91426, - rdat__h91456, - rdat__h91490, - rdat__h91523, - rdat__h91557, - rresp_data__h28457, - x3__h80237, - x__h40887, - x__h45847, - x__h56804, - x__h61968, - y__h46213, - y__h46773, - y__h62350; - wire [16 : 0] tlp_mesgLengthRemainPull_PLUS_3__q15, - tlp_mesgLengthRemainPush_PLUS_3__q16, - x__h46132, - x__h62287, - y__h46119, - y__h46134, - y__h62279, - y__h62289, - y__h63671; - wire [15 : 0] w_be__h47101, - x__h87138, - x__h88266, - x__h88271, - x__h88378, - x__h88415, - x__h88497, - x__h88502, - x__h88536, - x__h88541, - y__h46261, - y__h62959; - wire [12 : 0] spanToNextPage__h46093, - spanToNextPage__h62253, - thisRequestLength__h46094, - thisRequestLength__h62254, - tlp_tlpBRAM_readNxtDWAddr_PLUS_1__q13, - tlp_tlpBRAM_readNxtDWAddr_PLUS_2__q14, - tlp_tlpBRAM_readNxtDWAddr_PLUS_3__q12, - tlp_tlpBRAM_writeDWAddr_PLUS_1__q10, - tlp_tlpBRAM_writeDWAddr_PLUS_2__q11, - tlp_tlpBRAM_writeDWAddr_PLUS_3__q9, - y__h17488, - y__h26049; - wire [11 : 0] byteCount__h28412, x__h28530, x__h28532, y__h28531, y__h28533; - wire [9 : 0] y__h17555, y__h26037, y__h29472, y__h46739; - wire [7 : 0] rreq_tag__h46309, tag__h62529, tagm__h62748; - wire [6 : 0] lowAddr__h28411; - wire [3 : 0] lastBE__h46542, lastBE__h62561; - wire [2 : 0] bram_serverAdapterA_1_cnt_44_PLUS_IF_bram_serv_ETC___d150, - bram_serverAdapterA_2_cnt_62_PLUS_IF_bram_serv_ETC___d268, - bram_serverAdapterA_3_cnt_80_PLUS_IF_bram_serv_ETC___d386, - bram_serverAdapterA_cnt_6_PLUS_IF_bram_serverA_ETC___d32, - bram_serverAdapterB_1_cnt_03_PLUS_IF_bram_serv_ETC___d209, - bram_serverAdapterB_2_cnt_21_PLUS_IF_bram_serv_ETC___d327, - bram_serverAdapterB_3_cnt_39_PLUS_IF_bram_serv_ETC___d445, - bram_serverAdapterB_cnt_5_PLUS_IF_bram_serverA_ETC___d91; - wire [1 : 0] ab__h10453, - ab__h11857, - ab__h1613, - ab__h3019, - ab__h4561, - ab__h5965, - ab__h7507, - ab__h8911, - idx__h19187, - idx__h21418, - idx__h22722, - idx__h24026, - idx__h26267, - idx__h26735, - idx__h27108, - idx__h27481, - tlp_tlpBRAM_readReq_first__97_BITS_30_TO_29_99_ETC___d2404; - wire IF_1_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d708, - IF_tlp_tlpBRAM_readReq_first__97_BITS_30_TO_29_ETC___d921, - NOT_bml_lclBufDone_032_099_AND_IF_bml_dpContro_ETC___d2112, - NOT_wmi_wrActive_827_828_OR_NOT_wmi_rdActive_8_ETC___d1837, + wire [31 : 0] bml_fabFlowAddr_937_PLUS_bml_fabFlowSize_938___d1939, + mesgMeta_opcode__h81853, + nowLS__h46239, + nowLS__h62622, + nowMS__h45280, + nowMS__h61665, + opcode__h44022, + opcode__h60417, + rdat__h92026, + rdat__h92034, + rdat__h92042, + rdat__h92050, + rdat__h92058, + rdat__h92066, + rdat__h92074, + rdat__h92095, + rdat__h92102, + rdat__h92115, + rdat__h92122, + rdat__h92129, + rdat__h92401, + rdat__h92451, + rdat__h92551, + rdat__h92609, + rdat__h92631, + rdat__h92641, + rdat__h92763, + rdat__h92887, + rdat__h92915, + rdat__h92943, + rdat__h92971, + rdat__h93001, + rdat__h93035, + rdat__h93068, + rdat__h93102, + rresp_data__h29698, + x3__h81813, + x__h42208, + x__h47258, + x__h58352, + x__h63608, + y__h47623, + y__h48181, + y__h63989; + wire [16 : 0] tlp_mesgLengthRemainPull_PLUS_3__q14, + tlp_mesgLengthRemainPush_PLUS_3__q15, + x__h47542, + x__h63926, + y__h47529, + y__h47544, + y__h63918, + y__h63928, + y__h65310; + wire [15 : 0] w_be__h48508, + x__h88675, + x__h89803, + x__h89808, + x__h89915, + x__h89952, + x__h90034, + x__h90039, + x__h90073, + x__h90078, + y__h47671, + y__h64598; + wire [12 : 0] spanToNextPage__h47503, + spanToNextPage__h63892, + thisRequestLength__h47504, + thisRequestLength__h63893, + tlp_tlpBRAM_readNxtDWAddr_PLUS_1__q11, + tlp_tlpBRAM_readNxtDWAddr_PLUS_2__q12, + tlp_tlpBRAM_readNxtDWAddr_PLUS_3__q13, + tlp_tlpBRAM_writeDWAddr_PLUS_1__q8, + tlp_tlpBRAM_writeDWAddr_PLUS_2__q9, + tlp_tlpBRAM_writeDWAddr_PLUS_3__q10, + y__h17362, + y__h27665; + wire [11 : 0] byteCount__h29653, x__h29771, x__h29773, y__h29772, y__h29774; + wire [9 : 0] y__h17428, y__h27653, y__h30729, y__h48147; + wire [7 : 0] rreq_tag__h47719, tag__h64168, tagm__h64387; + wire [6 : 0] lowAddr__h29652; + wire [3 : 0] lastBE__h47950, lastBE__h64200; + wire [2 : 0] bram_0_serverAdapterA_cnt_6_PLUS_IF_bram_0_ser_ETC___d32, + bram_0_serverAdapterB_cnt_5_PLUS_IF_bram_0_ser_ETC___d91, + bram_1_serverAdapterA_cnt_44_PLUS_IF_bram_1_se_ETC___d150, + bram_1_serverAdapterB_cnt_03_PLUS_IF_bram_1_se_ETC___d209, + bram_2_serverAdapterA_cnt_62_PLUS_IF_bram_2_se_ETC___d268, + bram_2_serverAdapterB_cnt_21_PLUS_IF_bram_2_se_ETC___d327, + bram_3_serverAdapterA_cnt_80_PLUS_IF_bram_3_se_ETC___d386, + bram_3_serverAdapterB_cnt_39_PLUS_IF_bram_3_se_ETC___d445; + wire [1 : 0] ab__h10465, + ab__h11870, + ab__h1619, + ab__h3026, + ab__h4569, + ab__h5974, + ab__h7517, + ab__h8922, + idx__h21626, + idx__h23676, + idx__h24781, + idx__h25886, + idx__h27879, + idx__h28282, + idx__h28586, + idx__h28890, + tlp_tlpBRAM_readReq_first__98_BITS_30_TO_29_00_ETC___d922, + wci_respF_cntr_r_90_MINUS_1___d499, + wmi_wmi_respF_cntr_r_582_MINUS_1___d1590; + wire IF_bml_dpControl_wget__898_BITS_1_TO_0_904_EQ__ETC___d1984, + IF_bml_dpControl_wget__898_BITS_3_TO_2_899_EQ__ETC___d1995, + NOT_SEL_ARR_NOT_tlp_tlpBRAM_writeRemainDWLen_5_ETC___d681, + NOT_tlp_tlpBRAM_writeRemainDWLen_52_ULE_1_55___d656, + NOT_tlp_tlpBRAM_writeRemainDWLen_52_ULE_2_57___d658, + NOT_tlp_tlpBRAM_writeRemainDWLen_52_ULE_3_59___d660, + NOT_wmi_wrActive_717_718_OR_NOT_wmi_rdActive_7_ETC___d1727, + _dfoo1, + _dfoo3, _dfoo5, - bml_crdBuf_value_990_EQ_bml_crdBuf_modulus_bw__ETC___d2779, - bml_fabBuf_value_975_EQ_bml_fabBuf_modulus_bw__ETC___d2780, - bml_lclBufDone_032_AND_IF_bml_dpControl_wget___ETC___d2443, - bml_lclBuf_value_945_EQ_bml_lclBuf_modulus_bw__ETC___d2798, - bml_remBuf_value_960_EQ_bml_remBuf_modulus_bw__ETC___d2799, - bram_serverAdapterA_1_cnt_44_SLT_3___d2629, - bram_serverAdapterA_2_cnt_62_SLT_3___d2630, - bram_serverAdapterA_2_outDataCore_notEmpty__38_ETC___d993, - bram_serverAdapterA_3_cnt_80_SLT_3___d2631, - bram_serverAdapterA_cnt_6_SLT_3___d2628, - bram_serverAdapterA_outDataCore_notEmpty_OR_br_ETC___d995, - bram_serverAdapterB_1_cnt_03_SLT_3___d1777, - bram_serverAdapterB_1_outData_outData_whas__79_ETC___d1805, - bram_serverAdapterB_2_cnt_21_SLT_3___d1778, - bram_serverAdapterB_3_cnt_39_SLT_3___d1779, - bram_serverAdapterB_cnt_5_SLT_3_776_AND_bram_s_ETC___d1782, - bram_serverAdapterB_cnt_5_SLT_3___d1776, - bram_serverAdapterB_outData_outData_whas__795__ETC___d1807, - hasPull_AND_tlp_dpControl_wget__072_BITS_7_TO__ETC___d1341, - hasPull_AND_tlp_dpControl_wget__072_BITS_7_TO__ETC___d1382, - hasPull_AND_tlp_dpControl_wget__072_BITS_7_TO__ETC___d1434, - hasPull_AND_tlp_dpControl_wget__072_BITS_7_TO__ETC___d1473, - hasPull_AND_tlp_dpControl_wget__072_BITS_7_TO__ETC___d1493, - hasPull_AND_tlp_dpControl_wget__072_BITS_7_TO__ETC___d1518, - hasPush_AND_tlp_dpControl_wget__072_BITS_7_TO__ETC___d1093, - hasPush_AND_tlp_dpControl_wget__072_BITS_7_TO__ETC___d1166, - hasPush_AND_tlp_dpControl_wget__072_BITS_7_TO__ETC___d1206, - hasPush_AND_tlp_dpControl_wget__072_BITS_7_TO__ETC___d1263, - tlp_dmaPullRemainDWLen_481_ULE_tlp_dmaPullRema_ETC___d2625, - tlp_dmaPullRemainDWSub_495_ULE_4___d2626, - tlp_inF_first__367_BITS_63_TO_56_370_EQ_pciDev_ETC___d1380, - tlp_inF_first__367_BIT_152_570_AND_NOT_tlp_inF_ETC___d1595, - tlp_outDwRemain_237_ULE_4___d2557, - tlp_tlpBRAM_mReqF_first__18_BIT_60_02_OR_IF_tl_ETC___d813, - tlp_tlpBRAM_mReqF_first__18_BIT_63_19_OR_IF_tl_ETC___d634, - tlp_tlpBRAM_mRespF_first__108_BITS_71_TO_62_20_ETC___d2405, - tlp_tlpBRAM_rdRespDwRemain_024_ULE_4___d1026, - tlp_tlpBRAM_readRemainDWLen_46_ULE_4___d847, - tlp_tlpBRAM_writeRemainDWLen_62_ULE_1___d2402, - tlp_tlpBRAM_writeRemainDWLen_62_ULE_2___d2403, - tlp_tlpBRAM_writeRemainDWLen_62_ULE_3___d2401, - wmi_wmi_operateD_716_AND_wmi_wmi_peerIsReady_7_ETC___d1887, - wmi_wmi_operateD_716_AND_wmi_wmi_peerIsReady_7_ETC___d1908; + _dfoo7, + _dfoo9, + bml_crdBuf_value_880_EQ_bml_crdBuf_modulus_bw__ETC___d1882, + bml_fabBuf_value_865_EQ_bml_fabBuf_modulus_bw__ETC___d1867, + bml_lclBufDone_922_AND_IF_bml_dpControl_wget___ETC___d2003, + bml_lclBuf_value_835_EQ_bml_lclBuf_modulus_bw__ETC___d1837, + bml_remBuf_value_850_EQ_bml_remBuf_modulus_bw__ETC___d1852, + bram_0_serverAdapterA_cnt_6_SLT_3___d619, + bram_0_serverAdapterA_outDataCore_notEmpty_OR__ETC___d887, + bram_0_serverAdapterB_cnt_5_SLT_3_666_AND_bram_ETC___d1672, + bram_0_serverAdapterB_cnt_5_SLT_3___d1666, + bram_0_serverAdapterB_outData_outData_whas__68_ETC___d1697, + bram_1_serverAdapterA_cnt_44_SLT_3___d620, + bram_1_serverAdapterB_cnt_03_SLT_3___d1667, + bram_1_serverAdapterB_outData_outData_whas__68_ETC___d1695, + bram_2_serverAdapterA_cnt_62_SLT_3___d621, + bram_2_serverAdapterA_outDataCore_notEmpty__38_ETC___d885, + bram_2_serverAdapterB_cnt_21_SLT_3___d1668, + bram_3_serverAdapterA_cnt_80_SLT_3___d622, + bram_3_serverAdapterB_cnt_39_SLT_3___d1669, + hasPull_AND_tlp_dpControl_wget__64_BITS_7_TO_4_ETC___d1233, + hasPull_AND_tlp_dpControl_wget__64_BITS_7_TO_4_ETC___d1274, + hasPull_AND_tlp_dpControl_wget__64_BITS_7_TO_4_ETC___d1326, + hasPull_AND_tlp_dpControl_wget__64_BITS_7_TO_4_ETC___d1365, + hasPull_AND_tlp_dpControl_wget__64_BITS_7_TO_4_ETC___d1385, + hasPull_AND_tlp_dpControl_wget__64_BITS_7_TO_4_ETC___d1410, + hasPush_AND_tlp_dpControl_wget__64_BITS_7_TO_4_ETC___d1058, + hasPush_AND_tlp_dpControl_wget__64_BITS_7_TO_4_ETC___d1098, + hasPush_AND_tlp_dpControl_wget__64_BITS_7_TO_4_ETC___d1155, + hasPush_AND_tlp_dpControl_wget__64_BITS_7_TO_4_ETC___d985, + tlp_dmaPullRemainDWLen_373_ULE_tlp_dmaPullRema_ETC___d1395, + tlp_dmaPullRemainDWSub_387_ULE_4___d1388, + tlp_inF_first__259_BITS_63_TO_56_262_EQ_pciDev_ETC___d1272, + tlp_inF_first__259_BIT_152_462_AND_NOT_tlp_inF_ETC___d1487, + tlp_outDwRemain_129_ULE_4___d1130, + tlp_tlpBRAM_mRespF_first__000_BITS_71_TO_62_10_ETC___d1102, + tlp_tlpBRAM_mRespF_i_notFull__97_AND_tlp_tlpBR_ETC___d813, + tlp_tlpBRAM_rdRespDwRemain_16_ULE_4___d918, + tlp_tlpBRAM_readRemainDWLen_74_ULE_4___d775, + wmi_wmi_operateD_606_AND_wmi_wmi_peerIsReady_6_ETC___d1777, + wmi_wmi_operateD_606_AND_wmi_wmi_peerIsReady_6_ETC___d1798; // value method wci_s_sResp assign wci_s_SResp = wci_respF_q_0[33:32] ; @@ -2072,185 +2079,185 @@ module mkOCDP16B(pciDevice, assign server_response_get = tlp_outF$D_OUT ; assign RDY_server_response_get = tlp_outF$EMPTY_N ; - // submodule bram_memory + // submodule bram_0_memory BRAM2 #(.PIPELINED(1'd0), .ADDR_WIDTH(32'd11), .DATA_WIDTH(32'd32), - .MEMSIZE(12'd2048)) bram_memory(.CLKA(CLK), - .CLKB(CLK), - .ADDRA(bram_memory$ADDRA), - .ADDRB(bram_memory$ADDRB), - .DIA(bram_memory$DIA), - .DIB(bram_memory$DIB), - .WEA(bram_memory$WEA), - .WEB(bram_memory$WEB), - .ENA(bram_memory$ENA), - .ENB(bram_memory$ENB), - .DOA(bram_memory$DOA), - .DOB(bram_memory$DOB)); - - // submodule bram_memory_1 - BRAM2 #(.PIPELINED(1'd0), - .ADDR_WIDTH(32'd11), - .DATA_WIDTH(32'd32), - .MEMSIZE(12'd2048)) bram_memory_1(.CLKA(CLK), - .CLKB(CLK), - .ADDRA(bram_memory_1$ADDRA), - .ADDRB(bram_memory_1$ADDRB), - .DIA(bram_memory_1$DIA), - .DIB(bram_memory_1$DIB), - .WEA(bram_memory_1$WEA), - .WEB(bram_memory_1$WEB), - .ENA(bram_memory_1$ENA), - .ENB(bram_memory_1$ENB), - .DOA(bram_memory_1$DOA), - .DOB(bram_memory_1$DOB)); - - // submodule bram_memory_2 - BRAM2 #(.PIPELINED(1'd0), - .ADDR_WIDTH(32'd11), - .DATA_WIDTH(32'd32), - .MEMSIZE(12'd2048)) bram_memory_2(.CLKA(CLK), - .CLKB(CLK), - .ADDRA(bram_memory_2$ADDRA), - .ADDRB(bram_memory_2$ADDRB), - .DIA(bram_memory_2$DIA), - .DIB(bram_memory_2$DIB), - .WEA(bram_memory_2$WEA), - .WEB(bram_memory_2$WEB), - .ENA(bram_memory_2$ENA), - .ENB(bram_memory_2$ENB), - .DOA(bram_memory_2$DOA), - .DOB(bram_memory_2$DOB)); - - // submodule bram_memory_3 - BRAM2 #(.PIPELINED(1'd0), - .ADDR_WIDTH(32'd11), - .DATA_WIDTH(32'd32), - .MEMSIZE(12'd2048)) bram_memory_3(.CLKA(CLK), + .MEMSIZE(12'd2048)) bram_0_memory(.CLKA(CLK), .CLKB(CLK), - .ADDRA(bram_memory_3$ADDRA), - .ADDRB(bram_memory_3$ADDRB), - .DIA(bram_memory_3$DIA), - .DIB(bram_memory_3$DIB), - .WEA(bram_memory_3$WEA), - .WEB(bram_memory_3$WEB), - .ENA(bram_memory_3$ENA), - .ENB(bram_memory_3$ENB), - .DOA(bram_memory_3$DOA), - .DOB(bram_memory_3$DOB)); - - // submodule bram_serverAdapterA_1_outDataCore + .ADDRA(bram_0_memory$ADDRA), + .ADDRB(bram_0_memory$ADDRB), + .DIA(bram_0_memory$DIA), + .DIB(bram_0_memory$DIB), + .WEA(bram_0_memory$WEA), + .WEB(bram_0_memory$WEB), + .ENA(bram_0_memory$ENA), + .ENB(bram_0_memory$ENB), + .DOA(bram_0_memory$DOA), + .DOB(bram_0_memory$DOB)); + + // submodule bram_0_serverAdapterA_outDataCore SizedFIFO #(.p1width(32'd32), .p2depth(32'd3), .p3cntr_width(32'd1), - .guarded(32'd1)) bram_serverAdapterA_1_outDataCore(.RST(RST_N), + .guarded(32'd1)) bram_0_serverAdapterA_outDataCore(.RST(RST_N), .CLK(CLK), - .D_IN(bram_serverAdapterA_1_outDataCore$D_IN), - .ENQ(bram_serverAdapterA_1_outDataCore$ENQ), - .DEQ(bram_serverAdapterA_1_outDataCore$DEQ), - .CLR(bram_serverAdapterA_1_outDataCore$CLR), - .D_OUT(bram_serverAdapterA_1_outDataCore$D_OUT), - .FULL_N(bram_serverAdapterA_1_outDataCore$FULL_N), - .EMPTY_N(bram_serverAdapterA_1_outDataCore$EMPTY_N)); - - // submodule bram_serverAdapterA_2_outDataCore + .D_IN(bram_0_serverAdapterA_outDataCore$D_IN), + .ENQ(bram_0_serverAdapterA_outDataCore$ENQ), + .DEQ(bram_0_serverAdapterA_outDataCore$DEQ), + .CLR(bram_0_serverAdapterA_outDataCore$CLR), + .D_OUT(bram_0_serverAdapterA_outDataCore$D_OUT), + .FULL_N(bram_0_serverAdapterA_outDataCore$FULL_N), + .EMPTY_N(bram_0_serverAdapterA_outDataCore$EMPTY_N)); + + // submodule bram_0_serverAdapterB_outDataCore SizedFIFO #(.p1width(32'd32), .p2depth(32'd3), .p3cntr_width(32'd1), - .guarded(32'd1)) bram_serverAdapterA_2_outDataCore(.RST(RST_N), + .guarded(32'd1)) bram_0_serverAdapterB_outDataCore(.RST(RST_N), .CLK(CLK), - .D_IN(bram_serverAdapterA_2_outDataCore$D_IN), - .ENQ(bram_serverAdapterA_2_outDataCore$ENQ), - .DEQ(bram_serverAdapterA_2_outDataCore$DEQ), - .CLR(bram_serverAdapterA_2_outDataCore$CLR), - .D_OUT(bram_serverAdapterA_2_outDataCore$D_OUT), - .FULL_N(bram_serverAdapterA_2_outDataCore$FULL_N), - .EMPTY_N(bram_serverAdapterA_2_outDataCore$EMPTY_N)); - - // submodule bram_serverAdapterA_3_outDataCore + .D_IN(bram_0_serverAdapterB_outDataCore$D_IN), + .ENQ(bram_0_serverAdapterB_outDataCore$ENQ), + .DEQ(bram_0_serverAdapterB_outDataCore$DEQ), + .CLR(bram_0_serverAdapterB_outDataCore$CLR), + .D_OUT(bram_0_serverAdapterB_outDataCore$D_OUT), + .FULL_N(bram_0_serverAdapterB_outDataCore$FULL_N), + .EMPTY_N(bram_0_serverAdapterB_outDataCore$EMPTY_N)); + + // submodule bram_1_memory + BRAM2 #(.PIPELINED(1'd0), + .ADDR_WIDTH(32'd11), + .DATA_WIDTH(32'd32), + .MEMSIZE(12'd2048)) bram_1_memory(.CLKA(CLK), + .CLKB(CLK), + .ADDRA(bram_1_memory$ADDRA), + .ADDRB(bram_1_memory$ADDRB), + .DIA(bram_1_memory$DIA), + .DIB(bram_1_memory$DIB), + .WEA(bram_1_memory$WEA), + .WEB(bram_1_memory$WEB), + .ENA(bram_1_memory$ENA), + .ENB(bram_1_memory$ENB), + .DOA(bram_1_memory$DOA), + .DOB(bram_1_memory$DOB)); + + // submodule bram_1_serverAdapterA_outDataCore SizedFIFO #(.p1width(32'd32), .p2depth(32'd3), .p3cntr_width(32'd1), - .guarded(32'd1)) bram_serverAdapterA_3_outDataCore(.RST(RST_N), + .guarded(32'd1)) bram_1_serverAdapterA_outDataCore(.RST(RST_N), .CLK(CLK), - .D_IN(bram_serverAdapterA_3_outDataCore$D_IN), - .ENQ(bram_serverAdapterA_3_outDataCore$ENQ), - .DEQ(bram_serverAdapterA_3_outDataCore$DEQ), - .CLR(bram_serverAdapterA_3_outDataCore$CLR), - .D_OUT(bram_serverAdapterA_3_outDataCore$D_OUT), - .FULL_N(bram_serverAdapterA_3_outDataCore$FULL_N), - .EMPTY_N(bram_serverAdapterA_3_outDataCore$EMPTY_N)); - - // submodule bram_serverAdapterA_outDataCore + .D_IN(bram_1_serverAdapterA_outDataCore$D_IN), + .ENQ(bram_1_serverAdapterA_outDataCore$ENQ), + .DEQ(bram_1_serverAdapterA_outDataCore$DEQ), + .CLR(bram_1_serverAdapterA_outDataCore$CLR), + .D_OUT(bram_1_serverAdapterA_outDataCore$D_OUT), + .FULL_N(bram_1_serverAdapterA_outDataCore$FULL_N), + .EMPTY_N(bram_1_serverAdapterA_outDataCore$EMPTY_N)); + + // submodule bram_1_serverAdapterB_outDataCore SizedFIFO #(.p1width(32'd32), .p2depth(32'd3), .p3cntr_width(32'd1), - .guarded(32'd1)) bram_serverAdapterA_outDataCore(.RST(RST_N), - .CLK(CLK), - .D_IN(bram_serverAdapterA_outDataCore$D_IN), - .ENQ(bram_serverAdapterA_outDataCore$ENQ), - .DEQ(bram_serverAdapterA_outDataCore$DEQ), - .CLR(bram_serverAdapterA_outDataCore$CLR), - .D_OUT(bram_serverAdapterA_outDataCore$D_OUT), - .FULL_N(bram_serverAdapterA_outDataCore$FULL_N), - .EMPTY_N(bram_serverAdapterA_outDataCore$EMPTY_N)); - - // submodule bram_serverAdapterB_1_outDataCore + .guarded(32'd1)) bram_1_serverAdapterB_outDataCore(.RST(RST_N), + .CLK(CLK), + .D_IN(bram_1_serverAdapterB_outDataCore$D_IN), + .ENQ(bram_1_serverAdapterB_outDataCore$ENQ), + .DEQ(bram_1_serverAdapterB_outDataCore$DEQ), + .CLR(bram_1_serverAdapterB_outDataCore$CLR), + .D_OUT(bram_1_serverAdapterB_outDataCore$D_OUT), + .FULL_N(bram_1_serverAdapterB_outDataCore$FULL_N), + .EMPTY_N(bram_1_serverAdapterB_outDataCore$EMPTY_N)); + + // submodule bram_2_memory + BRAM2 #(.PIPELINED(1'd0), + .ADDR_WIDTH(32'd11), + .DATA_WIDTH(32'd32), + .MEMSIZE(12'd2048)) bram_2_memory(.CLKA(CLK), + .CLKB(CLK), + .ADDRA(bram_2_memory$ADDRA), + .ADDRB(bram_2_memory$ADDRB), + .DIA(bram_2_memory$DIA), + .DIB(bram_2_memory$DIB), + .WEA(bram_2_memory$WEA), + .WEB(bram_2_memory$WEB), + .ENA(bram_2_memory$ENA), + .ENB(bram_2_memory$ENB), + .DOA(bram_2_memory$DOA), + .DOB(bram_2_memory$DOB)); + + // submodule bram_2_serverAdapterA_outDataCore SizedFIFO #(.p1width(32'd32), .p2depth(32'd3), .p3cntr_width(32'd1), - .guarded(32'd1)) bram_serverAdapterB_1_outDataCore(.RST(RST_N), + .guarded(32'd1)) bram_2_serverAdapterA_outDataCore(.RST(RST_N), .CLK(CLK), - .D_IN(bram_serverAdapterB_1_outDataCore$D_IN), - .ENQ(bram_serverAdapterB_1_outDataCore$ENQ), - .DEQ(bram_serverAdapterB_1_outDataCore$DEQ), - .CLR(bram_serverAdapterB_1_outDataCore$CLR), - .D_OUT(bram_serverAdapterB_1_outDataCore$D_OUT), - .FULL_N(bram_serverAdapterB_1_outDataCore$FULL_N), - .EMPTY_N(bram_serverAdapterB_1_outDataCore$EMPTY_N)); - - // submodule bram_serverAdapterB_2_outDataCore + .D_IN(bram_2_serverAdapterA_outDataCore$D_IN), + .ENQ(bram_2_serverAdapterA_outDataCore$ENQ), + .DEQ(bram_2_serverAdapterA_outDataCore$DEQ), + .CLR(bram_2_serverAdapterA_outDataCore$CLR), + .D_OUT(bram_2_serverAdapterA_outDataCore$D_OUT), + .FULL_N(bram_2_serverAdapterA_outDataCore$FULL_N), + .EMPTY_N(bram_2_serverAdapterA_outDataCore$EMPTY_N)); + + // submodule bram_2_serverAdapterB_outDataCore SizedFIFO #(.p1width(32'd32), .p2depth(32'd3), .p3cntr_width(32'd1), - .guarded(32'd1)) bram_serverAdapterB_2_outDataCore(.RST(RST_N), + .guarded(32'd1)) bram_2_serverAdapterB_outDataCore(.RST(RST_N), .CLK(CLK), - .D_IN(bram_serverAdapterB_2_outDataCore$D_IN), - .ENQ(bram_serverAdapterB_2_outDataCore$ENQ), - .DEQ(bram_serverAdapterB_2_outDataCore$DEQ), - .CLR(bram_serverAdapterB_2_outDataCore$CLR), - .D_OUT(bram_serverAdapterB_2_outDataCore$D_OUT), - .FULL_N(bram_serverAdapterB_2_outDataCore$FULL_N), - .EMPTY_N(bram_serverAdapterB_2_outDataCore$EMPTY_N)); - - // submodule bram_serverAdapterB_3_outDataCore + .D_IN(bram_2_serverAdapterB_outDataCore$D_IN), + .ENQ(bram_2_serverAdapterB_outDataCore$ENQ), + .DEQ(bram_2_serverAdapterB_outDataCore$DEQ), + .CLR(bram_2_serverAdapterB_outDataCore$CLR), + .D_OUT(bram_2_serverAdapterB_outDataCore$D_OUT), + .FULL_N(bram_2_serverAdapterB_outDataCore$FULL_N), + .EMPTY_N(bram_2_serverAdapterB_outDataCore$EMPTY_N)); + + // submodule bram_3_memory + BRAM2 #(.PIPELINED(1'd0), + .ADDR_WIDTH(32'd11), + .DATA_WIDTH(32'd32), + .MEMSIZE(12'd2048)) bram_3_memory(.CLKA(CLK), + .CLKB(CLK), + .ADDRA(bram_3_memory$ADDRA), + .ADDRB(bram_3_memory$ADDRB), + .DIA(bram_3_memory$DIA), + .DIB(bram_3_memory$DIB), + .WEA(bram_3_memory$WEA), + .WEB(bram_3_memory$WEB), + .ENA(bram_3_memory$ENA), + .ENB(bram_3_memory$ENB), + .DOA(bram_3_memory$DOA), + .DOB(bram_3_memory$DOB)); + + // submodule bram_3_serverAdapterA_outDataCore SizedFIFO #(.p1width(32'd32), .p2depth(32'd3), .p3cntr_width(32'd1), - .guarded(32'd1)) bram_serverAdapterB_3_outDataCore(.RST(RST_N), + .guarded(32'd1)) bram_3_serverAdapterA_outDataCore(.RST(RST_N), .CLK(CLK), - .D_IN(bram_serverAdapterB_3_outDataCore$D_IN), - .ENQ(bram_serverAdapterB_3_outDataCore$ENQ), - .DEQ(bram_serverAdapterB_3_outDataCore$DEQ), - .CLR(bram_serverAdapterB_3_outDataCore$CLR), - .D_OUT(bram_serverAdapterB_3_outDataCore$D_OUT), - .FULL_N(bram_serverAdapterB_3_outDataCore$FULL_N), - .EMPTY_N(bram_serverAdapterB_3_outDataCore$EMPTY_N)); - - // submodule bram_serverAdapterB_outDataCore + .D_IN(bram_3_serverAdapterA_outDataCore$D_IN), + .ENQ(bram_3_serverAdapterA_outDataCore$ENQ), + .DEQ(bram_3_serverAdapterA_outDataCore$DEQ), + .CLR(bram_3_serverAdapterA_outDataCore$CLR), + .D_OUT(bram_3_serverAdapterA_outDataCore$D_OUT), + .FULL_N(bram_3_serverAdapterA_outDataCore$FULL_N), + .EMPTY_N(bram_3_serverAdapterA_outDataCore$EMPTY_N)); + + // submodule bram_3_serverAdapterB_outDataCore SizedFIFO #(.p1width(32'd32), .p2depth(32'd3), .p3cntr_width(32'd1), - .guarded(32'd1)) bram_serverAdapterB_outDataCore(.RST(RST_N), - .CLK(CLK), - .D_IN(bram_serverAdapterB_outDataCore$D_IN), - .ENQ(bram_serverAdapterB_outDataCore$ENQ), - .DEQ(bram_serverAdapterB_outDataCore$DEQ), - .CLR(bram_serverAdapterB_outDataCore$CLR), - .D_OUT(bram_serverAdapterB_outDataCore$D_OUT), - .FULL_N(bram_serverAdapterB_outDataCore$FULL_N), - .EMPTY_N(bram_serverAdapterB_outDataCore$EMPTY_N)); + .guarded(32'd1)) bram_3_serverAdapterB_outDataCore(.RST(RST_N), + .CLK(CLK), + .D_IN(bram_3_serverAdapterB_outDataCore$D_IN), + .ENQ(bram_3_serverAdapterB_outDataCore$ENQ), + .DEQ(bram_3_serverAdapterB_outDataCore$DEQ), + .CLR(bram_3_serverAdapterB_outDataCore$CLR), + .D_OUT(bram_3_serverAdapterB_outDataCore$D_OUT), + .FULL_N(bram_3_serverAdapterB_outDataCore$FULL_N), + .EMPTY_N(bram_3_serverAdapterB_outDataCore$EMPTY_N)); // submodule tlp_inF arSRLFIFOD #(.width(32'd153), .l2depth(32'd4)) tlp_inF(.CLK(CLK), @@ -2374,9 +2381,14 @@ module mkOCDP16B(pciDevice, .FULL_N(wmi_wmi_reqF$FULL_N), .EMPTY_N(wmi_wmi_reqF$EMPTY_N)); + // rule RL_bram_2_serverAdapterA_outData_setFirstEnq + assign WILL_FIRE_RL_bram_2_serverAdapterA_outData_setFirstEnq = + !bram_2_serverAdapterA_outDataCore$EMPTY_N && + bram_2_serverAdapterA_outData_enqData$whas ; + // rule RL_wci_cfrd assign WILL_FIRE_RL_wci_cfrd = - wci_respF_c_r != 2'd2 && wci_reqF$EMPTY_N && + wci_respF_cntr_r != 2'd2 && wci_reqF$EMPTY_N && wci_wci_cfrd_pw$whas && !WILL_FIRE_RL_wci_ctl_op_start && !WILL_FIRE_RL_wci_ctl_op_complete ; @@ -2389,14 +2401,14 @@ module mkOCDP16B(pciDevice, // rule RL_tlp_dmaRequestNearMeta assign WILL_FIRE_RL_tlp_dmaRequestNearMeta = tlp_tlpBRAM_mReqF$FULL_N && - hasPush_AND_tlp_dpControl_wget__072_BITS_7_TO__ETC___d1093 && + hasPush_AND_tlp_dpControl_wget__64_BITS_7_TO_4_ETC___d985 && tlp_farBufReady && tlp_postSeqDwell == 4'd0 ; // rule RL_tlp_dmaPushRequestMesg assign WILL_FIRE_RL_tlp_dmaPushRequestMesg = tlp_tlpBRAM_mReqF$FULL_N && - hasPush_AND_tlp_dpControl_wget__072_BITS_7_TO__ETC___d1166 && + hasPush_AND_tlp_dpControl_wget__64_BITS_7_TO_4_ETC___d1058 && !WILL_FIRE_RL_tlp_dmaResponseNearMetaBody ; // rule RL_tlp_dmaResponseNearMetaHead @@ -2411,7 +2423,7 @@ module mkOCDP16B(pciDevice, // rule RL_tlp_dmaPushResponseHeader assign WILL_FIRE_RL_tlp_dmaPushResponseHeader = tlp_outF$FULL_N && tlp_tlpBRAM_mRespF$EMPTY_N && - hasPush_AND_tlp_dpControl_wget__072_BITS_7_TO__ETC___d1206 ; + hasPush_AND_tlp_dpControl_wget__64_BITS_7_TO_4_ETC___d1098 ; // rule RL_tlp_dmaPushResponseBody assign WILL_FIRE_RL_tlp_dmaPushResponseBody = @@ -2425,7 +2437,7 @@ module mkOCDP16B(pciDevice, // rule RL_tlp_dmaXmtMetaHead assign WILL_FIRE_RL_tlp_dmaXmtMetaHead = tlp_outF$FULL_N && - hasPush_AND_tlp_dpControl_wget__072_BITS_7_TO__ETC___d1263 && + hasPush_AND_tlp_dpControl_wget__64_BITS_7_TO_4_ETC___d1155 && !WILL_FIRE_RL_tlp_dmaPushResponseBody && !WILL_FIRE_RL_tlp_dmaPushResponseHeader ; @@ -2459,12 +2471,12 @@ module mkOCDP16B(pciDevice, // rule RL_tlp_dmaRespHeadFarMeta assign WILL_FIRE_RL_tlp_dmaRespHeadFarMeta = tlp_inF$EMPTY_N && tlp_tlpBRAM_mReqF$FULL_N && - hasPull_AND_tlp_dpControl_wget__072_BITS_7_TO__ETC___d1382 ; + hasPull_AND_tlp_dpControl_wget__64_BITS_7_TO_4_ETC___d1274 ; // rule RL_tlp_dmaPullTailEvent assign WILL_FIRE_RL_tlp_dmaPullTailEvent = tlp_tailEventF$FULL_N && - hasPull_AND_tlp_dpControl_wget__072_BITS_7_TO__ETC___d1518 ; + hasPull_AND_tlp_dpControl_wget__64_BITS_7_TO_4_ETC___d1410 ; // rule RL_tlp_dmaRespBodyFarMeta assign CAN_FIRE_RL_tlp_dmaRespBodyFarMeta = @@ -2481,14 +2493,14 @@ module mkOCDP16B(pciDevice, // rule RL_tlp_dmaPullResponseHeader assign WILL_FIRE_RL_tlp_dmaPullResponseHeader = tlp_inF$EMPTY_N && tlp_tlpBRAM_mReqF$FULL_N && - hasPull_AND_tlp_dpControl_wget__072_BITS_7_TO__ETC___d1473 && + hasPull_AND_tlp_dpControl_wget__64_BITS_7_TO_4_ETC___d1365 && !WILL_FIRE_RL_tlp_dmaRespBodyFarMeta && !WILL_FIRE_RL_tlp_dmaRespHeadFarMeta ; // rule RL_tlp_dmaPullResponseBody assign WILL_FIRE_RL_tlp_dmaPullResponseBody = tlp_inF$EMPTY_N && tlp_tlpBRAM_mReqF$FULL_N && - hasPull_AND_tlp_dpControl_wget__072_BITS_7_TO__ETC___d1493 && + hasPull_AND_tlp_dpControl_wget__64_BITS_7_TO_4_ETC___d1385 && !WILL_FIRE_RL_tlp_dmaRespBodyFarMeta && !WILL_FIRE_RL_tlp_dmaRespHeadFarMeta ; @@ -2535,7 +2547,7 @@ module mkOCDP16B(pciDevice, // rule RL_tlp_dmaRequestFarMeta assign WILL_FIRE_RL_tlp_dmaRequestFarMeta = tlp_outF$FULL_N && - hasPull_AND_tlp_dpControl_wget__072_BITS_7_TO__ETC___d1341 && + hasPull_AND_tlp_dpControl_wget__64_BITS_7_TO_4_ETC___d1233 && tlp_nearBufReady && tlp_farBufReady && tlp_postSeqDwell == 4'd0 ; @@ -2543,7 +2555,7 @@ module mkOCDP16B(pciDevice, // rule RL_tlp_dmaPullRequestFarMesg assign WILL_FIRE_RL_tlp_dmaPullRequestFarMesg = tlp_outF$FULL_N && - hasPull_AND_tlp_dpControl_wget__072_BITS_7_TO__ETC___d1434 && + hasPull_AND_tlp_dpControl_wget__64_BITS_7_TO_4_ETC___d1326 && !WILL_FIRE_RL_tlp_dmaRespBodyFarMeta && !WILL_FIRE_RL_tlp_dmaRespHeadFarMeta ; @@ -2573,31 +2585,33 @@ module mkOCDP16B(pciDevice, // rule RL_tlp_tlpBRAM_writeReq assign WILL_FIRE_RL_tlp_tlpBRAM_writeReq = tlp_tlpBRAM_mReqF$EMPTY_N && - tlp_tlpBRAM_mReqF_first__18_BIT_63_19_OR_IF_tl_ETC___d634 && + (tlp_tlpBRAM_mReqF$D_OUT[63] || + CASE_tlp_tlpBRAM_mReqF_first__16_BITS_51_TO_50_ETC___d623) && tlp_tlpBRAM_mReqF$D_OUT[129:128] == 2'd0 ; // rule RL_tlp_tlpBRAM_writeData assign WILL_FIRE_RL_tlp_tlpBRAM_writeData = tlp_tlpBRAM_mReqF$EMPTY_N && - (IF_0_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d675 || - bram_serverAdapterA_cnt_6_SLT_3___d2628) && - IF_1_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d708 && + (!SEL_ARR_NOT_tlp_tlpBRAM_writeRemainDWLen_52_EQ_ETC___d665 || + bram_0_serverAdapterA_cnt_6_SLT_3___d619) && + NOT_SEL_ARR_NOT_tlp_tlpBRAM_writeRemainDWLen_5_ETC___d681 && tlp_tlpBRAM_mReqF$D_OUT[129:128] == 2'd1 ; // rule RL_tlp_tlpBRAM_read_FirstReq assign WILL_FIRE_RL_tlp_tlpBRAM_read_FirstReq = tlp_tlpBRAM_mReqF$EMPTY_N && tlp_tlpBRAM_readReq$FULL_N && - tlp_tlpBRAM_mReqF_first__18_BIT_60_02_OR_IF_tl_ETC___d813 && + (tlp_tlpBRAM_mReqF$D_OUT[60] || + CASE_tlp_tlpBRAM_mReqF_first__16_BITS_30_TO_29_ETC___d736) && !tlp_tlpBRAM_readStarted && tlp_tlpBRAM_mReqF$D_OUT[129:128] != 2'd0 && tlp_tlpBRAM_mReqF$D_OUT[129:128] != 2'd1 ; // rule RL_tlp_tlpBRAM_read_NextReq assign WILL_FIRE_RL_tlp_tlpBRAM_read_NextReq = - bram_serverAdapterA_cnt_6_SLT_3___d2628 && - bram_serverAdapterA_1_cnt_44_SLT_3___d2629 && - bram_serverAdapterA_2_cnt_62_SLT_3___d2630 && - bram_serverAdapterA_3_cnt_80_SLT_3___d2631 && + bram_0_serverAdapterA_cnt_6_SLT_3___d619 && + bram_1_serverAdapterA_cnt_44_SLT_3___d620 && + bram_2_serverAdapterA_cnt_62_SLT_3___d621 && + bram_3_serverAdapterA_cnt_80_SLT_3___d622 && tlp_tlpBRAM_mReqF$EMPTY_N && tlp_tlpBRAM_readStarted && tlp_tlpBRAM_mReqF$D_OUT[129:128] != 2'd0 && @@ -2605,48 +2619,47 @@ module mkOCDP16B(pciDevice, // rule RL_tlp_tlpBRAM_read_FirstResp assign WILL_FIRE_RL_tlp_tlpBRAM_read_FirstResp = - tlp_tlpBRAM_readReq$EMPTY_N && tlp_tlpBRAM_mRespF$FULL_N && - (tlp_tlpBRAM_readReq$D_OUT[60] || - IF_tlp_tlpBRAM_readReq_first__97_BITS_30_TO_29_ETC___d921) && + tlp_tlpBRAM_readReq$EMPTY_N && + tlp_tlpBRAM_mRespF_i_notFull__97_AND_tlp_tlpBR_ETC___d813 && !tlp_tlpBRAM_readHeaderSent ; // rule RL_tlp_tlpBRAM_read_NextResp assign WILL_FIRE_RL_tlp_tlpBRAM_read_NextResp = tlp_tlpBRAM_readReq$EMPTY_N && - bram_serverAdapterA_outDataCore_notEmpty_OR_br_ETC___d995 && + bram_0_serverAdapterA_outDataCore_notEmpty_OR__ETC___d887 && tlp_tlpBRAM_readHeaderSent ; - // rule RL_bram_serverAdapterA_outData_enqAndDeq - assign WILL_FIRE_RL_bram_serverAdapterA_outData_enqAndDeq = - bram_serverAdapterA_outDataCore$EMPTY_N && - bram_serverAdapterA_outDataCore$FULL_N && - bram_serverAdapterA_outData_deqCalled$whas && - bram_serverAdapterA_outData_enqData$whas ; - - // rule RL_bram_serverAdapterA_1_outData_enqAndDeq - assign WILL_FIRE_RL_bram_serverAdapterA_1_outData_enqAndDeq = - bram_serverAdapterA_1_outDataCore$EMPTY_N && - bram_serverAdapterA_1_outDataCore$FULL_N && - bram_serverAdapterA_1_outData_deqCalled$whas && - bram_serverAdapterA_1_outData_enqData$whas ; - - // rule RL_bram_serverAdapterA_2_outData_enqAndDeq - assign WILL_FIRE_RL_bram_serverAdapterA_2_outData_enqAndDeq = - bram_serverAdapterA_2_outDataCore$EMPTY_N && - bram_serverAdapterA_2_outDataCore$FULL_N && - bram_serverAdapterA_2_outData_deqCalled$whas && - bram_serverAdapterA_2_outData_enqData$whas ; - - // rule RL_bram_serverAdapterA_3_outData_enqAndDeq - assign WILL_FIRE_RL_bram_serverAdapterA_3_outData_enqAndDeq = - bram_serverAdapterA_3_outDataCore$EMPTY_N && - bram_serverAdapterA_3_outDataCore$FULL_N && - bram_serverAdapterA_3_outData_deqCalled$whas && - bram_serverAdapterA_3_outData_enqData$whas ; + // rule RL_bram_0_serverAdapterA_outData_enqAndDeq + assign WILL_FIRE_RL_bram_0_serverAdapterA_outData_enqAndDeq = + bram_0_serverAdapterA_outDataCore$EMPTY_N && + bram_0_serverAdapterA_outDataCore$FULL_N && + bram_0_serverAdapterA_outData_deqCalled$whas && + bram_0_serverAdapterA_outData_enqData$whas ; + + // rule RL_bram_1_serverAdapterA_outData_enqAndDeq + assign WILL_FIRE_RL_bram_1_serverAdapterA_outData_enqAndDeq = + bram_1_serverAdapterA_outDataCore$EMPTY_N && + bram_1_serverAdapterA_outDataCore$FULL_N && + bram_1_serverAdapterA_outData_deqCalled$whas && + bram_1_serverAdapterA_outData_enqData$whas ; + + // rule RL_bram_2_serverAdapterA_outData_enqAndDeq + assign WILL_FIRE_RL_bram_2_serverAdapterA_outData_enqAndDeq = + bram_2_serverAdapterA_outDataCore$EMPTY_N && + bram_2_serverAdapterA_outDataCore$FULL_N && + bram_2_serverAdapterA_outData_deqCalled$whas && + bram_2_serverAdapterA_outData_enqData$whas ; + + // rule RL_bram_3_serverAdapterA_outData_enqAndDeq + assign WILL_FIRE_RL_bram_3_serverAdapterA_outData_enqAndDeq = + bram_3_serverAdapterA_outDataCore$EMPTY_N && + bram_3_serverAdapterA_outDataCore$FULL_N && + bram_3_serverAdapterA_outData_deqCalled$whas && + bram_3_serverAdapterA_outData_enqData$whas ; // rule RL_wmi_reqMetadata assign CAN_FIRE_RL_wmi_reqMetadata = - bram_serverAdapterB_cnt_5_SLT_3_776_AND_bram_s_ETC___d1782 && + bram_0_serverAdapterB_cnt_5_SLT_3_666_AND_bram_ETC___d1672 && dpControl[3:2] != 2'd1 && !wmi_mesgMeta[128] && wmi_mesgBufReady && @@ -2659,15 +2672,15 @@ module mkOCDP16B(pciDevice, // rule RL_wmi_doWriteFinalize assign WILL_FIRE_RL_wmi_doWriteFinalize = - wmi_wmi_operateD_716_AND_wmi_wmi_peerIsReady_7_ETC___d1887 && + wmi_wmi_operateD_606_AND_wmi_wmi_peerIsReady_6_ETC___d1777 && wmi_wrFinalize ; // rule RL_wmi_respMetadata assign CAN_FIRE_RL_wmi_respMetadata = wmi_wmi_operateD && wmi_wmi_peerIsReady && - (bram_serverAdapterB_outDataCore$EMPTY_N || - bram_serverAdapterB_outData_enqData$whas) && - bram_serverAdapterB_outData_outData_whas__795__ETC___d1807 && + (bram_0_serverAdapterB_outDataCore$EMPTY_N || + bram_0_serverAdapterB_outData_enqData$whas) && + bram_0_serverAdapterB_outData_outData_whas__68_ETC___d1697 && dpControl[3:2] != 2'd1 && !wmi_mesgMeta[128] && wmi_mesgBufReady && @@ -2677,50 +2690,50 @@ module mkOCDP16B(pciDevice, // rule RL_wmi_doReadReq assign WILL_FIRE_RL_wmi_doReadReq = - bram_serverAdapterB_cnt_5_SLT_3_776_AND_bram_s_ETC___d1782 && + bram_0_serverAdapterB_cnt_5_SLT_3_666_AND_bram_ETC___d1672 && wmi_rdActive && !WILL_FIRE_RL_wmi_doWriteReq && !WILL_FIRE_RL_wmi_doWriteFinalize ; // rule RL_wmi_doReadResp assign WILL_FIRE_RL_wmi_doReadResp = - wmi_wmi_respF_c_r != 2'd2 && - wmi_wmi_operateD_716_AND_wmi_wmi_peerIsReady_7_ETC___d1908 && + wmi_wmi_respF_cntr_r != 2'd2 && + wmi_wmi_operateD_606_AND_wmi_wmi_peerIsReady_6_ETC___d1798 && wmi_bytesRemainResp != 14'd0 ; - // rule RL_bram_serverAdapterB_outData_enqAndDeq - assign WILL_FIRE_RL_bram_serverAdapterB_outData_enqAndDeq = - bram_serverAdapterB_outDataCore$EMPTY_N && - bram_serverAdapterB_outDataCore$FULL_N && - bram_serverAdapterB_outData_deqCalled$whas && - bram_serverAdapterB_outData_enqData$whas ; - - // rule RL_bram_serverAdapterB_1_outData_enqAndDeq - assign WILL_FIRE_RL_bram_serverAdapterB_1_outData_enqAndDeq = - bram_serverAdapterB_1_outDataCore$EMPTY_N && - bram_serverAdapterB_1_outDataCore$FULL_N && - bram_serverAdapterB_outData_deqCalled$whas && - bram_serverAdapterB_1_outData_enqData$whas ; - - // rule RL_bram_serverAdapterB_2_outData_enqAndDeq - assign WILL_FIRE_RL_bram_serverAdapterB_2_outData_enqAndDeq = - bram_serverAdapterB_2_outDataCore$EMPTY_N && - bram_serverAdapterB_2_outDataCore$FULL_N && - bram_serverAdapterB_outData_deqCalled$whas && - bram_serverAdapterB_2_outData_enqData$whas ; - - // rule RL_bram_serverAdapterB_3_outData_enqAndDeq - assign WILL_FIRE_RL_bram_serverAdapterB_3_outData_enqAndDeq = - bram_serverAdapterB_3_outDataCore$EMPTY_N && - bram_serverAdapterB_3_outDataCore$FULL_N && - bram_serverAdapterB_outData_deqCalled$whas && - bram_serverAdapterB_3_outData_enqData$whas ; + // rule RL_bram_0_serverAdapterB_outData_enqAndDeq + assign WILL_FIRE_RL_bram_0_serverAdapterB_outData_enqAndDeq = + bram_0_serverAdapterB_outDataCore$EMPTY_N && + bram_0_serverAdapterB_outDataCore$FULL_N && + bram_0_serverAdapterB_outData_deqCalled$whas && + bram_0_serverAdapterB_outData_enqData$whas ; + + // rule RL_bram_1_serverAdapterB_outData_enqAndDeq + assign WILL_FIRE_RL_bram_1_serverAdapterB_outData_enqAndDeq = + bram_1_serverAdapterB_outDataCore$EMPTY_N && + bram_1_serverAdapterB_outDataCore$FULL_N && + bram_0_serverAdapterB_outData_deqCalled$whas && + bram_1_serverAdapterB_outData_enqData$whas ; + + // rule RL_bram_2_serverAdapterB_outData_enqAndDeq + assign WILL_FIRE_RL_bram_2_serverAdapterB_outData_enqAndDeq = + bram_2_serverAdapterB_outDataCore$EMPTY_N && + bram_2_serverAdapterB_outDataCore$FULL_N && + bram_0_serverAdapterB_outData_deqCalled$whas && + bram_2_serverAdapterB_outData_enqData$whas ; + + // rule RL_bram_3_serverAdapterB_outData_enqAndDeq + assign WILL_FIRE_RL_bram_3_serverAdapterB_outData_enqAndDeq = + bram_3_serverAdapterB_outDataCore$EMPTY_N && + bram_3_serverAdapterB_outDataCore$FULL_N && + bram_0_serverAdapterB_outData_deqCalled$whas && + bram_3_serverAdapterB_outData_enqData$whas ; // rule RL_wmi_getRequest assign CAN_FIRE_RL_wmi_getRequest = wmi_wmi_operateD && wmi_wmi_peerIsReady && !wmi_wmi_blockReq && wmi_wmi_reqF$EMPTY_N && - NOT_wmi_wrActive_827_828_OR_NOT_wmi_rdActive_8_ETC___d1837 && + NOT_wmi_wrActive_717_718_OR_NOT_wmi_rdActive_7_ETC___d1727 && wmi_bufDwell == 2'd0 ; assign WILL_FIRE_RL_wmi_getRequest = CAN_FIRE_RL_wmi_getRequest && !WILL_FIRE_RL_wmi_doReadReq && @@ -2729,10 +2742,10 @@ module mkOCDP16B(pciDevice, // rule RL_wmi_doWriteReq assign CAN_FIRE_RL_wmi_doWriteReq = wmi_wmi_operateD && wmi_wmi_peerIsReady && - bram_serverAdapterB_cnt_5_SLT_3___d1776 && - bram_serverAdapterB_1_cnt_03_SLT_3___d1777 && - bram_serverAdapterB_2_cnt_21_SLT_3___d1778 && - bram_serverAdapterB_3_cnt_39_SLT_3___d1779 && + bram_0_serverAdapterB_cnt_5_SLT_3___d1666 && + bram_1_serverAdapterB_cnt_03_SLT_3___d1667 && + bram_2_serverAdapterB_cnt_21_SLT_3___d1668 && + bram_3_serverAdapterB_cnt_39_SLT_3___d1669 && wmi_wmi_dhF$EMPTY_N && wmi_wrActive ; assign WILL_FIRE_RL_wmi_doWriteReq = @@ -2740,22 +2753,16 @@ module mkOCDP16B(pciDevice, // rule RL_wmi_wmi_respF_incCtr assign WILL_FIRE_RL_wmi_wmi_respF_incCtr = - ((wmi_wmi_respF_c_r == 2'd0) ? - WILL_FIRE_RL_wmi_doReadResp : - wmi_wmi_respF_c_r != 2'd1 || WILL_FIRE_RL_wmi_doReadResp) && - WILL_FIRE_RL_wmi_doReadResp && - !(wmi_wmi_respF_c_r != 2'd0) ; + WILL_FIRE_RL_wmi_doReadResp && WILL_FIRE_RL_wmi_doReadResp && + !(wmi_wmi_respF_cntr_r != 2'd0) ; // rule RL_wmi_wmi_respF_decCtr assign WILL_FIRE_RL_wmi_wmi_respF_decCtr = - wmi_wmi_respF_c_r != 2'd0 && !WILL_FIRE_RL_wmi_doReadResp ; + wmi_wmi_respF_cntr_r != 2'd0 && !WILL_FIRE_RL_wmi_doReadResp ; // rule RL_wmi_wmi_respF_both assign WILL_FIRE_RL_wmi_wmi_respF_both = - ((wmi_wmi_respF_c_r == 2'd1) ? - WILL_FIRE_RL_wmi_doReadResp : - wmi_wmi_respF_c_r != 2'd2 || WILL_FIRE_RL_wmi_doReadResp) && - wmi_wmi_respF_c_r != 2'd0 && + WILL_FIRE_RL_wmi_doReadResp && wmi_wmi_respF_cntr_r != 2'd0 && WILL_FIRE_RL_wmi_doReadResp ; // rule RL_bml_fba @@ -2785,33 +2792,27 @@ module mkOCDP16B(pciDevice, // rule RL_wci_cfwr assign WILL_FIRE_RL_wci_cfwr = - wci_respF_c_r != 2'd2 && wci_reqF$EMPTY_N && + wci_respF_cntr_r != 2'd2 && wci_reqF$EMPTY_N && wci_wci_cfwr_pw$whas && !WILL_FIRE_RL_wci_ctl_op_start && !WILL_FIRE_RL_wci_ctl_op_complete ; // rule RL_wci_ctl_op_complete assign WILL_FIRE_RL_wci_ctl_op_complete = - wci_respF_c_r != 2'd2 && wci_ctlOpActive && wci_ctlAckReg ; + wci_respF_cntr_r != 2'd2 && wci_ctlOpActive && wci_ctlAckReg ; // rule RL_wci_respF_incCtr assign WILL_FIRE_RL_wci_respF_incCtr = - ((wci_respF_c_r == 2'd0) ? - wci_respF_x_wire$whas : - wci_respF_c_r != 2'd1 || wci_respF_x_wire$whas) && - wci_respF_enqueueing$whas && - !(wci_respF_c_r != 2'd0) ; + wci_respF_enqueueing$whas && wci_respF_enqueueing$whas && + !(wci_respF_cntr_r != 2'd0) ; // rule RL_wci_respF_decCtr assign WILL_FIRE_RL_wci_respF_decCtr = - wci_respF_c_r != 2'd0 && !wci_respF_enqueueing$whas ; + wci_respF_cntr_r != 2'd0 && !wci_respF_enqueueing$whas ; // rule RL_wci_respF_both assign WILL_FIRE_RL_wci_respF_both = - ((wci_respF_c_r == 2'd1) ? - wci_respF_x_wire$whas : - wci_respF_c_r != 2'd2 || wci_respF_x_wire$whas) && - wci_respF_c_r != 2'd0 && + wci_respF_enqueueing$whas && wci_respF_cntr_r != 2'd0 && wci_respF_enqueueing$whas ; // rule RL_wmi_wmi_reqF_reset @@ -2838,64 +2839,60 @@ module mkOCDP16B(pciDevice, WILL_FIRE_RL_bml_remAdvance && dpControl[1:0] == 2'd1 ; assign MUX_bml_lclBufsAR$write_1__SEL_1 = wci_cState == 3'd2 && - (IF_bml_dpControl_wget__008_BITS_1_TO_0_014_EQ__ETC___d2085 && - !bml_lclBufStart || - CASE_dpControl_BITS_1_TO_0_NOT_bml_fabDone_0_N_ETC__q8 && - bml_lclBufStart) ; + IF_bml_dpControl_wget__898_BITS_1_TO_0_904_EQ__ETC___d1984 ; assign MUX_bml_lclBufsCF$write_1__SEL_1 = wci_cState == 3'd2 && - (bml_lclBufDone_032_AND_IF_bml_dpControl_wget___ETC___d2443 || - NOT_bml_lclBufDone_032_099_AND_IF_bml_dpContro_ETC___d2112) ; + bml_lclBufDone_922_AND_IF_bml_dpControl_wget___ETC___d2003 ; assign MUX_bml_lclCredit$write_1__SEL_1 = WILL_FIRE_RL_bml_lcredit && (bml_lclBufDone && !bml_remStart || !bml_lclBufDone && bml_remStart) ; - assign MUX_bram_memory$a_put_1__SEL_1 = + assign MUX_bram_0_memory$a_put_1__SEL_1 = + WILL_FIRE_RL_tlp_tlpBRAM_writeData && + SEL_ARR_NOT_tlp_tlpBRAM_writeRemainDWLen_52_EQ_ETC___d665 ; + assign MUX_bram_0_memory$a_put_1__SEL_2 = WILL_FIRE_RL_tlp_tlpBRAM_writeReq && - !tlp_tlpBRAM_mReqF$D_OUT[63] && - tlp_tlpBRAM_mReqF$D_OUT[51:50] == 2'd0 ; - assign MUX_bram_memory$a_put_1__SEL_2 = + tlp_tlpBRAM_mReqF$D_OUT[51:50] == 2'd0 && + !tlp_tlpBRAM_mReqF$D_OUT[63] ; + assign MUX_bram_0_memory$a_put_1__SEL_3 = WILL_FIRE_RL_tlp_tlpBRAM_read_FirstReq && - !tlp_tlpBRAM_mReqF$D_OUT[60] && - tlp_tlpBRAM_mReqF$D_OUT[30:29] == 2'd0 ; - assign MUX_bram_memory$a_put_1__SEL_3 = + tlp_tlpBRAM_mReqF$D_OUT[30:29] == 2'd0 && + !tlp_tlpBRAM_mReqF$D_OUT[60] ; + assign MUX_bram_0_serverAdapterB_writeWithResp$wset_1__SEL_1 = + WILL_FIRE_RL_wmi_reqMetadata || WILL_FIRE_RL_wmi_doReadReq ; + assign MUX_bram_1_memory$a_put_1__SEL_1 = WILL_FIRE_RL_tlp_tlpBRAM_writeData && - IF_0_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2431 ; - assign MUX_bram_memory_1$a_put_1__SEL_1 = + SEL_ARR_NOT_tlp_tlpBRAM_writeRemainDWLen_52_EQ_ETC___d669 ; + assign MUX_bram_1_memory$a_put_1__SEL_2 = WILL_FIRE_RL_tlp_tlpBRAM_writeReq && - !tlp_tlpBRAM_mReqF$D_OUT[63] && - tlp_tlpBRAM_mReqF$D_OUT[51:50] == 2'd1 ; - assign MUX_bram_memory_1$a_put_1__SEL_2 = + tlp_tlpBRAM_mReqF$D_OUT[51:50] == 2'd1 && + !tlp_tlpBRAM_mReqF$D_OUT[63] ; + assign MUX_bram_1_memory$a_put_1__SEL_3 = WILL_FIRE_RL_tlp_tlpBRAM_read_FirstReq && - !tlp_tlpBRAM_mReqF$D_OUT[60] && - tlp_tlpBRAM_mReqF$D_OUT[30:29] == 2'd1 ; - assign MUX_bram_memory_1$a_put_1__SEL_3 = + tlp_tlpBRAM_mReqF$D_OUT[30:29] == 2'd1 && + !tlp_tlpBRAM_mReqF$D_OUT[60] ; + assign MUX_bram_2_memory$a_put_1__SEL_1 = WILL_FIRE_RL_tlp_tlpBRAM_writeData && - IF_1_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2432 ; - assign MUX_bram_memory_2$a_put_1__SEL_1 = + SEL_ARR_NOT_tlp_tlpBRAM_writeRemainDWLen_52_EQ_ETC___d673 ; + assign MUX_bram_2_memory$a_put_1__SEL_2 = WILL_FIRE_RL_tlp_tlpBRAM_writeReq && - !tlp_tlpBRAM_mReqF$D_OUT[63] && - tlp_tlpBRAM_mReqF$D_OUT[51:50] == 2'd2 ; - assign MUX_bram_memory_2$a_put_1__SEL_2 = + tlp_tlpBRAM_mReqF$D_OUT[51:50] == 2'd2 && + !tlp_tlpBRAM_mReqF$D_OUT[63] ; + assign MUX_bram_2_memory$a_put_1__SEL_3 = WILL_FIRE_RL_tlp_tlpBRAM_read_FirstReq && - !tlp_tlpBRAM_mReqF$D_OUT[60] && - tlp_tlpBRAM_mReqF$D_OUT[30:29] == 2'd2 ; - assign MUX_bram_memory_2$a_put_1__SEL_3 = + tlp_tlpBRAM_mReqF$D_OUT[30:29] == 2'd2 && + !tlp_tlpBRAM_mReqF$D_OUT[60] ; + assign MUX_bram_3_memory$a_put_1__SEL_1 = WILL_FIRE_RL_tlp_tlpBRAM_writeData && - IF_2_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2433 ; - assign MUX_bram_memory_3$a_put_1__SEL_1 = + SEL_ARR_NOT_tlp_tlpBRAM_writeRemainDWLen_52_EQ_ETC___d677 ; + assign MUX_bram_3_memory$a_put_1__SEL_2 = WILL_FIRE_RL_tlp_tlpBRAM_writeReq && - !tlp_tlpBRAM_mReqF$D_OUT[63] && - tlp_tlpBRAM_mReqF$D_OUT[51:50] == 2'd3 ; - assign MUX_bram_memory_3$a_put_1__SEL_2 = + tlp_tlpBRAM_mReqF$D_OUT[51:50] == 2'd3 && + !tlp_tlpBRAM_mReqF$D_OUT[63] ; + assign MUX_bram_3_memory$a_put_1__SEL_3 = WILL_FIRE_RL_tlp_tlpBRAM_read_FirstReq && - !tlp_tlpBRAM_mReqF$D_OUT[60] && - tlp_tlpBRAM_mReqF$D_OUT[30:29] == 2'd3 ; - assign MUX_bram_memory_3$a_put_1__SEL_3 = - WILL_FIRE_RL_tlp_tlpBRAM_writeData && - IF_3_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2434 ; - assign MUX_bram_serverAdapterB_1_writeWithResp$wset_1__SEL_1 = - WILL_FIRE_RL_wmi_reqMetadata || WILL_FIRE_RL_wmi_doReadReq ; + tlp_tlpBRAM_mReqF$D_OUT[30:29] == 2'd3 && + !tlp_tlpBRAM_mReqF$D_OUT[60] ; assign MUX_tlp_fabMesgAccu$write_1__SEL_1 = WILL_FIRE_RL_tlp_dmaRespBodyFarMeta || WILL_FIRE_RL_tlp_dmaResponseNearMetaBody ; @@ -2912,8 +2909,8 @@ module mkOCDP16B(pciDevice, WILL_FIRE_RL_tlp_dmaXmtTailEvent ; assign MUX_tlp_tlpBRAM_mReqF$enq_1__SEL_1 = WILL_FIRE_RL_tlp_tlpRcv && - tlp_inF_first__367_BIT_152_570_AND_NOT_tlp_inF_ETC___d1595 ; - assign MUX_tlp_tlpBRAM_mReqF$enq_1__SEL_6 = + tlp_inF_first__259_BIT_152_462_AND_NOT_tlp_inF_ETC___d1487 ; + assign MUX_tlp_tlpBRAM_mReqF$enq_1__SEL_2 = WILL_FIRE_RL_tlp_dmaPullResponseBody || WILL_FIRE_RL_tlp_dmaRespBodyFarMeta ; assign MUX_tlp_tlpBRAM_readHeaderSent$write_1__SEL_1 = @@ -2926,21 +2923,21 @@ module mkOCDP16B(pciDevice, tlp_tlpBRAM_mReqF$D_OUT[60]) ; assign MUX_tlp_tlpXmtBusy$write_1__SEL_1 = WILL_FIRE_RL_tlp_dmaPushResponseHeader && _dfoo5 ; + assign MUX_tlp_tlpXmtBusy$write_1__PSEL_2 = + WILL_FIRE_RL_tlp_dataXmt_Body || + WILL_FIRE_RL_tlp_dmaPushResponseBody ; assign MUX_tlp_tlpXmtBusy$write_1__SEL_2 = + MUX_tlp_tlpXmtBusy$write_1__PSEL_2 && + tlp_outDwRemain_129_ULE_4___d1130 ; + assign MUX_tlp_tlpXmtBusy$write_1__SEL_3 = WILL_FIRE_RL_tlp_dmaTailEventSender && tlp_fabFlowAddrMS != 32'd0 ; - assign MUX_tlp_tlpXmtBusy$write_1__SEL_3 = - WILL_FIRE_RL_tlp_dataXmt_Header && - !tlp_tlpBRAM_mRespF_first__108_BITS_71_TO_62_20_ETC___d2405 ; - assign MUX_tlp_tlpXmtBusy$write_1__PSEL_4 = - WILL_FIRE_RL_tlp_dataXmt_Body || - WILL_FIRE_RL_tlp_dmaPushResponseBody ; assign MUX_tlp_tlpXmtBusy$write_1__SEL_4 = - MUX_tlp_tlpXmtBusy$write_1__PSEL_4 && - tlp_outDwRemain_237_ULE_4___d2557 ; + WILL_FIRE_RL_tlp_dataXmt_Header && + !tlp_tlpBRAM_mRespF_first__000_BITS_71_TO_62_10_ETC___d1102 ; assign MUX_tlp_xmtMetaOK$write_1__SEL_3 = WILL_FIRE_RL_tlp_dmaPushResponseBody && - tlp_outDwRemain_237_ULE_4___d2557 && + tlp_outDwRemain_129_ULE_4___d1130 && tlp_tlpBRAM_mRespF$D_OUT[135:128] == 8'h01 ; assign MUX_tlp_xmtMetaOK$write_1__SEL_4 = WILL_FIRE_RL_tlp_dmaPushResponseHeader && @@ -2962,10 +2959,14 @@ module mkOCDP16B(pciDevice, wci_reqF$D_OUT[36:34] == 3'd5 || wci_reqF$D_OUT[36:34] == 3'd6 || wci_reqF$D_OUT[36:34] == 3'd7) ; + assign MUX_wci_respF_q_0$write_1__SEL_1 = + WILL_FIRE_RL_wci_respF_both && _dfoo3 ; assign MUX_wci_respF_q_0$write_1__SEL_2 = - WILL_FIRE_RL_wci_respF_incCtr && wci_respF_c_r == 2'd0 ; + WILL_FIRE_RL_wci_respF_incCtr && wci_respF_cntr_r == 2'd0 ; + assign MUX_wci_respF_q_1$write_1__SEL_1 = + WILL_FIRE_RL_wci_respF_both && _dfoo1 ; assign MUX_wci_respF_q_1$write_1__SEL_2 = - WILL_FIRE_RL_wci_respF_incCtr && wci_respF_c_r == 2'd1 ; + WILL_FIRE_RL_wci_respF_incCtr && wci_respF_cntr_r == 2'd1 ; assign MUX_wmi_bufDwell$write_1__SEL_1 = WILL_FIRE_RL_wmi_doReadReq && wmi_bytesRemainReq == 14'd16 && wmi_doneWithMesg ; @@ -2991,294 +2992,302 @@ module mkOCDP16B(pciDevice, assign MUX_wmi_wmi_reqF_levelsValid$write_1__SEL_2 = wmi_wmi_reqF$FULL_N && wmi_wmi_operateD && wmi_wmi_peerIsReady && wmi_wmi_wmiReq$wget[31:29] != 3'd0 ; + assign MUX_wmi_wmi_respF_q_0$write_1__SEL_1 = + WILL_FIRE_RL_wmi_wmi_respF_both && _dfoo9 ; assign MUX_wmi_wmi_respF_q_0$write_1__SEL_2 = - WILL_FIRE_RL_wmi_wmi_respF_incCtr && wmi_wmi_respF_c_r == 2'd0 ; + WILL_FIRE_RL_wmi_wmi_respF_incCtr && + wmi_wmi_respF_cntr_r == 2'd0 ; + assign MUX_wmi_wmi_respF_q_1$write_1__SEL_1 = + WILL_FIRE_RL_wmi_wmi_respF_both && _dfoo7 ; assign MUX_wmi_wmi_respF_q_1$write_1__SEL_2 = - WILL_FIRE_RL_wmi_wmi_respF_incCtr && wmi_wmi_respF_c_r == 2'd1 ; + WILL_FIRE_RL_wmi_wmi_respF_incCtr && + wmi_wmi_respF_cntr_r == 2'd1 ; assign MUX_wmi_wrActive$write_1__SEL_1 = WILL_FIRE_RL_wmi_doWriteReq && wmi_bytesRemainReq == 14'd16 ; assign MUX_wmi_wrFinalize$write_1__SEL_1 = WILL_FIRE_RL_wmi_doWriteReq && wmi_bytesRemainReq == 14'd16 && wmi_doneWithMesg ; assign MUX_bml_crdBuf_value$write_1__VAL_3 = - bml_crdBuf_value_990_EQ_bml_crdBuf_modulus_bw__ETC___d2779 ? + bml_crdBuf_value_880_EQ_bml_crdBuf_modulus_bw__ETC___d1882 ? 16'd0 : bml_crdBuf_value + 16'd1 ; assign MUX_bml_fabBuf_value$write_1__VAL_3 = - bml_fabBuf_value_975_EQ_bml_fabBuf_modulus_bw__ETC___d2780 ? + bml_fabBuf_value_865_EQ_bml_fabBuf_modulus_bw__ETC___d1867 ? 16'd0 : bml_fabBuf_value + 16'd1 ; assign MUX_bml_fabBufsAvail$write_1__VAL_1 = - (bml_fabAvail && !bml_remStart) ? x__h88497 : x__h88502 ; + (bml_fabAvail && !bml_remStart) ? x__h90034 : x__h90039 ; assign MUX_bml_fabBufsAvail$write_1__VAL_2 = - (dpControl[3:2] == 2'd1) ? x__h87138 : 16'd0 ; + (dpControl[3:2] == 2'd1) ? x__h88675 : 16'd0 ; assign MUX_bml_fabFlowAddr$write_1__VAL_1 = - bml_fabBuf_value_975_EQ_bml_fabBuf_modulus_bw__ETC___d2780 ? + bml_fabBuf_value_865_EQ_bml_fabBuf_modulus_bw__ETC___d1867 ? bml_fabFlowBase : - bml_fabFlowAddr_047_PLUS_bml_fabFlowSize_048___d2624 ; + bml_fabFlowAddr_937_PLUS_bml_fabFlowSize_938___d1939 ; assign MUX_bml_fabFlowAddr$write_1__VAL_3 = - bml_crdBuf_value_990_EQ_bml_crdBuf_modulus_bw__ETC___d2779 ? + bml_crdBuf_value_880_EQ_bml_crdBuf_modulus_bw__ETC___d1882 ? bml_fabFlowBase : - bml_fabFlowAddr_047_PLUS_bml_fabFlowSize_048___d2624 ; + bml_fabFlowAddr_937_PLUS_bml_fabFlowSize_938___d1939 ; assign MUX_bml_fabMesgAddr$write_1__VAL_1 = - bml_fabBuf_value_975_EQ_bml_fabBuf_modulus_bw__ETC___d2780 ? + bml_fabBuf_value_865_EQ_bml_fabBuf_modulus_bw__ETC___d1867 ? bml_fabMesgBase : bml_fabMesgAddr + bml_fabMesgSize ; assign MUX_bml_fabMetaAddr$write_1__VAL_1 = - bml_fabBuf_value_975_EQ_bml_fabBuf_modulus_bw__ETC___d2780 ? + bml_fabBuf_value_865_EQ_bml_fabBuf_modulus_bw__ETC___d1867 ? bml_fabMetaBase : bml_fabMetaAddr + bml_fabMetaSize ; assign MUX_bml_lclBuf_value$write_1__VAL_3 = - bml_lclBuf_value_945_EQ_bml_lclBuf_modulus_bw__ETC___d2798 ? + bml_lclBuf_value_835_EQ_bml_lclBuf_modulus_bw__ETC___d1837 ? 16'd0 : bml_lclBuf_value + 16'd1 ; assign MUX_bml_lclBufsAR$write_1__VAL_1 = - (IF_bml_dpControl_wget__008_BITS_1_TO_0_014_EQ__ETC___d2085 && + (CASE_dpControl_BITS_1_TO_0_0_bml_fabDone_1_bml_ETC__q4 && !bml_lclBufStart) ? - x__h88266 : - x__h88271 ; + x__h89803 : + x__h89808 ; assign MUX_bml_lclBufsAR$write_1__VAL_2 = (dpControl[3:2] == 2'd1) ? bml_lclNumBufs : 16'd0 ; assign MUX_bml_lclBufsCF$write_1__VAL_1 = - bml_lclBufDone_032_AND_IF_bml_dpControl_wget___ETC___d2443 ? - x__h88378 : - x__h88415 ; + (bml_lclBufDone && + CASE_dpControl_BITS_1_TO_0_0_NOT_bml_fabDone_1_ETC__q6) ? + x__h89915 : + x__h89952 ; assign MUX_bml_lclBufsCF$write_1__VAL_2 = (dpControl[3:2] == 2'd1) ? 16'd0 : bml_lclNumBufs ; assign MUX_bml_lclCredit$write_1__VAL_1 = - (bml_lclBufDone && !bml_remStart) ? x__h88536 : x__h88541 ; + (bml_lclBufDone && !bml_remStart) ? x__h90073 : x__h90078 ; assign MUX_bml_lclMesgAddr$write_1__VAL_2 = - bml_lclBuf_value_945_EQ_bml_lclBuf_modulus_bw__ETC___d2798 ? + bml_lclBuf_value_835_EQ_bml_lclBuf_modulus_bw__ETC___d1837 ? bml_mesgBase : bml_lclMesgAddr + bml_mesgSize ; assign MUX_bml_lclMetaAddr$write_1__VAL_2 = - bml_lclBuf_value_945_EQ_bml_lclBuf_modulus_bw__ETC___d2798 ? + bml_lclBuf_value_835_EQ_bml_lclBuf_modulus_bw__ETC___d1837 ? bml_metaBase : bml_lclMetaAddr + bml_metaSize ; assign MUX_bml_remBuf_value$write_1__VAL_3 = - bml_remBuf_value_960_EQ_bml_remBuf_modulus_bw__ETC___d2799 ? + bml_remBuf_value_850_EQ_bml_remBuf_modulus_bw__ETC___d1852 ? 16'd0 : bml_remBuf_value + 16'd1 ; assign MUX_bml_remMesgAddr$write_1__VAL_2 = - bml_remBuf_value_960_EQ_bml_remBuf_modulus_bw__ETC___d2799 ? + bml_remBuf_value_850_EQ_bml_remBuf_modulus_bw__ETC___d1852 ? bml_mesgBase : bml_remMesgAddr + bml_mesgSize ; assign MUX_bml_remMetaAddr$write_1__VAL_2 = - bml_remBuf_value_960_EQ_bml_remBuf_modulus_bw__ETC___d2799 ? + bml_remBuf_value_850_EQ_bml_remBuf_modulus_bw__ETC___d1852 ? bml_metaBase : bml_remMetaAddr + bml_metaSize ; - always@(idx__h19187 or - tlp_tlpBRAM_writeDWAddr_PLUS_3__q9 or + always@(idx__h21626 or tlp_tlpBRAM_writeDWAddr or - tlp_tlpBRAM_writeDWAddr_PLUS_1__q10 or - tlp_tlpBRAM_writeDWAddr_PLUS_2__q11) + tlp_tlpBRAM_writeDWAddr_PLUS_1__q8 or + tlp_tlpBRAM_writeDWAddr_PLUS_2__q9 or + tlp_tlpBRAM_writeDWAddr_PLUS_3__q10) begin - case (idx__h19187) - 2'd0: MUX_bram_memory$a_put_2__VAL_3 = tlp_tlpBRAM_writeDWAddr[12:2]; + case (idx__h21626) + 2'd0: MUX_bram_0_memory$a_put_2__VAL_1 = tlp_tlpBRAM_writeDWAddr[12:2]; 2'd1: - MUX_bram_memory$a_put_2__VAL_3 = - tlp_tlpBRAM_writeDWAddr_PLUS_1__q10[12:2]; + MUX_bram_0_memory$a_put_2__VAL_1 = + tlp_tlpBRAM_writeDWAddr_PLUS_1__q8[12:2]; 2'd2: - MUX_bram_memory$a_put_2__VAL_3 = - tlp_tlpBRAM_writeDWAddr_PLUS_2__q11[12:2]; + MUX_bram_0_memory$a_put_2__VAL_1 = + tlp_tlpBRAM_writeDWAddr_PLUS_2__q9[12:2]; 2'd3: - MUX_bram_memory$a_put_2__VAL_3 = - tlp_tlpBRAM_writeDWAddr_PLUS_3__q9[12:2]; + MUX_bram_0_memory$a_put_2__VAL_1 = + tlp_tlpBRAM_writeDWAddr_PLUS_3__q10[12:2]; endcase end - always@(idx__h26267 or - tlp_tlpBRAM_readNxtDWAddr_PLUS_3__q12 or + always@(idx__h27879 or tlp_tlpBRAM_readNxtDWAddr or - tlp_tlpBRAM_readNxtDWAddr_PLUS_1__q13 or - tlp_tlpBRAM_readNxtDWAddr_PLUS_2__q14) + tlp_tlpBRAM_readNxtDWAddr_PLUS_1__q11 or + tlp_tlpBRAM_readNxtDWAddr_PLUS_2__q12 or + tlp_tlpBRAM_readNxtDWAddr_PLUS_3__q13) begin - case (idx__h26267) - 2'd0: MUX_bram_memory$a_put_2__VAL_4 = tlp_tlpBRAM_readNxtDWAddr[12:2]; + case (idx__h27879) + 2'd0: + MUX_bram_0_memory$a_put_2__VAL_4 = tlp_tlpBRAM_readNxtDWAddr[12:2]; 2'd1: - MUX_bram_memory$a_put_2__VAL_4 = - tlp_tlpBRAM_readNxtDWAddr_PLUS_1__q13[12:2]; + MUX_bram_0_memory$a_put_2__VAL_4 = + tlp_tlpBRAM_readNxtDWAddr_PLUS_1__q11[12:2]; 2'd2: - MUX_bram_memory$a_put_2__VAL_4 = - tlp_tlpBRAM_readNxtDWAddr_PLUS_2__q14[12:2]; + MUX_bram_0_memory$a_put_2__VAL_4 = + tlp_tlpBRAM_readNxtDWAddr_PLUS_2__q12[12:2]; 2'd3: - MUX_bram_memory$a_put_2__VAL_4 = - tlp_tlpBRAM_readNxtDWAddr_PLUS_3__q12[12:2]; + MUX_bram_0_memory$a_put_2__VAL_4 = + tlp_tlpBRAM_readNxtDWAddr_PLUS_3__q13[12:2]; endcase end - assign MUX_bram_memory$a_put_3__VAL_1 = + assign MUX_bram_0_memory$a_put_3__VAL_1 = + { SEL_ARR_tlp_tlpBRAM_mReqF_first__16_BITS_127_T_ETC___d700[7:0], + SEL_ARR_tlp_tlpBRAM_mReqF_first__16_BITS_127_T_ETC___d700[15:8], + SEL_ARR_tlp_tlpBRAM_mReqF_first__16_BITS_127_T_ETC___d700[23:16], + SEL_ARR_tlp_tlpBRAM_mReqF_first__16_BITS_127_T_ETC___d700[31:24] } ; + assign MUX_bram_0_memory$a_put_3__VAL_2 = { tlp_tlpBRAM_mReqF$D_OUT[7:0], tlp_tlpBRAM_mReqF$D_OUT[15:8], tlp_tlpBRAM_mReqF$D_OUT[23:16], tlp_tlpBRAM_mReqF$D_OUT[31:24] } ; - assign MUX_bram_memory$a_put_3__VAL_3 = - { IF_0_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2477[7:0], - IF_0_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2477[15:8], - IF_0_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2477[23:16], - IF_0_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2477[31:24] } ; - assign MUX_bram_memory$b_put_2__VAL_2 = + assign MUX_bram_0_memory$b_put_2__VAL_2 = wmi_lclMesgAddr[14:4] + { 1'd0, wmi_addr[13:4] } ; - always@(idx__h21418 or - tlp_tlpBRAM_writeDWAddr_PLUS_3__q9 or + always@(idx__h23676 or tlp_tlpBRAM_writeDWAddr or - tlp_tlpBRAM_writeDWAddr_PLUS_1__q10 or - tlp_tlpBRAM_writeDWAddr_PLUS_2__q11) + tlp_tlpBRAM_writeDWAddr_PLUS_1__q8 or + tlp_tlpBRAM_writeDWAddr_PLUS_2__q9 or + tlp_tlpBRAM_writeDWAddr_PLUS_3__q10) begin - case (idx__h21418) - 2'd0: MUX_bram_memory_1$a_put_2__VAL_3 = tlp_tlpBRAM_writeDWAddr[12:2]; + case (idx__h23676) + 2'd0: MUX_bram_1_memory$a_put_2__VAL_1 = tlp_tlpBRAM_writeDWAddr[12:2]; 2'd1: - MUX_bram_memory_1$a_put_2__VAL_3 = - tlp_tlpBRAM_writeDWAddr_PLUS_1__q10[12:2]; + MUX_bram_1_memory$a_put_2__VAL_1 = + tlp_tlpBRAM_writeDWAddr_PLUS_1__q8[12:2]; 2'd2: - MUX_bram_memory_1$a_put_2__VAL_3 = - tlp_tlpBRAM_writeDWAddr_PLUS_2__q11[12:2]; + MUX_bram_1_memory$a_put_2__VAL_1 = + tlp_tlpBRAM_writeDWAddr_PLUS_2__q9[12:2]; 2'd3: - MUX_bram_memory_1$a_put_2__VAL_3 = - tlp_tlpBRAM_writeDWAddr_PLUS_3__q9[12:2]; + MUX_bram_1_memory$a_put_2__VAL_1 = + tlp_tlpBRAM_writeDWAddr_PLUS_3__q10[12:2]; endcase end - always@(idx__h26735 or - tlp_tlpBRAM_readNxtDWAddr_PLUS_3__q12 or + always@(idx__h28282 or tlp_tlpBRAM_readNxtDWAddr or - tlp_tlpBRAM_readNxtDWAddr_PLUS_1__q13 or - tlp_tlpBRAM_readNxtDWAddr_PLUS_2__q14) + tlp_tlpBRAM_readNxtDWAddr_PLUS_1__q11 or + tlp_tlpBRAM_readNxtDWAddr_PLUS_2__q12 or + tlp_tlpBRAM_readNxtDWAddr_PLUS_3__q13) begin - case (idx__h26735) + case (idx__h28282) 2'd0: - MUX_bram_memory_1$a_put_2__VAL_4 = tlp_tlpBRAM_readNxtDWAddr[12:2]; + MUX_bram_1_memory$a_put_2__VAL_4 = tlp_tlpBRAM_readNxtDWAddr[12:2]; 2'd1: - MUX_bram_memory_1$a_put_2__VAL_4 = - tlp_tlpBRAM_readNxtDWAddr_PLUS_1__q13[12:2]; + MUX_bram_1_memory$a_put_2__VAL_4 = + tlp_tlpBRAM_readNxtDWAddr_PLUS_1__q11[12:2]; 2'd2: - MUX_bram_memory_1$a_put_2__VAL_4 = - tlp_tlpBRAM_readNxtDWAddr_PLUS_2__q14[12:2]; + MUX_bram_1_memory$a_put_2__VAL_4 = + tlp_tlpBRAM_readNxtDWAddr_PLUS_2__q12[12:2]; 2'd3: - MUX_bram_memory_1$a_put_2__VAL_4 = - tlp_tlpBRAM_readNxtDWAddr_PLUS_3__q12[12:2]; + MUX_bram_1_memory$a_put_2__VAL_4 = + tlp_tlpBRAM_readNxtDWAddr_PLUS_3__q13[12:2]; endcase end - assign MUX_bram_memory_1$a_put_3__VAL_3 = - { IF_1_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2478[7:0], - IF_1_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2478[15:8], - IF_1_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2478[23:16], - IF_1_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2478[31:24] } ; - always@(idx__h22722 or - tlp_tlpBRAM_writeDWAddr_PLUS_3__q9 or + assign MUX_bram_1_memory$a_put_3__VAL_1 = + { SEL_ARR_tlp_tlpBRAM_mReqF_first__16_BITS_127_T_ETC___d708[7:0], + SEL_ARR_tlp_tlpBRAM_mReqF_first__16_BITS_127_T_ETC___d708[15:8], + SEL_ARR_tlp_tlpBRAM_mReqF_first__16_BITS_127_T_ETC___d708[23:16], + SEL_ARR_tlp_tlpBRAM_mReqF_first__16_BITS_127_T_ETC___d708[31:24] } ; + always@(idx__h24781 or tlp_tlpBRAM_writeDWAddr or - tlp_tlpBRAM_writeDWAddr_PLUS_1__q10 or - tlp_tlpBRAM_writeDWAddr_PLUS_2__q11) + tlp_tlpBRAM_writeDWAddr_PLUS_1__q8 or + tlp_tlpBRAM_writeDWAddr_PLUS_2__q9 or + tlp_tlpBRAM_writeDWAddr_PLUS_3__q10) begin - case (idx__h22722) - 2'd0: MUX_bram_memory_2$a_put_2__VAL_3 = tlp_tlpBRAM_writeDWAddr[12:2]; + case (idx__h24781) + 2'd0: MUX_bram_2_memory$a_put_2__VAL_1 = tlp_tlpBRAM_writeDWAddr[12:2]; 2'd1: - MUX_bram_memory_2$a_put_2__VAL_3 = - tlp_tlpBRAM_writeDWAddr_PLUS_1__q10[12:2]; + MUX_bram_2_memory$a_put_2__VAL_1 = + tlp_tlpBRAM_writeDWAddr_PLUS_1__q8[12:2]; 2'd2: - MUX_bram_memory_2$a_put_2__VAL_3 = - tlp_tlpBRAM_writeDWAddr_PLUS_2__q11[12:2]; + MUX_bram_2_memory$a_put_2__VAL_1 = + tlp_tlpBRAM_writeDWAddr_PLUS_2__q9[12:2]; 2'd3: - MUX_bram_memory_2$a_put_2__VAL_3 = - tlp_tlpBRAM_writeDWAddr_PLUS_3__q9[12:2]; + MUX_bram_2_memory$a_put_2__VAL_1 = + tlp_tlpBRAM_writeDWAddr_PLUS_3__q10[12:2]; endcase end - always@(idx__h27108 or - tlp_tlpBRAM_readNxtDWAddr_PLUS_3__q12 or + always@(idx__h28586 or tlp_tlpBRAM_readNxtDWAddr or - tlp_tlpBRAM_readNxtDWAddr_PLUS_1__q13 or - tlp_tlpBRAM_readNxtDWAddr_PLUS_2__q14) + tlp_tlpBRAM_readNxtDWAddr_PLUS_1__q11 or + tlp_tlpBRAM_readNxtDWAddr_PLUS_2__q12 or + tlp_tlpBRAM_readNxtDWAddr_PLUS_3__q13) begin - case (idx__h27108) + case (idx__h28586) 2'd0: - MUX_bram_memory_2$a_put_2__VAL_4 = tlp_tlpBRAM_readNxtDWAddr[12:2]; + MUX_bram_2_memory$a_put_2__VAL_4 = tlp_tlpBRAM_readNxtDWAddr[12:2]; 2'd1: - MUX_bram_memory_2$a_put_2__VAL_4 = - tlp_tlpBRAM_readNxtDWAddr_PLUS_1__q13[12:2]; + MUX_bram_2_memory$a_put_2__VAL_4 = + tlp_tlpBRAM_readNxtDWAddr_PLUS_1__q11[12:2]; 2'd2: - MUX_bram_memory_2$a_put_2__VAL_4 = - tlp_tlpBRAM_readNxtDWAddr_PLUS_2__q14[12:2]; + MUX_bram_2_memory$a_put_2__VAL_4 = + tlp_tlpBRAM_readNxtDWAddr_PLUS_2__q12[12:2]; 2'd3: - MUX_bram_memory_2$a_put_2__VAL_4 = - tlp_tlpBRAM_readNxtDWAddr_PLUS_3__q12[12:2]; + MUX_bram_2_memory$a_put_2__VAL_4 = + tlp_tlpBRAM_readNxtDWAddr_PLUS_3__q13[12:2]; endcase end - assign MUX_bram_memory_2$a_put_3__VAL_3 = - { IF_2_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2479[7:0], - IF_2_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2479[15:8], - IF_2_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2479[23:16], - IF_2_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2479[31:24] } ; - always@(idx__h24026 or - tlp_tlpBRAM_writeDWAddr_PLUS_3__q9 or + assign MUX_bram_2_memory$a_put_3__VAL_1 = + { SEL_ARR_tlp_tlpBRAM_mReqF_first__16_BITS_127_T_ETC___d716[7:0], + SEL_ARR_tlp_tlpBRAM_mReqF_first__16_BITS_127_T_ETC___d716[15:8], + SEL_ARR_tlp_tlpBRAM_mReqF_first__16_BITS_127_T_ETC___d716[23:16], + SEL_ARR_tlp_tlpBRAM_mReqF_first__16_BITS_127_T_ETC___d716[31:24] } ; + always@(idx__h25886 or tlp_tlpBRAM_writeDWAddr or - tlp_tlpBRAM_writeDWAddr_PLUS_1__q10 or - tlp_tlpBRAM_writeDWAddr_PLUS_2__q11) + tlp_tlpBRAM_writeDWAddr_PLUS_1__q8 or + tlp_tlpBRAM_writeDWAddr_PLUS_2__q9 or + tlp_tlpBRAM_writeDWAddr_PLUS_3__q10) begin - case (idx__h24026) - 2'd0: MUX_bram_memory_3$a_put_2__VAL_3 = tlp_tlpBRAM_writeDWAddr[12:2]; + case (idx__h25886) + 2'd0: MUX_bram_3_memory$a_put_2__VAL_1 = tlp_tlpBRAM_writeDWAddr[12:2]; 2'd1: - MUX_bram_memory_3$a_put_2__VAL_3 = - tlp_tlpBRAM_writeDWAddr_PLUS_1__q10[12:2]; + MUX_bram_3_memory$a_put_2__VAL_1 = + tlp_tlpBRAM_writeDWAddr_PLUS_1__q8[12:2]; 2'd2: - MUX_bram_memory_3$a_put_2__VAL_3 = - tlp_tlpBRAM_writeDWAddr_PLUS_2__q11[12:2]; + MUX_bram_3_memory$a_put_2__VAL_1 = + tlp_tlpBRAM_writeDWAddr_PLUS_2__q9[12:2]; 2'd3: - MUX_bram_memory_3$a_put_2__VAL_3 = - tlp_tlpBRAM_writeDWAddr_PLUS_3__q9[12:2]; + MUX_bram_3_memory$a_put_2__VAL_1 = + tlp_tlpBRAM_writeDWAddr_PLUS_3__q10[12:2]; endcase end - always@(idx__h27481 or - tlp_tlpBRAM_readNxtDWAddr_PLUS_3__q12 or + always@(idx__h28890 or tlp_tlpBRAM_readNxtDWAddr or - tlp_tlpBRAM_readNxtDWAddr_PLUS_1__q13 or - tlp_tlpBRAM_readNxtDWAddr_PLUS_2__q14) + tlp_tlpBRAM_readNxtDWAddr_PLUS_1__q11 or + tlp_tlpBRAM_readNxtDWAddr_PLUS_2__q12 or + tlp_tlpBRAM_readNxtDWAddr_PLUS_3__q13) begin - case (idx__h27481) + case (idx__h28890) 2'd0: - MUX_bram_memory_3$a_put_2__VAL_4 = tlp_tlpBRAM_readNxtDWAddr[12:2]; + MUX_bram_3_memory$a_put_2__VAL_4 = tlp_tlpBRAM_readNxtDWAddr[12:2]; 2'd1: - MUX_bram_memory_3$a_put_2__VAL_4 = - tlp_tlpBRAM_readNxtDWAddr_PLUS_1__q13[12:2]; + MUX_bram_3_memory$a_put_2__VAL_4 = + tlp_tlpBRAM_readNxtDWAddr_PLUS_1__q11[12:2]; 2'd2: - MUX_bram_memory_3$a_put_2__VAL_4 = - tlp_tlpBRAM_readNxtDWAddr_PLUS_2__q14[12:2]; + MUX_bram_3_memory$a_put_2__VAL_4 = + tlp_tlpBRAM_readNxtDWAddr_PLUS_2__q12[12:2]; 2'd3: - MUX_bram_memory_3$a_put_2__VAL_4 = - tlp_tlpBRAM_readNxtDWAddr_PLUS_3__q12[12:2]; + MUX_bram_3_memory$a_put_2__VAL_4 = + tlp_tlpBRAM_readNxtDWAddr_PLUS_3__q13[12:2]; endcase end - assign MUX_bram_memory_3$a_put_3__VAL_3 = - { IF_3_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2480[7:0], - IF_3_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2480[15:8], - IF_3_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2480[23:16], - IF_3_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2480[31:24] } ; + assign MUX_bram_3_memory$a_put_3__VAL_1 = + { SEL_ARR_tlp_tlpBRAM_mReqF_first__16_BITS_127_T_ETC___d724[7:0], + SEL_ARR_tlp_tlpBRAM_mReqF_first__16_BITS_127_T_ETC___d724[15:8], + SEL_ARR_tlp_tlpBRAM_mReqF_first__16_BITS_127_T_ETC___d724[23:16], + SEL_ARR_tlp_tlpBRAM_mReqF_first__16_BITS_127_T_ETC___d724[31:24] } ; assign MUX_tlp_dmaDoTailEvent$write_1__VAL_1 = - tlp_dmaPullRemainDWSub_495_ULE_4___d2626 && - tlp_dmaPullRemainDWLen_481_ULE_tlp_dmaPullRema_ETC___d2625 ; + tlp_dmaPullRemainDWSub_387_ULE_4___d1388 && + tlp_dmaPullRemainDWLen_373_ULE_tlp_dmaPullRema_ETC___d1395 ; assign MUX_tlp_dmaPullRemainDWLen$write_1__VAL_2 = tlp_dmaPullRemainDWLen - 10'd1 ; assign MUX_tlp_dmaPullRemainDWLen$write_1__VAL_3 = - tlp_dmaPullRemainDWSub_495_ULE_4___d2626 ? + tlp_dmaPullRemainDWSub_387_ULE_4___d1388 ? tlp_dmaPullRemainDWLen - tlp_dmaPullRemainDWSub : tlp_dmaPullRemainDWLen - 10'd4 ; assign MUX_tlp_dmaPullRemainDWSub$write_1__VAL_1 = tlp_inF$D_OUT[105:96] - 10'd1 ; assign MUX_tlp_dmaPullRemainDWSub$write_1__VAL_2 = - tlp_dmaPullRemainDWSub_495_ULE_4___d2626 ? + tlp_dmaPullRemainDWSub_387_ULE_4___d1388 ? 10'd0 : tlp_dmaPullRemainDWSub - 10'd4 ; assign MUX_tlp_doorSeqDwell$write_1__VAL_1 = tlp_doorSeqDwell - 4'd1 ; - assign MUX_tlp_fabMesgAccu$write_1__VAL_2 = tlp_fabMesgAccu + y__h46773 ; - assign MUX_tlp_fabMesgAccu$write_1__VAL_3 = tlp_fabMesgAccu + y__h62350 ; + assign MUX_tlp_fabMesgAccu$write_1__VAL_2 = tlp_fabMesgAccu + y__h48181 ; + assign MUX_tlp_fabMesgAccu$write_1__VAL_3 = tlp_fabMesgAccu + y__h63989 ; assign MUX_tlp_fabMeta$write_1__VAL_1 = { 1'd1, - x__h45847, - opcode__h42670, - nowMS__h43901, - nowLS__h44844 } ; + x__h47258, + opcode__h44022, + nowMS__h45280, + nowLS__h46239 } ; assign MUX_tlp_fabMeta$write_1__VAL_3 = { 1'd1, - x__h61968, - opcode__h58837, - nowMS__h60057, - nowLS__h60998 } ; + x__h63608, + opcode__h60417, + nowMS__h61665, + nowLS__h62622 } ; assign MUX_tlp_lastRuleFired$write_1__VAL_3 = (tlp_fabFlowAddrMS == 32'd0) ? 4'd8 : @@ -3286,36 +3295,42 @@ module mkOCDP16B(pciDevice, assign MUX_tlp_mesgComplReceived$write_1__VAL_1 = tlp_mesgComplReceived + 17'd4 ; assign MUX_tlp_mesgComplReceived$write_1__VAL_2 = - tlp_mesgComplReceived + y__h63671 ; + tlp_mesgComplReceived + y__h65310 ; assign MUX_tlp_mesgLengthRemainPull$write_1__VAL_1 = { tlp_inF$D_OUT[8], tlp_inF$D_OUT[23:16], tlp_inF$D_OUT[31:24] } ; assign MUX_tlp_mesgLengthRemainPull$write_1__VAL_2 = - { tlp_mesgLengthRemainPull_PLUS_3__q15[16:2], 2'd0 } ; + { tlp_mesgLengthRemainPull_PLUS_3__q14[16:2], 2'd0 } ; assign MUX_tlp_mesgLengthRemainPull$write_1__VAL_3 = - tlp_mesgLengthRemainPull - y__h62279 ; + tlp_mesgLengthRemainPull - y__h63918 ; assign MUX_tlp_mesgLengthRemainPush$write_1__VAL_1 = - { tlp_mesgLengthRemainPush_PLUS_3__q16[16:2], 2'd0 } ; + { tlp_mesgLengthRemainPush_PLUS_3__q15[16:2], 2'd0 } ; assign MUX_tlp_mesgLengthRemainPush$write_1__VAL_2 = { tlp_tlpBRAM_mRespF$D_OUT[8], tlp_tlpBRAM_mRespF$D_OUT[23:16], tlp_tlpBRAM_mRespF$D_OUT[31:24] } ; assign MUX_tlp_mesgLengthRemainPush$write_1__VAL_3 = - tlp_mesgLengthRemainPush - y__h46119 ; + tlp_mesgLengthRemainPush - y__h47529 ; assign MUX_tlp_outDwRemain$write_1__VAL_1 = - tlp_tlpBRAM_mRespF$D_OUT[71:62] - y__h46739 ; + tlp_tlpBRAM_mRespF$D_OUT[71:62] - y__h48147 ; assign MUX_tlp_outDwRemain$write_1__VAL_2 = tlp_outDwRemain - 10'd4 ; assign MUX_tlp_outDwRemain$write_1__VAL_3 = tlp_tlpBRAM_mRespF$D_OUT[71:62] - 10'd1 ; assign MUX_tlp_outF$enq_1__VAL_1 = + { 1'd0, + tlp_outDwRemain_129_ULE_4___d1130, + 7'h02, + w_be__h48508, + tlp_tlpBRAM_mRespF$D_OUT[127:0] } ; + assign MUX_tlp_outF$enq_1__VAL_2 = (tlp_fabMesgAddrMS == 32'd0) ? { 1'd1, tlp_tlpBRAM_mRespF$D_OUT[71:62] == 10'd1, 23'd196607, - w_data__h46507 } : - { 25'd16973823, w_data__h46644 } ; - assign MUX_tlp_outF$enq_1__VAL_2 = + w_data__h47916 } : + { 25'd16973823, w_data__h48052 } ; + assign MUX_tlp_outF$enq_1__VAL_3 = { 25'd16973823, (tlp_fabMetaAddrMS == 32'd0) ? 32'd1073741828 : 32'd1610612740, pciDevice, @@ -3327,7 +3342,7 @@ module mkOCDP16B(pciDevice, tlp_fabMeta[119:112], tlp_fabMeta[127:120] } : { tlp_fabMetaAddrMS, tlp_fabMetaAddr } } ; - assign MUX_tlp_outF$enq_1__VAL_3 = + assign MUX_tlp_outF$enq_1__VAL_4 = (tlp_fabMetaAddrMS == 32'd0) ? { 25'd8585200, tlp_fabMeta[71:64], @@ -3343,41 +3358,35 @@ module mkOCDP16B(pciDevice, tlp_fabMeta[23:16], tlp_fabMeta[31:24], tlp_fabMetaAddrMS } : - { 25'd8585215, w_data__h51409 } ; - assign MUX_tlp_outF$enq_1__VAL_4 = + { 25'd8585215, w_data__h52877 } ; + assign MUX_tlp_outF$enq_1__VAL_5 = { 9'd386, (tlp_fabMetaAddrMS == 32'd0) ? 16'hFFF0 : 16'd65535, - IF_tlp_fabMetaAddrMS_265_EQ_0_266_THEN_4_ELSE__ETC___d1356 } ; - assign MUX_tlp_outF$enq_1__VAL_5 = + IF_tlp_fabMetaAddrMS_157_EQ_0_158_THEN_4_ELSE__ETC___d1248 } ; + assign MUX_tlp_outF$enq_1__VAL_6 = { 9'd386, (tlp_fabMesgAddrMS == 32'd0) ? 16'hFFF0 : 16'd65535, - IF_tlp_fabMesgAddrMS_186_EQ_0_187_THEN_0_ELSE__ETC___d1461 } ; - assign MUX_tlp_outF$enq_1__VAL_6 = + IF_tlp_fabMesgAddrMS_078_EQ_0_079_THEN_0_ELSE__ETC___d1353 } ; + assign MUX_tlp_outF$enq_1__VAL_7 = (tlp_fabFlowAddrMS == 32'd0) ? - { 25'd25362431, w_data__h64198 } : + { 25'd25362431, w_data__h65836 } : (tlp_sentTail4DWHeader ? - { 25'd8581120, w_data__h65532 } : - { 25'd16973823, w_data__h65286 }) ; - assign MUX_tlp_outF$enq_1__VAL_7 = + { 25'd8581120, w_data__h67186 } : + { 25'd16973823, w_data__h66940 }) ; + assign MUX_tlp_outF$enq_1__VAL_8 = { 1'd1, tlp_tlpBRAM_mRespF$D_OUT[71:62] == 10'd1, 23'd196607, - pkt__h70068 } ; - assign MUX_tlp_outF$enq_1__VAL_8 = - { 1'd0, - tlp_outDwRemain_237_ULE_4___d2557, - 7'h02, - w_be__h47101, - tlp_tlpBRAM_mRespF$D_OUT[127:0] } ; + pkt__h71785 } ; assign MUX_tlp_postSeqDwell$write_1__VAL_1 = (dpControl[1:0] == 2'd2) ? 4'd8 : 4'd4 ; assign MUX_tlp_postSeqDwell$write_1__VAL_2 = tlp_postSeqDwell - 4'd1 ; - assign MUX_tlp_remMesgAccu$write_1__VAL_2 = tlp_remMesgAccu + y__h46261 ; - assign MUX_tlp_remMesgAccu$write_1__VAL_3 = tlp_remMesgAccu + y__h62959 ; + assign MUX_tlp_remMesgAccu$write_1__VAL_2 = tlp_remMesgAccu + y__h47671 ; + assign MUX_tlp_remMesgAccu$write_1__VAL_3 = tlp_remMesgAccu + y__h64598 ; assign MUX_tlp_reqMesgInFlight$write_1__VAL_2 = - !tlp_dmaPullRemainDWSub_495_ULE_4___d2626 || - !tlp_dmaPullRemainDWLen_481_ULE_tlp_dmaPullRema_ETC___d2625 ; - assign MUX_tlp_srcMesgAccu$write_1__VAL_2 = tlp_srcMesgAccu + y__h46213 ; + !tlp_dmaPullRemainDWSub_387_ULE_4___d1388 || + !tlp_dmaPullRemainDWLen_373_ULE_tlp_dmaPullRema_ETC___d1395 ; + assign MUX_tlp_srcMesgAccu$write_1__VAL_2 = tlp_srcMesgAccu + y__h47623 ; assign MUX_tlp_tlpBRAM_mReqF$enq_1__VAL_1 = tlp_inF$D_OUT[152] ? (tlp_inF$D_OUT[126] ? @@ -3396,63 +3405,63 @@ module mkOCDP16B(pciDevice, tlp_inF$D_OUT[79:72], tlp_inF$D_OUT[118:116] }) : { 2'd1, tlp_inF$D_OUT[127:0] } ; - assign MUX_tlp_tlpBRAM_mReqF$enq_1__VAL_2 = + assign MUX_tlp_tlpBRAM_mReqF$enq_1__VAL_2 = { 2'd1, tlp_inF$D_OUT[127:0] } ; + assign MUX_tlp_tlpBRAM_mReqF$enq_1__VAL_3 = { 88'h955555555555555553FFF8, tlp_remMetaAddr[14:2], 29'd2620074 } ; - assign MUX_tlp_tlpBRAM_mReqF$enq_1__VAL_3 = + assign MUX_tlp_tlpBRAM_mReqF$enq_1__VAL_4 = { 69'h12AAAAAAAAAAAAAAAA, tlp_fabMesgAddrMS != 32'd0, 18'd196600, tlp_remMesgAccu[14:2], - thisRequestLength__h46094[11:2], + thisRequestLength__h47504[11:2], 8'd255, - rreq_tag__h46309, + rreq_tag__h47719, 3'h2 } ; - assign MUX_tlp_tlpBRAM_mReqF$enq_1__VAL_4 = + assign MUX_tlp_tlpBRAM_mReqF$enq_1__VAL_5 = { 67'h15555555555555554, tlp_remMetaAddr[14:2], 18'd1279, tlp_inF$D_OUT[31:0] } ; - assign MUX_tlp_tlpBRAM_mReqF$enq_1__VAL_5 = + assign MUX_tlp_tlpBRAM_mReqF$enq_1__VAL_6 = { 67'h15555555555555554, tlp_remMesgAccu[14:2], tlp_inF$D_OUT[105:96], 8'd255, tlp_inF$D_OUT[31:0] } ; - assign MUX_tlp_tlpBRAM_mReqF$enq_1__VAL_6 = { 2'd1, tlp_inF$D_OUT[127:0] } ; assign MUX_tlp_tlpBRAM_mRespF$enq_1__VAL_1 = { 48'h2AAAAAAAAAAA, !tlp_tlpBRAM_readReq$D_OUT[60], tlp_tlpBRAM_readReq$D_OUT[59:42], tlp_tlpBRAM_readReq$D_OUT[28:19], - lowAddr__h28411, - byteCount__h28412, + lowAddr__h29652, + byteCount__h29653, tlp_tlpBRAM_readReq$D_OUT[10:0], - rresp_data__h28457 } ; + rresp_data__h29698 } ; assign MUX_tlp_tlpBRAM_mRespF$enq_1__VAL_2 = { 1'd1, tlp_tlpBRAM_readReq$D_OUT[59:58], tlp_tlpBRAM_readReq$D_OUT[10:3], - rdata__h33850 } ; + rdata__h35173 } ; assign MUX_tlp_tlpBRAM_rdRespDwRemain$write_1__VAL_1 = - tlp_tlpBRAM_readReq$D_OUT[28:19] - y__h29472 ; + tlp_tlpBRAM_readReq$D_OUT[28:19] - y__h30729 ; assign MUX_tlp_tlpBRAM_rdRespDwRemain$write_1__VAL_2 = tlp_tlpBRAM_rdRespDwRemain - 10'd4 ; assign MUX_tlp_tlpBRAM_readNxtDWAddr$write_1__VAL_1 = - tlp_tlpBRAM_mReqF$D_OUT[41:29] + y__h26049 ; + tlp_tlpBRAM_mReqF$D_OUT[41:29] + y__h27665 ; assign MUX_tlp_tlpBRAM_readNxtDWAddr$write_1__VAL_2 = tlp_tlpBRAM_readNxtDWAddr + 13'd4 ; assign MUX_tlp_tlpBRAM_readRemainDWLen$write_1__VAL_1 = - tlp_tlpBRAM_mReqF$D_OUT[28:19] - y__h26037 ; + tlp_tlpBRAM_mReqF$D_OUT[28:19] - y__h27653 ; assign MUX_tlp_tlpBRAM_readRemainDWLen$write_1__VAL_2 = tlp_tlpBRAM_readRemainDWLen - 10'd4 ; assign MUX_tlp_tlpBRAM_writeDWAddr$write_1__VAL_1 = - tlp_tlpBRAM_mReqF$D_OUT[62:50] + y__h17488 ; + tlp_tlpBRAM_mReqF$D_OUT[62:50] + y__h17362 ; assign MUX_tlp_tlpBRAM_writeDWAddr$write_1__VAL_2 = tlp_tlpBRAM_writeDWAddr + 13'd4 ; assign MUX_tlp_tlpBRAM_writeRemainDWLen$write_1__VAL_1 = - tlp_tlpBRAM_mReqF$D_OUT[49:40] - y__h17555 ; + tlp_tlpBRAM_mReqF$D_OUT[49:40] - y__h17428 ; assign MUX_tlp_tlpBRAM_writeRemainDWLen$write_1__VAL_2 = tlp_tlpBRAM_writeRemainDWLen - 10'd4 ; assign MUX_tlp_tlpXmtBusy$write_1__VAL_1 = @@ -3461,10 +3470,9 @@ module mkOCDP16B(pciDevice, assign MUX_wci_illegalEdge$write_1__VAL_2 = wci_reqF$D_OUT[36:34] != 3'd4 && wci_reqF$D_OUT[36:34] != 3'd5 && wci_reqF$D_OUT[36:34] != 3'd6 ; - assign MUX_wci_respF_c_r$write_1__VAL_1 = wci_respF_c_r + 2'd1 ; - assign MUX_wci_respF_c_r$write_1__VAL_2 = wci_respF_c_r - 2'd1 ; + assign MUX_wci_respF_cntr_r$write_1__VAL_2 = wci_respF_cntr_r + 2'd1 ; assign MUX_wci_respF_q_0$write_1__VAL_1 = - (wci_respF_c_r == 2'd1) ? + (wci_respF_cntr_r == 2'd1) ? MUX_wci_respF_q_0$write_1__VAL_2 : wci_respF_q_1 ; always@(WILL_FIRE_RL_wci_ctl_op_complete or @@ -3485,12 +3493,12 @@ module mkOCDP16B(pciDevice, endcase end assign MUX_wci_respF_q_1$write_1__VAL_1 = - (wci_respF_c_r == 2'd2) ? + (wci_respF_cntr_r == 2'd2) ? MUX_wci_respF_q_0$write_1__VAL_2 : 34'h0AAAAAAAA ; assign MUX_wci_respF_x_wire$wset_1__VAL_1 = wci_illegalEdge ? 34'h3C0DE4202 : 34'h1C0DE4201 ; - assign MUX_wci_respF_x_wire$wset_1__VAL_2 = { 2'd1, _theResult____h90410 } ; + assign MUX_wci_respF_x_wire$wset_1__VAL_2 = { 2'd1, _theResult____h91947 } ; assign MUX_wmi_addr$write_1__VAL_1 = wmi_addr + 14'd16 ; assign MUX_wmi_bufDwell$write_1__VAL_3 = wmi_bufDwell - 2'd1 ; assign MUX_wmi_bytesRemainReq$write_1__VAL_1 = wmi_bytesRemainReq - 14'd16 ; @@ -3501,297 +3509,296 @@ module mkOCDP16B(pciDevice, assign MUX_wmi_mesgCount$write_1__VAL_1 = wmi_mesgCount + 32'd1 ; assign MUX_wmi_mesgMeta$write_1__VAL_2 = { 1'd1, - bram_serverAdapterB_outData_outData$wget, - bram_serverAdapterB_1_outData_outData$wget, - bram_serverAdapterB_2_outData_outData$wget, - bram_serverAdapterB_3_outData_outData$wget } ; - assign MUX_wmi_wmi_respF_c_r$write_1__VAL_1 = wmi_wmi_respF_c_r + 2'd1 ; - assign MUX_wmi_wmi_respF_c_r$write_1__VAL_2 = wmi_wmi_respF_c_r - 2'd1 ; + bram_0_serverAdapterB_outData_outData$wget, + bram_1_serverAdapterB_outData_outData$wget, + bram_2_serverAdapterB_outData_outData$wget, + bram_3_serverAdapterB_outData_outData$wget } ; + assign MUX_wmi_wmi_respF_cntr_r$write_1__VAL_2 = + wmi_wmi_respF_cntr_r + 2'd1 ; assign MUX_wmi_wmi_respF_q_0$write_1__VAL_1 = - (wmi_wmi_respF_c_r == 2'd1) ? + (wmi_wmi_respF_cntr_r == 2'd1) ? MUX_wmi_wmi_respF_q_0$write_1__VAL_2 : wmi_wmi_respF_q_1 ; - assign MUX_wmi_wmi_respF_q_0$write_1__VAL_2 = { 2'd1, rdata__h82127 } ; + assign MUX_wmi_wmi_respF_q_0$write_1__VAL_2 = { 2'd1, rdata__h83703 } ; assign MUX_wmi_wmi_respF_q_1$write_1__VAL_1 = - (wmi_wmi_respF_c_r == 2'd2) ? + (wmi_wmi_respF_cntr_r == 2'd2) ? MUX_wmi_wmi_respF_q_0$write_1__VAL_2 : 130'd0 ; // inlined wires - assign bram_serverAdapterA_outData_enqData$wget = bram_memory$DOA ; - assign bram_serverAdapterA_outData_enqData$whas = - (!bram_serverAdapterA_s1[0] || - bram_serverAdapterA_outDataCore$FULL_N) && - bram_serverAdapterA_s1[1] && - bram_serverAdapterA_s1[0] ; - assign bram_serverAdapterA_outData_outData$wget = - bram_serverAdapterA_outDataCore$EMPTY_N ? - bram_serverAdapterA_outDataCore$D_OUT : - bram_memory$DOA ; - assign bram_serverAdapterA_outData_outData$whas = - bram_serverAdapterA_outDataCore$EMPTY_N || - !bram_serverAdapterA_outDataCore$EMPTY_N && - bram_serverAdapterA_outData_enqData$whas ; - assign bram_serverAdapterA_cnt_1$wget = 3'd1 ; - assign bram_serverAdapterA_cnt_1$whas = - (MUX_bram_memory$a_put_1__SEL_1 || - MUX_bram_memory$a_put_1__SEL_2 || - MUX_bram_memory$a_put_1__SEL_3 || + assign bram_0_serverAdapterA_outData_enqData$wget = bram_0_memory$DOA ; + assign bram_0_serverAdapterA_outData_enqData$whas = + (!bram_0_serverAdapterA_s1[0] || + bram_0_serverAdapterA_outDataCore$FULL_N) && + bram_0_serverAdapterA_s1[1] && + bram_0_serverAdapterA_s1[0] ; + assign bram_0_serverAdapterA_outData_outData$wget = + bram_0_serverAdapterA_outDataCore$EMPTY_N ? + bram_0_serverAdapterA_outDataCore$D_OUT : + bram_0_memory$DOA ; + assign bram_0_serverAdapterA_outData_outData$whas = + bram_0_serverAdapterA_outDataCore$EMPTY_N || + !bram_0_serverAdapterA_outDataCore$EMPTY_N && + bram_0_serverAdapterA_outData_enqData$whas ; + assign bram_0_serverAdapterA_cnt_1$wget = 3'd1 ; + assign bram_0_serverAdapterA_cnt_1$whas = + (MUX_bram_0_memory$a_put_1__SEL_1 || + MUX_bram_0_memory$a_put_1__SEL_2 || + MUX_bram_0_memory$a_put_1__SEL_3 || WILL_FIRE_RL_tlp_tlpBRAM_read_NextReq) && - (!ab__h1613[1] || ab__h1613[0]) ; - assign bram_serverAdapterA_cnt_2$wget = 3'd7 ; - assign bram_serverAdapterA_cnt_2$whas = - bram_serverAdapterA_outData_deqCalled$whas ; - assign bram_serverAdapterA_cnt_3$wget = 3'h0 ; - assign bram_serverAdapterA_cnt_3$whas = 1'b0 ; - assign bram_serverAdapterA_writeWithResp$wget = ab__h1613 ; - assign bram_serverAdapterA_writeWithResp$whas = - MUX_bram_memory$a_put_1__SEL_1 || - MUX_bram_memory$a_put_1__SEL_2 || - MUX_bram_memory$a_put_1__SEL_3 || + (!ab__h1619[1] || ab__h1619[0]) ; + assign bram_0_serverAdapterA_cnt_2$wget = 3'd7 ; + assign bram_0_serverAdapterA_cnt_2$whas = + bram_0_serverAdapterA_outData_deqCalled$whas ; + assign bram_0_serverAdapterA_cnt_3$wget = 3'h0 ; + assign bram_0_serverAdapterA_cnt_3$whas = 1'b0 ; + assign bram_0_serverAdapterA_writeWithResp$wget = ab__h1619 ; + assign bram_0_serverAdapterA_writeWithResp$whas = + MUX_bram_0_memory$a_put_1__SEL_1 || + MUX_bram_0_memory$a_put_1__SEL_2 || + MUX_bram_0_memory$a_put_1__SEL_3 || WILL_FIRE_RL_tlp_tlpBRAM_read_NextReq ; - assign bram_serverAdapterA_s1_1$wget = - { 1'd1, !ab__h1613[1] || ab__h1613[0] } ; - assign bram_serverAdapterA_s1_1$whas = - bram_serverAdapterA_writeWithResp$whas ; - assign bram_serverAdapterB_outData_enqData$wget = bram_memory$DOB ; - assign bram_serverAdapterB_outData_enqData$whas = - (!bram_serverAdapterB_s1[0] || - bram_serverAdapterB_outDataCore$FULL_N) && - bram_serverAdapterB_s1[1] && - bram_serverAdapterB_s1[0] ; - assign bram_serverAdapterB_outData_outData$wget = - bram_serverAdapterB_outDataCore$EMPTY_N ? - bram_serverAdapterB_outDataCore$D_OUT : - bram_memory$DOB ; - assign bram_serverAdapterB_outData_outData$whas = - bram_serverAdapterB_outDataCore$EMPTY_N || - !bram_serverAdapterB_outDataCore$EMPTY_N && - bram_serverAdapterB_outData_enqData$whas ; - assign bram_serverAdapterB_cnt_1$wget = 3'd1 ; - assign bram_serverAdapterB_cnt_1$whas = + assign bram_0_serverAdapterA_s1_1$wget = + { 1'd1, !ab__h1619[1] || ab__h1619[0] } ; + assign bram_0_serverAdapterA_s1_1$whas = + bram_0_serverAdapterA_writeWithResp$whas ; + assign bram_0_serverAdapterB_outData_enqData$wget = bram_0_memory$DOB ; + assign bram_0_serverAdapterB_outData_enqData$whas = + (!bram_0_serverAdapterB_s1[0] || + bram_0_serverAdapterB_outDataCore$FULL_N) && + bram_0_serverAdapterB_s1[1] && + bram_0_serverAdapterB_s1[0] ; + assign bram_0_serverAdapterB_outData_outData$wget = + bram_0_serverAdapterB_outDataCore$EMPTY_N ? + bram_0_serverAdapterB_outDataCore$D_OUT : + bram_0_memory$DOB ; + assign bram_0_serverAdapterB_outData_outData$whas = + bram_0_serverAdapterB_outDataCore$EMPTY_N || + !bram_0_serverAdapterB_outDataCore$EMPTY_N && + bram_0_serverAdapterB_outData_enqData$whas ; + assign bram_0_serverAdapterB_cnt_1$wget = 3'd1 ; + assign bram_0_serverAdapterB_cnt_1$whas = (WILL_FIRE_RL_wmi_reqMetadata || WILL_FIRE_RL_wmi_doReadReq || WILL_FIRE_RL_wmi_doWriteReq || WILL_FIRE_RL_wmi_doWriteFinalize) && - (!ab__h3019[1] || ab__h3019[0]) ; - assign bram_serverAdapterB_cnt_2$wget = 3'd7 ; - assign bram_serverAdapterB_cnt_2$whas = - bram_serverAdapterB_outData_deqCalled$whas ; - assign bram_serverAdapterB_cnt_3$wget = 3'h0 ; - assign bram_serverAdapterB_cnt_3$whas = 1'b0 ; - assign bram_serverAdapterB_writeWithResp$wget = ab__h3019 ; - assign bram_serverAdapterB_writeWithResp$whas = + (!ab__h3026[1] || ab__h3026[0]) ; + assign bram_0_serverAdapterB_cnt_2$wget = 3'd7 ; + assign bram_0_serverAdapterB_cnt_2$whas = + bram_0_serverAdapterB_outData_deqCalled$whas ; + assign bram_0_serverAdapterB_cnt_3$wget = 3'h0 ; + assign bram_0_serverAdapterB_cnt_3$whas = 1'b0 ; + assign bram_0_serverAdapterB_writeWithResp$wget = ab__h3026 ; + assign bram_0_serverAdapterB_writeWithResp$whas = WILL_FIRE_RL_wmi_reqMetadata || WILL_FIRE_RL_wmi_doReadReq || WILL_FIRE_RL_wmi_doWriteReq || WILL_FIRE_RL_wmi_doWriteFinalize ; - assign bram_serverAdapterB_s1_1$wget = - { 1'd1, !ab__h3019[1] || ab__h3019[0] } ; - assign bram_serverAdapterB_s1_1$whas = - bram_serverAdapterB_writeWithResp$whas ; - assign bram_serverAdapterA_1_outData_enqData$wget = bram_memory_1$DOA ; - assign bram_serverAdapterA_1_outData_enqData$whas = - (!bram_serverAdapterA_1_s1[0] || - bram_serverAdapterA_1_outDataCore$FULL_N) && - bram_serverAdapterA_1_s1[1] && - bram_serverAdapterA_1_s1[0] ; - assign bram_serverAdapterA_1_outData_outData$wget = - bram_serverAdapterA_1_outDataCore$EMPTY_N ? - bram_serverAdapterA_1_outDataCore$D_OUT : - bram_memory_1$DOA ; - assign bram_serverAdapterA_1_outData_outData$whas = - bram_serverAdapterA_1_outDataCore$EMPTY_N || - !bram_serverAdapterA_1_outDataCore$EMPTY_N && - bram_serverAdapterA_1_outData_enqData$whas ; - assign bram_serverAdapterA_1_cnt_1$wget = 3'd1 ; - assign bram_serverAdapterA_1_cnt_1$whas = - (MUX_bram_memory_1$a_put_1__SEL_1 || - MUX_bram_memory_1$a_put_1__SEL_2 || - MUX_bram_memory_1$a_put_1__SEL_3 || + assign bram_0_serverAdapterB_s1_1$wget = + { 1'd1, !ab__h3026[1] || ab__h3026[0] } ; + assign bram_0_serverAdapterB_s1_1$whas = + bram_0_serverAdapterB_writeWithResp$whas ; + assign bram_1_serverAdapterA_outData_enqData$wget = bram_1_memory$DOA ; + assign bram_1_serverAdapterA_outData_enqData$whas = + (!bram_1_serverAdapterA_s1[0] || + bram_1_serverAdapterA_outDataCore$FULL_N) && + bram_1_serverAdapterA_s1[1] && + bram_1_serverAdapterA_s1[0] ; + assign bram_1_serverAdapterA_outData_outData$wget = + bram_1_serverAdapterA_outDataCore$EMPTY_N ? + bram_1_serverAdapterA_outDataCore$D_OUT : + bram_1_memory$DOA ; + assign bram_1_serverAdapterA_outData_outData$whas = + bram_1_serverAdapterA_outDataCore$EMPTY_N || + !bram_1_serverAdapterA_outDataCore$EMPTY_N && + bram_1_serverAdapterA_outData_enqData$whas ; + assign bram_1_serverAdapterA_cnt_1$wget = 3'd1 ; + assign bram_1_serverAdapterA_cnt_1$whas = + (MUX_bram_1_memory$a_put_1__SEL_1 || + MUX_bram_1_memory$a_put_1__SEL_2 || + MUX_bram_1_memory$a_put_1__SEL_3 || WILL_FIRE_RL_tlp_tlpBRAM_read_NextReq) && - (!ab__h4561[1] || ab__h4561[0]) ; - assign bram_serverAdapterA_1_cnt_2$wget = 3'd7 ; - assign bram_serverAdapterA_1_cnt_2$whas = - bram_serverAdapterA_1_outData_deqCalled$whas ; - assign bram_serverAdapterA_1_cnt_3$wget = 3'h0 ; - assign bram_serverAdapterA_1_cnt_3$whas = 1'b0 ; - assign bram_serverAdapterA_1_writeWithResp$wget = ab__h4561 ; - assign bram_serverAdapterA_1_writeWithResp$whas = - MUX_bram_memory_1$a_put_1__SEL_1 || - MUX_bram_memory_1$a_put_1__SEL_2 || - MUX_bram_memory_1$a_put_1__SEL_3 || + (!ab__h4569[1] || ab__h4569[0]) ; + assign bram_1_serverAdapterA_cnt_2$wget = 3'd7 ; + assign bram_1_serverAdapterA_cnt_2$whas = + bram_1_serverAdapterA_outData_deqCalled$whas ; + assign bram_1_serverAdapterA_cnt_3$wget = 3'h0 ; + assign bram_1_serverAdapterA_cnt_3$whas = 1'b0 ; + assign bram_1_serverAdapterA_writeWithResp$wget = ab__h4569 ; + assign bram_1_serverAdapterA_writeWithResp$whas = + MUX_bram_1_memory$a_put_1__SEL_1 || + MUX_bram_1_memory$a_put_1__SEL_2 || + MUX_bram_1_memory$a_put_1__SEL_3 || WILL_FIRE_RL_tlp_tlpBRAM_read_NextReq ; - assign bram_serverAdapterA_1_s1_1$wget = - { 1'd1, !ab__h4561[1] || ab__h4561[0] } ; - assign bram_serverAdapterA_1_s1_1$whas = - bram_serverAdapterA_1_writeWithResp$whas ; - assign bram_serverAdapterB_1_outData_enqData$wget = bram_memory_1$DOB ; - assign bram_serverAdapterB_1_outData_enqData$whas = - (!bram_serverAdapterB_1_s1[0] || - bram_serverAdapterB_1_outDataCore$FULL_N) && - bram_serverAdapterB_1_s1[1] && - bram_serverAdapterB_1_s1[0] ; - assign bram_serverAdapterB_1_outData_outData$wget = - bram_serverAdapterB_1_outDataCore$EMPTY_N ? - bram_serverAdapterB_1_outDataCore$D_OUT : - bram_memory_1$DOB ; - assign bram_serverAdapterB_1_outData_outData$whas = - bram_serverAdapterB_1_outDataCore$EMPTY_N || - !bram_serverAdapterB_1_outDataCore$EMPTY_N && - bram_serverAdapterB_1_outData_enqData$whas ; - assign bram_serverAdapterB_1_cnt_1$wget = 3'd1 ; - assign bram_serverAdapterB_1_cnt_1$whas = + assign bram_1_serverAdapterA_s1_1$wget = + { 1'd1, !ab__h4569[1] || ab__h4569[0] } ; + assign bram_1_serverAdapterA_s1_1$whas = + bram_1_serverAdapterA_writeWithResp$whas ; + assign bram_1_serverAdapterB_outData_enqData$wget = bram_1_memory$DOB ; + assign bram_1_serverAdapterB_outData_enqData$whas = + (!bram_1_serverAdapterB_s1[0] || + bram_1_serverAdapterB_outDataCore$FULL_N) && + bram_1_serverAdapterB_s1[1] && + bram_1_serverAdapterB_s1[0] ; + assign bram_1_serverAdapterB_outData_outData$wget = + bram_1_serverAdapterB_outDataCore$EMPTY_N ? + bram_1_serverAdapterB_outDataCore$D_OUT : + bram_1_memory$DOB ; + assign bram_1_serverAdapterB_outData_outData$whas = + bram_1_serverAdapterB_outDataCore$EMPTY_N || + !bram_1_serverAdapterB_outDataCore$EMPTY_N && + bram_1_serverAdapterB_outData_enqData$whas ; + assign bram_1_serverAdapterB_cnt_1$wget = 3'd1 ; + assign bram_1_serverAdapterB_cnt_1$whas = (WILL_FIRE_RL_wmi_reqMetadata || WILL_FIRE_RL_wmi_doReadReq || WILL_FIRE_RL_wmi_doWriteReq || WILL_FIRE_RL_wmi_doWriteFinalize) && - (!ab__h5965[1] || ab__h5965[0]) ; - assign bram_serverAdapterB_1_cnt_2$wget = 3'd7 ; - assign bram_serverAdapterB_1_cnt_2$whas = - bram_serverAdapterB_outData_deqCalled$whas ; - assign bram_serverAdapterB_1_cnt_3$wget = 3'h0 ; - assign bram_serverAdapterB_1_cnt_3$whas = 1'b0 ; - assign bram_serverAdapterB_1_writeWithResp$wget = ab__h5965 ; - assign bram_serverAdapterB_1_writeWithResp$whas = - bram_serverAdapterB_writeWithResp$whas ; - assign bram_serverAdapterB_1_s1_1$wget = - { 1'd1, !ab__h5965[1] || ab__h5965[0] } ; - assign bram_serverAdapterB_1_s1_1$whas = - bram_serverAdapterB_writeWithResp$whas ; - assign bram_serverAdapterA_2_outData_enqData$wget = bram_memory_2$DOA ; - assign bram_serverAdapterA_2_outData_enqData$whas = - (!bram_serverAdapterA_2_s1[0] || - bram_serverAdapterA_2_outDataCore$FULL_N) && - bram_serverAdapterA_2_s1[1] && - bram_serverAdapterA_2_s1[0] ; - assign bram_serverAdapterA_2_outData_outData$wget = - bram_serverAdapterA_2_outDataCore$EMPTY_N ? - bram_serverAdapterA_2_outDataCore$D_OUT : - bram_memory_2$DOA ; - assign bram_serverAdapterA_2_outData_outData$whas = - bram_serverAdapterA_2_outDataCore$EMPTY_N || - !bram_serverAdapterA_2_outDataCore$EMPTY_N && - bram_serverAdapterA_2_outData_enqData$whas ; - assign bram_serverAdapterA_2_cnt_1$wget = 3'd1 ; - assign bram_serverAdapterA_2_cnt_1$whas = - (MUX_bram_memory_2$a_put_1__SEL_1 || - MUX_bram_memory_2$a_put_1__SEL_2 || - MUX_bram_memory_2$a_put_1__SEL_3 || + (!ab__h5974[1] || ab__h5974[0]) ; + assign bram_1_serverAdapterB_cnt_2$wget = 3'd7 ; + assign bram_1_serverAdapterB_cnt_2$whas = + bram_0_serverAdapterB_outData_deqCalled$whas ; + assign bram_1_serverAdapterB_cnt_3$wget = 3'h0 ; + assign bram_1_serverAdapterB_cnt_3$whas = 1'b0 ; + assign bram_1_serverAdapterB_writeWithResp$wget = ab__h5974 ; + assign bram_1_serverAdapterB_writeWithResp$whas = + bram_0_serverAdapterB_writeWithResp$whas ; + assign bram_1_serverAdapterB_s1_1$wget = + { 1'd1, !ab__h5974[1] || ab__h5974[0] } ; + assign bram_1_serverAdapterB_s1_1$whas = + bram_0_serverAdapterB_writeWithResp$whas ; + assign bram_2_serverAdapterA_outData_enqData$wget = bram_2_memory$DOA ; + assign bram_2_serverAdapterA_outData_enqData$whas = + (!bram_2_serverAdapterA_s1[0] || + bram_2_serverAdapterA_outDataCore$FULL_N) && + bram_2_serverAdapterA_s1[1] && + bram_2_serverAdapterA_s1[0] ; + assign bram_2_serverAdapterA_outData_outData$wget = + WILL_FIRE_RL_bram_2_serverAdapterA_outData_setFirstEnq ? + bram_2_memory$DOA : + bram_2_serverAdapterA_outDataCore$D_OUT ; + assign bram_2_serverAdapterA_outData_outData$whas = + WILL_FIRE_RL_bram_2_serverAdapterA_outData_setFirstEnq || + bram_2_serverAdapterA_outDataCore$EMPTY_N ; + assign bram_2_serverAdapterA_cnt_1$wget = 3'd1 ; + assign bram_2_serverAdapterA_cnt_1$whas = + (MUX_bram_2_memory$a_put_1__SEL_1 || + MUX_bram_2_memory$a_put_1__SEL_2 || + MUX_bram_2_memory$a_put_1__SEL_3 || WILL_FIRE_RL_tlp_tlpBRAM_read_NextReq) && - (!ab__h7507[1] || ab__h7507[0]) ; - assign bram_serverAdapterA_2_cnt_2$wget = 3'd7 ; - assign bram_serverAdapterA_2_cnt_2$whas = - bram_serverAdapterA_2_outData_deqCalled$whas ; - assign bram_serverAdapterA_2_cnt_3$wget = 3'h0 ; - assign bram_serverAdapterA_2_cnt_3$whas = 1'b0 ; - assign bram_serverAdapterA_2_writeWithResp$wget = ab__h7507 ; - assign bram_serverAdapterA_2_writeWithResp$whas = - MUX_bram_memory_2$a_put_1__SEL_1 || - MUX_bram_memory_2$a_put_1__SEL_2 || - MUX_bram_memory_2$a_put_1__SEL_3 || + (!ab__h7517[1] || ab__h7517[0]) ; + assign bram_2_serverAdapterA_cnt_2$wget = 3'd7 ; + assign bram_2_serverAdapterA_cnt_2$whas = + bram_2_serverAdapterA_outData_deqCalled$whas ; + assign bram_2_serverAdapterA_cnt_3$wget = 3'h0 ; + assign bram_2_serverAdapterA_cnt_3$whas = 1'b0 ; + assign bram_2_serverAdapterA_writeWithResp$wget = ab__h7517 ; + assign bram_2_serverAdapterA_writeWithResp$whas = + MUX_bram_2_memory$a_put_1__SEL_1 || + MUX_bram_2_memory$a_put_1__SEL_2 || + MUX_bram_2_memory$a_put_1__SEL_3 || WILL_FIRE_RL_tlp_tlpBRAM_read_NextReq ; - assign bram_serverAdapterA_2_s1_1$wget = - { 1'd1, !ab__h7507[1] || ab__h7507[0] } ; - assign bram_serverAdapterA_2_s1_1$whas = - bram_serverAdapterA_2_writeWithResp$whas ; - assign bram_serverAdapterB_2_outData_enqData$wget = bram_memory_2$DOB ; - assign bram_serverAdapterB_2_outData_enqData$whas = - (!bram_serverAdapterB_2_s1[0] || - bram_serverAdapterB_2_outDataCore$FULL_N) && - bram_serverAdapterB_2_s1[1] && - bram_serverAdapterB_2_s1[0] ; - assign bram_serverAdapterB_2_outData_outData$wget = - bram_serverAdapterB_2_outDataCore$EMPTY_N ? - bram_serverAdapterB_2_outDataCore$D_OUT : - bram_memory_2$DOB ; - assign bram_serverAdapterB_2_outData_outData$whas = - bram_serverAdapterB_2_outDataCore$EMPTY_N || - !bram_serverAdapterB_2_outDataCore$EMPTY_N && - bram_serverAdapterB_2_outData_enqData$whas ; - assign bram_serverAdapterB_2_cnt_1$wget = 3'd1 ; - assign bram_serverAdapterB_2_cnt_1$whas = + assign bram_2_serverAdapterA_s1_1$wget = + { 1'd1, !ab__h7517[1] || ab__h7517[0] } ; + assign bram_2_serverAdapterA_s1_1$whas = + bram_2_serverAdapterA_writeWithResp$whas ; + assign bram_2_serverAdapterB_outData_enqData$wget = bram_2_memory$DOB ; + assign bram_2_serverAdapterB_outData_enqData$whas = + (!bram_2_serverAdapterB_s1[0] || + bram_2_serverAdapterB_outDataCore$FULL_N) && + bram_2_serverAdapterB_s1[1] && + bram_2_serverAdapterB_s1[0] ; + assign bram_2_serverAdapterB_outData_outData$wget = + bram_2_serverAdapterB_outDataCore$EMPTY_N ? + bram_2_serverAdapterB_outDataCore$D_OUT : + bram_2_memory$DOB ; + assign bram_2_serverAdapterB_outData_outData$whas = + bram_2_serverAdapterB_outDataCore$EMPTY_N || + !bram_2_serverAdapterB_outDataCore$EMPTY_N && + bram_2_serverAdapterB_outData_enqData$whas ; + assign bram_2_serverAdapterB_cnt_1$wget = 3'd1 ; + assign bram_2_serverAdapterB_cnt_1$whas = (WILL_FIRE_RL_wmi_reqMetadata || WILL_FIRE_RL_wmi_doReadReq || WILL_FIRE_RL_wmi_doWriteReq || WILL_FIRE_RL_wmi_doWriteFinalize) && - (!ab__h8911[1] || ab__h8911[0]) ; - assign bram_serverAdapterB_2_cnt_2$wget = 3'd7 ; - assign bram_serverAdapterB_2_cnt_2$whas = - bram_serverAdapterB_outData_deqCalled$whas ; - assign bram_serverAdapterB_2_cnt_3$wget = 3'h0 ; - assign bram_serverAdapterB_2_cnt_3$whas = 1'b0 ; - assign bram_serverAdapterB_2_writeWithResp$wget = ab__h8911 ; - assign bram_serverAdapterB_2_writeWithResp$whas = - bram_serverAdapterB_writeWithResp$whas ; - assign bram_serverAdapterB_2_s1_1$wget = - { 1'd1, !ab__h8911[1] || ab__h8911[0] } ; - assign bram_serverAdapterB_2_s1_1$whas = - bram_serverAdapterB_writeWithResp$whas ; - assign bram_serverAdapterA_3_outData_enqData$wget = bram_memory_3$DOA ; - assign bram_serverAdapterA_3_outData_enqData$whas = - (!bram_serverAdapterA_3_s1[0] || - bram_serverAdapterA_3_outDataCore$FULL_N) && - bram_serverAdapterA_3_s1[1] && - bram_serverAdapterA_3_s1[0] ; - assign bram_serverAdapterA_3_outData_outData$wget = - bram_serverAdapterA_3_outDataCore$EMPTY_N ? - bram_serverAdapterA_3_outDataCore$D_OUT : - bram_memory_3$DOA ; - assign bram_serverAdapterA_3_outData_outData$whas = - bram_serverAdapterA_3_outDataCore$EMPTY_N || - !bram_serverAdapterA_3_outDataCore$EMPTY_N && - bram_serverAdapterA_3_outData_enqData$whas ; - assign bram_serverAdapterA_3_cnt_1$wget = 3'd1 ; - assign bram_serverAdapterA_3_cnt_1$whas = - (MUX_bram_memory_3$a_put_1__SEL_1 || - MUX_bram_memory_3$a_put_1__SEL_2 || - MUX_bram_memory_3$a_put_1__SEL_3 || + (!ab__h8922[1] || ab__h8922[0]) ; + assign bram_2_serverAdapterB_cnt_2$wget = 3'd7 ; + assign bram_2_serverAdapterB_cnt_2$whas = + bram_0_serverAdapterB_outData_deqCalled$whas ; + assign bram_2_serverAdapterB_cnt_3$wget = 3'h0 ; + assign bram_2_serverAdapterB_cnt_3$whas = 1'b0 ; + assign bram_2_serverAdapterB_writeWithResp$wget = ab__h8922 ; + assign bram_2_serverAdapterB_writeWithResp$whas = + bram_0_serverAdapterB_writeWithResp$whas ; + assign bram_2_serverAdapterB_s1_1$wget = + { 1'd1, !ab__h8922[1] || ab__h8922[0] } ; + assign bram_2_serverAdapterB_s1_1$whas = + bram_0_serverAdapterB_writeWithResp$whas ; + assign bram_3_serverAdapterA_outData_enqData$wget = bram_3_memory$DOA ; + assign bram_3_serverAdapterA_outData_enqData$whas = + (!bram_3_serverAdapterA_s1[0] || + bram_3_serverAdapterA_outDataCore$FULL_N) && + bram_3_serverAdapterA_s1[1] && + bram_3_serverAdapterA_s1[0] ; + assign bram_3_serverAdapterA_outData_outData$wget = + bram_3_serverAdapterA_outDataCore$EMPTY_N ? + bram_3_serverAdapterA_outDataCore$D_OUT : + bram_3_memory$DOA ; + assign bram_3_serverAdapterA_outData_outData$whas = + bram_3_serverAdapterA_outDataCore$EMPTY_N || + !bram_3_serverAdapterA_outDataCore$EMPTY_N && + bram_3_serverAdapterA_outData_enqData$whas ; + assign bram_3_serverAdapterA_cnt_1$wget = 3'd1 ; + assign bram_3_serverAdapterA_cnt_1$whas = + (MUX_bram_3_memory$a_put_1__SEL_1 || + MUX_bram_3_memory$a_put_1__SEL_2 || + MUX_bram_3_memory$a_put_1__SEL_3 || WILL_FIRE_RL_tlp_tlpBRAM_read_NextReq) && - (!ab__h10453[1] || ab__h10453[0]) ; - assign bram_serverAdapterA_3_cnt_2$wget = 3'd7 ; - assign bram_serverAdapterA_3_cnt_2$whas = - bram_serverAdapterA_3_outData_deqCalled$whas ; - assign bram_serverAdapterA_3_cnt_3$wget = 3'h0 ; - assign bram_serverAdapterA_3_cnt_3$whas = 1'b0 ; - assign bram_serverAdapterA_3_writeWithResp$wget = ab__h10453 ; - assign bram_serverAdapterA_3_writeWithResp$whas = - MUX_bram_memory_3$a_put_1__SEL_1 || - MUX_bram_memory_3$a_put_1__SEL_2 || - MUX_bram_memory_3$a_put_1__SEL_3 || + (!ab__h10465[1] || ab__h10465[0]) ; + assign bram_3_serverAdapterA_cnt_2$wget = 3'd7 ; + assign bram_3_serverAdapterA_cnt_2$whas = + bram_3_serverAdapterA_outData_deqCalled$whas ; + assign bram_3_serverAdapterA_cnt_3$wget = 3'h0 ; + assign bram_3_serverAdapterA_cnt_3$whas = 1'b0 ; + assign bram_3_serverAdapterA_writeWithResp$wget = ab__h10465 ; + assign bram_3_serverAdapterA_writeWithResp$whas = + MUX_bram_3_memory$a_put_1__SEL_1 || + MUX_bram_3_memory$a_put_1__SEL_2 || + MUX_bram_3_memory$a_put_1__SEL_3 || WILL_FIRE_RL_tlp_tlpBRAM_read_NextReq ; - assign bram_serverAdapterA_3_s1_1$wget = - { 1'd1, !ab__h10453[1] || ab__h10453[0] } ; - assign bram_serverAdapterA_3_s1_1$whas = - bram_serverAdapterA_3_writeWithResp$whas ; - assign bram_serverAdapterB_3_outData_enqData$wget = bram_memory_3$DOB ; - assign bram_serverAdapterB_3_outData_enqData$whas = - (!bram_serverAdapterB_3_s1[0] || - bram_serverAdapterB_3_outDataCore$FULL_N) && - bram_serverAdapterB_3_s1[1] && - bram_serverAdapterB_3_s1[0] ; - assign bram_serverAdapterB_3_outData_outData$wget = - bram_serverAdapterB_3_outDataCore$EMPTY_N ? - bram_serverAdapterB_3_outDataCore$D_OUT : - bram_memory_3$DOB ; - assign bram_serverAdapterB_3_outData_outData$whas = - bram_serverAdapterB_3_outDataCore$EMPTY_N || - !bram_serverAdapterB_3_outDataCore$EMPTY_N && - bram_serverAdapterB_3_outData_enqData$whas ; - assign bram_serverAdapterB_3_cnt_1$wget = 3'd1 ; - assign bram_serverAdapterB_3_cnt_1$whas = + assign bram_3_serverAdapterA_s1_1$wget = + { 1'd1, !ab__h10465[1] || ab__h10465[0] } ; + assign bram_3_serverAdapterA_s1_1$whas = + bram_3_serverAdapterA_writeWithResp$whas ; + assign bram_3_serverAdapterB_outData_enqData$wget = bram_3_memory$DOB ; + assign bram_3_serverAdapterB_outData_enqData$whas = + (!bram_3_serverAdapterB_s1[0] || + bram_3_serverAdapterB_outDataCore$FULL_N) && + bram_3_serverAdapterB_s1[1] && + bram_3_serverAdapterB_s1[0] ; + assign bram_3_serverAdapterB_outData_outData$wget = + bram_3_serverAdapterB_outDataCore$EMPTY_N ? + bram_3_serverAdapterB_outDataCore$D_OUT : + bram_3_memory$DOB ; + assign bram_3_serverAdapterB_outData_outData$whas = + bram_3_serverAdapterB_outDataCore$EMPTY_N || + !bram_3_serverAdapterB_outDataCore$EMPTY_N && + bram_3_serverAdapterB_outData_enqData$whas ; + assign bram_3_serverAdapterB_cnt_1$wget = 3'd1 ; + assign bram_3_serverAdapterB_cnt_1$whas = (WILL_FIRE_RL_wmi_reqMetadata || WILL_FIRE_RL_wmi_doReadReq || WILL_FIRE_RL_wmi_doWriteReq || WILL_FIRE_RL_wmi_doWriteFinalize) && - (!ab__h11857[1] || ab__h11857[0]) ; - assign bram_serverAdapterB_3_cnt_2$wget = 3'd7 ; - assign bram_serverAdapterB_3_cnt_2$whas = - bram_serverAdapterB_outData_deqCalled$whas ; - assign bram_serverAdapterB_3_cnt_3$wget = 3'h0 ; - assign bram_serverAdapterB_3_cnt_3$whas = 1'b0 ; - assign bram_serverAdapterB_3_writeWithResp$wget = ab__h11857 ; - assign bram_serverAdapterB_3_writeWithResp$whas = - bram_serverAdapterB_writeWithResp$whas ; - assign bram_serverAdapterB_3_s1_1$wget = - { 1'd1, !ab__h11857[1] || ab__h11857[0] } ; - assign bram_serverAdapterB_3_s1_1$whas = - bram_serverAdapterB_writeWithResp$whas ; + (!ab__h11870[1] || ab__h11870[0]) ; + assign bram_3_serverAdapterB_cnt_2$wget = 3'd7 ; + assign bram_3_serverAdapterB_cnt_2$whas = + bram_0_serverAdapterB_outData_deqCalled$whas ; + assign bram_3_serverAdapterB_cnt_3$wget = 3'h0 ; + assign bram_3_serverAdapterB_cnt_3$whas = 1'b0 ; + assign bram_3_serverAdapterB_writeWithResp$wget = ab__h11870 ; + assign bram_3_serverAdapterB_writeWithResp$whas = + bram_0_serverAdapterB_writeWithResp$whas ; + assign bram_3_serverAdapterB_s1_1$wget = + { 1'd1, !ab__h11870[1] || ab__h11870[0] } ; + assign bram_3_serverAdapterB_s1_1$whas = + bram_0_serverAdapterB_writeWithResp$whas ; assign wci_wciReq$wget = { wci_s_MCmd, wci_s_MAddrSpace, @@ -3800,9 +3807,7 @@ module mkOCDP16B(pciDevice, wci_s_MData } ; assign wci_wciReq$whas = 1'd1 ; assign wci_respF_x_wire$wget = MUX_wci_respF_q_0$write_1__VAL_2 ; - assign wci_respF_x_wire$whas = - WILL_FIRE_RL_wci_ctl_op_complete || WILL_FIRE_RL_wci_cfrd || - WILL_FIRE_RL_wci_cfwr ; + assign wci_respF_x_wire$whas = wci_respF_enqueueing$whas ; assign wci_wEdge$wget = wci_reqF$D_OUT[36:34] ; assign wci_wEdge$whas = WILL_FIRE_RL_wci_ctl_op_start ; assign wci_sFlagReg_1$wget = 1'b0 ; @@ -3841,8 +3846,8 @@ module mkOCDP16B(pciDevice, assign tlp_dpControl$wget = dpControl ; assign tlp_dpControl$whas = 1'd1 ; assign tlp_pullTagMatch_1$wget = - tagm__h62748 == tlp_inF$D_OUT[47:40] && - tlp_inF_first__367_BITS_63_TO_56_370_EQ_pciDev_ETC___d1380 ; + tagm__h64387 == tlp_inF$D_OUT[47:40] && + tlp_inF_first__259_BITS_63_TO_56_262_EQ_pciDev_ETC___d1272 ; assign tlp_pullTagMatch_1$whas = tlp_inF$EMPTY_N && hasPull && dpControl[7:4] == 4'd0 && dpControl[3:2] == 2'd2 && @@ -3944,43 +3949,43 @@ module mkOCDP16B(pciDevice, assign wmi_Es_mData_w$whas = 1'd1 ; assign wmi_Es_mDataByteEn_w$wget = wmiS0_MDataByteEn ; assign wmi_Es_mDataByteEn_w$whas = 1'd1 ; - assign bram_serverAdapterA_outData_deqCalled$whas = + assign bram_0_serverAdapterA_outData_deqCalled$whas = WILL_FIRE_RL_tlp_tlpBRAM_read_FirstResp && - !tlp_tlpBRAM_readReq$D_OUT[60] && - tlp_tlpBRAM_readReq$D_OUT[30:29] == 2'd0 || + tlp_tlpBRAM_readReq$D_OUT[30:29] == 2'd0 && + !tlp_tlpBRAM_readReq$D_OUT[60] || WILL_FIRE_RL_tlp_tlpBRAM_read_NextResp ; - assign bram_serverAdapterB_outData_deqCalled$whas = + assign bram_0_serverAdapterB_outData_deqCalled$whas = WILL_FIRE_RL_wmi_respMetadata || WILL_FIRE_RL_wmi_doReadResp ; - assign bram_serverAdapterA_1_outData_deqCalled$whas = + assign bram_1_serverAdapterA_outData_deqCalled$whas = WILL_FIRE_RL_tlp_tlpBRAM_read_FirstResp && - !tlp_tlpBRAM_readReq$D_OUT[60] && - tlp_tlpBRAM_readReq$D_OUT[30:29] == 2'd1 || + tlp_tlpBRAM_readReq$D_OUT[30:29] == 2'd1 && + !tlp_tlpBRAM_readReq$D_OUT[60] || WILL_FIRE_RL_tlp_tlpBRAM_read_NextResp ; - assign bram_serverAdapterB_1_outData_deqCalled$whas = - bram_serverAdapterB_outData_deqCalled$whas ; - assign bram_serverAdapterA_2_outData_deqCalled$whas = + assign bram_1_serverAdapterB_outData_deqCalled$whas = + bram_0_serverAdapterB_outData_deqCalled$whas ; + assign bram_2_serverAdapterA_outData_deqCalled$whas = WILL_FIRE_RL_tlp_tlpBRAM_read_FirstResp && - !tlp_tlpBRAM_readReq$D_OUT[60] && - tlp_tlpBRAM_readReq$D_OUT[30:29] == 2'd2 || + tlp_tlpBRAM_readReq$D_OUT[30:29] == 2'd2 && + !tlp_tlpBRAM_readReq$D_OUT[60] || WILL_FIRE_RL_tlp_tlpBRAM_read_NextResp ; - assign bram_serverAdapterB_2_outData_deqCalled$whas = - bram_serverAdapterB_outData_deqCalled$whas ; - assign bram_serverAdapterA_3_outData_deqCalled$whas = + assign bram_2_serverAdapterB_outData_deqCalled$whas = + bram_0_serverAdapterB_outData_deqCalled$whas ; + assign bram_3_serverAdapterA_outData_deqCalled$whas = WILL_FIRE_RL_tlp_tlpBRAM_read_FirstResp && - !tlp_tlpBRAM_readReq$D_OUT[60] && - tlp_tlpBRAM_readReq$D_OUT[30:29] == 2'd3 || + tlp_tlpBRAM_readReq$D_OUT[30:29] == 2'd3 && + !tlp_tlpBRAM_readReq$D_OUT[60] || WILL_FIRE_RL_tlp_tlpBRAM_read_NextResp ; - assign bram_serverAdapterB_3_outData_deqCalled$whas = - bram_serverAdapterB_outData_deqCalled$whas ; + assign bram_3_serverAdapterB_outData_deqCalled$whas = + bram_0_serverAdapterB_outData_deqCalled$whas ; assign wci_reqF_r_enq$whas = wci_wciReq$wget[71:69] != 3'd0 ; assign wci_reqF_r_deq$whas = - WILL_FIRE_RL_wci_cfwr || WILL_FIRE_RL_wci_ctl_op_start || - WILL_FIRE_RL_wci_cfrd ; + WILL_FIRE_RL_wci_ctl_op_start || WILL_FIRE_RL_wci_cfrd || + WILL_FIRE_RL_wci_cfwr ; assign wci_reqF_r_clr$whas = 1'b0 ; assign wci_respF_enqueueing$whas = - WILL_FIRE_RL_wci_cfwr || WILL_FIRE_RL_wci_ctl_op_complete || - WILL_FIRE_RL_wci_cfrd ; - assign wci_respF_dequeueing$whas = wci_respF_c_r != 2'd0 ; + WILL_FIRE_RL_wci_ctl_op_complete || WILL_FIRE_RL_wci_cfrd || + WILL_FIRE_RL_wci_cfwr ; + assign wci_respF_dequeueing$whas = wci_respF_cntr_r != 2'd0 ; assign wci_sThreadBusy_pw$whas = 1'b0 ; assign wci_wci_cfwr_pw$whas = wci_reqF$EMPTY_N && wci_reqF$D_OUT[68] && @@ -4018,7 +4023,7 @@ module mkOCDP16B(pciDevice, assign wmi_wmi_dhF_doResetDeq$whas = WILL_FIRE_RL_wmi_doWriteReq ; assign wmi_wmi_dhF_doResetClr$whas = 1'b0 ; assign wmi_wmi_respF_enqueueing$whas = WILL_FIRE_RL_wmi_doReadResp ; - assign wmi_wmi_respF_dequeueing$whas = wmi_wmi_respF_c_r != 2'd0 ; + assign wmi_wmi_respF_dequeueing$whas = wmi_wmi_respF_cntr_r != 2'd0 ; assign bml_lclBuf_incAction$whas = WILL_FIRE_RL_bml_lclAdvance ; assign bml_lclBuf_decAction$whas = 1'b0 ; assign bml_remBuf_incAction$whas = WILL_FIRE_RL_bml_remAdvance ; @@ -4202,7 +4207,8 @@ module mkOCDP16B(pciDevice, MUX_bml_lclBufsAR$write_1__VAL_1 : MUX_bml_lclBufsAR$write_1__VAL_2 ; assign bml_lclBufsAR$EN = - MUX_bml_lclBufsAR$write_1__SEL_1 || + wci_cState == 3'd2 && + IF_bml_dpControl_wget__898_BITS_1_TO_0_904_EQ__ETC___d1984 || WILL_FIRE_RL_bml_initAccumulators ; // register bml_lclBufsCF @@ -4212,8 +4218,7 @@ module mkOCDP16B(pciDevice, MUX_bml_lclBufsCF$write_1__VAL_2 ; assign bml_lclBufsCF$EN = wci_cState == 3'd2 && - (bml_lclBufDone_032_AND_IF_bml_dpControl_wget___ETC___d2443 || - NOT_bml_lclBufDone_032_099_AND_IF_bml_dpContro_ETC___d2112) || + bml_lclBufDone_922_AND_IF_bml_dpControl_wget___ETC___d2003 || WILL_FIRE_RL_bml_initAccumulators ; // register bml_lclCredit @@ -4325,117 +4330,117 @@ module mkOCDP16B(pciDevice, assign bml_remStarts$D_IN = bml_remStarts + 16'd1 ; assign bml_remStarts$EN = wci_cState == 3'd2 && bml_remStart ; - // register bram_serverAdapterA_1_cnt - assign bram_serverAdapterA_1_cnt$D_IN = - bram_serverAdapterA_1_cnt_44_PLUS_IF_bram_serv_ETC___d150 ; - assign bram_serverAdapterA_1_cnt$EN = - bram_serverAdapterA_1_cnt_1$whas || - bram_serverAdapterA_1_outData_deqCalled$whas ; - - // register bram_serverAdapterA_1_s1 - assign bram_serverAdapterA_1_s1$D_IN = - { bram_serverAdapterA_1_writeWithResp$whas && - bram_serverAdapterA_1_s1_1$wget[1], - bram_serverAdapterA_1_s1_1$wget[0] } ; - assign bram_serverAdapterA_1_s1$EN = 1'd1 ; - - // register bram_serverAdapterA_2_cnt - assign bram_serverAdapterA_2_cnt$D_IN = - bram_serverAdapterA_2_cnt_62_PLUS_IF_bram_serv_ETC___d268 ; - assign bram_serverAdapterA_2_cnt$EN = - bram_serverAdapterA_2_cnt_1$whas || - bram_serverAdapterA_2_outData_deqCalled$whas ; - - // register bram_serverAdapterA_2_s1 - assign bram_serverAdapterA_2_s1$D_IN = - { bram_serverAdapterA_2_writeWithResp$whas && - bram_serverAdapterA_2_s1_1$wget[1], - bram_serverAdapterA_2_s1_1$wget[0] } ; - assign bram_serverAdapterA_2_s1$EN = 1'd1 ; - - // register bram_serverAdapterA_3_cnt - assign bram_serverAdapterA_3_cnt$D_IN = - bram_serverAdapterA_3_cnt_80_PLUS_IF_bram_serv_ETC___d386 ; - assign bram_serverAdapterA_3_cnt$EN = - bram_serverAdapterA_3_cnt_1$whas || - bram_serverAdapterA_3_outData_deqCalled$whas ; - - // register bram_serverAdapterA_3_s1 - assign bram_serverAdapterA_3_s1$D_IN = - { bram_serverAdapterA_3_writeWithResp$whas && - bram_serverAdapterA_3_s1_1$wget[1], - bram_serverAdapterA_3_s1_1$wget[0] } ; - assign bram_serverAdapterA_3_s1$EN = 1'd1 ; - - // register bram_serverAdapterA_cnt - assign bram_serverAdapterA_cnt$D_IN = - bram_serverAdapterA_cnt_6_PLUS_IF_bram_serverA_ETC___d32 ; - assign bram_serverAdapterA_cnt$EN = - bram_serverAdapterA_cnt_1$whas || - bram_serverAdapterA_outData_deqCalled$whas ; - - // register bram_serverAdapterA_s1 - assign bram_serverAdapterA_s1$D_IN = - { bram_serverAdapterA_writeWithResp$whas && - bram_serverAdapterA_s1_1$wget[1], - bram_serverAdapterA_s1_1$wget[0] } ; - assign bram_serverAdapterA_s1$EN = 1'd1 ; - - // register bram_serverAdapterB_1_cnt - assign bram_serverAdapterB_1_cnt$D_IN = - bram_serverAdapterB_1_cnt_03_PLUS_IF_bram_serv_ETC___d209 ; - assign bram_serverAdapterB_1_cnt$EN = - bram_serverAdapterB_1_cnt_1$whas || - bram_serverAdapterB_outData_deqCalled$whas ; - - // register bram_serverAdapterB_1_s1 - assign bram_serverAdapterB_1_s1$D_IN = - { bram_serverAdapterB_writeWithResp$whas && - bram_serverAdapterB_1_s1_1$wget[1], - bram_serverAdapterB_1_s1_1$wget[0] } ; - assign bram_serverAdapterB_1_s1$EN = 1'd1 ; - - // register bram_serverAdapterB_2_cnt - assign bram_serverAdapterB_2_cnt$D_IN = - bram_serverAdapterB_2_cnt_21_PLUS_IF_bram_serv_ETC___d327 ; - assign bram_serverAdapterB_2_cnt$EN = - bram_serverAdapterB_2_cnt_1$whas || - bram_serverAdapterB_outData_deqCalled$whas ; - - // register bram_serverAdapterB_2_s1 - assign bram_serverAdapterB_2_s1$D_IN = - { bram_serverAdapterB_writeWithResp$whas && - bram_serverAdapterB_2_s1_1$wget[1], - bram_serverAdapterB_2_s1_1$wget[0] } ; - assign bram_serverAdapterB_2_s1$EN = 1'd1 ; - - // register bram_serverAdapterB_3_cnt - assign bram_serverAdapterB_3_cnt$D_IN = - bram_serverAdapterB_3_cnt_39_PLUS_IF_bram_serv_ETC___d445 ; - assign bram_serverAdapterB_3_cnt$EN = - bram_serverAdapterB_3_cnt_1$whas || - bram_serverAdapterB_outData_deqCalled$whas ; - - // register bram_serverAdapterB_3_s1 - assign bram_serverAdapterB_3_s1$D_IN = - { bram_serverAdapterB_writeWithResp$whas && - bram_serverAdapterB_3_s1_1$wget[1], - bram_serverAdapterB_3_s1_1$wget[0] } ; - assign bram_serverAdapterB_3_s1$EN = 1'd1 ; - - // register bram_serverAdapterB_cnt - assign bram_serverAdapterB_cnt$D_IN = - bram_serverAdapterB_cnt_5_PLUS_IF_bram_serverA_ETC___d91 ; - assign bram_serverAdapterB_cnt$EN = - bram_serverAdapterB_cnt_1$whas || - bram_serverAdapterB_outData_deqCalled$whas ; - - // register bram_serverAdapterB_s1 - assign bram_serverAdapterB_s1$D_IN = - { bram_serverAdapterB_writeWithResp$whas && - bram_serverAdapterB_s1_1$wget[1], - bram_serverAdapterB_s1_1$wget[0] } ; - assign bram_serverAdapterB_s1$EN = 1'd1 ; + // register bram_0_serverAdapterA_cnt + assign bram_0_serverAdapterA_cnt$D_IN = + bram_0_serverAdapterA_cnt_6_PLUS_IF_bram_0_ser_ETC___d32 ; + assign bram_0_serverAdapterA_cnt$EN = + bram_0_serverAdapterA_cnt_1$whas || + bram_0_serverAdapterA_outData_deqCalled$whas ; + + // register bram_0_serverAdapterA_s1 + assign bram_0_serverAdapterA_s1$D_IN = + { bram_0_serverAdapterA_writeWithResp$whas && + bram_0_serverAdapterA_s1_1$wget[1], + bram_0_serverAdapterA_s1_1$wget[0] } ; + assign bram_0_serverAdapterA_s1$EN = 1'd1 ; + + // register bram_0_serverAdapterB_cnt + assign bram_0_serverAdapterB_cnt$D_IN = + bram_0_serverAdapterB_cnt_5_PLUS_IF_bram_0_ser_ETC___d91 ; + assign bram_0_serverAdapterB_cnt$EN = + bram_0_serverAdapterB_cnt_1$whas || + bram_0_serverAdapterB_outData_deqCalled$whas ; + + // register bram_0_serverAdapterB_s1 + assign bram_0_serverAdapterB_s1$D_IN = + { bram_0_serverAdapterB_writeWithResp$whas && + bram_0_serverAdapterB_s1_1$wget[1], + bram_0_serverAdapterB_s1_1$wget[0] } ; + assign bram_0_serverAdapterB_s1$EN = 1'd1 ; + + // register bram_1_serverAdapterA_cnt + assign bram_1_serverAdapterA_cnt$D_IN = + bram_1_serverAdapterA_cnt_44_PLUS_IF_bram_1_se_ETC___d150 ; + assign bram_1_serverAdapterA_cnt$EN = + bram_1_serverAdapterA_cnt_1$whas || + bram_1_serverAdapterA_outData_deqCalled$whas ; + + // register bram_1_serverAdapterA_s1 + assign bram_1_serverAdapterA_s1$D_IN = + { bram_1_serverAdapterA_writeWithResp$whas && + bram_1_serverAdapterA_s1_1$wget[1], + bram_1_serverAdapterA_s1_1$wget[0] } ; + assign bram_1_serverAdapterA_s1$EN = 1'd1 ; + + // register bram_1_serverAdapterB_cnt + assign bram_1_serverAdapterB_cnt$D_IN = + bram_1_serverAdapterB_cnt_03_PLUS_IF_bram_1_se_ETC___d209 ; + assign bram_1_serverAdapterB_cnt$EN = + bram_1_serverAdapterB_cnt_1$whas || + bram_0_serverAdapterB_outData_deqCalled$whas ; + + // register bram_1_serverAdapterB_s1 + assign bram_1_serverAdapterB_s1$D_IN = + { bram_0_serverAdapterB_writeWithResp$whas && + bram_1_serverAdapterB_s1_1$wget[1], + bram_1_serverAdapterB_s1_1$wget[0] } ; + assign bram_1_serverAdapterB_s1$EN = 1'd1 ; + + // register bram_2_serverAdapterA_cnt + assign bram_2_serverAdapterA_cnt$D_IN = + bram_2_serverAdapterA_cnt_62_PLUS_IF_bram_2_se_ETC___d268 ; + assign bram_2_serverAdapterA_cnt$EN = + bram_2_serverAdapterA_cnt_1$whas || + bram_2_serverAdapterA_outData_deqCalled$whas ; + + // register bram_2_serverAdapterA_s1 + assign bram_2_serverAdapterA_s1$D_IN = + { bram_2_serverAdapterA_writeWithResp$whas && + bram_2_serverAdapterA_s1_1$wget[1], + bram_2_serverAdapterA_s1_1$wget[0] } ; + assign bram_2_serverAdapterA_s1$EN = 1'd1 ; + + // register bram_2_serverAdapterB_cnt + assign bram_2_serverAdapterB_cnt$D_IN = + bram_2_serverAdapterB_cnt_21_PLUS_IF_bram_2_se_ETC___d327 ; + assign bram_2_serverAdapterB_cnt$EN = + bram_2_serverAdapterB_cnt_1$whas || + bram_0_serverAdapterB_outData_deqCalled$whas ; + + // register bram_2_serverAdapterB_s1 + assign bram_2_serverAdapterB_s1$D_IN = + { bram_0_serverAdapterB_writeWithResp$whas && + bram_2_serverAdapterB_s1_1$wget[1], + bram_2_serverAdapterB_s1_1$wget[0] } ; + assign bram_2_serverAdapterB_s1$EN = 1'd1 ; + + // register bram_3_serverAdapterA_cnt + assign bram_3_serverAdapterA_cnt$D_IN = + bram_3_serverAdapterA_cnt_80_PLUS_IF_bram_3_se_ETC___d386 ; + assign bram_3_serverAdapterA_cnt$EN = + bram_3_serverAdapterA_cnt_1$whas || + bram_3_serverAdapterA_outData_deqCalled$whas ; + + // register bram_3_serverAdapterA_s1 + assign bram_3_serverAdapterA_s1$D_IN = + { bram_3_serverAdapterA_writeWithResp$whas && + bram_3_serverAdapterA_s1_1$wget[1], + bram_3_serverAdapterA_s1_1$wget[0] } ; + assign bram_3_serverAdapterA_s1$EN = 1'd1 ; + + // register bram_3_serverAdapterB_cnt + assign bram_3_serverAdapterB_cnt$D_IN = + bram_3_serverAdapterB_cnt_39_PLUS_IF_bram_3_se_ETC___d445 ; + assign bram_3_serverAdapterB_cnt$EN = + bram_3_serverAdapterB_cnt_1$whas || + bram_0_serverAdapterB_outData_deqCalled$whas ; + + // register bram_3_serverAdapterB_s1 + assign bram_3_serverAdapterB_s1$D_IN = + { bram_0_serverAdapterB_writeWithResp$whas && + bram_3_serverAdapterB_s1_1$wget[1], + bram_3_serverAdapterB_s1_1$wget[0] } ; + assign bram_3_serverAdapterB_s1$EN = 1'd1 ; // register dmaDoneTime assign dmaDoneTime$D_IN = wti_nowReq[63:0] ; @@ -4488,8 +4493,8 @@ module mkOCDP16B(pciDevice, endcase assign tlp_dmaDoTailEvent$EN = WILL_FIRE_RL_tlp_dmaRespBodyFarMeta || - WILL_FIRE_RL_tlp_dmaPullResponseBody || WILL_FIRE_RL_tlp_dmaPullResponseHeader || + WILL_FIRE_RL_tlp_dmaPullResponseBody || WILL_FIRE_RL_tlp_dmaPullTailEvent ; // register tlp_dmaDoneMark @@ -4498,7 +4503,7 @@ module mkOCDP16B(pciDevice, // register tlp_dmaPullRemainDWLen always@(WILL_FIRE_RL_tlp_dmaPullRequestFarMesg or - thisRequestLength__h62254 or + thisRequestLength__h63893 or WILL_FIRE_RL_tlp_dmaPullResponseHeader or MUX_tlp_dmaPullRemainDWLen$write_1__VAL_2 or WILL_FIRE_RL_tlp_dmaPullResponseBody or @@ -4506,7 +4511,7 @@ module mkOCDP16B(pciDevice, begin case (1'b1) // synopsys parallel_case WILL_FIRE_RL_tlp_dmaPullRequestFarMesg: - tlp_dmaPullRemainDWLen$D_IN = thisRequestLength__h62254[11:2]; + tlp_dmaPullRemainDWLen$D_IN = thisRequestLength__h63893[11:2]; WILL_FIRE_RL_tlp_dmaPullResponseHeader: tlp_dmaPullRemainDWLen$D_IN = MUX_tlp_dmaPullRemainDWLen$write_1__VAL_2; @@ -4636,26 +4641,25 @@ module mkOCDP16B(pciDevice, assign tlp_flowDiagCount$EN = WILL_FIRE_RL_tlp_dmaXmtDoorbell ; // register tlp_gotResponseHeader - always@(WILL_FIRE_RL_tlp_dmaPullResponseHeader or - tlp_inF$D_OUT or - WILL_FIRE_RL_tlp_dmaPullResponseBody or - tlp_dmaPullRemainDWSub_495_ULE_4___d2626 or - WILL_FIRE_RL_tlp_dmaPullRequestFarMesg) + always@(WILL_FIRE_RL_tlp_dmaPullResponseBody or + tlp_dmaPullRemainDWSub_387_ULE_4___d1388 or + WILL_FIRE_RL_tlp_dmaPullResponseHeader or + tlp_inF$D_OUT or WILL_FIRE_RL_tlp_dmaPullRequestFarMesg) begin case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_tlp_dmaPullResponseHeader: - tlp_gotResponseHeader$D_IN = tlp_inF$D_OUT[105:96] != 10'd1; WILL_FIRE_RL_tlp_dmaPullResponseBody: tlp_gotResponseHeader$D_IN = - !tlp_dmaPullRemainDWSub_495_ULE_4___d2626; + !tlp_dmaPullRemainDWSub_387_ULE_4___d1388; + WILL_FIRE_RL_tlp_dmaPullResponseHeader: + tlp_gotResponseHeader$D_IN = tlp_inF$D_OUT[105:96] != 10'd1; WILL_FIRE_RL_tlp_dmaPullRequestFarMesg: tlp_gotResponseHeader$D_IN = 1'd0; default: tlp_gotResponseHeader$D_IN = 1'b0 /* unspecified value */ ; endcase end assign tlp_gotResponseHeader$EN = - WILL_FIRE_RL_tlp_dmaPullResponseHeader || WILL_FIRE_RL_tlp_dmaPullResponseBody || + WILL_FIRE_RL_tlp_dmaPullResponseHeader || WILL_FIRE_RL_tlp_dmaPullRequestFarMesg ; // register tlp_inIgnorePkt @@ -4664,20 +4668,20 @@ module mkOCDP16B(pciDevice, tlp_inF$D_OUT[124:120] != 5'b0 ; assign tlp_inIgnorePkt$EN = WILL_FIRE_RL_tlp_tlpRcv && tlp_inF$D_OUT[152] ; - // register tlp_lastMetaV - assign tlp_lastMetaV$D_IN = + // register tlp_lastMetaV_0 + assign tlp_lastMetaV_0$D_IN = WILL_FIRE_RL_tlp_dmaResponseNearMetaHead ? - x__h40887 : - x__h56804 ; - assign tlp_lastMetaV$EN = + x__h42208 : + x__h58352 ; + assign tlp_lastMetaV_0$EN = WILL_FIRE_RL_tlp_dmaResponseNearMetaHead || WILL_FIRE_RL_tlp_dmaRespHeadFarMeta ; // register tlp_lastMetaV_1 assign tlp_lastMetaV_1$D_IN = WILL_FIRE_RL_tlp_dmaResponseNearMetaBody ? - opcode__h42670 : - opcode__h58837 ; + opcode__h44022 : + opcode__h60417 ; assign tlp_lastMetaV_1$EN = WILL_FIRE_RL_tlp_dmaResponseNearMetaBody || WILL_FIRE_RL_tlp_dmaRespBodyFarMeta ; @@ -4685,8 +4689,8 @@ module mkOCDP16B(pciDevice, // register tlp_lastMetaV_2 assign tlp_lastMetaV_2$D_IN = WILL_FIRE_RL_tlp_dmaResponseNearMetaBody ? - nowMS__h43901 : - nowMS__h60057 ; + nowMS__h45280 : + nowMS__h61665 ; assign tlp_lastMetaV_2$EN = WILL_FIRE_RL_tlp_dmaResponseNearMetaBody || WILL_FIRE_RL_tlp_dmaRespBodyFarMeta ; @@ -4694,8 +4698,8 @@ module mkOCDP16B(pciDevice, // register tlp_lastMetaV_3 assign tlp_lastMetaV_3$D_IN = WILL_FIRE_RL_tlp_dmaResponseNearMetaBody ? - nowLS__h44844 : - nowLS__h60998 ; + nowLS__h46239 : + nowLS__h62622 ; assign tlp_lastMetaV_3$EN = WILL_FIRE_RL_tlp_dmaResponseNearMetaBody || WILL_FIRE_RL_tlp_dmaRespBodyFarMeta ; @@ -4823,7 +4827,7 @@ module mkOCDP16B(pciDevice, // register tlp_outDwRemain always@(WILL_FIRE_RL_tlp_dmaPushResponseHeader or MUX_tlp_outDwRemain$write_1__VAL_1 or - MUX_tlp_tlpXmtBusy$write_1__PSEL_4 or + MUX_tlp_tlpXmtBusy$write_1__PSEL_2 or MUX_tlp_outDwRemain$write_1__VAL_2 or WILL_FIRE_RL_tlp_dataXmt_Header or MUX_tlp_outDwRemain$write_1__VAL_3) @@ -4831,7 +4835,7 @@ module mkOCDP16B(pciDevice, case (1'b1) // synopsys parallel_case WILL_FIRE_RL_tlp_dmaPushResponseHeader: tlp_outDwRemain$D_IN = MUX_tlp_outDwRemain$write_1__VAL_1; - MUX_tlp_tlpXmtBusy$write_1__PSEL_4: + MUX_tlp_tlpXmtBusy$write_1__PSEL_2: tlp_outDwRemain$D_IN = MUX_tlp_outDwRemain$write_1__VAL_2; WILL_FIRE_RL_tlp_dataXmt_Header: tlp_outDwRemain$D_IN = MUX_tlp_outDwRemain$write_1__VAL_3; @@ -4948,7 +4952,7 @@ module mkOCDP16B(pciDevice, // register tlp_sentTail4DWHeader assign tlp_sentTail4DWHeader$D_IN = !tlp_sentTail4DWHeader ; - assign tlp_sentTail4DWHeader$EN = MUX_tlp_tlpXmtBusy$write_1__SEL_2 ; + assign tlp_sentTail4DWHeader$EN = MUX_tlp_tlpXmtBusy$write_1__SEL_3 ; // register tlp_srcMesgAccu assign tlp_srcMesgAccu$D_IN = @@ -4961,22 +4965,22 @@ module mkOCDP16B(pciDevice, // register tlp_tlpBRAM_debugBdata assign tlp_tlpBRAM_debugBdata$D_IN = - { bram_serverAdapterA_3_outData_outData$wget[7:0], - bram_serverAdapterA_3_outData_outData$wget[15:8], - bram_serverAdapterA_3_outData_outData$wget[23:16], - bram_serverAdapterA_3_outData_outData$wget[31:24], - bram_serverAdapterA_2_outData_outData$wget[7:0], - bram_serverAdapterA_2_outData_outData$wget[15:8], - bram_serverAdapterA_2_outData_outData$wget[23:16], - bram_serverAdapterA_2_outData_outData$wget[31:24], - bram_serverAdapterA_1_outData_outData$wget[7:0], - bram_serverAdapterA_1_outData_outData$wget[15:8], - bram_serverAdapterA_1_outData_outData$wget[23:16], - bram_serverAdapterA_1_outData_outData$wget[31:24], - bram_serverAdapterA_outData_outData$wget[7:0], - bram_serverAdapterA_outData_outData$wget[15:8], - bram_serverAdapterA_outData_outData$wget[23:16], - bram_serverAdapterA_outData_outData$wget[31:24] } ; + { bram_3_serverAdapterA_outData_outData$wget[7:0], + bram_3_serverAdapterA_outData_outData$wget[15:8], + bram_3_serverAdapterA_outData_outData$wget[23:16], + bram_3_serverAdapterA_outData_outData$wget[31:24], + bram_2_serverAdapterA_outData_outData$wget[7:0], + bram_2_serverAdapterA_outData_outData$wget[15:8], + bram_2_serverAdapterA_outData_outData$wget[23:16], + bram_2_serverAdapterA_outData_outData$wget[31:24], + bram_1_serverAdapterA_outData_outData$wget[7:0], + bram_1_serverAdapterA_outData_outData$wget[15:8], + bram_1_serverAdapterA_outData_outData$wget[23:16], + bram_1_serverAdapterA_outData_outData$wget[31:24], + bram_0_serverAdapterA_outData_outData$wget[7:0], + bram_0_serverAdapterA_outData_outData$wget[15:8], + bram_0_serverAdapterA_outData_outData$wget[23:16], + bram_0_serverAdapterA_outData_outData$wget[31:24] } ; assign tlp_tlpBRAM_debugBdata$EN = WILL_FIRE_RL_tlp_tlpBRAM_read_NextResp ; // register tlp_tlpBRAM_rdRespDwRemain @@ -4996,7 +5000,7 @@ module mkOCDP16B(pciDevice, (tlp_tlpBRAM_readReq$D_OUT[28:19] != 10'd1 || tlp_tlpBRAM_readReq$D_OUT[60]) || WILL_FIRE_RL_tlp_tlpBRAM_read_NextResp && - tlp_tlpBRAM_rdRespDwRemain_024_ULE_4___d1026 ; + tlp_tlpBRAM_rdRespDwRemain_16_ULE_4___d918 ; // register tlp_tlpBRAM_readNxtDWAddr assign tlp_tlpBRAM_readNxtDWAddr$D_IN = @@ -5024,7 +5028,7 @@ module mkOCDP16B(pciDevice, (tlp_tlpBRAM_mReqF$D_OUT[28:19] != 10'd1 || tlp_tlpBRAM_mReqF$D_OUT[60]) || WILL_FIRE_RL_tlp_tlpBRAM_read_NextReq && - tlp_tlpBRAM_readRemainDWLen_46_ULE_4___d847 ; + tlp_tlpBRAM_readRemainDWLen_74_ULE_4___d775 ; // register tlp_tlpBRAM_writeDWAddr assign tlp_tlpBRAM_writeDWAddr$D_IN = @@ -5055,57 +5059,56 @@ module mkOCDP16B(pciDevice, WILL_FIRE_RL_tlp_dmaXmtMetaBody ; // register tlp_tlpRcvBusy - always@(WILL_FIRE_RL_tlp_tlpRcv or - tlp_inF$D_OUT or + always@(WILL_FIRE_RL_tlp_dmaPullResponseBody or + tlp_dmaPullRemainDWSub_387_ULE_4___d1388 or WILL_FIRE_RL_tlp_dmaPullResponseHeader or - WILL_FIRE_RL_tlp_dmaPullResponseBody or - tlp_dmaPullRemainDWSub_495_ULE_4___d2626) + tlp_inF$D_OUT or WILL_FIRE_RL_tlp_tlpRcv) begin case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_tlp_tlpRcv: tlp_tlpRcvBusy$D_IN = !tlp_inF$D_OUT[151]; + WILL_FIRE_RL_tlp_dmaPullResponseBody: + tlp_tlpRcvBusy$D_IN = !tlp_dmaPullRemainDWSub_387_ULE_4___d1388; WILL_FIRE_RL_tlp_dmaPullResponseHeader: tlp_tlpRcvBusy$D_IN = tlp_inF$D_OUT[105:96] != 10'd1; - WILL_FIRE_RL_tlp_dmaPullResponseBody: - tlp_tlpRcvBusy$D_IN = !tlp_dmaPullRemainDWSub_495_ULE_4___d2626; + WILL_FIRE_RL_tlp_tlpRcv: tlp_tlpRcvBusy$D_IN = !tlp_inF$D_OUT[151]; default: tlp_tlpRcvBusy$D_IN = 1'b0 /* unspecified value */ ; endcase end assign tlp_tlpRcvBusy$EN = - WILL_FIRE_RL_tlp_tlpRcv || + WILL_FIRE_RL_tlp_dmaPullResponseBody || WILL_FIRE_RL_tlp_dmaPullResponseHeader || - WILL_FIRE_RL_tlp_dmaPullResponseBody ; + WILL_FIRE_RL_tlp_tlpRcv ; // register tlp_tlpXmtBusy always@(MUX_tlp_tlpXmtBusy$write_1__SEL_1 or MUX_tlp_tlpXmtBusy$write_1__VAL_1 or - MUX_tlp_tlpXmtBusy$write_1__SEL_2 or + MUX_tlp_tlpXmtBusy$write_1__SEL_3 or tlp_sentTail4DWHeader or - MUX_tlp_tlpXmtBusy$write_1__SEL_4 or + MUX_tlp_tlpXmtBusy$write_1__SEL_2 or WILL_FIRE_RL_tlp_dmaXmtMetaBody or - MUX_tlp_tlpXmtBusy$write_1__SEL_3 or + MUX_tlp_tlpXmtBusy$write_1__SEL_4 or WILL_FIRE_RL_tlp_dmaXmtMetaHead) begin case (1'b1) // synopsys parallel_case MUX_tlp_tlpXmtBusy$write_1__SEL_1: tlp_tlpXmtBusy$D_IN = MUX_tlp_tlpXmtBusy$write_1__VAL_1; - MUX_tlp_tlpXmtBusy$write_1__SEL_2: + MUX_tlp_tlpXmtBusy$write_1__SEL_3: tlp_tlpXmtBusy$D_IN = !tlp_sentTail4DWHeader; - MUX_tlp_tlpXmtBusy$write_1__SEL_4 || WILL_FIRE_RL_tlp_dmaXmtMetaBody: + MUX_tlp_tlpXmtBusy$write_1__SEL_2 || WILL_FIRE_RL_tlp_dmaXmtMetaBody: tlp_tlpXmtBusy$D_IN = 1'd0; - MUX_tlp_tlpXmtBusy$write_1__SEL_3 || WILL_FIRE_RL_tlp_dmaXmtMetaHead: + MUX_tlp_tlpXmtBusy$write_1__SEL_4 || WILL_FIRE_RL_tlp_dmaXmtMetaHead: tlp_tlpXmtBusy$D_IN = 1'd1; default: tlp_tlpXmtBusy$D_IN = 1'b0 /* unspecified value */ ; endcase end assign tlp_tlpXmtBusy$EN = WILL_FIRE_RL_tlp_dmaPushResponseHeader && _dfoo5 || + (WILL_FIRE_RL_tlp_dataXmt_Body || + WILL_FIRE_RL_tlp_dmaPushResponseBody) && + tlp_outDwRemain_129_ULE_4___d1130 || WILL_FIRE_RL_tlp_dmaTailEventSender && tlp_fabFlowAddrMS != 32'd0 || WILL_FIRE_RL_tlp_dataXmt_Header && - !tlp_tlpBRAM_mRespF_first__108_BITS_71_TO_62_20_ETC___d2405 || - (WILL_FIRE_RL_tlp_dataXmt_Body || - WILL_FIRE_RL_tlp_dmaPushResponseBody) && - tlp_outDwRemain_237_ULE_4___d2557 || + !tlp_tlpBRAM_mRespF_first__000_BITS_71_TO_62_10_ETC___d1102 || WILL_FIRE_RL_tlp_dmaXmtMetaBody || WILL_FIRE_RL_tlp_dmaXmtMetaHead ; @@ -5135,7 +5138,7 @@ module mkOCDP16B(pciDevice, tlp_tlpBRAM_mRespF$D_OUT[71:62] == 10'd1 && tlp_tlpBRAM_mRespF$D_OUT[42:35] == 8'h01 || WILL_FIRE_RL_tlp_dmaPushResponseBody && - tlp_outDwRemain_237_ULE_4___d2557 && + tlp_outDwRemain_129_ULE_4___d1130 && tlp_tlpBRAM_mRespF$D_OUT[135:128] == 8'h01 || WILL_FIRE_RL_tlp_dmaResponseNearMetaBody || WILL_FIRE_RL_tlp_dmaXmtMetaHead ; @@ -5199,23 +5202,23 @@ module mkOCDP16B(pciDevice, assign wci_reqF_countReg$EN = (wci_wciReq$wget[71:69] != 3'd0) != wci_reqF_r_deq$whas ; - // register wci_respF_c_r - assign wci_respF_c_r$D_IN = - WILL_FIRE_RL_wci_respF_incCtr ? - MUX_wci_respF_c_r$write_1__VAL_1 : - MUX_wci_respF_c_r$write_1__VAL_2 ; - assign wci_respF_c_r$EN = - WILL_FIRE_RL_wci_respF_incCtr || WILL_FIRE_RL_wci_respF_decCtr ; + // register wci_respF_cntr_r + assign wci_respF_cntr_r$D_IN = + WILL_FIRE_RL_wci_respF_decCtr ? + wci_respF_cntr_r_90_MINUS_1___d499 : + MUX_wci_respF_cntr_r$write_1__VAL_2 ; + assign wci_respF_cntr_r$EN = + WILL_FIRE_RL_wci_respF_decCtr || WILL_FIRE_RL_wci_respF_incCtr ; // register wci_respF_q_0 - always@(WILL_FIRE_RL_wci_respF_both or + always@(MUX_wci_respF_q_0$write_1__SEL_1 or MUX_wci_respF_q_0$write_1__VAL_1 or MUX_wci_respF_q_0$write_1__SEL_2 or MUX_wci_respF_q_0$write_1__VAL_2 or WILL_FIRE_RL_wci_respF_decCtr or wci_respF_q_1) begin case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_wci_respF_both: + MUX_wci_respF_q_0$write_1__SEL_1: wci_respF_q_0$D_IN = MUX_wci_respF_q_0$write_1__VAL_1; MUX_wci_respF_q_0$write_1__SEL_2: wci_respF_q_0$D_IN = MUX_wci_respF_q_0$write_1__VAL_2; @@ -5224,18 +5227,18 @@ module mkOCDP16B(pciDevice, endcase end assign wci_respF_q_0$EN = - WILL_FIRE_RL_wci_respF_both || - WILL_FIRE_RL_wci_respF_incCtr && wci_respF_c_r == 2'd0 || + WILL_FIRE_RL_wci_respF_both && _dfoo3 || + WILL_FIRE_RL_wci_respF_incCtr && wci_respF_cntr_r == 2'd0 || WILL_FIRE_RL_wci_respF_decCtr ; // register wci_respF_q_1 - always@(WILL_FIRE_RL_wci_respF_both or + always@(MUX_wci_respF_q_1$write_1__SEL_1 or MUX_wci_respF_q_1$write_1__VAL_1 or MUX_wci_respF_q_1$write_1__SEL_2 or MUX_wci_respF_q_0$write_1__VAL_2 or WILL_FIRE_RL_wci_respF_decCtr) begin case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_wci_respF_both: + MUX_wci_respF_q_1$write_1__SEL_1: wci_respF_q_1$D_IN = MUX_wci_respF_q_1$write_1__VAL_1; MUX_wci_respF_q_1$write_1__SEL_2: wci_respF_q_1$D_IN = MUX_wci_respF_q_0$write_1__VAL_2; @@ -5244,8 +5247,8 @@ module mkOCDP16B(pciDevice, endcase end assign wci_respF_q_1$EN = - WILL_FIRE_RL_wci_respF_both || - WILL_FIRE_RL_wci_respF_incCtr && wci_respF_c_r == 2'd1 || + WILL_FIRE_RL_wci_respF_both && _dfoo1 || + WILL_FIRE_RL_wci_respF_incCtr && wci_respF_cntr_r == 2'd1 || WILL_FIRE_RL_wci_respF_decCtr ; // register wci_sFlagReg @@ -5465,24 +5468,24 @@ module mkOCDP16B(pciDevice, WILL_FIRE_RL_wmi_getRequest || WILL_FIRE_RL_wmi_wmi_reqF_reset ; - // register wmi_wmi_respF_c_r - assign wmi_wmi_respF_c_r$D_IN = - WILL_FIRE_RL_wmi_wmi_respF_incCtr ? - MUX_wmi_wmi_respF_c_r$write_1__VAL_1 : - MUX_wmi_wmi_respF_c_r$write_1__VAL_2 ; - assign wmi_wmi_respF_c_r$EN = - WILL_FIRE_RL_wmi_wmi_respF_incCtr || - WILL_FIRE_RL_wmi_wmi_respF_decCtr ; + // register wmi_wmi_respF_cntr_r + assign wmi_wmi_respF_cntr_r$D_IN = + WILL_FIRE_RL_wmi_wmi_respF_decCtr ? + wmi_wmi_respF_cntr_r_582_MINUS_1___d1590 : + MUX_wmi_wmi_respF_cntr_r$write_1__VAL_2 ; + assign wmi_wmi_respF_cntr_r$EN = + WILL_FIRE_RL_wmi_wmi_respF_decCtr || + WILL_FIRE_RL_wmi_wmi_respF_incCtr ; // register wmi_wmi_respF_q_0 - always@(WILL_FIRE_RL_wmi_wmi_respF_both or + always@(MUX_wmi_wmi_respF_q_0$write_1__SEL_1 or MUX_wmi_wmi_respF_q_0$write_1__VAL_1 or MUX_wmi_wmi_respF_q_0$write_1__SEL_2 or MUX_wmi_wmi_respF_q_0$write_1__VAL_2 or WILL_FIRE_RL_wmi_wmi_respF_decCtr or wmi_wmi_respF_q_1) begin case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_wmi_wmi_respF_both: + MUX_wmi_wmi_respF_q_0$write_1__SEL_1: wmi_wmi_respF_q_0$D_IN = MUX_wmi_wmi_respF_q_0$write_1__VAL_1; MUX_wmi_wmi_respF_q_0$write_1__SEL_2: wmi_wmi_respF_q_0$D_IN = MUX_wmi_wmi_respF_q_0$write_1__VAL_2; @@ -5493,19 +5496,20 @@ module mkOCDP16B(pciDevice, endcase end assign wmi_wmi_respF_q_0$EN = - WILL_FIRE_RL_wmi_wmi_respF_both || - WILL_FIRE_RL_wmi_wmi_respF_incCtr && wmi_wmi_respF_c_r == 2'd0 || + WILL_FIRE_RL_wmi_wmi_respF_both && _dfoo9 || + WILL_FIRE_RL_wmi_wmi_respF_incCtr && + wmi_wmi_respF_cntr_r == 2'd0 || WILL_FIRE_RL_wmi_wmi_respF_decCtr ; // register wmi_wmi_respF_q_1 - always@(WILL_FIRE_RL_wmi_wmi_respF_both or + always@(MUX_wmi_wmi_respF_q_1$write_1__SEL_1 or MUX_wmi_wmi_respF_q_1$write_1__VAL_1 or MUX_wmi_wmi_respF_q_1$write_1__SEL_2 or MUX_wmi_wmi_respF_q_0$write_1__VAL_2 or WILL_FIRE_RL_wmi_wmi_respF_decCtr) begin case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_wmi_wmi_respF_both: + MUX_wmi_wmi_respF_q_1$write_1__SEL_1: wmi_wmi_respF_q_1$D_IN = MUX_wmi_wmi_respF_q_1$write_1__VAL_1; MUX_wmi_wmi_respF_q_1$write_1__SEL_2: wmi_wmi_respF_q_1$D_IN = MUX_wmi_wmi_respF_q_0$write_1__VAL_2; @@ -5515,14 +5519,15 @@ module mkOCDP16B(pciDevice, endcase end assign wmi_wmi_respF_q_1$EN = - WILL_FIRE_RL_wmi_wmi_respF_both || - WILL_FIRE_RL_wmi_wmi_respF_incCtr && wmi_wmi_respF_c_r == 2'd1 || + WILL_FIRE_RL_wmi_wmi_respF_both && _dfoo7 || + WILL_FIRE_RL_wmi_wmi_respF_incCtr && + wmi_wmi_respF_cntr_r == 2'd1 || WILL_FIRE_RL_wmi_wmi_respF_decCtr ; // register wmi_wmi_sFlagReg assign wmi_wmi_sFlagReg$D_IN = - { bram_serverAdapterB_1_outData_outData$wget[7:0], - bram_serverAdapterB_outData_outData$wget[23:0] } ; + { bram_1_serverAdapterB_outData_outData$wget[7:0], + bram_0_serverAdapterB_outData_outData$wget[23:0] } ; assign wmi_wmi_sFlagReg$EN = WILL_FIRE_RL_wmi_respMetadata ; // register wmi_wmi_statusR @@ -5564,237 +5569,295 @@ module mkOCDP16B(pciDevice, assign wti_operateD$D_IN = 1'b1 ; assign wti_operateD$EN = 1'd1 ; - // submodule bram_memory - always@(MUX_bram_memory$a_put_1__SEL_1 or + // submodule bram_0_memory + always@(MUX_bram_0_memory$a_put_1__SEL_1 or + MUX_bram_0_memory$a_put_2__VAL_1 or + MUX_bram_0_memory$a_put_1__SEL_2 or tlp_tlpBRAM_mReqF$D_OUT or - MUX_bram_memory$a_put_1__SEL_2 or - MUX_bram_memory$a_put_1__SEL_3 or - MUX_bram_memory$a_put_2__VAL_3 or + MUX_bram_0_memory$a_put_1__SEL_3 or WILL_FIRE_RL_tlp_tlpBRAM_read_NextReq or - MUX_bram_memory$a_put_2__VAL_4) + MUX_bram_0_memory$a_put_2__VAL_4) begin case (1'b1) // synopsys parallel_case - MUX_bram_memory$a_put_1__SEL_1: - bram_memory$ADDRA = tlp_tlpBRAM_mReqF$D_OUT[62:52]; - MUX_bram_memory$a_put_1__SEL_2: - bram_memory$ADDRA = tlp_tlpBRAM_mReqF$D_OUT[41:31]; - MUX_bram_memory$a_put_1__SEL_3: - bram_memory$ADDRA = MUX_bram_memory$a_put_2__VAL_3; + MUX_bram_0_memory$a_put_1__SEL_1: + bram_0_memory$ADDRA = MUX_bram_0_memory$a_put_2__VAL_1; + MUX_bram_0_memory$a_put_1__SEL_2: + bram_0_memory$ADDRA = tlp_tlpBRAM_mReqF$D_OUT[62:52]; + MUX_bram_0_memory$a_put_1__SEL_3: + bram_0_memory$ADDRA = tlp_tlpBRAM_mReqF$D_OUT[41:31]; WILL_FIRE_RL_tlp_tlpBRAM_read_NextReq: - bram_memory$ADDRA = MUX_bram_memory$a_put_2__VAL_4; - default: bram_memory$ADDRA = 11'b01010101010 /* unspecified value */ ; + bram_0_memory$ADDRA = MUX_bram_0_memory$a_put_2__VAL_4; + default: bram_0_memory$ADDRA = 11'b01010101010 /* unspecified value */ ; endcase end always@(WILL_FIRE_RL_wmi_reqMetadata or WILL_FIRE_RL_wmi_doWriteFinalize or wmi_lclMetaAddr or WILL_FIRE_RL_wmi_doReadReq or - MUX_bram_memory$b_put_2__VAL_2 or WILL_FIRE_RL_wmi_doWriteReq) + MUX_bram_0_memory$b_put_2__VAL_2 or WILL_FIRE_RL_wmi_doWriteReq) begin case (1'b1) // synopsys parallel_case WILL_FIRE_RL_wmi_reqMetadata || WILL_FIRE_RL_wmi_doWriteFinalize: - bram_memory$ADDRB = wmi_lclMetaAddr[14:4]; + bram_0_memory$ADDRB = wmi_lclMetaAddr[14:4]; WILL_FIRE_RL_wmi_doReadReq: - bram_memory$ADDRB = MUX_bram_memory$b_put_2__VAL_2; + bram_0_memory$ADDRB = MUX_bram_0_memory$b_put_2__VAL_2; WILL_FIRE_RL_wmi_doWriteReq: - bram_memory$ADDRB = MUX_bram_memory$b_put_2__VAL_2; - default: bram_memory$ADDRB = 11'b01010101010 /* unspecified value */ ; + bram_0_memory$ADDRB = MUX_bram_0_memory$b_put_2__VAL_2; + default: bram_0_memory$ADDRB = 11'b01010101010 /* unspecified value */ ; endcase end - always@(MUX_bram_memory$a_put_1__SEL_1 or - MUX_bram_memory$a_put_3__VAL_1 or - MUX_bram_memory$a_put_1__SEL_3 or - MUX_bram_memory$a_put_3__VAL_3 or - MUX_bram_memory$a_put_1__SEL_2 or + always@(MUX_bram_0_memory$a_put_1__SEL_1 or + MUX_bram_0_memory$a_put_3__VAL_1 or + MUX_bram_0_memory$a_put_1__SEL_2 or + MUX_bram_0_memory$a_put_3__VAL_2 or + MUX_bram_0_memory$a_put_1__SEL_3 or WILL_FIRE_RL_tlp_tlpBRAM_read_NextReq) begin case (1'b1) // synopsys parallel_case - MUX_bram_memory$a_put_1__SEL_1: - bram_memory$DIA = MUX_bram_memory$a_put_3__VAL_1; - MUX_bram_memory$a_put_1__SEL_3: - bram_memory$DIA = MUX_bram_memory$a_put_3__VAL_3; - MUX_bram_memory$a_put_1__SEL_2 || WILL_FIRE_RL_tlp_tlpBRAM_read_NextReq: - bram_memory$DIA = 32'd0; - default: bram_memory$DIA = 32'hAAAAAAAA /* unspecified value */ ; + MUX_bram_0_memory$a_put_1__SEL_1: + bram_0_memory$DIA = MUX_bram_0_memory$a_put_3__VAL_1; + MUX_bram_0_memory$a_put_1__SEL_2: + bram_0_memory$DIA = MUX_bram_0_memory$a_put_3__VAL_2; + MUX_bram_0_memory$a_put_1__SEL_3 || + WILL_FIRE_RL_tlp_tlpBRAM_read_NextReq: + bram_0_memory$DIA = 32'd0; + default: bram_0_memory$DIA = 32'hAAAAAAAA /* unspecified value */ ; endcase end always@(WILL_FIRE_RL_wmi_doWriteReq or wmi_wmi_dhF$D_OUT or WILL_FIRE_RL_wmi_doWriteFinalize or - x3__h80237 or + x3__h81813 or WILL_FIRE_RL_wmi_reqMetadata or WILL_FIRE_RL_wmi_doReadReq) begin case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_wmi_doWriteReq: bram_memory$DIB = wmi_wmi_dhF$D_OUT[47:16]; - WILL_FIRE_RL_wmi_doWriteFinalize: bram_memory$DIB = x3__h80237; + WILL_FIRE_RL_wmi_doWriteReq: + bram_0_memory$DIB = wmi_wmi_dhF$D_OUT[47:16]; + WILL_FIRE_RL_wmi_doWriteFinalize: bram_0_memory$DIB = x3__h81813; WILL_FIRE_RL_wmi_reqMetadata || WILL_FIRE_RL_wmi_doReadReq: - bram_memory$DIB = 32'd0; - default: bram_memory$DIB = 32'hAAAAAAAA /* unspecified value */ ; + bram_0_memory$DIB = 32'd0; + default: bram_0_memory$DIB = 32'hAAAAAAAA /* unspecified value */ ; endcase end - assign bram_memory$WEA = - !MUX_bram_memory$a_put_1__SEL_2 && + assign bram_0_memory$WEA = + !MUX_bram_0_memory$a_put_1__SEL_3 && !WILL_FIRE_RL_tlp_tlpBRAM_read_NextReq ; - assign bram_memory$WEB = + assign bram_0_memory$WEB = !WILL_FIRE_RL_wmi_reqMetadata && !WILL_FIRE_RL_wmi_doReadReq ; - assign bram_memory$ENA = + assign bram_0_memory$ENA = + WILL_FIRE_RL_tlp_tlpBRAM_writeData && + SEL_ARR_NOT_tlp_tlpBRAM_writeRemainDWLen_52_EQ_ETC___d665 || WILL_FIRE_RL_tlp_tlpBRAM_writeReq && - !tlp_tlpBRAM_mReqF$D_OUT[63] && - tlp_tlpBRAM_mReqF$D_OUT[51:50] == 2'd0 || + tlp_tlpBRAM_mReqF$D_OUT[51:50] == 2'd0 && + !tlp_tlpBRAM_mReqF$D_OUT[63] || WILL_FIRE_RL_tlp_tlpBRAM_read_FirstReq && - !tlp_tlpBRAM_mReqF$D_OUT[60] && - tlp_tlpBRAM_mReqF$D_OUT[30:29] == 2'd0 || - WILL_FIRE_RL_tlp_tlpBRAM_writeData && - IF_0_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2431 || + tlp_tlpBRAM_mReqF$D_OUT[30:29] == 2'd0 && + !tlp_tlpBRAM_mReqF$D_OUT[60] || WILL_FIRE_RL_tlp_tlpBRAM_read_NextReq ; - assign bram_memory$ENB = + assign bram_0_memory$ENB = WILL_FIRE_RL_wmi_reqMetadata || WILL_FIRE_RL_wmi_doReadReq || WILL_FIRE_RL_wmi_doWriteFinalize || WILL_FIRE_RL_wmi_doWriteReq ; - // submodule bram_memory_1 - always@(MUX_bram_memory_1$a_put_1__SEL_1 or + // submodule bram_0_serverAdapterA_outDataCore + assign bram_0_serverAdapterA_outDataCore$D_IN = bram_0_memory$DOA ; + assign bram_0_serverAdapterA_outDataCore$ENQ = + WILL_FIRE_RL_bram_0_serverAdapterA_outData_enqAndDeq || + bram_0_serverAdapterA_outDataCore$FULL_N && + !bram_0_serverAdapterA_outData_deqCalled$whas && + bram_0_serverAdapterA_outData_enqData$whas ; + assign bram_0_serverAdapterA_outDataCore$DEQ = + WILL_FIRE_RL_bram_0_serverAdapterA_outData_enqAndDeq || + bram_0_serverAdapterA_outDataCore$EMPTY_N && + bram_0_serverAdapterA_outData_deqCalled$whas && + !bram_0_serverAdapterA_outData_enqData$whas ; + assign bram_0_serverAdapterA_outDataCore$CLR = 1'b0 ; + + // submodule bram_0_serverAdapterB_outDataCore + assign bram_0_serverAdapterB_outDataCore$D_IN = bram_0_memory$DOB ; + assign bram_0_serverAdapterB_outDataCore$ENQ = + WILL_FIRE_RL_bram_0_serverAdapterB_outData_enqAndDeq || + bram_0_serverAdapterB_outDataCore$FULL_N && + !bram_0_serverAdapterB_outData_deqCalled$whas && + bram_0_serverAdapterB_outData_enqData$whas ; + assign bram_0_serverAdapterB_outDataCore$DEQ = + WILL_FIRE_RL_bram_0_serverAdapterB_outData_enqAndDeq || + bram_0_serverAdapterB_outDataCore$EMPTY_N && + bram_0_serverAdapterB_outData_deqCalled$whas && + !bram_0_serverAdapterB_outData_enqData$whas ; + assign bram_0_serverAdapterB_outDataCore$CLR = 1'b0 ; + + // submodule bram_1_memory + always@(MUX_bram_1_memory$a_put_1__SEL_1 or + MUX_bram_1_memory$a_put_2__VAL_1 or + MUX_bram_1_memory$a_put_1__SEL_2 or tlp_tlpBRAM_mReqF$D_OUT or - MUX_bram_memory_1$a_put_1__SEL_2 or - MUX_bram_memory_1$a_put_1__SEL_3 or - MUX_bram_memory_1$a_put_2__VAL_3 or + MUX_bram_1_memory$a_put_1__SEL_3 or WILL_FIRE_RL_tlp_tlpBRAM_read_NextReq or - MUX_bram_memory_1$a_put_2__VAL_4) + MUX_bram_1_memory$a_put_2__VAL_4) begin case (1'b1) // synopsys parallel_case - MUX_bram_memory_1$a_put_1__SEL_1: - bram_memory_1$ADDRA = tlp_tlpBRAM_mReqF$D_OUT[62:52]; - MUX_bram_memory_1$a_put_1__SEL_2: - bram_memory_1$ADDRA = tlp_tlpBRAM_mReqF$D_OUT[41:31]; - MUX_bram_memory_1$a_put_1__SEL_3: - bram_memory_1$ADDRA = MUX_bram_memory_1$a_put_2__VAL_3; + MUX_bram_1_memory$a_put_1__SEL_1: + bram_1_memory$ADDRA = MUX_bram_1_memory$a_put_2__VAL_1; + MUX_bram_1_memory$a_put_1__SEL_2: + bram_1_memory$ADDRA = tlp_tlpBRAM_mReqF$D_OUT[62:52]; + MUX_bram_1_memory$a_put_1__SEL_3: + bram_1_memory$ADDRA = tlp_tlpBRAM_mReqF$D_OUT[41:31]; WILL_FIRE_RL_tlp_tlpBRAM_read_NextReq: - bram_memory_1$ADDRA = MUX_bram_memory_1$a_put_2__VAL_4; - default: bram_memory_1$ADDRA = 11'b01010101010 /* unspecified value */ ; + bram_1_memory$ADDRA = MUX_bram_1_memory$a_put_2__VAL_4; + default: bram_1_memory$ADDRA = 11'b01010101010 /* unspecified value */ ; endcase end always@(WILL_FIRE_RL_wmi_reqMetadata or WILL_FIRE_RL_wmi_doWriteFinalize or wmi_lclMetaAddr or WILL_FIRE_RL_wmi_doReadReq or - MUX_bram_memory$b_put_2__VAL_2 or WILL_FIRE_RL_wmi_doWriteReq) + MUX_bram_0_memory$b_put_2__VAL_2 or WILL_FIRE_RL_wmi_doWriteReq) begin case (1'b1) // synopsys parallel_case WILL_FIRE_RL_wmi_reqMetadata || WILL_FIRE_RL_wmi_doWriteFinalize: - bram_memory_1$ADDRB = wmi_lclMetaAddr[14:4]; + bram_1_memory$ADDRB = wmi_lclMetaAddr[14:4]; WILL_FIRE_RL_wmi_doReadReq: - bram_memory_1$ADDRB = MUX_bram_memory$b_put_2__VAL_2; + bram_1_memory$ADDRB = MUX_bram_0_memory$b_put_2__VAL_2; WILL_FIRE_RL_wmi_doWriteReq: - bram_memory_1$ADDRB = MUX_bram_memory$b_put_2__VAL_2; - default: bram_memory_1$ADDRB = 11'b01010101010 /* unspecified value */ ; + bram_1_memory$ADDRB = MUX_bram_0_memory$b_put_2__VAL_2; + default: bram_1_memory$ADDRB = 11'b01010101010 /* unspecified value */ ; endcase end - always@(MUX_bram_memory_1$a_put_1__SEL_1 or - MUX_bram_memory$a_put_3__VAL_1 or - MUX_bram_memory_1$a_put_1__SEL_3 or - MUX_bram_memory_1$a_put_3__VAL_3 or - MUX_bram_memory_1$a_put_1__SEL_2 or + always@(MUX_bram_1_memory$a_put_1__SEL_1 or + MUX_bram_1_memory$a_put_3__VAL_1 or + MUX_bram_1_memory$a_put_1__SEL_2 or + MUX_bram_0_memory$a_put_3__VAL_2 or + MUX_bram_1_memory$a_put_1__SEL_3 or WILL_FIRE_RL_tlp_tlpBRAM_read_NextReq) begin case (1'b1) // synopsys parallel_case - MUX_bram_memory_1$a_put_1__SEL_1: - bram_memory_1$DIA = MUX_bram_memory$a_put_3__VAL_1; - MUX_bram_memory_1$a_put_1__SEL_3: - bram_memory_1$DIA = MUX_bram_memory_1$a_put_3__VAL_3; - MUX_bram_memory_1$a_put_1__SEL_2 || + MUX_bram_1_memory$a_put_1__SEL_1: + bram_1_memory$DIA = MUX_bram_1_memory$a_put_3__VAL_1; + MUX_bram_1_memory$a_put_1__SEL_2: + bram_1_memory$DIA = MUX_bram_0_memory$a_put_3__VAL_2; + MUX_bram_1_memory$a_put_1__SEL_3 || WILL_FIRE_RL_tlp_tlpBRAM_read_NextReq: - bram_memory_1$DIA = 32'd0; - default: bram_memory_1$DIA = 32'hAAAAAAAA /* unspecified value */ ; + bram_1_memory$DIA = 32'd0; + default: bram_1_memory$DIA = 32'hAAAAAAAA /* unspecified value */ ; endcase end always@(WILL_FIRE_RL_wmi_doWriteReq or wmi_wmi_dhF$D_OUT or WILL_FIRE_RL_wmi_doWriteFinalize or - mesgMeta_opcode__h80277 or + mesgMeta_opcode__h81853 or WILL_FIRE_RL_wmi_reqMetadata or WILL_FIRE_RL_wmi_doReadReq) begin case (1'b1) // synopsys parallel_case WILL_FIRE_RL_wmi_doWriteReq: - bram_memory_1$DIB = wmi_wmi_dhF$D_OUT[79:48]; + bram_1_memory$DIB = wmi_wmi_dhF$D_OUT[79:48]; WILL_FIRE_RL_wmi_doWriteFinalize: - bram_memory_1$DIB = mesgMeta_opcode__h80277; + bram_1_memory$DIB = mesgMeta_opcode__h81853; WILL_FIRE_RL_wmi_reqMetadata || WILL_FIRE_RL_wmi_doReadReq: - bram_memory_1$DIB = 32'd0; - default: bram_memory_1$DIB = 32'hAAAAAAAA /* unspecified value */ ; + bram_1_memory$DIB = 32'd0; + default: bram_1_memory$DIB = 32'hAAAAAAAA /* unspecified value */ ; endcase end - assign bram_memory_1$WEA = - !MUX_bram_memory_1$a_put_1__SEL_2 && + assign bram_1_memory$WEA = + !MUX_bram_1_memory$a_put_1__SEL_3 && !WILL_FIRE_RL_tlp_tlpBRAM_read_NextReq ; - assign bram_memory_1$WEB = bram_memory$WEB ; - assign bram_memory_1$ENA = + assign bram_1_memory$WEB = bram_0_memory$WEB ; + assign bram_1_memory$ENA = + WILL_FIRE_RL_tlp_tlpBRAM_writeData && + SEL_ARR_NOT_tlp_tlpBRAM_writeRemainDWLen_52_EQ_ETC___d669 || WILL_FIRE_RL_tlp_tlpBRAM_writeReq && - !tlp_tlpBRAM_mReqF$D_OUT[63] && - tlp_tlpBRAM_mReqF$D_OUT[51:50] == 2'd1 || + tlp_tlpBRAM_mReqF$D_OUT[51:50] == 2'd1 && + !tlp_tlpBRAM_mReqF$D_OUT[63] || WILL_FIRE_RL_tlp_tlpBRAM_read_FirstReq && - !tlp_tlpBRAM_mReqF$D_OUT[60] && - tlp_tlpBRAM_mReqF$D_OUT[30:29] == 2'd1 || - WILL_FIRE_RL_tlp_tlpBRAM_writeData && - IF_1_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2432 || + tlp_tlpBRAM_mReqF$D_OUT[30:29] == 2'd1 && + !tlp_tlpBRAM_mReqF$D_OUT[60] || WILL_FIRE_RL_tlp_tlpBRAM_read_NextReq ; - assign bram_memory_1$ENB = + assign bram_1_memory$ENB = WILL_FIRE_RL_wmi_reqMetadata || WILL_FIRE_RL_wmi_doReadReq || WILL_FIRE_RL_wmi_doWriteFinalize || WILL_FIRE_RL_wmi_doWriteReq ; - // submodule bram_memory_2 - always@(MUX_bram_memory_2$a_put_1__SEL_1 or + // submodule bram_1_serverAdapterA_outDataCore + assign bram_1_serverAdapterA_outDataCore$D_IN = bram_1_memory$DOA ; + assign bram_1_serverAdapterA_outDataCore$ENQ = + WILL_FIRE_RL_bram_1_serverAdapterA_outData_enqAndDeq || + bram_1_serverAdapterA_outDataCore$FULL_N && + !bram_1_serverAdapterA_outData_deqCalled$whas && + bram_1_serverAdapterA_outData_enqData$whas ; + assign bram_1_serverAdapterA_outDataCore$DEQ = + WILL_FIRE_RL_bram_1_serverAdapterA_outData_enqAndDeq || + bram_1_serverAdapterA_outDataCore$EMPTY_N && + bram_1_serverAdapterA_outData_deqCalled$whas && + !bram_1_serverAdapterA_outData_enqData$whas ; + assign bram_1_serverAdapterA_outDataCore$CLR = 1'b0 ; + + // submodule bram_1_serverAdapterB_outDataCore + assign bram_1_serverAdapterB_outDataCore$D_IN = bram_1_memory$DOB ; + assign bram_1_serverAdapterB_outDataCore$ENQ = + WILL_FIRE_RL_bram_1_serverAdapterB_outData_enqAndDeq || + bram_1_serverAdapterB_outDataCore$FULL_N && + !bram_0_serverAdapterB_outData_deqCalled$whas && + bram_1_serverAdapterB_outData_enqData$whas ; + assign bram_1_serverAdapterB_outDataCore$DEQ = + WILL_FIRE_RL_bram_1_serverAdapterB_outData_enqAndDeq || + bram_1_serverAdapterB_outDataCore$EMPTY_N && + bram_0_serverAdapterB_outData_deqCalled$whas && + !bram_1_serverAdapterB_outData_enqData$whas ; + assign bram_1_serverAdapterB_outDataCore$CLR = 1'b0 ; + + // submodule bram_2_memory + always@(MUX_bram_2_memory$a_put_1__SEL_1 or + MUX_bram_2_memory$a_put_2__VAL_1 or + MUX_bram_2_memory$a_put_1__SEL_2 or tlp_tlpBRAM_mReqF$D_OUT or - MUX_bram_memory_2$a_put_1__SEL_2 or - MUX_bram_memory_2$a_put_1__SEL_3 or - MUX_bram_memory_2$a_put_2__VAL_3 or + MUX_bram_2_memory$a_put_1__SEL_3 or WILL_FIRE_RL_tlp_tlpBRAM_read_NextReq or - MUX_bram_memory_2$a_put_2__VAL_4) + MUX_bram_2_memory$a_put_2__VAL_4) begin case (1'b1) // synopsys parallel_case - MUX_bram_memory_2$a_put_1__SEL_1: - bram_memory_2$ADDRA = tlp_tlpBRAM_mReqF$D_OUT[62:52]; - MUX_bram_memory_2$a_put_1__SEL_2: - bram_memory_2$ADDRA = tlp_tlpBRAM_mReqF$D_OUT[41:31]; - MUX_bram_memory_2$a_put_1__SEL_3: - bram_memory_2$ADDRA = MUX_bram_memory_2$a_put_2__VAL_3; + MUX_bram_2_memory$a_put_1__SEL_1: + bram_2_memory$ADDRA = MUX_bram_2_memory$a_put_2__VAL_1; + MUX_bram_2_memory$a_put_1__SEL_2: + bram_2_memory$ADDRA = tlp_tlpBRAM_mReqF$D_OUT[62:52]; + MUX_bram_2_memory$a_put_1__SEL_3: + bram_2_memory$ADDRA = tlp_tlpBRAM_mReqF$D_OUT[41:31]; WILL_FIRE_RL_tlp_tlpBRAM_read_NextReq: - bram_memory_2$ADDRA = MUX_bram_memory_2$a_put_2__VAL_4; - default: bram_memory_2$ADDRA = 11'b01010101010 /* unspecified value */ ; + bram_2_memory$ADDRA = MUX_bram_2_memory$a_put_2__VAL_4; + default: bram_2_memory$ADDRA = 11'b01010101010 /* unspecified value */ ; endcase end always@(WILL_FIRE_RL_wmi_reqMetadata or WILL_FIRE_RL_wmi_doWriteFinalize or wmi_lclMetaAddr or WILL_FIRE_RL_wmi_doReadReq or - MUX_bram_memory$b_put_2__VAL_2 or WILL_FIRE_RL_wmi_doWriteReq) + MUX_bram_0_memory$b_put_2__VAL_2 or WILL_FIRE_RL_wmi_doWriteReq) begin case (1'b1) // synopsys parallel_case WILL_FIRE_RL_wmi_reqMetadata || WILL_FIRE_RL_wmi_doWriteFinalize: - bram_memory_2$ADDRB = wmi_lclMetaAddr[14:4]; + bram_2_memory$ADDRB = wmi_lclMetaAddr[14:4]; WILL_FIRE_RL_wmi_doReadReq: - bram_memory_2$ADDRB = MUX_bram_memory$b_put_2__VAL_2; + bram_2_memory$ADDRB = MUX_bram_0_memory$b_put_2__VAL_2; WILL_FIRE_RL_wmi_doWriteReq: - bram_memory_2$ADDRB = MUX_bram_memory$b_put_2__VAL_2; - default: bram_memory_2$ADDRB = 11'b01010101010 /* unspecified value */ ; + bram_2_memory$ADDRB = MUX_bram_0_memory$b_put_2__VAL_2; + default: bram_2_memory$ADDRB = 11'b01010101010 /* unspecified value */ ; endcase end - always@(MUX_bram_memory_2$a_put_1__SEL_1 or - MUX_bram_memory$a_put_3__VAL_1 or - MUX_bram_memory_2$a_put_1__SEL_3 or - MUX_bram_memory_2$a_put_3__VAL_3 or - MUX_bram_memory_2$a_put_1__SEL_2 or + always@(MUX_bram_2_memory$a_put_1__SEL_1 or + MUX_bram_2_memory$a_put_3__VAL_1 or + MUX_bram_2_memory$a_put_1__SEL_2 or + MUX_bram_0_memory$a_put_3__VAL_2 or + MUX_bram_2_memory$a_put_1__SEL_3 or WILL_FIRE_RL_tlp_tlpBRAM_read_NextReq) begin case (1'b1) // synopsys parallel_case - MUX_bram_memory_2$a_put_1__SEL_1: - bram_memory_2$DIA = MUX_bram_memory$a_put_3__VAL_1; - MUX_bram_memory_2$a_put_1__SEL_3: - bram_memory_2$DIA = MUX_bram_memory_2$a_put_3__VAL_3; - MUX_bram_memory_2$a_put_1__SEL_2 || + MUX_bram_2_memory$a_put_1__SEL_1: + bram_2_memory$DIA = MUX_bram_2_memory$a_put_3__VAL_1; + MUX_bram_2_memory$a_put_1__SEL_2: + bram_2_memory$DIA = MUX_bram_0_memory$a_put_3__VAL_2; + MUX_bram_2_memory$a_put_1__SEL_3 || WILL_FIRE_RL_tlp_tlpBRAM_read_NextReq: - bram_memory_2$DIA = 32'd0; - default: bram_memory_2$DIA = 32'hAAAAAAAA /* unspecified value */ ; + bram_2_memory$DIA = 32'd0; + default: bram_2_memory$DIA = 32'hAAAAAAAA /* unspecified value */ ; endcase end always@(WILL_FIRE_RL_wmi_doWriteFinalize or @@ -5805,86 +5868,114 @@ module mkOCDP16B(pciDevice, begin case (1'b1) // synopsys parallel_case WILL_FIRE_RL_wmi_doWriteFinalize: - bram_memory_2$DIB = wmi_nowW$wget[63:32]; + bram_2_memory$DIB = wmi_nowW$wget[63:32]; WILL_FIRE_RL_wmi_doWriteReq: - bram_memory_2$DIB = wmi_wmi_dhF$D_OUT[111:80]; + bram_2_memory$DIB = wmi_wmi_dhF$D_OUT[111:80]; WILL_FIRE_RL_wmi_reqMetadata || WILL_FIRE_RL_wmi_doReadReq: - bram_memory_2$DIB = 32'd0; - default: bram_memory_2$DIB = 32'hAAAAAAAA /* unspecified value */ ; + bram_2_memory$DIB = 32'd0; + default: bram_2_memory$DIB = 32'hAAAAAAAA /* unspecified value */ ; endcase end - assign bram_memory_2$WEA = - !MUX_bram_memory_2$a_put_1__SEL_2 && + assign bram_2_memory$WEA = + !MUX_bram_2_memory$a_put_1__SEL_3 && !WILL_FIRE_RL_tlp_tlpBRAM_read_NextReq ; - assign bram_memory_2$WEB = bram_memory$WEB ; - assign bram_memory_2$ENA = + assign bram_2_memory$WEB = bram_0_memory$WEB ; + assign bram_2_memory$ENA = + WILL_FIRE_RL_tlp_tlpBRAM_writeData && + SEL_ARR_NOT_tlp_tlpBRAM_writeRemainDWLen_52_EQ_ETC___d673 || WILL_FIRE_RL_tlp_tlpBRAM_writeReq && - !tlp_tlpBRAM_mReqF$D_OUT[63] && - tlp_tlpBRAM_mReqF$D_OUT[51:50] == 2'd2 || + tlp_tlpBRAM_mReqF$D_OUT[51:50] == 2'd2 && + !tlp_tlpBRAM_mReqF$D_OUT[63] || WILL_FIRE_RL_tlp_tlpBRAM_read_FirstReq && - !tlp_tlpBRAM_mReqF$D_OUT[60] && - tlp_tlpBRAM_mReqF$D_OUT[30:29] == 2'd2 || - WILL_FIRE_RL_tlp_tlpBRAM_writeData && - IF_2_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2433 || + tlp_tlpBRAM_mReqF$D_OUT[30:29] == 2'd2 && + !tlp_tlpBRAM_mReqF$D_OUT[60] || WILL_FIRE_RL_tlp_tlpBRAM_read_NextReq ; - assign bram_memory_2$ENB = + assign bram_2_memory$ENB = WILL_FIRE_RL_wmi_reqMetadata || WILL_FIRE_RL_wmi_doReadReq || WILL_FIRE_RL_wmi_doWriteFinalize || WILL_FIRE_RL_wmi_doWriteReq ; - // submodule bram_memory_3 - always@(MUX_bram_memory_3$a_put_1__SEL_1 or + // submodule bram_2_serverAdapterA_outDataCore + assign bram_2_serverAdapterA_outDataCore$D_IN = bram_2_memory$DOA ; + assign bram_2_serverAdapterA_outDataCore$ENQ = + WILL_FIRE_RL_bram_2_serverAdapterA_outData_enqAndDeq || + bram_2_serverAdapterA_outDataCore$FULL_N && + !bram_2_serverAdapterA_outData_deqCalled$whas && + bram_2_serverAdapterA_outData_enqData$whas ; + assign bram_2_serverAdapterA_outDataCore$DEQ = + WILL_FIRE_RL_bram_2_serverAdapterA_outData_enqAndDeq || + bram_2_serverAdapterA_outDataCore$EMPTY_N && + bram_2_serverAdapterA_outData_deqCalled$whas && + !bram_2_serverAdapterA_outData_enqData$whas ; + assign bram_2_serverAdapterA_outDataCore$CLR = 1'b0 ; + + // submodule bram_2_serverAdapterB_outDataCore + assign bram_2_serverAdapterB_outDataCore$D_IN = bram_2_memory$DOB ; + assign bram_2_serverAdapterB_outDataCore$ENQ = + WILL_FIRE_RL_bram_2_serverAdapterB_outData_enqAndDeq || + bram_2_serverAdapterB_outDataCore$FULL_N && + !bram_0_serverAdapterB_outData_deqCalled$whas && + bram_2_serverAdapterB_outData_enqData$whas ; + assign bram_2_serverAdapterB_outDataCore$DEQ = + WILL_FIRE_RL_bram_2_serverAdapterB_outData_enqAndDeq || + bram_2_serverAdapterB_outDataCore$EMPTY_N && + bram_0_serverAdapterB_outData_deqCalled$whas && + !bram_2_serverAdapterB_outData_enqData$whas ; + assign bram_2_serverAdapterB_outDataCore$CLR = 1'b0 ; + + // submodule bram_3_memory + always@(MUX_bram_3_memory$a_put_1__SEL_1 or + MUX_bram_3_memory$a_put_2__VAL_1 or + MUX_bram_3_memory$a_put_1__SEL_2 or tlp_tlpBRAM_mReqF$D_OUT or - MUX_bram_memory_3$a_put_1__SEL_2 or - MUX_bram_memory_3$a_put_1__SEL_3 or - MUX_bram_memory_3$a_put_2__VAL_3 or + MUX_bram_3_memory$a_put_1__SEL_3 or WILL_FIRE_RL_tlp_tlpBRAM_read_NextReq or - MUX_bram_memory_3$a_put_2__VAL_4) + MUX_bram_3_memory$a_put_2__VAL_4) begin case (1'b1) // synopsys parallel_case - MUX_bram_memory_3$a_put_1__SEL_1: - bram_memory_3$ADDRA = tlp_tlpBRAM_mReqF$D_OUT[62:52]; - MUX_bram_memory_3$a_put_1__SEL_2: - bram_memory_3$ADDRA = tlp_tlpBRAM_mReqF$D_OUT[41:31]; - MUX_bram_memory_3$a_put_1__SEL_3: - bram_memory_3$ADDRA = MUX_bram_memory_3$a_put_2__VAL_3; + MUX_bram_3_memory$a_put_1__SEL_1: + bram_3_memory$ADDRA = MUX_bram_3_memory$a_put_2__VAL_1; + MUX_bram_3_memory$a_put_1__SEL_2: + bram_3_memory$ADDRA = tlp_tlpBRAM_mReqF$D_OUT[62:52]; + MUX_bram_3_memory$a_put_1__SEL_3: + bram_3_memory$ADDRA = tlp_tlpBRAM_mReqF$D_OUT[41:31]; WILL_FIRE_RL_tlp_tlpBRAM_read_NextReq: - bram_memory_3$ADDRA = MUX_bram_memory_3$a_put_2__VAL_4; - default: bram_memory_3$ADDRA = 11'b01010101010 /* unspecified value */ ; + bram_3_memory$ADDRA = MUX_bram_3_memory$a_put_2__VAL_4; + default: bram_3_memory$ADDRA = 11'b01010101010 /* unspecified value */ ; endcase end always@(WILL_FIRE_RL_wmi_reqMetadata or WILL_FIRE_RL_wmi_doWriteFinalize or wmi_lclMetaAddr or WILL_FIRE_RL_wmi_doReadReq or - MUX_bram_memory$b_put_2__VAL_2 or WILL_FIRE_RL_wmi_doWriteReq) + MUX_bram_0_memory$b_put_2__VAL_2 or WILL_FIRE_RL_wmi_doWriteReq) begin case (1'b1) // synopsys parallel_case WILL_FIRE_RL_wmi_reqMetadata || WILL_FIRE_RL_wmi_doWriteFinalize: - bram_memory_3$ADDRB = wmi_lclMetaAddr[14:4]; + bram_3_memory$ADDRB = wmi_lclMetaAddr[14:4]; WILL_FIRE_RL_wmi_doReadReq: - bram_memory_3$ADDRB = MUX_bram_memory$b_put_2__VAL_2; + bram_3_memory$ADDRB = MUX_bram_0_memory$b_put_2__VAL_2; WILL_FIRE_RL_wmi_doWriteReq: - bram_memory_3$ADDRB = MUX_bram_memory$b_put_2__VAL_2; - default: bram_memory_3$ADDRB = 11'b01010101010 /* unspecified value */ ; + bram_3_memory$ADDRB = MUX_bram_0_memory$b_put_2__VAL_2; + default: bram_3_memory$ADDRB = 11'b01010101010 /* unspecified value */ ; endcase end - always@(MUX_bram_memory_3$a_put_1__SEL_1 or - MUX_bram_memory$a_put_3__VAL_1 or - MUX_bram_memory_3$a_put_1__SEL_3 or - MUX_bram_memory_3$a_put_3__VAL_3 or - MUX_bram_memory_3$a_put_1__SEL_2 or + always@(MUX_bram_3_memory$a_put_1__SEL_1 or + MUX_bram_3_memory$a_put_3__VAL_1 or + MUX_bram_3_memory$a_put_1__SEL_2 or + MUX_bram_0_memory$a_put_3__VAL_2 or + MUX_bram_3_memory$a_put_1__SEL_3 or WILL_FIRE_RL_tlp_tlpBRAM_read_NextReq) begin case (1'b1) // synopsys parallel_case - MUX_bram_memory_3$a_put_1__SEL_1: - bram_memory_3$DIA = MUX_bram_memory$a_put_3__VAL_1; - MUX_bram_memory_3$a_put_1__SEL_3: - bram_memory_3$DIA = MUX_bram_memory_3$a_put_3__VAL_3; - MUX_bram_memory_3$a_put_1__SEL_2 || + MUX_bram_3_memory$a_put_1__SEL_1: + bram_3_memory$DIA = MUX_bram_3_memory$a_put_3__VAL_1; + MUX_bram_3_memory$a_put_1__SEL_2: + bram_3_memory$DIA = MUX_bram_0_memory$a_put_3__VAL_2; + MUX_bram_3_memory$a_put_1__SEL_3 || WILL_FIRE_RL_tlp_tlpBRAM_read_NextReq: - bram_memory_3$DIA = 32'd0; - default: bram_memory_3$DIA = 32'hAAAAAAAA /* unspecified value */ ; + bram_3_memory$DIA = 32'd0; + default: bram_3_memory$DIA = 32'hAAAAAAAA /* unspecified value */ ; endcase end always@(WILL_FIRE_RL_wmi_doWriteFinalize or @@ -5895,144 +5986,60 @@ module mkOCDP16B(pciDevice, begin case (1'b1) // synopsys parallel_case WILL_FIRE_RL_wmi_doWriteFinalize: - bram_memory_3$DIB = wmi_nowW$wget[31:0]; + bram_3_memory$DIB = wmi_nowW$wget[31:0]; WILL_FIRE_RL_wmi_doWriteReq: - bram_memory_3$DIB = wmi_wmi_dhF$D_OUT[143:112]; + bram_3_memory$DIB = wmi_wmi_dhF$D_OUT[143:112]; WILL_FIRE_RL_wmi_reqMetadata || WILL_FIRE_RL_wmi_doReadReq: - bram_memory_3$DIB = 32'd0; - default: bram_memory_3$DIB = 32'hAAAAAAAA /* unspecified value */ ; + bram_3_memory$DIB = 32'd0; + default: bram_3_memory$DIB = 32'hAAAAAAAA /* unspecified value */ ; endcase end - assign bram_memory_3$WEA = - !MUX_bram_memory_3$a_put_1__SEL_2 && + assign bram_3_memory$WEA = + !MUX_bram_3_memory$a_put_1__SEL_3 && !WILL_FIRE_RL_tlp_tlpBRAM_read_NextReq ; - assign bram_memory_3$WEB = bram_memory$WEB ; - assign bram_memory_3$ENA = + assign bram_3_memory$WEB = bram_0_memory$WEB ; + assign bram_3_memory$ENA = + WILL_FIRE_RL_tlp_tlpBRAM_writeData && + SEL_ARR_NOT_tlp_tlpBRAM_writeRemainDWLen_52_EQ_ETC___d677 || WILL_FIRE_RL_tlp_tlpBRAM_writeReq && - !tlp_tlpBRAM_mReqF$D_OUT[63] && - tlp_tlpBRAM_mReqF$D_OUT[51:50] == 2'd3 || + tlp_tlpBRAM_mReqF$D_OUT[51:50] == 2'd3 && + !tlp_tlpBRAM_mReqF$D_OUT[63] || WILL_FIRE_RL_tlp_tlpBRAM_read_FirstReq && - !tlp_tlpBRAM_mReqF$D_OUT[60] && - tlp_tlpBRAM_mReqF$D_OUT[30:29] == 2'd3 || - WILL_FIRE_RL_tlp_tlpBRAM_writeData && - IF_3_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2434 || + tlp_tlpBRAM_mReqF$D_OUT[30:29] == 2'd3 && + !tlp_tlpBRAM_mReqF$D_OUT[60] || WILL_FIRE_RL_tlp_tlpBRAM_read_NextReq ; - assign bram_memory_3$ENB = + assign bram_3_memory$ENB = WILL_FIRE_RL_wmi_reqMetadata || WILL_FIRE_RL_wmi_doReadReq || WILL_FIRE_RL_wmi_doWriteFinalize || WILL_FIRE_RL_wmi_doWriteReq ; - // submodule bram_serverAdapterA_1_outDataCore - assign bram_serverAdapterA_1_outDataCore$D_IN = bram_memory_1$DOA ; - assign bram_serverAdapterA_1_outDataCore$ENQ = - WILL_FIRE_RL_bram_serverAdapterA_1_outData_enqAndDeq || - bram_serverAdapterA_1_outDataCore$FULL_N && - !bram_serverAdapterA_1_outData_deqCalled$whas && - bram_serverAdapterA_1_outData_enqData$whas ; - assign bram_serverAdapterA_1_outDataCore$DEQ = - WILL_FIRE_RL_bram_serverAdapterA_1_outData_enqAndDeq || - bram_serverAdapterA_1_outDataCore$EMPTY_N && - bram_serverAdapterA_1_outData_deqCalled$whas && - !bram_serverAdapterA_1_outData_enqData$whas ; - assign bram_serverAdapterA_1_outDataCore$CLR = 1'b0 ; - - // submodule bram_serverAdapterA_2_outDataCore - assign bram_serverAdapterA_2_outDataCore$D_IN = bram_memory_2$DOA ; - assign bram_serverAdapterA_2_outDataCore$ENQ = - WILL_FIRE_RL_bram_serverAdapterA_2_outData_enqAndDeq || - bram_serverAdapterA_2_outDataCore$FULL_N && - !bram_serverAdapterA_2_outData_deqCalled$whas && - bram_serverAdapterA_2_outData_enqData$whas ; - assign bram_serverAdapterA_2_outDataCore$DEQ = - WILL_FIRE_RL_bram_serverAdapterA_2_outData_enqAndDeq || - bram_serverAdapterA_2_outDataCore$EMPTY_N && - bram_serverAdapterA_2_outData_deqCalled$whas && - !bram_serverAdapterA_2_outData_enqData$whas ; - assign bram_serverAdapterA_2_outDataCore$CLR = 1'b0 ; - - // submodule bram_serverAdapterA_3_outDataCore - assign bram_serverAdapterA_3_outDataCore$D_IN = bram_memory_3$DOA ; - assign bram_serverAdapterA_3_outDataCore$ENQ = - WILL_FIRE_RL_bram_serverAdapterA_3_outData_enqAndDeq || - bram_serverAdapterA_3_outDataCore$FULL_N && - !bram_serverAdapterA_3_outData_deqCalled$whas && - bram_serverAdapterA_3_outData_enqData$whas ; - assign bram_serverAdapterA_3_outDataCore$DEQ = - WILL_FIRE_RL_bram_serverAdapterA_3_outData_enqAndDeq || - bram_serverAdapterA_3_outDataCore$EMPTY_N && - bram_serverAdapterA_3_outData_deqCalled$whas && - !bram_serverAdapterA_3_outData_enqData$whas ; - assign bram_serverAdapterA_3_outDataCore$CLR = 1'b0 ; - - // submodule bram_serverAdapterA_outDataCore - assign bram_serverAdapterA_outDataCore$D_IN = bram_memory$DOA ; - assign bram_serverAdapterA_outDataCore$ENQ = - WILL_FIRE_RL_bram_serverAdapterA_outData_enqAndDeq || - bram_serverAdapterA_outDataCore$FULL_N && - !bram_serverAdapterA_outData_deqCalled$whas && - bram_serverAdapterA_outData_enqData$whas ; - assign bram_serverAdapterA_outDataCore$DEQ = - WILL_FIRE_RL_bram_serverAdapterA_outData_enqAndDeq || - bram_serverAdapterA_outDataCore$EMPTY_N && - bram_serverAdapterA_outData_deqCalled$whas && - !bram_serverAdapterA_outData_enqData$whas ; - assign bram_serverAdapterA_outDataCore$CLR = 1'b0 ; - - // submodule bram_serverAdapterB_1_outDataCore - assign bram_serverAdapterB_1_outDataCore$D_IN = bram_memory_1$DOB ; - assign bram_serverAdapterB_1_outDataCore$ENQ = - WILL_FIRE_RL_bram_serverAdapterB_1_outData_enqAndDeq || - bram_serverAdapterB_1_outDataCore$FULL_N && - !bram_serverAdapterB_outData_deqCalled$whas && - bram_serverAdapterB_1_outData_enqData$whas ; - assign bram_serverAdapterB_1_outDataCore$DEQ = - WILL_FIRE_RL_bram_serverAdapterB_1_outData_enqAndDeq || - bram_serverAdapterB_1_outDataCore$EMPTY_N && - bram_serverAdapterB_outData_deqCalled$whas && - !bram_serverAdapterB_1_outData_enqData$whas ; - assign bram_serverAdapterB_1_outDataCore$CLR = 1'b0 ; - - // submodule bram_serverAdapterB_2_outDataCore - assign bram_serverAdapterB_2_outDataCore$D_IN = bram_memory_2$DOB ; - assign bram_serverAdapterB_2_outDataCore$ENQ = - WILL_FIRE_RL_bram_serverAdapterB_2_outData_enqAndDeq || - bram_serverAdapterB_2_outDataCore$FULL_N && - !bram_serverAdapterB_outData_deqCalled$whas && - bram_serverAdapterB_2_outData_enqData$whas ; - assign bram_serverAdapterB_2_outDataCore$DEQ = - WILL_FIRE_RL_bram_serverAdapterB_2_outData_enqAndDeq || - bram_serverAdapterB_2_outDataCore$EMPTY_N && - bram_serverAdapterB_outData_deqCalled$whas && - !bram_serverAdapterB_2_outData_enqData$whas ; - assign bram_serverAdapterB_2_outDataCore$CLR = 1'b0 ; - - // submodule bram_serverAdapterB_3_outDataCore - assign bram_serverAdapterB_3_outDataCore$D_IN = bram_memory_3$DOB ; - assign bram_serverAdapterB_3_outDataCore$ENQ = - WILL_FIRE_RL_bram_serverAdapterB_3_outData_enqAndDeq || - bram_serverAdapterB_3_outDataCore$FULL_N && - !bram_serverAdapterB_outData_deqCalled$whas && - bram_serverAdapterB_3_outData_enqData$whas ; - assign bram_serverAdapterB_3_outDataCore$DEQ = - WILL_FIRE_RL_bram_serverAdapterB_3_outData_enqAndDeq || - bram_serverAdapterB_3_outDataCore$EMPTY_N && - bram_serverAdapterB_outData_deqCalled$whas && - !bram_serverAdapterB_3_outData_enqData$whas ; - assign bram_serverAdapterB_3_outDataCore$CLR = 1'b0 ; - - // submodule bram_serverAdapterB_outDataCore - assign bram_serverAdapterB_outDataCore$D_IN = bram_memory$DOB ; - assign bram_serverAdapterB_outDataCore$ENQ = - WILL_FIRE_RL_bram_serverAdapterB_outData_enqAndDeq || - bram_serverAdapterB_outDataCore$FULL_N && - !bram_serverAdapterB_outData_deqCalled$whas && - bram_serverAdapterB_outData_enqData$whas ; - assign bram_serverAdapterB_outDataCore$DEQ = - WILL_FIRE_RL_bram_serverAdapterB_outData_enqAndDeq || - bram_serverAdapterB_outDataCore$EMPTY_N && - bram_serverAdapterB_outData_deqCalled$whas && - !bram_serverAdapterB_outData_enqData$whas ; - assign bram_serverAdapterB_outDataCore$CLR = 1'b0 ; + // submodule bram_3_serverAdapterA_outDataCore + assign bram_3_serverAdapterA_outDataCore$D_IN = bram_3_memory$DOA ; + assign bram_3_serverAdapterA_outDataCore$ENQ = + WILL_FIRE_RL_bram_3_serverAdapterA_outData_enqAndDeq || + bram_3_serverAdapterA_outDataCore$FULL_N && + !bram_3_serverAdapterA_outData_deqCalled$whas && + bram_3_serverAdapterA_outData_enqData$whas ; + assign bram_3_serverAdapterA_outDataCore$DEQ = + WILL_FIRE_RL_bram_3_serverAdapterA_outData_enqAndDeq || + bram_3_serverAdapterA_outDataCore$EMPTY_N && + bram_3_serverAdapterA_outData_deqCalled$whas && + !bram_3_serverAdapterA_outData_enqData$whas ; + assign bram_3_serverAdapterA_outDataCore$CLR = 1'b0 ; + + // submodule bram_3_serverAdapterB_outDataCore + assign bram_3_serverAdapterB_outDataCore$D_IN = bram_3_memory$DOB ; + assign bram_3_serverAdapterB_outDataCore$ENQ = + WILL_FIRE_RL_bram_3_serverAdapterB_outData_enqAndDeq || + bram_3_serverAdapterB_outDataCore$FULL_N && + !bram_0_serverAdapterB_outData_deqCalled$whas && + bram_3_serverAdapterB_outData_enqData$whas ; + assign bram_3_serverAdapterB_outDataCore$DEQ = + WILL_FIRE_RL_bram_3_serverAdapterB_outData_enqAndDeq || + bram_3_serverAdapterB_outDataCore$EMPTY_N && + bram_0_serverAdapterB_outData_deqCalled$whas && + !bram_3_serverAdapterB_outData_enqData$whas ; + assign bram_3_serverAdapterB_outDataCore$CLR = 1'b0 ; // submodule tlp_inF assign tlp_inF$D_IN = server_request_put ; @@ -6046,53 +6053,53 @@ module mkOCDP16B(pciDevice, assign tlp_inF$CLR = 1'b0 ; // submodule tlp_outF - always@(WILL_FIRE_RL_tlp_dmaPushResponseHeader or + always@(MUX_tlp_tlpXmtBusy$write_1__PSEL_2 or MUX_tlp_outF$enq_1__VAL_1 or - WILL_FIRE_RL_tlp_dmaXmtMetaHead or + WILL_FIRE_RL_tlp_dmaPushResponseHeader or MUX_tlp_outF$enq_1__VAL_2 or - WILL_FIRE_RL_tlp_dmaXmtMetaBody or + WILL_FIRE_RL_tlp_dmaXmtMetaHead or MUX_tlp_outF$enq_1__VAL_3 or - WILL_FIRE_RL_tlp_dmaRequestFarMeta or + WILL_FIRE_RL_tlp_dmaXmtMetaBody or MUX_tlp_outF$enq_1__VAL_4 or - WILL_FIRE_RL_tlp_dmaPullRequestFarMesg or + WILL_FIRE_RL_tlp_dmaRequestFarMeta or MUX_tlp_outF$enq_1__VAL_5 or - WILL_FIRE_RL_tlp_dmaTailEventSender or + WILL_FIRE_RL_tlp_dmaPullRequestFarMesg or MUX_tlp_outF$enq_1__VAL_6 or - WILL_FIRE_RL_tlp_dataXmt_Header or + WILL_FIRE_RL_tlp_dmaTailEventSender or MUX_tlp_outF$enq_1__VAL_7 or - MUX_tlp_tlpXmtBusy$write_1__PSEL_4 or MUX_tlp_outF$enq_1__VAL_8) + WILL_FIRE_RL_tlp_dataXmt_Header or MUX_tlp_outF$enq_1__VAL_8) begin case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_tlp_dmaPushResponseHeader: + MUX_tlp_tlpXmtBusy$write_1__PSEL_2: tlp_outF$D_IN = MUX_tlp_outF$enq_1__VAL_1; - WILL_FIRE_RL_tlp_dmaXmtMetaHead: + WILL_FIRE_RL_tlp_dmaPushResponseHeader: tlp_outF$D_IN = MUX_tlp_outF$enq_1__VAL_2; - WILL_FIRE_RL_tlp_dmaXmtMetaBody: + WILL_FIRE_RL_tlp_dmaXmtMetaHead: tlp_outF$D_IN = MUX_tlp_outF$enq_1__VAL_3; - WILL_FIRE_RL_tlp_dmaRequestFarMeta: + WILL_FIRE_RL_tlp_dmaXmtMetaBody: tlp_outF$D_IN = MUX_tlp_outF$enq_1__VAL_4; - WILL_FIRE_RL_tlp_dmaPullRequestFarMesg: + WILL_FIRE_RL_tlp_dmaRequestFarMeta: tlp_outF$D_IN = MUX_tlp_outF$enq_1__VAL_5; - WILL_FIRE_RL_tlp_dmaTailEventSender: + WILL_FIRE_RL_tlp_dmaPullRequestFarMesg: tlp_outF$D_IN = MUX_tlp_outF$enq_1__VAL_6; - WILL_FIRE_RL_tlp_dataXmt_Header: + WILL_FIRE_RL_tlp_dmaTailEventSender: tlp_outF$D_IN = MUX_tlp_outF$enq_1__VAL_7; - MUX_tlp_tlpXmtBusy$write_1__PSEL_4: + WILL_FIRE_RL_tlp_dataXmt_Header: tlp_outF$D_IN = MUX_tlp_outF$enq_1__VAL_8; default: tlp_outF$D_IN = 153'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ; endcase end assign tlp_outF$ENQ = + WILL_FIRE_RL_tlp_dataXmt_Body || + WILL_FIRE_RL_tlp_dmaPushResponseBody || WILL_FIRE_RL_tlp_dmaPushResponseHeader || WILL_FIRE_RL_tlp_dmaXmtMetaHead || WILL_FIRE_RL_tlp_dmaXmtMetaBody || WILL_FIRE_RL_tlp_dmaRequestFarMeta || WILL_FIRE_RL_tlp_dmaPullRequestFarMesg || WILL_FIRE_RL_tlp_dmaTailEventSender || - WILL_FIRE_RL_tlp_dataXmt_Header || - WILL_FIRE_RL_tlp_dataXmt_Body || - WILL_FIRE_RL_tlp_dmaPushResponseBody ; + WILL_FIRE_RL_tlp_dataXmt_Header ; assign tlp_outF$DEQ = EN_server_response_get ; assign tlp_outF$CLR = 1'b0 ; @@ -6108,29 +6115,29 @@ module mkOCDP16B(pciDevice, // submodule tlp_tlpBRAM_mReqF always@(MUX_tlp_tlpBRAM_mReqF$enq_1__SEL_1 or MUX_tlp_tlpBRAM_mReqF$enq_1__VAL_1 or - WILL_FIRE_RL_tlp_dmaRequestNearMeta or + MUX_tlp_tlpBRAM_mReqF$enq_1__SEL_2 or MUX_tlp_tlpBRAM_mReqF$enq_1__VAL_2 or - WILL_FIRE_RL_tlp_dmaPushRequestMesg or + WILL_FIRE_RL_tlp_dmaRequestNearMeta or MUX_tlp_tlpBRAM_mReqF$enq_1__VAL_3 or - WILL_FIRE_RL_tlp_dmaRespHeadFarMeta or + WILL_FIRE_RL_tlp_dmaPushRequestMesg or MUX_tlp_tlpBRAM_mReqF$enq_1__VAL_4 or - WILL_FIRE_RL_tlp_dmaPullResponseHeader or + WILL_FIRE_RL_tlp_dmaRespHeadFarMeta or MUX_tlp_tlpBRAM_mReqF$enq_1__VAL_5 or - MUX_tlp_tlpBRAM_mReqF$enq_1__SEL_6 or + WILL_FIRE_RL_tlp_dmaPullResponseHeader or MUX_tlp_tlpBRAM_mReqF$enq_1__VAL_6) begin case (1'b1) // synopsys parallel_case MUX_tlp_tlpBRAM_mReqF$enq_1__SEL_1: tlp_tlpBRAM_mReqF$D_IN = MUX_tlp_tlpBRAM_mReqF$enq_1__VAL_1; - WILL_FIRE_RL_tlp_dmaRequestNearMeta: + MUX_tlp_tlpBRAM_mReqF$enq_1__SEL_2: tlp_tlpBRAM_mReqF$D_IN = MUX_tlp_tlpBRAM_mReqF$enq_1__VAL_2; - WILL_FIRE_RL_tlp_dmaPushRequestMesg: + WILL_FIRE_RL_tlp_dmaRequestNearMeta: tlp_tlpBRAM_mReqF$D_IN = MUX_tlp_tlpBRAM_mReqF$enq_1__VAL_3; - WILL_FIRE_RL_tlp_dmaRespHeadFarMeta: + WILL_FIRE_RL_tlp_dmaPushRequestMesg: tlp_tlpBRAM_mReqF$D_IN = MUX_tlp_tlpBRAM_mReqF$enq_1__VAL_4; - WILL_FIRE_RL_tlp_dmaPullResponseHeader: + WILL_FIRE_RL_tlp_dmaRespHeadFarMeta: tlp_tlpBRAM_mReqF$D_IN = MUX_tlp_tlpBRAM_mReqF$enq_1__VAL_5; - MUX_tlp_tlpBRAM_mReqF$enq_1__SEL_6: + WILL_FIRE_RL_tlp_dmaPullResponseHeader: tlp_tlpBRAM_mReqF$D_IN = MUX_tlp_tlpBRAM_mReqF$enq_1__VAL_6; default: tlp_tlpBRAM_mReqF$D_IN = 130'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ; @@ -6138,19 +6145,19 @@ module mkOCDP16B(pciDevice, end assign tlp_tlpBRAM_mReqF$ENQ = WILL_FIRE_RL_tlp_tlpRcv && - tlp_inF_first__367_BIT_152_570_AND_NOT_tlp_inF_ETC___d1595 || + tlp_inF_first__259_BIT_152_462_AND_NOT_tlp_inF_ETC___d1487 || + WILL_FIRE_RL_tlp_dmaPullResponseBody || + WILL_FIRE_RL_tlp_dmaRespBodyFarMeta || WILL_FIRE_RL_tlp_dmaRequestNearMeta || WILL_FIRE_RL_tlp_dmaPushRequestMesg || WILL_FIRE_RL_tlp_dmaRespHeadFarMeta || - WILL_FIRE_RL_tlp_dmaPullResponseHeader || - WILL_FIRE_RL_tlp_dmaPullResponseBody || - WILL_FIRE_RL_tlp_dmaRespBodyFarMeta ; + WILL_FIRE_RL_tlp_dmaPullResponseHeader ; assign tlp_tlpBRAM_mReqF$DEQ = WILL_FIRE_RL_tlp_tlpBRAM_read_FirstReq && tlp_tlpBRAM_mReqF$D_OUT[28:19] == 10'd1 && !tlp_tlpBRAM_mReqF$D_OUT[60] || WILL_FIRE_RL_tlp_tlpBRAM_read_NextReq && - tlp_tlpBRAM_readRemainDWLen_46_ULE_4___d847 || + tlp_tlpBRAM_readRemainDWLen_74_ULE_4___d775 || WILL_FIRE_RL_tlp_tlpBRAM_writeData || WILL_FIRE_RL_tlp_tlpBRAM_writeReq ; assign tlp_tlpBRAM_mReqF$CLR = 1'b0 ; @@ -6180,7 +6187,7 @@ module mkOCDP16B(pciDevice, tlp_tlpBRAM_readReq$D_OUT[28:19] == 10'd1 && !tlp_tlpBRAM_readReq$D_OUT[60] || WILL_FIRE_RL_tlp_tlpBRAM_read_NextResp && - tlp_tlpBRAM_rdRespDwRemain_024_ULE_4___d1026 ; + tlp_tlpBRAM_rdRespDwRemain_16_ULE_4___d918 ; assign tlp_tlpBRAM_readReq$CLR = 1'b0 ; // submodule wci_reqF @@ -6208,259 +6215,280 @@ module mkOCDP16B(pciDevice, assign wmi_wmi_reqF$CLR = 1'b0 ; // remaining internal signals - assign IF_1_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d708 = - (IF_1_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d685 || - bram_serverAdapterA_1_cnt_44_SLT_3___d2629) && - (IF_2_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d695 || - bram_serverAdapterA_2_cnt_62_SLT_3___d2630) && - (IF_3_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d705 || - bram_serverAdapterA_3_cnt_80_SLT_3___d2631) ; - assign IF_tlp_fabMesgAddrMS_186_EQ_0_187_THEN_0_ELSE__ETC___d1461 = + assign IF_bml_dpControl_wget__898_BITS_1_TO_0_904_EQ__ETC___d1984 = + CASE_dpControl_BITS_1_TO_0_0_bml_fabDone_1_bml_ETC__q4 && + !bml_lclBufStart || + CASE_dpControl_BITS_1_TO_0_0_NOT_bml_fabDone_1_ETC__q5 && + bml_lclBufStart ; + assign IF_bml_dpControl_wget__898_BITS_3_TO_2_899_EQ__ETC___d1995 = + (dpControl[3:2] == 2'd1) ? !bml_remDone : !bml_remStart ; + assign IF_tlp_fabMesgAddrMS_078_EQ_0_079_THEN_0_ELSE__ETC___d1353 = { (tlp_fabMesgAddrMS == 32'd0) ? 22'd0 : 22'd524288, - thisRequestLength__h62254[11:2], + thisRequestLength__h63893[11:2], pciDevice, - tag__h62529, - lastBE__h62561, + tag__h64168, + lastBE__h64200, 4'd15, (tlp_fabMesgAddrMS == 32'd0) ? { tlp_fabMesgAccu[31:2], 34'd0 } : { tlp_fabMesgAddrMS, tlp_fabMesgAccu[31:2], 2'b0 } } ; - assign IF_tlp_fabMetaAddrMS_265_EQ_0_266_THEN_4_ELSE__ETC___d1356 = + assign IF_tlp_fabMetaAddrMS_157_EQ_0_158_THEN_4_ELSE__ETC___d1248 = { (tlp_fabMetaAddrMS == 32'd0) ? 32'd4 : 32'd536870916, pciDevice, - tag__h62529, + tag__h64168, 8'd255, (tlp_fabMetaAddrMS == 32'd0) ? { tlp_fabMetaAddr[31:2], 34'd0 } : { tlp_fabMetaAddrMS, tlp_fabMetaAddr[31:2], 2'b0 } } ; - assign IF_tlp_tlpBRAM_readReq_first__97_BITS_30_TO_29_ETC___d1037 = - tlp_tlpBRAM_readReq_first__97_BITS_30_TO_29_99_ETC___d2404[0] ? - { bram_serverAdapterA_3_outData_outData$wget[7:0], - bram_serverAdapterA_3_outData_outData$wget[15:8], - bram_serverAdapterA_3_outData_outData$wget[23:16], - bram_serverAdapterA_3_outData_outData$wget[31:24], - bram_serverAdapterA_outData_outData$wget[7:0], - bram_serverAdapterA_outData_outData$wget[15:8], - bram_serverAdapterA_outData_outData$wget[23:16], - bram_serverAdapterA_outData_outData$wget[31:24], - bram_serverAdapterA_1_outData_outData$wget[7:0], - bram_serverAdapterA_1_outData_outData$wget[15:8], - bram_serverAdapterA_1_outData_outData$wget[23:16], - bram_serverAdapterA_1_outData_outData$wget[31:24], - bram_serverAdapterA_2_outData_outData$wget[7:0], - bram_serverAdapterA_2_outData_outData$wget[15:8], - bram_serverAdapterA_2_outData_outData$wget[23:16], - bram_serverAdapterA_2_outData_outData$wget[31:24] } : - { bram_serverAdapterA_2_outData_outData$wget[7:0], - bram_serverAdapterA_2_outData_outData$wget[15:8], - bram_serverAdapterA_2_outData_outData$wget[23:16], - bram_serverAdapterA_2_outData_outData$wget[31:24], - bram_serverAdapterA_3_outData_outData$wget[7:0], - bram_serverAdapterA_3_outData_outData$wget[15:8], - bram_serverAdapterA_3_outData_outData$wget[23:16], - bram_serverAdapterA_3_outData_outData$wget[31:24], - bram_serverAdapterA_outData_outData$wget[7:0], - bram_serverAdapterA_outData_outData$wget[15:8], - bram_serverAdapterA_outData_outData$wget[23:16], - bram_serverAdapterA_outData_outData$wget[31:24], - bram_serverAdapterA_1_outData_outData$wget[7:0], - bram_serverAdapterA_1_outData_outData$wget[15:8], - bram_serverAdapterA_1_outData_outData$wget[23:16], - bram_serverAdapterA_1_outData_outData$wget[31:24] } ; - assign IF_tlp_tlpBRAM_readReq_first__97_BITS_30_TO_29_ETC___d1042 = - tlp_tlpBRAM_readReq_first__97_BITS_30_TO_29_99_ETC___d2404[0] ? - { bram_serverAdapterA_1_outData_outData$wget[7:0], - bram_serverAdapterA_1_outData_outData$wget[15:8], - bram_serverAdapterA_1_outData_outData$wget[23:16], - bram_serverAdapterA_1_outData_outData$wget[31:24], - bram_serverAdapterA_2_outData_outData$wget[7:0], - bram_serverAdapterA_2_outData_outData$wget[15:8], - bram_serverAdapterA_2_outData_outData$wget[23:16], - bram_serverAdapterA_2_outData_outData$wget[31:24], - bram_serverAdapterA_3_outData_outData$wget[7:0], - bram_serverAdapterA_3_outData_outData$wget[15:8], - bram_serverAdapterA_3_outData_outData$wget[23:16], - bram_serverAdapterA_3_outData_outData$wget[31:24], - bram_serverAdapterA_outData_outData$wget[7:0], - bram_serverAdapterA_outData_outData$wget[15:8], - bram_serverAdapterA_outData_outData$wget[23:16], - bram_serverAdapterA_outData_outData$wget[31:24] } : - { bram_serverAdapterA_outData_outData$wget[7:0], - bram_serverAdapterA_outData_outData$wget[15:8], - bram_serverAdapterA_outData_outData$wget[23:16], - bram_serverAdapterA_outData_outData$wget[31:24], - bram_serverAdapterA_1_outData_outData$wget[7:0], - bram_serverAdapterA_1_outData_outData$wget[15:8], - bram_serverAdapterA_1_outData_outData$wget[23:16], - bram_serverAdapterA_1_outData_outData$wget[31:24], - bram_serverAdapterA_2_outData_outData$wget[7:0], - bram_serverAdapterA_2_outData_outData$wget[15:8], - bram_serverAdapterA_2_outData_outData$wget[23:16], - bram_serverAdapterA_2_outData_outData$wget[31:24], - bram_serverAdapterA_3_outData_outData$wget[7:0], - bram_serverAdapterA_3_outData_outData$wget[15:8], - bram_serverAdapterA_3_outData_outData$wget[23:16], - bram_serverAdapterA_3_outData_outData$wget[31:24] } ; - assign IF_tlp_tlpBRAM_readReq_first__97_BITS_30_TO_29_ETC___d921 = - IF_tlp_tlpBRAM_readReq_first__97_BITS_30_TO_29_ETC___d912 && - CASE_tlp_tlpBRAM_readReqD_OUT_BITS_30_TO_29_N_ETC__q17 ; - assign NOT_bml_lclBufDone_032_099_AND_IF_bml_dpContro_ETC___d2112 = - !bml_lclBufDone && - CASE_dpControl_BITS_1_TO_0_bml_fabDone_0_bml_f_ETC__q3 ; - assign NOT_wmi_wrActive_827_828_OR_NOT_wmi_rdActive_8_ETC___d1837 = + assign IF_tlp_tlpBRAM_readReq_first__98_BITS_30_TO_29_ETC___d929 = + tlp_tlpBRAM_readReq_first__98_BITS_30_TO_29_00_ETC___d922[0] ? + { bram_3_serverAdapterA_outData_outData$wget[7:0], + bram_3_serverAdapterA_outData_outData$wget[15:8], + bram_3_serverAdapterA_outData_outData$wget[23:16], + bram_3_serverAdapterA_outData_outData$wget[31:24], + bram_0_serverAdapterA_outData_outData$wget[7:0], + bram_0_serverAdapterA_outData_outData$wget[15:8], + bram_0_serverAdapterA_outData_outData$wget[23:16], + bram_0_serverAdapterA_outData_outData$wget[31:24], + bram_1_serverAdapterA_outData_outData$wget[7:0], + bram_1_serverAdapterA_outData_outData$wget[15:8], + bram_1_serverAdapterA_outData_outData$wget[23:16], + bram_1_serverAdapterA_outData_outData$wget[31:24], + bram_2_serverAdapterA_outData_outData$wget[7:0], + bram_2_serverAdapterA_outData_outData$wget[15:8], + bram_2_serverAdapterA_outData_outData$wget[23:16], + bram_2_serverAdapterA_outData_outData$wget[31:24] } : + { bram_2_serverAdapterA_outData_outData$wget[7:0], + bram_2_serverAdapterA_outData_outData$wget[15:8], + bram_2_serverAdapterA_outData_outData$wget[23:16], + bram_2_serverAdapterA_outData_outData$wget[31:24], + bram_3_serverAdapterA_outData_outData$wget[7:0], + bram_3_serverAdapterA_outData_outData$wget[15:8], + bram_3_serverAdapterA_outData_outData$wget[23:16], + bram_3_serverAdapterA_outData_outData$wget[31:24], + bram_0_serverAdapterA_outData_outData$wget[7:0], + bram_0_serverAdapterA_outData_outData$wget[15:8], + bram_0_serverAdapterA_outData_outData$wget[23:16], + bram_0_serverAdapterA_outData_outData$wget[31:24], + bram_1_serverAdapterA_outData_outData$wget[7:0], + bram_1_serverAdapterA_outData_outData$wget[15:8], + bram_1_serverAdapterA_outData_outData$wget[23:16], + bram_1_serverAdapterA_outData_outData$wget[31:24] } ; + assign IF_tlp_tlpBRAM_readReq_first__98_BITS_30_TO_29_ETC___d934 = + tlp_tlpBRAM_readReq_first__98_BITS_30_TO_29_00_ETC___d922[0] ? + { bram_1_serverAdapterA_outData_outData$wget[7:0], + bram_1_serverAdapterA_outData_outData$wget[15:8], + bram_1_serverAdapterA_outData_outData$wget[23:16], + bram_1_serverAdapterA_outData_outData$wget[31:24], + bram_2_serverAdapterA_outData_outData$wget[7:0], + bram_2_serverAdapterA_outData_outData$wget[15:8], + bram_2_serverAdapterA_outData_outData$wget[23:16], + bram_2_serverAdapterA_outData_outData$wget[31:24], + bram_3_serverAdapterA_outData_outData$wget[7:0], + bram_3_serverAdapterA_outData_outData$wget[15:8], + bram_3_serverAdapterA_outData_outData$wget[23:16], + bram_3_serverAdapterA_outData_outData$wget[31:24], + bram_0_serverAdapterA_outData_outData$wget[7:0], + bram_0_serverAdapterA_outData_outData$wget[15:8], + bram_0_serverAdapterA_outData_outData$wget[23:16], + bram_0_serverAdapterA_outData_outData$wget[31:24] } : + { bram_0_serverAdapterA_outData_outData$wget[7:0], + bram_0_serverAdapterA_outData_outData$wget[15:8], + bram_0_serverAdapterA_outData_outData$wget[23:16], + bram_0_serverAdapterA_outData_outData$wget[31:24], + bram_1_serverAdapterA_outData_outData$wget[7:0], + bram_1_serverAdapterA_outData_outData$wget[15:8], + bram_1_serverAdapterA_outData_outData$wget[23:16], + bram_1_serverAdapterA_outData_outData$wget[31:24], + bram_2_serverAdapterA_outData_outData$wget[7:0], + bram_2_serverAdapterA_outData_outData$wget[15:8], + bram_2_serverAdapterA_outData_outData$wget[23:16], + bram_2_serverAdapterA_outData_outData$wget[31:24], + bram_3_serverAdapterA_outData_outData$wget[7:0], + bram_3_serverAdapterA_outData_outData$wget[15:8], + bram_3_serverAdapterA_outData_outData$wget[23:16], + bram_3_serverAdapterA_outData_outData$wget[31:24] } ; + assign NOT_SEL_ARR_NOT_tlp_tlpBRAM_writeRemainDWLen_5_ETC___d681 = + (!SEL_ARR_NOT_tlp_tlpBRAM_writeRemainDWLen_52_EQ_ETC___d669 || + bram_1_serverAdapterA_cnt_44_SLT_3___d620) && + (!SEL_ARR_NOT_tlp_tlpBRAM_writeRemainDWLen_52_EQ_ETC___d673 || + bram_2_serverAdapterA_cnt_62_SLT_3___d621) && + (!SEL_ARR_NOT_tlp_tlpBRAM_writeRemainDWLen_52_EQ_ETC___d677 || + bram_3_serverAdapterA_cnt_80_SLT_3___d622) ; + assign NOT_tlp_tlpBRAM_writeRemainDWLen_52_ULE_1_55___d656 = + tlp_tlpBRAM_writeRemainDWLen > 10'd1 ; + assign NOT_tlp_tlpBRAM_writeRemainDWLen_52_ULE_2_57___d658 = + tlp_tlpBRAM_writeRemainDWLen > 10'd2 ; + assign NOT_tlp_tlpBRAM_writeRemainDWLen_52_ULE_3_59___d660 = + tlp_tlpBRAM_writeRemainDWLen > 10'd3 ; + assign NOT_wmi_wrActive_717_718_OR_NOT_wmi_rdActive_7_ETC___d1727 = (!wmi_wrActive || !wmi_rdActive) && !wmi_wrFinalize && (wmi_mesgBufReady || wmi_mesgBusy) ; + assign _dfoo1 = + wci_respF_cntr_r != 2'd2 || + wci_respF_cntr_r_90_MINUS_1___d499 == 2'd1 ; + assign _dfoo3 = + wci_respF_cntr_r != 2'd1 || + wci_respF_cntr_r_90_MINUS_1___d499 == 2'd0 ; assign _dfoo5 = tlp_fabMesgAddrMS != 32'd0 || tlp_tlpBRAM_mRespF$D_OUT[71:62] != 10'd1 || tlp_tlpBRAM_mRespF$D_OUT[42:35] == 8'h01 ; - assign ab__h10453 = - (MUX_bram_memory_3$a_put_1__SEL_2 || + assign _dfoo7 = + wmi_wmi_respF_cntr_r != 2'd2 || + wmi_wmi_respF_cntr_r_582_MINUS_1___d1590 == 2'd1 ; + assign _dfoo9 = + wmi_wmi_respF_cntr_r != 2'd1 || + wmi_wmi_respF_cntr_r_582_MINUS_1___d1590 == 2'd0 ; + assign ab__h10465 = + (MUX_bram_3_memory$a_put_1__SEL_3 || WILL_FIRE_RL_tlp_tlpBRAM_read_NextReq) ? 2'd0 : 2'd2 ; - assign ab__h11857 = - MUX_bram_serverAdapterB_1_writeWithResp$wset_1__SEL_1 ? + assign ab__h11870 = + MUX_bram_0_serverAdapterB_writeWithResp$wset_1__SEL_1 ? 2'd0 : 2'd2 ; - assign ab__h1613 = - (MUX_bram_memory$a_put_1__SEL_2 || + assign ab__h1619 = + (MUX_bram_0_memory$a_put_1__SEL_3 || WILL_FIRE_RL_tlp_tlpBRAM_read_NextReq) ? 2'd0 : 2'd2 ; - assign ab__h3019 = - MUX_bram_serverAdapterB_1_writeWithResp$wset_1__SEL_1 ? + assign ab__h3026 = + MUX_bram_0_serverAdapterB_writeWithResp$wset_1__SEL_1 ? 2'd0 : 2'd2 ; - assign ab__h4561 = - (MUX_bram_memory_1$a_put_1__SEL_2 || + assign ab__h4569 = + (MUX_bram_1_memory$a_put_1__SEL_3 || WILL_FIRE_RL_tlp_tlpBRAM_read_NextReq) ? 2'd0 : 2'd2 ; - assign ab__h5965 = - MUX_bram_serverAdapterB_1_writeWithResp$wset_1__SEL_1 ? + assign ab__h5974 = + MUX_bram_0_serverAdapterB_writeWithResp$wset_1__SEL_1 ? 2'd0 : 2'd2 ; - assign ab__h7507 = - (MUX_bram_memory_2$a_put_1__SEL_2 || + assign ab__h7517 = + (MUX_bram_2_memory$a_put_1__SEL_3 || WILL_FIRE_RL_tlp_tlpBRAM_read_NextReq) ? 2'd0 : 2'd2 ; - assign ab__h8911 = - MUX_bram_serverAdapterB_1_writeWithResp$wset_1__SEL_1 ? + assign ab__h8922 = + MUX_bram_0_serverAdapterB_writeWithResp$wset_1__SEL_1 ? 2'd0 : 2'd2 ; - assign bml_crdBuf_value_990_EQ_bml_crdBuf_modulus_bw__ETC___d2779 = + assign bml_crdBuf_value_880_EQ_bml_crdBuf_modulus_bw__ETC___d1882 = bml_crdBuf_value == bml_crdBuf_modulus ; - assign bml_fabBuf_value_975_EQ_bml_fabBuf_modulus_bw__ETC___d2780 = + assign bml_fabBuf_value_865_EQ_bml_fabBuf_modulus_bw__ETC___d1867 = bml_fabBuf_value == bml_fabBuf_modulus ; - assign bml_fabFlowAddr_047_PLUS_bml_fabFlowSize_048___d2624 = + assign bml_fabFlowAddr_937_PLUS_bml_fabFlowSize_938___d1939 = bml_fabFlowAddr + bml_fabFlowSize ; - assign bml_lclBufDone_032_AND_IF_bml_dpControl_wget___ETC___d2443 = + assign bml_lclBufDone_922_AND_IF_bml_dpControl_wget___ETC___d2003 = bml_lclBufDone && - CASE_dpControl_BITS_1_TO_0_NOT_bml_fabDone_0_N_ETC__q5 ; - assign bml_lclBuf_value_945_EQ_bml_lclBuf_modulus_bw__ETC___d2798 = + CASE_dpControl_BITS_1_TO_0_0_NOT_bml_fabDone_1_ETC__q6 || + !bml_lclBufDone && + CASE_dpControl_BITS_1_TO_0_0_bml_fabDone_1_IF__ETC__q7 ; + assign bml_lclBuf_value_835_EQ_bml_lclBuf_modulus_bw__ETC___d1837 = bml_lclBuf_value == bml_lclBuf_modulus ; - assign bml_remBuf_value_960_EQ_bml_remBuf_modulus_bw__ETC___d2799 = + assign bml_remBuf_value_850_EQ_bml_remBuf_modulus_bw__ETC___d1852 = bml_remBuf_value == bml_remBuf_modulus ; - assign bram_serverAdapterA_1_cnt_44_PLUS_IF_bram_serv_ETC___d150 = - bram_serverAdapterA_1_cnt + - (bram_serverAdapterA_1_cnt_1$whas ? 3'd1 : 3'd0) + - (bram_serverAdapterA_1_outData_deqCalled$whas ? 3'd7 : 3'd0) ; - assign bram_serverAdapterA_1_cnt_44_SLT_3___d2629 = - (bram_serverAdapterA_1_cnt ^ 3'h4) < 3'd7 ; - assign bram_serverAdapterA_2_cnt_62_PLUS_IF_bram_serv_ETC___d268 = - bram_serverAdapterA_2_cnt + - (bram_serverAdapterA_2_cnt_1$whas ? 3'd1 : 3'd0) + - (bram_serverAdapterA_2_outData_deqCalled$whas ? 3'd7 : 3'd0) ; - assign bram_serverAdapterA_2_cnt_62_SLT_3___d2630 = - (bram_serverAdapterA_2_cnt ^ 3'h4) < 3'd7 ; - assign bram_serverAdapterA_2_outDataCore_notEmpty__38_ETC___d993 = - (bram_serverAdapterA_2_outDataCore$EMPTY_N || - bram_serverAdapterA_2_outData_enqData$whas) && - (bram_serverAdapterA_3_outDataCore$EMPTY_N || - bram_serverAdapterA_3_outData_enqData$whas) && - bram_serverAdapterA_outData_outData$whas && - bram_serverAdapterA_1_outData_outData$whas && - bram_serverAdapterA_2_outData_outData$whas && - bram_serverAdapterA_3_outData_outData$whas && + assign bram_0_serverAdapterA_cnt_6_PLUS_IF_bram_0_ser_ETC___d32 = + bram_0_serverAdapterA_cnt + + (bram_0_serverAdapterA_cnt_1$whas ? 3'd1 : 3'd0) + + (bram_0_serverAdapterA_outData_deqCalled$whas ? 3'd7 : 3'd0) ; + assign bram_0_serverAdapterA_cnt_6_SLT_3___d619 = + (bram_0_serverAdapterA_cnt ^ 3'h4) < 3'd7 ; + assign bram_0_serverAdapterA_outDataCore_notEmpty_OR__ETC___d887 = + (bram_0_serverAdapterA_outDataCore$EMPTY_N || + bram_0_serverAdapterA_outData_enqData$whas) && + (bram_1_serverAdapterA_outDataCore$EMPTY_N || + bram_1_serverAdapterA_outData_enqData$whas) && + bram_2_serverAdapterA_outDataCore_notEmpty__38_ETC___d885 ; + assign bram_0_serverAdapterB_cnt_5_PLUS_IF_bram_0_ser_ETC___d91 = + bram_0_serverAdapterB_cnt + + (bram_0_serverAdapterB_cnt_1$whas ? 3'd1 : 3'd0) + + (bram_0_serverAdapterB_outData_deqCalled$whas ? 3'd7 : 3'd0) ; + assign bram_0_serverAdapterB_cnt_5_SLT_3_666_AND_bram_ETC___d1672 = + bram_0_serverAdapterB_cnt_5_SLT_3___d1666 && + bram_1_serverAdapterB_cnt_03_SLT_3___d1667 && + bram_2_serverAdapterB_cnt_21_SLT_3___d1668 && + bram_3_serverAdapterB_cnt_39_SLT_3___d1669 ; + assign bram_0_serverAdapterB_cnt_5_SLT_3___d1666 = + (bram_0_serverAdapterB_cnt ^ 3'h4) < 3'd7 ; + assign bram_0_serverAdapterB_outData_outData_whas__68_ETC___d1697 = + bram_0_serverAdapterB_outData_outData$whas && + (bram_1_serverAdapterB_outDataCore$EMPTY_N || + bram_1_serverAdapterB_outData_enqData$whas) && + bram_1_serverAdapterB_outData_outData_whas__68_ETC___d1695 ; + assign bram_1_serverAdapterA_cnt_44_PLUS_IF_bram_1_se_ETC___d150 = + bram_1_serverAdapterA_cnt + + (bram_1_serverAdapterA_cnt_1$whas ? 3'd1 : 3'd0) + + (bram_1_serverAdapterA_outData_deqCalled$whas ? 3'd7 : 3'd0) ; + assign bram_1_serverAdapterA_cnt_44_SLT_3___d620 = + (bram_1_serverAdapterA_cnt ^ 3'h4) < 3'd7 ; + assign bram_1_serverAdapterB_cnt_03_PLUS_IF_bram_1_se_ETC___d209 = + bram_1_serverAdapterB_cnt + + (bram_1_serverAdapterB_cnt_1$whas ? 3'd1 : 3'd0) + + (bram_0_serverAdapterB_outData_deqCalled$whas ? 3'd7 : 3'd0) ; + assign bram_1_serverAdapterB_cnt_03_SLT_3___d1667 = + (bram_1_serverAdapterB_cnt ^ 3'h4) < 3'd7 ; + assign bram_1_serverAdapterB_outData_outData_whas__68_ETC___d1695 = + bram_1_serverAdapterB_outData_outData$whas && + (bram_2_serverAdapterB_outDataCore$EMPTY_N || + bram_2_serverAdapterB_outData_enqData$whas) && + bram_2_serverAdapterB_outData_outData$whas && + (bram_3_serverAdapterB_outDataCore$EMPTY_N || + bram_3_serverAdapterB_outData_enqData$whas) && + bram_3_serverAdapterB_outData_outData$whas ; + assign bram_2_serverAdapterA_cnt_62_PLUS_IF_bram_2_se_ETC___d268 = + bram_2_serverAdapterA_cnt + + (bram_2_serverAdapterA_cnt_1$whas ? 3'd1 : 3'd0) + + (bram_2_serverAdapterA_outData_deqCalled$whas ? 3'd7 : 3'd0) ; + assign bram_2_serverAdapterA_cnt_62_SLT_3___d621 = + (bram_2_serverAdapterA_cnt ^ 3'h4) < 3'd7 ; + assign bram_2_serverAdapterA_outDataCore_notEmpty__38_ETC___d885 = + (bram_2_serverAdapterA_outDataCore$EMPTY_N || + bram_2_serverAdapterA_outData_enqData$whas) && + (bram_3_serverAdapterA_outDataCore$EMPTY_N || + bram_3_serverAdapterA_outData_enqData$whas) && + bram_0_serverAdapterA_outData_outData$whas && + bram_1_serverAdapterA_outData_outData$whas && + bram_2_serverAdapterA_outData_outData$whas && + bram_3_serverAdapterA_outData_outData$whas && tlp_tlpBRAM_mRespF$FULL_N ; - assign bram_serverAdapterA_3_cnt_80_PLUS_IF_bram_serv_ETC___d386 = - bram_serverAdapterA_3_cnt + - (bram_serverAdapterA_3_cnt_1$whas ? 3'd1 : 3'd0) + - (bram_serverAdapterA_3_outData_deqCalled$whas ? 3'd7 : 3'd0) ; - assign bram_serverAdapterA_3_cnt_80_SLT_3___d2631 = - (bram_serverAdapterA_3_cnt ^ 3'h4) < 3'd7 ; - assign bram_serverAdapterA_cnt_6_PLUS_IF_bram_serverA_ETC___d32 = - bram_serverAdapterA_cnt + - (bram_serverAdapterA_cnt_1$whas ? 3'd1 : 3'd0) + - (bram_serverAdapterA_outData_deqCalled$whas ? 3'd7 : 3'd0) ; - assign bram_serverAdapterA_cnt_6_SLT_3___d2628 = - (bram_serverAdapterA_cnt ^ 3'h4) < 3'd7 ; - assign bram_serverAdapterA_outDataCore_notEmpty_OR_br_ETC___d995 = - (bram_serverAdapterA_outDataCore$EMPTY_N || - bram_serverAdapterA_outData_enqData$whas) && - (bram_serverAdapterA_1_outDataCore$EMPTY_N || - bram_serverAdapterA_1_outData_enqData$whas) && - bram_serverAdapterA_2_outDataCore_notEmpty__38_ETC___d993 ; - assign bram_serverAdapterB_1_cnt_03_PLUS_IF_bram_serv_ETC___d209 = - bram_serverAdapterB_1_cnt + - (bram_serverAdapterB_1_cnt_1$whas ? 3'd1 : 3'd0) + - (bram_serverAdapterB_outData_deqCalled$whas ? 3'd7 : 3'd0) ; - assign bram_serverAdapterB_1_cnt_03_SLT_3___d1777 = - (bram_serverAdapterB_1_cnt ^ 3'h4) < 3'd7 ; - assign bram_serverAdapterB_1_outData_outData_whas__79_ETC___d1805 = - bram_serverAdapterB_1_outData_outData$whas && - (bram_serverAdapterB_2_outDataCore$EMPTY_N || - bram_serverAdapterB_2_outData_enqData$whas) && - bram_serverAdapterB_2_outData_outData$whas && - (bram_serverAdapterB_3_outDataCore$EMPTY_N || - bram_serverAdapterB_3_outData_enqData$whas) && - bram_serverAdapterB_3_outData_outData$whas ; - assign bram_serverAdapterB_2_cnt_21_PLUS_IF_bram_serv_ETC___d327 = - bram_serverAdapterB_2_cnt + - (bram_serverAdapterB_2_cnt_1$whas ? 3'd1 : 3'd0) + - (bram_serverAdapterB_outData_deqCalled$whas ? 3'd7 : 3'd0) ; - assign bram_serverAdapterB_2_cnt_21_SLT_3___d1778 = - (bram_serverAdapterB_2_cnt ^ 3'h4) < 3'd7 ; - assign bram_serverAdapterB_3_cnt_39_PLUS_IF_bram_serv_ETC___d445 = - bram_serverAdapterB_3_cnt + - (bram_serverAdapterB_3_cnt_1$whas ? 3'd1 : 3'd0) + - (bram_serverAdapterB_outData_deqCalled$whas ? 3'd7 : 3'd0) ; - assign bram_serverAdapterB_3_cnt_39_SLT_3___d1779 = - (bram_serverAdapterB_3_cnt ^ 3'h4) < 3'd7 ; - assign bram_serverAdapterB_cnt_5_PLUS_IF_bram_serverA_ETC___d91 = - bram_serverAdapterB_cnt + - (bram_serverAdapterB_cnt_1$whas ? 3'd1 : 3'd0) + - (bram_serverAdapterB_outData_deqCalled$whas ? 3'd7 : 3'd0) ; - assign bram_serverAdapterB_cnt_5_SLT_3_776_AND_bram_s_ETC___d1782 = - bram_serverAdapterB_cnt_5_SLT_3___d1776 && - bram_serverAdapterB_1_cnt_03_SLT_3___d1777 && - bram_serverAdapterB_2_cnt_21_SLT_3___d1778 && - bram_serverAdapterB_3_cnt_39_SLT_3___d1779 ; - assign bram_serverAdapterB_cnt_5_SLT_3___d1776 = - (bram_serverAdapterB_cnt ^ 3'h4) < 3'd7 ; - assign bram_serverAdapterB_outData_outData_whas__795__ETC___d1807 = - bram_serverAdapterB_outData_outData$whas && - (bram_serverAdapterB_1_outDataCore$EMPTY_N || - bram_serverAdapterB_1_outData_enqData$whas) && - bram_serverAdapterB_1_outData_outData_whas__79_ETC___d1805 ; - assign byteCount__h28412 = x__h28530 - y__h28531 ; - assign hasPull_AND_tlp_dpControl_wget__072_BITS_7_TO__ETC___d1341 = + assign bram_2_serverAdapterB_cnt_21_PLUS_IF_bram_2_se_ETC___d327 = + bram_2_serverAdapterB_cnt + + (bram_2_serverAdapterB_cnt_1$whas ? 3'd1 : 3'd0) + + (bram_0_serverAdapterB_outData_deqCalled$whas ? 3'd7 : 3'd0) ; + assign bram_2_serverAdapterB_cnt_21_SLT_3___d1668 = + (bram_2_serverAdapterB_cnt ^ 3'h4) < 3'd7 ; + assign bram_3_serverAdapterA_cnt_80_PLUS_IF_bram_3_se_ETC___d386 = + bram_3_serverAdapterA_cnt + + (bram_3_serverAdapterA_cnt_1$whas ? 3'd1 : 3'd0) + + (bram_3_serverAdapterA_outData_deqCalled$whas ? 3'd7 : 3'd0) ; + assign bram_3_serverAdapterA_cnt_80_SLT_3___d622 = + (bram_3_serverAdapterA_cnt ^ 3'h4) < 3'd7 ; + assign bram_3_serverAdapterB_cnt_39_PLUS_IF_bram_3_se_ETC___d445 = + bram_3_serverAdapterB_cnt + + (bram_3_serverAdapterB_cnt_1$whas ? 3'd1 : 3'd0) + + (bram_0_serverAdapterB_outData_deqCalled$whas ? 3'd7 : 3'd0) ; + assign bram_3_serverAdapterB_cnt_39_SLT_3___d1669 = + (bram_3_serverAdapterB_cnt ^ 3'h4) < 3'd7 ; + assign byteCount__h29653 = x__h29771 - y__h29772 ; + assign hasPull_AND_tlp_dpControl_wget__64_BITS_7_TO_4_ETC___d1233 = hasPull && dpControl[7:4] == 4'd0 && dpControl[3:2] == 2'd2 && dpControl[1:0] == 2'd1 && !tlp_tlpXmtBusy && !tlp_reqMetaInFlight && !tlp_reqMetaBodyInFlight && !tlp_fabMeta[128] ; - assign hasPull_AND_tlp_dpControl_wget__072_BITS_7_TO__ETC___d1382 = + assign hasPull_AND_tlp_dpControl_wget__64_BITS_7_TO_4_ETC___d1274 = hasPull && dpControl[7:4] == 4'd0 && dpControl[3:2] == 2'd2 && dpControl[1:0] == 2'd1 && tlp_reqMetaInFlight && !tlp_tlpRcvBusy && - tagm__h62748 == tlp_inF$D_OUT[47:40] && - tlp_inF_first__367_BITS_63_TO_56_370_EQ_pciDev_ETC___d1380 ; - assign hasPull_AND_tlp_dpControl_wget__072_BITS_7_TO__ETC___d1434 = + tagm__h64387 == tlp_inF$D_OUT[47:40] && + tlp_inF_first__259_BITS_63_TO_56_262_EQ_pciDev_ETC___d1272 ; + assign hasPull_AND_tlp_dpControl_wget__64_BITS_7_TO_4_ETC___d1326 = hasPull && dpControl[7:4] == 4'd0 && dpControl[3:2] == 2'd2 && dpControl[1:0] == 2'd1 && tlp_fabMeta[128] && @@ -6468,7 +6496,7 @@ module mkOCDP16B(pciDevice, !tlp_tlpXmtBusy && !tlp_reqMesgInFlight && tlp_mesgLengthRemainPull != 17'd0 ; - assign hasPull_AND_tlp_dpControl_wget__072_BITS_7_TO__ETC___d1473 = + assign hasPull_AND_tlp_dpControl_wget__64_BITS_7_TO_4_ETC___d1365 = hasPull && dpControl[7:4] == 4'd0 && dpControl[3:2] == 2'd2 && dpControl[1:0] == 2'd1 && tlp_fabMeta[128] && @@ -6476,41 +6504,34 @@ module mkOCDP16B(pciDevice, !tlp_tlpRcvBusy && tlp_pullTagMatch && !tlp_gotResponseHeader ; - assign hasPull_AND_tlp_dpControl_wget__072_BITS_7_TO__ETC___d1493 = + assign hasPull_AND_tlp_dpControl_wget__64_BITS_7_TO_4_ETC___d1385 = hasPull && dpControl[7:4] == 4'd0 && dpControl[3:2] == 2'd2 && dpControl[1:0] == 2'd1 && tlp_fabMeta[128] && tlp_reqMesgInFlight && tlp_gotResponseHeader ; - assign hasPull_AND_tlp_dpControl_wget__072_BITS_7_TO__ETC___d1518 = + assign hasPull_AND_tlp_dpControl_wget__64_BITS_7_TO_4_ETC___d1410 = hasPull && dpControl[7:4] == 4'd0 && dpControl[3:2] == 2'd2 && dpControl[1:0] == 2'd1 && tlp_fabMeta[128] && tlp_dmaDoTailEvent && tlp_postSeqDwell == 4'd0 && tlp_mesgComplReceived >= tlp_fabMeta[112:96] ; - assign hasPush_AND_tlp_dpControl_wget__072_BITS_7_TO__ETC___d1093 = - hasPush && dpControl[7:4] == 4'd0 && dpControl[3:2] == 2'd1 && - dpControl[1:0] == 2'd1 && - !tlp_tlpRcvBusy && - !tlp_reqMetaInFlight && - !tlp_fabMeta[128] && - tlp_nearBufReady ; - assign hasPush_AND_tlp_dpControl_wget__072_BITS_7_TO__ETC___d1166 = + assign hasPush_AND_tlp_dpControl_wget__64_BITS_7_TO_4_ETC___d1058 = hasPush && dpControl[7:4] == 4'd0 && dpControl[3:2] == 2'd1 && dpControl[1:0] == 2'd1 && tlp_fabMeta[128] && tlp_fabMeta[127:96] != 32'd0 && !tlp_tlpRcvBusy && tlp_mesgLengthRemainPush != 17'd0 ; - assign hasPush_AND_tlp_dpControl_wget__072_BITS_7_TO__ETC___d1206 = + assign hasPush_AND_tlp_dpControl_wget__64_BITS_7_TO_4_ETC___d1098 = hasPush && dpControl[7:4] == 4'd0 && dpControl[3:2] == 2'd1 && dpControl[1:0] == 2'd1 && !tlp_tlpBRAM_mRespF$D_OUT[138] && tlp_tlpBRAM_mRespF$D_OUT[89:88] == 2'd2 && !tlp_tlpXmtBusy && tlp_postSeqDwell == 4'd0 ; - assign hasPush_AND_tlp_dpControl_wget__072_BITS_7_TO__ETC___d1263 = + assign hasPush_AND_tlp_dpControl_wget__64_BITS_7_TO_4_ETC___d1155 = hasPush && dpControl[7:4] == 4'd0 && dpControl[3:2] == 2'd1 && dpControl[1:0] == 2'd1 && tlp_fabMeta[128] && @@ -6518,55 +6539,62 @@ module mkOCDP16B(pciDevice, !tlp_xmtMetaInFlight && tlp_xmtMetaOK && tlp_postSeqDwell == 4'd0 ; - assign idx__h19187 = 2'd0 - tlp_tlpBRAM_writeDWAddr[1:0] ; - assign idx__h21418 = 2'd1 - tlp_tlpBRAM_writeDWAddr[1:0] ; - assign idx__h22722 = 2'd2 - tlp_tlpBRAM_writeDWAddr[1:0] ; - assign idx__h24026 = 2'd3 - tlp_tlpBRAM_writeDWAddr[1:0] ; - assign idx__h26267 = 2'd0 - tlp_tlpBRAM_readNxtDWAddr[1:0] ; - assign idx__h26735 = 2'd1 - tlp_tlpBRAM_readNxtDWAddr[1:0] ; - assign idx__h27108 = 2'd2 - tlp_tlpBRAM_readNxtDWAddr[1:0] ; - assign idx__h27481 = 2'd3 - tlp_tlpBRAM_readNxtDWAddr[1:0] ; - assign lastBE__h46542 = - tlp_tlpBRAM_mRespF_first__108_BITS_71_TO_62_20_ETC___d2405 ? + assign hasPush_AND_tlp_dpControl_wget__64_BITS_7_TO_4_ETC___d985 = + hasPush && dpControl[7:4] == 4'd0 && dpControl[3:2] == 2'd1 && + dpControl[1:0] == 2'd1 && + !tlp_tlpRcvBusy && + !tlp_reqMetaInFlight && + !tlp_fabMeta[128] && + tlp_nearBufReady ; + assign idx__h21626 = 2'd0 - tlp_tlpBRAM_writeDWAddr[1:0] ; + assign idx__h23676 = 2'd1 - tlp_tlpBRAM_writeDWAddr[1:0] ; + assign idx__h24781 = 2'd2 - tlp_tlpBRAM_writeDWAddr[1:0] ; + assign idx__h25886 = 2'd3 - tlp_tlpBRAM_writeDWAddr[1:0] ; + assign idx__h27879 = 2'd0 - tlp_tlpBRAM_readNxtDWAddr[1:0] ; + assign idx__h28282 = 2'd1 - tlp_tlpBRAM_readNxtDWAddr[1:0] ; + assign idx__h28586 = 2'd2 - tlp_tlpBRAM_readNxtDWAddr[1:0] ; + assign idx__h28890 = 2'd3 - tlp_tlpBRAM_readNxtDWAddr[1:0] ; + assign lastBE__h47950 = + tlp_tlpBRAM_mRespF_first__000_BITS_71_TO_62_10_ETC___d1102 ? 4'd0 : 4'd15 ; - assign lastBE__h62561 = - (thisRequestLength__h62254[11:2] == 10'd1) ? 4'd0 : 4'd15 ; - assign lowAddr__h28411 = - { tlp_tlpBRAM_readReq$D_OUT[33:29], lowAddr10__h28410 } ; - assign mesgMeta_opcode__h80277 = + assign lastBE__h64200 = + (thisRequestLength__h63893[11:2] == 10'd1) ? 4'd0 : 4'd15 ; + assign lowAddr__h29652 = + { tlp_tlpBRAM_readReq$D_OUT[33:29], lowAddr10__h29651 } ; + assign mesgMeta_opcode__h81853 = { 24'h800000, wmi_wmi_mFlagF$D_OUT[31:24] } ; - assign nowLS__h44844 = + assign nowLS__h46239 = { tlp_tlpBRAM_mRespF$D_OUT[39:32], tlp_tlpBRAM_mRespF$D_OUT[47:40], tlp_tlpBRAM_mRespF$D_OUT[55:48], tlp_tlpBRAM_mRespF$D_OUT[63:56] } ; - assign nowLS__h60998 = + assign nowLS__h62622 = { tlp_inF$D_OUT[39:32], tlp_inF$D_OUT[47:40], tlp_inF$D_OUT[55:48], tlp_inF$D_OUT[63:56] } ; - assign nowMS__h43901 = + assign nowMS__h45280 = { tlp_tlpBRAM_mRespF$D_OUT[71:64], tlp_tlpBRAM_mRespF$D_OUT[79:72], tlp_tlpBRAM_mRespF$D_OUT[87:80], tlp_tlpBRAM_mRespF$D_OUT[95:88] } ; - assign nowMS__h60057 = + assign nowMS__h61665 = { tlp_inF$D_OUT[71:64], tlp_inF$D_OUT[79:72], tlp_inF$D_OUT[87:80], tlp_inF$D_OUT[95:88] } ; - assign opcode__h42670 = + assign opcode__h44022 = { tlp_tlpBRAM_mRespF$D_OUT[103:96], tlp_tlpBRAM_mRespF$D_OUT[111:104], tlp_tlpBRAM_mRespF$D_OUT[119:112], tlp_tlpBRAM_mRespF$D_OUT[127:120] } ; - assign opcode__h58837 = + assign opcode__h60417 = { tlp_inF$D_OUT[103:96], tlp_inF$D_OUT[111:104], tlp_inF$D_OUT[119:112], tlp_inF$D_OUT[127:120] } ; - assign pkt__h70068 = + assign pkt__h71785 = { 9'd148, tlp_tlpBRAM_mRespF$D_OUT[34:32], 10'd0, @@ -6579,146 +6607,139 @@ module mkOCDP16B(pciDevice, 1'b0, tlp_tlpBRAM_mRespF$D_OUT[61:55], tlp_tlpBRAM_mRespF$D_OUT[31:0] } ; - assign rdat__h90489 = { 16'd0, bml_lclNumBufs } ; - assign rdat__h90497 = { 16'd0, bml_fabNumBufs } ; - assign rdat__h90505 = { 16'd0, bml_mesgBase } ; - assign rdat__h90513 = { 16'd0, bml_metaBase } ; - assign rdat__h90521 = { 16'd0, bml_mesgSize } ; - assign rdat__h90529 = { 16'd0, bml_metaSize } ; - assign rdat__h90537 = { 16'd0, bml_lclBufsCF } ; - assign rdat__h90558 = + assign rdat__h92026 = { 16'd0, bml_lclNumBufs } ; + assign rdat__h92034 = { 16'd0, bml_fabNumBufs } ; + assign rdat__h92042 = { 16'd0, bml_mesgBase } ; + assign rdat__h92050 = { 16'd0, bml_metaBase } ; + assign rdat__h92058 = { 16'd0, bml_mesgSize } ; + assign rdat__h92066 = { 16'd0, bml_metaSize } ; + assign rdat__h92074 = { 16'd0, bml_lclBufsCF } ; + assign rdat__h92095 = hasDebugLogic ? { bml_lclBufsAR, bml_fabBufsAvail } : 32'd0 ; - assign rdat__h90565 = + assign rdat__h92102 = hasDebugLogic ? { bml_remBuf_value, bml_lclBuf_value } : 32'd0 ; - assign rdat__h90578 = + assign rdat__h92115 = hasDebugLogic ? { bml_lclStarts, bml_lclDones } : 32'd0 ; - assign rdat__h90585 = + assign rdat__h92122 = hasDebugLogic ? { bml_remStarts, bml_remDones } : 32'd0 ; - assign rdat__h90592 = hasDebugLogic ? wmi_thisMesg : 32'd0 ; - assign rdat__h90856 = hasDebugLogic ? wmi_lastMesg : 32'd0 ; - assign rdat__h90906 = + assign rdat__h92129 = hasDebugLogic ? wmi_thisMesg : 32'd0 ; + assign rdat__h92401 = hasDebugLogic ? wmi_lastMesg : 32'd0 ; + assign rdat__h92451 = hasDebugLogic ? { wmi_reqCount, wmi_wrtCount } : 32'd0 ; - assign rdat__h91006 = hasDebugLogic ? 32'hDADEBABE : 32'd0 ; - assign rdat__h91064 = { 24'd0, dpControl } ; - assign rdat__h91086 = hasDebugLogic ? tlp_flowDiagCount : 32'd0 ; - assign rdat__h91096 = + assign rdat__h92551 = hasDebugLogic ? 32'hDADEBABE : 32'd0 ; + assign rdat__h92609 = { 24'd0, dpControl } ; + assign rdat__h92631 = hasDebugLogic ? tlp_flowDiagCount : 32'd0 ; + assign rdat__h92641 = hasDebugLogic ? { 4'h0, tlp_complTimerCount, 12'h0, - CASE_tlp_lastRuleFired_10_1_tlp_lastRuleFired__ETC__q1 } : + CASE_tlp_lastRuleFired_1_tlp_lastRuleFired_2_t_ETC__q1 } : 32'd0 ; - assign rdat__h91218 = hasDebugLogic ? tlp_lastMetaV : 32'd0 ; - assign rdat__h91339 = hasDebugLogic ? tlp_lastMetaV_1 : 32'd0 ; - assign rdat__h91368 = hasDebugLogic ? tlp_lastMetaV_2 : 32'd0 ; - assign rdat__h91397 = hasDebugLogic ? tlp_lastMetaV_3 : 32'd0 ; - assign rdat__h91426 = hasDebugLogic ? 32'hC0DE0111 : 32'd0 ; - assign rdat__h91456 = hasDebugLogic ? dmaStartTime[31:0] : 32'd0 ; - assign rdat__h91490 = hasDebugLogic ? dmaStartTime[63:32] : 32'd0 ; - assign rdat__h91523 = hasDebugLogic ? dmaDoneTime[31:0] : 32'd0 ; - assign rdat__h91557 = hasDebugLogic ? dmaDoneTime[63:32] : 32'd0 ; - assign rdata__h33850 = - tlp_tlpBRAM_readReq_first__97_BITS_30_TO_29_99_ETC___d2404[1] ? - IF_tlp_tlpBRAM_readReq_first__97_BITS_30_TO_29_ETC___d1037 : - IF_tlp_tlpBRAM_readReq_first__97_BITS_30_TO_29_ETC___d1042 ; - assign rdata__h82127 = - { bram_serverAdapterB_3_outData_outData$wget, - bram_serverAdapterB_2_outData_outData$wget, - bram_serverAdapterB_1_outData_outData$wget, - bram_serverAdapterB_outData_outData$wget } ; - assign rreq_tag__h46309 = - (y__h46119 == tlp_mesgLengthRemainPush) ? 8'h01 : 8'h0 ; - assign rresp_data__h28457 = - { IF_tlp_tlpBRAM_readReq_first__97_BITS_30_TO_29_ETC___d2397[7:0], - IF_tlp_tlpBRAM_readReq_first__97_BITS_30_TO_29_ETC___d2397[15:8], - IF_tlp_tlpBRAM_readReq_first__97_BITS_30_TO_29_ETC___d2397[23:16], - IF_tlp_tlpBRAM_readReq_first__97_BITS_30_TO_29_ETC___d2397[31:24] } ; - assign spanToNextPage__h46093 = 13'd4096 - { 1'd0, tlp_srcMesgAccu[11:0] } ; - assign spanToNextPage__h62253 = 13'd4096 - { 1'd0, tlp_fabMesgAccu[11:0] } ; - assign tag__h62529 = { 3'd0, tlp_dmaTag } ; - assign tagm__h62748 = { 3'd0, tlp_dmaReqTag } ; - assign thisRequestLength__h46094 = - (x__h46132[12:0] <= spanToNextPage__h46093) ? - x__h46132[12:0] : - spanToNextPage__h46093 ; - assign thisRequestLength__h62254 = - (x__h62287[12:0] <= spanToNextPage__h62253) ? - x__h62287[12:0] : - spanToNextPage__h62253 ; - assign tlp_dmaPullRemainDWLen_481_ULE_tlp_dmaPullRema_ETC___d2625 = + assign rdat__h92763 = hasDebugLogic ? tlp_lastMetaV_0 : 32'd0 ; + assign rdat__h92887 = hasDebugLogic ? tlp_lastMetaV_1 : 32'd0 ; + assign rdat__h92915 = hasDebugLogic ? tlp_lastMetaV_2 : 32'd0 ; + assign rdat__h92943 = hasDebugLogic ? tlp_lastMetaV_3 : 32'd0 ; + assign rdat__h92971 = hasDebugLogic ? 32'hC0DE0111 : 32'd0 ; + assign rdat__h93001 = hasDebugLogic ? dmaStartTime[31:0] : 32'd0 ; + assign rdat__h93035 = hasDebugLogic ? dmaStartTime[63:32] : 32'd0 ; + assign rdat__h93068 = hasDebugLogic ? dmaDoneTime[31:0] : 32'd0 ; + assign rdat__h93102 = hasDebugLogic ? dmaDoneTime[63:32] : 32'd0 ; + assign rdata__h35173 = + tlp_tlpBRAM_readReq_first__98_BITS_30_TO_29_00_ETC___d922[1] ? + IF_tlp_tlpBRAM_readReq_first__98_BITS_30_TO_29_ETC___d929 : + IF_tlp_tlpBRAM_readReq_first__98_BITS_30_TO_29_ETC___d934 ; + assign rdata__h83703 = + { bram_3_serverAdapterB_outData_outData$wget, + bram_2_serverAdapterB_outData_outData$wget, + bram_1_serverAdapterB_outData_outData$wget, + bram_0_serverAdapterB_outData_outData$wget } ; + assign rreq_tag__h47719 = + (y__h47529 == tlp_mesgLengthRemainPush) ? 8'h01 : 8'h0 ; + assign rresp_data__h29698 = + { SEL_ARR_bram_0_serverAdapterA_outData_outData__ETC___d863[7:0], + SEL_ARR_bram_0_serverAdapterA_outData_outData__ETC___d863[15:8], + SEL_ARR_bram_0_serverAdapterA_outData_outData__ETC___d863[23:16], + SEL_ARR_bram_0_serverAdapterA_outData_outData__ETC___d863[31:24] } ; + assign spanToNextPage__h47503 = 13'd4096 - { 1'd0, tlp_srcMesgAccu[11:0] } ; + assign spanToNextPage__h63892 = 13'd4096 - { 1'd0, tlp_fabMesgAccu[11:0] } ; + assign tag__h64168 = { 3'd0, tlp_dmaTag } ; + assign tagm__h64387 = { 3'd0, tlp_dmaReqTag } ; + assign thisRequestLength__h47504 = + (x__h47542[12:0] <= spanToNextPage__h47503) ? + x__h47542[12:0] : + spanToNextPage__h47503 ; + assign thisRequestLength__h63893 = + (x__h63926[12:0] <= spanToNextPage__h63892) ? + x__h63926[12:0] : + spanToNextPage__h63892 ; + assign tlp_dmaPullRemainDWLen_373_ULE_tlp_dmaPullRema_ETC___d1395 = tlp_dmaPullRemainDWLen <= tlp_dmaPullRemainDWSub ; - assign tlp_dmaPullRemainDWSub_495_ULE_4___d2626 = + assign tlp_dmaPullRemainDWSub_387_ULE_4___d1388 = tlp_dmaPullRemainDWSub <= 10'd4 ; - assign tlp_inF_first__367_BITS_63_TO_56_370_EQ_pciDev_ETC___d1380 = + assign tlp_inF_first__259_BITS_63_TO_56_262_EQ_pciDev_ETC___d1272 = tlp_inF$D_OUT[63:56] == pciDevice[15:8] && tlp_inF$D_OUT[55:51] == pciDevice[7:3] && tlp_inF$D_OUT[50:48] == pciDevice[2:0] ; - assign tlp_inF_first__367_BIT_152_570_AND_NOT_tlp_inF_ETC___d1595 = + assign tlp_inF_first__259_BIT_152_462_AND_NOT_tlp_inF_ETC___d1487 = tlp_inF$D_OUT[152] && !tlp_inF$D_OUT[110] && !tlp_inF$D_OUT[125] && tlp_inF$D_OUT[124:120] == 5'b0 || !tlp_inF$D_OUT[152] && !tlp_inIgnorePkt ; - assign tlp_mesgLengthRemainPull_PLUS_3__q15 = + assign tlp_mesgLengthRemainPull_PLUS_3__q14 = tlp_mesgLengthRemainPull + 17'd3 ; - assign tlp_mesgLengthRemainPush_PLUS_3__q16 = + assign tlp_mesgLengthRemainPush_PLUS_3__q15 = tlp_mesgLengthRemainPush + 17'd3 ; - assign tlp_outDwRemain_237_ULE_4___d2557 = tlp_outDwRemain <= 10'd4 ; - assign tlp_tlpBRAM_mReqF_first__18_BIT_60_02_OR_IF_tl_ETC___d813 = - tlp_tlpBRAM_mReqF$D_OUT[60] || - CASE_tlp_tlpBRAM_mReqFD_OUT_BITS_30_TO_29_NOT_ETC__q7 ; - assign tlp_tlpBRAM_mReqF_first__18_BIT_63_19_OR_IF_tl_ETC___d634 = - tlp_tlpBRAM_mReqF$D_OUT[63] || - CASE_tlp_tlpBRAM_mReqFD_OUT_BITS_51_TO_50_NOT_ETC__q6 ; - assign tlp_tlpBRAM_mRespF_first__108_BITS_71_TO_62_20_ETC___d2405 = + assign tlp_outDwRemain_129_ULE_4___d1130 = tlp_outDwRemain <= 10'd4 ; + assign tlp_tlpBRAM_mRespF_first__000_BITS_71_TO_62_10_ETC___d1102 = tlp_tlpBRAM_mRespF$D_OUT[71:62] <= 10'd1 ; - assign tlp_tlpBRAM_rdRespDwRemain_024_ULE_4___d1026 = + assign tlp_tlpBRAM_mRespF_i_notFull__97_AND_tlp_tlpBR_ETC___d813 = + tlp_tlpBRAM_mRespF$FULL_N && + (tlp_tlpBRAM_readReq$D_OUT[60] || + CASE_tlp_tlpBRAM_readReq_first__98_BITS_30_TO__ETC___d805 && + CASE_tlp_tlpBRAM_readReq_first__98_BITS_30_TO__ETC___d810) ; + assign tlp_tlpBRAM_rdRespDwRemain_16_ULE_4___d918 = tlp_tlpBRAM_rdRespDwRemain <= 10'd4 ; - assign tlp_tlpBRAM_readNxtDWAddr_PLUS_1__q13 = + assign tlp_tlpBRAM_readNxtDWAddr_PLUS_1__q11 = tlp_tlpBRAM_readNxtDWAddr + 13'd1 ; - assign tlp_tlpBRAM_readNxtDWAddr_PLUS_2__q14 = + assign tlp_tlpBRAM_readNxtDWAddr_PLUS_2__q12 = tlp_tlpBRAM_readNxtDWAddr + 13'd2 ; - assign tlp_tlpBRAM_readNxtDWAddr_PLUS_3__q12 = + assign tlp_tlpBRAM_readNxtDWAddr_PLUS_3__q13 = tlp_tlpBRAM_readNxtDWAddr + 13'd3 ; - assign tlp_tlpBRAM_readRemainDWLen_46_ULE_4___d847 = + assign tlp_tlpBRAM_readRemainDWLen_74_ULE_4___d775 = tlp_tlpBRAM_readRemainDWLen <= 10'd4 ; - assign tlp_tlpBRAM_readReq_first__97_BITS_30_TO_29_99_ETC___d2404 = + assign tlp_tlpBRAM_readReq_first__98_BITS_30_TO_29_00_ETC___d922 = tlp_tlpBRAM_readReq$D_OUT[30:29] + (tlp_tlpBRAM_readReq$D_OUT[60] ? 2'd0 : 2'd1) ; - assign tlp_tlpBRAM_writeDWAddr_PLUS_1__q10 = + assign tlp_tlpBRAM_writeDWAddr_PLUS_1__q8 = tlp_tlpBRAM_writeDWAddr + 13'd1 ; - assign tlp_tlpBRAM_writeDWAddr_PLUS_2__q11 = + assign tlp_tlpBRAM_writeDWAddr_PLUS_2__q9 = tlp_tlpBRAM_writeDWAddr + 13'd2 ; - assign tlp_tlpBRAM_writeDWAddr_PLUS_3__q9 = + assign tlp_tlpBRAM_writeDWAddr_PLUS_3__q10 = tlp_tlpBRAM_writeDWAddr + 13'd3 ; - assign tlp_tlpBRAM_writeRemainDWLen_62_ULE_1___d2402 = - tlp_tlpBRAM_writeRemainDWLen <= 10'd1 ; - assign tlp_tlpBRAM_writeRemainDWLen_62_ULE_2___d2403 = - tlp_tlpBRAM_writeRemainDWLen <= 10'd2 ; - assign tlp_tlpBRAM_writeRemainDWLen_62_ULE_3___d2401 = - tlp_tlpBRAM_writeRemainDWLen <= 10'd3 ; - assign w_be__h47101 = - tlp_outDwRemain_237_ULE_4___d2557 ? - CASE_tlp_outDwRemain_BITS_1_TO_0_0xFFF0_0b0_0x_ETC__q4 : + assign w_be__h48508 = + tlp_outDwRemain_129_ULE_4___d1130 ? + CASE_tlp_outDwRemain_BITS_1_TO_0_0b0_0xFFFF_0b_ETC__q3 : 16'd65535 ; - assign w_data__h46507 = + assign w_data__h47916 = { 22'd1048576, tlp_tlpBRAM_mRespF$D_OUT[71:62], pciDevice, 8'd0, - lastBE__h46542, + lastBE__h47950, 4'd15, tlp_fabMesgAccu, tlp_tlpBRAM_mRespF$D_OUT[31:0] } ; - assign w_data__h46644 = + assign w_data__h48052 = { 22'd1572864, tlp_tlpBRAM_mRespF$D_OUT[71:62], pciDevice, 8'd0, - lastBE__h46542, + lastBE__h47950, 4'd15, tlp_fabMesgAddrMS, tlp_fabMesgAccu } ; - assign w_data__h51409 = + assign w_data__h52877 = { tlp_fabMeta[103:96], tlp_fabMeta[111:104], tlp_fabMeta[119:112], @@ -6735,7 +6756,7 @@ module mkOCDP16B(pciDevice, tlp_fabMeta[15:8], tlp_fabMeta[23:16], tlp_fabMeta[31:24] } ; - assign w_data__h64198 = + assign w_data__h65836 = { 32'd1073741825, pciDevice, 16'd15, @@ -6745,616 +6766,533 @@ module mkOCDP16B(pciDevice, wti_nowReq_BITS_63_TO_0__q2[20:13], wti_nowReq_BITS_63_TO_0__q2[28:21], wti_nowReq_BITS_63_TO_0__q2[36:29] } ; - assign w_data__h65286 = + assign w_data__h66940 = { 32'd1610612737, pciDevice, 16'd15, tlp_fabFlowAddrMS, tlp_fabFlowAddr } ; - assign w_data__h65532 = + assign w_data__h67186 = { wti_nowReq_BITS_63_TO_0__q2[12:6], 1'd1, wti_nowReq_BITS_63_TO_0__q2[20:13], wti_nowReq_BITS_63_TO_0__q2[28:21], wti_nowReq_BITS_63_TO_0__q2[36:29], 96'd0 } ; - assign wmi_wmi_operateD_716_AND_wmi_wmi_peerIsReady_7_ETC___d1887 = + assign wci_respF_cntr_r_90_MINUS_1___d499 = wci_respF_cntr_r - 2'd1 ; + assign wmi_wmi_operateD_606_AND_wmi_wmi_peerIsReady_6_ETC___d1777 = wmi_wmi_operateD && wmi_wmi_peerIsReady && - bram_serverAdapterB_cnt_5_SLT_3___d1776 && - bram_serverAdapterB_1_cnt_03_SLT_3___d1777 && - bram_serverAdapterB_2_cnt_21_SLT_3___d1778 && - bram_serverAdapterB_3_cnt_39_SLT_3___d1779 && + bram_0_serverAdapterB_cnt_5_SLT_3___d1666 && + bram_1_serverAdapterB_cnt_03_SLT_3___d1667 && + bram_2_serverAdapterB_cnt_21_SLT_3___d1668 && + bram_3_serverAdapterB_cnt_39_SLT_3___d1669 && wmi_wmi_mFlagF$EMPTY_N ; - assign wmi_wmi_operateD_716_AND_wmi_wmi_peerIsReady_7_ETC___d1908 = + assign wmi_wmi_operateD_606_AND_wmi_wmi_peerIsReady_6_ETC___d1798 = wmi_wmi_operateD && wmi_wmi_peerIsReady && - (bram_serverAdapterB_outDataCore$EMPTY_N || - bram_serverAdapterB_outData_enqData$whas) && - bram_serverAdapterB_outData_outData_whas__795__ETC___d1807 ; + (bram_0_serverAdapterB_outDataCore$EMPTY_N || + bram_0_serverAdapterB_outData_enqData$whas) && + bram_0_serverAdapterB_outData_outData_whas__68_ETC___d1697 ; + assign wmi_wmi_respF_cntr_r_582_MINUS_1___d1590 = + wmi_wmi_respF_cntr_r - 2'd1 ; assign wti_nowReq_BITS_63_TO_0__q2 = wti_nowReq[63:0] ; - assign x3__h80237 = { 8'd0, wmi_wmi_mFlagF$D_OUT[23:0] } ; - assign x__h28530 = x__h28532 - y__h28533 ; - assign x__h28532 = { tlp_tlpBRAM_readReq$D_OUT[28:19], 2'b0 } ; - assign x__h40887 = + assign x3__h81813 = { 8'd0, wmi_wmi_mFlagF$D_OUT[23:0] } ; + assign x__h29771 = x__h29773 - y__h29774 ; + assign x__h29773 = { tlp_tlpBRAM_readReq$D_OUT[28:19], 2'b0 } ; + assign x__h42208 = { tlp_tlpBRAM_mRespF$D_OUT[7:0], tlp_tlpBRAM_mRespF$D_OUT[15:8], tlp_tlpBRAM_mRespF$D_OUT[23:16], tlp_tlpBRAM_mRespF$D_OUT[31:24] } ; - assign x__h45847 = { 15'd0, tlp_mesgLengthRemainPush } ; - assign x__h46132 = - (tlp_mesgLengthRemainPush <= y__h46134) ? + assign x__h47258 = { 15'd0, tlp_mesgLengthRemainPush } ; + assign x__h47542 = + (tlp_mesgLengthRemainPush <= y__h47544) ? tlp_mesgLengthRemainPush : - y__h46134 ; - assign x__h56804 = + y__h47544 ; + assign x__h58352 = { tlp_inF$D_OUT[7:0], tlp_inF$D_OUT[15:8], tlp_inF$D_OUT[23:16], tlp_inF$D_OUT[31:24] } ; - assign x__h61968 = { 15'd0, tlp_mesgLengthRemainPull } ; - assign x__h62287 = - (tlp_mesgLengthRemainPull <= y__h62289) ? + assign x__h63608 = { 15'd0, tlp_mesgLengthRemainPull } ; + assign x__h63926 = + (tlp_mesgLengthRemainPull <= y__h63928) ? tlp_mesgLengthRemainPull : - y__h62289 ; - assign x__h87138 = (dpControl[1:0] == 2'd1) ? bml_fabNumBufs : 16'd0 ; - assign x__h88266 = bml_lclBufsAR + 16'd1 ; - assign x__h88271 = bml_lclBufsAR - 16'd1 ; - assign x__h88378 = bml_lclBufsCF + 16'd1 ; - assign x__h88415 = bml_lclBufsCF - 16'd1 ; - assign x__h88497 = bml_fabBufsAvail + 16'd1 ; - assign x__h88502 = bml_fabBufsAvail - 16'd1 ; - assign x__h88536 = bml_lclCredit + 16'd1 ; - assign x__h88541 = bml_lclCredit - 16'd1 ; - assign y__h17488 = tlp_tlpBRAM_mReqF$D_OUT[63] ? 13'd0 : 13'd1 ; - assign y__h17555 = tlp_tlpBRAM_mReqF$D_OUT[63] ? 10'd0 : 10'd1 ; - assign y__h26037 = tlp_tlpBRAM_mReqF$D_OUT[60] ? 10'd0 : 10'd1 ; - assign y__h26049 = tlp_tlpBRAM_mReqF$D_OUT[60] ? 13'd0 : 13'd1 ; - assign y__h28531 = + y__h63928 ; + assign x__h88675 = (dpControl[1:0] == 2'd1) ? bml_fabNumBufs : 16'd0 ; + assign x__h89803 = bml_lclBufsAR + 16'd1 ; + assign x__h89808 = bml_lclBufsAR - 16'd1 ; + assign x__h89915 = bml_lclBufsCF + 16'd1 ; + assign x__h89952 = bml_lclBufsCF - 16'd1 ; + assign x__h90034 = bml_fabBufsAvail + 16'd1 ; + assign x__h90039 = bml_fabBufsAvail - 16'd1 ; + assign x__h90073 = bml_lclCredit + 16'd1 ; + assign x__h90078 = bml_lclCredit - 16'd1 ; + assign y__h17362 = tlp_tlpBRAM_mReqF$D_OUT[63] ? 13'd0 : 13'd1 ; + assign y__h17428 = tlp_tlpBRAM_mReqF$D_OUT[63] ? 10'd0 : 10'd1 ; + assign y__h27653 = tlp_tlpBRAM_mReqF$D_OUT[60] ? 10'd0 : 10'd1 ; + assign y__h27665 = tlp_tlpBRAM_mReqF$D_OUT[60] ? 13'd0 : 13'd1 ; + assign y__h29772 = (tlp_tlpBRAM_readReq$D_OUT[28:19] == 10'd1) ? 12'd0 : - { 10'd0, x__h28562 } ; - assign y__h28533 = { 10'd0, x__h28539 } ; - assign y__h29472 = tlp_tlpBRAM_readReq$D_OUT[60] ? 10'd0 : 10'd1 ; - assign y__h46119 = { 4'd0, thisRequestLength__h46094 } ; - assign y__h46134 = { 4'd0, tlp_maxPayloadSize } ; - assign y__h46213 = { 19'd0, thisRequestLength__h46094 } ; - assign y__h46261 = { 3'd0, thisRequestLength__h46094 } ; - assign y__h46739 = (tlp_fabMesgAddrMS == 32'd0) ? 10'd1 : 10'd0 ; - assign y__h46773 = { 20'd0, tlp_tlpBRAM_mRespF$D_OUT[71:62], 2'd0 } ; - assign y__h62279 = { 4'd0, thisRequestLength__h62254 } ; - assign y__h62289 = { 4'd0, tlp_maxReadReqSize } ; - assign y__h62350 = { 19'd0, thisRequestLength__h62254 } ; - assign y__h62959 = { 4'd0, tlp_inF$D_OUT[105:96], 2'd0 } ; - assign y__h63671 = - tlp_dmaPullRemainDWSub_495_ULE_4___d2626 ? + { 10'd0, x__h29803 } ; + assign y__h29774 = { 10'd0, x__h29780 } ; + assign y__h30729 = tlp_tlpBRAM_readReq$D_OUT[60] ? 10'd0 : 10'd1 ; + assign y__h47529 = { 4'd0, thisRequestLength__h47504 } ; + assign y__h47544 = { 4'd0, tlp_maxPayloadSize } ; + assign y__h47623 = { 19'd0, thisRequestLength__h47504 } ; + assign y__h47671 = { 3'd0, thisRequestLength__h47504 } ; + assign y__h48147 = (tlp_fabMesgAddrMS == 32'd0) ? 10'd1 : 10'd0 ; + assign y__h48181 = { 20'd0, tlp_tlpBRAM_mRespF$D_OUT[71:62], 2'd0 } ; + assign y__h63918 = { 4'd0, thisRequestLength__h63893 } ; + assign y__h63928 = { 4'd0, tlp_maxReadReqSize } ; + assign y__h63989 = { 19'd0, thisRequestLength__h63893 } ; + assign y__h64598 = { 4'd0, tlp_inF$D_OUT[105:96], 2'd0 } ; + assign y__h65310 = + tlp_dmaPullRemainDWSub_387_ULE_4___d1388 ? { 5'd0, tlp_dmaPullRemainDWSub, 2'd0 } : 17'd16 ; always@(tlp_tlpBRAM_readReq$D_OUT) begin case (tlp_tlpBRAM_readReq$D_OUT[18:15]) - 4'b1100: x__h28539 = 2'b10; - 4'b1110: x__h28539 = 2'b01; - 4'b1111: x__h28539 = 2'b0; - default: x__h28539 = 2'b11; + 4'b1100: x__h29780 = 2'b10; + 4'b1110: x__h29780 = 2'b01; + 4'b1111: x__h29780 = 2'b0; + default: x__h29780 = 2'b11; endcase end always@(tlp_tlpBRAM_readReq$D_OUT) begin case (tlp_tlpBRAM_readReq$D_OUT[14:11]) - 4'b1100: x__h28562 = 2'b10; - 4'b1110: x__h28562 = 2'b01; - 4'b1111: x__h28562 = 2'b0; - default: x__h28562 = 2'b11; + 4'b1100: x__h29803 = 2'b10; + 4'b1110: x__h29803 = 2'b01; + 4'b1111: x__h29803 = 2'b0; + default: x__h29803 = 2'b11; endcase end always@(tlp_lastRuleFired) begin case (tlp_lastRuleFired) 4'd1, 4'd2, 4'd3, 4'd4, 4'd5, 4'd6, 4'd7, 4'd8, 4'd9, 4'd15: - CASE_tlp_lastRuleFired_10_1_tlp_lastRuleFired__ETC__q1 = + CASE_tlp_lastRuleFired_1_tlp_lastRuleFired_2_t_ETC__q1 = tlp_lastRuleFired; - default: CASE_tlp_lastRuleFired_10_1_tlp_lastRuleFired__ETC__q1 = 4'd10; + default: CASE_tlp_lastRuleFired_1_tlp_lastRuleFired_2_t_ETC__q1 = 4'd10; endcase end always@(wci_reqF$D_OUT or - rdat__h90489 or - rdat__h90497 or - rdat__h90505 or - rdat__h90513 or - rdat__h90521 or - rdat__h90529 or - rdat__h90537 or - rdat__h90558 or - rdat__h90565 or - rdat__h90578 or - rdat__h90585 or - rdat__h90592 or - rdat__h90856 or - rdat__h90906 or - rdat__h91006 or + rdat__h92026 or + rdat__h92034 or + rdat__h92042 or + rdat__h92050 or + rdat__h92058 or + rdat__h92066 or + rdat__h92074 or + rdat__h92095 or + rdat__h92102 or + rdat__h92115 or + rdat__h92122 or + rdat__h92129 or + rdat__h92401 or + rdat__h92451 or + rdat__h92551 or bml_fabMesgBase or bml_fabMetaBase or bml_fabMesgSize or bml_fabMetaSize or bml_fabFlowBase or bml_fabFlowSize or - rdat__h91064 or - rdat__h91086 or - rdat__h91096 or - rdat__h91218 or - rdat__h91339 or - rdat__h91368 or - rdat__h91397 or - rdat__h91426 or + rdat__h92609 or + rdat__h92631 or + rdat__h92641 or + rdat__h92763 or + rdat__h92887 or + rdat__h92915 or + rdat__h92943 or + rdat__h92971 or bml_fabMesgBaseMS or bml_fabMetaBaseMS or bml_fabFlowBaseMS or - rdat__h91456 or rdat__h91490 or rdat__h91523 or rdat__h91557) + rdat__h93001 or rdat__h93035 or rdat__h93068 or rdat__h93102) begin case (wci_reqF$D_OUT[39:32]) - 8'h0: _theResult____h90410 = rdat__h90489; - 8'h04: _theResult____h90410 = rdat__h90497; - 8'h08: _theResult____h90410 = rdat__h90505; - 8'h0C: _theResult____h90410 = rdat__h90513; - 8'h10: _theResult____h90410 = rdat__h90521; - 8'h14: _theResult____h90410 = rdat__h90529; - 8'h20: _theResult____h90410 = rdat__h90537; - 8'h24: _theResult____h90410 = 32'hF00DFACE; - 8'h28: _theResult____h90410 = rdat__h90558; - 8'h2C: _theResult____h90410 = rdat__h90565; - 8'h30: _theResult____h90410 = rdat__h90578; - 8'h34: _theResult____h90410 = rdat__h90585; - 8'h38: _theResult____h90410 = rdat__h90592; - 8'h3C: _theResult____h90410 = rdat__h90856; - 8'h40: _theResult____h90410 = rdat__h90906; - 8'h44: _theResult____h90410 = 32'd0; - 8'h48: _theResult____h90410 = rdat__h91006; - 8'h4C: _theResult____h90410 = 32'h00008000; - 8'h50: _theResult____h90410 = bml_fabMesgBase; - 8'h54: _theResult____h90410 = bml_fabMetaBase; - 8'h58: _theResult____h90410 = bml_fabMesgSize; - 8'h5C: _theResult____h90410 = bml_fabMetaSize; - 8'h60: _theResult____h90410 = bml_fabFlowBase; - 8'h64: _theResult____h90410 = bml_fabFlowSize; - 8'h68: _theResult____h90410 = rdat__h91064; - 8'h6C: _theResult____h90410 = rdat__h91086; - 8'h70: _theResult____h90410 = rdat__h91096; - 8'h80: _theResult____h90410 = rdat__h91218; - 8'h84: _theResult____h90410 = rdat__h91339; - 8'h88: _theResult____h90410 = rdat__h91368; - 8'h8C: _theResult____h90410 = rdat__h91397; - 8'h90: _theResult____h90410 = rdat__h91426; - 8'h94: _theResult____h90410 = bml_fabMesgBaseMS; - 8'h98: _theResult____h90410 = bml_fabMetaBaseMS; - 8'h9C: _theResult____h90410 = bml_fabFlowBaseMS; - 8'hA0: _theResult____h90410 = rdat__h91456; - 8'hA4: _theResult____h90410 = rdat__h91490; - 8'hA8: _theResult____h90410 = rdat__h91523; - 8'hAC: _theResult____h90410 = rdat__h91557; - default: _theResult____h90410 = 32'd0; + 8'h0: _theResult____h91947 = rdat__h92026; + 8'h04: _theResult____h91947 = rdat__h92034; + 8'h08: _theResult____h91947 = rdat__h92042; + 8'h0C: _theResult____h91947 = rdat__h92050; + 8'h10: _theResult____h91947 = rdat__h92058; + 8'h14: _theResult____h91947 = rdat__h92066; + 8'h20: _theResult____h91947 = rdat__h92074; + 8'h24: _theResult____h91947 = 32'hF00DFACE; + 8'h28: _theResult____h91947 = rdat__h92095; + 8'h2C: _theResult____h91947 = rdat__h92102; + 8'h30: _theResult____h91947 = rdat__h92115; + 8'h34: _theResult____h91947 = rdat__h92122; + 8'h38: _theResult____h91947 = rdat__h92129; + 8'h3C: _theResult____h91947 = rdat__h92401; + 8'h40: _theResult____h91947 = rdat__h92451; + 8'h44: _theResult____h91947 = 32'd0; + 8'h48: _theResult____h91947 = rdat__h92551; + 8'h4C: _theResult____h91947 = 32'h00008000; + 8'h50: _theResult____h91947 = bml_fabMesgBase; + 8'h54: _theResult____h91947 = bml_fabMetaBase; + 8'h58: _theResult____h91947 = bml_fabMesgSize; + 8'h5C: _theResult____h91947 = bml_fabMetaSize; + 8'h60: _theResult____h91947 = bml_fabFlowBase; + 8'h64: _theResult____h91947 = bml_fabFlowSize; + 8'h68: _theResult____h91947 = rdat__h92609; + 8'h6C: _theResult____h91947 = rdat__h92631; + 8'h70: _theResult____h91947 = rdat__h92641; + 8'h80: _theResult____h91947 = rdat__h92763; + 8'h84: _theResult____h91947 = rdat__h92887; + 8'h88: _theResult____h91947 = rdat__h92915; + 8'h8C: _theResult____h91947 = rdat__h92943; + 8'h90: _theResult____h91947 = rdat__h92971; + 8'h94: _theResult____h91947 = bml_fabMesgBaseMS; + 8'h98: _theResult____h91947 = bml_fabMetaBaseMS; + 8'h9C: _theResult____h91947 = bml_fabFlowBaseMS; + 8'hA0: _theResult____h91947 = rdat__h93001; + 8'hA4: _theResult____h91947 = rdat__h93035; + 8'hA8: _theResult____h91947 = rdat__h93068; + 8'hAC: _theResult____h91947 = rdat__h93102; + default: _theResult____h91947 = 32'd0; endcase end always@(tlp_tlpBRAM_readReq$D_OUT) begin case (tlp_tlpBRAM_readReq$D_OUT[18:15]) - 4'b1000: lowAddr10__h28410 = 2'b11; - 4'b1100: lowAddr10__h28410 = 2'b10; - 4'b1110: lowAddr10__h28410 = 2'b01; - default: lowAddr10__h28410 = 2'b0; - endcase - end - always@(dpControl or bml_fabDone or bml_remDone) - begin - case (dpControl[1:0]) - 2'd0: - IF_bml_dpControl_wget__008_BITS_1_TO_0_014_EQ__ETC___d2085 = - bml_fabDone; - 2'd1: - IF_bml_dpControl_wget__008_BITS_1_TO_0_014_EQ__ETC___d2085 = - bml_remDone; - default: IF_bml_dpControl_wget__008_BITS_1_TO_0_014_EQ__ETC___d2085 = - bml_fabDone; - endcase - end - always@(dpControl or bml_fabDone or bml_remDone or bml_remStart) - begin - case (dpControl[1:0]) - 2'd0: - CASE_dpControl_BITS_1_TO_0_bml_fabDone_0_bml_f_ETC__q3 = - bml_fabDone; - 2'd1: - CASE_dpControl_BITS_1_TO_0_bml_fabDone_0_bml_f_ETC__q3 = - (dpControl[3:2] == 2'd1) ? bml_remDone : bml_remStart; - default: CASE_dpControl_BITS_1_TO_0_bml_fabDone_0_bml_f_ETC__q3 = - bml_fabDone; - endcase - end - always@(tlp_outDwRemain) - begin - case (tlp_outDwRemain[1:0]) - 2'b0: CASE_tlp_outDwRemain_BITS_1_TO_0_0xFFF0_0b0_0x_ETC__q4 = 16'hFFFF; - 2'b01: - CASE_tlp_outDwRemain_BITS_1_TO_0_0xFFF0_0b0_0x_ETC__q4 = 16'hF000; - 2'b10: - CASE_tlp_outDwRemain_BITS_1_TO_0_0xFFF0_0b0_0x_ETC__q4 = 16'hFF00; - 2'd3: CASE_tlp_outDwRemain_BITS_1_TO_0_0xFFF0_0b0_0x_ETC__q4 = 16'hFFF0; - endcase - end - always@(idx__h19187 or - tlp_tlpBRAM_writeRemainDWLen_62_ULE_3___d2401 or - tlp_tlpBRAM_writeRemainDWLen or - tlp_tlpBRAM_writeRemainDWLen_62_ULE_1___d2402 or - tlp_tlpBRAM_writeRemainDWLen_62_ULE_2___d2403) - begin - case (idx__h19187) - 2'd0: - IF_0_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d675 = - tlp_tlpBRAM_writeRemainDWLen == 10'd0; - 2'd1: - IF_0_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d675 = - tlp_tlpBRAM_writeRemainDWLen_62_ULE_1___d2402; - 2'd2: - IF_0_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d675 = - tlp_tlpBRAM_writeRemainDWLen_62_ULE_2___d2403; - 2'd3: - IF_0_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d675 = - tlp_tlpBRAM_writeRemainDWLen_62_ULE_3___d2401; - endcase - end - always@(idx__h21418 or - tlp_tlpBRAM_writeRemainDWLen_62_ULE_3___d2401 or - tlp_tlpBRAM_writeRemainDWLen or - tlp_tlpBRAM_writeRemainDWLen_62_ULE_1___d2402 or - tlp_tlpBRAM_writeRemainDWLen_62_ULE_2___d2403) - begin - case (idx__h21418) - 2'd0: - IF_1_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d685 = - tlp_tlpBRAM_writeRemainDWLen == 10'd0; - 2'd1: - IF_1_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d685 = - tlp_tlpBRAM_writeRemainDWLen_62_ULE_1___d2402; - 2'd2: - IF_1_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d685 = - tlp_tlpBRAM_writeRemainDWLen_62_ULE_2___d2403; - 2'd3: - IF_1_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d685 = - tlp_tlpBRAM_writeRemainDWLen_62_ULE_3___d2401; - endcase - end - always@(idx__h22722 or - tlp_tlpBRAM_writeRemainDWLen_62_ULE_3___d2401 or - tlp_tlpBRAM_writeRemainDWLen or - tlp_tlpBRAM_writeRemainDWLen_62_ULE_1___d2402 or - tlp_tlpBRAM_writeRemainDWLen_62_ULE_2___d2403) - begin - case (idx__h22722) - 2'd0: - IF_2_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d695 = - tlp_tlpBRAM_writeRemainDWLen == 10'd0; - 2'd1: - IF_2_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d695 = - tlp_tlpBRAM_writeRemainDWLen_62_ULE_1___d2402; - 2'd2: - IF_2_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d695 = - tlp_tlpBRAM_writeRemainDWLen_62_ULE_2___d2403; - 2'd3: - IF_2_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d695 = - tlp_tlpBRAM_writeRemainDWLen_62_ULE_3___d2401; - endcase - end - always@(idx__h24026 or - tlp_tlpBRAM_writeRemainDWLen_62_ULE_3___d2401 or - tlp_tlpBRAM_writeRemainDWLen or - tlp_tlpBRAM_writeRemainDWLen_62_ULE_1___d2402 or - tlp_tlpBRAM_writeRemainDWLen_62_ULE_2___d2403) - begin - case (idx__h24026) - 2'd0: - IF_3_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d705 = - tlp_tlpBRAM_writeRemainDWLen == 10'd0; - 2'd1: - IF_3_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d705 = - tlp_tlpBRAM_writeRemainDWLen_62_ULE_1___d2402; - 2'd2: - IF_3_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d705 = - tlp_tlpBRAM_writeRemainDWLen_62_ULE_2___d2403; - 2'd3: - IF_3_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d705 = - tlp_tlpBRAM_writeRemainDWLen_62_ULE_3___d2401; - endcase - end - always@(dpControl or bml_fabDone or bml_remDone or bml_remStart) - begin - case (dpControl[1:0]) - 2'd0: - CASE_dpControl_BITS_1_TO_0_NOT_bml_fabDone_0_N_ETC__q5 = - !bml_fabDone; - 2'd1: - CASE_dpControl_BITS_1_TO_0_NOT_bml_fabDone_0_N_ETC__q5 = - (dpControl[3:2] == 2'd1) ? !bml_remDone : !bml_remStart; - default: CASE_dpControl_BITS_1_TO_0_NOT_bml_fabDone_0_N_ETC__q5 = - !bml_fabDone; + 4'b1000: lowAddr10__h29651 = 2'b11; + 4'b1100: lowAddr10__h29651 = 2'b10; + 4'b1110: lowAddr10__h29651 = 2'b01; + default: lowAddr10__h29651 = 2'b0; endcase end always@(tlp_tlpBRAM_mReqF$D_OUT or - bram_serverAdapterA_3_cnt_80_SLT_3___d2631 or - bram_serverAdapterA_cnt_6_SLT_3___d2628 or - bram_serverAdapterA_1_cnt_44_SLT_3___d2629 or - bram_serverAdapterA_2_cnt_62_SLT_3___d2630) + bram_0_serverAdapterA_cnt_6_SLT_3___d619 or + bram_1_serverAdapterA_cnt_44_SLT_3___d620 or + bram_2_serverAdapterA_cnt_62_SLT_3___d621 or + bram_3_serverAdapterA_cnt_80_SLT_3___d622) begin case (tlp_tlpBRAM_mReqF$D_OUT[51:50]) 2'd0: - CASE_tlp_tlpBRAM_mReqFD_OUT_BITS_51_TO_50_NOT_ETC__q6 = - bram_serverAdapterA_cnt_6_SLT_3___d2628; + CASE_tlp_tlpBRAM_mReqF_first__16_BITS_51_TO_50_ETC___d623 = + bram_0_serverAdapterA_cnt_6_SLT_3___d619; 2'd1: - CASE_tlp_tlpBRAM_mReqFD_OUT_BITS_51_TO_50_NOT_ETC__q6 = - bram_serverAdapterA_1_cnt_44_SLT_3___d2629; + CASE_tlp_tlpBRAM_mReqF_first__16_BITS_51_TO_50_ETC___d623 = + bram_1_serverAdapterA_cnt_44_SLT_3___d620; 2'd2: - CASE_tlp_tlpBRAM_mReqFD_OUT_BITS_51_TO_50_NOT_ETC__q6 = - bram_serverAdapterA_2_cnt_62_SLT_3___d2630; + CASE_tlp_tlpBRAM_mReqF_first__16_BITS_51_TO_50_ETC___d623 = + bram_2_serverAdapterA_cnt_62_SLT_3___d621; 2'd3: - CASE_tlp_tlpBRAM_mReqFD_OUT_BITS_51_TO_50_NOT_ETC__q6 = - tlp_tlpBRAM_mReqF$D_OUT[51:50] != 2'd3 || - bram_serverAdapterA_3_cnt_80_SLT_3___d2631; + CASE_tlp_tlpBRAM_mReqF_first__16_BITS_51_TO_50_ETC___d623 = + bram_3_serverAdapterA_cnt_80_SLT_3___d622; endcase end - always@(tlp_tlpBRAM_mReqF$D_OUT or - bram_serverAdapterA_3_cnt_80_SLT_3___d2631 or - bram_serverAdapterA_cnt_6_SLT_3___d2628 or - bram_serverAdapterA_1_cnt_44_SLT_3___d2629 or - bram_serverAdapterA_2_cnt_62_SLT_3___d2630) + always@(idx__h21626 or + tlp_tlpBRAM_writeRemainDWLen or + NOT_tlp_tlpBRAM_writeRemainDWLen_52_ULE_1_55___d656 or + NOT_tlp_tlpBRAM_writeRemainDWLen_52_ULE_2_57___d658 or + NOT_tlp_tlpBRAM_writeRemainDWLen_52_ULE_3_59___d660) begin - case (tlp_tlpBRAM_mReqF$D_OUT[30:29]) + case (idx__h21626) 2'd0: - CASE_tlp_tlpBRAM_mReqFD_OUT_BITS_30_TO_29_NOT_ETC__q7 = - bram_serverAdapterA_cnt_6_SLT_3___d2628; + SEL_ARR_NOT_tlp_tlpBRAM_writeRemainDWLen_52_EQ_ETC___d665 = + tlp_tlpBRAM_writeRemainDWLen != 10'd0; 2'd1: - CASE_tlp_tlpBRAM_mReqFD_OUT_BITS_30_TO_29_NOT_ETC__q7 = - bram_serverAdapterA_1_cnt_44_SLT_3___d2629; + SEL_ARR_NOT_tlp_tlpBRAM_writeRemainDWLen_52_EQ_ETC___d665 = + NOT_tlp_tlpBRAM_writeRemainDWLen_52_ULE_1_55___d656; 2'd2: - CASE_tlp_tlpBRAM_mReqFD_OUT_BITS_30_TO_29_NOT_ETC__q7 = - bram_serverAdapterA_2_cnt_62_SLT_3___d2630; + SEL_ARR_NOT_tlp_tlpBRAM_writeRemainDWLen_52_EQ_ETC___d665 = + NOT_tlp_tlpBRAM_writeRemainDWLen_52_ULE_2_57___d658; 2'd3: - CASE_tlp_tlpBRAM_mReqFD_OUT_BITS_30_TO_29_NOT_ETC__q7 = - tlp_tlpBRAM_mReqF$D_OUT[30:29] != 2'd3 || - bram_serverAdapterA_3_cnt_80_SLT_3___d2631; + SEL_ARR_NOT_tlp_tlpBRAM_writeRemainDWLen_52_EQ_ETC___d665 = + NOT_tlp_tlpBRAM_writeRemainDWLen_52_ULE_3_59___d660; endcase end - always@(idx__h19187 or - tlp_tlpBRAM_writeRemainDWLen_62_ULE_3___d2401 or + always@(idx__h23676 or tlp_tlpBRAM_writeRemainDWLen or - tlp_tlpBRAM_writeRemainDWLen_62_ULE_1___d2402 or - tlp_tlpBRAM_writeRemainDWLen_62_ULE_2___d2403) + NOT_tlp_tlpBRAM_writeRemainDWLen_52_ULE_1_55___d656 or + NOT_tlp_tlpBRAM_writeRemainDWLen_52_ULE_2_57___d658 or + NOT_tlp_tlpBRAM_writeRemainDWLen_52_ULE_3_59___d660) begin - case (idx__h19187) + case (idx__h23676) 2'd0: - IF_0_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2431 = + SEL_ARR_NOT_tlp_tlpBRAM_writeRemainDWLen_52_EQ_ETC___d669 = tlp_tlpBRAM_writeRemainDWLen != 10'd0; 2'd1: - IF_0_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2431 = - !tlp_tlpBRAM_writeRemainDWLen_62_ULE_1___d2402; + SEL_ARR_NOT_tlp_tlpBRAM_writeRemainDWLen_52_EQ_ETC___d669 = + NOT_tlp_tlpBRAM_writeRemainDWLen_52_ULE_1_55___d656; 2'd2: - IF_0_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2431 = - !tlp_tlpBRAM_writeRemainDWLen_62_ULE_2___d2403; + SEL_ARR_NOT_tlp_tlpBRAM_writeRemainDWLen_52_EQ_ETC___d669 = + NOT_tlp_tlpBRAM_writeRemainDWLen_52_ULE_2_57___d658; 2'd3: - IF_0_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2431 = - !tlp_tlpBRAM_writeRemainDWLen_62_ULE_3___d2401; + SEL_ARR_NOT_tlp_tlpBRAM_writeRemainDWLen_52_EQ_ETC___d669 = + NOT_tlp_tlpBRAM_writeRemainDWLen_52_ULE_3_59___d660; endcase end - always@(idx__h21418 or - tlp_tlpBRAM_writeRemainDWLen_62_ULE_3___d2401 or + always@(idx__h24781 or tlp_tlpBRAM_writeRemainDWLen or - tlp_tlpBRAM_writeRemainDWLen_62_ULE_1___d2402 or - tlp_tlpBRAM_writeRemainDWLen_62_ULE_2___d2403) + NOT_tlp_tlpBRAM_writeRemainDWLen_52_ULE_1_55___d656 or + NOT_tlp_tlpBRAM_writeRemainDWLen_52_ULE_2_57___d658 or + NOT_tlp_tlpBRAM_writeRemainDWLen_52_ULE_3_59___d660) begin - case (idx__h21418) + case (idx__h24781) 2'd0: - IF_1_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2432 = + SEL_ARR_NOT_tlp_tlpBRAM_writeRemainDWLen_52_EQ_ETC___d673 = tlp_tlpBRAM_writeRemainDWLen != 10'd0; 2'd1: - IF_1_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2432 = - !tlp_tlpBRAM_writeRemainDWLen_62_ULE_1___d2402; + SEL_ARR_NOT_tlp_tlpBRAM_writeRemainDWLen_52_EQ_ETC___d673 = + NOT_tlp_tlpBRAM_writeRemainDWLen_52_ULE_1_55___d656; 2'd2: - IF_1_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2432 = - !tlp_tlpBRAM_writeRemainDWLen_62_ULE_2___d2403; + SEL_ARR_NOT_tlp_tlpBRAM_writeRemainDWLen_52_EQ_ETC___d673 = + NOT_tlp_tlpBRAM_writeRemainDWLen_52_ULE_2_57___d658; 2'd3: - IF_1_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2432 = - !tlp_tlpBRAM_writeRemainDWLen_62_ULE_3___d2401; + SEL_ARR_NOT_tlp_tlpBRAM_writeRemainDWLen_52_EQ_ETC___d673 = + NOT_tlp_tlpBRAM_writeRemainDWLen_52_ULE_3_59___d660; endcase end - always@(idx__h22722 or - tlp_tlpBRAM_writeRemainDWLen_62_ULE_3___d2401 or + always@(idx__h25886 or tlp_tlpBRAM_writeRemainDWLen or - tlp_tlpBRAM_writeRemainDWLen_62_ULE_1___d2402 or - tlp_tlpBRAM_writeRemainDWLen_62_ULE_2___d2403) + NOT_tlp_tlpBRAM_writeRemainDWLen_52_ULE_1_55___d656 or + NOT_tlp_tlpBRAM_writeRemainDWLen_52_ULE_2_57___d658 or + NOT_tlp_tlpBRAM_writeRemainDWLen_52_ULE_3_59___d660) begin - case (idx__h22722) + case (idx__h25886) 2'd0: - IF_2_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2433 = + SEL_ARR_NOT_tlp_tlpBRAM_writeRemainDWLen_52_EQ_ETC___d677 = tlp_tlpBRAM_writeRemainDWLen != 10'd0; 2'd1: - IF_2_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2433 = - !tlp_tlpBRAM_writeRemainDWLen_62_ULE_1___d2402; + SEL_ARR_NOT_tlp_tlpBRAM_writeRemainDWLen_52_EQ_ETC___d677 = + NOT_tlp_tlpBRAM_writeRemainDWLen_52_ULE_1_55___d656; 2'd2: - IF_2_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2433 = - !tlp_tlpBRAM_writeRemainDWLen_62_ULE_2___d2403; + SEL_ARR_NOT_tlp_tlpBRAM_writeRemainDWLen_52_EQ_ETC___d677 = + NOT_tlp_tlpBRAM_writeRemainDWLen_52_ULE_2_57___d658; 2'd3: - IF_2_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2433 = - !tlp_tlpBRAM_writeRemainDWLen_62_ULE_3___d2401; + SEL_ARR_NOT_tlp_tlpBRAM_writeRemainDWLen_52_EQ_ETC___d677 = + NOT_tlp_tlpBRAM_writeRemainDWLen_52_ULE_3_59___d660; endcase end - always@(idx__h24026 or - tlp_tlpBRAM_writeRemainDWLen_62_ULE_3___d2401 or - tlp_tlpBRAM_writeRemainDWLen or - tlp_tlpBRAM_writeRemainDWLen_62_ULE_1___d2402 or - tlp_tlpBRAM_writeRemainDWLen_62_ULE_2___d2403) + always@(idx__h21626 or tlp_tlpBRAM_mReqF$D_OUT) begin - case (idx__h24026) + case (idx__h21626) 2'd0: - IF_3_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2434 = - tlp_tlpBRAM_writeRemainDWLen != 10'd0; + SEL_ARR_tlp_tlpBRAM_mReqF_first__16_BITS_127_T_ETC___d700 = + tlp_tlpBRAM_mReqF$D_OUT[127:96]; 2'd1: - IF_3_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2434 = - !tlp_tlpBRAM_writeRemainDWLen_62_ULE_1___d2402; + SEL_ARR_tlp_tlpBRAM_mReqF_first__16_BITS_127_T_ETC___d700 = + tlp_tlpBRAM_mReqF$D_OUT[95:64]; 2'd2: - IF_3_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2434 = - !tlp_tlpBRAM_writeRemainDWLen_62_ULE_2___d2403; + SEL_ARR_tlp_tlpBRAM_mReqF_first__16_BITS_127_T_ETC___d700 = + tlp_tlpBRAM_mReqF$D_OUT[63:32]; 2'd3: - IF_3_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2434 = - !tlp_tlpBRAM_writeRemainDWLen_62_ULE_3___d2401; + SEL_ARR_tlp_tlpBRAM_mReqF_first__16_BITS_127_T_ETC___d700 = + tlp_tlpBRAM_mReqF$D_OUT[31:0]; endcase end - always@(idx__h19187 or tlp_tlpBRAM_mReqF$D_OUT) + always@(idx__h23676 or tlp_tlpBRAM_mReqF$D_OUT) begin - case (idx__h19187) + case (idx__h23676) 2'd0: - IF_0_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2477 = + SEL_ARR_tlp_tlpBRAM_mReqF_first__16_BITS_127_T_ETC___d708 = tlp_tlpBRAM_mReqF$D_OUT[127:96]; 2'd1: - IF_0_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2477 = + SEL_ARR_tlp_tlpBRAM_mReqF_first__16_BITS_127_T_ETC___d708 = tlp_tlpBRAM_mReqF$D_OUT[95:64]; 2'd2: - IF_0_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2477 = + SEL_ARR_tlp_tlpBRAM_mReqF_first__16_BITS_127_T_ETC___d708 = tlp_tlpBRAM_mReqF$D_OUT[63:32]; 2'd3: - IF_0_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2477 = + SEL_ARR_tlp_tlpBRAM_mReqF_first__16_BITS_127_T_ETC___d708 = tlp_tlpBRAM_mReqF$D_OUT[31:0]; endcase end - always@(idx__h21418 or tlp_tlpBRAM_mReqF$D_OUT) + always@(idx__h24781 or tlp_tlpBRAM_mReqF$D_OUT) begin - case (idx__h21418) + case (idx__h24781) 2'd0: - IF_1_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2478 = + SEL_ARR_tlp_tlpBRAM_mReqF_first__16_BITS_127_T_ETC___d716 = tlp_tlpBRAM_mReqF$D_OUT[127:96]; 2'd1: - IF_1_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2478 = + SEL_ARR_tlp_tlpBRAM_mReqF_first__16_BITS_127_T_ETC___d716 = tlp_tlpBRAM_mReqF$D_OUT[95:64]; 2'd2: - IF_1_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2478 = + SEL_ARR_tlp_tlpBRAM_mReqF_first__16_BITS_127_T_ETC___d716 = tlp_tlpBRAM_mReqF$D_OUT[63:32]; 2'd3: - IF_1_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2478 = + SEL_ARR_tlp_tlpBRAM_mReqF_first__16_BITS_127_T_ETC___d716 = tlp_tlpBRAM_mReqF$D_OUT[31:0]; endcase end - always@(idx__h22722 or tlp_tlpBRAM_mReqF$D_OUT) + always@(idx__h25886 or tlp_tlpBRAM_mReqF$D_OUT) begin - case (idx__h22722) + case (idx__h25886) 2'd0: - IF_2_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2479 = + SEL_ARR_tlp_tlpBRAM_mReqF_first__16_BITS_127_T_ETC___d724 = tlp_tlpBRAM_mReqF$D_OUT[127:96]; 2'd1: - IF_2_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2479 = + SEL_ARR_tlp_tlpBRAM_mReqF_first__16_BITS_127_T_ETC___d724 = tlp_tlpBRAM_mReqF$D_OUT[95:64]; 2'd2: - IF_2_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2479 = + SEL_ARR_tlp_tlpBRAM_mReqF_first__16_BITS_127_T_ETC___d724 = tlp_tlpBRAM_mReqF$D_OUT[63:32]; 2'd3: - IF_2_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2479 = + SEL_ARR_tlp_tlpBRAM_mReqF_first__16_BITS_127_T_ETC___d724 = tlp_tlpBRAM_mReqF$D_OUT[31:0]; endcase end - always@(idx__h24026 or tlp_tlpBRAM_mReqF$D_OUT) + always@(tlp_tlpBRAM_mReqF$D_OUT or + bram_0_serverAdapterA_cnt_6_SLT_3___d619 or + bram_1_serverAdapterA_cnt_44_SLT_3___d620 or + bram_2_serverAdapterA_cnt_62_SLT_3___d621 or + bram_3_serverAdapterA_cnt_80_SLT_3___d622) begin - case (idx__h24026) + case (tlp_tlpBRAM_mReqF$D_OUT[30:29]) 2'd0: - IF_3_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2480 = - tlp_tlpBRAM_mReqF$D_OUT[127:96]; + CASE_tlp_tlpBRAM_mReqF_first__16_BITS_30_TO_29_ETC___d736 = + bram_0_serverAdapterA_cnt_6_SLT_3___d619; 2'd1: - IF_3_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2480 = - tlp_tlpBRAM_mReqF$D_OUT[95:64]; + CASE_tlp_tlpBRAM_mReqF_first__16_BITS_30_TO_29_ETC___d736 = + bram_1_serverAdapterA_cnt_44_SLT_3___d620; 2'd2: - IF_3_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2480 = - tlp_tlpBRAM_mReqF$D_OUT[63:32]; + CASE_tlp_tlpBRAM_mReqF_first__16_BITS_30_TO_29_ETC___d736 = + bram_2_serverAdapterA_cnt_62_SLT_3___d621; 2'd3: - IF_3_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2480 = - tlp_tlpBRAM_mReqF$D_OUT[31:0]; + CASE_tlp_tlpBRAM_mReqF_first__16_BITS_30_TO_29_ETC___d736 = + bram_3_serverAdapterA_cnt_80_SLT_3___d622; + endcase + end + always@(tlp_outDwRemain) + begin + case (tlp_outDwRemain[1:0]) + 2'b0: CASE_tlp_outDwRemain_BITS_1_TO_0_0b0_0xFFFF_0b_ETC__q3 = 16'hFFFF; + 2'b01: + CASE_tlp_outDwRemain_BITS_1_TO_0_0b0_0xFFFF_0b_ETC__q3 = 16'hF000; + 2'b10: + CASE_tlp_outDwRemain_BITS_1_TO_0_0b0_0xFFFF_0b_ETC__q3 = 16'hFF00; + 2'd3: CASE_tlp_outDwRemain_BITS_1_TO_0_0b0_0xFFFF_0b_ETC__q3 = 16'hFFF0; endcase end always@(dpControl or bml_fabDone or bml_remDone) begin case (dpControl[1:0]) 2'd0: - CASE_dpControl_BITS_1_TO_0_NOT_bml_fabDone_0_N_ETC__q8 = + CASE_dpControl_BITS_1_TO_0_0_bml_fabDone_1_bml_ETC__q4 = + bml_fabDone; + 2'd1: + CASE_dpControl_BITS_1_TO_0_0_bml_fabDone_1_bml_ETC__q4 = + bml_remDone; + default: CASE_dpControl_BITS_1_TO_0_0_bml_fabDone_1_bml_ETC__q4 = + bml_fabDone; + endcase + end + always@(dpControl or bml_fabDone or bml_remDone) + begin + case (dpControl[1:0]) + 2'd0: + CASE_dpControl_BITS_1_TO_0_0_NOT_bml_fabDone_1_ETC__q5 = !bml_fabDone; 2'd1: - CASE_dpControl_BITS_1_TO_0_NOT_bml_fabDone_0_N_ETC__q8 = + CASE_dpControl_BITS_1_TO_0_0_NOT_bml_fabDone_1_ETC__q5 = !bml_remDone; - default: CASE_dpControl_BITS_1_TO_0_NOT_bml_fabDone_0_N_ETC__q8 = + default: CASE_dpControl_BITS_1_TO_0_0_NOT_bml_fabDone_1_ETC__q5 = + !bml_fabDone; + endcase + end + always@(dpControl or + bml_fabDone or + IF_bml_dpControl_wget__898_BITS_3_TO_2_899_EQ__ETC___d1995) + begin + case (dpControl[1:0]) + 2'd0: + CASE_dpControl_BITS_1_TO_0_0_NOT_bml_fabDone_1_ETC__q6 = + !bml_fabDone; + 2'd1: + CASE_dpControl_BITS_1_TO_0_0_NOT_bml_fabDone_1_ETC__q6 = + IF_bml_dpControl_wget__898_BITS_3_TO_2_899_EQ__ETC___d1995; + default: CASE_dpControl_BITS_1_TO_0_0_NOT_bml_fabDone_1_ETC__q6 = !bml_fabDone; endcase end + always@(dpControl or bml_fabDone or bml_remDone or bml_remStart) + begin + case (dpControl[1:0]) + 2'd0: + CASE_dpControl_BITS_1_TO_0_0_bml_fabDone_1_IF__ETC__q7 = + bml_fabDone; + 2'd1: + CASE_dpControl_BITS_1_TO_0_0_bml_fabDone_1_IF__ETC__q7 = + (dpControl[3:2] == 2'd1) ? bml_remDone : bml_remStart; + default: CASE_dpControl_BITS_1_TO_0_0_bml_fabDone_1_IF__ETC__q7 = + bml_fabDone; + endcase + end always@(tlp_tlpBRAM_readReq$D_OUT or - bram_serverAdapterA_3_outDataCore$EMPTY_N or - bram_serverAdapterA_3_outData_enqData$whas or - bram_serverAdapterA_outDataCore$EMPTY_N or - bram_serverAdapterA_outData_enqData$whas or - bram_serverAdapterA_1_outDataCore$EMPTY_N or - bram_serverAdapterA_1_outData_enqData$whas or - bram_serverAdapterA_2_outDataCore$EMPTY_N or - bram_serverAdapterA_2_outData_enqData$whas) + bram_0_serverAdapterA_outDataCore$EMPTY_N or + bram_0_serverAdapterA_outData_enqData$whas or + bram_1_serverAdapterA_outDataCore$EMPTY_N or + bram_1_serverAdapterA_outData_enqData$whas or + bram_2_serverAdapterA_outDataCore$EMPTY_N or + bram_2_serverAdapterA_outData_enqData$whas or + bram_3_serverAdapterA_outDataCore$EMPTY_N or + bram_3_serverAdapterA_outData_enqData$whas) begin case (tlp_tlpBRAM_readReq$D_OUT[30:29]) 2'd0: - IF_tlp_tlpBRAM_readReq_first__97_BITS_30_TO_29_ETC___d912 = - bram_serverAdapterA_outDataCore$EMPTY_N || - bram_serverAdapterA_outData_enqData$whas; + CASE_tlp_tlpBRAM_readReq_first__98_BITS_30_TO__ETC___d805 = + bram_0_serverAdapterA_outDataCore$EMPTY_N || + bram_0_serverAdapterA_outData_enqData$whas; 2'd1: - IF_tlp_tlpBRAM_readReq_first__97_BITS_30_TO_29_ETC___d912 = - bram_serverAdapterA_1_outDataCore$EMPTY_N || - bram_serverAdapterA_1_outData_enqData$whas; + CASE_tlp_tlpBRAM_readReq_first__98_BITS_30_TO__ETC___d805 = + bram_1_serverAdapterA_outDataCore$EMPTY_N || + bram_1_serverAdapterA_outData_enqData$whas; 2'd2: - IF_tlp_tlpBRAM_readReq_first__97_BITS_30_TO_29_ETC___d912 = - bram_serverAdapterA_2_outDataCore$EMPTY_N || - bram_serverAdapterA_2_outData_enqData$whas; + CASE_tlp_tlpBRAM_readReq_first__98_BITS_30_TO__ETC___d805 = + bram_2_serverAdapterA_outDataCore$EMPTY_N || + bram_2_serverAdapterA_outData_enqData$whas; 2'd3: - IF_tlp_tlpBRAM_readReq_first__97_BITS_30_TO_29_ETC___d912 = - tlp_tlpBRAM_readReq$D_OUT[30:29] != 2'd3 || - bram_serverAdapterA_3_outDataCore$EMPTY_N || - bram_serverAdapterA_3_outData_enqData$whas; + CASE_tlp_tlpBRAM_readReq_first__98_BITS_30_TO__ETC___d805 = + bram_3_serverAdapterA_outDataCore$EMPTY_N || + bram_3_serverAdapterA_outData_enqData$whas; endcase end always@(tlp_tlpBRAM_readReq$D_OUT or - bram_serverAdapterA_3_outData_outData$wget or - bram_serverAdapterA_outData_outData$wget or - bram_serverAdapterA_1_outData_outData$wget or - bram_serverAdapterA_2_outData_outData$wget) + bram_0_serverAdapterA_outData_outData$wget or + bram_1_serverAdapterA_outData_outData$wget or + bram_2_serverAdapterA_outData_outData$wget or + bram_3_serverAdapterA_outData_outData$wget) begin case (tlp_tlpBRAM_readReq$D_OUT[30:29]) 2'd0: - IF_tlp_tlpBRAM_readReq_first__97_BITS_30_TO_29_ETC___d2397 = - bram_serverAdapterA_outData_outData$wget; + SEL_ARR_bram_0_serverAdapterA_outData_outData__ETC___d863 = + bram_0_serverAdapterA_outData_outData$wget; 2'd1: - IF_tlp_tlpBRAM_readReq_first__97_BITS_30_TO_29_ETC___d2397 = - bram_serverAdapterA_1_outData_outData$wget; + SEL_ARR_bram_0_serverAdapterA_outData_outData__ETC___d863 = + bram_1_serverAdapterA_outData_outData$wget; 2'd2: - IF_tlp_tlpBRAM_readReq_first__97_BITS_30_TO_29_ETC___d2397 = - bram_serverAdapterA_2_outData_outData$wget; + SEL_ARR_bram_0_serverAdapterA_outData_outData__ETC___d863 = + bram_2_serverAdapterA_outData_outData$wget; 2'd3: - IF_tlp_tlpBRAM_readReq_first__97_BITS_30_TO_29_ETC___d2397 = - bram_serverAdapterA_3_outData_outData$wget; + SEL_ARR_bram_0_serverAdapterA_outData_outData__ETC___d863 = + bram_3_serverAdapterA_outData_outData$wget; endcase end always@(tlp_tlpBRAM_readReq$D_OUT or - bram_serverAdapterA_3_outData_outData$whas or - bram_serverAdapterA_outData_outData$whas or - bram_serverAdapterA_1_outData_outData$whas or - bram_serverAdapterA_2_outData_outData$whas) + bram_0_serverAdapterA_outData_outData$whas or + bram_1_serverAdapterA_outData_outData$whas or + bram_2_serverAdapterA_outData_outData$whas or + bram_3_serverAdapterA_outData_outData$whas) begin case (tlp_tlpBRAM_readReq$D_OUT[30:29]) 2'd0: - CASE_tlp_tlpBRAM_readReqD_OUT_BITS_30_TO_29_N_ETC__q17 = - bram_serverAdapterA_outData_outData$whas; + CASE_tlp_tlpBRAM_readReq_first__98_BITS_30_TO__ETC___d810 = + bram_0_serverAdapterA_outData_outData$whas; 2'd1: - CASE_tlp_tlpBRAM_readReqD_OUT_BITS_30_TO_29_N_ETC__q17 = - bram_serverAdapterA_1_outData_outData$whas; + CASE_tlp_tlpBRAM_readReq_first__98_BITS_30_TO__ETC___d810 = + bram_1_serverAdapterA_outData_outData$whas; 2'd2: - CASE_tlp_tlpBRAM_readReqD_OUT_BITS_30_TO_29_N_ETC__q17 = - bram_serverAdapterA_2_outData_outData$whas; + CASE_tlp_tlpBRAM_readReq_first__98_BITS_30_TO__ETC___d810 = + bram_2_serverAdapterA_outData_outData$whas; 2'd3: - CASE_tlp_tlpBRAM_readReqD_OUT_BITS_30_TO_29_N_ETC__q17 = - tlp_tlpBRAM_readReq$D_OUT[30:29] != 2'd3 || - bram_serverAdapterA_3_outData_outData$whas; + CASE_tlp_tlpBRAM_readReq_first__98_BITS_30_TO__ETC___d810 = + bram_3_serverAdapterA_outData_outData$whas; endcase end @@ -7398,22 +7336,22 @@ module mkOCDP16B(pciDevice, bml_remDones <= `BSV_ASSIGNMENT_DELAY 16'd0; bml_remStart <= `BSV_ASSIGNMENT_DELAY 1'd0; bml_remStarts <= `BSV_ASSIGNMENT_DELAY 16'd0; - bram_serverAdapterA_1_cnt <= `BSV_ASSIGNMENT_DELAY 3'd0; - bram_serverAdapterA_1_s1 <= `BSV_ASSIGNMENT_DELAY 2'd0; - bram_serverAdapterA_2_cnt <= `BSV_ASSIGNMENT_DELAY 3'd0; - bram_serverAdapterA_2_s1 <= `BSV_ASSIGNMENT_DELAY 2'd0; - bram_serverAdapterA_3_cnt <= `BSV_ASSIGNMENT_DELAY 3'd0; - bram_serverAdapterA_3_s1 <= `BSV_ASSIGNMENT_DELAY 2'd0; - bram_serverAdapterA_cnt <= `BSV_ASSIGNMENT_DELAY 3'd0; - bram_serverAdapterA_s1 <= `BSV_ASSIGNMENT_DELAY 2'd0; - bram_serverAdapterB_1_cnt <= `BSV_ASSIGNMENT_DELAY 3'd0; - bram_serverAdapterB_1_s1 <= `BSV_ASSIGNMENT_DELAY 2'd0; - bram_serverAdapterB_2_cnt <= `BSV_ASSIGNMENT_DELAY 3'd0; - bram_serverAdapterB_2_s1 <= `BSV_ASSIGNMENT_DELAY 2'd0; - bram_serverAdapterB_3_cnt <= `BSV_ASSIGNMENT_DELAY 3'd0; - bram_serverAdapterB_3_s1 <= `BSV_ASSIGNMENT_DELAY 2'd0; - bram_serverAdapterB_cnt <= `BSV_ASSIGNMENT_DELAY 3'd0; - bram_serverAdapterB_s1 <= `BSV_ASSIGNMENT_DELAY 2'd0; + bram_0_serverAdapterA_cnt <= `BSV_ASSIGNMENT_DELAY 3'd0; + bram_0_serverAdapterA_s1 <= `BSV_ASSIGNMENT_DELAY 2'd0; + bram_0_serverAdapterB_cnt <= `BSV_ASSIGNMENT_DELAY 3'd0; + bram_0_serverAdapterB_s1 <= `BSV_ASSIGNMENT_DELAY 2'd0; + bram_1_serverAdapterA_cnt <= `BSV_ASSIGNMENT_DELAY 3'd0; + bram_1_serverAdapterA_s1 <= `BSV_ASSIGNMENT_DELAY 2'd0; + bram_1_serverAdapterB_cnt <= `BSV_ASSIGNMENT_DELAY 3'd0; + bram_1_serverAdapterB_s1 <= `BSV_ASSIGNMENT_DELAY 2'd0; + bram_2_serverAdapterA_cnt <= `BSV_ASSIGNMENT_DELAY 3'd0; + bram_2_serverAdapterA_s1 <= `BSV_ASSIGNMENT_DELAY 2'd0; + bram_2_serverAdapterB_cnt <= `BSV_ASSIGNMENT_DELAY 3'd0; + bram_2_serverAdapterB_s1 <= `BSV_ASSIGNMENT_DELAY 2'd0; + bram_3_serverAdapterA_cnt <= `BSV_ASSIGNMENT_DELAY 3'd0; + bram_3_serverAdapterA_s1 <= `BSV_ASSIGNMENT_DELAY 2'd0; + bram_3_serverAdapterB_cnt <= `BSV_ASSIGNMENT_DELAY 3'd0; + bram_3_serverAdapterB_s1 <= `BSV_ASSIGNMENT_DELAY 2'd0; dmaDoneTime <= `BSV_ASSIGNMENT_DELAY 64'd0; dmaStartTime <= `BSV_ASSIGNMENT_DELAY 64'd0; dpControl <= `BSV_ASSIGNMENT_DELAY 8'd0; @@ -7431,7 +7369,7 @@ module mkOCDP16B(pciDevice, tlp_farBufReady <= `BSV_ASSIGNMENT_DELAY 1'd0; tlp_flowDiagCount <= `BSV_ASSIGNMENT_DELAY 32'd0; tlp_gotResponseHeader <= `BSV_ASSIGNMENT_DELAY 1'd0; - tlp_lastMetaV <= `BSV_ASSIGNMENT_DELAY 32'd0; + tlp_lastMetaV_0 <= `BSV_ASSIGNMENT_DELAY 32'd0; tlp_lastMetaV_1 <= `BSV_ASSIGNMENT_DELAY 32'd0; tlp_lastMetaV_2 <= `BSV_ASSIGNMENT_DELAY 32'd0; tlp_lastMetaV_3 <= `BSV_ASSIGNMENT_DELAY 32'd0; @@ -7462,7 +7400,7 @@ module mkOCDP16B(pciDevice, wci_illegalEdge <= `BSV_ASSIGNMENT_DELAY 1'd0; wci_nState <= `BSV_ASSIGNMENT_DELAY 3'd0; wci_reqF_countReg <= `BSV_ASSIGNMENT_DELAY 2'd0; - wci_respF_c_r <= `BSV_ASSIGNMENT_DELAY 2'd0; + wci_respF_cntr_r <= `BSV_ASSIGNMENT_DELAY 2'd0; wci_respF_q_0 <= `BSV_ASSIGNMENT_DELAY 34'h0AAAAAAAA; wci_respF_q_1 <= `BSV_ASSIGNMENT_DELAY 34'h0AAAAAAAA; wci_sFlagReg <= `BSV_ASSIGNMENT_DELAY 1'd0; @@ -7493,7 +7431,7 @@ module mkOCDP16B(pciDevice, wmi_wmi_peerIsReady <= `BSV_ASSIGNMENT_DELAY 1'd0; wmi_wmi_reqF_countReg <= `BSV_ASSIGNMENT_DELAY 2'd0; wmi_wmi_reqF_levelsValid <= `BSV_ASSIGNMENT_DELAY 1'd1; - wmi_wmi_respF_c_r <= `BSV_ASSIGNMENT_DELAY 2'd0; + wmi_wmi_respF_cntr_r <= `BSV_ASSIGNMENT_DELAY 2'd0; wmi_wmi_respF_q_0 <= `BSV_ASSIGNMENT_DELAY 130'd0; wmi_wmi_respF_q_1 <= `BSV_ASSIGNMENT_DELAY 130'd0; wmi_wmi_sFlagReg <= `BSV_ASSIGNMENT_DELAY 32'd0; @@ -7574,54 +7512,54 @@ module mkOCDP16B(pciDevice, bml_remStart <= `BSV_ASSIGNMENT_DELAY bml_remStart$D_IN; if (bml_remStarts$EN) bml_remStarts <= `BSV_ASSIGNMENT_DELAY bml_remStarts$D_IN; - if (bram_serverAdapterA_1_cnt$EN) - bram_serverAdapterA_1_cnt <= `BSV_ASSIGNMENT_DELAY - bram_serverAdapterA_1_cnt$D_IN; - if (bram_serverAdapterA_1_s1$EN) - bram_serverAdapterA_1_s1 <= `BSV_ASSIGNMENT_DELAY - bram_serverAdapterA_1_s1$D_IN; - if (bram_serverAdapterA_2_cnt$EN) - bram_serverAdapterA_2_cnt <= `BSV_ASSIGNMENT_DELAY - bram_serverAdapterA_2_cnt$D_IN; - if (bram_serverAdapterA_2_s1$EN) - bram_serverAdapterA_2_s1 <= `BSV_ASSIGNMENT_DELAY - bram_serverAdapterA_2_s1$D_IN; - if (bram_serverAdapterA_3_cnt$EN) - bram_serverAdapterA_3_cnt <= `BSV_ASSIGNMENT_DELAY - bram_serverAdapterA_3_cnt$D_IN; - if (bram_serverAdapterA_3_s1$EN) - bram_serverAdapterA_3_s1 <= `BSV_ASSIGNMENT_DELAY - bram_serverAdapterA_3_s1$D_IN; - if (bram_serverAdapterA_cnt$EN) - bram_serverAdapterA_cnt <= `BSV_ASSIGNMENT_DELAY - bram_serverAdapterA_cnt$D_IN; - if (bram_serverAdapterA_s1$EN) - bram_serverAdapterA_s1 <= `BSV_ASSIGNMENT_DELAY - bram_serverAdapterA_s1$D_IN; - if (bram_serverAdapterB_1_cnt$EN) - bram_serverAdapterB_1_cnt <= `BSV_ASSIGNMENT_DELAY - bram_serverAdapterB_1_cnt$D_IN; - if (bram_serverAdapterB_1_s1$EN) - bram_serverAdapterB_1_s1 <= `BSV_ASSIGNMENT_DELAY - bram_serverAdapterB_1_s1$D_IN; - if (bram_serverAdapterB_2_cnt$EN) - bram_serverAdapterB_2_cnt <= `BSV_ASSIGNMENT_DELAY - bram_serverAdapterB_2_cnt$D_IN; - if (bram_serverAdapterB_2_s1$EN) - bram_serverAdapterB_2_s1 <= `BSV_ASSIGNMENT_DELAY - bram_serverAdapterB_2_s1$D_IN; - if (bram_serverAdapterB_3_cnt$EN) - bram_serverAdapterB_3_cnt <= `BSV_ASSIGNMENT_DELAY - bram_serverAdapterB_3_cnt$D_IN; - if (bram_serverAdapterB_3_s1$EN) - bram_serverAdapterB_3_s1 <= `BSV_ASSIGNMENT_DELAY - bram_serverAdapterB_3_s1$D_IN; - if (bram_serverAdapterB_cnt$EN) - bram_serverAdapterB_cnt <= `BSV_ASSIGNMENT_DELAY - bram_serverAdapterB_cnt$D_IN; - if (bram_serverAdapterB_s1$EN) - bram_serverAdapterB_s1 <= `BSV_ASSIGNMENT_DELAY - bram_serverAdapterB_s1$D_IN; + if (bram_0_serverAdapterA_cnt$EN) + bram_0_serverAdapterA_cnt <= `BSV_ASSIGNMENT_DELAY + bram_0_serverAdapterA_cnt$D_IN; + if (bram_0_serverAdapterA_s1$EN) + bram_0_serverAdapterA_s1 <= `BSV_ASSIGNMENT_DELAY + bram_0_serverAdapterA_s1$D_IN; + if (bram_0_serverAdapterB_cnt$EN) + bram_0_serverAdapterB_cnt <= `BSV_ASSIGNMENT_DELAY + bram_0_serverAdapterB_cnt$D_IN; + if (bram_0_serverAdapterB_s1$EN) + bram_0_serverAdapterB_s1 <= `BSV_ASSIGNMENT_DELAY + bram_0_serverAdapterB_s1$D_IN; + if (bram_1_serverAdapterA_cnt$EN) + bram_1_serverAdapterA_cnt <= `BSV_ASSIGNMENT_DELAY + bram_1_serverAdapterA_cnt$D_IN; + if (bram_1_serverAdapterA_s1$EN) + bram_1_serverAdapterA_s1 <= `BSV_ASSIGNMENT_DELAY + bram_1_serverAdapterA_s1$D_IN; + if (bram_1_serverAdapterB_cnt$EN) + bram_1_serverAdapterB_cnt <= `BSV_ASSIGNMENT_DELAY + bram_1_serverAdapterB_cnt$D_IN; + if (bram_1_serverAdapterB_s1$EN) + bram_1_serverAdapterB_s1 <= `BSV_ASSIGNMENT_DELAY + bram_1_serverAdapterB_s1$D_IN; + if (bram_2_serverAdapterA_cnt$EN) + bram_2_serverAdapterA_cnt <= `BSV_ASSIGNMENT_DELAY + bram_2_serverAdapterA_cnt$D_IN; + if (bram_2_serverAdapterA_s1$EN) + bram_2_serverAdapterA_s1 <= `BSV_ASSIGNMENT_DELAY + bram_2_serverAdapterA_s1$D_IN; + if (bram_2_serverAdapterB_cnt$EN) + bram_2_serverAdapterB_cnt <= `BSV_ASSIGNMENT_DELAY + bram_2_serverAdapterB_cnt$D_IN; + if (bram_2_serverAdapterB_s1$EN) + bram_2_serverAdapterB_s1 <= `BSV_ASSIGNMENT_DELAY + bram_2_serverAdapterB_s1$D_IN; + if (bram_3_serverAdapterA_cnt$EN) + bram_3_serverAdapterA_cnt <= `BSV_ASSIGNMENT_DELAY + bram_3_serverAdapterA_cnt$D_IN; + if (bram_3_serverAdapterA_s1$EN) + bram_3_serverAdapterA_s1 <= `BSV_ASSIGNMENT_DELAY + bram_3_serverAdapterA_s1$D_IN; + if (bram_3_serverAdapterB_cnt$EN) + bram_3_serverAdapterB_cnt <= `BSV_ASSIGNMENT_DELAY + bram_3_serverAdapterB_cnt$D_IN; + if (bram_3_serverAdapterB_s1$EN) + bram_3_serverAdapterB_s1 <= `BSV_ASSIGNMENT_DELAY + bram_3_serverAdapterB_s1$D_IN; if (dmaDoneTime$EN) dmaDoneTime <= `BSV_ASSIGNMENT_DELAY dmaDoneTime$D_IN; if (dmaStartTime$EN) @@ -7656,8 +7594,8 @@ module mkOCDP16B(pciDevice, if (tlp_gotResponseHeader$EN) tlp_gotResponseHeader <= `BSV_ASSIGNMENT_DELAY tlp_gotResponseHeader$D_IN; - if (tlp_lastMetaV$EN) - tlp_lastMetaV <= `BSV_ASSIGNMENT_DELAY tlp_lastMetaV$D_IN; + if (tlp_lastMetaV_0$EN) + tlp_lastMetaV_0 <= `BSV_ASSIGNMENT_DELAY tlp_lastMetaV_0$D_IN; if (tlp_lastMetaV_1$EN) tlp_lastMetaV_1 <= `BSV_ASSIGNMENT_DELAY tlp_lastMetaV_1$D_IN; if (tlp_lastMetaV_2$EN) @@ -7725,8 +7663,8 @@ module mkOCDP16B(pciDevice, wci_nState <= `BSV_ASSIGNMENT_DELAY wci_nState$D_IN; if (wci_reqF_countReg$EN) wci_reqF_countReg <= `BSV_ASSIGNMENT_DELAY wci_reqF_countReg$D_IN; - if (wci_respF_c_r$EN) - wci_respF_c_r <= `BSV_ASSIGNMENT_DELAY wci_respF_c_r$D_IN; + if (wci_respF_cntr_r$EN) + wci_respF_cntr_r <= `BSV_ASSIGNMENT_DELAY wci_respF_cntr_r$D_IN; if (wci_respF_q_0$EN) wci_respF_q_0 <= `BSV_ASSIGNMENT_DELAY wci_respF_q_0$D_IN; if (wci_respF_q_1$EN) @@ -7793,8 +7731,9 @@ module mkOCDP16B(pciDevice, if (wmi_wmi_reqF_levelsValid$EN) wmi_wmi_reqF_levelsValid <= `BSV_ASSIGNMENT_DELAY wmi_wmi_reqF_levelsValid$D_IN; - if (wmi_wmi_respF_c_r$EN) - wmi_wmi_respF_c_r <= `BSV_ASSIGNMENT_DELAY wmi_wmi_respF_c_r$D_IN; + if (wmi_wmi_respF_cntr_r$EN) + wmi_wmi_respF_cntr_r <= `BSV_ASSIGNMENT_DELAY + wmi_wmi_respF_cntr_r$D_IN; if (wmi_wmi_respF_q_0$EN) wmi_wmi_respF_q_0 <= `BSV_ASSIGNMENT_DELAY wmi_wmi_respF_q_0$D_IN; if (wmi_wmi_respF_q_1$EN) @@ -7979,22 +7918,22 @@ module mkOCDP16B(pciDevice, bml_remMetaAddr = 16'hAAAA; bml_remStart = 1'h0; bml_remStarts = 16'hAAAA; - bram_serverAdapterA_1_cnt = 3'h2; - bram_serverAdapterA_1_s1 = 2'h2; - bram_serverAdapterA_2_cnt = 3'h2; - bram_serverAdapterA_2_s1 = 2'h2; - bram_serverAdapterA_3_cnt = 3'h2; - bram_serverAdapterA_3_s1 = 2'h2; - bram_serverAdapterA_cnt = 3'h2; - bram_serverAdapterA_s1 = 2'h2; - bram_serverAdapterB_1_cnt = 3'h2; - bram_serverAdapterB_1_s1 = 2'h2; - bram_serverAdapterB_2_cnt = 3'h2; - bram_serverAdapterB_2_s1 = 2'h2; - bram_serverAdapterB_3_cnt = 3'h2; - bram_serverAdapterB_3_s1 = 2'h2; - bram_serverAdapterB_cnt = 3'h2; - bram_serverAdapterB_s1 = 2'h2; + bram_0_serverAdapterA_cnt = 3'h2; + bram_0_serverAdapterA_s1 = 2'h2; + bram_0_serverAdapterB_cnt = 3'h2; + bram_0_serverAdapterB_s1 = 2'h2; + bram_1_serverAdapterA_cnt = 3'h2; + bram_1_serverAdapterA_s1 = 2'h2; + bram_1_serverAdapterB_cnt = 3'h2; + bram_1_serverAdapterB_s1 = 2'h2; + bram_2_serverAdapterA_cnt = 3'h2; + bram_2_serverAdapterA_s1 = 2'h2; + bram_2_serverAdapterB_cnt = 3'h2; + bram_2_serverAdapterB_s1 = 2'h2; + bram_3_serverAdapterA_cnt = 3'h2; + bram_3_serverAdapterA_s1 = 2'h2; + bram_3_serverAdapterB_cnt = 3'h2; + bram_3_serverAdapterB_s1 = 2'h2; dmaDoneTime = 64'hAAAAAAAAAAAAAAAA; dmaStartTime = 64'hAAAAAAAAAAAAAAAA; dpControl = 8'hAA; @@ -8022,7 +7961,7 @@ module mkOCDP16B(pciDevice, tlp_flowDiagCount = 32'hAAAAAAAA; tlp_gotResponseHeader = 1'h0; tlp_inIgnorePkt = 1'h0; - tlp_lastMetaV = 32'hAAAAAAAA; + tlp_lastMetaV_0 = 32'hAAAAAAAA; tlp_lastMetaV_1 = 32'hAAAAAAAA; tlp_lastMetaV_2 = 32'hAAAAAAAA; tlp_lastMetaV_3 = 32'hAAAAAAAA; @@ -8068,7 +8007,7 @@ module mkOCDP16B(pciDevice, wci_isReset_isInReset = 1'h0; wci_nState = 3'h2; wci_reqF_countReg = 2'h2; - wci_respF_c_r = 2'h2; + wci_respF_cntr_r = 2'h2; wci_respF_q_0 = 34'h2AAAAAAAA; wci_respF_q_1 = 34'h2AAAAAAAA; wci_sFlagReg = 1'h0; @@ -8103,7 +8042,7 @@ module mkOCDP16B(pciDevice, wmi_wmi_peerIsReady = 1'h0; wmi_wmi_reqF_countReg = 2'h2; wmi_wmi_reqF_levelsValid = 1'h0; - wmi_wmi_respF_c_r = 2'h2; + wmi_wmi_respF_cntr_r = 2'h2; wmi_wmi_respF_q_0 = 130'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; wmi_wmi_respF_q_1 = 130'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; wmi_wmi_sFlagReg = 32'hAAAAAAAA; @@ -8126,305 +8065,305 @@ module mkOCDP16B(pciDevice, begin #0; if (RST_N != `BSV_RESET_VALUE) - if (bram_serverAdapterA_s1[1] && - !bram_serverAdapterA_outDataCore$FULL_N) + if (bram_0_serverAdapterA_s1[1] && + !bram_0_serverAdapterA_outDataCore$FULL_N) $display("ERROR: %m: mkBRAMSeverAdapter overrun"); if (RST_N != `BSV_RESET_VALUE) - if (bram_serverAdapterB_s1[1] && - !bram_serverAdapterB_outDataCore$FULL_N) + if (bram_0_serverAdapterB_s1[1] && + !bram_0_serverAdapterB_outDataCore$FULL_N) $display("ERROR: %m: mkBRAMSeverAdapter overrun"); if (RST_N != `BSV_RESET_VALUE) - if (bram_serverAdapterA_1_s1[1] && - !bram_serverAdapterA_1_outDataCore$FULL_N) + if (bram_1_serverAdapterA_s1[1] && + !bram_1_serverAdapterA_outDataCore$FULL_N) $display("ERROR: %m: mkBRAMSeverAdapter overrun"); if (RST_N != `BSV_RESET_VALUE) - if (bram_serverAdapterB_1_s1[1] && - !bram_serverAdapterB_1_outDataCore$FULL_N) + if (bram_1_serverAdapterB_s1[1] && + !bram_1_serverAdapterB_outDataCore$FULL_N) $display("ERROR: %m: mkBRAMSeverAdapter overrun"); if (RST_N != `BSV_RESET_VALUE) - if (bram_serverAdapterA_2_s1[1] && - !bram_serverAdapterA_2_outDataCore$FULL_N) + if (bram_2_serverAdapterA_s1[1] && + !bram_2_serverAdapterA_outDataCore$FULL_N) $display("ERROR: %m: mkBRAMSeverAdapter overrun"); if (RST_N != `BSV_RESET_VALUE) - if (bram_serverAdapterB_2_s1[1] && - !bram_serverAdapterB_2_outDataCore$FULL_N) + if (bram_2_serverAdapterB_s1[1] && + !bram_2_serverAdapterB_outDataCore$FULL_N) $display("ERROR: %m: mkBRAMSeverAdapter overrun"); if (RST_N != `BSV_RESET_VALUE) - if (bram_serverAdapterA_3_s1[1] && - !bram_serverAdapterA_3_outDataCore$FULL_N) + if (bram_3_serverAdapterA_s1[1] && + !bram_3_serverAdapterA_outDataCore$FULL_N) $display("ERROR: %m: mkBRAMSeverAdapter overrun"); if (RST_N != `BSV_RESET_VALUE) - if (bram_serverAdapterB_3_s1[1] && - !bram_serverAdapterB_3_outDataCore$FULL_N) + if (bram_3_serverAdapterB_s1[1] && + !bram_3_serverAdapterB_outDataCore$FULL_N) $display("ERROR: %m: mkBRAMSeverAdapter overrun"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfrd) begin - v__h90426 = $time; + v__h91963 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfrd) $display("[%0d]: %m: WCI CONFIG READ Addr:%0x BE:%0x Data:%0x", - v__h90426, + v__h91963, wci_reqF$D_OUT[63:32], wci_reqF$D_OUT[67:64], - _theResult____h90410); + _theResult____h91947); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_ctl_op_start) begin - v__h15697 = $time; + v__h15577 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_ctl_op_start) $display("[%0d]: %m: WCI ControlOp: Starting-transition edge:%x from:%x", - v__h15697, + v__h15577, wci_reqF$D_OUT[36:34], wci_cState); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_tlp_dmaRequestNearMeta) begin - v__h39702 = $time; + v__h41005 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_tlp_dmaRequestNearMeta) $display("[%0d]: %m: dmaRequestNearMeta FPactMesg-Step1/7", - v__h39702); + v__h41005); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_tlp_dmaPushRequestMesg) begin - v__h46380 = $time; + v__h47790 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_tlp_dmaPushRequestMesg) $display("[%0d]: %m: dmaPushRequestMesg FPactMesg-Step3/7", - v__h46380); + v__h47790); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_tlp_dmaResponseNearMetaHead) begin - v__h41753 = $time; + v__h43090 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_tlp_dmaResponseNearMetaHead) $display("[%0d]: %m: dmaResponseNearMetaHead FPactMesg-Step2a/7 mesgLength:%0x", - v__h41753, - x__h40887); + v__h43090, + x__h42208); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_tlp_dmaPushResponseHeader) begin - v__h47001 = $time; + v__h48409 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_tlp_dmaPushResponseHeader) $display("[%0d]: %m: dmaPushResponseHeader FPactMesg-Step4a/7", - v__h47001); + v__h48409); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_tlp_dmaPushResponseBody) begin - v__h47351 = $time; + v__h48757 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_tlp_dmaPushResponseBody) $display("[%0d]: %m: dmaPushResponseBody FPactMesg-Step4b/7", - v__h47351); + v__h48757); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_tlp_dmaXmtMetaHead) begin - v__h48586 = $time; + v__h50007 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_tlp_dmaXmtMetaHead) - $display("[%0d]: %m: dmaXmtMetaHead FPactMesg-Step5/7", v__h48586); + $display("[%0d]: %m: dmaXmtMetaHead FPactMesg-Step5/7", v__h50007); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_tlp_dmaXmtTailEvent) begin - v__h54974 = $time; + v__h56506 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_tlp_dmaXmtTailEvent) - $display("[%0d]: %m: dmaXmtTailEvent FPactMesg-Step7/7", v__h54974); + $display("[%0d]: %m: dmaXmtTailEvent FPactMesg-Step7/7", v__h56506); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_tlp_dmaXmtMetaBody) begin - v__h54850 = $time; + v__h56382 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_tlp_dmaXmtMetaBody) - $display("[%0d]: %m: dmaXmtMetaBody FPactMesg-Step6/7", v__h54850); + $display("[%0d]: %m: dmaXmtMetaBody FPactMesg-Step6/7", v__h56382); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_tlp_dmaXmtDoorbell) begin - v__h55182 = $time; + v__h56714 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_tlp_dmaXmtDoorbell) - $display("[%0d]: %m: dmaXmtDoorbell FC/FPactFlow-Step1/1", v__h55182); + $display("[%0d]: %m: dmaXmtDoorbell FC/FPactFlow-Step1/1", v__h56714); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_tlp_dmaRespHeadFarMeta) begin - v__h57878 = $time; + v__h59442 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_tlp_dmaRespHeadFarMeta) $display("[%0d]: %m: dmaRespHeadFarMeta FPactMesg-Step2a/N fabMeta:%0x", - v__h57878, - x__h56804); + v__h59442, + x__h58352); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_tlp_dmaPullTailEvent) begin - v__h63884 = $time; + v__h65522 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_tlp_dmaPullTailEvent) - $display("[%0d]: %m: dmaPullTailEvent FPactMesg-Step5/5", v__h63884); + $display("[%0d]: %m: dmaPullTailEvent FPactMesg-Step5/5", v__h65522); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_tlp_dmaRespBodyFarMeta) begin - v__h62195 = $time; + v__h63835 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_tlp_dmaRespBodyFarMeta) $display("[%0d]: %m: dmaRespBodyFarMeta FPactMesg-Step2b/N opcode:%0x nowMS:%0x nowLS:%0x", - v__h62195, - opcode__h58837, - nowMS__h60057, - nowLS__h60998); + v__h63835, + opcode__h60417, + nowMS__h61665, + nowLS__h62622); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_tlp_dmaPullResponseHeader) begin - v__h63372 = $time; + v__h65011 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_tlp_dmaPullResponseHeader) $display("[%0d]: %m: dmaPullResponseHeader FPactMesg-Step4a/5", - v__h63372); + v__h65011); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_tlp_dmaPullResponseBody) begin - v__h63720 = $time; + v__h65359 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_tlp_dmaPullResponseBody) $display("[%0d]: %m: dmaPullResponseBody FPactMesg-Step4b/5", - v__h63720); + v__h65359); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_tlp_dmaTailEventSender) begin - v__h69047 = $time; + v__h70765 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_tlp_dmaTailEventSender) - $display("[%0d]: %m: dmaTailEventSender - generic", v__h69047); + $display("[%0d]: %m: dmaTailEventSender - generic", v__h70765); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_tlp_dmaResponseNearMetaBody) begin - v__h46039 = $time; + v__h47450 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_tlp_dmaResponseNearMetaBody) $display("[%0d]: %m: dmaResponseNearMetaBody FPactMesg-Step2b/7 opcode:%0x nowMS:%0x nowLS:%0x", - v__h46039, - opcode__h42670, - nowMS__h43901, - nowLS__h44844); + v__h47450, + opcode__h44022, + nowMS__h45280, + nowLS__h46239); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_tlp_dmaRequestFarMeta) begin - v__h55645 = $time; + v__h57177 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_tlp_dmaRequestFarMeta) - $display("[%0d]: %m: dmaRequestFarMeta FCactMesg-Step1/5", v__h55645); + $display("[%0d]: %m: dmaRequestFarMeta FCactMesg-Step1/5", v__h57177); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_tlp_dmaPullRequestFarMesg) begin - v__h62717 = $time; + v__h64356 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_tlp_dmaPullRequestFarMesg) $display("[%0d]: %m: dmaPullRequestFarMesg FCactMesg-Step3/5", - v__h62717); + v__h64356); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wmi_doWriteFinalize) begin - v__h80879 = $time; + v__h82455 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wmi_doWriteFinalize) $display("[%0d]: %m: doWriteFinalize lclMetaAddr :%0x length:%0x opcode:%0x nowMS:%0x nowLS:%0x ", - v__h80879, + v__h82455, wmi_lclMetaAddr, - x3__h80237, - mesgMeta_opcode__h80277, + x3__h81813, + mesgMeta_opcode__h81853, dmaStartTime$D_IN[63:32], dmaStartTime$D_IN[31:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfwr && wci_reqF$D_OUT[39:32] == 8'h18) begin - v__h89794 = $time; + v__h91331 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfwr && wci_reqF$D_OUT[39:32] == 8'h18) - $display("[%0d] %m: fabDoneAvail Event", v__h89794); + $display("[%0d] %m: fabDoneAvail Event", v__h91331); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfwr) begin - v__h90263 = $time; + v__h91800 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfwr) $display("[%0d]: %m: WCI CONFIG WRITE Addr:%0x BE:%0x Data:%0x", - v__h90263, + v__h91800, wci_reqF$D_OUT[63:32], wci_reqF$D_OUT[67:64], wci_reqF$D_OUT[31:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_wci_cfrd && WILL_FIRE_RL_wci_cfwr) - $display("Error: \"bsv/inf/OCDP.bsv\", line 68, column 36: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and [RL_wci_cfwr] )\n fired in the same clock cycle.\n"); + if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_cfrd) + $display("Error: \"bsv/inf/OCDP.bsv\", line 68, column 26: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and [RL_wci_cfrd] )\n fired in the same clock cycle.\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_ctl_op_complete && wci_illegalEdge) begin - v__h16016 = $time; + v__h15896 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_ctl_op_complete && wci_illegalEdge) $display("[%0d]: %m: WCI ControlOp: ILLEGAL-EDGE Completed-transition edge:%x from:%x", - v__h16016, + v__h15896, wci_cEdge, wci_cState); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_ctl_op_complete && !wci_illegalEdge) begin - v__h15872 = $time; + v__h15752 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_ctl_op_complete && !wci_illegalEdge) $display("[%0d]: %m: WCI ControlOp: Completed-transition edge:%x from:%x to:%x", - v__h15872, + v__h15752, wci_cEdge, wci_cState, wci_nState); diff --git a/rtl/mkOCDP4B.v b/rtl/mkOCDP4B.v index 40a46317..f503faf1 100644 --- a/rtl/mkOCDP4B.v +++ b/rtl/mkOCDP4B.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2012.09.beta1 (build 29570, 2012-09.11) // -// On Tue Dec 11 16:21:37 EST 2012 +// On Tue Jan 1 09:13:31 EST 2013 // // // Ports: @@ -19,9 +19,9 @@ // wmiS0_SRespLast O 1 const // wmiS0_SFlag O 32 reg // wmiS0_SReset_n O 1 -// RDY_server_request_put O 1 -// server_response_get O 153 -// RDY_server_response_get O 1 +// RDY_server_request_put O 1 reg +// server_response_get O 153 reg +// RDY_server_response_get O 1 reg // pciDevice I 16 // CLK I 1 clock // RST_N I 1 reset @@ -40,7 +40,7 @@ // wmiS0_MData I 32 // wmiS0_MDataByteEn I 4 // wmiS0_arg_mFlag I 32 reg -// server_request_put I 153 +// server_request_put I 153 reg // wmiS0_MReqLast I 1 // wmiS0_MDataValid I 1 // wmiS0_MDataLast I 1 @@ -1810,38 +1810,38 @@ module mkOCDP4B(pciDevice, reg [63 : 0] v__h15697, v__h15872, v__h16016, - v__h39702, - v__h41753, - v__h46039, - v__h46380, - v__h47001, - v__h47351, - v__h48586, - v__h54850, - v__h54974, - v__h55182, - v__h55645, - v__h57878, - v__h62195, - v__h62717, - v__h63372, - v__h63720, - v__h63884, - v__h69047, - v__h80656, - v__h89024, - v__h89493, - v__h89656; - reg [31 : 0] IF_0_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2529, - IF_1_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2507, - IF_2_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2493, - IF_3_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2530, - IF_tlp_tlpBRAM_readReq_first__97_BITS_30_TO_29_ETC___d2433, - _theResult____h89640, - rdata__h81777; + v__h39786, + v__h41837, + v__h46123, + v__h46464, + v__h47085, + v__h47434, + v__h48668, + v__h54931, + v__h55054, + v__h55262, + v__h55725, + v__h57955, + v__h62270, + v__h62790, + v__h63443, + v__h63789, + v__h63951, + v__h69114, + v__h80718, + v__h89086, + v__h89555, + v__h89718; + reg [31 : 0] IF_0_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2509, + IF_1_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2510, + IF_2_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2511, + IF_3_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2512, + IF_tlp_tlpBRAM_readReq_first__97_BITS_30_TO_29_ETC___d2432, + _theResult____h89702, + rdata__h81839; reg [15 : 0] CASE_tlp_outDwRemain_BITS_1_TO_0_0xFFF0_0b0_0x_ETC__q4; reg [3 : 0] CASE_tlp_lastRuleFired_10_1_tlp_lastRuleFired__ETC__q1; - reg [1 : 0] lowAddr10__h28410, x__h28539, x__h28562; + reg [1 : 0] lowAddr10__h28494, x__h28623, x__h28646; reg CASE_dpControl_BITS_1_TO_0_NOT_bml_fabDone_0_N_ETC__q7, CASE_dpControl_BITS_1_TO_0_NOT_bml_fabDone_0_N_ETC__q8, CASE_dpControl_BITS_1_TO_0_bml_fabDone_0_bml_f_ETC__q3, @@ -1849,117 +1849,117 @@ module mkOCDP4B(pciDevice, CASE_tlp_tlpBRAM_mReqFD_OUT_BITS_51_TO_50_NOT_ETC__q5, CASE_tlp_tlpBRAM_readReqD_OUT_BITS_30_TO_29_N_ETC__q17, CASE_wmi_p4B_NOT_wmi_p4B_EQ_3_OR_bram_serverAd_ETC__q18, - IF_0_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2464, + IF_0_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2469, IF_0_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d675, - IF_1_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2465, + IF_1_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2470, IF_1_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d685, - IF_2_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2466, + IF_2_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2471, IF_2_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d695, - IF_3_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2467, + IF_3_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2472, IF_3_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d705, - IF_bml_dpControl_wget__029_BITS_1_TO_0_035_EQ__ETC___d2106, + IF_bml_dpControl_wget__026_BITS_1_TO_0_032_EQ__ETC___d2103, IF_tlp_tlpBRAM_readReq_first__97_BITS_30_TO_29_ETC___d912, - IF_wmi_addr_855_BITS_3_TO_2_856_EQ_0_857_THEN__ETC___d2860, - IF_wmi_p4B_912_EQ_1_915_THEN_bram_serverAdapte_ETC___d1921; - wire [127 : 0] IF_tlp_fabMesgAddrMS_186_EQ_0_187_THEN_0_ELSE__ETC___d1461, + IF_wmi_addr_852_BITS_3_TO_2_853_EQ_0_854_THEN__ETC___d2853, + IF_wmi_p4B_909_EQ_1_912_THEN_bram_serverAdapte_ETC___d1918; + wire [127 : 0] IF_tlp_fabMesgAddrMS_186_EQ_0_187_THEN_0_ELSE__ETC___d1460, IF_tlp_fabMetaAddrMS_265_EQ_0_266_THEN_4_ELSE__ETC___d1356, IF_tlp_tlpBRAM_readReq_first__97_BITS_30_TO_29_ETC___d1037, IF_tlp_tlpBRAM_readReq_first__97_BITS_30_TO_29_ETC___d1042, - pkt__h70068, - rdata__h33850, - w_data__h46507, - w_data__h46644, - w_data__h51409, - w_data__h64198, - w_data__h65286, - w_data__h65532; + pkt__h70132, + rdata__h33934, + w_data__h46591, + w_data__h46728, + w_data__h51490, + w_data__h64265, + w_data__h65353, + w_data__h65599; wire [63 : 0] wti_nowReq_BITS_63_TO_0__q2; - wire [31 : 0] bml_fabFlowAddr_068_PLUS_bml_fabFlowSize_069___d2666, - mesgMeta_opcode__h80054, - nowLS__h44844, - nowLS__h60998, - nowMS__h43901, - nowMS__h60057, - opcode__h42670, - opcode__h58837, - rdat__h89719, - rdat__h89727, - rdat__h89735, - rdat__h89743, - rdat__h89751, - rdat__h89759, - rdat__h89767, - rdat__h89788, - rdat__h89795, - rdat__h89808, - rdat__h89815, - rdat__h89822, - rdat__h90086, - rdat__h90136, - rdat__h90236, - rdat__h90294, - rdat__h90316, - rdat__h90326, - rdat__h90448, - rdat__h90569, - rdat__h90598, - rdat__h90627, - rdat__h90656, - rdat__h90686, - rdat__h90720, - rdat__h90753, - rdat__h90787, - rresp_data__h28457, - x3__h80014, - x__h40887, - x__h45847, - x__h56804, - x__h61968, - y__h46213, - y__h46773, - y__h62350, - y_avValue__h81613, - y_avValue__h81633, - y_avValue__h81653, - y_avValue__h81673; + wire [31 : 0] bml_fabFlowAddr_065_PLUS_bml_fabFlowSize_066___d2653, + mesgMeta_opcode__h80116, + nowLS__h44928, + nowLS__h61073, + nowMS__h43985, + nowMS__h60132, + opcode__h42754, + opcode__h58912, + rdat__h89781, + rdat__h89789, + rdat__h89797, + rdat__h89805, + rdat__h89813, + rdat__h89821, + rdat__h89829, + rdat__h89850, + rdat__h89857, + rdat__h89870, + rdat__h89877, + rdat__h89884, + rdat__h90148, + rdat__h90198, + rdat__h90298, + rdat__h90356, + rdat__h90378, + rdat__h90388, + rdat__h90510, + rdat__h90631, + rdat__h90660, + rdat__h90689, + rdat__h90718, + rdat__h90748, + rdat__h90782, + rdat__h90815, + rdat__h90849, + rresp_data__h28541, + x3__h80076, + x__h40971, + x__h45931, + x__h56883, + x__h62043, + y__h46297, + y__h46857, + y__h62423, + y_avValue__h81675, + y_avValue__h81695, + y_avValue__h81715, + y_avValue__h81735; wire [16 : 0] tlp_mesgLengthRemainPull_PLUS_3__q15, tlp_mesgLengthRemainPush_PLUS_3__q16, - x__h46132, - x__h62287, - y__h46119, - y__h46134, - y__h62279, - y__h62289, - y__h63671; - wire [15 : 0] w_be__h47101, - x__h86368, - x__h87496, - x__h87501, - x__h87608, - x__h87645, - x__h87727, - x__h87732, - x__h87766, - x__h87771, - y__h46261, - y__h62959; - wire [12 : 0] spanToNextPage__h46093, - spanToNextPage__h62253, - thisRequestLength__h46094, - thisRequestLength__h62254, + x__h46216, + x__h62360, + y__h46203, + y__h46218, + y__h62352, + y__h62362, + y__h63740; + wire [15 : 0] w_be__h47184, + x__h86430, + x__h87558, + x__h87563, + x__h87670, + x__h87707, + x__h87789, + x__h87794, + x__h87828, + x__h87833, + y__h46345, + y__h63030; + wire [12 : 0] spanToNextPage__h46177, + spanToNextPage__h62326, + thisRequestLength__h46178, + thisRequestLength__h62327, tlp_tlpBRAM_readNxtDWAddr_PLUS_1__q13, tlp_tlpBRAM_readNxtDWAddr_PLUS_2__q14, tlp_tlpBRAM_readNxtDWAddr_PLUS_3__q12, tlp_tlpBRAM_writeDWAddr_PLUS_1__q10, tlp_tlpBRAM_writeDWAddr_PLUS_2__q11, tlp_tlpBRAM_writeDWAddr_PLUS_3__q9, - y__h17488, - y__h26049; - wire [11 : 0] byteCount__h28412, x__h28530, x__h28532, y__h28531, y__h28533; - wire [9 : 0] y__h17555, y__h26037, y__h29472, y__h46739; - wire [7 : 0] rreq_tag__h46309, tag__h62529, tagm__h62748; - wire [6 : 0] lowAddr__h28411; - wire [3 : 0] lastBE__h46542, lastBE__h62561; + y__h17572, + y__h26133; + wire [11 : 0] byteCount__h28496, x__h28614, x__h28616, y__h28615, y__h28617; + wire [9 : 0] y__h17639, y__h26121, y__h29556, y__h46823; + wire [7 : 0] rreq_tag__h46393, tag__h62602, tagm__h62820; + wire [6 : 0] lowAddr__h28495; + wire [3 : 0] lastBE__h46626, lastBE__h62634; wire [2 : 0] bram_serverAdapterA_1_cnt_44_PLUS_IF_bram_serv_ETC___d150, bram_serverAdapterA_2_cnt_62_PLUS_IF_bram_serv_ETC___d268, bram_serverAdapterA_3_cnt_80_PLUS_IF_bram_serv_ETC___d386, @@ -1976,62 +1976,62 @@ module mkOCDP4B(pciDevice, ab__h5965, ab__h7507, ab__h8911, - idx__h19187, - idx__h21418, - idx__h22722, - idx__h24026, - idx__h26267, - idx__h26735, - idx__h27108, - idx__h27481, - tlp_tlpBRAM_readReq_first__97_BITS_30_TO_29_99_ETC___d2439; + idx__h19271, + idx__h21502, + idx__h22806, + idx__h24110, + idx__h26351, + idx__h26819, + idx__h27192, + idx__h27565, + tlp_tlpBRAM_readReq_first__97_BITS_30_TO_29_99_ETC___d2433; wire IF_1_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d708, IF_tlp_tlpBRAM_readReq_first__97_BITS_30_TO_29_ETC___d921, - IF_wmi_p4B_912_EQ_0_913_THEN_bram_serverAdapte_ETC___d1926, - NOT_bml_lclBufDone_053_120_AND_IF_bml_dpContro_ETC___d2133, - NOT_wmi_wrActive_827_828_OR_NOT_wmi_rdActive_8_ETC___d1837, + IF_wmi_p4B_909_EQ_0_910_THEN_bram_serverAdapte_ETC___d1923, + NOT_bml_lclBufDone_050_117_AND_IF_bml_dpContro_ETC___d2130, + NOT_wmi_wrActive_824_825_OR_NOT_wmi_rdActive_8_ETC___d1834, _dfoo5, - bml_crdBuf_value_011_EQ_bml_crdBuf_modulus_bw__ETC___d2806, - bml_fabBuf_value_996_EQ_bml_fabBuf_modulus_bw__ETC___d2807, - bml_lclBufDone_053_AND_IF_bml_dpControl_wget___ETC___d2477, - bml_lclBuf_value_966_EQ_bml_lclBuf_modulus_bw__ETC___d2825, - bml_remBuf_value_981_EQ_bml_remBuf_modulus_bw__ETC___d2826, - bram_serverAdapterA_1_cnt_44_SLT_3___d2671, - bram_serverAdapterA_2_cnt_62_SLT_3___d2672, + bml_crdBuf_value_008_EQ_bml_crdBuf_modulus_bw__ETC___d2800, + bml_fabBuf_value_993_EQ_bml_fabBuf_modulus_bw__ETC___d2801, + bml_lclBufDone_050_AND_IF_bml_dpControl_wget___ETC___d2480, + bml_lclBuf_value_963_EQ_bml_lclBuf_modulus_bw__ETC___d2819, + bml_remBuf_value_978_EQ_bml_remBuf_modulus_bw__ETC___d2820, + bram_serverAdapterA_1_cnt_44_SLT_3___d2658, + bram_serverAdapterA_2_cnt_62_SLT_3___d2418, bram_serverAdapterA_2_outDataCore_notEmpty__38_ETC___d993, - bram_serverAdapterA_3_cnt_80_SLT_3___d2504, - bram_serverAdapterA_cnt_6_SLT_3___d2670, + bram_serverAdapterA_3_cnt_80_SLT_3___d2659, + bram_serverAdapterA_cnt_6_SLT_3___d2657, bram_serverAdapterA_outDataCore_notEmpty_OR_br_ETC___d995, - bram_serverAdapterB_1_cnt_03_SLT_3___d1777, - bram_serverAdapterB_1_outData_outData_whas__79_ETC___d1805, - bram_serverAdapterB_2_cnt_21_SLT_3___d1778, - bram_serverAdapterB_3_cnt_39_SLT_3___d1779, - bram_serverAdapterB_cnt_5_SLT_3___d1776, + bram_serverAdapterB_1_cnt_03_SLT_3___d1774, + bram_serverAdapterB_1_outData_outData_whas__79_ETC___d1802, + bram_serverAdapterB_2_cnt_21_SLT_3___d1775, + bram_serverAdapterB_3_cnt_39_SLT_3___d1776, + bram_serverAdapterB_cnt_5_SLT_3___d1773, hasPull_AND_tlp_dpControl_wget__072_BITS_7_TO__ETC___d1341, - hasPull_AND_tlp_dpControl_wget__072_BITS_7_TO__ETC___d1382, - hasPull_AND_tlp_dpControl_wget__072_BITS_7_TO__ETC___d1434, - hasPull_AND_tlp_dpControl_wget__072_BITS_7_TO__ETC___d1473, - hasPull_AND_tlp_dpControl_wget__072_BITS_7_TO__ETC___d1493, - hasPull_AND_tlp_dpControl_wget__072_BITS_7_TO__ETC___d1518, + hasPull_AND_tlp_dpControl_wget__072_BITS_7_TO__ETC___d1381, + hasPull_AND_tlp_dpControl_wget__072_BITS_7_TO__ETC___d1433, + hasPull_AND_tlp_dpControl_wget__072_BITS_7_TO__ETC___d1471, + hasPull_AND_tlp_dpControl_wget__072_BITS_7_TO__ETC___d1491, + hasPull_AND_tlp_dpControl_wget__072_BITS_7_TO__ETC___d1516, hasPush_AND_tlp_dpControl_wget__072_BITS_7_TO__ETC___d1093, hasPush_AND_tlp_dpControl_wget__072_BITS_7_TO__ETC___d1166, - hasPush_AND_tlp_dpControl_wget__072_BITS_7_TO__ETC___d1206, + hasPush_AND_tlp_dpControl_wget__072_BITS_7_TO__ETC___d1207, hasPush_AND_tlp_dpControl_wget__072_BITS_7_TO__ETC___d1263, - tlp_dmaPullRemainDWLen_481_ULE_tlp_dmaPullRema_ETC___d2667, - tlp_dmaPullRemainDWSub_495_ULE_4___d2668, - tlp_inF_first__367_BITS_63_TO_56_370_EQ_pciDev_ETC___d1380, - tlp_inF_first__367_BIT_152_570_AND_NOT_tlp_inF_ETC___d1595, - tlp_outDwRemain_237_ULE_4___d2605, + tlp_dmaPullRemainDWLen_479_ULE_tlp_dmaPullRema_ETC___d2654, + tlp_dmaPullRemainDWSub_493_ULE_4___d2655, + tlp_inF_first__366_BITS_63_TO_56_369_EQ_pciDev_ETC___d1379, + tlp_inF_first__366_BIT_152_568_AND_NOT_tlp_inF_ETC___d1592, + tlp_outDwRemain_238_ULE_4___d2590, tlp_tlpBRAM_mReqF_first__18_BIT_60_02_OR_IF_tl_ETC___d813, tlp_tlpBRAM_mReqF_first__18_BIT_63_19_OR_IF_tl_ETC___d634, - tlp_tlpBRAM_mRespF_first__108_BITS_71_TO_62_20_ETC___d2421, + tlp_tlpBRAM_mRespF_first__108_BITS_71_TO_62_20_ETC___d2442, tlp_tlpBRAM_rdRespDwRemain_024_ULE_4___d1026, tlp_tlpBRAM_readRemainDWLen_46_ULE_4___d847, - tlp_tlpBRAM_writeRemainDWLen_62_ULE_1___d2437, - tlp_tlpBRAM_writeRemainDWLen_62_ULE_2___d2430, - tlp_tlpBRAM_writeRemainDWLen_62_ULE_3___d2413, - wmi_dpControl_whas__763_AND_bram_serverAdapter_ETC___d1809, - wmi_wmi_operateD_716_AND_wmi_wmi_peerIsReady_7_ETC___d1891; + tlp_tlpBRAM_writeRemainDWLen_62_ULE_1___d2440, + tlp_tlpBRAM_writeRemainDWLen_62_ULE_2___d2431, + tlp_tlpBRAM_writeRemainDWLen_62_ULE_3___d2441, + wmi_dpControl_whas__760_AND_bram_serverAdapter_ETC___d1806, + wmi_wmi_operateD_713_AND_wmi_wmi_peerIsReady_7_ETC___d1888; // value method wci_s_sResp assign wci_s_SResp = wci_respF_q_0[33:32] ; @@ -2264,26 +2264,26 @@ module mkOCDP4B(pciDevice, .EMPTY_N(bram_serverAdapterB_outDataCore$EMPTY_N)); // submodule tlp_inF - arSRLFIFOD #(.width(32'd153), .l2depth(32'd4)) tlp_inF(.CLK(CLK), - .RST_N(RST_N), - .D_IN(tlp_inF$D_IN), - .DEQ(tlp_inF$DEQ), - .ENQ(tlp_inF$ENQ), - .CLR(tlp_inF$CLR), - .EMPTY_N(tlp_inF$EMPTY_N), - .D_OUT(tlp_inF$D_OUT), - .FULL_N(tlp_inF$FULL_N)); + FIFO2 #(.width(32'd153), .guarded(32'd1)) tlp_inF(.RST(RST_N), + .CLK(CLK), + .D_IN(tlp_inF$D_IN), + .ENQ(tlp_inF$ENQ), + .DEQ(tlp_inF$DEQ), + .CLR(tlp_inF$CLR), + .D_OUT(tlp_inF$D_OUT), + .FULL_N(tlp_inF$FULL_N), + .EMPTY_N(tlp_inF$EMPTY_N)); // submodule tlp_outF - arSRLFIFOD #(.width(32'd153), .l2depth(32'd4)) tlp_outF(.CLK(CLK), - .RST_N(RST_N), - .D_IN(tlp_outF$D_IN), - .DEQ(tlp_outF$DEQ), - .ENQ(tlp_outF$ENQ), - .CLR(tlp_outF$CLR), - .EMPTY_N(tlp_outF$EMPTY_N), - .D_OUT(tlp_outF$D_OUT), - .FULL_N(tlp_outF$FULL_N)); + FIFO2 #(.width(32'd153), .guarded(32'd1)) tlp_outF(.RST(RST_N), + .CLK(CLK), + .D_IN(tlp_outF$D_IN), + .ENQ(tlp_outF$ENQ), + .DEQ(tlp_outF$DEQ), + .CLR(tlp_outF$CLR), + .D_OUT(tlp_outF$D_OUT), + .FULL_N(tlp_outF$FULL_N), + .EMPTY_N(tlp_outF$EMPTY_N)); // submodule tlp_tailEventF FIFO2 #(.width(32'd1), .guarded(32'd1)) tlp_tailEventF(.RST(RST_N), @@ -2421,12 +2421,12 @@ module mkOCDP4B(pciDevice, // rule RL_tlp_dmaPushResponseHeader assign WILL_FIRE_RL_tlp_dmaPushResponseHeader = - tlp_outF$FULL_N && tlp_tlpBRAM_mRespF$EMPTY_N && - hasPush_AND_tlp_dpControl_wget__072_BITS_7_TO__ETC___d1206 ; + tlp_tlpBRAM_mRespF$EMPTY_N && tlp_outF$FULL_N && + hasPush_AND_tlp_dpControl_wget__072_BITS_7_TO__ETC___d1207 ; // rule RL_tlp_dmaPushResponseBody assign WILL_FIRE_RL_tlp_dmaPushResponseBody = - tlp_outF$FULL_N && tlp_tlpBRAM_mRespF$EMPTY_N && hasPush && + tlp_tlpBRAM_mRespF$EMPTY_N && tlp_outF$FULL_N && hasPush && dpControl[7:4] == 4'd0 && dpControl[3:2] == 2'd1 && dpControl[1:0] == 2'd1 && @@ -2469,17 +2469,17 @@ module mkOCDP4B(pciDevice, // rule RL_tlp_dmaRespHeadFarMeta assign WILL_FIRE_RL_tlp_dmaRespHeadFarMeta = - tlp_inF$EMPTY_N && tlp_tlpBRAM_mReqF$FULL_N && - hasPull_AND_tlp_dpControl_wget__072_BITS_7_TO__ETC___d1382 ; + tlp_tlpBRAM_mReqF$FULL_N && tlp_inF$EMPTY_N && + hasPull_AND_tlp_dpControl_wget__072_BITS_7_TO__ETC___d1381 ; // rule RL_tlp_dmaPullTailEvent assign WILL_FIRE_RL_tlp_dmaPullTailEvent = tlp_tailEventF$FULL_N && - hasPull_AND_tlp_dpControl_wget__072_BITS_7_TO__ETC___d1518 ; + hasPull_AND_tlp_dpControl_wget__072_BITS_7_TO__ETC___d1516 ; // rule RL_tlp_dmaRespBodyFarMeta assign CAN_FIRE_RL_tlp_dmaRespBodyFarMeta = - tlp_inF$EMPTY_N && tlp_tlpBRAM_mReqF$FULL_N && hasPull && + tlp_tlpBRAM_mReqF$FULL_N && tlp_inF$EMPTY_N && hasPull && dpControl[7:4] == 4'd0 && dpControl[3:2] == 2'd2 && dpControl[1:0] == 2'd1 && @@ -2491,15 +2491,15 @@ module mkOCDP4B(pciDevice, // rule RL_tlp_dmaPullResponseHeader assign WILL_FIRE_RL_tlp_dmaPullResponseHeader = - tlp_inF$EMPTY_N && tlp_tlpBRAM_mReqF$FULL_N && - hasPull_AND_tlp_dpControl_wget__072_BITS_7_TO__ETC___d1473 && + tlp_tlpBRAM_mReqF$FULL_N && tlp_inF$EMPTY_N && + hasPull_AND_tlp_dpControl_wget__072_BITS_7_TO__ETC___d1471 && !WILL_FIRE_RL_tlp_dmaRespBodyFarMeta && !WILL_FIRE_RL_tlp_dmaRespHeadFarMeta ; // rule RL_tlp_dmaPullResponseBody assign WILL_FIRE_RL_tlp_dmaPullResponseBody = - tlp_inF$EMPTY_N && tlp_tlpBRAM_mReqF$FULL_N && - hasPull_AND_tlp_dpControl_wget__072_BITS_7_TO__ETC___d1493 && + tlp_tlpBRAM_mReqF$FULL_N && tlp_inF$EMPTY_N && + hasPull_AND_tlp_dpControl_wget__072_BITS_7_TO__ETC___d1491 && !WILL_FIRE_RL_tlp_dmaRespBodyFarMeta && !WILL_FIRE_RL_tlp_dmaRespHeadFarMeta ; @@ -2554,13 +2554,13 @@ module mkOCDP4B(pciDevice, // rule RL_tlp_dmaPullRequestFarMesg assign WILL_FIRE_RL_tlp_dmaPullRequestFarMesg = tlp_outF$FULL_N && - hasPull_AND_tlp_dpControl_wget__072_BITS_7_TO__ETC___d1434 && + hasPull_AND_tlp_dpControl_wget__072_BITS_7_TO__ETC___d1433 && !WILL_FIRE_RL_tlp_dmaRespBodyFarMeta && !WILL_FIRE_RL_tlp_dmaRespHeadFarMeta ; // rule RL_tlp_dataXmt_Header assign WILL_FIRE_RL_tlp_dataXmt_Header = - tlp_outF$FULL_N && tlp_tlpBRAM_mRespF$EMPTY_N && + tlp_tlpBRAM_mRespF$EMPTY_N && tlp_outF$FULL_N && !tlp_tlpBRAM_mRespF$D_OUT[138] && tlp_tlpBRAM_mRespF$D_OUT[89:88] == 2'd1 && !tlp_tlpXmtBusy && @@ -2572,7 +2572,7 @@ module mkOCDP4B(pciDevice, // rule RL_tlp_dataXmt_Body assign WILL_FIRE_RL_tlp_dataXmt_Body = - tlp_outF$FULL_N && tlp_tlpBRAM_mRespF$EMPTY_N && + tlp_tlpBRAM_mRespF$EMPTY_N && tlp_outF$FULL_N && tlp_tlpBRAM_mRespF$D_OUT[138] && tlp_tlpBRAM_mRespF$D_OUT[137:136] == 2'd1 && !WILL_FIRE_RL_tlp_dmaTailEventSender && @@ -2591,7 +2591,7 @@ module mkOCDP4B(pciDevice, assign WILL_FIRE_RL_tlp_tlpBRAM_writeData = tlp_tlpBRAM_mReqF$EMPTY_N && (IF_0_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d675 || - bram_serverAdapterA_cnt_6_SLT_3___d2670) && + bram_serverAdapterA_cnt_6_SLT_3___d2657) && IF_1_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d708 && tlp_tlpBRAM_mReqF$D_OUT[129:128] == 2'd1 ; @@ -2605,10 +2605,10 @@ module mkOCDP4B(pciDevice, // rule RL_tlp_tlpBRAM_read_NextReq assign WILL_FIRE_RL_tlp_tlpBRAM_read_NextReq = - bram_serverAdapterA_cnt_6_SLT_3___d2670 && - bram_serverAdapterA_1_cnt_44_SLT_3___d2671 && - bram_serverAdapterA_2_cnt_62_SLT_3___d2672 && - bram_serverAdapterA_3_cnt_80_SLT_3___d2504 && + bram_serverAdapterA_cnt_6_SLT_3___d2657 && + bram_serverAdapterA_1_cnt_44_SLT_3___d2658 && + bram_serverAdapterA_2_cnt_62_SLT_3___d2418 && + bram_serverAdapterA_3_cnt_80_SLT_3___d2659 && tlp_tlpBRAM_mReqF$EMPTY_N && tlp_tlpBRAM_readStarted && tlp_tlpBRAM_mReqF$D_OUT[129:128] != 2'd0 && @@ -2657,10 +2657,10 @@ module mkOCDP4B(pciDevice, // rule RL_wmi_reqMetadata assign CAN_FIRE_RL_wmi_reqMetadata = - bram_serverAdapterB_cnt_5_SLT_3___d1776 && - bram_serverAdapterB_1_cnt_03_SLT_3___d1777 && - bram_serverAdapterB_2_cnt_21_SLT_3___d1778 && - bram_serverAdapterB_3_cnt_39_SLT_3___d1779 && + bram_serverAdapterB_cnt_5_SLT_3___d1773 && + bram_serverAdapterB_1_cnt_03_SLT_3___d1774 && + bram_serverAdapterB_2_cnt_21_SLT_3___d1775 && + bram_serverAdapterB_3_cnt_39_SLT_3___d1776 && dpControl[3:2] != 2'd1 && !wmi_mesgMeta[128] && wmi_mesgBufReady && @@ -2673,13 +2673,13 @@ module mkOCDP4B(pciDevice, // rule RL_wmi_doWriteFinalize assign WILL_FIRE_RL_wmi_doWriteFinalize = - wmi_wmi_operateD_716_AND_wmi_wmi_peerIsReady_7_ETC___d1891 && + wmi_wmi_operateD_713_AND_wmi_wmi_peerIsReady_7_ETC___d1888 && wmi_wrFinalize ; // rule RL_wmi_respMetadata assign CAN_FIRE_RL_wmi_respMetadata = wmi_wmi_operateD && wmi_wmi_peerIsReady && - wmi_dpControl_whas__763_AND_bram_serverAdapter_ETC___d1809 && + wmi_dpControl_whas__760_AND_bram_serverAdapter_ETC___d1806 && dpControl[3:2] != 2'd1 && !wmi_mesgMeta[128] && wmi_mesgBufReady && @@ -2689,7 +2689,7 @@ module mkOCDP4B(pciDevice, // rule RL_wmi_doReadReq assign WILL_FIRE_RL_wmi_doReadReq = - IF_wmi_addr_855_BITS_3_TO_2_856_EQ_0_857_THEN__ETC___d2860 && + IF_wmi_addr_852_BITS_3_TO_2_853_EQ_0_854_THEN__ETC___d2853 && wmi_rdActive && !WILL_FIRE_RL_wmi_doWriteReq && !WILL_FIRE_RL_wmi_doWriteFinalize ; @@ -2698,7 +2698,7 @@ module mkOCDP4B(pciDevice, assign WILL_FIRE_RL_wmi_doReadResp = wmi_wmi_respF_c_r != 2'd2 && wmi_wmi_operateD && wmi_wmi_peerIsReady && - IF_wmi_p4B_912_EQ_0_913_THEN_bram_serverAdapte_ETC___d1926 && + IF_wmi_p4B_909_EQ_0_910_THEN_bram_serverAdapte_ETC___d1923 && wmi_bytesRemainResp != 14'd0 ; // rule RL_bram_serverAdapterB_outData_enqAndDeq @@ -2719,7 +2719,7 @@ module mkOCDP4B(pciDevice, assign WILL_FIRE_RL_bram_serverAdapterB_2_outData_enqAndDeq = bram_serverAdapterB_2_outDataCore$EMPTY_N && bram_serverAdapterB_2_outDataCore$FULL_N && - bram_serverAdapterB_2_cnt_2$whas && + bram_serverAdapterB_2_outData_deqCalled$whas && bram_serverAdapterB_2_outData_enqData$whas ; // rule RL_bram_serverAdapterB_3_outData_enqAndDeq @@ -2733,7 +2733,7 @@ module mkOCDP4B(pciDevice, assign CAN_FIRE_RL_wmi_getRequest = wmi_wmi_operateD && wmi_wmi_peerIsReady && !wmi_wmi_blockReq && wmi_wmi_reqF$EMPTY_N && - NOT_wmi_wrActive_827_828_OR_NOT_wmi_rdActive_8_ETC___d1837 && + NOT_wmi_wrActive_824_825_OR_NOT_wmi_rdActive_8_ETC___d1834 && wmi_bufDwell == 2'd0 ; assign WILL_FIRE_RL_wmi_getRequest = CAN_FIRE_RL_wmi_getRequest && !WILL_FIRE_RL_wmi_doReadReq && @@ -2742,7 +2742,7 @@ module mkOCDP4B(pciDevice, // rule RL_wmi_doWriteReq assign CAN_FIRE_RL_wmi_doWriteReq = wmi_wmi_operateD && wmi_wmi_peerIsReady && wmi_wmi_dhF$EMPTY_N && - IF_wmi_addr_855_BITS_3_TO_2_856_EQ_0_857_THEN__ETC___d2860 && + IF_wmi_addr_852_BITS_3_TO_2_853_EQ_0_854_THEN__ETC___d2853 && wmi_wrActive ; assign WILL_FIRE_RL_wmi_doWriteReq = CAN_FIRE_RL_wmi_doWriteReq && !WILL_FIRE_RL_wmi_doWriteFinalize ; @@ -2847,14 +2847,14 @@ module mkOCDP4B(pciDevice, WILL_FIRE_RL_bml_remAdvance && dpControl[1:0] == 2'd1 ; assign MUX_bml_lclBufsAR$write_1__SEL_1 = wci_cState == 3'd2 && - (IF_bml_dpControl_wget__029_BITS_1_TO_0_035_EQ__ETC___d2106 && + (IF_bml_dpControl_wget__026_BITS_1_TO_0_032_EQ__ETC___d2103 && !bml_lclBufStart || CASE_dpControl_BITS_1_TO_0_NOT_bml_fabDone_0_N_ETC__q8 && bml_lclBufStart) ; assign MUX_bml_lclBufsCF$write_1__SEL_1 = wci_cState == 3'd2 && - (bml_lclBufDone_053_AND_IF_bml_dpControl_wget___ETC___d2477 || - NOT_bml_lclBufDone_053_120_AND_IF_bml_dpContro_ETC___d2133) ; + (bml_lclBufDone_050_AND_IF_bml_dpControl_wget___ETC___d2480 || + NOT_bml_lclBufDone_050_117_AND_IF_bml_dpContro_ETC___d2130) ; assign MUX_bml_lclCredit$write_1__SEL_1 = WILL_FIRE_RL_bml_lcredit && (bml_lclBufDone && !bml_remStart || @@ -2869,7 +2869,7 @@ module mkOCDP4B(pciDevice, tlp_tlpBRAM_mReqF$D_OUT[30:29] == 2'd0 ; assign MUX_bram_memory$a_put_1__SEL_3 = WILL_FIRE_RL_tlp_tlpBRAM_writeData && - IF_0_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2464 ; + IF_0_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2469 ; assign MUX_bram_memory$b_put_1__SEL_1 = WILL_FIRE_RL_wmi_doReadReq && wmi_addr[3:2] == 2'd0 ; assign MUX_bram_memory$b_put_1__SEL_2 = @@ -2884,7 +2884,7 @@ module mkOCDP4B(pciDevice, tlp_tlpBRAM_mReqF$D_OUT[30:29] == 2'd1 ; assign MUX_bram_memory_1$a_put_1__SEL_3 = WILL_FIRE_RL_tlp_tlpBRAM_writeData && - IF_1_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2465 ; + IF_1_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2470 ; assign MUX_bram_memory_1$b_put_1__SEL_1 = WILL_FIRE_RL_wmi_doReadReq && wmi_addr[3:2] == 2'd1 ; assign MUX_bram_memory_1$b_put_1__SEL_2 = @@ -2899,7 +2899,7 @@ module mkOCDP4B(pciDevice, tlp_tlpBRAM_mReqF$D_OUT[30:29] == 2'd2 ; assign MUX_bram_memory_2$a_put_1__SEL_3 = WILL_FIRE_RL_tlp_tlpBRAM_writeData && - IF_2_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2466 ; + IF_2_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2471 ; assign MUX_bram_memory_2$b_put_1__SEL_1 = WILL_FIRE_RL_wmi_doReadReq && wmi_addr[3:2] == 2'd2 ; assign MUX_bram_memory_2$b_put_1__SEL_2 = @@ -2914,7 +2914,7 @@ module mkOCDP4B(pciDevice, tlp_tlpBRAM_mReqF$D_OUT[30:29] == 2'd3 ; assign MUX_bram_memory_3$a_put_1__SEL_3 = WILL_FIRE_RL_tlp_tlpBRAM_writeData && - IF_3_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2467 ; + IF_3_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2472 ; assign MUX_bram_memory_3$b_put_1__SEL_1 = WILL_FIRE_RL_wmi_doReadReq && wmi_addr[3:2] == 2'd3 ; assign MUX_bram_memory_3$b_put_1__SEL_2 = @@ -2935,7 +2935,7 @@ module mkOCDP4B(pciDevice, WILL_FIRE_RL_tlp_dmaXmtTailEvent ; assign MUX_tlp_tlpBRAM_mReqF$enq_1__SEL_1 = WILL_FIRE_RL_tlp_tlpRcv && - tlp_inF_first__367_BIT_152_570_AND_NOT_tlp_inF_ETC___d1595 ; + tlp_inF_first__366_BIT_152_568_AND_NOT_tlp_inF_ETC___d1592 ; assign MUX_tlp_tlpBRAM_mReqF$enq_1__SEL_6 = WILL_FIRE_RL_tlp_dmaPullResponseBody || WILL_FIRE_RL_tlp_dmaRespBodyFarMeta ; @@ -2954,16 +2954,16 @@ module mkOCDP4B(pciDevice, tlp_fabFlowAddrMS != 32'd0 ; assign MUX_tlp_tlpXmtBusy$write_1__SEL_3 = WILL_FIRE_RL_tlp_dataXmt_Header && - !tlp_tlpBRAM_mRespF_first__108_BITS_71_TO_62_20_ETC___d2421 ; + !tlp_tlpBRAM_mRespF_first__108_BITS_71_TO_62_20_ETC___d2442 ; assign MUX_tlp_tlpXmtBusy$write_1__PSEL_4 = WILL_FIRE_RL_tlp_dataXmt_Body || WILL_FIRE_RL_tlp_dmaPushResponseBody ; assign MUX_tlp_tlpXmtBusy$write_1__SEL_4 = MUX_tlp_tlpXmtBusy$write_1__PSEL_4 && - tlp_outDwRemain_237_ULE_4___d2605 ; + tlp_outDwRemain_238_ULE_4___d2590 ; assign MUX_tlp_xmtMetaOK$write_1__SEL_3 = WILL_FIRE_RL_tlp_dmaPushResponseBody && - tlp_outDwRemain_237_ULE_4___d2605 && + tlp_outDwRemain_238_ULE_4___d2590 && tlp_tlpBRAM_mRespF$D_OUT[135:128] == 8'h01 ; assign MUX_tlp_xmtMetaOK$write_1__SEL_4 = WILL_FIRE_RL_tlp_dmaPushResponseHeader && @@ -3024,79 +3024,79 @@ module mkOCDP4B(pciDevice, WILL_FIRE_RL_wmi_doWriteReq && wmi_bytesRemainReq == 14'd4 && wmi_doneWithMesg ; assign MUX_bml_crdBuf_value$write_1__VAL_3 = - bml_crdBuf_value_011_EQ_bml_crdBuf_modulus_bw__ETC___d2806 ? + bml_crdBuf_value_008_EQ_bml_crdBuf_modulus_bw__ETC___d2800 ? 16'd0 : bml_crdBuf_value + 16'd1 ; assign MUX_bml_fabBuf_value$write_1__VAL_3 = - bml_fabBuf_value_996_EQ_bml_fabBuf_modulus_bw__ETC___d2807 ? + bml_fabBuf_value_993_EQ_bml_fabBuf_modulus_bw__ETC___d2801 ? 16'd0 : bml_fabBuf_value + 16'd1 ; assign MUX_bml_fabBufsAvail$write_1__VAL_1 = - (bml_fabAvail && !bml_remStart) ? x__h87727 : x__h87732 ; + (bml_fabAvail && !bml_remStart) ? x__h87789 : x__h87794 ; assign MUX_bml_fabBufsAvail$write_1__VAL_2 = - (dpControl[3:2] == 2'd1) ? x__h86368 : 16'd0 ; + (dpControl[3:2] == 2'd1) ? x__h86430 : 16'd0 ; assign MUX_bml_fabFlowAddr$write_1__VAL_1 = - bml_fabBuf_value_996_EQ_bml_fabBuf_modulus_bw__ETC___d2807 ? + bml_fabBuf_value_993_EQ_bml_fabBuf_modulus_bw__ETC___d2801 ? bml_fabFlowBase : - bml_fabFlowAddr_068_PLUS_bml_fabFlowSize_069___d2666 ; + bml_fabFlowAddr_065_PLUS_bml_fabFlowSize_066___d2653 ; assign MUX_bml_fabFlowAddr$write_1__VAL_3 = - bml_crdBuf_value_011_EQ_bml_crdBuf_modulus_bw__ETC___d2806 ? + bml_crdBuf_value_008_EQ_bml_crdBuf_modulus_bw__ETC___d2800 ? bml_fabFlowBase : - bml_fabFlowAddr_068_PLUS_bml_fabFlowSize_069___d2666 ; + bml_fabFlowAddr_065_PLUS_bml_fabFlowSize_066___d2653 ; assign MUX_bml_fabMesgAddr$write_1__VAL_1 = - bml_fabBuf_value_996_EQ_bml_fabBuf_modulus_bw__ETC___d2807 ? + bml_fabBuf_value_993_EQ_bml_fabBuf_modulus_bw__ETC___d2801 ? bml_fabMesgBase : bml_fabMesgAddr + bml_fabMesgSize ; assign MUX_bml_fabMetaAddr$write_1__VAL_1 = - bml_fabBuf_value_996_EQ_bml_fabBuf_modulus_bw__ETC___d2807 ? + bml_fabBuf_value_993_EQ_bml_fabBuf_modulus_bw__ETC___d2801 ? bml_fabMetaBase : bml_fabMetaAddr + bml_fabMetaSize ; assign MUX_bml_lclBuf_value$write_1__VAL_3 = - bml_lclBuf_value_966_EQ_bml_lclBuf_modulus_bw__ETC___d2825 ? + bml_lclBuf_value_963_EQ_bml_lclBuf_modulus_bw__ETC___d2819 ? 16'd0 : bml_lclBuf_value + 16'd1 ; assign MUX_bml_lclBufsAR$write_1__VAL_1 = - (IF_bml_dpControl_wget__029_BITS_1_TO_0_035_EQ__ETC___d2106 && + (IF_bml_dpControl_wget__026_BITS_1_TO_0_032_EQ__ETC___d2103 && !bml_lclBufStart) ? - x__h87496 : - x__h87501 ; + x__h87558 : + x__h87563 ; assign MUX_bml_lclBufsAR$write_1__VAL_2 = (dpControl[3:2] == 2'd1) ? bml_lclNumBufs : 16'd0 ; assign MUX_bml_lclBufsCF$write_1__VAL_1 = - bml_lclBufDone_053_AND_IF_bml_dpControl_wget___ETC___d2477 ? - x__h87608 : - x__h87645 ; + bml_lclBufDone_050_AND_IF_bml_dpControl_wget___ETC___d2480 ? + x__h87670 : + x__h87707 ; assign MUX_bml_lclBufsCF$write_1__VAL_2 = (dpControl[3:2] == 2'd1) ? 16'd0 : bml_lclNumBufs ; assign MUX_bml_lclCredit$write_1__VAL_1 = - (bml_lclBufDone && !bml_remStart) ? x__h87766 : x__h87771 ; + (bml_lclBufDone && !bml_remStart) ? x__h87828 : x__h87833 ; assign MUX_bml_lclMesgAddr$write_1__VAL_2 = - bml_lclBuf_value_966_EQ_bml_lclBuf_modulus_bw__ETC___d2825 ? + bml_lclBuf_value_963_EQ_bml_lclBuf_modulus_bw__ETC___d2819 ? bml_mesgBase : bml_lclMesgAddr + bml_mesgSize ; assign MUX_bml_lclMetaAddr$write_1__VAL_2 = - bml_lclBuf_value_966_EQ_bml_lclBuf_modulus_bw__ETC___d2825 ? + bml_lclBuf_value_963_EQ_bml_lclBuf_modulus_bw__ETC___d2819 ? bml_metaBase : bml_lclMetaAddr + bml_metaSize ; assign MUX_bml_remBuf_value$write_1__VAL_3 = - bml_remBuf_value_981_EQ_bml_remBuf_modulus_bw__ETC___d2826 ? + bml_remBuf_value_978_EQ_bml_remBuf_modulus_bw__ETC___d2820 ? 16'd0 : bml_remBuf_value + 16'd1 ; assign MUX_bml_remMesgAddr$write_1__VAL_2 = - bml_remBuf_value_981_EQ_bml_remBuf_modulus_bw__ETC___d2826 ? + bml_remBuf_value_978_EQ_bml_remBuf_modulus_bw__ETC___d2820 ? bml_mesgBase : bml_remMesgAddr + bml_mesgSize ; assign MUX_bml_remMetaAddr$write_1__VAL_2 = - bml_remBuf_value_981_EQ_bml_remBuf_modulus_bw__ETC___d2826 ? + bml_remBuf_value_978_EQ_bml_remBuf_modulus_bw__ETC___d2820 ? bml_metaBase : bml_remMetaAddr + bml_metaSize ; - always@(idx__h19187 or + always@(idx__h19271 or tlp_tlpBRAM_writeDWAddr_PLUS_3__q9 or tlp_tlpBRAM_writeDWAddr or tlp_tlpBRAM_writeDWAddr_PLUS_1__q10 or tlp_tlpBRAM_writeDWAddr_PLUS_2__q11) begin - case (idx__h19187) + case (idx__h19271) 2'd0: MUX_bram_memory$a_put_2__VAL_3 = tlp_tlpBRAM_writeDWAddr[12:2]; 2'd1: MUX_bram_memory$a_put_2__VAL_3 = @@ -3109,13 +3109,13 @@ module mkOCDP4B(pciDevice, tlp_tlpBRAM_writeDWAddr_PLUS_3__q9[12:2]; endcase end - always@(idx__h26267 or + always@(idx__h26351 or tlp_tlpBRAM_readNxtDWAddr_PLUS_3__q12 or tlp_tlpBRAM_readNxtDWAddr or tlp_tlpBRAM_readNxtDWAddr_PLUS_1__q13 or tlp_tlpBRAM_readNxtDWAddr_PLUS_2__q14) begin - case (idx__h26267) + case (idx__h26351) 2'd0: MUX_bram_memory$a_put_2__VAL_4 = tlp_tlpBRAM_readNxtDWAddr[12:2]; 2'd1: MUX_bram_memory$a_put_2__VAL_4 = @@ -3134,19 +3134,19 @@ module mkOCDP4B(pciDevice, tlp_tlpBRAM_mReqF$D_OUT[23:16], tlp_tlpBRAM_mReqF$D_OUT[31:24] } ; assign MUX_bram_memory$a_put_3__VAL_3 = - { IF_0_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2529[7:0], - IF_0_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2529[15:8], - IF_0_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2529[23:16], - IF_0_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2529[31:24] } ; + { IF_0_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2509[7:0], + IF_0_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2509[15:8], + IF_0_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2509[23:16], + IF_0_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2509[31:24] } ; assign MUX_bram_memory$b_put_2__VAL_1 = wmi_lclMesgAddr[14:4] + { 1'd0, wmi_addr[13:4] } ; - always@(idx__h21418 or + always@(idx__h21502 or tlp_tlpBRAM_writeDWAddr_PLUS_3__q9 or tlp_tlpBRAM_writeDWAddr or tlp_tlpBRAM_writeDWAddr_PLUS_1__q10 or tlp_tlpBRAM_writeDWAddr_PLUS_2__q11) begin - case (idx__h21418) + case (idx__h21502) 2'd0: MUX_bram_memory_1$a_put_2__VAL_3 = tlp_tlpBRAM_writeDWAddr[12:2]; 2'd1: MUX_bram_memory_1$a_put_2__VAL_3 = @@ -3159,13 +3159,13 @@ module mkOCDP4B(pciDevice, tlp_tlpBRAM_writeDWAddr_PLUS_3__q9[12:2]; endcase end - always@(idx__h26735 or + always@(idx__h26819 or tlp_tlpBRAM_readNxtDWAddr_PLUS_3__q12 or tlp_tlpBRAM_readNxtDWAddr or tlp_tlpBRAM_readNxtDWAddr_PLUS_1__q13 or tlp_tlpBRAM_readNxtDWAddr_PLUS_2__q14) begin - case (idx__h26735) + case (idx__h26819) 2'd0: MUX_bram_memory_1$a_put_2__VAL_4 = tlp_tlpBRAM_readNxtDWAddr[12:2]; 2'd1: @@ -3180,17 +3180,17 @@ module mkOCDP4B(pciDevice, endcase end assign MUX_bram_memory_1$a_put_3__VAL_3 = - { IF_1_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2507[7:0], - IF_1_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2507[15:8], - IF_1_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2507[23:16], - IF_1_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2507[31:24] } ; - always@(idx__h22722 or + { IF_1_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2510[7:0], + IF_1_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2510[15:8], + IF_1_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2510[23:16], + IF_1_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2510[31:24] } ; + always@(idx__h22806 or tlp_tlpBRAM_writeDWAddr_PLUS_3__q9 or tlp_tlpBRAM_writeDWAddr or tlp_tlpBRAM_writeDWAddr_PLUS_1__q10 or tlp_tlpBRAM_writeDWAddr_PLUS_2__q11) begin - case (idx__h22722) + case (idx__h22806) 2'd0: MUX_bram_memory_2$a_put_2__VAL_3 = tlp_tlpBRAM_writeDWAddr[12:2]; 2'd1: MUX_bram_memory_2$a_put_2__VAL_3 = @@ -3203,13 +3203,13 @@ module mkOCDP4B(pciDevice, tlp_tlpBRAM_writeDWAddr_PLUS_3__q9[12:2]; endcase end - always@(idx__h27108 or + always@(idx__h27192 or tlp_tlpBRAM_readNxtDWAddr_PLUS_3__q12 or tlp_tlpBRAM_readNxtDWAddr or tlp_tlpBRAM_readNxtDWAddr_PLUS_1__q13 or tlp_tlpBRAM_readNxtDWAddr_PLUS_2__q14) begin - case (idx__h27108) + case (idx__h27192) 2'd0: MUX_bram_memory_2$a_put_2__VAL_4 = tlp_tlpBRAM_readNxtDWAddr[12:2]; 2'd1: @@ -3224,17 +3224,17 @@ module mkOCDP4B(pciDevice, endcase end assign MUX_bram_memory_2$a_put_3__VAL_3 = - { IF_2_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2493[7:0], - IF_2_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2493[15:8], - IF_2_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2493[23:16], - IF_2_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2493[31:24] } ; - always@(idx__h24026 or + { IF_2_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2511[7:0], + IF_2_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2511[15:8], + IF_2_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2511[23:16], + IF_2_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2511[31:24] } ; + always@(idx__h24110 or tlp_tlpBRAM_writeDWAddr_PLUS_3__q9 or tlp_tlpBRAM_writeDWAddr or tlp_tlpBRAM_writeDWAddr_PLUS_1__q10 or tlp_tlpBRAM_writeDWAddr_PLUS_2__q11) begin - case (idx__h24026) + case (idx__h24110) 2'd0: MUX_bram_memory_3$a_put_2__VAL_3 = tlp_tlpBRAM_writeDWAddr[12:2]; 2'd1: MUX_bram_memory_3$a_put_2__VAL_3 = @@ -3247,13 +3247,13 @@ module mkOCDP4B(pciDevice, tlp_tlpBRAM_writeDWAddr_PLUS_3__q9[12:2]; endcase end - always@(idx__h27481 or + always@(idx__h27565 or tlp_tlpBRAM_readNxtDWAddr_PLUS_3__q12 or tlp_tlpBRAM_readNxtDWAddr or tlp_tlpBRAM_readNxtDWAddr_PLUS_1__q13 or tlp_tlpBRAM_readNxtDWAddr_PLUS_2__q14) begin - case (idx__h27481) + case (idx__h27565) 2'd0: MUX_bram_memory_3$a_put_2__VAL_4 = tlp_tlpBRAM_readNxtDWAddr[12:2]; 2'd1: @@ -3268,40 +3268,40 @@ module mkOCDP4B(pciDevice, endcase end assign MUX_bram_memory_3$a_put_3__VAL_3 = - { IF_3_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2530[7:0], - IF_3_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2530[15:8], - IF_3_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2530[23:16], - IF_3_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2530[31:24] } ; + { IF_3_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2512[7:0], + IF_3_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2512[15:8], + IF_3_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2512[23:16], + IF_3_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2512[31:24] } ; assign MUX_tlp_dmaDoTailEvent$write_1__VAL_1 = - tlp_dmaPullRemainDWSub_495_ULE_4___d2668 && - tlp_dmaPullRemainDWLen_481_ULE_tlp_dmaPullRema_ETC___d2667 ; + tlp_dmaPullRemainDWSub_493_ULE_4___d2655 && + tlp_dmaPullRemainDWLen_479_ULE_tlp_dmaPullRema_ETC___d2654 ; assign MUX_tlp_dmaPullRemainDWLen$write_1__VAL_2 = tlp_dmaPullRemainDWLen - 10'd1 ; assign MUX_tlp_dmaPullRemainDWLen$write_1__VAL_3 = - tlp_dmaPullRemainDWSub_495_ULE_4___d2668 ? + tlp_dmaPullRemainDWSub_493_ULE_4___d2655 ? tlp_dmaPullRemainDWLen - tlp_dmaPullRemainDWSub : tlp_dmaPullRemainDWLen - 10'd4 ; assign MUX_tlp_dmaPullRemainDWSub$write_1__VAL_1 = tlp_inF$D_OUT[105:96] - 10'd1 ; assign MUX_tlp_dmaPullRemainDWSub$write_1__VAL_2 = - tlp_dmaPullRemainDWSub_495_ULE_4___d2668 ? + tlp_dmaPullRemainDWSub_493_ULE_4___d2655 ? 10'd0 : tlp_dmaPullRemainDWSub - 10'd4 ; assign MUX_tlp_doorSeqDwell$write_1__VAL_1 = tlp_doorSeqDwell - 4'd1 ; - assign MUX_tlp_fabMesgAccu$write_1__VAL_2 = tlp_fabMesgAccu + y__h46773 ; - assign MUX_tlp_fabMesgAccu$write_1__VAL_3 = tlp_fabMesgAccu + y__h62350 ; + assign MUX_tlp_fabMesgAccu$write_1__VAL_2 = tlp_fabMesgAccu + y__h46857 ; + assign MUX_tlp_fabMesgAccu$write_1__VAL_3 = tlp_fabMesgAccu + y__h62423 ; assign MUX_tlp_fabMeta$write_1__VAL_1 = { 1'd1, - x__h45847, - opcode__h42670, - nowMS__h43901, - nowLS__h44844 } ; + x__h45931, + opcode__h42754, + nowMS__h43985, + nowLS__h44928 } ; assign MUX_tlp_fabMeta$write_1__VAL_3 = { 1'd1, - x__h61968, - opcode__h58837, - nowMS__h60057, - nowLS__h60998 } ; + x__h62043, + opcode__h58912, + nowMS__h60132, + nowLS__h61073 } ; assign MUX_tlp_lastRuleFired$write_1__VAL_3 = (tlp_fabFlowAddrMS == 32'd0) ? 4'd8 : @@ -3309,7 +3309,7 @@ module mkOCDP4B(pciDevice, assign MUX_tlp_mesgComplReceived$write_1__VAL_1 = tlp_mesgComplReceived + 17'd4 ; assign MUX_tlp_mesgComplReceived$write_1__VAL_2 = - tlp_mesgComplReceived + y__h63671 ; + tlp_mesgComplReceived + y__h63740 ; assign MUX_tlp_mesgLengthRemainPull$write_1__VAL_1 = { tlp_inF$D_OUT[8], tlp_inF$D_OUT[23:16], @@ -3317,7 +3317,7 @@ module mkOCDP4B(pciDevice, assign MUX_tlp_mesgLengthRemainPull$write_1__VAL_2 = { tlp_mesgLengthRemainPull_PLUS_3__q15[16:2], 2'd0 } ; assign MUX_tlp_mesgLengthRemainPull$write_1__VAL_3 = - tlp_mesgLengthRemainPull - y__h62279 ; + tlp_mesgLengthRemainPull - y__h62352 ; assign MUX_tlp_mesgLengthRemainPush$write_1__VAL_1 = { tlp_mesgLengthRemainPush_PLUS_3__q16[16:2], 2'd0 } ; assign MUX_tlp_mesgLengthRemainPush$write_1__VAL_2 = @@ -3325,9 +3325,9 @@ module mkOCDP4B(pciDevice, tlp_tlpBRAM_mRespF$D_OUT[23:16], tlp_tlpBRAM_mRespF$D_OUT[31:24] } ; assign MUX_tlp_mesgLengthRemainPush$write_1__VAL_3 = - tlp_mesgLengthRemainPush - y__h46119 ; + tlp_mesgLengthRemainPush - y__h46203 ; assign MUX_tlp_outDwRemain$write_1__VAL_1 = - tlp_tlpBRAM_mRespF$D_OUT[71:62] - y__h46739 ; + tlp_tlpBRAM_mRespF$D_OUT[71:62] - y__h46823 ; assign MUX_tlp_outDwRemain$write_1__VAL_2 = tlp_outDwRemain - 10'd4 ; assign MUX_tlp_outDwRemain$write_1__VAL_3 = tlp_tlpBRAM_mRespF$D_OUT[71:62] - 10'd1 ; @@ -3336,8 +3336,8 @@ module mkOCDP4B(pciDevice, { 1'd1, tlp_tlpBRAM_mRespF$D_OUT[71:62] == 10'd1, 23'd196607, - w_data__h46507 } : - { 25'd16973823, w_data__h46644 } ; + w_data__h46591 } : + { 25'd16973823, w_data__h46728 } ; assign MUX_tlp_outF$enq_1__VAL_2 = { 25'd16973823, (tlp_fabMetaAddrMS == 32'd0) ? 32'd1073741828 : 32'd1610612740, @@ -3366,7 +3366,7 @@ module mkOCDP4B(pciDevice, tlp_fabMeta[23:16], tlp_fabMeta[31:24], tlp_fabMetaAddrMS } : - { 25'd8585215, w_data__h51409 } ; + { 25'd8585215, w_data__h51490 } ; assign MUX_tlp_outF$enq_1__VAL_4 = { 9'd386, (tlp_fabMetaAddrMS == 32'd0) ? 16'hFFF0 : 16'd65535, @@ -3374,33 +3374,33 @@ module mkOCDP4B(pciDevice, assign MUX_tlp_outF$enq_1__VAL_5 = { 9'd386, (tlp_fabMesgAddrMS == 32'd0) ? 16'hFFF0 : 16'd65535, - IF_tlp_fabMesgAddrMS_186_EQ_0_187_THEN_0_ELSE__ETC___d1461 } ; + IF_tlp_fabMesgAddrMS_186_EQ_0_187_THEN_0_ELSE__ETC___d1460 } ; assign MUX_tlp_outF$enq_1__VAL_6 = (tlp_fabFlowAddrMS == 32'd0) ? - { 25'd25362431, w_data__h64198 } : + { 25'd25362431, w_data__h64265 } : (tlp_sentTail4DWHeader ? - { 25'd8581120, w_data__h65532 } : - { 25'd16973823, w_data__h65286 }) ; + { 25'd8581120, w_data__h65599 } : + { 25'd16973823, w_data__h65353 }) ; assign MUX_tlp_outF$enq_1__VAL_7 = { 1'd1, tlp_tlpBRAM_mRespF$D_OUT[71:62] == 10'd1, 23'd196607, - pkt__h70068 } ; + pkt__h70132 } ; assign MUX_tlp_outF$enq_1__VAL_8 = { 1'd0, - tlp_outDwRemain_237_ULE_4___d2605, + tlp_outDwRemain_238_ULE_4___d2590, 7'h02, - w_be__h47101, + w_be__h47184, tlp_tlpBRAM_mRespF$D_OUT[127:0] } ; assign MUX_tlp_postSeqDwell$write_1__VAL_1 = (dpControl[1:0] == 2'd2) ? 4'd8 : 4'd4 ; assign MUX_tlp_postSeqDwell$write_1__VAL_2 = tlp_postSeqDwell - 4'd1 ; - assign MUX_tlp_remMesgAccu$write_1__VAL_2 = tlp_remMesgAccu + y__h46261 ; - assign MUX_tlp_remMesgAccu$write_1__VAL_3 = tlp_remMesgAccu + y__h62959 ; + assign MUX_tlp_remMesgAccu$write_1__VAL_2 = tlp_remMesgAccu + y__h46345 ; + assign MUX_tlp_remMesgAccu$write_1__VAL_3 = tlp_remMesgAccu + y__h63030 ; assign MUX_tlp_reqMesgInFlight$write_1__VAL_2 = - !tlp_dmaPullRemainDWSub_495_ULE_4___d2668 || - !tlp_dmaPullRemainDWLen_481_ULE_tlp_dmaPullRema_ETC___d2667 ; - assign MUX_tlp_srcMesgAccu$write_1__VAL_2 = tlp_srcMesgAccu + y__h46213 ; + !tlp_dmaPullRemainDWSub_493_ULE_4___d2655 || + !tlp_dmaPullRemainDWLen_479_ULE_tlp_dmaPullRema_ETC___d2654 ; + assign MUX_tlp_srcMesgAccu$write_1__VAL_2 = tlp_srcMesgAccu + y__h46297 ; assign MUX_tlp_tlpBRAM_mReqF$enq_1__VAL_1 = tlp_inF$D_OUT[152] ? (tlp_inF$D_OUT[126] ? @@ -3428,9 +3428,9 @@ module mkOCDP4B(pciDevice, tlp_fabMesgAddrMS != 32'd0, 18'd196600, tlp_remMesgAccu[14:2], - thisRequestLength__h46094[11:2], + thisRequestLength__h46178[11:2], 8'd255, - rreq_tag__h46309, + rreq_tag__h46393, 3'h2 } ; assign MUX_tlp_tlpBRAM_mReqF$enq_1__VAL_4 = { 67'h15555555555555554, @@ -3449,33 +3449,33 @@ module mkOCDP4B(pciDevice, !tlp_tlpBRAM_readReq$D_OUT[60], tlp_tlpBRAM_readReq$D_OUT[59:42], tlp_tlpBRAM_readReq$D_OUT[28:19], - lowAddr__h28411, - byteCount__h28412, + lowAddr__h28495, + byteCount__h28496, tlp_tlpBRAM_readReq$D_OUT[10:0], - rresp_data__h28457 } ; + rresp_data__h28541 } ; assign MUX_tlp_tlpBRAM_mRespF$enq_1__VAL_2 = { 1'd1, tlp_tlpBRAM_readReq$D_OUT[59:58], tlp_tlpBRAM_readReq$D_OUT[10:3], - rdata__h33850 } ; + rdata__h33934 } ; assign MUX_tlp_tlpBRAM_rdRespDwRemain$write_1__VAL_1 = - tlp_tlpBRAM_readReq$D_OUT[28:19] - y__h29472 ; + tlp_tlpBRAM_readReq$D_OUT[28:19] - y__h29556 ; assign MUX_tlp_tlpBRAM_rdRespDwRemain$write_1__VAL_2 = tlp_tlpBRAM_rdRespDwRemain - 10'd4 ; assign MUX_tlp_tlpBRAM_readNxtDWAddr$write_1__VAL_1 = - tlp_tlpBRAM_mReqF$D_OUT[41:29] + y__h26049 ; + tlp_tlpBRAM_mReqF$D_OUT[41:29] + y__h26133 ; assign MUX_tlp_tlpBRAM_readNxtDWAddr$write_1__VAL_2 = tlp_tlpBRAM_readNxtDWAddr + 13'd4 ; assign MUX_tlp_tlpBRAM_readRemainDWLen$write_1__VAL_1 = - tlp_tlpBRAM_mReqF$D_OUT[28:19] - y__h26037 ; + tlp_tlpBRAM_mReqF$D_OUT[28:19] - y__h26121 ; assign MUX_tlp_tlpBRAM_readRemainDWLen$write_1__VAL_2 = tlp_tlpBRAM_readRemainDWLen - 10'd4 ; assign MUX_tlp_tlpBRAM_writeDWAddr$write_1__VAL_1 = - tlp_tlpBRAM_mReqF$D_OUT[62:50] + y__h17488 ; + tlp_tlpBRAM_mReqF$D_OUT[62:50] + y__h17572 ; assign MUX_tlp_tlpBRAM_writeDWAddr$write_1__VAL_2 = tlp_tlpBRAM_writeDWAddr + 13'd4 ; assign MUX_tlp_tlpBRAM_writeRemainDWLen$write_1__VAL_1 = - tlp_tlpBRAM_mReqF$D_OUT[49:40] - y__h17555 ; + tlp_tlpBRAM_mReqF$D_OUT[49:40] - y__h17639 ; assign MUX_tlp_tlpBRAM_writeRemainDWLen$write_1__VAL_2 = tlp_tlpBRAM_writeRemainDWLen - 10'd4 ; assign MUX_tlp_tlpXmtBusy$write_1__VAL_1 = @@ -3513,7 +3513,7 @@ module mkOCDP4B(pciDevice, 34'h0AAAAAAAA ; assign MUX_wci_respF_x_wire$wset_1__VAL_1 = wci_illegalEdge ? 34'h3C0DE4202 : 34'h1C0DE4201 ; - assign MUX_wci_respF_x_wire$wset_1__VAL_2 = { 2'd1, _theResult____h89640 } ; + assign MUX_wci_respF_x_wire$wset_1__VAL_2 = { 2'd1, _theResult____h89702 } ; assign MUX_wmi_addr$write_1__VAL_1 = wmi_addr + 14'd4 ; assign MUX_wmi_bufDwell$write_1__VAL_3 = wmi_bufDwell - 2'd1 ; assign MUX_wmi_bytesRemainReq$write_1__VAL_1 = wmi_bytesRemainReq - 14'd4 ; @@ -3524,10 +3524,10 @@ module mkOCDP4B(pciDevice, assign MUX_wmi_mesgCount$write_1__VAL_1 = wmi_mesgCount + 32'd1 ; assign MUX_wmi_mesgMeta$write_1__VAL_2 = { 1'd1, - y_avValue__h81613, - y_avValue__h81633, - y_avValue__h81653, - y_avValue__h81673 } ; + y_avValue__h81675, + y_avValue__h81695, + y_avValue__h81715, + y_avValue__h81735 } ; assign MUX_wmi_p4B$write_1__VAL_2 = wmi_p4B + 2'd1 ; assign MUX_wmi_wmi_respF_c_r$write_1__VAL_1 = wmi_wmi_respF_c_r + 2'd1 ; assign MUX_wmi_wmi_respF_c_r$write_1__VAL_2 = wmi_wmi_respF_c_r - 2'd1 ; @@ -3535,7 +3535,7 @@ module mkOCDP4B(pciDevice, (wmi_wmi_respF_c_r == 2'd1) ? MUX_wmi_wmi_respF_q_0$write_1__VAL_2 : wmi_wmi_respF_q_1 ; - assign MUX_wmi_wmi_respF_q_0$write_1__VAL_2 = { 2'd1, rdata__h81777 } ; + assign MUX_wmi_wmi_respF_q_0$write_1__VAL_2 = { 2'd1, rdata__h81839 } ; assign MUX_wmi_wmi_respF_q_1$write_1__VAL_1 = (wmi_wmi_respF_c_r == 2'd2) ? MUX_wmi_wmi_respF_q_0$write_1__VAL_2 : @@ -3584,7 +3584,7 @@ module mkOCDP4B(pciDevice, bram_serverAdapterB_outDataCore$FULL_N) && bram_serverAdapterB_s1[1] && bram_serverAdapterB_s1[0] ; - assign bram_serverAdapterB_outData_outData$wget = y_avValue__h81613 ; + assign bram_serverAdapterB_outData_outData$wget = y_avValue__h81675 ; assign bram_serverAdapterB_outData_outData$whas = bram_serverAdapterB_outDataCore$EMPTY_N || !bram_serverAdapterB_outDataCore$EMPTY_N && @@ -3603,14 +3603,14 @@ module mkOCDP4B(pciDevice, assign bram_serverAdapterB_cnt_3$whas = 1'b0 ; assign bram_serverAdapterB_writeWithResp$wget = ab__h3019 ; assign bram_serverAdapterB_writeWithResp$whas = - bram_serverAdapterB_s1_1$whas ; - assign bram_serverAdapterB_s1_1$wget = - { 1'd1, !ab__h3019[1] || ab__h3019[0] } ; - assign bram_serverAdapterB_s1_1$whas = MUX_bram_memory$b_put_1__SEL_1 || MUX_bram_memory$b_put_1__SEL_2 || WILL_FIRE_RL_wmi_reqMetadata || WILL_FIRE_RL_wmi_doWriteFinalize ; + assign bram_serverAdapterB_s1_1$wget = + { 1'd1, !ab__h3019[1] || ab__h3019[0] } ; + assign bram_serverAdapterB_s1_1$whas = + bram_serverAdapterB_writeWithResp$whas ; assign bram_serverAdapterA_1_outData_enqData$wget = bram_memory_1$DOA ; assign bram_serverAdapterA_1_outData_enqData$whas = (!bram_serverAdapterA_1_s1[0] || @@ -3653,7 +3653,7 @@ module mkOCDP4B(pciDevice, bram_serverAdapterB_1_outDataCore$FULL_N) && bram_serverAdapterB_1_s1[1] && bram_serverAdapterB_1_s1[0] ; - assign bram_serverAdapterB_1_outData_outData$wget = y_avValue__h81633 ; + assign bram_serverAdapterB_1_outData_outData$wget = y_avValue__h81695 ; assign bram_serverAdapterB_1_outData_outData$whas = bram_serverAdapterB_1_outDataCore$EMPTY_N || !bram_serverAdapterB_1_outDataCore$EMPTY_N && @@ -3722,7 +3722,7 @@ module mkOCDP4B(pciDevice, bram_serverAdapterB_2_outDataCore$FULL_N) && bram_serverAdapterB_2_s1[1] && bram_serverAdapterB_2_s1[0] ; - assign bram_serverAdapterB_2_outData_outData$wget = y_avValue__h81653 ; + assign bram_serverAdapterB_2_outData_outData$wget = y_avValue__h81715 ; assign bram_serverAdapterB_2_outData_outData$whas = bram_serverAdapterB_2_outDataCore$EMPTY_N || !bram_serverAdapterB_2_outDataCore$EMPTY_N && @@ -3736,8 +3736,7 @@ module mkOCDP4B(pciDevice, (!ab__h8911[1] || ab__h8911[0]) ; assign bram_serverAdapterB_2_cnt_2$wget = 3'd7 ; assign bram_serverAdapterB_2_cnt_2$whas = - WILL_FIRE_RL_wmi_doReadResp && wmi_p4B == 2'd2 || - WILL_FIRE_RL_wmi_respMetadata ; + bram_serverAdapterB_2_outData_deqCalled$whas ; assign bram_serverAdapterB_2_cnt_3$wget = 3'h0 ; assign bram_serverAdapterB_2_cnt_3$whas = 1'b0 ; assign bram_serverAdapterB_2_writeWithResp$wget = ab__h8911 ; @@ -3792,7 +3791,7 @@ module mkOCDP4B(pciDevice, bram_serverAdapterB_3_outDataCore$FULL_N) && bram_serverAdapterB_3_s1[1] && bram_serverAdapterB_3_s1[0] ; - assign bram_serverAdapterB_3_outData_outData$wget = y_avValue__h81673 ; + assign bram_serverAdapterB_3_outData_outData$wget = y_avValue__h81735 ; assign bram_serverAdapterB_3_outData_outData$whas = bram_serverAdapterB_3_outDataCore$EMPTY_N || !bram_serverAdapterB_3_outDataCore$EMPTY_N && @@ -3866,8 +3865,8 @@ module mkOCDP4B(pciDevice, assign tlp_dpControl$wget = dpControl ; assign tlp_dpControl$whas = 1'd1 ; assign tlp_pullTagMatch_1$wget = - tagm__h62748 == tlp_inF$D_OUT[47:40] && - tlp_inF_first__367_BITS_63_TO_56_370_EQ_pciDev_ETC___d1380 ; + tagm__h62820 == tlp_inF$D_OUT[47:40] && + tlp_inF_first__366_BITS_63_TO_56_369_EQ_pciDev_ETC___d1379 ; assign tlp_pullTagMatch_1$whas = tlp_inF$EMPTY_N && hasPull && dpControl[7:4] == 4'd0 && dpControl[3:2] == 2'd2 && @@ -3991,7 +3990,8 @@ module mkOCDP4B(pciDevice, tlp_tlpBRAM_readReq$D_OUT[30:29] == 2'd2 || WILL_FIRE_RL_tlp_tlpBRAM_read_NextResp ; assign bram_serverAdapterB_2_outData_deqCalled$whas = - bram_serverAdapterB_2_cnt_2$whas ; + WILL_FIRE_RL_wmi_doReadResp && wmi_p4B == 2'd2 || + WILL_FIRE_RL_wmi_respMetadata ; assign bram_serverAdapterA_3_outData_deqCalled$whas = WILL_FIRE_RL_tlp_tlpBRAM_read_FirstResp && !tlp_tlpBRAM_readReq$D_OUT[60] && @@ -4240,8 +4240,8 @@ module mkOCDP4B(pciDevice, MUX_bml_lclBufsCF$write_1__VAL_2 ; assign bml_lclBufsCF$EN = wci_cState == 3'd2 && - (bml_lclBufDone_053_AND_IF_bml_dpControl_wget___ETC___d2477 || - NOT_bml_lclBufDone_053_120_AND_IF_bml_dpContro_ETC___d2133) || + (bml_lclBufDone_050_AND_IF_bml_dpControl_wget___ETC___d2480 || + NOT_bml_lclBufDone_050_117_AND_IF_bml_dpContro_ETC___d2130) || WILL_FIRE_RL_bml_initAccumulators ; // register bml_lclCredit @@ -4428,7 +4428,7 @@ module mkOCDP4B(pciDevice, bram_serverAdapterB_2_cnt_21_PLUS_IF_bram_serv_ETC___d327 ; assign bram_serverAdapterB_2_cnt$EN = bram_serverAdapterB_2_cnt_1$whas || - bram_serverAdapterB_2_cnt_2$whas ; + bram_serverAdapterB_2_outData_deqCalled$whas ; // register bram_serverAdapterB_2_s1 assign bram_serverAdapterB_2_s1$D_IN = @@ -4460,7 +4460,7 @@ module mkOCDP4B(pciDevice, // register bram_serverAdapterB_s1 assign bram_serverAdapterB_s1$D_IN = - { bram_serverAdapterB_s1_1$whas && + { bram_serverAdapterB_writeWithResp$whas && bram_serverAdapterB_s1_1$wget[1], bram_serverAdapterB_s1_1$wget[0] } ; assign bram_serverAdapterB_s1$EN = 1'd1 ; @@ -4526,7 +4526,7 @@ module mkOCDP4B(pciDevice, // register tlp_dmaPullRemainDWLen always@(WILL_FIRE_RL_tlp_dmaPullRequestFarMesg or - thisRequestLength__h62254 or + thisRequestLength__h62327 or WILL_FIRE_RL_tlp_dmaPullResponseHeader or MUX_tlp_dmaPullRemainDWLen$write_1__VAL_2 or WILL_FIRE_RL_tlp_dmaPullResponseBody or @@ -4534,7 +4534,7 @@ module mkOCDP4B(pciDevice, begin case (1'b1) // synopsys parallel_case WILL_FIRE_RL_tlp_dmaPullRequestFarMesg: - tlp_dmaPullRemainDWLen$D_IN = thisRequestLength__h62254[11:2]; + tlp_dmaPullRemainDWLen$D_IN = thisRequestLength__h62327[11:2]; WILL_FIRE_RL_tlp_dmaPullResponseHeader: tlp_dmaPullRemainDWLen$D_IN = MUX_tlp_dmaPullRemainDWLen$write_1__VAL_2; @@ -4667,7 +4667,7 @@ module mkOCDP4B(pciDevice, always@(WILL_FIRE_RL_tlp_dmaPullResponseHeader or tlp_inF$D_OUT or WILL_FIRE_RL_tlp_dmaPullResponseBody or - tlp_dmaPullRemainDWSub_495_ULE_4___d2668 or + tlp_dmaPullRemainDWSub_493_ULE_4___d2655 or WILL_FIRE_RL_tlp_dmaPullRequestFarMesg) begin case (1'b1) // synopsys parallel_case @@ -4675,7 +4675,7 @@ module mkOCDP4B(pciDevice, tlp_gotResponseHeader$D_IN = tlp_inF$D_OUT[105:96] != 10'd1; WILL_FIRE_RL_tlp_dmaPullResponseBody: tlp_gotResponseHeader$D_IN = - !tlp_dmaPullRemainDWSub_495_ULE_4___d2668; + !tlp_dmaPullRemainDWSub_493_ULE_4___d2655; WILL_FIRE_RL_tlp_dmaPullRequestFarMesg: tlp_gotResponseHeader$D_IN = 1'd0; default: tlp_gotResponseHeader$D_IN = 1'b0 /* unspecified value */ ; @@ -4695,8 +4695,8 @@ module mkOCDP4B(pciDevice, // register tlp_lastMetaV assign tlp_lastMetaV$D_IN = WILL_FIRE_RL_tlp_dmaResponseNearMetaHead ? - x__h40887 : - x__h56804 ; + x__h40971 : + x__h56883 ; assign tlp_lastMetaV$EN = WILL_FIRE_RL_tlp_dmaResponseNearMetaHead || WILL_FIRE_RL_tlp_dmaRespHeadFarMeta ; @@ -4704,8 +4704,8 @@ module mkOCDP4B(pciDevice, // register tlp_lastMetaV_1 assign tlp_lastMetaV_1$D_IN = WILL_FIRE_RL_tlp_dmaResponseNearMetaBody ? - opcode__h42670 : - opcode__h58837 ; + opcode__h42754 : + opcode__h58912 ; assign tlp_lastMetaV_1$EN = WILL_FIRE_RL_tlp_dmaResponseNearMetaBody || WILL_FIRE_RL_tlp_dmaRespBodyFarMeta ; @@ -4713,8 +4713,8 @@ module mkOCDP4B(pciDevice, // register tlp_lastMetaV_2 assign tlp_lastMetaV_2$D_IN = WILL_FIRE_RL_tlp_dmaResponseNearMetaBody ? - nowMS__h43901 : - nowMS__h60057 ; + nowMS__h43985 : + nowMS__h60132 ; assign tlp_lastMetaV_2$EN = WILL_FIRE_RL_tlp_dmaResponseNearMetaBody || WILL_FIRE_RL_tlp_dmaRespBodyFarMeta ; @@ -4722,8 +4722,8 @@ module mkOCDP4B(pciDevice, // register tlp_lastMetaV_3 assign tlp_lastMetaV_3$D_IN = WILL_FIRE_RL_tlp_dmaResponseNearMetaBody ? - nowLS__h44844 : - nowLS__h60998 ; + nowLS__h44928 : + nowLS__h61073 ; assign tlp_lastMetaV_3$EN = WILL_FIRE_RL_tlp_dmaResponseNearMetaBody || WILL_FIRE_RL_tlp_dmaRespBodyFarMeta ; @@ -5087,14 +5087,14 @@ module mkOCDP4B(pciDevice, tlp_inF$D_OUT or WILL_FIRE_RL_tlp_dmaPullResponseHeader or WILL_FIRE_RL_tlp_dmaPullResponseBody or - tlp_dmaPullRemainDWSub_495_ULE_4___d2668) + tlp_dmaPullRemainDWSub_493_ULE_4___d2655) begin case (1'b1) // synopsys parallel_case WILL_FIRE_RL_tlp_tlpRcv: tlp_tlpRcvBusy$D_IN = !tlp_inF$D_OUT[151]; WILL_FIRE_RL_tlp_dmaPullResponseHeader: tlp_tlpRcvBusy$D_IN = tlp_inF$D_OUT[105:96] != 10'd1; WILL_FIRE_RL_tlp_dmaPullResponseBody: - tlp_tlpRcvBusy$D_IN = !tlp_dmaPullRemainDWSub_495_ULE_4___d2668; + tlp_tlpRcvBusy$D_IN = !tlp_dmaPullRemainDWSub_493_ULE_4___d2655; default: tlp_tlpRcvBusy$D_IN = 1'b0 /* unspecified value */ ; endcase end @@ -5130,10 +5130,10 @@ module mkOCDP4B(pciDevice, WILL_FIRE_RL_tlp_dmaTailEventSender && tlp_fabFlowAddrMS != 32'd0 || WILL_FIRE_RL_tlp_dataXmt_Header && - !tlp_tlpBRAM_mRespF_first__108_BITS_71_TO_62_20_ETC___d2421 || + !tlp_tlpBRAM_mRespF_first__108_BITS_71_TO_62_20_ETC___d2442 || (WILL_FIRE_RL_tlp_dataXmt_Body || WILL_FIRE_RL_tlp_dmaPushResponseBody) && - tlp_outDwRemain_237_ULE_4___d2605 || + tlp_outDwRemain_238_ULE_4___d2590 || WILL_FIRE_RL_tlp_dmaXmtMetaBody || WILL_FIRE_RL_tlp_dmaXmtMetaHead ; @@ -5163,7 +5163,7 @@ module mkOCDP4B(pciDevice, tlp_tlpBRAM_mRespF$D_OUT[71:62] == 10'd1 && tlp_tlpBRAM_mRespF$D_OUT[42:35] == 8'h01 || WILL_FIRE_RL_tlp_dmaPushResponseBody && - tlp_outDwRemain_237_ULE_4___d2605 && + tlp_outDwRemain_238_ULE_4___d2590 && tlp_tlpBRAM_mRespF$D_OUT[135:128] == 8'h01 || WILL_FIRE_RL_tlp_dmaResponseNearMetaBody || WILL_FIRE_RL_tlp_dmaXmtMetaHead ; @@ -5549,7 +5549,7 @@ module mkOCDP4B(pciDevice, // register wmi_wmi_sFlagReg assign wmi_wmi_sFlagReg$D_IN = - { y_avValue__h81633[7:0], y_avValue__h81613[23:0] } ; + { y_avValue__h81695[7:0], y_avValue__h81675[23:0] } ; assign wmi_wmi_sFlagReg$EN = WILL_FIRE_RL_wmi_respMetadata ; // register wmi_wmi_statusR @@ -5648,13 +5648,13 @@ module mkOCDP4B(pciDevice, always@(MUX_bram_memory$b_put_1__SEL_2 or wmi_wmi_dhF$D_OUT or WILL_FIRE_RL_wmi_doWriteFinalize or - x3__h80014 or + x3__h80076 or MUX_bram_memory$b_put_1__SEL_1 or WILL_FIRE_RL_wmi_reqMetadata) begin case (1'b1) // synopsys parallel_case MUX_bram_memory$b_put_1__SEL_2: bram_memory$DIB = wmi_wmi_dhF$D_OUT[35:4]; - WILL_FIRE_RL_wmi_doWriteFinalize: bram_memory$DIB = x3__h80014; + WILL_FIRE_RL_wmi_doWriteFinalize: bram_memory$DIB = x3__h80076; MUX_bram_memory$b_put_1__SEL_1 || WILL_FIRE_RL_wmi_reqMetadata: bram_memory$DIB = 32'd0; default: bram_memory$DIB = 32'hAAAAAAAA /* unspecified value */ ; @@ -5674,7 +5674,7 @@ module mkOCDP4B(pciDevice, !tlp_tlpBRAM_mReqF$D_OUT[60] && tlp_tlpBRAM_mReqF$D_OUT[30:29] == 2'd0 || WILL_FIRE_RL_tlp_tlpBRAM_writeData && - IF_0_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2464 || + IF_0_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2469 || WILL_FIRE_RL_tlp_tlpBRAM_read_NextReq ; assign bram_memory$ENB = WILL_FIRE_RL_wmi_doReadReq && wmi_addr[3:2] == 2'd0 || @@ -5740,14 +5740,14 @@ module mkOCDP4B(pciDevice, always@(MUX_bram_memory_1$b_put_1__SEL_2 or wmi_wmi_dhF$D_OUT or WILL_FIRE_RL_wmi_doWriteFinalize or - mesgMeta_opcode__h80054 or + mesgMeta_opcode__h80116 or MUX_bram_memory_1$b_put_1__SEL_1 or WILL_FIRE_RL_wmi_reqMetadata) begin case (1'b1) // synopsys parallel_case MUX_bram_memory_1$b_put_1__SEL_2: bram_memory_1$DIB = wmi_wmi_dhF$D_OUT[35:4]; WILL_FIRE_RL_wmi_doWriteFinalize: - bram_memory_1$DIB = mesgMeta_opcode__h80054; + bram_memory_1$DIB = mesgMeta_opcode__h80116; MUX_bram_memory_1$b_put_1__SEL_1 || WILL_FIRE_RL_wmi_reqMetadata: bram_memory_1$DIB = 32'd0; default: bram_memory_1$DIB = 32'hAAAAAAAA /* unspecified value */ ; @@ -5767,7 +5767,7 @@ module mkOCDP4B(pciDevice, !tlp_tlpBRAM_mReqF$D_OUT[60] && tlp_tlpBRAM_mReqF$D_OUT[30:29] == 2'd1 || WILL_FIRE_RL_tlp_tlpBRAM_writeData && - IF_1_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2465 || + IF_1_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2470 || WILL_FIRE_RL_tlp_tlpBRAM_read_NextReq ; assign bram_memory_1$ENB = WILL_FIRE_RL_wmi_doReadReq && wmi_addr[3:2] == 2'd1 || @@ -5860,7 +5860,7 @@ module mkOCDP4B(pciDevice, !tlp_tlpBRAM_mReqF$D_OUT[60] && tlp_tlpBRAM_mReqF$D_OUT[30:29] == 2'd2 || WILL_FIRE_RL_tlp_tlpBRAM_writeData && - IF_2_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2466 || + IF_2_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2471 || WILL_FIRE_RL_tlp_tlpBRAM_read_NextReq ; assign bram_memory_2$ENB = WILL_FIRE_RL_wmi_doReadReq && wmi_addr[3:2] == 2'd2 || @@ -5953,7 +5953,7 @@ module mkOCDP4B(pciDevice, !tlp_tlpBRAM_mReqF$D_OUT[60] && tlp_tlpBRAM_mReqF$D_OUT[30:29] == 2'd3 || WILL_FIRE_RL_tlp_tlpBRAM_writeData && - IF_3_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2467 || + IF_3_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2472 || WILL_FIRE_RL_tlp_tlpBRAM_read_NextReq ; assign bram_memory_3$ENB = WILL_FIRE_RL_wmi_doReadReq && wmi_addr[3:2] == 2'd3 || @@ -6036,12 +6036,12 @@ module mkOCDP4B(pciDevice, assign bram_serverAdapterB_2_outDataCore$ENQ = WILL_FIRE_RL_bram_serverAdapterB_2_outData_enqAndDeq || bram_serverAdapterB_2_outDataCore$FULL_N && - !bram_serverAdapterB_2_cnt_2$whas && + !bram_serverAdapterB_2_outData_deqCalled$whas && bram_serverAdapterB_2_outData_enqData$whas ; assign bram_serverAdapterB_2_outDataCore$DEQ = WILL_FIRE_RL_bram_serverAdapterB_2_outData_enqAndDeq || bram_serverAdapterB_2_outDataCore$EMPTY_N && - bram_serverAdapterB_2_cnt_2$whas && + bram_serverAdapterB_2_outData_deqCalled$whas && !bram_serverAdapterB_2_outData_enqData$whas ; assign bram_serverAdapterB_2_outDataCore$CLR = 1'b0 ; @@ -6075,13 +6075,13 @@ module mkOCDP4B(pciDevice, // submodule tlp_inF assign tlp_inF$D_IN = server_request_put ; + assign tlp_inF$ENQ = EN_server_request_put ; assign tlp_inF$DEQ = WILL_FIRE_RL_tlp_tlpRcv || WILL_FIRE_RL_tlp_dmaPullResponseBody || WILL_FIRE_RL_tlp_dmaPullResponseHeader || WILL_FIRE_RL_tlp_dmaRespBodyFarMeta || WILL_FIRE_RL_tlp_dmaRespHeadFarMeta ; - assign tlp_inF$ENQ = EN_server_request_put ; assign tlp_inF$CLR = 1'b0 ; // submodule tlp_outF @@ -6122,7 +6122,6 @@ module mkOCDP4B(pciDevice, 153'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ; endcase end - assign tlp_outF$DEQ = EN_server_response_get ; assign tlp_outF$ENQ = WILL_FIRE_RL_tlp_dmaPushResponseHeader || WILL_FIRE_RL_tlp_dmaXmtMetaHead || @@ -6133,6 +6132,7 @@ module mkOCDP4B(pciDevice, WILL_FIRE_RL_tlp_dataXmt_Header || WILL_FIRE_RL_tlp_dataXmt_Body || WILL_FIRE_RL_tlp_dmaPushResponseBody ; + assign tlp_outF$DEQ = EN_server_response_get ; assign tlp_outF$CLR = 1'b0 ; // submodule tlp_tailEventF @@ -6177,7 +6177,7 @@ module mkOCDP4B(pciDevice, end assign tlp_tlpBRAM_mReqF$ENQ = WILL_FIRE_RL_tlp_tlpRcv && - tlp_inF_first__367_BIT_152_570_AND_NOT_tlp_inF_ETC___d1595 || + tlp_inF_first__366_BIT_152_568_AND_NOT_tlp_inF_ETC___d1592 || WILL_FIRE_RL_tlp_dmaRequestNearMeta || WILL_FIRE_RL_tlp_dmaPushRequestMesg || WILL_FIRE_RL_tlp_dmaRespHeadFarMeta || @@ -6249,17 +6249,17 @@ module mkOCDP4B(pciDevice, // remaining internal signals assign IF_1_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d708 = (IF_1_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d685 || - bram_serverAdapterA_1_cnt_44_SLT_3___d2671) && + bram_serverAdapterA_1_cnt_44_SLT_3___d2658) && (IF_2_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d695 || - bram_serverAdapterA_2_cnt_62_SLT_3___d2672) && + bram_serverAdapterA_2_cnt_62_SLT_3___d2418) && (IF_3_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d705 || - bram_serverAdapterA_3_cnt_80_SLT_3___d2504) ; - assign IF_tlp_fabMesgAddrMS_186_EQ_0_187_THEN_0_ELSE__ETC___d1461 = + bram_serverAdapterA_3_cnt_80_SLT_3___d2659) ; + assign IF_tlp_fabMesgAddrMS_186_EQ_0_187_THEN_0_ELSE__ETC___d1460 = { (tlp_fabMesgAddrMS == 32'd0) ? 22'd0 : 22'd524288, - thisRequestLength__h62254[11:2], + thisRequestLength__h62327[11:2], pciDevice, - tag__h62529, - lastBE__h62561, + tag__h62602, + lastBE__h62634, 4'd15, (tlp_fabMesgAddrMS == 32'd0) ? { tlp_fabMesgAccu[31:2], 34'd0 } : @@ -6267,13 +6267,13 @@ module mkOCDP4B(pciDevice, assign IF_tlp_fabMetaAddrMS_265_EQ_0_266_THEN_4_ELSE__ETC___d1356 = { (tlp_fabMetaAddrMS == 32'd0) ? 32'd4 : 32'd536870916, pciDevice, - tag__h62529, + tag__h62602, 8'd255, (tlp_fabMetaAddrMS == 32'd0) ? { tlp_fabMetaAddr[31:2], 34'd0 } : { tlp_fabMetaAddrMS, tlp_fabMetaAddr[31:2], 2'b0 } } ; assign IF_tlp_tlpBRAM_readReq_first__97_BITS_30_TO_29_ETC___d1037 = - tlp_tlpBRAM_readReq_first__97_BITS_30_TO_29_99_ETC___d2439[0] ? + tlp_tlpBRAM_readReq_first__97_BITS_30_TO_29_99_ETC___d2433[0] ? { bram_serverAdapterA_3_outData_outData$wget[7:0], bram_serverAdapterA_3_outData_outData$wget[15:8], bram_serverAdapterA_3_outData_outData$wget[23:16], @@ -6307,7 +6307,7 @@ module mkOCDP4B(pciDevice, bram_serverAdapterA_1_outData_outData$wget[23:16], bram_serverAdapterA_1_outData_outData$wget[31:24] } ; assign IF_tlp_tlpBRAM_readReq_first__97_BITS_30_TO_29_ETC___d1042 = - tlp_tlpBRAM_readReq_first__97_BITS_30_TO_29_99_ETC___d2439[0] ? + tlp_tlpBRAM_readReq_first__97_BITS_30_TO_29_99_ETC___d2433[0] ? { bram_serverAdapterA_1_outData_outData$wget[7:0], bram_serverAdapterA_1_outData_outData$wget[15:8], bram_serverAdapterA_1_outData_outData$wget[23:16], @@ -6343,17 +6343,17 @@ module mkOCDP4B(pciDevice, assign IF_tlp_tlpBRAM_readReq_first__97_BITS_30_TO_29_ETC___d921 = IF_tlp_tlpBRAM_readReq_first__97_BITS_30_TO_29_ETC___d912 && CASE_tlp_tlpBRAM_readReqD_OUT_BITS_30_TO_29_N_ETC__q17 ; - assign IF_wmi_p4B_912_EQ_0_913_THEN_bram_serverAdapte_ETC___d1926 = + assign IF_wmi_p4B_909_EQ_0_910_THEN_bram_serverAdapte_ETC___d1923 = (wmi_p4B == 2'd0) ? (bram_serverAdapterB_outDataCore$EMPTY_N || bram_serverAdapterB_outData_enqData$whas) && bram_serverAdapterB_outData_outData$whas : - IF_wmi_p4B_912_EQ_1_915_THEN_bram_serverAdapte_ETC___d1921 && + IF_wmi_p4B_909_EQ_1_912_THEN_bram_serverAdapte_ETC___d1918 && CASE_wmi_p4B_NOT_wmi_p4B_EQ_3_OR_bram_serverAd_ETC__q18 ; - assign NOT_bml_lclBufDone_053_120_AND_IF_bml_dpContro_ETC___d2133 = + assign NOT_bml_lclBufDone_050_117_AND_IF_bml_dpContro_ETC___d2130 = !bml_lclBufDone && CASE_dpControl_BITS_1_TO_0_bml_fabDone_0_bml_f_ETC__q3 ; - assign NOT_wmi_wrActive_827_828_OR_NOT_wmi_rdActive_8_ETC___d1837 = + assign NOT_wmi_wrActive_824_825_OR_NOT_wmi_rdActive_8_ETC___d1834 = (!wmi_wrActive || !wmi_rdActive) && !wmi_wrFinalize && (wmi_mesgBufReady || wmi_mesgBusy) ; assign _dfoo5 = @@ -6400,30 +6400,30 @@ module mkOCDP4B(pciDevice, WILL_FIRE_RL_wmi_reqMetadata) ? 2'd0 : 2'd2 ; - assign bml_crdBuf_value_011_EQ_bml_crdBuf_modulus_bw__ETC___d2806 = + assign bml_crdBuf_value_008_EQ_bml_crdBuf_modulus_bw__ETC___d2800 = bml_crdBuf_value == bml_crdBuf_modulus ; - assign bml_fabBuf_value_996_EQ_bml_fabBuf_modulus_bw__ETC___d2807 = + assign bml_fabBuf_value_993_EQ_bml_fabBuf_modulus_bw__ETC___d2801 = bml_fabBuf_value == bml_fabBuf_modulus ; - assign bml_fabFlowAddr_068_PLUS_bml_fabFlowSize_069___d2666 = + assign bml_fabFlowAddr_065_PLUS_bml_fabFlowSize_066___d2653 = bml_fabFlowAddr + bml_fabFlowSize ; - assign bml_lclBufDone_053_AND_IF_bml_dpControl_wget___ETC___d2477 = + assign bml_lclBufDone_050_AND_IF_bml_dpControl_wget___ETC___d2480 = bml_lclBufDone && CASE_dpControl_BITS_1_TO_0_NOT_bml_fabDone_0_N_ETC__q7 ; - assign bml_lclBuf_value_966_EQ_bml_lclBuf_modulus_bw__ETC___d2825 = + assign bml_lclBuf_value_963_EQ_bml_lclBuf_modulus_bw__ETC___d2819 = bml_lclBuf_value == bml_lclBuf_modulus ; - assign bml_remBuf_value_981_EQ_bml_remBuf_modulus_bw__ETC___d2826 = + assign bml_remBuf_value_978_EQ_bml_remBuf_modulus_bw__ETC___d2820 = bml_remBuf_value == bml_remBuf_modulus ; assign bram_serverAdapterA_1_cnt_44_PLUS_IF_bram_serv_ETC___d150 = bram_serverAdapterA_1_cnt + (bram_serverAdapterA_1_cnt_1$whas ? 3'd1 : 3'd0) + (bram_serverAdapterA_1_outData_deqCalled$whas ? 3'd7 : 3'd0) ; - assign bram_serverAdapterA_1_cnt_44_SLT_3___d2671 = + assign bram_serverAdapterA_1_cnt_44_SLT_3___d2658 = (bram_serverAdapterA_1_cnt ^ 3'h4) < 3'd7 ; assign bram_serverAdapterA_2_cnt_62_PLUS_IF_bram_serv_ETC___d268 = bram_serverAdapterA_2_cnt + (bram_serverAdapterA_2_cnt_1$whas ? 3'd1 : 3'd0) + (bram_serverAdapterA_2_outData_deqCalled$whas ? 3'd7 : 3'd0) ; - assign bram_serverAdapterA_2_cnt_62_SLT_3___d2672 = + assign bram_serverAdapterA_2_cnt_62_SLT_3___d2418 = (bram_serverAdapterA_2_cnt ^ 3'h4) < 3'd7 ; assign bram_serverAdapterA_2_outDataCore_notEmpty__38_ETC___d993 = (bram_serverAdapterA_2_outDataCore$EMPTY_N || @@ -6439,13 +6439,13 @@ module mkOCDP4B(pciDevice, bram_serverAdapterA_3_cnt + (bram_serverAdapterA_3_cnt_1$whas ? 3'd1 : 3'd0) + (bram_serverAdapterA_3_outData_deqCalled$whas ? 3'd7 : 3'd0) ; - assign bram_serverAdapterA_3_cnt_80_SLT_3___d2504 = + assign bram_serverAdapterA_3_cnt_80_SLT_3___d2659 = (bram_serverAdapterA_3_cnt ^ 3'h4) < 3'd7 ; assign bram_serverAdapterA_cnt_6_PLUS_IF_bram_serverA_ETC___d32 = bram_serverAdapterA_cnt + (bram_serverAdapterA_cnt_1$whas ? 3'd1 : 3'd0) + (bram_serverAdapterA_outData_deqCalled$whas ? 3'd7 : 3'd0) ; - assign bram_serverAdapterA_cnt_6_SLT_3___d2670 = + assign bram_serverAdapterA_cnt_6_SLT_3___d2657 = (bram_serverAdapterA_cnt ^ 3'h4) < 3'd7 ; assign bram_serverAdapterA_outDataCore_notEmpty_OR_br_ETC___d995 = (bram_serverAdapterA_outDataCore$EMPTY_N || @@ -6457,9 +6457,9 @@ module mkOCDP4B(pciDevice, bram_serverAdapterB_1_cnt + (bram_serverAdapterB_1_cnt_1$whas ? 3'd1 : 3'd0) + (bram_serverAdapterB_1_outData_deqCalled$whas ? 3'd7 : 3'd0) ; - assign bram_serverAdapterB_1_cnt_03_SLT_3___d1777 = + assign bram_serverAdapterB_1_cnt_03_SLT_3___d1774 = (bram_serverAdapterB_1_cnt ^ 3'h4) < 3'd7 ; - assign bram_serverAdapterB_1_outData_outData_whas__79_ETC___d1805 = + assign bram_serverAdapterB_1_outData_outData_whas__79_ETC___d1802 = bram_serverAdapterB_1_outData_outData$whas && (bram_serverAdapterB_2_outDataCore$EMPTY_N || bram_serverAdapterB_2_outData_enqData$whas) && @@ -6470,22 +6470,22 @@ module mkOCDP4B(pciDevice, assign bram_serverAdapterB_2_cnt_21_PLUS_IF_bram_serv_ETC___d327 = bram_serverAdapterB_2_cnt + (bram_serverAdapterB_2_cnt_1$whas ? 3'd1 : 3'd0) + - (bram_serverAdapterB_2_cnt_2$whas ? 3'd7 : 3'd0) ; - assign bram_serverAdapterB_2_cnt_21_SLT_3___d1778 = + (bram_serverAdapterB_2_outData_deqCalled$whas ? 3'd7 : 3'd0) ; + assign bram_serverAdapterB_2_cnt_21_SLT_3___d1775 = (bram_serverAdapterB_2_cnt ^ 3'h4) < 3'd7 ; assign bram_serverAdapterB_3_cnt_39_PLUS_IF_bram_serv_ETC___d445 = bram_serverAdapterB_3_cnt + (bram_serverAdapterB_3_cnt_1$whas ? 3'd1 : 3'd0) + (bram_serverAdapterB_3_outData_deqCalled$whas ? 3'd7 : 3'd0) ; - assign bram_serverAdapterB_3_cnt_39_SLT_3___d1779 = + assign bram_serverAdapterB_3_cnt_39_SLT_3___d1776 = (bram_serverAdapterB_3_cnt ^ 3'h4) < 3'd7 ; assign bram_serverAdapterB_cnt_5_PLUS_IF_bram_serverA_ETC___d91 = bram_serverAdapterB_cnt + (bram_serverAdapterB_cnt_1$whas ? 3'd1 : 3'd0) + (bram_serverAdapterB_outData_deqCalled$whas ? 3'd7 : 3'd0) ; - assign bram_serverAdapterB_cnt_5_SLT_3___d1776 = + assign bram_serverAdapterB_cnt_5_SLT_3___d1773 = (bram_serverAdapterB_cnt ^ 3'h4) < 3'd7 ; - assign byteCount__h28412 = x__h28530 - y__h28531 ; + assign byteCount__h28496 = x__h28614 - y__h28615 ; assign hasPull_AND_tlp_dpControl_wget__072_BITS_7_TO__ETC___d1341 = hasPull && dpControl[7:4] == 4'd0 && dpControl[3:2] == 2'd2 && dpControl[1:0] == 2'd1 && @@ -6493,14 +6493,14 @@ module mkOCDP4B(pciDevice, !tlp_reqMetaInFlight && !tlp_reqMetaBodyInFlight && !tlp_fabMeta[128] ; - assign hasPull_AND_tlp_dpControl_wget__072_BITS_7_TO__ETC___d1382 = + assign hasPull_AND_tlp_dpControl_wget__072_BITS_7_TO__ETC___d1381 = hasPull && dpControl[7:4] == 4'd0 && dpControl[3:2] == 2'd2 && dpControl[1:0] == 2'd1 && tlp_reqMetaInFlight && !tlp_tlpRcvBusy && - tagm__h62748 == tlp_inF$D_OUT[47:40] && - tlp_inF_first__367_BITS_63_TO_56_370_EQ_pciDev_ETC___d1380 ; - assign hasPull_AND_tlp_dpControl_wget__072_BITS_7_TO__ETC___d1434 = + tagm__h62820 == tlp_inF$D_OUT[47:40] && + tlp_inF_first__366_BITS_63_TO_56_369_EQ_pciDev_ETC___d1379 ; + assign hasPull_AND_tlp_dpControl_wget__072_BITS_7_TO__ETC___d1433 = hasPull && dpControl[7:4] == 4'd0 && dpControl[3:2] == 2'd2 && dpControl[1:0] == 2'd1 && tlp_fabMeta[128] && @@ -6508,7 +6508,7 @@ module mkOCDP4B(pciDevice, !tlp_tlpXmtBusy && !tlp_reqMesgInFlight && tlp_mesgLengthRemainPull != 17'd0 ; - assign hasPull_AND_tlp_dpControl_wget__072_BITS_7_TO__ETC___d1473 = + assign hasPull_AND_tlp_dpControl_wget__072_BITS_7_TO__ETC___d1471 = hasPull && dpControl[7:4] == 4'd0 && dpControl[3:2] == 2'd2 && dpControl[1:0] == 2'd1 && tlp_fabMeta[128] && @@ -6516,13 +6516,13 @@ module mkOCDP4B(pciDevice, !tlp_tlpRcvBusy && tlp_pullTagMatch && !tlp_gotResponseHeader ; - assign hasPull_AND_tlp_dpControl_wget__072_BITS_7_TO__ETC___d1493 = + assign hasPull_AND_tlp_dpControl_wget__072_BITS_7_TO__ETC___d1491 = hasPull && dpControl[7:4] == 4'd0 && dpControl[3:2] == 2'd2 && dpControl[1:0] == 2'd1 && tlp_fabMeta[128] && tlp_reqMesgInFlight && tlp_gotResponseHeader ; - assign hasPull_AND_tlp_dpControl_wget__072_BITS_7_TO__ETC___d1518 = + assign hasPull_AND_tlp_dpControl_wget__072_BITS_7_TO__ETC___d1516 = hasPull && dpControl[7:4] == 4'd0 && dpControl[3:2] == 2'd2 && dpControl[1:0] == 2'd1 && tlp_fabMeta[128] && @@ -6543,7 +6543,7 @@ module mkOCDP4B(pciDevice, tlp_fabMeta[127:96] != 32'd0 && !tlp_tlpRcvBusy && tlp_mesgLengthRemainPush != 17'd0 ; - assign hasPush_AND_tlp_dpControl_wget__072_BITS_7_TO__ETC___d1206 = + assign hasPush_AND_tlp_dpControl_wget__072_BITS_7_TO__ETC___d1207 = hasPush && dpControl[7:4] == 4'd0 && dpControl[3:2] == 2'd1 && dpControl[1:0] == 2'd1 && !tlp_tlpBRAM_mRespF$D_OUT[138] && @@ -6558,55 +6558,55 @@ module mkOCDP4B(pciDevice, !tlp_xmtMetaInFlight && tlp_xmtMetaOK && tlp_postSeqDwell == 4'd0 ; - assign idx__h19187 = 2'd0 - tlp_tlpBRAM_writeDWAddr[1:0] ; - assign idx__h21418 = 2'd1 - tlp_tlpBRAM_writeDWAddr[1:0] ; - assign idx__h22722 = 2'd2 - tlp_tlpBRAM_writeDWAddr[1:0] ; - assign idx__h24026 = 2'd3 - tlp_tlpBRAM_writeDWAddr[1:0] ; - assign idx__h26267 = 2'd0 - tlp_tlpBRAM_readNxtDWAddr[1:0] ; - assign idx__h26735 = 2'd1 - tlp_tlpBRAM_readNxtDWAddr[1:0] ; - assign idx__h27108 = 2'd2 - tlp_tlpBRAM_readNxtDWAddr[1:0] ; - assign idx__h27481 = 2'd3 - tlp_tlpBRAM_readNxtDWAddr[1:0] ; - assign lastBE__h46542 = - tlp_tlpBRAM_mRespF_first__108_BITS_71_TO_62_20_ETC___d2421 ? + assign idx__h19271 = 2'd0 - tlp_tlpBRAM_writeDWAddr[1:0] ; + assign idx__h21502 = 2'd1 - tlp_tlpBRAM_writeDWAddr[1:0] ; + assign idx__h22806 = 2'd2 - tlp_tlpBRAM_writeDWAddr[1:0] ; + assign idx__h24110 = 2'd3 - tlp_tlpBRAM_writeDWAddr[1:0] ; + assign idx__h26351 = 2'd0 - tlp_tlpBRAM_readNxtDWAddr[1:0] ; + assign idx__h26819 = 2'd1 - tlp_tlpBRAM_readNxtDWAddr[1:0] ; + assign idx__h27192 = 2'd2 - tlp_tlpBRAM_readNxtDWAddr[1:0] ; + assign idx__h27565 = 2'd3 - tlp_tlpBRAM_readNxtDWAddr[1:0] ; + assign lastBE__h46626 = + tlp_tlpBRAM_mRespF_first__108_BITS_71_TO_62_20_ETC___d2442 ? 4'd0 : 4'd15 ; - assign lastBE__h62561 = - (thisRequestLength__h62254[11:2] == 10'd1) ? 4'd0 : 4'd15 ; - assign lowAddr__h28411 = - { tlp_tlpBRAM_readReq$D_OUT[33:29], lowAddr10__h28410 } ; - assign mesgMeta_opcode__h80054 = + assign lastBE__h62634 = + (thisRequestLength__h62327[11:2] == 10'd1) ? 4'd0 : 4'd15 ; + assign lowAddr__h28495 = + { tlp_tlpBRAM_readReq$D_OUT[33:29], lowAddr10__h28494 } ; + assign mesgMeta_opcode__h80116 = { 24'h800000, wmi_wmi_mFlagF$D_OUT[31:24] } ; - assign nowLS__h44844 = + assign nowLS__h44928 = { tlp_tlpBRAM_mRespF$D_OUT[39:32], tlp_tlpBRAM_mRespF$D_OUT[47:40], tlp_tlpBRAM_mRespF$D_OUT[55:48], tlp_tlpBRAM_mRespF$D_OUT[63:56] } ; - assign nowLS__h60998 = + assign nowLS__h61073 = { tlp_inF$D_OUT[39:32], tlp_inF$D_OUT[47:40], tlp_inF$D_OUT[55:48], tlp_inF$D_OUT[63:56] } ; - assign nowMS__h43901 = + assign nowMS__h43985 = { tlp_tlpBRAM_mRespF$D_OUT[71:64], tlp_tlpBRAM_mRespF$D_OUT[79:72], tlp_tlpBRAM_mRespF$D_OUT[87:80], tlp_tlpBRAM_mRespF$D_OUT[95:88] } ; - assign nowMS__h60057 = + assign nowMS__h60132 = { tlp_inF$D_OUT[71:64], tlp_inF$D_OUT[79:72], tlp_inF$D_OUT[87:80], tlp_inF$D_OUT[95:88] } ; - assign opcode__h42670 = + assign opcode__h42754 = { tlp_tlpBRAM_mRespF$D_OUT[103:96], tlp_tlpBRAM_mRespF$D_OUT[111:104], tlp_tlpBRAM_mRespF$D_OUT[119:112], tlp_tlpBRAM_mRespF$D_OUT[127:120] } ; - assign opcode__h58837 = + assign opcode__h58912 = { tlp_inF$D_OUT[103:96], tlp_inF$D_OUT[111:104], tlp_inF$D_OUT[119:112], tlp_inF$D_OUT[127:120] } ; - assign pkt__h70068 = + assign pkt__h70132 = { 9'd148, tlp_tlpBRAM_mRespF$D_OUT[34:32], 10'd0, @@ -6619,76 +6619,76 @@ module mkOCDP4B(pciDevice, 1'b0, tlp_tlpBRAM_mRespF$D_OUT[61:55], tlp_tlpBRAM_mRespF$D_OUT[31:0] } ; - assign rdat__h89719 = { 16'd0, bml_lclNumBufs } ; - assign rdat__h89727 = { 16'd0, bml_fabNumBufs } ; - assign rdat__h89735 = { 16'd0, bml_mesgBase } ; - assign rdat__h89743 = { 16'd0, bml_metaBase } ; - assign rdat__h89751 = { 16'd0, bml_mesgSize } ; - assign rdat__h89759 = { 16'd0, bml_metaSize } ; - assign rdat__h89767 = { 16'd0, bml_lclBufsCF } ; - assign rdat__h89788 = + assign rdat__h89781 = { 16'd0, bml_lclNumBufs } ; + assign rdat__h89789 = { 16'd0, bml_fabNumBufs } ; + assign rdat__h89797 = { 16'd0, bml_mesgBase } ; + assign rdat__h89805 = { 16'd0, bml_metaBase } ; + assign rdat__h89813 = { 16'd0, bml_mesgSize } ; + assign rdat__h89821 = { 16'd0, bml_metaSize } ; + assign rdat__h89829 = { 16'd0, bml_lclBufsCF } ; + assign rdat__h89850 = hasDebugLogic ? { bml_lclBufsAR, bml_fabBufsAvail } : 32'd0 ; - assign rdat__h89795 = + assign rdat__h89857 = hasDebugLogic ? { bml_remBuf_value, bml_lclBuf_value } : 32'd0 ; - assign rdat__h89808 = + assign rdat__h89870 = hasDebugLogic ? { bml_lclStarts, bml_lclDones } : 32'd0 ; - assign rdat__h89815 = + assign rdat__h89877 = hasDebugLogic ? { bml_remStarts, bml_remDones } : 32'd0 ; - assign rdat__h89822 = hasDebugLogic ? wmi_thisMesg : 32'd0 ; - assign rdat__h90086 = hasDebugLogic ? wmi_lastMesg : 32'd0 ; - assign rdat__h90136 = + assign rdat__h89884 = hasDebugLogic ? wmi_thisMesg : 32'd0 ; + assign rdat__h90148 = hasDebugLogic ? wmi_lastMesg : 32'd0 ; + assign rdat__h90198 = hasDebugLogic ? { wmi_reqCount, wmi_wrtCount } : 32'd0 ; - assign rdat__h90236 = hasDebugLogic ? 32'hDADEBABE : 32'd0 ; - assign rdat__h90294 = { 24'd0, dpControl } ; - assign rdat__h90316 = hasDebugLogic ? tlp_flowDiagCount : 32'd0 ; - assign rdat__h90326 = + assign rdat__h90298 = hasDebugLogic ? 32'hDADEBABE : 32'd0 ; + assign rdat__h90356 = { 24'd0, dpControl } ; + assign rdat__h90378 = hasDebugLogic ? tlp_flowDiagCount : 32'd0 ; + assign rdat__h90388 = hasDebugLogic ? { 4'h0, tlp_complTimerCount, 12'h0, CASE_tlp_lastRuleFired_10_1_tlp_lastRuleFired__ETC__q1 } : 32'd0 ; - assign rdat__h90448 = hasDebugLogic ? tlp_lastMetaV : 32'd0 ; - assign rdat__h90569 = hasDebugLogic ? tlp_lastMetaV_1 : 32'd0 ; - assign rdat__h90598 = hasDebugLogic ? tlp_lastMetaV_2 : 32'd0 ; - assign rdat__h90627 = hasDebugLogic ? tlp_lastMetaV_3 : 32'd0 ; - assign rdat__h90656 = hasDebugLogic ? 32'hC0DE0111 : 32'd0 ; - assign rdat__h90686 = hasDebugLogic ? dmaStartTime[31:0] : 32'd0 ; - assign rdat__h90720 = hasDebugLogic ? dmaStartTime[63:32] : 32'd0 ; - assign rdat__h90753 = hasDebugLogic ? dmaDoneTime[31:0] : 32'd0 ; - assign rdat__h90787 = hasDebugLogic ? dmaDoneTime[63:32] : 32'd0 ; - assign rdata__h33850 = - tlp_tlpBRAM_readReq_first__97_BITS_30_TO_29_99_ETC___d2439[1] ? + assign rdat__h90510 = hasDebugLogic ? tlp_lastMetaV : 32'd0 ; + assign rdat__h90631 = hasDebugLogic ? tlp_lastMetaV_1 : 32'd0 ; + assign rdat__h90660 = hasDebugLogic ? tlp_lastMetaV_2 : 32'd0 ; + assign rdat__h90689 = hasDebugLogic ? tlp_lastMetaV_3 : 32'd0 ; + assign rdat__h90718 = hasDebugLogic ? 32'hC0DE0111 : 32'd0 ; + assign rdat__h90748 = hasDebugLogic ? dmaStartTime[31:0] : 32'd0 ; + assign rdat__h90782 = hasDebugLogic ? dmaStartTime[63:32] : 32'd0 ; + assign rdat__h90815 = hasDebugLogic ? dmaDoneTime[31:0] : 32'd0 ; + assign rdat__h90849 = hasDebugLogic ? dmaDoneTime[63:32] : 32'd0 ; + assign rdata__h33934 = + tlp_tlpBRAM_readReq_first__97_BITS_30_TO_29_99_ETC___d2433[1] ? IF_tlp_tlpBRAM_readReq_first__97_BITS_30_TO_29_ETC___d1037 : IF_tlp_tlpBRAM_readReq_first__97_BITS_30_TO_29_ETC___d1042 ; - assign rreq_tag__h46309 = - (y__h46119 == tlp_mesgLengthRemainPush) ? 8'h01 : 8'h0 ; - assign rresp_data__h28457 = - { IF_tlp_tlpBRAM_readReq_first__97_BITS_30_TO_29_ETC___d2433[7:0], - IF_tlp_tlpBRAM_readReq_first__97_BITS_30_TO_29_ETC___d2433[15:8], - IF_tlp_tlpBRAM_readReq_first__97_BITS_30_TO_29_ETC___d2433[23:16], - IF_tlp_tlpBRAM_readReq_first__97_BITS_30_TO_29_ETC___d2433[31:24] } ; - assign spanToNextPage__h46093 = 13'd4096 - { 1'd0, tlp_srcMesgAccu[11:0] } ; - assign spanToNextPage__h62253 = 13'd4096 - { 1'd0, tlp_fabMesgAccu[11:0] } ; - assign tag__h62529 = { 3'd0, tlp_dmaTag } ; - assign tagm__h62748 = { 3'd0, tlp_dmaReqTag } ; - assign thisRequestLength__h46094 = - (x__h46132[12:0] <= spanToNextPage__h46093) ? - x__h46132[12:0] : - spanToNextPage__h46093 ; - assign thisRequestLength__h62254 = - (x__h62287[12:0] <= spanToNextPage__h62253) ? - x__h62287[12:0] : - spanToNextPage__h62253 ; - assign tlp_dmaPullRemainDWLen_481_ULE_tlp_dmaPullRema_ETC___d2667 = + assign rreq_tag__h46393 = + (y__h46203 == tlp_mesgLengthRemainPush) ? 8'h01 : 8'h0 ; + assign rresp_data__h28541 = + { IF_tlp_tlpBRAM_readReq_first__97_BITS_30_TO_29_ETC___d2432[7:0], + IF_tlp_tlpBRAM_readReq_first__97_BITS_30_TO_29_ETC___d2432[15:8], + IF_tlp_tlpBRAM_readReq_first__97_BITS_30_TO_29_ETC___d2432[23:16], + IF_tlp_tlpBRAM_readReq_first__97_BITS_30_TO_29_ETC___d2432[31:24] } ; + assign spanToNextPage__h46177 = 13'd4096 - { 1'd0, tlp_srcMesgAccu[11:0] } ; + assign spanToNextPage__h62326 = 13'd4096 - { 1'd0, tlp_fabMesgAccu[11:0] } ; + assign tag__h62602 = { 3'd0, tlp_dmaTag } ; + assign tagm__h62820 = { 3'd0, tlp_dmaReqTag } ; + assign thisRequestLength__h46178 = + (x__h46216[12:0] <= spanToNextPage__h46177) ? + x__h46216[12:0] : + spanToNextPage__h46177 ; + assign thisRequestLength__h62327 = + (x__h62360[12:0] <= spanToNextPage__h62326) ? + x__h62360[12:0] : + spanToNextPage__h62326 ; + assign tlp_dmaPullRemainDWLen_479_ULE_tlp_dmaPullRema_ETC___d2654 = tlp_dmaPullRemainDWLen <= tlp_dmaPullRemainDWSub ; - assign tlp_dmaPullRemainDWSub_495_ULE_4___d2668 = + assign tlp_dmaPullRemainDWSub_493_ULE_4___d2655 = tlp_dmaPullRemainDWSub <= 10'd4 ; - assign tlp_inF_first__367_BITS_63_TO_56_370_EQ_pciDev_ETC___d1380 = + assign tlp_inF_first__366_BITS_63_TO_56_369_EQ_pciDev_ETC___d1379 = tlp_inF$D_OUT[63:56] == pciDevice[15:8] && tlp_inF$D_OUT[55:51] == pciDevice[7:3] && tlp_inF$D_OUT[50:48] == pciDevice[2:0] ; - assign tlp_inF_first__367_BIT_152_570_AND_NOT_tlp_inF_ETC___d1595 = + assign tlp_inF_first__366_BIT_152_568_AND_NOT_tlp_inF_ETC___d1592 = tlp_inF$D_OUT[152] && !tlp_inF$D_OUT[110] && !tlp_inF$D_OUT[125] && tlp_inF$D_OUT[124:120] == 5'b0 || @@ -6697,14 +6697,14 @@ module mkOCDP4B(pciDevice, tlp_mesgLengthRemainPull + 17'd3 ; assign tlp_mesgLengthRemainPush_PLUS_3__q16 = tlp_mesgLengthRemainPush + 17'd3 ; - assign tlp_outDwRemain_237_ULE_4___d2605 = tlp_outDwRemain <= 10'd4 ; + assign tlp_outDwRemain_238_ULE_4___d2590 = tlp_outDwRemain <= 10'd4 ; assign tlp_tlpBRAM_mReqF_first__18_BIT_60_02_OR_IF_tl_ETC___d813 = tlp_tlpBRAM_mReqF$D_OUT[60] || CASE_tlp_tlpBRAM_mReqFD_OUT_BITS_30_TO_29_NOT_ETC__q6 ; assign tlp_tlpBRAM_mReqF_first__18_BIT_63_19_OR_IF_tl_ETC___d634 = tlp_tlpBRAM_mReqF$D_OUT[63] || CASE_tlp_tlpBRAM_mReqFD_OUT_BITS_51_TO_50_NOT_ETC__q5 ; - assign tlp_tlpBRAM_mRespF_first__108_BITS_71_TO_62_20_ETC___d2421 = + assign tlp_tlpBRAM_mRespF_first__108_BITS_71_TO_62_20_ETC___d2442 = tlp_tlpBRAM_mRespF$D_OUT[71:62] <= 10'd1 ; assign tlp_tlpBRAM_rdRespDwRemain_024_ULE_4___d1026 = tlp_tlpBRAM_rdRespDwRemain <= 10'd4 ; @@ -6716,7 +6716,7 @@ module mkOCDP4B(pciDevice, tlp_tlpBRAM_readNxtDWAddr + 13'd3 ; assign tlp_tlpBRAM_readRemainDWLen_46_ULE_4___d847 = tlp_tlpBRAM_readRemainDWLen <= 10'd4 ; - assign tlp_tlpBRAM_readReq_first__97_BITS_30_TO_29_99_ETC___d2439 = + assign tlp_tlpBRAM_readReq_first__97_BITS_30_TO_29_99_ETC___d2433 = tlp_tlpBRAM_readReq$D_OUT[30:29] + (tlp_tlpBRAM_readReq$D_OUT[60] ? 2'd0 : 2'd1) ; assign tlp_tlpBRAM_writeDWAddr_PLUS_1__q10 = @@ -6725,35 +6725,35 @@ module mkOCDP4B(pciDevice, tlp_tlpBRAM_writeDWAddr + 13'd2 ; assign tlp_tlpBRAM_writeDWAddr_PLUS_3__q9 = tlp_tlpBRAM_writeDWAddr + 13'd3 ; - assign tlp_tlpBRAM_writeRemainDWLen_62_ULE_1___d2437 = + assign tlp_tlpBRAM_writeRemainDWLen_62_ULE_1___d2440 = tlp_tlpBRAM_writeRemainDWLen <= 10'd1 ; - assign tlp_tlpBRAM_writeRemainDWLen_62_ULE_2___d2430 = + assign tlp_tlpBRAM_writeRemainDWLen_62_ULE_2___d2431 = tlp_tlpBRAM_writeRemainDWLen <= 10'd2 ; - assign tlp_tlpBRAM_writeRemainDWLen_62_ULE_3___d2413 = + assign tlp_tlpBRAM_writeRemainDWLen_62_ULE_3___d2441 = tlp_tlpBRAM_writeRemainDWLen <= 10'd3 ; - assign w_be__h47101 = - tlp_outDwRemain_237_ULE_4___d2605 ? + assign w_be__h47184 = + tlp_outDwRemain_238_ULE_4___d2590 ? CASE_tlp_outDwRemain_BITS_1_TO_0_0xFFF0_0b0_0x_ETC__q4 : 16'd65535 ; - assign w_data__h46507 = + assign w_data__h46591 = { 22'd1048576, tlp_tlpBRAM_mRespF$D_OUT[71:62], pciDevice, 8'd0, - lastBE__h46542, + lastBE__h46626, 4'd15, tlp_fabMesgAccu, tlp_tlpBRAM_mRespF$D_OUT[31:0] } ; - assign w_data__h46644 = + assign w_data__h46728 = { 22'd1572864, tlp_tlpBRAM_mRespF$D_OUT[71:62], pciDevice, 8'd0, - lastBE__h46542, + lastBE__h46626, 4'd15, tlp_fabMesgAddrMS, tlp_fabMesgAccu } ; - assign w_data__h51409 = + assign w_data__h51490 = { tlp_fabMeta[103:96], tlp_fabMeta[111:104], tlp_fabMeta[119:112], @@ -6770,7 +6770,7 @@ module mkOCDP4B(pciDevice, tlp_fabMeta[15:8], tlp_fabMeta[23:16], tlp_fabMeta[31:24] } ; - assign w_data__h64198 = + assign w_data__h64265 = { 32'd1073741825, pciDevice, 16'd15, @@ -6780,122 +6780,122 @@ module mkOCDP4B(pciDevice, wti_nowReq_BITS_63_TO_0__q2[20:13], wti_nowReq_BITS_63_TO_0__q2[28:21], wti_nowReq_BITS_63_TO_0__q2[36:29] } ; - assign w_data__h65286 = + assign w_data__h65353 = { 32'd1610612737, pciDevice, 16'd15, tlp_fabFlowAddrMS, tlp_fabFlowAddr } ; - assign w_data__h65532 = + assign w_data__h65599 = { wti_nowReq_BITS_63_TO_0__q2[12:6], 1'd1, wti_nowReq_BITS_63_TO_0__q2[20:13], wti_nowReq_BITS_63_TO_0__q2[28:21], wti_nowReq_BITS_63_TO_0__q2[36:29], 96'd0 } ; - assign wmi_dpControl_whas__763_AND_bram_serverAdapter_ETC___d1809 = + assign wmi_dpControl_whas__760_AND_bram_serverAdapter_ETC___d1806 = (bram_serverAdapterB_outDataCore$EMPTY_N || bram_serverAdapterB_outData_enqData$whas) && bram_serverAdapterB_outData_outData$whas && (bram_serverAdapterB_1_outDataCore$EMPTY_N || bram_serverAdapterB_1_outData_enqData$whas) && - bram_serverAdapterB_1_outData_outData_whas__79_ETC___d1805 ; - assign wmi_wmi_operateD_716_AND_wmi_wmi_peerIsReady_7_ETC___d1891 = + bram_serverAdapterB_1_outData_outData_whas__79_ETC___d1802 ; + assign wmi_wmi_operateD_713_AND_wmi_wmi_peerIsReady_7_ETC___d1888 = wmi_wmi_operateD && wmi_wmi_peerIsReady && - bram_serverAdapterB_cnt_5_SLT_3___d1776 && - bram_serverAdapterB_1_cnt_03_SLT_3___d1777 && - bram_serverAdapterB_2_cnt_21_SLT_3___d1778 && - bram_serverAdapterB_3_cnt_39_SLT_3___d1779 && + bram_serverAdapterB_cnt_5_SLT_3___d1773 && + bram_serverAdapterB_1_cnt_03_SLT_3___d1774 && + bram_serverAdapterB_2_cnt_21_SLT_3___d1775 && + bram_serverAdapterB_3_cnt_39_SLT_3___d1776 && wmi_wmi_mFlagF$EMPTY_N ; assign wti_nowReq_BITS_63_TO_0__q2 = wti_nowReq[63:0] ; - assign x3__h80014 = { 8'd0, wmi_wmi_mFlagF$D_OUT[23:0] } ; - assign x__h28530 = x__h28532 - y__h28533 ; - assign x__h28532 = { tlp_tlpBRAM_readReq$D_OUT[28:19], 2'b0 } ; - assign x__h40887 = + assign x3__h80076 = { 8'd0, wmi_wmi_mFlagF$D_OUT[23:0] } ; + assign x__h28614 = x__h28616 - y__h28617 ; + assign x__h28616 = { tlp_tlpBRAM_readReq$D_OUT[28:19], 2'b0 } ; + assign x__h40971 = { tlp_tlpBRAM_mRespF$D_OUT[7:0], tlp_tlpBRAM_mRespF$D_OUT[15:8], tlp_tlpBRAM_mRespF$D_OUT[23:16], tlp_tlpBRAM_mRespF$D_OUT[31:24] } ; - assign x__h45847 = { 15'd0, tlp_mesgLengthRemainPush } ; - assign x__h46132 = - (tlp_mesgLengthRemainPush <= y__h46134) ? + assign x__h45931 = { 15'd0, tlp_mesgLengthRemainPush } ; + assign x__h46216 = + (tlp_mesgLengthRemainPush <= y__h46218) ? tlp_mesgLengthRemainPush : - y__h46134 ; - assign x__h56804 = + y__h46218 ; + assign x__h56883 = { tlp_inF$D_OUT[7:0], tlp_inF$D_OUT[15:8], tlp_inF$D_OUT[23:16], tlp_inF$D_OUT[31:24] } ; - assign x__h61968 = { 15'd0, tlp_mesgLengthRemainPull } ; - assign x__h62287 = - (tlp_mesgLengthRemainPull <= y__h62289) ? + assign x__h62043 = { 15'd0, tlp_mesgLengthRemainPull } ; + assign x__h62360 = + (tlp_mesgLengthRemainPull <= y__h62362) ? tlp_mesgLengthRemainPull : - y__h62289 ; - assign x__h86368 = (dpControl[1:0] == 2'd1) ? bml_fabNumBufs : 16'd0 ; - assign x__h87496 = bml_lclBufsAR + 16'd1 ; - assign x__h87501 = bml_lclBufsAR - 16'd1 ; - assign x__h87608 = bml_lclBufsCF + 16'd1 ; - assign x__h87645 = bml_lclBufsCF - 16'd1 ; - assign x__h87727 = bml_fabBufsAvail + 16'd1 ; - assign x__h87732 = bml_fabBufsAvail - 16'd1 ; - assign x__h87766 = bml_lclCredit + 16'd1 ; - assign x__h87771 = bml_lclCredit - 16'd1 ; - assign y__h17488 = tlp_tlpBRAM_mReqF$D_OUT[63] ? 13'd0 : 13'd1 ; - assign y__h17555 = tlp_tlpBRAM_mReqF$D_OUT[63] ? 10'd0 : 10'd1 ; - assign y__h26037 = tlp_tlpBRAM_mReqF$D_OUT[60] ? 10'd0 : 10'd1 ; - assign y__h26049 = tlp_tlpBRAM_mReqF$D_OUT[60] ? 13'd0 : 13'd1 ; - assign y__h28531 = + y__h62362 ; + assign x__h86430 = (dpControl[1:0] == 2'd1) ? bml_fabNumBufs : 16'd0 ; + assign x__h87558 = bml_lclBufsAR + 16'd1 ; + assign x__h87563 = bml_lclBufsAR - 16'd1 ; + assign x__h87670 = bml_lclBufsCF + 16'd1 ; + assign x__h87707 = bml_lclBufsCF - 16'd1 ; + assign x__h87789 = bml_fabBufsAvail + 16'd1 ; + assign x__h87794 = bml_fabBufsAvail - 16'd1 ; + assign x__h87828 = bml_lclCredit + 16'd1 ; + assign x__h87833 = bml_lclCredit - 16'd1 ; + assign y__h17572 = tlp_tlpBRAM_mReqF$D_OUT[63] ? 13'd0 : 13'd1 ; + assign y__h17639 = tlp_tlpBRAM_mReqF$D_OUT[63] ? 10'd0 : 10'd1 ; + assign y__h26121 = tlp_tlpBRAM_mReqF$D_OUT[60] ? 10'd0 : 10'd1 ; + assign y__h26133 = tlp_tlpBRAM_mReqF$D_OUT[60] ? 13'd0 : 13'd1 ; + assign y__h28615 = (tlp_tlpBRAM_readReq$D_OUT[28:19] == 10'd1) ? 12'd0 : - { 10'd0, x__h28562 } ; - assign y__h28533 = { 10'd0, x__h28539 } ; - assign y__h29472 = tlp_tlpBRAM_readReq$D_OUT[60] ? 10'd0 : 10'd1 ; - assign y__h46119 = { 4'd0, thisRequestLength__h46094 } ; - assign y__h46134 = { 4'd0, tlp_maxPayloadSize } ; - assign y__h46213 = { 19'd0, thisRequestLength__h46094 } ; - assign y__h46261 = { 3'd0, thisRequestLength__h46094 } ; - assign y__h46739 = (tlp_fabMesgAddrMS == 32'd0) ? 10'd1 : 10'd0 ; - assign y__h46773 = { 20'd0, tlp_tlpBRAM_mRespF$D_OUT[71:62], 2'd0 } ; - assign y__h62279 = { 4'd0, thisRequestLength__h62254 } ; - assign y__h62289 = { 4'd0, tlp_maxReadReqSize } ; - assign y__h62350 = { 19'd0, thisRequestLength__h62254 } ; - assign y__h62959 = { 4'd0, tlp_inF$D_OUT[105:96], 2'd0 } ; - assign y__h63671 = - tlp_dmaPullRemainDWSub_495_ULE_4___d2668 ? + { 10'd0, x__h28646 } ; + assign y__h28617 = { 10'd0, x__h28623 } ; + assign y__h29556 = tlp_tlpBRAM_readReq$D_OUT[60] ? 10'd0 : 10'd1 ; + assign y__h46203 = { 4'd0, thisRequestLength__h46178 } ; + assign y__h46218 = { 4'd0, tlp_maxPayloadSize } ; + assign y__h46297 = { 19'd0, thisRequestLength__h46178 } ; + assign y__h46345 = { 3'd0, thisRequestLength__h46178 } ; + assign y__h46823 = (tlp_fabMesgAddrMS == 32'd0) ? 10'd1 : 10'd0 ; + assign y__h46857 = { 20'd0, tlp_tlpBRAM_mRespF$D_OUT[71:62], 2'd0 } ; + assign y__h62352 = { 4'd0, thisRequestLength__h62327 } ; + assign y__h62362 = { 4'd0, tlp_maxReadReqSize } ; + assign y__h62423 = { 19'd0, thisRequestLength__h62327 } ; + assign y__h63030 = { 4'd0, tlp_inF$D_OUT[105:96], 2'd0 } ; + assign y__h63740 = + tlp_dmaPullRemainDWSub_493_ULE_4___d2655 ? { 5'd0, tlp_dmaPullRemainDWSub, 2'd0 } : 17'd16 ; - assign y_avValue__h81613 = + assign y_avValue__h81675 = bram_serverAdapterB_outDataCore$EMPTY_N ? bram_serverAdapterB_outDataCore$D_OUT : bram_memory$DOB ; - assign y_avValue__h81633 = + assign y_avValue__h81695 = bram_serverAdapterB_1_outDataCore$EMPTY_N ? bram_serverAdapterB_1_outDataCore$D_OUT : bram_memory_1$DOB ; - assign y_avValue__h81653 = + assign y_avValue__h81715 = bram_serverAdapterB_2_outDataCore$EMPTY_N ? bram_serverAdapterB_2_outDataCore$D_OUT : bram_memory_2$DOB ; - assign y_avValue__h81673 = + assign y_avValue__h81735 = bram_serverAdapterB_3_outDataCore$EMPTY_N ? bram_serverAdapterB_3_outDataCore$D_OUT : bram_memory_3$DOB ; always@(tlp_tlpBRAM_readReq$D_OUT) begin - case (tlp_tlpBRAM_readReq$D_OUT[18:15]) - 4'b1100: x__h28539 = 2'b10; - 4'b1110: x__h28539 = 2'b01; - 4'b1111: x__h28539 = 2'b0; - default: x__h28539 = 2'b11; + case (tlp_tlpBRAM_readReq$D_OUT[14:11]) + 4'b1100: x__h28646 = 2'b10; + 4'b1110: x__h28646 = 2'b01; + 4'b1111: x__h28646 = 2'b0; + default: x__h28646 = 2'b11; endcase end always@(tlp_tlpBRAM_readReq$D_OUT) begin - case (tlp_tlpBRAM_readReq$D_OUT[14:11]) - 4'b1100: x__h28562 = 2'b10; - 4'b1110: x__h28562 = 2'b01; - 4'b1111: x__h28562 = 2'b0; - default: x__h28562 = 2'b11; + case (tlp_tlpBRAM_readReq$D_OUT[18:15]) + 4'b1100: x__h28623 = 2'b10; + 4'b1110: x__h28623 = 2'b01; + 4'b1111: x__h28623 = 2'b0; + default: x__h28623 = 2'b11; endcase end always@(tlp_lastRuleFired) @@ -6907,114 +6907,114 @@ module mkOCDP4B(pciDevice, default: CASE_tlp_lastRuleFired_10_1_tlp_lastRuleFired__ETC__q1 = 4'd10; endcase end + always@(wmi_p4B or + y_avValue__h81735 or + y_avValue__h81675 or y_avValue__h81695 or y_avValue__h81715) + begin + case (wmi_p4B) + 2'd0: rdata__h81839 = y_avValue__h81675; + 2'd1: rdata__h81839 = y_avValue__h81695; + 2'd2: rdata__h81839 = y_avValue__h81715; + 2'd3: rdata__h81839 = y_avValue__h81735; + endcase + end always@(wci_reqF$D_OUT or - rdat__h89719 or - rdat__h89727 or - rdat__h89735 or - rdat__h89743 or - rdat__h89751 or - rdat__h89759 or - rdat__h89767 or - rdat__h89788 or - rdat__h89795 or - rdat__h89808 or - rdat__h89815 or - rdat__h89822 or - rdat__h90086 or - rdat__h90136 or - rdat__h90236 or + rdat__h89781 or + rdat__h89789 or + rdat__h89797 or + rdat__h89805 or + rdat__h89813 or + rdat__h89821 or + rdat__h89829 or + rdat__h89850 or + rdat__h89857 or + rdat__h89870 or + rdat__h89877 or + rdat__h89884 or + rdat__h90148 or + rdat__h90198 or + rdat__h90298 or bml_fabMesgBase or bml_fabMetaBase or bml_fabMesgSize or bml_fabMetaSize or bml_fabFlowBase or bml_fabFlowSize or - rdat__h90294 or - rdat__h90316 or - rdat__h90326 or - rdat__h90448 or - rdat__h90569 or - rdat__h90598 or - rdat__h90627 or - rdat__h90656 or + rdat__h90356 or + rdat__h90378 or + rdat__h90388 or + rdat__h90510 or + rdat__h90631 or + rdat__h90660 or + rdat__h90689 or + rdat__h90718 or bml_fabMesgBaseMS or bml_fabMetaBaseMS or bml_fabFlowBaseMS or - rdat__h90686 or rdat__h90720 or rdat__h90753 or rdat__h90787) + rdat__h90748 or rdat__h90782 or rdat__h90815 or rdat__h90849) begin case (wci_reqF$D_OUT[39:32]) - 8'h0: _theResult____h89640 = rdat__h89719; - 8'h04: _theResult____h89640 = rdat__h89727; - 8'h08: _theResult____h89640 = rdat__h89735; - 8'h0C: _theResult____h89640 = rdat__h89743; - 8'h10: _theResult____h89640 = rdat__h89751; - 8'h14: _theResult____h89640 = rdat__h89759; - 8'h20: _theResult____h89640 = rdat__h89767; - 8'h24: _theResult____h89640 = 32'hF00DFACE; - 8'h28: _theResult____h89640 = rdat__h89788; - 8'h2C: _theResult____h89640 = rdat__h89795; - 8'h30: _theResult____h89640 = rdat__h89808; - 8'h34: _theResult____h89640 = rdat__h89815; - 8'h38: _theResult____h89640 = rdat__h89822; - 8'h3C: _theResult____h89640 = rdat__h90086; - 8'h40: _theResult____h89640 = rdat__h90136; - 8'h44: _theResult____h89640 = 32'd0; - 8'h48: _theResult____h89640 = rdat__h90236; - 8'h4C: _theResult____h89640 = 32'h00008000; - 8'h50: _theResult____h89640 = bml_fabMesgBase; - 8'h54: _theResult____h89640 = bml_fabMetaBase; - 8'h58: _theResult____h89640 = bml_fabMesgSize; - 8'h5C: _theResult____h89640 = bml_fabMetaSize; - 8'h60: _theResult____h89640 = bml_fabFlowBase; - 8'h64: _theResult____h89640 = bml_fabFlowSize; - 8'h68: _theResult____h89640 = rdat__h90294; - 8'h6C: _theResult____h89640 = rdat__h90316; - 8'h70: _theResult____h89640 = rdat__h90326; - 8'h80: _theResult____h89640 = rdat__h90448; - 8'h84: _theResult____h89640 = rdat__h90569; - 8'h88: _theResult____h89640 = rdat__h90598; - 8'h8C: _theResult____h89640 = rdat__h90627; - 8'h90: _theResult____h89640 = rdat__h90656; - 8'h94: _theResult____h89640 = bml_fabMesgBaseMS; - 8'h98: _theResult____h89640 = bml_fabMetaBaseMS; - 8'h9C: _theResult____h89640 = bml_fabFlowBaseMS; - 8'hA0: _theResult____h89640 = rdat__h90686; - 8'hA4: _theResult____h89640 = rdat__h90720; - 8'hA8: _theResult____h89640 = rdat__h90753; - 8'hAC: _theResult____h89640 = rdat__h90787; - default: _theResult____h89640 = 32'd0; - endcase - end - always@(wmi_p4B or - y_avValue__h81673 or - y_avValue__h81613 or y_avValue__h81633 or y_avValue__h81653) - begin - case (wmi_p4B) - 2'd0: rdata__h81777 = y_avValue__h81613; - 2'd1: rdata__h81777 = y_avValue__h81633; - 2'd2: rdata__h81777 = y_avValue__h81653; - 2'd3: rdata__h81777 = y_avValue__h81673; + 8'h0: _theResult____h89702 = rdat__h89781; + 8'h04: _theResult____h89702 = rdat__h89789; + 8'h08: _theResult____h89702 = rdat__h89797; + 8'h0C: _theResult____h89702 = rdat__h89805; + 8'h10: _theResult____h89702 = rdat__h89813; + 8'h14: _theResult____h89702 = rdat__h89821; + 8'h20: _theResult____h89702 = rdat__h89829; + 8'h24: _theResult____h89702 = 32'hF00DFACE; + 8'h28: _theResult____h89702 = rdat__h89850; + 8'h2C: _theResult____h89702 = rdat__h89857; + 8'h30: _theResult____h89702 = rdat__h89870; + 8'h34: _theResult____h89702 = rdat__h89877; + 8'h38: _theResult____h89702 = rdat__h89884; + 8'h3C: _theResult____h89702 = rdat__h90148; + 8'h40: _theResult____h89702 = rdat__h90198; + 8'h44: _theResult____h89702 = 32'd0; + 8'h48: _theResult____h89702 = rdat__h90298; + 8'h4C: _theResult____h89702 = 32'h00008000; + 8'h50: _theResult____h89702 = bml_fabMesgBase; + 8'h54: _theResult____h89702 = bml_fabMetaBase; + 8'h58: _theResult____h89702 = bml_fabMesgSize; + 8'h5C: _theResult____h89702 = bml_fabMetaSize; + 8'h60: _theResult____h89702 = bml_fabFlowBase; + 8'h64: _theResult____h89702 = bml_fabFlowSize; + 8'h68: _theResult____h89702 = rdat__h90356; + 8'h6C: _theResult____h89702 = rdat__h90378; + 8'h70: _theResult____h89702 = rdat__h90388; + 8'h80: _theResult____h89702 = rdat__h90510; + 8'h84: _theResult____h89702 = rdat__h90631; + 8'h88: _theResult____h89702 = rdat__h90660; + 8'h8C: _theResult____h89702 = rdat__h90689; + 8'h90: _theResult____h89702 = rdat__h90718; + 8'h94: _theResult____h89702 = bml_fabMesgBaseMS; + 8'h98: _theResult____h89702 = bml_fabMetaBaseMS; + 8'h9C: _theResult____h89702 = bml_fabFlowBaseMS; + 8'hA0: _theResult____h89702 = rdat__h90748; + 8'hA4: _theResult____h89702 = rdat__h90782; + 8'hA8: _theResult____h89702 = rdat__h90815; + 8'hAC: _theResult____h89702 = rdat__h90849; + default: _theResult____h89702 = 32'd0; endcase end always@(tlp_tlpBRAM_readReq$D_OUT) begin case (tlp_tlpBRAM_readReq$D_OUT[18:15]) - 4'b1000: lowAddr10__h28410 = 2'b11; - 4'b1100: lowAddr10__h28410 = 2'b10; - 4'b1110: lowAddr10__h28410 = 2'b01; - default: lowAddr10__h28410 = 2'b0; + 4'b1000: lowAddr10__h28494 = 2'b11; + 4'b1100: lowAddr10__h28494 = 2'b10; + 4'b1110: lowAddr10__h28494 = 2'b01; + default: lowAddr10__h28494 = 2'b0; endcase end always@(dpControl or bml_fabDone or bml_remDone) begin case (dpControl[1:0]) 2'd0: - IF_bml_dpControl_wget__029_BITS_1_TO_0_035_EQ__ETC___d2106 = + IF_bml_dpControl_wget__026_BITS_1_TO_0_032_EQ__ETC___d2103 = bml_fabDone; 2'd1: - IF_bml_dpControl_wget__029_BITS_1_TO_0_035_EQ__ETC___d2106 = + IF_bml_dpControl_wget__026_BITS_1_TO_0_032_EQ__ETC___d2103 = bml_remDone; - default: IF_bml_dpControl_wget__029_BITS_1_TO_0_035_EQ__ETC___d2106 = + default: IF_bml_dpControl_wget__026_BITS_1_TO_0_032_EQ__ETC___d2103 = bml_fabDone; endcase end @@ -7042,154 +7042,154 @@ module mkOCDP4B(pciDevice, 2'd3: CASE_tlp_outDwRemain_BITS_1_TO_0_0xFFF0_0b0_0x_ETC__q4 = 16'hFFF0; endcase end - always@(idx__h19187 or - tlp_tlpBRAM_writeRemainDWLen_62_ULE_3___d2413 or + always@(idx__h19271 or + tlp_tlpBRAM_writeRemainDWLen_62_ULE_3___d2441 or tlp_tlpBRAM_writeRemainDWLen or - tlp_tlpBRAM_writeRemainDWLen_62_ULE_1___d2437 or - tlp_tlpBRAM_writeRemainDWLen_62_ULE_2___d2430) + tlp_tlpBRAM_writeRemainDWLen_62_ULE_1___d2440 or + tlp_tlpBRAM_writeRemainDWLen_62_ULE_2___d2431) begin - case (idx__h19187) + case (idx__h19271) 2'd0: IF_0_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d675 = tlp_tlpBRAM_writeRemainDWLen == 10'd0; 2'd1: IF_0_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d675 = - tlp_tlpBRAM_writeRemainDWLen_62_ULE_1___d2437; + tlp_tlpBRAM_writeRemainDWLen_62_ULE_1___d2440; 2'd2: IF_0_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d675 = - tlp_tlpBRAM_writeRemainDWLen_62_ULE_2___d2430; + tlp_tlpBRAM_writeRemainDWLen_62_ULE_2___d2431; 2'd3: IF_0_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d675 = - tlp_tlpBRAM_writeRemainDWLen_62_ULE_3___d2413; + tlp_tlpBRAM_writeRemainDWLen_62_ULE_3___d2441; endcase end - always@(idx__h21418 or - tlp_tlpBRAM_writeRemainDWLen_62_ULE_3___d2413 or + always@(idx__h21502 or + tlp_tlpBRAM_writeRemainDWLen_62_ULE_3___d2441 or tlp_tlpBRAM_writeRemainDWLen or - tlp_tlpBRAM_writeRemainDWLen_62_ULE_1___d2437 or - tlp_tlpBRAM_writeRemainDWLen_62_ULE_2___d2430) + tlp_tlpBRAM_writeRemainDWLen_62_ULE_1___d2440 or + tlp_tlpBRAM_writeRemainDWLen_62_ULE_2___d2431) begin - case (idx__h21418) + case (idx__h21502) 2'd0: IF_1_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d685 = tlp_tlpBRAM_writeRemainDWLen == 10'd0; 2'd1: IF_1_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d685 = - tlp_tlpBRAM_writeRemainDWLen_62_ULE_1___d2437; + tlp_tlpBRAM_writeRemainDWLen_62_ULE_1___d2440; 2'd2: IF_1_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d685 = - tlp_tlpBRAM_writeRemainDWLen_62_ULE_2___d2430; + tlp_tlpBRAM_writeRemainDWLen_62_ULE_2___d2431; 2'd3: IF_1_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d685 = - tlp_tlpBRAM_writeRemainDWLen_62_ULE_3___d2413; + tlp_tlpBRAM_writeRemainDWLen_62_ULE_3___d2441; endcase end - always@(idx__h22722 or - tlp_tlpBRAM_writeRemainDWLen_62_ULE_3___d2413 or + always@(idx__h22806 or + tlp_tlpBRAM_writeRemainDWLen_62_ULE_3___d2441 or tlp_tlpBRAM_writeRemainDWLen or - tlp_tlpBRAM_writeRemainDWLen_62_ULE_1___d2437 or - tlp_tlpBRAM_writeRemainDWLen_62_ULE_2___d2430) + tlp_tlpBRAM_writeRemainDWLen_62_ULE_1___d2440 or + tlp_tlpBRAM_writeRemainDWLen_62_ULE_2___d2431) begin - case (idx__h22722) + case (idx__h22806) 2'd0: IF_2_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d695 = tlp_tlpBRAM_writeRemainDWLen == 10'd0; 2'd1: IF_2_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d695 = - tlp_tlpBRAM_writeRemainDWLen_62_ULE_1___d2437; + tlp_tlpBRAM_writeRemainDWLen_62_ULE_1___d2440; 2'd2: IF_2_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d695 = - tlp_tlpBRAM_writeRemainDWLen_62_ULE_2___d2430; + tlp_tlpBRAM_writeRemainDWLen_62_ULE_2___d2431; 2'd3: IF_2_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d695 = - tlp_tlpBRAM_writeRemainDWLen_62_ULE_3___d2413; + tlp_tlpBRAM_writeRemainDWLen_62_ULE_3___d2441; endcase end - always@(idx__h24026 or - tlp_tlpBRAM_writeRemainDWLen_62_ULE_3___d2413 or + always@(idx__h24110 or + tlp_tlpBRAM_writeRemainDWLen_62_ULE_3___d2441 or tlp_tlpBRAM_writeRemainDWLen or - tlp_tlpBRAM_writeRemainDWLen_62_ULE_1___d2437 or - tlp_tlpBRAM_writeRemainDWLen_62_ULE_2___d2430) + tlp_tlpBRAM_writeRemainDWLen_62_ULE_1___d2440 or + tlp_tlpBRAM_writeRemainDWLen_62_ULE_2___d2431) begin - case (idx__h24026) + case (idx__h24110) 2'd0: IF_3_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d705 = tlp_tlpBRAM_writeRemainDWLen == 10'd0; 2'd1: IF_3_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d705 = - tlp_tlpBRAM_writeRemainDWLen_62_ULE_1___d2437; + tlp_tlpBRAM_writeRemainDWLen_62_ULE_1___d2440; 2'd2: IF_3_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d705 = - tlp_tlpBRAM_writeRemainDWLen_62_ULE_2___d2430; + tlp_tlpBRAM_writeRemainDWLen_62_ULE_2___d2431; 2'd3: IF_3_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d705 = - tlp_tlpBRAM_writeRemainDWLen_62_ULE_3___d2413; + tlp_tlpBRAM_writeRemainDWLen_62_ULE_3___d2441; endcase end always@(tlp_tlpBRAM_mReqF$D_OUT or - bram_serverAdapterA_3_cnt_80_SLT_3___d2504 or - bram_serverAdapterA_cnt_6_SLT_3___d2670 or - bram_serverAdapterA_1_cnt_44_SLT_3___d2671 or - bram_serverAdapterA_2_cnt_62_SLT_3___d2672) + bram_serverAdapterA_3_cnt_80_SLT_3___d2659 or + bram_serverAdapterA_cnt_6_SLT_3___d2657 or + bram_serverAdapterA_1_cnt_44_SLT_3___d2658 or + bram_serverAdapterA_2_cnt_62_SLT_3___d2418) begin case (tlp_tlpBRAM_mReqF$D_OUT[51:50]) 2'd0: CASE_tlp_tlpBRAM_mReqFD_OUT_BITS_51_TO_50_NOT_ETC__q5 = - bram_serverAdapterA_cnt_6_SLT_3___d2670; + bram_serverAdapterA_cnt_6_SLT_3___d2657; 2'd1: CASE_tlp_tlpBRAM_mReqFD_OUT_BITS_51_TO_50_NOT_ETC__q5 = - bram_serverAdapterA_1_cnt_44_SLT_3___d2671; + bram_serverAdapterA_1_cnt_44_SLT_3___d2658; 2'd2: CASE_tlp_tlpBRAM_mReqFD_OUT_BITS_51_TO_50_NOT_ETC__q5 = - bram_serverAdapterA_2_cnt_62_SLT_3___d2672; + bram_serverAdapterA_2_cnt_62_SLT_3___d2418; 2'd3: CASE_tlp_tlpBRAM_mReqFD_OUT_BITS_51_TO_50_NOT_ETC__q5 = tlp_tlpBRAM_mReqF$D_OUT[51:50] != 2'd3 || - bram_serverAdapterA_3_cnt_80_SLT_3___d2504; + bram_serverAdapterA_3_cnt_80_SLT_3___d2659; endcase end always@(tlp_tlpBRAM_mReqF$D_OUT or - bram_serverAdapterA_3_cnt_80_SLT_3___d2504 or - bram_serverAdapterA_cnt_6_SLT_3___d2670 or - bram_serverAdapterA_1_cnt_44_SLT_3___d2671 or - bram_serverAdapterA_2_cnt_62_SLT_3___d2672) + bram_serverAdapterA_3_cnt_80_SLT_3___d2659 or + bram_serverAdapterA_cnt_6_SLT_3___d2657 or + bram_serverAdapterA_1_cnt_44_SLT_3___d2658 or + bram_serverAdapterA_2_cnt_62_SLT_3___d2418) begin case (tlp_tlpBRAM_mReqF$D_OUT[30:29]) 2'd0: CASE_tlp_tlpBRAM_mReqFD_OUT_BITS_30_TO_29_NOT_ETC__q6 = - bram_serverAdapterA_cnt_6_SLT_3___d2670; + bram_serverAdapterA_cnt_6_SLT_3___d2657; 2'd1: CASE_tlp_tlpBRAM_mReqFD_OUT_BITS_30_TO_29_NOT_ETC__q6 = - bram_serverAdapterA_1_cnt_44_SLT_3___d2671; + bram_serverAdapterA_1_cnt_44_SLT_3___d2658; 2'd2: CASE_tlp_tlpBRAM_mReqFD_OUT_BITS_30_TO_29_NOT_ETC__q6 = - bram_serverAdapterA_2_cnt_62_SLT_3___d2672; + bram_serverAdapterA_2_cnt_62_SLT_3___d2418; 2'd3: CASE_tlp_tlpBRAM_mReqFD_OUT_BITS_30_TO_29_NOT_ETC__q6 = tlp_tlpBRAM_mReqF$D_OUT[30:29] != 2'd3 || - bram_serverAdapterA_3_cnt_80_SLT_3___d2504; + bram_serverAdapterA_3_cnt_80_SLT_3___d2659; endcase end always@(wmi_addr or - bram_serverAdapterB_3_cnt_39_SLT_3___d1779 or - bram_serverAdapterB_cnt_5_SLT_3___d1776 or - bram_serverAdapterB_1_cnt_03_SLT_3___d1777 or - bram_serverAdapterB_2_cnt_21_SLT_3___d1778) + bram_serverAdapterB_3_cnt_39_SLT_3___d1776 or + bram_serverAdapterB_cnt_5_SLT_3___d1773 or + bram_serverAdapterB_1_cnt_03_SLT_3___d1774 or + bram_serverAdapterB_2_cnt_21_SLT_3___d1775) begin case (wmi_addr[3:2]) 2'd0: - IF_wmi_addr_855_BITS_3_TO_2_856_EQ_0_857_THEN__ETC___d2860 = - bram_serverAdapterB_cnt_5_SLT_3___d1776; + IF_wmi_addr_852_BITS_3_TO_2_853_EQ_0_854_THEN__ETC___d2853 = + bram_serverAdapterB_cnt_5_SLT_3___d1773; 2'd1: - IF_wmi_addr_855_BITS_3_TO_2_856_EQ_0_857_THEN__ETC___d2860 = - bram_serverAdapterB_1_cnt_03_SLT_3___d1777; + IF_wmi_addr_852_BITS_3_TO_2_853_EQ_0_854_THEN__ETC___d2853 = + bram_serverAdapterB_1_cnt_03_SLT_3___d1774; 2'd2: - IF_wmi_addr_855_BITS_3_TO_2_856_EQ_0_857_THEN__ETC___d2860 = - bram_serverAdapterB_2_cnt_21_SLT_3___d1778; + IF_wmi_addr_852_BITS_3_TO_2_853_EQ_0_854_THEN__ETC___d2853 = + bram_serverAdapterB_2_cnt_21_SLT_3___d1775; 2'd3: - IF_wmi_addr_855_BITS_3_TO_2_856_EQ_0_857_THEN__ETC___d2860 = + IF_wmi_addr_852_BITS_3_TO_2_853_EQ_0_854_THEN__ETC___d2853 = wmi_addr[3:2] != 2'd3 || - bram_serverAdapterB_3_cnt_39_SLT_3___d1779; + bram_serverAdapterB_3_cnt_39_SLT_3___d1776; endcase end always@(dpControl or bml_fabDone or bml_remDone or bml_remStart) @@ -7205,155 +7205,155 @@ module mkOCDP4B(pciDevice, !bml_fabDone; endcase end - always@(idx__h19187 or - tlp_tlpBRAM_writeRemainDWLen_62_ULE_3___d2413 or + always@(idx__h19271 or + tlp_tlpBRAM_writeRemainDWLen_62_ULE_3___d2441 or tlp_tlpBRAM_writeRemainDWLen or - tlp_tlpBRAM_writeRemainDWLen_62_ULE_1___d2437 or - tlp_tlpBRAM_writeRemainDWLen_62_ULE_2___d2430) + tlp_tlpBRAM_writeRemainDWLen_62_ULE_1___d2440 or + tlp_tlpBRAM_writeRemainDWLen_62_ULE_2___d2431) begin - case (idx__h19187) + case (idx__h19271) 2'd0: - IF_0_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2464 = + IF_0_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2469 = tlp_tlpBRAM_writeRemainDWLen != 10'd0; 2'd1: - IF_0_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2464 = - !tlp_tlpBRAM_writeRemainDWLen_62_ULE_1___d2437; + IF_0_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2469 = + !tlp_tlpBRAM_writeRemainDWLen_62_ULE_1___d2440; 2'd2: - IF_0_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2464 = - !tlp_tlpBRAM_writeRemainDWLen_62_ULE_2___d2430; + IF_0_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2469 = + !tlp_tlpBRAM_writeRemainDWLen_62_ULE_2___d2431; 2'd3: - IF_0_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2464 = - !tlp_tlpBRAM_writeRemainDWLen_62_ULE_3___d2413; + IF_0_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2469 = + !tlp_tlpBRAM_writeRemainDWLen_62_ULE_3___d2441; endcase end - always@(idx__h21418 or - tlp_tlpBRAM_writeRemainDWLen_62_ULE_3___d2413 or + always@(idx__h21502 or + tlp_tlpBRAM_writeRemainDWLen_62_ULE_3___d2441 or tlp_tlpBRAM_writeRemainDWLen or - tlp_tlpBRAM_writeRemainDWLen_62_ULE_1___d2437 or - tlp_tlpBRAM_writeRemainDWLen_62_ULE_2___d2430) + tlp_tlpBRAM_writeRemainDWLen_62_ULE_1___d2440 or + tlp_tlpBRAM_writeRemainDWLen_62_ULE_2___d2431) begin - case (idx__h21418) + case (idx__h21502) 2'd0: - IF_1_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2465 = + IF_1_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2470 = tlp_tlpBRAM_writeRemainDWLen != 10'd0; 2'd1: - IF_1_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2465 = - !tlp_tlpBRAM_writeRemainDWLen_62_ULE_1___d2437; + IF_1_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2470 = + !tlp_tlpBRAM_writeRemainDWLen_62_ULE_1___d2440; 2'd2: - IF_1_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2465 = - !tlp_tlpBRAM_writeRemainDWLen_62_ULE_2___d2430; + IF_1_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2470 = + !tlp_tlpBRAM_writeRemainDWLen_62_ULE_2___d2431; 2'd3: - IF_1_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2465 = - !tlp_tlpBRAM_writeRemainDWLen_62_ULE_3___d2413; + IF_1_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2470 = + !tlp_tlpBRAM_writeRemainDWLen_62_ULE_3___d2441; endcase end - always@(idx__h22722 or - tlp_tlpBRAM_writeRemainDWLen_62_ULE_3___d2413 or + always@(idx__h22806 or + tlp_tlpBRAM_writeRemainDWLen_62_ULE_3___d2441 or tlp_tlpBRAM_writeRemainDWLen or - tlp_tlpBRAM_writeRemainDWLen_62_ULE_1___d2437 or - tlp_tlpBRAM_writeRemainDWLen_62_ULE_2___d2430) + tlp_tlpBRAM_writeRemainDWLen_62_ULE_1___d2440 or + tlp_tlpBRAM_writeRemainDWLen_62_ULE_2___d2431) begin - case (idx__h22722) + case (idx__h22806) 2'd0: - IF_2_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2466 = + IF_2_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2471 = tlp_tlpBRAM_writeRemainDWLen != 10'd0; 2'd1: - IF_2_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2466 = - !tlp_tlpBRAM_writeRemainDWLen_62_ULE_1___d2437; + IF_2_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2471 = + !tlp_tlpBRAM_writeRemainDWLen_62_ULE_1___d2440; 2'd2: - IF_2_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2466 = - !tlp_tlpBRAM_writeRemainDWLen_62_ULE_2___d2430; + IF_2_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2471 = + !tlp_tlpBRAM_writeRemainDWLen_62_ULE_2___d2431; 2'd3: - IF_2_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2466 = - !tlp_tlpBRAM_writeRemainDWLen_62_ULE_3___d2413; + IF_2_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2471 = + !tlp_tlpBRAM_writeRemainDWLen_62_ULE_3___d2441; endcase end - always@(idx__h24026 or - tlp_tlpBRAM_writeRemainDWLen_62_ULE_3___d2413 or + always@(idx__h24110 or + tlp_tlpBRAM_writeRemainDWLen_62_ULE_3___d2441 or tlp_tlpBRAM_writeRemainDWLen or - tlp_tlpBRAM_writeRemainDWLen_62_ULE_1___d2437 or - tlp_tlpBRAM_writeRemainDWLen_62_ULE_2___d2430) + tlp_tlpBRAM_writeRemainDWLen_62_ULE_1___d2440 or + tlp_tlpBRAM_writeRemainDWLen_62_ULE_2___d2431) begin - case (idx__h24026) + case (idx__h24110) 2'd0: - IF_3_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2467 = + IF_3_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2472 = tlp_tlpBRAM_writeRemainDWLen != 10'd0; 2'd1: - IF_3_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2467 = - !tlp_tlpBRAM_writeRemainDWLen_62_ULE_1___d2437; + IF_3_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2472 = + !tlp_tlpBRAM_writeRemainDWLen_62_ULE_1___d2440; 2'd2: - IF_3_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2467 = - !tlp_tlpBRAM_writeRemainDWLen_62_ULE_2___d2430; + IF_3_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2472 = + !tlp_tlpBRAM_writeRemainDWLen_62_ULE_2___d2431; 2'd3: - IF_3_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2467 = - !tlp_tlpBRAM_writeRemainDWLen_62_ULE_3___d2413; + IF_3_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2472 = + !tlp_tlpBRAM_writeRemainDWLen_62_ULE_3___d2441; endcase end - always@(idx__h19187 or tlp_tlpBRAM_mReqF$D_OUT) + always@(idx__h19271 or tlp_tlpBRAM_mReqF$D_OUT) begin - case (idx__h19187) + case (idx__h19271) 2'd0: - IF_0_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2529 = + IF_0_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2509 = tlp_tlpBRAM_mReqF$D_OUT[127:96]; 2'd1: - IF_0_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2529 = + IF_0_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2509 = tlp_tlpBRAM_mReqF$D_OUT[95:64]; 2'd2: - IF_0_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2529 = + IF_0_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2509 = tlp_tlpBRAM_mReqF$D_OUT[63:32]; 2'd3: - IF_0_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2529 = + IF_0_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2509 = tlp_tlpBRAM_mReqF$D_OUT[31:0]; endcase end - always@(idx__h21418 or tlp_tlpBRAM_mReqF$D_OUT) + always@(idx__h21502 or tlp_tlpBRAM_mReqF$D_OUT) begin - case (idx__h21418) + case (idx__h21502) 2'd0: - IF_1_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2507 = + IF_1_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2510 = tlp_tlpBRAM_mReqF$D_OUT[127:96]; 2'd1: - IF_1_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2507 = + IF_1_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2510 = tlp_tlpBRAM_mReqF$D_OUT[95:64]; 2'd2: - IF_1_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2507 = + IF_1_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2510 = tlp_tlpBRAM_mReqF$D_OUT[63:32]; 2'd3: - IF_1_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2507 = + IF_1_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2510 = tlp_tlpBRAM_mReqF$D_OUT[31:0]; endcase end - always@(idx__h22722 or tlp_tlpBRAM_mReqF$D_OUT) + always@(idx__h22806 or tlp_tlpBRAM_mReqF$D_OUT) begin - case (idx__h22722) + case (idx__h22806) 2'd0: - IF_2_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2493 = + IF_2_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2511 = tlp_tlpBRAM_mReqF$D_OUT[127:96]; 2'd1: - IF_2_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2493 = + IF_2_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2511 = tlp_tlpBRAM_mReqF$D_OUT[95:64]; 2'd2: - IF_2_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2493 = + IF_2_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2511 = tlp_tlpBRAM_mReqF$D_OUT[63:32]; 2'd3: - IF_2_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2493 = + IF_2_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2511 = tlp_tlpBRAM_mReqF$D_OUT[31:0]; endcase end - always@(idx__h24026 or tlp_tlpBRAM_mReqF$D_OUT) + always@(idx__h24110 or tlp_tlpBRAM_mReqF$D_OUT) begin - case (idx__h24026) + case (idx__h24110) 2'd0: - IF_3_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2530 = + IF_3_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2512 = tlp_tlpBRAM_mReqF$D_OUT[127:96]; 2'd1: - IF_3_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2530 = + IF_3_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2512 = tlp_tlpBRAM_mReqF$D_OUT[95:64]; 2'd2: - IF_3_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2530 = + IF_3_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2512 = tlp_tlpBRAM_mReqF$D_OUT[63:32]; 2'd3: - IF_3_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2530 = + IF_3_MINUS_tlp_tlpBRAM_writeDWAddr_58_BITS_1_T_ETC___d2512 = tlp_tlpBRAM_mReqF$D_OUT[31:0]; endcase end @@ -7408,16 +7408,16 @@ module mkOCDP4B(pciDevice, begin case (tlp_tlpBRAM_readReq$D_OUT[30:29]) 2'd0: - IF_tlp_tlpBRAM_readReq_first__97_BITS_30_TO_29_ETC___d2433 = + IF_tlp_tlpBRAM_readReq_first__97_BITS_30_TO_29_ETC___d2432 = bram_serverAdapterA_outData_outData$wget; 2'd1: - IF_tlp_tlpBRAM_readReq_first__97_BITS_30_TO_29_ETC___d2433 = + IF_tlp_tlpBRAM_readReq_first__97_BITS_30_TO_29_ETC___d2432 = bram_serverAdapterA_1_outData_outData$wget; 2'd2: - IF_tlp_tlpBRAM_readReq_first__97_BITS_30_TO_29_ETC___d2433 = + IF_tlp_tlpBRAM_readReq_first__97_BITS_30_TO_29_ETC___d2432 = bram_serverAdapterA_2_outData_outData$wget; 2'd3: - IF_tlp_tlpBRAM_readReq_first__97_BITS_30_TO_29_ETC___d2433 = + IF_tlp_tlpBRAM_readReq_first__97_BITS_30_TO_29_ETC___d2432 = bram_serverAdapterA_3_outData_outData$wget; endcase end @@ -7453,14 +7453,14 @@ module mkOCDP4B(pciDevice, begin case (wmi_p4B) 2'd1: - IF_wmi_p4B_912_EQ_1_915_THEN_bram_serverAdapte_ETC___d1921 = + IF_wmi_p4B_909_EQ_1_912_THEN_bram_serverAdapte_ETC___d1918 = bram_serverAdapterB_1_outDataCore$EMPTY_N || bram_serverAdapterB_1_outData_enqData$whas; 2'd2: - IF_wmi_p4B_912_EQ_1_915_THEN_bram_serverAdapte_ETC___d1921 = + IF_wmi_p4B_909_EQ_1_912_THEN_bram_serverAdapte_ETC___d1918 = bram_serverAdapterB_2_outDataCore$EMPTY_N || bram_serverAdapterB_2_outData_enqData$whas; - default: IF_wmi_p4B_912_EQ_1_915_THEN_bram_serverAdapte_ETC___d1921 = + default: IF_wmi_p4B_909_EQ_1_912_THEN_bram_serverAdapte_ETC___d1918 = wmi_p4B != 2'd3 || bram_serverAdapterB_3_outDataCore$EMPTY_N || bram_serverAdapterB_3_outData_enqData$whas; @@ -8286,16 +8286,16 @@ module mkOCDP4B(pciDevice, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfrd) begin - v__h89656 = $time; + v__h89718 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfrd) $display("[%0d]: %m: WCI CONFIG READ Addr:%0x BE:%0x Data:%0x", - v__h89656, + v__h89718, wci_reqF$D_OUT[63:32], wci_reqF$D_OUT[67:64], - _theResult____h89640); + _theResult____h89702); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_ctl_op_start) begin @@ -8311,218 +8311,218 @@ module mkOCDP4B(pciDevice, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_tlp_dmaRequestNearMeta) begin - v__h39702 = $time; + v__h39786 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_tlp_dmaRequestNearMeta) $display("[%0d]: %m: dmaRequestNearMeta FPactMesg-Step1/7", - v__h39702); + v__h39786); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_tlp_dmaPushRequestMesg) begin - v__h46380 = $time; + v__h46464 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_tlp_dmaPushRequestMesg) $display("[%0d]: %m: dmaPushRequestMesg FPactMesg-Step3/7", - v__h46380); + v__h46464); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_tlp_dmaResponseNearMetaHead) begin - v__h41753 = $time; + v__h41837 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_tlp_dmaResponseNearMetaHead) $display("[%0d]: %m: dmaResponseNearMetaHead FPactMesg-Step2a/7 mesgLength:%0x", - v__h41753, - x__h40887); + v__h41837, + x__h40971); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_tlp_dmaPushResponseHeader) begin - v__h47001 = $time; + v__h47085 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_tlp_dmaPushResponseHeader) $display("[%0d]: %m: dmaPushResponseHeader FPactMesg-Step4a/7", - v__h47001); + v__h47085); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_tlp_dmaPushResponseBody) begin - v__h47351 = $time; + v__h47434 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_tlp_dmaPushResponseBody) $display("[%0d]: %m: dmaPushResponseBody FPactMesg-Step4b/7", - v__h47351); + v__h47434); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_tlp_dmaXmtMetaHead) begin - v__h48586 = $time; + v__h48668 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_tlp_dmaXmtMetaHead) - $display("[%0d]: %m: dmaXmtMetaHead FPactMesg-Step5/7", v__h48586); + $display("[%0d]: %m: dmaXmtMetaHead FPactMesg-Step5/7", v__h48668); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_tlp_dmaXmtTailEvent) begin - v__h54974 = $time; + v__h55054 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_tlp_dmaXmtTailEvent) - $display("[%0d]: %m: dmaXmtTailEvent FPactMesg-Step7/7", v__h54974); + $display("[%0d]: %m: dmaXmtTailEvent FPactMesg-Step7/7", v__h55054); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_tlp_dmaXmtMetaBody) begin - v__h54850 = $time; + v__h54931 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_tlp_dmaXmtMetaBody) - $display("[%0d]: %m: dmaXmtMetaBody FPactMesg-Step6/7", v__h54850); + $display("[%0d]: %m: dmaXmtMetaBody FPactMesg-Step6/7", v__h54931); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_tlp_dmaXmtDoorbell) begin - v__h55182 = $time; + v__h55262 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_tlp_dmaXmtDoorbell) - $display("[%0d]: %m: dmaXmtDoorbell FC/FPactFlow-Step1/1", v__h55182); + $display("[%0d]: %m: dmaXmtDoorbell FC/FPactFlow-Step1/1", v__h55262); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_tlp_dmaRespHeadFarMeta) begin - v__h57878 = $time; + v__h57955 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_tlp_dmaRespHeadFarMeta) $display("[%0d]: %m: dmaRespHeadFarMeta FPactMesg-Step2a/N fabMeta:%0x", - v__h57878, - x__h56804); + v__h57955, + x__h56883); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_tlp_dmaPullTailEvent) begin - v__h63884 = $time; + v__h63951 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_tlp_dmaPullTailEvent) - $display("[%0d]: %m: dmaPullTailEvent FPactMesg-Step5/5", v__h63884); + $display("[%0d]: %m: dmaPullTailEvent FPactMesg-Step5/5", v__h63951); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_tlp_dmaRespBodyFarMeta) begin - v__h62195 = $time; + v__h62270 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_tlp_dmaRespBodyFarMeta) $display("[%0d]: %m: dmaRespBodyFarMeta FPactMesg-Step2b/N opcode:%0x nowMS:%0x nowLS:%0x", - v__h62195, - opcode__h58837, - nowMS__h60057, - nowLS__h60998); + v__h62270, + opcode__h58912, + nowMS__h60132, + nowLS__h61073); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_tlp_dmaPullResponseHeader) begin - v__h63372 = $time; + v__h63443 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_tlp_dmaPullResponseHeader) $display("[%0d]: %m: dmaPullResponseHeader FPactMesg-Step4a/5", - v__h63372); + v__h63443); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_tlp_dmaPullResponseBody) begin - v__h63720 = $time; + v__h63789 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_tlp_dmaPullResponseBody) $display("[%0d]: %m: dmaPullResponseBody FPactMesg-Step4b/5", - v__h63720); + v__h63789); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_tlp_dmaTailEventSender) begin - v__h69047 = $time; + v__h69114 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_tlp_dmaTailEventSender) - $display("[%0d]: %m: dmaTailEventSender - generic", v__h69047); + $display("[%0d]: %m: dmaTailEventSender - generic", v__h69114); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_tlp_dmaResponseNearMetaBody) begin - v__h46039 = $time; + v__h46123 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_tlp_dmaResponseNearMetaBody) $display("[%0d]: %m: dmaResponseNearMetaBody FPactMesg-Step2b/7 opcode:%0x nowMS:%0x nowLS:%0x", - v__h46039, - opcode__h42670, - nowMS__h43901, - nowLS__h44844); + v__h46123, + opcode__h42754, + nowMS__h43985, + nowLS__h44928); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_tlp_dmaRequestFarMeta) begin - v__h55645 = $time; + v__h55725 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_tlp_dmaRequestFarMeta) - $display("[%0d]: %m: dmaRequestFarMeta FCactMesg-Step1/5", v__h55645); + $display("[%0d]: %m: dmaRequestFarMeta FCactMesg-Step1/5", v__h55725); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_tlp_dmaPullRequestFarMesg) begin - v__h62717 = $time; + v__h62790 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_tlp_dmaPullRequestFarMesg) $display("[%0d]: %m: dmaPullRequestFarMesg FCactMesg-Step3/5", - v__h62717); + v__h62790); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wmi_doWriteFinalize) begin - v__h80656 = $time; + v__h80718 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wmi_doWriteFinalize) $display("[%0d]: %m: doWriteFinalize lclMetaAddr :%0x length:%0x opcode:%0x nowMS:%0x nowLS:%0x ", - v__h80656, + v__h80718, wmi_lclMetaAddr, - x3__h80014, - mesgMeta_opcode__h80054, + x3__h80076, + mesgMeta_opcode__h80116, dmaStartTime$D_IN[63:32], dmaStartTime$D_IN[31:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfwr && wci_reqF$D_OUT[39:32] == 8'h18) begin - v__h89024 = $time; + v__h89086 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfwr && wci_reqF$D_OUT[39:32] == 8'h18) - $display("[%0d] %m: fabDoneAvail Event", v__h89024); + $display("[%0d] %m: fabDoneAvail Event", v__h89086); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfwr) begin - v__h89493 = $time; + v__h89555 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfwr) $display("[%0d]: %m: WCI CONFIG WRITE Addr:%0x BE:%0x Data:%0x", - v__h89493, + v__h89555, wci_reqF$D_OUT[63:32], wci_reqF$D_OUT[67:64], wci_reqF$D_OUT[31:0]); diff --git a/rtl/mkOCInf16B.v b/rtl/mkOCInf16B.v index 760bb46b..fc49af20 100644 --- a/rtl/mkOCInf16B.v +++ b/rtl/mkOCInf16B.v @@ -1,7 +1,7 @@ // -// Generated by Bluespec Compiler, version 2012.09.beta1 (build 29570, 2012-09.11) +// Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Wed Nov 28 10:39:14 EST 2012 +// On Fri Jun 21 17:01:09 EDT 2013 // // // Ports: @@ -1304,63 +1304,6 @@ module mkOCInf16B(pciDevice, wmiDP1_SRespLast, wmiDP1_SThreadBusy; - // register cpTlp_cmpActive - reg cpTlp_cmpActive; - wire cpTlp_cmpActive$D_IN, cpTlp_cmpActive$EN; - - // register cpTlp_cmpDWRemain - reg [9 : 0] cpTlp_cmpDWRemain; - wire [9 : 0] cpTlp_cmpDWRemain$D_IN; - wire cpTlp_cmpDWRemain$EN; - - // register cpTlp_rdp - reg [1 : 0] cpTlp_rdp; - wire [1 : 0] cpTlp_rdp$D_IN; - wire cpTlp_rdp$EN; - - // register cpTlp_rdv - reg [127 : 0] cpTlp_rdv; - wire [127 : 0] cpTlp_rdv$D_IN; - wire cpTlp_rdv$EN; - - // register cpTlp_rss - reg [1 : 0] cpTlp_rss; - wire [1 : 0] cpTlp_rss$D_IN; - wire cpTlp_rss$EN; - - // register cpTlp_tlpActive - reg cpTlp_tlpActive; - wire cpTlp_tlpActive$D_IN, cpTlp_tlpActive$EN; - - // register cpTlp_tlpDW - reg [31 : 0] cpTlp_tlpDW; - wire [31 : 0] cpTlp_tlpDW$D_IN; - wire cpTlp_tlpDW$EN; - - // register cpTlp_tlpDWAddr - reg [29 : 0] cpTlp_tlpDWAddr; - wire [29 : 0] cpTlp_tlpDWAddr$D_IN; - wire cpTlp_tlpDWAddr$EN; - - // register cpTlp_tlpDWp - reg [1 : 0] cpTlp_tlpDWp; - wire [1 : 0] cpTlp_tlpDWp$D_IN; - wire cpTlp_tlpDWp$EN; - - // register cpTlp_tlpFirst - reg cpTlp_tlpFirst; - wire cpTlp_tlpFirst$D_IN, cpTlp_tlpFirst$EN; - - // register cpTlp_tlpReq - reg [63 : 0] cpTlp_tlpReq; - wire [63 : 0] cpTlp_tlpReq$D_IN; - wire cpTlp_tlpReq$EN; - - // register cpTlp_tlpUnroll - reg [9 : 0] cpTlp_tlpUnroll; - wire [9 : 0] cpTlp_tlpUnroll$D_IN; - wire cpTlp_tlpUnroll$EN; - // register noc_chompCnt reg [7 : 0] noc_chompCnt; wire [7 : 0] noc_chompCnt$D_IN; @@ -1602,45 +1545,18 @@ module mkOCInf16B(pciDevice, cpMux_respBF$ENQ, cpMux_respBF$FULL_N; - // ports of submodule cpTlp_cmpF - wire [55 : 0] cpTlp_cmpF$D_IN, cpTlp_cmpF$D_OUT; - wire cpTlp_cmpF$CLR, - cpTlp_cmpF$DEQ, - cpTlp_cmpF$EMPTY_N, - cpTlp_cmpF$ENQ, - cpTlp_cmpF$FULL_N; - - // ports of submodule cpTlp_cpReqF - wire [58 : 0] cpTlp_cpReqF$D_IN, cpTlp_cpReqF$D_OUT; - wire cpTlp_cpReqF$CLR, - cpTlp_cpReqF$DEQ, - cpTlp_cpReqF$EMPTY_N, - cpTlp_cpReqF$ENQ, - cpTlp_cpReqF$FULL_N; - - // ports of submodule cpTlp_cpRespF - wire [39 : 0] cpTlp_cpRespF$D_IN, cpTlp_cpRespF$D_OUT; - wire cpTlp_cpRespF$CLR, - cpTlp_cpRespF$DEQ, - cpTlp_cpRespF$EMPTY_N, - cpTlp_cpRespF$ENQ, - cpTlp_cpRespF$FULL_N; - - // ports of submodule cpTlp_inF - wire [152 : 0] cpTlp_inF$D_IN, cpTlp_inF$D_OUT; - wire cpTlp_inF$CLR, - cpTlp_inF$DEQ, - cpTlp_inF$EMPTY_N, - cpTlp_inF$ENQ, - cpTlp_inF$FULL_N; - - // ports of submodule cpTlp_outF - wire [152 : 0] cpTlp_outF$D_IN, cpTlp_outF$D_OUT; - wire cpTlp_outF$CLR, - cpTlp_outF$DEQ, - cpTlp_outF$EMPTY_N, - cpTlp_outF$ENQ, - cpTlp_outF$FULL_N; + // ports of submodule cpTlp + wire [152 : 0] cpTlp$server_request_put, cpTlp$server_response_get; + wire [58 : 0] cpTlp$client_request_get; + wire [39 : 0] cpTlp$client_response_put; + wire cpTlp$EN_client_request_get, + cpTlp$EN_client_response_put, + cpTlp$EN_server_request_put, + cpTlp$EN_server_response_get, + cpTlp$RDY_client_request_get, + cpTlp$RDY_client_response_put, + cpTlp$RDY_server_request_put, + cpTlp$RDY_server_response_get; // ports of submodule dp0 wire [152 : 0] dp0$server_request_put, dp0$server_response_get; @@ -1793,45 +1709,15 @@ module mkOCInf16B(pciDevice, // rule scheduling signals wire WILL_FIRE_RL_cpMux_request_portA, WILL_FIRE_RL_cpMux_request_portB, - WILL_FIRE_RL_cpMux_response_cp, - WILL_FIRE_RL_cpTlp_tlpFirstComplWord, - WILL_FIRE_RL_cpTlp_tlpFirstRcv, - WILL_FIRE_RL_cpTlp_tlpNextComplWord, - WILL_FIRE_RL_cpTlp_tlpReqGen, - WILL_FIRE_RL_cpTlp_tlpStageNextWord; + WILL_FIRE_RL_cpMux_response_cp; // inputs to muxes for submodule ports - wire [152 : 0] MUX_cpTlp_outF$enq_1__VAL_1, MUX_cpTlp_outF$enq_1__VAL_2; - wire [29 : 0] MUX_cpTlp_tlpDWAddr$write_1__VAL_2; - wire [9 : 0] MUX_cpTlp_cmpDWRemain$write_1__VAL_1, - MUX_cpTlp_cmpDWRemain$write_1__VAL_2, - MUX_cpTlp_tlpUnroll$write_1__VAL_2; - wire [1 : 0] MUX_cpTlp_rdp$write_1__VAL_1, - MUX_cpTlp_rss$write_1__VAL_1, - MUX_cpTlp_tlpDWp$write_1__VAL_2; - wire MUX_cpMux_aActF$enq_1__SEL_1, - MUX_cpTlp_cmpActive$write_1__SEL_1, - MUX_cpTlp_rss$write_1__SEL_1, - MUX_cpTlp_tlpActive$write_1__SEL_1, - MUX_cpTlp_tlpDWAddr$write_1__SEL_1; + wire MUX_cpMux_aActF$enq_1__SEL_1; // remaining internal signals reg [63 : 0] v__h1839; - reg [31 : 0] v__h5693; - reg [15 : 0] lastRema__h10373; - reg [1 : 0] lowAddr10__h5218, x__h5448, x__h5471; - reg CASE_cpTlp_tlpDWp_NOT_cpTlp_tlpDWp_EQ_3_OR_cpT_ETC__q1; - wire [127 : 0] pkt__h7418, pw_data__h10406; - wire [57 : 0] IF_cpTlp_tlpReq_6_BIT_62_7_THEN_cpTlp_tlpDWAdd_ETC___d147; - wire [31 : 0] IF_cpTlp_tlpReq_6_BIT_62_7_AND_NOT_cpTlp_tlpFi_ETC___d336, - wreq_data__h6249; - wire [15 : 0] pw_be__h10405, x__h2791, x__h3085; - wire [11 : 0] byteCount__h5220, x__h5439, x__h5441, y__h5440, y__h5442; - wire [6 : 0] lowAddr__h5219; - wire [3 : 0] _theResult_____2__h5635; - wire [2 : 0] x__h10825; - wire cpMux_aActF_i_notEmpty__45_AND_IF_cpMux_aActF__ETC___d250, - cpTlp_tlpFirst_9_OR_IF_cpTlp_tlpDWp_00_EQ_0_01_ETC___d110; + wire [15 : 0] x__h2806, x__h3100; + wire cpMux_aActF_i_notEmpty__1_AND_IF_cpMux_aActF_f_ETC___d46; // output resets assign RST_N_wci_m_0 = cp$RST_N_wci_Vm_0 ; @@ -2413,65 +2299,27 @@ module mkOCInf16B(pciDevice, .FULL_N(cpMux_respBF$FULL_N), .EMPTY_N(cpMux_respBF$EMPTY_N)); - // submodule cpTlp_cmpF - FIFO2 #(.width(32'd56), .guarded(32'd1)) cpTlp_cmpF(.RST(RST_N), - .CLK(CLK), - .D_IN(cpTlp_cmpF$D_IN), - .ENQ(cpTlp_cmpF$ENQ), - .DEQ(cpTlp_cmpF$DEQ), - .CLR(cpTlp_cmpF$CLR), - .D_OUT(cpTlp_cmpF$D_OUT), - .FULL_N(cpTlp_cmpF$FULL_N), - .EMPTY_N(cpTlp_cmpF$EMPTY_N)); - - // submodule cpTlp_cpReqF - FIFO2 #(.width(32'd59), .guarded(32'd1)) cpTlp_cpReqF(.RST(RST_N), - .CLK(CLK), - .D_IN(cpTlp_cpReqF$D_IN), - .ENQ(cpTlp_cpReqF$ENQ), - .DEQ(cpTlp_cpReqF$DEQ), - .CLR(cpTlp_cpReqF$CLR), - .D_OUT(cpTlp_cpReqF$D_OUT), - .FULL_N(cpTlp_cpReqF$FULL_N), - .EMPTY_N(cpTlp_cpReqF$EMPTY_N)); - - // submodule cpTlp_cpRespF - FIFO2 #(.width(32'd40), .guarded(32'd1)) cpTlp_cpRespF(.RST(RST_N), - .CLK(CLK), - .D_IN(cpTlp_cpRespF$D_IN), - .ENQ(cpTlp_cpRespF$ENQ), - .DEQ(cpTlp_cpRespF$DEQ), - .CLR(cpTlp_cpRespF$CLR), - .D_OUT(cpTlp_cpRespF$D_OUT), - .FULL_N(cpTlp_cpRespF$FULL_N), - .EMPTY_N(cpTlp_cpRespF$EMPTY_N)); - - // submodule cpTlp_inF - FIFO2 #(.width(32'd153), .guarded(32'd1)) cpTlp_inF(.RST(RST_N), - .CLK(CLK), - .D_IN(cpTlp_inF$D_IN), - .ENQ(cpTlp_inF$ENQ), - .DEQ(cpTlp_inF$DEQ), - .CLR(cpTlp_inF$CLR), - .D_OUT(cpTlp_inF$D_OUT), - .FULL_N(cpTlp_inF$FULL_N), - .EMPTY_N(cpTlp_inF$EMPTY_N)); - - // submodule cpTlp_outF - FIFO2 #(.width(32'd153), .guarded(32'd1)) cpTlp_outF(.RST(RST_N), - .CLK(CLK), - .D_IN(cpTlp_outF$D_IN), - .ENQ(cpTlp_outF$ENQ), - .DEQ(cpTlp_outF$DEQ), - .CLR(cpTlp_outF$CLR), - .D_OUT(cpTlp_outF$D_OUT), - .FULL_N(cpTlp_outF$FULL_N), - .EMPTY_N(cpTlp_outF$EMPTY_N)); + // submodule cpTlp + mkTLPSerializer cpTlp(.pciDevice(pciDevice), + .CLK(CLK), + .RST_N(RST_N), + .client_response_put(cpTlp$client_response_put), + .server_request_put(cpTlp$server_request_put), + .EN_server_request_put(cpTlp$EN_server_request_put), + .EN_server_response_get(cpTlp$EN_server_response_get), + .EN_client_request_get(cpTlp$EN_client_request_get), + .EN_client_response_put(cpTlp$EN_client_response_put), + .RDY_server_request_put(cpTlp$RDY_server_request_put), + .server_response_get(cpTlp$server_response_get), + .RDY_server_response_get(cpTlp$RDY_server_response_get), + .client_request_get(cpTlp$client_request_get), + .RDY_client_request_get(cpTlp$RDY_client_request_get), + .RDY_client_response_put(cpTlp$RDY_client_response_put)); // submodule dp0 mkOCDP16B #(.hasPush(1'd0), .hasPull(1'd1), - .hasDebugLogic(1'd1)) dp0(.pciDevice(x__h2791), + .hasDebugLogic(1'd1)) dp0(.pciDevice(x__h2806), .CLK(CLK), .RST_N(cp$RST_N_wci_Vm_13), .server_request_put(dp0$server_request_put), @@ -2516,7 +2364,7 @@ module mkOCInf16B(pciDevice, // submodule dp1 mkOCDP16B #(.hasPush(1'd1), .hasPull(1'd0), - .hasDebugLogic(1'd1)) dp1(.pciDevice(x__h3085), + .hasDebugLogic(1'd1)) dp1(.pciDevice(x__h3100), .CLK(CLK), .RST_N(cp$RST_N_wci_Vm_14), .server_request_put(dp1$server_request_put), @@ -2655,40 +2503,6 @@ module mkOCInf16B(pciDevice, .RDY_c1_request_get(noc_sm2$RDY_c1_request_get), .RDY_c1_response_put()); - // rule RL_cpTlp_tlpFirstRcv - assign WILL_FIRE_RL_cpTlp_tlpFirstRcv = - cpTlp_inF$EMPTY_N && - (!cpTlp_inF$D_OUT[152] || cpTlp_inF$D_OUT[110] || - cpTlp_inF$D_OUT[125] || - cpTlp_inF$D_OUT[124:120] != 5'b0 || - cpTlp_inF$D_OUT[126] || - cpTlp_cmpF$FULL_N) && - !cpTlp_tlpActive ; - - // rule RL_cpTlp_tlpReqGen - assign WILL_FIRE_RL_cpTlp_tlpReqGen = - cpTlp_cpReqF$FULL_N && - (!cpTlp_tlpReq[62] || - cpTlp_tlpFirst_9_OR_IF_cpTlp_tlpDWp_00_EQ_0_01_ETC___d110) && - (!cpTlp_tlpReq[62] || cpTlp_tlpFirst || cpTlp_inF$EMPTY_N) && - cpTlp_tlpActive ; - - // rule RL_cpTlp_tlpFirstComplWord - assign WILL_FIRE_RL_cpTlp_tlpFirstComplWord = - cpTlp_cmpF$EMPTY_N && cpTlp_cpRespF$EMPTY_N && - cpTlp_outF$FULL_N && - !cpTlp_cmpActive ; - - // rule RL_cpTlp_tlpStageNextWord - assign WILL_FIRE_RL_cpTlp_tlpStageNextWord = - cpTlp_cpRespF$EMPTY_N && cpTlp_cmpActive && - cpTlp_cmpDWRemain != 10'd0 && - !WILL_FIRE_RL_cpTlp_tlpNextComplWord ; - - // rule RL_cpTlp_tlpNextComplWord - assign WILL_FIRE_RL_cpTlp_tlpNextComplWord = - cpTlp_outF$FULL_N && cpTlp_cmpActive && cpTlp_rss != 2'd0 ; - // rule RL_cpMux_request_portA assign WILL_FIRE_RL_cpMux_request_portA = cpMux_reqAF$EMPTY_N && cpMux_cpReqF$FULL_N && @@ -2703,156 +2517,11 @@ module mkOCInf16B(pciDevice, // rule RL_cpMux_response_cp assign WILL_FIRE_RL_cpMux_response_cp = cpMux_cpRespF$EMPTY_N && - cpMux_aActF_i_notEmpty__45_AND_IF_cpMux_aActF__ETC___d250 ; + cpMux_aActF_i_notEmpty__1_AND_IF_cpMux_aActF_f_ETC___d46 ; // inputs to muxes for submodule ports assign MUX_cpMux_aActF$enq_1__SEL_1 = WILL_FIRE_RL_cpMux_request_portA && cpMux_reqAF$D_OUT[58] ; - assign MUX_cpTlp_cmpActive$write_1__SEL_1 = - WILL_FIRE_RL_cpTlp_tlpFirstComplWord && - cpTlp_cmpF$D_OUT[21:12] != 10'd1 ; - assign MUX_cpTlp_rss$write_1__SEL_1 = - WILL_FIRE_RL_cpTlp_tlpStageNextWord && - (cpTlp_cmpDWRemain == 10'd1 || cpTlp_rdp == 2'd3) ; - assign MUX_cpTlp_tlpActive$write_1__SEL_1 = - WILL_FIRE_RL_cpTlp_tlpReqGen && cpTlp_tlpUnroll == 10'd1 ; - assign MUX_cpTlp_tlpDWAddr$write_1__SEL_1 = - WILL_FIRE_RL_cpTlp_tlpFirstRcv && cpTlp_inF$D_OUT[152] && - !cpTlp_inF$D_OUT[110] && - !cpTlp_inF$D_OUT[125] && - cpTlp_inF$D_OUT[124:120] == 5'b0 ; - assign MUX_cpTlp_cmpDWRemain$write_1__VAL_1 = - cpTlp_cmpF$D_OUT[21:12] - 10'd1 ; - assign MUX_cpTlp_cmpDWRemain$write_1__VAL_2 = cpTlp_cmpDWRemain - 10'd1 ; - assign MUX_cpTlp_outF$enq_1__VAL_1 = - { 1'd1, - cpTlp_cmpF$D_OUT[21:12] == 10'd1, - 23'h2AFFFF, - pkt__h7418 } ; - assign MUX_cpTlp_outF$enq_1__VAL_2 = - { 1'd0, - cpTlp_rss == 2'd2, - 7'h2A, - pw_be__h10405, - pw_data__h10406 } ; - assign MUX_cpTlp_rdp$write_1__VAL_1 = cpTlp_rdp + 2'd1 ; - assign MUX_cpTlp_rss$write_1__VAL_1 = - (cpTlp_cmpDWRemain == 10'd1) ? 2'd2 : 2'd1 ; - assign MUX_cpTlp_tlpDWAddr$write_1__VAL_2 = cpTlp_tlpDWAddr + 30'd1 ; - assign MUX_cpTlp_tlpDWp$write_1__VAL_2 = cpTlp_tlpDWp - 2'd1 ; - assign MUX_cpTlp_tlpUnroll$write_1__VAL_2 = cpTlp_tlpUnroll - 10'd1 ; - - // register cpTlp_cmpActive - assign cpTlp_cmpActive$D_IN = MUX_cpTlp_cmpActive$write_1__SEL_1 ; - assign cpTlp_cmpActive$EN = - WILL_FIRE_RL_cpTlp_tlpFirstComplWord && - cpTlp_cmpF$D_OUT[21:12] != 10'd1 || - WILL_FIRE_RL_cpTlp_tlpNextComplWord && cpTlp_rss == 2'd2 ; - - // register cpTlp_cmpDWRemain - assign cpTlp_cmpDWRemain$D_IN = - WILL_FIRE_RL_cpTlp_tlpFirstComplWord ? - MUX_cpTlp_cmpDWRemain$write_1__VAL_1 : - MUX_cpTlp_cmpDWRemain$write_1__VAL_2 ; - assign cpTlp_cmpDWRemain$EN = - WILL_FIRE_RL_cpTlp_tlpFirstComplWord || - WILL_FIRE_RL_cpTlp_tlpStageNextWord ; - - // register cpTlp_rdp - assign cpTlp_rdp$D_IN = - WILL_FIRE_RL_cpTlp_tlpStageNextWord ? - MUX_cpTlp_rdp$write_1__VAL_1 : - 2'd0 ; - assign cpTlp_rdp$EN = - WILL_FIRE_RL_cpTlp_tlpStageNextWord || - WILL_FIRE_RL_cpTlp_tlpNextComplWord ; - - // register cpTlp_rdv - assign cpTlp_rdv$D_IN = - { cpTlp_rdv[95:0], - cpTlp_cpRespF$D_OUT[7:0], - cpTlp_cpRespF$D_OUT[15:8], - cpTlp_cpRespF$D_OUT[23:16], - cpTlp_cpRespF$D_OUT[31:24] } ; - assign cpTlp_rdv$EN = WILL_FIRE_RL_cpTlp_tlpStageNextWord ; - - // register cpTlp_rss - assign cpTlp_rss$D_IN = - MUX_cpTlp_rss$write_1__SEL_1 ? - MUX_cpTlp_rss$write_1__VAL_1 : - 2'd0 ; - assign cpTlp_rss$EN = - WILL_FIRE_RL_cpTlp_tlpStageNextWord && - (cpTlp_cmpDWRemain == 10'd1 || cpTlp_rdp == 2'd3) || - WILL_FIRE_RL_cpTlp_tlpNextComplWord && cpTlp_rss == 2'd2 ; - - // register cpTlp_tlpActive - assign cpTlp_tlpActive$D_IN = !MUX_cpTlp_tlpActive$write_1__SEL_1 ; - assign cpTlp_tlpActive$EN = - WILL_FIRE_RL_cpTlp_tlpReqGen && cpTlp_tlpUnroll == 10'd1 || - WILL_FIRE_RL_cpTlp_tlpFirstRcv ; - - // register cpTlp_tlpDW - assign cpTlp_tlpDW$D_IN = cpTlp_inF$D_OUT[31:0] ; - assign cpTlp_tlpDW$EN = MUX_cpTlp_tlpDWAddr$write_1__SEL_1 ; - - // register cpTlp_tlpDWAddr - assign cpTlp_tlpDWAddr$D_IN = - MUX_cpTlp_tlpDWAddr$write_1__SEL_1 ? - cpTlp_inF$D_OUT[63:34] : - MUX_cpTlp_tlpDWAddr$write_1__VAL_2 ; - assign cpTlp_tlpDWAddr$EN = - WILL_FIRE_RL_cpTlp_tlpFirstRcv && cpTlp_inF$D_OUT[152] && - !cpTlp_inF$D_OUT[110] && - !cpTlp_inF$D_OUT[125] && - cpTlp_inF$D_OUT[124:120] == 5'b0 || - WILL_FIRE_RL_cpTlp_tlpReqGen ; - - // register cpTlp_tlpDWp - assign cpTlp_tlpDWp$D_IN = - MUX_cpTlp_tlpDWAddr$write_1__SEL_1 ? - 2'd3 : - MUX_cpTlp_tlpDWp$write_1__VAL_2 ; - assign cpTlp_tlpDWp$EN = - WILL_FIRE_RL_cpTlp_tlpFirstRcv && cpTlp_inF$D_OUT[152] && - !cpTlp_inF$D_OUT[110] && - !cpTlp_inF$D_OUT[125] && - cpTlp_inF$D_OUT[124:120] == 5'b0 || - WILL_FIRE_RL_cpTlp_tlpReqGen && cpTlp_tlpReq[62] && - !cpTlp_tlpFirst ; - - // register cpTlp_tlpFirst - assign cpTlp_tlpFirst$D_IN = MUX_cpTlp_tlpDWAddr$write_1__SEL_1 ; - assign cpTlp_tlpFirst$EN = - WILL_FIRE_RL_cpTlp_tlpFirstRcv && cpTlp_inF$D_OUT[152] && - !cpTlp_inF$D_OUT[110] && - !cpTlp_inF$D_OUT[125] && - cpTlp_inF$D_OUT[124:120] == 5'b0 || - WILL_FIRE_RL_cpTlp_tlpReqGen ; - - // register cpTlp_tlpReq - assign cpTlp_tlpReq$D_IN = - { 1'b0, - cpTlp_inF$D_OUT[126:120], - 1'b0, - cpTlp_inF$D_OUT[118:116], - 4'b0, - cpTlp_inF$D_OUT[111:108], - 2'b0, - cpTlp_inF$D_OUT[105:64] } ; - assign cpTlp_tlpReq$EN = MUX_cpTlp_tlpDWAddr$write_1__SEL_1 ; - - // register cpTlp_tlpUnroll - assign cpTlp_tlpUnroll$D_IN = - MUX_cpTlp_tlpDWAddr$write_1__SEL_1 ? - cpTlp_inF$D_OUT[105:96] : - MUX_cpTlp_tlpUnroll$write_1__VAL_2 ; - assign cpTlp_tlpUnroll$EN = - WILL_FIRE_RL_cpTlp_tlpFirstRcv && cpTlp_inF$D_OUT[152] && - !cpTlp_inF$D_OUT[110] && - !cpTlp_inF$D_OUT[125] && - cpTlp_inF$D_OUT[124:120] == 5'b0 || - WILL_FIRE_RL_cpTlp_tlpReqGen ; // register noc_chompCnt assign noc_chompCnt$D_IN = noc_chompCnt + 8'd1 ; @@ -2957,8 +2626,9 @@ module mkOCInf16B(pciDevice, assign cpMux_cpRespF$CLR = 1'b0 ; // submodule cpMux_reqAF - assign cpMux_reqAF$D_IN = cpTlp_cpReqF$D_OUT ; - assign cpMux_reqAF$ENQ = cpTlp_cpReqF$EMPTY_N && cpMux_reqAF$FULL_N ; + assign cpMux_reqAF$D_IN = cpTlp$client_request_get ; + assign cpMux_reqAF$ENQ = + cpTlp$RDY_client_request_get && cpMux_reqAF$FULL_N ; assign cpMux_reqAF$DEQ = WILL_FIRE_RL_cpMux_request_portA ; assign cpMux_reqAF$CLR = 1'b0 ; @@ -2972,7 +2642,8 @@ module mkOCInf16B(pciDevice, assign cpMux_respAF$D_IN = cpMux_cpRespF$D_OUT ; assign cpMux_respAF$ENQ = WILL_FIRE_RL_cpMux_response_cp && cpMux_aActF$D_OUT ; - assign cpMux_respAF$DEQ = cpMux_respAF$EMPTY_N && cpTlp_cpRespF$FULL_N ; + assign cpMux_respAF$DEQ = + cpTlp$RDY_client_response_put && cpMux_respAF$EMPTY_N ; assign cpMux_respAF$CLR = 1'b0 ; // submodule cpMux_respBF @@ -2982,58 +2653,17 @@ module mkOCInf16B(pciDevice, assign cpMux_respBF$DEQ = EN_cpServer_response_get ; assign cpMux_respBF$CLR = 1'b0 ; - // submodule cpTlp_cmpF - assign cpTlp_cmpF$D_IN = - { cpTlp_inF$D_OUT[95:80], - cpTlp_inF$D_OUT[118:116], - cpTlp_inF$D_OUT[79:72], - lowAddr__h5219, - cpTlp_inF$D_OUT[105:96], - byteCount__h5220 } ; - assign cpTlp_cmpF$ENQ = - WILL_FIRE_RL_cpTlp_tlpFirstRcv && cpTlp_inF$D_OUT[152] && - !cpTlp_inF$D_OUT[110] && - !cpTlp_inF$D_OUT[125] && - cpTlp_inF$D_OUT[124:120] == 5'b0 && - !cpTlp_inF$D_OUT[126] ; - assign cpTlp_cmpF$DEQ = WILL_FIRE_RL_cpTlp_tlpFirstComplWord ; - assign cpTlp_cmpF$CLR = 1'b0 ; - - // submodule cpTlp_cpReqF - assign cpTlp_cpReqF$D_IN = - { !cpTlp_tlpReq[62], - IF_cpTlp_tlpReq_6_BIT_62_7_THEN_cpTlp_tlpDWAdd_ETC___d147 } ; - assign cpTlp_cpReqF$ENQ = WILL_FIRE_RL_cpTlp_tlpReqGen ; - assign cpTlp_cpReqF$DEQ = cpTlp_cpReqF$EMPTY_N && cpMux_reqAF$FULL_N ; - assign cpTlp_cpReqF$CLR = 1'b0 ; - - // submodule cpTlp_cpRespF - assign cpTlp_cpRespF$D_IN = cpMux_respAF$D_OUT ; - assign cpTlp_cpRespF$ENQ = cpMux_respAF$EMPTY_N && cpTlp_cpRespF$FULL_N ; - assign cpTlp_cpRespF$DEQ = - WILL_FIRE_RL_cpTlp_tlpFirstComplWord || - WILL_FIRE_RL_cpTlp_tlpStageNextWord ; - assign cpTlp_cpRespF$CLR = 1'b0 ; - - // submodule cpTlp_inF - assign cpTlp_inF$D_IN = noc_sm0$c0_request_get ; - assign cpTlp_inF$ENQ = noc_sm0$RDY_c0_request_get && cpTlp_inF$FULL_N ; - assign cpTlp_inF$DEQ = - WILL_FIRE_RL_cpTlp_tlpReqGen && cpTlp_tlpReq[62] && - !cpTlp_tlpFirst || - WILL_FIRE_RL_cpTlp_tlpFirstRcv ; - assign cpTlp_inF$CLR = 1'b0 ; - - // submodule cpTlp_outF - assign cpTlp_outF$D_IN = - WILL_FIRE_RL_cpTlp_tlpFirstComplWord ? - MUX_cpTlp_outF$enq_1__VAL_1 : - MUX_cpTlp_outF$enq_1__VAL_2 ; - assign cpTlp_outF$ENQ = - WILL_FIRE_RL_cpTlp_tlpFirstComplWord || - WILL_FIRE_RL_cpTlp_tlpNextComplWord ; - assign cpTlp_outF$DEQ = noc_sm0$RDY_c0_response_put && cpTlp_outF$EMPTY_N ; - assign cpTlp_outF$CLR = 1'b0 ; + // submodule cpTlp + assign cpTlp$client_response_put = cpMux_respAF$D_OUT ; + assign cpTlp$server_request_put = noc_sm0$c0_request_get ; + assign cpTlp$EN_server_request_put = + cpTlp$RDY_server_request_put && noc_sm0$RDY_c0_request_get ; + assign cpTlp$EN_server_response_get = + cpTlp$RDY_server_response_get && noc_sm0$RDY_c0_response_put ; + assign cpTlp$EN_client_request_get = + cpTlp$RDY_client_request_get && cpMux_reqAF$FULL_N ; + assign cpTlp$EN_client_response_put = + cpTlp$RDY_client_response_put && cpMux_respAF$EMPTY_N ; // submodule dp0 assign dp0$server_request_put = noc_sm1$c0_request_get ; @@ -3057,9 +2687,9 @@ module mkOCInf16B(pciDevice, assign dp0$wmiS0_MDataLast = wmiDP0_MDataLast ; assign dp0$wmiS0_MReset_n = wmiDP0_MReset_n ; assign dp0$EN_server_request_put = - noc_sm1$RDY_c0_request_get && dp0$RDY_server_request_put ; + dp0$RDY_server_request_put && noc_sm1$RDY_c0_request_get ; assign dp0$EN_server_response_get = - noc_sm1$RDY_c0_response_put && dp0$RDY_server_response_get ; + dp0$RDY_server_response_get && noc_sm1$RDY_c0_response_put ; // submodule dp1 assign dp1$server_request_put = noc_sm2$c0_request_get ; @@ -3083,9 +2713,9 @@ module mkOCInf16B(pciDevice, assign dp1$wmiS0_MDataLast = wmiDP1_MDataLast ; assign dp1$wmiS0_MReset_n = wmiDP1_MReset_n ; assign dp1$EN_server_request_put = - noc_sm2$RDY_c0_request_get && dp1$RDY_server_request_put ; + dp1$RDY_server_request_put && noc_sm2$RDY_c0_request_get ; assign dp1$EN_server_response_get = - noc_sm2$RDY_c0_response_put && dp1$RDY_server_response_get ; + dp1$RDY_server_response_get && noc_sm2$RDY_c0_response_put ; // submodule itc0 assign itc0$gpsTime_arg = cp$cpNow ; @@ -3100,172 +2730,58 @@ module mkOCInf16B(pciDevice, assign itc1$wti_m_SReset_n = dp1$wti_s_SReset_n ; // submodule noc_sm0 - assign noc_sm0$c0_response_put = cpTlp_outF$D_OUT ; + assign noc_sm0$c0_response_put = cpTlp$server_response_get ; assign noc_sm0$c1_response_put = noc_sm1$s_response_get ; assign noc_sm0$s_request_put = server_request_put ; assign noc_sm0$EN_s_request_put = EN_server_request_put ; assign noc_sm0$EN_s_response_get = EN_server_response_get ; assign noc_sm0$EN_c0_request_get = - noc_sm0$RDY_c0_request_get && cpTlp_inF$FULL_N ; + cpTlp$RDY_server_request_put && noc_sm0$RDY_c0_request_get ; assign noc_sm0$EN_c0_response_put = - noc_sm0$RDY_c0_response_put && cpTlp_outF$EMPTY_N ; + cpTlp$RDY_server_response_get && noc_sm0$RDY_c0_response_put ; assign noc_sm0$EN_c1_request_get = - noc_sm1$RDY_s_request_put && noc_sm0$RDY_c1_request_get ; + noc_sm0$RDY_c1_request_get && noc_sm1$RDY_s_request_put ; assign noc_sm0$EN_c1_response_put = - noc_sm1$RDY_s_response_get && noc_sm0$RDY_c1_response_put ; + noc_sm0$RDY_c1_response_put && noc_sm1$RDY_s_response_get ; // submodule noc_sm1 assign noc_sm1$c0_response_put = dp0$server_response_get ; assign noc_sm1$c1_response_put = noc_sm2$s_response_get ; assign noc_sm1$s_request_put = noc_sm0$c1_request_get ; assign noc_sm1$EN_s_request_put = - noc_sm1$RDY_s_request_put && noc_sm0$RDY_c1_request_get ; + noc_sm0$RDY_c1_request_get && noc_sm1$RDY_s_request_put ; assign noc_sm1$EN_s_response_get = - noc_sm1$RDY_s_response_get && noc_sm0$RDY_c1_response_put ; + noc_sm0$RDY_c1_response_put && noc_sm1$RDY_s_response_get ; assign noc_sm1$EN_c0_request_get = - noc_sm1$RDY_c0_request_get && dp0$RDY_server_request_put ; + dp0$RDY_server_request_put && noc_sm1$RDY_c0_request_get ; assign noc_sm1$EN_c0_response_put = - noc_sm1$RDY_c0_response_put && dp0$RDY_server_response_get ; + dp0$RDY_server_response_get && noc_sm1$RDY_c0_response_put ; assign noc_sm1$EN_c1_request_get = - noc_sm2$RDY_s_request_put && noc_sm1$RDY_c1_request_get ; + noc_sm1$RDY_c1_request_get && noc_sm2$RDY_s_request_put ; assign noc_sm1$EN_c1_response_put = - noc_sm2$RDY_s_response_get && noc_sm1$RDY_c1_response_put ; + noc_sm1$RDY_c1_response_put && noc_sm2$RDY_s_response_get ; // submodule noc_sm2 assign noc_sm2$c0_response_put = dp1$server_response_get ; assign noc_sm2$c1_response_put = 153'h0 ; assign noc_sm2$s_request_put = noc_sm1$c1_request_get ; assign noc_sm2$EN_s_request_put = - noc_sm2$RDY_s_request_put && noc_sm1$RDY_c1_request_get ; + noc_sm1$RDY_c1_request_get && noc_sm2$RDY_s_request_put ; assign noc_sm2$EN_s_response_get = - noc_sm2$RDY_s_response_get && noc_sm1$RDY_c1_response_put ; + noc_sm1$RDY_c1_response_put && noc_sm2$RDY_s_response_get ; assign noc_sm2$EN_c0_request_get = - noc_sm2$RDY_c0_request_get && dp1$RDY_server_request_put ; + dp1$RDY_server_request_put && noc_sm2$RDY_c0_request_get ; assign noc_sm2$EN_c0_response_put = - noc_sm2$RDY_c0_response_put && dp1$RDY_server_response_get ; + dp1$RDY_server_response_get && noc_sm2$RDY_c0_response_put ; assign noc_sm2$EN_c1_request_get = noc_sm2$RDY_c1_request_get ; assign noc_sm2$EN_c1_response_put = 1'b0 ; // remaining internal signals - assign IF_cpTlp_tlpReq_6_BIT_62_7_AND_NOT_cpTlp_tlpFi_ETC___d336 = - (cpTlp_tlpReq[62] && !cpTlp_tlpFirst) ? v__h5693 : cpTlp_tlpDW ; - assign IF_cpTlp_tlpReq_6_BIT_62_7_THEN_cpTlp_tlpDWAdd_ETC___d147 = - cpTlp_tlpReq[62] ? - { cpTlp_tlpDWAddr[21:0], - _theResult_____2__h5635, - wreq_data__h6249 } : - { 24'hAAAAAA, - cpTlp_tlpReq[15:8], - cpTlp_tlpDWAddr[21:0], - _theResult_____2__h5635 } ; - assign _theResult_____2__h5635 = - cpTlp_tlpFirst ? - cpTlp_tlpReq[3:0] : - ((cpTlp_tlpUnroll == 10'd1) ? cpTlp_tlpReq[7:4] : 4'hF) ; - assign byteCount__h5220 = x__h5439 - y__h5440 ; - assign cpMux_aActF_i_notEmpty__45_AND_IF_cpMux_aActF__ETC___d250 = + assign cpMux_aActF_i_notEmpty__1_AND_IF_cpMux_aActF_f_ETC___d46 = cpMux_aActF$EMPTY_N && (cpMux_aActF$D_OUT ? cpMux_respAF$FULL_N : cpMux_respBF$FULL_N) ; - assign cpTlp_tlpFirst_9_OR_IF_cpTlp_tlpDWp_00_EQ_0_01_ETC___d110 = - cpTlp_tlpFirst || - CASE_cpTlp_tlpDWp_NOT_cpTlp_tlpDWp_EQ_3_OR_cpT_ETC__q1 ; - assign lowAddr__h5219 = { cpTlp_inF$D_OUT[38:34], lowAddr10__h5218 } ; - assign pkt__h7418 = - { 9'd148, - cpTlp_cmpF$D_OUT[39:37], - 10'd0, - cpTlp_cmpF$D_OUT[21:12], - pciDevice, - 4'd0, - cpTlp_cmpF$D_OUT[11:0], - cpTlp_cmpF$D_OUT[55:40], - cpTlp_cmpF$D_OUT[36:29], - 1'b0, - cpTlp_cmpF$D_OUT[28:22], - cpTlp_cpRespF$D_OUT[7:0], - cpTlp_cpRespF$D_OUT[15:8], - cpTlp_cpRespF$D_OUT[23:16], - cpTlp_cpRespF$D_OUT[31:24] } ; - assign pw_be__h10405 = (cpTlp_rss == 2'd2) ? lastRema__h10373 : 16'd65535 ; - assign pw_data__h10406 = - x__h10825[1] ? - (x__h10825[0] ? - { cpTlp_rdv[31:0], cpTlp_rdv[127:32] } : - { cpTlp_rdv[63:0], cpTlp_rdv[127:64] }) : - (x__h10825[0] ? - { cpTlp_rdv[95:0], cpTlp_rdv[127:96] } : - cpTlp_rdv) ; - assign wreq_data__h6249 = - { IF_cpTlp_tlpReq_6_BIT_62_7_AND_NOT_cpTlp_tlpFi_ETC___d336[7:0], - IF_cpTlp_tlpReq_6_BIT_62_7_AND_NOT_cpTlp_tlpFi_ETC___d336[15:8], - IF_cpTlp_tlpReq_6_BIT_62_7_AND_NOT_cpTlp_tlpFi_ETC___d336[23:16], - IF_cpTlp_tlpReq_6_BIT_62_7_AND_NOT_cpTlp_tlpFi_ETC___d336[31:24] } ; - assign x__h10825 = 3'h4 - { 1'd0, cpTlp_rdp } ; - assign x__h2791 = { pciDevice[15:3], 3'd0 } ; - assign x__h3085 = { pciDevice[15:3], 3'd1 } ; - assign x__h5439 = x__h5441 - y__h5442 ; - assign x__h5441 = { cpTlp_inF$D_OUT[105:96], 2'b0 } ; - assign y__h5440 = - (cpTlp_inF$D_OUT[105:96] == 10'd1) ? - 12'd0 : - { 10'd0, x__h5471 } ; - assign y__h5442 = { 10'd0, x__h5448 } ; - always@(cpTlp_inF$D_OUT) - begin - case (cpTlp_inF$D_OUT[67:64]) - 4'b1100: x__h5448 = 2'b10; - 4'b1110: x__h5448 = 2'b01; - 4'b1111: x__h5448 = 2'b0; - default: x__h5448 = 2'b11; - endcase - end - always@(cpTlp_inF$D_OUT) - begin - case (cpTlp_inF$D_OUT[71:68]) - 4'b1100: x__h5471 = 2'b10; - 4'b1110: x__h5471 = 2'b01; - 4'b1111: x__h5471 = 2'b0; - default: x__h5471 = 2'b11; - endcase - end - always@(cpTlp_tlpDWp or cpTlp_inF$D_OUT) - begin - case (cpTlp_tlpDWp) - 2'd0: v__h5693 = cpTlp_inF$D_OUT[31:0]; - 2'd1: v__h5693 = cpTlp_inF$D_OUT[63:32]; - 2'd2: v__h5693 = cpTlp_inF$D_OUT[95:64]; - 2'd3: v__h5693 = cpTlp_inF$D_OUT[127:96]; - endcase - end - always@(cpTlp_rdp) - begin - case (cpTlp_rdp) - 2'b0: lastRema__h10373 = 16'hFFFF; - 2'b01: lastRema__h10373 = 16'hF000; - 2'b10: lastRema__h10373 = 16'hFF00; - 2'd3: lastRema__h10373 = 16'hFFF0; - endcase - end - always@(cpTlp_inF$D_OUT) - begin - case (cpTlp_inF$D_OUT[67:64]) - 4'b1000: lowAddr10__h5218 = 2'b11; - 4'b1100: lowAddr10__h5218 = 2'b10; - 4'b1110: lowAddr10__h5218 = 2'b01; - default: lowAddr10__h5218 = 2'b0; - endcase - end - always@(cpTlp_tlpDWp or cpTlp_inF$EMPTY_N) - begin - case (cpTlp_tlpDWp) - 2'd0, 2'd1, 2'd2: - CASE_cpTlp_tlpDWp_NOT_cpTlp_tlpDWp_EQ_3_OR_cpT_ETC__q1 = - cpTlp_inF$EMPTY_N; - 2'd3: - CASE_cpTlp_tlpDWp_NOT_cpTlp_tlpDWp_EQ_3_OR_cpT_ETC__q1 = - cpTlp_tlpDWp != 2'd3 || cpTlp_inF$EMPTY_N; - endcase - end + assign x__h2806 = { pciDevice[15:3], 3'd0 } ; + assign x__h3100 = { pciDevice[15:3], 3'd1 } ; // handling of inlined registers @@ -3273,37 +2789,13 @@ module mkOCInf16B(pciDevice, begin if (RST_N == `BSV_RESET_VALUE) begin - cpTlp_cmpActive <= `BSV_ASSIGNMENT_DELAY 1'd0; - cpTlp_rdp <= `BSV_ASSIGNMENT_DELAY 2'd0; - cpTlp_rss <= `BSV_ASSIGNMENT_DELAY 2'd0; - cpTlp_tlpActive <= `BSV_ASSIGNMENT_DELAY 1'd0; - noc_chompCnt <= `BSV_ASSIGNMENT_DELAY 8'd0; + noc_chompCnt <= `BSV_ASSIGNMENT_DELAY 8'd0; end else begin - if (cpTlp_cmpActive$EN) - cpTlp_cmpActive <= `BSV_ASSIGNMENT_DELAY cpTlp_cmpActive$D_IN; - if (cpTlp_rdp$EN) cpTlp_rdp <= `BSV_ASSIGNMENT_DELAY cpTlp_rdp$D_IN; - if (cpTlp_rss$EN) cpTlp_rss <= `BSV_ASSIGNMENT_DELAY cpTlp_rss$D_IN; - if (cpTlp_tlpActive$EN) - cpTlp_tlpActive <= `BSV_ASSIGNMENT_DELAY cpTlp_tlpActive$D_IN; - if (noc_chompCnt$EN) + if (noc_chompCnt$EN) noc_chompCnt <= `BSV_ASSIGNMENT_DELAY noc_chompCnt$D_IN; end - if (cpTlp_cmpDWRemain$EN) - cpTlp_cmpDWRemain <= `BSV_ASSIGNMENT_DELAY cpTlp_cmpDWRemain$D_IN; - if (cpTlp_rdv$EN) cpTlp_rdv <= `BSV_ASSIGNMENT_DELAY cpTlp_rdv$D_IN; - if (cpTlp_tlpDW$EN) cpTlp_tlpDW <= `BSV_ASSIGNMENT_DELAY cpTlp_tlpDW$D_IN; - if (cpTlp_tlpDWAddr$EN) - cpTlp_tlpDWAddr <= `BSV_ASSIGNMENT_DELAY cpTlp_tlpDWAddr$D_IN; - if (cpTlp_tlpDWp$EN) - cpTlp_tlpDWp <= `BSV_ASSIGNMENT_DELAY cpTlp_tlpDWp$D_IN; - if (cpTlp_tlpFirst$EN) - cpTlp_tlpFirst <= `BSV_ASSIGNMENT_DELAY cpTlp_tlpFirst$D_IN; - if (cpTlp_tlpReq$EN) - cpTlp_tlpReq <= `BSV_ASSIGNMENT_DELAY cpTlp_tlpReq$D_IN; - if (cpTlp_tlpUnroll$EN) - cpTlp_tlpUnroll <= `BSV_ASSIGNMENT_DELAY cpTlp_tlpUnroll$D_IN; end // synopsys translate_off @@ -3311,18 +2803,6 @@ module mkOCInf16B(pciDevice, `else // not BSV_NO_INITIAL_BLOCKS initial begin - cpTlp_cmpActive = 1'h0; - cpTlp_cmpDWRemain = 10'h2AA; - cpTlp_rdp = 2'h2; - cpTlp_rdv = 128'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - cpTlp_rss = 2'h2; - cpTlp_tlpActive = 1'h0; - cpTlp_tlpDW = 32'hAAAAAAAA; - cpTlp_tlpDWAddr = 30'h2AAAAAAA; - cpTlp_tlpDWp = 2'h2; - cpTlp_tlpFirst = 1'h0; - cpTlp_tlpReq = 64'hAAAAAAAAAAAAAAAA; - cpTlp_tlpUnroll = 10'h2AA; noc_chompCnt = 8'hAA; end `endif // BSV_NO_INITIAL_BLOCKS diff --git a/rtl/mkOCInf4B.v b/rtl/mkOCInf4B.v index b99af721..81d9cc2c 100644 --- a/rtl/mkOCInf4B.v +++ b/rtl/mkOCInf4B.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2012.09.beta1 (build 29570, 2012-09.11) // -// On Tue Dec 11 16:21:45 EST 2012 +// On Tue Jan 1 09:13:37 EST 2013 // // // Ports: @@ -1824,7 +1824,7 @@ module mkOCInf4B(pciDevice, reg CASE_cpTlp_tlpDWp_NOT_cpTlp_tlpDWp_EQ_3_OR_cpT_ETC__q1; wire [127 : 0] pkt__h7418, pw_data__h10406; wire [57 : 0] IF_cpTlp_tlpReq_6_BIT_62_7_THEN_cpTlp_tlpDWAdd_ETC___d147; - wire [31 : 0] IF_cpTlp_tlpReq_6_BIT_62_7_AND_NOT_cpTlp_tlpFi_ETC___d337, + wire [31 : 0] IF_cpTlp_tlpReq_6_BIT_62_7_AND_NOT_cpTlp_tlpFi_ETC___d335, wreq_data__h6249; wire [15 : 0] pw_be__h10405, x__h2791, x__h3085; wire [11 : 0] byteCount__h5220, x__h5439, x__h5441, y__h5440, y__h5442; @@ -2472,7 +2472,7 @@ module mkOCInf4B(pciDevice, // submodule dp0 mkOCDP4B #(.hasPush(1'd0), .hasPull(1'd1), - .hasDebugLogic(1'd0)) dp0(.pciDevice(x__h2791), + .hasDebugLogic(1'd1)) dp0(.pciDevice(x__h2791), .CLK(CLK), .RST_N(cp$RST_N_wci_Vm_13), .server_request_put(dp0$server_request_put), @@ -2517,7 +2517,7 @@ module mkOCInf4B(pciDevice, // submodule dp1 mkOCDP4B #(.hasPush(1'd1), .hasPull(1'd0), - .hasDebugLogic(1'd0)) dp1(.pciDevice(x__h3085), + .hasDebugLogic(1'd1)) dp1(.pciDevice(x__h3085), .CLK(CLK), .RST_N(cp$RST_N_wci_Vm_14), .server_request_put(dp1$server_request_put), @@ -3111,35 +3111,35 @@ module mkOCInf4B(pciDevice, assign noc_sm0$EN_c0_response_put = noc_sm0$RDY_c0_response_put && cpTlp_outF$EMPTY_N ; assign noc_sm0$EN_c1_request_get = - noc_sm0$RDY_c1_request_get && noc_sm1$RDY_s_request_put ; + noc_sm1$RDY_s_request_put && noc_sm0$RDY_c1_request_get ; assign noc_sm0$EN_c1_response_put = - noc_sm0$RDY_c1_response_put && noc_sm1$RDY_s_response_get ; + noc_sm1$RDY_s_response_get && noc_sm0$RDY_c1_response_put ; // submodule noc_sm1 assign noc_sm1$c0_response_put = dp0$server_response_get ; assign noc_sm1$c1_response_put = noc_sm2$s_response_get ; assign noc_sm1$s_request_put = noc_sm0$c1_request_get ; assign noc_sm1$EN_s_request_put = - noc_sm0$RDY_c1_request_get && noc_sm1$RDY_s_request_put ; + noc_sm1$RDY_s_request_put && noc_sm0$RDY_c1_request_get ; assign noc_sm1$EN_s_response_get = - noc_sm0$RDY_c1_response_put && noc_sm1$RDY_s_response_get ; + noc_sm1$RDY_s_response_get && noc_sm0$RDY_c1_response_put ; assign noc_sm1$EN_c0_request_get = noc_sm1$RDY_c0_request_get && dp0$RDY_server_request_put ; assign noc_sm1$EN_c0_response_put = noc_sm1$RDY_c0_response_put && dp0$RDY_server_response_get ; assign noc_sm1$EN_c1_request_get = - noc_sm1$RDY_c1_request_get && noc_sm2$RDY_s_request_put ; + noc_sm2$RDY_s_request_put && noc_sm1$RDY_c1_request_get ; assign noc_sm1$EN_c1_response_put = - noc_sm1$RDY_c1_response_put && noc_sm2$RDY_s_response_get ; + noc_sm2$RDY_s_response_get && noc_sm1$RDY_c1_response_put ; // submodule noc_sm2 assign noc_sm2$c0_response_put = dp1$server_response_get ; assign noc_sm2$c1_response_put = 153'h0 ; assign noc_sm2$s_request_put = noc_sm1$c1_request_get ; assign noc_sm2$EN_s_request_put = - noc_sm1$RDY_c1_request_get && noc_sm2$RDY_s_request_put ; + noc_sm2$RDY_s_request_put && noc_sm1$RDY_c1_request_get ; assign noc_sm2$EN_s_response_get = - noc_sm1$RDY_c1_response_put && noc_sm2$RDY_s_response_get ; + noc_sm2$RDY_s_response_get && noc_sm1$RDY_c1_response_put ; assign noc_sm2$EN_c0_request_get = noc_sm2$RDY_c0_request_get && dp1$RDY_server_request_put ; assign noc_sm2$EN_c0_response_put = @@ -3148,7 +3148,7 @@ module mkOCInf4B(pciDevice, assign noc_sm2$EN_c1_response_put = 1'b0 ; // remaining internal signals - assign IF_cpTlp_tlpReq_6_BIT_62_7_AND_NOT_cpTlp_tlpFi_ETC___d337 = + assign IF_cpTlp_tlpReq_6_BIT_62_7_AND_NOT_cpTlp_tlpFi_ETC___d335 = (cpTlp_tlpReq[62] && !cpTlp_tlpFirst) ? v__h5693 : cpTlp_tlpDW ; assign IF_cpTlp_tlpReq_6_BIT_62_7_THEN_cpTlp_tlpDWAdd_ETC___d147 = cpTlp_tlpReq[62] ? @@ -3197,10 +3197,10 @@ module mkOCInf4B(pciDevice, { cpTlp_rdv[95:0], cpTlp_rdv[127:96] } : cpTlp_rdv) ; assign wreq_data__h6249 = - { IF_cpTlp_tlpReq_6_BIT_62_7_AND_NOT_cpTlp_tlpFi_ETC___d337[7:0], - IF_cpTlp_tlpReq_6_BIT_62_7_AND_NOT_cpTlp_tlpFi_ETC___d337[15:8], - IF_cpTlp_tlpReq_6_BIT_62_7_AND_NOT_cpTlp_tlpFi_ETC___d337[23:16], - IF_cpTlp_tlpReq_6_BIT_62_7_AND_NOT_cpTlp_tlpFi_ETC___d337[31:24] } ; + { IF_cpTlp_tlpReq_6_BIT_62_7_AND_NOT_cpTlp_tlpFi_ETC___d335[7:0], + IF_cpTlp_tlpReq_6_BIT_62_7_AND_NOT_cpTlp_tlpFi_ETC___d335[15:8], + IF_cpTlp_tlpReq_6_BIT_62_7_AND_NOT_cpTlp_tlpFi_ETC___d335[23:16], + IF_cpTlp_tlpReq_6_BIT_62_7_AND_NOT_cpTlp_tlpFi_ETC___d335[31:24] } ; assign x__h10825 = 3'h4 - { 1'd0, cpTlp_rdp } ; assign x__h2791 = { pciDevice[15:3], 3'd0 } ; assign x__h3085 = { pciDevice[15:3], 3'd1 } ; diff --git a/rtl/mkPktFork.v b/rtl/mkPktFork.v index 5e861c93..a204cdf1 100644 --- a/rtl/mkPktFork.v +++ b/rtl/mkPktFork.v @@ -1,7 +1,7 @@ // -// Generated by Bluespec Compiler, version 2012.09.beta1 (build 29570, 2012-09.11) +// Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Tue Dec 11 16:19:42 EST 2012 +// On Fri Jun 21 16:58:23 EDT 2013 // // // Ports: @@ -103,12 +103,12 @@ module mkPktFork(pfk, wire MUX_f0Active$write_1__SEL_1, MUX_f1Active$write_1__SEL_1; // remaining internal signals - reg IF_pfk_BITS_13_TO_12_5_EQ_0_6_THEN_fi_first_BI_ETC___d69; - wire [6 : 0] y__h617, y__h842; + reg IF_pfk_BITS_13_TO_12_5_EQ_0_6_THEN_fi_first_BI_ETC___d45; + wire [6 : 0] y__h617, y__h837; wire IF_fi_first_BITS_124_TO_120_2_EQ_0b1010_3_THEN_ETC___d33, IF_fi_first_BITS_124_TO_120_2_EQ_0b1010_3_THEN_ETC___d42, fi_RDY_first_AND_IF_IF_pfk_BITS_13_TO_12_5_EQ__ETC___d47, - fi_first_BITS_63_TO_56_5_EQ_pfk_BITS_7_TO_0_6___d66; + fi_first_BITS_63_TO_56_5_EQ_pfk_BITS_7_TO_0_6___d37; // action method iport_put assign RDY_iport_put = fi$FULL_N ; @@ -125,34 +125,34 @@ module mkPktFork(pfk, arSRLFIFOD #(.width(32'd153), .l2depth(32'd4)) fi(.CLK(CLK), .RST_N(RST_N), .D_IN(fi$D_IN), - .DEQ(fi$DEQ), .ENQ(fi$ENQ), + .DEQ(fi$DEQ), .CLR(fi$CLR), - .EMPTY_N(fi$EMPTY_N), .D_OUT(fi$D_OUT), - .FULL_N(fi$FULL_N)); + .FULL_N(fi$FULL_N), + .EMPTY_N(fi$EMPTY_N)); // submodule fo0 arSRLFIFOD #(.width(32'd153), .l2depth(32'd4)) fo0(.CLK(CLK), .RST_N(RST_N), .D_IN(fo0$D_IN), - .DEQ(fo0$DEQ), .ENQ(fo0$ENQ), + .DEQ(fo0$DEQ), .CLR(fo0$CLR), - .EMPTY_N(fo0$EMPTY_N), .D_OUT(fo0$D_OUT), - .FULL_N(fo0$FULL_N)); + .FULL_N(fo0$FULL_N), + .EMPTY_N(fo0$EMPTY_N)); // submodule fo1 arSRLFIFOD #(.width(32'd153), .l2depth(32'd4)) fo1(.CLK(CLK), .RST_N(RST_N), .D_IN(fo1$D_IN), - .DEQ(fo1$DEQ), .ENQ(fo1$ENQ), + .DEQ(fo1$DEQ), .CLR(fo1$CLR), - .EMPTY_N(fo1$EMPTY_N), .D_OUT(fo1$D_OUT), - .FULL_N(fo1$FULL_N)); + .FULL_N(fo1$FULL_N), + .EMPTY_N(fo1$EMPTY_N)); // rule RL_fo0_advance assign WILL_FIRE_RL_fo0_advance = fo0$FULL_N && fi$EMPTY_N && f0Active ; @@ -172,17 +172,17 @@ module mkPktFork(pfk, // inputs to muxes for submodule ports assign MUX_f0Active$write_1__SEL_1 = WILL_FIRE_RL_select && - IF_pfk_BITS_13_TO_12_5_EQ_0_6_THEN_fi_first_BI_ETC___d69 ; + IF_pfk_BITS_13_TO_12_5_EQ_0_6_THEN_fi_first_BI_ETC___d45 ; assign MUX_f1Active$write_1__SEL_1 = WILL_FIRE_RL_select && - !IF_pfk_BITS_13_TO_12_5_EQ_0_6_THEN_fi_first_BI_ETC___d69 ; + !IF_pfk_BITS_13_TO_12_5_EQ_0_6_THEN_fi_first_BI_ETC___d45 ; // register f0Active assign f0Active$D_IN = MUX_f0Active$write_1__SEL_1 ? !fi$D_OUT[151] : !fi$D_OUT[151] ; assign f0Active$EN = WILL_FIRE_RL_select && - IF_pfk_BITS_13_TO_12_5_EQ_0_6_THEN_fi_first_BI_ETC___d69 || + IF_pfk_BITS_13_TO_12_5_EQ_0_6_THEN_fi_first_BI_ETC___d45 || WILL_FIRE_RL_fo0_advance ; // register f1Active @@ -190,73 +190,73 @@ module mkPktFork(pfk, MUX_f1Active$write_1__SEL_1 ? !fi$D_OUT[151] : !fi$D_OUT[151] ; assign f1Active$EN = WILL_FIRE_RL_select && - !IF_pfk_BITS_13_TO_12_5_EQ_0_6_THEN_fi_first_BI_ETC___d69 || + !IF_pfk_BITS_13_TO_12_5_EQ_0_6_THEN_fi_first_BI_ETC___d45 || WILL_FIRE_RL_fo1_advance ; // submodule fi assign fi$D_IN = iport_put ; + assign fi$ENQ = EN_iport_put ; assign fi$DEQ = WILL_FIRE_RL_select || WILL_FIRE_RL_fo1_advance || WILL_FIRE_RL_fo0_advance ; - assign fi$ENQ = EN_iport_put ; assign fi$CLR = 1'b0 ; // submodule fo0 assign fo0$D_IN = fi$D_OUT ; - assign fo0$DEQ = EN_oport0_get ; assign fo0$ENQ = WILL_FIRE_RL_select && - IF_pfk_BITS_13_TO_12_5_EQ_0_6_THEN_fi_first_BI_ETC___d69 || + IF_pfk_BITS_13_TO_12_5_EQ_0_6_THEN_fi_first_BI_ETC___d45 || WILL_FIRE_RL_fo0_advance ; + assign fo0$DEQ = EN_oport0_get ; assign fo0$CLR = 1'b0 ; // submodule fo1 assign fo1$D_IN = fi$D_OUT ; - assign fo1$DEQ = EN_oport1_get ; assign fo1$ENQ = WILL_FIRE_RL_select && - !IF_pfk_BITS_13_TO_12_5_EQ_0_6_THEN_fi_first_BI_ETC___d69 || + !IF_pfk_BITS_13_TO_12_5_EQ_0_6_THEN_fi_first_BI_ETC___d45 || WILL_FIRE_RL_fo1_advance ; + assign fo1$DEQ = EN_oport1_get ; assign fo1$CLR = 1'b0 ; // remaining internal signals assign IF_fi_first_BITS_124_TO_120_2_EQ_0b1010_3_THEN_ETC___d33 = (fi$D_OUT[124:120] == 5'b01010) ? fi$D_OUT[50:48] == pfk[2:0] : - fi$D_OUT[150:144] == y__h842 && pfk[3] == fi$D_OUT[47] ; + fi$D_OUT[150:144] == y__h837 && pfk[3] == fi$D_OUT[47] ; assign IF_fi_first_BITS_124_TO_120_2_EQ_0b1010_3_THEN_ETC___d42 = (fi$D_OUT[124:120] == 5'b01010) ? - fi_first_BITS_63_TO_56_5_EQ_pfk_BITS_7_TO_0_6___d66 : + fi_first_BITS_63_TO_56_5_EQ_pfk_BITS_7_TO_0_6___d37 : pfk[11:8] == fi$D_OUT[60:57] ; assign fi_RDY_first_AND_IF_IF_pfk_BITS_13_TO_12_5_EQ__ETC___d47 = fi$EMPTY_N && - (IF_pfk_BITS_13_TO_12_5_EQ_0_6_THEN_fi_first_BI_ETC___d69 ? + (IF_pfk_BITS_13_TO_12_5_EQ_0_6_THEN_fi_first_BI_ETC___d45 ? fo0$FULL_N : fo1$FULL_N) ; - assign fi_first_BITS_63_TO_56_5_EQ_pfk_BITS_7_TO_0_6___d66 = + assign fi_first_BITS_63_TO_56_5_EQ_pfk_BITS_7_TO_0_6___d37 = fi$D_OUT[63:56] == pfk[7:0] ; assign y__h617 = 7'd1 << pfk[2:0] ; - assign y__h842 = 7'd1 << pfk[6:4] ; + assign y__h837 = 7'd1 << pfk[6:4] ; always@(pfk or IF_fi_first_BITS_124_TO_120_2_EQ_0b1010_3_THEN_ETC___d42 or fi$D_OUT or y__h617 or - fi_first_BITS_63_TO_56_5_EQ_pfk_BITS_7_TO_0_6___d66 or + fi_first_BITS_63_TO_56_5_EQ_pfk_BITS_7_TO_0_6___d37 or IF_fi_first_BITS_124_TO_120_2_EQ_0b1010_3_THEN_ETC___d33) begin case (pfk[13:12]) 2'd0: - IF_pfk_BITS_13_TO_12_5_EQ_0_6_THEN_fi_first_BI_ETC___d69 = + IF_pfk_BITS_13_TO_12_5_EQ_0_6_THEN_fi_first_BI_ETC___d45 = fi$D_OUT[150:144] == y__h617; 2'd1: - IF_pfk_BITS_13_TO_12_5_EQ_0_6_THEN_fi_first_BI_ETC___d69 = - fi_first_BITS_63_TO_56_5_EQ_pfk_BITS_7_TO_0_6___d66 && + IF_pfk_BITS_13_TO_12_5_EQ_0_6_THEN_fi_first_BI_ETC___d45 = + fi_first_BITS_63_TO_56_5_EQ_pfk_BITS_7_TO_0_6___d37 && fi$D_OUT[124:120] == 5'b01010; 2'd2: - IF_pfk_BITS_13_TO_12_5_EQ_0_6_THEN_fi_first_BI_ETC___d69 = + IF_pfk_BITS_13_TO_12_5_EQ_0_6_THEN_fi_first_BI_ETC___d45 = IF_fi_first_BITS_124_TO_120_2_EQ_0b1010_3_THEN_ETC___d33; 2'd3: - IF_pfk_BITS_13_TO_12_5_EQ_0_6_THEN_fi_first_BI_ETC___d69 = + IF_pfk_BITS_13_TO_12_5_EQ_0_6_THEN_fi_first_BI_ETC___d45 = IF_fi_first_BITS_124_TO_120_2_EQ_0b1010_3_THEN_ETC___d42; endcase end diff --git a/rtl/mkPktMerge.v b/rtl/mkPktMerge.v index f96a200f..fa1d755d 100644 --- a/rtl/mkPktMerge.v +++ b/rtl/mkPktMerge.v @@ -1,7 +1,7 @@ // -// Generated by Bluespec Compiler, version 2012.09.beta1 (build 29570, 2012-09.11) +// Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Tue Dec 11 16:19:42 EST 2012 +// On Fri Jun 21 16:58:23 EDT 2013 // // // Ports: @@ -103,7 +103,7 @@ module mkPktMerge(CLK, WILL_FIRE_RL_fi1_advance; // inputs to muxes for submodule ports - wire [152 : 0] MUX_fo$enq_1__VAL_1; + wire [152 : 0] MUX_fo$enq_1__VAL_3; wire MUX_fi0Active$write_1__SEL_1, MUX_fi0Active$write_1__VAL_1, MUX_fi1Active$write_1__SEL_1; @@ -126,34 +126,34 @@ module mkPktMerge(CLK, arSRLFIFOD #(.width(32'd153), .l2depth(32'd4)) fi0(.CLK(CLK), .RST_N(RST_N), .D_IN(fi0$D_IN), - .DEQ(fi0$DEQ), .ENQ(fi0$ENQ), + .DEQ(fi0$DEQ), .CLR(fi0$CLR), - .EMPTY_N(fi0$EMPTY_N), .D_OUT(fi0$D_OUT), - .FULL_N(fi0$FULL_N)); + .FULL_N(fi0$FULL_N), + .EMPTY_N(fi0$EMPTY_N)); // submodule fi1 arSRLFIFOD #(.width(32'd153), .l2depth(32'd4)) fi1(.CLK(CLK), .RST_N(RST_N), .D_IN(fi1$D_IN), - .DEQ(fi1$DEQ), .ENQ(fi1$ENQ), + .DEQ(fi1$DEQ), .CLR(fi1$CLR), - .EMPTY_N(fi1$EMPTY_N), .D_OUT(fi1$D_OUT), - .FULL_N(fi1$FULL_N)); + .FULL_N(fi1$FULL_N), + .EMPTY_N(fi1$EMPTY_N)); // submodule fo arSRLFIFOD #(.width(32'd153), .l2depth(32'd4)) fo(.CLK(CLK), .RST_N(RST_N), .D_IN(fo$D_IN), - .DEQ(fo$DEQ), .ENQ(fo$ENQ), + .DEQ(fo$DEQ), .CLR(fo$CLR), - .EMPTY_N(fo$EMPTY_N), .D_OUT(fo$D_OUT), - .FULL_N(fo$FULL_N)); + .FULL_N(fo$FULL_N), + .EMPTY_N(fo$EMPTY_N)); // rule RL_fi0_advance assign WILL_FIRE_RL_fi0_advance = @@ -180,7 +180,7 @@ module mkPktMerge(CLK, WILL_FIRE_RL_arbitrate && !fi0HasPrio ; assign MUX_fi0Active$write_1__VAL_1 = fi0HasPrio ? !fi0$D_OUT[151] : !fi1$D_OUT[151] ; - assign MUX_fo$enq_1__VAL_1 = fi0HasPrio ? fi0$D_OUT : fi1$D_OUT ; + assign MUX_fo$enq_1__VAL_3 = fi0HasPrio ? fi0$D_OUT : fi1$D_OUT ; // register fi0Active assign fi0Active$D_IN = @@ -217,38 +217,38 @@ module mkPktMerge(CLK, // submodule fi0 assign fi0$D_IN = iport0_put ; + assign fi0$ENQ = EN_iport0_put ; assign fi0$DEQ = WILL_FIRE_RL_arbitrate && fi0HasPrio || WILL_FIRE_RL_fi0_advance ; - assign fi0$ENQ = EN_iport0_put ; assign fi0$CLR = 1'b0 ; // submodule fi1 assign fi1$D_IN = iport1_put ; + assign fi1$ENQ = EN_iport1_put ; assign fi1$DEQ = WILL_FIRE_RL_arbitrate && !fi0HasPrio || WILL_FIRE_RL_fi1_advance ; - assign fi1$ENQ = EN_iport1_put ; assign fi1$CLR = 1'b0 ; // submodule fo - always@(WILL_FIRE_RL_arbitrate or - MUX_fo$enq_1__VAL_1 or - WILL_FIRE_RL_fi0_advance or - fi0$D_OUT or WILL_FIRE_RL_fi1_advance or fi1$D_OUT) + always@(WILL_FIRE_RL_fi0_advance or + fi0$D_OUT or + WILL_FIRE_RL_fi1_advance or + fi1$D_OUT or WILL_FIRE_RL_arbitrate or MUX_fo$enq_1__VAL_3) begin case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_arbitrate: fo$D_IN = MUX_fo$enq_1__VAL_1; WILL_FIRE_RL_fi0_advance: fo$D_IN = fi0$D_OUT; WILL_FIRE_RL_fi1_advance: fo$D_IN = fi1$D_OUT; + WILL_FIRE_RL_arbitrate: fo$D_IN = MUX_fo$enq_1__VAL_3; default: fo$D_IN = 153'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ; endcase end - assign fo$DEQ = EN_oport_get ; assign fo$ENQ = - WILL_FIRE_RL_arbitrate || WILL_FIRE_RL_fi0_advance || - WILL_FIRE_RL_fi1_advance ; + WILL_FIRE_RL_fi0_advance || WILL_FIRE_RL_fi1_advance || + WILL_FIRE_RL_arbitrate ; + assign fo$DEQ = EN_oport_get ; assign fo$CLR = 1'b0 ; // remaining internal signals diff --git a/rtl/mkQABSMF.v b/rtl/mkQABSMF.v index aa063a17..eb476918 100644 --- a/rtl/mkQABSMF.v +++ b/rtl/mkQABSMF.v @@ -1,7 +1,7 @@ // -// Generated by Bluespec Compiler, version 2012.09.beta1 (build 29570, 2012-09.11) +// Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Wed Nov 28 10:31:23 EST 2012 +// On Fri Jun 21 16:56:44 EDT 2013 // // // Ports: @@ -217,100 +217,100 @@ module mkQABSMF(et0, MUX_merge_fi1Active$write_1__VAL_2; // remaining internal signals - reg [7 : 0] IF_frk_ptr_19_EQ_0_37_THEN_frk_sr_23_BITS_17_T_ETC___d703, - IF_frk_ptr_19_EQ_0_37_THEN_frk_sr_23_BITS_27_T_ETC___d702, - IF_frk_ptr_19_EQ_0_37_THEN_frk_sr_23_BITS_37_T_ETC___d701, - IF_frk_ptr_19_EQ_0_37_THEN_frk_sr_23_BITS_7_TO_ETC___d704; - reg [1 : 0] CASE_client0_response_put_BITS_19_TO_18_3_0_cl_ETC__q51, - CASE_client0_response_put_BITS_29_TO_28_3_0_cl_ETC__q50, - CASE_client0_response_put_BITS_39_TO_38_3_0_cl_ETC__q49, - CASE_client0_response_put_BITS_9_TO_8_3_0_clie_ETC__q52, - CASE_client1_response_put_BITS_19_TO_18_3_0_cl_ETC__q55, - CASE_client1_response_put_BITS_29_TO_28_3_0_cl_ETC__q54, - CASE_client1_response_put_BITS_39_TO_38_3_0_cl_ETC__q53, - CASE_client1_response_put_BITS_9_TO_8_3_0_clie_ETC__q56, - CASE_frk_d0FD_OUT_BITS_19_TO_18_3_0_frk_d0FD_ETC__q7, - CASE_frk_d0FD_OUT_BITS_29_TO_28_3_0_frk_d0FD_ETC__q6, - CASE_frk_d0FD_OUT_BITS_39_TO_38_3_0_frk_d0FD_ETC__q5, - CASE_frk_d0FD_OUT_BITS_9_TO_8_3_0_frk_d0FD_O_ETC__q8, - CASE_frk_d1FD_OUT_BITS_19_TO_18_3_0_frk_d1FD_ETC__q3, - CASE_frk_d1FD_OUT_BITS_29_TO_28_3_0_frk_d1FD_ETC__q2, - CASE_frk_d1FD_OUT_BITS_39_TO_38_3_0_frk_d1FD_ETC__q1, - CASE_frk_d1FD_OUT_BITS_9_TO_8_3_0_frk_d1FD_O_ETC__q4, - CASE_frk_sr_BITS_109_TO_108_3_0_frk_sr_BITS_10_ETC__q38, - CASE_frk_sr_BITS_119_TO_118_3_0_frk_sr_BITS_11_ETC__q37, - CASE_frk_sr_BITS_49_TO_48_3_0_frk_sr_BITS_49_T_ETC__q44, - CASE_frk_sr_BITS_59_TO_58_3_0_frk_sr_BITS_59_T_ETC__q43, - CASE_frk_sr_BITS_69_TO_68_3_0_frk_sr_BITS_69_T_ETC__q42, - CASE_frk_sr_BITS_79_TO_78_3_0_frk_sr_BITS_79_T_ETC__q41, - CASE_frk_sr_BITS_89_TO_88_3_0_frk_sr_BITS_89_T_ETC__q40, - CASE_frk_sr_BITS_99_TO_98_3_0_frk_sr_BITS_99_T_ETC__q39, - CASE_frk_srcFD_OUT_BITS_19_TO_18_3_0_frk_srcF_ETC__q27, - CASE_frk_srcFD_OUT_BITS_29_TO_28_3_0_frk_srcF_ETC__q26, - CASE_frk_srcFD_OUT_BITS_39_TO_38_3_0_frk_srcF_ETC__q25, - CASE_frk_srcFD_OUT_BITS_9_TO_8_3_0_frk_srcFD_ETC__q28, - CASE_merge_fi0D_OUT_BITS_19_TO_18_3_0_merge_f_ETC__q31, - CASE_merge_fi0D_OUT_BITS_29_TO_28_3_0_merge_f_ETC__q30, - CASE_merge_fi0D_OUT_BITS_39_TO_38_3_0_merge_f_ETC__q29, - CASE_merge_fi0D_OUT_BITS_9_TO_8_3_0_merge_fi0_ETC__q32, - CASE_merge_fi1D_OUT_BITS_19_TO_18_3_0_merge_f_ETC__q35, - CASE_merge_fi1D_OUT_BITS_29_TO_28_3_0_merge_f_ETC__q34, - CASE_merge_fi1D_OUT_BITS_39_TO_38_3_0_merge_f_ETC__q33, - CASE_merge_fi1D_OUT_BITS_9_TO_8_3_0_merge_fi1_ETC__q36, - CASE_merge_foD_OUT_BITS_19_TO_18_3_0_merge_fo_ETC__q11, - CASE_merge_foD_OUT_BITS_29_TO_28_3_0_merge_fo_ETC__q10, - CASE_merge_foD_OUT_BITS_39_TO_38_3_0_merge_fo_ETC__q9, - CASE_merge_foD_OUT_BITS_9_TO_8_3_0_merge_foD_ETC__q12, - CASE_server_request_put_BITS_19_TO_18_3_0_serv_ETC__q47, - CASE_server_request_put_BITS_29_TO_28_3_0_serv_ETC__q46, - CASE_server_request_put_BITS_39_TO_38_3_0_serv_ETC__q45, - CASE_server_request_put_BITS_9_TO_8_3_0_server_ETC__q48; - reg CASE_frk_ptr_frk_ptr_EQ_2_AND_frk_sr_BITS_109__ETC__q16, - CASE_frk_ptr_frk_ptr_EQ_2_AND_frk_sr_BITS_109__ETC__q17, - CASE_frk_ptr_frk_ptr_EQ_2_AND_frk_sr_BITS_109__ETC__q18, - CASE_frk_ptr_frk_ptr_EQ_2_AND_frk_sr_BITS_119__ETC__q13, - CASE_frk_ptr_frk_ptr_EQ_2_AND_frk_sr_BITS_119__ETC__q14, - CASE_frk_ptr_frk_ptr_EQ_2_AND_frk_sr_BITS_119__ETC__q15, - CASE_frk_ptr_frk_ptr_EQ_2_AND_frk_sr_BITS_89_T_ETC__q22, - CASE_frk_ptr_frk_ptr_EQ_2_AND_frk_sr_BITS_89_T_ETC__q23, - CASE_frk_ptr_frk_ptr_EQ_2_AND_frk_sr_BITS_89_T_ETC__q24, - CASE_frk_ptr_frk_ptr_EQ_2_AND_frk_sr_BITS_99_T_ETC__q19, - CASE_frk_ptr_frk_ptr_EQ_2_AND_frk_sr_BITS_99_T_ETC__q20, - CASE_frk_ptr_frk_ptr_EQ_2_AND_frk_sr_BITS_99_T_ETC__q21; - wire [39 : 0] IF_frk_srcF_first__79_BITS_39_TO_38_80_EQ_0_81_ETC___d705; + reg [7 : 0] SEL_ARR_frk_sr_23_BITS_17_TO_10_80_frk_sr_23_B_ETC___d382, + SEL_ARR_frk_sr_23_BITS_27_TO_20_60_frk_sr_23_B_ETC___d362, + SEL_ARR_frk_sr_23_BITS_37_TO_30_41_frk_sr_23_B_ETC___d343, + SEL_ARR_frk_sr_23_BITS_7_TO_0_99_frk_sr_23_BIT_ETC___d401; + reg [1 : 0] CASE_client0_response_put_BITS_19_TO_18_0_clie_ETC__q51, + CASE_client0_response_put_BITS_29_TO_28_0_clie_ETC__q50, + CASE_client0_response_put_BITS_39_TO_38_0_clie_ETC__q49, + CASE_client0_response_put_BITS_9_TO_8_0_client_ETC__q52, + CASE_client1_response_put_BITS_19_TO_18_0_clie_ETC__q55, + CASE_client1_response_put_BITS_29_TO_28_0_clie_ETC__q54, + CASE_client1_response_put_BITS_39_TO_38_0_clie_ETC__q53, + CASE_client1_response_put_BITS_9_TO_8_0_client_ETC__q56, + CASE_frk_d0FD_OUT_BITS_19_TO_18_0_frk_d0FD_O_ETC__q7, + CASE_frk_d0FD_OUT_BITS_29_TO_28_0_frk_d0FD_O_ETC__q6, + CASE_frk_d0FD_OUT_BITS_39_TO_38_0_frk_d0FD_O_ETC__q5, + CASE_frk_d0FD_OUT_BITS_9_TO_8_0_frk_d0FD_OUT_ETC__q8, + CASE_frk_d1FD_OUT_BITS_19_TO_18_0_frk_d1FD_O_ETC__q3, + CASE_frk_d1FD_OUT_BITS_29_TO_28_0_frk_d1FD_O_ETC__q2, + CASE_frk_d1FD_OUT_BITS_39_TO_38_0_frk_d1FD_O_ETC__q1, + CASE_frk_d1FD_OUT_BITS_9_TO_8_0_frk_d1FD_OUT_ETC__q4, + CASE_frk_sr_BITS_109_TO_108_0_frk_sr_BITS_109__ETC__q38, + CASE_frk_sr_BITS_119_TO_118_0_frk_sr_BITS_119__ETC__q37, + CASE_frk_sr_BITS_49_TO_48_0_frk_sr_BITS_49_TO__ETC__q44, + CASE_frk_sr_BITS_59_TO_58_0_frk_sr_BITS_59_TO__ETC__q43, + CASE_frk_sr_BITS_69_TO_68_0_frk_sr_BITS_69_TO__ETC__q42, + CASE_frk_sr_BITS_79_TO_78_0_frk_sr_BITS_79_TO__ETC__q41, + CASE_frk_sr_BITS_89_TO_88_0_frk_sr_BITS_89_TO__ETC__q40, + CASE_frk_sr_BITS_99_TO_98_0_frk_sr_BITS_99_TO__ETC__q39, + CASE_frk_srcFD_OUT_BITS_19_TO_18_0_frk_srcFD_ETC__q21, + CASE_frk_srcFD_OUT_BITS_29_TO_28_0_frk_srcFD_ETC__q20, + CASE_frk_srcFD_OUT_BITS_39_TO_38_0_frk_srcFD_ETC__q19, + CASE_frk_srcFD_OUT_BITS_9_TO_8_0_frk_srcFD_O_ETC__q22, + CASE_merge_fi0D_OUT_BITS_19_TO_18_0_merge_fi0_ETC__q31, + CASE_merge_fi0D_OUT_BITS_29_TO_28_0_merge_fi0_ETC__q30, + CASE_merge_fi0D_OUT_BITS_39_TO_38_0_merge_fi0_ETC__q29, + CASE_merge_fi0D_OUT_BITS_9_TO_8_0_merge_fi0D_ETC__q32, + CASE_merge_fi1D_OUT_BITS_19_TO_18_0_merge_fi1_ETC__q35, + CASE_merge_fi1D_OUT_BITS_29_TO_28_0_merge_fi1_ETC__q34, + CASE_merge_fi1D_OUT_BITS_39_TO_38_0_merge_fi1_ETC__q33, + CASE_merge_fi1D_OUT_BITS_9_TO_8_0_merge_fi1D_ETC__q36, + CASE_merge_foD_OUT_BITS_19_TO_18_0_merge_foD_ETC__q11, + CASE_merge_foD_OUT_BITS_29_TO_28_0_merge_foD_ETC__q10, + CASE_merge_foD_OUT_BITS_39_TO_38_0_merge_foD_ETC__q9, + CASE_merge_foD_OUT_BITS_9_TO_8_0_merge_foD_O_ETC__q12, + CASE_server_request_put_BITS_19_TO_18_0_server_ETC__q47, + CASE_server_request_put_BITS_29_TO_28_0_server_ETC__q46, + CASE_server_request_put_BITS_39_TO_38_0_server_ETC__q45, + CASE_server_request_put_BITS_9_TO_8_0_server_r_ETC__q48; + reg CASE_frk_ptr_0_frk_sr_BITS_19_TO_18_EQ_0_1_frk_ETC__q25, + CASE_frk_ptr_0_frk_sr_BITS_19_TO_18_EQ_1_1_frk_ETC__q24, + CASE_frk_ptr_0_frk_sr_BITS_19_TO_18_EQ_2_1_frk_ETC__q23, + CASE_frk_ptr_0_frk_sr_BITS_29_TO_28_EQ_0_1_frk_ETC__q18, + CASE_frk_ptr_0_frk_sr_BITS_29_TO_28_EQ_1_1_frk_ETC__q17, + CASE_frk_ptr_0_frk_sr_BITS_29_TO_28_EQ_2_1_frk_ETC__q16, + CASE_frk_ptr_0_frk_sr_BITS_39_TO_38_EQ_0_1_frk_ETC__q15, + CASE_frk_ptr_0_frk_sr_BITS_39_TO_38_EQ_1_1_frk_ETC__q14, + CASE_frk_ptr_0_frk_sr_BITS_39_TO_38_EQ_2_1_frk_ETC__q13, + CASE_frk_ptr_0_frk_sr_BITS_9_TO_8_EQ_0_1_frk_s_ETC__q28, + CASE_frk_ptr_0_frk_sr_BITS_9_TO_8_EQ_1_1_frk_s_ETC__q27, + CASE_frk_ptr_0_frk_sr_BITS_9_TO_8_EQ_2_1_frk_s_ETC__q26; + wire [39 : 0] IF_frk_srcF_first__79_BITS_39_TO_38_80_EQ_0_81_ETC___d222; wire [19 : 0] IF_IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_ETC___d147; - wire [15 : 0] seen__h10720; - wire [9 : 0] IF_IF_frk_ptr_19_EQ_0_37_THEN_frk_sr_23_BITS_1_ETC___d406, - IF_IF_frk_ptr_19_EQ_0_37_THEN_frk_sr_23_BITS_1_ETC___d407, - IF_IF_frk_ptr_19_EQ_0_37_THEN_frk_sr_23_BITS_1_ETC___d408, - IF_IF_frk_ptr_19_EQ_0_37_THEN_frk_sr_23_BITS_2_ETC___d382, - IF_IF_frk_ptr_19_EQ_0_37_THEN_frk_sr_23_BITS_2_ETC___d383, - IF_IF_frk_ptr_19_EQ_0_37_THEN_frk_sr_23_BITS_2_ETC___d384, - IF_IF_frk_ptr_19_EQ_0_37_THEN_frk_sr_23_BITS_3_ETC___d359, - IF_IF_frk_ptr_19_EQ_0_37_THEN_frk_sr_23_BITS_3_ETC___d360, - IF_IF_frk_ptr_19_EQ_0_37_THEN_frk_sr_23_BITS_3_ETC___d361, - IF_IF_frk_ptr_19_EQ_0_37_THEN_frk_sr_23_BITS_9_ETC___d429, - IF_IF_frk_ptr_19_EQ_0_37_THEN_frk_sr_23_BITS_9_ETC___d430, - IF_IF_frk_ptr_19_EQ_0_37_THEN_frk_sr_23_BITS_9_ETC___d431, - IF_IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_ETC___d135, + wire [15 : 0] seen__h10254; + wire [9 : 0] IF_IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_ETC___d135, IF_IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_ETC___d145, IF_IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_ETC___d156, - IF_IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_ETC___d166; - wire [7 : 0] IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d697, - IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d698, - IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d699, - IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d700; - wire [2 : 0] frk_ptr_19_PLUS_1___d760; + IF_IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_ETC___d166, + IF_SEL_ARR_frk_sr_23_BITS_19_TO_18_76_EQ_0_77__ETC___d394, + IF_SEL_ARR_frk_sr_23_BITS_19_TO_18_76_EQ_1_84__ETC___d393, + IF_SEL_ARR_frk_sr_23_BITS_19_TO_18_76_EQ_2_88__ETC___d392, + IF_SEL_ARR_frk_sr_23_BITS_29_TO_28_56_EQ_0_57__ETC___d374, + IF_SEL_ARR_frk_sr_23_BITS_29_TO_28_56_EQ_1_64__ETC___d373, + IF_SEL_ARR_frk_sr_23_BITS_29_TO_28_56_EQ_2_68__ETC___d372, + IF_SEL_ARR_frk_sr_23_BITS_39_TO_38_37_EQ_0_38__ETC___d355, + IF_SEL_ARR_frk_sr_23_BITS_39_TO_38_37_EQ_1_45__ETC___d354, + IF_SEL_ARR_frk_sr_23_BITS_39_TO_38_37_EQ_2_49__ETC___d353, + IF_SEL_ARR_frk_sr_23_BITS_9_TO_8_95_EQ_0_96_fr_ETC___d413, + IF_SEL_ARR_frk_sr_23_BITS_9_TO_8_95_EQ_1_03_fr_ETC___d412, + IF_SEL_ARR_frk_sr_23_BITS_9_TO_8_95_EQ_2_07_fr_ETC___d411; + wire [7 : 0] IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d128, + IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d138, + IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d149, + IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d159; + wire [2 : 0] frk_ptr_19_PLUS_1___d320; wire [1 : 0] IF_IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_ETC___d133, IF_IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_ETC___d143, IF_IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_ETC___d154, IF_IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_ETC___d164; wire IF_merge_fi0HasPrio_06_THEN_NOT_merge_fi0_i_no_ETC___d113, - IF_merge_fi0HasPrio_06_THEN_NOT_merge_fi0_i_no_ETC___d878, - IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d876, - IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d877, - IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d879, - IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d887, + IF_merge_fi0HasPrio_06_THEN_NOT_merge_fi0_i_no_ETC___d115, + IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d127, + IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d137, + IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d148, + IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d158, IF_merge_fi0HasPrio_06_THEN_merge_fi0_i_notEmp_ETC___d118, NOT_frk_stageSent_27_28_OR_frk_srcF_i_notEmpty_ETC___d334; @@ -319,25 +319,25 @@ module mkQABSMF(et0, // actionvalue method server_response_get assign server_response_get = - { CASE_merge_foD_OUT_BITS_39_TO_38_3_0_merge_fo_ETC__q9, + { CASE_merge_foD_OUT_BITS_39_TO_38_0_merge_foD_ETC__q9, merge_fo$D_OUT[37:30], - CASE_merge_foD_OUT_BITS_29_TO_28_3_0_merge_fo_ETC__q10, + CASE_merge_foD_OUT_BITS_29_TO_28_0_merge_foD_ETC__q10, merge_fo$D_OUT[27:20], - CASE_merge_foD_OUT_BITS_19_TO_18_3_0_merge_fo_ETC__q11, + CASE_merge_foD_OUT_BITS_19_TO_18_0_merge_foD_ETC__q11, merge_fo$D_OUT[17:10], - CASE_merge_foD_OUT_BITS_9_TO_8_3_0_merge_foD_ETC__q12, + CASE_merge_foD_OUT_BITS_9_TO_8_0_merge_foD_O_ETC__q12, merge_fo$D_OUT[7:0] } ; assign RDY_server_response_get = merge_fo$EMPTY_N ; // actionvalue method client0_request_get assign client0_request_get = - { CASE_frk_d0FD_OUT_BITS_39_TO_38_3_0_frk_d0FD_ETC__q5, + { CASE_frk_d0FD_OUT_BITS_39_TO_38_0_frk_d0FD_O_ETC__q5, frk_d0F$D_OUT[37:30], - CASE_frk_d0FD_OUT_BITS_29_TO_28_3_0_frk_d0FD_ETC__q6, + CASE_frk_d0FD_OUT_BITS_29_TO_28_0_frk_d0FD_O_ETC__q6, frk_d0F$D_OUT[27:20], - CASE_frk_d0FD_OUT_BITS_19_TO_18_3_0_frk_d0FD_ETC__q7, + CASE_frk_d0FD_OUT_BITS_19_TO_18_0_frk_d0FD_O_ETC__q7, frk_d0F$D_OUT[17:10], - CASE_frk_d0FD_OUT_BITS_9_TO_8_3_0_frk_d0FD_O_ETC__q8, + CASE_frk_d0FD_OUT_BITS_9_TO_8_0_frk_d0FD_OUT_ETC__q8, frk_d0F$D_OUT[7:0] } ; assign RDY_client0_request_get = frk_d0F$EMPTY_N ; @@ -346,13 +346,13 @@ module mkQABSMF(et0, // actionvalue method client1_request_get assign client1_request_get = - { CASE_frk_d1FD_OUT_BITS_39_TO_38_3_0_frk_d1FD_ETC__q1, + { CASE_frk_d1FD_OUT_BITS_39_TO_38_0_frk_d1FD_O_ETC__q1, frk_d1F$D_OUT[37:30], - CASE_frk_d1FD_OUT_BITS_29_TO_28_3_0_frk_d1FD_ETC__q2, + CASE_frk_d1FD_OUT_BITS_29_TO_28_0_frk_d1FD_O_ETC__q2, frk_d1F$D_OUT[27:20], - CASE_frk_d1FD_OUT_BITS_19_TO_18_3_0_frk_d1FD_ETC__q3, + CASE_frk_d1FD_OUT_BITS_19_TO_18_0_frk_d1FD_O_ETC__q3, frk_d1F$D_OUT[17:10], - CASE_frk_d1FD_OUT_BITS_9_TO_8_3_0_frk_d1FD_O_ETC__q4, + CASE_frk_d1FD_OUT_BITS_9_TO_8_0_frk_d1FD_OUT_ETC__q4, frk_d1F$D_OUT[7:0] } ; assign RDY_client1_request_get = frk_d1F$EMPTY_N ; @@ -476,18 +476,18 @@ module mkQABSMF(et0, assign MUX_merge_fi1Active$write_1__SEL_1 = WILL_FIRE_RL_merge_arbitrate && !merge_fi0HasPrio ; assign MUX_frk_ptr$write_1__VAL_1 = - frk_stageSent ? 3'd0 : frk_ptr_19_PLUS_1___d760 ; + frk_stageSent ? 3'd0 : frk_ptr_19_PLUS_1___d320 ; assign MUX_frk_ptr$write_1__VAL_2 = (frk_srcF$D_OUT[9:8] != 2'd0 || frk_srcF$D_OUT[19:18] != 2'd0 || frk_srcF$D_OUT[29:28] != 2'd0 || frk_srcF$D_OUT[39:38] != 2'd0) ? 3'd0 : - frk_ptr_19_PLUS_1___d760 ; + frk_ptr_19_PLUS_1___d320 ; assign MUX_merge_fi0Active$write_1__VAL_1 = - IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d879 && - IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d877 && - IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d876 && - IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d887 ; + IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d158 && + IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d148 && + IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d137 && + IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d127 ; assign MUX_merge_fi0Active$write_1__VAL_2 = merge_fi0$D_OUT[9:8] == 2'd0 && merge_fi0$D_OUT[19:18] == 2'd0 && merge_fi0$D_OUT[29:28] == 2'd0 && @@ -497,32 +497,32 @@ module mkQABSMF(et0, merge_fi1$D_OUT[29:28] == 2'd0 && merge_fi1$D_OUT[39:38] == 2'd0 ; assign MUX_merge_fo$enq_1__VAL_1 = - { CASE_merge_fi0D_OUT_BITS_39_TO_38_3_0_merge_f_ETC__q29, + { CASE_merge_fi0D_OUT_BITS_39_TO_38_0_merge_fi0_ETC__q29, merge_fi0$D_OUT[37:30], - CASE_merge_fi0D_OUT_BITS_29_TO_28_3_0_merge_f_ETC__q30, + CASE_merge_fi0D_OUT_BITS_29_TO_28_0_merge_fi0_ETC__q30, merge_fi0$D_OUT[27:20], - CASE_merge_fi0D_OUT_BITS_19_TO_18_3_0_merge_f_ETC__q31, + CASE_merge_fi0D_OUT_BITS_19_TO_18_0_merge_fi0_ETC__q31, merge_fi0$D_OUT[17:10], - CASE_merge_fi0D_OUT_BITS_9_TO_8_3_0_merge_fi0_ETC__q32, + CASE_merge_fi0D_OUT_BITS_9_TO_8_0_merge_fi0D_ETC__q32, merge_fi0$D_OUT[7:0] } ; assign MUX_merge_fo$enq_1__VAL_2 = - { CASE_merge_fi1D_OUT_BITS_39_TO_38_3_0_merge_f_ETC__q33, + { CASE_merge_fi1D_OUT_BITS_39_TO_38_0_merge_fi1_ETC__q33, merge_fi1$D_OUT[37:30], - CASE_merge_fi1D_OUT_BITS_29_TO_28_3_0_merge_f_ETC__q34, + CASE_merge_fi1D_OUT_BITS_29_TO_28_0_merge_fi1_ETC__q34, merge_fi1$D_OUT[27:20], - CASE_merge_fi1D_OUT_BITS_19_TO_18_3_0_merge_f_ETC__q35, + CASE_merge_fi1D_OUT_BITS_19_TO_18_0_merge_fi1_ETC__q35, merge_fi1$D_OUT[17:10], - CASE_merge_fi1D_OUT_BITS_9_TO_8_3_0_merge_fi1_ETC__q36, + CASE_merge_fi1D_OUT_BITS_9_TO_8_0_merge_fi1D_ETC__q36, merge_fi1$D_OUT[7:0] } ; assign MUX_merge_fo$enq_1__VAL_3 = { IF_IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_ETC___d147, - IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d877 ? + IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d148 ? { 2'd0, - IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d699 } : + IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d149 } : IF_IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_ETC___d156, - IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d879 ? + IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d158 ? { 2'd0, - IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d700 } : + IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d159 } : IF_IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_ETC___d166 } ; // register frk_decided @@ -535,7 +535,7 @@ module mkQABSMF(et0, WILL_FIRE_RL_frk_decide ; // register frk_match0 - assign frk_match0$D_IN = et0 == seen__h10720 ; + assign frk_match0$D_IN = et0 == seen__h10254 ; assign frk_match0$EN = WILL_FIRE_RL_frk_decide ; // register frk_ptr @@ -562,22 +562,22 @@ module mkQABSMF(et0, // register frk_sr assign frk_sr$D_IN = - { IF_frk_srcF_first__79_BITS_39_TO_38_80_EQ_0_81_ETC___d705, - CASE_frk_sr_BITS_119_TO_118_3_0_frk_sr_BITS_11_ETC__q37, + { IF_frk_srcF_first__79_BITS_39_TO_38_80_EQ_0_81_ETC___d222, + CASE_frk_sr_BITS_119_TO_118_0_frk_sr_BITS_119__ETC__q37, frk_sr[117:110], - CASE_frk_sr_BITS_109_TO_108_3_0_frk_sr_BITS_10_ETC__q38, + CASE_frk_sr_BITS_109_TO_108_0_frk_sr_BITS_109__ETC__q38, frk_sr[107:100], - CASE_frk_sr_BITS_99_TO_98_3_0_frk_sr_BITS_99_T_ETC__q39, + CASE_frk_sr_BITS_99_TO_98_0_frk_sr_BITS_99_TO__ETC__q39, frk_sr[97:90], - CASE_frk_sr_BITS_89_TO_88_3_0_frk_sr_BITS_89_T_ETC__q40, + CASE_frk_sr_BITS_89_TO_88_0_frk_sr_BITS_89_TO__ETC__q40, frk_sr[87:80], - CASE_frk_sr_BITS_79_TO_78_3_0_frk_sr_BITS_79_T_ETC__q41, + CASE_frk_sr_BITS_79_TO_78_0_frk_sr_BITS_79_TO__ETC__q41, frk_sr[77:70], - CASE_frk_sr_BITS_69_TO_68_3_0_frk_sr_BITS_69_T_ETC__q42, + CASE_frk_sr_BITS_69_TO_68_0_frk_sr_BITS_69_TO__ETC__q42, frk_sr[67:60], - CASE_frk_sr_BITS_59_TO_58_3_0_frk_sr_BITS_59_T_ETC__q43, + CASE_frk_sr_BITS_59_TO_58_0_frk_sr_BITS_59_TO__ETC__q43, frk_sr[57:50], - CASE_frk_sr_BITS_49_TO_48_3_0_frk_sr_BITS_49_T_ETC__q44, + CASE_frk_sr_BITS_49_TO_48_0_frk_sr_BITS_49_TO__ETC__q44, frk_sr[47:40] } ; assign frk_sr$EN = WILL_FIRE_RL_frk_stage ; @@ -632,11 +632,11 @@ module mkQABSMF(et0, // submodule frk_d0F assign frk_d0F$D_IN = frk_stageSent ? - IF_frk_srcF_first__79_BITS_39_TO_38_80_EQ_0_81_ETC___d705 : - { IF_IF_frk_ptr_19_EQ_0_37_THEN_frk_sr_23_BITS_3_ETC___d361, - IF_IF_frk_ptr_19_EQ_0_37_THEN_frk_sr_23_BITS_2_ETC___d384, - IF_IF_frk_ptr_19_EQ_0_37_THEN_frk_sr_23_BITS_1_ETC___d408, - IF_IF_frk_ptr_19_EQ_0_37_THEN_frk_sr_23_BITS_9_ETC___d431 } ; + IF_frk_srcF_first__79_BITS_39_TO_38_80_EQ_0_81_ETC___d222 : + { IF_SEL_ARR_frk_sr_23_BITS_39_TO_38_37_EQ_0_38__ETC___d355, + IF_SEL_ARR_frk_sr_23_BITS_29_TO_28_56_EQ_0_57__ETC___d374, + IF_SEL_ARR_frk_sr_23_BITS_19_TO_18_76_EQ_0_77__ETC___d394, + IF_SEL_ARR_frk_sr_23_BITS_9_TO_8_95_EQ_0_96_fr_ETC___d413 } ; assign frk_d0F$ENQ = WILL_FIRE_RL_frk_egress && frk_match0 ; assign frk_d0F$DEQ = EN_client0_request_get ; assign frk_d0F$CLR = 1'b0 ; @@ -649,13 +649,13 @@ module mkQABSMF(et0, // submodule frk_srcF assign frk_srcF$D_IN = - { CASE_server_request_put_BITS_39_TO_38_3_0_serv_ETC__q45, + { CASE_server_request_put_BITS_39_TO_38_0_server_ETC__q45, server_request_put[37:30], - CASE_server_request_put_BITS_29_TO_28_3_0_serv_ETC__q46, + CASE_server_request_put_BITS_29_TO_28_0_server_ETC__q46, server_request_put[27:20], - CASE_server_request_put_BITS_19_TO_18_3_0_serv_ETC__q47, + CASE_server_request_put_BITS_19_TO_18_0_server_ETC__q47, server_request_put[17:10], - CASE_server_request_put_BITS_9_TO_8_3_0_server_ETC__q48, + CASE_server_request_put_BITS_9_TO_8_0_server_r_ETC__q48, server_request_put[7:0] } ; assign frk_srcF$ENQ = EN_server_request_put ; assign frk_srcF$DEQ = @@ -665,13 +665,13 @@ module mkQABSMF(et0, // submodule merge_fi0 assign merge_fi0$D_IN = - { CASE_client0_response_put_BITS_39_TO_38_3_0_cl_ETC__q49, + { CASE_client0_response_put_BITS_39_TO_38_0_clie_ETC__q49, client0_response_put[37:30], - CASE_client0_response_put_BITS_29_TO_28_3_0_cl_ETC__q50, + CASE_client0_response_put_BITS_29_TO_28_0_clie_ETC__q50, client0_response_put[27:20], - CASE_client0_response_put_BITS_19_TO_18_3_0_cl_ETC__q51, + CASE_client0_response_put_BITS_19_TO_18_0_clie_ETC__q51, client0_response_put[17:10], - CASE_client0_response_put_BITS_9_TO_8_3_0_clie_ETC__q52, + CASE_client0_response_put_BITS_9_TO_8_0_client_ETC__q52, client0_response_put[7:0] } ; assign merge_fi0$ENQ = EN_client0_response_put ; assign merge_fi0$DEQ = @@ -681,13 +681,13 @@ module mkQABSMF(et0, // submodule merge_fi1 assign merge_fi1$D_IN = - { CASE_client1_response_put_BITS_39_TO_38_3_0_cl_ETC__q53, + { CASE_client1_response_put_BITS_39_TO_38_0_clie_ETC__q53, client1_response_put[37:30], - CASE_client1_response_put_BITS_29_TO_28_3_0_cl_ETC__q54, + CASE_client1_response_put_BITS_29_TO_28_0_clie_ETC__q54, client1_response_put[27:20], - CASE_client1_response_put_BITS_19_TO_18_3_0_cl_ETC__q55, + CASE_client1_response_put_BITS_19_TO_18_0_clie_ETC__q55, client1_response_put[17:10], - CASE_client1_response_put_BITS_9_TO_8_3_0_clie_ETC__q56, + CASE_client1_response_put_BITS_9_TO_8_0_client_ETC__q56, client1_response_put[7:0] } ; assign merge_fi1$ENQ = EN_client1_response_put ; assign merge_fi1$DEQ = @@ -719,66 +719,6 @@ module mkQABSMF(et0, assign merge_fo$CLR = 1'b0 ; // remaining internal signals - assign IF_IF_frk_ptr_19_EQ_0_37_THEN_frk_sr_23_BITS_1_ETC___d406 = - { CASE_frk_ptr_frk_ptr_EQ_2_AND_frk_sr_BITS_99_T_ETC__q19 ? - 2'd2 : - 2'd3, - IF_frk_ptr_19_EQ_0_37_THEN_frk_sr_23_BITS_17_T_ETC___d703 } ; - assign IF_IF_frk_ptr_19_EQ_0_37_THEN_frk_sr_23_BITS_1_ETC___d407 = - CASE_frk_ptr_frk_ptr_EQ_2_AND_frk_sr_BITS_99_T_ETC__q20 ? - { 2'd1, - IF_frk_ptr_19_EQ_0_37_THEN_frk_sr_23_BITS_17_T_ETC___d703 } : - IF_IF_frk_ptr_19_EQ_0_37_THEN_frk_sr_23_BITS_1_ETC___d406 ; - assign IF_IF_frk_ptr_19_EQ_0_37_THEN_frk_sr_23_BITS_1_ETC___d408 = - CASE_frk_ptr_frk_ptr_EQ_2_AND_frk_sr_BITS_99_T_ETC__q21 ? - { 2'd0, - IF_frk_ptr_19_EQ_0_37_THEN_frk_sr_23_BITS_17_T_ETC___d703 } : - IF_IF_frk_ptr_19_EQ_0_37_THEN_frk_sr_23_BITS_1_ETC___d407 ; - assign IF_IF_frk_ptr_19_EQ_0_37_THEN_frk_sr_23_BITS_2_ETC___d382 = - { CASE_frk_ptr_frk_ptr_EQ_2_AND_frk_sr_BITS_109__ETC__q16 ? - 2'd2 : - 2'd3, - IF_frk_ptr_19_EQ_0_37_THEN_frk_sr_23_BITS_27_T_ETC___d702 } ; - assign IF_IF_frk_ptr_19_EQ_0_37_THEN_frk_sr_23_BITS_2_ETC___d383 = - CASE_frk_ptr_frk_ptr_EQ_2_AND_frk_sr_BITS_109__ETC__q17 ? - { 2'd1, - IF_frk_ptr_19_EQ_0_37_THEN_frk_sr_23_BITS_27_T_ETC___d702 } : - IF_IF_frk_ptr_19_EQ_0_37_THEN_frk_sr_23_BITS_2_ETC___d382 ; - assign IF_IF_frk_ptr_19_EQ_0_37_THEN_frk_sr_23_BITS_2_ETC___d384 = - CASE_frk_ptr_frk_ptr_EQ_2_AND_frk_sr_BITS_109__ETC__q18 ? - { 2'd0, - IF_frk_ptr_19_EQ_0_37_THEN_frk_sr_23_BITS_27_T_ETC___d702 } : - IF_IF_frk_ptr_19_EQ_0_37_THEN_frk_sr_23_BITS_2_ETC___d383 ; - assign IF_IF_frk_ptr_19_EQ_0_37_THEN_frk_sr_23_BITS_3_ETC___d359 = - { CASE_frk_ptr_frk_ptr_EQ_2_AND_frk_sr_BITS_119__ETC__q13 ? - 2'd2 : - 2'd3, - IF_frk_ptr_19_EQ_0_37_THEN_frk_sr_23_BITS_37_T_ETC___d701 } ; - assign IF_IF_frk_ptr_19_EQ_0_37_THEN_frk_sr_23_BITS_3_ETC___d360 = - CASE_frk_ptr_frk_ptr_EQ_2_AND_frk_sr_BITS_119__ETC__q14 ? - { 2'd1, - IF_frk_ptr_19_EQ_0_37_THEN_frk_sr_23_BITS_37_T_ETC___d701 } : - IF_IF_frk_ptr_19_EQ_0_37_THEN_frk_sr_23_BITS_3_ETC___d359 ; - assign IF_IF_frk_ptr_19_EQ_0_37_THEN_frk_sr_23_BITS_3_ETC___d361 = - CASE_frk_ptr_frk_ptr_EQ_2_AND_frk_sr_BITS_119__ETC__q15 ? - { 2'd0, - IF_frk_ptr_19_EQ_0_37_THEN_frk_sr_23_BITS_37_T_ETC___d701 } : - IF_IF_frk_ptr_19_EQ_0_37_THEN_frk_sr_23_BITS_3_ETC___d360 ; - assign IF_IF_frk_ptr_19_EQ_0_37_THEN_frk_sr_23_BITS_9_ETC___d429 = - { CASE_frk_ptr_frk_ptr_EQ_2_AND_frk_sr_BITS_89_T_ETC__q22 ? - 2'd2 : - 2'd3, - IF_frk_ptr_19_EQ_0_37_THEN_frk_sr_23_BITS_7_TO_ETC___d704 } ; - assign IF_IF_frk_ptr_19_EQ_0_37_THEN_frk_sr_23_BITS_9_ETC___d430 = - CASE_frk_ptr_frk_ptr_EQ_2_AND_frk_sr_BITS_89_T_ETC__q23 ? - { 2'd1, - IF_frk_ptr_19_EQ_0_37_THEN_frk_sr_23_BITS_7_TO_ETC___d704 } : - IF_IF_frk_ptr_19_EQ_0_37_THEN_frk_sr_23_BITS_9_ETC___d429 ; - assign IF_IF_frk_ptr_19_EQ_0_37_THEN_frk_sr_23_BITS_9_ETC___d431 = - CASE_frk_ptr_frk_ptr_EQ_2_AND_frk_sr_BITS_89_T_ETC__q24 ? - { 2'd0, - IF_frk_ptr_19_EQ_0_37_THEN_frk_sr_23_BITS_7_TO_ETC___d704 } : - IF_IF_frk_ptr_19_EQ_0_37_THEN_frk_sr_23_BITS_9_ETC___d430 ; assign IF_IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_ETC___d133 = (merge_fi0HasPrio ? merge_fi0$D_OUT[39:38] == 2'd2 : @@ -790,9 +730,9 @@ module mkQABSMF(et0, merge_fi0$D_OUT[39:38] == 2'd1 : merge_fi1$D_OUT[39:38] == 2'd1) ? { 2'd1, - IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d697 } : + IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d128 } : { IF_IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_ETC___d133, - IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d697 } ; + IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d128 } ; assign IF_IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_ETC___d143 = (merge_fi0HasPrio ? merge_fi0$D_OUT[29:28] == 2'd2 : @@ -804,17 +744,17 @@ module mkQABSMF(et0, merge_fi0$D_OUT[29:28] == 2'd1 : merge_fi1$D_OUT[29:28] == 2'd1) ? { 2'd1, - IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d698 } : + IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d138 } : { IF_IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_ETC___d143, - IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d698 } ; + IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d138 } ; assign IF_IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_ETC___d147 = - { IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d887 ? + { IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d127 ? { 2'd0, - IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d697 } : + IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d128 } : IF_IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_ETC___d135, - IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d876 ? + IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d137 ? { 2'd0, - IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d698 } : + IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d138 } : IF_IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_ETC___d145 } ; assign IF_IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_ETC___d154 = (merge_fi0HasPrio ? @@ -827,9 +767,9 @@ module mkQABSMF(et0, merge_fi0$D_OUT[19:18] == 2'd1 : merge_fi1$D_OUT[19:18] == 2'd1) ? { 2'd1, - IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d699 } : + IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d149 } : { IF_IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_ETC___d154, - IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d699 } ; + IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d149 } ; assign IF_IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_ETC___d164 = (merge_fi0HasPrio ? merge_fi0$D_OUT[9:8] == 2'd2 : @@ -841,668 +781,776 @@ module mkQABSMF(et0, merge_fi0$D_OUT[9:8] == 2'd1 : merge_fi1$D_OUT[9:8] == 2'd1) ? { 2'd1, - IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d700 } : + IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d159 } : { IF_IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_ETC___d164, - IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d700 } ; - assign IF_frk_srcF_first__79_BITS_39_TO_38_80_EQ_0_81_ETC___d705 = - { CASE_frk_srcFD_OUT_BITS_39_TO_38_3_0_frk_srcF_ETC__q25, + IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d159 } ; + assign IF_SEL_ARR_frk_sr_23_BITS_19_TO_18_76_EQ_0_77__ETC___d394 = + CASE_frk_ptr_0_frk_sr_BITS_19_TO_18_EQ_0_1_frk_ETC__q25 ? + { 2'd0, + SEL_ARR_frk_sr_23_BITS_17_TO_10_80_frk_sr_23_B_ETC___d382 } : + IF_SEL_ARR_frk_sr_23_BITS_19_TO_18_76_EQ_1_84__ETC___d393 ; + assign IF_SEL_ARR_frk_sr_23_BITS_19_TO_18_76_EQ_1_84__ETC___d393 = + CASE_frk_ptr_0_frk_sr_BITS_19_TO_18_EQ_1_1_frk_ETC__q24 ? + { 2'd1, + SEL_ARR_frk_sr_23_BITS_17_TO_10_80_frk_sr_23_B_ETC___d382 } : + IF_SEL_ARR_frk_sr_23_BITS_19_TO_18_76_EQ_2_88__ETC___d392 ; + assign IF_SEL_ARR_frk_sr_23_BITS_19_TO_18_76_EQ_2_88__ETC___d392 = + { CASE_frk_ptr_0_frk_sr_BITS_19_TO_18_EQ_2_1_frk_ETC__q23 ? + 2'd2 : + 2'd3, + SEL_ARR_frk_sr_23_BITS_17_TO_10_80_frk_sr_23_B_ETC___d382 } ; + assign IF_SEL_ARR_frk_sr_23_BITS_29_TO_28_56_EQ_0_57__ETC___d374 = + CASE_frk_ptr_0_frk_sr_BITS_29_TO_28_EQ_0_1_frk_ETC__q18 ? + { 2'd0, + SEL_ARR_frk_sr_23_BITS_27_TO_20_60_frk_sr_23_B_ETC___d362 } : + IF_SEL_ARR_frk_sr_23_BITS_29_TO_28_56_EQ_1_64__ETC___d373 ; + assign IF_SEL_ARR_frk_sr_23_BITS_29_TO_28_56_EQ_1_64__ETC___d373 = + CASE_frk_ptr_0_frk_sr_BITS_29_TO_28_EQ_1_1_frk_ETC__q17 ? + { 2'd1, + SEL_ARR_frk_sr_23_BITS_27_TO_20_60_frk_sr_23_B_ETC___d362 } : + IF_SEL_ARR_frk_sr_23_BITS_29_TO_28_56_EQ_2_68__ETC___d372 ; + assign IF_SEL_ARR_frk_sr_23_BITS_29_TO_28_56_EQ_2_68__ETC___d372 = + { CASE_frk_ptr_0_frk_sr_BITS_29_TO_28_EQ_2_1_frk_ETC__q16 ? + 2'd2 : + 2'd3, + SEL_ARR_frk_sr_23_BITS_27_TO_20_60_frk_sr_23_B_ETC___d362 } ; + assign IF_SEL_ARR_frk_sr_23_BITS_39_TO_38_37_EQ_0_38__ETC___d355 = + CASE_frk_ptr_0_frk_sr_BITS_39_TO_38_EQ_0_1_frk_ETC__q15 ? + { 2'd0, + SEL_ARR_frk_sr_23_BITS_37_TO_30_41_frk_sr_23_B_ETC___d343 } : + IF_SEL_ARR_frk_sr_23_BITS_39_TO_38_37_EQ_1_45__ETC___d354 ; + assign IF_SEL_ARR_frk_sr_23_BITS_39_TO_38_37_EQ_1_45__ETC___d354 = + CASE_frk_ptr_0_frk_sr_BITS_39_TO_38_EQ_1_1_frk_ETC__q14 ? + { 2'd1, + SEL_ARR_frk_sr_23_BITS_37_TO_30_41_frk_sr_23_B_ETC___d343 } : + IF_SEL_ARR_frk_sr_23_BITS_39_TO_38_37_EQ_2_49__ETC___d353 ; + assign IF_SEL_ARR_frk_sr_23_BITS_39_TO_38_37_EQ_2_49__ETC___d353 = + { CASE_frk_ptr_0_frk_sr_BITS_39_TO_38_EQ_2_1_frk_ETC__q13 ? + 2'd2 : + 2'd3, + SEL_ARR_frk_sr_23_BITS_37_TO_30_41_frk_sr_23_B_ETC___d343 } ; + assign IF_SEL_ARR_frk_sr_23_BITS_9_TO_8_95_EQ_0_96_fr_ETC___d413 = + CASE_frk_ptr_0_frk_sr_BITS_9_TO_8_EQ_0_1_frk_s_ETC__q28 ? + { 2'd0, + SEL_ARR_frk_sr_23_BITS_7_TO_0_99_frk_sr_23_BIT_ETC___d401 } : + IF_SEL_ARR_frk_sr_23_BITS_9_TO_8_95_EQ_1_03_fr_ETC___d412 ; + assign IF_SEL_ARR_frk_sr_23_BITS_9_TO_8_95_EQ_1_03_fr_ETC___d412 = + CASE_frk_ptr_0_frk_sr_BITS_9_TO_8_EQ_1_1_frk_s_ETC__q27 ? + { 2'd1, + SEL_ARR_frk_sr_23_BITS_7_TO_0_99_frk_sr_23_BIT_ETC___d401 } : + IF_SEL_ARR_frk_sr_23_BITS_9_TO_8_95_EQ_2_07_fr_ETC___d411 ; + assign IF_SEL_ARR_frk_sr_23_BITS_9_TO_8_95_EQ_2_07_fr_ETC___d411 = + { CASE_frk_ptr_0_frk_sr_BITS_9_TO_8_EQ_2_1_frk_s_ETC__q26 ? + 2'd2 : + 2'd3, + SEL_ARR_frk_sr_23_BITS_7_TO_0_99_frk_sr_23_BIT_ETC___d401 } ; + assign IF_frk_srcF_first__79_BITS_39_TO_38_80_EQ_0_81_ETC___d222 = + { CASE_frk_srcFD_OUT_BITS_39_TO_38_0_frk_srcFD_ETC__q19, frk_srcF$D_OUT[37:30], - CASE_frk_srcFD_OUT_BITS_29_TO_28_3_0_frk_srcF_ETC__q26, + CASE_frk_srcFD_OUT_BITS_29_TO_28_0_frk_srcFD_ETC__q20, frk_srcF$D_OUT[27:20], - CASE_frk_srcFD_OUT_BITS_19_TO_18_3_0_frk_srcF_ETC__q27, + CASE_frk_srcFD_OUT_BITS_19_TO_18_0_frk_srcFD_ETC__q21, frk_srcF$D_OUT[17:10], - CASE_frk_srcFD_OUT_BITS_9_TO_8_3_0_frk_srcFD_ETC__q28, + CASE_frk_srcFD_OUT_BITS_9_TO_8_0_frk_srcFD_O_ETC__q22, frk_srcF$D_OUT[7:0] } ; assign IF_merge_fi0HasPrio_06_THEN_NOT_merge_fi0_i_no_ETC___d113 = merge_fi0HasPrio ? !merge_fi0$EMPTY_N || merge_fi0$D_OUT[9:8] != 2'd0 : !merge_fi1$EMPTY_N || merge_fi1$D_OUT[9:8] != 2'd0 ; - assign IF_merge_fi0HasPrio_06_THEN_NOT_merge_fi0_i_no_ETC___d878 = + assign IF_merge_fi0HasPrio_06_THEN_NOT_merge_fi0_i_no_ETC___d115 = IF_merge_fi0HasPrio_06_THEN_NOT_merge_fi0_i_no_ETC___d113 || (merge_fi0HasPrio ? merge_fi0$EMPTY_N : merge_fi1$EMPTY_N) ; - assign IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d697 = + assign IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d127 = + merge_fi0HasPrio ? + merge_fi0$D_OUT[39:38] == 2'd0 : + merge_fi1$D_OUT[39:38] == 2'd0 ; + assign IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d128 = merge_fi0HasPrio ? merge_fi0$D_OUT[37:30] : merge_fi1$D_OUT[37:30] ; - assign IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d698 = - merge_fi0HasPrio ? - merge_fi0$D_OUT[27:20] : - merge_fi1$D_OUT[27:20] ; - assign IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d699 = - merge_fi0HasPrio ? - merge_fi0$D_OUT[17:10] : - merge_fi1$D_OUT[17:10] ; - assign IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d700 = - merge_fi0HasPrio ? merge_fi0$D_OUT[7:0] : merge_fi1$D_OUT[7:0] ; - assign IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d876 = + assign IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d137 = merge_fi0HasPrio ? merge_fi0$D_OUT[29:28] == 2'd0 : merge_fi1$D_OUT[29:28] == 2'd0 ; - assign IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d877 = + assign IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d138 = + merge_fi0HasPrio ? + merge_fi0$D_OUT[27:20] : + merge_fi1$D_OUT[27:20] ; + assign IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d148 = merge_fi0HasPrio ? merge_fi0$D_OUT[19:18] == 2'd0 : merge_fi1$D_OUT[19:18] == 2'd0 ; - assign IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d879 = + assign IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d149 = + merge_fi0HasPrio ? + merge_fi0$D_OUT[17:10] : + merge_fi1$D_OUT[17:10] ; + assign IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d158 = merge_fi0HasPrio ? merge_fi0$D_OUT[9:8] == 2'd0 : merge_fi1$D_OUT[9:8] == 2'd0 ; - assign IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d887 = - merge_fi0HasPrio ? - merge_fi0$D_OUT[39:38] == 2'd0 : - merge_fi1$D_OUT[39:38] == 2'd0 ; + assign IF_merge_fi0HasPrio_06_THEN_merge_fi0_first_BI_ETC___d159 = + merge_fi0HasPrio ? merge_fi0$D_OUT[7:0] : merge_fi1$D_OUT[7:0] ; assign IF_merge_fi0HasPrio_06_THEN_merge_fi0_i_notEmp_ETC___d118 = merge_fi0HasPrio ? merge_fi0$EMPTY_N && - IF_merge_fi0HasPrio_06_THEN_NOT_merge_fi0_i_no_ETC___d878 : + IF_merge_fi0HasPrio_06_THEN_NOT_merge_fi0_i_no_ETC___d115 : merge_fi1$EMPTY_N && - IF_merge_fi0HasPrio_06_THEN_NOT_merge_fi0_i_no_ETC___d878 ; + IF_merge_fi0HasPrio_06_THEN_NOT_merge_fi0_i_no_ETC___d115 ; assign NOT_frk_stageSent_27_28_OR_frk_srcF_i_notEmpty_ETC___d334 = (!frk_stageSent || frk_srcF$EMPTY_N) && (frk_match0 ? frk_d0F$FULL_N : frk_d1F$FULL_N) ; - assign frk_ptr_19_PLUS_1___d760 = frk_ptr + 3'd1 ; - assign seen__h10720 = { frk_srcF$D_OUT[7:0], frk_srcF$D_OUT[17:10] } ; + assign frk_ptr_19_PLUS_1___d320 = frk_ptr + 3'd1 ; + assign seen__h10254 = { frk_srcF$D_OUT[7:0], frk_srcF$D_OUT[17:10] } ; always@(frk_d1F$D_OUT) begin case (frk_d1F$D_OUT[39:38]) 2'd0, 2'd1, 2'd2: - CASE_frk_d1FD_OUT_BITS_39_TO_38_3_0_frk_d1FD_ETC__q1 = + CASE_frk_d1FD_OUT_BITS_39_TO_38_0_frk_d1FD_O_ETC__q1 = frk_d1F$D_OUT[39:38]; - 2'd3: CASE_frk_d1FD_OUT_BITS_39_TO_38_3_0_frk_d1FD_ETC__q1 = 2'd3; + 2'd3: CASE_frk_d1FD_OUT_BITS_39_TO_38_0_frk_d1FD_O_ETC__q1 = 2'd3; endcase end always@(frk_d1F$D_OUT) begin case (frk_d1F$D_OUT[29:28]) 2'd0, 2'd1, 2'd2: - CASE_frk_d1FD_OUT_BITS_29_TO_28_3_0_frk_d1FD_ETC__q2 = + CASE_frk_d1FD_OUT_BITS_29_TO_28_0_frk_d1FD_O_ETC__q2 = frk_d1F$D_OUT[29:28]; - 2'd3: CASE_frk_d1FD_OUT_BITS_29_TO_28_3_0_frk_d1FD_ETC__q2 = 2'd3; + 2'd3: CASE_frk_d1FD_OUT_BITS_29_TO_28_0_frk_d1FD_O_ETC__q2 = 2'd3; endcase end always@(frk_d1F$D_OUT) begin case (frk_d1F$D_OUT[19:18]) 2'd0, 2'd1, 2'd2: - CASE_frk_d1FD_OUT_BITS_19_TO_18_3_0_frk_d1FD_ETC__q3 = + CASE_frk_d1FD_OUT_BITS_19_TO_18_0_frk_d1FD_O_ETC__q3 = frk_d1F$D_OUT[19:18]; - 2'd3: CASE_frk_d1FD_OUT_BITS_19_TO_18_3_0_frk_d1FD_ETC__q3 = 2'd3; + 2'd3: CASE_frk_d1FD_OUT_BITS_19_TO_18_0_frk_d1FD_O_ETC__q3 = 2'd3; endcase end always@(frk_d1F$D_OUT) begin case (frk_d1F$D_OUT[9:8]) 2'd0, 2'd1, 2'd2: - CASE_frk_d1FD_OUT_BITS_9_TO_8_3_0_frk_d1FD_O_ETC__q4 = + CASE_frk_d1FD_OUT_BITS_9_TO_8_0_frk_d1FD_OUT_ETC__q4 = frk_d1F$D_OUT[9:8]; - 2'd3: CASE_frk_d1FD_OUT_BITS_9_TO_8_3_0_frk_d1FD_O_ETC__q4 = 2'd3; + 2'd3: CASE_frk_d1FD_OUT_BITS_9_TO_8_0_frk_d1FD_OUT_ETC__q4 = 2'd3; endcase end always@(frk_d0F$D_OUT) begin case (frk_d0F$D_OUT[39:38]) 2'd0, 2'd1, 2'd2: - CASE_frk_d0FD_OUT_BITS_39_TO_38_3_0_frk_d0FD_ETC__q5 = + CASE_frk_d0FD_OUT_BITS_39_TO_38_0_frk_d0FD_O_ETC__q5 = frk_d0F$D_OUT[39:38]; - 2'd3: CASE_frk_d0FD_OUT_BITS_39_TO_38_3_0_frk_d0FD_ETC__q5 = 2'd3; + 2'd3: CASE_frk_d0FD_OUT_BITS_39_TO_38_0_frk_d0FD_O_ETC__q5 = 2'd3; endcase end always@(frk_d0F$D_OUT) begin case (frk_d0F$D_OUT[29:28]) 2'd0, 2'd1, 2'd2: - CASE_frk_d0FD_OUT_BITS_29_TO_28_3_0_frk_d0FD_ETC__q6 = + CASE_frk_d0FD_OUT_BITS_29_TO_28_0_frk_d0FD_O_ETC__q6 = frk_d0F$D_OUT[29:28]; - 2'd3: CASE_frk_d0FD_OUT_BITS_29_TO_28_3_0_frk_d0FD_ETC__q6 = 2'd3; + 2'd3: CASE_frk_d0FD_OUT_BITS_29_TO_28_0_frk_d0FD_O_ETC__q6 = 2'd3; endcase end always@(frk_d0F$D_OUT) begin case (frk_d0F$D_OUT[19:18]) 2'd0, 2'd1, 2'd2: - CASE_frk_d0FD_OUT_BITS_19_TO_18_3_0_frk_d0FD_ETC__q7 = + CASE_frk_d0FD_OUT_BITS_19_TO_18_0_frk_d0FD_O_ETC__q7 = frk_d0F$D_OUT[19:18]; - 2'd3: CASE_frk_d0FD_OUT_BITS_19_TO_18_3_0_frk_d0FD_ETC__q7 = 2'd3; + 2'd3: CASE_frk_d0FD_OUT_BITS_19_TO_18_0_frk_d0FD_O_ETC__q7 = 2'd3; endcase end always@(frk_d0F$D_OUT) begin case (frk_d0F$D_OUT[9:8]) 2'd0, 2'd1, 2'd2: - CASE_frk_d0FD_OUT_BITS_9_TO_8_3_0_frk_d0FD_O_ETC__q8 = + CASE_frk_d0FD_OUT_BITS_9_TO_8_0_frk_d0FD_OUT_ETC__q8 = frk_d0F$D_OUT[9:8]; - 2'd3: CASE_frk_d0FD_OUT_BITS_9_TO_8_3_0_frk_d0FD_O_ETC__q8 = 2'd3; + 2'd3: CASE_frk_d0FD_OUT_BITS_9_TO_8_0_frk_d0FD_OUT_ETC__q8 = 2'd3; endcase end always@(merge_fo$D_OUT) begin case (merge_fo$D_OUT[39:38]) 2'd0, 2'd1, 2'd2: - CASE_merge_foD_OUT_BITS_39_TO_38_3_0_merge_fo_ETC__q9 = + CASE_merge_foD_OUT_BITS_39_TO_38_0_merge_foD_ETC__q9 = merge_fo$D_OUT[39:38]; - 2'd3: CASE_merge_foD_OUT_BITS_39_TO_38_3_0_merge_fo_ETC__q9 = 2'd3; + 2'd3: CASE_merge_foD_OUT_BITS_39_TO_38_0_merge_foD_ETC__q9 = 2'd3; endcase end always@(merge_fo$D_OUT) begin case (merge_fo$D_OUT[29:28]) 2'd0, 2'd1, 2'd2: - CASE_merge_foD_OUT_BITS_29_TO_28_3_0_merge_fo_ETC__q10 = + CASE_merge_foD_OUT_BITS_29_TO_28_0_merge_foD_ETC__q10 = merge_fo$D_OUT[29:28]; - 2'd3: CASE_merge_foD_OUT_BITS_29_TO_28_3_0_merge_fo_ETC__q10 = 2'd3; + 2'd3: CASE_merge_foD_OUT_BITS_29_TO_28_0_merge_foD_ETC__q10 = 2'd3; endcase end always@(merge_fo$D_OUT) begin case (merge_fo$D_OUT[19:18]) 2'd0, 2'd1, 2'd2: - CASE_merge_foD_OUT_BITS_19_TO_18_3_0_merge_fo_ETC__q11 = + CASE_merge_foD_OUT_BITS_19_TO_18_0_merge_foD_ETC__q11 = merge_fo$D_OUT[19:18]; - 2'd3: CASE_merge_foD_OUT_BITS_19_TO_18_3_0_merge_fo_ETC__q11 = 2'd3; + 2'd3: CASE_merge_foD_OUT_BITS_19_TO_18_0_merge_foD_ETC__q11 = 2'd3; endcase end always@(merge_fo$D_OUT) begin case (merge_fo$D_OUT[9:8]) 2'd0, 2'd1, 2'd2: - CASE_merge_foD_OUT_BITS_9_TO_8_3_0_merge_foD_ETC__q12 = + CASE_merge_foD_OUT_BITS_9_TO_8_0_merge_foD_O_ETC__q12 = merge_fo$D_OUT[9:8]; - 2'd3: CASE_merge_foD_OUT_BITS_9_TO_8_3_0_merge_foD_ETC__q12 = 2'd3; + 2'd3: CASE_merge_foD_OUT_BITS_9_TO_8_0_merge_foD_O_ETC__q12 = 2'd3; endcase end always@(frk_ptr or frk_sr) begin case (frk_ptr) 3'd0: - IF_frk_ptr_19_EQ_0_37_THEN_frk_sr_23_BITS_37_T_ETC___d701 = + SEL_ARR_frk_sr_23_BITS_27_TO_20_60_frk_sr_23_B_ETC___d362 = + frk_sr[27:20]; + 3'd1: + SEL_ARR_frk_sr_23_BITS_27_TO_20_60_frk_sr_23_B_ETC___d362 = + frk_sr[67:60]; + 3'd2: + SEL_ARR_frk_sr_23_BITS_27_TO_20_60_frk_sr_23_B_ETC___d362 = + frk_sr[107:100]; + default: SEL_ARR_frk_sr_23_BITS_27_TO_20_60_frk_sr_23_B_ETC___d362 = + 8'b10101010 /* unspecified value */ ; + endcase + end + always@(frk_ptr or frk_sr) + begin + case (frk_ptr) + 3'd0: + SEL_ARR_frk_sr_23_BITS_37_TO_30_41_frk_sr_23_B_ETC___d343 = frk_sr[37:30]; 3'd1: - IF_frk_ptr_19_EQ_0_37_THEN_frk_sr_23_BITS_37_T_ETC___d701 = + SEL_ARR_frk_sr_23_BITS_37_TO_30_41_frk_sr_23_B_ETC___d343 = frk_sr[77:70]; - default: IF_frk_ptr_19_EQ_0_37_THEN_frk_sr_23_BITS_37_T_ETC___d701 = - frk_sr[117:110]; + 3'd2: + SEL_ARR_frk_sr_23_BITS_37_TO_30_41_frk_sr_23_B_ETC___d343 = + frk_sr[117:110]; + default: SEL_ARR_frk_sr_23_BITS_37_TO_30_41_frk_sr_23_B_ETC___d343 = + 8'b10101010 /* unspecified value */ ; endcase end always@(frk_ptr or frk_sr) begin case (frk_ptr) 3'd0: - CASE_frk_ptr_frk_ptr_EQ_2_AND_frk_sr_BITS_119__ETC__q13 = + CASE_frk_ptr_0_frk_sr_BITS_39_TO_38_EQ_2_1_frk_ETC__q13 = frk_sr[39:38] == 2'd2; 3'd1: - CASE_frk_ptr_frk_ptr_EQ_2_AND_frk_sr_BITS_119__ETC__q13 = + CASE_frk_ptr_0_frk_sr_BITS_39_TO_38_EQ_2_1_frk_ETC__q13 = frk_sr[79:78] == 2'd2; - default: CASE_frk_ptr_frk_ptr_EQ_2_AND_frk_sr_BITS_119__ETC__q13 = - frk_ptr == 3'd2 && frk_sr[119:118] == 2'd2; + 3'd2: + CASE_frk_ptr_0_frk_sr_BITS_39_TO_38_EQ_2_1_frk_ETC__q13 = + frk_sr[119:118] == 2'd2; + default: CASE_frk_ptr_0_frk_sr_BITS_39_TO_38_EQ_2_1_frk_ETC__q13 = + 1'b0 /* unspecified value */ ; endcase end always@(frk_ptr or frk_sr) begin case (frk_ptr) 3'd0: - CASE_frk_ptr_frk_ptr_EQ_2_AND_frk_sr_BITS_119__ETC__q14 = + CASE_frk_ptr_0_frk_sr_BITS_39_TO_38_EQ_1_1_frk_ETC__q14 = frk_sr[39:38] == 2'd1; 3'd1: - CASE_frk_ptr_frk_ptr_EQ_2_AND_frk_sr_BITS_119__ETC__q14 = + CASE_frk_ptr_0_frk_sr_BITS_39_TO_38_EQ_1_1_frk_ETC__q14 = frk_sr[79:78] == 2'd1; - default: CASE_frk_ptr_frk_ptr_EQ_2_AND_frk_sr_BITS_119__ETC__q14 = - frk_ptr == 3'd2 && frk_sr[119:118] == 2'd1; + 3'd2: + CASE_frk_ptr_0_frk_sr_BITS_39_TO_38_EQ_1_1_frk_ETC__q14 = + frk_sr[119:118] == 2'd1; + default: CASE_frk_ptr_0_frk_sr_BITS_39_TO_38_EQ_1_1_frk_ETC__q14 = + 1'b0 /* unspecified value */ ; endcase end always@(frk_ptr or frk_sr) begin case (frk_ptr) 3'd0: - CASE_frk_ptr_frk_ptr_EQ_2_AND_frk_sr_BITS_119__ETC__q15 = + CASE_frk_ptr_0_frk_sr_BITS_39_TO_38_EQ_0_1_frk_ETC__q15 = frk_sr[39:38] == 2'd0; 3'd1: - CASE_frk_ptr_frk_ptr_EQ_2_AND_frk_sr_BITS_119__ETC__q15 = + CASE_frk_ptr_0_frk_sr_BITS_39_TO_38_EQ_0_1_frk_ETC__q15 = frk_sr[79:78] == 2'd0; - default: CASE_frk_ptr_frk_ptr_EQ_2_AND_frk_sr_BITS_119__ETC__q15 = - frk_ptr == 3'd2 && frk_sr[119:118] == 2'd0; + 3'd2: + CASE_frk_ptr_0_frk_sr_BITS_39_TO_38_EQ_0_1_frk_ETC__q15 = + frk_sr[119:118] == 2'd0; + default: CASE_frk_ptr_0_frk_sr_BITS_39_TO_38_EQ_0_1_frk_ETC__q15 = + 1'b0 /* unspecified value */ ; endcase end always@(frk_ptr or frk_sr) begin case (frk_ptr) 3'd0: - IF_frk_ptr_19_EQ_0_37_THEN_frk_sr_23_BITS_27_T_ETC___d702 = - frk_sr[27:20]; + SEL_ARR_frk_sr_23_BITS_17_TO_10_80_frk_sr_23_B_ETC___d382 = + frk_sr[17:10]; 3'd1: - IF_frk_ptr_19_EQ_0_37_THEN_frk_sr_23_BITS_27_T_ETC___d702 = - frk_sr[67:60]; - default: IF_frk_ptr_19_EQ_0_37_THEN_frk_sr_23_BITS_27_T_ETC___d702 = - frk_sr[107:100]; + SEL_ARR_frk_sr_23_BITS_17_TO_10_80_frk_sr_23_B_ETC___d382 = + frk_sr[57:50]; + 3'd2: + SEL_ARR_frk_sr_23_BITS_17_TO_10_80_frk_sr_23_B_ETC___d382 = + frk_sr[97:90]; + default: SEL_ARR_frk_sr_23_BITS_17_TO_10_80_frk_sr_23_B_ETC___d382 = + 8'b10101010 /* unspecified value */ ; + endcase + end + always@(frk_ptr or frk_sr) + begin + case (frk_ptr) + 3'd0: + SEL_ARR_frk_sr_23_BITS_7_TO_0_99_frk_sr_23_BIT_ETC___d401 = + frk_sr[7:0]; + 3'd1: + SEL_ARR_frk_sr_23_BITS_7_TO_0_99_frk_sr_23_BIT_ETC___d401 = + frk_sr[47:40]; + 3'd2: + SEL_ARR_frk_sr_23_BITS_7_TO_0_99_frk_sr_23_BIT_ETC___d401 = + frk_sr[87:80]; + default: SEL_ARR_frk_sr_23_BITS_7_TO_0_99_frk_sr_23_BIT_ETC___d401 = + 8'b10101010 /* unspecified value */ ; endcase end always@(frk_ptr or frk_sr) begin case (frk_ptr) 3'd0: - CASE_frk_ptr_frk_ptr_EQ_2_AND_frk_sr_BITS_109__ETC__q16 = + CASE_frk_ptr_0_frk_sr_BITS_29_TO_28_EQ_2_1_frk_ETC__q16 = frk_sr[29:28] == 2'd2; 3'd1: - CASE_frk_ptr_frk_ptr_EQ_2_AND_frk_sr_BITS_109__ETC__q16 = + CASE_frk_ptr_0_frk_sr_BITS_29_TO_28_EQ_2_1_frk_ETC__q16 = frk_sr[69:68] == 2'd2; - default: CASE_frk_ptr_frk_ptr_EQ_2_AND_frk_sr_BITS_109__ETC__q16 = - frk_ptr == 3'd2 && frk_sr[109:108] == 2'd2; + 3'd2: + CASE_frk_ptr_0_frk_sr_BITS_29_TO_28_EQ_2_1_frk_ETC__q16 = + frk_sr[109:108] == 2'd2; + default: CASE_frk_ptr_0_frk_sr_BITS_29_TO_28_EQ_2_1_frk_ETC__q16 = + 1'b0 /* unspecified value */ ; endcase end always@(frk_ptr or frk_sr) begin case (frk_ptr) 3'd0: - CASE_frk_ptr_frk_ptr_EQ_2_AND_frk_sr_BITS_109__ETC__q17 = + CASE_frk_ptr_0_frk_sr_BITS_29_TO_28_EQ_1_1_frk_ETC__q17 = frk_sr[29:28] == 2'd1; 3'd1: - CASE_frk_ptr_frk_ptr_EQ_2_AND_frk_sr_BITS_109__ETC__q17 = + CASE_frk_ptr_0_frk_sr_BITS_29_TO_28_EQ_1_1_frk_ETC__q17 = frk_sr[69:68] == 2'd1; - default: CASE_frk_ptr_frk_ptr_EQ_2_AND_frk_sr_BITS_109__ETC__q17 = - frk_ptr == 3'd2 && frk_sr[109:108] == 2'd1; + 3'd2: + CASE_frk_ptr_0_frk_sr_BITS_29_TO_28_EQ_1_1_frk_ETC__q17 = + frk_sr[109:108] == 2'd1; + default: CASE_frk_ptr_0_frk_sr_BITS_29_TO_28_EQ_1_1_frk_ETC__q17 = + 1'b0 /* unspecified value */ ; endcase end always@(frk_ptr or frk_sr) begin case (frk_ptr) 3'd0: - CASE_frk_ptr_frk_ptr_EQ_2_AND_frk_sr_BITS_109__ETC__q18 = + CASE_frk_ptr_0_frk_sr_BITS_29_TO_28_EQ_0_1_frk_ETC__q18 = frk_sr[29:28] == 2'd0; 3'd1: - CASE_frk_ptr_frk_ptr_EQ_2_AND_frk_sr_BITS_109__ETC__q18 = + CASE_frk_ptr_0_frk_sr_BITS_29_TO_28_EQ_0_1_frk_ETC__q18 = frk_sr[69:68] == 2'd0; - default: CASE_frk_ptr_frk_ptr_EQ_2_AND_frk_sr_BITS_109__ETC__q18 = - frk_ptr == 3'd2 && frk_sr[109:108] == 2'd0; + 3'd2: + CASE_frk_ptr_0_frk_sr_BITS_29_TO_28_EQ_0_1_frk_ETC__q18 = + frk_sr[109:108] == 2'd0; + default: CASE_frk_ptr_0_frk_sr_BITS_29_TO_28_EQ_0_1_frk_ETC__q18 = + 1'b0 /* unspecified value */ ; endcase end - always@(frk_ptr or frk_sr) + always@(frk_srcF$D_OUT) begin - case (frk_ptr) - 3'd0: - IF_frk_ptr_19_EQ_0_37_THEN_frk_sr_23_BITS_17_T_ETC___d703 = - frk_sr[17:10]; - 3'd1: - IF_frk_ptr_19_EQ_0_37_THEN_frk_sr_23_BITS_17_T_ETC___d703 = - frk_sr[57:50]; - default: IF_frk_ptr_19_EQ_0_37_THEN_frk_sr_23_BITS_17_T_ETC___d703 = - frk_sr[97:90]; + case (frk_srcF$D_OUT[39:38]) + 2'd0, 2'd1, 2'd2: + CASE_frk_srcFD_OUT_BITS_39_TO_38_0_frk_srcFD_ETC__q19 = + frk_srcF$D_OUT[39:38]; + 2'd3: CASE_frk_srcFD_OUT_BITS_39_TO_38_0_frk_srcFD_ETC__q19 = 2'd3; + endcase + end + always@(frk_srcF$D_OUT) + begin + case (frk_srcF$D_OUT[29:28]) + 2'd0, 2'd1, 2'd2: + CASE_frk_srcFD_OUT_BITS_29_TO_28_0_frk_srcFD_ETC__q20 = + frk_srcF$D_OUT[29:28]; + 2'd3: CASE_frk_srcFD_OUT_BITS_29_TO_28_0_frk_srcFD_ETC__q20 = 2'd3; + endcase + end + always@(frk_srcF$D_OUT) + begin + case (frk_srcF$D_OUT[19:18]) + 2'd0, 2'd1, 2'd2: + CASE_frk_srcFD_OUT_BITS_19_TO_18_0_frk_srcFD_ETC__q21 = + frk_srcF$D_OUT[19:18]; + 2'd3: CASE_frk_srcFD_OUT_BITS_19_TO_18_0_frk_srcFD_ETC__q21 = 2'd3; + endcase + end + always@(frk_srcF$D_OUT) + begin + case (frk_srcF$D_OUT[9:8]) + 2'd0, 2'd1, 2'd2: + CASE_frk_srcFD_OUT_BITS_9_TO_8_0_frk_srcFD_O_ETC__q22 = + frk_srcF$D_OUT[9:8]; + 2'd3: CASE_frk_srcFD_OUT_BITS_9_TO_8_0_frk_srcFD_O_ETC__q22 = 2'd3; endcase end always@(frk_ptr or frk_sr) begin case (frk_ptr) 3'd0: - CASE_frk_ptr_frk_ptr_EQ_2_AND_frk_sr_BITS_99_T_ETC__q19 = + CASE_frk_ptr_0_frk_sr_BITS_19_TO_18_EQ_2_1_frk_ETC__q23 = frk_sr[19:18] == 2'd2; 3'd1: - CASE_frk_ptr_frk_ptr_EQ_2_AND_frk_sr_BITS_99_T_ETC__q19 = + CASE_frk_ptr_0_frk_sr_BITS_19_TO_18_EQ_2_1_frk_ETC__q23 = frk_sr[59:58] == 2'd2; - default: CASE_frk_ptr_frk_ptr_EQ_2_AND_frk_sr_BITS_99_T_ETC__q19 = - frk_ptr == 3'd2 && frk_sr[99:98] == 2'd2; + 3'd2: + CASE_frk_ptr_0_frk_sr_BITS_19_TO_18_EQ_2_1_frk_ETC__q23 = + frk_sr[99:98] == 2'd2; + default: CASE_frk_ptr_0_frk_sr_BITS_19_TO_18_EQ_2_1_frk_ETC__q23 = + 1'b0 /* unspecified value */ ; endcase end always@(frk_ptr or frk_sr) begin case (frk_ptr) 3'd0: - CASE_frk_ptr_frk_ptr_EQ_2_AND_frk_sr_BITS_99_T_ETC__q20 = + CASE_frk_ptr_0_frk_sr_BITS_19_TO_18_EQ_1_1_frk_ETC__q24 = frk_sr[19:18] == 2'd1; 3'd1: - CASE_frk_ptr_frk_ptr_EQ_2_AND_frk_sr_BITS_99_T_ETC__q20 = + CASE_frk_ptr_0_frk_sr_BITS_19_TO_18_EQ_1_1_frk_ETC__q24 = frk_sr[59:58] == 2'd1; - default: CASE_frk_ptr_frk_ptr_EQ_2_AND_frk_sr_BITS_99_T_ETC__q20 = - frk_ptr == 3'd2 && frk_sr[99:98] == 2'd1; + 3'd2: + CASE_frk_ptr_0_frk_sr_BITS_19_TO_18_EQ_1_1_frk_ETC__q24 = + frk_sr[99:98] == 2'd1; + default: CASE_frk_ptr_0_frk_sr_BITS_19_TO_18_EQ_1_1_frk_ETC__q24 = + 1'b0 /* unspecified value */ ; endcase end always@(frk_ptr or frk_sr) begin case (frk_ptr) 3'd0: - CASE_frk_ptr_frk_ptr_EQ_2_AND_frk_sr_BITS_99_T_ETC__q21 = + CASE_frk_ptr_0_frk_sr_BITS_19_TO_18_EQ_0_1_frk_ETC__q25 = frk_sr[19:18] == 2'd0; 3'd1: - CASE_frk_ptr_frk_ptr_EQ_2_AND_frk_sr_BITS_99_T_ETC__q21 = + CASE_frk_ptr_0_frk_sr_BITS_19_TO_18_EQ_0_1_frk_ETC__q25 = frk_sr[59:58] == 2'd0; - default: CASE_frk_ptr_frk_ptr_EQ_2_AND_frk_sr_BITS_99_T_ETC__q21 = - frk_ptr == 3'd2 && frk_sr[99:98] == 2'd0; + 3'd2: + CASE_frk_ptr_0_frk_sr_BITS_19_TO_18_EQ_0_1_frk_ETC__q25 = + frk_sr[99:98] == 2'd0; + default: CASE_frk_ptr_0_frk_sr_BITS_19_TO_18_EQ_0_1_frk_ETC__q25 = + 1'b0 /* unspecified value */ ; endcase end always@(frk_ptr or frk_sr) begin case (frk_ptr) 3'd0: - IF_frk_ptr_19_EQ_0_37_THEN_frk_sr_23_BITS_7_TO_ETC___d704 = - frk_sr[7:0]; - 3'd1: - IF_frk_ptr_19_EQ_0_37_THEN_frk_sr_23_BITS_7_TO_ETC___d704 = - frk_sr[47:40]; - default: IF_frk_ptr_19_EQ_0_37_THEN_frk_sr_23_BITS_7_TO_ETC___d704 = - frk_sr[87:80]; - endcase - end - always@(frk_ptr or frk_sr) - begin - case (frk_ptr) - 3'd0: - CASE_frk_ptr_frk_ptr_EQ_2_AND_frk_sr_BITS_89_T_ETC__q22 = + CASE_frk_ptr_0_frk_sr_BITS_9_TO_8_EQ_2_1_frk_s_ETC__q26 = frk_sr[9:8] == 2'd2; 3'd1: - CASE_frk_ptr_frk_ptr_EQ_2_AND_frk_sr_BITS_89_T_ETC__q22 = + CASE_frk_ptr_0_frk_sr_BITS_9_TO_8_EQ_2_1_frk_s_ETC__q26 = frk_sr[49:48] == 2'd2; - default: CASE_frk_ptr_frk_ptr_EQ_2_AND_frk_sr_BITS_89_T_ETC__q22 = - frk_ptr == 3'd2 && frk_sr[89:88] == 2'd2; + 3'd2: + CASE_frk_ptr_0_frk_sr_BITS_9_TO_8_EQ_2_1_frk_s_ETC__q26 = + frk_sr[89:88] == 2'd2; + default: CASE_frk_ptr_0_frk_sr_BITS_9_TO_8_EQ_2_1_frk_s_ETC__q26 = + 1'b0 /* unspecified value */ ; endcase end always@(frk_ptr or frk_sr) begin case (frk_ptr) 3'd0: - CASE_frk_ptr_frk_ptr_EQ_2_AND_frk_sr_BITS_89_T_ETC__q23 = + CASE_frk_ptr_0_frk_sr_BITS_9_TO_8_EQ_1_1_frk_s_ETC__q27 = frk_sr[9:8] == 2'd1; 3'd1: - CASE_frk_ptr_frk_ptr_EQ_2_AND_frk_sr_BITS_89_T_ETC__q23 = + CASE_frk_ptr_0_frk_sr_BITS_9_TO_8_EQ_1_1_frk_s_ETC__q27 = frk_sr[49:48] == 2'd1; - default: CASE_frk_ptr_frk_ptr_EQ_2_AND_frk_sr_BITS_89_T_ETC__q23 = - frk_ptr == 3'd2 && frk_sr[89:88] == 2'd1; + 3'd2: + CASE_frk_ptr_0_frk_sr_BITS_9_TO_8_EQ_1_1_frk_s_ETC__q27 = + frk_sr[89:88] == 2'd1; + default: CASE_frk_ptr_0_frk_sr_BITS_9_TO_8_EQ_1_1_frk_s_ETC__q27 = + 1'b0 /* unspecified value */ ; endcase end always@(frk_ptr or frk_sr) begin case (frk_ptr) 3'd0: - CASE_frk_ptr_frk_ptr_EQ_2_AND_frk_sr_BITS_89_T_ETC__q24 = + CASE_frk_ptr_0_frk_sr_BITS_9_TO_8_EQ_0_1_frk_s_ETC__q28 = frk_sr[9:8] == 2'd0; 3'd1: - CASE_frk_ptr_frk_ptr_EQ_2_AND_frk_sr_BITS_89_T_ETC__q24 = + CASE_frk_ptr_0_frk_sr_BITS_9_TO_8_EQ_0_1_frk_s_ETC__q28 = frk_sr[49:48] == 2'd0; - default: CASE_frk_ptr_frk_ptr_EQ_2_AND_frk_sr_BITS_89_T_ETC__q24 = - frk_ptr == 3'd2 && frk_sr[89:88] == 2'd0; - endcase - end - always@(frk_srcF$D_OUT) - begin - case (frk_srcF$D_OUT[39:38]) - 2'd0, 2'd1, 2'd2: - CASE_frk_srcFD_OUT_BITS_39_TO_38_3_0_frk_srcF_ETC__q25 = - frk_srcF$D_OUT[39:38]; - 2'd3: CASE_frk_srcFD_OUT_BITS_39_TO_38_3_0_frk_srcF_ETC__q25 = 2'd3; - endcase - end - always@(frk_srcF$D_OUT) - begin - case (frk_srcF$D_OUT[29:28]) - 2'd0, 2'd1, 2'd2: - CASE_frk_srcFD_OUT_BITS_29_TO_28_3_0_frk_srcF_ETC__q26 = - frk_srcF$D_OUT[29:28]; - 2'd3: CASE_frk_srcFD_OUT_BITS_29_TO_28_3_0_frk_srcF_ETC__q26 = 2'd3; - endcase - end - always@(frk_srcF$D_OUT) - begin - case (frk_srcF$D_OUT[19:18]) - 2'd0, 2'd1, 2'd2: - CASE_frk_srcFD_OUT_BITS_19_TO_18_3_0_frk_srcF_ETC__q27 = - frk_srcF$D_OUT[19:18]; - 2'd3: CASE_frk_srcFD_OUT_BITS_19_TO_18_3_0_frk_srcF_ETC__q27 = 2'd3; - endcase - end - always@(frk_srcF$D_OUT) - begin - case (frk_srcF$D_OUT[9:8]) - 2'd0, 2'd1, 2'd2: - CASE_frk_srcFD_OUT_BITS_9_TO_8_3_0_frk_srcFD_ETC__q28 = - frk_srcF$D_OUT[9:8]; - 2'd3: CASE_frk_srcFD_OUT_BITS_9_TO_8_3_0_frk_srcFD_ETC__q28 = 2'd3; + 3'd2: + CASE_frk_ptr_0_frk_sr_BITS_9_TO_8_EQ_0_1_frk_s_ETC__q28 = + frk_sr[89:88] == 2'd0; + default: CASE_frk_ptr_0_frk_sr_BITS_9_TO_8_EQ_0_1_frk_s_ETC__q28 = + 1'b0 /* unspecified value */ ; endcase end always@(merge_fi0$D_OUT) begin case (merge_fi0$D_OUT[39:38]) 2'd0, 2'd1, 2'd2: - CASE_merge_fi0D_OUT_BITS_39_TO_38_3_0_merge_f_ETC__q29 = + CASE_merge_fi0D_OUT_BITS_39_TO_38_0_merge_fi0_ETC__q29 = merge_fi0$D_OUT[39:38]; - 2'd3: CASE_merge_fi0D_OUT_BITS_39_TO_38_3_0_merge_f_ETC__q29 = 2'd3; + 2'd3: CASE_merge_fi0D_OUT_BITS_39_TO_38_0_merge_fi0_ETC__q29 = 2'd3; endcase end always@(merge_fi0$D_OUT) begin case (merge_fi0$D_OUT[29:28]) 2'd0, 2'd1, 2'd2: - CASE_merge_fi0D_OUT_BITS_29_TO_28_3_0_merge_f_ETC__q30 = + CASE_merge_fi0D_OUT_BITS_29_TO_28_0_merge_fi0_ETC__q30 = merge_fi0$D_OUT[29:28]; - 2'd3: CASE_merge_fi0D_OUT_BITS_29_TO_28_3_0_merge_f_ETC__q30 = 2'd3; + 2'd3: CASE_merge_fi0D_OUT_BITS_29_TO_28_0_merge_fi0_ETC__q30 = 2'd3; endcase end always@(merge_fi0$D_OUT) begin case (merge_fi0$D_OUT[19:18]) 2'd0, 2'd1, 2'd2: - CASE_merge_fi0D_OUT_BITS_19_TO_18_3_0_merge_f_ETC__q31 = + CASE_merge_fi0D_OUT_BITS_19_TO_18_0_merge_fi0_ETC__q31 = merge_fi0$D_OUT[19:18]; - 2'd3: CASE_merge_fi0D_OUT_BITS_19_TO_18_3_0_merge_f_ETC__q31 = 2'd3; + 2'd3: CASE_merge_fi0D_OUT_BITS_19_TO_18_0_merge_fi0_ETC__q31 = 2'd3; endcase end always@(merge_fi0$D_OUT) begin case (merge_fi0$D_OUT[9:8]) 2'd0, 2'd1, 2'd2: - CASE_merge_fi0D_OUT_BITS_9_TO_8_3_0_merge_fi0_ETC__q32 = + CASE_merge_fi0D_OUT_BITS_9_TO_8_0_merge_fi0D_ETC__q32 = merge_fi0$D_OUT[9:8]; - 2'd3: CASE_merge_fi0D_OUT_BITS_9_TO_8_3_0_merge_fi0_ETC__q32 = 2'd3; + 2'd3: CASE_merge_fi0D_OUT_BITS_9_TO_8_0_merge_fi0D_ETC__q32 = 2'd3; endcase end always@(merge_fi1$D_OUT) begin case (merge_fi1$D_OUT[39:38]) 2'd0, 2'd1, 2'd2: - CASE_merge_fi1D_OUT_BITS_39_TO_38_3_0_merge_f_ETC__q33 = + CASE_merge_fi1D_OUT_BITS_39_TO_38_0_merge_fi1_ETC__q33 = merge_fi1$D_OUT[39:38]; - 2'd3: CASE_merge_fi1D_OUT_BITS_39_TO_38_3_0_merge_f_ETC__q33 = 2'd3; + 2'd3: CASE_merge_fi1D_OUT_BITS_39_TO_38_0_merge_fi1_ETC__q33 = 2'd3; endcase end always@(merge_fi1$D_OUT) begin case (merge_fi1$D_OUT[29:28]) 2'd0, 2'd1, 2'd2: - CASE_merge_fi1D_OUT_BITS_29_TO_28_3_0_merge_f_ETC__q34 = + CASE_merge_fi1D_OUT_BITS_29_TO_28_0_merge_fi1_ETC__q34 = merge_fi1$D_OUT[29:28]; - 2'd3: CASE_merge_fi1D_OUT_BITS_29_TO_28_3_0_merge_f_ETC__q34 = 2'd3; + 2'd3: CASE_merge_fi1D_OUT_BITS_29_TO_28_0_merge_fi1_ETC__q34 = 2'd3; endcase end always@(merge_fi1$D_OUT) begin case (merge_fi1$D_OUT[19:18]) 2'd0, 2'd1, 2'd2: - CASE_merge_fi1D_OUT_BITS_19_TO_18_3_0_merge_f_ETC__q35 = + CASE_merge_fi1D_OUT_BITS_19_TO_18_0_merge_fi1_ETC__q35 = merge_fi1$D_OUT[19:18]; - 2'd3: CASE_merge_fi1D_OUT_BITS_19_TO_18_3_0_merge_f_ETC__q35 = 2'd3; + 2'd3: CASE_merge_fi1D_OUT_BITS_19_TO_18_0_merge_fi1_ETC__q35 = 2'd3; endcase end always@(merge_fi1$D_OUT) begin case (merge_fi1$D_OUT[9:8]) 2'd0, 2'd1, 2'd2: - CASE_merge_fi1D_OUT_BITS_9_TO_8_3_0_merge_fi1_ETC__q36 = + CASE_merge_fi1D_OUT_BITS_9_TO_8_0_merge_fi1D_ETC__q36 = merge_fi1$D_OUT[9:8]; - 2'd3: CASE_merge_fi1D_OUT_BITS_9_TO_8_3_0_merge_fi1_ETC__q36 = 2'd3; + 2'd3: CASE_merge_fi1D_OUT_BITS_9_TO_8_0_merge_fi1D_ETC__q36 = 2'd3; endcase end always@(frk_sr) begin case (frk_sr[119:118]) 2'd0, 2'd1, 2'd2: - CASE_frk_sr_BITS_119_TO_118_3_0_frk_sr_BITS_11_ETC__q37 = + CASE_frk_sr_BITS_119_TO_118_0_frk_sr_BITS_119__ETC__q37 = frk_sr[119:118]; - 2'd3: CASE_frk_sr_BITS_119_TO_118_3_0_frk_sr_BITS_11_ETC__q37 = 2'd3; + 2'd3: CASE_frk_sr_BITS_119_TO_118_0_frk_sr_BITS_119__ETC__q37 = 2'd3; endcase end always@(frk_sr) begin case (frk_sr[109:108]) 2'd0, 2'd1, 2'd2: - CASE_frk_sr_BITS_109_TO_108_3_0_frk_sr_BITS_10_ETC__q38 = + CASE_frk_sr_BITS_109_TO_108_0_frk_sr_BITS_109__ETC__q38 = frk_sr[109:108]; - 2'd3: CASE_frk_sr_BITS_109_TO_108_3_0_frk_sr_BITS_10_ETC__q38 = 2'd3; + 2'd3: CASE_frk_sr_BITS_109_TO_108_0_frk_sr_BITS_109__ETC__q38 = 2'd3; endcase end always@(frk_sr) begin case (frk_sr[99:98]) 2'd0, 2'd1, 2'd2: - CASE_frk_sr_BITS_99_TO_98_3_0_frk_sr_BITS_99_T_ETC__q39 = + CASE_frk_sr_BITS_99_TO_98_0_frk_sr_BITS_99_TO__ETC__q39 = frk_sr[99:98]; - 2'd3: CASE_frk_sr_BITS_99_TO_98_3_0_frk_sr_BITS_99_T_ETC__q39 = 2'd3; + 2'd3: CASE_frk_sr_BITS_99_TO_98_0_frk_sr_BITS_99_TO__ETC__q39 = 2'd3; endcase end always@(frk_sr) begin case (frk_sr[89:88]) 2'd0, 2'd1, 2'd2: - CASE_frk_sr_BITS_89_TO_88_3_0_frk_sr_BITS_89_T_ETC__q40 = + CASE_frk_sr_BITS_89_TO_88_0_frk_sr_BITS_89_TO__ETC__q40 = frk_sr[89:88]; - 2'd3: CASE_frk_sr_BITS_89_TO_88_3_0_frk_sr_BITS_89_T_ETC__q40 = 2'd3; + 2'd3: CASE_frk_sr_BITS_89_TO_88_0_frk_sr_BITS_89_TO__ETC__q40 = 2'd3; endcase end always@(frk_sr) begin case (frk_sr[79:78]) 2'd0, 2'd1, 2'd2: - CASE_frk_sr_BITS_79_TO_78_3_0_frk_sr_BITS_79_T_ETC__q41 = + CASE_frk_sr_BITS_79_TO_78_0_frk_sr_BITS_79_TO__ETC__q41 = frk_sr[79:78]; - 2'd3: CASE_frk_sr_BITS_79_TO_78_3_0_frk_sr_BITS_79_T_ETC__q41 = 2'd3; + 2'd3: CASE_frk_sr_BITS_79_TO_78_0_frk_sr_BITS_79_TO__ETC__q41 = 2'd3; endcase end always@(frk_sr) begin case (frk_sr[69:68]) 2'd0, 2'd1, 2'd2: - CASE_frk_sr_BITS_69_TO_68_3_0_frk_sr_BITS_69_T_ETC__q42 = + CASE_frk_sr_BITS_69_TO_68_0_frk_sr_BITS_69_TO__ETC__q42 = frk_sr[69:68]; - 2'd3: CASE_frk_sr_BITS_69_TO_68_3_0_frk_sr_BITS_69_T_ETC__q42 = 2'd3; + 2'd3: CASE_frk_sr_BITS_69_TO_68_0_frk_sr_BITS_69_TO__ETC__q42 = 2'd3; endcase end always@(frk_sr) begin case (frk_sr[59:58]) 2'd0, 2'd1, 2'd2: - CASE_frk_sr_BITS_59_TO_58_3_0_frk_sr_BITS_59_T_ETC__q43 = + CASE_frk_sr_BITS_59_TO_58_0_frk_sr_BITS_59_TO__ETC__q43 = frk_sr[59:58]; - 2'd3: CASE_frk_sr_BITS_59_TO_58_3_0_frk_sr_BITS_59_T_ETC__q43 = 2'd3; + 2'd3: CASE_frk_sr_BITS_59_TO_58_0_frk_sr_BITS_59_TO__ETC__q43 = 2'd3; endcase end always@(frk_sr) begin case (frk_sr[49:48]) 2'd0, 2'd1, 2'd2: - CASE_frk_sr_BITS_49_TO_48_3_0_frk_sr_BITS_49_T_ETC__q44 = + CASE_frk_sr_BITS_49_TO_48_0_frk_sr_BITS_49_TO__ETC__q44 = frk_sr[49:48]; - 2'd3: CASE_frk_sr_BITS_49_TO_48_3_0_frk_sr_BITS_49_T_ETC__q44 = 2'd3; + 2'd3: CASE_frk_sr_BITS_49_TO_48_0_frk_sr_BITS_49_TO__ETC__q44 = 2'd3; endcase end always@(server_request_put) begin case (server_request_put[39:38]) 2'd0, 2'd1, 2'd2: - CASE_server_request_put_BITS_39_TO_38_3_0_serv_ETC__q45 = + CASE_server_request_put_BITS_39_TO_38_0_server_ETC__q45 = server_request_put[39:38]; - 2'd3: CASE_server_request_put_BITS_39_TO_38_3_0_serv_ETC__q45 = 2'd3; + 2'd3: CASE_server_request_put_BITS_39_TO_38_0_server_ETC__q45 = 2'd3; endcase end always@(server_request_put) begin case (server_request_put[29:28]) 2'd0, 2'd1, 2'd2: - CASE_server_request_put_BITS_29_TO_28_3_0_serv_ETC__q46 = + CASE_server_request_put_BITS_29_TO_28_0_server_ETC__q46 = server_request_put[29:28]; - 2'd3: CASE_server_request_put_BITS_29_TO_28_3_0_serv_ETC__q46 = 2'd3; + 2'd3: CASE_server_request_put_BITS_29_TO_28_0_server_ETC__q46 = 2'd3; endcase end always@(server_request_put) begin case (server_request_put[19:18]) 2'd0, 2'd1, 2'd2: - CASE_server_request_put_BITS_19_TO_18_3_0_serv_ETC__q47 = + CASE_server_request_put_BITS_19_TO_18_0_server_ETC__q47 = server_request_put[19:18]; - 2'd3: CASE_server_request_put_BITS_19_TO_18_3_0_serv_ETC__q47 = 2'd3; + 2'd3: CASE_server_request_put_BITS_19_TO_18_0_server_ETC__q47 = 2'd3; endcase end always@(server_request_put) begin case (server_request_put[9:8]) 2'd0, 2'd1, 2'd2: - CASE_server_request_put_BITS_9_TO_8_3_0_server_ETC__q48 = + CASE_server_request_put_BITS_9_TO_8_0_server_r_ETC__q48 = server_request_put[9:8]; - 2'd3: CASE_server_request_put_BITS_9_TO_8_3_0_server_ETC__q48 = 2'd3; + 2'd3: CASE_server_request_put_BITS_9_TO_8_0_server_r_ETC__q48 = 2'd3; endcase end always@(client0_response_put) begin case (client0_response_put[39:38]) 2'd0, 2'd1, 2'd2: - CASE_client0_response_put_BITS_39_TO_38_3_0_cl_ETC__q49 = + CASE_client0_response_put_BITS_39_TO_38_0_clie_ETC__q49 = client0_response_put[39:38]; - 2'd3: CASE_client0_response_put_BITS_39_TO_38_3_0_cl_ETC__q49 = 2'd3; + 2'd3: CASE_client0_response_put_BITS_39_TO_38_0_clie_ETC__q49 = 2'd3; endcase end always@(client0_response_put) begin case (client0_response_put[29:28]) 2'd0, 2'd1, 2'd2: - CASE_client0_response_put_BITS_29_TO_28_3_0_cl_ETC__q50 = + CASE_client0_response_put_BITS_29_TO_28_0_clie_ETC__q50 = client0_response_put[29:28]; - 2'd3: CASE_client0_response_put_BITS_29_TO_28_3_0_cl_ETC__q50 = 2'd3; + 2'd3: CASE_client0_response_put_BITS_29_TO_28_0_clie_ETC__q50 = 2'd3; endcase end always@(client0_response_put) begin case (client0_response_put[19:18]) 2'd0, 2'd1, 2'd2: - CASE_client0_response_put_BITS_19_TO_18_3_0_cl_ETC__q51 = + CASE_client0_response_put_BITS_19_TO_18_0_clie_ETC__q51 = client0_response_put[19:18]; - 2'd3: CASE_client0_response_put_BITS_19_TO_18_3_0_cl_ETC__q51 = 2'd3; + 2'd3: CASE_client0_response_put_BITS_19_TO_18_0_clie_ETC__q51 = 2'd3; endcase end always@(client0_response_put) begin case (client0_response_put[9:8]) 2'd0, 2'd1, 2'd2: - CASE_client0_response_put_BITS_9_TO_8_3_0_clie_ETC__q52 = + CASE_client0_response_put_BITS_9_TO_8_0_client_ETC__q52 = client0_response_put[9:8]; - 2'd3: CASE_client0_response_put_BITS_9_TO_8_3_0_clie_ETC__q52 = 2'd3; + 2'd3: CASE_client0_response_put_BITS_9_TO_8_0_client_ETC__q52 = 2'd3; endcase end always@(client1_response_put) begin case (client1_response_put[39:38]) 2'd0, 2'd1, 2'd2: - CASE_client1_response_put_BITS_39_TO_38_3_0_cl_ETC__q53 = + CASE_client1_response_put_BITS_39_TO_38_0_clie_ETC__q53 = client1_response_put[39:38]; - 2'd3: CASE_client1_response_put_BITS_39_TO_38_3_0_cl_ETC__q53 = 2'd3; + 2'd3: CASE_client1_response_put_BITS_39_TO_38_0_clie_ETC__q53 = 2'd3; endcase end always@(client1_response_put) begin case (client1_response_put[29:28]) 2'd0, 2'd1, 2'd2: - CASE_client1_response_put_BITS_29_TO_28_3_0_cl_ETC__q54 = + CASE_client1_response_put_BITS_29_TO_28_0_clie_ETC__q54 = client1_response_put[29:28]; - 2'd3: CASE_client1_response_put_BITS_29_TO_28_3_0_cl_ETC__q54 = 2'd3; + 2'd3: CASE_client1_response_put_BITS_29_TO_28_0_clie_ETC__q54 = 2'd3; endcase end always@(client1_response_put) begin case (client1_response_put[19:18]) 2'd0, 2'd1, 2'd2: - CASE_client1_response_put_BITS_19_TO_18_3_0_cl_ETC__q55 = + CASE_client1_response_put_BITS_19_TO_18_0_clie_ETC__q55 = client1_response_put[19:18]; - 2'd3: CASE_client1_response_put_BITS_19_TO_18_3_0_cl_ETC__q55 = 2'd3; + 2'd3: CASE_client1_response_put_BITS_19_TO_18_0_clie_ETC__q55 = 2'd3; endcase end always@(client1_response_put) begin case (client1_response_put[9:8]) 2'd0, 2'd1, 2'd2: - CASE_client1_response_put_BITS_9_TO_8_3_0_clie_ETC__q56 = + CASE_client1_response_put_BITS_9_TO_8_0_client_ETC__q56 = client1_response_put[9:8]; - 2'd3: CASE_client1_response_put_BITS_9_TO_8_3_0_clie_ETC__q56 = 2'd3; + 2'd3: CASE_client1_response_put_BITS_9_TO_8_0_client_ETC__q56 = 2'd3; endcase end diff --git a/rtl/mkQABSMF3.v b/rtl/mkQABSMF3.v index ee902aa6..1c54fd85 100644 --- a/rtl/mkQABSMF3.v +++ b/rtl/mkQABSMF3.v @@ -1,7 +1,7 @@ // -// Generated by Bluespec Compiler, version 2012.09.beta1 (build 29570, 2012-09.11) +// Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Wed Nov 28 10:31:25 EST 2012 +// On Fri Jun 21 16:56:46 EDT 2013 // // // Ports: @@ -364,164 +364,164 @@ module mkQABSMF3(et0, MUX_merge1_fi1Active$write_1__VAL_2; // remaining internal signals - reg [7 : 0] IF_fork0_ptr_90_EQ_0_08_THEN_fork0_sr_94_BITS__ETC___d1350, - IF_fork0_ptr_90_EQ_0_08_THEN_fork0_sr_94_BITS__ETC___d1351, - IF_fork0_ptr_90_EQ_0_08_THEN_fork0_sr_94_BITS__ETC___d1352, - IF_fork0_ptr_90_EQ_0_08_THEN_fork0_sr_94_BITS__ETC___d1353, - IF_fork1_ptr_57_EQ_0_75_THEN_fork1_sr_61_BITS__ETC___d1354, - IF_fork1_ptr_57_EQ_0_75_THEN_fork1_sr_61_BITS__ETC___d1355, - IF_fork1_ptr_57_EQ_0_75_THEN_fork1_sr_61_BITS__ETC___d1356, - IF_fork1_ptr_57_EQ_0_75_THEN_fork1_sr_61_BITS__ETC___d1357; - reg [1 : 0] CASE_client0_response_put_BITS_19_TO_18_3_0_cl_ETC__q91, - CASE_client0_response_put_BITS_29_TO_28_3_0_cl_ETC__q90, - CASE_client0_response_put_BITS_39_TO_38_3_0_cl_ETC__q89, - CASE_client0_response_put_BITS_9_TO_8_3_0_clie_ETC__q92, - CASE_client1_response_put_BITS_19_TO_18_3_0_cl_ETC__q99, - CASE_client1_response_put_BITS_29_TO_28_3_0_cl_ETC__q98, - CASE_client1_response_put_BITS_39_TO_38_3_0_cl_ETC__q97, - CASE_client1_response_put_BITS_9_TO_8_3_0_clie_ETC__q100, - CASE_client2_response_put_BITS_19_TO_18_3_0_cl_ETC__q103, - CASE_client2_response_put_BITS_29_TO_28_3_0_cl_ETC__q102, - CASE_client2_response_put_BITS_39_TO_38_3_0_cl_ETC__q101, - CASE_client2_response_put_BITS_9_TO_8_3_0_clie_ETC__q104, - CASE_fork0_d0FD_OUT_BITS_19_TO_18_3_0_fork0_d_ETC__q7, - CASE_fork0_d0FD_OUT_BITS_29_TO_28_3_0_fork0_d_ETC__q6, - CASE_fork0_d0FD_OUT_BITS_39_TO_38_3_0_fork0_d_ETC__q5, - CASE_fork0_d0FD_OUT_BITS_9_TO_8_3_0_fork0_d0F_ETC__q8, - CASE_fork0_d1FD_OUT_BITS_19_TO_18_3_0_fork0_d_ETC__q87, - CASE_fork0_d1FD_OUT_BITS_29_TO_28_3_0_fork0_d_ETC__q86, - CASE_fork0_d1FD_OUT_BITS_39_TO_38_3_0_fork0_d_ETC__q85, - CASE_fork0_d1FD_OUT_BITS_9_TO_8_3_0_fork0_d1F_ETC__q88, - CASE_fork0_sr_BITS_109_TO_108_3_0_fork0_sr_BIT_ETC__q66, - CASE_fork0_sr_BITS_119_TO_118_3_0_fork0_sr_BIT_ETC__q65, - CASE_fork0_sr_BITS_49_TO_48_3_0_fork0_sr_BITS__ETC__q72, - CASE_fork0_sr_BITS_59_TO_58_3_0_fork0_sr_BITS__ETC__q71, - CASE_fork0_sr_BITS_69_TO_68_3_0_fork0_sr_BITS__ETC__q70, - CASE_fork0_sr_BITS_79_TO_78_3_0_fork0_sr_BITS__ETC__q69, - CASE_fork0_sr_BITS_89_TO_88_3_0_fork0_sr_BITS__ETC__q68, - CASE_fork0_sr_BITS_99_TO_98_3_0_fork0_sr_BITS__ETC__q67, - CASE_fork0_srcFD_OUT_BITS_19_TO_18_3_0_fork0__ETC__q43, - CASE_fork0_srcFD_OUT_BITS_29_TO_28_3_0_fork0__ETC__q42, - CASE_fork0_srcFD_OUT_BITS_39_TO_38_3_0_fork0__ETC__q41, - CASE_fork0_srcFD_OUT_BITS_9_TO_8_3_0_fork0_sr_ETC__q44, - CASE_fork1_d0FD_OUT_BITS_19_TO_18_3_0_fork1_d_ETC__q3, - CASE_fork1_d0FD_OUT_BITS_29_TO_28_3_0_fork1_d_ETC__q2, - CASE_fork1_d0FD_OUT_BITS_39_TO_38_3_0_fork1_d_ETC__q1, - CASE_fork1_d0FD_OUT_BITS_9_TO_8_3_0_fork1_d0F_ETC__q4, - CASE_fork1_d1FD_OUT_BITS_19_TO_18_3_0_fork1_d_ETC__q15, - CASE_fork1_d1FD_OUT_BITS_29_TO_28_3_0_fork1_d_ETC__q14, - CASE_fork1_d1FD_OUT_BITS_39_TO_38_3_0_fork1_d_ETC__q13, - CASE_fork1_d1FD_OUT_BITS_9_TO_8_3_0_fork1_d1F_ETC__q16, - CASE_fork1_sr_BITS_109_TO_108_3_0_fork1_sr_BIT_ETC__q78, - CASE_fork1_sr_BITS_119_TO_118_3_0_fork1_sr_BIT_ETC__q77, - CASE_fork1_sr_BITS_49_TO_48_3_0_fork1_sr_BITS__ETC__q84, - CASE_fork1_sr_BITS_59_TO_58_3_0_fork1_sr_BITS__ETC__q83, - CASE_fork1_sr_BITS_69_TO_68_3_0_fork1_sr_BITS__ETC__q82, - CASE_fork1_sr_BITS_79_TO_78_3_0_fork1_sr_BITS__ETC__q81, - CASE_fork1_sr_BITS_89_TO_88_3_0_fork1_sr_BITS__ETC__q80, - CASE_fork1_sr_BITS_99_TO_98_3_0_fork1_sr_BITS__ETC__q79, - CASE_fork1_srcFD_OUT_BITS_19_TO_18_3_0_fork1__ETC__q47, - CASE_fork1_srcFD_OUT_BITS_29_TO_28_3_0_fork1__ETC__q46, - CASE_fork1_srcFD_OUT_BITS_39_TO_38_3_0_fork1__ETC__q45, - CASE_fork1_srcFD_OUT_BITS_9_TO_8_3_0_fork1_sr_ETC__q48, - CASE_merge0_fi0D_OUT_BITS_19_TO_18_3_0_merge0_ETC__q51, - CASE_merge0_fi0D_OUT_BITS_29_TO_28_3_0_merge0_ETC__q50, - CASE_merge0_fi0D_OUT_BITS_39_TO_38_3_0_merge0_ETC__q49, - CASE_merge0_fi0D_OUT_BITS_9_TO_8_3_0_merge0_f_ETC__q52, - CASE_merge0_fi1D_OUT_BITS_19_TO_18_3_0_merge0_ETC__q55, - CASE_merge0_fi1D_OUT_BITS_29_TO_28_3_0_merge0_ETC__q54, - CASE_merge0_fi1D_OUT_BITS_39_TO_38_3_0_merge0_ETC__q53, - CASE_merge0_fi1D_OUT_BITS_9_TO_8_3_0_merge0_f_ETC__q56, - CASE_merge0_foD_OUT_BITS_19_TO_18_3_0_merge0__ETC__q11, - CASE_merge0_foD_OUT_BITS_29_TO_28_3_0_merge0__ETC__q10, - CASE_merge0_foD_OUT_BITS_39_TO_38_3_0_merge0__ETC__q9, - CASE_merge0_foD_OUT_BITS_9_TO_8_3_0_merge0_fo_ETC__q12, - CASE_merge1_fi0D_OUT_BITS_19_TO_18_3_0_merge1_ETC__q59, - CASE_merge1_fi0D_OUT_BITS_29_TO_28_3_0_merge1_ETC__q58, - CASE_merge1_fi0D_OUT_BITS_39_TO_38_3_0_merge1_ETC__q57, - CASE_merge1_fi0D_OUT_BITS_9_TO_8_3_0_merge1_f_ETC__q60, - CASE_merge1_fi1D_OUT_BITS_19_TO_18_3_0_merge1_ETC__q63, - CASE_merge1_fi1D_OUT_BITS_29_TO_28_3_0_merge1_ETC__q62, - CASE_merge1_fi1D_OUT_BITS_39_TO_38_3_0_merge1_ETC__q61, - CASE_merge1_fi1D_OUT_BITS_9_TO_8_3_0_merge1_f_ETC__q64, - CASE_merge1_foD_OUT_BITS_19_TO_18_3_0_merge1__ETC__q95, - CASE_merge1_foD_OUT_BITS_29_TO_28_3_0_merge1__ETC__q94, - CASE_merge1_foD_OUT_BITS_39_TO_38_3_0_merge1__ETC__q93, - CASE_merge1_foD_OUT_BITS_9_TO_8_3_0_merge1_fo_ETC__q96, - CASE_server_request_put_BITS_19_TO_18_3_0_serv_ETC__q75, - CASE_server_request_put_BITS_29_TO_28_3_0_serv_ETC__q74, - CASE_server_request_put_BITS_39_TO_38_3_0_serv_ETC__q73, - CASE_server_request_put_BITS_9_TO_8_3_0_server_ETC__q76; - reg CASE_fork0_ptr_fork0_ptr_EQ_2_AND_fork0_sr_BIT_ETC__q17, - CASE_fork0_ptr_fork0_ptr_EQ_2_AND_fork0_sr_BIT_ETC__q18, - CASE_fork0_ptr_fork0_ptr_EQ_2_AND_fork0_sr_BIT_ETC__q19, - CASE_fork0_ptr_fork0_ptr_EQ_2_AND_fork0_sr_BIT_ETC__q20, - CASE_fork0_ptr_fork0_ptr_EQ_2_AND_fork0_sr_BIT_ETC__q21, - CASE_fork0_ptr_fork0_ptr_EQ_2_AND_fork0_sr_BIT_ETC__q22, - CASE_fork0_ptr_fork0_ptr_EQ_2_AND_fork0_sr_BIT_ETC__q23, - CASE_fork0_ptr_fork0_ptr_EQ_2_AND_fork0_sr_BIT_ETC__q24, - CASE_fork0_ptr_fork0_ptr_EQ_2_AND_fork0_sr_BIT_ETC__q25, - CASE_fork0_ptr_fork0_ptr_EQ_2_AND_fork0_sr_BIT_ETC__q26, - CASE_fork0_ptr_fork0_ptr_EQ_2_AND_fork0_sr_BIT_ETC__q27, - CASE_fork0_ptr_fork0_ptr_EQ_2_AND_fork0_sr_BIT_ETC__q28, - CASE_fork1_ptr_fork1_ptr_EQ_2_AND_fork1_sr_BIT_ETC__q29, - CASE_fork1_ptr_fork1_ptr_EQ_2_AND_fork1_sr_BIT_ETC__q30, - CASE_fork1_ptr_fork1_ptr_EQ_2_AND_fork1_sr_BIT_ETC__q31, - CASE_fork1_ptr_fork1_ptr_EQ_2_AND_fork1_sr_BIT_ETC__q32, - CASE_fork1_ptr_fork1_ptr_EQ_2_AND_fork1_sr_BIT_ETC__q33, - CASE_fork1_ptr_fork1_ptr_EQ_2_AND_fork1_sr_BIT_ETC__q34, - CASE_fork1_ptr_fork1_ptr_EQ_2_AND_fork1_sr_BIT_ETC__q35, - CASE_fork1_ptr_fork1_ptr_EQ_2_AND_fork1_sr_BIT_ETC__q36, - CASE_fork1_ptr_fork1_ptr_EQ_2_AND_fork1_sr_BIT_ETC__q37, - CASE_fork1_ptr_fork1_ptr_EQ_2_AND_fork1_sr_BIT_ETC__q38, - CASE_fork1_ptr_fork1_ptr_EQ_2_AND_fork1_sr_BIT_ETC__q39, - CASE_fork1_ptr_fork1_ptr_EQ_2_AND_fork1_sr_BIT_ETC__q40; - wire [39 : 0] IF_fork0_srcF_first__50_BITS_39_TO_38_51_EQ_0__ETC___d1358, - IF_fork1_srcF_first__17_BITS_39_TO_38_18_EQ_0__ETC___d1359; + reg [7 : 0] SEL_ARR_fork0_sr_94_BITS_17_TO_10_51_fork0_sr__ETC___d553, + SEL_ARR_fork0_sr_94_BITS_27_TO_20_31_fork0_sr__ETC___d533, + SEL_ARR_fork0_sr_94_BITS_37_TO_30_12_fork0_sr__ETC___d514, + SEL_ARR_fork0_sr_94_BITS_7_TO_0_70_fork0_sr_94_ETC___d572, + SEL_ARR_fork1_sr_43_BITS_17_TO_10_00_fork1_sr__ETC___d802, + SEL_ARR_fork1_sr_43_BITS_27_TO_20_80_fork1_sr__ETC___d782, + SEL_ARR_fork1_sr_43_BITS_37_TO_30_61_fork1_sr__ETC___d763, + SEL_ARR_fork1_sr_43_BITS_7_TO_0_19_fork1_sr_43_ETC___d821; + reg [1 : 0] CASE_client0_response_put_BITS_19_TO_18_0_clie_ETC__q91, + CASE_client0_response_put_BITS_29_TO_28_0_clie_ETC__q90, + CASE_client0_response_put_BITS_39_TO_38_0_clie_ETC__q89, + CASE_client0_response_put_BITS_9_TO_8_0_client_ETC__q92, + CASE_client1_response_put_BITS_19_TO_18_0_clie_ETC__q99, + CASE_client1_response_put_BITS_29_TO_28_0_clie_ETC__q98, + CASE_client1_response_put_BITS_39_TO_38_0_clie_ETC__q97, + CASE_client1_response_put_BITS_9_TO_8_0_client_ETC__q100, + CASE_client2_response_put_BITS_19_TO_18_0_clie_ETC__q103, + CASE_client2_response_put_BITS_29_TO_28_0_clie_ETC__q102, + CASE_client2_response_put_BITS_39_TO_38_0_clie_ETC__q101, + CASE_client2_response_put_BITS_9_TO_8_0_client_ETC__q104, + CASE_fork0_d0FD_OUT_BITS_19_TO_18_0_fork0_d0F_ETC__q7, + CASE_fork0_d0FD_OUT_BITS_29_TO_28_0_fork0_d0F_ETC__q6, + CASE_fork0_d0FD_OUT_BITS_39_TO_38_0_fork0_d0F_ETC__q5, + CASE_fork0_d0FD_OUT_BITS_9_TO_8_0_fork0_d0FD_ETC__q8, + CASE_fork0_d1FD_OUT_BITS_19_TO_18_0_fork0_d1F_ETC__q87, + CASE_fork0_d1FD_OUT_BITS_29_TO_28_0_fork0_d1F_ETC__q86, + CASE_fork0_d1FD_OUT_BITS_39_TO_38_0_fork0_d1F_ETC__q85, + CASE_fork0_d1FD_OUT_BITS_9_TO_8_0_fork0_d1FD_ETC__q88, + CASE_fork0_sr_BITS_109_TO_108_0_fork0_sr_BITS__ETC__q66, + CASE_fork0_sr_BITS_119_TO_118_0_fork0_sr_BITS__ETC__q65, + CASE_fork0_sr_BITS_49_TO_48_0_fork0_sr_BITS_49_ETC__q72, + CASE_fork0_sr_BITS_59_TO_58_0_fork0_sr_BITS_59_ETC__q71, + CASE_fork0_sr_BITS_69_TO_68_0_fork0_sr_BITS_69_ETC__q70, + CASE_fork0_sr_BITS_79_TO_78_0_fork0_sr_BITS_79_ETC__q69, + CASE_fork0_sr_BITS_89_TO_88_0_fork0_sr_BITS_89_ETC__q68, + CASE_fork0_sr_BITS_99_TO_98_0_fork0_sr_BITS_99_ETC__q67, + CASE_fork0_srcFD_OUT_BITS_19_TO_18_0_fork0_sr_ETC__q29, + CASE_fork0_srcFD_OUT_BITS_29_TO_28_0_fork0_sr_ETC__q28, + CASE_fork0_srcFD_OUT_BITS_39_TO_38_0_fork0_sr_ETC__q27, + CASE_fork0_srcFD_OUT_BITS_9_TO_8_0_fork0_srcF_ETC__q30, + CASE_fork1_d0FD_OUT_BITS_19_TO_18_0_fork1_d0F_ETC__q3, + CASE_fork1_d0FD_OUT_BITS_29_TO_28_0_fork1_d0F_ETC__q2, + CASE_fork1_d0FD_OUT_BITS_39_TO_38_0_fork1_d0F_ETC__q1, + CASE_fork1_d0FD_OUT_BITS_9_TO_8_0_fork1_d0FD_ETC__q4, + CASE_fork1_d1FD_OUT_BITS_19_TO_18_0_fork1_d1F_ETC__q15, + CASE_fork1_d1FD_OUT_BITS_29_TO_28_0_fork1_d1F_ETC__q14, + CASE_fork1_d1FD_OUT_BITS_39_TO_38_0_fork1_d1F_ETC__q13, + CASE_fork1_d1FD_OUT_BITS_9_TO_8_0_fork1_d1FD_ETC__q16, + CASE_fork1_sr_BITS_109_TO_108_0_fork1_sr_BITS__ETC__q78, + CASE_fork1_sr_BITS_119_TO_118_0_fork1_sr_BITS__ETC__q77, + CASE_fork1_sr_BITS_49_TO_48_0_fork1_sr_BITS_49_ETC__q84, + CASE_fork1_sr_BITS_59_TO_58_0_fork1_sr_BITS_59_ETC__q83, + CASE_fork1_sr_BITS_69_TO_68_0_fork1_sr_BITS_69_ETC__q82, + CASE_fork1_sr_BITS_79_TO_78_0_fork1_sr_BITS_79_ETC__q81, + CASE_fork1_sr_BITS_89_TO_88_0_fork1_sr_BITS_89_ETC__q80, + CASE_fork1_sr_BITS_99_TO_98_0_fork1_sr_BITS_99_ETC__q79, + CASE_fork1_srcFD_OUT_BITS_19_TO_18_0_fork1_sr_ETC__q25, + CASE_fork1_srcFD_OUT_BITS_29_TO_28_0_fork1_sr_ETC__q24, + CASE_fork1_srcFD_OUT_BITS_39_TO_38_0_fork1_sr_ETC__q23, + CASE_fork1_srcFD_OUT_BITS_9_TO_8_0_fork1_srcF_ETC__q26, + CASE_merge0_fi0D_OUT_BITS_19_TO_18_0_merge0_f_ETC__q51, + CASE_merge0_fi0D_OUT_BITS_29_TO_28_0_merge0_f_ETC__q50, + CASE_merge0_fi0D_OUT_BITS_39_TO_38_0_merge0_f_ETC__q49, + CASE_merge0_fi0D_OUT_BITS_9_TO_8_0_merge0_fi0_ETC__q52, + CASE_merge0_fi1D_OUT_BITS_19_TO_18_0_merge0_f_ETC__q55, + CASE_merge0_fi1D_OUT_BITS_29_TO_28_0_merge0_f_ETC__q54, + CASE_merge0_fi1D_OUT_BITS_39_TO_38_0_merge0_f_ETC__q53, + CASE_merge0_fi1D_OUT_BITS_9_TO_8_0_merge0_fi1_ETC__q56, + CASE_merge0_foD_OUT_BITS_19_TO_18_0_merge0_fo_ETC__q11, + CASE_merge0_foD_OUT_BITS_29_TO_28_0_merge0_fo_ETC__q10, + CASE_merge0_foD_OUT_BITS_39_TO_38_0_merge0_fo_ETC__q9, + CASE_merge0_foD_OUT_BITS_9_TO_8_0_merge0_foD_ETC__q12, + CASE_merge1_fi0D_OUT_BITS_19_TO_18_0_merge1_f_ETC__q59, + CASE_merge1_fi0D_OUT_BITS_29_TO_28_0_merge1_f_ETC__q58, + CASE_merge1_fi0D_OUT_BITS_39_TO_38_0_merge1_f_ETC__q57, + CASE_merge1_fi0D_OUT_BITS_9_TO_8_0_merge1_fi0_ETC__q60, + CASE_merge1_fi1D_OUT_BITS_19_TO_18_0_merge1_f_ETC__q63, + CASE_merge1_fi1D_OUT_BITS_29_TO_28_0_merge1_f_ETC__q62, + CASE_merge1_fi1D_OUT_BITS_39_TO_38_0_merge1_f_ETC__q61, + CASE_merge1_fi1D_OUT_BITS_9_TO_8_0_merge1_fi1_ETC__q64, + CASE_merge1_foD_OUT_BITS_19_TO_18_0_merge1_fo_ETC__q95, + CASE_merge1_foD_OUT_BITS_29_TO_28_0_merge1_fo_ETC__q94, + CASE_merge1_foD_OUT_BITS_39_TO_38_0_merge1_fo_ETC__q93, + CASE_merge1_foD_OUT_BITS_9_TO_8_0_merge1_foD_ETC__q96, + CASE_server_request_put_BITS_19_TO_18_0_server_ETC__q75, + CASE_server_request_put_BITS_29_TO_28_0_server_ETC__q74, + CASE_server_request_put_BITS_39_TO_38_0_server_ETC__q73, + CASE_server_request_put_BITS_9_TO_8_0_server_r_ETC__q76; + reg CASE_fork0_ptr_0_fork0_sr_BITS_19_TO_18_EQ_0_1_ETC__q39, + CASE_fork0_ptr_0_fork0_sr_BITS_19_TO_18_EQ_1_1_ETC__q38, + CASE_fork0_ptr_0_fork0_sr_BITS_19_TO_18_EQ_2_1_ETC__q37, + CASE_fork0_ptr_0_fork0_sr_BITS_29_TO_28_EQ_0_1_ETC__q22, + CASE_fork0_ptr_0_fork0_sr_BITS_29_TO_28_EQ_1_1_ETC__q21, + CASE_fork0_ptr_0_fork0_sr_BITS_29_TO_28_EQ_2_1_ETC__q20, + CASE_fork0_ptr_0_fork0_sr_BITS_39_TO_38_EQ_0_1_ETC__q19, + CASE_fork0_ptr_0_fork0_sr_BITS_39_TO_38_EQ_1_1_ETC__q18, + CASE_fork0_ptr_0_fork0_sr_BITS_39_TO_38_EQ_2_1_ETC__q17, + CASE_fork0_ptr_0_fork0_sr_BITS_9_TO_8_EQ_0_1_f_ETC__q42, + CASE_fork0_ptr_0_fork0_sr_BITS_9_TO_8_EQ_1_1_f_ETC__q41, + CASE_fork0_ptr_0_fork0_sr_BITS_9_TO_8_EQ_2_1_f_ETC__q40, + CASE_fork1_ptr_0_fork1_sr_BITS_19_TO_18_EQ_0_1_ETC__q45, + CASE_fork1_ptr_0_fork1_sr_BITS_19_TO_18_EQ_1_1_ETC__q44, + CASE_fork1_ptr_0_fork1_sr_BITS_19_TO_18_EQ_2_1_ETC__q43, + CASE_fork1_ptr_0_fork1_sr_BITS_29_TO_28_EQ_0_1_ETC__q36, + CASE_fork1_ptr_0_fork1_sr_BITS_29_TO_28_EQ_1_1_ETC__q35, + CASE_fork1_ptr_0_fork1_sr_BITS_29_TO_28_EQ_2_1_ETC__q34, + CASE_fork1_ptr_0_fork1_sr_BITS_39_TO_38_EQ_0_1_ETC__q33, + CASE_fork1_ptr_0_fork1_sr_BITS_39_TO_38_EQ_1_1_ETC__q32, + CASE_fork1_ptr_0_fork1_sr_BITS_39_TO_38_EQ_2_1_ETC__q31, + CASE_fork1_ptr_0_fork1_sr_BITS_9_TO_8_EQ_0_1_f_ETC__q48, + CASE_fork1_ptr_0_fork1_sr_BITS_9_TO_8_EQ_1_1_f_ETC__q47, + CASE_fork1_ptr_0_fork1_sr_BITS_9_TO_8_EQ_2_1_f_ETC__q46; + wire [39 : 0] IF_fork0_srcF_first__50_BITS_39_TO_38_51_EQ_0__ETC___d393, + IF_fork1_srcF_first__99_BITS_39_TO_38_00_EQ_0__ETC___d642; wire [19 : 0] IF_IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_fir_ETC___d147, IF_IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_fir_ETC___d318; - wire [15 : 0] seen__h15847, seen__h26440; - wire [9 : 0] IF_IF_fork0_ptr_90_EQ_0_08_THEN_fork0_sr_94_BI_ETC___d530, - IF_IF_fork0_ptr_90_EQ_0_08_THEN_fork0_sr_94_BI_ETC___d531, - IF_IF_fork0_ptr_90_EQ_0_08_THEN_fork0_sr_94_BI_ETC___d532, - IF_IF_fork0_ptr_90_EQ_0_08_THEN_fork0_sr_94_BI_ETC___d553, - IF_IF_fork0_ptr_90_EQ_0_08_THEN_fork0_sr_94_BI_ETC___d554, - IF_IF_fork0_ptr_90_EQ_0_08_THEN_fork0_sr_94_BI_ETC___d555, - IF_IF_fork0_ptr_90_EQ_0_08_THEN_fork0_sr_94_BI_ETC___d577, - IF_IF_fork0_ptr_90_EQ_0_08_THEN_fork0_sr_94_BI_ETC___d578, - IF_IF_fork0_ptr_90_EQ_0_08_THEN_fork0_sr_94_BI_ETC___d579, - IF_IF_fork0_ptr_90_EQ_0_08_THEN_fork0_sr_94_BI_ETC___d600, - IF_IF_fork0_ptr_90_EQ_0_08_THEN_fork0_sr_94_BI_ETC___d601, - IF_IF_fork0_ptr_90_EQ_0_08_THEN_fork0_sr_94_BI_ETC___d602, - IF_IF_fork1_ptr_57_EQ_0_75_THEN_fork1_sr_61_BI_ETC___d797, - IF_IF_fork1_ptr_57_EQ_0_75_THEN_fork1_sr_61_BI_ETC___d798, - IF_IF_fork1_ptr_57_EQ_0_75_THEN_fork1_sr_61_BI_ETC___d799, - IF_IF_fork1_ptr_57_EQ_0_75_THEN_fork1_sr_61_BI_ETC___d820, - IF_IF_fork1_ptr_57_EQ_0_75_THEN_fork1_sr_61_BI_ETC___d821, - IF_IF_fork1_ptr_57_EQ_0_75_THEN_fork1_sr_61_BI_ETC___d822, - IF_IF_fork1_ptr_57_EQ_0_75_THEN_fork1_sr_61_BI_ETC___d844, - IF_IF_fork1_ptr_57_EQ_0_75_THEN_fork1_sr_61_BI_ETC___d845, - IF_IF_fork1_ptr_57_EQ_0_75_THEN_fork1_sr_61_BI_ETC___d846, - IF_IF_fork1_ptr_57_EQ_0_75_THEN_fork1_sr_61_BI_ETC___d867, - IF_IF_fork1_ptr_57_EQ_0_75_THEN_fork1_sr_61_BI_ETC___d868, - IF_IF_fork1_ptr_57_EQ_0_75_THEN_fork1_sr_61_BI_ETC___d869, - IF_IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_fir_ETC___d135, + wire [15 : 0] seen__h14989, seen__h24820; + wire [9 : 0] IF_IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_fir_ETC___d135, IF_IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_fir_ETC___d145, IF_IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_fir_ETC___d156, IF_IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_fir_ETC___d166, IF_IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_fir_ETC___d306, IF_IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_fir_ETC___d316, IF_IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_fir_ETC___d327, - IF_IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_fir_ETC___d337; - wire [7 : 0] IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1343, - IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1344, - IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1345, - IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1346, - IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_first__ETC___d1321, - IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_first__ETC___d1347, - IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_first__ETC___d1348, - IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_first__ETC___d1349; - wire [2 : 0] fork0_ptr_90_PLUS_1___d1456, fork1_ptr_57_PLUS_1___d1457; + IF_IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_fir_ETC___d337, + IF_SEL_ARR_fork0_sr_94_BITS_19_TO_18_47_EQ_0_4_ETC___d565, + IF_SEL_ARR_fork0_sr_94_BITS_19_TO_18_47_EQ_1_5_ETC___d564, + IF_SEL_ARR_fork0_sr_94_BITS_19_TO_18_47_EQ_2_5_ETC___d563, + IF_SEL_ARR_fork0_sr_94_BITS_29_TO_28_27_EQ_0_2_ETC___d545, + IF_SEL_ARR_fork0_sr_94_BITS_29_TO_28_27_EQ_1_3_ETC___d544, + IF_SEL_ARR_fork0_sr_94_BITS_29_TO_28_27_EQ_2_3_ETC___d543, + IF_SEL_ARR_fork0_sr_94_BITS_39_TO_38_08_EQ_0_0_ETC___d526, + IF_SEL_ARR_fork0_sr_94_BITS_39_TO_38_08_EQ_1_1_ETC___d525, + IF_SEL_ARR_fork0_sr_94_BITS_39_TO_38_08_EQ_2_2_ETC___d524, + IF_SEL_ARR_fork0_sr_94_BITS_9_TO_8_66_EQ_0_67__ETC___d584, + IF_SEL_ARR_fork0_sr_94_BITS_9_TO_8_66_EQ_1_74__ETC___d583, + IF_SEL_ARR_fork0_sr_94_BITS_9_TO_8_66_EQ_2_78__ETC___d582, + IF_SEL_ARR_fork1_sr_43_BITS_19_TO_18_96_EQ_0_9_ETC___d814, + IF_SEL_ARR_fork1_sr_43_BITS_19_TO_18_96_EQ_1_0_ETC___d813, + IF_SEL_ARR_fork1_sr_43_BITS_19_TO_18_96_EQ_2_0_ETC___d812, + IF_SEL_ARR_fork1_sr_43_BITS_29_TO_28_76_EQ_0_7_ETC___d794, + IF_SEL_ARR_fork1_sr_43_BITS_29_TO_28_76_EQ_1_8_ETC___d793, + IF_SEL_ARR_fork1_sr_43_BITS_29_TO_28_76_EQ_2_8_ETC___d792, + IF_SEL_ARR_fork1_sr_43_BITS_39_TO_38_57_EQ_0_5_ETC___d775, + IF_SEL_ARR_fork1_sr_43_BITS_39_TO_38_57_EQ_1_6_ETC___d774, + IF_SEL_ARR_fork1_sr_43_BITS_39_TO_38_57_EQ_2_6_ETC___d773, + IF_SEL_ARR_fork1_sr_43_BITS_9_TO_8_15_EQ_0_16__ETC___d833, + IF_SEL_ARR_fork1_sr_43_BITS_9_TO_8_15_EQ_1_23__ETC___d832, + IF_SEL_ARR_fork1_sr_43_BITS_9_TO_8_15_EQ_2_27__ETC___d831; + wire [7 : 0] IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d128, + IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d138, + IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d149, + IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d159, + IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_first__ETC___d299, + IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_first__ETC___d309, + IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_first__ETC___d320, + IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_first__ETC___d330; + wire [2 : 0] fork0_ptr_90_PLUS_1___d491, fork1_ptr_39_PLUS_1___d740; wire [1 : 0] IF_IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_fir_ETC___d133, IF_IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_fir_ETC___d143, IF_IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_fir_ETC___d154, @@ -531,46 +531,46 @@ module mkQABSMF3(et0, IF_IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_fir_ETC___d325, IF_IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_fir_ETC___d335; wire IF_merge0_fi0HasPrio_06_THEN_NOT_merge0_fi0_i__ETC___d113, - IF_merge0_fi0HasPrio_06_THEN_NOT_merge0_fi0_i__ETC___d1666, - IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1327, - IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1334, - IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1665, - IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1667, + IF_merge0_fi0HasPrio_06_THEN_NOT_merge0_fi0_i__ETC___d115, + IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d127, + IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d137, + IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d148, + IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d158, IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_i_notE_ETC___d118, - IF_merge1_fi0HasPrio_77_THEN_NOT_merge1_fi0_i__ETC___d1670, IF_merge1_fi0HasPrio_77_THEN_NOT_merge1_fi0_i__ETC___d284, - IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_first__ETC___d1333, - IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_first__ETC___d1668, - IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_first__ETC___d1669, - IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_first__ETC___d1671, + IF_merge1_fi0HasPrio_77_THEN_NOT_merge1_fi0_i__ETC___d286, + IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_first__ETC___d298, + IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_first__ETC___d308, + IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_first__ETC___d319, + IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_first__ETC___d329, IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_i_notE_ETC___d289, NOT_fork0_stageSent_98_99_OR_fork0_srcF_i_notE_ETC___d505, - NOT_fork1_stageSent_65_66_OR_fork1_srcF_i_notE_ETC___d772; + NOT_fork1_stageSent_47_48_OR_fork1_srcF_i_notE_ETC___d754; // action method server_request_put assign RDY_server_request_put = fork0_srcF$FULL_N ; // actionvalue method server_response_get assign server_response_get = - { CASE_merge0_foD_OUT_BITS_39_TO_38_3_0_merge0__ETC__q9, + { CASE_merge0_foD_OUT_BITS_39_TO_38_0_merge0_fo_ETC__q9, merge0_fo$D_OUT[37:30], - CASE_merge0_foD_OUT_BITS_29_TO_28_3_0_merge0__ETC__q10, + CASE_merge0_foD_OUT_BITS_29_TO_28_0_merge0_fo_ETC__q10, merge0_fo$D_OUT[27:20], - CASE_merge0_foD_OUT_BITS_19_TO_18_3_0_merge0__ETC__q11, + CASE_merge0_foD_OUT_BITS_19_TO_18_0_merge0_fo_ETC__q11, merge0_fo$D_OUT[17:10], - CASE_merge0_foD_OUT_BITS_9_TO_8_3_0_merge0_fo_ETC__q12, + CASE_merge0_foD_OUT_BITS_9_TO_8_0_merge0_foD_ETC__q12, merge0_fo$D_OUT[7:0] } ; assign RDY_server_response_get = merge0_fo$EMPTY_N ; // actionvalue method client0_request_get assign client0_request_get = - { CASE_fork0_d0FD_OUT_BITS_39_TO_38_3_0_fork0_d_ETC__q5, + { CASE_fork0_d0FD_OUT_BITS_39_TO_38_0_fork0_d0F_ETC__q5, fork0_d0F$D_OUT[37:30], - CASE_fork0_d0FD_OUT_BITS_29_TO_28_3_0_fork0_d_ETC__q6, + CASE_fork0_d0FD_OUT_BITS_29_TO_28_0_fork0_d0F_ETC__q6, fork0_d0F$D_OUT[27:20], - CASE_fork0_d0FD_OUT_BITS_19_TO_18_3_0_fork0_d_ETC__q7, + CASE_fork0_d0FD_OUT_BITS_19_TO_18_0_fork0_d0F_ETC__q7, fork0_d0F$D_OUT[17:10], - CASE_fork0_d0FD_OUT_BITS_9_TO_8_3_0_fork0_d0F_ETC__q8, + CASE_fork0_d0FD_OUT_BITS_9_TO_8_0_fork0_d0FD_ETC__q8, fork0_d0F$D_OUT[7:0] } ; assign RDY_client0_request_get = fork0_d0F$EMPTY_N ; @@ -579,13 +579,13 @@ module mkQABSMF3(et0, // actionvalue method client1_request_get assign client1_request_get = - { CASE_fork1_d0FD_OUT_BITS_39_TO_38_3_0_fork1_d_ETC__q1, + { CASE_fork1_d0FD_OUT_BITS_39_TO_38_0_fork1_d0F_ETC__q1, fork1_d0F$D_OUT[37:30], - CASE_fork1_d0FD_OUT_BITS_29_TO_28_3_0_fork1_d_ETC__q2, + CASE_fork1_d0FD_OUT_BITS_29_TO_28_0_fork1_d0F_ETC__q2, fork1_d0F$D_OUT[27:20], - CASE_fork1_d0FD_OUT_BITS_19_TO_18_3_0_fork1_d_ETC__q3, + CASE_fork1_d0FD_OUT_BITS_19_TO_18_0_fork1_d0F_ETC__q3, fork1_d0F$D_OUT[17:10], - CASE_fork1_d0FD_OUT_BITS_9_TO_8_3_0_fork1_d0F_ETC__q4, + CASE_fork1_d0FD_OUT_BITS_9_TO_8_0_fork1_d0FD_ETC__q4, fork1_d0F$D_OUT[7:0] } ; assign RDY_client1_request_get = fork1_d0F$EMPTY_N ; @@ -594,13 +594,13 @@ module mkQABSMF3(et0, // actionvalue method client2_request_get assign client2_request_get = - { CASE_fork1_d1FD_OUT_BITS_39_TO_38_3_0_fork1_d_ETC__q13, + { CASE_fork1_d1FD_OUT_BITS_39_TO_38_0_fork1_d1F_ETC__q13, fork1_d1F$D_OUT[37:30], - CASE_fork1_d1FD_OUT_BITS_29_TO_28_3_0_fork1_d_ETC__q14, + CASE_fork1_d1FD_OUT_BITS_29_TO_28_0_fork1_d1F_ETC__q14, fork1_d1F$D_OUT[27:20], - CASE_fork1_d1FD_OUT_BITS_19_TO_18_3_0_fork1_d_ETC__q15, + CASE_fork1_d1FD_OUT_BITS_19_TO_18_0_fork1_d1F_ETC__q15, fork1_d1F$D_OUT[17:10], - CASE_fork1_d1FD_OUT_BITS_9_TO_8_3_0_fork1_d1F_ETC__q16, + CASE_fork1_d1FD_OUT_BITS_9_TO_8_0_fork1_d1FD_ETC__q16, fork1_d1F$D_OUT[7:0] } ; assign RDY_client2_request_get = fork1_d1F$EMPTY_N ; @@ -803,7 +803,7 @@ module mkQABSMF3(et0, // rule RL_fork1_egress assign WILL_FIRE_RL_fork1_egress = - NOT_fork1_stageSent_65_66_OR_fork1_srcF_i_notE_ETC___d772 && + NOT_fork1_stageSent_47_48_OR_fork1_srcF_i_notE_ETC___d754 && fork1_staged && fork1_decided ; @@ -843,28 +843,28 @@ module mkQABSMF3(et0, assign MUX_merge1_fi1Active$write_1__SEL_1 = WILL_FIRE_RL_merge1_arbitrate && !merge1_fi0HasPrio ; assign MUX_fork0_ptr$write_1__VAL_1 = - fork0_stageSent ? 3'd0 : fork0_ptr_90_PLUS_1___d1456 ; + fork0_stageSent ? 3'd0 : fork0_ptr_90_PLUS_1___d491 ; assign MUX_fork0_ptr$write_1__VAL_2 = (fork0_srcF$D_OUT[9:8] != 2'd0 || fork0_srcF$D_OUT[19:18] != 2'd0 || fork0_srcF$D_OUT[29:28] != 2'd0 || fork0_srcF$D_OUT[39:38] != 2'd0) ? 3'd0 : - fork0_ptr_90_PLUS_1___d1456 ; + fork0_ptr_90_PLUS_1___d491 ; assign MUX_fork1_ptr$write_1__VAL_1 = - fork1_stageSent ? 3'd0 : fork1_ptr_57_PLUS_1___d1457 ; + fork1_stageSent ? 3'd0 : fork1_ptr_39_PLUS_1___d740 ; assign MUX_fork1_ptr$write_1__VAL_2 = (fork1_srcF$D_OUT[9:8] != 2'd0 || fork1_srcF$D_OUT[19:18] != 2'd0 || fork1_srcF$D_OUT[29:28] != 2'd0 || fork1_srcF$D_OUT[39:38] != 2'd0) ? 3'd0 : - fork1_ptr_57_PLUS_1___d1457 ; + fork1_ptr_39_PLUS_1___d740 ; assign MUX_merge0_fi0Active$write_1__VAL_1 = - IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1667 && - IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1665 && - IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1327 && - IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1334 ; + IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d158 && + IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d148 && + IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d137 && + IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d127 ; assign MUX_merge0_fi0Active$write_1__VAL_2 = merge0_fi0$D_OUT[9:8] == 2'd0 && merge0_fi0$D_OUT[19:18] == 2'd0 && @@ -876,38 +876,38 @@ module mkQABSMF3(et0, merge0_fi1$D_OUT[29:28] == 2'd0 && merge0_fi1$D_OUT[39:38] == 2'd0 ; assign MUX_merge0_fo$enq_1__VAL_1 = - { CASE_merge0_fi0D_OUT_BITS_39_TO_38_3_0_merge0_ETC__q49, + { CASE_merge0_fi0D_OUT_BITS_39_TO_38_0_merge0_f_ETC__q49, merge0_fi0$D_OUT[37:30], - CASE_merge0_fi0D_OUT_BITS_29_TO_28_3_0_merge0_ETC__q50, + CASE_merge0_fi0D_OUT_BITS_29_TO_28_0_merge0_f_ETC__q50, merge0_fi0$D_OUT[27:20], - CASE_merge0_fi0D_OUT_BITS_19_TO_18_3_0_merge0_ETC__q51, + CASE_merge0_fi0D_OUT_BITS_19_TO_18_0_merge0_f_ETC__q51, merge0_fi0$D_OUT[17:10], - CASE_merge0_fi0D_OUT_BITS_9_TO_8_3_0_merge0_f_ETC__q52, + CASE_merge0_fi0D_OUT_BITS_9_TO_8_0_merge0_fi0_ETC__q52, merge0_fi0$D_OUT[7:0] } ; assign MUX_merge0_fo$enq_1__VAL_2 = - { CASE_merge0_fi1D_OUT_BITS_39_TO_38_3_0_merge0_ETC__q53, + { CASE_merge0_fi1D_OUT_BITS_39_TO_38_0_merge0_f_ETC__q53, merge0_fi1$D_OUT[37:30], - CASE_merge0_fi1D_OUT_BITS_29_TO_28_3_0_merge0_ETC__q54, + CASE_merge0_fi1D_OUT_BITS_29_TO_28_0_merge0_f_ETC__q54, merge0_fi1$D_OUT[27:20], - CASE_merge0_fi1D_OUT_BITS_19_TO_18_3_0_merge0_ETC__q55, + CASE_merge0_fi1D_OUT_BITS_19_TO_18_0_merge0_f_ETC__q55, merge0_fi1$D_OUT[17:10], - CASE_merge0_fi1D_OUT_BITS_9_TO_8_3_0_merge0_f_ETC__q56, + CASE_merge0_fi1D_OUT_BITS_9_TO_8_0_merge0_fi1_ETC__q56, merge0_fi1$D_OUT[7:0] } ; assign MUX_merge0_fo$enq_1__VAL_3 = { IF_IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_fir_ETC___d147, - IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1665 ? + IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d148 ? { 2'd0, - IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1345 } : + IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d149 } : IF_IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_fir_ETC___d156, - IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1667 ? + IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d158 ? { 2'd0, - IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1346 } : + IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d159 } : IF_IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_fir_ETC___d166 } ; assign MUX_merge1_fi0Active$write_1__VAL_1 = - IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_first__ETC___d1671 && - IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_first__ETC___d1669 && - IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_first__ETC___d1668 && - IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_first__ETC___d1333 ; + IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_first__ETC___d329 && + IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_first__ETC___d319 && + IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_first__ETC___d308 && + IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_first__ETC___d298 ; assign MUX_merge1_fi0Active$write_1__VAL_2 = merge1_fi0$D_OUT[9:8] == 2'd0 && merge1_fi0$D_OUT[19:18] == 2'd0 && @@ -919,32 +919,32 @@ module mkQABSMF3(et0, merge1_fi1$D_OUT[29:28] == 2'd0 && merge1_fi1$D_OUT[39:38] == 2'd0 ; assign MUX_merge1_fo$enq_1__VAL_1 = - { CASE_merge1_fi0D_OUT_BITS_39_TO_38_3_0_merge1_ETC__q57, + { CASE_merge1_fi0D_OUT_BITS_39_TO_38_0_merge1_f_ETC__q57, merge1_fi0$D_OUT[37:30], - CASE_merge1_fi0D_OUT_BITS_29_TO_28_3_0_merge1_ETC__q58, + CASE_merge1_fi0D_OUT_BITS_29_TO_28_0_merge1_f_ETC__q58, merge1_fi0$D_OUT[27:20], - CASE_merge1_fi0D_OUT_BITS_19_TO_18_3_0_merge1_ETC__q59, + CASE_merge1_fi0D_OUT_BITS_19_TO_18_0_merge1_f_ETC__q59, merge1_fi0$D_OUT[17:10], - CASE_merge1_fi0D_OUT_BITS_9_TO_8_3_0_merge1_f_ETC__q60, + CASE_merge1_fi0D_OUT_BITS_9_TO_8_0_merge1_fi0_ETC__q60, merge1_fi0$D_OUT[7:0] } ; assign MUX_merge1_fo$enq_1__VAL_2 = - { CASE_merge1_fi1D_OUT_BITS_39_TO_38_3_0_merge1_ETC__q61, + { CASE_merge1_fi1D_OUT_BITS_39_TO_38_0_merge1_f_ETC__q61, merge1_fi1$D_OUT[37:30], - CASE_merge1_fi1D_OUT_BITS_29_TO_28_3_0_merge1_ETC__q62, + CASE_merge1_fi1D_OUT_BITS_29_TO_28_0_merge1_f_ETC__q62, merge1_fi1$D_OUT[27:20], - CASE_merge1_fi1D_OUT_BITS_19_TO_18_3_0_merge1_ETC__q63, + CASE_merge1_fi1D_OUT_BITS_19_TO_18_0_merge1_f_ETC__q63, merge1_fi1$D_OUT[17:10], - CASE_merge1_fi1D_OUT_BITS_9_TO_8_3_0_merge1_f_ETC__q64, + CASE_merge1_fi1D_OUT_BITS_9_TO_8_0_merge1_fi1_ETC__q64, merge1_fi1$D_OUT[7:0] } ; assign MUX_merge1_fo$enq_1__VAL_3 = { IF_IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_fir_ETC___d318, - IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_first__ETC___d1669 ? + IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_first__ETC___d319 ? { 2'd0, - IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_first__ETC___d1349 } : + IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_first__ETC___d320 } : IF_IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_fir_ETC___d327, - IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_first__ETC___d1671 ? + IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_first__ETC___d329 ? { 2'd0, - IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_first__ETC___d1321 } : + IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_first__ETC___d330 } : IF_IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_fir_ETC___d337 } ; // register fork0_decided @@ -958,7 +958,7 @@ module mkQABSMF3(et0, WILL_FIRE_RL_fork0_decide ; // register fork0_match0 - assign fork0_match0$D_IN = et0 == seen__h15847 ; + assign fork0_match0$D_IN = et0 == seen__h14989 ; assign fork0_match0$EN = WILL_FIRE_RL_fork0_decide ; // register fork0_ptr @@ -987,22 +987,22 @@ module mkQABSMF3(et0, // register fork0_sr assign fork0_sr$D_IN = - { IF_fork0_srcF_first__50_BITS_39_TO_38_51_EQ_0__ETC___d1358, - CASE_fork0_sr_BITS_119_TO_118_3_0_fork0_sr_BIT_ETC__q65, + { IF_fork0_srcF_first__50_BITS_39_TO_38_51_EQ_0__ETC___d393, + CASE_fork0_sr_BITS_119_TO_118_0_fork0_sr_BITS__ETC__q65, fork0_sr[117:110], - CASE_fork0_sr_BITS_109_TO_108_3_0_fork0_sr_BIT_ETC__q66, + CASE_fork0_sr_BITS_109_TO_108_0_fork0_sr_BITS__ETC__q66, fork0_sr[107:100], - CASE_fork0_sr_BITS_99_TO_98_3_0_fork0_sr_BITS__ETC__q67, + CASE_fork0_sr_BITS_99_TO_98_0_fork0_sr_BITS_99_ETC__q67, fork0_sr[97:90], - CASE_fork0_sr_BITS_89_TO_88_3_0_fork0_sr_BITS__ETC__q68, + CASE_fork0_sr_BITS_89_TO_88_0_fork0_sr_BITS_89_ETC__q68, fork0_sr[87:80], - CASE_fork0_sr_BITS_79_TO_78_3_0_fork0_sr_BITS__ETC__q69, + CASE_fork0_sr_BITS_79_TO_78_0_fork0_sr_BITS_79_ETC__q69, fork0_sr[77:70], - CASE_fork0_sr_BITS_69_TO_68_3_0_fork0_sr_BITS__ETC__q70, + CASE_fork0_sr_BITS_69_TO_68_0_fork0_sr_BITS_69_ETC__q70, fork0_sr[67:60], - CASE_fork0_sr_BITS_59_TO_58_3_0_fork0_sr_BITS__ETC__q71, + CASE_fork0_sr_BITS_59_TO_58_0_fork0_sr_BITS_59_ETC__q71, fork0_sr[57:50], - CASE_fork0_sr_BITS_49_TO_48_3_0_fork0_sr_BITS__ETC__q72, + CASE_fork0_sr_BITS_49_TO_48_0_fork0_sr_BITS_49_ETC__q72, fork0_sr[47:40] } ; assign fork0_sr$EN = WILL_FIRE_RL_fork0_stage ; @@ -1032,7 +1032,7 @@ module mkQABSMF3(et0, WILL_FIRE_RL_fork1_decide ; // register fork1_match0 - assign fork1_match0$D_IN = did == seen__h26440 ; + assign fork1_match0$D_IN = did == seen__h24820 ; assign fork1_match0$EN = WILL_FIRE_RL_fork1_decide ; // register fork1_ptr @@ -1061,22 +1061,22 @@ module mkQABSMF3(et0, // register fork1_sr assign fork1_sr$D_IN = - { IF_fork1_srcF_first__17_BITS_39_TO_38_18_EQ_0__ETC___d1359, - CASE_fork1_sr_BITS_119_TO_118_3_0_fork1_sr_BIT_ETC__q77, + { IF_fork1_srcF_first__99_BITS_39_TO_38_00_EQ_0__ETC___d642, + CASE_fork1_sr_BITS_119_TO_118_0_fork1_sr_BITS__ETC__q77, fork1_sr[117:110], - CASE_fork1_sr_BITS_109_TO_108_3_0_fork1_sr_BIT_ETC__q78, + CASE_fork1_sr_BITS_109_TO_108_0_fork1_sr_BITS__ETC__q78, fork1_sr[107:100], - CASE_fork1_sr_BITS_99_TO_98_3_0_fork1_sr_BITS__ETC__q79, + CASE_fork1_sr_BITS_99_TO_98_0_fork1_sr_BITS_99_ETC__q79, fork1_sr[97:90], - CASE_fork1_sr_BITS_89_TO_88_3_0_fork1_sr_BITS__ETC__q80, + CASE_fork1_sr_BITS_89_TO_88_0_fork1_sr_BITS_89_ETC__q80, fork1_sr[87:80], - CASE_fork1_sr_BITS_79_TO_78_3_0_fork1_sr_BITS__ETC__q81, + CASE_fork1_sr_BITS_79_TO_78_0_fork1_sr_BITS_79_ETC__q81, fork1_sr[77:70], - CASE_fork1_sr_BITS_69_TO_68_3_0_fork1_sr_BITS__ETC__q82, + CASE_fork1_sr_BITS_69_TO_68_0_fork1_sr_BITS_69_ETC__q82, fork1_sr[67:60], - CASE_fork1_sr_BITS_59_TO_58_3_0_fork1_sr_BITS__ETC__q83, + CASE_fork1_sr_BITS_59_TO_58_0_fork1_sr_BITS_59_ETC__q83, fork1_sr[57:50], - CASE_fork1_sr_BITS_49_TO_48_3_0_fork1_sr_BITS__ETC__q84, + CASE_fork1_sr_BITS_49_TO_48_0_fork1_sr_BITS_49_ETC__q84, fork1_sr[47:40] } ; assign fork1_sr$EN = WILL_FIRE_RL_fork1_stage ; @@ -1170,11 +1170,11 @@ module mkQABSMF3(et0, // submodule fork0_d0F assign fork0_d0F$D_IN = fork0_stageSent ? - IF_fork0_srcF_first__50_BITS_39_TO_38_51_EQ_0__ETC___d1358 : - { IF_IF_fork0_ptr_90_EQ_0_08_THEN_fork0_sr_94_BI_ETC___d532, - IF_IF_fork0_ptr_90_EQ_0_08_THEN_fork0_sr_94_BI_ETC___d555, - IF_IF_fork0_ptr_90_EQ_0_08_THEN_fork0_sr_94_BI_ETC___d579, - IF_IF_fork0_ptr_90_EQ_0_08_THEN_fork0_sr_94_BI_ETC___d602 } ; + IF_fork0_srcF_first__50_BITS_39_TO_38_51_EQ_0__ETC___d393 : + { IF_SEL_ARR_fork0_sr_94_BITS_39_TO_38_08_EQ_0_0_ETC___d526, + IF_SEL_ARR_fork0_sr_94_BITS_29_TO_28_27_EQ_0_2_ETC___d545, + IF_SEL_ARR_fork0_sr_94_BITS_19_TO_18_47_EQ_0_4_ETC___d565, + IF_SEL_ARR_fork0_sr_94_BITS_9_TO_8_66_EQ_0_67__ETC___d584 } ; assign fork0_d0F$ENQ = WILL_FIRE_RL_fork0_egress && fork0_match0 ; assign fork0_d0F$DEQ = EN_client0_request_get ; assign fork0_d0F$CLR = 1'b0 ; @@ -1187,13 +1187,13 @@ module mkQABSMF3(et0, // submodule fork0_srcF assign fork0_srcF$D_IN = - { CASE_server_request_put_BITS_39_TO_38_3_0_serv_ETC__q73, + { CASE_server_request_put_BITS_39_TO_38_0_server_ETC__q73, server_request_put[37:30], - CASE_server_request_put_BITS_29_TO_28_3_0_serv_ETC__q74, + CASE_server_request_put_BITS_29_TO_28_0_server_ETC__q74, server_request_put[27:20], - CASE_server_request_put_BITS_19_TO_18_3_0_serv_ETC__q75, + CASE_server_request_put_BITS_19_TO_18_0_server_ETC__q75, server_request_put[17:10], - CASE_server_request_put_BITS_9_TO_8_3_0_server_ETC__q76, + CASE_server_request_put_BITS_9_TO_8_0_server_r_ETC__q76, server_request_put[7:0] } ; assign fork0_srcF$ENQ = EN_server_request_put ; assign fork0_srcF$DEQ = @@ -1204,11 +1204,11 @@ module mkQABSMF3(et0, // submodule fork1_d0F assign fork1_d0F$D_IN = fork1_stageSent ? - IF_fork1_srcF_first__17_BITS_39_TO_38_18_EQ_0__ETC___d1359 : - { IF_IF_fork1_ptr_57_EQ_0_75_THEN_fork1_sr_61_BI_ETC___d799, - IF_IF_fork1_ptr_57_EQ_0_75_THEN_fork1_sr_61_BI_ETC___d822, - IF_IF_fork1_ptr_57_EQ_0_75_THEN_fork1_sr_61_BI_ETC___d846, - IF_IF_fork1_ptr_57_EQ_0_75_THEN_fork1_sr_61_BI_ETC___d869 } ; + IF_fork1_srcF_first__99_BITS_39_TO_38_00_EQ_0__ETC___d642 : + { IF_SEL_ARR_fork1_sr_43_BITS_39_TO_38_57_EQ_0_5_ETC___d775, + IF_SEL_ARR_fork1_sr_43_BITS_29_TO_28_76_EQ_0_7_ETC___d794, + IF_SEL_ARR_fork1_sr_43_BITS_19_TO_18_96_EQ_0_9_ETC___d814, + IF_SEL_ARR_fork1_sr_43_BITS_9_TO_8_15_EQ_0_16__ETC___d833 } ; assign fork1_d0F$ENQ = WILL_FIRE_RL_fork1_egress && fork1_match0 ; assign fork1_d0F$DEQ = EN_client1_request_get ; assign fork1_d0F$CLR = 1'b0 ; @@ -1221,13 +1221,13 @@ module mkQABSMF3(et0, // submodule fork1_srcF assign fork1_srcF$D_IN = - { CASE_fork0_d1FD_OUT_BITS_39_TO_38_3_0_fork0_d_ETC__q85, + { CASE_fork0_d1FD_OUT_BITS_39_TO_38_0_fork0_d1F_ETC__q85, fork0_d1F$D_OUT[37:30], - CASE_fork0_d1FD_OUT_BITS_29_TO_28_3_0_fork0_d_ETC__q86, + CASE_fork0_d1FD_OUT_BITS_29_TO_28_0_fork0_d1F_ETC__q86, fork0_d1F$D_OUT[27:20], - CASE_fork0_d1FD_OUT_BITS_19_TO_18_3_0_fork0_d_ETC__q87, + CASE_fork0_d1FD_OUT_BITS_19_TO_18_0_fork0_d1F_ETC__q87, fork0_d1F$D_OUT[17:10], - CASE_fork0_d1FD_OUT_BITS_9_TO_8_3_0_fork0_d1F_ETC__q88, + CASE_fork0_d1FD_OUT_BITS_9_TO_8_0_fork0_d1FD_ETC__q88, fork0_d1F$D_OUT[7:0] } ; assign fork1_srcF$ENQ = fork0_d1F$EMPTY_N && fork1_srcF$FULL_N ; assign fork1_srcF$DEQ = @@ -1237,13 +1237,13 @@ module mkQABSMF3(et0, // submodule merge0_fi0 assign merge0_fi0$D_IN = - { CASE_client0_response_put_BITS_39_TO_38_3_0_cl_ETC__q89, + { CASE_client0_response_put_BITS_39_TO_38_0_clie_ETC__q89, client0_response_put[37:30], - CASE_client0_response_put_BITS_29_TO_28_3_0_cl_ETC__q90, + CASE_client0_response_put_BITS_29_TO_28_0_clie_ETC__q90, client0_response_put[27:20], - CASE_client0_response_put_BITS_19_TO_18_3_0_cl_ETC__q91, + CASE_client0_response_put_BITS_19_TO_18_0_clie_ETC__q91, client0_response_put[17:10], - CASE_client0_response_put_BITS_9_TO_8_3_0_clie_ETC__q92, + CASE_client0_response_put_BITS_9_TO_8_0_client_ETC__q92, client0_response_put[7:0] } ; assign merge0_fi0$ENQ = EN_client0_response_put ; assign merge0_fi0$DEQ = @@ -1253,13 +1253,13 @@ module mkQABSMF3(et0, // submodule merge0_fi1 assign merge0_fi1$D_IN = - { CASE_merge1_foD_OUT_BITS_39_TO_38_3_0_merge1__ETC__q93, + { CASE_merge1_foD_OUT_BITS_39_TO_38_0_merge1_fo_ETC__q93, merge1_fo$D_OUT[37:30], - CASE_merge1_foD_OUT_BITS_29_TO_28_3_0_merge1__ETC__q94, + CASE_merge1_foD_OUT_BITS_29_TO_28_0_merge1_fo_ETC__q94, merge1_fo$D_OUT[27:20], - CASE_merge1_foD_OUT_BITS_19_TO_18_3_0_merge1__ETC__q95, + CASE_merge1_foD_OUT_BITS_19_TO_18_0_merge1_fo_ETC__q95, merge1_fo$D_OUT[17:10], - CASE_merge1_foD_OUT_BITS_9_TO_8_3_0_merge1_fo_ETC__q96, + CASE_merge1_foD_OUT_BITS_9_TO_8_0_merge1_foD_ETC__q96, merge1_fo$D_OUT[7:0] } ; assign merge0_fi1$ENQ = merge1_fo$EMPTY_N && merge0_fi1$FULL_N ; assign merge0_fi1$DEQ = @@ -1293,13 +1293,13 @@ module mkQABSMF3(et0, // submodule merge1_fi0 assign merge1_fi0$D_IN = - { CASE_client1_response_put_BITS_39_TO_38_3_0_cl_ETC__q97, + { CASE_client1_response_put_BITS_39_TO_38_0_clie_ETC__q97, client1_response_put[37:30], - CASE_client1_response_put_BITS_29_TO_28_3_0_cl_ETC__q98, + CASE_client1_response_put_BITS_29_TO_28_0_clie_ETC__q98, client1_response_put[27:20], - CASE_client1_response_put_BITS_19_TO_18_3_0_cl_ETC__q99, + CASE_client1_response_put_BITS_19_TO_18_0_clie_ETC__q99, client1_response_put[17:10], - CASE_client1_response_put_BITS_9_TO_8_3_0_clie_ETC__q100, + CASE_client1_response_put_BITS_9_TO_8_0_client_ETC__q100, client1_response_put[7:0] } ; assign merge1_fi0$ENQ = EN_client1_response_put ; assign merge1_fi0$DEQ = @@ -1309,13 +1309,13 @@ module mkQABSMF3(et0, // submodule merge1_fi1 assign merge1_fi1$D_IN = - { CASE_client2_response_put_BITS_39_TO_38_3_0_cl_ETC__q101, + { CASE_client2_response_put_BITS_39_TO_38_0_clie_ETC__q101, client2_response_put[37:30], - CASE_client2_response_put_BITS_29_TO_28_3_0_cl_ETC__q102, + CASE_client2_response_put_BITS_29_TO_28_0_clie_ETC__q102, client2_response_put[27:20], - CASE_client2_response_put_BITS_19_TO_18_3_0_cl_ETC__q103, + CASE_client2_response_put_BITS_19_TO_18_0_clie_ETC__q103, client2_response_put[17:10], - CASE_client2_response_put_BITS_9_TO_8_3_0_clie_ETC__q104, + CASE_client2_response_put_BITS_9_TO_8_0_client_ETC__q104, client2_response_put[7:0] } ; assign merge1_fi1$ENQ = EN_client2_response_put ; assign merge1_fi1$DEQ = @@ -1348,126 +1348,6 @@ module mkQABSMF3(et0, assign merge1_fo$CLR = 1'b0 ; // remaining internal signals - assign IF_IF_fork0_ptr_90_EQ_0_08_THEN_fork0_sr_94_BI_ETC___d530 = - { CASE_fork0_ptr_fork0_ptr_EQ_2_AND_fork0_sr_BIT_ETC__q17 ? - 2'd2 : - 2'd3, - IF_fork0_ptr_90_EQ_0_08_THEN_fork0_sr_94_BITS__ETC___d1350 } ; - assign IF_IF_fork0_ptr_90_EQ_0_08_THEN_fork0_sr_94_BI_ETC___d531 = - CASE_fork0_ptr_fork0_ptr_EQ_2_AND_fork0_sr_BIT_ETC__q18 ? - { 2'd1, - IF_fork0_ptr_90_EQ_0_08_THEN_fork0_sr_94_BITS__ETC___d1350 } : - IF_IF_fork0_ptr_90_EQ_0_08_THEN_fork0_sr_94_BI_ETC___d530 ; - assign IF_IF_fork0_ptr_90_EQ_0_08_THEN_fork0_sr_94_BI_ETC___d532 = - CASE_fork0_ptr_fork0_ptr_EQ_2_AND_fork0_sr_BIT_ETC__q19 ? - { 2'd0, - IF_fork0_ptr_90_EQ_0_08_THEN_fork0_sr_94_BITS__ETC___d1350 } : - IF_IF_fork0_ptr_90_EQ_0_08_THEN_fork0_sr_94_BI_ETC___d531 ; - assign IF_IF_fork0_ptr_90_EQ_0_08_THEN_fork0_sr_94_BI_ETC___d553 = - { CASE_fork0_ptr_fork0_ptr_EQ_2_AND_fork0_sr_BIT_ETC__q20 ? - 2'd2 : - 2'd3, - IF_fork0_ptr_90_EQ_0_08_THEN_fork0_sr_94_BITS__ETC___d1351 } ; - assign IF_IF_fork0_ptr_90_EQ_0_08_THEN_fork0_sr_94_BI_ETC___d554 = - CASE_fork0_ptr_fork0_ptr_EQ_2_AND_fork0_sr_BIT_ETC__q21 ? - { 2'd1, - IF_fork0_ptr_90_EQ_0_08_THEN_fork0_sr_94_BITS__ETC___d1351 } : - IF_IF_fork0_ptr_90_EQ_0_08_THEN_fork0_sr_94_BI_ETC___d553 ; - assign IF_IF_fork0_ptr_90_EQ_0_08_THEN_fork0_sr_94_BI_ETC___d555 = - CASE_fork0_ptr_fork0_ptr_EQ_2_AND_fork0_sr_BIT_ETC__q22 ? - { 2'd0, - IF_fork0_ptr_90_EQ_0_08_THEN_fork0_sr_94_BITS__ETC___d1351 } : - IF_IF_fork0_ptr_90_EQ_0_08_THEN_fork0_sr_94_BI_ETC___d554 ; - assign IF_IF_fork0_ptr_90_EQ_0_08_THEN_fork0_sr_94_BI_ETC___d577 = - { CASE_fork0_ptr_fork0_ptr_EQ_2_AND_fork0_sr_BIT_ETC__q23 ? - 2'd2 : - 2'd3, - IF_fork0_ptr_90_EQ_0_08_THEN_fork0_sr_94_BITS__ETC___d1352 } ; - assign IF_IF_fork0_ptr_90_EQ_0_08_THEN_fork0_sr_94_BI_ETC___d578 = - CASE_fork0_ptr_fork0_ptr_EQ_2_AND_fork0_sr_BIT_ETC__q24 ? - { 2'd1, - IF_fork0_ptr_90_EQ_0_08_THEN_fork0_sr_94_BITS__ETC___d1352 } : - IF_IF_fork0_ptr_90_EQ_0_08_THEN_fork0_sr_94_BI_ETC___d577 ; - assign IF_IF_fork0_ptr_90_EQ_0_08_THEN_fork0_sr_94_BI_ETC___d579 = - CASE_fork0_ptr_fork0_ptr_EQ_2_AND_fork0_sr_BIT_ETC__q25 ? - { 2'd0, - IF_fork0_ptr_90_EQ_0_08_THEN_fork0_sr_94_BITS__ETC___d1352 } : - IF_IF_fork0_ptr_90_EQ_0_08_THEN_fork0_sr_94_BI_ETC___d578 ; - assign IF_IF_fork0_ptr_90_EQ_0_08_THEN_fork0_sr_94_BI_ETC___d600 = - { CASE_fork0_ptr_fork0_ptr_EQ_2_AND_fork0_sr_BIT_ETC__q26 ? - 2'd2 : - 2'd3, - IF_fork0_ptr_90_EQ_0_08_THEN_fork0_sr_94_BITS__ETC___d1353 } ; - assign IF_IF_fork0_ptr_90_EQ_0_08_THEN_fork0_sr_94_BI_ETC___d601 = - CASE_fork0_ptr_fork0_ptr_EQ_2_AND_fork0_sr_BIT_ETC__q27 ? - { 2'd1, - IF_fork0_ptr_90_EQ_0_08_THEN_fork0_sr_94_BITS__ETC___d1353 } : - IF_IF_fork0_ptr_90_EQ_0_08_THEN_fork0_sr_94_BI_ETC___d600 ; - assign IF_IF_fork0_ptr_90_EQ_0_08_THEN_fork0_sr_94_BI_ETC___d602 = - CASE_fork0_ptr_fork0_ptr_EQ_2_AND_fork0_sr_BIT_ETC__q28 ? - { 2'd0, - IF_fork0_ptr_90_EQ_0_08_THEN_fork0_sr_94_BITS__ETC___d1353 } : - IF_IF_fork0_ptr_90_EQ_0_08_THEN_fork0_sr_94_BI_ETC___d601 ; - assign IF_IF_fork1_ptr_57_EQ_0_75_THEN_fork1_sr_61_BI_ETC___d797 = - { CASE_fork1_ptr_fork1_ptr_EQ_2_AND_fork1_sr_BIT_ETC__q29 ? - 2'd2 : - 2'd3, - IF_fork1_ptr_57_EQ_0_75_THEN_fork1_sr_61_BITS__ETC___d1354 } ; - assign IF_IF_fork1_ptr_57_EQ_0_75_THEN_fork1_sr_61_BI_ETC___d798 = - CASE_fork1_ptr_fork1_ptr_EQ_2_AND_fork1_sr_BIT_ETC__q30 ? - { 2'd1, - IF_fork1_ptr_57_EQ_0_75_THEN_fork1_sr_61_BITS__ETC___d1354 } : - IF_IF_fork1_ptr_57_EQ_0_75_THEN_fork1_sr_61_BI_ETC___d797 ; - assign IF_IF_fork1_ptr_57_EQ_0_75_THEN_fork1_sr_61_BI_ETC___d799 = - CASE_fork1_ptr_fork1_ptr_EQ_2_AND_fork1_sr_BIT_ETC__q31 ? - { 2'd0, - IF_fork1_ptr_57_EQ_0_75_THEN_fork1_sr_61_BITS__ETC___d1354 } : - IF_IF_fork1_ptr_57_EQ_0_75_THEN_fork1_sr_61_BI_ETC___d798 ; - assign IF_IF_fork1_ptr_57_EQ_0_75_THEN_fork1_sr_61_BI_ETC___d820 = - { CASE_fork1_ptr_fork1_ptr_EQ_2_AND_fork1_sr_BIT_ETC__q32 ? - 2'd2 : - 2'd3, - IF_fork1_ptr_57_EQ_0_75_THEN_fork1_sr_61_BITS__ETC___d1355 } ; - assign IF_IF_fork1_ptr_57_EQ_0_75_THEN_fork1_sr_61_BI_ETC___d821 = - CASE_fork1_ptr_fork1_ptr_EQ_2_AND_fork1_sr_BIT_ETC__q33 ? - { 2'd1, - IF_fork1_ptr_57_EQ_0_75_THEN_fork1_sr_61_BITS__ETC___d1355 } : - IF_IF_fork1_ptr_57_EQ_0_75_THEN_fork1_sr_61_BI_ETC___d820 ; - assign IF_IF_fork1_ptr_57_EQ_0_75_THEN_fork1_sr_61_BI_ETC___d822 = - CASE_fork1_ptr_fork1_ptr_EQ_2_AND_fork1_sr_BIT_ETC__q34 ? - { 2'd0, - IF_fork1_ptr_57_EQ_0_75_THEN_fork1_sr_61_BITS__ETC___d1355 } : - IF_IF_fork1_ptr_57_EQ_0_75_THEN_fork1_sr_61_BI_ETC___d821 ; - assign IF_IF_fork1_ptr_57_EQ_0_75_THEN_fork1_sr_61_BI_ETC___d844 = - { CASE_fork1_ptr_fork1_ptr_EQ_2_AND_fork1_sr_BIT_ETC__q35 ? - 2'd2 : - 2'd3, - IF_fork1_ptr_57_EQ_0_75_THEN_fork1_sr_61_BITS__ETC___d1356 } ; - assign IF_IF_fork1_ptr_57_EQ_0_75_THEN_fork1_sr_61_BI_ETC___d845 = - CASE_fork1_ptr_fork1_ptr_EQ_2_AND_fork1_sr_BIT_ETC__q36 ? - { 2'd1, - IF_fork1_ptr_57_EQ_0_75_THEN_fork1_sr_61_BITS__ETC___d1356 } : - IF_IF_fork1_ptr_57_EQ_0_75_THEN_fork1_sr_61_BI_ETC___d844 ; - assign IF_IF_fork1_ptr_57_EQ_0_75_THEN_fork1_sr_61_BI_ETC___d846 = - CASE_fork1_ptr_fork1_ptr_EQ_2_AND_fork1_sr_BIT_ETC__q37 ? - { 2'd0, - IF_fork1_ptr_57_EQ_0_75_THEN_fork1_sr_61_BITS__ETC___d1356 } : - IF_IF_fork1_ptr_57_EQ_0_75_THEN_fork1_sr_61_BI_ETC___d845 ; - assign IF_IF_fork1_ptr_57_EQ_0_75_THEN_fork1_sr_61_BI_ETC___d867 = - { CASE_fork1_ptr_fork1_ptr_EQ_2_AND_fork1_sr_BIT_ETC__q38 ? - 2'd2 : - 2'd3, - IF_fork1_ptr_57_EQ_0_75_THEN_fork1_sr_61_BITS__ETC___d1357 } ; - assign IF_IF_fork1_ptr_57_EQ_0_75_THEN_fork1_sr_61_BI_ETC___d868 = - CASE_fork1_ptr_fork1_ptr_EQ_2_AND_fork1_sr_BIT_ETC__q39 ? - { 2'd1, - IF_fork1_ptr_57_EQ_0_75_THEN_fork1_sr_61_BITS__ETC___d1357 } : - IF_IF_fork1_ptr_57_EQ_0_75_THEN_fork1_sr_61_BI_ETC___d867 ; - assign IF_IF_fork1_ptr_57_EQ_0_75_THEN_fork1_sr_61_BI_ETC___d869 = - CASE_fork1_ptr_fork1_ptr_EQ_2_AND_fork1_sr_BIT_ETC__q40 ? - { 2'd0, - IF_fork1_ptr_57_EQ_0_75_THEN_fork1_sr_61_BITS__ETC___d1357 } : - IF_IF_fork1_ptr_57_EQ_0_75_THEN_fork1_sr_61_BI_ETC___d868 ; assign IF_IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_fir_ETC___d133 = (merge0_fi0HasPrio ? merge0_fi0$D_OUT[39:38] == 2'd2 : @@ -1479,9 +1359,9 @@ module mkQABSMF3(et0, merge0_fi0$D_OUT[39:38] == 2'd1 : merge0_fi1$D_OUT[39:38] == 2'd1) ? { 2'd1, - IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1343 } : + IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d128 } : { IF_IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_fir_ETC___d133, - IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1343 } ; + IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d128 } ; assign IF_IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_fir_ETC___d143 = (merge0_fi0HasPrio ? merge0_fi0$D_OUT[29:28] == 2'd2 : @@ -1493,17 +1373,17 @@ module mkQABSMF3(et0, merge0_fi0$D_OUT[29:28] == 2'd1 : merge0_fi1$D_OUT[29:28] == 2'd1) ? { 2'd1, - IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1344 } : + IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d138 } : { IF_IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_fir_ETC___d143, - IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1344 } ; + IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d138 } ; assign IF_IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_fir_ETC___d147 = - { IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1334 ? + { IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d127 ? { 2'd0, - IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1343 } : + IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d128 } : IF_IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_fir_ETC___d135, - IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1327 ? + IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d137 ? { 2'd0, - IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1344 } : + IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d138 } : IF_IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_fir_ETC___d145 } ; assign IF_IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_fir_ETC___d154 = (merge0_fi0HasPrio ? @@ -1516,9 +1396,9 @@ module mkQABSMF3(et0, merge0_fi0$D_OUT[19:18] == 2'd1 : merge0_fi1$D_OUT[19:18] == 2'd1) ? { 2'd1, - IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1345 } : + IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d149 } : { IF_IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_fir_ETC___d154, - IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1345 } ; + IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d149 } ; assign IF_IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_fir_ETC___d164 = (merge0_fi0HasPrio ? merge0_fi0$D_OUT[9:8] == 2'd2 : @@ -1530,9 +1410,9 @@ module mkQABSMF3(et0, merge0_fi0$D_OUT[9:8] == 2'd1 : merge0_fi1$D_OUT[9:8] == 2'd1) ? { 2'd1, - IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1346 } : + IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d159 } : { IF_IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_fir_ETC___d164, - IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1346 } ; + IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d159 } ; assign IF_IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_fir_ETC___d304 = (merge1_fi0HasPrio ? merge1_fi0$D_OUT[39:38] == 2'd2 : @@ -1544,9 +1424,9 @@ module mkQABSMF3(et0, merge1_fi0$D_OUT[39:38] == 2'd1 : merge1_fi1$D_OUT[39:38] == 2'd1) ? { 2'd1, - IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_first__ETC___d1347 } : + IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_first__ETC___d299 } : { IF_IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_fir_ETC___d304, - IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_first__ETC___d1347 } ; + IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_first__ETC___d299 } ; assign IF_IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_fir_ETC___d314 = (merge1_fi0HasPrio ? merge1_fi0$D_OUT[29:28] == 2'd2 : @@ -1558,17 +1438,17 @@ module mkQABSMF3(et0, merge1_fi0$D_OUT[29:28] == 2'd1 : merge1_fi1$D_OUT[29:28] == 2'd1) ? { 2'd1, - IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_first__ETC___d1348 } : + IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_first__ETC___d309 } : { IF_IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_fir_ETC___d314, - IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_first__ETC___d1348 } ; + IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_first__ETC___d309 } ; assign IF_IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_fir_ETC___d318 = - { IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_first__ETC___d1333 ? + { IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_first__ETC___d298 ? { 2'd0, - IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_first__ETC___d1347 } : + IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_first__ETC___d299 } : IF_IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_fir_ETC___d306, - IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_first__ETC___d1668 ? + IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_first__ETC___d308 ? { 2'd0, - IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_first__ETC___d1348 } : + IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_first__ETC___d309 } : IF_IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_fir_ETC___d316 } ; assign IF_IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_fir_ETC___d325 = (merge1_fi0HasPrio ? @@ -1581,9 +1461,9 @@ module mkQABSMF3(et0, merge1_fi0$D_OUT[19:18] == 2'd1 : merge1_fi1$D_OUT[19:18] == 2'd1) ? { 2'd1, - IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_first__ETC___d1349 } : + IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_first__ETC___d320 } : { IF_IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_fir_ETC___d325, - IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_first__ETC___d1349 } ; + IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_first__ETC___d320 } ; assign IF_IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_fir_ETC___d335 = (merge1_fi0HasPrio ? merge1_fi0$D_OUT[9:8] == 2'd2 : @@ -1595,1261 +1475,1477 @@ module mkQABSMF3(et0, merge1_fi0$D_OUT[9:8] == 2'd1 : merge1_fi1$D_OUT[9:8] == 2'd1) ? { 2'd1, - IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_first__ETC___d1321 } : + IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_first__ETC___d330 } : { IF_IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_fir_ETC___d335, - IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_first__ETC___d1321 } ; - assign IF_fork0_srcF_first__50_BITS_39_TO_38_51_EQ_0__ETC___d1358 = - { CASE_fork0_srcFD_OUT_BITS_39_TO_38_3_0_fork0__ETC__q41, + IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_first__ETC___d330 } ; + assign IF_SEL_ARR_fork0_sr_94_BITS_19_TO_18_47_EQ_0_4_ETC___d565 = + CASE_fork0_ptr_0_fork0_sr_BITS_19_TO_18_EQ_0_1_ETC__q39 ? + { 2'd0, + SEL_ARR_fork0_sr_94_BITS_17_TO_10_51_fork0_sr__ETC___d553 } : + IF_SEL_ARR_fork0_sr_94_BITS_19_TO_18_47_EQ_1_5_ETC___d564 ; + assign IF_SEL_ARR_fork0_sr_94_BITS_19_TO_18_47_EQ_1_5_ETC___d564 = + CASE_fork0_ptr_0_fork0_sr_BITS_19_TO_18_EQ_1_1_ETC__q38 ? + { 2'd1, + SEL_ARR_fork0_sr_94_BITS_17_TO_10_51_fork0_sr__ETC___d553 } : + IF_SEL_ARR_fork0_sr_94_BITS_19_TO_18_47_EQ_2_5_ETC___d563 ; + assign IF_SEL_ARR_fork0_sr_94_BITS_19_TO_18_47_EQ_2_5_ETC___d563 = + { CASE_fork0_ptr_0_fork0_sr_BITS_19_TO_18_EQ_2_1_ETC__q37 ? + 2'd2 : + 2'd3, + SEL_ARR_fork0_sr_94_BITS_17_TO_10_51_fork0_sr__ETC___d553 } ; + assign IF_SEL_ARR_fork0_sr_94_BITS_29_TO_28_27_EQ_0_2_ETC___d545 = + CASE_fork0_ptr_0_fork0_sr_BITS_29_TO_28_EQ_0_1_ETC__q22 ? + { 2'd0, + SEL_ARR_fork0_sr_94_BITS_27_TO_20_31_fork0_sr__ETC___d533 } : + IF_SEL_ARR_fork0_sr_94_BITS_29_TO_28_27_EQ_1_3_ETC___d544 ; + assign IF_SEL_ARR_fork0_sr_94_BITS_29_TO_28_27_EQ_1_3_ETC___d544 = + CASE_fork0_ptr_0_fork0_sr_BITS_29_TO_28_EQ_1_1_ETC__q21 ? + { 2'd1, + SEL_ARR_fork0_sr_94_BITS_27_TO_20_31_fork0_sr__ETC___d533 } : + IF_SEL_ARR_fork0_sr_94_BITS_29_TO_28_27_EQ_2_3_ETC___d543 ; + assign IF_SEL_ARR_fork0_sr_94_BITS_29_TO_28_27_EQ_2_3_ETC___d543 = + { CASE_fork0_ptr_0_fork0_sr_BITS_29_TO_28_EQ_2_1_ETC__q20 ? + 2'd2 : + 2'd3, + SEL_ARR_fork0_sr_94_BITS_27_TO_20_31_fork0_sr__ETC___d533 } ; + assign IF_SEL_ARR_fork0_sr_94_BITS_39_TO_38_08_EQ_0_0_ETC___d526 = + CASE_fork0_ptr_0_fork0_sr_BITS_39_TO_38_EQ_0_1_ETC__q19 ? + { 2'd0, + SEL_ARR_fork0_sr_94_BITS_37_TO_30_12_fork0_sr__ETC___d514 } : + IF_SEL_ARR_fork0_sr_94_BITS_39_TO_38_08_EQ_1_1_ETC___d525 ; + assign IF_SEL_ARR_fork0_sr_94_BITS_39_TO_38_08_EQ_1_1_ETC___d525 = + CASE_fork0_ptr_0_fork0_sr_BITS_39_TO_38_EQ_1_1_ETC__q18 ? + { 2'd1, + SEL_ARR_fork0_sr_94_BITS_37_TO_30_12_fork0_sr__ETC___d514 } : + IF_SEL_ARR_fork0_sr_94_BITS_39_TO_38_08_EQ_2_2_ETC___d524 ; + assign IF_SEL_ARR_fork0_sr_94_BITS_39_TO_38_08_EQ_2_2_ETC___d524 = + { CASE_fork0_ptr_0_fork0_sr_BITS_39_TO_38_EQ_2_1_ETC__q17 ? + 2'd2 : + 2'd3, + SEL_ARR_fork0_sr_94_BITS_37_TO_30_12_fork0_sr__ETC___d514 } ; + assign IF_SEL_ARR_fork0_sr_94_BITS_9_TO_8_66_EQ_0_67__ETC___d584 = + CASE_fork0_ptr_0_fork0_sr_BITS_9_TO_8_EQ_0_1_f_ETC__q42 ? + { 2'd0, + SEL_ARR_fork0_sr_94_BITS_7_TO_0_70_fork0_sr_94_ETC___d572 } : + IF_SEL_ARR_fork0_sr_94_BITS_9_TO_8_66_EQ_1_74__ETC___d583 ; + assign IF_SEL_ARR_fork0_sr_94_BITS_9_TO_8_66_EQ_1_74__ETC___d583 = + CASE_fork0_ptr_0_fork0_sr_BITS_9_TO_8_EQ_1_1_f_ETC__q41 ? + { 2'd1, + SEL_ARR_fork0_sr_94_BITS_7_TO_0_70_fork0_sr_94_ETC___d572 } : + IF_SEL_ARR_fork0_sr_94_BITS_9_TO_8_66_EQ_2_78__ETC___d582 ; + assign IF_SEL_ARR_fork0_sr_94_BITS_9_TO_8_66_EQ_2_78__ETC___d582 = + { CASE_fork0_ptr_0_fork0_sr_BITS_9_TO_8_EQ_2_1_f_ETC__q40 ? + 2'd2 : + 2'd3, + SEL_ARR_fork0_sr_94_BITS_7_TO_0_70_fork0_sr_94_ETC___d572 } ; + assign IF_SEL_ARR_fork1_sr_43_BITS_19_TO_18_96_EQ_0_9_ETC___d814 = + CASE_fork1_ptr_0_fork1_sr_BITS_19_TO_18_EQ_0_1_ETC__q45 ? + { 2'd0, + SEL_ARR_fork1_sr_43_BITS_17_TO_10_00_fork1_sr__ETC___d802 } : + IF_SEL_ARR_fork1_sr_43_BITS_19_TO_18_96_EQ_1_0_ETC___d813 ; + assign IF_SEL_ARR_fork1_sr_43_BITS_19_TO_18_96_EQ_1_0_ETC___d813 = + CASE_fork1_ptr_0_fork1_sr_BITS_19_TO_18_EQ_1_1_ETC__q44 ? + { 2'd1, + SEL_ARR_fork1_sr_43_BITS_17_TO_10_00_fork1_sr__ETC___d802 } : + IF_SEL_ARR_fork1_sr_43_BITS_19_TO_18_96_EQ_2_0_ETC___d812 ; + assign IF_SEL_ARR_fork1_sr_43_BITS_19_TO_18_96_EQ_2_0_ETC___d812 = + { CASE_fork1_ptr_0_fork1_sr_BITS_19_TO_18_EQ_2_1_ETC__q43 ? + 2'd2 : + 2'd3, + SEL_ARR_fork1_sr_43_BITS_17_TO_10_00_fork1_sr__ETC___d802 } ; + assign IF_SEL_ARR_fork1_sr_43_BITS_29_TO_28_76_EQ_0_7_ETC___d794 = + CASE_fork1_ptr_0_fork1_sr_BITS_29_TO_28_EQ_0_1_ETC__q36 ? + { 2'd0, + SEL_ARR_fork1_sr_43_BITS_27_TO_20_80_fork1_sr__ETC___d782 } : + IF_SEL_ARR_fork1_sr_43_BITS_29_TO_28_76_EQ_1_8_ETC___d793 ; + assign IF_SEL_ARR_fork1_sr_43_BITS_29_TO_28_76_EQ_1_8_ETC___d793 = + CASE_fork1_ptr_0_fork1_sr_BITS_29_TO_28_EQ_1_1_ETC__q35 ? + { 2'd1, + SEL_ARR_fork1_sr_43_BITS_27_TO_20_80_fork1_sr__ETC___d782 } : + IF_SEL_ARR_fork1_sr_43_BITS_29_TO_28_76_EQ_2_8_ETC___d792 ; + assign IF_SEL_ARR_fork1_sr_43_BITS_29_TO_28_76_EQ_2_8_ETC___d792 = + { CASE_fork1_ptr_0_fork1_sr_BITS_29_TO_28_EQ_2_1_ETC__q34 ? + 2'd2 : + 2'd3, + SEL_ARR_fork1_sr_43_BITS_27_TO_20_80_fork1_sr__ETC___d782 } ; + assign IF_SEL_ARR_fork1_sr_43_BITS_39_TO_38_57_EQ_0_5_ETC___d775 = + CASE_fork1_ptr_0_fork1_sr_BITS_39_TO_38_EQ_0_1_ETC__q33 ? + { 2'd0, + SEL_ARR_fork1_sr_43_BITS_37_TO_30_61_fork1_sr__ETC___d763 } : + IF_SEL_ARR_fork1_sr_43_BITS_39_TO_38_57_EQ_1_6_ETC___d774 ; + assign IF_SEL_ARR_fork1_sr_43_BITS_39_TO_38_57_EQ_1_6_ETC___d774 = + CASE_fork1_ptr_0_fork1_sr_BITS_39_TO_38_EQ_1_1_ETC__q32 ? + { 2'd1, + SEL_ARR_fork1_sr_43_BITS_37_TO_30_61_fork1_sr__ETC___d763 } : + IF_SEL_ARR_fork1_sr_43_BITS_39_TO_38_57_EQ_2_6_ETC___d773 ; + assign IF_SEL_ARR_fork1_sr_43_BITS_39_TO_38_57_EQ_2_6_ETC___d773 = + { CASE_fork1_ptr_0_fork1_sr_BITS_39_TO_38_EQ_2_1_ETC__q31 ? + 2'd2 : + 2'd3, + SEL_ARR_fork1_sr_43_BITS_37_TO_30_61_fork1_sr__ETC___d763 } ; + assign IF_SEL_ARR_fork1_sr_43_BITS_9_TO_8_15_EQ_0_16__ETC___d833 = + CASE_fork1_ptr_0_fork1_sr_BITS_9_TO_8_EQ_0_1_f_ETC__q48 ? + { 2'd0, + SEL_ARR_fork1_sr_43_BITS_7_TO_0_19_fork1_sr_43_ETC___d821 } : + IF_SEL_ARR_fork1_sr_43_BITS_9_TO_8_15_EQ_1_23__ETC___d832 ; + assign IF_SEL_ARR_fork1_sr_43_BITS_9_TO_8_15_EQ_1_23__ETC___d832 = + CASE_fork1_ptr_0_fork1_sr_BITS_9_TO_8_EQ_1_1_f_ETC__q47 ? + { 2'd1, + SEL_ARR_fork1_sr_43_BITS_7_TO_0_19_fork1_sr_43_ETC___d821 } : + IF_SEL_ARR_fork1_sr_43_BITS_9_TO_8_15_EQ_2_27__ETC___d831 ; + assign IF_SEL_ARR_fork1_sr_43_BITS_9_TO_8_15_EQ_2_27__ETC___d831 = + { CASE_fork1_ptr_0_fork1_sr_BITS_9_TO_8_EQ_2_1_f_ETC__q46 ? + 2'd2 : + 2'd3, + SEL_ARR_fork1_sr_43_BITS_7_TO_0_19_fork1_sr_43_ETC___d821 } ; + assign IF_fork0_srcF_first__50_BITS_39_TO_38_51_EQ_0__ETC___d393 = + { CASE_fork0_srcFD_OUT_BITS_39_TO_38_0_fork0_sr_ETC__q27, fork0_srcF$D_OUT[37:30], - CASE_fork0_srcFD_OUT_BITS_29_TO_28_3_0_fork0__ETC__q42, + CASE_fork0_srcFD_OUT_BITS_29_TO_28_0_fork0_sr_ETC__q28, fork0_srcF$D_OUT[27:20], - CASE_fork0_srcFD_OUT_BITS_19_TO_18_3_0_fork0__ETC__q43, + CASE_fork0_srcFD_OUT_BITS_19_TO_18_0_fork0_sr_ETC__q29, fork0_srcF$D_OUT[17:10], - CASE_fork0_srcFD_OUT_BITS_9_TO_8_3_0_fork0_sr_ETC__q44, + CASE_fork0_srcFD_OUT_BITS_9_TO_8_0_fork0_srcF_ETC__q30, fork0_srcF$D_OUT[7:0] } ; - assign IF_fork1_srcF_first__17_BITS_39_TO_38_18_EQ_0__ETC___d1359 = - { CASE_fork1_srcFD_OUT_BITS_39_TO_38_3_0_fork1__ETC__q45, + assign IF_fork1_srcF_first__99_BITS_39_TO_38_00_EQ_0__ETC___d642 = + { CASE_fork1_srcFD_OUT_BITS_39_TO_38_0_fork1_sr_ETC__q23, fork1_srcF$D_OUT[37:30], - CASE_fork1_srcFD_OUT_BITS_29_TO_28_3_0_fork1__ETC__q46, + CASE_fork1_srcFD_OUT_BITS_29_TO_28_0_fork1_sr_ETC__q24, fork1_srcF$D_OUT[27:20], - CASE_fork1_srcFD_OUT_BITS_19_TO_18_3_0_fork1__ETC__q47, + CASE_fork1_srcFD_OUT_BITS_19_TO_18_0_fork1_sr_ETC__q25, fork1_srcF$D_OUT[17:10], - CASE_fork1_srcFD_OUT_BITS_9_TO_8_3_0_fork1_sr_ETC__q48, + CASE_fork1_srcFD_OUT_BITS_9_TO_8_0_fork1_srcF_ETC__q26, fork1_srcF$D_OUT[7:0] } ; assign IF_merge0_fi0HasPrio_06_THEN_NOT_merge0_fi0_i__ETC___d113 = merge0_fi0HasPrio ? !merge0_fi0$EMPTY_N || merge0_fi0$D_OUT[9:8] != 2'd0 : !merge0_fi1$EMPTY_N || merge0_fi1$D_OUT[9:8] != 2'd0 ; - assign IF_merge0_fi0HasPrio_06_THEN_NOT_merge0_fi0_i__ETC___d1666 = + assign IF_merge0_fi0HasPrio_06_THEN_NOT_merge0_fi0_i__ETC___d115 = IF_merge0_fi0HasPrio_06_THEN_NOT_merge0_fi0_i__ETC___d113 || (merge0_fi0HasPrio ? merge0_fi0$EMPTY_N : merge0_fi1$EMPTY_N) ; - assign IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1327 = - merge0_fi0HasPrio ? - merge0_fi0$D_OUT[29:28] == 2'd0 : - merge0_fi1$D_OUT[29:28] == 2'd0 ; - assign IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1334 = + assign IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d127 = merge0_fi0HasPrio ? merge0_fi0$D_OUT[39:38] == 2'd0 : merge0_fi1$D_OUT[39:38] == 2'd0 ; - assign IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1343 = + assign IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d128 = merge0_fi0HasPrio ? merge0_fi0$D_OUT[37:30] : merge0_fi1$D_OUT[37:30] ; - assign IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1344 = + assign IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d137 = + merge0_fi0HasPrio ? + merge0_fi0$D_OUT[29:28] == 2'd0 : + merge0_fi1$D_OUT[29:28] == 2'd0 ; + assign IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d138 = merge0_fi0HasPrio ? merge0_fi0$D_OUT[27:20] : merge0_fi1$D_OUT[27:20] ; - assign IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1345 = - merge0_fi0HasPrio ? - merge0_fi0$D_OUT[17:10] : - merge0_fi1$D_OUT[17:10] ; - assign IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1346 = - merge0_fi0HasPrio ? - merge0_fi0$D_OUT[7:0] : - merge0_fi1$D_OUT[7:0] ; - assign IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1665 = + assign IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d148 = merge0_fi0HasPrio ? merge0_fi0$D_OUT[19:18] == 2'd0 : merge0_fi1$D_OUT[19:18] == 2'd0 ; - assign IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d1667 = + assign IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d149 = + merge0_fi0HasPrio ? + merge0_fi0$D_OUT[17:10] : + merge0_fi1$D_OUT[17:10] ; + assign IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d158 = merge0_fi0HasPrio ? merge0_fi0$D_OUT[9:8] == 2'd0 : merge0_fi1$D_OUT[9:8] == 2'd0 ; + assign IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d159 = + merge0_fi0HasPrio ? + merge0_fi0$D_OUT[7:0] : + merge0_fi1$D_OUT[7:0] ; assign IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_i_notE_ETC___d118 = merge0_fi0HasPrio ? merge0_fi0$EMPTY_N && - IF_merge0_fi0HasPrio_06_THEN_NOT_merge0_fi0_i__ETC___d1666 : + IF_merge0_fi0HasPrio_06_THEN_NOT_merge0_fi0_i__ETC___d115 : merge0_fi1$EMPTY_N && - IF_merge0_fi0HasPrio_06_THEN_NOT_merge0_fi0_i__ETC___d1666 ; - assign IF_merge1_fi0HasPrio_77_THEN_NOT_merge1_fi0_i__ETC___d1670 = - IF_merge1_fi0HasPrio_77_THEN_NOT_merge1_fi0_i__ETC___d284 || - (merge1_fi0HasPrio ? merge1_fi0$EMPTY_N : merge1_fi1$EMPTY_N) ; + IF_merge0_fi0HasPrio_06_THEN_NOT_merge0_fi0_i__ETC___d115 ; assign IF_merge1_fi0HasPrio_77_THEN_NOT_merge1_fi0_i__ETC___d284 = merge1_fi0HasPrio ? !merge1_fi0$EMPTY_N || merge1_fi0$D_OUT[9:8] != 2'd0 : !merge1_fi1$EMPTY_N || merge1_fi1$D_OUT[9:8] != 2'd0 ; - assign IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_first__ETC___d1321 = - merge1_fi0HasPrio ? - merge1_fi0$D_OUT[7:0] : - merge1_fi1$D_OUT[7:0] ; - assign IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_first__ETC___d1333 = + assign IF_merge1_fi0HasPrio_77_THEN_NOT_merge1_fi0_i__ETC___d286 = + IF_merge1_fi0HasPrio_77_THEN_NOT_merge1_fi0_i__ETC___d284 || + (merge1_fi0HasPrio ? merge1_fi0$EMPTY_N : merge1_fi1$EMPTY_N) ; + assign IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_first__ETC___d298 = merge1_fi0HasPrio ? merge1_fi0$D_OUT[39:38] == 2'd0 : merge1_fi1$D_OUT[39:38] == 2'd0 ; - assign IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_first__ETC___d1347 = + assign IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_first__ETC___d299 = merge1_fi0HasPrio ? merge1_fi0$D_OUT[37:30] : merge1_fi1$D_OUT[37:30] ; - assign IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_first__ETC___d1348 = - merge1_fi0HasPrio ? - merge1_fi0$D_OUT[27:20] : - merge1_fi1$D_OUT[27:20] ; - assign IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_first__ETC___d1349 = - merge1_fi0HasPrio ? - merge1_fi0$D_OUT[17:10] : - merge1_fi1$D_OUT[17:10] ; - assign IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_first__ETC___d1668 = + assign IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_first__ETC___d308 = merge1_fi0HasPrio ? merge1_fi0$D_OUT[29:28] == 2'd0 : merge1_fi1$D_OUT[29:28] == 2'd0 ; - assign IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_first__ETC___d1669 = + assign IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_first__ETC___d309 = + merge1_fi0HasPrio ? + merge1_fi0$D_OUT[27:20] : + merge1_fi1$D_OUT[27:20] ; + assign IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_first__ETC___d319 = merge1_fi0HasPrio ? merge1_fi0$D_OUT[19:18] == 2'd0 : merge1_fi1$D_OUT[19:18] == 2'd0 ; - assign IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_first__ETC___d1671 = + assign IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_first__ETC___d320 = + merge1_fi0HasPrio ? + merge1_fi0$D_OUT[17:10] : + merge1_fi1$D_OUT[17:10] ; + assign IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_first__ETC___d329 = merge1_fi0HasPrio ? merge1_fi0$D_OUT[9:8] == 2'd0 : merge1_fi1$D_OUT[9:8] == 2'd0 ; + assign IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_first__ETC___d330 = + merge1_fi0HasPrio ? + merge1_fi0$D_OUT[7:0] : + merge1_fi1$D_OUT[7:0] ; assign IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_i_notE_ETC___d289 = merge1_fi0HasPrio ? merge1_fi0$EMPTY_N && - IF_merge1_fi0HasPrio_77_THEN_NOT_merge1_fi0_i__ETC___d1670 : + IF_merge1_fi0HasPrio_77_THEN_NOT_merge1_fi0_i__ETC___d286 : merge1_fi1$EMPTY_N && - IF_merge1_fi0HasPrio_77_THEN_NOT_merge1_fi0_i__ETC___d1670 ; + IF_merge1_fi0HasPrio_77_THEN_NOT_merge1_fi0_i__ETC___d286 ; assign NOT_fork0_stageSent_98_99_OR_fork0_srcF_i_notE_ETC___d505 = (!fork0_stageSent || fork0_srcF$EMPTY_N) && (fork0_match0 ? fork0_d0F$FULL_N : fork0_d1F$FULL_N) ; - assign NOT_fork1_stageSent_65_66_OR_fork1_srcF_i_notE_ETC___d772 = + assign NOT_fork1_stageSent_47_48_OR_fork1_srcF_i_notE_ETC___d754 = (!fork1_stageSent || fork1_srcF$EMPTY_N) && (fork1_match0 ? fork1_d0F$FULL_N : fork1_d1F$FULL_N) ; - assign fork0_ptr_90_PLUS_1___d1456 = fork0_ptr + 3'd1 ; - assign fork1_ptr_57_PLUS_1___d1457 = fork1_ptr + 3'd1 ; - assign seen__h15847 = { fork0_srcF$D_OUT[7:0], fork0_srcF$D_OUT[17:10] } ; - assign seen__h26440 = { fork1_srcF$D_OUT[27:20], fork1_srcF$D_OUT[37:30] } ; + assign fork0_ptr_90_PLUS_1___d491 = fork0_ptr + 3'd1 ; + assign fork1_ptr_39_PLUS_1___d740 = fork1_ptr + 3'd1 ; + assign seen__h14989 = { fork0_srcF$D_OUT[7:0], fork0_srcF$D_OUT[17:10] } ; + assign seen__h24820 = { fork1_srcF$D_OUT[27:20], fork1_srcF$D_OUT[37:30] } ; always@(fork1_d0F$D_OUT) begin case (fork1_d0F$D_OUT[39:38]) 2'd0, 2'd1, 2'd2: - CASE_fork1_d0FD_OUT_BITS_39_TO_38_3_0_fork1_d_ETC__q1 = + CASE_fork1_d0FD_OUT_BITS_39_TO_38_0_fork1_d0F_ETC__q1 = fork1_d0F$D_OUT[39:38]; - 2'd3: CASE_fork1_d0FD_OUT_BITS_39_TO_38_3_0_fork1_d_ETC__q1 = 2'd3; + 2'd3: CASE_fork1_d0FD_OUT_BITS_39_TO_38_0_fork1_d0F_ETC__q1 = 2'd3; endcase end always@(fork1_d0F$D_OUT) begin case (fork1_d0F$D_OUT[29:28]) 2'd0, 2'd1, 2'd2: - CASE_fork1_d0FD_OUT_BITS_29_TO_28_3_0_fork1_d_ETC__q2 = + CASE_fork1_d0FD_OUT_BITS_29_TO_28_0_fork1_d0F_ETC__q2 = fork1_d0F$D_OUT[29:28]; - 2'd3: CASE_fork1_d0FD_OUT_BITS_29_TO_28_3_0_fork1_d_ETC__q2 = 2'd3; + 2'd3: CASE_fork1_d0FD_OUT_BITS_29_TO_28_0_fork1_d0F_ETC__q2 = 2'd3; endcase end always@(fork1_d0F$D_OUT) begin case (fork1_d0F$D_OUT[19:18]) 2'd0, 2'd1, 2'd2: - CASE_fork1_d0FD_OUT_BITS_19_TO_18_3_0_fork1_d_ETC__q3 = + CASE_fork1_d0FD_OUT_BITS_19_TO_18_0_fork1_d0F_ETC__q3 = fork1_d0F$D_OUT[19:18]; - 2'd3: CASE_fork1_d0FD_OUT_BITS_19_TO_18_3_0_fork1_d_ETC__q3 = 2'd3; + 2'd3: CASE_fork1_d0FD_OUT_BITS_19_TO_18_0_fork1_d0F_ETC__q3 = 2'd3; endcase end always@(fork1_d0F$D_OUT) begin case (fork1_d0F$D_OUT[9:8]) 2'd0, 2'd1, 2'd2: - CASE_fork1_d0FD_OUT_BITS_9_TO_8_3_0_fork1_d0F_ETC__q4 = + CASE_fork1_d0FD_OUT_BITS_9_TO_8_0_fork1_d0FD_ETC__q4 = fork1_d0F$D_OUT[9:8]; - 2'd3: CASE_fork1_d0FD_OUT_BITS_9_TO_8_3_0_fork1_d0F_ETC__q4 = 2'd3; + 2'd3: CASE_fork1_d0FD_OUT_BITS_9_TO_8_0_fork1_d0FD_ETC__q4 = 2'd3; endcase end always@(fork0_d0F$D_OUT) begin case (fork0_d0F$D_OUT[39:38]) 2'd0, 2'd1, 2'd2: - CASE_fork0_d0FD_OUT_BITS_39_TO_38_3_0_fork0_d_ETC__q5 = + CASE_fork0_d0FD_OUT_BITS_39_TO_38_0_fork0_d0F_ETC__q5 = fork0_d0F$D_OUT[39:38]; - 2'd3: CASE_fork0_d0FD_OUT_BITS_39_TO_38_3_0_fork0_d_ETC__q5 = 2'd3; + 2'd3: CASE_fork0_d0FD_OUT_BITS_39_TO_38_0_fork0_d0F_ETC__q5 = 2'd3; endcase end always@(fork0_d0F$D_OUT) begin case (fork0_d0F$D_OUT[29:28]) 2'd0, 2'd1, 2'd2: - CASE_fork0_d0FD_OUT_BITS_29_TO_28_3_0_fork0_d_ETC__q6 = + CASE_fork0_d0FD_OUT_BITS_29_TO_28_0_fork0_d0F_ETC__q6 = fork0_d0F$D_OUT[29:28]; - 2'd3: CASE_fork0_d0FD_OUT_BITS_29_TO_28_3_0_fork0_d_ETC__q6 = 2'd3; + 2'd3: CASE_fork0_d0FD_OUT_BITS_29_TO_28_0_fork0_d0F_ETC__q6 = 2'd3; endcase end always@(fork0_d0F$D_OUT) begin case (fork0_d0F$D_OUT[19:18]) 2'd0, 2'd1, 2'd2: - CASE_fork0_d0FD_OUT_BITS_19_TO_18_3_0_fork0_d_ETC__q7 = + CASE_fork0_d0FD_OUT_BITS_19_TO_18_0_fork0_d0F_ETC__q7 = fork0_d0F$D_OUT[19:18]; - 2'd3: CASE_fork0_d0FD_OUT_BITS_19_TO_18_3_0_fork0_d_ETC__q7 = 2'd3; + 2'd3: CASE_fork0_d0FD_OUT_BITS_19_TO_18_0_fork0_d0F_ETC__q7 = 2'd3; endcase end always@(fork0_d0F$D_OUT) begin case (fork0_d0F$D_OUT[9:8]) 2'd0, 2'd1, 2'd2: - CASE_fork0_d0FD_OUT_BITS_9_TO_8_3_0_fork0_d0F_ETC__q8 = + CASE_fork0_d0FD_OUT_BITS_9_TO_8_0_fork0_d0FD_ETC__q8 = fork0_d0F$D_OUT[9:8]; - 2'd3: CASE_fork0_d0FD_OUT_BITS_9_TO_8_3_0_fork0_d0F_ETC__q8 = 2'd3; + 2'd3: CASE_fork0_d0FD_OUT_BITS_9_TO_8_0_fork0_d0FD_ETC__q8 = 2'd3; endcase end always@(merge0_fo$D_OUT) begin case (merge0_fo$D_OUT[39:38]) 2'd0, 2'd1, 2'd2: - CASE_merge0_foD_OUT_BITS_39_TO_38_3_0_merge0__ETC__q9 = + CASE_merge0_foD_OUT_BITS_39_TO_38_0_merge0_fo_ETC__q9 = merge0_fo$D_OUT[39:38]; - 2'd3: CASE_merge0_foD_OUT_BITS_39_TO_38_3_0_merge0__ETC__q9 = 2'd3; + 2'd3: CASE_merge0_foD_OUT_BITS_39_TO_38_0_merge0_fo_ETC__q9 = 2'd3; endcase end always@(merge0_fo$D_OUT) begin case (merge0_fo$D_OUT[29:28]) 2'd0, 2'd1, 2'd2: - CASE_merge0_foD_OUT_BITS_29_TO_28_3_0_merge0__ETC__q10 = + CASE_merge0_foD_OUT_BITS_29_TO_28_0_merge0_fo_ETC__q10 = merge0_fo$D_OUT[29:28]; - 2'd3: CASE_merge0_foD_OUT_BITS_29_TO_28_3_0_merge0__ETC__q10 = 2'd3; + 2'd3: CASE_merge0_foD_OUT_BITS_29_TO_28_0_merge0_fo_ETC__q10 = 2'd3; endcase end always@(merge0_fo$D_OUT) begin case (merge0_fo$D_OUT[19:18]) 2'd0, 2'd1, 2'd2: - CASE_merge0_foD_OUT_BITS_19_TO_18_3_0_merge0__ETC__q11 = + CASE_merge0_foD_OUT_BITS_19_TO_18_0_merge0_fo_ETC__q11 = merge0_fo$D_OUT[19:18]; - 2'd3: CASE_merge0_foD_OUT_BITS_19_TO_18_3_0_merge0__ETC__q11 = 2'd3; + 2'd3: CASE_merge0_foD_OUT_BITS_19_TO_18_0_merge0_fo_ETC__q11 = 2'd3; endcase end always@(merge0_fo$D_OUT) begin case (merge0_fo$D_OUT[9:8]) 2'd0, 2'd1, 2'd2: - CASE_merge0_foD_OUT_BITS_9_TO_8_3_0_merge0_fo_ETC__q12 = + CASE_merge0_foD_OUT_BITS_9_TO_8_0_merge0_foD_ETC__q12 = merge0_fo$D_OUT[9:8]; - 2'd3: CASE_merge0_foD_OUT_BITS_9_TO_8_3_0_merge0_fo_ETC__q12 = 2'd3; + 2'd3: CASE_merge0_foD_OUT_BITS_9_TO_8_0_merge0_foD_ETC__q12 = 2'd3; endcase end always@(fork1_d1F$D_OUT) begin case (fork1_d1F$D_OUT[39:38]) 2'd0, 2'd1, 2'd2: - CASE_fork1_d1FD_OUT_BITS_39_TO_38_3_0_fork1_d_ETC__q13 = + CASE_fork1_d1FD_OUT_BITS_39_TO_38_0_fork1_d1F_ETC__q13 = fork1_d1F$D_OUT[39:38]; - 2'd3: CASE_fork1_d1FD_OUT_BITS_39_TO_38_3_0_fork1_d_ETC__q13 = 2'd3; + 2'd3: CASE_fork1_d1FD_OUT_BITS_39_TO_38_0_fork1_d1F_ETC__q13 = 2'd3; endcase end always@(fork1_d1F$D_OUT) begin case (fork1_d1F$D_OUT[29:28]) 2'd0, 2'd1, 2'd2: - CASE_fork1_d1FD_OUT_BITS_29_TO_28_3_0_fork1_d_ETC__q14 = + CASE_fork1_d1FD_OUT_BITS_29_TO_28_0_fork1_d1F_ETC__q14 = fork1_d1F$D_OUT[29:28]; - 2'd3: CASE_fork1_d1FD_OUT_BITS_29_TO_28_3_0_fork1_d_ETC__q14 = 2'd3; + 2'd3: CASE_fork1_d1FD_OUT_BITS_29_TO_28_0_fork1_d1F_ETC__q14 = 2'd3; endcase end always@(fork1_d1F$D_OUT) begin case (fork1_d1F$D_OUT[19:18]) 2'd0, 2'd1, 2'd2: - CASE_fork1_d1FD_OUT_BITS_19_TO_18_3_0_fork1_d_ETC__q15 = + CASE_fork1_d1FD_OUT_BITS_19_TO_18_0_fork1_d1F_ETC__q15 = fork1_d1F$D_OUT[19:18]; - 2'd3: CASE_fork1_d1FD_OUT_BITS_19_TO_18_3_0_fork1_d_ETC__q15 = 2'd3; + 2'd3: CASE_fork1_d1FD_OUT_BITS_19_TO_18_0_fork1_d1F_ETC__q15 = 2'd3; endcase end always@(fork1_d1F$D_OUT) begin case (fork1_d1F$D_OUT[9:8]) 2'd0, 2'd1, 2'd2: - CASE_fork1_d1FD_OUT_BITS_9_TO_8_3_0_fork1_d1F_ETC__q16 = + CASE_fork1_d1FD_OUT_BITS_9_TO_8_0_fork1_d1FD_ETC__q16 = fork1_d1F$D_OUT[9:8]; - 2'd3: CASE_fork1_d1FD_OUT_BITS_9_TO_8_3_0_fork1_d1F_ETC__q16 = 2'd3; + 2'd3: CASE_fork1_d1FD_OUT_BITS_9_TO_8_0_fork1_d1FD_ETC__q16 = 2'd3; endcase end always@(fork0_ptr or fork0_sr) begin case (fork0_ptr) 3'd0: - IF_fork0_ptr_90_EQ_0_08_THEN_fork0_sr_94_BITS__ETC___d1350 = + SEL_ARR_fork0_sr_94_BITS_37_TO_30_12_fork0_sr__ETC___d514 = fork0_sr[37:30]; 3'd1: - IF_fork0_ptr_90_EQ_0_08_THEN_fork0_sr_94_BITS__ETC___d1350 = + SEL_ARR_fork0_sr_94_BITS_37_TO_30_12_fork0_sr__ETC___d514 = fork0_sr[77:70]; - default: IF_fork0_ptr_90_EQ_0_08_THEN_fork0_sr_94_BITS__ETC___d1350 = - fork0_sr[117:110]; + 3'd2: + SEL_ARR_fork0_sr_94_BITS_37_TO_30_12_fork0_sr__ETC___d514 = + fork0_sr[117:110]; + default: SEL_ARR_fork0_sr_94_BITS_37_TO_30_12_fork0_sr__ETC___d514 = + 8'b10101010 /* unspecified value */ ; endcase end always@(fork0_ptr or fork0_sr) begin case (fork0_ptr) 3'd0: - CASE_fork0_ptr_fork0_ptr_EQ_2_AND_fork0_sr_BIT_ETC__q17 = + SEL_ARR_fork0_sr_94_BITS_27_TO_20_31_fork0_sr__ETC___d533 = + fork0_sr[27:20]; + 3'd1: + SEL_ARR_fork0_sr_94_BITS_27_TO_20_31_fork0_sr__ETC___d533 = + fork0_sr[67:60]; + 3'd2: + SEL_ARR_fork0_sr_94_BITS_27_TO_20_31_fork0_sr__ETC___d533 = + fork0_sr[107:100]; + default: SEL_ARR_fork0_sr_94_BITS_27_TO_20_31_fork0_sr__ETC___d533 = + 8'b10101010 /* unspecified value */ ; + endcase + end + always@(fork0_ptr or fork0_sr) + begin + case (fork0_ptr) + 3'd0: + CASE_fork0_ptr_0_fork0_sr_BITS_39_TO_38_EQ_2_1_ETC__q17 = fork0_sr[39:38] == 2'd2; 3'd1: - CASE_fork0_ptr_fork0_ptr_EQ_2_AND_fork0_sr_BIT_ETC__q17 = + CASE_fork0_ptr_0_fork0_sr_BITS_39_TO_38_EQ_2_1_ETC__q17 = fork0_sr[79:78] == 2'd2; - default: CASE_fork0_ptr_fork0_ptr_EQ_2_AND_fork0_sr_BIT_ETC__q17 = - fork0_ptr == 3'd2 && fork0_sr[119:118] == 2'd2; + 3'd2: + CASE_fork0_ptr_0_fork0_sr_BITS_39_TO_38_EQ_2_1_ETC__q17 = + fork0_sr[119:118] == 2'd2; + default: CASE_fork0_ptr_0_fork0_sr_BITS_39_TO_38_EQ_2_1_ETC__q17 = + 1'b0 /* unspecified value */ ; endcase end always@(fork0_ptr or fork0_sr) begin case (fork0_ptr) 3'd0: - CASE_fork0_ptr_fork0_ptr_EQ_2_AND_fork0_sr_BIT_ETC__q18 = + CASE_fork0_ptr_0_fork0_sr_BITS_39_TO_38_EQ_1_1_ETC__q18 = fork0_sr[39:38] == 2'd1; 3'd1: - CASE_fork0_ptr_fork0_ptr_EQ_2_AND_fork0_sr_BIT_ETC__q18 = + CASE_fork0_ptr_0_fork0_sr_BITS_39_TO_38_EQ_1_1_ETC__q18 = fork0_sr[79:78] == 2'd1; - default: CASE_fork0_ptr_fork0_ptr_EQ_2_AND_fork0_sr_BIT_ETC__q18 = - fork0_ptr == 3'd2 && fork0_sr[119:118] == 2'd1; + 3'd2: + CASE_fork0_ptr_0_fork0_sr_BITS_39_TO_38_EQ_1_1_ETC__q18 = + fork0_sr[119:118] == 2'd1; + default: CASE_fork0_ptr_0_fork0_sr_BITS_39_TO_38_EQ_1_1_ETC__q18 = + 1'b0 /* unspecified value */ ; endcase end always@(fork0_ptr or fork0_sr) begin case (fork0_ptr) 3'd0: - CASE_fork0_ptr_fork0_ptr_EQ_2_AND_fork0_sr_BIT_ETC__q19 = + CASE_fork0_ptr_0_fork0_sr_BITS_39_TO_38_EQ_0_1_ETC__q19 = fork0_sr[39:38] == 2'd0; 3'd1: - CASE_fork0_ptr_fork0_ptr_EQ_2_AND_fork0_sr_BIT_ETC__q19 = + CASE_fork0_ptr_0_fork0_sr_BITS_39_TO_38_EQ_0_1_ETC__q19 = fork0_sr[79:78] == 2'd0; - default: CASE_fork0_ptr_fork0_ptr_EQ_2_AND_fork0_sr_BIT_ETC__q19 = - fork0_ptr == 3'd2 && fork0_sr[119:118] == 2'd0; + 3'd2: + CASE_fork0_ptr_0_fork0_sr_BITS_39_TO_38_EQ_0_1_ETC__q19 = + fork0_sr[119:118] == 2'd0; + default: CASE_fork0_ptr_0_fork0_sr_BITS_39_TO_38_EQ_0_1_ETC__q19 = + 1'b0 /* unspecified value */ ; endcase end always@(fork0_ptr or fork0_sr) begin case (fork0_ptr) 3'd0: - IF_fork0_ptr_90_EQ_0_08_THEN_fork0_sr_94_BITS__ETC___d1351 = - fork0_sr[27:20]; + SEL_ARR_fork0_sr_94_BITS_17_TO_10_51_fork0_sr__ETC___d553 = + fork0_sr[17:10]; 3'd1: - IF_fork0_ptr_90_EQ_0_08_THEN_fork0_sr_94_BITS__ETC___d1351 = - fork0_sr[67:60]; - default: IF_fork0_ptr_90_EQ_0_08_THEN_fork0_sr_94_BITS__ETC___d1351 = - fork0_sr[107:100]; + SEL_ARR_fork0_sr_94_BITS_17_TO_10_51_fork0_sr__ETC___d553 = + fork0_sr[57:50]; + 3'd2: + SEL_ARR_fork0_sr_94_BITS_17_TO_10_51_fork0_sr__ETC___d553 = + fork0_sr[97:90]; + default: SEL_ARR_fork0_sr_94_BITS_17_TO_10_51_fork0_sr__ETC___d553 = + 8'b10101010 /* unspecified value */ ; endcase end always@(fork0_ptr or fork0_sr) begin case (fork0_ptr) 3'd0: - CASE_fork0_ptr_fork0_ptr_EQ_2_AND_fork0_sr_BIT_ETC__q20 = + SEL_ARR_fork0_sr_94_BITS_7_TO_0_70_fork0_sr_94_ETC___d572 = + fork0_sr[7:0]; + 3'd1: + SEL_ARR_fork0_sr_94_BITS_7_TO_0_70_fork0_sr_94_ETC___d572 = + fork0_sr[47:40]; + 3'd2: + SEL_ARR_fork0_sr_94_BITS_7_TO_0_70_fork0_sr_94_ETC___d572 = + fork0_sr[87:80]; + default: SEL_ARR_fork0_sr_94_BITS_7_TO_0_70_fork0_sr_94_ETC___d572 = + 8'b10101010 /* unspecified value */ ; + endcase + end + always@(fork0_ptr or fork0_sr) + begin + case (fork0_ptr) + 3'd0: + CASE_fork0_ptr_0_fork0_sr_BITS_29_TO_28_EQ_2_1_ETC__q20 = fork0_sr[29:28] == 2'd2; 3'd1: - CASE_fork0_ptr_fork0_ptr_EQ_2_AND_fork0_sr_BIT_ETC__q20 = + CASE_fork0_ptr_0_fork0_sr_BITS_29_TO_28_EQ_2_1_ETC__q20 = fork0_sr[69:68] == 2'd2; - default: CASE_fork0_ptr_fork0_ptr_EQ_2_AND_fork0_sr_BIT_ETC__q20 = - fork0_ptr == 3'd2 && fork0_sr[109:108] == 2'd2; + 3'd2: + CASE_fork0_ptr_0_fork0_sr_BITS_29_TO_28_EQ_2_1_ETC__q20 = + fork0_sr[109:108] == 2'd2; + default: CASE_fork0_ptr_0_fork0_sr_BITS_29_TO_28_EQ_2_1_ETC__q20 = + 1'b0 /* unspecified value */ ; endcase end always@(fork0_ptr or fork0_sr) begin case (fork0_ptr) 3'd0: - CASE_fork0_ptr_fork0_ptr_EQ_2_AND_fork0_sr_BIT_ETC__q21 = + CASE_fork0_ptr_0_fork0_sr_BITS_29_TO_28_EQ_1_1_ETC__q21 = fork0_sr[29:28] == 2'd1; 3'd1: - CASE_fork0_ptr_fork0_ptr_EQ_2_AND_fork0_sr_BIT_ETC__q21 = + CASE_fork0_ptr_0_fork0_sr_BITS_29_TO_28_EQ_1_1_ETC__q21 = fork0_sr[69:68] == 2'd1; - default: CASE_fork0_ptr_fork0_ptr_EQ_2_AND_fork0_sr_BIT_ETC__q21 = - fork0_ptr == 3'd2 && fork0_sr[109:108] == 2'd1; + 3'd2: + CASE_fork0_ptr_0_fork0_sr_BITS_29_TO_28_EQ_1_1_ETC__q21 = + fork0_sr[109:108] == 2'd1; + default: CASE_fork0_ptr_0_fork0_sr_BITS_29_TO_28_EQ_1_1_ETC__q21 = + 1'b0 /* unspecified value */ ; endcase end always@(fork0_ptr or fork0_sr) begin case (fork0_ptr) 3'd0: - CASE_fork0_ptr_fork0_ptr_EQ_2_AND_fork0_sr_BIT_ETC__q22 = + CASE_fork0_ptr_0_fork0_sr_BITS_29_TO_28_EQ_0_1_ETC__q22 = fork0_sr[29:28] == 2'd0; 3'd1: - CASE_fork0_ptr_fork0_ptr_EQ_2_AND_fork0_sr_BIT_ETC__q22 = + CASE_fork0_ptr_0_fork0_sr_BITS_29_TO_28_EQ_0_1_ETC__q22 = fork0_sr[69:68] == 2'd0; - default: CASE_fork0_ptr_fork0_ptr_EQ_2_AND_fork0_sr_BIT_ETC__q22 = - fork0_ptr == 3'd2 && fork0_sr[109:108] == 2'd0; + 3'd2: + CASE_fork0_ptr_0_fork0_sr_BITS_29_TO_28_EQ_0_1_ETC__q22 = + fork0_sr[109:108] == 2'd0; + default: CASE_fork0_ptr_0_fork0_sr_BITS_29_TO_28_EQ_0_1_ETC__q22 = + 1'b0 /* unspecified value */ ; endcase end - always@(fork0_ptr or fork0_sr) + always@(fork1_srcF$D_OUT) begin - case (fork0_ptr) - 3'd0: - IF_fork0_ptr_90_EQ_0_08_THEN_fork0_sr_94_BITS__ETC___d1352 = - fork0_sr[17:10]; - 3'd1: - IF_fork0_ptr_90_EQ_0_08_THEN_fork0_sr_94_BITS__ETC___d1352 = - fork0_sr[57:50]; - default: IF_fork0_ptr_90_EQ_0_08_THEN_fork0_sr_94_BITS__ETC___d1352 = - fork0_sr[97:90]; + case (fork1_srcF$D_OUT[39:38]) + 2'd0, 2'd1, 2'd2: + CASE_fork1_srcFD_OUT_BITS_39_TO_38_0_fork1_sr_ETC__q23 = + fork1_srcF$D_OUT[39:38]; + 2'd3: CASE_fork1_srcFD_OUT_BITS_39_TO_38_0_fork1_sr_ETC__q23 = 2'd3; endcase end - always@(fork0_ptr or fork0_sr) + always@(fork1_srcF$D_OUT) begin - case (fork0_ptr) - 3'd0: - CASE_fork0_ptr_fork0_ptr_EQ_2_AND_fork0_sr_BIT_ETC__q23 = - fork0_sr[19:18] == 2'd2; - 3'd1: - CASE_fork0_ptr_fork0_ptr_EQ_2_AND_fork0_sr_BIT_ETC__q23 = - fork0_sr[59:58] == 2'd2; - default: CASE_fork0_ptr_fork0_ptr_EQ_2_AND_fork0_sr_BIT_ETC__q23 = - fork0_ptr == 3'd2 && fork0_sr[99:98] == 2'd2; + case (fork1_srcF$D_OUT[29:28]) + 2'd0, 2'd1, 2'd2: + CASE_fork1_srcFD_OUT_BITS_29_TO_28_0_fork1_sr_ETC__q24 = + fork1_srcF$D_OUT[29:28]; + 2'd3: CASE_fork1_srcFD_OUT_BITS_29_TO_28_0_fork1_sr_ETC__q24 = 2'd3; endcase end - always@(fork0_ptr or fork0_sr) + always@(fork1_srcF$D_OUT) begin - case (fork0_ptr) - 3'd0: - CASE_fork0_ptr_fork0_ptr_EQ_2_AND_fork0_sr_BIT_ETC__q24 = - fork0_sr[19:18] == 2'd1; - 3'd1: - CASE_fork0_ptr_fork0_ptr_EQ_2_AND_fork0_sr_BIT_ETC__q24 = - fork0_sr[59:58] == 2'd1; - default: CASE_fork0_ptr_fork0_ptr_EQ_2_AND_fork0_sr_BIT_ETC__q24 = - fork0_ptr == 3'd2 && fork0_sr[99:98] == 2'd1; + case (fork1_srcF$D_OUT[19:18]) + 2'd0, 2'd1, 2'd2: + CASE_fork1_srcFD_OUT_BITS_19_TO_18_0_fork1_sr_ETC__q25 = + fork1_srcF$D_OUT[19:18]; + 2'd3: CASE_fork1_srcFD_OUT_BITS_19_TO_18_0_fork1_sr_ETC__q25 = 2'd3; endcase end - always@(fork0_ptr or fork0_sr) + always@(fork1_srcF$D_OUT) begin - case (fork0_ptr) - 3'd0: - CASE_fork0_ptr_fork0_ptr_EQ_2_AND_fork0_sr_BIT_ETC__q25 = - fork0_sr[19:18] == 2'd0; - 3'd1: - CASE_fork0_ptr_fork0_ptr_EQ_2_AND_fork0_sr_BIT_ETC__q25 = - fork0_sr[59:58] == 2'd0; - default: CASE_fork0_ptr_fork0_ptr_EQ_2_AND_fork0_sr_BIT_ETC__q25 = - fork0_ptr == 3'd2 && fork0_sr[99:98] == 2'd0; + case (fork1_srcF$D_OUT[9:8]) + 2'd0, 2'd1, 2'd2: + CASE_fork1_srcFD_OUT_BITS_9_TO_8_0_fork1_srcF_ETC__q26 = + fork1_srcF$D_OUT[9:8]; + 2'd3: CASE_fork1_srcFD_OUT_BITS_9_TO_8_0_fork1_srcF_ETC__q26 = 2'd3; endcase end - always@(fork0_ptr or fork0_sr) + always@(fork0_srcF$D_OUT) begin - case (fork0_ptr) - 3'd0: - IF_fork0_ptr_90_EQ_0_08_THEN_fork0_sr_94_BITS__ETC___d1353 = - fork0_sr[7:0]; - 3'd1: - IF_fork0_ptr_90_EQ_0_08_THEN_fork0_sr_94_BITS__ETC___d1353 = - fork0_sr[47:40]; - default: IF_fork0_ptr_90_EQ_0_08_THEN_fork0_sr_94_BITS__ETC___d1353 = - fork0_sr[87:80]; + case (fork0_srcF$D_OUT[39:38]) + 2'd0, 2'd1, 2'd2: + CASE_fork0_srcFD_OUT_BITS_39_TO_38_0_fork0_sr_ETC__q27 = + fork0_srcF$D_OUT[39:38]; + 2'd3: CASE_fork0_srcFD_OUT_BITS_39_TO_38_0_fork0_sr_ETC__q27 = 2'd3; endcase end - always@(fork0_ptr or fork0_sr) + always@(fork0_srcF$D_OUT) begin - case (fork0_ptr) - 3'd0: - CASE_fork0_ptr_fork0_ptr_EQ_2_AND_fork0_sr_BIT_ETC__q26 = - fork0_sr[9:8] == 2'd2; - 3'd1: - CASE_fork0_ptr_fork0_ptr_EQ_2_AND_fork0_sr_BIT_ETC__q26 = - fork0_sr[49:48] == 2'd2; - default: CASE_fork0_ptr_fork0_ptr_EQ_2_AND_fork0_sr_BIT_ETC__q26 = - fork0_ptr == 3'd2 && fork0_sr[89:88] == 2'd2; + case (fork0_srcF$D_OUT[29:28]) + 2'd0, 2'd1, 2'd2: + CASE_fork0_srcFD_OUT_BITS_29_TO_28_0_fork0_sr_ETC__q28 = + fork0_srcF$D_OUT[29:28]; + 2'd3: CASE_fork0_srcFD_OUT_BITS_29_TO_28_0_fork0_sr_ETC__q28 = 2'd3; endcase end - always@(fork0_ptr or fork0_sr) + always@(fork0_srcF$D_OUT) begin - case (fork0_ptr) - 3'd0: - CASE_fork0_ptr_fork0_ptr_EQ_2_AND_fork0_sr_BIT_ETC__q27 = - fork0_sr[9:8] == 2'd1; - 3'd1: - CASE_fork0_ptr_fork0_ptr_EQ_2_AND_fork0_sr_BIT_ETC__q27 = - fork0_sr[49:48] == 2'd1; - default: CASE_fork0_ptr_fork0_ptr_EQ_2_AND_fork0_sr_BIT_ETC__q27 = - fork0_ptr == 3'd2 && fork0_sr[89:88] == 2'd1; + case (fork0_srcF$D_OUT[19:18]) + 2'd0, 2'd1, 2'd2: + CASE_fork0_srcFD_OUT_BITS_19_TO_18_0_fork0_sr_ETC__q29 = + fork0_srcF$D_OUT[19:18]; + 2'd3: CASE_fork0_srcFD_OUT_BITS_19_TO_18_0_fork0_sr_ETC__q29 = 2'd3; endcase end - always@(fork0_ptr or fork0_sr) + always@(fork0_srcF$D_OUT) begin - case (fork0_ptr) + case (fork0_srcF$D_OUT[9:8]) + 2'd0, 2'd1, 2'd2: + CASE_fork0_srcFD_OUT_BITS_9_TO_8_0_fork0_srcF_ETC__q30 = + fork0_srcF$D_OUT[9:8]; + 2'd3: CASE_fork0_srcFD_OUT_BITS_9_TO_8_0_fork0_srcF_ETC__q30 = 2'd3; + endcase + end + always@(fork1_ptr or fork1_sr) + begin + case (fork1_ptr) 3'd0: - CASE_fork0_ptr_fork0_ptr_EQ_2_AND_fork0_sr_BIT_ETC__q28 = - fork0_sr[9:8] == 2'd0; + SEL_ARR_fork1_sr_43_BITS_27_TO_20_80_fork1_sr__ETC___d782 = + fork1_sr[27:20]; 3'd1: - CASE_fork0_ptr_fork0_ptr_EQ_2_AND_fork0_sr_BIT_ETC__q28 = - fork0_sr[49:48] == 2'd0; - default: CASE_fork0_ptr_fork0_ptr_EQ_2_AND_fork0_sr_BIT_ETC__q28 = - fork0_ptr == 3'd2 && fork0_sr[89:88] == 2'd0; + SEL_ARR_fork1_sr_43_BITS_27_TO_20_80_fork1_sr__ETC___d782 = + fork1_sr[67:60]; + 3'd2: + SEL_ARR_fork1_sr_43_BITS_27_TO_20_80_fork1_sr__ETC___d782 = + fork1_sr[107:100]; + default: SEL_ARR_fork1_sr_43_BITS_27_TO_20_80_fork1_sr__ETC___d782 = + 8'b10101010 /* unspecified value */ ; endcase end always@(fork1_ptr or fork1_sr) begin case (fork1_ptr) 3'd0: - IF_fork1_ptr_57_EQ_0_75_THEN_fork1_sr_61_BITS__ETC___d1354 = + SEL_ARR_fork1_sr_43_BITS_37_TO_30_61_fork1_sr__ETC___d763 = fork1_sr[37:30]; 3'd1: - IF_fork1_ptr_57_EQ_0_75_THEN_fork1_sr_61_BITS__ETC___d1354 = + SEL_ARR_fork1_sr_43_BITS_37_TO_30_61_fork1_sr__ETC___d763 = fork1_sr[77:70]; - default: IF_fork1_ptr_57_EQ_0_75_THEN_fork1_sr_61_BITS__ETC___d1354 = - fork1_sr[117:110]; + 3'd2: + SEL_ARR_fork1_sr_43_BITS_37_TO_30_61_fork1_sr__ETC___d763 = + fork1_sr[117:110]; + default: SEL_ARR_fork1_sr_43_BITS_37_TO_30_61_fork1_sr__ETC___d763 = + 8'b10101010 /* unspecified value */ ; endcase end always@(fork1_ptr or fork1_sr) begin case (fork1_ptr) 3'd0: - CASE_fork1_ptr_fork1_ptr_EQ_2_AND_fork1_sr_BIT_ETC__q29 = + CASE_fork1_ptr_0_fork1_sr_BITS_39_TO_38_EQ_2_1_ETC__q31 = fork1_sr[39:38] == 2'd2; 3'd1: - CASE_fork1_ptr_fork1_ptr_EQ_2_AND_fork1_sr_BIT_ETC__q29 = + CASE_fork1_ptr_0_fork1_sr_BITS_39_TO_38_EQ_2_1_ETC__q31 = fork1_sr[79:78] == 2'd2; - default: CASE_fork1_ptr_fork1_ptr_EQ_2_AND_fork1_sr_BIT_ETC__q29 = - fork1_ptr == 3'd2 && fork1_sr[119:118] == 2'd2; + 3'd2: + CASE_fork1_ptr_0_fork1_sr_BITS_39_TO_38_EQ_2_1_ETC__q31 = + fork1_sr[119:118] == 2'd2; + default: CASE_fork1_ptr_0_fork1_sr_BITS_39_TO_38_EQ_2_1_ETC__q31 = + 1'b0 /* unspecified value */ ; endcase end always@(fork1_ptr or fork1_sr) begin case (fork1_ptr) 3'd0: - CASE_fork1_ptr_fork1_ptr_EQ_2_AND_fork1_sr_BIT_ETC__q30 = + CASE_fork1_ptr_0_fork1_sr_BITS_39_TO_38_EQ_1_1_ETC__q32 = fork1_sr[39:38] == 2'd1; 3'd1: - CASE_fork1_ptr_fork1_ptr_EQ_2_AND_fork1_sr_BIT_ETC__q30 = + CASE_fork1_ptr_0_fork1_sr_BITS_39_TO_38_EQ_1_1_ETC__q32 = fork1_sr[79:78] == 2'd1; - default: CASE_fork1_ptr_fork1_ptr_EQ_2_AND_fork1_sr_BIT_ETC__q30 = - fork1_ptr == 3'd2 && fork1_sr[119:118] == 2'd1; + 3'd2: + CASE_fork1_ptr_0_fork1_sr_BITS_39_TO_38_EQ_1_1_ETC__q32 = + fork1_sr[119:118] == 2'd1; + default: CASE_fork1_ptr_0_fork1_sr_BITS_39_TO_38_EQ_1_1_ETC__q32 = + 1'b0 /* unspecified value */ ; endcase end always@(fork1_ptr or fork1_sr) begin case (fork1_ptr) 3'd0: - CASE_fork1_ptr_fork1_ptr_EQ_2_AND_fork1_sr_BIT_ETC__q31 = + CASE_fork1_ptr_0_fork1_sr_BITS_39_TO_38_EQ_0_1_ETC__q33 = fork1_sr[39:38] == 2'd0; 3'd1: - CASE_fork1_ptr_fork1_ptr_EQ_2_AND_fork1_sr_BIT_ETC__q31 = + CASE_fork1_ptr_0_fork1_sr_BITS_39_TO_38_EQ_0_1_ETC__q33 = fork1_sr[79:78] == 2'd0; - default: CASE_fork1_ptr_fork1_ptr_EQ_2_AND_fork1_sr_BIT_ETC__q31 = - fork1_ptr == 3'd2 && fork1_sr[119:118] == 2'd0; + 3'd2: + CASE_fork1_ptr_0_fork1_sr_BITS_39_TO_38_EQ_0_1_ETC__q33 = + fork1_sr[119:118] == 2'd0; + default: CASE_fork1_ptr_0_fork1_sr_BITS_39_TO_38_EQ_0_1_ETC__q33 = + 1'b0 /* unspecified value */ ; endcase end always@(fork1_ptr or fork1_sr) begin case (fork1_ptr) 3'd0: - IF_fork1_ptr_57_EQ_0_75_THEN_fork1_sr_61_BITS__ETC___d1355 = - fork1_sr[27:20]; + SEL_ARR_fork1_sr_43_BITS_17_TO_10_00_fork1_sr__ETC___d802 = + fork1_sr[17:10]; 3'd1: - IF_fork1_ptr_57_EQ_0_75_THEN_fork1_sr_61_BITS__ETC___d1355 = - fork1_sr[67:60]; - default: IF_fork1_ptr_57_EQ_0_75_THEN_fork1_sr_61_BITS__ETC___d1355 = - fork1_sr[107:100]; + SEL_ARR_fork1_sr_43_BITS_17_TO_10_00_fork1_sr__ETC___d802 = + fork1_sr[57:50]; + 3'd2: + SEL_ARR_fork1_sr_43_BITS_17_TO_10_00_fork1_sr__ETC___d802 = + fork1_sr[97:90]; + default: SEL_ARR_fork1_sr_43_BITS_17_TO_10_00_fork1_sr__ETC___d802 = + 8'b10101010 /* unspecified value */ ; endcase end always@(fork1_ptr or fork1_sr) begin case (fork1_ptr) 3'd0: - CASE_fork1_ptr_fork1_ptr_EQ_2_AND_fork1_sr_BIT_ETC__q32 = + SEL_ARR_fork1_sr_43_BITS_7_TO_0_19_fork1_sr_43_ETC___d821 = + fork1_sr[7:0]; + 3'd1: + SEL_ARR_fork1_sr_43_BITS_7_TO_0_19_fork1_sr_43_ETC___d821 = + fork1_sr[47:40]; + 3'd2: + SEL_ARR_fork1_sr_43_BITS_7_TO_0_19_fork1_sr_43_ETC___d821 = + fork1_sr[87:80]; + default: SEL_ARR_fork1_sr_43_BITS_7_TO_0_19_fork1_sr_43_ETC___d821 = + 8'b10101010 /* unspecified value */ ; + endcase + end + always@(fork1_ptr or fork1_sr) + begin + case (fork1_ptr) + 3'd0: + CASE_fork1_ptr_0_fork1_sr_BITS_29_TO_28_EQ_2_1_ETC__q34 = fork1_sr[29:28] == 2'd2; 3'd1: - CASE_fork1_ptr_fork1_ptr_EQ_2_AND_fork1_sr_BIT_ETC__q32 = + CASE_fork1_ptr_0_fork1_sr_BITS_29_TO_28_EQ_2_1_ETC__q34 = fork1_sr[69:68] == 2'd2; - default: CASE_fork1_ptr_fork1_ptr_EQ_2_AND_fork1_sr_BIT_ETC__q32 = - fork1_ptr == 3'd2 && fork1_sr[109:108] == 2'd2; + 3'd2: + CASE_fork1_ptr_0_fork1_sr_BITS_29_TO_28_EQ_2_1_ETC__q34 = + fork1_sr[109:108] == 2'd2; + default: CASE_fork1_ptr_0_fork1_sr_BITS_29_TO_28_EQ_2_1_ETC__q34 = + 1'b0 /* unspecified value */ ; endcase end always@(fork1_ptr or fork1_sr) begin case (fork1_ptr) 3'd0: - CASE_fork1_ptr_fork1_ptr_EQ_2_AND_fork1_sr_BIT_ETC__q33 = + CASE_fork1_ptr_0_fork1_sr_BITS_29_TO_28_EQ_1_1_ETC__q35 = fork1_sr[29:28] == 2'd1; 3'd1: - CASE_fork1_ptr_fork1_ptr_EQ_2_AND_fork1_sr_BIT_ETC__q33 = + CASE_fork1_ptr_0_fork1_sr_BITS_29_TO_28_EQ_1_1_ETC__q35 = fork1_sr[69:68] == 2'd1; - default: CASE_fork1_ptr_fork1_ptr_EQ_2_AND_fork1_sr_BIT_ETC__q33 = - fork1_ptr == 3'd2 && fork1_sr[109:108] == 2'd1; + 3'd2: + CASE_fork1_ptr_0_fork1_sr_BITS_29_TO_28_EQ_1_1_ETC__q35 = + fork1_sr[109:108] == 2'd1; + default: CASE_fork1_ptr_0_fork1_sr_BITS_29_TO_28_EQ_1_1_ETC__q35 = + 1'b0 /* unspecified value */ ; endcase end always@(fork1_ptr or fork1_sr) begin case (fork1_ptr) 3'd0: - CASE_fork1_ptr_fork1_ptr_EQ_2_AND_fork1_sr_BIT_ETC__q34 = + CASE_fork1_ptr_0_fork1_sr_BITS_29_TO_28_EQ_0_1_ETC__q36 = fork1_sr[29:28] == 2'd0; 3'd1: - CASE_fork1_ptr_fork1_ptr_EQ_2_AND_fork1_sr_BIT_ETC__q34 = + CASE_fork1_ptr_0_fork1_sr_BITS_29_TO_28_EQ_0_1_ETC__q36 = fork1_sr[69:68] == 2'd0; - default: CASE_fork1_ptr_fork1_ptr_EQ_2_AND_fork1_sr_BIT_ETC__q34 = - fork1_ptr == 3'd2 && fork1_sr[109:108] == 2'd0; + 3'd2: + CASE_fork1_ptr_0_fork1_sr_BITS_29_TO_28_EQ_0_1_ETC__q36 = + fork1_sr[109:108] == 2'd0; + default: CASE_fork1_ptr_0_fork1_sr_BITS_29_TO_28_EQ_0_1_ETC__q36 = + 1'b0 /* unspecified value */ ; endcase end - always@(fork1_ptr or fork1_sr) + always@(fork0_ptr or fork0_sr) begin - case (fork1_ptr) + case (fork0_ptr) 3'd0: - IF_fork1_ptr_57_EQ_0_75_THEN_fork1_sr_61_BITS__ETC___d1356 = - fork1_sr[17:10]; + CASE_fork0_ptr_0_fork0_sr_BITS_19_TO_18_EQ_2_1_ETC__q37 = + fork0_sr[19:18] == 2'd2; 3'd1: - IF_fork1_ptr_57_EQ_0_75_THEN_fork1_sr_61_BITS__ETC___d1356 = - fork1_sr[57:50]; - default: IF_fork1_ptr_57_EQ_0_75_THEN_fork1_sr_61_BITS__ETC___d1356 = - fork1_sr[97:90]; + CASE_fork0_ptr_0_fork0_sr_BITS_19_TO_18_EQ_2_1_ETC__q37 = + fork0_sr[59:58] == 2'd2; + 3'd2: + CASE_fork0_ptr_0_fork0_sr_BITS_19_TO_18_EQ_2_1_ETC__q37 = + fork0_sr[99:98] == 2'd2; + default: CASE_fork0_ptr_0_fork0_sr_BITS_19_TO_18_EQ_2_1_ETC__q37 = + 1'b0 /* unspecified value */ ; + endcase + end + always@(fork0_ptr or fork0_sr) + begin + case (fork0_ptr) + 3'd0: + CASE_fork0_ptr_0_fork0_sr_BITS_19_TO_18_EQ_1_1_ETC__q38 = + fork0_sr[19:18] == 2'd1; + 3'd1: + CASE_fork0_ptr_0_fork0_sr_BITS_19_TO_18_EQ_1_1_ETC__q38 = + fork0_sr[59:58] == 2'd1; + 3'd2: + CASE_fork0_ptr_0_fork0_sr_BITS_19_TO_18_EQ_1_1_ETC__q38 = + fork0_sr[99:98] == 2'd1; + default: CASE_fork0_ptr_0_fork0_sr_BITS_19_TO_18_EQ_1_1_ETC__q38 = + 1'b0 /* unspecified value */ ; + endcase + end + always@(fork0_ptr or fork0_sr) + begin + case (fork0_ptr) + 3'd0: + CASE_fork0_ptr_0_fork0_sr_BITS_19_TO_18_EQ_0_1_ETC__q39 = + fork0_sr[19:18] == 2'd0; + 3'd1: + CASE_fork0_ptr_0_fork0_sr_BITS_19_TO_18_EQ_0_1_ETC__q39 = + fork0_sr[59:58] == 2'd0; + 3'd2: + CASE_fork0_ptr_0_fork0_sr_BITS_19_TO_18_EQ_0_1_ETC__q39 = + fork0_sr[99:98] == 2'd0; + default: CASE_fork0_ptr_0_fork0_sr_BITS_19_TO_18_EQ_0_1_ETC__q39 = + 1'b0 /* unspecified value */ ; + endcase + end + always@(fork0_ptr or fork0_sr) + begin + case (fork0_ptr) + 3'd0: + CASE_fork0_ptr_0_fork0_sr_BITS_9_TO_8_EQ_2_1_f_ETC__q40 = + fork0_sr[9:8] == 2'd2; + 3'd1: + CASE_fork0_ptr_0_fork0_sr_BITS_9_TO_8_EQ_2_1_f_ETC__q40 = + fork0_sr[49:48] == 2'd2; + 3'd2: + CASE_fork0_ptr_0_fork0_sr_BITS_9_TO_8_EQ_2_1_f_ETC__q40 = + fork0_sr[89:88] == 2'd2; + default: CASE_fork0_ptr_0_fork0_sr_BITS_9_TO_8_EQ_2_1_f_ETC__q40 = + 1'b0 /* unspecified value */ ; + endcase + end + always@(fork0_ptr or fork0_sr) + begin + case (fork0_ptr) + 3'd0: + CASE_fork0_ptr_0_fork0_sr_BITS_9_TO_8_EQ_1_1_f_ETC__q41 = + fork0_sr[9:8] == 2'd1; + 3'd1: + CASE_fork0_ptr_0_fork0_sr_BITS_9_TO_8_EQ_1_1_f_ETC__q41 = + fork0_sr[49:48] == 2'd1; + 3'd2: + CASE_fork0_ptr_0_fork0_sr_BITS_9_TO_8_EQ_1_1_f_ETC__q41 = + fork0_sr[89:88] == 2'd1; + default: CASE_fork0_ptr_0_fork0_sr_BITS_9_TO_8_EQ_1_1_f_ETC__q41 = + 1'b0 /* unspecified value */ ; + endcase + end + always@(fork0_ptr or fork0_sr) + begin + case (fork0_ptr) + 3'd0: + CASE_fork0_ptr_0_fork0_sr_BITS_9_TO_8_EQ_0_1_f_ETC__q42 = + fork0_sr[9:8] == 2'd0; + 3'd1: + CASE_fork0_ptr_0_fork0_sr_BITS_9_TO_8_EQ_0_1_f_ETC__q42 = + fork0_sr[49:48] == 2'd0; + 3'd2: + CASE_fork0_ptr_0_fork0_sr_BITS_9_TO_8_EQ_0_1_f_ETC__q42 = + fork0_sr[89:88] == 2'd0; + default: CASE_fork0_ptr_0_fork0_sr_BITS_9_TO_8_EQ_0_1_f_ETC__q42 = + 1'b0 /* unspecified value */ ; endcase end always@(fork1_ptr or fork1_sr) begin case (fork1_ptr) 3'd0: - CASE_fork1_ptr_fork1_ptr_EQ_2_AND_fork1_sr_BIT_ETC__q35 = + CASE_fork1_ptr_0_fork1_sr_BITS_19_TO_18_EQ_2_1_ETC__q43 = fork1_sr[19:18] == 2'd2; 3'd1: - CASE_fork1_ptr_fork1_ptr_EQ_2_AND_fork1_sr_BIT_ETC__q35 = + CASE_fork1_ptr_0_fork1_sr_BITS_19_TO_18_EQ_2_1_ETC__q43 = fork1_sr[59:58] == 2'd2; - default: CASE_fork1_ptr_fork1_ptr_EQ_2_AND_fork1_sr_BIT_ETC__q35 = - fork1_ptr == 3'd2 && fork1_sr[99:98] == 2'd2; + 3'd2: + CASE_fork1_ptr_0_fork1_sr_BITS_19_TO_18_EQ_2_1_ETC__q43 = + fork1_sr[99:98] == 2'd2; + default: CASE_fork1_ptr_0_fork1_sr_BITS_19_TO_18_EQ_2_1_ETC__q43 = + 1'b0 /* unspecified value */ ; endcase end always@(fork1_ptr or fork1_sr) begin case (fork1_ptr) 3'd0: - CASE_fork1_ptr_fork1_ptr_EQ_2_AND_fork1_sr_BIT_ETC__q36 = + CASE_fork1_ptr_0_fork1_sr_BITS_19_TO_18_EQ_1_1_ETC__q44 = fork1_sr[19:18] == 2'd1; 3'd1: - CASE_fork1_ptr_fork1_ptr_EQ_2_AND_fork1_sr_BIT_ETC__q36 = + CASE_fork1_ptr_0_fork1_sr_BITS_19_TO_18_EQ_1_1_ETC__q44 = fork1_sr[59:58] == 2'd1; - default: CASE_fork1_ptr_fork1_ptr_EQ_2_AND_fork1_sr_BIT_ETC__q36 = - fork1_ptr == 3'd2 && fork1_sr[99:98] == 2'd1; + 3'd2: + CASE_fork1_ptr_0_fork1_sr_BITS_19_TO_18_EQ_1_1_ETC__q44 = + fork1_sr[99:98] == 2'd1; + default: CASE_fork1_ptr_0_fork1_sr_BITS_19_TO_18_EQ_1_1_ETC__q44 = + 1'b0 /* unspecified value */ ; endcase end always@(fork1_ptr or fork1_sr) begin case (fork1_ptr) 3'd0: - CASE_fork1_ptr_fork1_ptr_EQ_2_AND_fork1_sr_BIT_ETC__q37 = + CASE_fork1_ptr_0_fork1_sr_BITS_19_TO_18_EQ_0_1_ETC__q45 = fork1_sr[19:18] == 2'd0; 3'd1: - CASE_fork1_ptr_fork1_ptr_EQ_2_AND_fork1_sr_BIT_ETC__q37 = + CASE_fork1_ptr_0_fork1_sr_BITS_19_TO_18_EQ_0_1_ETC__q45 = fork1_sr[59:58] == 2'd0; - default: CASE_fork1_ptr_fork1_ptr_EQ_2_AND_fork1_sr_BIT_ETC__q37 = - fork1_ptr == 3'd2 && fork1_sr[99:98] == 2'd0; + 3'd2: + CASE_fork1_ptr_0_fork1_sr_BITS_19_TO_18_EQ_0_1_ETC__q45 = + fork1_sr[99:98] == 2'd0; + default: CASE_fork1_ptr_0_fork1_sr_BITS_19_TO_18_EQ_0_1_ETC__q45 = + 1'b0 /* unspecified value */ ; endcase end always@(fork1_ptr or fork1_sr) begin case (fork1_ptr) 3'd0: - IF_fork1_ptr_57_EQ_0_75_THEN_fork1_sr_61_BITS__ETC___d1357 = - fork1_sr[7:0]; - 3'd1: - IF_fork1_ptr_57_EQ_0_75_THEN_fork1_sr_61_BITS__ETC___d1357 = - fork1_sr[47:40]; - default: IF_fork1_ptr_57_EQ_0_75_THEN_fork1_sr_61_BITS__ETC___d1357 = - fork1_sr[87:80]; - endcase - end - always@(fork1_ptr or fork1_sr) - begin - case (fork1_ptr) - 3'd0: - CASE_fork1_ptr_fork1_ptr_EQ_2_AND_fork1_sr_BIT_ETC__q38 = + CASE_fork1_ptr_0_fork1_sr_BITS_9_TO_8_EQ_2_1_f_ETC__q46 = fork1_sr[9:8] == 2'd2; 3'd1: - CASE_fork1_ptr_fork1_ptr_EQ_2_AND_fork1_sr_BIT_ETC__q38 = + CASE_fork1_ptr_0_fork1_sr_BITS_9_TO_8_EQ_2_1_f_ETC__q46 = fork1_sr[49:48] == 2'd2; - default: CASE_fork1_ptr_fork1_ptr_EQ_2_AND_fork1_sr_BIT_ETC__q38 = - fork1_ptr == 3'd2 && fork1_sr[89:88] == 2'd2; + 3'd2: + CASE_fork1_ptr_0_fork1_sr_BITS_9_TO_8_EQ_2_1_f_ETC__q46 = + fork1_sr[89:88] == 2'd2; + default: CASE_fork1_ptr_0_fork1_sr_BITS_9_TO_8_EQ_2_1_f_ETC__q46 = + 1'b0 /* unspecified value */ ; endcase end always@(fork1_ptr or fork1_sr) begin case (fork1_ptr) 3'd0: - CASE_fork1_ptr_fork1_ptr_EQ_2_AND_fork1_sr_BIT_ETC__q39 = + CASE_fork1_ptr_0_fork1_sr_BITS_9_TO_8_EQ_1_1_f_ETC__q47 = fork1_sr[9:8] == 2'd1; 3'd1: - CASE_fork1_ptr_fork1_ptr_EQ_2_AND_fork1_sr_BIT_ETC__q39 = + CASE_fork1_ptr_0_fork1_sr_BITS_9_TO_8_EQ_1_1_f_ETC__q47 = fork1_sr[49:48] == 2'd1; - default: CASE_fork1_ptr_fork1_ptr_EQ_2_AND_fork1_sr_BIT_ETC__q39 = - fork1_ptr == 3'd2 && fork1_sr[89:88] == 2'd1; + 3'd2: + CASE_fork1_ptr_0_fork1_sr_BITS_9_TO_8_EQ_1_1_f_ETC__q47 = + fork1_sr[89:88] == 2'd1; + default: CASE_fork1_ptr_0_fork1_sr_BITS_9_TO_8_EQ_1_1_f_ETC__q47 = + 1'b0 /* unspecified value */ ; endcase end always@(fork1_ptr or fork1_sr) begin case (fork1_ptr) 3'd0: - CASE_fork1_ptr_fork1_ptr_EQ_2_AND_fork1_sr_BIT_ETC__q40 = + CASE_fork1_ptr_0_fork1_sr_BITS_9_TO_8_EQ_0_1_f_ETC__q48 = fork1_sr[9:8] == 2'd0; 3'd1: - CASE_fork1_ptr_fork1_ptr_EQ_2_AND_fork1_sr_BIT_ETC__q40 = + CASE_fork1_ptr_0_fork1_sr_BITS_9_TO_8_EQ_0_1_f_ETC__q48 = fork1_sr[49:48] == 2'd0; - default: CASE_fork1_ptr_fork1_ptr_EQ_2_AND_fork1_sr_BIT_ETC__q40 = - fork1_ptr == 3'd2 && fork1_sr[89:88] == 2'd0; - endcase - end - always@(fork0_srcF$D_OUT) - begin - case (fork0_srcF$D_OUT[39:38]) - 2'd0, 2'd1, 2'd2: - CASE_fork0_srcFD_OUT_BITS_39_TO_38_3_0_fork0__ETC__q41 = - fork0_srcF$D_OUT[39:38]; - 2'd3: CASE_fork0_srcFD_OUT_BITS_39_TO_38_3_0_fork0__ETC__q41 = 2'd3; - endcase - end - always@(fork0_srcF$D_OUT) - begin - case (fork0_srcF$D_OUT[29:28]) - 2'd0, 2'd1, 2'd2: - CASE_fork0_srcFD_OUT_BITS_29_TO_28_3_0_fork0__ETC__q42 = - fork0_srcF$D_OUT[29:28]; - 2'd3: CASE_fork0_srcFD_OUT_BITS_29_TO_28_3_0_fork0__ETC__q42 = 2'd3; - endcase - end - always@(fork0_srcF$D_OUT) - begin - case (fork0_srcF$D_OUT[19:18]) - 2'd0, 2'd1, 2'd2: - CASE_fork0_srcFD_OUT_BITS_19_TO_18_3_0_fork0__ETC__q43 = - fork0_srcF$D_OUT[19:18]; - 2'd3: CASE_fork0_srcFD_OUT_BITS_19_TO_18_3_0_fork0__ETC__q43 = 2'd3; - endcase - end - always@(fork0_srcF$D_OUT) - begin - case (fork0_srcF$D_OUT[9:8]) - 2'd0, 2'd1, 2'd2: - CASE_fork0_srcFD_OUT_BITS_9_TO_8_3_0_fork0_sr_ETC__q44 = - fork0_srcF$D_OUT[9:8]; - 2'd3: CASE_fork0_srcFD_OUT_BITS_9_TO_8_3_0_fork0_sr_ETC__q44 = 2'd3; - endcase - end - always@(fork1_srcF$D_OUT) - begin - case (fork1_srcF$D_OUT[39:38]) - 2'd0, 2'd1, 2'd2: - CASE_fork1_srcFD_OUT_BITS_39_TO_38_3_0_fork1__ETC__q45 = - fork1_srcF$D_OUT[39:38]; - 2'd3: CASE_fork1_srcFD_OUT_BITS_39_TO_38_3_0_fork1__ETC__q45 = 2'd3; - endcase - end - always@(fork1_srcF$D_OUT) - begin - case (fork1_srcF$D_OUT[29:28]) - 2'd0, 2'd1, 2'd2: - CASE_fork1_srcFD_OUT_BITS_29_TO_28_3_0_fork1__ETC__q46 = - fork1_srcF$D_OUT[29:28]; - 2'd3: CASE_fork1_srcFD_OUT_BITS_29_TO_28_3_0_fork1__ETC__q46 = 2'd3; - endcase - end - always@(fork1_srcF$D_OUT) - begin - case (fork1_srcF$D_OUT[19:18]) - 2'd0, 2'd1, 2'd2: - CASE_fork1_srcFD_OUT_BITS_19_TO_18_3_0_fork1__ETC__q47 = - fork1_srcF$D_OUT[19:18]; - 2'd3: CASE_fork1_srcFD_OUT_BITS_19_TO_18_3_0_fork1__ETC__q47 = 2'd3; - endcase - end - always@(fork1_srcF$D_OUT) - begin - case (fork1_srcF$D_OUT[9:8]) - 2'd0, 2'd1, 2'd2: - CASE_fork1_srcFD_OUT_BITS_9_TO_8_3_0_fork1_sr_ETC__q48 = - fork1_srcF$D_OUT[9:8]; - 2'd3: CASE_fork1_srcFD_OUT_BITS_9_TO_8_3_0_fork1_sr_ETC__q48 = 2'd3; + 3'd2: + CASE_fork1_ptr_0_fork1_sr_BITS_9_TO_8_EQ_0_1_f_ETC__q48 = + fork1_sr[89:88] == 2'd0; + default: CASE_fork1_ptr_0_fork1_sr_BITS_9_TO_8_EQ_0_1_f_ETC__q48 = + 1'b0 /* unspecified value */ ; endcase end always@(merge0_fi0$D_OUT) begin case (merge0_fi0$D_OUT[39:38]) 2'd0, 2'd1, 2'd2: - CASE_merge0_fi0D_OUT_BITS_39_TO_38_3_0_merge0_ETC__q49 = + CASE_merge0_fi0D_OUT_BITS_39_TO_38_0_merge0_f_ETC__q49 = merge0_fi0$D_OUT[39:38]; - 2'd3: CASE_merge0_fi0D_OUT_BITS_39_TO_38_3_0_merge0_ETC__q49 = 2'd3; + 2'd3: CASE_merge0_fi0D_OUT_BITS_39_TO_38_0_merge0_f_ETC__q49 = 2'd3; endcase end always@(merge0_fi0$D_OUT) begin case (merge0_fi0$D_OUT[29:28]) 2'd0, 2'd1, 2'd2: - CASE_merge0_fi0D_OUT_BITS_29_TO_28_3_0_merge0_ETC__q50 = + CASE_merge0_fi0D_OUT_BITS_29_TO_28_0_merge0_f_ETC__q50 = merge0_fi0$D_OUT[29:28]; - 2'd3: CASE_merge0_fi0D_OUT_BITS_29_TO_28_3_0_merge0_ETC__q50 = 2'd3; + 2'd3: CASE_merge0_fi0D_OUT_BITS_29_TO_28_0_merge0_f_ETC__q50 = 2'd3; endcase end always@(merge0_fi0$D_OUT) begin case (merge0_fi0$D_OUT[19:18]) 2'd0, 2'd1, 2'd2: - CASE_merge0_fi0D_OUT_BITS_19_TO_18_3_0_merge0_ETC__q51 = + CASE_merge0_fi0D_OUT_BITS_19_TO_18_0_merge0_f_ETC__q51 = merge0_fi0$D_OUT[19:18]; - 2'd3: CASE_merge0_fi0D_OUT_BITS_19_TO_18_3_0_merge0_ETC__q51 = 2'd3; + 2'd3: CASE_merge0_fi0D_OUT_BITS_19_TO_18_0_merge0_f_ETC__q51 = 2'd3; endcase end always@(merge0_fi0$D_OUT) begin case (merge0_fi0$D_OUT[9:8]) 2'd0, 2'd1, 2'd2: - CASE_merge0_fi0D_OUT_BITS_9_TO_8_3_0_merge0_f_ETC__q52 = + CASE_merge0_fi0D_OUT_BITS_9_TO_8_0_merge0_fi0_ETC__q52 = merge0_fi0$D_OUT[9:8]; - 2'd3: CASE_merge0_fi0D_OUT_BITS_9_TO_8_3_0_merge0_f_ETC__q52 = 2'd3; + 2'd3: CASE_merge0_fi0D_OUT_BITS_9_TO_8_0_merge0_fi0_ETC__q52 = 2'd3; endcase end always@(merge0_fi1$D_OUT) begin case (merge0_fi1$D_OUT[39:38]) 2'd0, 2'd1, 2'd2: - CASE_merge0_fi1D_OUT_BITS_39_TO_38_3_0_merge0_ETC__q53 = + CASE_merge0_fi1D_OUT_BITS_39_TO_38_0_merge0_f_ETC__q53 = merge0_fi1$D_OUT[39:38]; - 2'd3: CASE_merge0_fi1D_OUT_BITS_39_TO_38_3_0_merge0_ETC__q53 = 2'd3; + 2'd3: CASE_merge0_fi1D_OUT_BITS_39_TO_38_0_merge0_f_ETC__q53 = 2'd3; endcase end always@(merge0_fi1$D_OUT) begin case (merge0_fi1$D_OUT[29:28]) 2'd0, 2'd1, 2'd2: - CASE_merge0_fi1D_OUT_BITS_29_TO_28_3_0_merge0_ETC__q54 = + CASE_merge0_fi1D_OUT_BITS_29_TO_28_0_merge0_f_ETC__q54 = merge0_fi1$D_OUT[29:28]; - 2'd3: CASE_merge0_fi1D_OUT_BITS_29_TO_28_3_0_merge0_ETC__q54 = 2'd3; + 2'd3: CASE_merge0_fi1D_OUT_BITS_29_TO_28_0_merge0_f_ETC__q54 = 2'd3; endcase end always@(merge0_fi1$D_OUT) begin case (merge0_fi1$D_OUT[19:18]) 2'd0, 2'd1, 2'd2: - CASE_merge0_fi1D_OUT_BITS_19_TO_18_3_0_merge0_ETC__q55 = + CASE_merge0_fi1D_OUT_BITS_19_TO_18_0_merge0_f_ETC__q55 = merge0_fi1$D_OUT[19:18]; - 2'd3: CASE_merge0_fi1D_OUT_BITS_19_TO_18_3_0_merge0_ETC__q55 = 2'd3; + 2'd3: CASE_merge0_fi1D_OUT_BITS_19_TO_18_0_merge0_f_ETC__q55 = 2'd3; endcase end always@(merge0_fi1$D_OUT) begin case (merge0_fi1$D_OUT[9:8]) 2'd0, 2'd1, 2'd2: - CASE_merge0_fi1D_OUT_BITS_9_TO_8_3_0_merge0_f_ETC__q56 = + CASE_merge0_fi1D_OUT_BITS_9_TO_8_0_merge0_fi1_ETC__q56 = merge0_fi1$D_OUT[9:8]; - 2'd3: CASE_merge0_fi1D_OUT_BITS_9_TO_8_3_0_merge0_f_ETC__q56 = 2'd3; + 2'd3: CASE_merge0_fi1D_OUT_BITS_9_TO_8_0_merge0_fi1_ETC__q56 = 2'd3; endcase end always@(merge1_fi0$D_OUT) begin case (merge1_fi0$D_OUT[39:38]) 2'd0, 2'd1, 2'd2: - CASE_merge1_fi0D_OUT_BITS_39_TO_38_3_0_merge1_ETC__q57 = + CASE_merge1_fi0D_OUT_BITS_39_TO_38_0_merge1_f_ETC__q57 = merge1_fi0$D_OUT[39:38]; - 2'd3: CASE_merge1_fi0D_OUT_BITS_39_TO_38_3_0_merge1_ETC__q57 = 2'd3; + 2'd3: CASE_merge1_fi0D_OUT_BITS_39_TO_38_0_merge1_f_ETC__q57 = 2'd3; endcase end always@(merge1_fi0$D_OUT) begin case (merge1_fi0$D_OUT[29:28]) 2'd0, 2'd1, 2'd2: - CASE_merge1_fi0D_OUT_BITS_29_TO_28_3_0_merge1_ETC__q58 = + CASE_merge1_fi0D_OUT_BITS_29_TO_28_0_merge1_f_ETC__q58 = merge1_fi0$D_OUT[29:28]; - 2'd3: CASE_merge1_fi0D_OUT_BITS_29_TO_28_3_0_merge1_ETC__q58 = 2'd3; + 2'd3: CASE_merge1_fi0D_OUT_BITS_29_TO_28_0_merge1_f_ETC__q58 = 2'd3; endcase end always@(merge1_fi0$D_OUT) begin case (merge1_fi0$D_OUT[19:18]) 2'd0, 2'd1, 2'd2: - CASE_merge1_fi0D_OUT_BITS_19_TO_18_3_0_merge1_ETC__q59 = + CASE_merge1_fi0D_OUT_BITS_19_TO_18_0_merge1_f_ETC__q59 = merge1_fi0$D_OUT[19:18]; - 2'd3: CASE_merge1_fi0D_OUT_BITS_19_TO_18_3_0_merge1_ETC__q59 = 2'd3; + 2'd3: CASE_merge1_fi0D_OUT_BITS_19_TO_18_0_merge1_f_ETC__q59 = 2'd3; endcase end always@(merge1_fi0$D_OUT) begin case (merge1_fi0$D_OUT[9:8]) 2'd0, 2'd1, 2'd2: - CASE_merge1_fi0D_OUT_BITS_9_TO_8_3_0_merge1_f_ETC__q60 = + CASE_merge1_fi0D_OUT_BITS_9_TO_8_0_merge1_fi0_ETC__q60 = merge1_fi0$D_OUT[9:8]; - 2'd3: CASE_merge1_fi0D_OUT_BITS_9_TO_8_3_0_merge1_f_ETC__q60 = 2'd3; + 2'd3: CASE_merge1_fi0D_OUT_BITS_9_TO_8_0_merge1_fi0_ETC__q60 = 2'd3; endcase end always@(merge1_fi1$D_OUT) begin case (merge1_fi1$D_OUT[39:38]) 2'd0, 2'd1, 2'd2: - CASE_merge1_fi1D_OUT_BITS_39_TO_38_3_0_merge1_ETC__q61 = + CASE_merge1_fi1D_OUT_BITS_39_TO_38_0_merge1_f_ETC__q61 = merge1_fi1$D_OUT[39:38]; - 2'd3: CASE_merge1_fi1D_OUT_BITS_39_TO_38_3_0_merge1_ETC__q61 = 2'd3; + 2'd3: CASE_merge1_fi1D_OUT_BITS_39_TO_38_0_merge1_f_ETC__q61 = 2'd3; endcase end always@(merge1_fi1$D_OUT) begin case (merge1_fi1$D_OUT[29:28]) 2'd0, 2'd1, 2'd2: - CASE_merge1_fi1D_OUT_BITS_29_TO_28_3_0_merge1_ETC__q62 = + CASE_merge1_fi1D_OUT_BITS_29_TO_28_0_merge1_f_ETC__q62 = merge1_fi1$D_OUT[29:28]; - 2'd3: CASE_merge1_fi1D_OUT_BITS_29_TO_28_3_0_merge1_ETC__q62 = 2'd3; + 2'd3: CASE_merge1_fi1D_OUT_BITS_29_TO_28_0_merge1_f_ETC__q62 = 2'd3; endcase end always@(merge1_fi1$D_OUT) begin case (merge1_fi1$D_OUT[19:18]) 2'd0, 2'd1, 2'd2: - CASE_merge1_fi1D_OUT_BITS_19_TO_18_3_0_merge1_ETC__q63 = + CASE_merge1_fi1D_OUT_BITS_19_TO_18_0_merge1_f_ETC__q63 = merge1_fi1$D_OUT[19:18]; - 2'd3: CASE_merge1_fi1D_OUT_BITS_19_TO_18_3_0_merge1_ETC__q63 = 2'd3; + 2'd3: CASE_merge1_fi1D_OUT_BITS_19_TO_18_0_merge1_f_ETC__q63 = 2'd3; endcase end always@(merge1_fi1$D_OUT) begin case (merge1_fi1$D_OUT[9:8]) 2'd0, 2'd1, 2'd2: - CASE_merge1_fi1D_OUT_BITS_9_TO_8_3_0_merge1_f_ETC__q64 = + CASE_merge1_fi1D_OUT_BITS_9_TO_8_0_merge1_fi1_ETC__q64 = merge1_fi1$D_OUT[9:8]; - 2'd3: CASE_merge1_fi1D_OUT_BITS_9_TO_8_3_0_merge1_f_ETC__q64 = 2'd3; + 2'd3: CASE_merge1_fi1D_OUT_BITS_9_TO_8_0_merge1_fi1_ETC__q64 = 2'd3; endcase end always@(fork0_sr) begin case (fork0_sr[119:118]) 2'd0, 2'd1, 2'd2: - CASE_fork0_sr_BITS_119_TO_118_3_0_fork0_sr_BIT_ETC__q65 = + CASE_fork0_sr_BITS_119_TO_118_0_fork0_sr_BITS__ETC__q65 = fork0_sr[119:118]; - 2'd3: CASE_fork0_sr_BITS_119_TO_118_3_0_fork0_sr_BIT_ETC__q65 = 2'd3; + 2'd3: CASE_fork0_sr_BITS_119_TO_118_0_fork0_sr_BITS__ETC__q65 = 2'd3; endcase end always@(fork0_sr) begin case (fork0_sr[109:108]) 2'd0, 2'd1, 2'd2: - CASE_fork0_sr_BITS_109_TO_108_3_0_fork0_sr_BIT_ETC__q66 = + CASE_fork0_sr_BITS_109_TO_108_0_fork0_sr_BITS__ETC__q66 = fork0_sr[109:108]; - 2'd3: CASE_fork0_sr_BITS_109_TO_108_3_0_fork0_sr_BIT_ETC__q66 = 2'd3; + 2'd3: CASE_fork0_sr_BITS_109_TO_108_0_fork0_sr_BITS__ETC__q66 = 2'd3; endcase end always@(fork0_sr) begin case (fork0_sr[99:98]) 2'd0, 2'd1, 2'd2: - CASE_fork0_sr_BITS_99_TO_98_3_0_fork0_sr_BITS__ETC__q67 = + CASE_fork0_sr_BITS_99_TO_98_0_fork0_sr_BITS_99_ETC__q67 = fork0_sr[99:98]; - 2'd3: CASE_fork0_sr_BITS_99_TO_98_3_0_fork0_sr_BITS__ETC__q67 = 2'd3; + 2'd3: CASE_fork0_sr_BITS_99_TO_98_0_fork0_sr_BITS_99_ETC__q67 = 2'd3; endcase end always@(fork0_sr) begin case (fork0_sr[89:88]) 2'd0, 2'd1, 2'd2: - CASE_fork0_sr_BITS_89_TO_88_3_0_fork0_sr_BITS__ETC__q68 = + CASE_fork0_sr_BITS_89_TO_88_0_fork0_sr_BITS_89_ETC__q68 = fork0_sr[89:88]; - 2'd3: CASE_fork0_sr_BITS_89_TO_88_3_0_fork0_sr_BITS__ETC__q68 = 2'd3; + 2'd3: CASE_fork0_sr_BITS_89_TO_88_0_fork0_sr_BITS_89_ETC__q68 = 2'd3; endcase end always@(fork0_sr) begin case (fork0_sr[79:78]) 2'd0, 2'd1, 2'd2: - CASE_fork0_sr_BITS_79_TO_78_3_0_fork0_sr_BITS__ETC__q69 = + CASE_fork0_sr_BITS_79_TO_78_0_fork0_sr_BITS_79_ETC__q69 = fork0_sr[79:78]; - 2'd3: CASE_fork0_sr_BITS_79_TO_78_3_0_fork0_sr_BITS__ETC__q69 = 2'd3; + 2'd3: CASE_fork0_sr_BITS_79_TO_78_0_fork0_sr_BITS_79_ETC__q69 = 2'd3; endcase end always@(fork0_sr) begin case (fork0_sr[69:68]) 2'd0, 2'd1, 2'd2: - CASE_fork0_sr_BITS_69_TO_68_3_0_fork0_sr_BITS__ETC__q70 = + CASE_fork0_sr_BITS_69_TO_68_0_fork0_sr_BITS_69_ETC__q70 = fork0_sr[69:68]; - 2'd3: CASE_fork0_sr_BITS_69_TO_68_3_0_fork0_sr_BITS__ETC__q70 = 2'd3; + 2'd3: CASE_fork0_sr_BITS_69_TO_68_0_fork0_sr_BITS_69_ETC__q70 = 2'd3; endcase end always@(fork0_sr) begin case (fork0_sr[59:58]) 2'd0, 2'd1, 2'd2: - CASE_fork0_sr_BITS_59_TO_58_3_0_fork0_sr_BITS__ETC__q71 = + CASE_fork0_sr_BITS_59_TO_58_0_fork0_sr_BITS_59_ETC__q71 = fork0_sr[59:58]; - 2'd3: CASE_fork0_sr_BITS_59_TO_58_3_0_fork0_sr_BITS__ETC__q71 = 2'd3; + 2'd3: CASE_fork0_sr_BITS_59_TO_58_0_fork0_sr_BITS_59_ETC__q71 = 2'd3; endcase end always@(fork0_sr) begin case (fork0_sr[49:48]) 2'd0, 2'd1, 2'd2: - CASE_fork0_sr_BITS_49_TO_48_3_0_fork0_sr_BITS__ETC__q72 = + CASE_fork0_sr_BITS_49_TO_48_0_fork0_sr_BITS_49_ETC__q72 = fork0_sr[49:48]; - 2'd3: CASE_fork0_sr_BITS_49_TO_48_3_0_fork0_sr_BITS__ETC__q72 = 2'd3; + 2'd3: CASE_fork0_sr_BITS_49_TO_48_0_fork0_sr_BITS_49_ETC__q72 = 2'd3; endcase end always@(server_request_put) begin case (server_request_put[39:38]) 2'd0, 2'd1, 2'd2: - CASE_server_request_put_BITS_39_TO_38_3_0_serv_ETC__q73 = + CASE_server_request_put_BITS_39_TO_38_0_server_ETC__q73 = server_request_put[39:38]; - 2'd3: CASE_server_request_put_BITS_39_TO_38_3_0_serv_ETC__q73 = 2'd3; + 2'd3: CASE_server_request_put_BITS_39_TO_38_0_server_ETC__q73 = 2'd3; endcase end always@(server_request_put) begin case (server_request_put[29:28]) 2'd0, 2'd1, 2'd2: - CASE_server_request_put_BITS_29_TO_28_3_0_serv_ETC__q74 = + CASE_server_request_put_BITS_29_TO_28_0_server_ETC__q74 = server_request_put[29:28]; - 2'd3: CASE_server_request_put_BITS_29_TO_28_3_0_serv_ETC__q74 = 2'd3; + 2'd3: CASE_server_request_put_BITS_29_TO_28_0_server_ETC__q74 = 2'd3; endcase end always@(server_request_put) begin case (server_request_put[19:18]) 2'd0, 2'd1, 2'd2: - CASE_server_request_put_BITS_19_TO_18_3_0_serv_ETC__q75 = + CASE_server_request_put_BITS_19_TO_18_0_server_ETC__q75 = server_request_put[19:18]; - 2'd3: CASE_server_request_put_BITS_19_TO_18_3_0_serv_ETC__q75 = 2'd3; + 2'd3: CASE_server_request_put_BITS_19_TO_18_0_server_ETC__q75 = 2'd3; endcase end always@(server_request_put) begin case (server_request_put[9:8]) 2'd0, 2'd1, 2'd2: - CASE_server_request_put_BITS_9_TO_8_3_0_server_ETC__q76 = + CASE_server_request_put_BITS_9_TO_8_0_server_r_ETC__q76 = server_request_put[9:8]; - 2'd3: CASE_server_request_put_BITS_9_TO_8_3_0_server_ETC__q76 = 2'd3; + 2'd3: CASE_server_request_put_BITS_9_TO_8_0_server_r_ETC__q76 = 2'd3; endcase end always@(fork1_sr) begin case (fork1_sr[119:118]) 2'd0, 2'd1, 2'd2: - CASE_fork1_sr_BITS_119_TO_118_3_0_fork1_sr_BIT_ETC__q77 = + CASE_fork1_sr_BITS_119_TO_118_0_fork1_sr_BITS__ETC__q77 = fork1_sr[119:118]; - 2'd3: CASE_fork1_sr_BITS_119_TO_118_3_0_fork1_sr_BIT_ETC__q77 = 2'd3; + 2'd3: CASE_fork1_sr_BITS_119_TO_118_0_fork1_sr_BITS__ETC__q77 = 2'd3; endcase end always@(fork1_sr) begin case (fork1_sr[109:108]) 2'd0, 2'd1, 2'd2: - CASE_fork1_sr_BITS_109_TO_108_3_0_fork1_sr_BIT_ETC__q78 = + CASE_fork1_sr_BITS_109_TO_108_0_fork1_sr_BITS__ETC__q78 = fork1_sr[109:108]; - 2'd3: CASE_fork1_sr_BITS_109_TO_108_3_0_fork1_sr_BIT_ETC__q78 = 2'd3; + 2'd3: CASE_fork1_sr_BITS_109_TO_108_0_fork1_sr_BITS__ETC__q78 = 2'd3; endcase end always@(fork1_sr) begin case (fork1_sr[99:98]) 2'd0, 2'd1, 2'd2: - CASE_fork1_sr_BITS_99_TO_98_3_0_fork1_sr_BITS__ETC__q79 = + CASE_fork1_sr_BITS_99_TO_98_0_fork1_sr_BITS_99_ETC__q79 = fork1_sr[99:98]; - 2'd3: CASE_fork1_sr_BITS_99_TO_98_3_0_fork1_sr_BITS__ETC__q79 = 2'd3; + 2'd3: CASE_fork1_sr_BITS_99_TO_98_0_fork1_sr_BITS_99_ETC__q79 = 2'd3; endcase end always@(fork1_sr) begin case (fork1_sr[89:88]) 2'd0, 2'd1, 2'd2: - CASE_fork1_sr_BITS_89_TO_88_3_0_fork1_sr_BITS__ETC__q80 = + CASE_fork1_sr_BITS_89_TO_88_0_fork1_sr_BITS_89_ETC__q80 = fork1_sr[89:88]; - 2'd3: CASE_fork1_sr_BITS_89_TO_88_3_0_fork1_sr_BITS__ETC__q80 = 2'd3; + 2'd3: CASE_fork1_sr_BITS_89_TO_88_0_fork1_sr_BITS_89_ETC__q80 = 2'd3; endcase end always@(fork1_sr) begin case (fork1_sr[79:78]) 2'd0, 2'd1, 2'd2: - CASE_fork1_sr_BITS_79_TO_78_3_0_fork1_sr_BITS__ETC__q81 = + CASE_fork1_sr_BITS_79_TO_78_0_fork1_sr_BITS_79_ETC__q81 = fork1_sr[79:78]; - 2'd3: CASE_fork1_sr_BITS_79_TO_78_3_0_fork1_sr_BITS__ETC__q81 = 2'd3; + 2'd3: CASE_fork1_sr_BITS_79_TO_78_0_fork1_sr_BITS_79_ETC__q81 = 2'd3; endcase end always@(fork1_sr) begin case (fork1_sr[69:68]) 2'd0, 2'd1, 2'd2: - CASE_fork1_sr_BITS_69_TO_68_3_0_fork1_sr_BITS__ETC__q82 = + CASE_fork1_sr_BITS_69_TO_68_0_fork1_sr_BITS_69_ETC__q82 = fork1_sr[69:68]; - 2'd3: CASE_fork1_sr_BITS_69_TO_68_3_0_fork1_sr_BITS__ETC__q82 = 2'd3; + 2'd3: CASE_fork1_sr_BITS_69_TO_68_0_fork1_sr_BITS_69_ETC__q82 = 2'd3; endcase end always@(fork1_sr) begin case (fork1_sr[59:58]) 2'd0, 2'd1, 2'd2: - CASE_fork1_sr_BITS_59_TO_58_3_0_fork1_sr_BITS__ETC__q83 = + CASE_fork1_sr_BITS_59_TO_58_0_fork1_sr_BITS_59_ETC__q83 = fork1_sr[59:58]; - 2'd3: CASE_fork1_sr_BITS_59_TO_58_3_0_fork1_sr_BITS__ETC__q83 = 2'd3; + 2'd3: CASE_fork1_sr_BITS_59_TO_58_0_fork1_sr_BITS_59_ETC__q83 = 2'd3; endcase end always@(fork1_sr) begin case (fork1_sr[49:48]) 2'd0, 2'd1, 2'd2: - CASE_fork1_sr_BITS_49_TO_48_3_0_fork1_sr_BITS__ETC__q84 = + CASE_fork1_sr_BITS_49_TO_48_0_fork1_sr_BITS_49_ETC__q84 = fork1_sr[49:48]; - 2'd3: CASE_fork1_sr_BITS_49_TO_48_3_0_fork1_sr_BITS__ETC__q84 = 2'd3; + 2'd3: CASE_fork1_sr_BITS_49_TO_48_0_fork1_sr_BITS_49_ETC__q84 = 2'd3; endcase end always@(fork0_d1F$D_OUT) begin case (fork0_d1F$D_OUT[39:38]) 2'd0, 2'd1, 2'd2: - CASE_fork0_d1FD_OUT_BITS_39_TO_38_3_0_fork0_d_ETC__q85 = + CASE_fork0_d1FD_OUT_BITS_39_TO_38_0_fork0_d1F_ETC__q85 = fork0_d1F$D_OUT[39:38]; - 2'd3: CASE_fork0_d1FD_OUT_BITS_39_TO_38_3_0_fork0_d_ETC__q85 = 2'd3; + 2'd3: CASE_fork0_d1FD_OUT_BITS_39_TO_38_0_fork0_d1F_ETC__q85 = 2'd3; endcase end always@(fork0_d1F$D_OUT) begin case (fork0_d1F$D_OUT[29:28]) 2'd0, 2'd1, 2'd2: - CASE_fork0_d1FD_OUT_BITS_29_TO_28_3_0_fork0_d_ETC__q86 = + CASE_fork0_d1FD_OUT_BITS_29_TO_28_0_fork0_d1F_ETC__q86 = fork0_d1F$D_OUT[29:28]; - 2'd3: CASE_fork0_d1FD_OUT_BITS_29_TO_28_3_0_fork0_d_ETC__q86 = 2'd3; + 2'd3: CASE_fork0_d1FD_OUT_BITS_29_TO_28_0_fork0_d1F_ETC__q86 = 2'd3; endcase end always@(fork0_d1F$D_OUT) begin case (fork0_d1F$D_OUT[19:18]) 2'd0, 2'd1, 2'd2: - CASE_fork0_d1FD_OUT_BITS_19_TO_18_3_0_fork0_d_ETC__q87 = + CASE_fork0_d1FD_OUT_BITS_19_TO_18_0_fork0_d1F_ETC__q87 = fork0_d1F$D_OUT[19:18]; - 2'd3: CASE_fork0_d1FD_OUT_BITS_19_TO_18_3_0_fork0_d_ETC__q87 = 2'd3; + 2'd3: CASE_fork0_d1FD_OUT_BITS_19_TO_18_0_fork0_d1F_ETC__q87 = 2'd3; endcase end always@(fork0_d1F$D_OUT) begin case (fork0_d1F$D_OUT[9:8]) 2'd0, 2'd1, 2'd2: - CASE_fork0_d1FD_OUT_BITS_9_TO_8_3_0_fork0_d1F_ETC__q88 = + CASE_fork0_d1FD_OUT_BITS_9_TO_8_0_fork0_d1FD_ETC__q88 = fork0_d1F$D_OUT[9:8]; - 2'd3: CASE_fork0_d1FD_OUT_BITS_9_TO_8_3_0_fork0_d1F_ETC__q88 = 2'd3; + 2'd3: CASE_fork0_d1FD_OUT_BITS_9_TO_8_0_fork0_d1FD_ETC__q88 = 2'd3; endcase end always@(client0_response_put) begin case (client0_response_put[39:38]) 2'd0, 2'd1, 2'd2: - CASE_client0_response_put_BITS_39_TO_38_3_0_cl_ETC__q89 = + CASE_client0_response_put_BITS_39_TO_38_0_clie_ETC__q89 = client0_response_put[39:38]; - 2'd3: CASE_client0_response_put_BITS_39_TO_38_3_0_cl_ETC__q89 = 2'd3; + 2'd3: CASE_client0_response_put_BITS_39_TO_38_0_clie_ETC__q89 = 2'd3; endcase end always@(client0_response_put) begin case (client0_response_put[29:28]) 2'd0, 2'd1, 2'd2: - CASE_client0_response_put_BITS_29_TO_28_3_0_cl_ETC__q90 = + CASE_client0_response_put_BITS_29_TO_28_0_clie_ETC__q90 = client0_response_put[29:28]; - 2'd3: CASE_client0_response_put_BITS_29_TO_28_3_0_cl_ETC__q90 = 2'd3; + 2'd3: CASE_client0_response_put_BITS_29_TO_28_0_clie_ETC__q90 = 2'd3; endcase end always@(client0_response_put) begin case (client0_response_put[19:18]) 2'd0, 2'd1, 2'd2: - CASE_client0_response_put_BITS_19_TO_18_3_0_cl_ETC__q91 = + CASE_client0_response_put_BITS_19_TO_18_0_clie_ETC__q91 = client0_response_put[19:18]; - 2'd3: CASE_client0_response_put_BITS_19_TO_18_3_0_cl_ETC__q91 = 2'd3; + 2'd3: CASE_client0_response_put_BITS_19_TO_18_0_clie_ETC__q91 = 2'd3; endcase end always@(client0_response_put) begin case (client0_response_put[9:8]) 2'd0, 2'd1, 2'd2: - CASE_client0_response_put_BITS_9_TO_8_3_0_clie_ETC__q92 = + CASE_client0_response_put_BITS_9_TO_8_0_client_ETC__q92 = client0_response_put[9:8]; - 2'd3: CASE_client0_response_put_BITS_9_TO_8_3_0_clie_ETC__q92 = 2'd3; + 2'd3: CASE_client0_response_put_BITS_9_TO_8_0_client_ETC__q92 = 2'd3; endcase end always@(merge1_fo$D_OUT) begin case (merge1_fo$D_OUT[39:38]) 2'd0, 2'd1, 2'd2: - CASE_merge1_foD_OUT_BITS_39_TO_38_3_0_merge1__ETC__q93 = + CASE_merge1_foD_OUT_BITS_39_TO_38_0_merge1_fo_ETC__q93 = merge1_fo$D_OUT[39:38]; - 2'd3: CASE_merge1_foD_OUT_BITS_39_TO_38_3_0_merge1__ETC__q93 = 2'd3; + 2'd3: CASE_merge1_foD_OUT_BITS_39_TO_38_0_merge1_fo_ETC__q93 = 2'd3; endcase end always@(merge1_fo$D_OUT) begin case (merge1_fo$D_OUT[29:28]) 2'd0, 2'd1, 2'd2: - CASE_merge1_foD_OUT_BITS_29_TO_28_3_0_merge1__ETC__q94 = + CASE_merge1_foD_OUT_BITS_29_TO_28_0_merge1_fo_ETC__q94 = merge1_fo$D_OUT[29:28]; - 2'd3: CASE_merge1_foD_OUT_BITS_29_TO_28_3_0_merge1__ETC__q94 = 2'd3; + 2'd3: CASE_merge1_foD_OUT_BITS_29_TO_28_0_merge1_fo_ETC__q94 = 2'd3; endcase end always@(merge1_fo$D_OUT) begin case (merge1_fo$D_OUT[19:18]) 2'd0, 2'd1, 2'd2: - CASE_merge1_foD_OUT_BITS_19_TO_18_3_0_merge1__ETC__q95 = + CASE_merge1_foD_OUT_BITS_19_TO_18_0_merge1_fo_ETC__q95 = merge1_fo$D_OUT[19:18]; - 2'd3: CASE_merge1_foD_OUT_BITS_19_TO_18_3_0_merge1__ETC__q95 = 2'd3; + 2'd3: CASE_merge1_foD_OUT_BITS_19_TO_18_0_merge1_fo_ETC__q95 = 2'd3; endcase end always@(merge1_fo$D_OUT) begin case (merge1_fo$D_OUT[9:8]) 2'd0, 2'd1, 2'd2: - CASE_merge1_foD_OUT_BITS_9_TO_8_3_0_merge1_fo_ETC__q96 = + CASE_merge1_foD_OUT_BITS_9_TO_8_0_merge1_foD_ETC__q96 = merge1_fo$D_OUT[9:8]; - 2'd3: CASE_merge1_foD_OUT_BITS_9_TO_8_3_0_merge1_fo_ETC__q96 = 2'd3; + 2'd3: CASE_merge1_foD_OUT_BITS_9_TO_8_0_merge1_foD_ETC__q96 = 2'd3; endcase end always@(client1_response_put) begin case (client1_response_put[39:38]) 2'd0, 2'd1, 2'd2: - CASE_client1_response_put_BITS_39_TO_38_3_0_cl_ETC__q97 = + CASE_client1_response_put_BITS_39_TO_38_0_clie_ETC__q97 = client1_response_put[39:38]; - 2'd3: CASE_client1_response_put_BITS_39_TO_38_3_0_cl_ETC__q97 = 2'd3; + 2'd3: CASE_client1_response_put_BITS_39_TO_38_0_clie_ETC__q97 = 2'd3; endcase end always@(client1_response_put) begin case (client1_response_put[29:28]) 2'd0, 2'd1, 2'd2: - CASE_client1_response_put_BITS_29_TO_28_3_0_cl_ETC__q98 = + CASE_client1_response_put_BITS_29_TO_28_0_clie_ETC__q98 = client1_response_put[29:28]; - 2'd3: CASE_client1_response_put_BITS_29_TO_28_3_0_cl_ETC__q98 = 2'd3; + 2'd3: CASE_client1_response_put_BITS_29_TO_28_0_clie_ETC__q98 = 2'd3; endcase end always@(client1_response_put) begin case (client1_response_put[19:18]) 2'd0, 2'd1, 2'd2: - CASE_client1_response_put_BITS_19_TO_18_3_0_cl_ETC__q99 = + CASE_client1_response_put_BITS_19_TO_18_0_clie_ETC__q99 = client1_response_put[19:18]; - 2'd3: CASE_client1_response_put_BITS_19_TO_18_3_0_cl_ETC__q99 = 2'd3; + 2'd3: CASE_client1_response_put_BITS_19_TO_18_0_clie_ETC__q99 = 2'd3; endcase end always@(client1_response_put) begin case (client1_response_put[9:8]) 2'd0, 2'd1, 2'd2: - CASE_client1_response_put_BITS_9_TO_8_3_0_clie_ETC__q100 = + CASE_client1_response_put_BITS_9_TO_8_0_client_ETC__q100 = client1_response_put[9:8]; - 2'd3: CASE_client1_response_put_BITS_9_TO_8_3_0_clie_ETC__q100 = 2'd3; + 2'd3: CASE_client1_response_put_BITS_9_TO_8_0_client_ETC__q100 = 2'd3; endcase end always@(client2_response_put) begin case (client2_response_put[39:38]) 2'd0, 2'd1, 2'd2: - CASE_client2_response_put_BITS_39_TO_38_3_0_cl_ETC__q101 = + CASE_client2_response_put_BITS_39_TO_38_0_clie_ETC__q101 = client2_response_put[39:38]; - 2'd3: CASE_client2_response_put_BITS_39_TO_38_3_0_cl_ETC__q101 = 2'd3; + 2'd3: CASE_client2_response_put_BITS_39_TO_38_0_clie_ETC__q101 = 2'd3; endcase end always@(client2_response_put) begin case (client2_response_put[29:28]) 2'd0, 2'd1, 2'd2: - CASE_client2_response_put_BITS_29_TO_28_3_0_cl_ETC__q102 = + CASE_client2_response_put_BITS_29_TO_28_0_clie_ETC__q102 = client2_response_put[29:28]; - 2'd3: CASE_client2_response_put_BITS_29_TO_28_3_0_cl_ETC__q102 = 2'd3; + 2'd3: CASE_client2_response_put_BITS_29_TO_28_0_clie_ETC__q102 = 2'd3; endcase end always@(client2_response_put) begin case (client2_response_put[19:18]) 2'd0, 2'd1, 2'd2: - CASE_client2_response_put_BITS_19_TO_18_3_0_cl_ETC__q103 = + CASE_client2_response_put_BITS_19_TO_18_0_clie_ETC__q103 = client2_response_put[19:18]; - 2'd3: CASE_client2_response_put_BITS_19_TO_18_3_0_cl_ETC__q103 = 2'd3; + 2'd3: CASE_client2_response_put_BITS_19_TO_18_0_clie_ETC__q103 = 2'd3; endcase end always@(client2_response_put) begin case (client2_response_put[9:8]) 2'd0, 2'd1, 2'd2: - CASE_client2_response_put_BITS_9_TO_8_3_0_clie_ETC__q104 = + CASE_client2_response_put_BITS_9_TO_8_0_client_ETC__q104 = client2_response_put[9:8]; - 2'd3: CASE_client2_response_put_BITS_9_TO_8_3_0_clie_ETC__q104 = 2'd3; + 2'd3: CASE_client2_response_put_BITS_9_TO_8_0_client_ETC__q104 = 2'd3; endcase end diff --git a/rtl/mkSMAdapter16B.v b/rtl/mkSMAdapter16B.v index 6bad17b8..8baae877 100644 --- a/rtl/mkSMAdapter16B.v +++ b/rtl/mkSMAdapter16B.v @@ -1,7 +1,7 @@ // -// Generated by Bluespec Compiler, version 2012.09.beta1 (build 29570, 2012-09.11) +// Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Tue Dec 11 16:21:11 EST 2012 +// On Fri Jun 21 16:57:54 EDT 2013 // // // Ports: @@ -384,6 +384,7 @@ module mkSMAdapter16B(wciS0_Clk, fabRespCredit_acc_v2$whas, mesgPreRequest_1$wget, mesgPreRequest_1$whas, + respF_pwClear$whas, respF_pwDequeue$whas, respF_pwEnqueue$whas, respF_wDataIn$whas, @@ -609,10 +610,10 @@ module mkSMAdapter16B(wciS0_Clk, wire [1 : 0] wci_wslv_reqF_countReg$D_IN; wire wci_wslv_reqF_countReg$EN; - // register wci_wslv_respF_c_r - reg [1 : 0] wci_wslv_respF_c_r; - wire [1 : 0] wci_wslv_respF_c_r$D_IN; - wire wci_wslv_respF_c_r$EN; + // register wci_wslv_respF_cntr_r + reg [1 : 0] wci_wslv_respF_cntr_r; + wire [1 : 0] wci_wslv_respF_cntr_r$D_IN; + wire wci_wslv_respF_cntr_r$EN; // register wci_wslv_respF_q_0 reg [33 : 0] wci_wslv_respF_q_0; @@ -636,10 +637,10 @@ module mkSMAdapter16B(wciS0_Clk, reg wmi_busyWithMessage; wire wmi_busyWithMessage$D_IN, wmi_busyWithMessage$EN; - // register wmi_dhF_c_r - reg [1 : 0] wmi_dhF_c_r; - wire [1 : 0] wmi_dhF_c_r$D_IN; - wire wmi_dhF_c_r$EN; + // register wmi_dhF_cntr_r + reg [1 : 0] wmi_dhF_cntr_r; + wire [1 : 0] wmi_dhF_cntr_r$D_IN; + wire wmi_dhF_cntr_r$EN; // register wmi_dhF_q_0 reg [145 : 0] wmi_dhF_q_0; @@ -659,10 +660,10 @@ module mkSMAdapter16B(wciS0_Clk, reg wmi_isReset_isInReset; wire wmi_isReset_isInReset$D_IN, wmi_isReset_isInReset$EN; - // register wmi_mFlagF_c_r - reg [1 : 0] wmi_mFlagF_c_r; - wire [1 : 0] wmi_mFlagF_c_r$D_IN; - wire wmi_mFlagF_c_r$EN; + // register wmi_mFlagF_cntr_r + reg [1 : 0] wmi_mFlagF_cntr_r; + wire [1 : 0] wmi_mFlagF_cntr_r$D_IN; + wire wmi_mFlagF_cntr_r$EN; // register wmi_mFlagF_q_0 reg [31 : 0] wmi_mFlagF_q_0; @@ -682,10 +683,10 @@ module mkSMAdapter16B(wciS0_Clk, reg wmi_peerIsReady; wire wmi_peerIsReady$D_IN, wmi_peerIsReady$EN; - // register wmi_reqF_c_r - reg [1 : 0] wmi_reqF_c_r; - wire [1 : 0] wmi_reqF_c_r$D_IN; - wire wmi_reqF_c_r$EN; + // register wmi_reqF_cntr_r + reg [1 : 0] wmi_reqF_cntr_r; + wire [1 : 0] wmi_reqF_cntr_r$D_IN; + wire wmi_reqF_cntr_r$EN; // register wmi_reqF_q_0 reg [31 : 0] wmi_reqF_q_0; @@ -765,10 +766,10 @@ module mkSMAdapter16B(wciS0_Clk, reg wsiM_peerIsReady; wire wsiM_peerIsReady$D_IN, wsiM_peerIsReady$EN; - // register wsiM_reqFifo_c_r - reg [1 : 0] wsiM_reqFifo_c_r; - wire [1 : 0] wsiM_reqFifo_c_r$D_IN; - wire wsiM_reqFifo_c_r$EN; + // register wsiM_reqFifo_cntr_r + reg [1 : 0] wsiM_reqFifo_cntr_r; + wire [1 : 0] wsiM_reqFifo_cntr_r$D_IN; + wire wsiM_reqFifo_cntr_r$EN; // register wsiM_reqFifo_q_0 reg [168 : 0] wsiM_reqFifo_q_0; @@ -938,16 +939,16 @@ module mkSMAdapter16B(wciS0_Clk, reg [33 : 0] MUX_wci_wslv_respF_q_0$write_1__VAL_2; wire [168 : 0] MUX_wsiM_reqFifo_q_0$write_1__VAL_1, MUX_wsiM_reqFifo_q_0$write_1__VAL_2, - MUX_wsiM_reqFifo_q_1$write_1__VAL_1, + MUX_wsiM_reqFifo_q_1$write_1__VAL_2, MUX_wsiM_reqFifo_x_wire$wset_1__VAL_3; wire [145 : 0] MUX_wmi_dhF_q_0$write_1__VAL_1, - MUX_wmi_dhF_q_1$write_1__VAL_1, + MUX_wmi_dhF_q_0$write_1__VAL_2, MUX_wmi_dhF_q_1$write_1__VAL_2; wire [33 : 0] MUX_wci_wslv_respF_q_0$write_1__VAL_1, MUX_wci_wslv_respF_q_1$write_1__VAL_1, MUX_wci_wslv_respF_x_wire$wset_1__VAL_1, MUX_wci_wslv_respF_x_wire$wset_1__VAL_2; - wire [31 : 0] MUX_mesgCount$write_1__VAL_1, + wire [31 : 0] MUX_mesgCount$write_1__VAL_2, MUX_thisMesg$write_1__VAL_1, MUX_thisMesg$write_1__VAL_2, MUX_wmi_mFlagF_q_0$write_1__VAL_1, @@ -961,20 +962,15 @@ module mkSMAdapter16B(wciS0_Clk, wire [15 : 0] MUX_unrollCnt$write_1__VAL_1, MUX_unrollCnt$write_1__VAL_2; wire [13 : 0] MUX_fabWordsRemain$write_1__VAL_1, MUX_fabWordsRemain$write_1__VAL_2, - MUX_mesgLengthSoFar$write_1__VAL_1, MUX_mesgReqAddr$write_1__VAL_2; wire [11 : 0] MUX_fabRespCredit_value$write_1__VAL_2; wire [8 : 0] MUX_opcode$write_1__VAL_3; - wire [1 : 0] MUX_wci_wslv_respF_c_r$write_1__VAL_1, - MUX_wci_wslv_respF_c_r$write_1__VAL_2, - MUX_wmi_dhF_c_r$write_1__VAL_1, - MUX_wmi_dhF_c_r$write_1__VAL_2, - MUX_wmi_mFlagF_c_r$write_1__VAL_1, - MUX_wmi_mFlagF_c_r$write_1__VAL_2, - MUX_wmi_reqF_c_r$write_1__VAL_1, - MUX_wmi_reqF_c_r$write_1__VAL_2, - MUX_wsiM_reqFifo_c_r$write_1__VAL_1, - MUX_wsiM_reqFifo_c_r$write_1__VAL_2; + wire [1 : 0] MUX_wci_wslv_respF_cntr_r$write_1__VAL_2, + MUX_wmi_dhF_cntr_r$write_1__VAL_2, + MUX_wmi_mFlagF_cntr_r$write_1__VAL_2, + MUX_wmi_reqF_cntr_r$write_1__VAL_2, + MUX_wsiM_reqFifo_cntr_r$write_1__VAL_1, + MUX_wsiM_reqFifo_cntr_r$write_1__VAL_2; wire MUX_endOfMessage$write_1__SEL_1, MUX_mesgCount$write_1__SEL_1, MUX_mesgReqOK$write_1__SEL_3, @@ -982,99 +978,123 @@ module mkSMAdapter16B(wciS0_Clk, MUX_unrollCnt$write_1__SEL_2, MUX_wci_wslv_illegalEdge$write_1__SEL_1, MUX_wci_wslv_illegalEdge$write_1__VAL_1, + MUX_wci_wslv_respF_q_0$write_1__SEL_1, MUX_wci_wslv_respF_q_0$write_1__SEL_2, + MUX_wci_wslv_respF_q_1$write_1__SEL_1, MUX_wci_wslv_respF_q_1$write_1__SEL_2, + MUX_wmi_dhF_q_0$write_1__SEL_1, MUX_wmi_dhF_q_0$write_1__SEL_2, + MUX_wmi_dhF_q_1$write_1__SEL_1, MUX_wmi_dhF_q_1$write_1__SEL_2, + MUX_wmi_mFlagF_q_0$write_1__SEL_1, MUX_wmi_mFlagF_q_0$write_1__SEL_2, + MUX_wmi_mFlagF_q_1$write_1__SEL_1, MUX_wmi_mFlagF_q_1$write_1__SEL_2, MUX_wmi_mFlagF_x_wire$wset_1__SEL_1, + MUX_wmi_reqF_q_0$write_1__SEL_1, MUX_wmi_reqF_q_0$write_1__SEL_2, + MUX_wmi_reqF_q_1$write_1__SEL_1, MUX_wmi_reqF_q_1$write_1__SEL_2, + MUX_wsiM_reqFifo_q_0$write_1__SEL_1, MUX_wsiM_reqFifo_q_0$write_1__SEL_2, + MUX_wsiM_reqFifo_q_1$write_1__SEL_1, MUX_wsiM_reqFifo_q_1$write_1__SEL_2, MUX_wsiM_reqFifo_x_wire$wset_1__SEL_1, MUX_wsiM_reqFifo_x_wire$wset_1__SEL_2, MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3; // remaining internal signals - reg [63 : 0] v__h18699, - v__h22418, - v__h22477, - v__h24317, - v__h24500, - v__h24696, - v__h25358, - v__h3729, - v__h3904, - v__h4048; - reg [31 : 0] g_data__h24868; - wire [163 : 0] IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d928; - wire [31 : 0] rdat__h24911, - rdat__h24917, - rdat__h24923, - rdat__h24936, - rdat__h24959, - rdat__h25059, - rdat__h25073, - rdat__h25081, - rdat__h25087, - rdat__h25101, - rdat__h25109, - rdat__h25115, - rdat__h25121, - rdat__h25127, - rdat__h25133, - rdat__h25143, - value__h6702, - x__h19302; - wire [23 : 0] b__h18410, - mesgMetaF_length__h22999, - residue__h18273, - x__h18530; - wire [15 : 0] sendData_byteEn__h19245, - wsiBurstLength__h19161, - x__h24963, - x_length__h23891; - wire [13 : 0] b__h18783, mlB__h22832, mlInc__h22831; - wire [11 : 0] b__h15473, sendData_burstLength__h19243, x__h16878; - wire [7 : 0] mesgMetaF_opcode__h22998; - wire [4 : 0] x__h23038, - x__h23050, - x__h23062, - x__h23074, - x__h23086, - x__h23098, - x__h23110, - x__h23122, - x__h23134, - x__h23146, - x__h23158, - x__h23170, - x__h23182, - x__h23194, - x__h23206, - y__h23039, - y__h23051, - y__h23063, - y__h23075, - y__h23087, - y__h23099, - y__h23111, - y__h23123, - y__h23135, - y__h23147, - y__h23159, - y__h23171, - y__h23183, - y__h23195, - y__h23207; - wire [2 : 0] IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d920; - wire NOT_wmi_reqF_c_r_57_EQ_2_75_76_AND_wmi_operate_ETC___d524, - wmi_respF_i_notEmpty__37_AND_smaCtrl_65_BIT_4__ETC___d542, - wsiS_reqFifo_i_notEmpty__64_AND_NOT_smaCtrl_65_ETC___d670, - x__h18954, - x__h25137; + reg [63 : 0] v__h18073, + v__h22489, + v__h22548, + v__h24386, + v__h24569, + v__h24765, + v__h25422, + v__h3597, + v__h3772, + v__h3916; + reg [31 : 0] g_data__h24937; + wire [163 : 0] IF_respF_wDataIn_whas__28_THEN_respF_wDataIn_w_ETC___d437; + wire [31 : 0] rdat__h24980, + rdat__h24986, + rdat__h24992, + rdat__h25005, + rdat__h25028, + rdat__h25128, + rdat__h25142, + rdat__h25150, + rdat__h25156, + rdat__h25170, + rdat__h25178, + rdat__h25184, + rdat__h25190, + rdat__h25196, + rdat__h25202, + rdat__h25212, + value__h6387, + x__h18676; + wire [23 : 0] b__h17784, + mesgMetaF_length__h23070, + residue__h17647, + x__h17904; + wire [15 : 0] sendData_byteEn__h18619, + wsiBurstLength__h18535, + x__h25032, + x_length__h23961; + wire [13 : 0] b__h18157, mlB__h22903, mlInc__h22902; + wire [11 : 0] b__h14802, sendData_burstLength__h18617, x__h16103, x__h16253; + wire [7 : 0] mesgMetaF_opcode__h23069; + wire [4 : 0] x__h23108, + x__h23120, + x__h23132, + x__h23144, + x__h23156, + x__h23168, + x__h23180, + x__h23192, + x__h23204, + x__h23216, + x__h23228, + x__h23240, + x__h23252, + x__h23264, + x__h23276, + y__h23109, + y__h23121, + y__h23133, + y__h23145, + y__h23157, + y__h23169, + y__h23181, + y__h23193, + y__h23205, + y__h23217, + y__h23229, + y__h23241, + y__h23253, + y__h23265, + y__h23277; + wire [2 : 0] IF_respF_wDataIn_whas__28_THEN_respF_wDataIn_w_ETC___d431; + wire [1 : 0] wci_wslv_respF_cntr_r_8_MINUS_1___d27, + wmi_dhF_cntr_r_05_MINUS_1___d213, + wmi_mFlagF_cntr_r_83_MINUS_1___d191, + wmi_reqF_cntr_r_61_MINUS_1___d169; + wire NOT_wmi_reqF_cntr_r_61_EQ_2_73_74_AND_wmi_oper_ETC___d521, + _dfoo1, + _dfoo11, + _dfoo13, + _dfoo15, + _dfoo17, + _dfoo19, + _dfoo3, + _dfoo5, + _dfoo7, + _dfoo9, + wmi_respF_i_notEmpty__34_AND_smaCtrl_62_BIT_4__ETC___d539, + wsiS_reqFifo_i_notEmpty__61_AND_NOT_smaCtrl_62_ETC___d667, + x__h18328, + x__h25206; // value method wciS0_sResp assign wciS0_SResp = wci_wslv_respF_q_0[33:32] ; @@ -1234,7 +1254,7 @@ module mkSMAdapter16B(wciS0_Clk, // rule RL_wmrd_mesgBodyRequest assign WILL_FIRE_RL_wmrd_mesgBodyRequest = - NOT_wmi_reqF_c_r_57_EQ_2_75_76_AND_wmi_operate_ETC___d524 && + NOT_wmi_reqF_cntr_r_61_EQ_2_73_74_AND_wmi_oper_ETC___d521 && wci_wslv_cState == 3'd2 && (smaCtrl[3:0] == 4'h1 || smaCtrl[3:0] == 4'h4 || smaCtrl[3:0] == 4'h9) && @@ -1265,18 +1285,18 @@ module mkSMAdapter16B(wciS0_Clk, // rule RL_wsiM_reqFifo_deq assign WILL_FIRE_RL_wsiM_reqFifo_deq = - wsiM_reqFifo_c_r != 2'd0 && !wsiM_sThreadBusy_d ; + wsiM_reqFifo_cntr_r != 2'd0 && !wsiM_sThreadBusy_d ; // rule RL_wsipass_doMessagePush assign WILL_FIRE_RL_wsipass_doMessagePush = wsiS_reqFifo$EMPTY_N && - (smaCtrl[4] || wsiM_reqFifo_c_r != 2'd2) && + (smaCtrl[4] || wsiM_reqFifo_cntr_r != 2'd2) && wci_wslv_cState == 3'd2 && smaCtrl[3:0] == 4'h0 ; // rule RL_wci_cfrd assign WILL_FIRE_RL_wci_cfrd = - wci_wslv_respF_c_r != 2'd2 && wci_wslv_reqF$EMPTY_N && + wci_wslv_respF_cntr_r != 2'd2 && wci_wslv_reqF$EMPTY_N && wci_wslv_wci_cfrd_pw$whas && !WILL_FIRE_RL_wci_wslv_ctl_op_start && !WILL_FIRE_RL_wci_wslv_ctl_op_complete ; @@ -1295,9 +1315,10 @@ module mkSMAdapter16B(wciS0_Clk, // rule RL_wmwt_messagePush assign CAN_FIRE_RL_wmwt_messagePush = - wmi_reqF_c_r != 2'd2 && wmi_dhF_c_r != 2'd2 && wmi_operateD && + wmi_reqF_cntr_r != 2'd2 && wmi_dhF_cntr_r != 2'd2 && + wmi_operateD && wmi_peerIsReady && - wsiS_reqFifo_i_notEmpty__64_AND_NOT_smaCtrl_65_ETC___d670 && + wsiS_reqFifo_i_notEmpty__61_AND_NOT_smaCtrl_62_ETC___d667 && wci_wslv_cState == 3'd2 && (smaCtrl[3:0] == 4'h2 || smaCtrl[3:0] == 4'h3) && readyToPush ; @@ -1317,10 +1338,7 @@ module mkSMAdapter16B(wciS0_Clk, // rule RL_wmi_reqF_incCtr assign WILL_FIRE_RL_wmi_reqF_incCtr = - ((wmi_reqF_c_r == 2'd0) ? - wmi_reqF_x_wire$whas : - wmi_reqF_c_r != 2'd1 || wmi_reqF_x_wire$whas) && - wmi_reqF_enqueueing$whas && + wmi_reqF_x_wire$whas && wmi_reqF_enqueueing$whas && !wmi_reqF_dequeueing$whas ; // rule RL_wmi_reqF_decCtr @@ -1329,18 +1347,12 @@ module mkSMAdapter16B(wciS0_Clk, // rule RL_wmi_reqF_both assign WILL_FIRE_RL_wmi_reqF_both = - ((wmi_reqF_c_r == 2'd1) ? - wmi_reqF_x_wire$whas : - wmi_reqF_c_r != 2'd2 || wmi_reqF_x_wire$whas) && - wmi_reqF_dequeueing$whas && + wmi_reqF_x_wire$whas && wmi_reqF_dequeueing$whas && wmi_reqF_enqueueing$whas ; // rule RL_wmi_mFlagF_incCtr assign WILL_FIRE_RL_wmi_mFlagF_incCtr = - ((wmi_mFlagF_c_r == 2'd0) ? - wmi_mFlagF_enqueueing$whas : - wmi_mFlagF_c_r != 2'd1 || wmi_mFlagF_enqueueing$whas) && - wmi_mFlagF_enqueueing$whas && + wmi_mFlagF_enqueueing$whas && wmi_mFlagF_enqueueing$whas && !wmi_mFlagF_dequeueing$whas ; // rule RL_wmi_mFlagF_decCtr @@ -1349,18 +1361,12 @@ module mkSMAdapter16B(wciS0_Clk, // rule RL_wmi_mFlagF_both assign WILL_FIRE_RL_wmi_mFlagF_both = - ((wmi_mFlagF_c_r == 2'd1) ? - wmi_mFlagF_enqueueing$whas : - wmi_mFlagF_c_r != 2'd2 || wmi_mFlagF_enqueueing$whas) && - wmi_mFlagF_dequeueing$whas && + wmi_mFlagF_enqueueing$whas && wmi_mFlagF_dequeueing$whas && wmi_mFlagF_enqueueing$whas ; // rule RL_wmi_dhF_incCtr assign WILL_FIRE_RL_wmi_dhF_incCtr = - ((wmi_dhF_c_r == 2'd0) ? - MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 : - wmi_dhF_c_r != 2'd1 || - MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3) && + MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 && MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 && !wmi_dhF_dequeueing$whas ; @@ -1371,33 +1377,27 @@ module mkSMAdapter16B(wciS0_Clk, // rule RL_wmi_dhF_both assign WILL_FIRE_RL_wmi_dhF_both = - ((wmi_dhF_c_r == 2'd1) ? - MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 : - wmi_dhF_c_r != 2'd2 || - MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3) && + MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 && wmi_dhF_dequeueing$whas && MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 ; // rule RL_wmrd_mesgResptoWsi assign WILL_FIRE_RL_wmrd_mesgResptoWsi = - wsiM_reqFifo_c_r != 2'd2 && respF_rRdPtr != respF_rWrPtr && + wsiM_reqFifo_cntr_r != 2'd2 && respF_rRdPtr != respF_rWrPtr && wci_wslv_cState == 3'd2 && (smaCtrl[3:0] == 4'h1 || smaCtrl[3:0] == 4'h4 || smaCtrl[3:0] == 4'h9) ; // rule RL_wci_cfwr assign WILL_FIRE_RL_wci_cfwr = - wci_wslv_respF_c_r != 2'd2 && wci_wslv_reqF$EMPTY_N && + wci_wslv_respF_cntr_r != 2'd2 && wci_wslv_reqF$EMPTY_N && wci_wslv_wci_cfwr_pw$whas && !WILL_FIRE_RL_wci_wslv_ctl_op_start && !WILL_FIRE_RL_wci_wslv_ctl_op_complete ; // rule RL_wsiM_reqFifo_incCtr assign WILL_FIRE_RL_wsiM_reqFifo_incCtr = - ((wsiM_reqFifo_c_r == 2'd0) ? - wsiM_reqFifo_enqueueing$whas : - wsiM_reqFifo_c_r != 2'd1 || wsiM_reqFifo_enqueueing$whas) && - wsiM_reqFifo_enqueueing$whas && + wsiM_reqFifo_enqueueing$whas && wsiM_reqFifo_enqueueing$whas && !WILL_FIRE_RL_wsiM_reqFifo_deq ; // rule RL_wsiM_reqFifo_decCtr @@ -1406,10 +1406,7 @@ module mkSMAdapter16B(wciS0_Clk, // rule RL_wsiM_reqFifo_both assign WILL_FIRE_RL_wsiM_reqFifo_both = - ((wsiM_reqFifo_c_r == 2'd1) ? - wsiM_reqFifo_enqueueing$whas : - wsiM_reqFifo_c_r != 2'd2 || wsiM_reqFifo_enqueueing$whas) && - WILL_FIRE_RL_wsiM_reqFifo_deq && + wsiM_reqFifo_enqueueing$whas && WILL_FIRE_RL_wsiM_reqFifo_deq && wsiM_reqFifo_enqueueing$whas ; // rule RL_wci_ctrl_IsO @@ -1421,27 +1418,22 @@ module mkSMAdapter16B(wciS0_Clk, // rule RL_wci_wslv_ctl_op_complete assign WILL_FIRE_RL_wci_wslv_ctl_op_complete = - wci_wslv_respF_c_r != 2'd2 && wci_wslv_ctlOpActive && + wci_wslv_respF_cntr_r != 2'd2 && wci_wslv_ctlOpActive && wci_wslv_ctlAckReg ; // rule RL_wci_wslv_respF_incCtr assign WILL_FIRE_RL_wci_wslv_respF_incCtr = - ((wci_wslv_respF_c_r == 2'd0) ? - wci_wslv_respF_x_wire$whas : - wci_wslv_respF_c_r != 2'd1 || wci_wslv_respF_x_wire$whas) && - wci_wslv_respF_enqueueing$whas && - !(wci_wslv_respF_c_r != 2'd0) ; + wci_wslv_respF_x_wire$whas && wci_wslv_respF_enqueueing$whas && + !(wci_wslv_respF_cntr_r != 2'd0) ; // rule RL_wci_wslv_respF_decCtr assign WILL_FIRE_RL_wci_wslv_respF_decCtr = - wci_wslv_respF_c_r != 2'd0 && !wci_wslv_respF_enqueueing$whas ; + wci_wslv_respF_cntr_r != 2'd0 && + !wci_wslv_respF_enqueueing$whas ; // rule RL_wci_wslv_respF_both assign WILL_FIRE_RL_wci_wslv_respF_both = - ((wci_wslv_respF_c_r == 2'd1) ? - wci_wslv_respF_x_wire$whas : - wci_wslv_respF_c_r != 2'd2 || wci_wslv_respF_x_wire$whas) && - wci_wslv_respF_c_r != 2'd0 && + wci_wslv_respF_x_wire$whas && wci_wslv_respF_cntr_r != 2'd0 && wci_wslv_respF_enqueueing$whas ; // rule RL_wsiS_reqFifo_enq @@ -1470,7 +1462,7 @@ module mkSMAdapter16B(wciS0_Clk, !wmi_sDataThreadBusy_d && unrollCnt == 16'd0 ; assign MUX_unrollCnt$write_1__SEL_2 = - wmi_respF_i_notEmpty__37_AND_smaCtrl_65_BIT_4__ETC___d542 && + wmi_respF_i_notEmpty__34_AND_smaCtrl_62_BIT_4__ETC___d539 && wci_wslv_cState == 3'd2 && (smaCtrl[3:0] == 4'h1 || smaCtrl[3:0] == 4'h4 || smaCtrl[3:0] == 4'h9) && @@ -1488,66 +1480,84 @@ module mkSMAdapter16B(wciS0_Clk, wci_wslv_reqF$D_OUT[36:34] == 3'd5 || wci_wslv_reqF$D_OUT[36:34] == 3'd6 || wci_wslv_reqF$D_OUT[36:34] == 3'd7) ; + assign MUX_wci_wslv_respF_q_0$write_1__SEL_1 = + WILL_FIRE_RL_wci_wslv_respF_both && _dfoo3 ; assign MUX_wci_wslv_respF_q_0$write_1__SEL_2 = WILL_FIRE_RL_wci_wslv_respF_incCtr && - wci_wslv_respF_c_r == 2'd0 ; + wci_wslv_respF_cntr_r == 2'd0 ; + assign MUX_wci_wslv_respF_q_1$write_1__SEL_1 = + WILL_FIRE_RL_wci_wslv_respF_both && _dfoo1 ; assign MUX_wci_wslv_respF_q_1$write_1__SEL_2 = WILL_FIRE_RL_wci_wslv_respF_incCtr && - wci_wslv_respF_c_r == 2'd1 ; + wci_wslv_respF_cntr_r == 2'd1 ; + assign MUX_wmi_dhF_q_0$write_1__SEL_1 = + WILL_FIRE_RL_wmi_dhF_incCtr && wmi_dhF_cntr_r == 2'd0 ; assign MUX_wmi_dhF_q_0$write_1__SEL_2 = - WILL_FIRE_RL_wmi_dhF_incCtr && wmi_dhF_c_r == 2'd0 ; + WILL_FIRE_RL_wmi_dhF_both && _dfoo15 ; + assign MUX_wmi_dhF_q_1$write_1__SEL_1 = + WILL_FIRE_RL_wmi_dhF_incCtr && wmi_dhF_cntr_r == 2'd1 ; assign MUX_wmi_dhF_q_1$write_1__SEL_2 = - WILL_FIRE_RL_wmi_dhF_incCtr && wmi_dhF_c_r == 2'd1 ; + WILL_FIRE_RL_wmi_dhF_both && _dfoo13 ; + assign MUX_wmi_mFlagF_q_0$write_1__SEL_1 = + WILL_FIRE_RL_wmi_mFlagF_both && _dfoo11 ; assign MUX_wmi_mFlagF_q_0$write_1__SEL_2 = - WILL_FIRE_RL_wmi_mFlagF_incCtr && wmi_mFlagF_c_r == 2'd0 ; + WILL_FIRE_RL_wmi_mFlagF_incCtr && wmi_mFlagF_cntr_r == 2'd0 ; + assign MUX_wmi_mFlagF_q_1$write_1__SEL_1 = + WILL_FIRE_RL_wmi_mFlagF_both && _dfoo9 ; assign MUX_wmi_mFlagF_q_1$write_1__SEL_2 = - WILL_FIRE_RL_wmi_mFlagF_incCtr && wmi_mFlagF_c_r == 2'd1 ; + WILL_FIRE_RL_wmi_mFlagF_incCtr && wmi_mFlagF_cntr_r == 2'd1 ; assign MUX_wmi_mFlagF_x_wire$wset_1__SEL_1 = - WILL_FIRE_RL_wmrd_mesgBodyRequest && x__h18954 ; + WILL_FIRE_RL_wmrd_mesgBodyRequest && x__h18328 ; + assign MUX_wmi_reqF_q_0$write_1__SEL_1 = + WILL_FIRE_RL_wmi_reqF_both && _dfoo7 ; assign MUX_wmi_reqF_q_0$write_1__SEL_2 = - WILL_FIRE_RL_wmi_reqF_incCtr && wmi_reqF_c_r == 2'd0 ; + WILL_FIRE_RL_wmi_reqF_incCtr && wmi_reqF_cntr_r == 2'd0 ; + assign MUX_wmi_reqF_q_1$write_1__SEL_1 = + WILL_FIRE_RL_wmi_reqF_both && _dfoo5 ; assign MUX_wmi_reqF_q_1$write_1__SEL_2 = - WILL_FIRE_RL_wmi_reqF_incCtr && wmi_reqF_c_r == 2'd1 ; + WILL_FIRE_RL_wmi_reqF_incCtr && wmi_reqF_cntr_r == 2'd1 ; + assign MUX_wsiM_reqFifo_q_0$write_1__SEL_1 = + WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_cntr_r == 2'd0 ; assign MUX_wsiM_reqFifo_q_0$write_1__SEL_2 = - WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_c_r == 2'd0 ; + WILL_FIRE_RL_wsiM_reqFifo_both && _dfoo19 ; + assign MUX_wsiM_reqFifo_q_1$write_1__SEL_1 = + WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_cntr_r == 2'd1 ; assign MUX_wsiM_reqFifo_q_1$write_1__SEL_2 = - WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_c_r == 2'd1 ; + WILL_FIRE_RL_wsiM_reqFifo_both && _dfoo17 ; assign MUX_wsiM_reqFifo_x_wire$wset_1__SEL_1 = - WILL_FIRE_RL_wsipass_doMessagePush && !smaCtrl[4] ; - assign MUX_wsiM_reqFifo_x_wire$wset_1__SEL_2 = MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 && smaCtrl[3:0] == 4'h3 ; + assign MUX_wsiM_reqFifo_x_wire$wset_1__SEL_2 = + WILL_FIRE_RL_wsipass_doMessagePush && !smaCtrl[4] ; assign MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 = CAN_FIRE_RL_wmwt_messagePush && !WILL_FIRE_RL_wmwt_messageFinalize ; assign MUX_fabRespCredit_value$write_1__VAL_2 = fabRespCredit_value + - (WILL_FIRE_RL_wmrd_mesgBodyRequest ? b__h15473 : 12'd0) + + (WILL_FIRE_RL_wmrd_mesgBodyRequest ? b__h14802 : 12'd0) + (WILL_FIRE_RL_wmrd_mesgResptoWsi ? 12'd1 : 12'd0) ; assign MUX_fabWordsRemain$write_1__VAL_1 = - (wmi_sFlagReg[23:0] == 24'd0) ? 14'd1 : b__h18410[13:0] ; + (wmi_sFlagReg[23:0] == 24'd0) ? 14'd1 : b__h17784[13:0] ; assign MUX_fabWordsRemain$write_1__VAL_2 = fabWordsRemain - fabWordsCurReq ; - assign MUX_mesgCount$write_1__VAL_1 = mesgCount + 32'd1 ; - assign MUX_mesgLengthSoFar$write_1__VAL_1 = - mesgLengthSoFar + mlInc__h22831 ; + assign MUX_mesgCount$write_1__VAL_2 = mesgCount + 32'd1 ; assign MUX_mesgReqAddr$write_1__VAL_2 = mesgReqAddr + { fabWordsCurReq[9:0], 4'd0 } ; assign MUX_opcode$write_1__VAL_3 = { 1'd1, wsiS_reqFifo$D_OUT[7:0] } ; assign MUX_thisMesg$write_1__VAL_1 = - { mesgCount[7:0], mesgMetaF_opcode__h22998, x_length__h23891 } ; + { mesgCount[7:0], mesgMetaF_opcode__h23069, x_length__h23961 } ; assign MUX_thisMesg$write_1__VAL_2 = { mesgCount[7:0], wmi_sFlagReg[31:24], wmi_sFlagReg[15:0] } ; assign MUX_unrollCnt$write_1__VAL_1 = - (wmi_sFlagReg[23:0] == 24'd0) ? 16'd1 : b__h18410[15:0] ; + (wmi_sFlagReg[23:0] == 24'd0) ? 16'd1 : b__h17784[15:0] ; assign MUX_unrollCnt$write_1__VAL_2 = unrollCnt - 16'd1 ; assign MUX_wci_wslv_illegalEdge$write_1__VAL_1 = wci_wslv_reqF$D_OUT[36:34] != 3'd4 && wci_wslv_reqF$D_OUT[36:34] != 3'd5 && wci_wslv_reqF$D_OUT[36:34] != 3'd6 ; - assign MUX_wci_wslv_respF_c_r$write_1__VAL_1 = wci_wslv_respF_c_r + 2'd1 ; - assign MUX_wci_wslv_respF_c_r$write_1__VAL_2 = wci_wslv_respF_c_r - 2'd1 ; + assign MUX_wci_wslv_respF_cntr_r$write_1__VAL_2 = + wci_wslv_respF_cntr_r + 2'd1 ; assign MUX_wci_wslv_respF_q_0$write_1__VAL_1 = - (wci_wslv_respF_c_r == 2'd1) ? + (wci_wslv_respF_cntr_r == 2'd1) ? MUX_wci_wslv_respF_q_0$write_1__VAL_2 : wci_wslv_respF_q_1 ; always@(WILL_FIRE_RL_wci_wslv_ctl_op_complete or @@ -1569,34 +1579,33 @@ module mkSMAdapter16B(wciS0_Clk, endcase end assign MUX_wci_wslv_respF_q_1$write_1__VAL_1 = - (wci_wslv_respF_c_r == 2'd2) ? + (wci_wslv_respF_cntr_r == 2'd2) ? MUX_wci_wslv_respF_q_0$write_1__VAL_2 : 34'h0AAAAAAAA ; assign MUX_wci_wslv_respF_x_wire$wset_1__VAL_1 = wci_wslv_illegalEdge ? 34'h3C0DE4202 : 34'h1C0DE4201 ; - assign MUX_wci_wslv_respF_x_wire$wset_1__VAL_2 = { 2'd1, g_data__h24868 } ; - assign MUX_wmi_dhF_c_r$write_1__VAL_1 = wmi_dhF_c_r + 2'd1 ; - assign MUX_wmi_dhF_c_r$write_1__VAL_2 = wmi_dhF_c_r - 2'd1 ; + assign MUX_wci_wslv_respF_x_wire$wset_1__VAL_2 = { 2'd1, g_data__h24937 } ; + assign MUX_wmi_dhF_cntr_r$write_1__VAL_2 = wmi_dhF_cntr_r + 2'd1 ; assign MUX_wmi_dhF_q_0$write_1__VAL_1 = - (wmi_dhF_c_r == 2'd1) ? - MUX_wmi_dhF_q_1$write_1__VAL_2 : + { 1'd1, wsiS_reqFifo$D_OUT[165], wsiS_reqFifo$D_OUT[151:8] } ; + assign MUX_wmi_dhF_q_0$write_1__VAL_2 = + (wmi_dhF_cntr_r == 2'd1) ? + MUX_wmi_dhF_q_0$write_1__VAL_1 : wmi_dhF_q_1 ; - assign MUX_wmi_dhF_q_1$write_1__VAL_1 = - (wmi_dhF_c_r == 2'd2) ? MUX_wmi_dhF_q_1$write_1__VAL_2 : 146'd0 ; assign MUX_wmi_dhF_q_1$write_1__VAL_2 = - { 1'd1, wsiS_reqFifo$D_OUT[165], wsiS_reqFifo$D_OUT[151:8] } ; - assign MUX_wmi_mFlagF_c_r$write_1__VAL_1 = wmi_mFlagF_c_r + 2'd1 ; - assign MUX_wmi_mFlagF_c_r$write_1__VAL_2 = wmi_mFlagF_c_r - 2'd1 ; + (wmi_dhF_cntr_r == 2'd2) ? + MUX_wmi_dhF_q_0$write_1__VAL_1 : + 146'd0 ; + assign MUX_wmi_mFlagF_cntr_r$write_1__VAL_2 = wmi_mFlagF_cntr_r + 2'd1 ; assign MUX_wmi_mFlagF_q_0$write_1__VAL_1 = - (wmi_mFlagF_c_r == 2'd1) ? value__h6702 : wmi_mFlagF_q_1 ; + (wmi_mFlagF_cntr_r == 2'd1) ? value__h6387 : wmi_mFlagF_q_1 ; assign MUX_wmi_mFlagF_q_1$write_1__VAL_1 = - (wmi_mFlagF_c_r == 2'd2) ? value__h6702 : 32'd0 ; + (wmi_mFlagF_cntr_r == 2'd2) ? value__h6387 : 32'd0 ; assign MUX_wmi_mFlagF_x_wire$wset_1__VAL_2 = - { mesgMetaF_opcode__h22998, mesgMetaF_length__h22999 } ; - assign MUX_wmi_reqF_c_r$write_1__VAL_1 = wmi_reqF_c_r + 2'd1 ; - assign MUX_wmi_reqF_c_r$write_1__VAL_2 = wmi_reqF_c_r - 2'd1 ; + { mesgMetaF_opcode__h23069, mesgMetaF_length__h23070 } ; + assign MUX_wmi_reqF_cntr_r$write_1__VAL_2 = wmi_reqF_cntr_r + 2'd1 ; assign MUX_wmi_reqF_q_0$write_1__VAL_1 = - (wmi_reqF_c_r == 2'd1) ? + (wmi_reqF_cntr_r == 2'd1) ? MUX_wmi_reqF_q_0$write_1__VAL_2 : wmi_reqF_q_1 ; assign MUX_wmi_reqF_q_0$write_1__VAL_2 = @@ -1604,27 +1613,27 @@ module mkSMAdapter16B(wciS0_Clk, MUX_wmi_reqF_x_wire$wset_1__VAL_1 : MUX_wmi_reqF_x_wire$wset_1__VAL_2 ; assign MUX_wmi_reqF_q_1$write_1__VAL_1 = - (wmi_reqF_c_r == 2'd2) ? + (wmi_reqF_cntr_r == 2'd2) ? MUX_wmi_reqF_q_0$write_1__VAL_2 : 32'd0 ; assign MUX_wmi_reqF_x_wire$wset_1__VAL_1 = - { 4'd5, x__h18954, 1'b0, mesgReqAddr, fabWordsCurReq[11:0] } ; + { 4'd5, x__h18328, 1'b0, mesgReqAddr, fabWordsCurReq[11:0] } ; assign MUX_wmi_reqF_x_wire$wset_1__VAL_2 = { 4'd3, wsiS_reqFifo$D_OUT[165], 1'b0, mesgLengthSoFar, 12'd1 } ; - assign MUX_wsiM_reqFifo_c_r$write_1__VAL_1 = wsiM_reqFifo_c_r + 2'd1 ; - assign MUX_wsiM_reqFifo_c_r$write_1__VAL_2 = wsiM_reqFifo_c_r - 2'd1 ; + assign MUX_wsiM_reqFifo_cntr_r$write_1__VAL_1 = wsiM_reqFifo_cntr_r - 2'd1 ; + assign MUX_wsiM_reqFifo_cntr_r$write_1__VAL_2 = wsiM_reqFifo_cntr_r + 2'd1 ; assign MUX_wsiM_reqFifo_q_0$write_1__VAL_1 = - (wsiM_reqFifo_c_r == 2'd1) ? - MUX_wsiM_reqFifo_q_0$write_1__VAL_2 : - wsiM_reqFifo_q_1 ; - assign MUX_wsiM_reqFifo_q_0$write_1__VAL_2 = (MUX_wsiM_reqFifo_x_wire$wset_1__SEL_1 || MUX_wsiM_reqFifo_x_wire$wset_1__SEL_2) ? wsiS_reqFifo$D_OUT : MUX_wsiM_reqFifo_x_wire$wset_1__VAL_3 ; - assign MUX_wsiM_reqFifo_q_1$write_1__VAL_1 = - (wsiM_reqFifo_c_r == 2'd2) ? - MUX_wsiM_reqFifo_q_0$write_1__VAL_2 : + assign MUX_wsiM_reqFifo_q_0$write_1__VAL_2 = + (wsiM_reqFifo_cntr_r == 2'd1) ? + MUX_wsiM_reqFifo_q_0$write_1__VAL_1 : + wsiM_reqFifo_q_1 ; + assign MUX_wsiM_reqFifo_q_1$write_1__VAL_2 = + (wsiM_reqFifo_cntr_r == 2'd2) ? + MUX_wsiM_reqFifo_q_0$write_1__VAL_1 : 169'h00000AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA00 ; assign MUX_wsiM_reqFifo_x_wire$wset_1__VAL_3 = (respF_rCache[181] && respF_rCache[180:169] == respF_rRdPtr) ? @@ -1665,9 +1674,9 @@ module mkSMAdapter16B(wciS0_Clk, assign wmi_reqF_x_wire$whas = WILL_FIRE_RL_wmrd_mesgBodyRequest || MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 ; - assign wmi_mFlagF_x_wire$wget = value__h6702 ; + assign wmi_mFlagF_x_wire$wget = value__h6387 ; assign wmi_mFlagF_x_wire$whas = wmi_mFlagF_enqueueing$whas ; - assign wmi_dhF_x_wire$wget = MUX_wmi_dhF_q_1$write_1__VAL_2 ; + assign wmi_dhF_x_wire$wget = MUX_wmi_dhF_q_0$write_1__VAL_1 ; assign wmi_dhF_x_wire$whas = MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 ; assign wmi_wmiResponse$wget = { wmiM0_SResp, wmiM0_SData } ; assign wmi_wmiResponse$whas = 1'd1 ; @@ -1679,7 +1688,7 @@ module mkSMAdapter16B(wciS0_Clk, assign wmi_operateD_1$whas = wci_wslv_cState == 3'd2 ; assign wmi_peerIsReady_1$wget = 1'd1 ; assign wmi_peerIsReady_1$whas = wmiM0_SReset_n ; - assign wsiM_reqFifo_x_wire$wget = MUX_wsiM_reqFifo_q_0$write_1__VAL_2 ; + assign wsiM_reqFifo_x_wire$wget = MUX_wsiM_reqFifo_q_0$write_1__VAL_1 ; assign wsiM_reqFifo_x_wire$whas = wsiM_reqFifo_enqueueing$whas ; assign wsiM_operateD_1$wget = 1'd1 ; assign wsiM_operateD_1$whas = wci_wslv_cState == 3'd2 ; @@ -1701,7 +1710,7 @@ module mkSMAdapter16B(wciS0_Clk, assign wsiS_sThreadBusy_dw$wget = wsiS_reqFifo_countReg > 2'd1 ; assign wsiS_sThreadBusy_dw$whas = wsiS_reqFifo_levelsValid && wsiS_operateD && wsiS_peerIsReady ; - assign fabRespCredit_acc_v1$wget = b__h15473 ; + assign fabRespCredit_acc_v1$wget = b__h14802 ; assign fabRespCredit_acc_v1$whas = WILL_FIRE_RL_wmrd_mesgBodyRequest ; assign fabRespCredit_acc_v2$wget = 12'd1 ; assign fabRespCredit_acc_v2$whas = WILL_FIRE_RL_wmrd_mesgResptoWsi ; @@ -1711,9 +1720,9 @@ module mkSMAdapter16B(wciS0_Clk, { 3'd1, unrollCnt == 16'd1, !smaCtrl[5], - sendData_burstLength__h19243, + sendData_burstLength__h18617, wmi_respF$D_OUT[127:0], - sendData_byteEn__h19245, + sendData_byteEn__h18619, thisMesg[23:16] } ; assign respF_wDataIn$whas = respF_pwEnqueue$whas ; assign respF_wDataOut$wget = MUX_wsiM_reqFifo_x_wire$wset_1__VAL_3 ; @@ -1740,7 +1749,7 @@ module mkSMAdapter16B(wciS0_Clk, assign wci_wslv_respF_enqueueing$whas = WILL_FIRE_RL_wci_cfrd || WILL_FIRE_RL_wci_cfwr || WILL_FIRE_RL_wci_wslv_ctl_op_complete ; - assign wci_wslv_respF_dequeueing$whas = wci_wslv_respF_c_r != 2'd0 ; + assign wci_wslv_respF_dequeueing$whas = wci_wslv_respF_cntr_r != 2'd0 ; assign wci_wslv_sThreadBusy_pw$whas = 1'b0 ; assign wci_wslv_wci_cfwr_pw$whas = wci_wslv_reqF$EMPTY_N && wci_wslv_reqF$D_OUT[68] && @@ -1755,23 +1764,23 @@ module mkSMAdapter16B(wciS0_Clk, MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 || WILL_FIRE_RL_wmrd_mesgBodyRequest ; assign wmi_reqF_dequeueing$whas = - WILL_FIRE_RL_wmi_reqF_deq && wmi_reqF_c_r != 2'd0 ; + WILL_FIRE_RL_wmi_reqF_deq && wmi_reqF_cntr_r != 2'd0 ; assign wmi_mFlagF_enqueueing$whas = - WILL_FIRE_RL_wmrd_mesgBodyRequest && x__h18954 || + WILL_FIRE_RL_wmrd_mesgBodyRequest && x__h18328 || MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 && wsiS_reqFifo$D_OUT[165] ; assign wmi_mFlagF_dequeueing$whas = WILL_FIRE_RL_wmi_reqF_deq && wmi_reqF_q_0[27] && - wmi_mFlagF_c_r != 2'd0 ; + wmi_mFlagF_cntr_r != 2'd0 ; assign wmi_dhF_enqueueing$whas = MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 ; assign wmi_dhF_dequeueing$whas = wmi_operateD && wmi_peerIsReady && !wmi_sDataThreadBusy_d && - wmi_dhF_c_r != 2'd0 ; + wmi_dhF_cntr_r != 2'd0 ; assign wsiM_reqFifo_enqueueing$whas = - WILL_FIRE_RL_wsipass_doMessagePush && !smaCtrl[4] || MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 && smaCtrl[3:0] == 4'h3 || + WILL_FIRE_RL_wsipass_doMessagePush && !smaCtrl[4] || WILL_FIRE_RL_wmrd_mesgResptoWsi ; assign wsiM_reqFifo_dequeueing$whas = WILL_FIRE_RL_wsiM_reqFifo_deq ; assign wsiM_sThreadBusy_pw$whas = wsiM0_SThreadBusy ; @@ -1785,6 +1794,7 @@ module mkSMAdapter16B(wciS0_Clk, assign wsiS_reqFifo_doResetClr$whas = 1'b0 ; assign respF_pwDequeue$whas = WILL_FIRE_RL_wmrd_mesgResptoWsi ; assign respF_pwEnqueue$whas = MUX_unrollCnt$write_1__SEL_2 && !smaCtrl[4] ; + assign respF_pwClear$whas = 1'b0 ; assign wsi_Es_mReqLast_w$whas = wsiS0_MReqLast ; assign wsi_Es_mBurstPrecise_w$whas = wsiS0_MBurstPrecise ; assign wsi_Es_mDataInfo_w$whas = 1'd1 ; @@ -1825,7 +1835,7 @@ module mkSMAdapter16B(wciS0_Clk, // register fabWordsCurReq assign fabWordsCurReq$D_IN = - (fabWordsRemain <= b__h18783) ? fabWordsRemain : b__h18783 ; + (fabWordsRemain <= b__h18157) ? fabWordsRemain : b__h18157 ; assign fabWordsCurReq$EN = MUX_mesgReqOK$write_1__SEL_3 ; // register fabWordsRemain @@ -1855,14 +1865,14 @@ module mkSMAdapter16B(wciS0_Clk, // register mesgCount always@(MUX_mesgCount$write_1__SEL_1 or - MUX_mesgCount$write_1__VAL_1 or + MUX_mesgCount$write_1__VAL_2 or WILL_FIRE_RL_wmwt_messageFinalize or WILL_FIRE_RL_wci_ctrl_IsO) begin case (1'b1) // synopsys parallel_case MUX_mesgCount$write_1__SEL_1: - mesgCount$D_IN = MUX_mesgCount$write_1__VAL_1; + mesgCount$D_IN = MUX_mesgCount$write_1__VAL_2; WILL_FIRE_RL_wmwt_messageFinalize: - mesgCount$D_IN = MUX_mesgCount$write_1__VAL_1; + mesgCount$D_IN = MUX_mesgCount$write_1__VAL_2; WILL_FIRE_RL_wci_ctrl_IsO: mesgCount$D_IN = 32'd0; default: mesgCount$D_IN = 32'hAAAAAAAA /* unspecified value */ ; endcase @@ -1875,7 +1885,7 @@ module mkSMAdapter16B(wciS0_Clk, // register mesgLengthSoFar assign mesgLengthSoFar$D_IN = MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 ? - MUX_mesgLengthSoFar$write_1__VAL_1 : + mlB__h22903 : 14'd0 ; assign mesgLengthSoFar$EN = MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 || @@ -1910,9 +1920,8 @@ module mkSMAdapter16B(wciS0_Clk, 9'd170 : MUX_opcode$write_1__VAL_3 ; assign opcode$EN = - WILL_FIRE_RL_wmwt_mesgBegin || - WILL_FIRE_RL_wmwt_messageFinalize || - WILL_FIRE_RL_wmwt_doAbort ; + WILL_FIRE_RL_wmwt_messageFinalize || WILL_FIRE_RL_wmwt_doAbort || + WILL_FIRE_RL_wmwt_mesgBegin ; // register readyToPush assign readyToPush$D_IN = @@ -1931,18 +1940,18 @@ module mkSMAdapter16B(wciS0_Clk, assign respF_rCache$D_IN = { 1'd1, respF_rWrPtr, - IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d920, + IF_respF_wDataIn_whas__28_THEN_respF_wDataIn_w_ETC___d431, respF_pwEnqueue$whas && respF_wDataIn$wget[165], respF_pwEnqueue$whas && respF_wDataIn$wget[164], - IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d928 } ; + IF_respF_wDataIn_whas__28_THEN_respF_wDataIn_w_ETC___d437 } ; assign respF_rCache$EN = respF_pwEnqueue$whas ; // register respF_rRdPtr - assign respF_rRdPtr$D_IN = x__h16878 ; + assign respF_rRdPtr$D_IN = x__h16253 ; assign respF_rRdPtr$EN = WILL_FIRE_RL_wmrd_mesgResptoWsi ; // register respF_rWrPtr - assign respF_rWrPtr$D_IN = respF_rWrPtr + 12'd1 ; + assign respF_rWrPtr$D_IN = x__h16103 ; assign respF_rWrPtr$EN = respF_pwEnqueue$whas ; // register smaCtrl @@ -2046,24 +2055,24 @@ module mkSMAdapter16B(wciS0_Clk, (wci_wslv_wciReq$wget[71:69] != 3'd0) != wci_wslv_reqF_r_deq$whas ; - // register wci_wslv_respF_c_r - assign wci_wslv_respF_c_r$D_IN = - WILL_FIRE_RL_wci_wslv_respF_incCtr ? - MUX_wci_wslv_respF_c_r$write_1__VAL_1 : - MUX_wci_wslv_respF_c_r$write_1__VAL_2 ; - assign wci_wslv_respF_c_r$EN = - WILL_FIRE_RL_wci_wslv_respF_incCtr || - WILL_FIRE_RL_wci_wslv_respF_decCtr ; + // register wci_wslv_respF_cntr_r + assign wci_wslv_respF_cntr_r$D_IN = + WILL_FIRE_RL_wci_wslv_respF_decCtr ? + wci_wslv_respF_cntr_r_8_MINUS_1___d27 : + MUX_wci_wslv_respF_cntr_r$write_1__VAL_2 ; + assign wci_wslv_respF_cntr_r$EN = + WILL_FIRE_RL_wci_wslv_respF_decCtr || + WILL_FIRE_RL_wci_wslv_respF_incCtr ; // register wci_wslv_respF_q_0 - always@(WILL_FIRE_RL_wci_wslv_respF_both or + always@(MUX_wci_wslv_respF_q_0$write_1__SEL_1 or MUX_wci_wslv_respF_q_0$write_1__VAL_1 or MUX_wci_wslv_respF_q_0$write_1__SEL_2 or MUX_wci_wslv_respF_q_0$write_1__VAL_2 or WILL_FIRE_RL_wci_wslv_respF_decCtr or wci_wslv_respF_q_1) begin case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_wci_wslv_respF_both: + MUX_wci_wslv_respF_q_0$write_1__SEL_1: wci_wslv_respF_q_0$D_IN = MUX_wci_wslv_respF_q_0$write_1__VAL_1; MUX_wci_wslv_respF_q_0$write_1__SEL_2: wci_wslv_respF_q_0$D_IN = MUX_wci_wslv_respF_q_0$write_1__VAL_2; @@ -2074,20 +2083,20 @@ module mkSMAdapter16B(wciS0_Clk, endcase end assign wci_wslv_respF_q_0$EN = - WILL_FIRE_RL_wci_wslv_respF_both || + WILL_FIRE_RL_wci_wslv_respF_both && _dfoo3 || WILL_FIRE_RL_wci_wslv_respF_incCtr && - wci_wslv_respF_c_r == 2'd0 || + wci_wslv_respF_cntr_r == 2'd0 || WILL_FIRE_RL_wci_wslv_respF_decCtr ; // register wci_wslv_respF_q_1 - always@(WILL_FIRE_RL_wci_wslv_respF_both or + always@(MUX_wci_wslv_respF_q_1$write_1__SEL_1 or MUX_wci_wslv_respF_q_1$write_1__VAL_1 or MUX_wci_wslv_respF_q_1$write_1__SEL_2 or MUX_wci_wslv_respF_q_0$write_1__VAL_2 or WILL_FIRE_RL_wci_wslv_respF_decCtr) begin case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_wci_wslv_respF_both: + MUX_wci_wslv_respF_q_1$write_1__SEL_1: wci_wslv_respF_q_1$D_IN = MUX_wci_wslv_respF_q_1$write_1__VAL_1; MUX_wci_wslv_respF_q_1$write_1__SEL_2: wci_wslv_respF_q_1$D_IN = MUX_wci_wslv_respF_q_0$write_1__VAL_2; @@ -2098,9 +2107,9 @@ module mkSMAdapter16B(wciS0_Clk, endcase end assign wci_wslv_respF_q_1$EN = - WILL_FIRE_RL_wci_wslv_respF_both || + WILL_FIRE_RL_wci_wslv_respF_both && _dfoo1 || WILL_FIRE_RL_wci_wslv_respF_incCtr && - wci_wslv_respF_c_r == 2'd1 || + wci_wslv_respF_cntr_r == 2'd1 || WILL_FIRE_RL_wci_wslv_respF_decCtr ; // register wci_wslv_sFlagReg @@ -2115,45 +2124,45 @@ module mkSMAdapter16B(wciS0_Clk, assign wmi_busyWithMessage$D_IN = 1'b0 ; assign wmi_busyWithMessage$EN = 1'b0 ; - // register wmi_dhF_c_r - assign wmi_dhF_c_r$D_IN = - WILL_FIRE_RL_wmi_dhF_incCtr ? - MUX_wmi_dhF_c_r$write_1__VAL_1 : - MUX_wmi_dhF_c_r$write_1__VAL_2 ; - assign wmi_dhF_c_r$EN = - WILL_FIRE_RL_wmi_dhF_incCtr || WILL_FIRE_RL_wmi_dhF_decCtr ; + // register wmi_dhF_cntr_r + assign wmi_dhF_cntr_r$D_IN = + WILL_FIRE_RL_wmi_dhF_decCtr ? + wmi_dhF_cntr_r_05_MINUS_1___d213 : + MUX_wmi_dhF_cntr_r$write_1__VAL_2 ; + assign wmi_dhF_cntr_r$EN = + WILL_FIRE_RL_wmi_dhF_decCtr || WILL_FIRE_RL_wmi_dhF_incCtr ; // register wmi_dhF_q_0 - always@(WILL_FIRE_RL_wmi_dhF_both or + always@(MUX_wmi_dhF_q_0$write_1__SEL_1 or MUX_wmi_dhF_q_0$write_1__VAL_1 or MUX_wmi_dhF_q_0$write_1__SEL_2 or - MUX_wmi_dhF_q_1$write_1__VAL_2 or + MUX_wmi_dhF_q_0$write_1__VAL_2 or WILL_FIRE_RL_wmi_dhF_decCtr or wmi_dhF_q_1) begin case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_wmi_dhF_both: + MUX_wmi_dhF_q_0$write_1__SEL_1: wmi_dhF_q_0$D_IN = MUX_wmi_dhF_q_0$write_1__VAL_1; MUX_wmi_dhF_q_0$write_1__SEL_2: - wmi_dhF_q_0$D_IN = MUX_wmi_dhF_q_1$write_1__VAL_2; + wmi_dhF_q_0$D_IN = MUX_wmi_dhF_q_0$write_1__VAL_2; WILL_FIRE_RL_wmi_dhF_decCtr: wmi_dhF_q_0$D_IN = wmi_dhF_q_1; default: wmi_dhF_q_0$D_IN = 146'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ; endcase end assign wmi_dhF_q_0$EN = - WILL_FIRE_RL_wmi_dhF_both || - WILL_FIRE_RL_wmi_dhF_incCtr && wmi_dhF_c_r == 2'd0 || + WILL_FIRE_RL_wmi_dhF_incCtr && wmi_dhF_cntr_r == 2'd0 || + WILL_FIRE_RL_wmi_dhF_both && _dfoo15 || WILL_FIRE_RL_wmi_dhF_decCtr ; // register wmi_dhF_q_1 - always@(WILL_FIRE_RL_wmi_dhF_both or - MUX_wmi_dhF_q_1$write_1__VAL_1 or + always@(MUX_wmi_dhF_q_1$write_1__SEL_1 or + MUX_wmi_dhF_q_0$write_1__VAL_1 or MUX_wmi_dhF_q_1$write_1__SEL_2 or MUX_wmi_dhF_q_1$write_1__VAL_2 or WILL_FIRE_RL_wmi_dhF_decCtr) begin case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_wmi_dhF_both: - wmi_dhF_q_1$D_IN = MUX_wmi_dhF_q_1$write_1__VAL_1; + MUX_wmi_dhF_q_1$write_1__SEL_1: + wmi_dhF_q_1$D_IN = MUX_wmi_dhF_q_0$write_1__VAL_1; MUX_wmi_dhF_q_1$write_1__SEL_2: wmi_dhF_q_1$D_IN = MUX_wmi_dhF_q_1$write_1__VAL_2; WILL_FIRE_RL_wmi_dhF_decCtr: wmi_dhF_q_1$D_IN = 146'd0; @@ -2162,8 +2171,8 @@ module mkSMAdapter16B(wciS0_Clk, endcase end assign wmi_dhF_q_1$EN = - WILL_FIRE_RL_wmi_dhF_both || - WILL_FIRE_RL_wmi_dhF_incCtr && wmi_dhF_c_r == 2'd1 || + WILL_FIRE_RL_wmi_dhF_incCtr && wmi_dhF_cntr_r == 2'd1 || + WILL_FIRE_RL_wmi_dhF_both && _dfoo13 || WILL_FIRE_RL_wmi_dhF_decCtr ; // register wmi_errorSticky @@ -2174,51 +2183,51 @@ module mkSMAdapter16B(wciS0_Clk, assign wmi_isReset_isInReset$D_IN = 1'd0 ; assign wmi_isReset_isInReset$EN = wmi_isReset_isInReset ; - // register wmi_mFlagF_c_r - assign wmi_mFlagF_c_r$D_IN = - WILL_FIRE_RL_wmi_mFlagF_incCtr ? - MUX_wmi_mFlagF_c_r$write_1__VAL_1 : - MUX_wmi_mFlagF_c_r$write_1__VAL_2 ; - assign wmi_mFlagF_c_r$EN = - WILL_FIRE_RL_wmi_mFlagF_incCtr || - WILL_FIRE_RL_wmi_mFlagF_decCtr ; + // register wmi_mFlagF_cntr_r + assign wmi_mFlagF_cntr_r$D_IN = + WILL_FIRE_RL_wmi_mFlagF_decCtr ? + wmi_mFlagF_cntr_r_83_MINUS_1___d191 : + MUX_wmi_mFlagF_cntr_r$write_1__VAL_2 ; + assign wmi_mFlagF_cntr_r$EN = + WILL_FIRE_RL_wmi_mFlagF_decCtr || + WILL_FIRE_RL_wmi_mFlagF_incCtr ; // register wmi_mFlagF_q_0 - always@(WILL_FIRE_RL_wmi_mFlagF_both or + always@(MUX_wmi_mFlagF_q_0$write_1__SEL_1 or MUX_wmi_mFlagF_q_0$write_1__VAL_1 or MUX_wmi_mFlagF_q_0$write_1__SEL_2 or - value__h6702 or WILL_FIRE_RL_wmi_mFlagF_decCtr or wmi_mFlagF_q_1) + value__h6387 or WILL_FIRE_RL_wmi_mFlagF_decCtr or wmi_mFlagF_q_1) begin case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_wmi_mFlagF_both: + MUX_wmi_mFlagF_q_0$write_1__SEL_1: wmi_mFlagF_q_0$D_IN = MUX_wmi_mFlagF_q_0$write_1__VAL_1; - MUX_wmi_mFlagF_q_0$write_1__SEL_2: wmi_mFlagF_q_0$D_IN = value__h6702; + MUX_wmi_mFlagF_q_0$write_1__SEL_2: wmi_mFlagF_q_0$D_IN = value__h6387; WILL_FIRE_RL_wmi_mFlagF_decCtr: wmi_mFlagF_q_0$D_IN = wmi_mFlagF_q_1; default: wmi_mFlagF_q_0$D_IN = 32'hAAAAAAAA /* unspecified value */ ; endcase end assign wmi_mFlagF_q_0$EN = - WILL_FIRE_RL_wmi_mFlagF_both || - WILL_FIRE_RL_wmi_mFlagF_incCtr && wmi_mFlagF_c_r == 2'd0 || + WILL_FIRE_RL_wmi_mFlagF_both && _dfoo11 || + WILL_FIRE_RL_wmi_mFlagF_incCtr && wmi_mFlagF_cntr_r == 2'd0 || WILL_FIRE_RL_wmi_mFlagF_decCtr ; // register wmi_mFlagF_q_1 - always@(WILL_FIRE_RL_wmi_mFlagF_both or + always@(MUX_wmi_mFlagF_q_1$write_1__SEL_1 or MUX_wmi_mFlagF_q_1$write_1__VAL_1 or MUX_wmi_mFlagF_q_1$write_1__SEL_2 or - value__h6702 or WILL_FIRE_RL_wmi_mFlagF_decCtr) + value__h6387 or WILL_FIRE_RL_wmi_mFlagF_decCtr) begin case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_wmi_mFlagF_both: + MUX_wmi_mFlagF_q_1$write_1__SEL_1: wmi_mFlagF_q_1$D_IN = MUX_wmi_mFlagF_q_1$write_1__VAL_1; - MUX_wmi_mFlagF_q_1$write_1__SEL_2: wmi_mFlagF_q_1$D_IN = value__h6702; + MUX_wmi_mFlagF_q_1$write_1__SEL_2: wmi_mFlagF_q_1$D_IN = value__h6387; WILL_FIRE_RL_wmi_mFlagF_decCtr: wmi_mFlagF_q_1$D_IN = 32'd0; default: wmi_mFlagF_q_1$D_IN = 32'hAAAAAAAA /* unspecified value */ ; endcase end assign wmi_mFlagF_q_1$EN = - WILL_FIRE_RL_wmi_mFlagF_both || - WILL_FIRE_RL_wmi_mFlagF_incCtr && wmi_mFlagF_c_r == 2'd1 || + WILL_FIRE_RL_wmi_mFlagF_both && _dfoo9 || + WILL_FIRE_RL_wmi_mFlagF_incCtr && wmi_mFlagF_cntr_r == 2'd1 || WILL_FIRE_RL_wmi_mFlagF_decCtr ; // register wmi_operateD @@ -2229,23 +2238,23 @@ module mkSMAdapter16B(wciS0_Clk, assign wmi_peerIsReady$D_IN = wmiM0_SReset_n ; assign wmi_peerIsReady$EN = 1'd1 ; - // register wmi_reqF_c_r - assign wmi_reqF_c_r$D_IN = - WILL_FIRE_RL_wmi_reqF_incCtr ? - MUX_wmi_reqF_c_r$write_1__VAL_1 : - MUX_wmi_reqF_c_r$write_1__VAL_2 ; - assign wmi_reqF_c_r$EN = - WILL_FIRE_RL_wmi_reqF_incCtr || WILL_FIRE_RL_wmi_reqF_decCtr ; + // register wmi_reqF_cntr_r + assign wmi_reqF_cntr_r$D_IN = + WILL_FIRE_RL_wmi_reqF_decCtr ? + wmi_reqF_cntr_r_61_MINUS_1___d169 : + MUX_wmi_reqF_cntr_r$write_1__VAL_2 ; + assign wmi_reqF_cntr_r$EN = + WILL_FIRE_RL_wmi_reqF_decCtr || WILL_FIRE_RL_wmi_reqF_incCtr ; // register wmi_reqF_q_0 - always@(WILL_FIRE_RL_wmi_reqF_both or + always@(MUX_wmi_reqF_q_0$write_1__SEL_1 or MUX_wmi_reqF_q_0$write_1__VAL_1 or MUX_wmi_reqF_q_0$write_1__SEL_2 or MUX_wmi_reqF_q_0$write_1__VAL_2 or WILL_FIRE_RL_wmi_reqF_decCtr or wmi_reqF_q_1) begin case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_wmi_reqF_both: + MUX_wmi_reqF_q_0$write_1__SEL_1: wmi_reqF_q_0$D_IN = MUX_wmi_reqF_q_0$write_1__VAL_1; MUX_wmi_reqF_q_0$write_1__SEL_2: wmi_reqF_q_0$D_IN = MUX_wmi_reqF_q_0$write_1__VAL_2; @@ -2254,18 +2263,18 @@ module mkSMAdapter16B(wciS0_Clk, endcase end assign wmi_reqF_q_0$EN = - WILL_FIRE_RL_wmi_reqF_both || - WILL_FIRE_RL_wmi_reqF_incCtr && wmi_reqF_c_r == 2'd0 || + WILL_FIRE_RL_wmi_reqF_both && _dfoo7 || + WILL_FIRE_RL_wmi_reqF_incCtr && wmi_reqF_cntr_r == 2'd0 || WILL_FIRE_RL_wmi_reqF_decCtr ; // register wmi_reqF_q_1 - always@(WILL_FIRE_RL_wmi_reqF_both or + always@(MUX_wmi_reqF_q_1$write_1__SEL_1 or MUX_wmi_reqF_q_1$write_1__VAL_1 or MUX_wmi_reqF_q_1$write_1__SEL_2 or MUX_wmi_reqF_q_0$write_1__VAL_2 or WILL_FIRE_RL_wmi_reqF_decCtr) begin case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_wmi_reqF_both: + MUX_wmi_reqF_q_1$write_1__SEL_1: wmi_reqF_q_1$D_IN = MUX_wmi_reqF_q_1$write_1__VAL_1; MUX_wmi_reqF_q_1$write_1__SEL_2: wmi_reqF_q_1$D_IN = MUX_wmi_reqF_q_0$write_1__VAL_2; @@ -2274,8 +2283,8 @@ module mkSMAdapter16B(wciS0_Clk, endcase end assign wmi_reqF_q_1$EN = - WILL_FIRE_RL_wmi_reqF_both || - WILL_FIRE_RL_wmi_reqF_incCtr && wmi_reqF_c_r == 2'd1 || + WILL_FIRE_RL_wmi_reqF_both && _dfoo5 || + WILL_FIRE_RL_wmi_reqF_incCtr && wmi_reqF_cntr_r == 2'd1 || WILL_FIRE_RL_wmi_reqF_decCtr ; // register wmi_sDataThreadBusy_d @@ -2354,24 +2363,24 @@ module mkSMAdapter16B(wciS0_Clk, assign wsiM_peerIsReady$D_IN = wsiM0_SReset_n ; assign wsiM_peerIsReady$EN = 1'd1 ; - // register wsiM_reqFifo_c_r - assign wsiM_reqFifo_c_r$D_IN = - WILL_FIRE_RL_wsiM_reqFifo_incCtr ? - MUX_wsiM_reqFifo_c_r$write_1__VAL_1 : - MUX_wsiM_reqFifo_c_r$write_1__VAL_2 ; - assign wsiM_reqFifo_c_r$EN = - WILL_FIRE_RL_wsiM_reqFifo_incCtr || - WILL_FIRE_RL_wsiM_reqFifo_decCtr ; + // register wsiM_reqFifo_cntr_r + assign wsiM_reqFifo_cntr_r$D_IN = + WILL_FIRE_RL_wsiM_reqFifo_decCtr ? + MUX_wsiM_reqFifo_cntr_r$write_1__VAL_1 : + MUX_wsiM_reqFifo_cntr_r$write_1__VAL_2 ; + assign wsiM_reqFifo_cntr_r$EN = + WILL_FIRE_RL_wsiM_reqFifo_decCtr || + WILL_FIRE_RL_wsiM_reqFifo_incCtr ; // register wsiM_reqFifo_q_0 - always@(WILL_FIRE_RL_wsiM_reqFifo_both or + always@(MUX_wsiM_reqFifo_q_0$write_1__SEL_1 or MUX_wsiM_reqFifo_q_0$write_1__VAL_1 or MUX_wsiM_reqFifo_q_0$write_1__SEL_2 or MUX_wsiM_reqFifo_q_0$write_1__VAL_2 or WILL_FIRE_RL_wsiM_reqFifo_decCtr or wsiM_reqFifo_q_1) begin case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_wsiM_reqFifo_both: + MUX_wsiM_reqFifo_q_0$write_1__SEL_1: wsiM_reqFifo_q_0$D_IN = MUX_wsiM_reqFifo_q_0$write_1__VAL_1; MUX_wsiM_reqFifo_q_0$write_1__SEL_2: wsiM_reqFifo_q_0$D_IN = MUX_wsiM_reqFifo_q_0$write_1__VAL_2; @@ -2382,22 +2391,23 @@ module mkSMAdapter16B(wciS0_Clk, endcase end assign wsiM_reqFifo_q_0$EN = - WILL_FIRE_RL_wsiM_reqFifo_both || - WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_c_r == 2'd0 || + WILL_FIRE_RL_wsiM_reqFifo_incCtr && + wsiM_reqFifo_cntr_r == 2'd0 || + WILL_FIRE_RL_wsiM_reqFifo_both && _dfoo19 || WILL_FIRE_RL_wsiM_reqFifo_decCtr ; // register wsiM_reqFifo_q_1 - always@(WILL_FIRE_RL_wsiM_reqFifo_both or - MUX_wsiM_reqFifo_q_1$write_1__VAL_1 or + always@(MUX_wsiM_reqFifo_q_1$write_1__SEL_1 or + MUX_wsiM_reqFifo_q_0$write_1__VAL_1 or MUX_wsiM_reqFifo_q_1$write_1__SEL_2 or - MUX_wsiM_reqFifo_q_0$write_1__VAL_2 or + MUX_wsiM_reqFifo_q_1$write_1__VAL_2 or WILL_FIRE_RL_wsiM_reqFifo_decCtr) begin case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_wsiM_reqFifo_both: - wsiM_reqFifo_q_1$D_IN = MUX_wsiM_reqFifo_q_1$write_1__VAL_1; + MUX_wsiM_reqFifo_q_1$write_1__SEL_1: + wsiM_reqFifo_q_1$D_IN = MUX_wsiM_reqFifo_q_0$write_1__VAL_1; MUX_wsiM_reqFifo_q_1$write_1__SEL_2: - wsiM_reqFifo_q_1$D_IN = MUX_wsiM_reqFifo_q_0$write_1__VAL_2; + wsiM_reqFifo_q_1$D_IN = MUX_wsiM_reqFifo_q_1$write_1__VAL_2; WILL_FIRE_RL_wsiM_reqFifo_decCtr: wsiM_reqFifo_q_1$D_IN = 169'h00000AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA00; @@ -2406,8 +2416,9 @@ module mkSMAdapter16B(wciS0_Clk, endcase end assign wsiM_reqFifo_q_1$EN = - WILL_FIRE_RL_wsiM_reqFifo_both || - WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_c_r == 2'd1 || + WILL_FIRE_RL_wsiM_reqFifo_incCtr && + wsiM_reqFifo_cntr_r == 2'd1 || + WILL_FIRE_RL_wsiM_reqFifo_both && _dfoo17 || WILL_FIRE_RL_wsiM_reqFifo_decCtr ; // register wsiM_sThreadBusy_d @@ -2533,19 +2544,19 @@ module mkSMAdapter16B(wciS0_Clk, assign respF_memory$ADDRA = respF_rWrPtr[10:0] ; assign respF_memory$ADDRB = WILL_FIRE_RL_wmrd_mesgResptoWsi ? - x__h16878[10:0] : + x__h16253[10:0] : respF_rRdPtr[10:0] ; assign respF_memory$DIA = - { IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d920, + { IF_respF_wDataIn_whas__28_THEN_respF_wDataIn_w_ETC___d431, respF_pwEnqueue$whas && respF_wDataIn$wget[165], respF_pwEnqueue$whas && respF_wDataIn$wget[164], - IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d928 } ; + IF_respF_wDataIn_whas__28_THEN_respF_wDataIn_w_ETC___d437 } ; assign respF_memory$DIB = 169'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ; assign respF_memory$WEA = respF_pwEnqueue$whas ; assign respF_memory$WEB = 1'd0 ; - assign respF_memory$ENA = 1'd1 ; - assign respF_memory$ENB = 1'd1 ; + assign respF_memory$ENA = 1'b1 ; + assign respF_memory$ENB = 1'b1 ; // submodule wci_wslv_reqF assign wci_wslv_reqF$D_IN = wci_wslv_wciReq$wget ; @@ -2568,70 +2579,106 @@ module mkSMAdapter16B(wciS0_Clk, assign wsiS_reqFifo$CLR = 1'b0 ; // remaining internal signals - assign IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d920 = + assign IF_respF_wDataIn_whas__28_THEN_respF_wDataIn_w_ETC___d431 = respF_pwEnqueue$whas ? respF_wDataIn$wget[168:166] : 3'd0 ; - assign IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d928 = + assign IF_respF_wDataIn_whas__28_THEN_respF_wDataIn_w_ETC___d437 = respF_pwEnqueue$whas ? respF_wDataIn$wget[163:0] : 164'd0 ; - assign NOT_wmi_reqF_c_r_57_EQ_2_75_76_AND_wmi_operate_ETC___d524 = - wmi_reqF_c_r != 2'd2 && wmi_operateD && wmi_peerIsReady && - (!x__h18954 || wmi_mFlagF_c_r != 2'd2) ; - assign b__h15473 = -fabWordsCurReq[11:0] ; - assign b__h18410 = x__h18530 + residue__h18273 ; - assign b__h18783 = { {2{fabRespCredit_value[11]}}, fabRespCredit_value } ; - assign mesgMetaF_length__h22999 = + assign NOT_wmi_reqF_cntr_r_61_EQ_2_73_74_AND_wmi_oper_ETC___d521 = + wmi_reqF_cntr_r != 2'd2 && wmi_operateD && wmi_peerIsReady && + (!x__h18328 || wmi_mFlagF_cntr_r != 2'd2) ; + assign _dfoo1 = + wci_wslv_respF_cntr_r != 2'd2 || + wci_wslv_respF_cntr_r_8_MINUS_1___d27 == 2'd1 ; + assign _dfoo11 = + wmi_mFlagF_cntr_r != 2'd1 || + wmi_mFlagF_cntr_r_83_MINUS_1___d191 == 2'd0 ; + assign _dfoo13 = + wmi_dhF_cntr_r != 2'd2 || + wmi_dhF_cntr_r_05_MINUS_1___d213 == 2'd1 ; + assign _dfoo15 = + wmi_dhF_cntr_r != 2'd1 || + wmi_dhF_cntr_r_05_MINUS_1___d213 == 2'd0 ; + assign _dfoo17 = + wsiM_reqFifo_cntr_r != 2'd2 || + MUX_wsiM_reqFifo_cntr_r$write_1__VAL_1 == 2'd1 ; + assign _dfoo19 = + wsiM_reqFifo_cntr_r != 2'd1 || + MUX_wsiM_reqFifo_cntr_r$write_1__VAL_1 == 2'd0 ; + assign _dfoo3 = + wci_wslv_respF_cntr_r != 2'd1 || + wci_wslv_respF_cntr_r_8_MINUS_1___d27 == 2'd0 ; + assign _dfoo5 = + wmi_reqF_cntr_r != 2'd2 || + wmi_reqF_cntr_r_61_MINUS_1___d169 == 2'd1 ; + assign _dfoo7 = + wmi_reqF_cntr_r != 2'd1 || + wmi_reqF_cntr_r_61_MINUS_1___d169 == 2'd0 ; + assign _dfoo9 = + wmi_mFlagF_cntr_r != 2'd2 || + wmi_mFlagF_cntr_r_83_MINUS_1___d191 == 2'd1 ; + assign b__h14802 = -fabWordsCurReq[11:0] ; + assign b__h17784 = x__h17904 + residue__h17647 ; + assign b__h18157 = { {2{fabRespCredit_value[11]}}, fabRespCredit_value } ; + assign mesgMetaF_length__h23070 = (wsiS_reqFifo$D_OUT[165] && wsiS_reqFifo$D_OUT[23:8] == 16'd0 && mesgLengthSoFar == 14'd0) ? 24'd0 : - { 10'd0, mlB__h22832 } ; - assign mesgMetaF_opcode__h22998 = opcode[8] ? opcode[7:0] : 8'd0 ; - assign mlB__h22832 = MUX_mesgLengthSoFar$write_1__VAL_1 ; - assign mlInc__h22831 = + { 10'd0, mlB__h22903 } ; + assign mesgMetaF_opcode__h23069 = opcode[8] ? opcode[7:0] : 8'd0 ; + assign mlB__h22903 = mesgLengthSoFar + mlInc__h22902 ; + assign mlInc__h22902 = wsiS_reqFifo$D_OUT[165] ? - { 9'd0, x__h23038 + y__h23039 } : + { 9'd0, x__h23108 + y__h23109 } : 14'd16 ; - assign rdat__h24911 = hasDebugLogic ? mesgCount : 32'd0 ; - assign rdat__h24917 = hasDebugLogic ? abortCount : 32'd0 ; - assign rdat__h24923 = hasDebugLogic ? thisMesg : 32'd0 ; - assign rdat__h24936 = hasDebugLogic ? lastMesg : 32'd0 ; - assign rdat__h24959 = hasDebugLogic ? { 16'd0, x__h24963 } : 32'd0 ; - assign rdat__h25059 = hasDebugLogic ? wsiS_extStatusW$wget[95:64] : 32'd0 ; - assign rdat__h25073 = hasDebugLogic ? wsiS_extStatusW$wget[63:32] : 32'd0 ; - assign rdat__h25081 = hasDebugLogic ? wsiS_extStatusW$wget[31:0] : 32'd0 ; - assign rdat__h25087 = hasDebugLogic ? wsiM_extStatusW$wget[95:64] : 32'd0 ; - assign rdat__h25101 = hasDebugLogic ? wsiM_extStatusW$wget[63:32] : 32'd0 ; - assign rdat__h25109 = hasDebugLogic ? wsiM_extStatusW$wget[31:0] : 32'd0 ; - assign rdat__h25115 = hasDebugLogic ? wmwtBeginCount : 32'd0 ; - assign rdat__h25121 = hasDebugLogic ? wmwtPushCount : 32'd0 ; - assign rdat__h25127 = hasDebugLogic ? wmwtFinalCount : 32'd0 ; - assign rdat__h25133 = hasDebugLogic ? { 31'd0, x__h25137 } : 32'd0 ; - assign rdat__h25143 = hasDebugLogic ? 32'hFEEDC0DE : 32'd0 ; - assign residue__h18273 = + assign rdat__h24980 = hasDebugLogic ? mesgCount : 32'd0 ; + assign rdat__h24986 = hasDebugLogic ? abortCount : 32'd0 ; + assign rdat__h24992 = hasDebugLogic ? thisMesg : 32'd0 ; + assign rdat__h25005 = hasDebugLogic ? lastMesg : 32'd0 ; + assign rdat__h25028 = hasDebugLogic ? { 16'd0, x__h25032 } : 32'd0 ; + assign rdat__h25128 = hasDebugLogic ? wsiS_extStatusW$wget[95:64] : 32'd0 ; + assign rdat__h25142 = hasDebugLogic ? wsiS_extStatusW$wget[63:32] : 32'd0 ; + assign rdat__h25150 = hasDebugLogic ? wsiS_extStatusW$wget[31:0] : 32'd0 ; + assign rdat__h25156 = hasDebugLogic ? wsiM_extStatusW$wget[95:64] : 32'd0 ; + assign rdat__h25170 = hasDebugLogic ? wsiM_extStatusW$wget[63:32] : 32'd0 ; + assign rdat__h25178 = hasDebugLogic ? wsiM_extStatusW$wget[31:0] : 32'd0 ; + assign rdat__h25184 = hasDebugLogic ? wmwtBeginCount : 32'd0 ; + assign rdat__h25190 = hasDebugLogic ? wmwtPushCount : 32'd0 ; + assign rdat__h25196 = hasDebugLogic ? wmwtFinalCount : 32'd0 ; + assign rdat__h25202 = hasDebugLogic ? { 31'd0, x__h25206 } : 32'd0 ; + assign rdat__h25212 = hasDebugLogic ? 32'hFEEDC0DE : 32'd0 ; + assign residue__h17647 = ({ 2'd0, wmi_sFlagReg[3:0] } == 6'd0) ? 24'd0 : 24'd1 ; - assign sendData_burstLength__h19243 = + assign sendData_burstLength__h18617 = (thisMesg[15:0] == 16'd0 || smaCtrl[5] && unrollCnt == 16'd1) ? 12'd1 : - (smaCtrl[5] ? 12'd4095 : wsiBurstLength__h19161[11:0]) ; - assign sendData_byteEn__h19245 = + (smaCtrl[5] ? 12'd4095 : wsiBurstLength__h18535[11:0]) ; + assign sendData_byteEn__h18619 = (thisMesg[15:0] == 16'd0) ? thisMesg[15:0] : - ((unrollCnt == 16'd1) ? x__h19302[15:0] : 16'd65535) ; - assign value__h6702 = + ((unrollCnt == 16'd1) ? x__h18676[15:0] : 16'd65535) ; + assign value__h6387 = MUX_wmi_mFlagF_x_wire$wset_1__SEL_1 ? 32'hAAAAAAAA /* unspecified value */ : MUX_wmi_mFlagF_x_wire$wset_1__VAL_2 ; - assign wmi_respF_i_notEmpty__37_AND_smaCtrl_65_BIT_4__ETC___d542 = + assign wci_wslv_respF_cntr_r_8_MINUS_1___d27 = + wci_wslv_respF_cntr_r - 2'd1 ; + assign wmi_dhF_cntr_r_05_MINUS_1___d213 = wmi_dhF_cntr_r - 2'd1 ; + assign wmi_mFlagF_cntr_r_83_MINUS_1___d191 = wmi_mFlagF_cntr_r - 2'd1 ; + assign wmi_reqF_cntr_r_61_MINUS_1___d169 = wmi_reqF_cntr_r - 2'd1 ; + assign wmi_respF_i_notEmpty__34_AND_smaCtrl_62_BIT_4__ETC___d539 = wmi_respF$EMPTY_N && (smaCtrl[4] || respF_rRdPtr + 12'd1024 != respF_rWrPtr) ; - assign wsiBurstLength__h19161 = + assign wsiBurstLength__h18535 = smaCtrl[5] ? 16'd2 : { 4'd0, thisMesg[15:4] } ; - assign wsiS_reqFifo_i_notEmpty__64_AND_NOT_smaCtrl_65_ETC___d670 = + assign wsiS_reqFifo_i_notEmpty__61_AND_NOT_smaCtrl_62_ETC___d667 = wsiS_reqFifo$EMPTY_N && - (smaCtrl[3:0] != 4'h3 || wsiM_reqFifo_c_r != 2'd2) && - (!wsiS_reqFifo$D_OUT[165] || wmi_mFlagF_c_r != 2'd2) ; - assign x__h16878 = respF_rRdPtr + 12'd1 ; - assign x__h18530 = { 4'd0, wmi_sFlagReg[23:4] } ; - assign x__h18954 = fabWordsRemain == fabWordsCurReq ; - assign x__h19302 = + (smaCtrl[3:0] != 4'h3 || wsiM_reqFifo_cntr_r != 2'd2) && + (!wsiS_reqFifo$D_OUT[165] || wmi_mFlagF_cntr_r != 2'd2) ; + assign x__h16103 = respF_rWrPtr + 12'd1 ; + assign x__h16253 = respF_rRdPtr + 12'd1 ; + assign x__h17904 = { 4'd0, wmi_sFlagReg[23:4] } ; + assign x__h18328 = fabWordsRemain == fabWordsCurReq ; + assign x__h18676 = ({ 2'd0, thisMesg[3:0] } == 6'd0) ? 32'hFFFFFFFF : (({ 2'd0, thisMesg[3:0] } <= 6'd1) ? @@ -2738,74 +2785,74 @@ module mkSMAdapter16B(wciS0_Clk, 6'd31) ? 32'h7FFFFFFF : 32'hFFFFFFFF))))))))))))))))))))))))))))))) ; - assign x__h23038 = x__h23050 + y__h23051 ; - assign x__h23050 = x__h23062 + y__h23063 ; - assign x__h23062 = x__h23074 + y__h23075 ; - assign x__h23074 = x__h23086 + y__h23087 ; - assign x__h23086 = x__h23098 + y__h23099 ; - assign x__h23098 = x__h23110 + y__h23111 ; - assign x__h23110 = x__h23122 + y__h23123 ; - assign x__h23122 = x__h23134 + y__h23135 ; - assign x__h23134 = x__h23146 + y__h23147 ; - assign x__h23146 = x__h23158 + y__h23159 ; - assign x__h23158 = x__h23170 + y__h23171 ; - assign x__h23170 = x__h23182 + y__h23183 ; - assign x__h23182 = x__h23194 + y__h23195 ; - assign x__h23194 = x__h23206 + y__h23207 ; - assign x__h23206 = { 4'd0, wsiS_reqFifo$D_OUT[23] } ; - assign x__h24963 = { wsiS_statusR, wsiM_statusR } ; - assign x__h25137 = wmi_sThreadBusy_d || wmi_sDataThreadBusy_d ; - assign x_length__h23891 = { 2'd0, mlB__h22832 } ; - assign y__h23039 = { 4'd0, wsiS_reqFifo$D_OUT[8] } ; - assign y__h23051 = { 4'd0, wsiS_reqFifo$D_OUT[9] } ; - assign y__h23063 = { 4'd0, wsiS_reqFifo$D_OUT[10] } ; - assign y__h23075 = { 4'd0, wsiS_reqFifo$D_OUT[11] } ; - assign y__h23087 = { 4'd0, wsiS_reqFifo$D_OUT[12] } ; - assign y__h23099 = { 4'd0, wsiS_reqFifo$D_OUT[13] } ; - assign y__h23111 = { 4'd0, wsiS_reqFifo$D_OUT[14] } ; - assign y__h23123 = { 4'd0, wsiS_reqFifo$D_OUT[15] } ; - assign y__h23135 = { 4'd0, wsiS_reqFifo$D_OUT[16] } ; - assign y__h23147 = { 4'd0, wsiS_reqFifo$D_OUT[17] } ; - assign y__h23159 = { 4'd0, wsiS_reqFifo$D_OUT[18] } ; - assign y__h23171 = { 4'd0, wsiS_reqFifo$D_OUT[19] } ; - assign y__h23183 = { 4'd0, wsiS_reqFifo$D_OUT[20] } ; - assign y__h23195 = { 4'd0, wsiS_reqFifo$D_OUT[21] } ; - assign y__h23207 = { 4'd0, wsiS_reqFifo$D_OUT[22] } ; + assign x__h23108 = x__h23120 + y__h23121 ; + assign x__h23120 = x__h23132 + y__h23133 ; + assign x__h23132 = x__h23144 + y__h23145 ; + assign x__h23144 = x__h23156 + y__h23157 ; + assign x__h23156 = x__h23168 + y__h23169 ; + assign x__h23168 = x__h23180 + y__h23181 ; + assign x__h23180 = x__h23192 + y__h23193 ; + assign x__h23192 = x__h23204 + y__h23205 ; + assign x__h23204 = x__h23216 + y__h23217 ; + assign x__h23216 = x__h23228 + y__h23229 ; + assign x__h23228 = x__h23240 + y__h23241 ; + assign x__h23240 = x__h23252 + y__h23253 ; + assign x__h23252 = x__h23264 + y__h23265 ; + assign x__h23264 = x__h23276 + y__h23277 ; + assign x__h23276 = { 4'd0, wsiS_reqFifo$D_OUT[23] } ; + assign x__h25032 = { wsiS_statusR, wsiM_statusR } ; + assign x__h25206 = wmi_sThreadBusy_d || wmi_sDataThreadBusy_d ; + assign x_length__h23961 = { 2'd0, mlB__h22903 } ; + assign y__h23109 = { 4'd0, wsiS_reqFifo$D_OUT[8] } ; + assign y__h23121 = { 4'd0, wsiS_reqFifo$D_OUT[9] } ; + assign y__h23133 = { 4'd0, wsiS_reqFifo$D_OUT[10] } ; + assign y__h23145 = { 4'd0, wsiS_reqFifo$D_OUT[11] } ; + assign y__h23157 = { 4'd0, wsiS_reqFifo$D_OUT[12] } ; + assign y__h23169 = { 4'd0, wsiS_reqFifo$D_OUT[13] } ; + assign y__h23181 = { 4'd0, wsiS_reqFifo$D_OUT[14] } ; + assign y__h23193 = { 4'd0, wsiS_reqFifo$D_OUT[15] } ; + assign y__h23205 = { 4'd0, wsiS_reqFifo$D_OUT[16] } ; + assign y__h23217 = { 4'd0, wsiS_reqFifo$D_OUT[17] } ; + assign y__h23229 = { 4'd0, wsiS_reqFifo$D_OUT[18] } ; + assign y__h23241 = { 4'd0, wsiS_reqFifo$D_OUT[19] } ; + assign y__h23253 = { 4'd0, wsiS_reqFifo$D_OUT[20] } ; + assign y__h23265 = { 4'd0, wsiS_reqFifo$D_OUT[21] } ; + assign y__h23277 = { 4'd0, wsiS_reqFifo$D_OUT[22] } ; always@(wci_wslv_reqF$D_OUT or smaCtrl or - rdat__h24911 or - rdat__h24917 or - rdat__h24923 or - rdat__h24936 or - rdat__h24959 or - rdat__h25059 or - rdat__h25073 or - rdat__h25081 or - rdat__h25087 or - rdat__h25101 or - rdat__h25109 or - rdat__h25115 or - rdat__h25121 or rdat__h25127 or rdat__h25133 or rdat__h25143) + rdat__h24980 or + rdat__h24986 or + rdat__h24992 or + rdat__h25005 or + rdat__h25028 or + rdat__h25128 or + rdat__h25142 or + rdat__h25150 or + rdat__h25156 or + rdat__h25170 or + rdat__h25178 or + rdat__h25184 or + rdat__h25190 or rdat__h25196 or rdat__h25202 or rdat__h25212) begin case (wci_wslv_reqF$D_OUT[39:32]) - 8'h0: g_data__h24868 = smaCtrl; - 8'h04: g_data__h24868 = rdat__h24911; - 8'h08: g_data__h24868 = rdat__h24917; - 8'h10: g_data__h24868 = rdat__h24923; - 8'h14: g_data__h24868 = rdat__h24936; - 8'h18: g_data__h24868 = rdat__h24959; - 8'h20: g_data__h24868 = rdat__h25059; - 8'h24: g_data__h24868 = rdat__h25073; - 8'h28: g_data__h24868 = rdat__h25081; - 8'h2C: g_data__h24868 = rdat__h25087; - 8'h30: g_data__h24868 = rdat__h25101; - 8'h34: g_data__h24868 = rdat__h25109; - 8'h38: g_data__h24868 = rdat__h25115; - 8'h3C: g_data__h24868 = rdat__h25121; - 8'h40: g_data__h24868 = rdat__h25127; - 8'h44: g_data__h24868 = rdat__h25133; - 8'h48: g_data__h24868 = rdat__h25143; - default: g_data__h24868 = 32'd0; + 8'h0: g_data__h24937 = smaCtrl; + 8'h04: g_data__h24937 = rdat__h24980; + 8'h08: g_data__h24937 = rdat__h24986; + 8'h10: g_data__h24937 = rdat__h24992; + 8'h14: g_data__h24937 = rdat__h25005; + 8'h18: g_data__h24937 = rdat__h25028; + 8'h20: g_data__h24937 = rdat__h25128; + 8'h24: g_data__h24937 = rdat__h25142; + 8'h28: g_data__h24937 = rdat__h25150; + 8'h2C: g_data__h24937 = rdat__h25156; + 8'h30: g_data__h24937 = rdat__h25170; + 8'h34: g_data__h24937 = rdat__h25178; + 8'h38: g_data__h24937 = rdat__h25184; + 8'h3C: g_data__h24937 = rdat__h25190; + 8'h40: g_data__h24937 = rdat__h25196; + 8'h44: g_data__h24937 = rdat__h25202; + 8'h48: g_data__h24937 = rdat__h25212; + default: g_data__h24937 = 32'd0; endcase end @@ -2845,22 +2892,22 @@ module mkSMAdapter16B(wciS0_Clk, wci_wslv_illegalEdge <= `BSV_ASSIGNMENT_DELAY 1'd0; wci_wslv_nState <= `BSV_ASSIGNMENT_DELAY 3'd0; wci_wslv_reqF_countReg <= `BSV_ASSIGNMENT_DELAY 2'd0; - wci_wslv_respF_c_r <= `BSV_ASSIGNMENT_DELAY 2'd0; + wci_wslv_respF_cntr_r <= `BSV_ASSIGNMENT_DELAY 2'd0; wci_wslv_respF_q_0 <= `BSV_ASSIGNMENT_DELAY 34'h0AAAAAAAA; wci_wslv_respF_q_1 <= `BSV_ASSIGNMENT_DELAY 34'h0AAAAAAAA; wci_wslv_sFlagReg <= `BSV_ASSIGNMENT_DELAY 1'd0; wci_wslv_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY 1'd1; wmi_busyWithMessage <= `BSV_ASSIGNMENT_DELAY 1'd0; - wmi_dhF_c_r <= `BSV_ASSIGNMENT_DELAY 2'd0; + wmi_dhF_cntr_r <= `BSV_ASSIGNMENT_DELAY 2'd0; wmi_dhF_q_0 <= `BSV_ASSIGNMENT_DELAY 146'd0; wmi_dhF_q_1 <= `BSV_ASSIGNMENT_DELAY 146'd0; wmi_errorSticky <= `BSV_ASSIGNMENT_DELAY 1'd0; - wmi_mFlagF_c_r <= `BSV_ASSIGNMENT_DELAY 2'd0; + wmi_mFlagF_cntr_r <= `BSV_ASSIGNMENT_DELAY 2'd0; wmi_mFlagF_q_0 <= `BSV_ASSIGNMENT_DELAY 32'd0; wmi_mFlagF_q_1 <= `BSV_ASSIGNMENT_DELAY 32'd0; wmi_operateD <= `BSV_ASSIGNMENT_DELAY 1'd0; wmi_peerIsReady <= `BSV_ASSIGNMENT_DELAY 1'd0; - wmi_reqF_c_r <= `BSV_ASSIGNMENT_DELAY 2'd0; + wmi_reqF_cntr_r <= `BSV_ASSIGNMENT_DELAY 2'd0; wmi_reqF_q_0 <= `BSV_ASSIGNMENT_DELAY 32'd0; wmi_reqF_q_1 <= `BSV_ASSIGNMENT_DELAY 32'd0; wmi_sDataThreadBusy_d <= `BSV_ASSIGNMENT_DELAY 1'd0; @@ -2876,7 +2923,7 @@ module mkSMAdapter16B(wciS0_Clk, wsiM_operateD <= `BSV_ASSIGNMENT_DELAY 1'd0; wsiM_pMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0; wsiM_peerIsReady <= `BSV_ASSIGNMENT_DELAY 1'd0; - wsiM_reqFifo_c_r <= `BSV_ASSIGNMENT_DELAY 2'd0; + wsiM_reqFifo_cntr_r <= `BSV_ASSIGNMENT_DELAY 2'd0; wsiM_reqFifo_q_0 <= `BSV_ASSIGNMENT_DELAY 169'h00000AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA00; wsiM_reqFifo_q_1 <= `BSV_ASSIGNMENT_DELAY @@ -2950,8 +2997,9 @@ module mkSMAdapter16B(wciS0_Clk, if (wci_wslv_reqF_countReg$EN) wci_wslv_reqF_countReg <= `BSV_ASSIGNMENT_DELAY wci_wslv_reqF_countReg$D_IN; - if (wci_wslv_respF_c_r$EN) - wci_wslv_respF_c_r <= `BSV_ASSIGNMENT_DELAY wci_wslv_respF_c_r$D_IN; + if (wci_wslv_respF_cntr_r$EN) + wci_wslv_respF_cntr_r <= `BSV_ASSIGNMENT_DELAY + wci_wslv_respF_cntr_r$D_IN; if (wci_wslv_respF_q_0$EN) wci_wslv_respF_q_0 <= `BSV_ASSIGNMENT_DELAY wci_wslv_respF_q_0$D_IN; if (wci_wslv_respF_q_1$EN) @@ -2964,16 +3012,16 @@ module mkSMAdapter16B(wciS0_Clk, if (wmi_busyWithMessage$EN) wmi_busyWithMessage <= `BSV_ASSIGNMENT_DELAY wmi_busyWithMessage$D_IN; - if (wmi_dhF_c_r$EN) - wmi_dhF_c_r <= `BSV_ASSIGNMENT_DELAY wmi_dhF_c_r$D_IN; + if (wmi_dhF_cntr_r$EN) + wmi_dhF_cntr_r <= `BSV_ASSIGNMENT_DELAY wmi_dhF_cntr_r$D_IN; if (wmi_dhF_q_0$EN) wmi_dhF_q_0 <= `BSV_ASSIGNMENT_DELAY wmi_dhF_q_0$D_IN; if (wmi_dhF_q_1$EN) wmi_dhF_q_1 <= `BSV_ASSIGNMENT_DELAY wmi_dhF_q_1$D_IN; if (wmi_errorSticky$EN) wmi_errorSticky <= `BSV_ASSIGNMENT_DELAY wmi_errorSticky$D_IN; - if (wmi_mFlagF_c_r$EN) - wmi_mFlagF_c_r <= `BSV_ASSIGNMENT_DELAY wmi_mFlagF_c_r$D_IN; + if (wmi_mFlagF_cntr_r$EN) + wmi_mFlagF_cntr_r <= `BSV_ASSIGNMENT_DELAY wmi_mFlagF_cntr_r$D_IN; if (wmi_mFlagF_q_0$EN) wmi_mFlagF_q_0 <= `BSV_ASSIGNMENT_DELAY wmi_mFlagF_q_0$D_IN; if (wmi_mFlagF_q_1$EN) @@ -2982,8 +3030,8 @@ module mkSMAdapter16B(wciS0_Clk, wmi_operateD <= `BSV_ASSIGNMENT_DELAY wmi_operateD$D_IN; if (wmi_peerIsReady$EN) wmi_peerIsReady <= `BSV_ASSIGNMENT_DELAY wmi_peerIsReady$D_IN; - if (wmi_reqF_c_r$EN) - wmi_reqF_c_r <= `BSV_ASSIGNMENT_DELAY wmi_reqF_c_r$D_IN; + if (wmi_reqF_cntr_r$EN) + wmi_reqF_cntr_r <= `BSV_ASSIGNMENT_DELAY wmi_reqF_cntr_r$D_IN; if (wmi_reqF_q_0$EN) wmi_reqF_q_0 <= `BSV_ASSIGNMENT_DELAY wmi_reqF_q_0$D_IN; if (wmi_reqF_q_1$EN) @@ -3015,8 +3063,9 @@ module mkSMAdapter16B(wciS0_Clk, wsiM_pMesgCount <= `BSV_ASSIGNMENT_DELAY wsiM_pMesgCount$D_IN; if (wsiM_peerIsReady$EN) wsiM_peerIsReady <= `BSV_ASSIGNMENT_DELAY wsiM_peerIsReady$D_IN; - if (wsiM_reqFifo_c_r$EN) - wsiM_reqFifo_c_r <= `BSV_ASSIGNMENT_DELAY wsiM_reqFifo_c_r$D_IN; + if (wsiM_reqFifo_cntr_r$EN) + wsiM_reqFifo_cntr_r <= `BSV_ASSIGNMENT_DELAY + wsiM_reqFifo_cntr_r$D_IN; if (wsiM_reqFifo_q_0$EN) wsiM_reqFifo_q_0 <= `BSV_ASSIGNMENT_DELAY wsiM_reqFifo_q_0$D_IN; if (wsiM_reqFifo_q_1$EN) @@ -3125,23 +3174,23 @@ module mkSMAdapter16B(wciS0_Clk, wci_wslv_isReset_isInReset = 1'h0; wci_wslv_nState = 3'h2; wci_wslv_reqF_countReg = 2'h2; - wci_wslv_respF_c_r = 2'h2; + wci_wslv_respF_cntr_r = 2'h2; wci_wslv_respF_q_0 = 34'h2AAAAAAAA; wci_wslv_respF_q_1 = 34'h2AAAAAAAA; wci_wslv_sFlagReg = 1'h0; wci_wslv_sThreadBusy_d = 1'h0; wmi_busyWithMessage = 1'h0; - wmi_dhF_c_r = 2'h2; + wmi_dhF_cntr_r = 2'h2; wmi_dhF_q_0 = 146'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; wmi_dhF_q_1 = 146'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; wmi_errorSticky = 1'h0; wmi_isReset_isInReset = 1'h0; - wmi_mFlagF_c_r = 2'h2; + wmi_mFlagF_cntr_r = 2'h2; wmi_mFlagF_q_0 = 32'hAAAAAAAA; wmi_mFlagF_q_1 = 32'hAAAAAAAA; wmi_operateD = 1'h0; wmi_peerIsReady = 1'h0; - wmi_reqF_c_r = 2'h2; + wmi_reqF_cntr_r = 2'h2; wmi_reqF_q_0 = 32'hAAAAAAAA; wmi_reqF_q_1 = 32'hAAAAAAAA; wmi_sDataThreadBusy_d = 1'h0; @@ -3159,7 +3208,7 @@ module mkSMAdapter16B(wciS0_Clk, wsiM_operateD = 1'h0; wsiM_pMesgCount = 32'hAAAAAAAA; wsiM_peerIsReady = 1'h0; - wsiM_reqFifo_c_r = 2'h2; + wsiM_reqFifo_cntr_r = 2'h2; wsiM_reqFifo_q_0 = 169'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; wsiM_reqFifo_q_1 = 169'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; wsiM_sThreadBusy_d = 1'h0; @@ -3193,96 +3242,96 @@ module mkSMAdapter16B(wciS0_Clk, if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_start) begin - v__h3729 = $time; + v__h3597 = $time; #0; end if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_start) $display("[%0d]: %m: WCI ControlOp: Starting-transition edge:%x from:%x", - v__h3729, + v__h3597, wci_wslv_reqF$D_OUT[36:34], wci_wslv_cState); if (wciS0_MReset_n != `BSV_RESET_VALUE) if (MUX_unrollCnt$write_1__SEL_1) begin - v__h18699 = $time; + v__h18073 = $time; #0; end if (wciS0_MReset_n != `BSV_RESET_VALUE) if (MUX_unrollCnt$write_1__SEL_1) $display("[%0d]: %m: wmrd_mesgBegin mesgCount:%0h mesgLength:%0h reqInfo:%0h", - v__h18699, + v__h18073, mesgCount, wmi_sFlagReg[23:0], wmi_sFlagReg[31:24]); if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wmwt_mesgBegin && wsiS_reqFifo$D_OUT[164]) begin - v__h22418 = $time; + v__h22489 = $time; #0; end if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wmwt_mesgBegin && wsiS_reqFifo$D_OUT[164]) $display("[%0d]: %m: mesgBegin PRECISE mesgCount:%0x WSI burstLength:%0x reqInfo:%0x", - v__h22418, + v__h22489, mesgCount, wsiS_reqFifo$D_OUT[163:152], wsiS_reqFifo$D_OUT[7:0]); if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wmwt_mesgBegin && !wsiS_reqFifo$D_OUT[164]) begin - v__h22477 = $time; + v__h22548 = $time; #0; end if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wmwt_mesgBegin && !wsiS_reqFifo$D_OUT[164]) $display("[%0d]: %m: wmwt_mesgBegin IMPRECISE mesgCount:%0x", - v__h22477, + v__h22548, mesgCount); if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wmwt_doAbort) begin - v__h24317 = $time; + v__h24386 = $time; #0; end if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wmwt_doAbort) - $display("[%0d]: %m: wmwt_doAbort", v__h24317); + $display("[%0d]: %m: wmwt_doAbort", v__h24386); if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wmwt_messageFinalize) begin - v__h24500 = $time; + v__h24569 = $time; #0; end if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wmwt_messageFinalize) $display("[%0d]: %m: wmwt_messageFinalize mesgCount:%0x WSI mesgLength:%0x", - v__h24500, + v__h24569, mesgCount, thisMesg[15:0]); if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfwr) begin - v__h24696 = $time; + v__h24765 = $time; #0; end if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfwr) $display("[%0d]: %m: SMAdapter WCI CONFIG WRITE Addr:%0x BE:%0x Data:%0x", - v__h24696, + v__h24765, wci_wslv_reqF$D_OUT[63:32], wci_wslv_reqF$D_OUT[67:64], wci_wslv_reqF$D_OUT[31:0]); if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_ctrl_IsO) begin - v__h25358 = $time; + v__h25422 = $time; #0; end if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_ctrl_IsO) $display("[%0d]: %m: Starting SMAdapter smaCtrl:%0x", - v__h25358, + v__h25422, smaCtrl); if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_OrE) @@ -3317,25 +3366,25 @@ module mkSMAdapter16B(wciS0_Clk, if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge) begin - v__h4048 = $time; + v__h3916 = $time; #0; end if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge) $display("[%0d]: %m: WCI ControlOp: ILLEGAL-EDGE Completed-transition edge:%x from:%x", - v__h4048, + v__h3916, wci_wslv_cEdge, wci_wslv_cState); if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && !wci_wslv_illegalEdge) begin - v__h3904 = $time; + v__h3772 = $time; #0; end if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && !wci_wslv_illegalEdge) $display("[%0d]: %m: WCI ControlOp: Completed-transition edge:%x from:%x to:%x", - v__h3904, + v__h3772, wci_wslv_cEdge, wci_wslv_cState, wci_wslv_nState); diff --git a/rtl/mkSMAdapter32B.v b/rtl/mkSMAdapter32B.v index 4dfb5495..93101b0e 100644 --- a/rtl/mkSMAdapter32B.v +++ b/rtl/mkSMAdapter32B.v @@ -1,7 +1,7 @@ // -// Generated by Bluespec Compiler, version 2012.09.beta1 (build 29570, 2012-09.11) +// Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Tue Dec 11 16:21:14 EST 2012 +// On Fri Jun 21 16:58:01 EDT 2013 // // // Ports: @@ -383,6 +383,7 @@ module mkSMAdapter32B(wciS0_Clk, fabRespCredit_acc_v2$whas, mesgPreRequest_1$wget, mesgPreRequest_1$whas, + respF_pwClear$whas, respF_pwDequeue$whas, respF_pwEnqueue$whas, respF_wDataIn$whas, @@ -608,10 +609,10 @@ module mkSMAdapter32B(wciS0_Clk, wire [1 : 0] wci_wslv_reqF_countReg$D_IN; wire wci_wslv_reqF_countReg$EN; - // register wci_wslv_respF_c_r - reg [1 : 0] wci_wslv_respF_c_r; - wire [1 : 0] wci_wslv_respF_c_r$D_IN; - wire wci_wslv_respF_c_r$EN; + // register wci_wslv_respF_cntr_r + reg [1 : 0] wci_wslv_respF_cntr_r; + wire [1 : 0] wci_wslv_respF_cntr_r$D_IN; + wire wci_wslv_respF_cntr_r$EN; // register wci_wslv_respF_q_0 reg [33 : 0] wci_wslv_respF_q_0; @@ -635,10 +636,10 @@ module mkSMAdapter32B(wciS0_Clk, reg wmi_busyWithMessage; wire wmi_busyWithMessage$D_IN, wmi_busyWithMessage$EN; - // register wmi_dhF_c_r - reg [1 : 0] wmi_dhF_c_r; - wire [1 : 0] wmi_dhF_c_r$D_IN; - wire wmi_dhF_c_r$EN; + // register wmi_dhF_cntr_r + reg [1 : 0] wmi_dhF_cntr_r; + wire [1 : 0] wmi_dhF_cntr_r$D_IN; + wire wmi_dhF_cntr_r$EN; // register wmi_dhF_q_0 reg [289 : 0] wmi_dhF_q_0; @@ -658,10 +659,10 @@ module mkSMAdapter32B(wciS0_Clk, reg wmi_isReset_isInReset; wire wmi_isReset_isInReset$D_IN, wmi_isReset_isInReset$EN; - // register wmi_mFlagF_c_r - reg [1 : 0] wmi_mFlagF_c_r; - wire [1 : 0] wmi_mFlagF_c_r$D_IN; - wire wmi_mFlagF_c_r$EN; + // register wmi_mFlagF_cntr_r + reg [1 : 0] wmi_mFlagF_cntr_r; + wire [1 : 0] wmi_mFlagF_cntr_r$D_IN; + wire wmi_mFlagF_cntr_r$EN; // register wmi_mFlagF_q_0 reg [31 : 0] wmi_mFlagF_q_0; @@ -681,10 +682,10 @@ module mkSMAdapter32B(wciS0_Clk, reg wmi_peerIsReady; wire wmi_peerIsReady$D_IN, wmi_peerIsReady$EN; - // register wmi_reqF_c_r - reg [1 : 0] wmi_reqF_c_r; - wire [1 : 0] wmi_reqF_c_r$D_IN; - wire wmi_reqF_c_r$EN; + // register wmi_reqF_cntr_r + reg [1 : 0] wmi_reqF_cntr_r; + wire [1 : 0] wmi_reqF_cntr_r$D_IN; + wire wmi_reqF_cntr_r$EN; // register wmi_reqF_q_0 reg [31 : 0] wmi_reqF_q_0; @@ -764,10 +765,10 @@ module mkSMAdapter32B(wciS0_Clk, reg wsiM_peerIsReady; wire wsiM_peerIsReady$D_IN, wsiM_peerIsReady$EN; - // register wsiM_reqFifo_c_r - reg [1 : 0] wsiM_reqFifo_c_r; - wire [1 : 0] wsiM_reqFifo_c_r$D_IN; - wire wsiM_reqFifo_c_r$EN; + // register wsiM_reqFifo_cntr_r + reg [1 : 0] wsiM_reqFifo_cntr_r; + wire [1 : 0] wsiM_reqFifo_cntr_r$D_IN; + wire wsiM_reqFifo_cntr_r$EN; // register wsiM_reqFifo_q_0 reg [312 : 0] wsiM_reqFifo_q_0; @@ -937,11 +938,11 @@ module mkSMAdapter32B(wciS0_Clk, reg [33 : 0] MUX_wci_wslv_respF_q_0$write_1__VAL_2; wire [312 : 0] MUX_wsiM_reqFifo_q_0$write_1__VAL_1, MUX_wsiM_reqFifo_q_0$write_1__VAL_2, - MUX_wsiM_reqFifo_q_1$write_1__VAL_1, + MUX_wsiM_reqFifo_q_1$write_1__VAL_2, MUX_wsiM_reqFifo_x_wire$wset_1__VAL_3; wire [289 : 0] MUX_wmi_dhF_q_0$write_1__VAL_1, MUX_wmi_dhF_q_0$write_1__VAL_2, - MUX_wmi_dhF_q_1$write_1__VAL_1; + MUX_wmi_dhF_q_1$write_1__VAL_2; wire [33 : 0] MUX_wci_wslv_respF_q_0$write_1__VAL_1, MUX_wci_wslv_respF_q_1$write_1__VAL_1, MUX_wci_wslv_respF_x_wire$wset_1__VAL_1, @@ -964,16 +965,12 @@ module mkSMAdapter32B(wciS0_Clk, MUX_mesgReqAddr$write_1__VAL_2; wire [11 : 0] MUX_fabRespCredit_value$write_1__VAL_2; wire [8 : 0] MUX_opcode$write_1__VAL_3; - wire [1 : 0] MUX_wci_wslv_respF_c_r$write_1__VAL_1, - MUX_wci_wslv_respF_c_r$write_1__VAL_2, - MUX_wmi_dhF_c_r$write_1__VAL_1, - MUX_wmi_dhF_c_r$write_1__VAL_2, - MUX_wmi_mFlagF_c_r$write_1__VAL_1, - MUX_wmi_mFlagF_c_r$write_1__VAL_2, - MUX_wmi_reqF_c_r$write_1__VAL_1, - MUX_wmi_reqF_c_r$write_1__VAL_2, - MUX_wsiM_reqFifo_c_r$write_1__VAL_1, - MUX_wsiM_reqFifo_c_r$write_1__VAL_2; + wire [1 : 0] MUX_wci_wslv_respF_cntr_r$write_1__VAL_2, + MUX_wmi_dhF_cntr_r$write_1__VAL_2, + MUX_wmi_mFlagF_cntr_r$write_1__VAL_2, + MUX_wmi_reqF_cntr_r$write_1__VAL_2, + MUX_wsiM_reqFifo_cntr_r$write_1__VAL_1, + MUX_wsiM_reqFifo_cntr_r$write_1__VAL_2; wire MUX_endOfMessage$write_1__SEL_1, MUX_mesgCount$write_1__SEL_1, MUX_mesgReqOK$write_1__SEL_3, @@ -981,128 +978,152 @@ module mkSMAdapter32B(wciS0_Clk, MUX_unrollCnt$write_1__SEL_2, MUX_wci_wslv_illegalEdge$write_1__SEL_1, MUX_wci_wslv_illegalEdge$write_1__VAL_1, + MUX_wci_wslv_respF_q_0$write_1__SEL_1, MUX_wci_wslv_respF_q_0$write_1__SEL_2, + MUX_wci_wslv_respF_q_1$write_1__SEL_1, MUX_wci_wslv_respF_q_1$write_1__SEL_2, + MUX_wmi_dhF_q_0$write_1__SEL_1, MUX_wmi_dhF_q_0$write_1__SEL_2, + MUX_wmi_dhF_q_1$write_1__SEL_1, MUX_wmi_dhF_q_1$write_1__SEL_2, + MUX_wmi_mFlagF_q_0$write_1__SEL_1, MUX_wmi_mFlagF_q_0$write_1__SEL_2, + MUX_wmi_mFlagF_q_1$write_1__SEL_1, MUX_wmi_mFlagF_q_1$write_1__SEL_2, MUX_wmi_mFlagF_x_wire$wset_1__SEL_1, + MUX_wmi_reqF_q_0$write_1__SEL_1, MUX_wmi_reqF_q_0$write_1__SEL_2, + MUX_wmi_reqF_q_1$write_1__SEL_1, MUX_wmi_reqF_q_1$write_1__SEL_2, + MUX_wsiM_reqFifo_q_0$write_1__SEL_1, MUX_wsiM_reqFifo_q_0$write_1__SEL_2, + MUX_wsiM_reqFifo_q_1$write_1__SEL_1, MUX_wsiM_reqFifo_q_1$write_1__SEL_2, MUX_wsiM_reqFifo_x_wire$wset_1__SEL_1, MUX_wsiM_reqFifo_x_wire$wset_1__SEL_2, MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3; // remaining internal signals - reg [63 : 0] v__h18699, - v__h22418, - v__h22477, - v__h24973, - v__h25156, - v__h25352, - v__h26014, - v__h3729, - v__h3904, - v__h4048; - reg [31 : 0] g_data__h25524; - wire [307 : 0] IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d968; - wire [31 : 0] rdat__h25567, - rdat__h25573, - rdat__h25579, - rdat__h25592, - rdat__h25615, - rdat__h25715, - rdat__h25729, - rdat__h25737, - rdat__h25743, - rdat__h25757, - rdat__h25765, - rdat__h25771, - rdat__h25777, - rdat__h25783, - rdat__h25789, - rdat__h25799, - sendData_byteEn__h19245, - value__h6702; - wire [23 : 0] b__h18410, - mesgMetaF_length__h22999, - residue__h18273, - x__h18530; - wire [15 : 0] wsiBurstLength__h19161, x__h25619, x_length__h24547; - wire [13 : 0] b__h18783, mlB__h22832, mlInc__h22831; - wire [11 : 0] b__h15473, sendData_burstLength__h19243, x__h16878; - wire [7 : 0] mesgMetaF_opcode__h22998; - wire [5 : 0] x__h23038, - x__h23050, - x__h23062, - x__h23074, - x__h23086, - x__h23098, - x__h23110, - x__h23122, - x__h23134, - x__h23146, - x__h23158, - x__h23170, - x__h23182, - x__h23194, - x__h23206, - x__h23218, - x__h23230, - x__h23242, - x__h23254, - x__h23266, - x__h23278, - x__h23290, - x__h23302, - x__h23314, - x__h23326, - x__h23338, - x__h23350, - x__h23362, - x__h23374, - x__h23386, - x__h23398, - y__h23039, - y__h23051, - y__h23063, - y__h23075, - y__h23087, - y__h23099, - y__h23111, - y__h23123, - y__h23135, - y__h23147, - y__h23159, - y__h23171, - y__h23183, - y__h23195, - y__h23207, - y__h23219, - y__h23231, - y__h23243, - y__h23255, - y__h23267, - y__h23279, - y__h23291, - y__h23303, - y__h23315, - y__h23327, - y__h23339, - y__h23351, - y__h23363, - y__h23375, - y__h23387, - y__h23399; - wire [2 : 0] IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d966; - wire NOT_wmi_reqF_c_r_57_EQ_2_75_76_AND_wmi_operate_ETC___d524, - wmi_respF_i_notEmpty__37_AND_smaCtrl_65_BIT_4__ETC___d542, - wsiS_reqFifo_i_notEmpty__64_AND_NOT_smaCtrl_65_ETC___d669, - x__h18954, - x__h25793; + reg [63 : 0] v__h18073, + v__h21792, + v__h21851, + v__h24345, + v__h24528, + v__h24724, + v__h25381, + v__h3597, + v__h3772, + v__h3916; + reg [31 : 0] g_data__h24896; + wire [307 : 0] IF_respF_wDataIn_whas__28_THEN_respF_wDataIn_w_ETC___d437; + wire [31 : 0] rdat__h24939, + rdat__h24945, + rdat__h24951, + rdat__h24964, + rdat__h24987, + rdat__h25087, + rdat__h25101, + rdat__h25109, + rdat__h25115, + rdat__h25129, + rdat__h25137, + rdat__h25143, + rdat__h25149, + rdat__h25155, + rdat__h25161, + rdat__h25171, + sendData_byteEn__h18619, + value__h6387; + wire [23 : 0] b__h17784, + mesgMetaF_length__h22373, + residue__h17647, + x__h17904; + wire [15 : 0] wsiBurstLength__h18535, x__h24991, x_length__h23920; + wire [13 : 0] b__h18157, mlB__h22206, mlInc__h22205; + wire [11 : 0] b__h14802, sendData_burstLength__h18617, x__h16103, x__h16253; + wire [7 : 0] mesgMetaF_opcode__h22372; + wire [5 : 0] x__h22411, + x__h22423, + x__h22435, + x__h22447, + x__h22459, + x__h22471, + x__h22483, + x__h22495, + x__h22507, + x__h22519, + x__h22531, + x__h22543, + x__h22555, + x__h22567, + x__h22579, + x__h22591, + x__h22603, + x__h22615, + x__h22627, + x__h22639, + x__h22651, + x__h22663, + x__h22675, + x__h22687, + x__h22699, + x__h22711, + x__h22723, + x__h22735, + x__h22747, + x__h22759, + x__h22771, + y__h22412, + y__h22424, + y__h22436, + y__h22448, + y__h22460, + y__h22472, + y__h22484, + y__h22496, + y__h22508, + y__h22520, + y__h22532, + y__h22544, + y__h22556, + y__h22568, + y__h22580, + y__h22592, + y__h22604, + y__h22616, + y__h22628, + y__h22640, + y__h22652, + y__h22664, + y__h22676, + y__h22688, + y__h22700, + y__h22712, + y__h22724, + y__h22736, + y__h22748, + y__h22760, + y__h22772; + wire [2 : 0] IF_respF_wDataIn_whas__28_THEN_respF_wDataIn_w_ETC___d431; + wire [1 : 0] wci_wslv_respF_cntr_r_8_MINUS_1___d27, + wmi_dhF_cntr_r_05_MINUS_1___d213, + wmi_mFlagF_cntr_r_83_MINUS_1___d191, + wmi_reqF_cntr_r_61_MINUS_1___d169; + wire NOT_wmi_reqF_cntr_r_61_EQ_2_73_74_AND_wmi_oper_ETC___d521, + _dfoo1, + _dfoo11, + _dfoo13, + _dfoo15, + _dfoo17, + _dfoo19, + _dfoo3, + _dfoo5, + _dfoo7, + _dfoo9, + wmi_respF_i_notEmpty__34_AND_smaCtrl_62_BIT_4__ETC___d539, + wsiS_reqFifo_i_notEmpty__61_AND_NOT_smaCtrl_62_ETC___d666, + x__h18328, + x__h25165; // value method wciS0_sResp assign wciS0_SResp = wci_wslv_respF_q_0[33:32] ; @@ -1262,7 +1283,7 @@ module mkSMAdapter32B(wciS0_Clk, // rule RL_wmrd_mesgBodyRequest assign WILL_FIRE_RL_wmrd_mesgBodyRequest = - NOT_wmi_reqF_c_r_57_EQ_2_75_76_AND_wmi_operate_ETC___d524 && + NOT_wmi_reqF_cntr_r_61_EQ_2_73_74_AND_wmi_oper_ETC___d521 && wci_wslv_cState == 3'd2 && (smaCtrl[3:0] == 4'h1 || smaCtrl[3:0] == 4'h4 || smaCtrl[3:0] == 4'h9) && @@ -1293,18 +1314,18 @@ module mkSMAdapter32B(wciS0_Clk, // rule RL_wsiM_reqFifo_deq assign WILL_FIRE_RL_wsiM_reqFifo_deq = - wsiM_reqFifo_c_r != 2'd0 && !wsiM_sThreadBusy_d ; + wsiM_reqFifo_cntr_r != 2'd0 && !wsiM_sThreadBusy_d ; // rule RL_wsipass_doMessagePush assign WILL_FIRE_RL_wsipass_doMessagePush = wsiS_reqFifo$EMPTY_N && - (smaCtrl[4] || wsiM_reqFifo_c_r != 2'd2) && + (smaCtrl[4] || wsiM_reqFifo_cntr_r != 2'd2) && wci_wslv_cState == 3'd2 && smaCtrl[3:0] == 4'h0 ; // rule RL_wci_cfrd assign WILL_FIRE_RL_wci_cfrd = - wci_wslv_respF_c_r != 2'd2 && wci_wslv_reqF$EMPTY_N && + wci_wslv_respF_cntr_r != 2'd2 && wci_wslv_reqF$EMPTY_N && wci_wslv_wci_cfrd_pw$whas && !WILL_FIRE_RL_wci_wslv_ctl_op_start && !WILL_FIRE_RL_wci_wslv_ctl_op_complete ; @@ -1323,9 +1344,10 @@ module mkSMAdapter32B(wciS0_Clk, // rule RL_wmwt_messagePush assign CAN_FIRE_RL_wmwt_messagePush = - wmi_reqF_c_r != 2'd2 && wmi_dhF_c_r != 2'd2 && wmi_operateD && + wmi_reqF_cntr_r != 2'd2 && wmi_dhF_cntr_r != 2'd2 && + wmi_operateD && wmi_peerIsReady && - wsiS_reqFifo_i_notEmpty__64_AND_NOT_smaCtrl_65_ETC___d669 && + wsiS_reqFifo_i_notEmpty__61_AND_NOT_smaCtrl_62_ETC___d666 && wci_wslv_cState == 3'd2 && (smaCtrl[3:0] == 4'h2 || smaCtrl[3:0] == 4'h3) && readyToPush ; @@ -1345,10 +1367,7 @@ module mkSMAdapter32B(wciS0_Clk, // rule RL_wmi_reqF_incCtr assign WILL_FIRE_RL_wmi_reqF_incCtr = - ((wmi_reqF_c_r == 2'd0) ? - wmi_reqF_x_wire$whas : - wmi_reqF_c_r != 2'd1 || wmi_reqF_x_wire$whas) && - wmi_reqF_enqueueing$whas && + wmi_reqF_x_wire$whas && wmi_reqF_enqueueing$whas && !wmi_reqF_dequeueing$whas ; // rule RL_wmi_reqF_decCtr @@ -1357,18 +1376,12 @@ module mkSMAdapter32B(wciS0_Clk, // rule RL_wmi_reqF_both assign WILL_FIRE_RL_wmi_reqF_both = - ((wmi_reqF_c_r == 2'd1) ? - wmi_reqF_x_wire$whas : - wmi_reqF_c_r != 2'd2 || wmi_reqF_x_wire$whas) && - wmi_reqF_dequeueing$whas && + wmi_reqF_x_wire$whas && wmi_reqF_dequeueing$whas && wmi_reqF_enqueueing$whas ; // rule RL_wmi_mFlagF_incCtr assign WILL_FIRE_RL_wmi_mFlagF_incCtr = - ((wmi_mFlagF_c_r == 2'd0) ? - wmi_mFlagF_enqueueing$whas : - wmi_mFlagF_c_r != 2'd1 || wmi_mFlagF_enqueueing$whas) && - wmi_mFlagF_enqueueing$whas && + wmi_mFlagF_enqueueing$whas && wmi_mFlagF_enqueueing$whas && !wmi_mFlagF_dequeueing$whas ; // rule RL_wmi_mFlagF_decCtr @@ -1377,18 +1390,12 @@ module mkSMAdapter32B(wciS0_Clk, // rule RL_wmi_mFlagF_both assign WILL_FIRE_RL_wmi_mFlagF_both = - ((wmi_mFlagF_c_r == 2'd1) ? - wmi_mFlagF_enqueueing$whas : - wmi_mFlagF_c_r != 2'd2 || wmi_mFlagF_enqueueing$whas) && - wmi_mFlagF_dequeueing$whas && + wmi_mFlagF_enqueueing$whas && wmi_mFlagF_dequeueing$whas && wmi_mFlagF_enqueueing$whas ; // rule RL_wmi_dhF_incCtr assign WILL_FIRE_RL_wmi_dhF_incCtr = - ((wmi_dhF_c_r == 2'd0) ? - MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 : - wmi_dhF_c_r != 2'd1 || - MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3) && + MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 && MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 && !wmi_dhF_dequeueing$whas ; @@ -1399,33 +1406,27 @@ module mkSMAdapter32B(wciS0_Clk, // rule RL_wmi_dhF_both assign WILL_FIRE_RL_wmi_dhF_both = - ((wmi_dhF_c_r == 2'd1) ? - MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 : - wmi_dhF_c_r != 2'd2 || - MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3) && + MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 && wmi_dhF_dequeueing$whas && MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 ; // rule RL_wmrd_mesgResptoWsi assign WILL_FIRE_RL_wmrd_mesgResptoWsi = - wsiM_reqFifo_c_r != 2'd2 && respF_rRdPtr != respF_rWrPtr && + wsiM_reqFifo_cntr_r != 2'd2 && respF_rRdPtr != respF_rWrPtr && wci_wslv_cState == 3'd2 && (smaCtrl[3:0] == 4'h1 || smaCtrl[3:0] == 4'h4 || smaCtrl[3:0] == 4'h9) ; // rule RL_wci_cfwr assign WILL_FIRE_RL_wci_cfwr = - wci_wslv_respF_c_r != 2'd2 && wci_wslv_reqF$EMPTY_N && + wci_wslv_respF_cntr_r != 2'd2 && wci_wslv_reqF$EMPTY_N && wci_wslv_wci_cfwr_pw$whas && !WILL_FIRE_RL_wci_wslv_ctl_op_start && !WILL_FIRE_RL_wci_wslv_ctl_op_complete ; // rule RL_wsiM_reqFifo_incCtr assign WILL_FIRE_RL_wsiM_reqFifo_incCtr = - ((wsiM_reqFifo_c_r == 2'd0) ? - wsiM_reqFifo_enqueueing$whas : - wsiM_reqFifo_c_r != 2'd1 || wsiM_reqFifo_enqueueing$whas) && - wsiM_reqFifo_enqueueing$whas && + wsiM_reqFifo_enqueueing$whas && wsiM_reqFifo_enqueueing$whas && !WILL_FIRE_RL_wsiM_reqFifo_deq ; // rule RL_wsiM_reqFifo_decCtr @@ -1434,10 +1435,7 @@ module mkSMAdapter32B(wciS0_Clk, // rule RL_wsiM_reqFifo_both assign WILL_FIRE_RL_wsiM_reqFifo_both = - ((wsiM_reqFifo_c_r == 2'd1) ? - wsiM_reqFifo_enqueueing$whas : - wsiM_reqFifo_c_r != 2'd2 || wsiM_reqFifo_enqueueing$whas) && - WILL_FIRE_RL_wsiM_reqFifo_deq && + wsiM_reqFifo_enqueueing$whas && WILL_FIRE_RL_wsiM_reqFifo_deq && wsiM_reqFifo_enqueueing$whas ; // rule RL_wci_ctrl_IsO @@ -1449,27 +1447,22 @@ module mkSMAdapter32B(wciS0_Clk, // rule RL_wci_wslv_ctl_op_complete assign WILL_FIRE_RL_wci_wslv_ctl_op_complete = - wci_wslv_respF_c_r != 2'd2 && wci_wslv_ctlOpActive && + wci_wslv_respF_cntr_r != 2'd2 && wci_wslv_ctlOpActive && wci_wslv_ctlAckReg ; // rule RL_wci_wslv_respF_incCtr assign WILL_FIRE_RL_wci_wslv_respF_incCtr = - ((wci_wslv_respF_c_r == 2'd0) ? - wci_wslv_respF_x_wire$whas : - wci_wslv_respF_c_r != 2'd1 || wci_wslv_respF_x_wire$whas) && - wci_wslv_respF_enqueueing$whas && - !(wci_wslv_respF_c_r != 2'd0) ; + wci_wslv_respF_x_wire$whas && wci_wslv_respF_enqueueing$whas && + !(wci_wslv_respF_cntr_r != 2'd0) ; // rule RL_wci_wslv_respF_decCtr assign WILL_FIRE_RL_wci_wslv_respF_decCtr = - wci_wslv_respF_c_r != 2'd0 && !wci_wslv_respF_enqueueing$whas ; + wci_wslv_respF_cntr_r != 2'd0 && + !wci_wslv_respF_enqueueing$whas ; // rule RL_wci_wslv_respF_both assign WILL_FIRE_RL_wci_wslv_respF_both = - ((wci_wslv_respF_c_r == 2'd1) ? - wci_wslv_respF_x_wire$whas : - wci_wslv_respF_c_r != 2'd2 || wci_wslv_respF_x_wire$whas) && - wci_wslv_respF_c_r != 2'd0 && + wci_wslv_respF_x_wire$whas && wci_wslv_respF_cntr_r != 2'd0 && wci_wslv_respF_enqueueing$whas ; // rule RL_wsiS_reqFifo_enq @@ -1498,7 +1491,7 @@ module mkSMAdapter32B(wciS0_Clk, !wmi_sDataThreadBusy_d && unrollCnt == 16'd0 ; assign MUX_unrollCnt$write_1__SEL_2 = - wmi_respF_i_notEmpty__37_AND_smaCtrl_65_BIT_4__ETC___d542 && + wmi_respF_i_notEmpty__34_AND_smaCtrl_62_BIT_4__ETC___d539 && wci_wslv_cState == 3'd2 && (smaCtrl[3:0] == 4'h1 || smaCtrl[3:0] == 4'h4 || smaCtrl[3:0] == 4'h9) && @@ -1516,66 +1509,86 @@ module mkSMAdapter32B(wciS0_Clk, wci_wslv_reqF$D_OUT[36:34] == 3'd5 || wci_wslv_reqF$D_OUT[36:34] == 3'd6 || wci_wslv_reqF$D_OUT[36:34] == 3'd7) ; + assign MUX_wci_wslv_respF_q_0$write_1__SEL_1 = + WILL_FIRE_RL_wci_wslv_respF_both && _dfoo3 ; assign MUX_wci_wslv_respF_q_0$write_1__SEL_2 = WILL_FIRE_RL_wci_wslv_respF_incCtr && - wci_wslv_respF_c_r == 2'd0 ; + wci_wslv_respF_cntr_r == 2'd0 ; + assign MUX_wci_wslv_respF_q_1$write_1__SEL_1 = + WILL_FIRE_RL_wci_wslv_respF_both && _dfoo1 ; assign MUX_wci_wslv_respF_q_1$write_1__SEL_2 = WILL_FIRE_RL_wci_wslv_respF_incCtr && - wci_wslv_respF_c_r == 2'd1 ; + wci_wslv_respF_cntr_r == 2'd1 ; + assign MUX_wmi_dhF_q_0$write_1__SEL_1 = + WILL_FIRE_RL_wmi_dhF_incCtr && wmi_dhF_cntr_r == 2'd0 ; assign MUX_wmi_dhF_q_0$write_1__SEL_2 = - WILL_FIRE_RL_wmi_dhF_incCtr && wmi_dhF_c_r == 2'd0 ; + WILL_FIRE_RL_wmi_dhF_both && _dfoo15 ; + assign MUX_wmi_dhF_q_1$write_1__SEL_1 = + WILL_FIRE_RL_wmi_dhF_incCtr && wmi_dhF_cntr_r == 2'd1 ; assign MUX_wmi_dhF_q_1$write_1__SEL_2 = - WILL_FIRE_RL_wmi_dhF_incCtr && wmi_dhF_c_r == 2'd1 ; + WILL_FIRE_RL_wmi_dhF_both && _dfoo13 ; + assign MUX_wmi_mFlagF_q_0$write_1__SEL_1 = + WILL_FIRE_RL_wmi_mFlagF_both && _dfoo11 ; assign MUX_wmi_mFlagF_q_0$write_1__SEL_2 = - WILL_FIRE_RL_wmi_mFlagF_incCtr && wmi_mFlagF_c_r == 2'd0 ; + WILL_FIRE_RL_wmi_mFlagF_incCtr && wmi_mFlagF_cntr_r == 2'd0 ; + assign MUX_wmi_mFlagF_q_1$write_1__SEL_1 = + WILL_FIRE_RL_wmi_mFlagF_both && _dfoo9 ; assign MUX_wmi_mFlagF_q_1$write_1__SEL_2 = - WILL_FIRE_RL_wmi_mFlagF_incCtr && wmi_mFlagF_c_r == 2'd1 ; + WILL_FIRE_RL_wmi_mFlagF_incCtr && wmi_mFlagF_cntr_r == 2'd1 ; assign MUX_wmi_mFlagF_x_wire$wset_1__SEL_1 = - WILL_FIRE_RL_wmrd_mesgBodyRequest && x__h18954 ; + WILL_FIRE_RL_wmrd_mesgBodyRequest && x__h18328 ; + assign MUX_wmi_reqF_q_0$write_1__SEL_1 = + WILL_FIRE_RL_wmi_reqF_both && _dfoo7 ; assign MUX_wmi_reqF_q_0$write_1__SEL_2 = - WILL_FIRE_RL_wmi_reqF_incCtr && wmi_reqF_c_r == 2'd0 ; + WILL_FIRE_RL_wmi_reqF_incCtr && wmi_reqF_cntr_r == 2'd0 ; + assign MUX_wmi_reqF_q_1$write_1__SEL_1 = + WILL_FIRE_RL_wmi_reqF_both && _dfoo5 ; assign MUX_wmi_reqF_q_1$write_1__SEL_2 = - WILL_FIRE_RL_wmi_reqF_incCtr && wmi_reqF_c_r == 2'd1 ; + WILL_FIRE_RL_wmi_reqF_incCtr && wmi_reqF_cntr_r == 2'd1 ; + assign MUX_wsiM_reqFifo_q_0$write_1__SEL_1 = + WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_cntr_r == 2'd0 ; assign MUX_wsiM_reqFifo_q_0$write_1__SEL_2 = - WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_c_r == 2'd0 ; + WILL_FIRE_RL_wsiM_reqFifo_both && _dfoo19 ; + assign MUX_wsiM_reqFifo_q_1$write_1__SEL_1 = + WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_cntr_r == 2'd1 ; assign MUX_wsiM_reqFifo_q_1$write_1__SEL_2 = - WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_c_r == 2'd1 ; + WILL_FIRE_RL_wsiM_reqFifo_both && _dfoo17 ; assign MUX_wsiM_reqFifo_x_wire$wset_1__SEL_1 = + WILL_FIRE_RL_wsipass_doMessagePush && !smaCtrl[4] ; + assign MUX_wsiM_reqFifo_x_wire$wset_1__SEL_2 = MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 && smaCtrl[3:0] == 4'h3 ; - assign MUX_wsiM_reqFifo_x_wire$wset_1__SEL_2 = - WILL_FIRE_RL_wsipass_doMessagePush && !smaCtrl[4] ; assign MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 = CAN_FIRE_RL_wmwt_messagePush && !WILL_FIRE_RL_wmwt_messageFinalize ; assign MUX_fabRespCredit_value$write_1__VAL_2 = fabRespCredit_value + - (WILL_FIRE_RL_wmrd_mesgBodyRequest ? b__h15473 : 12'd0) + + (WILL_FIRE_RL_wmrd_mesgBodyRequest ? b__h14802 : 12'd0) + (WILL_FIRE_RL_wmrd_mesgResptoWsi ? 12'd1 : 12'd0) ; assign MUX_fabWordsRemain$write_1__VAL_1 = - (wmi_sFlagReg[23:0] == 24'd0) ? 14'd1 : b__h18410[13:0] ; + (wmi_sFlagReg[23:0] == 24'd0) ? 14'd1 : b__h17784[13:0] ; assign MUX_fabWordsRemain$write_1__VAL_2 = fabWordsRemain - fabWordsCurReq ; assign MUX_mesgCount$write_1__VAL_1 = mesgCount + 32'd1 ; assign MUX_mesgLengthSoFar$write_1__VAL_1 = - mesgLengthSoFar + mlInc__h22831 ; + mesgLengthSoFar + mlInc__h22205 ; assign MUX_mesgReqAddr$write_1__VAL_2 = mesgReqAddr + { fabWordsCurReq[8:0], 5'd0 } ; assign MUX_opcode$write_1__VAL_3 = { 1'd1, wsiS_reqFifo$D_OUT[7:0] } ; assign MUX_thisMesg$write_1__VAL_1 = - { mesgCount[7:0], mesgMetaF_opcode__h22998, x_length__h24547 } ; + { mesgCount[7:0], mesgMetaF_opcode__h22372, x_length__h23920 } ; assign MUX_thisMesg$write_1__VAL_2 = { mesgCount[7:0], wmi_sFlagReg[31:24], wmi_sFlagReg[15:0] } ; assign MUX_unrollCnt$write_1__VAL_1 = - (wmi_sFlagReg[23:0] == 24'd0) ? 16'd1 : b__h18410[15:0] ; + (wmi_sFlagReg[23:0] == 24'd0) ? 16'd1 : b__h17784[15:0] ; assign MUX_unrollCnt$write_1__VAL_2 = unrollCnt - 16'd1 ; assign MUX_wci_wslv_illegalEdge$write_1__VAL_1 = wci_wslv_reqF$D_OUT[36:34] != 3'd4 && wci_wslv_reqF$D_OUT[36:34] != 3'd5 && wci_wslv_reqF$D_OUT[36:34] != 3'd6 ; - assign MUX_wci_wslv_respF_c_r$write_1__VAL_1 = wci_wslv_respF_c_r + 2'd1 ; - assign MUX_wci_wslv_respF_c_r$write_1__VAL_2 = wci_wslv_respF_c_r - 2'd1 ; + assign MUX_wci_wslv_respF_cntr_r$write_1__VAL_2 = + wci_wslv_respF_cntr_r + 2'd1 ; assign MUX_wci_wslv_respF_q_0$write_1__VAL_1 = - (wci_wslv_respF_c_r == 2'd1) ? + (wci_wslv_respF_cntr_r == 2'd1) ? MUX_wci_wslv_respF_q_0$write_1__VAL_2 : wci_wslv_respF_q_1 ; always@(WILL_FIRE_RL_wci_wslv_ctl_op_complete or @@ -1597,34 +1610,33 @@ module mkSMAdapter32B(wciS0_Clk, endcase end assign MUX_wci_wslv_respF_q_1$write_1__VAL_1 = - (wci_wslv_respF_c_r == 2'd2) ? + (wci_wslv_respF_cntr_r == 2'd2) ? MUX_wci_wslv_respF_q_0$write_1__VAL_2 : 34'h0AAAAAAAA ; assign MUX_wci_wslv_respF_x_wire$wset_1__VAL_1 = wci_wslv_illegalEdge ? 34'h3C0DE4202 : 34'h1C0DE4201 ; - assign MUX_wci_wslv_respF_x_wire$wset_1__VAL_2 = { 2'd1, g_data__h25524 } ; - assign MUX_wmi_dhF_c_r$write_1__VAL_1 = wmi_dhF_c_r + 2'd1 ; - assign MUX_wmi_dhF_c_r$write_1__VAL_2 = wmi_dhF_c_r - 2'd1 ; + assign MUX_wci_wslv_respF_x_wire$wset_1__VAL_2 = { 2'd1, g_data__h24896 } ; + assign MUX_wmi_dhF_cntr_r$write_1__VAL_2 = wmi_dhF_cntr_r + 2'd1 ; assign MUX_wmi_dhF_q_0$write_1__VAL_1 = - (wmi_dhF_c_r == 2'd1) ? - MUX_wmi_dhF_q_0$write_1__VAL_2 : - wmi_dhF_q_1 ; - assign MUX_wmi_dhF_q_0$write_1__VAL_2 = { 1'd1, wsiS_reqFifo$D_OUT[309], wsiS_reqFifo$D_OUT[295:8] } ; - assign MUX_wmi_dhF_q_1$write_1__VAL_1 = - (wmi_dhF_c_r == 2'd2) ? MUX_wmi_dhF_q_0$write_1__VAL_2 : 290'd0 ; - assign MUX_wmi_mFlagF_c_r$write_1__VAL_1 = wmi_mFlagF_c_r + 2'd1 ; - assign MUX_wmi_mFlagF_c_r$write_1__VAL_2 = wmi_mFlagF_c_r - 2'd1 ; + assign MUX_wmi_dhF_q_0$write_1__VAL_2 = + (wmi_dhF_cntr_r == 2'd1) ? + MUX_wmi_dhF_q_0$write_1__VAL_1 : + wmi_dhF_q_1 ; + assign MUX_wmi_dhF_q_1$write_1__VAL_2 = + (wmi_dhF_cntr_r == 2'd2) ? + MUX_wmi_dhF_q_0$write_1__VAL_1 : + 290'd0 ; + assign MUX_wmi_mFlagF_cntr_r$write_1__VAL_2 = wmi_mFlagF_cntr_r + 2'd1 ; assign MUX_wmi_mFlagF_q_0$write_1__VAL_1 = - (wmi_mFlagF_c_r == 2'd1) ? value__h6702 : wmi_mFlagF_q_1 ; + (wmi_mFlagF_cntr_r == 2'd1) ? value__h6387 : wmi_mFlagF_q_1 ; assign MUX_wmi_mFlagF_q_1$write_1__VAL_1 = - (wmi_mFlagF_c_r == 2'd2) ? value__h6702 : 32'd0 ; + (wmi_mFlagF_cntr_r == 2'd2) ? value__h6387 : 32'd0 ; assign MUX_wmi_mFlagF_x_wire$wset_1__VAL_2 = - { mesgMetaF_opcode__h22998, mesgMetaF_length__h22999 } ; - assign MUX_wmi_reqF_c_r$write_1__VAL_1 = wmi_reqF_c_r + 2'd1 ; - assign MUX_wmi_reqF_c_r$write_1__VAL_2 = wmi_reqF_c_r - 2'd1 ; + { mesgMetaF_opcode__h22372, mesgMetaF_length__h22373 } ; + assign MUX_wmi_reqF_cntr_r$write_1__VAL_2 = wmi_reqF_cntr_r + 2'd1 ; assign MUX_wmi_reqF_q_0$write_1__VAL_1 = - (wmi_reqF_c_r == 2'd1) ? + (wmi_reqF_cntr_r == 2'd1) ? MUX_wmi_reqF_q_0$write_1__VAL_2 : wmi_reqF_q_1 ; assign MUX_wmi_reqF_q_0$write_1__VAL_2 = @@ -1632,27 +1644,27 @@ module mkSMAdapter32B(wciS0_Clk, MUX_wmi_reqF_x_wire$wset_1__VAL_1 : MUX_wmi_reqF_x_wire$wset_1__VAL_2 ; assign MUX_wmi_reqF_q_1$write_1__VAL_1 = - (wmi_reqF_c_r == 2'd2) ? + (wmi_reqF_cntr_r == 2'd2) ? MUX_wmi_reqF_q_0$write_1__VAL_2 : 32'd0 ; assign MUX_wmi_reqF_x_wire$wset_1__VAL_1 = - { 4'd5, x__h18954, 1'b0, mesgReqAddr, fabWordsCurReq[11:0] } ; + { 4'd5, x__h18328, 1'b0, mesgReqAddr, fabWordsCurReq[11:0] } ; assign MUX_wmi_reqF_x_wire$wset_1__VAL_2 = { 4'd3, wsiS_reqFifo$D_OUT[309], 1'b0, mesgLengthSoFar, 12'd1 } ; - assign MUX_wsiM_reqFifo_c_r$write_1__VAL_1 = wsiM_reqFifo_c_r + 2'd1 ; - assign MUX_wsiM_reqFifo_c_r$write_1__VAL_2 = wsiM_reqFifo_c_r - 2'd1 ; + assign MUX_wsiM_reqFifo_cntr_r$write_1__VAL_1 = wsiM_reqFifo_cntr_r - 2'd1 ; + assign MUX_wsiM_reqFifo_cntr_r$write_1__VAL_2 = wsiM_reqFifo_cntr_r + 2'd1 ; assign MUX_wsiM_reqFifo_q_0$write_1__VAL_1 = - (wsiM_reqFifo_c_r == 2'd1) ? - MUX_wsiM_reqFifo_q_0$write_1__VAL_2 : - wsiM_reqFifo_q_1 ; - assign MUX_wsiM_reqFifo_q_0$write_1__VAL_2 = (MUX_wsiM_reqFifo_x_wire$wset_1__SEL_1 || MUX_wsiM_reqFifo_x_wire$wset_1__SEL_2) ? wsiS_reqFifo$D_OUT : MUX_wsiM_reqFifo_x_wire$wset_1__VAL_3 ; - assign MUX_wsiM_reqFifo_q_1$write_1__VAL_1 = - (wsiM_reqFifo_c_r == 2'd2) ? - MUX_wsiM_reqFifo_q_0$write_1__VAL_2 : + assign MUX_wsiM_reqFifo_q_0$write_1__VAL_2 = + (wsiM_reqFifo_cntr_r == 2'd1) ? + MUX_wsiM_reqFifo_q_0$write_1__VAL_1 : + wsiM_reqFifo_q_1 ; + assign MUX_wsiM_reqFifo_q_1$write_1__VAL_2 = + (wsiM_reqFifo_cntr_r == 2'd2) ? + MUX_wsiM_reqFifo_q_0$write_1__VAL_1 : 313'h00000AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA00 ; assign MUX_wsiM_reqFifo_x_wire$wset_1__VAL_3 = (respF_rCache[325] && respF_rCache[324:313] == respF_rRdPtr) ? @@ -1693,9 +1705,9 @@ module mkSMAdapter32B(wciS0_Clk, assign wmi_reqF_x_wire$whas = WILL_FIRE_RL_wmrd_mesgBodyRequest || MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 ; - assign wmi_mFlagF_x_wire$wget = value__h6702 ; + assign wmi_mFlagF_x_wire$wget = value__h6387 ; assign wmi_mFlagF_x_wire$whas = wmi_mFlagF_enqueueing$whas ; - assign wmi_dhF_x_wire$wget = MUX_wmi_dhF_q_0$write_1__VAL_2 ; + assign wmi_dhF_x_wire$wget = MUX_wmi_dhF_q_0$write_1__VAL_1 ; assign wmi_dhF_x_wire$whas = MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 ; assign wmi_wmiResponse$wget = { wmiM0_SResp, wmiM0_SData } ; assign wmi_wmiResponse$whas = 1'd1 ; @@ -1707,7 +1719,7 @@ module mkSMAdapter32B(wciS0_Clk, assign wmi_operateD_1$whas = wci_wslv_cState == 3'd2 ; assign wmi_peerIsReady_1$wget = 1'd1 ; assign wmi_peerIsReady_1$whas = wmiM0_SReset_n ; - assign wsiM_reqFifo_x_wire$wget = MUX_wsiM_reqFifo_q_0$write_1__VAL_2 ; + assign wsiM_reqFifo_x_wire$wget = MUX_wsiM_reqFifo_q_0$write_1__VAL_1 ; assign wsiM_reqFifo_x_wire$whas = wsiM_reqFifo_enqueueing$whas ; assign wsiM_operateD_1$wget = 1'd1 ; assign wsiM_operateD_1$whas = wci_wslv_cState == 3'd2 ; @@ -1729,7 +1741,7 @@ module mkSMAdapter32B(wciS0_Clk, assign wsiS_sThreadBusy_dw$wget = wsiS_reqFifo_countReg > 2'd1 ; assign wsiS_sThreadBusy_dw$whas = wsiS_reqFifo_levelsValid && wsiS_operateD && wsiS_peerIsReady ; - assign fabRespCredit_acc_v1$wget = b__h15473 ; + assign fabRespCredit_acc_v1$wget = b__h14802 ; assign fabRespCredit_acc_v1$whas = WILL_FIRE_RL_wmrd_mesgBodyRequest ; assign fabRespCredit_acc_v2$wget = 12'd1 ; assign fabRespCredit_acc_v2$whas = WILL_FIRE_RL_wmrd_mesgResptoWsi ; @@ -1739,9 +1751,9 @@ module mkSMAdapter32B(wciS0_Clk, { 3'd1, unrollCnt == 16'd1, !smaCtrl[5], - sendData_burstLength__h19243, + sendData_burstLength__h18617, wmi_respF$D_OUT[255:0], - sendData_byteEn__h19245, + sendData_byteEn__h18619, thisMesg[23:16] } ; assign respF_wDataIn$whas = respF_pwEnqueue$whas ; assign respF_wDataOut$wget = MUX_wsiM_reqFifo_x_wire$wset_1__VAL_3 ; @@ -1768,7 +1780,7 @@ module mkSMAdapter32B(wciS0_Clk, assign wci_wslv_respF_enqueueing$whas = WILL_FIRE_RL_wci_cfrd || WILL_FIRE_RL_wci_cfwr || WILL_FIRE_RL_wci_wslv_ctl_op_complete ; - assign wci_wslv_respF_dequeueing$whas = wci_wslv_respF_c_r != 2'd0 ; + assign wci_wslv_respF_dequeueing$whas = wci_wslv_respF_cntr_r != 2'd0 ; assign wci_wslv_sThreadBusy_pw$whas = 1'b0 ; assign wci_wslv_wci_cfwr_pw$whas = wci_wslv_reqF$EMPTY_N && wci_wslv_reqF$D_OUT[68] && @@ -1783,23 +1795,23 @@ module mkSMAdapter32B(wciS0_Clk, MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 || WILL_FIRE_RL_wmrd_mesgBodyRequest ; assign wmi_reqF_dequeueing$whas = - WILL_FIRE_RL_wmi_reqF_deq && wmi_reqF_c_r != 2'd0 ; + WILL_FIRE_RL_wmi_reqF_deq && wmi_reqF_cntr_r != 2'd0 ; assign wmi_mFlagF_enqueueing$whas = - WILL_FIRE_RL_wmrd_mesgBodyRequest && x__h18954 || + WILL_FIRE_RL_wmrd_mesgBodyRequest && x__h18328 || MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 && wsiS_reqFifo$D_OUT[309] ; assign wmi_mFlagF_dequeueing$whas = WILL_FIRE_RL_wmi_reqF_deq && wmi_reqF_q_0[27] && - wmi_mFlagF_c_r != 2'd0 ; + wmi_mFlagF_cntr_r != 2'd0 ; assign wmi_dhF_enqueueing$whas = MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 ; assign wmi_dhF_dequeueing$whas = wmi_operateD && wmi_peerIsReady && !wmi_sDataThreadBusy_d && - wmi_dhF_c_r != 2'd0 ; + wmi_dhF_cntr_r != 2'd0 ; assign wsiM_reqFifo_enqueueing$whas = + WILL_FIRE_RL_wsipass_doMessagePush && !smaCtrl[4] || MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 && smaCtrl[3:0] == 4'h3 || - WILL_FIRE_RL_wsipass_doMessagePush && !smaCtrl[4] || WILL_FIRE_RL_wmrd_mesgResptoWsi ; assign wsiM_reqFifo_dequeueing$whas = WILL_FIRE_RL_wsiM_reqFifo_deq ; assign wsiM_sThreadBusy_pw$whas = wsiM0_SThreadBusy ; @@ -1813,6 +1825,7 @@ module mkSMAdapter32B(wciS0_Clk, assign wsiS_reqFifo_doResetClr$whas = 1'b0 ; assign respF_pwDequeue$whas = WILL_FIRE_RL_wmrd_mesgResptoWsi ; assign respF_pwEnqueue$whas = MUX_unrollCnt$write_1__SEL_2 && !smaCtrl[4] ; + assign respF_pwClear$whas = 1'b0 ; assign wsi_Es_mReqLast_w$whas = wsiS0_MReqLast ; assign wsi_Es_mBurstPrecise_w$whas = wsiS0_MBurstPrecise ; assign wsi_Es_mDataInfo_w$whas = 1'd1 ; @@ -1853,7 +1866,7 @@ module mkSMAdapter32B(wciS0_Clk, // register fabWordsCurReq assign fabWordsCurReq$D_IN = - (fabWordsRemain <= b__h18783) ? fabWordsRemain : b__h18783 ; + (fabWordsRemain <= b__h18157) ? fabWordsRemain : b__h18157 ; assign fabWordsCurReq$EN = MUX_mesgReqOK$write_1__SEL_3 ; // register fabWordsRemain @@ -1959,18 +1972,18 @@ module mkSMAdapter32B(wciS0_Clk, assign respF_rCache$D_IN = { 1'd1, respF_rWrPtr, - IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d966, + IF_respF_wDataIn_whas__28_THEN_respF_wDataIn_w_ETC___d431, respF_pwEnqueue$whas && respF_wDataIn$wget[309], respF_pwEnqueue$whas && respF_wDataIn$wget[308], - IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d968 } ; + IF_respF_wDataIn_whas__28_THEN_respF_wDataIn_w_ETC___d437 } ; assign respF_rCache$EN = respF_pwEnqueue$whas ; // register respF_rRdPtr - assign respF_rRdPtr$D_IN = x__h16878 ; + assign respF_rRdPtr$D_IN = x__h16253 ; assign respF_rRdPtr$EN = WILL_FIRE_RL_wmrd_mesgResptoWsi ; // register respF_rWrPtr - assign respF_rWrPtr$D_IN = respF_rWrPtr + 12'd1 ; + assign respF_rWrPtr$D_IN = x__h16103 ; assign respF_rWrPtr$EN = respF_pwEnqueue$whas ; // register smaCtrl @@ -2074,24 +2087,24 @@ module mkSMAdapter32B(wciS0_Clk, (wci_wslv_wciReq$wget[71:69] != 3'd0) != wci_wslv_reqF_r_deq$whas ; - // register wci_wslv_respF_c_r - assign wci_wslv_respF_c_r$D_IN = - WILL_FIRE_RL_wci_wslv_respF_incCtr ? - MUX_wci_wslv_respF_c_r$write_1__VAL_1 : - MUX_wci_wslv_respF_c_r$write_1__VAL_2 ; - assign wci_wslv_respF_c_r$EN = - WILL_FIRE_RL_wci_wslv_respF_incCtr || - WILL_FIRE_RL_wci_wslv_respF_decCtr ; + // register wci_wslv_respF_cntr_r + assign wci_wslv_respF_cntr_r$D_IN = + WILL_FIRE_RL_wci_wslv_respF_decCtr ? + wci_wslv_respF_cntr_r_8_MINUS_1___d27 : + MUX_wci_wslv_respF_cntr_r$write_1__VAL_2 ; + assign wci_wslv_respF_cntr_r$EN = + WILL_FIRE_RL_wci_wslv_respF_decCtr || + WILL_FIRE_RL_wci_wslv_respF_incCtr ; // register wci_wslv_respF_q_0 - always@(WILL_FIRE_RL_wci_wslv_respF_both or + always@(MUX_wci_wslv_respF_q_0$write_1__SEL_1 or MUX_wci_wslv_respF_q_0$write_1__VAL_1 or MUX_wci_wslv_respF_q_0$write_1__SEL_2 or MUX_wci_wslv_respF_q_0$write_1__VAL_2 or WILL_FIRE_RL_wci_wslv_respF_decCtr or wci_wslv_respF_q_1) begin case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_wci_wslv_respF_both: + MUX_wci_wslv_respF_q_0$write_1__SEL_1: wci_wslv_respF_q_0$D_IN = MUX_wci_wslv_respF_q_0$write_1__VAL_1; MUX_wci_wslv_respF_q_0$write_1__SEL_2: wci_wslv_respF_q_0$D_IN = MUX_wci_wslv_respF_q_0$write_1__VAL_2; @@ -2102,20 +2115,20 @@ module mkSMAdapter32B(wciS0_Clk, endcase end assign wci_wslv_respF_q_0$EN = - WILL_FIRE_RL_wci_wslv_respF_both || + WILL_FIRE_RL_wci_wslv_respF_both && _dfoo3 || WILL_FIRE_RL_wci_wslv_respF_incCtr && - wci_wslv_respF_c_r == 2'd0 || + wci_wslv_respF_cntr_r == 2'd0 || WILL_FIRE_RL_wci_wslv_respF_decCtr ; // register wci_wslv_respF_q_1 - always@(WILL_FIRE_RL_wci_wslv_respF_both or + always@(MUX_wci_wslv_respF_q_1$write_1__SEL_1 or MUX_wci_wslv_respF_q_1$write_1__VAL_1 or MUX_wci_wslv_respF_q_1$write_1__SEL_2 or MUX_wci_wslv_respF_q_0$write_1__VAL_2 or WILL_FIRE_RL_wci_wslv_respF_decCtr) begin case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_wci_wslv_respF_both: + MUX_wci_wslv_respF_q_1$write_1__SEL_1: wci_wslv_respF_q_1$D_IN = MUX_wci_wslv_respF_q_1$write_1__VAL_1; MUX_wci_wslv_respF_q_1$write_1__SEL_2: wci_wslv_respF_q_1$D_IN = MUX_wci_wslv_respF_q_0$write_1__VAL_2; @@ -2126,9 +2139,9 @@ module mkSMAdapter32B(wciS0_Clk, endcase end assign wci_wslv_respF_q_1$EN = - WILL_FIRE_RL_wci_wslv_respF_both || + WILL_FIRE_RL_wci_wslv_respF_both && _dfoo1 || WILL_FIRE_RL_wci_wslv_respF_incCtr && - wci_wslv_respF_c_r == 2'd1 || + wci_wslv_respF_cntr_r == 2'd1 || WILL_FIRE_RL_wci_wslv_respF_decCtr ; // register wci_wslv_sFlagReg @@ -2143,23 +2156,23 @@ module mkSMAdapter32B(wciS0_Clk, assign wmi_busyWithMessage$D_IN = 1'b0 ; assign wmi_busyWithMessage$EN = 1'b0 ; - // register wmi_dhF_c_r - assign wmi_dhF_c_r$D_IN = - WILL_FIRE_RL_wmi_dhF_incCtr ? - MUX_wmi_dhF_c_r$write_1__VAL_1 : - MUX_wmi_dhF_c_r$write_1__VAL_2 ; - assign wmi_dhF_c_r$EN = - WILL_FIRE_RL_wmi_dhF_incCtr || WILL_FIRE_RL_wmi_dhF_decCtr ; + // register wmi_dhF_cntr_r + assign wmi_dhF_cntr_r$D_IN = + WILL_FIRE_RL_wmi_dhF_decCtr ? + wmi_dhF_cntr_r_05_MINUS_1___d213 : + MUX_wmi_dhF_cntr_r$write_1__VAL_2 ; + assign wmi_dhF_cntr_r$EN = + WILL_FIRE_RL_wmi_dhF_decCtr || WILL_FIRE_RL_wmi_dhF_incCtr ; // register wmi_dhF_q_0 - always@(WILL_FIRE_RL_wmi_dhF_both or + always@(MUX_wmi_dhF_q_0$write_1__SEL_1 or MUX_wmi_dhF_q_0$write_1__VAL_1 or MUX_wmi_dhF_q_0$write_1__SEL_2 or MUX_wmi_dhF_q_0$write_1__VAL_2 or WILL_FIRE_RL_wmi_dhF_decCtr or wmi_dhF_q_1) begin case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_wmi_dhF_both: + MUX_wmi_dhF_q_0$write_1__SEL_1: wmi_dhF_q_0$D_IN = MUX_wmi_dhF_q_0$write_1__VAL_1; MUX_wmi_dhF_q_0$write_1__SEL_2: wmi_dhF_q_0$D_IN = MUX_wmi_dhF_q_0$write_1__VAL_2; @@ -2169,29 +2182,29 @@ module mkSMAdapter32B(wciS0_Clk, endcase end assign wmi_dhF_q_0$EN = - WILL_FIRE_RL_wmi_dhF_both || - WILL_FIRE_RL_wmi_dhF_incCtr && wmi_dhF_c_r == 2'd0 || + WILL_FIRE_RL_wmi_dhF_incCtr && wmi_dhF_cntr_r == 2'd0 || + WILL_FIRE_RL_wmi_dhF_both && _dfoo15 || WILL_FIRE_RL_wmi_dhF_decCtr ; // register wmi_dhF_q_1 - always@(WILL_FIRE_RL_wmi_dhF_both or - MUX_wmi_dhF_q_1$write_1__VAL_1 or + always@(MUX_wmi_dhF_q_1$write_1__SEL_1 or + MUX_wmi_dhF_q_0$write_1__VAL_1 or MUX_wmi_dhF_q_1$write_1__SEL_2 or - MUX_wmi_dhF_q_0$write_1__VAL_2 or WILL_FIRE_RL_wmi_dhF_decCtr) + MUX_wmi_dhF_q_1$write_1__VAL_2 or WILL_FIRE_RL_wmi_dhF_decCtr) begin case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_wmi_dhF_both: - wmi_dhF_q_1$D_IN = MUX_wmi_dhF_q_1$write_1__VAL_1; + MUX_wmi_dhF_q_1$write_1__SEL_1: + wmi_dhF_q_1$D_IN = MUX_wmi_dhF_q_0$write_1__VAL_1; MUX_wmi_dhF_q_1$write_1__SEL_2: - wmi_dhF_q_1$D_IN = MUX_wmi_dhF_q_0$write_1__VAL_2; + wmi_dhF_q_1$D_IN = MUX_wmi_dhF_q_1$write_1__VAL_2; WILL_FIRE_RL_wmi_dhF_decCtr: wmi_dhF_q_1$D_IN = 290'd0; default: wmi_dhF_q_1$D_IN = 290'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ; endcase end assign wmi_dhF_q_1$EN = - WILL_FIRE_RL_wmi_dhF_both || - WILL_FIRE_RL_wmi_dhF_incCtr && wmi_dhF_c_r == 2'd1 || + WILL_FIRE_RL_wmi_dhF_incCtr && wmi_dhF_cntr_r == 2'd1 || + WILL_FIRE_RL_wmi_dhF_both && _dfoo13 || WILL_FIRE_RL_wmi_dhF_decCtr ; // register wmi_errorSticky @@ -2202,51 +2215,51 @@ module mkSMAdapter32B(wciS0_Clk, assign wmi_isReset_isInReset$D_IN = 1'd0 ; assign wmi_isReset_isInReset$EN = wmi_isReset_isInReset ; - // register wmi_mFlagF_c_r - assign wmi_mFlagF_c_r$D_IN = - WILL_FIRE_RL_wmi_mFlagF_incCtr ? - MUX_wmi_mFlagF_c_r$write_1__VAL_1 : - MUX_wmi_mFlagF_c_r$write_1__VAL_2 ; - assign wmi_mFlagF_c_r$EN = - WILL_FIRE_RL_wmi_mFlagF_incCtr || - WILL_FIRE_RL_wmi_mFlagF_decCtr ; + // register wmi_mFlagF_cntr_r + assign wmi_mFlagF_cntr_r$D_IN = + WILL_FIRE_RL_wmi_mFlagF_decCtr ? + wmi_mFlagF_cntr_r_83_MINUS_1___d191 : + MUX_wmi_mFlagF_cntr_r$write_1__VAL_2 ; + assign wmi_mFlagF_cntr_r$EN = + WILL_FIRE_RL_wmi_mFlagF_decCtr || + WILL_FIRE_RL_wmi_mFlagF_incCtr ; // register wmi_mFlagF_q_0 - always@(WILL_FIRE_RL_wmi_mFlagF_both or + always@(MUX_wmi_mFlagF_q_0$write_1__SEL_1 or MUX_wmi_mFlagF_q_0$write_1__VAL_1 or MUX_wmi_mFlagF_q_0$write_1__SEL_2 or - value__h6702 or WILL_FIRE_RL_wmi_mFlagF_decCtr or wmi_mFlagF_q_1) + value__h6387 or WILL_FIRE_RL_wmi_mFlagF_decCtr or wmi_mFlagF_q_1) begin case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_wmi_mFlagF_both: + MUX_wmi_mFlagF_q_0$write_1__SEL_1: wmi_mFlagF_q_0$D_IN = MUX_wmi_mFlagF_q_0$write_1__VAL_1; - MUX_wmi_mFlagF_q_0$write_1__SEL_2: wmi_mFlagF_q_0$D_IN = value__h6702; + MUX_wmi_mFlagF_q_0$write_1__SEL_2: wmi_mFlagF_q_0$D_IN = value__h6387; WILL_FIRE_RL_wmi_mFlagF_decCtr: wmi_mFlagF_q_0$D_IN = wmi_mFlagF_q_1; default: wmi_mFlagF_q_0$D_IN = 32'hAAAAAAAA /* unspecified value */ ; endcase end assign wmi_mFlagF_q_0$EN = - WILL_FIRE_RL_wmi_mFlagF_both || - WILL_FIRE_RL_wmi_mFlagF_incCtr && wmi_mFlagF_c_r == 2'd0 || + WILL_FIRE_RL_wmi_mFlagF_both && _dfoo11 || + WILL_FIRE_RL_wmi_mFlagF_incCtr && wmi_mFlagF_cntr_r == 2'd0 || WILL_FIRE_RL_wmi_mFlagF_decCtr ; // register wmi_mFlagF_q_1 - always@(WILL_FIRE_RL_wmi_mFlagF_both or + always@(MUX_wmi_mFlagF_q_1$write_1__SEL_1 or MUX_wmi_mFlagF_q_1$write_1__VAL_1 or MUX_wmi_mFlagF_q_1$write_1__SEL_2 or - value__h6702 or WILL_FIRE_RL_wmi_mFlagF_decCtr) + value__h6387 or WILL_FIRE_RL_wmi_mFlagF_decCtr) begin case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_wmi_mFlagF_both: + MUX_wmi_mFlagF_q_1$write_1__SEL_1: wmi_mFlagF_q_1$D_IN = MUX_wmi_mFlagF_q_1$write_1__VAL_1; - MUX_wmi_mFlagF_q_1$write_1__SEL_2: wmi_mFlagF_q_1$D_IN = value__h6702; + MUX_wmi_mFlagF_q_1$write_1__SEL_2: wmi_mFlagF_q_1$D_IN = value__h6387; WILL_FIRE_RL_wmi_mFlagF_decCtr: wmi_mFlagF_q_1$D_IN = 32'd0; default: wmi_mFlagF_q_1$D_IN = 32'hAAAAAAAA /* unspecified value */ ; endcase end assign wmi_mFlagF_q_1$EN = - WILL_FIRE_RL_wmi_mFlagF_both || - WILL_FIRE_RL_wmi_mFlagF_incCtr && wmi_mFlagF_c_r == 2'd1 || + WILL_FIRE_RL_wmi_mFlagF_both && _dfoo9 || + WILL_FIRE_RL_wmi_mFlagF_incCtr && wmi_mFlagF_cntr_r == 2'd1 || WILL_FIRE_RL_wmi_mFlagF_decCtr ; // register wmi_operateD @@ -2257,23 +2270,23 @@ module mkSMAdapter32B(wciS0_Clk, assign wmi_peerIsReady$D_IN = wmiM0_SReset_n ; assign wmi_peerIsReady$EN = 1'd1 ; - // register wmi_reqF_c_r - assign wmi_reqF_c_r$D_IN = - WILL_FIRE_RL_wmi_reqF_incCtr ? - MUX_wmi_reqF_c_r$write_1__VAL_1 : - MUX_wmi_reqF_c_r$write_1__VAL_2 ; - assign wmi_reqF_c_r$EN = - WILL_FIRE_RL_wmi_reqF_incCtr || WILL_FIRE_RL_wmi_reqF_decCtr ; + // register wmi_reqF_cntr_r + assign wmi_reqF_cntr_r$D_IN = + WILL_FIRE_RL_wmi_reqF_decCtr ? + wmi_reqF_cntr_r_61_MINUS_1___d169 : + MUX_wmi_reqF_cntr_r$write_1__VAL_2 ; + assign wmi_reqF_cntr_r$EN = + WILL_FIRE_RL_wmi_reqF_decCtr || WILL_FIRE_RL_wmi_reqF_incCtr ; // register wmi_reqF_q_0 - always@(WILL_FIRE_RL_wmi_reqF_both or + always@(MUX_wmi_reqF_q_0$write_1__SEL_1 or MUX_wmi_reqF_q_0$write_1__VAL_1 or MUX_wmi_reqF_q_0$write_1__SEL_2 or MUX_wmi_reqF_q_0$write_1__VAL_2 or WILL_FIRE_RL_wmi_reqF_decCtr or wmi_reqF_q_1) begin case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_wmi_reqF_both: + MUX_wmi_reqF_q_0$write_1__SEL_1: wmi_reqF_q_0$D_IN = MUX_wmi_reqF_q_0$write_1__VAL_1; MUX_wmi_reqF_q_0$write_1__SEL_2: wmi_reqF_q_0$D_IN = MUX_wmi_reqF_q_0$write_1__VAL_2; @@ -2282,18 +2295,18 @@ module mkSMAdapter32B(wciS0_Clk, endcase end assign wmi_reqF_q_0$EN = - WILL_FIRE_RL_wmi_reqF_both || - WILL_FIRE_RL_wmi_reqF_incCtr && wmi_reqF_c_r == 2'd0 || + WILL_FIRE_RL_wmi_reqF_both && _dfoo7 || + WILL_FIRE_RL_wmi_reqF_incCtr && wmi_reqF_cntr_r == 2'd0 || WILL_FIRE_RL_wmi_reqF_decCtr ; // register wmi_reqF_q_1 - always@(WILL_FIRE_RL_wmi_reqF_both or + always@(MUX_wmi_reqF_q_1$write_1__SEL_1 or MUX_wmi_reqF_q_1$write_1__VAL_1 or MUX_wmi_reqF_q_1$write_1__SEL_2 or MUX_wmi_reqF_q_0$write_1__VAL_2 or WILL_FIRE_RL_wmi_reqF_decCtr) begin case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_wmi_reqF_both: + MUX_wmi_reqF_q_1$write_1__SEL_1: wmi_reqF_q_1$D_IN = MUX_wmi_reqF_q_1$write_1__VAL_1; MUX_wmi_reqF_q_1$write_1__SEL_2: wmi_reqF_q_1$D_IN = MUX_wmi_reqF_q_0$write_1__VAL_2; @@ -2302,8 +2315,8 @@ module mkSMAdapter32B(wciS0_Clk, endcase end assign wmi_reqF_q_1$EN = - WILL_FIRE_RL_wmi_reqF_both || - WILL_FIRE_RL_wmi_reqF_incCtr && wmi_reqF_c_r == 2'd1 || + WILL_FIRE_RL_wmi_reqF_both && _dfoo5 || + WILL_FIRE_RL_wmi_reqF_incCtr && wmi_reqF_cntr_r == 2'd1 || WILL_FIRE_RL_wmi_reqF_decCtr ; // register wmi_sDataThreadBusy_d @@ -2382,24 +2395,24 @@ module mkSMAdapter32B(wciS0_Clk, assign wsiM_peerIsReady$D_IN = wsiM0_SReset_n ; assign wsiM_peerIsReady$EN = 1'd1 ; - // register wsiM_reqFifo_c_r - assign wsiM_reqFifo_c_r$D_IN = - WILL_FIRE_RL_wsiM_reqFifo_incCtr ? - MUX_wsiM_reqFifo_c_r$write_1__VAL_1 : - MUX_wsiM_reqFifo_c_r$write_1__VAL_2 ; - assign wsiM_reqFifo_c_r$EN = - WILL_FIRE_RL_wsiM_reqFifo_incCtr || - WILL_FIRE_RL_wsiM_reqFifo_decCtr ; + // register wsiM_reqFifo_cntr_r + assign wsiM_reqFifo_cntr_r$D_IN = + WILL_FIRE_RL_wsiM_reqFifo_decCtr ? + MUX_wsiM_reqFifo_cntr_r$write_1__VAL_1 : + MUX_wsiM_reqFifo_cntr_r$write_1__VAL_2 ; + assign wsiM_reqFifo_cntr_r$EN = + WILL_FIRE_RL_wsiM_reqFifo_decCtr || + WILL_FIRE_RL_wsiM_reqFifo_incCtr ; // register wsiM_reqFifo_q_0 - always@(WILL_FIRE_RL_wsiM_reqFifo_both or + always@(MUX_wsiM_reqFifo_q_0$write_1__SEL_1 or MUX_wsiM_reqFifo_q_0$write_1__VAL_1 or MUX_wsiM_reqFifo_q_0$write_1__SEL_2 or MUX_wsiM_reqFifo_q_0$write_1__VAL_2 or WILL_FIRE_RL_wsiM_reqFifo_decCtr or wsiM_reqFifo_q_1) begin case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_wsiM_reqFifo_both: + MUX_wsiM_reqFifo_q_0$write_1__SEL_1: wsiM_reqFifo_q_0$D_IN = MUX_wsiM_reqFifo_q_0$write_1__VAL_1; MUX_wsiM_reqFifo_q_0$write_1__SEL_2: wsiM_reqFifo_q_0$D_IN = MUX_wsiM_reqFifo_q_0$write_1__VAL_2; @@ -2410,22 +2423,23 @@ module mkSMAdapter32B(wciS0_Clk, endcase end assign wsiM_reqFifo_q_0$EN = - WILL_FIRE_RL_wsiM_reqFifo_both || - WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_c_r == 2'd0 || + WILL_FIRE_RL_wsiM_reqFifo_incCtr && + wsiM_reqFifo_cntr_r == 2'd0 || + WILL_FIRE_RL_wsiM_reqFifo_both && _dfoo19 || WILL_FIRE_RL_wsiM_reqFifo_decCtr ; // register wsiM_reqFifo_q_1 - always@(WILL_FIRE_RL_wsiM_reqFifo_both or - MUX_wsiM_reqFifo_q_1$write_1__VAL_1 or + always@(MUX_wsiM_reqFifo_q_1$write_1__SEL_1 or + MUX_wsiM_reqFifo_q_0$write_1__VAL_1 or MUX_wsiM_reqFifo_q_1$write_1__SEL_2 or - MUX_wsiM_reqFifo_q_0$write_1__VAL_2 or + MUX_wsiM_reqFifo_q_1$write_1__VAL_2 or WILL_FIRE_RL_wsiM_reqFifo_decCtr) begin case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_wsiM_reqFifo_both: - wsiM_reqFifo_q_1$D_IN = MUX_wsiM_reqFifo_q_1$write_1__VAL_1; + MUX_wsiM_reqFifo_q_1$write_1__SEL_1: + wsiM_reqFifo_q_1$D_IN = MUX_wsiM_reqFifo_q_0$write_1__VAL_1; MUX_wsiM_reqFifo_q_1$write_1__SEL_2: - wsiM_reqFifo_q_1$D_IN = MUX_wsiM_reqFifo_q_0$write_1__VAL_2; + wsiM_reqFifo_q_1$D_IN = MUX_wsiM_reqFifo_q_1$write_1__VAL_2; WILL_FIRE_RL_wsiM_reqFifo_decCtr: wsiM_reqFifo_q_1$D_IN = 313'h00000AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA00; @@ -2434,8 +2448,9 @@ module mkSMAdapter32B(wciS0_Clk, endcase end assign wsiM_reqFifo_q_1$EN = - WILL_FIRE_RL_wsiM_reqFifo_both || - WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_c_r == 2'd1 || + WILL_FIRE_RL_wsiM_reqFifo_incCtr && + wsiM_reqFifo_cntr_r == 2'd1 || + WILL_FIRE_RL_wsiM_reqFifo_both && _dfoo17 || WILL_FIRE_RL_wsiM_reqFifo_decCtr ; // register wsiM_sThreadBusy_d @@ -2561,19 +2576,19 @@ module mkSMAdapter32B(wciS0_Clk, assign respF_memory$ADDRA = respF_rWrPtr[10:0] ; assign respF_memory$ADDRB = WILL_FIRE_RL_wmrd_mesgResptoWsi ? - x__h16878[10:0] : + x__h16253[10:0] : respF_rRdPtr[10:0] ; assign respF_memory$DIA = - { IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d966, + { IF_respF_wDataIn_whas__28_THEN_respF_wDataIn_w_ETC___d431, respF_pwEnqueue$whas && respF_wDataIn$wget[309], respF_pwEnqueue$whas && respF_wDataIn$wget[308], - IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d968 } ; + IF_respF_wDataIn_whas__28_THEN_respF_wDataIn_w_ETC___d437 } ; assign respF_memory$DIB = 313'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ; assign respF_memory$WEA = respF_pwEnqueue$whas ; assign respF_memory$WEB = 1'd0 ; - assign respF_memory$ENA = 1'd1 ; - assign respF_memory$ENB = 1'd1 ; + assign respF_memory$ENA = 1'b1 ; + assign respF_memory$ENB = 1'b1 ; // submodule wci_wslv_reqF assign wci_wslv_reqF$D_IN = wci_wslv_wciReq$wget ; @@ -2596,50 +2611,80 @@ module mkSMAdapter32B(wciS0_Clk, assign wsiS_reqFifo$CLR = 1'b0 ; // remaining internal signals - assign IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d966 = + assign IF_respF_wDataIn_whas__28_THEN_respF_wDataIn_w_ETC___d431 = respF_pwEnqueue$whas ? respF_wDataIn$wget[312:310] : 3'd0 ; - assign IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d968 = + assign IF_respF_wDataIn_whas__28_THEN_respF_wDataIn_w_ETC___d437 = respF_pwEnqueue$whas ? respF_wDataIn$wget[307:0] : 308'd0 ; - assign NOT_wmi_reqF_c_r_57_EQ_2_75_76_AND_wmi_operate_ETC___d524 = - wmi_reqF_c_r != 2'd2 && wmi_operateD && wmi_peerIsReady && - (!x__h18954 || wmi_mFlagF_c_r != 2'd2) ; - assign b__h15473 = -fabWordsCurReq[11:0] ; - assign b__h18410 = x__h18530 + residue__h18273 ; - assign b__h18783 = { {2{fabRespCredit_value[11]}}, fabRespCredit_value } ; - assign mesgMetaF_length__h22999 = + assign NOT_wmi_reqF_cntr_r_61_EQ_2_73_74_AND_wmi_oper_ETC___d521 = + wmi_reqF_cntr_r != 2'd2 && wmi_operateD && wmi_peerIsReady && + (!x__h18328 || wmi_mFlagF_cntr_r != 2'd2) ; + assign _dfoo1 = + wci_wslv_respF_cntr_r != 2'd2 || + wci_wslv_respF_cntr_r_8_MINUS_1___d27 == 2'd1 ; + assign _dfoo11 = + wmi_mFlagF_cntr_r != 2'd1 || + wmi_mFlagF_cntr_r_83_MINUS_1___d191 == 2'd0 ; + assign _dfoo13 = + wmi_dhF_cntr_r != 2'd2 || + wmi_dhF_cntr_r_05_MINUS_1___d213 == 2'd1 ; + assign _dfoo15 = + wmi_dhF_cntr_r != 2'd1 || + wmi_dhF_cntr_r_05_MINUS_1___d213 == 2'd0 ; + assign _dfoo17 = + wsiM_reqFifo_cntr_r != 2'd2 || + MUX_wsiM_reqFifo_cntr_r$write_1__VAL_1 == 2'd1 ; + assign _dfoo19 = + wsiM_reqFifo_cntr_r != 2'd1 || + MUX_wsiM_reqFifo_cntr_r$write_1__VAL_1 == 2'd0 ; + assign _dfoo3 = + wci_wslv_respF_cntr_r != 2'd1 || + wci_wslv_respF_cntr_r_8_MINUS_1___d27 == 2'd0 ; + assign _dfoo5 = + wmi_reqF_cntr_r != 2'd2 || + wmi_reqF_cntr_r_61_MINUS_1___d169 == 2'd1 ; + assign _dfoo7 = + wmi_reqF_cntr_r != 2'd1 || + wmi_reqF_cntr_r_61_MINUS_1___d169 == 2'd0 ; + assign _dfoo9 = + wmi_mFlagF_cntr_r != 2'd2 || + wmi_mFlagF_cntr_r_83_MINUS_1___d191 == 2'd1 ; + assign b__h14802 = -fabWordsCurReq[11:0] ; + assign b__h17784 = x__h17904 + residue__h17647 ; + assign b__h18157 = { {2{fabRespCredit_value[11]}}, fabRespCredit_value } ; + assign mesgMetaF_length__h22373 = (wsiS_reqFifo$D_OUT[309] && wsiS_reqFifo$D_OUT[39:8] == 32'd0 && mesgLengthSoFar == 14'd0) ? 24'd0 : - { 10'd0, mlB__h22832 } ; - assign mesgMetaF_opcode__h22998 = opcode[8] ? opcode[7:0] : 8'd0 ; - assign mlB__h22832 = MUX_mesgLengthSoFar$write_1__VAL_1 ; - assign mlInc__h22831 = + { 10'd0, mlB__h22206 } ; + assign mesgMetaF_opcode__h22372 = opcode[8] ? opcode[7:0] : 8'd0 ; + assign mlB__h22206 = MUX_mesgLengthSoFar$write_1__VAL_1 ; + assign mlInc__h22205 = wsiS_reqFifo$D_OUT[309] ? - { 8'd0, x__h23038 + y__h23039 } : + { 8'd0, x__h22411 + y__h22412 } : 14'd32 ; - assign rdat__h25567 = hasDebugLogic ? mesgCount : 32'd0 ; - assign rdat__h25573 = hasDebugLogic ? abortCount : 32'd0 ; - assign rdat__h25579 = hasDebugLogic ? thisMesg : 32'd0 ; - assign rdat__h25592 = hasDebugLogic ? lastMesg : 32'd0 ; - assign rdat__h25615 = hasDebugLogic ? { 16'd0, x__h25619 } : 32'd0 ; - assign rdat__h25715 = hasDebugLogic ? wsiS_extStatusW$wget[95:64] : 32'd0 ; - assign rdat__h25729 = hasDebugLogic ? wsiS_extStatusW$wget[63:32] : 32'd0 ; - assign rdat__h25737 = hasDebugLogic ? wsiS_extStatusW$wget[31:0] : 32'd0 ; - assign rdat__h25743 = hasDebugLogic ? wsiM_extStatusW$wget[95:64] : 32'd0 ; - assign rdat__h25757 = hasDebugLogic ? wsiM_extStatusW$wget[63:32] : 32'd0 ; - assign rdat__h25765 = hasDebugLogic ? wsiM_extStatusW$wget[31:0] : 32'd0 ; - assign rdat__h25771 = hasDebugLogic ? wmwtBeginCount : 32'd0 ; - assign rdat__h25777 = hasDebugLogic ? wmwtPushCount : 32'd0 ; - assign rdat__h25783 = hasDebugLogic ? wmwtFinalCount : 32'd0 ; - assign rdat__h25789 = hasDebugLogic ? { 31'd0, x__h25793 } : 32'd0 ; - assign rdat__h25799 = hasDebugLogic ? 32'hFEEDC0DE : 32'd0 ; - assign residue__h18273 = + assign rdat__h24939 = hasDebugLogic ? mesgCount : 32'd0 ; + assign rdat__h24945 = hasDebugLogic ? abortCount : 32'd0 ; + assign rdat__h24951 = hasDebugLogic ? thisMesg : 32'd0 ; + assign rdat__h24964 = hasDebugLogic ? lastMesg : 32'd0 ; + assign rdat__h24987 = hasDebugLogic ? { 16'd0, x__h24991 } : 32'd0 ; + assign rdat__h25087 = hasDebugLogic ? wsiS_extStatusW$wget[95:64] : 32'd0 ; + assign rdat__h25101 = hasDebugLogic ? wsiS_extStatusW$wget[63:32] : 32'd0 ; + assign rdat__h25109 = hasDebugLogic ? wsiS_extStatusW$wget[31:0] : 32'd0 ; + assign rdat__h25115 = hasDebugLogic ? wsiM_extStatusW$wget[95:64] : 32'd0 ; + assign rdat__h25129 = hasDebugLogic ? wsiM_extStatusW$wget[63:32] : 32'd0 ; + assign rdat__h25137 = hasDebugLogic ? wsiM_extStatusW$wget[31:0] : 32'd0 ; + assign rdat__h25143 = hasDebugLogic ? wmwtBeginCount : 32'd0 ; + assign rdat__h25149 = hasDebugLogic ? wmwtPushCount : 32'd0 ; + assign rdat__h25155 = hasDebugLogic ? wmwtFinalCount : 32'd0 ; + assign rdat__h25161 = hasDebugLogic ? { 31'd0, x__h25165 } : 32'd0 ; + assign rdat__h25171 = hasDebugLogic ? 32'hFEEDC0DE : 32'd0 ; + assign residue__h17647 = ({ 1'd0, wmi_sFlagReg[4:0] } == 6'd0) ? 24'd0 : 24'd1 ; - assign sendData_burstLength__h19243 = + assign sendData_burstLength__h18617 = (thisMesg[15:0] == 16'd0 || smaCtrl[5] && unrollCnt == 16'd1) ? 12'd1 : - (smaCtrl[5] ? 12'd4095 : wsiBurstLength__h19161[11:0]) ; - assign sendData_byteEn__h19245 = + (smaCtrl[5] ? 12'd4095 : wsiBurstLength__h18535[11:0]) ; + assign sendData_byteEn__h18619 = (thisMesg[15:0] == 16'd0) ? 32'd0 : ((unrollCnt == 16'd1) ? @@ -2753,122 +2798,128 @@ module mkSMAdapter32B(wciS0_Clk, 32'h7FFFFFFF : 32'hFFFFFFFF)))))))))))))))))))))))))))))))) : 32'hFFFFFFFF) ; - assign value__h6702 = + assign value__h6387 = MUX_wmi_mFlagF_x_wire$wset_1__SEL_1 ? 32'hAAAAAAAA /* unspecified value */ : MUX_wmi_mFlagF_x_wire$wset_1__VAL_2 ; - assign wmi_respF_i_notEmpty__37_AND_smaCtrl_65_BIT_4__ETC___d542 = + assign wci_wslv_respF_cntr_r_8_MINUS_1___d27 = + wci_wslv_respF_cntr_r - 2'd1 ; + assign wmi_dhF_cntr_r_05_MINUS_1___d213 = wmi_dhF_cntr_r - 2'd1 ; + assign wmi_mFlagF_cntr_r_83_MINUS_1___d191 = wmi_mFlagF_cntr_r - 2'd1 ; + assign wmi_reqF_cntr_r_61_MINUS_1___d169 = wmi_reqF_cntr_r - 2'd1 ; + assign wmi_respF_i_notEmpty__34_AND_smaCtrl_62_BIT_4__ETC___d539 = wmi_respF$EMPTY_N && (smaCtrl[4] || respF_rRdPtr + 12'd1024 != respF_rWrPtr) ; - assign wsiBurstLength__h19161 = + assign wsiBurstLength__h18535 = smaCtrl[5] ? 16'd2 : { 5'd0, thisMesg[15:5] } ; - assign wsiS_reqFifo_i_notEmpty__64_AND_NOT_smaCtrl_65_ETC___d669 = + assign wsiS_reqFifo_i_notEmpty__61_AND_NOT_smaCtrl_62_ETC___d666 = wsiS_reqFifo$EMPTY_N && - (smaCtrl[3:0] != 4'h3 || wsiM_reqFifo_c_r != 2'd2) && - (!wsiS_reqFifo$D_OUT[309] || wmi_mFlagF_c_r != 2'd2) ; - assign x__h16878 = respF_rRdPtr + 12'd1 ; - assign x__h18530 = { 5'd0, wmi_sFlagReg[23:5] } ; - assign x__h18954 = fabWordsRemain == fabWordsCurReq ; - assign x__h23038 = x__h23050 + y__h23051 ; - assign x__h23050 = x__h23062 + y__h23063 ; - assign x__h23062 = x__h23074 + y__h23075 ; - assign x__h23074 = x__h23086 + y__h23087 ; - assign x__h23086 = x__h23098 + y__h23099 ; - assign x__h23098 = x__h23110 + y__h23111 ; - assign x__h23110 = x__h23122 + y__h23123 ; - assign x__h23122 = x__h23134 + y__h23135 ; - assign x__h23134 = x__h23146 + y__h23147 ; - assign x__h23146 = x__h23158 + y__h23159 ; - assign x__h23158 = x__h23170 + y__h23171 ; - assign x__h23170 = x__h23182 + y__h23183 ; - assign x__h23182 = x__h23194 + y__h23195 ; - assign x__h23194 = x__h23206 + y__h23207 ; - assign x__h23206 = x__h23218 + y__h23219 ; - assign x__h23218 = x__h23230 + y__h23231 ; - assign x__h23230 = x__h23242 + y__h23243 ; - assign x__h23242 = x__h23254 + y__h23255 ; - assign x__h23254 = x__h23266 + y__h23267 ; - assign x__h23266 = x__h23278 + y__h23279 ; - assign x__h23278 = x__h23290 + y__h23291 ; - assign x__h23290 = x__h23302 + y__h23303 ; - assign x__h23302 = x__h23314 + y__h23315 ; - assign x__h23314 = x__h23326 + y__h23327 ; - assign x__h23326 = x__h23338 + y__h23339 ; - assign x__h23338 = x__h23350 + y__h23351 ; - assign x__h23350 = x__h23362 + y__h23363 ; - assign x__h23362 = x__h23374 + y__h23375 ; - assign x__h23374 = x__h23386 + y__h23387 ; - assign x__h23386 = x__h23398 + y__h23399 ; - assign x__h23398 = { 5'd0, wsiS_reqFifo$D_OUT[39] } ; - assign x__h25619 = { wsiS_statusR, wsiM_statusR } ; - assign x__h25793 = wmi_sThreadBusy_d || wmi_sDataThreadBusy_d ; - assign x_length__h24547 = { 2'd0, mlB__h22832 } ; - assign y__h23039 = { 5'd0, wsiS_reqFifo$D_OUT[8] } ; - assign y__h23051 = { 5'd0, wsiS_reqFifo$D_OUT[9] } ; - assign y__h23063 = { 5'd0, wsiS_reqFifo$D_OUT[10] } ; - assign y__h23075 = { 5'd0, wsiS_reqFifo$D_OUT[11] } ; - assign y__h23087 = { 5'd0, wsiS_reqFifo$D_OUT[12] } ; - assign y__h23099 = { 5'd0, wsiS_reqFifo$D_OUT[13] } ; - assign y__h23111 = { 5'd0, wsiS_reqFifo$D_OUT[14] } ; - assign y__h23123 = { 5'd0, wsiS_reqFifo$D_OUT[15] } ; - assign y__h23135 = { 5'd0, wsiS_reqFifo$D_OUT[16] } ; - assign y__h23147 = { 5'd0, wsiS_reqFifo$D_OUT[17] } ; - assign y__h23159 = { 5'd0, wsiS_reqFifo$D_OUT[18] } ; - assign y__h23171 = { 5'd0, wsiS_reqFifo$D_OUT[19] } ; - assign y__h23183 = { 5'd0, wsiS_reqFifo$D_OUT[20] } ; - assign y__h23195 = { 5'd0, wsiS_reqFifo$D_OUT[21] } ; - assign y__h23207 = { 5'd0, wsiS_reqFifo$D_OUT[22] } ; - assign y__h23219 = { 5'd0, wsiS_reqFifo$D_OUT[23] } ; - assign y__h23231 = { 5'd0, wsiS_reqFifo$D_OUT[24] } ; - assign y__h23243 = { 5'd0, wsiS_reqFifo$D_OUT[25] } ; - assign y__h23255 = { 5'd0, wsiS_reqFifo$D_OUT[26] } ; - assign y__h23267 = { 5'd0, wsiS_reqFifo$D_OUT[27] } ; - assign y__h23279 = { 5'd0, wsiS_reqFifo$D_OUT[28] } ; - assign y__h23291 = { 5'd0, wsiS_reqFifo$D_OUT[29] } ; - assign y__h23303 = { 5'd0, wsiS_reqFifo$D_OUT[30] } ; - assign y__h23315 = { 5'd0, wsiS_reqFifo$D_OUT[31] } ; - assign y__h23327 = { 5'd0, wsiS_reqFifo$D_OUT[32] } ; - assign y__h23339 = { 5'd0, wsiS_reqFifo$D_OUT[33] } ; - assign y__h23351 = { 5'd0, wsiS_reqFifo$D_OUT[34] } ; - assign y__h23363 = { 5'd0, wsiS_reqFifo$D_OUT[35] } ; - assign y__h23375 = { 5'd0, wsiS_reqFifo$D_OUT[36] } ; - assign y__h23387 = { 5'd0, wsiS_reqFifo$D_OUT[37] } ; - assign y__h23399 = { 5'd0, wsiS_reqFifo$D_OUT[38] } ; + (smaCtrl[3:0] != 4'h3 || wsiM_reqFifo_cntr_r != 2'd2) && + (!wsiS_reqFifo$D_OUT[309] || wmi_mFlagF_cntr_r != 2'd2) ; + assign x__h16103 = respF_rWrPtr + 12'd1 ; + assign x__h16253 = respF_rRdPtr + 12'd1 ; + assign x__h17904 = { 5'd0, wmi_sFlagReg[23:5] } ; + assign x__h18328 = fabWordsRemain == fabWordsCurReq ; + assign x__h22411 = x__h22423 + y__h22424 ; + assign x__h22423 = x__h22435 + y__h22436 ; + assign x__h22435 = x__h22447 + y__h22448 ; + assign x__h22447 = x__h22459 + y__h22460 ; + assign x__h22459 = x__h22471 + y__h22472 ; + assign x__h22471 = x__h22483 + y__h22484 ; + assign x__h22483 = x__h22495 + y__h22496 ; + assign x__h22495 = x__h22507 + y__h22508 ; + assign x__h22507 = x__h22519 + y__h22520 ; + assign x__h22519 = x__h22531 + y__h22532 ; + assign x__h22531 = x__h22543 + y__h22544 ; + assign x__h22543 = x__h22555 + y__h22556 ; + assign x__h22555 = x__h22567 + y__h22568 ; + assign x__h22567 = x__h22579 + y__h22580 ; + assign x__h22579 = x__h22591 + y__h22592 ; + assign x__h22591 = x__h22603 + y__h22604 ; + assign x__h22603 = x__h22615 + y__h22616 ; + assign x__h22615 = x__h22627 + y__h22628 ; + assign x__h22627 = x__h22639 + y__h22640 ; + assign x__h22639 = x__h22651 + y__h22652 ; + assign x__h22651 = x__h22663 + y__h22664 ; + assign x__h22663 = x__h22675 + y__h22676 ; + assign x__h22675 = x__h22687 + y__h22688 ; + assign x__h22687 = x__h22699 + y__h22700 ; + assign x__h22699 = x__h22711 + y__h22712 ; + assign x__h22711 = x__h22723 + y__h22724 ; + assign x__h22723 = x__h22735 + y__h22736 ; + assign x__h22735 = x__h22747 + y__h22748 ; + assign x__h22747 = x__h22759 + y__h22760 ; + assign x__h22759 = x__h22771 + y__h22772 ; + assign x__h22771 = { 5'd0, wsiS_reqFifo$D_OUT[39] } ; + assign x__h24991 = { wsiS_statusR, wsiM_statusR } ; + assign x__h25165 = wmi_sThreadBusy_d || wmi_sDataThreadBusy_d ; + assign x_length__h23920 = { 2'd0, mlB__h22206 } ; + assign y__h22412 = { 5'd0, wsiS_reqFifo$D_OUT[8] } ; + assign y__h22424 = { 5'd0, wsiS_reqFifo$D_OUT[9] } ; + assign y__h22436 = { 5'd0, wsiS_reqFifo$D_OUT[10] } ; + assign y__h22448 = { 5'd0, wsiS_reqFifo$D_OUT[11] } ; + assign y__h22460 = { 5'd0, wsiS_reqFifo$D_OUT[12] } ; + assign y__h22472 = { 5'd0, wsiS_reqFifo$D_OUT[13] } ; + assign y__h22484 = { 5'd0, wsiS_reqFifo$D_OUT[14] } ; + assign y__h22496 = { 5'd0, wsiS_reqFifo$D_OUT[15] } ; + assign y__h22508 = { 5'd0, wsiS_reqFifo$D_OUT[16] } ; + assign y__h22520 = { 5'd0, wsiS_reqFifo$D_OUT[17] } ; + assign y__h22532 = { 5'd0, wsiS_reqFifo$D_OUT[18] } ; + assign y__h22544 = { 5'd0, wsiS_reqFifo$D_OUT[19] } ; + assign y__h22556 = { 5'd0, wsiS_reqFifo$D_OUT[20] } ; + assign y__h22568 = { 5'd0, wsiS_reqFifo$D_OUT[21] } ; + assign y__h22580 = { 5'd0, wsiS_reqFifo$D_OUT[22] } ; + assign y__h22592 = { 5'd0, wsiS_reqFifo$D_OUT[23] } ; + assign y__h22604 = { 5'd0, wsiS_reqFifo$D_OUT[24] } ; + assign y__h22616 = { 5'd0, wsiS_reqFifo$D_OUT[25] } ; + assign y__h22628 = { 5'd0, wsiS_reqFifo$D_OUT[26] } ; + assign y__h22640 = { 5'd0, wsiS_reqFifo$D_OUT[27] } ; + assign y__h22652 = { 5'd0, wsiS_reqFifo$D_OUT[28] } ; + assign y__h22664 = { 5'd0, wsiS_reqFifo$D_OUT[29] } ; + assign y__h22676 = { 5'd0, wsiS_reqFifo$D_OUT[30] } ; + assign y__h22688 = { 5'd0, wsiS_reqFifo$D_OUT[31] } ; + assign y__h22700 = { 5'd0, wsiS_reqFifo$D_OUT[32] } ; + assign y__h22712 = { 5'd0, wsiS_reqFifo$D_OUT[33] } ; + assign y__h22724 = { 5'd0, wsiS_reqFifo$D_OUT[34] } ; + assign y__h22736 = { 5'd0, wsiS_reqFifo$D_OUT[35] } ; + assign y__h22748 = { 5'd0, wsiS_reqFifo$D_OUT[36] } ; + assign y__h22760 = { 5'd0, wsiS_reqFifo$D_OUT[37] } ; + assign y__h22772 = { 5'd0, wsiS_reqFifo$D_OUT[38] } ; always@(wci_wslv_reqF$D_OUT or smaCtrl or - rdat__h25567 or - rdat__h25573 or - rdat__h25579 or - rdat__h25592 or - rdat__h25615 or - rdat__h25715 or - rdat__h25729 or - rdat__h25737 or - rdat__h25743 or - rdat__h25757 or - rdat__h25765 or - rdat__h25771 or - rdat__h25777 or rdat__h25783 or rdat__h25789 or rdat__h25799) + rdat__h24939 or + rdat__h24945 or + rdat__h24951 or + rdat__h24964 or + rdat__h24987 or + rdat__h25087 or + rdat__h25101 or + rdat__h25109 or + rdat__h25115 or + rdat__h25129 or + rdat__h25137 or + rdat__h25143 or + rdat__h25149 or rdat__h25155 or rdat__h25161 or rdat__h25171) begin case (wci_wslv_reqF$D_OUT[39:32]) - 8'h0: g_data__h25524 = smaCtrl; - 8'h04: g_data__h25524 = rdat__h25567; - 8'h08: g_data__h25524 = rdat__h25573; - 8'h10: g_data__h25524 = rdat__h25579; - 8'h14: g_data__h25524 = rdat__h25592; - 8'h18: g_data__h25524 = rdat__h25615; - 8'h20: g_data__h25524 = rdat__h25715; - 8'h24: g_data__h25524 = rdat__h25729; - 8'h28: g_data__h25524 = rdat__h25737; - 8'h2C: g_data__h25524 = rdat__h25743; - 8'h30: g_data__h25524 = rdat__h25757; - 8'h34: g_data__h25524 = rdat__h25765; - 8'h38: g_data__h25524 = rdat__h25771; - 8'h3C: g_data__h25524 = rdat__h25777; - 8'h40: g_data__h25524 = rdat__h25783; - 8'h44: g_data__h25524 = rdat__h25789; - 8'h48: g_data__h25524 = rdat__h25799; - default: g_data__h25524 = 32'd0; + 8'h0: g_data__h24896 = smaCtrl; + 8'h04: g_data__h24896 = rdat__h24939; + 8'h08: g_data__h24896 = rdat__h24945; + 8'h10: g_data__h24896 = rdat__h24951; + 8'h14: g_data__h24896 = rdat__h24964; + 8'h18: g_data__h24896 = rdat__h24987; + 8'h20: g_data__h24896 = rdat__h25087; + 8'h24: g_data__h24896 = rdat__h25101; + 8'h28: g_data__h24896 = rdat__h25109; + 8'h2C: g_data__h24896 = rdat__h25115; + 8'h30: g_data__h24896 = rdat__h25129; + 8'h34: g_data__h24896 = rdat__h25137; + 8'h38: g_data__h24896 = rdat__h25143; + 8'h3C: g_data__h24896 = rdat__h25149; + 8'h40: g_data__h24896 = rdat__h25155; + 8'h44: g_data__h24896 = rdat__h25161; + 8'h48: g_data__h24896 = rdat__h25171; + default: g_data__h24896 = 32'd0; endcase end @@ -2908,22 +2959,22 @@ module mkSMAdapter32B(wciS0_Clk, wci_wslv_illegalEdge <= `BSV_ASSIGNMENT_DELAY 1'd0; wci_wslv_nState <= `BSV_ASSIGNMENT_DELAY 3'd0; wci_wslv_reqF_countReg <= `BSV_ASSIGNMENT_DELAY 2'd0; - wci_wslv_respF_c_r <= `BSV_ASSIGNMENT_DELAY 2'd0; + wci_wslv_respF_cntr_r <= `BSV_ASSIGNMENT_DELAY 2'd0; wci_wslv_respF_q_0 <= `BSV_ASSIGNMENT_DELAY 34'h0AAAAAAAA; wci_wslv_respF_q_1 <= `BSV_ASSIGNMENT_DELAY 34'h0AAAAAAAA; wci_wslv_sFlagReg <= `BSV_ASSIGNMENT_DELAY 1'd0; wci_wslv_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY 1'd1; wmi_busyWithMessage <= `BSV_ASSIGNMENT_DELAY 1'd0; - wmi_dhF_c_r <= `BSV_ASSIGNMENT_DELAY 2'd0; + wmi_dhF_cntr_r <= `BSV_ASSIGNMENT_DELAY 2'd0; wmi_dhF_q_0 <= `BSV_ASSIGNMENT_DELAY 290'd0; wmi_dhF_q_1 <= `BSV_ASSIGNMENT_DELAY 290'd0; wmi_errorSticky <= `BSV_ASSIGNMENT_DELAY 1'd0; - wmi_mFlagF_c_r <= `BSV_ASSIGNMENT_DELAY 2'd0; + wmi_mFlagF_cntr_r <= `BSV_ASSIGNMENT_DELAY 2'd0; wmi_mFlagF_q_0 <= `BSV_ASSIGNMENT_DELAY 32'd0; wmi_mFlagF_q_1 <= `BSV_ASSIGNMENT_DELAY 32'd0; wmi_operateD <= `BSV_ASSIGNMENT_DELAY 1'd0; wmi_peerIsReady <= `BSV_ASSIGNMENT_DELAY 1'd0; - wmi_reqF_c_r <= `BSV_ASSIGNMENT_DELAY 2'd0; + wmi_reqF_cntr_r <= `BSV_ASSIGNMENT_DELAY 2'd0; wmi_reqF_q_0 <= `BSV_ASSIGNMENT_DELAY 32'd0; wmi_reqF_q_1 <= `BSV_ASSIGNMENT_DELAY 32'd0; wmi_sDataThreadBusy_d <= `BSV_ASSIGNMENT_DELAY 1'd0; @@ -2939,7 +2990,7 @@ module mkSMAdapter32B(wciS0_Clk, wsiM_operateD <= `BSV_ASSIGNMENT_DELAY 1'd0; wsiM_pMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0; wsiM_peerIsReady <= `BSV_ASSIGNMENT_DELAY 1'd0; - wsiM_reqFifo_c_r <= `BSV_ASSIGNMENT_DELAY 2'd0; + wsiM_reqFifo_cntr_r <= `BSV_ASSIGNMENT_DELAY 2'd0; wsiM_reqFifo_q_0 <= `BSV_ASSIGNMENT_DELAY 313'h00000AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA00; wsiM_reqFifo_q_1 <= `BSV_ASSIGNMENT_DELAY @@ -3013,8 +3064,9 @@ module mkSMAdapter32B(wciS0_Clk, if (wci_wslv_reqF_countReg$EN) wci_wslv_reqF_countReg <= `BSV_ASSIGNMENT_DELAY wci_wslv_reqF_countReg$D_IN; - if (wci_wslv_respF_c_r$EN) - wci_wslv_respF_c_r <= `BSV_ASSIGNMENT_DELAY wci_wslv_respF_c_r$D_IN; + if (wci_wslv_respF_cntr_r$EN) + wci_wslv_respF_cntr_r <= `BSV_ASSIGNMENT_DELAY + wci_wslv_respF_cntr_r$D_IN; if (wci_wslv_respF_q_0$EN) wci_wslv_respF_q_0 <= `BSV_ASSIGNMENT_DELAY wci_wslv_respF_q_0$D_IN; if (wci_wslv_respF_q_1$EN) @@ -3027,16 +3079,16 @@ module mkSMAdapter32B(wciS0_Clk, if (wmi_busyWithMessage$EN) wmi_busyWithMessage <= `BSV_ASSIGNMENT_DELAY wmi_busyWithMessage$D_IN; - if (wmi_dhF_c_r$EN) - wmi_dhF_c_r <= `BSV_ASSIGNMENT_DELAY wmi_dhF_c_r$D_IN; + if (wmi_dhF_cntr_r$EN) + wmi_dhF_cntr_r <= `BSV_ASSIGNMENT_DELAY wmi_dhF_cntr_r$D_IN; if (wmi_dhF_q_0$EN) wmi_dhF_q_0 <= `BSV_ASSIGNMENT_DELAY wmi_dhF_q_0$D_IN; if (wmi_dhF_q_1$EN) wmi_dhF_q_1 <= `BSV_ASSIGNMENT_DELAY wmi_dhF_q_1$D_IN; if (wmi_errorSticky$EN) wmi_errorSticky <= `BSV_ASSIGNMENT_DELAY wmi_errorSticky$D_IN; - if (wmi_mFlagF_c_r$EN) - wmi_mFlagF_c_r <= `BSV_ASSIGNMENT_DELAY wmi_mFlagF_c_r$D_IN; + if (wmi_mFlagF_cntr_r$EN) + wmi_mFlagF_cntr_r <= `BSV_ASSIGNMENT_DELAY wmi_mFlagF_cntr_r$D_IN; if (wmi_mFlagF_q_0$EN) wmi_mFlagF_q_0 <= `BSV_ASSIGNMENT_DELAY wmi_mFlagF_q_0$D_IN; if (wmi_mFlagF_q_1$EN) @@ -3045,8 +3097,8 @@ module mkSMAdapter32B(wciS0_Clk, wmi_operateD <= `BSV_ASSIGNMENT_DELAY wmi_operateD$D_IN; if (wmi_peerIsReady$EN) wmi_peerIsReady <= `BSV_ASSIGNMENT_DELAY wmi_peerIsReady$D_IN; - if (wmi_reqF_c_r$EN) - wmi_reqF_c_r <= `BSV_ASSIGNMENT_DELAY wmi_reqF_c_r$D_IN; + if (wmi_reqF_cntr_r$EN) + wmi_reqF_cntr_r <= `BSV_ASSIGNMENT_DELAY wmi_reqF_cntr_r$D_IN; if (wmi_reqF_q_0$EN) wmi_reqF_q_0 <= `BSV_ASSIGNMENT_DELAY wmi_reqF_q_0$D_IN; if (wmi_reqF_q_1$EN) @@ -3078,8 +3130,9 @@ module mkSMAdapter32B(wciS0_Clk, wsiM_pMesgCount <= `BSV_ASSIGNMENT_DELAY wsiM_pMesgCount$D_IN; if (wsiM_peerIsReady$EN) wsiM_peerIsReady <= `BSV_ASSIGNMENT_DELAY wsiM_peerIsReady$D_IN; - if (wsiM_reqFifo_c_r$EN) - wsiM_reqFifo_c_r <= `BSV_ASSIGNMENT_DELAY wsiM_reqFifo_c_r$D_IN; + if (wsiM_reqFifo_cntr_r$EN) + wsiM_reqFifo_cntr_r <= `BSV_ASSIGNMENT_DELAY + wsiM_reqFifo_cntr_r$D_IN; if (wsiM_reqFifo_q_0$EN) wsiM_reqFifo_q_0 <= `BSV_ASSIGNMENT_DELAY wsiM_reqFifo_q_0$D_IN; if (wsiM_reqFifo_q_1$EN) @@ -3191,25 +3244,25 @@ module mkSMAdapter32B(wciS0_Clk, wci_wslv_isReset_isInReset = 1'h0; wci_wslv_nState = 3'h2; wci_wslv_reqF_countReg = 2'h2; - wci_wslv_respF_c_r = 2'h2; + wci_wslv_respF_cntr_r = 2'h2; wci_wslv_respF_q_0 = 34'h2AAAAAAAA; wci_wslv_respF_q_1 = 34'h2AAAAAAAA; wci_wslv_sFlagReg = 1'h0; wci_wslv_sThreadBusy_d = 1'h0; wmi_busyWithMessage = 1'h0; - wmi_dhF_c_r = 2'h2; + wmi_dhF_cntr_r = 2'h2; wmi_dhF_q_0 = 290'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; wmi_dhF_q_1 = 290'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; wmi_errorSticky = 1'h0; wmi_isReset_isInReset = 1'h0; - wmi_mFlagF_c_r = 2'h2; + wmi_mFlagF_cntr_r = 2'h2; wmi_mFlagF_q_0 = 32'hAAAAAAAA; wmi_mFlagF_q_1 = 32'hAAAAAAAA; wmi_operateD = 1'h0; wmi_peerIsReady = 1'h0; - wmi_reqF_c_r = 2'h2; + wmi_reqF_cntr_r = 2'h2; wmi_reqF_q_0 = 32'hAAAAAAAA; wmi_reqF_q_1 = 32'hAAAAAAAA; wmi_sDataThreadBusy_d = 1'h0; @@ -3227,7 +3280,7 @@ module mkSMAdapter32B(wciS0_Clk, wsiM_operateD = 1'h0; wsiM_pMesgCount = 32'hAAAAAAAA; wsiM_peerIsReady = 1'h0; - wsiM_reqFifo_c_r = 2'h2; + wsiM_reqFifo_cntr_r = 2'h2; wsiM_reqFifo_q_0 = 313'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; wsiM_reqFifo_q_1 = @@ -3263,96 +3316,96 @@ module mkSMAdapter32B(wciS0_Clk, if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_start) begin - v__h3729 = $time; + v__h3597 = $time; #0; end if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_start) $display("[%0d]: %m: WCI ControlOp: Starting-transition edge:%x from:%x", - v__h3729, + v__h3597, wci_wslv_reqF$D_OUT[36:34], wci_wslv_cState); if (wciS0_MReset_n != `BSV_RESET_VALUE) if (MUX_unrollCnt$write_1__SEL_1) begin - v__h18699 = $time; + v__h18073 = $time; #0; end if (wciS0_MReset_n != `BSV_RESET_VALUE) if (MUX_unrollCnt$write_1__SEL_1) $display("[%0d]: %m: wmrd_mesgBegin mesgCount:%0h mesgLength:%0h reqInfo:%0h", - v__h18699, + v__h18073, mesgCount, wmi_sFlagReg[23:0], wmi_sFlagReg[31:24]); if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wmwt_mesgBegin && wsiS_reqFifo$D_OUT[308]) begin - v__h22418 = $time; + v__h21792 = $time; #0; end if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wmwt_mesgBegin && wsiS_reqFifo$D_OUT[308]) $display("[%0d]: %m: mesgBegin PRECISE mesgCount:%0x WSI burstLength:%0x reqInfo:%0x", - v__h22418, + v__h21792, mesgCount, wsiS_reqFifo$D_OUT[307:296], wsiS_reqFifo$D_OUT[7:0]); if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wmwt_mesgBegin && !wsiS_reqFifo$D_OUT[308]) begin - v__h22477 = $time; + v__h21851 = $time; #0; end if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wmwt_mesgBegin && !wsiS_reqFifo$D_OUT[308]) $display("[%0d]: %m: wmwt_mesgBegin IMPRECISE mesgCount:%0x", - v__h22477, + v__h21851, mesgCount); if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wmwt_doAbort) begin - v__h24973 = $time; + v__h24345 = $time; #0; end if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wmwt_doAbort) - $display("[%0d]: %m: wmwt_doAbort", v__h24973); + $display("[%0d]: %m: wmwt_doAbort", v__h24345); if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wmwt_messageFinalize) begin - v__h25156 = $time; + v__h24528 = $time; #0; end if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wmwt_messageFinalize) $display("[%0d]: %m: wmwt_messageFinalize mesgCount:%0x WSI mesgLength:%0x", - v__h25156, + v__h24528, mesgCount, thisMesg[15:0]); if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfwr) begin - v__h25352 = $time; + v__h24724 = $time; #0; end if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfwr) $display("[%0d]: %m: SMAdapter WCI CONFIG WRITE Addr:%0x BE:%0x Data:%0x", - v__h25352, + v__h24724, wci_wslv_reqF$D_OUT[63:32], wci_wslv_reqF$D_OUT[67:64], wci_wslv_reqF$D_OUT[31:0]); if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_ctrl_IsO) begin - v__h26014 = $time; + v__h25381 = $time; #0; end if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_ctrl_IsO) $display("[%0d]: %m: Starting SMAdapter smaCtrl:%0x", - v__h26014, + v__h25381, smaCtrl); if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_OrE) @@ -3387,25 +3440,25 @@ module mkSMAdapter32B(wciS0_Clk, if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge) begin - v__h4048 = $time; + v__h3916 = $time; #0; end if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge) $display("[%0d]: %m: WCI ControlOp: ILLEGAL-EDGE Completed-transition edge:%x from:%x", - v__h4048, + v__h3916, wci_wslv_cEdge, wci_wslv_cState); if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && !wci_wslv_illegalEdge) begin - v__h3904 = $time; + v__h3772 = $time; #0; end if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && !wci_wslv_illegalEdge) $display("[%0d]: %m: WCI ControlOp: Completed-transition edge:%x from:%x to:%x", - v__h3904, + v__h3772, wci_wslv_cEdge, wci_wslv_cState, wci_wslv_nState); diff --git a/rtl/mkSMAdapter4B.v b/rtl/mkSMAdapter4B.v index 2d740a77..0512bff3 100644 --- a/rtl/mkSMAdapter4B.v +++ b/rtl/mkSMAdapter4B.v @@ -1,7 +1,7 @@ // -// Generated by Bluespec Compiler, version 2012.09.beta1 (build 29570, 2012-09.11) +// Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Tue Dec 11 16:21:06 EST 2012 +// On Fri Jun 21 16:57:56 EDT 2013 // // // Ports: @@ -382,6 +382,7 @@ module mkSMAdapter4B(wciS0_Clk, fabRespCredit_acc_v2$whas, mesgPreRequest_1$wget, mesgPreRequest_1$whas, + respF_pwClear$whas, respF_pwDequeue$whas, respF_pwEnqueue$whas, respF_wDataIn$whas, @@ -607,10 +608,10 @@ module mkSMAdapter4B(wciS0_Clk, wire [1 : 0] wci_wslv_reqF_countReg$D_IN; wire wci_wslv_reqF_countReg$EN; - // register wci_wslv_respF_c_r - reg [1 : 0] wci_wslv_respF_c_r; - wire [1 : 0] wci_wslv_respF_c_r$D_IN; - wire wci_wslv_respF_c_r$EN; + // register wci_wslv_respF_cntr_r + reg [1 : 0] wci_wslv_respF_cntr_r; + wire [1 : 0] wci_wslv_respF_cntr_r$D_IN; + wire wci_wslv_respF_cntr_r$EN; // register wci_wslv_respF_q_0 reg [33 : 0] wci_wslv_respF_q_0; @@ -634,10 +635,10 @@ module mkSMAdapter4B(wciS0_Clk, reg wmi_busyWithMessage; wire wmi_busyWithMessage$D_IN, wmi_busyWithMessage$EN; - // register wmi_dhF_c_r - reg [1 : 0] wmi_dhF_c_r; - wire [1 : 0] wmi_dhF_c_r$D_IN; - wire wmi_dhF_c_r$EN; + // register wmi_dhF_cntr_r + reg [1 : 0] wmi_dhF_cntr_r; + wire [1 : 0] wmi_dhF_cntr_r$D_IN; + wire wmi_dhF_cntr_r$EN; // register wmi_dhF_q_0 reg [37 : 0] wmi_dhF_q_0; @@ -657,10 +658,10 @@ module mkSMAdapter4B(wciS0_Clk, reg wmi_isReset_isInReset; wire wmi_isReset_isInReset$D_IN, wmi_isReset_isInReset$EN; - // register wmi_mFlagF_c_r - reg [1 : 0] wmi_mFlagF_c_r; - wire [1 : 0] wmi_mFlagF_c_r$D_IN; - wire wmi_mFlagF_c_r$EN; + // register wmi_mFlagF_cntr_r + reg [1 : 0] wmi_mFlagF_cntr_r; + wire [1 : 0] wmi_mFlagF_cntr_r$D_IN; + wire wmi_mFlagF_cntr_r$EN; // register wmi_mFlagF_q_0 reg [31 : 0] wmi_mFlagF_q_0; @@ -680,10 +681,10 @@ module mkSMAdapter4B(wciS0_Clk, reg wmi_peerIsReady; wire wmi_peerIsReady$D_IN, wmi_peerIsReady$EN; - // register wmi_reqF_c_r - reg [1 : 0] wmi_reqF_c_r; - wire [1 : 0] wmi_reqF_c_r$D_IN; - wire wmi_reqF_c_r$EN; + // register wmi_reqF_cntr_r + reg [1 : 0] wmi_reqF_cntr_r; + wire [1 : 0] wmi_reqF_cntr_r$D_IN; + wire wmi_reqF_cntr_r$EN; // register wmi_reqF_q_0 reg [31 : 0] wmi_reqF_q_0; @@ -763,10 +764,10 @@ module mkSMAdapter4B(wciS0_Clk, reg wsiM_peerIsReady; wire wsiM_peerIsReady$D_IN, wsiM_peerIsReady$EN; - // register wsiM_reqFifo_c_r - reg [1 : 0] wsiM_reqFifo_c_r; - wire [1 : 0] wsiM_reqFifo_c_r$D_IN; - wire wsiM_reqFifo_c_r$EN; + // register wsiM_reqFifo_cntr_r + reg [1 : 0] wsiM_reqFifo_cntr_r; + wire [1 : 0] wsiM_reqFifo_cntr_r$D_IN; + wire wsiM_reqFifo_cntr_r$EN; // register wsiM_reqFifo_q_0 reg [60 : 0] wsiM_reqFifo_q_0; @@ -936,16 +937,16 @@ module mkSMAdapter4B(wciS0_Clk, reg [33 : 0] MUX_wci_wslv_respF_q_0$write_1__VAL_2; wire [60 : 0] MUX_wsiM_reqFifo_q_0$write_1__VAL_1, MUX_wsiM_reqFifo_q_0$write_1__VAL_2, - MUX_wsiM_reqFifo_q_1$write_1__VAL_1, + MUX_wsiM_reqFifo_q_1$write_1__VAL_2, MUX_wsiM_reqFifo_x_wire$wset_1__VAL_3; wire [37 : 0] MUX_wmi_dhF_q_0$write_1__VAL_1, MUX_wmi_dhF_q_0$write_1__VAL_2, - MUX_wmi_dhF_q_1$write_1__VAL_1; + MUX_wmi_dhF_q_1$write_1__VAL_2; wire [33 : 0] MUX_wci_wslv_respF_q_0$write_1__VAL_1, MUX_wci_wslv_respF_q_1$write_1__VAL_1, MUX_wci_wslv_respF_x_wire$wset_1__VAL_1, MUX_wci_wslv_respF_x_wire$wset_1__VAL_2; - wire [31 : 0] MUX_mesgCount$write_1__VAL_2, + wire [31 : 0] MUX_mesgCount$write_1__VAL_1, MUX_thisMesg$write_1__VAL_1, MUX_thisMesg$write_1__VAL_2, MUX_wmi_mFlagF_q_0$write_1__VAL_1, @@ -959,19 +960,16 @@ module mkSMAdapter4B(wciS0_Clk, wire [15 : 0] MUX_unrollCnt$write_1__VAL_1, MUX_unrollCnt$write_1__VAL_2; wire [13 : 0] MUX_fabWordsRemain$write_1__VAL_1, MUX_fabWordsRemain$write_1__VAL_2, + MUX_mesgLengthSoFar$write_1__VAL_1, MUX_mesgReqAddr$write_1__VAL_2; wire [11 : 0] MUX_fabRespCredit_value$write_1__VAL_2; wire [8 : 0] MUX_opcode$write_1__VAL_3; - wire [1 : 0] MUX_wci_wslv_respF_c_r$write_1__VAL_1, - MUX_wci_wslv_respF_c_r$write_1__VAL_2, - MUX_wmi_dhF_c_r$write_1__VAL_1, - MUX_wmi_dhF_c_r$write_1__VAL_2, - MUX_wmi_mFlagF_c_r$write_1__VAL_1, - MUX_wmi_mFlagF_c_r$write_1__VAL_2, - MUX_wmi_reqF_c_r$write_1__VAL_1, - MUX_wmi_reqF_c_r$write_1__VAL_2, - MUX_wsiM_reqFifo_c_r$write_1__VAL_1, - MUX_wsiM_reqFifo_c_r$write_1__VAL_2; + wire [1 : 0] MUX_wci_wslv_respF_cntr_r$write_1__VAL_2, + MUX_wmi_dhF_cntr_r$write_1__VAL_2, + MUX_wmi_mFlagF_cntr_r$write_1__VAL_2, + MUX_wmi_reqF_cntr_r$write_1__VAL_2, + MUX_wsiM_reqFifo_cntr_r$write_1__VAL_1, + MUX_wsiM_reqFifo_cntr_r$write_1__VAL_2; wire MUX_endOfMessage$write_1__SEL_1, MUX_mesgCount$write_1__SEL_1, MUX_mesgReqOK$write_1__SEL_3, @@ -979,73 +977,97 @@ module mkSMAdapter4B(wciS0_Clk, MUX_unrollCnt$write_1__SEL_2, MUX_wci_wslv_illegalEdge$write_1__SEL_1, MUX_wci_wslv_illegalEdge$write_1__VAL_1, + MUX_wci_wslv_respF_q_0$write_1__SEL_1, MUX_wci_wslv_respF_q_0$write_1__SEL_2, + MUX_wci_wslv_respF_q_1$write_1__SEL_1, MUX_wci_wslv_respF_q_1$write_1__SEL_2, + MUX_wmi_dhF_q_0$write_1__SEL_1, MUX_wmi_dhF_q_0$write_1__SEL_2, + MUX_wmi_dhF_q_1$write_1__SEL_1, MUX_wmi_dhF_q_1$write_1__SEL_2, + MUX_wmi_mFlagF_q_0$write_1__SEL_1, MUX_wmi_mFlagF_q_0$write_1__SEL_2, + MUX_wmi_mFlagF_q_1$write_1__SEL_1, MUX_wmi_mFlagF_q_1$write_1__SEL_2, MUX_wmi_mFlagF_x_wire$wset_1__SEL_1, + MUX_wmi_reqF_q_0$write_1__SEL_1, MUX_wmi_reqF_q_0$write_1__SEL_2, + MUX_wmi_reqF_q_1$write_1__SEL_1, MUX_wmi_reqF_q_1$write_1__SEL_2, + MUX_wsiM_reqFifo_q_0$write_1__SEL_1, MUX_wsiM_reqFifo_q_0$write_1__SEL_2, + MUX_wsiM_reqFifo_q_1$write_1__SEL_1, MUX_wsiM_reqFifo_q_1$write_1__SEL_2, MUX_wsiM_reqFifo_x_wire$wset_1__SEL_1, MUX_wsiM_reqFifo_x_wire$wset_1__SEL_2, MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3; // remaining internal signals - reg [63 : 0] v__h18699, - v__h23115, - v__h23174, - v__h24522, - v__h24705, - v__h24901, - v__h25563, - v__h3729, - v__h3904, - v__h4048; - reg [31 : 0] g_data__h25073; - wire [55 : 0] IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d881; - wire [31 : 0] rdat__h25116, - rdat__h25122, - rdat__h25128, - rdat__h25141, - rdat__h25164, - rdat__h25264, - rdat__h25278, - rdat__h25286, - rdat__h25292, - rdat__h25306, - rdat__h25314, - rdat__h25320, - rdat__h25326, - rdat__h25332, - rdat__h25338, - rdat__h25348, - value__h6702, - x__h19302; - wire [23 : 0] b__h18410, - mesgMetaF_length__h23696, - residue__h18273, - x__h18530; - wire [15 : 0] wsiBurstLength__h19161, x__h25168, x_length__h24096; - wire [13 : 0] b__h18783, mlB__h23529, mlInc__h23528; - wire [11 : 0] b__h15473, sendData_burstLength__h19243, x__h16878; - wire [7 : 0] mesgMetaF_opcode__h23695; - wire [3 : 0] sendData_byteEn__h19245; - wire [2 : 0] IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d889, - x__h23735, - x__h23747, - x__h23759, - y__h23736, - y__h23748, - y__h23760; - wire NOT_wmi_reqF_c_r_57_EQ_2_75_76_AND_wmi_operate_ETC___d524, - wmi_respF_i_notEmpty__36_AND_smaCtrl_65_BIT_4__ETC___d541, - wsiS_reqFifo_i_notEmpty__64_AND_NOT_smaCtrl_65_ETC___d669, - x__h18954, - x__h25342; + reg [63 : 0] v__h18073, + v__h21792, + v__h21851, + v__h23197, + v__h23380, + v__h23576, + v__h24233, + v__h3597, + v__h3772, + v__h3916; + reg [31 : 0] g_data__h23748; + wire [55 : 0] IF_respF_wDataIn_whas__28_THEN_respF_wDataIn_w_ETC___d437; + wire [31 : 0] rdat__h23791, + rdat__h23797, + rdat__h23803, + rdat__h23816, + rdat__h23839, + rdat__h23939, + rdat__h23953, + rdat__h23961, + rdat__h23967, + rdat__h23981, + rdat__h23989, + rdat__h23995, + rdat__h24001, + rdat__h24007, + rdat__h24013, + rdat__h24023, + value__h6387, + x__h18676; + wire [23 : 0] b__h17784, + mesgMetaF_length__h22373, + residue__h17647, + x__h17904; + wire [15 : 0] wsiBurstLength__h18535, x__h23843, x_length__h22772; + wire [13 : 0] b__h18157, mlB__h22206, mlInc__h22205; + wire [11 : 0] b__h14802, sendData_burstLength__h18617, x__h16103, x__h16253; + wire [7 : 0] mesgMetaF_opcode__h22372; + wire [3 : 0] sendData_byteEn__h18619; + wire [2 : 0] IF_respF_wDataIn_whas__28_THEN_respF_wDataIn_w_ETC___d431, + x__h22411, + x__h22423, + x__h22435, + y__h22412, + y__h22424, + y__h22436; + wire [1 : 0] wci_wslv_respF_cntr_r_8_MINUS_1___d27, + wmi_dhF_cntr_r_05_MINUS_1___d213, + wmi_mFlagF_cntr_r_83_MINUS_1___d191, + wmi_reqF_cntr_r_61_MINUS_1___d169; + wire NOT_wmi_reqF_cntr_r_61_EQ_2_73_74_AND_wmi_oper_ETC___d521, + _dfoo1, + _dfoo11, + _dfoo13, + _dfoo15, + _dfoo17, + _dfoo19, + _dfoo3, + _dfoo5, + _dfoo7, + _dfoo9, + wmi_respF_i_notEmpty__33_AND_smaCtrl_62_BIT_4__ETC___d538, + wsiS_reqFifo_i_notEmpty__61_AND_NOT_smaCtrl_62_ETC___d666, + x__h18328, + x__h24017; // value method wciS0_sResp assign wciS0_SResp = wci_wslv_respF_q_0[33:32] ; @@ -1204,7 +1226,7 @@ module mkSMAdapter4B(wciS0_Clk, // rule RL_wmrd_mesgBodyRequest assign WILL_FIRE_RL_wmrd_mesgBodyRequest = - NOT_wmi_reqF_c_r_57_EQ_2_75_76_AND_wmi_operate_ETC___d524 && + NOT_wmi_reqF_cntr_r_61_EQ_2_73_74_AND_wmi_oper_ETC___d521 && wci_wslv_cState == 3'd2 && (smaCtrl[3:0] == 4'h1 || smaCtrl[3:0] == 4'h4 || smaCtrl[3:0] == 4'h9) && @@ -1235,18 +1257,18 @@ module mkSMAdapter4B(wciS0_Clk, // rule RL_wsiM_reqFifo_deq assign WILL_FIRE_RL_wsiM_reqFifo_deq = - wsiM_reqFifo_c_r != 2'd0 && !wsiM_sThreadBusy_d ; + wsiM_reqFifo_cntr_r != 2'd0 && !wsiM_sThreadBusy_d ; // rule RL_wsipass_doMessagePush assign WILL_FIRE_RL_wsipass_doMessagePush = wsiS_reqFifo$EMPTY_N && - (smaCtrl[4] || wsiM_reqFifo_c_r != 2'd2) && + (smaCtrl[4] || wsiM_reqFifo_cntr_r != 2'd2) && wci_wslv_cState == 3'd2 && smaCtrl[3:0] == 4'h0 ; // rule RL_wci_cfrd assign WILL_FIRE_RL_wci_cfrd = - wci_wslv_respF_c_r != 2'd2 && wci_wslv_reqF$EMPTY_N && + wci_wslv_respF_cntr_r != 2'd2 && wci_wslv_reqF$EMPTY_N && wci_wslv_wci_cfrd_pw$whas && !WILL_FIRE_RL_wci_wslv_ctl_op_start && !WILL_FIRE_RL_wci_wslv_ctl_op_complete ; @@ -1265,9 +1287,10 @@ module mkSMAdapter4B(wciS0_Clk, // rule RL_wmwt_messagePush assign CAN_FIRE_RL_wmwt_messagePush = - wmi_reqF_c_r != 2'd2 && wmi_dhF_c_r != 2'd2 && wmi_operateD && + wmi_reqF_cntr_r != 2'd2 && wmi_dhF_cntr_r != 2'd2 && + wmi_operateD && wmi_peerIsReady && - wsiS_reqFifo_i_notEmpty__64_AND_NOT_smaCtrl_65_ETC___d669 && + wsiS_reqFifo_i_notEmpty__61_AND_NOT_smaCtrl_62_ETC___d666 && wci_wslv_cState == 3'd2 && (smaCtrl[3:0] == 4'h2 || smaCtrl[3:0] == 4'h3) && readyToPush ; @@ -1287,10 +1310,7 @@ module mkSMAdapter4B(wciS0_Clk, // rule RL_wmi_reqF_incCtr assign WILL_FIRE_RL_wmi_reqF_incCtr = - ((wmi_reqF_c_r == 2'd0) ? - wmi_reqF_x_wire$whas : - wmi_reqF_c_r != 2'd1 || wmi_reqF_x_wire$whas) && - wmi_reqF_enqueueing$whas && + wmi_reqF_x_wire$whas && wmi_reqF_enqueueing$whas && !wmi_reqF_dequeueing$whas ; // rule RL_wmi_reqF_decCtr @@ -1299,18 +1319,12 @@ module mkSMAdapter4B(wciS0_Clk, // rule RL_wmi_reqF_both assign WILL_FIRE_RL_wmi_reqF_both = - ((wmi_reqF_c_r == 2'd1) ? - wmi_reqF_x_wire$whas : - wmi_reqF_c_r != 2'd2 || wmi_reqF_x_wire$whas) && - wmi_reqF_dequeueing$whas && + wmi_reqF_x_wire$whas && wmi_reqF_dequeueing$whas && wmi_reqF_enqueueing$whas ; // rule RL_wmi_mFlagF_incCtr assign WILL_FIRE_RL_wmi_mFlagF_incCtr = - ((wmi_mFlagF_c_r == 2'd0) ? - wmi_mFlagF_enqueueing$whas : - wmi_mFlagF_c_r != 2'd1 || wmi_mFlagF_enqueueing$whas) && - wmi_mFlagF_enqueueing$whas && + wmi_mFlagF_enqueueing$whas && wmi_mFlagF_enqueueing$whas && !wmi_mFlagF_dequeueing$whas ; // rule RL_wmi_mFlagF_decCtr @@ -1319,18 +1333,12 @@ module mkSMAdapter4B(wciS0_Clk, // rule RL_wmi_mFlagF_both assign WILL_FIRE_RL_wmi_mFlagF_both = - ((wmi_mFlagF_c_r == 2'd1) ? - wmi_mFlagF_enqueueing$whas : - wmi_mFlagF_c_r != 2'd2 || wmi_mFlagF_enqueueing$whas) && - wmi_mFlagF_dequeueing$whas && + wmi_mFlagF_enqueueing$whas && wmi_mFlagF_dequeueing$whas && wmi_mFlagF_enqueueing$whas ; // rule RL_wmi_dhF_incCtr assign WILL_FIRE_RL_wmi_dhF_incCtr = - ((wmi_dhF_c_r == 2'd0) ? - MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 : - wmi_dhF_c_r != 2'd1 || - MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3) && + MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 && MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 && !wmi_dhF_dequeueing$whas ; @@ -1341,33 +1349,27 @@ module mkSMAdapter4B(wciS0_Clk, // rule RL_wmi_dhF_both assign WILL_FIRE_RL_wmi_dhF_both = - ((wmi_dhF_c_r == 2'd1) ? - MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 : - wmi_dhF_c_r != 2'd2 || - MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3) && + MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 && wmi_dhF_dequeueing$whas && MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 ; // rule RL_wmrd_mesgResptoWsi assign WILL_FIRE_RL_wmrd_mesgResptoWsi = - wsiM_reqFifo_c_r != 2'd2 && respF_rRdPtr != respF_rWrPtr && + wsiM_reqFifo_cntr_r != 2'd2 && respF_rRdPtr != respF_rWrPtr && wci_wslv_cState == 3'd2 && (smaCtrl[3:0] == 4'h1 || smaCtrl[3:0] == 4'h4 || smaCtrl[3:0] == 4'h9) ; // rule RL_wci_cfwr assign WILL_FIRE_RL_wci_cfwr = - wci_wslv_respF_c_r != 2'd2 && wci_wslv_reqF$EMPTY_N && + wci_wslv_respF_cntr_r != 2'd2 && wci_wslv_reqF$EMPTY_N && wci_wslv_wci_cfwr_pw$whas && !WILL_FIRE_RL_wci_wslv_ctl_op_start && !WILL_FIRE_RL_wci_wslv_ctl_op_complete ; // rule RL_wsiM_reqFifo_incCtr assign WILL_FIRE_RL_wsiM_reqFifo_incCtr = - ((wsiM_reqFifo_c_r == 2'd0) ? - wsiM_reqFifo_enqueueing$whas : - wsiM_reqFifo_c_r != 2'd1 || wsiM_reqFifo_enqueueing$whas) && - wsiM_reqFifo_enqueueing$whas && + wsiM_reqFifo_enqueueing$whas && wsiM_reqFifo_enqueueing$whas && !WILL_FIRE_RL_wsiM_reqFifo_deq ; // rule RL_wsiM_reqFifo_decCtr @@ -1376,10 +1378,7 @@ module mkSMAdapter4B(wciS0_Clk, // rule RL_wsiM_reqFifo_both assign WILL_FIRE_RL_wsiM_reqFifo_both = - ((wsiM_reqFifo_c_r == 2'd1) ? - wsiM_reqFifo_enqueueing$whas : - wsiM_reqFifo_c_r != 2'd2 || wsiM_reqFifo_enqueueing$whas) && - WILL_FIRE_RL_wsiM_reqFifo_deq && + wsiM_reqFifo_enqueueing$whas && WILL_FIRE_RL_wsiM_reqFifo_deq && wsiM_reqFifo_enqueueing$whas ; // rule RL_wci_ctrl_IsO @@ -1391,27 +1390,22 @@ module mkSMAdapter4B(wciS0_Clk, // rule RL_wci_wslv_ctl_op_complete assign WILL_FIRE_RL_wci_wslv_ctl_op_complete = - wci_wslv_respF_c_r != 2'd2 && wci_wslv_ctlOpActive && + wci_wslv_respF_cntr_r != 2'd2 && wci_wslv_ctlOpActive && wci_wslv_ctlAckReg ; // rule RL_wci_wslv_respF_incCtr assign WILL_FIRE_RL_wci_wslv_respF_incCtr = - ((wci_wslv_respF_c_r == 2'd0) ? - wci_wslv_respF_x_wire$whas : - wci_wslv_respF_c_r != 2'd1 || wci_wslv_respF_x_wire$whas) && - wci_wslv_respF_enqueueing$whas && - !(wci_wslv_respF_c_r != 2'd0) ; + wci_wslv_respF_x_wire$whas && wci_wslv_respF_enqueueing$whas && + !(wci_wslv_respF_cntr_r != 2'd0) ; // rule RL_wci_wslv_respF_decCtr assign WILL_FIRE_RL_wci_wslv_respF_decCtr = - wci_wslv_respF_c_r != 2'd0 && !wci_wslv_respF_enqueueing$whas ; + wci_wslv_respF_cntr_r != 2'd0 && + !wci_wslv_respF_enqueueing$whas ; // rule RL_wci_wslv_respF_both assign WILL_FIRE_RL_wci_wslv_respF_both = - ((wci_wslv_respF_c_r == 2'd1) ? - wci_wslv_respF_x_wire$whas : - wci_wslv_respF_c_r != 2'd2 || wci_wslv_respF_x_wire$whas) && - wci_wslv_respF_c_r != 2'd0 && + wci_wslv_respF_x_wire$whas && wci_wslv_respF_cntr_r != 2'd0 && wci_wslv_respF_enqueueing$whas ; // rule RL_wsiS_reqFifo_enq @@ -1440,7 +1434,7 @@ module mkSMAdapter4B(wciS0_Clk, !wmi_sDataThreadBusy_d && unrollCnt == 16'd0 ; assign MUX_unrollCnt$write_1__SEL_2 = - wmi_respF_i_notEmpty__36_AND_smaCtrl_65_BIT_4__ETC___d541 && + wmi_respF_i_notEmpty__33_AND_smaCtrl_62_BIT_4__ETC___d538 && wci_wslv_cState == 3'd2 && (smaCtrl[3:0] == 4'h1 || smaCtrl[3:0] == 4'h4 || smaCtrl[3:0] == 4'h9) && @@ -1458,64 +1452,86 @@ module mkSMAdapter4B(wciS0_Clk, wci_wslv_reqF$D_OUT[36:34] == 3'd5 || wci_wslv_reqF$D_OUT[36:34] == 3'd6 || wci_wslv_reqF$D_OUT[36:34] == 3'd7) ; + assign MUX_wci_wslv_respF_q_0$write_1__SEL_1 = + WILL_FIRE_RL_wci_wslv_respF_both && _dfoo3 ; assign MUX_wci_wslv_respF_q_0$write_1__SEL_2 = WILL_FIRE_RL_wci_wslv_respF_incCtr && - wci_wslv_respF_c_r == 2'd0 ; + wci_wslv_respF_cntr_r == 2'd0 ; + assign MUX_wci_wslv_respF_q_1$write_1__SEL_1 = + WILL_FIRE_RL_wci_wslv_respF_both && _dfoo1 ; assign MUX_wci_wslv_respF_q_1$write_1__SEL_2 = WILL_FIRE_RL_wci_wslv_respF_incCtr && - wci_wslv_respF_c_r == 2'd1 ; + wci_wslv_respF_cntr_r == 2'd1 ; + assign MUX_wmi_dhF_q_0$write_1__SEL_1 = + WILL_FIRE_RL_wmi_dhF_incCtr && wmi_dhF_cntr_r == 2'd0 ; assign MUX_wmi_dhF_q_0$write_1__SEL_2 = - WILL_FIRE_RL_wmi_dhF_incCtr && wmi_dhF_c_r == 2'd0 ; + WILL_FIRE_RL_wmi_dhF_both && _dfoo15 ; + assign MUX_wmi_dhF_q_1$write_1__SEL_1 = + WILL_FIRE_RL_wmi_dhF_incCtr && wmi_dhF_cntr_r == 2'd1 ; assign MUX_wmi_dhF_q_1$write_1__SEL_2 = - WILL_FIRE_RL_wmi_dhF_incCtr && wmi_dhF_c_r == 2'd1 ; + WILL_FIRE_RL_wmi_dhF_both && _dfoo13 ; + assign MUX_wmi_mFlagF_q_0$write_1__SEL_1 = + WILL_FIRE_RL_wmi_mFlagF_both && _dfoo11 ; assign MUX_wmi_mFlagF_q_0$write_1__SEL_2 = - WILL_FIRE_RL_wmi_mFlagF_incCtr && wmi_mFlagF_c_r == 2'd0 ; + WILL_FIRE_RL_wmi_mFlagF_incCtr && wmi_mFlagF_cntr_r == 2'd0 ; + assign MUX_wmi_mFlagF_q_1$write_1__SEL_1 = + WILL_FIRE_RL_wmi_mFlagF_both && _dfoo9 ; assign MUX_wmi_mFlagF_q_1$write_1__SEL_2 = - WILL_FIRE_RL_wmi_mFlagF_incCtr && wmi_mFlagF_c_r == 2'd1 ; + WILL_FIRE_RL_wmi_mFlagF_incCtr && wmi_mFlagF_cntr_r == 2'd1 ; assign MUX_wmi_mFlagF_x_wire$wset_1__SEL_1 = - WILL_FIRE_RL_wmrd_mesgBodyRequest && x__h18954 ; + WILL_FIRE_RL_wmrd_mesgBodyRequest && x__h18328 ; + assign MUX_wmi_reqF_q_0$write_1__SEL_1 = + WILL_FIRE_RL_wmi_reqF_both && _dfoo7 ; assign MUX_wmi_reqF_q_0$write_1__SEL_2 = - WILL_FIRE_RL_wmi_reqF_incCtr && wmi_reqF_c_r == 2'd0 ; + WILL_FIRE_RL_wmi_reqF_incCtr && wmi_reqF_cntr_r == 2'd0 ; + assign MUX_wmi_reqF_q_1$write_1__SEL_1 = + WILL_FIRE_RL_wmi_reqF_both && _dfoo5 ; assign MUX_wmi_reqF_q_1$write_1__SEL_2 = - WILL_FIRE_RL_wmi_reqF_incCtr && wmi_reqF_c_r == 2'd1 ; + WILL_FIRE_RL_wmi_reqF_incCtr && wmi_reqF_cntr_r == 2'd1 ; + assign MUX_wsiM_reqFifo_q_0$write_1__SEL_1 = + WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_cntr_r == 2'd0 ; assign MUX_wsiM_reqFifo_q_0$write_1__SEL_2 = - WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_c_r == 2'd0 ; + WILL_FIRE_RL_wsiM_reqFifo_both && _dfoo19 ; + assign MUX_wsiM_reqFifo_q_1$write_1__SEL_1 = + WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_cntr_r == 2'd1 ; assign MUX_wsiM_reqFifo_q_1$write_1__SEL_2 = - WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_c_r == 2'd1 ; + WILL_FIRE_RL_wsiM_reqFifo_both && _dfoo17 ; assign MUX_wsiM_reqFifo_x_wire$wset_1__SEL_1 = + WILL_FIRE_RL_wsipass_doMessagePush && !smaCtrl[4] ; + assign MUX_wsiM_reqFifo_x_wire$wset_1__SEL_2 = MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 && smaCtrl[3:0] == 4'h3 ; - assign MUX_wsiM_reqFifo_x_wire$wset_1__SEL_2 = - WILL_FIRE_RL_wsipass_doMessagePush && !smaCtrl[4] ; assign MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 = CAN_FIRE_RL_wmwt_messagePush && !WILL_FIRE_RL_wmwt_messageFinalize ; assign MUX_fabRespCredit_value$write_1__VAL_2 = fabRespCredit_value + - (WILL_FIRE_RL_wmrd_mesgBodyRequest ? b__h15473 : 12'd0) + + (WILL_FIRE_RL_wmrd_mesgBodyRequest ? b__h14802 : 12'd0) + (WILL_FIRE_RL_wmrd_mesgResptoWsi ? 12'd1 : 12'd0) ; assign MUX_fabWordsRemain$write_1__VAL_1 = - (wmi_sFlagReg[23:0] == 24'd0) ? 14'd1 : b__h18410[13:0] ; + (wmi_sFlagReg[23:0] == 24'd0) ? 14'd1 : b__h17784[13:0] ; assign MUX_fabWordsRemain$write_1__VAL_2 = fabWordsRemain - fabWordsCurReq ; - assign MUX_mesgCount$write_1__VAL_2 = mesgCount + 32'd1 ; + assign MUX_mesgCount$write_1__VAL_1 = mesgCount + 32'd1 ; + assign MUX_mesgLengthSoFar$write_1__VAL_1 = + mesgLengthSoFar + mlInc__h22205 ; assign MUX_mesgReqAddr$write_1__VAL_2 = mesgReqAddr + { fabWordsCurReq[11:0], 2'd0 } ; assign MUX_opcode$write_1__VAL_3 = { 1'd1, wsiS_reqFifo$D_OUT[7:0] } ; assign MUX_thisMesg$write_1__VAL_1 = - { mesgCount[7:0], mesgMetaF_opcode__h23695, x_length__h24096 } ; + { mesgCount[7:0], mesgMetaF_opcode__h22372, x_length__h22772 } ; assign MUX_thisMesg$write_1__VAL_2 = { mesgCount[7:0], wmi_sFlagReg[31:24], wmi_sFlagReg[15:0] } ; assign MUX_unrollCnt$write_1__VAL_1 = - (wmi_sFlagReg[23:0] == 24'd0) ? 16'd1 : b__h18410[15:0] ; + (wmi_sFlagReg[23:0] == 24'd0) ? 16'd1 : b__h17784[15:0] ; assign MUX_unrollCnt$write_1__VAL_2 = unrollCnt - 16'd1 ; assign MUX_wci_wslv_illegalEdge$write_1__VAL_1 = wci_wslv_reqF$D_OUT[36:34] != 3'd4 && wci_wslv_reqF$D_OUT[36:34] != 3'd5 && wci_wslv_reqF$D_OUT[36:34] != 3'd6 ; - assign MUX_wci_wslv_respF_c_r$write_1__VAL_1 = wci_wslv_respF_c_r + 2'd1 ; - assign MUX_wci_wslv_respF_c_r$write_1__VAL_2 = wci_wslv_respF_c_r - 2'd1 ; + assign MUX_wci_wslv_respF_cntr_r$write_1__VAL_2 = + wci_wslv_respF_cntr_r + 2'd1 ; assign MUX_wci_wslv_respF_q_0$write_1__VAL_1 = - (wci_wslv_respF_c_r == 2'd1) ? + (wci_wslv_respF_cntr_r == 2'd1) ? MUX_wci_wslv_respF_q_0$write_1__VAL_2 : wci_wslv_respF_q_1 ; always@(WILL_FIRE_RL_wci_wslv_ctl_op_complete or @@ -1537,34 +1553,33 @@ module mkSMAdapter4B(wciS0_Clk, endcase end assign MUX_wci_wslv_respF_q_1$write_1__VAL_1 = - (wci_wslv_respF_c_r == 2'd2) ? + (wci_wslv_respF_cntr_r == 2'd2) ? MUX_wci_wslv_respF_q_0$write_1__VAL_2 : 34'h0AAAAAAAA ; assign MUX_wci_wslv_respF_x_wire$wset_1__VAL_1 = wci_wslv_illegalEdge ? 34'h3C0DE4202 : 34'h1C0DE4201 ; - assign MUX_wci_wslv_respF_x_wire$wset_1__VAL_2 = { 2'd1, g_data__h25073 } ; - assign MUX_wmi_dhF_c_r$write_1__VAL_1 = wmi_dhF_c_r + 2'd1 ; - assign MUX_wmi_dhF_c_r$write_1__VAL_2 = wmi_dhF_c_r - 2'd1 ; + assign MUX_wci_wslv_respF_x_wire$wset_1__VAL_2 = { 2'd1, g_data__h23748 } ; + assign MUX_wmi_dhF_cntr_r$write_1__VAL_2 = wmi_dhF_cntr_r + 2'd1 ; assign MUX_wmi_dhF_q_0$write_1__VAL_1 = - (wmi_dhF_c_r == 2'd1) ? - MUX_wmi_dhF_q_0$write_1__VAL_2 : - wmi_dhF_q_1 ; - assign MUX_wmi_dhF_q_0$write_1__VAL_2 = { 1'd1, wsiS_reqFifo$D_OUT[57], wsiS_reqFifo$D_OUT[43:8] } ; - assign MUX_wmi_dhF_q_1$write_1__VAL_1 = - (wmi_dhF_c_r == 2'd2) ? MUX_wmi_dhF_q_0$write_1__VAL_2 : 38'd0 ; - assign MUX_wmi_mFlagF_c_r$write_1__VAL_1 = wmi_mFlagF_c_r + 2'd1 ; - assign MUX_wmi_mFlagF_c_r$write_1__VAL_2 = wmi_mFlagF_c_r - 2'd1 ; + assign MUX_wmi_dhF_q_0$write_1__VAL_2 = + (wmi_dhF_cntr_r == 2'd1) ? + MUX_wmi_dhF_q_0$write_1__VAL_1 : + wmi_dhF_q_1 ; + assign MUX_wmi_dhF_q_1$write_1__VAL_2 = + (wmi_dhF_cntr_r == 2'd2) ? + MUX_wmi_dhF_q_0$write_1__VAL_1 : + 38'd0 ; + assign MUX_wmi_mFlagF_cntr_r$write_1__VAL_2 = wmi_mFlagF_cntr_r + 2'd1 ; assign MUX_wmi_mFlagF_q_0$write_1__VAL_1 = - (wmi_mFlagF_c_r == 2'd1) ? value__h6702 : wmi_mFlagF_q_1 ; + (wmi_mFlagF_cntr_r == 2'd1) ? value__h6387 : wmi_mFlagF_q_1 ; assign MUX_wmi_mFlagF_q_1$write_1__VAL_1 = - (wmi_mFlagF_c_r == 2'd2) ? value__h6702 : 32'd0 ; + (wmi_mFlagF_cntr_r == 2'd2) ? value__h6387 : 32'd0 ; assign MUX_wmi_mFlagF_x_wire$wset_1__VAL_2 = - { mesgMetaF_opcode__h23695, mesgMetaF_length__h23696 } ; - assign MUX_wmi_reqF_c_r$write_1__VAL_1 = wmi_reqF_c_r + 2'd1 ; - assign MUX_wmi_reqF_c_r$write_1__VAL_2 = wmi_reqF_c_r - 2'd1 ; + { mesgMetaF_opcode__h22372, mesgMetaF_length__h22373 } ; + assign MUX_wmi_reqF_cntr_r$write_1__VAL_2 = wmi_reqF_cntr_r + 2'd1 ; assign MUX_wmi_reqF_q_0$write_1__VAL_1 = - (wmi_reqF_c_r == 2'd1) ? + (wmi_reqF_cntr_r == 2'd1) ? MUX_wmi_reqF_q_0$write_1__VAL_2 : wmi_reqF_q_1 ; assign MUX_wmi_reqF_q_0$write_1__VAL_2 = @@ -1572,27 +1587,27 @@ module mkSMAdapter4B(wciS0_Clk, MUX_wmi_reqF_x_wire$wset_1__VAL_1 : MUX_wmi_reqF_x_wire$wset_1__VAL_2 ; assign MUX_wmi_reqF_q_1$write_1__VAL_1 = - (wmi_reqF_c_r == 2'd2) ? + (wmi_reqF_cntr_r == 2'd2) ? MUX_wmi_reqF_q_0$write_1__VAL_2 : 32'd0 ; assign MUX_wmi_reqF_x_wire$wset_1__VAL_1 = - { 4'd5, x__h18954, 1'b0, mesgReqAddr, fabWordsCurReq[11:0] } ; + { 4'd5, x__h18328, 1'b0, mesgReqAddr, fabWordsCurReq[11:0] } ; assign MUX_wmi_reqF_x_wire$wset_1__VAL_2 = { 4'd3, wsiS_reqFifo$D_OUT[57], 1'b0, mesgLengthSoFar, 12'd1 } ; - assign MUX_wsiM_reqFifo_c_r$write_1__VAL_1 = wsiM_reqFifo_c_r + 2'd1 ; - assign MUX_wsiM_reqFifo_c_r$write_1__VAL_2 = wsiM_reqFifo_c_r - 2'd1 ; + assign MUX_wsiM_reqFifo_cntr_r$write_1__VAL_1 = wsiM_reqFifo_cntr_r - 2'd1 ; + assign MUX_wsiM_reqFifo_cntr_r$write_1__VAL_2 = wsiM_reqFifo_cntr_r + 2'd1 ; assign MUX_wsiM_reqFifo_q_0$write_1__VAL_1 = - (wsiM_reqFifo_c_r == 2'd1) ? - MUX_wsiM_reqFifo_q_0$write_1__VAL_2 : - wsiM_reqFifo_q_1 ; - assign MUX_wsiM_reqFifo_q_0$write_1__VAL_2 = (MUX_wsiM_reqFifo_x_wire$wset_1__SEL_1 || MUX_wsiM_reqFifo_x_wire$wset_1__SEL_2) ? wsiS_reqFifo$D_OUT : MUX_wsiM_reqFifo_x_wire$wset_1__VAL_3 ; - assign MUX_wsiM_reqFifo_q_1$write_1__VAL_1 = - (wsiM_reqFifo_c_r == 2'd2) ? - MUX_wsiM_reqFifo_q_0$write_1__VAL_2 : + assign MUX_wsiM_reqFifo_q_0$write_1__VAL_2 = + (wsiM_reqFifo_cntr_r == 2'd1) ? + MUX_wsiM_reqFifo_q_0$write_1__VAL_1 : + wsiM_reqFifo_q_1 ; + assign MUX_wsiM_reqFifo_q_1$write_1__VAL_2 = + (wsiM_reqFifo_cntr_r == 2'd2) ? + MUX_wsiM_reqFifo_q_0$write_1__VAL_1 : 61'h00000AAAAAAAAA00 ; assign MUX_wsiM_reqFifo_x_wire$wset_1__VAL_3 = (respF_rCache[73] && respF_rCache[72:61] == respF_rRdPtr) ? @@ -1633,9 +1648,9 @@ module mkSMAdapter4B(wciS0_Clk, assign wmi_reqF_x_wire$whas = WILL_FIRE_RL_wmrd_mesgBodyRequest || MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 ; - assign wmi_mFlagF_x_wire$wget = value__h6702 ; + assign wmi_mFlagF_x_wire$wget = value__h6387 ; assign wmi_mFlagF_x_wire$whas = wmi_mFlagF_enqueueing$whas ; - assign wmi_dhF_x_wire$wget = MUX_wmi_dhF_q_0$write_1__VAL_2 ; + assign wmi_dhF_x_wire$wget = MUX_wmi_dhF_q_0$write_1__VAL_1 ; assign wmi_dhF_x_wire$whas = MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 ; assign wmi_wmiResponse$wget = { wmiM0_SResp, wmiM0_SData } ; assign wmi_wmiResponse$whas = 1'd1 ; @@ -1647,7 +1662,7 @@ module mkSMAdapter4B(wciS0_Clk, assign wmi_operateD_1$whas = wci_wslv_cState == 3'd2 ; assign wmi_peerIsReady_1$wget = 1'd1 ; assign wmi_peerIsReady_1$whas = wmiM0_SReset_n ; - assign wsiM_reqFifo_x_wire$wget = MUX_wsiM_reqFifo_q_0$write_1__VAL_2 ; + assign wsiM_reqFifo_x_wire$wget = MUX_wsiM_reqFifo_q_0$write_1__VAL_1 ; assign wsiM_reqFifo_x_wire$whas = wsiM_reqFifo_enqueueing$whas ; assign wsiM_operateD_1$wget = 1'd1 ; assign wsiM_operateD_1$whas = wci_wslv_cState == 3'd2 ; @@ -1669,7 +1684,7 @@ module mkSMAdapter4B(wciS0_Clk, assign wsiS_sThreadBusy_dw$wget = wsiS_reqFifo_countReg > 2'd1 ; assign wsiS_sThreadBusy_dw$whas = wsiS_reqFifo_levelsValid && wsiS_operateD && wsiS_peerIsReady ; - assign fabRespCredit_acc_v1$wget = b__h15473 ; + assign fabRespCredit_acc_v1$wget = b__h14802 ; assign fabRespCredit_acc_v1$whas = WILL_FIRE_RL_wmrd_mesgBodyRequest ; assign fabRespCredit_acc_v2$wget = 12'd1 ; assign fabRespCredit_acc_v2$whas = WILL_FIRE_RL_wmrd_mesgResptoWsi ; @@ -1679,9 +1694,9 @@ module mkSMAdapter4B(wciS0_Clk, { 3'd1, unrollCnt == 16'd1, !smaCtrl[5], - sendData_burstLength__h19243, + sendData_burstLength__h18617, wmi_respF$D_OUT[31:0], - sendData_byteEn__h19245, + sendData_byteEn__h18619, thisMesg[23:16] } ; assign respF_wDataIn$whas = respF_pwEnqueue$whas ; assign respF_wDataOut$wget = MUX_wsiM_reqFifo_x_wire$wset_1__VAL_3 ; @@ -1708,7 +1723,7 @@ module mkSMAdapter4B(wciS0_Clk, assign wci_wslv_respF_enqueueing$whas = WILL_FIRE_RL_wci_cfrd || WILL_FIRE_RL_wci_cfwr || WILL_FIRE_RL_wci_wslv_ctl_op_complete ; - assign wci_wslv_respF_dequeueing$whas = wci_wslv_respF_c_r != 2'd0 ; + assign wci_wslv_respF_dequeueing$whas = wci_wslv_respF_cntr_r != 2'd0 ; assign wci_wslv_sThreadBusy_pw$whas = 1'b0 ; assign wci_wslv_wci_cfwr_pw$whas = wci_wslv_reqF$EMPTY_N && wci_wslv_reqF$D_OUT[68] && @@ -1723,23 +1738,23 @@ module mkSMAdapter4B(wciS0_Clk, MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 || WILL_FIRE_RL_wmrd_mesgBodyRequest ; assign wmi_reqF_dequeueing$whas = - WILL_FIRE_RL_wmi_reqF_deq && wmi_reqF_c_r != 2'd0 ; + WILL_FIRE_RL_wmi_reqF_deq && wmi_reqF_cntr_r != 2'd0 ; assign wmi_mFlagF_enqueueing$whas = - WILL_FIRE_RL_wmrd_mesgBodyRequest && x__h18954 || + WILL_FIRE_RL_wmrd_mesgBodyRequest && x__h18328 || MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 && wsiS_reqFifo$D_OUT[57] ; assign wmi_mFlagF_dequeueing$whas = WILL_FIRE_RL_wmi_reqF_deq && wmi_reqF_q_0[27] && - wmi_mFlagF_c_r != 2'd0 ; + wmi_mFlagF_cntr_r != 2'd0 ; assign wmi_dhF_enqueueing$whas = MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 ; assign wmi_dhF_dequeueing$whas = wmi_operateD && wmi_peerIsReady && !wmi_sDataThreadBusy_d && - wmi_dhF_c_r != 2'd0 ; + wmi_dhF_cntr_r != 2'd0 ; assign wsiM_reqFifo_enqueueing$whas = + WILL_FIRE_RL_wsipass_doMessagePush && !smaCtrl[4] || MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 && smaCtrl[3:0] == 4'h3 || - WILL_FIRE_RL_wsipass_doMessagePush && !smaCtrl[4] || WILL_FIRE_RL_wmrd_mesgResptoWsi ; assign wsiM_reqFifo_dequeueing$whas = WILL_FIRE_RL_wsiM_reqFifo_deq ; assign wsiM_sThreadBusy_pw$whas = wsiM0_SThreadBusy ; @@ -1753,6 +1768,7 @@ module mkSMAdapter4B(wciS0_Clk, assign wsiS_reqFifo_doResetClr$whas = 1'b0 ; assign respF_pwDequeue$whas = WILL_FIRE_RL_wmrd_mesgResptoWsi ; assign respF_pwEnqueue$whas = MUX_unrollCnt$write_1__SEL_2 && !smaCtrl[4] ; + assign respF_pwClear$whas = 1'b0 ; assign wsi_Es_mReqLast_w$whas = wsiS0_MReqLast ; assign wsi_Es_mBurstPrecise_w$whas = wsiS0_MBurstPrecise ; assign wsi_Es_mDataInfo_w$whas = 1'd1 ; @@ -1793,7 +1809,7 @@ module mkSMAdapter4B(wciS0_Clk, // register fabWordsCurReq assign fabWordsCurReq$D_IN = - (fabWordsRemain <= b__h18783) ? fabWordsRemain : b__h18783 ; + (fabWordsRemain <= b__h18157) ? fabWordsRemain : b__h18157 ; assign fabWordsCurReq$EN = MUX_mesgReqOK$write_1__SEL_3 ; // register fabWordsRemain @@ -1823,14 +1839,14 @@ module mkSMAdapter4B(wciS0_Clk, // register mesgCount always@(MUX_mesgCount$write_1__SEL_1 or - MUX_mesgCount$write_1__VAL_2 or + MUX_mesgCount$write_1__VAL_1 or WILL_FIRE_RL_wmwt_messageFinalize or WILL_FIRE_RL_wci_ctrl_IsO) begin case (1'b1) // synopsys parallel_case MUX_mesgCount$write_1__SEL_1: - mesgCount$D_IN = MUX_mesgCount$write_1__VAL_2; + mesgCount$D_IN = MUX_mesgCount$write_1__VAL_1; WILL_FIRE_RL_wmwt_messageFinalize: - mesgCount$D_IN = MUX_mesgCount$write_1__VAL_2; + mesgCount$D_IN = MUX_mesgCount$write_1__VAL_1; WILL_FIRE_RL_wci_ctrl_IsO: mesgCount$D_IN = 32'd0; default: mesgCount$D_IN = 32'hAAAAAAAA /* unspecified value */ ; endcase @@ -1843,7 +1859,7 @@ module mkSMAdapter4B(wciS0_Clk, // register mesgLengthSoFar assign mesgLengthSoFar$D_IN = MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 ? - mlB__h23529 : + MUX_mesgLengthSoFar$write_1__VAL_1 : 14'd0 ; assign mesgLengthSoFar$EN = MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 || @@ -1878,9 +1894,8 @@ module mkSMAdapter4B(wciS0_Clk, 9'd170 : MUX_opcode$write_1__VAL_3 ; assign opcode$EN = - WILL_FIRE_RL_wmwt_mesgBegin || - WILL_FIRE_RL_wmwt_messageFinalize || - WILL_FIRE_RL_wmwt_doAbort ; + WILL_FIRE_RL_wmwt_messageFinalize || WILL_FIRE_RL_wmwt_doAbort || + WILL_FIRE_RL_wmwt_mesgBegin ; // register readyToPush assign readyToPush$D_IN = @@ -1899,18 +1914,18 @@ module mkSMAdapter4B(wciS0_Clk, assign respF_rCache$D_IN = { 1'd1, respF_rWrPtr, - IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d889, + IF_respF_wDataIn_whas__28_THEN_respF_wDataIn_w_ETC___d431, respF_pwEnqueue$whas && respF_wDataIn$wget[57], respF_pwEnqueue$whas && respF_wDataIn$wget[56], - IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d881 } ; + IF_respF_wDataIn_whas__28_THEN_respF_wDataIn_w_ETC___d437 } ; assign respF_rCache$EN = respF_pwEnqueue$whas ; // register respF_rRdPtr - assign respF_rRdPtr$D_IN = x__h16878 ; + assign respF_rRdPtr$D_IN = x__h16253 ; assign respF_rRdPtr$EN = WILL_FIRE_RL_wmrd_mesgResptoWsi ; // register respF_rWrPtr - assign respF_rWrPtr$D_IN = respF_rWrPtr + 12'd1 ; + assign respF_rWrPtr$D_IN = x__h16103 ; assign respF_rWrPtr$EN = respF_pwEnqueue$whas ; // register smaCtrl @@ -2014,24 +2029,24 @@ module mkSMAdapter4B(wciS0_Clk, (wci_wslv_wciReq$wget[71:69] != 3'd0) != wci_wslv_reqF_r_deq$whas ; - // register wci_wslv_respF_c_r - assign wci_wslv_respF_c_r$D_IN = - WILL_FIRE_RL_wci_wslv_respF_incCtr ? - MUX_wci_wslv_respF_c_r$write_1__VAL_1 : - MUX_wci_wslv_respF_c_r$write_1__VAL_2 ; - assign wci_wslv_respF_c_r$EN = - WILL_FIRE_RL_wci_wslv_respF_incCtr || - WILL_FIRE_RL_wci_wslv_respF_decCtr ; + // register wci_wslv_respF_cntr_r + assign wci_wslv_respF_cntr_r$D_IN = + WILL_FIRE_RL_wci_wslv_respF_decCtr ? + wci_wslv_respF_cntr_r_8_MINUS_1___d27 : + MUX_wci_wslv_respF_cntr_r$write_1__VAL_2 ; + assign wci_wslv_respF_cntr_r$EN = + WILL_FIRE_RL_wci_wslv_respF_decCtr || + WILL_FIRE_RL_wci_wslv_respF_incCtr ; // register wci_wslv_respF_q_0 - always@(WILL_FIRE_RL_wci_wslv_respF_both or + always@(MUX_wci_wslv_respF_q_0$write_1__SEL_1 or MUX_wci_wslv_respF_q_0$write_1__VAL_1 or MUX_wci_wslv_respF_q_0$write_1__SEL_2 or MUX_wci_wslv_respF_q_0$write_1__VAL_2 or WILL_FIRE_RL_wci_wslv_respF_decCtr or wci_wslv_respF_q_1) begin case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_wci_wslv_respF_both: + MUX_wci_wslv_respF_q_0$write_1__SEL_1: wci_wslv_respF_q_0$D_IN = MUX_wci_wslv_respF_q_0$write_1__VAL_1; MUX_wci_wslv_respF_q_0$write_1__SEL_2: wci_wslv_respF_q_0$D_IN = MUX_wci_wslv_respF_q_0$write_1__VAL_2; @@ -2042,20 +2057,20 @@ module mkSMAdapter4B(wciS0_Clk, endcase end assign wci_wslv_respF_q_0$EN = - WILL_FIRE_RL_wci_wslv_respF_both || + WILL_FIRE_RL_wci_wslv_respF_both && _dfoo3 || WILL_FIRE_RL_wci_wslv_respF_incCtr && - wci_wslv_respF_c_r == 2'd0 || + wci_wslv_respF_cntr_r == 2'd0 || WILL_FIRE_RL_wci_wslv_respF_decCtr ; // register wci_wslv_respF_q_1 - always@(WILL_FIRE_RL_wci_wslv_respF_both or + always@(MUX_wci_wslv_respF_q_1$write_1__SEL_1 or MUX_wci_wslv_respF_q_1$write_1__VAL_1 or MUX_wci_wslv_respF_q_1$write_1__SEL_2 or MUX_wci_wslv_respF_q_0$write_1__VAL_2 or WILL_FIRE_RL_wci_wslv_respF_decCtr) begin case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_wci_wslv_respF_both: + MUX_wci_wslv_respF_q_1$write_1__SEL_1: wci_wslv_respF_q_1$D_IN = MUX_wci_wslv_respF_q_1$write_1__VAL_1; MUX_wci_wslv_respF_q_1$write_1__SEL_2: wci_wslv_respF_q_1$D_IN = MUX_wci_wslv_respF_q_0$write_1__VAL_2; @@ -2066,9 +2081,9 @@ module mkSMAdapter4B(wciS0_Clk, endcase end assign wci_wslv_respF_q_1$EN = - WILL_FIRE_RL_wci_wslv_respF_both || + WILL_FIRE_RL_wci_wslv_respF_both && _dfoo1 || WILL_FIRE_RL_wci_wslv_respF_incCtr && - wci_wslv_respF_c_r == 2'd1 || + wci_wslv_respF_cntr_r == 2'd1 || WILL_FIRE_RL_wci_wslv_respF_decCtr ; // register wci_wslv_sFlagReg @@ -2083,23 +2098,23 @@ module mkSMAdapter4B(wciS0_Clk, assign wmi_busyWithMessage$D_IN = 1'b0 ; assign wmi_busyWithMessage$EN = 1'b0 ; - // register wmi_dhF_c_r - assign wmi_dhF_c_r$D_IN = - WILL_FIRE_RL_wmi_dhF_incCtr ? - MUX_wmi_dhF_c_r$write_1__VAL_1 : - MUX_wmi_dhF_c_r$write_1__VAL_2 ; - assign wmi_dhF_c_r$EN = - WILL_FIRE_RL_wmi_dhF_incCtr || WILL_FIRE_RL_wmi_dhF_decCtr ; + // register wmi_dhF_cntr_r + assign wmi_dhF_cntr_r$D_IN = + WILL_FIRE_RL_wmi_dhF_decCtr ? + wmi_dhF_cntr_r_05_MINUS_1___d213 : + MUX_wmi_dhF_cntr_r$write_1__VAL_2 ; + assign wmi_dhF_cntr_r$EN = + WILL_FIRE_RL_wmi_dhF_decCtr || WILL_FIRE_RL_wmi_dhF_incCtr ; // register wmi_dhF_q_0 - always@(WILL_FIRE_RL_wmi_dhF_both or + always@(MUX_wmi_dhF_q_0$write_1__SEL_1 or MUX_wmi_dhF_q_0$write_1__VAL_1 or MUX_wmi_dhF_q_0$write_1__SEL_2 or MUX_wmi_dhF_q_0$write_1__VAL_2 or WILL_FIRE_RL_wmi_dhF_decCtr or wmi_dhF_q_1) begin case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_wmi_dhF_both: + MUX_wmi_dhF_q_0$write_1__SEL_1: wmi_dhF_q_0$D_IN = MUX_wmi_dhF_q_0$write_1__VAL_1; MUX_wmi_dhF_q_0$write_1__SEL_2: wmi_dhF_q_0$D_IN = MUX_wmi_dhF_q_0$write_1__VAL_2; @@ -2108,28 +2123,28 @@ module mkSMAdapter4B(wciS0_Clk, endcase end assign wmi_dhF_q_0$EN = - WILL_FIRE_RL_wmi_dhF_both || - WILL_FIRE_RL_wmi_dhF_incCtr && wmi_dhF_c_r == 2'd0 || + WILL_FIRE_RL_wmi_dhF_incCtr && wmi_dhF_cntr_r == 2'd0 || + WILL_FIRE_RL_wmi_dhF_both && _dfoo15 || WILL_FIRE_RL_wmi_dhF_decCtr ; // register wmi_dhF_q_1 - always@(WILL_FIRE_RL_wmi_dhF_both or - MUX_wmi_dhF_q_1$write_1__VAL_1 or + always@(MUX_wmi_dhF_q_1$write_1__SEL_1 or + MUX_wmi_dhF_q_0$write_1__VAL_1 or MUX_wmi_dhF_q_1$write_1__SEL_2 or - MUX_wmi_dhF_q_0$write_1__VAL_2 or WILL_FIRE_RL_wmi_dhF_decCtr) + MUX_wmi_dhF_q_1$write_1__VAL_2 or WILL_FIRE_RL_wmi_dhF_decCtr) begin case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_wmi_dhF_both: - wmi_dhF_q_1$D_IN = MUX_wmi_dhF_q_1$write_1__VAL_1; + MUX_wmi_dhF_q_1$write_1__SEL_1: + wmi_dhF_q_1$D_IN = MUX_wmi_dhF_q_0$write_1__VAL_1; MUX_wmi_dhF_q_1$write_1__SEL_2: - wmi_dhF_q_1$D_IN = MUX_wmi_dhF_q_0$write_1__VAL_2; + wmi_dhF_q_1$D_IN = MUX_wmi_dhF_q_1$write_1__VAL_2; WILL_FIRE_RL_wmi_dhF_decCtr: wmi_dhF_q_1$D_IN = 38'd0; default: wmi_dhF_q_1$D_IN = 38'h2AAAAAAAAA /* unspecified value */ ; endcase end assign wmi_dhF_q_1$EN = - WILL_FIRE_RL_wmi_dhF_both || - WILL_FIRE_RL_wmi_dhF_incCtr && wmi_dhF_c_r == 2'd1 || + WILL_FIRE_RL_wmi_dhF_incCtr && wmi_dhF_cntr_r == 2'd1 || + WILL_FIRE_RL_wmi_dhF_both && _dfoo13 || WILL_FIRE_RL_wmi_dhF_decCtr ; // register wmi_errorSticky @@ -2140,51 +2155,51 @@ module mkSMAdapter4B(wciS0_Clk, assign wmi_isReset_isInReset$D_IN = 1'd0 ; assign wmi_isReset_isInReset$EN = wmi_isReset_isInReset ; - // register wmi_mFlagF_c_r - assign wmi_mFlagF_c_r$D_IN = - WILL_FIRE_RL_wmi_mFlagF_incCtr ? - MUX_wmi_mFlagF_c_r$write_1__VAL_1 : - MUX_wmi_mFlagF_c_r$write_1__VAL_2 ; - assign wmi_mFlagF_c_r$EN = - WILL_FIRE_RL_wmi_mFlagF_incCtr || - WILL_FIRE_RL_wmi_mFlagF_decCtr ; + // register wmi_mFlagF_cntr_r + assign wmi_mFlagF_cntr_r$D_IN = + WILL_FIRE_RL_wmi_mFlagF_decCtr ? + wmi_mFlagF_cntr_r_83_MINUS_1___d191 : + MUX_wmi_mFlagF_cntr_r$write_1__VAL_2 ; + assign wmi_mFlagF_cntr_r$EN = + WILL_FIRE_RL_wmi_mFlagF_decCtr || + WILL_FIRE_RL_wmi_mFlagF_incCtr ; // register wmi_mFlagF_q_0 - always@(WILL_FIRE_RL_wmi_mFlagF_both or + always@(MUX_wmi_mFlagF_q_0$write_1__SEL_1 or MUX_wmi_mFlagF_q_0$write_1__VAL_1 or MUX_wmi_mFlagF_q_0$write_1__SEL_2 or - value__h6702 or WILL_FIRE_RL_wmi_mFlagF_decCtr or wmi_mFlagF_q_1) + value__h6387 or WILL_FIRE_RL_wmi_mFlagF_decCtr or wmi_mFlagF_q_1) begin case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_wmi_mFlagF_both: + MUX_wmi_mFlagF_q_0$write_1__SEL_1: wmi_mFlagF_q_0$D_IN = MUX_wmi_mFlagF_q_0$write_1__VAL_1; - MUX_wmi_mFlagF_q_0$write_1__SEL_2: wmi_mFlagF_q_0$D_IN = value__h6702; + MUX_wmi_mFlagF_q_0$write_1__SEL_2: wmi_mFlagF_q_0$D_IN = value__h6387; WILL_FIRE_RL_wmi_mFlagF_decCtr: wmi_mFlagF_q_0$D_IN = wmi_mFlagF_q_1; default: wmi_mFlagF_q_0$D_IN = 32'hAAAAAAAA /* unspecified value */ ; endcase end assign wmi_mFlagF_q_0$EN = - WILL_FIRE_RL_wmi_mFlagF_both || - WILL_FIRE_RL_wmi_mFlagF_incCtr && wmi_mFlagF_c_r == 2'd0 || + WILL_FIRE_RL_wmi_mFlagF_both && _dfoo11 || + WILL_FIRE_RL_wmi_mFlagF_incCtr && wmi_mFlagF_cntr_r == 2'd0 || WILL_FIRE_RL_wmi_mFlagF_decCtr ; // register wmi_mFlagF_q_1 - always@(WILL_FIRE_RL_wmi_mFlagF_both or + always@(MUX_wmi_mFlagF_q_1$write_1__SEL_1 or MUX_wmi_mFlagF_q_1$write_1__VAL_1 or MUX_wmi_mFlagF_q_1$write_1__SEL_2 or - value__h6702 or WILL_FIRE_RL_wmi_mFlagF_decCtr) + value__h6387 or WILL_FIRE_RL_wmi_mFlagF_decCtr) begin case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_wmi_mFlagF_both: + MUX_wmi_mFlagF_q_1$write_1__SEL_1: wmi_mFlagF_q_1$D_IN = MUX_wmi_mFlagF_q_1$write_1__VAL_1; - MUX_wmi_mFlagF_q_1$write_1__SEL_2: wmi_mFlagF_q_1$D_IN = value__h6702; + MUX_wmi_mFlagF_q_1$write_1__SEL_2: wmi_mFlagF_q_1$D_IN = value__h6387; WILL_FIRE_RL_wmi_mFlagF_decCtr: wmi_mFlagF_q_1$D_IN = 32'd0; default: wmi_mFlagF_q_1$D_IN = 32'hAAAAAAAA /* unspecified value */ ; endcase end assign wmi_mFlagF_q_1$EN = - WILL_FIRE_RL_wmi_mFlagF_both || - WILL_FIRE_RL_wmi_mFlagF_incCtr && wmi_mFlagF_c_r == 2'd1 || + WILL_FIRE_RL_wmi_mFlagF_both && _dfoo9 || + WILL_FIRE_RL_wmi_mFlagF_incCtr && wmi_mFlagF_cntr_r == 2'd1 || WILL_FIRE_RL_wmi_mFlagF_decCtr ; // register wmi_operateD @@ -2195,23 +2210,23 @@ module mkSMAdapter4B(wciS0_Clk, assign wmi_peerIsReady$D_IN = wmiM0_SReset_n ; assign wmi_peerIsReady$EN = 1'd1 ; - // register wmi_reqF_c_r - assign wmi_reqF_c_r$D_IN = - WILL_FIRE_RL_wmi_reqF_incCtr ? - MUX_wmi_reqF_c_r$write_1__VAL_1 : - MUX_wmi_reqF_c_r$write_1__VAL_2 ; - assign wmi_reqF_c_r$EN = - WILL_FIRE_RL_wmi_reqF_incCtr || WILL_FIRE_RL_wmi_reqF_decCtr ; + // register wmi_reqF_cntr_r + assign wmi_reqF_cntr_r$D_IN = + WILL_FIRE_RL_wmi_reqF_decCtr ? + wmi_reqF_cntr_r_61_MINUS_1___d169 : + MUX_wmi_reqF_cntr_r$write_1__VAL_2 ; + assign wmi_reqF_cntr_r$EN = + WILL_FIRE_RL_wmi_reqF_decCtr || WILL_FIRE_RL_wmi_reqF_incCtr ; // register wmi_reqF_q_0 - always@(WILL_FIRE_RL_wmi_reqF_both or + always@(MUX_wmi_reqF_q_0$write_1__SEL_1 or MUX_wmi_reqF_q_0$write_1__VAL_1 or MUX_wmi_reqF_q_0$write_1__SEL_2 or MUX_wmi_reqF_q_0$write_1__VAL_2 or WILL_FIRE_RL_wmi_reqF_decCtr or wmi_reqF_q_1) begin case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_wmi_reqF_both: + MUX_wmi_reqF_q_0$write_1__SEL_1: wmi_reqF_q_0$D_IN = MUX_wmi_reqF_q_0$write_1__VAL_1; MUX_wmi_reqF_q_0$write_1__SEL_2: wmi_reqF_q_0$D_IN = MUX_wmi_reqF_q_0$write_1__VAL_2; @@ -2220,18 +2235,18 @@ module mkSMAdapter4B(wciS0_Clk, endcase end assign wmi_reqF_q_0$EN = - WILL_FIRE_RL_wmi_reqF_both || - WILL_FIRE_RL_wmi_reqF_incCtr && wmi_reqF_c_r == 2'd0 || + WILL_FIRE_RL_wmi_reqF_both && _dfoo7 || + WILL_FIRE_RL_wmi_reqF_incCtr && wmi_reqF_cntr_r == 2'd0 || WILL_FIRE_RL_wmi_reqF_decCtr ; // register wmi_reqF_q_1 - always@(WILL_FIRE_RL_wmi_reqF_both or + always@(MUX_wmi_reqF_q_1$write_1__SEL_1 or MUX_wmi_reqF_q_1$write_1__VAL_1 or MUX_wmi_reqF_q_1$write_1__SEL_2 or MUX_wmi_reqF_q_0$write_1__VAL_2 or WILL_FIRE_RL_wmi_reqF_decCtr) begin case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_wmi_reqF_both: + MUX_wmi_reqF_q_1$write_1__SEL_1: wmi_reqF_q_1$D_IN = MUX_wmi_reqF_q_1$write_1__VAL_1; MUX_wmi_reqF_q_1$write_1__SEL_2: wmi_reqF_q_1$D_IN = MUX_wmi_reqF_q_0$write_1__VAL_2; @@ -2240,8 +2255,8 @@ module mkSMAdapter4B(wciS0_Clk, endcase end assign wmi_reqF_q_1$EN = - WILL_FIRE_RL_wmi_reqF_both || - WILL_FIRE_RL_wmi_reqF_incCtr && wmi_reqF_c_r == 2'd1 || + WILL_FIRE_RL_wmi_reqF_both && _dfoo5 || + WILL_FIRE_RL_wmi_reqF_incCtr && wmi_reqF_cntr_r == 2'd1 || WILL_FIRE_RL_wmi_reqF_decCtr ; // register wmi_sDataThreadBusy_d @@ -2320,24 +2335,24 @@ module mkSMAdapter4B(wciS0_Clk, assign wsiM_peerIsReady$D_IN = wsiM0_SReset_n ; assign wsiM_peerIsReady$EN = 1'd1 ; - // register wsiM_reqFifo_c_r - assign wsiM_reqFifo_c_r$D_IN = - WILL_FIRE_RL_wsiM_reqFifo_incCtr ? - MUX_wsiM_reqFifo_c_r$write_1__VAL_1 : - MUX_wsiM_reqFifo_c_r$write_1__VAL_2 ; - assign wsiM_reqFifo_c_r$EN = - WILL_FIRE_RL_wsiM_reqFifo_incCtr || - WILL_FIRE_RL_wsiM_reqFifo_decCtr ; + // register wsiM_reqFifo_cntr_r + assign wsiM_reqFifo_cntr_r$D_IN = + WILL_FIRE_RL_wsiM_reqFifo_decCtr ? + MUX_wsiM_reqFifo_cntr_r$write_1__VAL_1 : + MUX_wsiM_reqFifo_cntr_r$write_1__VAL_2 ; + assign wsiM_reqFifo_cntr_r$EN = + WILL_FIRE_RL_wsiM_reqFifo_decCtr || + WILL_FIRE_RL_wsiM_reqFifo_incCtr ; // register wsiM_reqFifo_q_0 - always@(WILL_FIRE_RL_wsiM_reqFifo_both or + always@(MUX_wsiM_reqFifo_q_0$write_1__SEL_1 or MUX_wsiM_reqFifo_q_0$write_1__VAL_1 or MUX_wsiM_reqFifo_q_0$write_1__SEL_2 or MUX_wsiM_reqFifo_q_0$write_1__VAL_2 or WILL_FIRE_RL_wsiM_reqFifo_decCtr or wsiM_reqFifo_q_1) begin case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_wsiM_reqFifo_both: + MUX_wsiM_reqFifo_q_0$write_1__SEL_1: wsiM_reqFifo_q_0$D_IN = MUX_wsiM_reqFifo_q_0$write_1__VAL_1; MUX_wsiM_reqFifo_q_0$write_1__SEL_2: wsiM_reqFifo_q_0$D_IN = MUX_wsiM_reqFifo_q_0$write_1__VAL_2; @@ -2348,22 +2363,23 @@ module mkSMAdapter4B(wciS0_Clk, endcase end assign wsiM_reqFifo_q_0$EN = - WILL_FIRE_RL_wsiM_reqFifo_both || - WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_c_r == 2'd0 || + WILL_FIRE_RL_wsiM_reqFifo_incCtr && + wsiM_reqFifo_cntr_r == 2'd0 || + WILL_FIRE_RL_wsiM_reqFifo_both && _dfoo19 || WILL_FIRE_RL_wsiM_reqFifo_decCtr ; // register wsiM_reqFifo_q_1 - always@(WILL_FIRE_RL_wsiM_reqFifo_both or - MUX_wsiM_reqFifo_q_1$write_1__VAL_1 or + always@(MUX_wsiM_reqFifo_q_1$write_1__SEL_1 or + MUX_wsiM_reqFifo_q_0$write_1__VAL_1 or MUX_wsiM_reqFifo_q_1$write_1__SEL_2 or - MUX_wsiM_reqFifo_q_0$write_1__VAL_2 or + MUX_wsiM_reqFifo_q_1$write_1__VAL_2 or WILL_FIRE_RL_wsiM_reqFifo_decCtr) begin case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_wsiM_reqFifo_both: - wsiM_reqFifo_q_1$D_IN = MUX_wsiM_reqFifo_q_1$write_1__VAL_1; + MUX_wsiM_reqFifo_q_1$write_1__SEL_1: + wsiM_reqFifo_q_1$D_IN = MUX_wsiM_reqFifo_q_0$write_1__VAL_1; MUX_wsiM_reqFifo_q_1$write_1__SEL_2: - wsiM_reqFifo_q_1$D_IN = MUX_wsiM_reqFifo_q_0$write_1__VAL_2; + wsiM_reqFifo_q_1$D_IN = MUX_wsiM_reqFifo_q_1$write_1__VAL_2; WILL_FIRE_RL_wsiM_reqFifo_decCtr: wsiM_reqFifo_q_1$D_IN = 61'h00000AAAAAAAAA00; default: wsiM_reqFifo_q_1$D_IN = @@ -2371,8 +2387,9 @@ module mkSMAdapter4B(wciS0_Clk, endcase end assign wsiM_reqFifo_q_1$EN = - WILL_FIRE_RL_wsiM_reqFifo_both || - WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_c_r == 2'd1 || + WILL_FIRE_RL_wsiM_reqFifo_incCtr && + wsiM_reqFifo_cntr_r == 2'd1 || + WILL_FIRE_RL_wsiM_reqFifo_both && _dfoo17 || WILL_FIRE_RL_wsiM_reqFifo_decCtr ; // register wsiM_sThreadBusy_d @@ -2498,18 +2515,18 @@ module mkSMAdapter4B(wciS0_Clk, assign respF_memory$ADDRA = respF_rWrPtr[10:0] ; assign respF_memory$ADDRB = WILL_FIRE_RL_wmrd_mesgResptoWsi ? - x__h16878[10:0] : + x__h16253[10:0] : respF_rRdPtr[10:0] ; assign respF_memory$DIA = - { IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d889, + { IF_respF_wDataIn_whas__28_THEN_respF_wDataIn_w_ETC___d431, respF_pwEnqueue$whas && respF_wDataIn$wget[57], respF_pwEnqueue$whas && respF_wDataIn$wget[56], - IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d881 } ; + IF_respF_wDataIn_whas__28_THEN_respF_wDataIn_w_ETC___d437 } ; assign respF_memory$DIB = 61'h0AAAAAAAAAAAAAAA /* unspecified value */ ; assign respF_memory$WEA = respF_pwEnqueue$whas ; assign respF_memory$WEB = 1'd0 ; - assign respF_memory$ENA = 1'd1 ; - assign respF_memory$ENB = 1'd1 ; + assign respF_memory$ENA = 1'b1 ; + assign respF_memory$ENB = 1'b1 ; // submodule wci_wslv_reqF assign wci_wslv_reqF$D_IN = wci_wslv_wciReq$wget ; @@ -2532,70 +2549,106 @@ module mkSMAdapter4B(wciS0_Clk, assign wsiS_reqFifo$CLR = 1'b0 ; // remaining internal signals - assign IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d881 = - respF_pwEnqueue$whas ? respF_wDataIn$wget[55:0] : 56'd0 ; - assign IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d889 = + assign IF_respF_wDataIn_whas__28_THEN_respF_wDataIn_w_ETC___d431 = respF_pwEnqueue$whas ? respF_wDataIn$wget[60:58] : 3'd0 ; - assign NOT_wmi_reqF_c_r_57_EQ_2_75_76_AND_wmi_operate_ETC___d524 = - wmi_reqF_c_r != 2'd2 && wmi_operateD && wmi_peerIsReady && - (!x__h18954 || wmi_mFlagF_c_r != 2'd2) ; - assign b__h15473 = -fabWordsCurReq[11:0] ; - assign b__h18410 = x__h18530 + residue__h18273 ; - assign b__h18783 = { {2{fabRespCredit_value[11]}}, fabRespCredit_value } ; - assign mesgMetaF_length__h23696 = + assign IF_respF_wDataIn_whas__28_THEN_respF_wDataIn_w_ETC___d437 = + respF_pwEnqueue$whas ? respF_wDataIn$wget[55:0] : 56'd0 ; + assign NOT_wmi_reqF_cntr_r_61_EQ_2_73_74_AND_wmi_oper_ETC___d521 = + wmi_reqF_cntr_r != 2'd2 && wmi_operateD && wmi_peerIsReady && + (!x__h18328 || wmi_mFlagF_cntr_r != 2'd2) ; + assign _dfoo1 = + wci_wslv_respF_cntr_r != 2'd2 || + wci_wslv_respF_cntr_r_8_MINUS_1___d27 == 2'd1 ; + assign _dfoo11 = + wmi_mFlagF_cntr_r != 2'd1 || + wmi_mFlagF_cntr_r_83_MINUS_1___d191 == 2'd0 ; + assign _dfoo13 = + wmi_dhF_cntr_r != 2'd2 || + wmi_dhF_cntr_r_05_MINUS_1___d213 == 2'd1 ; + assign _dfoo15 = + wmi_dhF_cntr_r != 2'd1 || + wmi_dhF_cntr_r_05_MINUS_1___d213 == 2'd0 ; + assign _dfoo17 = + wsiM_reqFifo_cntr_r != 2'd2 || + MUX_wsiM_reqFifo_cntr_r$write_1__VAL_1 == 2'd1 ; + assign _dfoo19 = + wsiM_reqFifo_cntr_r != 2'd1 || + MUX_wsiM_reqFifo_cntr_r$write_1__VAL_1 == 2'd0 ; + assign _dfoo3 = + wci_wslv_respF_cntr_r != 2'd1 || + wci_wslv_respF_cntr_r_8_MINUS_1___d27 == 2'd0 ; + assign _dfoo5 = + wmi_reqF_cntr_r != 2'd2 || + wmi_reqF_cntr_r_61_MINUS_1___d169 == 2'd1 ; + assign _dfoo7 = + wmi_reqF_cntr_r != 2'd1 || + wmi_reqF_cntr_r_61_MINUS_1___d169 == 2'd0 ; + assign _dfoo9 = + wmi_mFlagF_cntr_r != 2'd2 || + wmi_mFlagF_cntr_r_83_MINUS_1___d191 == 2'd1 ; + assign b__h14802 = -fabWordsCurReq[11:0] ; + assign b__h17784 = x__h17904 + residue__h17647 ; + assign b__h18157 = { {2{fabRespCredit_value[11]}}, fabRespCredit_value } ; + assign mesgMetaF_length__h22373 = (wsiS_reqFifo$D_OUT[57] && wsiS_reqFifo$D_OUT[11:8] == 4'd0 && mesgLengthSoFar == 14'd0) ? 24'd0 : - { 10'd0, mlB__h23529 } ; - assign mesgMetaF_opcode__h23695 = opcode[8] ? opcode[7:0] : 8'd0 ; - assign mlB__h23529 = mesgLengthSoFar + mlInc__h23528 ; - assign mlInc__h23528 = + { 10'd0, mlB__h22206 } ; + assign mesgMetaF_opcode__h22372 = opcode[8] ? opcode[7:0] : 8'd0 ; + assign mlB__h22206 = MUX_mesgLengthSoFar$write_1__VAL_1 ; + assign mlInc__h22205 = wsiS_reqFifo$D_OUT[57] ? - { 11'd0, x__h23735 + y__h23736 } : + { 11'd0, x__h22411 + y__h22412 } : 14'd4 ; - assign rdat__h25116 = hasDebugLogic ? mesgCount : 32'd0 ; - assign rdat__h25122 = hasDebugLogic ? abortCount : 32'd0 ; - assign rdat__h25128 = hasDebugLogic ? thisMesg : 32'd0 ; - assign rdat__h25141 = hasDebugLogic ? lastMesg : 32'd0 ; - assign rdat__h25164 = hasDebugLogic ? { 16'd0, x__h25168 } : 32'd0 ; - assign rdat__h25264 = hasDebugLogic ? wsiS_extStatusW$wget[95:64] : 32'd0 ; - assign rdat__h25278 = hasDebugLogic ? wsiS_extStatusW$wget[63:32] : 32'd0 ; - assign rdat__h25286 = hasDebugLogic ? wsiS_extStatusW$wget[31:0] : 32'd0 ; - assign rdat__h25292 = hasDebugLogic ? wsiM_extStatusW$wget[95:64] : 32'd0 ; - assign rdat__h25306 = hasDebugLogic ? wsiM_extStatusW$wget[63:32] : 32'd0 ; - assign rdat__h25314 = hasDebugLogic ? wsiM_extStatusW$wget[31:0] : 32'd0 ; - assign rdat__h25320 = hasDebugLogic ? wmwtBeginCount : 32'd0 ; - assign rdat__h25326 = hasDebugLogic ? wmwtPushCount : 32'd0 ; - assign rdat__h25332 = hasDebugLogic ? wmwtFinalCount : 32'd0 ; - assign rdat__h25338 = hasDebugLogic ? { 31'd0, x__h25342 } : 32'd0 ; - assign rdat__h25348 = hasDebugLogic ? 32'hFEEDC0DE : 32'd0 ; - assign residue__h18273 = + assign rdat__h23791 = hasDebugLogic ? mesgCount : 32'd0 ; + assign rdat__h23797 = hasDebugLogic ? abortCount : 32'd0 ; + assign rdat__h23803 = hasDebugLogic ? thisMesg : 32'd0 ; + assign rdat__h23816 = hasDebugLogic ? lastMesg : 32'd0 ; + assign rdat__h23839 = hasDebugLogic ? { 16'd0, x__h23843 } : 32'd0 ; + assign rdat__h23939 = hasDebugLogic ? wsiS_extStatusW$wget[95:64] : 32'd0 ; + assign rdat__h23953 = hasDebugLogic ? wsiS_extStatusW$wget[63:32] : 32'd0 ; + assign rdat__h23961 = hasDebugLogic ? wsiS_extStatusW$wget[31:0] : 32'd0 ; + assign rdat__h23967 = hasDebugLogic ? wsiM_extStatusW$wget[95:64] : 32'd0 ; + assign rdat__h23981 = hasDebugLogic ? wsiM_extStatusW$wget[63:32] : 32'd0 ; + assign rdat__h23989 = hasDebugLogic ? wsiM_extStatusW$wget[31:0] : 32'd0 ; + assign rdat__h23995 = hasDebugLogic ? wmwtBeginCount : 32'd0 ; + assign rdat__h24001 = hasDebugLogic ? wmwtPushCount : 32'd0 ; + assign rdat__h24007 = hasDebugLogic ? wmwtFinalCount : 32'd0 ; + assign rdat__h24013 = hasDebugLogic ? { 31'd0, x__h24017 } : 32'd0 ; + assign rdat__h24023 = hasDebugLogic ? 32'hFEEDC0DE : 32'd0 ; + assign residue__h17647 = ({ 4'd0, wmi_sFlagReg[1:0] } == 6'd0) ? 24'd0 : 24'd1 ; - assign sendData_burstLength__h19243 = + assign sendData_burstLength__h18617 = (thisMesg[15:0] == 16'd0 || smaCtrl[5] && unrollCnt == 16'd1) ? 12'd1 : - (smaCtrl[5] ? 12'd4095 : wsiBurstLength__h19161[11:0]) ; - assign sendData_byteEn__h19245 = + (smaCtrl[5] ? 12'd4095 : wsiBurstLength__h18535[11:0]) ; + assign sendData_byteEn__h18619 = (thisMesg[15:0] == 16'd0) ? 4'd0 : - ((unrollCnt == 16'd1) ? x__h19302[3:0] : 4'd15) ; - assign value__h6702 = + ((unrollCnt == 16'd1) ? x__h18676[3:0] : 4'd15) ; + assign value__h6387 = MUX_wmi_mFlagF_x_wire$wset_1__SEL_1 ? 32'hAAAAAAAA /* unspecified value */ : MUX_wmi_mFlagF_x_wire$wset_1__VAL_2 ; - assign wmi_respF_i_notEmpty__36_AND_smaCtrl_65_BIT_4__ETC___d541 = + assign wci_wslv_respF_cntr_r_8_MINUS_1___d27 = + wci_wslv_respF_cntr_r - 2'd1 ; + assign wmi_dhF_cntr_r_05_MINUS_1___d213 = wmi_dhF_cntr_r - 2'd1 ; + assign wmi_mFlagF_cntr_r_83_MINUS_1___d191 = wmi_mFlagF_cntr_r - 2'd1 ; + assign wmi_reqF_cntr_r_61_MINUS_1___d169 = wmi_reqF_cntr_r - 2'd1 ; + assign wmi_respF_i_notEmpty__33_AND_smaCtrl_62_BIT_4__ETC___d538 = wmi_respF$EMPTY_N && (smaCtrl[4] || respF_rRdPtr + 12'd1024 != respF_rWrPtr) ; - assign wsiBurstLength__h19161 = + assign wsiBurstLength__h18535 = smaCtrl[5] ? 16'd2 : { 2'd0, thisMesg[15:2] } ; - assign wsiS_reqFifo_i_notEmpty__64_AND_NOT_smaCtrl_65_ETC___d669 = + assign wsiS_reqFifo_i_notEmpty__61_AND_NOT_smaCtrl_62_ETC___d666 = wsiS_reqFifo$EMPTY_N && - (smaCtrl[3:0] != 4'h3 || wsiM_reqFifo_c_r != 2'd2) && - (!wsiS_reqFifo$D_OUT[57] || wmi_mFlagF_c_r != 2'd2) ; - assign x__h16878 = respF_rRdPtr + 12'd1 ; - assign x__h18530 = { 2'd0, wmi_sFlagReg[23:2] } ; - assign x__h18954 = fabWordsRemain == fabWordsCurReq ; - assign x__h19302 = + (smaCtrl[3:0] != 4'h3 || wsiM_reqFifo_cntr_r != 2'd2) && + (!wsiS_reqFifo$D_OUT[57] || wmi_mFlagF_cntr_r != 2'd2) ; + assign x__h16103 = respF_rWrPtr + 12'd1 ; + assign x__h16253 = respF_rRdPtr + 12'd1 ; + assign x__h17904 = { 2'd0, wmi_sFlagReg[23:2] } ; + assign x__h18328 = fabWordsRemain == fabWordsCurReq ; + assign x__h18676 = ({ 4'd0, thisMesg[1:0] } == 6'd0) ? 32'hFFFFFFFF : (({ 4'd0, thisMesg[1:0] } <= 6'd1) ? @@ -2702,50 +2755,50 @@ module mkSMAdapter4B(wciS0_Clk, 6'd31) ? 32'h7FFFFFFF : 32'hFFFFFFFF))))))))))))))))))))))))))))))) ; - assign x__h23735 = x__h23747 + y__h23748 ; - assign x__h23747 = x__h23759 + y__h23760 ; - assign x__h23759 = { 2'd0, wsiS_reqFifo$D_OUT[11] } ; - assign x__h25168 = { wsiS_statusR, wsiM_statusR } ; - assign x__h25342 = wmi_sThreadBusy_d || wmi_sDataThreadBusy_d ; - assign x_length__h24096 = { 2'd0, mlB__h23529 } ; - assign y__h23736 = { 2'd0, wsiS_reqFifo$D_OUT[8] } ; - assign y__h23748 = { 2'd0, wsiS_reqFifo$D_OUT[9] } ; - assign y__h23760 = { 2'd0, wsiS_reqFifo$D_OUT[10] } ; + assign x__h22411 = x__h22423 + y__h22424 ; + assign x__h22423 = x__h22435 + y__h22436 ; + assign x__h22435 = { 2'd0, wsiS_reqFifo$D_OUT[11] } ; + assign x__h23843 = { wsiS_statusR, wsiM_statusR } ; + assign x__h24017 = wmi_sThreadBusy_d || wmi_sDataThreadBusy_d ; + assign x_length__h22772 = { 2'd0, mlB__h22206 } ; + assign y__h22412 = { 2'd0, wsiS_reqFifo$D_OUT[8] } ; + assign y__h22424 = { 2'd0, wsiS_reqFifo$D_OUT[9] } ; + assign y__h22436 = { 2'd0, wsiS_reqFifo$D_OUT[10] } ; always@(wci_wslv_reqF$D_OUT or smaCtrl or - rdat__h25116 or - rdat__h25122 or - rdat__h25128 or - rdat__h25141 or - rdat__h25164 or - rdat__h25264 or - rdat__h25278 or - rdat__h25286 or - rdat__h25292 or - rdat__h25306 or - rdat__h25314 or - rdat__h25320 or - rdat__h25326 or rdat__h25332 or rdat__h25338 or rdat__h25348) + rdat__h23791 or + rdat__h23797 or + rdat__h23803 or + rdat__h23816 or + rdat__h23839 or + rdat__h23939 or + rdat__h23953 or + rdat__h23961 or + rdat__h23967 or + rdat__h23981 or + rdat__h23989 or + rdat__h23995 or + rdat__h24001 or rdat__h24007 or rdat__h24013 or rdat__h24023) begin case (wci_wslv_reqF$D_OUT[39:32]) - 8'h0: g_data__h25073 = smaCtrl; - 8'h04: g_data__h25073 = rdat__h25116; - 8'h08: g_data__h25073 = rdat__h25122; - 8'h10: g_data__h25073 = rdat__h25128; - 8'h14: g_data__h25073 = rdat__h25141; - 8'h18: g_data__h25073 = rdat__h25164; - 8'h20: g_data__h25073 = rdat__h25264; - 8'h24: g_data__h25073 = rdat__h25278; - 8'h28: g_data__h25073 = rdat__h25286; - 8'h2C: g_data__h25073 = rdat__h25292; - 8'h30: g_data__h25073 = rdat__h25306; - 8'h34: g_data__h25073 = rdat__h25314; - 8'h38: g_data__h25073 = rdat__h25320; - 8'h3C: g_data__h25073 = rdat__h25326; - 8'h40: g_data__h25073 = rdat__h25332; - 8'h44: g_data__h25073 = rdat__h25338; - 8'h48: g_data__h25073 = rdat__h25348; - default: g_data__h25073 = 32'd0; + 8'h0: g_data__h23748 = smaCtrl; + 8'h04: g_data__h23748 = rdat__h23791; + 8'h08: g_data__h23748 = rdat__h23797; + 8'h10: g_data__h23748 = rdat__h23803; + 8'h14: g_data__h23748 = rdat__h23816; + 8'h18: g_data__h23748 = rdat__h23839; + 8'h20: g_data__h23748 = rdat__h23939; + 8'h24: g_data__h23748 = rdat__h23953; + 8'h28: g_data__h23748 = rdat__h23961; + 8'h2C: g_data__h23748 = rdat__h23967; + 8'h30: g_data__h23748 = rdat__h23981; + 8'h34: g_data__h23748 = rdat__h23989; + 8'h38: g_data__h23748 = rdat__h23995; + 8'h3C: g_data__h23748 = rdat__h24001; + 8'h40: g_data__h23748 = rdat__h24007; + 8'h44: g_data__h23748 = rdat__h24013; + 8'h48: g_data__h23748 = rdat__h24023; + default: g_data__h23748 = 32'd0; endcase end @@ -2784,22 +2837,22 @@ module mkSMAdapter4B(wciS0_Clk, wci_wslv_illegalEdge <= `BSV_ASSIGNMENT_DELAY 1'd0; wci_wslv_nState <= `BSV_ASSIGNMENT_DELAY 3'd0; wci_wslv_reqF_countReg <= `BSV_ASSIGNMENT_DELAY 2'd0; - wci_wslv_respF_c_r <= `BSV_ASSIGNMENT_DELAY 2'd0; + wci_wslv_respF_cntr_r <= `BSV_ASSIGNMENT_DELAY 2'd0; wci_wslv_respF_q_0 <= `BSV_ASSIGNMENT_DELAY 34'h0AAAAAAAA; wci_wslv_respF_q_1 <= `BSV_ASSIGNMENT_DELAY 34'h0AAAAAAAA; wci_wslv_sFlagReg <= `BSV_ASSIGNMENT_DELAY 1'd0; wci_wslv_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY 1'd1; wmi_busyWithMessage <= `BSV_ASSIGNMENT_DELAY 1'd0; - wmi_dhF_c_r <= `BSV_ASSIGNMENT_DELAY 2'd0; + wmi_dhF_cntr_r <= `BSV_ASSIGNMENT_DELAY 2'd0; wmi_dhF_q_0 <= `BSV_ASSIGNMENT_DELAY 38'd0; wmi_dhF_q_1 <= `BSV_ASSIGNMENT_DELAY 38'd0; wmi_errorSticky <= `BSV_ASSIGNMENT_DELAY 1'd0; - wmi_mFlagF_c_r <= `BSV_ASSIGNMENT_DELAY 2'd0; + wmi_mFlagF_cntr_r <= `BSV_ASSIGNMENT_DELAY 2'd0; wmi_mFlagF_q_0 <= `BSV_ASSIGNMENT_DELAY 32'd0; wmi_mFlagF_q_1 <= `BSV_ASSIGNMENT_DELAY 32'd0; wmi_operateD <= `BSV_ASSIGNMENT_DELAY 1'd0; wmi_peerIsReady <= `BSV_ASSIGNMENT_DELAY 1'd0; - wmi_reqF_c_r <= `BSV_ASSIGNMENT_DELAY 2'd0; + wmi_reqF_cntr_r <= `BSV_ASSIGNMENT_DELAY 2'd0; wmi_reqF_q_0 <= `BSV_ASSIGNMENT_DELAY 32'd0; wmi_reqF_q_1 <= `BSV_ASSIGNMENT_DELAY 32'd0; wmi_sDataThreadBusy_d <= `BSV_ASSIGNMENT_DELAY 1'd0; @@ -2815,7 +2868,7 @@ module mkSMAdapter4B(wciS0_Clk, wsiM_operateD <= `BSV_ASSIGNMENT_DELAY 1'd0; wsiM_pMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0; wsiM_peerIsReady <= `BSV_ASSIGNMENT_DELAY 1'd0; - wsiM_reqFifo_c_r <= `BSV_ASSIGNMENT_DELAY 2'd0; + wsiM_reqFifo_cntr_r <= `BSV_ASSIGNMENT_DELAY 2'd0; wsiM_reqFifo_q_0 <= `BSV_ASSIGNMENT_DELAY 61'h00000AAAAAAAAA00; wsiM_reqFifo_q_1 <= `BSV_ASSIGNMENT_DELAY 61'h00000AAAAAAAAA00; wsiM_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY 1'd1; @@ -2887,8 +2940,9 @@ module mkSMAdapter4B(wciS0_Clk, if (wci_wslv_reqF_countReg$EN) wci_wslv_reqF_countReg <= `BSV_ASSIGNMENT_DELAY wci_wslv_reqF_countReg$D_IN; - if (wci_wslv_respF_c_r$EN) - wci_wslv_respF_c_r <= `BSV_ASSIGNMENT_DELAY wci_wslv_respF_c_r$D_IN; + if (wci_wslv_respF_cntr_r$EN) + wci_wslv_respF_cntr_r <= `BSV_ASSIGNMENT_DELAY + wci_wslv_respF_cntr_r$D_IN; if (wci_wslv_respF_q_0$EN) wci_wslv_respF_q_0 <= `BSV_ASSIGNMENT_DELAY wci_wslv_respF_q_0$D_IN; if (wci_wslv_respF_q_1$EN) @@ -2901,16 +2955,16 @@ module mkSMAdapter4B(wciS0_Clk, if (wmi_busyWithMessage$EN) wmi_busyWithMessage <= `BSV_ASSIGNMENT_DELAY wmi_busyWithMessage$D_IN; - if (wmi_dhF_c_r$EN) - wmi_dhF_c_r <= `BSV_ASSIGNMENT_DELAY wmi_dhF_c_r$D_IN; + if (wmi_dhF_cntr_r$EN) + wmi_dhF_cntr_r <= `BSV_ASSIGNMENT_DELAY wmi_dhF_cntr_r$D_IN; if (wmi_dhF_q_0$EN) wmi_dhF_q_0 <= `BSV_ASSIGNMENT_DELAY wmi_dhF_q_0$D_IN; if (wmi_dhF_q_1$EN) wmi_dhF_q_1 <= `BSV_ASSIGNMENT_DELAY wmi_dhF_q_1$D_IN; if (wmi_errorSticky$EN) wmi_errorSticky <= `BSV_ASSIGNMENT_DELAY wmi_errorSticky$D_IN; - if (wmi_mFlagF_c_r$EN) - wmi_mFlagF_c_r <= `BSV_ASSIGNMENT_DELAY wmi_mFlagF_c_r$D_IN; + if (wmi_mFlagF_cntr_r$EN) + wmi_mFlagF_cntr_r <= `BSV_ASSIGNMENT_DELAY wmi_mFlagF_cntr_r$D_IN; if (wmi_mFlagF_q_0$EN) wmi_mFlagF_q_0 <= `BSV_ASSIGNMENT_DELAY wmi_mFlagF_q_0$D_IN; if (wmi_mFlagF_q_1$EN) @@ -2919,8 +2973,8 @@ module mkSMAdapter4B(wciS0_Clk, wmi_operateD <= `BSV_ASSIGNMENT_DELAY wmi_operateD$D_IN; if (wmi_peerIsReady$EN) wmi_peerIsReady <= `BSV_ASSIGNMENT_DELAY wmi_peerIsReady$D_IN; - if (wmi_reqF_c_r$EN) - wmi_reqF_c_r <= `BSV_ASSIGNMENT_DELAY wmi_reqF_c_r$D_IN; + if (wmi_reqF_cntr_r$EN) + wmi_reqF_cntr_r <= `BSV_ASSIGNMENT_DELAY wmi_reqF_cntr_r$D_IN; if (wmi_reqF_q_0$EN) wmi_reqF_q_0 <= `BSV_ASSIGNMENT_DELAY wmi_reqF_q_0$D_IN; if (wmi_reqF_q_1$EN) @@ -2952,8 +3006,9 @@ module mkSMAdapter4B(wciS0_Clk, wsiM_pMesgCount <= `BSV_ASSIGNMENT_DELAY wsiM_pMesgCount$D_IN; if (wsiM_peerIsReady$EN) wsiM_peerIsReady <= `BSV_ASSIGNMENT_DELAY wsiM_peerIsReady$D_IN; - if (wsiM_reqFifo_c_r$EN) - wsiM_reqFifo_c_r <= `BSV_ASSIGNMENT_DELAY wsiM_reqFifo_c_r$D_IN; + if (wsiM_reqFifo_cntr_r$EN) + wsiM_reqFifo_cntr_r <= `BSV_ASSIGNMENT_DELAY + wsiM_reqFifo_cntr_r$D_IN; if (wsiM_reqFifo_q_0$EN) wsiM_reqFifo_q_0 <= `BSV_ASSIGNMENT_DELAY wsiM_reqFifo_q_0$D_IN; if (wsiM_reqFifo_q_1$EN) @@ -3062,23 +3117,23 @@ module mkSMAdapter4B(wciS0_Clk, wci_wslv_isReset_isInReset = 1'h0; wci_wslv_nState = 3'h2; wci_wslv_reqF_countReg = 2'h2; - wci_wslv_respF_c_r = 2'h2; + wci_wslv_respF_cntr_r = 2'h2; wci_wslv_respF_q_0 = 34'h2AAAAAAAA; wci_wslv_respF_q_1 = 34'h2AAAAAAAA; wci_wslv_sFlagReg = 1'h0; wci_wslv_sThreadBusy_d = 1'h0; wmi_busyWithMessage = 1'h0; - wmi_dhF_c_r = 2'h2; + wmi_dhF_cntr_r = 2'h2; wmi_dhF_q_0 = 38'h2AAAAAAAAA; wmi_dhF_q_1 = 38'h2AAAAAAAAA; wmi_errorSticky = 1'h0; wmi_isReset_isInReset = 1'h0; - wmi_mFlagF_c_r = 2'h2; + wmi_mFlagF_cntr_r = 2'h2; wmi_mFlagF_q_0 = 32'hAAAAAAAA; wmi_mFlagF_q_1 = 32'hAAAAAAAA; wmi_operateD = 1'h0; wmi_peerIsReady = 1'h0; - wmi_reqF_c_r = 2'h2; + wmi_reqF_cntr_r = 2'h2; wmi_reqF_q_0 = 32'hAAAAAAAA; wmi_reqF_q_1 = 32'hAAAAAAAA; wmi_sDataThreadBusy_d = 1'h0; @@ -3096,7 +3151,7 @@ module mkSMAdapter4B(wciS0_Clk, wsiM_operateD = 1'h0; wsiM_pMesgCount = 32'hAAAAAAAA; wsiM_peerIsReady = 1'h0; - wsiM_reqFifo_c_r = 2'h2; + wsiM_reqFifo_cntr_r = 2'h2; wsiM_reqFifo_q_0 = 61'h0AAAAAAAAAAAAAAA; wsiM_reqFifo_q_1 = 61'h0AAAAAAAAAAAAAAA; wsiM_sThreadBusy_d = 1'h0; @@ -3130,96 +3185,96 @@ module mkSMAdapter4B(wciS0_Clk, if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_start) begin - v__h3729 = $time; + v__h3597 = $time; #0; end if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_start) $display("[%0d]: %m: WCI ControlOp: Starting-transition edge:%x from:%x", - v__h3729, + v__h3597, wci_wslv_reqF$D_OUT[36:34], wci_wslv_cState); if (wciS0_MReset_n != `BSV_RESET_VALUE) if (MUX_unrollCnt$write_1__SEL_1) begin - v__h18699 = $time; + v__h18073 = $time; #0; end if (wciS0_MReset_n != `BSV_RESET_VALUE) if (MUX_unrollCnt$write_1__SEL_1) $display("[%0d]: %m: wmrd_mesgBegin mesgCount:%0h mesgLength:%0h reqInfo:%0h", - v__h18699, + v__h18073, mesgCount, wmi_sFlagReg[23:0], wmi_sFlagReg[31:24]); if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wmwt_mesgBegin && wsiS_reqFifo$D_OUT[56]) begin - v__h23115 = $time; + v__h21792 = $time; #0; end if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wmwt_mesgBegin && wsiS_reqFifo$D_OUT[56]) $display("[%0d]: %m: mesgBegin PRECISE mesgCount:%0x WSI burstLength:%0x reqInfo:%0x", - v__h23115, + v__h21792, mesgCount, wsiS_reqFifo$D_OUT[55:44], wsiS_reqFifo$D_OUT[7:0]); if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wmwt_mesgBegin && !wsiS_reqFifo$D_OUT[56]) begin - v__h23174 = $time; + v__h21851 = $time; #0; end if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wmwt_mesgBegin && !wsiS_reqFifo$D_OUT[56]) $display("[%0d]: %m: wmwt_mesgBegin IMPRECISE mesgCount:%0x", - v__h23174, + v__h21851, mesgCount); if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wmwt_doAbort) begin - v__h24522 = $time; + v__h23197 = $time; #0; end if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wmwt_doAbort) - $display("[%0d]: %m: wmwt_doAbort", v__h24522); + $display("[%0d]: %m: wmwt_doAbort", v__h23197); if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wmwt_messageFinalize) begin - v__h24705 = $time; + v__h23380 = $time; #0; end if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wmwt_messageFinalize) $display("[%0d]: %m: wmwt_messageFinalize mesgCount:%0x WSI mesgLength:%0x", - v__h24705, + v__h23380, mesgCount, thisMesg[15:0]); if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfwr) begin - v__h24901 = $time; + v__h23576 = $time; #0; end if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfwr) $display("[%0d]: %m: SMAdapter WCI CONFIG WRITE Addr:%0x BE:%0x Data:%0x", - v__h24901, + v__h23576, wci_wslv_reqF$D_OUT[63:32], wci_wslv_reqF$D_OUT[67:64], wci_wslv_reqF$D_OUT[31:0]); if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_ctrl_IsO) begin - v__h25563 = $time; + v__h24233 = $time; #0; end if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_ctrl_IsO) $display("[%0d]: %m: Starting SMAdapter smaCtrl:%0x", - v__h25563, + v__h24233, smaCtrl); if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_OrE) @@ -3254,25 +3309,25 @@ module mkSMAdapter4B(wciS0_Clk, if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge) begin - v__h4048 = $time; + v__h3916 = $time; #0; end if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge) $display("[%0d]: %m: WCI ControlOp: ILLEGAL-EDGE Completed-transition edge:%x from:%x", - v__h4048, + v__h3916, wci_wslv_cEdge, wci_wslv_cState); if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && !wci_wslv_illegalEdge) begin - v__h3904 = $time; + v__h3772 = $time; #0; end if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && !wci_wslv_illegalEdge) $display("[%0d]: %m: WCI ControlOp: Completed-transition edge:%x from:%x to:%x", - v__h3904, + v__h3772, wci_wslv_cEdge, wci_wslv_cState, wci_wslv_nState); diff --git a/rtl/mkSMAdapter8B.v b/rtl/mkSMAdapter8B.v index 693b1d9f..4cb07b01 100644 --- a/rtl/mkSMAdapter8B.v +++ b/rtl/mkSMAdapter8B.v @@ -1,7 +1,7 @@ // -// Generated by Bluespec Compiler, version 2012.09.beta1 (build 29570, 2012-09.11) +// Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Tue Dec 11 16:21:09 EST 2012 +// On Fri Jun 21 16:57:59 EDT 2013 // // // Ports: @@ -382,6 +382,7 @@ module mkSMAdapter8B(wciS0_Clk, fabRespCredit_acc_v2$whas, mesgPreRequest_1$wget, mesgPreRequest_1$whas, + respF_pwClear$whas, respF_pwDequeue$whas, respF_pwEnqueue$whas, respF_wDataIn$whas, @@ -607,10 +608,10 @@ module mkSMAdapter8B(wciS0_Clk, wire [1 : 0] wci_wslv_reqF_countReg$D_IN; wire wci_wslv_reqF_countReg$EN; - // register wci_wslv_respF_c_r - reg [1 : 0] wci_wslv_respF_c_r; - wire [1 : 0] wci_wslv_respF_c_r$D_IN; - wire wci_wslv_respF_c_r$EN; + // register wci_wslv_respF_cntr_r + reg [1 : 0] wci_wslv_respF_cntr_r; + wire [1 : 0] wci_wslv_respF_cntr_r$D_IN; + wire wci_wslv_respF_cntr_r$EN; // register wci_wslv_respF_q_0 reg [33 : 0] wci_wslv_respF_q_0; @@ -634,10 +635,10 @@ module mkSMAdapter8B(wciS0_Clk, reg wmi_busyWithMessage; wire wmi_busyWithMessage$D_IN, wmi_busyWithMessage$EN; - // register wmi_dhF_c_r - reg [1 : 0] wmi_dhF_c_r; - wire [1 : 0] wmi_dhF_c_r$D_IN; - wire wmi_dhF_c_r$EN; + // register wmi_dhF_cntr_r + reg [1 : 0] wmi_dhF_cntr_r; + wire [1 : 0] wmi_dhF_cntr_r$D_IN; + wire wmi_dhF_cntr_r$EN; // register wmi_dhF_q_0 reg [73 : 0] wmi_dhF_q_0; @@ -657,10 +658,10 @@ module mkSMAdapter8B(wciS0_Clk, reg wmi_isReset_isInReset; wire wmi_isReset_isInReset$D_IN, wmi_isReset_isInReset$EN; - // register wmi_mFlagF_c_r - reg [1 : 0] wmi_mFlagF_c_r; - wire [1 : 0] wmi_mFlagF_c_r$D_IN; - wire wmi_mFlagF_c_r$EN; + // register wmi_mFlagF_cntr_r + reg [1 : 0] wmi_mFlagF_cntr_r; + wire [1 : 0] wmi_mFlagF_cntr_r$D_IN; + wire wmi_mFlagF_cntr_r$EN; // register wmi_mFlagF_q_0 reg [31 : 0] wmi_mFlagF_q_0; @@ -680,10 +681,10 @@ module mkSMAdapter8B(wciS0_Clk, reg wmi_peerIsReady; wire wmi_peerIsReady$D_IN, wmi_peerIsReady$EN; - // register wmi_reqF_c_r - reg [1 : 0] wmi_reqF_c_r; - wire [1 : 0] wmi_reqF_c_r$D_IN; - wire wmi_reqF_c_r$EN; + // register wmi_reqF_cntr_r + reg [1 : 0] wmi_reqF_cntr_r; + wire [1 : 0] wmi_reqF_cntr_r$D_IN; + wire wmi_reqF_cntr_r$EN; // register wmi_reqF_q_0 reg [31 : 0] wmi_reqF_q_0; @@ -763,10 +764,10 @@ module mkSMAdapter8B(wciS0_Clk, reg wsiM_peerIsReady; wire wsiM_peerIsReady$D_IN, wsiM_peerIsReady$EN; - // register wsiM_reqFifo_c_r - reg [1 : 0] wsiM_reqFifo_c_r; - wire [1 : 0] wsiM_reqFifo_c_r$D_IN; - wire wsiM_reqFifo_c_r$EN; + // register wsiM_reqFifo_cntr_r + reg [1 : 0] wsiM_reqFifo_cntr_r; + wire [1 : 0] wsiM_reqFifo_cntr_r$D_IN; + wire wsiM_reqFifo_cntr_r$EN; // register wsiM_reqFifo_q_0 reg [96 : 0] wsiM_reqFifo_q_0; @@ -936,16 +937,16 @@ module mkSMAdapter8B(wciS0_Clk, reg [33 : 0] MUX_wci_wslv_respF_q_0$write_1__VAL_2; wire [96 : 0] MUX_wsiM_reqFifo_q_0$write_1__VAL_1, MUX_wsiM_reqFifo_q_0$write_1__VAL_2, - MUX_wsiM_reqFifo_q_1$write_1__VAL_1, + MUX_wsiM_reqFifo_q_1$write_1__VAL_2, MUX_wsiM_reqFifo_x_wire$wset_1__VAL_3; wire [73 : 0] MUX_wmi_dhF_q_0$write_1__VAL_1, MUX_wmi_dhF_q_0$write_1__VAL_2, - MUX_wmi_dhF_q_1$write_1__VAL_1; + MUX_wmi_dhF_q_1$write_1__VAL_2; wire [33 : 0] MUX_wci_wslv_respF_q_0$write_1__VAL_1, MUX_wci_wslv_respF_q_1$write_1__VAL_1, MUX_wci_wslv_respF_x_wire$wset_1__VAL_1, MUX_wci_wslv_respF_x_wire$wset_1__VAL_2; - wire [31 : 0] MUX_mesgCount$write_1__VAL_1, + wire [31 : 0] MUX_mesgCount$write_1__VAL_2, MUX_thisMesg$write_1__VAL_1, MUX_thisMesg$write_1__VAL_2, MUX_wmi_mFlagF_q_0$write_1__VAL_1, @@ -963,16 +964,12 @@ module mkSMAdapter8B(wciS0_Clk, MUX_mesgReqAddr$write_1__VAL_2; wire [11 : 0] MUX_fabRespCredit_value$write_1__VAL_2; wire [8 : 0] MUX_opcode$write_1__VAL_3; - wire [1 : 0] MUX_wci_wslv_respF_c_r$write_1__VAL_1, - MUX_wci_wslv_respF_c_r$write_1__VAL_2, - MUX_wmi_dhF_c_r$write_1__VAL_1, - MUX_wmi_dhF_c_r$write_1__VAL_2, - MUX_wmi_mFlagF_c_r$write_1__VAL_1, - MUX_wmi_mFlagF_c_r$write_1__VAL_2, - MUX_wmi_reqF_c_r$write_1__VAL_1, - MUX_wmi_reqF_c_r$write_1__VAL_2, - MUX_wsiM_reqFifo_c_r$write_1__VAL_1, - MUX_wsiM_reqFifo_c_r$write_1__VAL_2; + wire [1 : 0] MUX_wci_wslv_respF_cntr_r$write_1__VAL_2, + MUX_wmi_dhF_cntr_r$write_1__VAL_2, + MUX_wmi_mFlagF_cntr_r$write_1__VAL_2, + MUX_wmi_reqF_cntr_r$write_1__VAL_2, + MUX_wsiM_reqFifo_cntr_r$write_1__VAL_1, + MUX_wsiM_reqFifo_cntr_r$write_1__VAL_2; wire MUX_endOfMessage$write_1__SEL_1, MUX_mesgCount$write_1__SEL_1, MUX_mesgReqOK$write_1__SEL_3, @@ -980,80 +977,104 @@ module mkSMAdapter8B(wciS0_Clk, MUX_unrollCnt$write_1__SEL_2, MUX_wci_wslv_illegalEdge$write_1__SEL_1, MUX_wci_wslv_illegalEdge$write_1__VAL_1, + MUX_wci_wslv_respF_q_0$write_1__SEL_1, MUX_wci_wslv_respF_q_0$write_1__SEL_2, + MUX_wci_wslv_respF_q_1$write_1__SEL_1, MUX_wci_wslv_respF_q_1$write_1__SEL_2, + MUX_wmi_dhF_q_0$write_1__SEL_1, MUX_wmi_dhF_q_0$write_1__SEL_2, + MUX_wmi_dhF_q_1$write_1__SEL_1, MUX_wmi_dhF_q_1$write_1__SEL_2, + MUX_wmi_mFlagF_q_0$write_1__SEL_1, MUX_wmi_mFlagF_q_0$write_1__SEL_2, + MUX_wmi_mFlagF_q_1$write_1__SEL_1, MUX_wmi_mFlagF_q_1$write_1__SEL_2, MUX_wmi_mFlagF_x_wire$wset_1__SEL_1, + MUX_wmi_reqF_q_0$write_1__SEL_1, MUX_wmi_reqF_q_0$write_1__SEL_2, + MUX_wmi_reqF_q_1$write_1__SEL_1, MUX_wmi_reqF_q_1$write_1__SEL_2, + MUX_wsiM_reqFifo_q_0$write_1__SEL_1, MUX_wsiM_reqFifo_q_0$write_1__SEL_2, + MUX_wsiM_reqFifo_q_1$write_1__SEL_1, MUX_wsiM_reqFifo_q_1$write_1__SEL_2, MUX_wsiM_reqFifo_x_wire$wset_1__SEL_1, MUX_wsiM_reqFifo_x_wire$wset_1__SEL_2, MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3; // remaining internal signals - reg [63 : 0] v__h18699, - v__h22418, - v__h22477, - v__h23989, - v__h24172, - v__h24368, - v__h25030, - v__h3729, - v__h3904, - v__h4048; - reg [31 : 0] g_data__h24540; - wire [91 : 0] IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d896; - wire [31 : 0] rdat__h24583, - rdat__h24589, - rdat__h24595, - rdat__h24608, - rdat__h24631, - rdat__h24731, - rdat__h24745, - rdat__h24753, - rdat__h24759, - rdat__h24773, - rdat__h24781, - rdat__h24787, - rdat__h24793, - rdat__h24799, - rdat__h24805, - rdat__h24815, - value__h6702, - x__h19302; - wire [23 : 0] b__h18410, - mesgMetaF_length__h22999, - residue__h18273, - x__h18530; - wire [15 : 0] wsiBurstLength__h19161, x__h24635, x_length__h23563; - wire [13 : 0] b__h18783, mlB__h22832, mlInc__h22831; - wire [11 : 0] b__h15473, sendData_burstLength__h19243, x__h16878; - wire [7 : 0] mesgMetaF_opcode__h22998, sendData_byteEn__h19245; - wire [3 : 0] x__h23038, - x__h23050, - x__h23062, - x__h23074, - x__h23086, - x__h23098, - x__h23110, - y__h23039, - y__h23051, - y__h23063, - y__h23075, - y__h23087, - y__h23099, - y__h23111; - wire [2 : 0] IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d894; - wire NOT_wmi_reqF_c_r_57_EQ_2_75_76_AND_wmi_operate_ETC___d524, - wmi_respF_i_notEmpty__37_AND_smaCtrl_65_BIT_4__ETC___d542, - wsiS_reqFifo_i_notEmpty__64_AND_NOT_smaCtrl_65_ETC___d670, - x__h18954, - x__h24809; + reg [63 : 0] v__h18073, + v__h21792, + v__h21851, + v__h23361, + v__h23544, + v__h23740, + v__h24397, + v__h3597, + v__h3772, + v__h3916; + reg [31 : 0] g_data__h23912; + wire [91 : 0] IF_respF_wDataIn_whas__28_THEN_respF_wDataIn_w_ETC___d437; + wire [31 : 0] rdat__h23955, + rdat__h23961, + rdat__h23967, + rdat__h23980, + rdat__h24003, + rdat__h24103, + rdat__h24117, + rdat__h24125, + rdat__h24131, + rdat__h24145, + rdat__h24153, + rdat__h24159, + rdat__h24165, + rdat__h24171, + rdat__h24177, + rdat__h24187, + value__h6387, + x__h18676; + wire [23 : 0] b__h17784, + mesgMetaF_length__h22373, + residue__h17647, + x__h17904; + wire [15 : 0] wsiBurstLength__h18535, x__h24007, x_length__h22936; + wire [13 : 0] b__h18157, mlB__h22206, mlInc__h22205; + wire [11 : 0] b__h14802, sendData_burstLength__h18617, x__h16103, x__h16253; + wire [7 : 0] mesgMetaF_opcode__h22372, sendData_byteEn__h18619; + wire [3 : 0] x__h22411, + x__h22423, + x__h22435, + x__h22447, + x__h22459, + x__h22471, + x__h22483, + y__h22412, + y__h22424, + y__h22436, + y__h22448, + y__h22460, + y__h22472, + y__h22484; + wire [2 : 0] IF_respF_wDataIn_whas__28_THEN_respF_wDataIn_w_ETC___d431; + wire [1 : 0] wci_wslv_respF_cntr_r_8_MINUS_1___d27, + wmi_dhF_cntr_r_05_MINUS_1___d213, + wmi_mFlagF_cntr_r_83_MINUS_1___d191, + wmi_reqF_cntr_r_61_MINUS_1___d169; + wire NOT_wmi_reqF_cntr_r_61_EQ_2_73_74_AND_wmi_oper_ETC___d521, + _dfoo1, + _dfoo11, + _dfoo13, + _dfoo15, + _dfoo17, + _dfoo19, + _dfoo3, + _dfoo5, + _dfoo7, + _dfoo9, + wmi_respF_i_notEmpty__34_AND_smaCtrl_62_BIT_4__ETC___d539, + wsiS_reqFifo_i_notEmpty__61_AND_NOT_smaCtrl_62_ETC___d667, + x__h18328, + x__h24181; // value method wciS0_sResp assign wciS0_SResp = wci_wslv_respF_q_0[33:32] ; @@ -1212,7 +1233,7 @@ module mkSMAdapter8B(wciS0_Clk, // rule RL_wmrd_mesgBodyRequest assign WILL_FIRE_RL_wmrd_mesgBodyRequest = - NOT_wmi_reqF_c_r_57_EQ_2_75_76_AND_wmi_operate_ETC___d524 && + NOT_wmi_reqF_cntr_r_61_EQ_2_73_74_AND_wmi_oper_ETC___d521 && wci_wslv_cState == 3'd2 && (smaCtrl[3:0] == 4'h1 || smaCtrl[3:0] == 4'h4 || smaCtrl[3:0] == 4'h9) && @@ -1243,18 +1264,18 @@ module mkSMAdapter8B(wciS0_Clk, // rule RL_wsiM_reqFifo_deq assign WILL_FIRE_RL_wsiM_reqFifo_deq = - wsiM_reqFifo_c_r != 2'd0 && !wsiM_sThreadBusy_d ; + wsiM_reqFifo_cntr_r != 2'd0 && !wsiM_sThreadBusy_d ; // rule RL_wsipass_doMessagePush assign WILL_FIRE_RL_wsipass_doMessagePush = wsiS_reqFifo$EMPTY_N && - (smaCtrl[4] || wsiM_reqFifo_c_r != 2'd2) && + (smaCtrl[4] || wsiM_reqFifo_cntr_r != 2'd2) && wci_wslv_cState == 3'd2 && smaCtrl[3:0] == 4'h0 ; // rule RL_wci_cfrd assign WILL_FIRE_RL_wci_cfrd = - wci_wslv_respF_c_r != 2'd2 && wci_wslv_reqF$EMPTY_N && + wci_wslv_respF_cntr_r != 2'd2 && wci_wslv_reqF$EMPTY_N && wci_wslv_wci_cfrd_pw$whas && !WILL_FIRE_RL_wci_wslv_ctl_op_start && !WILL_FIRE_RL_wci_wslv_ctl_op_complete ; @@ -1273,9 +1294,10 @@ module mkSMAdapter8B(wciS0_Clk, // rule RL_wmwt_messagePush assign CAN_FIRE_RL_wmwt_messagePush = - wmi_reqF_c_r != 2'd2 && wmi_dhF_c_r != 2'd2 && wmi_operateD && + wmi_reqF_cntr_r != 2'd2 && wmi_dhF_cntr_r != 2'd2 && + wmi_operateD && wmi_peerIsReady && - wsiS_reqFifo_i_notEmpty__64_AND_NOT_smaCtrl_65_ETC___d670 && + wsiS_reqFifo_i_notEmpty__61_AND_NOT_smaCtrl_62_ETC___d667 && wci_wslv_cState == 3'd2 && (smaCtrl[3:0] == 4'h2 || smaCtrl[3:0] == 4'h3) && readyToPush ; @@ -1295,10 +1317,7 @@ module mkSMAdapter8B(wciS0_Clk, // rule RL_wmi_reqF_incCtr assign WILL_FIRE_RL_wmi_reqF_incCtr = - ((wmi_reqF_c_r == 2'd0) ? - wmi_reqF_x_wire$whas : - wmi_reqF_c_r != 2'd1 || wmi_reqF_x_wire$whas) && - wmi_reqF_enqueueing$whas && + wmi_reqF_x_wire$whas && wmi_reqF_enqueueing$whas && !wmi_reqF_dequeueing$whas ; // rule RL_wmi_reqF_decCtr @@ -1307,18 +1326,12 @@ module mkSMAdapter8B(wciS0_Clk, // rule RL_wmi_reqF_both assign WILL_FIRE_RL_wmi_reqF_both = - ((wmi_reqF_c_r == 2'd1) ? - wmi_reqF_x_wire$whas : - wmi_reqF_c_r != 2'd2 || wmi_reqF_x_wire$whas) && - wmi_reqF_dequeueing$whas && + wmi_reqF_x_wire$whas && wmi_reqF_dequeueing$whas && wmi_reqF_enqueueing$whas ; // rule RL_wmi_mFlagF_incCtr assign WILL_FIRE_RL_wmi_mFlagF_incCtr = - ((wmi_mFlagF_c_r == 2'd0) ? - wmi_mFlagF_enqueueing$whas : - wmi_mFlagF_c_r != 2'd1 || wmi_mFlagF_enqueueing$whas) && - wmi_mFlagF_enqueueing$whas && + wmi_mFlagF_enqueueing$whas && wmi_mFlagF_enqueueing$whas && !wmi_mFlagF_dequeueing$whas ; // rule RL_wmi_mFlagF_decCtr @@ -1327,18 +1340,12 @@ module mkSMAdapter8B(wciS0_Clk, // rule RL_wmi_mFlagF_both assign WILL_FIRE_RL_wmi_mFlagF_both = - ((wmi_mFlagF_c_r == 2'd1) ? - wmi_mFlagF_enqueueing$whas : - wmi_mFlagF_c_r != 2'd2 || wmi_mFlagF_enqueueing$whas) && - wmi_mFlagF_dequeueing$whas && + wmi_mFlagF_enqueueing$whas && wmi_mFlagF_dequeueing$whas && wmi_mFlagF_enqueueing$whas ; // rule RL_wmi_dhF_incCtr assign WILL_FIRE_RL_wmi_dhF_incCtr = - ((wmi_dhF_c_r == 2'd0) ? - MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 : - wmi_dhF_c_r != 2'd1 || - MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3) && + MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 && MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 && !wmi_dhF_dequeueing$whas ; @@ -1349,33 +1356,27 @@ module mkSMAdapter8B(wciS0_Clk, // rule RL_wmi_dhF_both assign WILL_FIRE_RL_wmi_dhF_both = - ((wmi_dhF_c_r == 2'd1) ? - MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 : - wmi_dhF_c_r != 2'd2 || - MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3) && + MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 && wmi_dhF_dequeueing$whas && MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 ; // rule RL_wmrd_mesgResptoWsi assign WILL_FIRE_RL_wmrd_mesgResptoWsi = - wsiM_reqFifo_c_r != 2'd2 && respF_rRdPtr != respF_rWrPtr && + wsiM_reqFifo_cntr_r != 2'd2 && respF_rRdPtr != respF_rWrPtr && wci_wslv_cState == 3'd2 && (smaCtrl[3:0] == 4'h1 || smaCtrl[3:0] == 4'h4 || smaCtrl[3:0] == 4'h9) ; // rule RL_wci_cfwr assign WILL_FIRE_RL_wci_cfwr = - wci_wslv_respF_c_r != 2'd2 && wci_wslv_reqF$EMPTY_N && + wci_wslv_respF_cntr_r != 2'd2 && wci_wslv_reqF$EMPTY_N && wci_wslv_wci_cfwr_pw$whas && !WILL_FIRE_RL_wci_wslv_ctl_op_start && !WILL_FIRE_RL_wci_wslv_ctl_op_complete ; // rule RL_wsiM_reqFifo_incCtr assign WILL_FIRE_RL_wsiM_reqFifo_incCtr = - ((wsiM_reqFifo_c_r == 2'd0) ? - wsiM_reqFifo_enqueueing$whas : - wsiM_reqFifo_c_r != 2'd1 || wsiM_reqFifo_enqueueing$whas) && - wsiM_reqFifo_enqueueing$whas && + wsiM_reqFifo_enqueueing$whas && wsiM_reqFifo_enqueueing$whas && !WILL_FIRE_RL_wsiM_reqFifo_deq ; // rule RL_wsiM_reqFifo_decCtr @@ -1384,10 +1385,7 @@ module mkSMAdapter8B(wciS0_Clk, // rule RL_wsiM_reqFifo_both assign WILL_FIRE_RL_wsiM_reqFifo_both = - ((wsiM_reqFifo_c_r == 2'd1) ? - wsiM_reqFifo_enqueueing$whas : - wsiM_reqFifo_c_r != 2'd2 || wsiM_reqFifo_enqueueing$whas) && - WILL_FIRE_RL_wsiM_reqFifo_deq && + wsiM_reqFifo_enqueueing$whas && WILL_FIRE_RL_wsiM_reqFifo_deq && wsiM_reqFifo_enqueueing$whas ; // rule RL_wci_ctrl_IsO @@ -1399,27 +1397,22 @@ module mkSMAdapter8B(wciS0_Clk, // rule RL_wci_wslv_ctl_op_complete assign WILL_FIRE_RL_wci_wslv_ctl_op_complete = - wci_wslv_respF_c_r != 2'd2 && wci_wslv_ctlOpActive && + wci_wslv_respF_cntr_r != 2'd2 && wci_wslv_ctlOpActive && wci_wslv_ctlAckReg ; // rule RL_wci_wslv_respF_incCtr assign WILL_FIRE_RL_wci_wslv_respF_incCtr = - ((wci_wslv_respF_c_r == 2'd0) ? - wci_wslv_respF_x_wire$whas : - wci_wslv_respF_c_r != 2'd1 || wci_wslv_respF_x_wire$whas) && - wci_wslv_respF_enqueueing$whas && - !(wci_wslv_respF_c_r != 2'd0) ; + wci_wslv_respF_x_wire$whas && wci_wslv_respF_enqueueing$whas && + !(wci_wslv_respF_cntr_r != 2'd0) ; // rule RL_wci_wslv_respF_decCtr assign WILL_FIRE_RL_wci_wslv_respF_decCtr = - wci_wslv_respF_c_r != 2'd0 && !wci_wslv_respF_enqueueing$whas ; + wci_wslv_respF_cntr_r != 2'd0 && + !wci_wslv_respF_enqueueing$whas ; // rule RL_wci_wslv_respF_both assign WILL_FIRE_RL_wci_wslv_respF_both = - ((wci_wslv_respF_c_r == 2'd1) ? - wci_wslv_respF_x_wire$whas : - wci_wslv_respF_c_r != 2'd2 || wci_wslv_respF_x_wire$whas) && - wci_wslv_respF_c_r != 2'd0 && + wci_wslv_respF_x_wire$whas && wci_wslv_respF_cntr_r != 2'd0 && wci_wslv_respF_enqueueing$whas ; // rule RL_wsiS_reqFifo_enq @@ -1448,7 +1441,7 @@ module mkSMAdapter8B(wciS0_Clk, !wmi_sDataThreadBusy_d && unrollCnt == 16'd0 ; assign MUX_unrollCnt$write_1__SEL_2 = - wmi_respF_i_notEmpty__37_AND_smaCtrl_65_BIT_4__ETC___d542 && + wmi_respF_i_notEmpty__34_AND_smaCtrl_62_BIT_4__ETC___d539 && wci_wslv_cState == 3'd2 && (smaCtrl[3:0] == 4'h1 || smaCtrl[3:0] == 4'h4 || smaCtrl[3:0] == 4'h9) && @@ -1466,66 +1459,86 @@ module mkSMAdapter8B(wciS0_Clk, wci_wslv_reqF$D_OUT[36:34] == 3'd5 || wci_wslv_reqF$D_OUT[36:34] == 3'd6 || wci_wslv_reqF$D_OUT[36:34] == 3'd7) ; + assign MUX_wci_wslv_respF_q_0$write_1__SEL_1 = + WILL_FIRE_RL_wci_wslv_respF_both && _dfoo3 ; assign MUX_wci_wslv_respF_q_0$write_1__SEL_2 = WILL_FIRE_RL_wci_wslv_respF_incCtr && - wci_wslv_respF_c_r == 2'd0 ; + wci_wslv_respF_cntr_r == 2'd0 ; + assign MUX_wci_wslv_respF_q_1$write_1__SEL_1 = + WILL_FIRE_RL_wci_wslv_respF_both && _dfoo1 ; assign MUX_wci_wslv_respF_q_1$write_1__SEL_2 = WILL_FIRE_RL_wci_wslv_respF_incCtr && - wci_wslv_respF_c_r == 2'd1 ; + wci_wslv_respF_cntr_r == 2'd1 ; + assign MUX_wmi_dhF_q_0$write_1__SEL_1 = + WILL_FIRE_RL_wmi_dhF_incCtr && wmi_dhF_cntr_r == 2'd0 ; assign MUX_wmi_dhF_q_0$write_1__SEL_2 = - WILL_FIRE_RL_wmi_dhF_incCtr && wmi_dhF_c_r == 2'd0 ; + WILL_FIRE_RL_wmi_dhF_both && _dfoo15 ; + assign MUX_wmi_dhF_q_1$write_1__SEL_1 = + WILL_FIRE_RL_wmi_dhF_incCtr && wmi_dhF_cntr_r == 2'd1 ; assign MUX_wmi_dhF_q_1$write_1__SEL_2 = - WILL_FIRE_RL_wmi_dhF_incCtr && wmi_dhF_c_r == 2'd1 ; + WILL_FIRE_RL_wmi_dhF_both && _dfoo13 ; + assign MUX_wmi_mFlagF_q_0$write_1__SEL_1 = + WILL_FIRE_RL_wmi_mFlagF_both && _dfoo11 ; assign MUX_wmi_mFlagF_q_0$write_1__SEL_2 = - WILL_FIRE_RL_wmi_mFlagF_incCtr && wmi_mFlagF_c_r == 2'd0 ; + WILL_FIRE_RL_wmi_mFlagF_incCtr && wmi_mFlagF_cntr_r == 2'd0 ; + assign MUX_wmi_mFlagF_q_1$write_1__SEL_1 = + WILL_FIRE_RL_wmi_mFlagF_both && _dfoo9 ; assign MUX_wmi_mFlagF_q_1$write_1__SEL_2 = - WILL_FIRE_RL_wmi_mFlagF_incCtr && wmi_mFlagF_c_r == 2'd1 ; + WILL_FIRE_RL_wmi_mFlagF_incCtr && wmi_mFlagF_cntr_r == 2'd1 ; assign MUX_wmi_mFlagF_x_wire$wset_1__SEL_1 = - WILL_FIRE_RL_wmrd_mesgBodyRequest && x__h18954 ; + WILL_FIRE_RL_wmrd_mesgBodyRequest && x__h18328 ; + assign MUX_wmi_reqF_q_0$write_1__SEL_1 = + WILL_FIRE_RL_wmi_reqF_both && _dfoo7 ; assign MUX_wmi_reqF_q_0$write_1__SEL_2 = - WILL_FIRE_RL_wmi_reqF_incCtr && wmi_reqF_c_r == 2'd0 ; + WILL_FIRE_RL_wmi_reqF_incCtr && wmi_reqF_cntr_r == 2'd0 ; + assign MUX_wmi_reqF_q_1$write_1__SEL_1 = + WILL_FIRE_RL_wmi_reqF_both && _dfoo5 ; assign MUX_wmi_reqF_q_1$write_1__SEL_2 = - WILL_FIRE_RL_wmi_reqF_incCtr && wmi_reqF_c_r == 2'd1 ; + WILL_FIRE_RL_wmi_reqF_incCtr && wmi_reqF_cntr_r == 2'd1 ; + assign MUX_wsiM_reqFifo_q_0$write_1__SEL_1 = + WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_cntr_r == 2'd0 ; assign MUX_wsiM_reqFifo_q_0$write_1__SEL_2 = - WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_c_r == 2'd0 ; + WILL_FIRE_RL_wsiM_reqFifo_both && _dfoo19 ; + assign MUX_wsiM_reqFifo_q_1$write_1__SEL_1 = + WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_cntr_r == 2'd1 ; assign MUX_wsiM_reqFifo_q_1$write_1__SEL_2 = - WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_c_r == 2'd1 ; + WILL_FIRE_RL_wsiM_reqFifo_both && _dfoo17 ; assign MUX_wsiM_reqFifo_x_wire$wset_1__SEL_1 = - WILL_FIRE_RL_wsipass_doMessagePush && !smaCtrl[4] ; - assign MUX_wsiM_reqFifo_x_wire$wset_1__SEL_2 = MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 && smaCtrl[3:0] == 4'h3 ; + assign MUX_wsiM_reqFifo_x_wire$wset_1__SEL_2 = + WILL_FIRE_RL_wsipass_doMessagePush && !smaCtrl[4] ; assign MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 = CAN_FIRE_RL_wmwt_messagePush && !WILL_FIRE_RL_wmwt_messageFinalize ; assign MUX_fabRespCredit_value$write_1__VAL_2 = fabRespCredit_value + - (WILL_FIRE_RL_wmrd_mesgBodyRequest ? b__h15473 : 12'd0) + + (WILL_FIRE_RL_wmrd_mesgBodyRequest ? b__h14802 : 12'd0) + (WILL_FIRE_RL_wmrd_mesgResptoWsi ? 12'd1 : 12'd0) ; assign MUX_fabWordsRemain$write_1__VAL_1 = - (wmi_sFlagReg[23:0] == 24'd0) ? 14'd1 : b__h18410[13:0] ; + (wmi_sFlagReg[23:0] == 24'd0) ? 14'd1 : b__h17784[13:0] ; assign MUX_fabWordsRemain$write_1__VAL_2 = fabWordsRemain - fabWordsCurReq ; - assign MUX_mesgCount$write_1__VAL_1 = mesgCount + 32'd1 ; + assign MUX_mesgCount$write_1__VAL_2 = mesgCount + 32'd1 ; assign MUX_mesgLengthSoFar$write_1__VAL_1 = - mesgLengthSoFar + mlInc__h22831 ; + mesgLengthSoFar + mlInc__h22205 ; assign MUX_mesgReqAddr$write_1__VAL_2 = mesgReqAddr + { fabWordsCurReq[10:0], 3'd0 } ; assign MUX_opcode$write_1__VAL_3 = { 1'd1, wsiS_reqFifo$D_OUT[7:0] } ; assign MUX_thisMesg$write_1__VAL_1 = - { mesgCount[7:0], mesgMetaF_opcode__h22998, x_length__h23563 } ; + { mesgCount[7:0], mesgMetaF_opcode__h22372, x_length__h22936 } ; assign MUX_thisMesg$write_1__VAL_2 = { mesgCount[7:0], wmi_sFlagReg[31:24], wmi_sFlagReg[15:0] } ; assign MUX_unrollCnt$write_1__VAL_1 = - (wmi_sFlagReg[23:0] == 24'd0) ? 16'd1 : b__h18410[15:0] ; + (wmi_sFlagReg[23:0] == 24'd0) ? 16'd1 : b__h17784[15:0] ; assign MUX_unrollCnt$write_1__VAL_2 = unrollCnt - 16'd1 ; assign MUX_wci_wslv_illegalEdge$write_1__VAL_1 = wci_wslv_reqF$D_OUT[36:34] != 3'd4 && wci_wslv_reqF$D_OUT[36:34] != 3'd5 && wci_wslv_reqF$D_OUT[36:34] != 3'd6 ; - assign MUX_wci_wslv_respF_c_r$write_1__VAL_1 = wci_wslv_respF_c_r + 2'd1 ; - assign MUX_wci_wslv_respF_c_r$write_1__VAL_2 = wci_wslv_respF_c_r - 2'd1 ; + assign MUX_wci_wslv_respF_cntr_r$write_1__VAL_2 = + wci_wslv_respF_cntr_r + 2'd1 ; assign MUX_wci_wslv_respF_q_0$write_1__VAL_1 = - (wci_wslv_respF_c_r == 2'd1) ? + (wci_wslv_respF_cntr_r == 2'd1) ? MUX_wci_wslv_respF_q_0$write_1__VAL_2 : wci_wslv_respF_q_1 ; always@(WILL_FIRE_RL_wci_wslv_ctl_op_complete or @@ -1547,34 +1560,33 @@ module mkSMAdapter8B(wciS0_Clk, endcase end assign MUX_wci_wslv_respF_q_1$write_1__VAL_1 = - (wci_wslv_respF_c_r == 2'd2) ? + (wci_wslv_respF_cntr_r == 2'd2) ? MUX_wci_wslv_respF_q_0$write_1__VAL_2 : 34'h0AAAAAAAA ; assign MUX_wci_wslv_respF_x_wire$wset_1__VAL_1 = wci_wslv_illegalEdge ? 34'h3C0DE4202 : 34'h1C0DE4201 ; - assign MUX_wci_wslv_respF_x_wire$wset_1__VAL_2 = { 2'd1, g_data__h24540 } ; - assign MUX_wmi_dhF_c_r$write_1__VAL_1 = wmi_dhF_c_r + 2'd1 ; - assign MUX_wmi_dhF_c_r$write_1__VAL_2 = wmi_dhF_c_r - 2'd1 ; + assign MUX_wci_wslv_respF_x_wire$wset_1__VAL_2 = { 2'd1, g_data__h23912 } ; + assign MUX_wmi_dhF_cntr_r$write_1__VAL_2 = wmi_dhF_cntr_r + 2'd1 ; assign MUX_wmi_dhF_q_0$write_1__VAL_1 = - (wmi_dhF_c_r == 2'd1) ? - MUX_wmi_dhF_q_0$write_1__VAL_2 : - wmi_dhF_q_1 ; - assign MUX_wmi_dhF_q_0$write_1__VAL_2 = { 1'd1, wsiS_reqFifo$D_OUT[93], wsiS_reqFifo$D_OUT[79:8] } ; - assign MUX_wmi_dhF_q_1$write_1__VAL_1 = - (wmi_dhF_c_r == 2'd2) ? MUX_wmi_dhF_q_0$write_1__VAL_2 : 74'd0 ; - assign MUX_wmi_mFlagF_c_r$write_1__VAL_1 = wmi_mFlagF_c_r + 2'd1 ; - assign MUX_wmi_mFlagF_c_r$write_1__VAL_2 = wmi_mFlagF_c_r - 2'd1 ; + assign MUX_wmi_dhF_q_0$write_1__VAL_2 = + (wmi_dhF_cntr_r == 2'd1) ? + MUX_wmi_dhF_q_0$write_1__VAL_1 : + wmi_dhF_q_1 ; + assign MUX_wmi_dhF_q_1$write_1__VAL_2 = + (wmi_dhF_cntr_r == 2'd2) ? + MUX_wmi_dhF_q_0$write_1__VAL_1 : + 74'd0 ; + assign MUX_wmi_mFlagF_cntr_r$write_1__VAL_2 = wmi_mFlagF_cntr_r + 2'd1 ; assign MUX_wmi_mFlagF_q_0$write_1__VAL_1 = - (wmi_mFlagF_c_r == 2'd1) ? value__h6702 : wmi_mFlagF_q_1 ; + (wmi_mFlagF_cntr_r == 2'd1) ? value__h6387 : wmi_mFlagF_q_1 ; assign MUX_wmi_mFlagF_q_1$write_1__VAL_1 = - (wmi_mFlagF_c_r == 2'd2) ? value__h6702 : 32'd0 ; + (wmi_mFlagF_cntr_r == 2'd2) ? value__h6387 : 32'd0 ; assign MUX_wmi_mFlagF_x_wire$wset_1__VAL_2 = - { mesgMetaF_opcode__h22998, mesgMetaF_length__h22999 } ; - assign MUX_wmi_reqF_c_r$write_1__VAL_1 = wmi_reqF_c_r + 2'd1 ; - assign MUX_wmi_reqF_c_r$write_1__VAL_2 = wmi_reqF_c_r - 2'd1 ; + { mesgMetaF_opcode__h22372, mesgMetaF_length__h22373 } ; + assign MUX_wmi_reqF_cntr_r$write_1__VAL_2 = wmi_reqF_cntr_r + 2'd1 ; assign MUX_wmi_reqF_q_0$write_1__VAL_1 = - (wmi_reqF_c_r == 2'd1) ? + (wmi_reqF_cntr_r == 2'd1) ? MUX_wmi_reqF_q_0$write_1__VAL_2 : wmi_reqF_q_1 ; assign MUX_wmi_reqF_q_0$write_1__VAL_2 = @@ -1582,27 +1594,27 @@ module mkSMAdapter8B(wciS0_Clk, MUX_wmi_reqF_x_wire$wset_1__VAL_1 : MUX_wmi_reqF_x_wire$wset_1__VAL_2 ; assign MUX_wmi_reqF_q_1$write_1__VAL_1 = - (wmi_reqF_c_r == 2'd2) ? + (wmi_reqF_cntr_r == 2'd2) ? MUX_wmi_reqF_q_0$write_1__VAL_2 : 32'd0 ; assign MUX_wmi_reqF_x_wire$wset_1__VAL_1 = - { 4'd5, x__h18954, 1'b0, mesgReqAddr, fabWordsCurReq[11:0] } ; + { 4'd5, x__h18328, 1'b0, mesgReqAddr, fabWordsCurReq[11:0] } ; assign MUX_wmi_reqF_x_wire$wset_1__VAL_2 = { 4'd3, wsiS_reqFifo$D_OUT[93], 1'b0, mesgLengthSoFar, 12'd1 } ; - assign MUX_wsiM_reqFifo_c_r$write_1__VAL_1 = wsiM_reqFifo_c_r + 2'd1 ; - assign MUX_wsiM_reqFifo_c_r$write_1__VAL_2 = wsiM_reqFifo_c_r - 2'd1 ; + assign MUX_wsiM_reqFifo_cntr_r$write_1__VAL_1 = wsiM_reqFifo_cntr_r - 2'd1 ; + assign MUX_wsiM_reqFifo_cntr_r$write_1__VAL_2 = wsiM_reqFifo_cntr_r + 2'd1 ; assign MUX_wsiM_reqFifo_q_0$write_1__VAL_1 = - (wsiM_reqFifo_c_r == 2'd1) ? - MUX_wsiM_reqFifo_q_0$write_1__VAL_2 : - wsiM_reqFifo_q_1 ; - assign MUX_wsiM_reqFifo_q_0$write_1__VAL_2 = (MUX_wsiM_reqFifo_x_wire$wset_1__SEL_1 || MUX_wsiM_reqFifo_x_wire$wset_1__SEL_2) ? wsiS_reqFifo$D_OUT : MUX_wsiM_reqFifo_x_wire$wset_1__VAL_3 ; - assign MUX_wsiM_reqFifo_q_1$write_1__VAL_1 = - (wsiM_reqFifo_c_r == 2'd2) ? - MUX_wsiM_reqFifo_q_0$write_1__VAL_2 : + assign MUX_wsiM_reqFifo_q_0$write_1__VAL_2 = + (wsiM_reqFifo_cntr_r == 2'd1) ? + MUX_wsiM_reqFifo_q_0$write_1__VAL_1 : + wsiM_reqFifo_q_1 ; + assign MUX_wsiM_reqFifo_q_1$write_1__VAL_2 = + (wsiM_reqFifo_cntr_r == 2'd2) ? + MUX_wsiM_reqFifo_q_0$write_1__VAL_1 : 97'h00000AAAAAAAAAAAAAAAAAA00 ; assign MUX_wsiM_reqFifo_x_wire$wset_1__VAL_3 = (respF_rCache[109] && respF_rCache[108:97] == respF_rRdPtr) ? @@ -1643,9 +1655,9 @@ module mkSMAdapter8B(wciS0_Clk, assign wmi_reqF_x_wire$whas = WILL_FIRE_RL_wmrd_mesgBodyRequest || MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 ; - assign wmi_mFlagF_x_wire$wget = value__h6702 ; + assign wmi_mFlagF_x_wire$wget = value__h6387 ; assign wmi_mFlagF_x_wire$whas = wmi_mFlagF_enqueueing$whas ; - assign wmi_dhF_x_wire$wget = MUX_wmi_dhF_q_0$write_1__VAL_2 ; + assign wmi_dhF_x_wire$wget = MUX_wmi_dhF_q_0$write_1__VAL_1 ; assign wmi_dhF_x_wire$whas = MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 ; assign wmi_wmiResponse$wget = { wmiM0_SResp, wmiM0_SData } ; assign wmi_wmiResponse$whas = 1'd1 ; @@ -1657,7 +1669,7 @@ module mkSMAdapter8B(wciS0_Clk, assign wmi_operateD_1$whas = wci_wslv_cState == 3'd2 ; assign wmi_peerIsReady_1$wget = 1'd1 ; assign wmi_peerIsReady_1$whas = wmiM0_SReset_n ; - assign wsiM_reqFifo_x_wire$wget = MUX_wsiM_reqFifo_q_0$write_1__VAL_2 ; + assign wsiM_reqFifo_x_wire$wget = MUX_wsiM_reqFifo_q_0$write_1__VAL_1 ; assign wsiM_reqFifo_x_wire$whas = wsiM_reqFifo_enqueueing$whas ; assign wsiM_operateD_1$wget = 1'd1 ; assign wsiM_operateD_1$whas = wci_wslv_cState == 3'd2 ; @@ -1679,7 +1691,7 @@ module mkSMAdapter8B(wciS0_Clk, assign wsiS_sThreadBusy_dw$wget = wsiS_reqFifo_countReg > 2'd1 ; assign wsiS_sThreadBusy_dw$whas = wsiS_reqFifo_levelsValid && wsiS_operateD && wsiS_peerIsReady ; - assign fabRespCredit_acc_v1$wget = b__h15473 ; + assign fabRespCredit_acc_v1$wget = b__h14802 ; assign fabRespCredit_acc_v1$whas = WILL_FIRE_RL_wmrd_mesgBodyRequest ; assign fabRespCredit_acc_v2$wget = 12'd1 ; assign fabRespCredit_acc_v2$whas = WILL_FIRE_RL_wmrd_mesgResptoWsi ; @@ -1689,9 +1701,9 @@ module mkSMAdapter8B(wciS0_Clk, { 3'd1, unrollCnt == 16'd1, !smaCtrl[5], - sendData_burstLength__h19243, + sendData_burstLength__h18617, wmi_respF$D_OUT[63:0], - sendData_byteEn__h19245, + sendData_byteEn__h18619, thisMesg[23:16] } ; assign respF_wDataIn$whas = respF_pwEnqueue$whas ; assign respF_wDataOut$wget = MUX_wsiM_reqFifo_x_wire$wset_1__VAL_3 ; @@ -1718,7 +1730,7 @@ module mkSMAdapter8B(wciS0_Clk, assign wci_wslv_respF_enqueueing$whas = WILL_FIRE_RL_wci_cfrd || WILL_FIRE_RL_wci_cfwr || WILL_FIRE_RL_wci_wslv_ctl_op_complete ; - assign wci_wslv_respF_dequeueing$whas = wci_wslv_respF_c_r != 2'd0 ; + assign wci_wslv_respF_dequeueing$whas = wci_wslv_respF_cntr_r != 2'd0 ; assign wci_wslv_sThreadBusy_pw$whas = 1'b0 ; assign wci_wslv_wci_cfwr_pw$whas = wci_wslv_reqF$EMPTY_N && wci_wslv_reqF$D_OUT[68] && @@ -1733,23 +1745,23 @@ module mkSMAdapter8B(wciS0_Clk, MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 || WILL_FIRE_RL_wmrd_mesgBodyRequest ; assign wmi_reqF_dequeueing$whas = - WILL_FIRE_RL_wmi_reqF_deq && wmi_reqF_c_r != 2'd0 ; + WILL_FIRE_RL_wmi_reqF_deq && wmi_reqF_cntr_r != 2'd0 ; assign wmi_mFlagF_enqueueing$whas = - WILL_FIRE_RL_wmrd_mesgBodyRequest && x__h18954 || + WILL_FIRE_RL_wmrd_mesgBodyRequest && x__h18328 || MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 && wsiS_reqFifo$D_OUT[93] ; assign wmi_mFlagF_dequeueing$whas = WILL_FIRE_RL_wmi_reqF_deq && wmi_reqF_q_0[27] && - wmi_mFlagF_c_r != 2'd0 ; + wmi_mFlagF_cntr_r != 2'd0 ; assign wmi_dhF_enqueueing$whas = MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 ; assign wmi_dhF_dequeueing$whas = wmi_operateD && wmi_peerIsReady && !wmi_sDataThreadBusy_d && - wmi_dhF_c_r != 2'd0 ; + wmi_dhF_cntr_r != 2'd0 ; assign wsiM_reqFifo_enqueueing$whas = - WILL_FIRE_RL_wsipass_doMessagePush && !smaCtrl[4] || MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 && smaCtrl[3:0] == 4'h3 || + WILL_FIRE_RL_wsipass_doMessagePush && !smaCtrl[4] || WILL_FIRE_RL_wmrd_mesgResptoWsi ; assign wsiM_reqFifo_dequeueing$whas = WILL_FIRE_RL_wsiM_reqFifo_deq ; assign wsiM_sThreadBusy_pw$whas = wsiM0_SThreadBusy ; @@ -1763,6 +1775,7 @@ module mkSMAdapter8B(wciS0_Clk, assign wsiS_reqFifo_doResetClr$whas = 1'b0 ; assign respF_pwDequeue$whas = WILL_FIRE_RL_wmrd_mesgResptoWsi ; assign respF_pwEnqueue$whas = MUX_unrollCnt$write_1__SEL_2 && !smaCtrl[4] ; + assign respF_pwClear$whas = 1'b0 ; assign wsi_Es_mReqLast_w$whas = wsiS0_MReqLast ; assign wsi_Es_mBurstPrecise_w$whas = wsiS0_MBurstPrecise ; assign wsi_Es_mDataInfo_w$whas = 1'd1 ; @@ -1803,7 +1816,7 @@ module mkSMAdapter8B(wciS0_Clk, // register fabWordsCurReq assign fabWordsCurReq$D_IN = - (fabWordsRemain <= b__h18783) ? fabWordsRemain : b__h18783 ; + (fabWordsRemain <= b__h18157) ? fabWordsRemain : b__h18157 ; assign fabWordsCurReq$EN = MUX_mesgReqOK$write_1__SEL_3 ; // register fabWordsRemain @@ -1833,14 +1846,14 @@ module mkSMAdapter8B(wciS0_Clk, // register mesgCount always@(MUX_mesgCount$write_1__SEL_1 or - MUX_mesgCount$write_1__VAL_1 or + MUX_mesgCount$write_1__VAL_2 or WILL_FIRE_RL_wmwt_messageFinalize or WILL_FIRE_RL_wci_ctrl_IsO) begin case (1'b1) // synopsys parallel_case MUX_mesgCount$write_1__SEL_1: - mesgCount$D_IN = MUX_mesgCount$write_1__VAL_1; + mesgCount$D_IN = MUX_mesgCount$write_1__VAL_2; WILL_FIRE_RL_wmwt_messageFinalize: - mesgCount$D_IN = MUX_mesgCount$write_1__VAL_1; + mesgCount$D_IN = MUX_mesgCount$write_1__VAL_2; WILL_FIRE_RL_wci_ctrl_IsO: mesgCount$D_IN = 32'd0; default: mesgCount$D_IN = 32'hAAAAAAAA /* unspecified value */ ; endcase @@ -1909,18 +1922,18 @@ module mkSMAdapter8B(wciS0_Clk, assign respF_rCache$D_IN = { 1'd1, respF_rWrPtr, - IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d894, + IF_respF_wDataIn_whas__28_THEN_respF_wDataIn_w_ETC___d431, respF_pwEnqueue$whas && respF_wDataIn$wget[93], respF_pwEnqueue$whas && respF_wDataIn$wget[92], - IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d896 } ; + IF_respF_wDataIn_whas__28_THEN_respF_wDataIn_w_ETC___d437 } ; assign respF_rCache$EN = respF_pwEnqueue$whas ; // register respF_rRdPtr - assign respF_rRdPtr$D_IN = x__h16878 ; + assign respF_rRdPtr$D_IN = x__h16253 ; assign respF_rRdPtr$EN = WILL_FIRE_RL_wmrd_mesgResptoWsi ; // register respF_rWrPtr - assign respF_rWrPtr$D_IN = respF_rWrPtr + 12'd1 ; + assign respF_rWrPtr$D_IN = x__h16103 ; assign respF_rWrPtr$EN = respF_pwEnqueue$whas ; // register smaCtrl @@ -2024,24 +2037,24 @@ module mkSMAdapter8B(wciS0_Clk, (wci_wslv_wciReq$wget[71:69] != 3'd0) != wci_wslv_reqF_r_deq$whas ; - // register wci_wslv_respF_c_r - assign wci_wslv_respF_c_r$D_IN = - WILL_FIRE_RL_wci_wslv_respF_incCtr ? - MUX_wci_wslv_respF_c_r$write_1__VAL_1 : - MUX_wci_wslv_respF_c_r$write_1__VAL_2 ; - assign wci_wslv_respF_c_r$EN = - WILL_FIRE_RL_wci_wslv_respF_incCtr || - WILL_FIRE_RL_wci_wslv_respF_decCtr ; + // register wci_wslv_respF_cntr_r + assign wci_wslv_respF_cntr_r$D_IN = + WILL_FIRE_RL_wci_wslv_respF_decCtr ? + wci_wslv_respF_cntr_r_8_MINUS_1___d27 : + MUX_wci_wslv_respF_cntr_r$write_1__VAL_2 ; + assign wci_wslv_respF_cntr_r$EN = + WILL_FIRE_RL_wci_wslv_respF_decCtr || + WILL_FIRE_RL_wci_wslv_respF_incCtr ; // register wci_wslv_respF_q_0 - always@(WILL_FIRE_RL_wci_wslv_respF_both or + always@(MUX_wci_wslv_respF_q_0$write_1__SEL_1 or MUX_wci_wslv_respF_q_0$write_1__VAL_1 or MUX_wci_wslv_respF_q_0$write_1__SEL_2 or MUX_wci_wslv_respF_q_0$write_1__VAL_2 or WILL_FIRE_RL_wci_wslv_respF_decCtr or wci_wslv_respF_q_1) begin case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_wci_wslv_respF_both: + MUX_wci_wslv_respF_q_0$write_1__SEL_1: wci_wslv_respF_q_0$D_IN = MUX_wci_wslv_respF_q_0$write_1__VAL_1; MUX_wci_wslv_respF_q_0$write_1__SEL_2: wci_wslv_respF_q_0$D_IN = MUX_wci_wslv_respF_q_0$write_1__VAL_2; @@ -2052,20 +2065,20 @@ module mkSMAdapter8B(wciS0_Clk, endcase end assign wci_wslv_respF_q_0$EN = - WILL_FIRE_RL_wci_wslv_respF_both || + WILL_FIRE_RL_wci_wslv_respF_both && _dfoo3 || WILL_FIRE_RL_wci_wslv_respF_incCtr && - wci_wslv_respF_c_r == 2'd0 || + wci_wslv_respF_cntr_r == 2'd0 || WILL_FIRE_RL_wci_wslv_respF_decCtr ; // register wci_wslv_respF_q_1 - always@(WILL_FIRE_RL_wci_wslv_respF_both or + always@(MUX_wci_wslv_respF_q_1$write_1__SEL_1 or MUX_wci_wslv_respF_q_1$write_1__VAL_1 or MUX_wci_wslv_respF_q_1$write_1__SEL_2 or MUX_wci_wslv_respF_q_0$write_1__VAL_2 or WILL_FIRE_RL_wci_wslv_respF_decCtr) begin case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_wci_wslv_respF_both: + MUX_wci_wslv_respF_q_1$write_1__SEL_1: wci_wslv_respF_q_1$D_IN = MUX_wci_wslv_respF_q_1$write_1__VAL_1; MUX_wci_wslv_respF_q_1$write_1__SEL_2: wci_wslv_respF_q_1$D_IN = MUX_wci_wslv_respF_q_0$write_1__VAL_2; @@ -2076,9 +2089,9 @@ module mkSMAdapter8B(wciS0_Clk, endcase end assign wci_wslv_respF_q_1$EN = - WILL_FIRE_RL_wci_wslv_respF_both || + WILL_FIRE_RL_wci_wslv_respF_both && _dfoo1 || WILL_FIRE_RL_wci_wslv_respF_incCtr && - wci_wslv_respF_c_r == 2'd1 || + wci_wslv_respF_cntr_r == 2'd1 || WILL_FIRE_RL_wci_wslv_respF_decCtr ; // register wci_wslv_sFlagReg @@ -2093,23 +2106,23 @@ module mkSMAdapter8B(wciS0_Clk, assign wmi_busyWithMessage$D_IN = 1'b0 ; assign wmi_busyWithMessage$EN = 1'b0 ; - // register wmi_dhF_c_r - assign wmi_dhF_c_r$D_IN = - WILL_FIRE_RL_wmi_dhF_incCtr ? - MUX_wmi_dhF_c_r$write_1__VAL_1 : - MUX_wmi_dhF_c_r$write_1__VAL_2 ; - assign wmi_dhF_c_r$EN = - WILL_FIRE_RL_wmi_dhF_incCtr || WILL_FIRE_RL_wmi_dhF_decCtr ; + // register wmi_dhF_cntr_r + assign wmi_dhF_cntr_r$D_IN = + WILL_FIRE_RL_wmi_dhF_decCtr ? + wmi_dhF_cntr_r_05_MINUS_1___d213 : + MUX_wmi_dhF_cntr_r$write_1__VAL_2 ; + assign wmi_dhF_cntr_r$EN = + WILL_FIRE_RL_wmi_dhF_decCtr || WILL_FIRE_RL_wmi_dhF_incCtr ; // register wmi_dhF_q_0 - always@(WILL_FIRE_RL_wmi_dhF_both or + always@(MUX_wmi_dhF_q_0$write_1__SEL_1 or MUX_wmi_dhF_q_0$write_1__VAL_1 or MUX_wmi_dhF_q_0$write_1__SEL_2 or MUX_wmi_dhF_q_0$write_1__VAL_2 or WILL_FIRE_RL_wmi_dhF_decCtr or wmi_dhF_q_1) begin case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_wmi_dhF_both: + MUX_wmi_dhF_q_0$write_1__SEL_1: wmi_dhF_q_0$D_IN = MUX_wmi_dhF_q_0$write_1__VAL_1; MUX_wmi_dhF_q_0$write_1__SEL_2: wmi_dhF_q_0$D_IN = MUX_wmi_dhF_q_0$write_1__VAL_2; @@ -2119,29 +2132,29 @@ module mkSMAdapter8B(wciS0_Clk, endcase end assign wmi_dhF_q_0$EN = - WILL_FIRE_RL_wmi_dhF_both || - WILL_FIRE_RL_wmi_dhF_incCtr && wmi_dhF_c_r == 2'd0 || + WILL_FIRE_RL_wmi_dhF_incCtr && wmi_dhF_cntr_r == 2'd0 || + WILL_FIRE_RL_wmi_dhF_both && _dfoo15 || WILL_FIRE_RL_wmi_dhF_decCtr ; // register wmi_dhF_q_1 - always@(WILL_FIRE_RL_wmi_dhF_both or - MUX_wmi_dhF_q_1$write_1__VAL_1 or + always@(MUX_wmi_dhF_q_1$write_1__SEL_1 or + MUX_wmi_dhF_q_0$write_1__VAL_1 or MUX_wmi_dhF_q_1$write_1__SEL_2 or - MUX_wmi_dhF_q_0$write_1__VAL_2 or WILL_FIRE_RL_wmi_dhF_decCtr) + MUX_wmi_dhF_q_1$write_1__VAL_2 or WILL_FIRE_RL_wmi_dhF_decCtr) begin case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_wmi_dhF_both: - wmi_dhF_q_1$D_IN = MUX_wmi_dhF_q_1$write_1__VAL_1; + MUX_wmi_dhF_q_1$write_1__SEL_1: + wmi_dhF_q_1$D_IN = MUX_wmi_dhF_q_0$write_1__VAL_1; MUX_wmi_dhF_q_1$write_1__SEL_2: - wmi_dhF_q_1$D_IN = MUX_wmi_dhF_q_0$write_1__VAL_2; + wmi_dhF_q_1$D_IN = MUX_wmi_dhF_q_1$write_1__VAL_2; WILL_FIRE_RL_wmi_dhF_decCtr: wmi_dhF_q_1$D_IN = 74'd0; default: wmi_dhF_q_1$D_IN = 74'h2AAAAAAAAAAAAAAAAAA /* unspecified value */ ; endcase end assign wmi_dhF_q_1$EN = - WILL_FIRE_RL_wmi_dhF_both || - WILL_FIRE_RL_wmi_dhF_incCtr && wmi_dhF_c_r == 2'd1 || + WILL_FIRE_RL_wmi_dhF_incCtr && wmi_dhF_cntr_r == 2'd1 || + WILL_FIRE_RL_wmi_dhF_both && _dfoo13 || WILL_FIRE_RL_wmi_dhF_decCtr ; // register wmi_errorSticky @@ -2152,51 +2165,51 @@ module mkSMAdapter8B(wciS0_Clk, assign wmi_isReset_isInReset$D_IN = 1'd0 ; assign wmi_isReset_isInReset$EN = wmi_isReset_isInReset ; - // register wmi_mFlagF_c_r - assign wmi_mFlagF_c_r$D_IN = - WILL_FIRE_RL_wmi_mFlagF_incCtr ? - MUX_wmi_mFlagF_c_r$write_1__VAL_1 : - MUX_wmi_mFlagF_c_r$write_1__VAL_2 ; - assign wmi_mFlagF_c_r$EN = - WILL_FIRE_RL_wmi_mFlagF_incCtr || - WILL_FIRE_RL_wmi_mFlagF_decCtr ; + // register wmi_mFlagF_cntr_r + assign wmi_mFlagF_cntr_r$D_IN = + WILL_FIRE_RL_wmi_mFlagF_decCtr ? + wmi_mFlagF_cntr_r_83_MINUS_1___d191 : + MUX_wmi_mFlagF_cntr_r$write_1__VAL_2 ; + assign wmi_mFlagF_cntr_r$EN = + WILL_FIRE_RL_wmi_mFlagF_decCtr || + WILL_FIRE_RL_wmi_mFlagF_incCtr ; // register wmi_mFlagF_q_0 - always@(WILL_FIRE_RL_wmi_mFlagF_both or + always@(MUX_wmi_mFlagF_q_0$write_1__SEL_1 or MUX_wmi_mFlagF_q_0$write_1__VAL_1 or MUX_wmi_mFlagF_q_0$write_1__SEL_2 or - value__h6702 or WILL_FIRE_RL_wmi_mFlagF_decCtr or wmi_mFlagF_q_1) + value__h6387 or WILL_FIRE_RL_wmi_mFlagF_decCtr or wmi_mFlagF_q_1) begin case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_wmi_mFlagF_both: + MUX_wmi_mFlagF_q_0$write_1__SEL_1: wmi_mFlagF_q_0$D_IN = MUX_wmi_mFlagF_q_0$write_1__VAL_1; - MUX_wmi_mFlagF_q_0$write_1__SEL_2: wmi_mFlagF_q_0$D_IN = value__h6702; + MUX_wmi_mFlagF_q_0$write_1__SEL_2: wmi_mFlagF_q_0$D_IN = value__h6387; WILL_FIRE_RL_wmi_mFlagF_decCtr: wmi_mFlagF_q_0$D_IN = wmi_mFlagF_q_1; default: wmi_mFlagF_q_0$D_IN = 32'hAAAAAAAA /* unspecified value */ ; endcase end assign wmi_mFlagF_q_0$EN = - WILL_FIRE_RL_wmi_mFlagF_both || - WILL_FIRE_RL_wmi_mFlagF_incCtr && wmi_mFlagF_c_r == 2'd0 || + WILL_FIRE_RL_wmi_mFlagF_both && _dfoo11 || + WILL_FIRE_RL_wmi_mFlagF_incCtr && wmi_mFlagF_cntr_r == 2'd0 || WILL_FIRE_RL_wmi_mFlagF_decCtr ; // register wmi_mFlagF_q_1 - always@(WILL_FIRE_RL_wmi_mFlagF_both or + always@(MUX_wmi_mFlagF_q_1$write_1__SEL_1 or MUX_wmi_mFlagF_q_1$write_1__VAL_1 or MUX_wmi_mFlagF_q_1$write_1__SEL_2 or - value__h6702 or WILL_FIRE_RL_wmi_mFlagF_decCtr) + value__h6387 or WILL_FIRE_RL_wmi_mFlagF_decCtr) begin case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_wmi_mFlagF_both: + MUX_wmi_mFlagF_q_1$write_1__SEL_1: wmi_mFlagF_q_1$D_IN = MUX_wmi_mFlagF_q_1$write_1__VAL_1; - MUX_wmi_mFlagF_q_1$write_1__SEL_2: wmi_mFlagF_q_1$D_IN = value__h6702; + MUX_wmi_mFlagF_q_1$write_1__SEL_2: wmi_mFlagF_q_1$D_IN = value__h6387; WILL_FIRE_RL_wmi_mFlagF_decCtr: wmi_mFlagF_q_1$D_IN = 32'd0; default: wmi_mFlagF_q_1$D_IN = 32'hAAAAAAAA /* unspecified value */ ; endcase end assign wmi_mFlagF_q_1$EN = - WILL_FIRE_RL_wmi_mFlagF_both || - WILL_FIRE_RL_wmi_mFlagF_incCtr && wmi_mFlagF_c_r == 2'd1 || + WILL_FIRE_RL_wmi_mFlagF_both && _dfoo9 || + WILL_FIRE_RL_wmi_mFlagF_incCtr && wmi_mFlagF_cntr_r == 2'd1 || WILL_FIRE_RL_wmi_mFlagF_decCtr ; // register wmi_operateD @@ -2207,23 +2220,23 @@ module mkSMAdapter8B(wciS0_Clk, assign wmi_peerIsReady$D_IN = wmiM0_SReset_n ; assign wmi_peerIsReady$EN = 1'd1 ; - // register wmi_reqF_c_r - assign wmi_reqF_c_r$D_IN = - WILL_FIRE_RL_wmi_reqF_incCtr ? - MUX_wmi_reqF_c_r$write_1__VAL_1 : - MUX_wmi_reqF_c_r$write_1__VAL_2 ; - assign wmi_reqF_c_r$EN = - WILL_FIRE_RL_wmi_reqF_incCtr || WILL_FIRE_RL_wmi_reqF_decCtr ; + // register wmi_reqF_cntr_r + assign wmi_reqF_cntr_r$D_IN = + WILL_FIRE_RL_wmi_reqF_decCtr ? + wmi_reqF_cntr_r_61_MINUS_1___d169 : + MUX_wmi_reqF_cntr_r$write_1__VAL_2 ; + assign wmi_reqF_cntr_r$EN = + WILL_FIRE_RL_wmi_reqF_decCtr || WILL_FIRE_RL_wmi_reqF_incCtr ; // register wmi_reqF_q_0 - always@(WILL_FIRE_RL_wmi_reqF_both or + always@(MUX_wmi_reqF_q_0$write_1__SEL_1 or MUX_wmi_reqF_q_0$write_1__VAL_1 or MUX_wmi_reqF_q_0$write_1__SEL_2 or MUX_wmi_reqF_q_0$write_1__VAL_2 or WILL_FIRE_RL_wmi_reqF_decCtr or wmi_reqF_q_1) begin case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_wmi_reqF_both: + MUX_wmi_reqF_q_0$write_1__SEL_1: wmi_reqF_q_0$D_IN = MUX_wmi_reqF_q_0$write_1__VAL_1; MUX_wmi_reqF_q_0$write_1__SEL_2: wmi_reqF_q_0$D_IN = MUX_wmi_reqF_q_0$write_1__VAL_2; @@ -2232,18 +2245,18 @@ module mkSMAdapter8B(wciS0_Clk, endcase end assign wmi_reqF_q_0$EN = - WILL_FIRE_RL_wmi_reqF_both || - WILL_FIRE_RL_wmi_reqF_incCtr && wmi_reqF_c_r == 2'd0 || + WILL_FIRE_RL_wmi_reqF_both && _dfoo7 || + WILL_FIRE_RL_wmi_reqF_incCtr && wmi_reqF_cntr_r == 2'd0 || WILL_FIRE_RL_wmi_reqF_decCtr ; // register wmi_reqF_q_1 - always@(WILL_FIRE_RL_wmi_reqF_both or + always@(MUX_wmi_reqF_q_1$write_1__SEL_1 or MUX_wmi_reqF_q_1$write_1__VAL_1 or MUX_wmi_reqF_q_1$write_1__SEL_2 or MUX_wmi_reqF_q_0$write_1__VAL_2 or WILL_FIRE_RL_wmi_reqF_decCtr) begin case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_wmi_reqF_both: + MUX_wmi_reqF_q_1$write_1__SEL_1: wmi_reqF_q_1$D_IN = MUX_wmi_reqF_q_1$write_1__VAL_1; MUX_wmi_reqF_q_1$write_1__SEL_2: wmi_reqF_q_1$D_IN = MUX_wmi_reqF_q_0$write_1__VAL_2; @@ -2252,8 +2265,8 @@ module mkSMAdapter8B(wciS0_Clk, endcase end assign wmi_reqF_q_1$EN = - WILL_FIRE_RL_wmi_reqF_both || - WILL_FIRE_RL_wmi_reqF_incCtr && wmi_reqF_c_r == 2'd1 || + WILL_FIRE_RL_wmi_reqF_both && _dfoo5 || + WILL_FIRE_RL_wmi_reqF_incCtr && wmi_reqF_cntr_r == 2'd1 || WILL_FIRE_RL_wmi_reqF_decCtr ; // register wmi_sDataThreadBusy_d @@ -2332,24 +2345,24 @@ module mkSMAdapter8B(wciS0_Clk, assign wsiM_peerIsReady$D_IN = wsiM0_SReset_n ; assign wsiM_peerIsReady$EN = 1'd1 ; - // register wsiM_reqFifo_c_r - assign wsiM_reqFifo_c_r$D_IN = - WILL_FIRE_RL_wsiM_reqFifo_incCtr ? - MUX_wsiM_reqFifo_c_r$write_1__VAL_1 : - MUX_wsiM_reqFifo_c_r$write_1__VAL_2 ; - assign wsiM_reqFifo_c_r$EN = - WILL_FIRE_RL_wsiM_reqFifo_incCtr || - WILL_FIRE_RL_wsiM_reqFifo_decCtr ; + // register wsiM_reqFifo_cntr_r + assign wsiM_reqFifo_cntr_r$D_IN = + WILL_FIRE_RL_wsiM_reqFifo_decCtr ? + MUX_wsiM_reqFifo_cntr_r$write_1__VAL_1 : + MUX_wsiM_reqFifo_cntr_r$write_1__VAL_2 ; + assign wsiM_reqFifo_cntr_r$EN = + WILL_FIRE_RL_wsiM_reqFifo_decCtr || + WILL_FIRE_RL_wsiM_reqFifo_incCtr ; // register wsiM_reqFifo_q_0 - always@(WILL_FIRE_RL_wsiM_reqFifo_both or + always@(MUX_wsiM_reqFifo_q_0$write_1__SEL_1 or MUX_wsiM_reqFifo_q_0$write_1__VAL_1 or MUX_wsiM_reqFifo_q_0$write_1__SEL_2 or MUX_wsiM_reqFifo_q_0$write_1__VAL_2 or WILL_FIRE_RL_wsiM_reqFifo_decCtr or wsiM_reqFifo_q_1) begin case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_wsiM_reqFifo_both: + MUX_wsiM_reqFifo_q_0$write_1__SEL_1: wsiM_reqFifo_q_0$D_IN = MUX_wsiM_reqFifo_q_0$write_1__VAL_1; MUX_wsiM_reqFifo_q_0$write_1__SEL_2: wsiM_reqFifo_q_0$D_IN = MUX_wsiM_reqFifo_q_0$write_1__VAL_2; @@ -2360,22 +2373,23 @@ module mkSMAdapter8B(wciS0_Clk, endcase end assign wsiM_reqFifo_q_0$EN = - WILL_FIRE_RL_wsiM_reqFifo_both || - WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_c_r == 2'd0 || + WILL_FIRE_RL_wsiM_reqFifo_incCtr && + wsiM_reqFifo_cntr_r == 2'd0 || + WILL_FIRE_RL_wsiM_reqFifo_both && _dfoo19 || WILL_FIRE_RL_wsiM_reqFifo_decCtr ; // register wsiM_reqFifo_q_1 - always@(WILL_FIRE_RL_wsiM_reqFifo_both or - MUX_wsiM_reqFifo_q_1$write_1__VAL_1 or + always@(MUX_wsiM_reqFifo_q_1$write_1__SEL_1 or + MUX_wsiM_reqFifo_q_0$write_1__VAL_1 or MUX_wsiM_reqFifo_q_1$write_1__SEL_2 or - MUX_wsiM_reqFifo_q_0$write_1__VAL_2 or + MUX_wsiM_reqFifo_q_1$write_1__VAL_2 or WILL_FIRE_RL_wsiM_reqFifo_decCtr) begin case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_wsiM_reqFifo_both: - wsiM_reqFifo_q_1$D_IN = MUX_wsiM_reqFifo_q_1$write_1__VAL_1; + MUX_wsiM_reqFifo_q_1$write_1__SEL_1: + wsiM_reqFifo_q_1$D_IN = MUX_wsiM_reqFifo_q_0$write_1__VAL_1; MUX_wsiM_reqFifo_q_1$write_1__SEL_2: - wsiM_reqFifo_q_1$D_IN = MUX_wsiM_reqFifo_q_0$write_1__VAL_2; + wsiM_reqFifo_q_1$D_IN = MUX_wsiM_reqFifo_q_1$write_1__VAL_2; WILL_FIRE_RL_wsiM_reqFifo_decCtr: wsiM_reqFifo_q_1$D_IN = 97'h00000AAAAAAAAAAAAAAAAAA00; default: wsiM_reqFifo_q_1$D_IN = @@ -2383,8 +2397,9 @@ module mkSMAdapter8B(wciS0_Clk, endcase end assign wsiM_reqFifo_q_1$EN = - WILL_FIRE_RL_wsiM_reqFifo_both || - WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_c_r == 2'd1 || + WILL_FIRE_RL_wsiM_reqFifo_incCtr && + wsiM_reqFifo_cntr_r == 2'd1 || + WILL_FIRE_RL_wsiM_reqFifo_both && _dfoo17 || WILL_FIRE_RL_wsiM_reqFifo_decCtr ; // register wsiM_sThreadBusy_d @@ -2510,19 +2525,19 @@ module mkSMAdapter8B(wciS0_Clk, assign respF_memory$ADDRA = respF_rWrPtr[10:0] ; assign respF_memory$ADDRB = WILL_FIRE_RL_wmrd_mesgResptoWsi ? - x__h16878[10:0] : + x__h16253[10:0] : respF_rRdPtr[10:0] ; assign respF_memory$DIA = - { IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d894, + { IF_respF_wDataIn_whas__28_THEN_respF_wDataIn_w_ETC___d431, respF_pwEnqueue$whas && respF_wDataIn$wget[93], respF_pwEnqueue$whas && respF_wDataIn$wget[92], - IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d896 } ; + IF_respF_wDataIn_whas__28_THEN_respF_wDataIn_w_ETC___d437 } ; assign respF_memory$DIB = 97'h0AAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ; assign respF_memory$WEA = respF_pwEnqueue$whas ; assign respF_memory$WEB = 1'd0 ; - assign respF_memory$ENA = 1'd1 ; - assign respF_memory$ENB = 1'd1 ; + assign respF_memory$ENA = 1'b1 ; + assign respF_memory$ENB = 1'b1 ; // submodule wci_wslv_reqF assign wci_wslv_reqF$D_IN = wci_wslv_wciReq$wget ; @@ -2545,70 +2560,106 @@ module mkSMAdapter8B(wciS0_Clk, assign wsiS_reqFifo$CLR = 1'b0 ; // remaining internal signals - assign IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d894 = + assign IF_respF_wDataIn_whas__28_THEN_respF_wDataIn_w_ETC___d431 = respF_pwEnqueue$whas ? respF_wDataIn$wget[96:94] : 3'd0 ; - assign IF_respF_wDataIn_whas__33_THEN_respF_wDataIn_w_ETC___d896 = + assign IF_respF_wDataIn_whas__28_THEN_respF_wDataIn_w_ETC___d437 = respF_pwEnqueue$whas ? respF_wDataIn$wget[91:0] : 92'd0 ; - assign NOT_wmi_reqF_c_r_57_EQ_2_75_76_AND_wmi_operate_ETC___d524 = - wmi_reqF_c_r != 2'd2 && wmi_operateD && wmi_peerIsReady && - (!x__h18954 || wmi_mFlagF_c_r != 2'd2) ; - assign b__h15473 = -fabWordsCurReq[11:0] ; - assign b__h18410 = x__h18530 + residue__h18273 ; - assign b__h18783 = { {2{fabRespCredit_value[11]}}, fabRespCredit_value } ; - assign mesgMetaF_length__h22999 = + assign NOT_wmi_reqF_cntr_r_61_EQ_2_73_74_AND_wmi_oper_ETC___d521 = + wmi_reqF_cntr_r != 2'd2 && wmi_operateD && wmi_peerIsReady && + (!x__h18328 || wmi_mFlagF_cntr_r != 2'd2) ; + assign _dfoo1 = + wci_wslv_respF_cntr_r != 2'd2 || + wci_wslv_respF_cntr_r_8_MINUS_1___d27 == 2'd1 ; + assign _dfoo11 = + wmi_mFlagF_cntr_r != 2'd1 || + wmi_mFlagF_cntr_r_83_MINUS_1___d191 == 2'd0 ; + assign _dfoo13 = + wmi_dhF_cntr_r != 2'd2 || + wmi_dhF_cntr_r_05_MINUS_1___d213 == 2'd1 ; + assign _dfoo15 = + wmi_dhF_cntr_r != 2'd1 || + wmi_dhF_cntr_r_05_MINUS_1___d213 == 2'd0 ; + assign _dfoo17 = + wsiM_reqFifo_cntr_r != 2'd2 || + MUX_wsiM_reqFifo_cntr_r$write_1__VAL_1 == 2'd1 ; + assign _dfoo19 = + wsiM_reqFifo_cntr_r != 2'd1 || + MUX_wsiM_reqFifo_cntr_r$write_1__VAL_1 == 2'd0 ; + assign _dfoo3 = + wci_wslv_respF_cntr_r != 2'd1 || + wci_wslv_respF_cntr_r_8_MINUS_1___d27 == 2'd0 ; + assign _dfoo5 = + wmi_reqF_cntr_r != 2'd2 || + wmi_reqF_cntr_r_61_MINUS_1___d169 == 2'd1 ; + assign _dfoo7 = + wmi_reqF_cntr_r != 2'd1 || + wmi_reqF_cntr_r_61_MINUS_1___d169 == 2'd0 ; + assign _dfoo9 = + wmi_mFlagF_cntr_r != 2'd2 || + wmi_mFlagF_cntr_r_83_MINUS_1___d191 == 2'd1 ; + assign b__h14802 = -fabWordsCurReq[11:0] ; + assign b__h17784 = x__h17904 + residue__h17647 ; + assign b__h18157 = { {2{fabRespCredit_value[11]}}, fabRespCredit_value } ; + assign mesgMetaF_length__h22373 = (wsiS_reqFifo$D_OUT[93] && wsiS_reqFifo$D_OUT[15:8] == 8'd0 && mesgLengthSoFar == 14'd0) ? 24'd0 : - { 10'd0, mlB__h22832 } ; - assign mesgMetaF_opcode__h22998 = opcode[8] ? opcode[7:0] : 8'd0 ; - assign mlB__h22832 = MUX_mesgLengthSoFar$write_1__VAL_1 ; - assign mlInc__h22831 = + { 10'd0, mlB__h22206 } ; + assign mesgMetaF_opcode__h22372 = opcode[8] ? opcode[7:0] : 8'd0 ; + assign mlB__h22206 = MUX_mesgLengthSoFar$write_1__VAL_1 ; + assign mlInc__h22205 = wsiS_reqFifo$D_OUT[93] ? - { 10'd0, x__h23038 + y__h23039 } : + { 10'd0, x__h22411 + y__h22412 } : 14'd8 ; - assign rdat__h24583 = hasDebugLogic ? mesgCount : 32'd0 ; - assign rdat__h24589 = hasDebugLogic ? abortCount : 32'd0 ; - assign rdat__h24595 = hasDebugLogic ? thisMesg : 32'd0 ; - assign rdat__h24608 = hasDebugLogic ? lastMesg : 32'd0 ; - assign rdat__h24631 = hasDebugLogic ? { 16'd0, x__h24635 } : 32'd0 ; - assign rdat__h24731 = hasDebugLogic ? wsiS_extStatusW$wget[95:64] : 32'd0 ; - assign rdat__h24745 = hasDebugLogic ? wsiS_extStatusW$wget[63:32] : 32'd0 ; - assign rdat__h24753 = hasDebugLogic ? wsiS_extStatusW$wget[31:0] : 32'd0 ; - assign rdat__h24759 = hasDebugLogic ? wsiM_extStatusW$wget[95:64] : 32'd0 ; - assign rdat__h24773 = hasDebugLogic ? wsiM_extStatusW$wget[63:32] : 32'd0 ; - assign rdat__h24781 = hasDebugLogic ? wsiM_extStatusW$wget[31:0] : 32'd0 ; - assign rdat__h24787 = hasDebugLogic ? wmwtBeginCount : 32'd0 ; - assign rdat__h24793 = hasDebugLogic ? wmwtPushCount : 32'd0 ; - assign rdat__h24799 = hasDebugLogic ? wmwtFinalCount : 32'd0 ; - assign rdat__h24805 = hasDebugLogic ? { 31'd0, x__h24809 } : 32'd0 ; - assign rdat__h24815 = hasDebugLogic ? 32'hFEEDC0DE : 32'd0 ; - assign residue__h18273 = + assign rdat__h23955 = hasDebugLogic ? mesgCount : 32'd0 ; + assign rdat__h23961 = hasDebugLogic ? abortCount : 32'd0 ; + assign rdat__h23967 = hasDebugLogic ? thisMesg : 32'd0 ; + assign rdat__h23980 = hasDebugLogic ? lastMesg : 32'd0 ; + assign rdat__h24003 = hasDebugLogic ? { 16'd0, x__h24007 } : 32'd0 ; + assign rdat__h24103 = hasDebugLogic ? wsiS_extStatusW$wget[95:64] : 32'd0 ; + assign rdat__h24117 = hasDebugLogic ? wsiS_extStatusW$wget[63:32] : 32'd0 ; + assign rdat__h24125 = hasDebugLogic ? wsiS_extStatusW$wget[31:0] : 32'd0 ; + assign rdat__h24131 = hasDebugLogic ? wsiM_extStatusW$wget[95:64] : 32'd0 ; + assign rdat__h24145 = hasDebugLogic ? wsiM_extStatusW$wget[63:32] : 32'd0 ; + assign rdat__h24153 = hasDebugLogic ? wsiM_extStatusW$wget[31:0] : 32'd0 ; + assign rdat__h24159 = hasDebugLogic ? wmwtBeginCount : 32'd0 ; + assign rdat__h24165 = hasDebugLogic ? wmwtPushCount : 32'd0 ; + assign rdat__h24171 = hasDebugLogic ? wmwtFinalCount : 32'd0 ; + assign rdat__h24177 = hasDebugLogic ? { 31'd0, x__h24181 } : 32'd0 ; + assign rdat__h24187 = hasDebugLogic ? 32'hFEEDC0DE : 32'd0 ; + assign residue__h17647 = ({ 3'd0, wmi_sFlagReg[2:0] } == 6'd0) ? 24'd0 : 24'd1 ; - assign sendData_burstLength__h19243 = + assign sendData_burstLength__h18617 = (thisMesg[15:0] == 16'd0 || smaCtrl[5] && unrollCnt == 16'd1) ? 12'd1 : - (smaCtrl[5] ? 12'd4095 : wsiBurstLength__h19161[11:0]) ; - assign sendData_byteEn__h19245 = + (smaCtrl[5] ? 12'd4095 : wsiBurstLength__h18535[11:0]) ; + assign sendData_byteEn__h18619 = (thisMesg[15:0] == 16'd0) ? 8'd0 : - ((unrollCnt == 16'd1) ? x__h19302[7:0] : 8'd255) ; - assign value__h6702 = + ((unrollCnt == 16'd1) ? x__h18676[7:0] : 8'd255) ; + assign value__h6387 = MUX_wmi_mFlagF_x_wire$wset_1__SEL_1 ? 32'hAAAAAAAA /* unspecified value */ : MUX_wmi_mFlagF_x_wire$wset_1__VAL_2 ; - assign wmi_respF_i_notEmpty__37_AND_smaCtrl_65_BIT_4__ETC___d542 = + assign wci_wslv_respF_cntr_r_8_MINUS_1___d27 = + wci_wslv_respF_cntr_r - 2'd1 ; + assign wmi_dhF_cntr_r_05_MINUS_1___d213 = wmi_dhF_cntr_r - 2'd1 ; + assign wmi_mFlagF_cntr_r_83_MINUS_1___d191 = wmi_mFlagF_cntr_r - 2'd1 ; + assign wmi_reqF_cntr_r_61_MINUS_1___d169 = wmi_reqF_cntr_r - 2'd1 ; + assign wmi_respF_i_notEmpty__34_AND_smaCtrl_62_BIT_4__ETC___d539 = wmi_respF$EMPTY_N && (smaCtrl[4] || respF_rRdPtr + 12'd1024 != respF_rWrPtr) ; - assign wsiBurstLength__h19161 = + assign wsiBurstLength__h18535 = smaCtrl[5] ? 16'd2 : { 3'd0, thisMesg[15:3] } ; - assign wsiS_reqFifo_i_notEmpty__64_AND_NOT_smaCtrl_65_ETC___d670 = + assign wsiS_reqFifo_i_notEmpty__61_AND_NOT_smaCtrl_62_ETC___d667 = wsiS_reqFifo$EMPTY_N && - (smaCtrl[3:0] != 4'h3 || wsiM_reqFifo_c_r != 2'd2) && - (!wsiS_reqFifo$D_OUT[93] || wmi_mFlagF_c_r != 2'd2) ; - assign x__h16878 = respF_rRdPtr + 12'd1 ; - assign x__h18530 = { 3'd0, wmi_sFlagReg[23:3] } ; - assign x__h18954 = fabWordsRemain == fabWordsCurReq ; - assign x__h19302 = + (smaCtrl[3:0] != 4'h3 || wsiM_reqFifo_cntr_r != 2'd2) && + (!wsiS_reqFifo$D_OUT[93] || wmi_mFlagF_cntr_r != 2'd2) ; + assign x__h16103 = respF_rWrPtr + 12'd1 ; + assign x__h16253 = respF_rRdPtr + 12'd1 ; + assign x__h17904 = { 3'd0, wmi_sFlagReg[23:3] } ; + assign x__h18328 = fabWordsRemain == fabWordsCurReq ; + assign x__h18676 = ({ 3'd0, thisMesg[2:0] } == 6'd0) ? 32'hFFFFFFFF : (({ 3'd0, thisMesg[2:0] } <= 6'd1) ? @@ -2715,58 +2766,58 @@ module mkSMAdapter8B(wciS0_Clk, 6'd31) ? 32'h7FFFFFFF : 32'hFFFFFFFF))))))))))))))))))))))))))))))) ; - assign x__h23038 = x__h23050 + y__h23051 ; - assign x__h23050 = x__h23062 + y__h23063 ; - assign x__h23062 = x__h23074 + y__h23075 ; - assign x__h23074 = x__h23086 + y__h23087 ; - assign x__h23086 = x__h23098 + y__h23099 ; - assign x__h23098 = x__h23110 + y__h23111 ; - assign x__h23110 = { 3'd0, wsiS_reqFifo$D_OUT[15] } ; - assign x__h24635 = { wsiS_statusR, wsiM_statusR } ; - assign x__h24809 = wmi_sThreadBusy_d || wmi_sDataThreadBusy_d ; - assign x_length__h23563 = { 2'd0, mlB__h22832 } ; - assign y__h23039 = { 3'd0, wsiS_reqFifo$D_OUT[8] } ; - assign y__h23051 = { 3'd0, wsiS_reqFifo$D_OUT[9] } ; - assign y__h23063 = { 3'd0, wsiS_reqFifo$D_OUT[10] } ; - assign y__h23075 = { 3'd0, wsiS_reqFifo$D_OUT[11] } ; - assign y__h23087 = { 3'd0, wsiS_reqFifo$D_OUT[12] } ; - assign y__h23099 = { 3'd0, wsiS_reqFifo$D_OUT[13] } ; - assign y__h23111 = { 3'd0, wsiS_reqFifo$D_OUT[14] } ; + assign x__h22411 = x__h22423 + y__h22424 ; + assign x__h22423 = x__h22435 + y__h22436 ; + assign x__h22435 = x__h22447 + y__h22448 ; + assign x__h22447 = x__h22459 + y__h22460 ; + assign x__h22459 = x__h22471 + y__h22472 ; + assign x__h22471 = x__h22483 + y__h22484 ; + assign x__h22483 = { 3'd0, wsiS_reqFifo$D_OUT[15] } ; + assign x__h24007 = { wsiS_statusR, wsiM_statusR } ; + assign x__h24181 = wmi_sThreadBusy_d || wmi_sDataThreadBusy_d ; + assign x_length__h22936 = { 2'd0, mlB__h22206 } ; + assign y__h22412 = { 3'd0, wsiS_reqFifo$D_OUT[8] } ; + assign y__h22424 = { 3'd0, wsiS_reqFifo$D_OUT[9] } ; + assign y__h22436 = { 3'd0, wsiS_reqFifo$D_OUT[10] } ; + assign y__h22448 = { 3'd0, wsiS_reqFifo$D_OUT[11] } ; + assign y__h22460 = { 3'd0, wsiS_reqFifo$D_OUT[12] } ; + assign y__h22472 = { 3'd0, wsiS_reqFifo$D_OUT[13] } ; + assign y__h22484 = { 3'd0, wsiS_reqFifo$D_OUT[14] } ; always@(wci_wslv_reqF$D_OUT or smaCtrl or - rdat__h24583 or - rdat__h24589 or - rdat__h24595 or - rdat__h24608 or - rdat__h24631 or - rdat__h24731 or - rdat__h24745 or - rdat__h24753 or - rdat__h24759 or - rdat__h24773 or - rdat__h24781 or - rdat__h24787 or - rdat__h24793 or rdat__h24799 or rdat__h24805 or rdat__h24815) + rdat__h23955 or + rdat__h23961 or + rdat__h23967 or + rdat__h23980 or + rdat__h24003 or + rdat__h24103 or + rdat__h24117 or + rdat__h24125 or + rdat__h24131 or + rdat__h24145 or + rdat__h24153 or + rdat__h24159 or + rdat__h24165 or rdat__h24171 or rdat__h24177 or rdat__h24187) begin case (wci_wslv_reqF$D_OUT[39:32]) - 8'h0: g_data__h24540 = smaCtrl; - 8'h04: g_data__h24540 = rdat__h24583; - 8'h08: g_data__h24540 = rdat__h24589; - 8'h10: g_data__h24540 = rdat__h24595; - 8'h14: g_data__h24540 = rdat__h24608; - 8'h18: g_data__h24540 = rdat__h24631; - 8'h20: g_data__h24540 = rdat__h24731; - 8'h24: g_data__h24540 = rdat__h24745; - 8'h28: g_data__h24540 = rdat__h24753; - 8'h2C: g_data__h24540 = rdat__h24759; - 8'h30: g_data__h24540 = rdat__h24773; - 8'h34: g_data__h24540 = rdat__h24781; - 8'h38: g_data__h24540 = rdat__h24787; - 8'h3C: g_data__h24540 = rdat__h24793; - 8'h40: g_data__h24540 = rdat__h24799; - 8'h44: g_data__h24540 = rdat__h24805; - 8'h48: g_data__h24540 = rdat__h24815; - default: g_data__h24540 = 32'd0; + 8'h0: g_data__h23912 = smaCtrl; + 8'h04: g_data__h23912 = rdat__h23955; + 8'h08: g_data__h23912 = rdat__h23961; + 8'h10: g_data__h23912 = rdat__h23967; + 8'h14: g_data__h23912 = rdat__h23980; + 8'h18: g_data__h23912 = rdat__h24003; + 8'h20: g_data__h23912 = rdat__h24103; + 8'h24: g_data__h23912 = rdat__h24117; + 8'h28: g_data__h23912 = rdat__h24125; + 8'h2C: g_data__h23912 = rdat__h24131; + 8'h30: g_data__h23912 = rdat__h24145; + 8'h34: g_data__h23912 = rdat__h24153; + 8'h38: g_data__h23912 = rdat__h24159; + 8'h3C: g_data__h23912 = rdat__h24165; + 8'h40: g_data__h23912 = rdat__h24171; + 8'h44: g_data__h23912 = rdat__h24177; + 8'h48: g_data__h23912 = rdat__h24187; + default: g_data__h23912 = 32'd0; endcase end @@ -2806,22 +2857,22 @@ module mkSMAdapter8B(wciS0_Clk, wci_wslv_illegalEdge <= `BSV_ASSIGNMENT_DELAY 1'd0; wci_wslv_nState <= `BSV_ASSIGNMENT_DELAY 3'd0; wci_wslv_reqF_countReg <= `BSV_ASSIGNMENT_DELAY 2'd0; - wci_wslv_respF_c_r <= `BSV_ASSIGNMENT_DELAY 2'd0; + wci_wslv_respF_cntr_r <= `BSV_ASSIGNMENT_DELAY 2'd0; wci_wslv_respF_q_0 <= `BSV_ASSIGNMENT_DELAY 34'h0AAAAAAAA; wci_wslv_respF_q_1 <= `BSV_ASSIGNMENT_DELAY 34'h0AAAAAAAA; wci_wslv_sFlagReg <= `BSV_ASSIGNMENT_DELAY 1'd0; wci_wslv_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY 1'd1; wmi_busyWithMessage <= `BSV_ASSIGNMENT_DELAY 1'd0; - wmi_dhF_c_r <= `BSV_ASSIGNMENT_DELAY 2'd0; + wmi_dhF_cntr_r <= `BSV_ASSIGNMENT_DELAY 2'd0; wmi_dhF_q_0 <= `BSV_ASSIGNMENT_DELAY 74'd0; wmi_dhF_q_1 <= `BSV_ASSIGNMENT_DELAY 74'd0; wmi_errorSticky <= `BSV_ASSIGNMENT_DELAY 1'd0; - wmi_mFlagF_c_r <= `BSV_ASSIGNMENT_DELAY 2'd0; + wmi_mFlagF_cntr_r <= `BSV_ASSIGNMENT_DELAY 2'd0; wmi_mFlagF_q_0 <= `BSV_ASSIGNMENT_DELAY 32'd0; wmi_mFlagF_q_1 <= `BSV_ASSIGNMENT_DELAY 32'd0; wmi_operateD <= `BSV_ASSIGNMENT_DELAY 1'd0; wmi_peerIsReady <= `BSV_ASSIGNMENT_DELAY 1'd0; - wmi_reqF_c_r <= `BSV_ASSIGNMENT_DELAY 2'd0; + wmi_reqF_cntr_r <= `BSV_ASSIGNMENT_DELAY 2'd0; wmi_reqF_q_0 <= `BSV_ASSIGNMENT_DELAY 32'd0; wmi_reqF_q_1 <= `BSV_ASSIGNMENT_DELAY 32'd0; wmi_sDataThreadBusy_d <= `BSV_ASSIGNMENT_DELAY 1'd0; @@ -2837,7 +2888,7 @@ module mkSMAdapter8B(wciS0_Clk, wsiM_operateD <= `BSV_ASSIGNMENT_DELAY 1'd0; wsiM_pMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0; wsiM_peerIsReady <= `BSV_ASSIGNMENT_DELAY 1'd0; - wsiM_reqFifo_c_r <= `BSV_ASSIGNMENT_DELAY 2'd0; + wsiM_reqFifo_cntr_r <= `BSV_ASSIGNMENT_DELAY 2'd0; wsiM_reqFifo_q_0 <= `BSV_ASSIGNMENT_DELAY 97'h00000AAAAAAAAAAAAAAAAAA00; wsiM_reqFifo_q_1 <= `BSV_ASSIGNMENT_DELAY @@ -2911,8 +2962,9 @@ module mkSMAdapter8B(wciS0_Clk, if (wci_wslv_reqF_countReg$EN) wci_wslv_reqF_countReg <= `BSV_ASSIGNMENT_DELAY wci_wslv_reqF_countReg$D_IN; - if (wci_wslv_respF_c_r$EN) - wci_wslv_respF_c_r <= `BSV_ASSIGNMENT_DELAY wci_wslv_respF_c_r$D_IN; + if (wci_wslv_respF_cntr_r$EN) + wci_wslv_respF_cntr_r <= `BSV_ASSIGNMENT_DELAY + wci_wslv_respF_cntr_r$D_IN; if (wci_wslv_respF_q_0$EN) wci_wslv_respF_q_0 <= `BSV_ASSIGNMENT_DELAY wci_wslv_respF_q_0$D_IN; if (wci_wslv_respF_q_1$EN) @@ -2925,16 +2977,16 @@ module mkSMAdapter8B(wciS0_Clk, if (wmi_busyWithMessage$EN) wmi_busyWithMessage <= `BSV_ASSIGNMENT_DELAY wmi_busyWithMessage$D_IN; - if (wmi_dhF_c_r$EN) - wmi_dhF_c_r <= `BSV_ASSIGNMENT_DELAY wmi_dhF_c_r$D_IN; + if (wmi_dhF_cntr_r$EN) + wmi_dhF_cntr_r <= `BSV_ASSIGNMENT_DELAY wmi_dhF_cntr_r$D_IN; if (wmi_dhF_q_0$EN) wmi_dhF_q_0 <= `BSV_ASSIGNMENT_DELAY wmi_dhF_q_0$D_IN; if (wmi_dhF_q_1$EN) wmi_dhF_q_1 <= `BSV_ASSIGNMENT_DELAY wmi_dhF_q_1$D_IN; if (wmi_errorSticky$EN) wmi_errorSticky <= `BSV_ASSIGNMENT_DELAY wmi_errorSticky$D_IN; - if (wmi_mFlagF_c_r$EN) - wmi_mFlagF_c_r <= `BSV_ASSIGNMENT_DELAY wmi_mFlagF_c_r$D_IN; + if (wmi_mFlagF_cntr_r$EN) + wmi_mFlagF_cntr_r <= `BSV_ASSIGNMENT_DELAY wmi_mFlagF_cntr_r$D_IN; if (wmi_mFlagF_q_0$EN) wmi_mFlagF_q_0 <= `BSV_ASSIGNMENT_DELAY wmi_mFlagF_q_0$D_IN; if (wmi_mFlagF_q_1$EN) @@ -2943,8 +2995,8 @@ module mkSMAdapter8B(wciS0_Clk, wmi_operateD <= `BSV_ASSIGNMENT_DELAY wmi_operateD$D_IN; if (wmi_peerIsReady$EN) wmi_peerIsReady <= `BSV_ASSIGNMENT_DELAY wmi_peerIsReady$D_IN; - if (wmi_reqF_c_r$EN) - wmi_reqF_c_r <= `BSV_ASSIGNMENT_DELAY wmi_reqF_c_r$D_IN; + if (wmi_reqF_cntr_r$EN) + wmi_reqF_cntr_r <= `BSV_ASSIGNMENT_DELAY wmi_reqF_cntr_r$D_IN; if (wmi_reqF_q_0$EN) wmi_reqF_q_0 <= `BSV_ASSIGNMENT_DELAY wmi_reqF_q_0$D_IN; if (wmi_reqF_q_1$EN) @@ -2976,8 +3028,9 @@ module mkSMAdapter8B(wciS0_Clk, wsiM_pMesgCount <= `BSV_ASSIGNMENT_DELAY wsiM_pMesgCount$D_IN; if (wsiM_peerIsReady$EN) wsiM_peerIsReady <= `BSV_ASSIGNMENT_DELAY wsiM_peerIsReady$D_IN; - if (wsiM_reqFifo_c_r$EN) - wsiM_reqFifo_c_r <= `BSV_ASSIGNMENT_DELAY wsiM_reqFifo_c_r$D_IN; + if (wsiM_reqFifo_cntr_r$EN) + wsiM_reqFifo_cntr_r <= `BSV_ASSIGNMENT_DELAY + wsiM_reqFifo_cntr_r$D_IN; if (wsiM_reqFifo_q_0$EN) wsiM_reqFifo_q_0 <= `BSV_ASSIGNMENT_DELAY wsiM_reqFifo_q_0$D_IN; if (wsiM_reqFifo_q_1$EN) @@ -3086,23 +3139,23 @@ module mkSMAdapter8B(wciS0_Clk, wci_wslv_isReset_isInReset = 1'h0; wci_wslv_nState = 3'h2; wci_wslv_reqF_countReg = 2'h2; - wci_wslv_respF_c_r = 2'h2; + wci_wslv_respF_cntr_r = 2'h2; wci_wslv_respF_q_0 = 34'h2AAAAAAAA; wci_wslv_respF_q_1 = 34'h2AAAAAAAA; wci_wslv_sFlagReg = 1'h0; wci_wslv_sThreadBusy_d = 1'h0; wmi_busyWithMessage = 1'h0; - wmi_dhF_c_r = 2'h2; + wmi_dhF_cntr_r = 2'h2; wmi_dhF_q_0 = 74'h2AAAAAAAAAAAAAAAAAA; wmi_dhF_q_1 = 74'h2AAAAAAAAAAAAAAAAAA; wmi_errorSticky = 1'h0; wmi_isReset_isInReset = 1'h0; - wmi_mFlagF_c_r = 2'h2; + wmi_mFlagF_cntr_r = 2'h2; wmi_mFlagF_q_0 = 32'hAAAAAAAA; wmi_mFlagF_q_1 = 32'hAAAAAAAA; wmi_operateD = 1'h0; wmi_peerIsReady = 1'h0; - wmi_reqF_c_r = 2'h2; + wmi_reqF_cntr_r = 2'h2; wmi_reqF_q_0 = 32'hAAAAAAAA; wmi_reqF_q_1 = 32'hAAAAAAAA; wmi_sDataThreadBusy_d = 1'h0; @@ -3120,7 +3173,7 @@ module mkSMAdapter8B(wciS0_Clk, wsiM_operateD = 1'h0; wsiM_pMesgCount = 32'hAAAAAAAA; wsiM_peerIsReady = 1'h0; - wsiM_reqFifo_c_r = 2'h2; + wsiM_reqFifo_cntr_r = 2'h2; wsiM_reqFifo_q_0 = 97'h0AAAAAAAAAAAAAAAAAAAAAAAA; wsiM_reqFifo_q_1 = 97'h0AAAAAAAAAAAAAAAAAAAAAAAA; wsiM_sThreadBusy_d = 1'h0; @@ -3154,96 +3207,96 @@ module mkSMAdapter8B(wciS0_Clk, if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_start) begin - v__h3729 = $time; + v__h3597 = $time; #0; end if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_start) $display("[%0d]: %m: WCI ControlOp: Starting-transition edge:%x from:%x", - v__h3729, + v__h3597, wci_wslv_reqF$D_OUT[36:34], wci_wslv_cState); if (wciS0_MReset_n != `BSV_RESET_VALUE) if (MUX_unrollCnt$write_1__SEL_1) begin - v__h18699 = $time; + v__h18073 = $time; #0; end if (wciS0_MReset_n != `BSV_RESET_VALUE) if (MUX_unrollCnt$write_1__SEL_1) $display("[%0d]: %m: wmrd_mesgBegin mesgCount:%0h mesgLength:%0h reqInfo:%0h", - v__h18699, + v__h18073, mesgCount, wmi_sFlagReg[23:0], wmi_sFlagReg[31:24]); if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wmwt_mesgBegin && wsiS_reqFifo$D_OUT[92]) begin - v__h22418 = $time; + v__h21792 = $time; #0; end if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wmwt_mesgBegin && wsiS_reqFifo$D_OUT[92]) $display("[%0d]: %m: mesgBegin PRECISE mesgCount:%0x WSI burstLength:%0x reqInfo:%0x", - v__h22418, + v__h21792, mesgCount, wsiS_reqFifo$D_OUT[91:80], wsiS_reqFifo$D_OUT[7:0]); if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wmwt_mesgBegin && !wsiS_reqFifo$D_OUT[92]) begin - v__h22477 = $time; + v__h21851 = $time; #0; end if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wmwt_mesgBegin && !wsiS_reqFifo$D_OUT[92]) $display("[%0d]: %m: wmwt_mesgBegin IMPRECISE mesgCount:%0x", - v__h22477, + v__h21851, mesgCount); if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wmwt_doAbort) begin - v__h23989 = $time; + v__h23361 = $time; #0; end if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wmwt_doAbort) - $display("[%0d]: %m: wmwt_doAbort", v__h23989); + $display("[%0d]: %m: wmwt_doAbort", v__h23361); if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wmwt_messageFinalize) begin - v__h24172 = $time; + v__h23544 = $time; #0; end if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wmwt_messageFinalize) $display("[%0d]: %m: wmwt_messageFinalize mesgCount:%0x WSI mesgLength:%0x", - v__h24172, + v__h23544, mesgCount, thisMesg[15:0]); if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfwr) begin - v__h24368 = $time; + v__h23740 = $time; #0; end if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfwr) $display("[%0d]: %m: SMAdapter WCI CONFIG WRITE Addr:%0x BE:%0x Data:%0x", - v__h24368, + v__h23740, wci_wslv_reqF$D_OUT[63:32], wci_wslv_reqF$D_OUT[67:64], wci_wslv_reqF$D_OUT[31:0]); if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_ctrl_IsO) begin - v__h25030 = $time; + v__h24397 = $time; #0; end if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_ctrl_IsO) $display("[%0d]: %m: Starting SMAdapter smaCtrl:%0x", - v__h25030, + v__h24397, smaCtrl); if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_OrE) @@ -3278,25 +3331,25 @@ module mkSMAdapter8B(wciS0_Clk, if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge) begin - v__h4048 = $time; + v__h3916 = $time; #0; end if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge) $display("[%0d]: %m: WCI ControlOp: ILLEGAL-EDGE Completed-transition edge:%x from:%x", - v__h4048, + v__h3916, wci_wslv_cEdge, wci_wslv_cState); if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && !wci_wslv_illegalEdge) begin - v__h3904 = $time; + v__h3772 = $time; #0; end if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && !wci_wslv_illegalEdge) $display("[%0d]: %m: WCI ControlOp: Completed-transition edge:%x from:%x to:%x", - v__h3904, + v__h3772, wci_wslv_cEdge, wci_wslv_cState, wci_wslv_nState); diff --git a/rtl/mkSimDCP.v b/rtl/mkSimDCP.v index c78dbe8a..97ff5fdb 100644 --- a/rtl/mkSimDCP.v +++ b/rtl/mkSimDCP.v @@ -1,7 +1,7 @@ // -// Generated by Bluespec Compiler, version 2012.09.beta1 (build 29570, 2012-09.11) +// Generated by Bluespec Compiler, version 2013.01.beta1 (build 30202, 2013-01-08) // -// On Mon Nov 19 07:38:55 EST 2012 +// On Tue Jan 22 07:12:40 EST 2013 // // // Ports: @@ -92,8 +92,8 @@ module mkSimDCP(CLK, eDoReq_1$whas, edpFsm_abort$wget, edpFsm_abort$whas, - edpFsm_start_reg_1_1$wget, - edpFsm_start_reg_1_1$whas, + edpFsm_start_reg_2$wget, + edpFsm_start_reg_2$whas, edpFsm_start_wire$wget, edpFsm_start_wire$whas, edpFsm_state_fired_1$wget, @@ -246,33 +246,34 @@ module mkSimDCP(CLK, MUX_edpFsm_state_mkFSMstate$write_1__SEL_1; // remaining internal signals - reg [63 : 0] v__h27055, - v__h27213, - v__h27412, - v__h3767, - v__h3781, - v__h3795, - v__h4547, - v__h5128; - reg [7 : 0] CASE_dcpRespFD_OUT_BITS_44_TO_43_IF_dcpRespF__ETC__q3; - reg CASE_dcpReqFD_OUT_BITS_78_TO_77_IF_NOT_dcpReq_ETC__q2, - CASE_eDMH_BITS_13_TO_12_NOT_eDMH_BITS_13_TO_12_ETC__q1; - wire [31 : 0] x__h1902, - x__h1919, - x__h1964, - x__h2009, - x__h2068, - x__h2113, - x__h2157, - x__h2216, - x__h2261, - x__h2305; - wire [15 : 0] x__h1872, y__h1883; - wire [7 : 0] IF_dcpRespF_first__35_BIT_42_42_THEN_0x70_ELSE_ETC___d397; + reg [63 : 0] v__h26988, + v__h27142, + v__h27335, + v__h3777, + v__h3791, + v__h3805, + v__h4532, + v__h5089; + reg [7 : 0] CASE_dcpRespFD_OUT_BITS_44_TO_43_0_IF_dcpResp_ETC__q4; + reg [1 : 0] CASE_lastResp_BITS_44_TO_43_0_lastResp_BITS_44_ETC__q3; + reg CASE_dcpReqFD_OUT_BITS_78_TO_77_0_dcpRespFFU_ETC__q2, + CASE_eDMH_BITS_13_TO_12_0_dcpReqFFULL_N_0b1_d_ETC__q1; + wire [31 : 0] x__h1896, + x__h1913, + x__h1958, + x__h2003, + x__h2062, + x__h2107, + x__h2151, + x__h2210, + x__h2255, + x__h2299; + wire [15 : 0] x__h1866, y__h1877; + wire [7 : 0] IF_dcpRespF_first__35_BIT_42_42_THEN_0x70_ELSE_ETC___d343; wire IF_NOT_dcpReqF_first__33_BITS_39_TO_32_51_EQ_I_ETC___d158, NOT_dcpReqF_first__33_BITS_78_TO_77_34_EQ_0_35_ETC___d221, - dcpReqF_first__33_BITS_39_TO_32_51_EQ_IF_lastT_ETC___d398, - dcpReqF_first__33_BITS_71_TO_64_38_EQ_IF_lastT_ETC___d395, + dcpReqF_first__33_BITS_39_TO_32_51_EQ_IF_lastT_ETC___d152, + dcpReqF_first__33_BITS_71_TO_64_38_EQ_IF_lastT_ETC___d143, dcpReqF_first__33_BITS_78_TO_77_34_EQ_0_35_OR__ETC___d166, dcpReqF_first__33_BITS_78_TO_77_34_EQ_1_37_AND_ETC___d207, edpFsm_abort_whas__35_AND_edpFsm_abort_wget__3_ETC___d324, @@ -363,13 +364,12 @@ module mkSimDCP(CLK, // rule RL_rx_sim_dcp assign WILL_FIRE_RL_rx_sim_dcp = - CASE_eDMH_BITS_13_TO_12_NOT_eDMH_BITS_13_TO_12_ETC__q1 && - eDoReq ; + CASE_eDMH_BITS_13_TO_12_0_dcpReqFFULL_N_0b1_d_ETC__q1 && eDoReq ; // rule RL_dcp_to_cp_request assign WILL_FIRE_RL_dcp_to_cp_request = dcpReqF$EMPTY_N && - CASE_dcpReqFD_OUT_BITS_78_TO_77_IF_NOT_dcpReq_ETC__q2 ; + CASE_dcpReqFD_OUT_BITS_78_TO_77_0_dcpRespFFU_ETC__q2 ; // rule RL_cp_to_dcp_response assign WILL_FIRE_RL_cp_to_dcp_response = @@ -455,7 +455,8 @@ module mkSimDCP(CLK, assign MUX_edpFsm_state_mkFSMstate$write_1__SEL_1 = WILL_FIRE_RL_edpFsm_idle_l219c3_1 || WILL_FIRE_RL_edpFsm_idle_l219c3 ; - always@(dcpReqF$D_OUT or lastResp) + always@(dcpReqF$D_OUT or + CASE_lastResp_BITS_44_TO_43_0_lastResp_BITS_44_ETC__q3 or lastResp) begin case (dcpReqF$D_OUT[78:77]) 2'd0: @@ -473,9 +474,7 @@ module mkSimDCP(CLK, dcpReqF$D_OUT[71:64], 2'd0 }; default: MUX_dcpRespF$enq_1__VAL_1 = - { (lastResp[44:43] == 2'd0 || lastResp[44:43] == 2'd1) ? - lastResp[44:43] : - 2'd2, + { CASE_lastResp_BITS_44_TO_43_0_lastResp_BITS_44_ETC__q3, lastResp[42:0] }; endcase end @@ -493,8 +492,8 @@ module mkSimDCP(CLK, assign edpFsm_start_wire$whas = WILL_FIRE_RL_edpFsm_fsm_start || edpFsm_start_reg_1 && !edpFsm_state_fired ; - assign edpFsm_start_reg_1_1$wget = 1'd1 ; - assign edpFsm_start_reg_1_1$whas = edpFsm_start_wire$whas ; + assign edpFsm_start_reg_2$wget = 1'd1 ; + assign edpFsm_start_reg_2$whas = edpFsm_start_wire$whas ; assign edpFsm_abort$wget = 1'b0 ; assign edpFsm_abort$whas = 1'b0 ; assign edpFsm_state_fired_1$wget = 1'd1 ; @@ -525,13 +524,13 @@ module mkSimDCP(CLK, WILL_FIRE_RL_cp_to_dcp_response ; // register eAddr - always@(ptr or x__h2157 or x__h1902 or x__h2068 or x__h2113) + always@(ptr or x__h2151 or x__h1896 or x__h2062 or x__h2107) begin case (ptr) - 4'd6: eAddr$D_IN = x__h1902; - 4'd7: eAddr$D_IN = x__h2068; - 4'd8: eAddr$D_IN = x__h2113; - default: eAddr$D_IN = x__h2157; + 4'd6: eAddr$D_IN = x__h1896; + 4'd7: eAddr$D_IN = x__h2062; + 4'd8: eAddr$D_IN = x__h2107; + default: eAddr$D_IN = x__h2151; endcase end assign eAddr$EN = @@ -539,13 +538,13 @@ module mkSimDCP(CLK, (ptr == 4'd6 || ptr == 4'd7 || ptr == 4'd8 || ptr == 4'd9) ; // register eDMH - always@(ptr or x__h2009 or x__h1902 or x__h1919 or x__h1964) + always@(ptr or x__h2003 or x__h1896 or x__h1913 or x__h1958) begin case (ptr) - 4'd2: eDMH$D_IN = x__h1902; - 4'd3: eDMH$D_IN = x__h1919; - 4'd4: eDMH$D_IN = x__h1964; - default: eDMH$D_IN = x__h2009; + 4'd2: eDMH$D_IN = x__h1896; + 4'd3: eDMH$D_IN = x__h1913; + 4'd4: eDMH$D_IN = x__h1958; + default: eDMH$D_IN = x__h2003; endcase end assign eDMH$EN = @@ -553,13 +552,13 @@ module mkSimDCP(CLK, (ptr == 4'd2 || ptr == 4'd3 || ptr == 4'd4 || ptr == 4'd5) ; // register eData - always@(ptr or x__h2305 or x__h1902 or x__h2216 or x__h2261) + always@(ptr or x__h2299 or x__h1896 or x__h2210 or x__h2255) begin case (ptr) - 4'd10: eData$D_IN = x__h1902; - 4'd11: eData$D_IN = x__h2216; - 4'd12: eData$D_IN = x__h2261; - default: eData$D_IN = x__h2305; + 4'd10: eData$D_IN = x__h1896; + 4'd11: eData$D_IN = x__h2210; + 4'd12: eData$D_IN = x__h2255; + default: eData$D_IN = x__h2299; endcase end assign eData$EN = @@ -571,7 +570,7 @@ module mkSimDCP(CLK, assign eDoReq$EN = 1'd1 ; // register ePli - assign ePli$D_IN = (ptr == 4'd0) ? 16'd0 : x__h1872 ; + assign ePli$D_IN = (ptr == 4'd0) ? 16'd0 : x__h1866 ; assign ePli$EN = WILL_FIRE_RL_sim_ingress && (ptr == 4'd0 || ptr == 4'd1) ; // register edpFsm_start_reg @@ -644,7 +643,7 @@ module mkSimDCP(CLK, // register eeDmh assign eeDmh$D_IN = { dcpRespF$D_OUT[9:2], - CASE_dcpRespFD_OUT_BITS_44_TO_43_IF_dcpRespF__ETC__q3, + CASE_dcpRespFD_OUT_BITS_44_TO_43_0_IF_dcpResp_ETC__q4, 16'h0 } ; assign eeDmh$EN = WILL_FIRE_RL_sim_egress ; @@ -678,11 +677,11 @@ module mkSimDCP(CLK, (dcpReqF$D_OUT[78:77] == 2'd0 && !dcpReqF$D_OUT[40] || dcpReqF$D_OUT[78:77] != 2'd0 && (dcpReqF$D_OUT[78:77] == 2'd1 && - (!dcpReqF_first__33_BITS_71_TO_64_38_EQ_IF_lastT_ETC___d395 || + (!dcpReqF_first__33_BITS_71_TO_64_38_EQ_IF_lastT_ETC___d143 || !lastTag[8]) && !dcpReqF$D_OUT[76] || dcpReqF$D_OUT[78:77] != 2'd1 && - (!dcpReqF_first__33_BITS_39_TO_32_51_EQ_IF_lastT_ETC___d398 || + (!dcpReqF_first__33_BITS_39_TO_32_51_EQ_IF_lastT_ETC___d152 || !lastTag[8]) && !dcpReqF$D_OUT[44])) ; @@ -796,34 +795,34 @@ module mkSimDCP(CLK, // remaining internal signals assign IF_NOT_dcpReqF_first__33_BITS_39_TO_32_51_EQ_I_ETC___d158 = - (!dcpReqF_first__33_BITS_39_TO_32_51_EQ_IF_lastT_ETC___d398 || + (!dcpReqF_first__33_BITS_39_TO_32_51_EQ_IF_lastT_ETC___d152 || !lastTag[8] || dcpReqF$D_OUT[44]) ? cpReqF$FULL_N : dcpRespF$FULL_N ; - assign IF_dcpRespF_first__35_BIT_42_42_THEN_0x70_ELSE_ETC___d397 = + assign IF_dcpRespF_first__35_BIT_42_42_THEN_0x70_ELSE_ETC___d343 = dcpRespF$D_OUT[42] ? 8'h70 : 8'h30 ; assign NOT_dcpReqF_first__33_BITS_78_TO_77_34_EQ_0_35_ETC___d221 = dcpReqF$D_OUT[78:77] != 2'd0 && dcpReqF$D_OUT[78:77] != 2'd1 && - dcpReqF_first__33_BITS_39_TO_32_51_EQ_IF_lastT_ETC___d398 && + dcpReqF_first__33_BITS_39_TO_32_51_EQ_IF_lastT_ETC___d152 && lastTag[8] && !dcpReqF$D_OUT[44] ; - assign dcpReqF_first__33_BITS_39_TO_32_51_EQ_IF_lastT_ETC___d398 = + assign dcpReqF_first__33_BITS_39_TO_32_51_EQ_IF_lastT_ETC___d152 = dcpReqF$D_OUT[39:32] == lastTag[7:0] ; - assign dcpReqF_first__33_BITS_71_TO_64_38_EQ_IF_lastT_ETC___d395 = + assign dcpReqF_first__33_BITS_71_TO_64_38_EQ_IF_lastT_ETC___d143 = dcpReqF$D_OUT[71:64] == lastTag[7:0] ; assign dcpReqF_first__33_BITS_78_TO_77_34_EQ_0_35_OR__ETC___d166 = dcpReqF$D_OUT[78:77] == 2'd0 || dcpReqF$D_OUT[78:77] == 2'd1 || - dcpReqF_first__33_BITS_39_TO_32_51_EQ_IF_lastT_ETC___d398 && + dcpReqF_first__33_BITS_39_TO_32_51_EQ_IF_lastT_ETC___d152 && lastTag[8] && !dcpReqF$D_OUT[44] ; assign dcpReqF_first__33_BITS_78_TO_77_34_EQ_1_37_AND_ETC___d207 = dcpReqF$D_OUT[78:77] == 2'd1 && - (!dcpReqF_first__33_BITS_71_TO_64_38_EQ_IF_lastT_ETC___d395 || + (!dcpReqF_first__33_BITS_71_TO_64_38_EQ_IF_lastT_ETC___d143 || !lastTag[8] || dcpReqF$D_OUT[76]) || dcpReqF$D_OUT[78:77] != 2'd1 && - (!dcpReqF_first__33_BITS_39_TO_32_51_EQ_IF_lastT_ETC___d398 || + (!dcpReqF_first__33_BITS_39_TO_32_51_EQ_IF_lastT_ETC___d152 || !lastTag[8] || dcpReqF$D_OUT[44]) ; assign edpFsm_abort_whas__35_AND_edpFsm_abort_wget__3_ETC___d324 = @@ -834,61 +833,70 @@ module mkSimDCP(CLK, edpFsm_state_mkFSMstate == 4'd10) && (!edpFsm_start_reg_1 || edpFsm_state_fired) && !edpFsm_start_reg ; - assign x__h1872 = ePli | y__h1883 ; - assign x__h1902 = { simReqF$D_OUT, 24'h0 } ; - assign x__h1919 = { eDMH[31:24], simReqF$D_OUT, 16'h0 } ; - assign x__h1964 = { eDMH[31:16], simReqF$D_OUT, 8'h0 } ; - assign x__h2009 = { eDMH[31:8], simReqF$D_OUT } ; - assign x__h2068 = { eAddr[31:24], simReqF$D_OUT, 16'h0 } ; - assign x__h2113 = { eAddr[31:16], simReqF$D_OUT, 8'h0 } ; - assign x__h2157 = { eAddr[31:8], simReqF$D_OUT } ; - assign x__h2216 = { eData[31:24], simReqF$D_OUT, 16'h0 } ; - assign x__h2261 = { eData[31:16], simReqF$D_OUT, 8'h0 } ; - assign x__h2305 = { eData[31:8], simReqF$D_OUT } ; - assign y__h1883 = { 8'd0, simReqF$D_OUT } ; + assign x__h1866 = ePli | y__h1877 ; + assign x__h1896 = { simReqF$D_OUT, 24'h0 } ; + assign x__h1913 = { eDMH[31:24], simReqF$D_OUT, 16'h0 } ; + assign x__h1958 = { eDMH[31:16], simReqF$D_OUT, 8'h0 } ; + assign x__h2003 = { eDMH[31:8], simReqF$D_OUT } ; + assign x__h2062 = { eAddr[31:24], simReqF$D_OUT, 16'h0 } ; + assign x__h2107 = { eAddr[31:16], simReqF$D_OUT, 8'h0 } ; + assign x__h2151 = { eAddr[31:8], simReqF$D_OUT } ; + assign x__h2210 = { eData[31:24], simReqF$D_OUT, 16'h0 } ; + assign x__h2255 = { eData[31:16], simReqF$D_OUT, 8'h0 } ; + assign x__h2299 = { eData[31:8], simReqF$D_OUT } ; + assign y__h1877 = { 8'd0, simReqF$D_OUT } ; always@(eDMH or dcpReqF$FULL_N) begin case (eDMH[13:12]) 2'd0, 2'b01: - CASE_eDMH_BITS_13_TO_12_NOT_eDMH_BITS_13_TO_12_ETC__q1 = + CASE_eDMH_BITS_13_TO_12_0_dcpReqFFULL_N_0b1_d_ETC__q1 = dcpReqF$FULL_N; - default: CASE_eDMH_BITS_13_TO_12_NOT_eDMH_BITS_13_TO_12_ETC__q1 = + default: CASE_eDMH_BITS_13_TO_12_0_dcpReqFFULL_N_0b1_d_ETC__q1 = eDMH[13:12] != 2'd2 || dcpReqF$FULL_N; endcase end always@(dcpReqF$D_OUT or IF_NOT_dcpReqF_first__33_BITS_39_TO_32_51_EQ_I_ETC___d158 or dcpRespF$FULL_N or - dcpReqF_first__33_BITS_71_TO_64_38_EQ_IF_lastT_ETC___d395 or + dcpReqF_first__33_BITS_71_TO_64_38_EQ_IF_lastT_ETC___d143 or lastTag or cpReqF$FULL_N) begin case (dcpReqF$D_OUT[78:77]) 2'd0: - CASE_dcpReqFD_OUT_BITS_78_TO_77_IF_NOT_dcpReq_ETC__q2 = + CASE_dcpReqFD_OUT_BITS_78_TO_77_0_dcpRespFFU_ETC__q2 = dcpRespF$FULL_N; 2'd1: - CASE_dcpReqFD_OUT_BITS_78_TO_77_IF_NOT_dcpReq_ETC__q2 = + CASE_dcpReqFD_OUT_BITS_78_TO_77_0_dcpRespFFU_ETC__q2 = dcpRespF$FULL_N && - (dcpReqF_first__33_BITS_71_TO_64_38_EQ_IF_lastT_ETC___d395 && + (dcpReqF_first__33_BITS_71_TO_64_38_EQ_IF_lastT_ETC___d143 && lastTag[8] && !dcpReqF$D_OUT[76] || cpReqF$FULL_N); - default: CASE_dcpReqFD_OUT_BITS_78_TO_77_IF_NOT_dcpReq_ETC__q2 = + default: CASE_dcpReqFD_OUT_BITS_78_TO_77_0_dcpRespFFU_ETC__q2 = IF_NOT_dcpReqF_first__33_BITS_39_TO_32_51_EQ_I_ETC___d158; endcase end + always@(lastResp) + begin + case (lastResp[44:43]) + 2'd0, 2'd1: + CASE_lastResp_BITS_44_TO_43_0_lastResp_BITS_44_ETC__q3 = + lastResp[44:43]; + default: CASE_lastResp_BITS_44_TO_43_0_lastResp_BITS_44_ETC__q3 = 2'd2; + endcase + end always@(dcpRespF$D_OUT or - IF_dcpRespF_first__35_BIT_42_42_THEN_0x70_ELSE_ETC___d397) + IF_dcpRespF_first__35_BIT_42_42_THEN_0x70_ELSE_ETC___d343) begin case (dcpRespF$D_OUT[44:43]) 2'd0: - CASE_dcpRespFD_OUT_BITS_44_TO_43_IF_dcpRespF__ETC__q3 = - IF_dcpRespF_first__35_BIT_42_42_THEN_0x70_ELSE_ETC___d397; + CASE_dcpRespFD_OUT_BITS_44_TO_43_0_IF_dcpResp_ETC__q4 = + IF_dcpRespF_first__35_BIT_42_42_THEN_0x70_ELSE_ETC___d343; 2'd1: - CASE_dcpRespFD_OUT_BITS_44_TO_43_IF_dcpRespF__ETC__q3 = + CASE_dcpRespFD_OUT_BITS_44_TO_43_0_IF_dcpResp_ETC__q4 = dcpRespF$D_OUT[10] ? 8'h70 : 8'h30; - default: CASE_dcpRespFD_OUT_BITS_44_TO_43_IF_dcpRespF__ETC__q3 = - IF_dcpRespF_first__35_BIT_42_42_THEN_0x70_ELSE_ETC___d397; + default: CASE_dcpRespFD_OUT_BITS_44_TO_43_0_IF_dcpResp_ETC__q4 = + IF_dcpRespF_first__35_BIT_42_42_THEN_0x70_ELSE_ETC___d343; endcase end @@ -975,63 +983,63 @@ module mkSimDCP(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rx_sim_dcp && eDMH[13:12] == 2'd0) begin - v__h3767 = $time; + v__h3777 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rx_sim_dcp && eDMH[13:12] == 2'd0) - $display("[%0d]: rx_sim_dcp REQUEST: NOP ", v__h3767); + $display("[%0d]: rx_sim_dcp REQUEST: NOP ", v__h3777); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rx_sim_dcp && eDMH[13:12] == 2'b01) begin - v__h3781 = $time; + v__h3791 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rx_sim_dcp && eDMH[13:12] == 2'b01) $display("[%0d]: rx_sim_dcp REQUEST: WRITE Addr:0x%0x Data:0x%0x", - v__h3781, + v__h3791, eAddr, eData); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rx_sim_dcp && eDMH[13:12] == 2'd2) begin - v__h3795 = $time; + v__h3805 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rx_sim_dcp && eDMH[13:12] == 2'd2) $display("[%0d]: rx_sim_dcp REQUEST: READ Addr:0x%0x ", - v__h3795, + v__h3805, eAddr); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_dcp_to_cp_request && dcpReqF$D_OUT[78:77] == 2'd1 && - dcpReqF_first__33_BITS_71_TO_64_38_EQ_IF_lastT_ETC___d395 && + dcpReqF_first__33_BITS_71_TO_64_38_EQ_IF_lastT_ETC___d143 && lastTag[8] && !dcpReqF$D_OUT[76]) begin - v__h4547 = $time; + v__h4532 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_dcp_to_cp_request && dcpReqF$D_OUT[78:77] == 2'd1 && - dcpReqF_first__33_BITS_71_TO_64_38_EQ_IF_lastT_ETC___d395 && + dcpReqF_first__33_BITS_71_TO_64_38_EQ_IF_lastT_ETC___d143 && lastTag[8] && !dcpReqF$D_OUT[76]) $display("[%0d]: dcp_to_cp_request ***TAG MATCH IN DCP WRITE*** (Not Forwarding Write Request to OCCP)", - v__h4547); + v__h4532); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_dcp_to_cp_request && NOT_dcpReqF_first__33_BITS_78_TO_77_34_EQ_0_35_ETC___d221) begin - v__h5128 = $time; + v__h5089 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_dcp_to_cp_request && NOT_dcpReqF_first__33_BITS_78_TO_77_34_EQ_0_35_ETC___d221) $display("[%0d]: dcp_to_cp_request ***TAG MATCH IN DCP READ*** (Returning Previous Response)", - v__h5128); + v__h5089); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_edpFsm_action_l221c14 && (WILL_FIRE_RL_edpFsm_action_l222c14 || @@ -1107,33 +1115,33 @@ module mkSimDCP(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_sim_egress && dcpRespF$D_OUT[44:43] == 2'd0) begin - v__h27055 = $time; + v__h26988 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_sim_egress && dcpRespF$D_OUT[44:43] == 2'd0) - $display("[%0d]: sim_egress NOP_RESPONSE", v__h27055); + $display("[%0d]: sim_egress NOP_RESPONSE", v__h26988); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_sim_egress && dcpRespF$D_OUT[44:43] == 2'd1) begin - v__h27213 = $time; + v__h27142 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_sim_egress && dcpRespF$D_OUT[44:43] == 2'd1) - $display("[%0d]: sim_egress WRITE_RESPONSE", v__h27213); + $display("[%0d]: sim_egress WRITE_RESPONSE", v__h27142); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_sim_egress && dcpRespF$D_OUT[44:43] != 2'd0 && dcpRespF$D_OUT[44:43] != 2'd1) begin - v__h27412 = $time; + v__h27335 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_sim_egress && dcpRespF$D_OUT[44:43] != 2'd0 && dcpRespF$D_OUT[44:43] != 2'd1) $display("[%0d]: sim_egress READ_RESPONSE Data:0x%0x ", - v__h27412, + v__h27335, dcpRespF$D_OUT[41:10]); end // synopsys translate_on diff --git a/rtl/mkSimIO.v b/rtl/mkSimIO.v index fd6bb055..9eda936e 100644 --- a/rtl/mkSimIO.v +++ b/rtl/mkSimIO.v @@ -1,7 +1,7 @@ // -// Generated by Bluespec Compiler, version 2012.09.beta1 (build 29570, 2012-09.11) +// Generated by Bluespec Compiler, version 2013.01.beta1 (build 30202, 2013-01-08) // -// On Mon Nov 19 07:38:56 EST 2012 +// On Tue Jan 22 07:12:41 EST 2013 // // // Ports: @@ -144,23 +144,23 @@ module mkSimIO(CLK, wire MUX_r_hdl$write_1__SEL_1, MUX_s_hdl$write_1__SEL_1; // remaining internal signals - reg [63 : 0] v__h1543, - v__h1836, - v__h2075, - v__h2289, - v__h2642, - v__h2665, - v__h2875, - v__h3399, - v__h3440, - v__h3483, - v__h3526; + reg [63 : 0] v__h1534, + v__h1822, + v__h2056, + v__h2264, + v__h2612, + v__h2635, + v__h2839, + v__h3347, + v__h3388, + v__h3431, + v__h3474; reg [31 : 0] TASK_fopen___d24, TASK_fopen___d31, TASK_fopen___d38, - b__h2122, - b__h2718; - wire [15 : 0] b__h1083, b__h824; + b__h2103, + b__h2688; + wire [15 : 0] b__h1081, b__h824; // actionvalue method host_request_get assign host_request_get = reqF$D_OUT ; @@ -210,11 +210,11 @@ module mkSimIO(CLK, // inputs to muxes for submodule ports assign MUX_r_hdl$write_1__SEL_1 = - WILL_FIRE_RL_do_r_char && b__h2718 == 32'hFFFFFFFF ; + WILL_FIRE_RL_do_r_char && b__h2688 == 32'hFFFFFFFF ; assign MUX_s_hdl$write_1__SEL_1 = - WILL_FIRE_RL_do_s_char && b__h2122 == 32'hFFFFFFFF ; + WILL_FIRE_RL_do_s_char && b__h2103 == 32'hFFFFFFFF ; assign MUX_dcpCredit_value$write_1__VAL_2 = - dcpCredit_value + (dcpCredit_acc_v1$whas ? b__h1083 : 16'd0) + + dcpCredit_value + (dcpCredit_acc_v1$whas ? b__h1081 : 16'd0) + (dcpCredit_acc_v2$whas ? 16'd65535 : 16'd0) ; assign MUX_r_hdl$write_1__VAL_2 = { 1'd1, TASK_fopen___d38 } ; assign MUX_s_hdl$write_1__VAL_2 = { 1'd1, TASK_fopen___d31 } ; @@ -225,19 +225,19 @@ module mkSimIO(CLK, // inlined wires assign spinCredit_acc_v1$wget = b__h824 ; assign spinCredit_acc_v1$whas = - WILL_FIRE_RL_do_s_char && b__h2122 != 32'hFFFFFFFF && + WILL_FIRE_RL_do_s_char && b__h2103 != 32'hFFFFFFFF && !isOpcode && ioOpcode == 8'd0 ; assign spinCredit_acc_v2$wget = 16'd65535 ; assign spinCredit_acc_v2$whas = (spinCredit_value ^ 16'h8000) > 16'd32768 ; assign dcpCredit_acc_v1$wget = b__h824 ; assign dcpCredit_acc_v1$whas = - WILL_FIRE_RL_do_s_char && b__h2122 != 32'hFFFFFFFF && + WILL_FIRE_RL_do_s_char && b__h2103 != 32'hFFFFFFFF && !isOpcode && ioOpcode == 8'd1 ; assign dcpCredit_acc_v2$wget = 16'd65535 ; assign dcpCredit_acc_v2$whas = - WILL_FIRE_RL_do_r_char && b__h2718 != 32'hFFFFFFFF ; + WILL_FIRE_RL_do_r_char && b__h2688 != 32'hFFFFFFFF ; // register cp2hByteCount assign cp2hByteCount$D_IN = cp2hByteCount + 32'd1 ; @@ -253,7 +253,7 @@ module mkSimIO(CLK, // register doTerminate assign doTerminate$D_IN = 1'd1 ; assign doTerminate$EN = - WILL_FIRE_RL_do_s_char && b__h2122 != 32'hFFFFFFFF && + WILL_FIRE_RL_do_s_char && b__h2103 != 32'hFFFFFFFF && !isOpcode && ioOpcode == 8'd255 ; @@ -264,16 +264,16 @@ module mkSimIO(CLK, // register h2ioByteCount assign h2ioByteCount$D_IN = h2ioByteCount + 32'd1 ; assign h2ioByteCount$EN = - WILL_FIRE_RL_do_s_char && b__h2122 != 32'hFFFFFFFF ; + WILL_FIRE_RL_do_s_char && b__h2103 != 32'hFFFFFFFF ; // register ioOpcode - assign ioOpcode$D_IN = b__h2122[7:0] ; + assign ioOpcode$D_IN = b__h2103[7:0] ; assign ioOpcode$EN = - WILL_FIRE_RL_do_s_char && b__h2122 != 32'hFFFFFFFF && isOpcode ; + WILL_FIRE_RL_do_s_char && b__h2103 != 32'hFFFFFFFF && isOpcode ; // register isOpcode assign isOpcode$D_IN = !isOpcode ; - assign isOpcode$EN = WILL_FIRE_RL_do_s_char && b__h2122 != 32'hFFFFFFFF ; + assign isOpcode$EN = WILL_FIRE_RL_do_s_char && b__h2103 != 32'hFFFFFFFF ; // register r_hdl assign r_hdl$D_IN = @@ -281,7 +281,7 @@ module mkSimIO(CLK, 33'h0AAAAAAAA : MUX_r_hdl$write_1__VAL_2 ; assign r_hdl$EN = - WILL_FIRE_RL_do_r_char && b__h2718 == 32'hFFFFFFFF || + WILL_FIRE_RL_do_r_char && b__h2688 == 32'hFFFFFFFF || WILL_FIRE_RL_do_r_open ; // register s_hdl @@ -290,7 +290,7 @@ module mkSimIO(CLK, 33'h0AAAAAAAA : MUX_s_hdl$write_1__VAL_2 ; assign s_hdl$EN = - WILL_FIRE_RL_do_s_char && b__h2122 == 32'hFFFFFFFF || + WILL_FIRE_RL_do_s_char && b__h2103 == 32'hFFFFFFFF || WILL_FIRE_RL_do_s_open ; // register spinCredit_value @@ -305,7 +305,7 @@ module mkSimIO(CLK, assign w_hdl$EN = !w_hdl[32] ; // submodule reqF - assign reqF$D_IN = b__h2718[7:0] ; + assign reqF$D_IN = b__h2688[7:0] ; assign reqF$ENQ = dcpCredit_acc_v2$whas ; assign reqF$DEQ = EN_host_request_get ; assign reqF$CLR = 1'b0 ; @@ -317,8 +317,8 @@ module mkSimIO(CLK, assign respF$CLR = 1'b0 ; // remaining internal signals - assign b__h1083 = b__h824 ; - assign b__h824 = { 8'd0, b__h2122[7:0] } ; + assign b__h1081 = b__h824 ; + assign b__h824 = { 8'd0, b__h2103[7:0] } ; // handling of inlined registers @@ -394,11 +394,11 @@ module mkSimIO(CLK, if (RST_N != `BSV_RESET_VALUE) if (!w_hdl[32]) begin - v__h1543 = $time; + v__h1534 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (!w_hdl[32]) $display("[%0d]: do_w_open called", v__h1543); + if (!w_hdl[32]) $display("[%0d]: do_w_open called", v__h1534); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_do_r_open) begin @@ -408,118 +408,118 @@ module mkSimIO(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_do_r_open) begin - v__h2075 = $time; + v__h2056 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_do_r_open) - $display("[%0d]: do_r_open called", v__h2075); + $display("[%0d]: do_r_open called", v__h2056); if (RST_N != `BSV_RESET_VALUE) if (doTerminate) begin - v__h3399 = $time; + v__h3347 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (doTerminate) - $display("[%0d]: doTerminate called by IOCTL channel", v__h3399); + $display("[%0d]: doTerminate called by IOCTL channel", v__h3347); if (RST_N != `BSV_RESET_VALUE) if (doTerminate) begin - v__h3440 = $time; + v__h3388 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (doTerminate) - $display("[%0d]: IOCTL Bytes Read :%0d", v__h3440, h2ioByteCount); + $display("[%0d]: IOCTL Bytes Read :%0d", v__h3388, h2ioByteCount); if (RST_N != `BSV_RESET_VALUE) if (doTerminate) begin - v__h3483 = $time; + v__h3431 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (doTerminate) - $display("[%0d]: DCP Bytes Read :%0d", v__h3483, h2cpByteCount); + $display("[%0d]: DCP Bytes Read :%0d", v__h3431, h2cpByteCount); if (RST_N != `BSV_RESET_VALUE) if (doTerminate) begin - v__h3526 = $time; + v__h3474 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (doTerminate) - $display("[%0d]: DCP Bytes Written :%0d", v__h3526, cp2hByteCount); + $display("[%0d]: DCP Bytes Written :%0d", v__h3474, cp2hByteCount); if (RST_N != `BSV_RESET_VALUE) if (doTerminate) $finish(32'd1); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_do_s_char) begin - b__h2122 = $fgetc(s_hdl[31:0]); + b__h2103 = $fgetc(s_hdl[31:0]); #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_do_s_char && b__h2122 == 32'hFFFFFFFF) + if (WILL_FIRE_RL_do_s_char && b__h2103 == 32'hFFFFFFFF) begin - v__h2289 = $time; + v__h2264 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_do_s_char && b__h2122 == 32'hFFFFFFFF) + if (WILL_FIRE_RL_do_s_char && b__h2103 == 32'hFFFFFFFF) $display("[%0d]: do_s_char IOCTL fgetc returned -1 after %0d Bytes", - v__h2289, + v__h2264, h2ioByteCount); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_do_s_char && b__h2122 == 32'hFFFFFFFF) + if (WILL_FIRE_RL_do_s_char && b__h2103 == 32'hFFFFFFFF) $fclose(s_hdl[31:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_do_s_char && b__h2122 != 32'hFFFFFFFF && !isOpcode && + if (WILL_FIRE_RL_do_s_char && b__h2103 != 32'hFFFFFFFF && !isOpcode && ioOpcode == 8'd253) $dumpoff; if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_do_s_char && b__h2122 != 32'hFFFFFFFF && !isOpcode && + if (WILL_FIRE_RL_do_s_char && b__h2103 != 32'hFFFFFFFF && !isOpcode && ioOpcode == 8'd253) begin - v__h2642 = $time; + v__h2612 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_do_s_char && b__h2122 != 32'hFFFFFFFF && !isOpcode && + if (WILL_FIRE_RL_do_s_char && b__h2103 != 32'hFFFFFFFF && !isOpcode && ioOpcode == 8'd253) - $display("[%0d]: dumpoff called", v__h2642); + $display("[%0d]: dumpoff called", v__h2612); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_do_s_char && b__h2122 != 32'hFFFFFFFF && !isOpcode && + if (WILL_FIRE_RL_do_s_char && b__h2103 != 32'hFFFFFFFF && !isOpcode && ioOpcode == 8'd254) $dumpon; if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_do_s_char && b__h2122 != 32'hFFFFFFFF && !isOpcode && + if (WILL_FIRE_RL_do_s_char && b__h2103 != 32'hFFFFFFFF && !isOpcode && ioOpcode == 8'd254) begin - v__h2665 = $time; + v__h2635 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_do_s_char && b__h2122 != 32'hFFFFFFFF && !isOpcode && + if (WILL_FIRE_RL_do_s_char && b__h2103 != 32'hFFFFFFFF && !isOpcode && ioOpcode == 8'd254) - $display("[%0d]: dumpon called", v__h2665); + $display("[%0d]: dumpon called", v__h2635); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_do_r_char) begin - b__h2718 = $fgetc(r_hdl[31:0]); + b__h2688 = $fgetc(r_hdl[31:0]); #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_do_r_char && b__h2718 == 32'hFFFFFFFF) + if (WILL_FIRE_RL_do_r_char && b__h2688 == 32'hFFFFFFFF) begin - v__h2875 = $time; + v__h2839 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_do_r_char && b__h2718 == 32'hFFFFFFFF) + if (WILL_FIRE_RL_do_r_char && b__h2688 == 32'hFFFFFFFF) $display("[%0d]: do_r_char DCP fgetc returned -1 after %0d Bytes", - v__h2875, + v__h2839, h2cpByteCount); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_do_r_char && b__h2718 == 32'hFFFFFFFF) + if (WILL_FIRE_RL_do_r_char && b__h2688 == 32'hFFFFFFFF) $fclose(r_hdl[31:0]); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_do_w_char) $fwrite(w_hdl[31:0], "%c", respF$D_OUT); @@ -534,12 +534,12 @@ module mkSimIO(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_do_s_open) begin - v__h1836 = $time; + v__h1822 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_do_s_open) - $display("[%0d]: do_s_open called", v__h1836); + $display("[%0d]: do_s_open called", v__h1822); end // synopsys translate_on endmodule // mkSimIO diff --git a/rtl/mkTB1.v b/rtl/mkTB1.v new file mode 100644 index 00000000..e5a1fdbf --- /dev/null +++ b/rtl/mkTB1.v @@ -0,0 +1,3972 @@ +// +// Generated by Bluespec Compiler, version 2012.09.beta1 (build 29570, 2012-09.11) +// +// On Tue Jan 22 07:28:54 EST 2013 +// +// +// Ports: +// Name I/O size props +// CLK I 1 clock +// RST_N I 1 reset +// +// No combinational paths from inputs to outputs +// +// + +`ifdef BSV_ASSIGNMENT_DELAY +`else + `define BSV_ASSIGNMENT_DELAY +`endif + +`ifdef BSV_POSITIVE_RESET + `define BSV_RESET_VALUE 1'b1 + `define BSV_RESET_EDGE posedge +`else + `define BSV_RESET_VALUE 1'b0 + `define BSV_RESET_EDGE negedge +`endif + +module mkTB1(CLK, + RST_N); + input CLK; + input RST_N; + + // inlined wires + wire [95 : 0] biasWorker_wsiM_extStatusW$wget, + biasWorker_wsiS_extStatusW$wget, + wsiM_extStatusW$wget, + wsiS_extStatusW$wget; + wire [71 : 0] biasWorker_wci_wslv_wciReq$wget, wci_reqF_x_wire$wget; + wire [60 : 0] biasWorker_wsiM_reqFifo_x_wire$wget, + biasWorker_wsiS_wsiReq$wget, + wsiM_reqFifo_x_wire$wget, + wsiS_wsiReq$wget; + wire [33 : 0] biasWorker_wci_wslv_respF_x_wire$wget, wci_wciResponse$wget; + wire [31 : 0] biasWorker_wci_wci_Es_mAddr_w$wget, + biasWorker_wci_wci_Es_mData_w$wget, + biasWorker_wsi_Es_mData_w$wget, + wci_wci_Em_respData_w$wget, + wsi_Es_mData_w$wget; + wire [11 : 0] biasWorker_wsi_Es_mBurstLength_w$wget, + wsi_Es_mBurstLength_w$wget; + wire [7 : 0] biasWorker_wsi_Es_mReqInfo_w$wget, wsi_Es_mReqInfo_w$wget; + wire [3 : 0] biasWorker_wci_wci_Es_mByteEn_w$wget, + biasWorker_wsi_Es_mByteEn_w$wget, + wsi_Es_mByteEn_w$wget; + wire [2 : 0] biasWorker_wci_wci_Es_mCmd_w$wget, + biasWorker_wci_wslv_wEdge$wget, + biasWorker_wsi_Es_mCmd_w$wget, + wsi_Es_mCmd_w$wget; + wire [1 : 0] wci_wci_Em_resp_w$wget; + wire biasWorker_wci_wci_Es_mAddrSpace_w$wget, + biasWorker_wci_wci_Es_mAddrSpace_w$whas, + biasWorker_wci_wci_Es_mAddr_w$whas, + biasWorker_wci_wci_Es_mByteEn_w$whas, + biasWorker_wci_wci_Es_mCmd_w$whas, + biasWorker_wci_wci_Es_mData_w$whas, + biasWorker_wci_wslv_ctlAckReg_1$wget, + biasWorker_wci_wslv_ctlAckReg_1$whas, + biasWorker_wci_wslv_reqF_r_clr$whas, + biasWorker_wci_wslv_reqF_r_deq$whas, + biasWorker_wci_wslv_reqF_r_enq$whas, + biasWorker_wci_wslv_respF_dequeueing$whas, + biasWorker_wci_wslv_respF_enqueueing$whas, + biasWorker_wci_wslv_respF_x_wire$whas, + biasWorker_wci_wslv_sFlagReg_1$wget, + biasWorker_wci_wslv_sFlagReg_1$whas, + biasWorker_wci_wslv_sThreadBusy_pw$whas, + biasWorker_wci_wslv_wEdge$whas, + biasWorker_wci_wslv_wciReq$whas, + biasWorker_wci_wslv_wci_cfrd_pw$whas, + biasWorker_wci_wslv_wci_cfwr_pw$whas, + biasWorker_wci_wslv_wci_ctrl_pw$whas, + biasWorker_wsiM_operateD_1$wget, + biasWorker_wsiM_operateD_1$whas, + biasWorker_wsiM_peerIsReady_1$wget, + biasWorker_wsiM_peerIsReady_1$whas, + biasWorker_wsiM_reqFifo_dequeueing$whas, + biasWorker_wsiM_reqFifo_enqueueing$whas, + biasWorker_wsiM_reqFifo_x_wire$whas, + biasWorker_wsiM_sThreadBusy_pw$whas, + biasWorker_wsiS_operateD_1$wget, + biasWorker_wsiS_operateD_1$whas, + biasWorker_wsiS_peerIsReady_1$wget, + biasWorker_wsiS_peerIsReady_1$whas, + biasWorker_wsiS_reqFifo_doResetClr$whas, + biasWorker_wsiS_reqFifo_doResetDeq$whas, + biasWorker_wsiS_reqFifo_doResetEnq$whas, + biasWorker_wsiS_reqFifo_r_clr$whas, + biasWorker_wsiS_reqFifo_r_deq$whas, + biasWorker_wsiS_reqFifo_r_enq$whas, + biasWorker_wsiS_sThreadBusy_dw$wget, + biasWorker_wsiS_sThreadBusy_dw$whas, + biasWorker_wsiS_wsiReq$whas, + biasWorker_wsi_Es_mBurstLength_w$whas, + biasWorker_wsi_Es_mBurstPrecise_w$whas, + biasWorker_wsi_Es_mByteEn_w$whas, + biasWorker_wsi_Es_mCmd_w$whas, + biasWorker_wsi_Es_mDataInfo_w$whas, + biasWorker_wsi_Es_mData_w$whas, + biasWorker_wsi_Es_mReqInfo_w$whas, + biasWorker_wsi_Es_mReqLast_w$whas, + wciSeqFsm_abort$wget, + wciSeqFsm_abort$whas, + wciSeqFsm_start_reg_1_1$wget, + wciSeqFsm_start_reg_1_1$whas, + wciSeqFsm_start_wire$wget, + wciSeqFsm_start_wire$whas, + wciSeqFsm_state_fired_1$wget, + wciSeqFsm_state_fired_1$whas, + wciSeqFsm_state_overlap_pw$whas, + wciSeqFsm_state_set_pw$whas, + wci_reqF_dequeueing$whas, + wci_reqF_enqueueing$whas, + wci_reqF_x_wire$whas, + wci_sThreadBusy_pw$whas, + wci_sfCapClear_1$wget, + wci_sfCapClear_1$whas, + wci_sfCapSet_1$wget, + wci_sfCapSet_1$whas, + wci_wciResponse$whas, + wci_wci_Em_respData_w$whas, + wci_wci_Em_resp_w$whas, + wsiM_operateD_1$wget, + wsiM_operateD_1$whas, + wsiM_peerIsReady_1$wget, + wsiM_peerIsReady_1$whas, + wsiM_reqFifo_dequeueing$whas, + wsiM_reqFifo_enqueueing$whas, + wsiM_reqFifo_x_wire$whas, + wsiM_sThreadBusy_pw$whas, + wsiS_operateD_1$wget, + wsiS_operateD_1$whas, + wsiS_peerIsReady_1$wget, + wsiS_peerIsReady_1$whas, + wsiS_reqFifo_doResetClr$whas, + wsiS_reqFifo_doResetDeq$whas, + wsiS_reqFifo_doResetEnq$whas, + wsiS_reqFifo_r_clr$whas, + wsiS_reqFifo_r_deq$whas, + wsiS_reqFifo_r_enq$whas, + wsiS_sThreadBusy_dw$wget, + wsiS_sThreadBusy_dw$whas, + wsiS_wsiReq$whas, + wsi_Es_mBurstLength_w$whas, + wsi_Es_mBurstPrecise_w$whas, + wsi_Es_mByteEn_w$whas, + wsi_Es_mCmd_w$whas, + wsi_Es_mDataInfo_w$whas, + wsi_Es_mData_w$whas, + wsi_Es_mReqInfo_w$whas, + wsi_Es_mReqLast_w$whas; + + // register badDataCnt + reg [31 : 0] badDataCnt; + wire [31 : 0] badDataCnt$D_IN; + wire badDataCnt$EN; + + // register badMesgCnt + reg [31 : 0] badMesgCnt; + wire [31 : 0] badMesgCnt$D_IN; + wire badMesgCnt$EN; + + // register biasWorker_biasValue + reg [31 : 0] biasWorker_biasValue; + wire [31 : 0] biasWorker_biasValue$D_IN; + wire biasWorker_biasValue$EN; + + // register biasWorker_controlReg + reg [31 : 0] biasWorker_controlReg; + wire [31 : 0] biasWorker_controlReg$D_IN; + wire biasWorker_controlReg$EN; + + // register biasWorker_wci_wslv_cEdge + reg [2 : 0] biasWorker_wci_wslv_cEdge; + wire [2 : 0] biasWorker_wci_wslv_cEdge$D_IN; + wire biasWorker_wci_wslv_cEdge$EN; + + // register biasWorker_wci_wslv_cState + reg [2 : 0] biasWorker_wci_wslv_cState; + wire [2 : 0] biasWorker_wci_wslv_cState$D_IN; + wire biasWorker_wci_wslv_cState$EN; + + // register biasWorker_wci_wslv_ctlAckReg + reg biasWorker_wci_wslv_ctlAckReg; + wire biasWorker_wci_wslv_ctlAckReg$D_IN, biasWorker_wci_wslv_ctlAckReg$EN; + + // register biasWorker_wci_wslv_ctlOpActive + reg biasWorker_wci_wslv_ctlOpActive; + wire biasWorker_wci_wslv_ctlOpActive$D_IN, + biasWorker_wci_wslv_ctlOpActive$EN; + + // register biasWorker_wci_wslv_illegalEdge + reg biasWorker_wci_wslv_illegalEdge; + wire biasWorker_wci_wslv_illegalEdge$D_IN, + biasWorker_wci_wslv_illegalEdge$EN; + + // register biasWorker_wci_wslv_isReset_isInReset + reg biasWorker_wci_wslv_isReset_isInReset; + wire biasWorker_wci_wslv_isReset_isInReset$D_IN, + biasWorker_wci_wslv_isReset_isInReset$EN; + + // register biasWorker_wci_wslv_nState + reg [2 : 0] biasWorker_wci_wslv_nState; + reg [2 : 0] biasWorker_wci_wslv_nState$D_IN; + wire biasWorker_wci_wslv_nState$EN; + + // register biasWorker_wci_wslv_reqF_countReg + reg [1 : 0] biasWorker_wci_wslv_reqF_countReg; + wire [1 : 0] biasWorker_wci_wslv_reqF_countReg$D_IN; + wire biasWorker_wci_wslv_reqF_countReg$EN; + + // register biasWorker_wci_wslv_respF_c_r + reg [1 : 0] biasWorker_wci_wslv_respF_c_r; + wire [1 : 0] biasWorker_wci_wslv_respF_c_r$D_IN; + wire biasWorker_wci_wslv_respF_c_r$EN; + + // register biasWorker_wci_wslv_respF_q_0 + reg [33 : 0] biasWorker_wci_wslv_respF_q_0; + reg [33 : 0] biasWorker_wci_wslv_respF_q_0$D_IN; + wire biasWorker_wci_wslv_respF_q_0$EN; + + // register biasWorker_wci_wslv_respF_q_1 + reg [33 : 0] biasWorker_wci_wslv_respF_q_1; + reg [33 : 0] biasWorker_wci_wslv_respF_q_1$D_IN; + wire biasWorker_wci_wslv_respF_q_1$EN; + + // register biasWorker_wci_wslv_sFlagReg + reg biasWorker_wci_wslv_sFlagReg; + wire biasWorker_wci_wslv_sFlagReg$D_IN, biasWorker_wci_wslv_sFlagReg$EN; + + // register biasWorker_wci_wslv_sThreadBusy_d + reg biasWorker_wci_wslv_sThreadBusy_d; + wire biasWorker_wci_wslv_sThreadBusy_d$D_IN, + biasWorker_wci_wslv_sThreadBusy_d$EN; + + // register biasWorker_wsiM_burstKind + reg [1 : 0] biasWorker_wsiM_burstKind; + wire [1 : 0] biasWorker_wsiM_burstKind$D_IN; + wire biasWorker_wsiM_burstKind$EN; + + // register biasWorker_wsiM_errorSticky + reg biasWorker_wsiM_errorSticky; + wire biasWorker_wsiM_errorSticky$D_IN, biasWorker_wsiM_errorSticky$EN; + + // register biasWorker_wsiM_iMesgCount + reg [31 : 0] biasWorker_wsiM_iMesgCount; + wire [31 : 0] biasWorker_wsiM_iMesgCount$D_IN; + wire biasWorker_wsiM_iMesgCount$EN; + + // register biasWorker_wsiM_isReset_isInReset + reg biasWorker_wsiM_isReset_isInReset; + wire biasWorker_wsiM_isReset_isInReset$D_IN, + biasWorker_wsiM_isReset_isInReset$EN; + + // register biasWorker_wsiM_operateD + reg biasWorker_wsiM_operateD; + wire biasWorker_wsiM_operateD$D_IN, biasWorker_wsiM_operateD$EN; + + // register biasWorker_wsiM_pMesgCount + reg [31 : 0] biasWorker_wsiM_pMesgCount; + wire [31 : 0] biasWorker_wsiM_pMesgCount$D_IN; + wire biasWorker_wsiM_pMesgCount$EN; + + // register biasWorker_wsiM_peerIsReady + reg biasWorker_wsiM_peerIsReady; + wire biasWorker_wsiM_peerIsReady$D_IN, biasWorker_wsiM_peerIsReady$EN; + + // register biasWorker_wsiM_reqFifo_c_r + reg [1 : 0] biasWorker_wsiM_reqFifo_c_r; + wire [1 : 0] biasWorker_wsiM_reqFifo_c_r$D_IN; + wire biasWorker_wsiM_reqFifo_c_r$EN; + + // register biasWorker_wsiM_reqFifo_q_0 + reg [60 : 0] biasWorker_wsiM_reqFifo_q_0; + reg [60 : 0] biasWorker_wsiM_reqFifo_q_0$D_IN; + wire biasWorker_wsiM_reqFifo_q_0$EN; + + // register biasWorker_wsiM_reqFifo_q_1 + reg [60 : 0] biasWorker_wsiM_reqFifo_q_1; + reg [60 : 0] biasWorker_wsiM_reqFifo_q_1$D_IN; + wire biasWorker_wsiM_reqFifo_q_1$EN; + + // register biasWorker_wsiM_sThreadBusy_d + reg biasWorker_wsiM_sThreadBusy_d; + wire biasWorker_wsiM_sThreadBusy_d$D_IN, biasWorker_wsiM_sThreadBusy_d$EN; + + // register biasWorker_wsiM_statusR + reg [7 : 0] biasWorker_wsiM_statusR; + wire [7 : 0] biasWorker_wsiM_statusR$D_IN; + wire biasWorker_wsiM_statusR$EN; + + // register biasWorker_wsiM_tBusyCount + reg [31 : 0] biasWorker_wsiM_tBusyCount; + wire [31 : 0] biasWorker_wsiM_tBusyCount$D_IN; + wire biasWorker_wsiM_tBusyCount$EN; + + // register biasWorker_wsiM_trafficSticky + reg biasWorker_wsiM_trafficSticky; + wire biasWorker_wsiM_trafficSticky$D_IN, biasWorker_wsiM_trafficSticky$EN; + + // register biasWorker_wsiS_burstKind + reg [1 : 0] biasWorker_wsiS_burstKind; + wire [1 : 0] biasWorker_wsiS_burstKind$D_IN; + wire biasWorker_wsiS_burstKind$EN; + + // register biasWorker_wsiS_errorSticky + reg biasWorker_wsiS_errorSticky; + wire biasWorker_wsiS_errorSticky$D_IN, biasWorker_wsiS_errorSticky$EN; + + // register biasWorker_wsiS_iMesgCount + reg [31 : 0] biasWorker_wsiS_iMesgCount; + wire [31 : 0] biasWorker_wsiS_iMesgCount$D_IN; + wire biasWorker_wsiS_iMesgCount$EN; + + // register biasWorker_wsiS_isReset_isInReset + reg biasWorker_wsiS_isReset_isInReset; + wire biasWorker_wsiS_isReset_isInReset$D_IN, + biasWorker_wsiS_isReset_isInReset$EN; + + // register biasWorker_wsiS_mesgWordLength + reg [11 : 0] biasWorker_wsiS_mesgWordLength; + wire [11 : 0] biasWorker_wsiS_mesgWordLength$D_IN; + wire biasWorker_wsiS_mesgWordLength$EN; + + // register biasWorker_wsiS_operateD + reg biasWorker_wsiS_operateD; + wire biasWorker_wsiS_operateD$D_IN, biasWorker_wsiS_operateD$EN; + + // register biasWorker_wsiS_pMesgCount + reg [31 : 0] biasWorker_wsiS_pMesgCount; + wire [31 : 0] biasWorker_wsiS_pMesgCount$D_IN; + wire biasWorker_wsiS_pMesgCount$EN; + + // register biasWorker_wsiS_peerIsReady + reg biasWorker_wsiS_peerIsReady; + wire biasWorker_wsiS_peerIsReady$D_IN, biasWorker_wsiS_peerIsReady$EN; + + // register biasWorker_wsiS_reqFifo_countReg + reg [1 : 0] biasWorker_wsiS_reqFifo_countReg; + wire [1 : 0] biasWorker_wsiS_reqFifo_countReg$D_IN; + wire biasWorker_wsiS_reqFifo_countReg$EN; + + // register biasWorker_wsiS_reqFifo_levelsValid + reg biasWorker_wsiS_reqFifo_levelsValid; + wire biasWorker_wsiS_reqFifo_levelsValid$D_IN, + biasWorker_wsiS_reqFifo_levelsValid$EN; + + // register biasWorker_wsiS_statusR + reg [7 : 0] biasWorker_wsiS_statusR; + wire [7 : 0] biasWorker_wsiS_statusR$D_IN; + wire biasWorker_wsiS_statusR$EN; + + // register biasWorker_wsiS_tBusyCount + reg [31 : 0] biasWorker_wsiS_tBusyCount; + wire [31 : 0] biasWorker_wsiS_tBusyCount$D_IN; + wire biasWorker_wsiS_tBusyCount$EN; + + // register biasWorker_wsiS_trafficSticky + reg biasWorker_wsiS_trafficSticky; + wire biasWorker_wsiS_trafficSticky$D_IN, biasWorker_wsiS_trafficSticky$EN; + + // register biasWorker_wsiS_wordCount + reg [11 : 0] biasWorker_wsiS_wordCount; + wire [11 : 0] biasWorker_wsiS_wordCount$D_IN; + wire biasWorker_wsiS_wordCount$EN; + + // register dstDataOut + reg [31 : 0] dstDataOut; + wire [31 : 0] dstDataOut$D_IN; + wire dstDataOut$EN; + + // register dstMesgCount + reg [15 : 0] dstMesgCount; + wire [15 : 0] dstMesgCount$D_IN; + wire dstMesgCount$EN; + + // register dstUnrollCnt + reg [15 : 0] dstUnrollCnt; + wire [15 : 0] dstUnrollCnt$D_IN; + wire dstUnrollCnt$EN; + + // register enWsiChecker + reg enWsiChecker; + wire enWsiChecker$D_IN, enWsiChecker$EN; + + // register enWsiSource + reg enWsiSource; + wire enWsiSource$D_IN, enWsiSource$EN; + + // register goodDataCnt + reg [31 : 0] goodDataCnt; + wire [31 : 0] goodDataCnt$D_IN; + wire goodDataCnt$EN; + + // register goodMesgCnt + reg [31 : 0] goodMesgCnt; + wire [31 : 0] goodMesgCnt$D_IN; + wire goodMesgCnt$EN; + + // register mesgHadError + reg mesgHadError; + wire mesgHadError$D_IN, mesgHadError$EN; + + // register simCycle + reg [15 : 0] simCycle; + wire [15 : 0] simCycle$D_IN; + wire simCycle$EN; + + // register srcDataOut + reg [31 : 0] srcDataOut; + wire [31 : 0] srcDataOut$D_IN; + wire srcDataOut$EN; + + // register srcMesgCount + reg [15 : 0] srcMesgCount; + wire [15 : 0] srcMesgCount$D_IN; + wire srcMesgCount$EN; + + // register srcUnrollCnt + reg [15 : 0] srcUnrollCnt; + wire [15 : 0] srcUnrollCnt$D_IN; + wire srcUnrollCnt$EN; + + // register testOperating + reg testOperating; + wire testOperating$D_IN, testOperating$EN; + + // register wciSeqFsm_start_reg + reg wciSeqFsm_start_reg; + wire wciSeqFsm_start_reg$D_IN, wciSeqFsm_start_reg$EN; + + // register wciSeqFsm_start_reg_1 + reg wciSeqFsm_start_reg_1; + wire wciSeqFsm_start_reg_1$D_IN, wciSeqFsm_start_reg_1$EN; + + // register wciSeqFsm_state_can_overlap + reg wciSeqFsm_state_can_overlap; + wire wciSeqFsm_state_can_overlap$D_IN, wciSeqFsm_state_can_overlap$EN; + + // register wciSeqFsm_state_fired + reg wciSeqFsm_state_fired; + wire wciSeqFsm_state_fired$D_IN, wciSeqFsm_state_fired$EN; + + // register wciSeqFsm_state_mkFSMstate + reg [4 : 0] wciSeqFsm_state_mkFSMstate; + reg [4 : 0] wciSeqFsm_state_mkFSMstate$D_IN; + wire wciSeqFsm_state_mkFSMstate$EN; + + // register wciSeqOnce_onceReady + reg wciSeqOnce_onceReady; + wire wciSeqOnce_onceReady$D_IN, wciSeqOnce_onceReady$EN; + + // register wci_busy + reg wci_busy; + wire wci_busy$D_IN, wci_busy$EN; + + // register wci_lastConfigAddr + reg [32 : 0] wci_lastConfigAddr; + wire [32 : 0] wci_lastConfigAddr$D_IN; + wire wci_lastConfigAddr$EN; + + // register wci_lastConfigBE + reg [4 : 0] wci_lastConfigBE; + wire [4 : 0] wci_lastConfigBE$D_IN; + wire wci_lastConfigBE$EN; + + // register wci_lastControlOp + reg [3 : 0] wci_lastControlOp; + wire [3 : 0] wci_lastControlOp$D_IN; + wire wci_lastControlOp$EN; + + // register wci_lastOpWrite + reg [1 : 0] wci_lastOpWrite; + wire [1 : 0] wci_lastOpWrite$D_IN; + wire wci_lastOpWrite$EN; + + // register wci_mFlagReg + reg [1 : 0] wci_mFlagReg; + wire [1 : 0] wci_mFlagReg$D_IN; + wire wci_mFlagReg$EN; + + // register wci_pageWindow + reg [11 : 0] wci_pageWindow; + wire [11 : 0] wci_pageWindow$D_IN; + wire wci_pageWindow$EN; + + // register wci_reqERR + reg [2 : 0] wci_reqERR; + reg [2 : 0] wci_reqERR$D_IN; + wire wci_reqERR$EN; + + // register wci_reqFAIL + reg [2 : 0] wci_reqFAIL; + reg [2 : 0] wci_reqFAIL$D_IN; + wire wci_reqFAIL$EN; + + // register wci_reqF_c_r + reg wci_reqF_c_r; + wire wci_reqF_c_r$D_IN, wci_reqF_c_r$EN; + + // register wci_reqF_q_0 + reg [71 : 0] wci_reqF_q_0; + reg [71 : 0] wci_reqF_q_0$D_IN; + wire wci_reqF_q_0$EN; + + // register wci_reqPend + reg [1 : 0] wci_reqPend; + reg [1 : 0] wci_reqPend$D_IN; + wire wci_reqPend$EN; + + // register wci_reqTO + reg [2 : 0] wci_reqTO; + reg [2 : 0] wci_reqTO$D_IN; + wire wci_reqTO$EN; + + // register wci_respTimr + reg [31 : 0] wci_respTimr; + wire [31 : 0] wci_respTimr$D_IN; + wire wci_respTimr$EN; + + // register wci_respTimrAct + reg wci_respTimrAct; + wire wci_respTimrAct$D_IN, wci_respTimrAct$EN; + + // register wci_sThreadBusy_d + reg wci_sThreadBusy_d; + wire wci_sThreadBusy_d$D_IN, wci_sThreadBusy_d$EN; + + // register wci_sfCap + reg wci_sfCap; + wire wci_sfCap$D_IN, wci_sfCap$EN; + + // register wci_sfCapClear + reg wci_sfCapClear; + wire wci_sfCapClear$D_IN, wci_sfCapClear$EN; + + // register wci_sfCapSet + reg wci_sfCapSet; + wire wci_sfCapSet$D_IN, wci_sfCapSet$EN; + + // register wci_slvPresent + reg wci_slvPresent; + wire wci_slvPresent$D_IN, wci_slvPresent$EN; + + // register wci_wReset_n + reg wci_wReset_n; + wire wci_wReset_n$D_IN, wci_wReset_n$EN; + + // register wci_wStatus + reg [31 : 0] wci_wStatus; + wire [31 : 0] wci_wStatus$D_IN; + wire wci_wStatus$EN; + + // register wci_wTimeout + reg [4 : 0] wci_wTimeout; + wire [4 : 0] wci_wTimeout$D_IN; + wire wci_wTimeout$EN; + + // register wsiM_burstKind + reg [1 : 0] wsiM_burstKind; + wire [1 : 0] wsiM_burstKind$D_IN; + wire wsiM_burstKind$EN; + + // register wsiM_errorSticky + reg wsiM_errorSticky; + wire wsiM_errorSticky$D_IN, wsiM_errorSticky$EN; + + // register wsiM_iMesgCount + reg [31 : 0] wsiM_iMesgCount; + wire [31 : 0] wsiM_iMesgCount$D_IN; + wire wsiM_iMesgCount$EN; + + // register wsiM_isReset_isInReset + reg wsiM_isReset_isInReset; + wire wsiM_isReset_isInReset$D_IN, wsiM_isReset_isInReset$EN; + + // register wsiM_operateD + reg wsiM_operateD; + wire wsiM_operateD$D_IN, wsiM_operateD$EN; + + // register wsiM_pMesgCount + reg [31 : 0] wsiM_pMesgCount; + wire [31 : 0] wsiM_pMesgCount$D_IN; + wire wsiM_pMesgCount$EN; + + // register wsiM_peerIsReady + reg wsiM_peerIsReady; + wire wsiM_peerIsReady$D_IN, wsiM_peerIsReady$EN; + + // register wsiM_reqFifo_c_r + reg [1 : 0] wsiM_reqFifo_c_r; + wire [1 : 0] wsiM_reqFifo_c_r$D_IN; + wire wsiM_reqFifo_c_r$EN; + + // register wsiM_reqFifo_q_0 + reg [60 : 0] wsiM_reqFifo_q_0; + reg [60 : 0] wsiM_reqFifo_q_0$D_IN; + wire wsiM_reqFifo_q_0$EN; + + // register wsiM_reqFifo_q_1 + reg [60 : 0] wsiM_reqFifo_q_1; + reg [60 : 0] wsiM_reqFifo_q_1$D_IN; + wire wsiM_reqFifo_q_1$EN; + + // register wsiM_sThreadBusy_d + reg wsiM_sThreadBusy_d; + wire wsiM_sThreadBusy_d$D_IN, wsiM_sThreadBusy_d$EN; + + // register wsiM_statusR + reg [7 : 0] wsiM_statusR; + wire [7 : 0] wsiM_statusR$D_IN; + wire wsiM_statusR$EN; + + // register wsiM_tBusyCount + reg [31 : 0] wsiM_tBusyCount; + wire [31 : 0] wsiM_tBusyCount$D_IN; + wire wsiM_tBusyCount$EN; + + // register wsiM_trafficSticky + reg wsiM_trafficSticky; + wire wsiM_trafficSticky$D_IN, wsiM_trafficSticky$EN; + + // register wsiS_burstKind + reg [1 : 0] wsiS_burstKind; + wire [1 : 0] wsiS_burstKind$D_IN; + wire wsiS_burstKind$EN; + + // register wsiS_errorSticky + reg wsiS_errorSticky; + wire wsiS_errorSticky$D_IN, wsiS_errorSticky$EN; + + // register wsiS_iMesgCount + reg [31 : 0] wsiS_iMesgCount; + wire [31 : 0] wsiS_iMesgCount$D_IN; + wire wsiS_iMesgCount$EN; + + // register wsiS_isReset_isInReset + reg wsiS_isReset_isInReset; + wire wsiS_isReset_isInReset$D_IN, wsiS_isReset_isInReset$EN; + + // register wsiS_mesgWordLength + reg [11 : 0] wsiS_mesgWordLength; + wire [11 : 0] wsiS_mesgWordLength$D_IN; + wire wsiS_mesgWordLength$EN; + + // register wsiS_operateD + reg wsiS_operateD; + wire wsiS_operateD$D_IN, wsiS_operateD$EN; + + // register wsiS_pMesgCount + reg [31 : 0] wsiS_pMesgCount; + wire [31 : 0] wsiS_pMesgCount$D_IN; + wire wsiS_pMesgCount$EN; + + // register wsiS_peerIsReady + reg wsiS_peerIsReady; + wire wsiS_peerIsReady$D_IN, wsiS_peerIsReady$EN; + + // register wsiS_reqFifo_countReg + reg [1 : 0] wsiS_reqFifo_countReg; + wire [1 : 0] wsiS_reqFifo_countReg$D_IN; + wire wsiS_reqFifo_countReg$EN; + + // register wsiS_reqFifo_levelsValid + reg wsiS_reqFifo_levelsValid; + wire wsiS_reqFifo_levelsValid$D_IN, wsiS_reqFifo_levelsValid$EN; + + // register wsiS_statusR + reg [7 : 0] wsiS_statusR; + wire [7 : 0] wsiS_statusR$D_IN; + wire wsiS_statusR$EN; + + // register wsiS_tBusyCount + reg [31 : 0] wsiS_tBusyCount; + wire [31 : 0] wsiS_tBusyCount$D_IN; + wire wsiS_tBusyCount$EN; + + // register wsiS_trafficSticky + reg wsiS_trafficSticky; + wire wsiS_trafficSticky$D_IN, wsiS_trafficSticky$EN; + + // register wsiS_wordCount + reg [11 : 0] wsiS_wordCount; + wire [11 : 0] wsiS_wordCount$D_IN; + wire wsiS_wordCount$EN; + + // ports of submodule biasWorker_wci_wslv_reqF + wire [71 : 0] biasWorker_wci_wslv_reqF$D_IN, biasWorker_wci_wslv_reqF$D_OUT; + wire biasWorker_wci_wslv_reqF$CLR, + biasWorker_wci_wslv_reqF$DEQ, + biasWorker_wci_wslv_reqF$EMPTY_N, + biasWorker_wci_wslv_reqF$ENQ; + + // ports of submodule biasWorker_wsiS_reqFifo + wire [60 : 0] biasWorker_wsiS_reqFifo$D_IN, biasWorker_wsiS_reqFifo$D_OUT; + wire biasWorker_wsiS_reqFifo$CLR, + biasWorker_wsiS_reqFifo$DEQ, + biasWorker_wsiS_reqFifo$EMPTY_N, + biasWorker_wsiS_reqFifo$ENQ, + biasWorker_wsiS_reqFifo$FULL_N; + + // ports of submodule wci_mReset + wire wci_mReset$ASSERT_IN, wci_mReset$OUT_RST; + + // ports of submodule wci_respF + reg [33 : 0] wci_respF$D_IN; + wire wci_respF$CLR, + wci_respF$DEQ, + wci_respF$EMPTY_N, + wci_respF$ENQ, + wci_respF$FULL_N; + + // ports of submodule wsiS_reqFifo + wire [60 : 0] wsiS_reqFifo$D_IN, wsiS_reqFifo$D_OUT; + wire wsiS_reqFifo$CLR, + wsiS_reqFifo$DEQ, + wsiS_reqFifo$EMPTY_N, + wsiS_reqFifo$ENQ, + wsiS_reqFifo$FULL_N; + + // rule scheduling signals + wire WILL_FIRE_RL_biasWorker_wci_cfrd, + WILL_FIRE_RL_biasWorker_wci_cfwr, + WILL_FIRE_RL_biasWorker_wci_ctrl_EiI, + WILL_FIRE_RL_biasWorker_wci_ctrl_IsO, + WILL_FIRE_RL_biasWorker_wci_ctrl_OrE, + WILL_FIRE_RL_biasWorker_wci_wslv_ctl_op_complete, + WILL_FIRE_RL_biasWorker_wci_wslv_ctl_op_start, + WILL_FIRE_RL_biasWorker_wci_wslv_respF_both, + WILL_FIRE_RL_biasWorker_wci_wslv_respF_decCtr, + WILL_FIRE_RL_biasWorker_wci_wslv_respF_incCtr, + WILL_FIRE_RL_biasWorker_wsiM_reqFifo_both, + WILL_FIRE_RL_biasWorker_wsiM_reqFifo_decCtr, + WILL_FIRE_RL_biasWorker_wsiM_reqFifo_deq, + WILL_FIRE_RL_biasWorker_wsiM_reqFifo_incCtr, + WILL_FIRE_RL_biasWorker_wsiS_reqFifo_enq, + WILL_FIRE_RL_biasWorker_wsiS_reqFifo_reset, + WILL_FIRE_RL_wciSeqFsm_action_l50c5, + WILL_FIRE_RL_wciSeqFsm_action_l51c10, + WILL_FIRE_RL_wciSeqFsm_action_l54c8, + WILL_FIRE_RL_wciSeqFsm_action_l55c5, + WILL_FIRE_RL_wciSeqFsm_action_l58c8, + WILL_FIRE_RL_wciSeqFsm_action_l59c5, + WILL_FIRE_RL_wciSeqFsm_action_l62c8, + WILL_FIRE_RL_wciSeqFsm_action_l63c5, + WILL_FIRE_RL_wciSeqFsm_action_l66c8, + WILL_FIRE_RL_wciSeqFsm_action_l67c5, + WILL_FIRE_RL_wciSeqFsm_action_l70c8, + WILL_FIRE_RL_wciSeqFsm_action_l71c5, + WILL_FIRE_RL_wciSeqFsm_fsm_start, + WILL_FIRE_RL_wciSeqFsm_idle_l49c3, + WILL_FIRE_RL_wci_reqF_both, + WILL_FIRE_RL_wci_reqF_decCtr, + WILL_FIRE_RL_wci_reqF_incCtr, + WILL_FIRE_RL_wci_wrkBusy, + WILL_FIRE_RL_wsiM_reqFifo_both, + WILL_FIRE_RL_wsiM_reqFifo_decCtr, + WILL_FIRE_RL_wsiM_reqFifo_deq, + WILL_FIRE_RL_wsiM_reqFifo_incCtr, + WILL_FIRE_RL_wsiS_reqFifo_enq, + WILL_FIRE_RL_wsiS_reqFifo_reset; + + // inputs to muxes for submodule ports + reg [71 : 0] MUX_wci_reqF_q_0$write_1__VAL_2; + reg [33 : 0] MUX_biasWorker_wci_wslv_respF_q_0$write_1__VAL_1; + wire [71 : 0] MUX_wci_reqF_q_0$write_1__VAL_1, + MUX_wci_reqF_x_wire$wset_1__VAL_2, + MUX_wci_reqF_x_wire$wset_1__VAL_3; + wire [60 : 0] MUX_biasWorker_wsiM_reqFifo_q_0$write_1__VAL_1, + MUX_biasWorker_wsiM_reqFifo_q_0$write_1__VAL_2, + MUX_biasWorker_wsiM_reqFifo_q_1$write_1__VAL_2, + MUX_wsiM_reqFifo_q_0$write_1__VAL_1, + MUX_wsiM_reqFifo_q_0$write_1__VAL_2, + MUX_wsiM_reqFifo_q_1$write_1__VAL_1; + wire [33 : 0] MUX_biasWorker_wci_wslv_respF_q_0$write_1__VAL_2, + MUX_biasWorker_wci_wslv_respF_q_1$write_1__VAL_1, + MUX_biasWorker_wci_wslv_respF_x_wire$wset_1__VAL_1, + MUX_biasWorker_wci_wslv_respF_x_wire$wset_1__VAL_2, + MUX_wci_respF$enq_1__VAL_2; + wire [31 : 0] MUX_wci_respTimr$write_1__VAL_2; + wire [15 : 0] MUX_dstUnrollCnt$write_1__VAL_2, + MUX_srcUnrollCnt$write_1__VAL_2; + wire [1 : 0] MUX_biasWorker_wci_wslv_respF_c_r$write_1__VAL_1, + MUX_biasWorker_wci_wslv_respF_c_r$write_1__VAL_2, + MUX_biasWorker_wsiM_reqFifo_c_r$write_1__VAL_1, + MUX_biasWorker_wsiM_reqFifo_c_r$write_1__VAL_2, + MUX_wsiM_reqFifo_c_r$write_1__VAL_1, + MUX_wsiM_reqFifo_c_r$write_1__VAL_2; + wire MUX_biasWorker_biasValue$write_1__SEL_1, + MUX_biasWorker_controlReg$write_1__SEL_1, + MUX_biasWorker_wci_wslv_illegalEdge$write_1__SEL_1, + MUX_biasWorker_wci_wslv_illegalEdge$write_1__SEL_2, + MUX_biasWorker_wci_wslv_illegalEdge$write_1__VAL_2, + MUX_biasWorker_wci_wslv_respF_q_0$write_1__SEL_1, + MUX_biasWorker_wci_wslv_respF_q_1$write_1__SEL_2, + MUX_biasWorker_wsiM_reqFifo_q_0$write_1__SEL_1, + MUX_biasWorker_wsiM_reqFifo_q_1$write_1__SEL_1, + MUX_biasWorker_wsiS_reqFifo_levelsValid$write_1__SEL_3, + MUX_wciSeqFsm_start_reg$write_1__SEL_2, + MUX_wci_busy$write_1__PSEL_1, + MUX_wci_busy$write_1__SEL_1, + MUX_wci_busy$write_1__SEL_2, + MUX_wci_lastConfigBE$write_1__SEL_1, + MUX_wci_lastConfigBE$write_1__SEL_2, + MUX_wci_lastControlOp$write_1__SEL_1, + MUX_wci_lastControlOp$write_1__SEL_2, + MUX_wci_reqF_c_r$write_1__VAL_1, + MUX_wci_reqF_c_r$write_1__VAL_2, + MUX_wci_reqF_q_0$write_1__SEL_2, + MUX_wci_reqPend$write_1__PSEL_3, + MUX_wci_reqPend$write_1__SEL_3, + MUX_wci_reqPend$write_1__SEL_4, + MUX_wci_respF$enq_1__SEL_1, + MUX_wsiM_reqFifo_q_0$write_1__SEL_2, + MUX_wsiM_reqFifo_q_1$write_1__SEL_2, + MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3; + + // remaining internal signals + reg [63 : 0] v__h13915, + v__h14090, + v__h14234, + v__h21121, + v__h21276, + v__h2879, + v__h2969, + v__h3058, + v__h3282, + v__h3372, + v__h3461, + v__h3690, + v__h3780, + v__h3869, + v__h57858, + v__h58288, + v__h59334, + v__h59639, + v__h60412, + v__h61491, + v__h62651, + v__h63028, + v__h66131, + v__h66381, + v__h66575, + v__h66773; + reg [31 : 0] _theResult____h21260; + wire [31 : 0] rdat__h21350, + toCount__h2586, + wciAddr__h60695, + x__h2746, + x_data__h20592; + wire [26 : 0] IF_wci_lastControlOp_22_BIT_3_23_THEN_wci_last_ETC___d137; + wire [15 : 0] wsiBurstLength__h66174, x__h21353, x__h66071, x__h66543; + wire NOT_wci_busy_5_04_AND_IF_wci_wReset_n_5_THEN_N_ETC___d817, + _dand1wci_busy$EN_write, + _dand1wci_respF$EN_enq, + _dor1wci_lastConfigAddr$EN_write, + wciSeqFsm_abort_whas__63_AND_wciSeqFsm_abort_w_ETC___d875, + wci_respTimr_7_ULT_1_SL_wci_wTimeout_8_9___d969, + wsiS_reqFifo_first__99_BITS_43_TO_12_00_EQ_dst_ETC___d943; + + // submodule biasWorker_wci_wslv_reqF + SizedFIFO #(.p1width(32'd72), + .p2depth(32'd3), + .p3cntr_width(32'd1), + .guarded(32'd1)) biasWorker_wci_wslv_reqF(.RST(wci_mReset$OUT_RST), + .CLK(CLK), + .D_IN(biasWorker_wci_wslv_reqF$D_IN), + .ENQ(biasWorker_wci_wslv_reqF$ENQ), + .DEQ(biasWorker_wci_wslv_reqF$DEQ), + .CLR(biasWorker_wci_wslv_reqF$CLR), + .D_OUT(biasWorker_wci_wslv_reqF$D_OUT), + .FULL_N(), + .EMPTY_N(biasWorker_wci_wslv_reqF$EMPTY_N)); + + // submodule biasWorker_wsiS_reqFifo + SizedFIFO #(.p1width(32'd61), + .p2depth(32'd3), + .p3cntr_width(32'd1), + .guarded(32'd1)) biasWorker_wsiS_reqFifo(.RST(wci_mReset$OUT_RST), + .CLK(CLK), + .D_IN(biasWorker_wsiS_reqFifo$D_IN), + .ENQ(biasWorker_wsiS_reqFifo$ENQ), + .DEQ(biasWorker_wsiS_reqFifo$DEQ), + .CLR(biasWorker_wsiS_reqFifo$CLR), + .D_OUT(biasWorker_wsiS_reqFifo$D_OUT), + .FULL_N(biasWorker_wsiS_reqFifo$FULL_N), + .EMPTY_N(biasWorker_wsiS_reqFifo$EMPTY_N)); + + // submodule wci_mReset + MakeResetA #(.RSTDELAY(32'd16), .init(1'd0)) wci_mReset(.CLK(CLK), + .RST(RST_N), + .DST_CLK(CLK), + .ASSERT_IN(wci_mReset$ASSERT_IN), + .ASSERT_OUT(), + .OUT_RST(wci_mReset$OUT_RST)); + + // submodule wci_respF + FIFO1 #(.width(32'd34), .guarded(32'd1)) wci_respF(.RST(RST_N), + .CLK(CLK), + .D_IN(wci_respF$D_IN), + .ENQ(wci_respF$ENQ), + .DEQ(wci_respF$DEQ), + .CLR(wci_respF$CLR), + .D_OUT(), + .FULL_N(wci_respF$FULL_N), + .EMPTY_N(wci_respF$EMPTY_N)); + + // submodule wsiS_reqFifo + SizedFIFO #(.p1width(32'd61), + .p2depth(32'd3), + .p3cntr_width(32'd1), + .guarded(32'd1)) wsiS_reqFifo(.RST(RST_N), + .CLK(CLK), + .D_IN(wsiS_reqFifo$D_IN), + .ENQ(wsiS_reqFifo$ENQ), + .DEQ(wsiS_reqFifo$DEQ), + .CLR(wsiS_reqFifo$CLR), + .D_OUT(wsiS_reqFifo$D_OUT), + .FULL_N(wsiS_reqFifo$FULL_N), + .EMPTY_N(wsiS_reqFifo$EMPTY_N)); + + // rule RL_wci_wrkBusy + assign WILL_FIRE_RL_wci_wrkBusy = + ((biasWorker_wci_wslv_respF_q_0[33:32] == 2'd0) ? + wci_respTimr_7_ULT_1_SL_wci_wTimeout_8_9___d969 || + wci_respF$FULL_N : + wci_respF$FULL_N) && + wci_busy ; + + // rule RL_wsiM_reqFifo_deq + assign WILL_FIRE_RL_wsiM_reqFifo_deq = + wsiM_reqFifo_c_r != 2'd0 && !wsiM_sThreadBusy_d ; + + // rule RL_wsiM_reqFifo_incCtr + assign WILL_FIRE_RL_wsiM_reqFifo_incCtr = + ((wsiM_reqFifo_c_r == 2'd0) ? + wsiM_reqFifo_enqueueing$whas : + wsiM_reqFifo_c_r != 2'd1 || wsiM_reqFifo_enqueueing$whas) && + wsiM_reqFifo_enqueueing$whas && + !WILL_FIRE_RL_wsiM_reqFifo_deq ; + + // rule RL_wsiM_reqFifo_decCtr + assign WILL_FIRE_RL_wsiM_reqFifo_decCtr = + WILL_FIRE_RL_wsiM_reqFifo_deq && !wsiM_reqFifo_enqueueing$whas ; + + // rule RL_wsiM_reqFifo_both + assign WILL_FIRE_RL_wsiM_reqFifo_both = + ((wsiM_reqFifo_c_r == 2'd1) ? + wsiM_reqFifo_enqueueing$whas : + wsiM_reqFifo_c_r != 2'd2 || wsiM_reqFifo_enqueueing$whas) && + WILL_FIRE_RL_wsiM_reqFifo_deq && + wsiM_reqFifo_enqueueing$whas ; + + // rule RL_biasWorker_wci_wslv_ctl_op_start + assign WILL_FIRE_RL_biasWorker_wci_wslv_ctl_op_start = + biasWorker_wci_wslv_reqF$EMPTY_N && + biasWorker_wci_wslv_wci_ctrl_pw$whas && + !WILL_FIRE_RL_biasWorker_wci_wslv_ctl_op_complete ; + + // rule RL_biasWorker_wci_ctrl_EiI + assign WILL_FIRE_RL_biasWorker_wci_ctrl_EiI = + biasWorker_wci_wslv_wci_ctrl_pw$whas && + WILL_FIRE_RL_biasWorker_wci_wslv_ctl_op_start && + biasWorker_wci_wslv_cState == 3'd0 && + biasWorker_wci_wslv_reqF$D_OUT[36:34] == 3'd0 ; + + // rule RL_biasWorker_wci_ctrl_IsO + assign WILL_FIRE_RL_biasWorker_wci_ctrl_IsO = + biasWorker_wci_wslv_wci_ctrl_pw$whas && + WILL_FIRE_RL_biasWorker_wci_wslv_ctl_op_start && + biasWorker_wci_wslv_cState == 3'd1 && + biasWorker_wci_wslv_reqF$D_OUT[36:34] == 3'd1 ; + + // rule RL_biasWorker_wci_ctrl_OrE + assign WILL_FIRE_RL_biasWorker_wci_ctrl_OrE = + biasWorker_wci_wslv_wci_ctrl_pw$whas && + WILL_FIRE_RL_biasWorker_wci_wslv_ctl_op_start && + biasWorker_wci_wslv_cState == 3'd2 && + biasWorker_wci_wslv_reqF$D_OUT[36:34] == 3'd3 ; + + // rule RL_biasWorker_wci_cfwr + assign WILL_FIRE_RL_biasWorker_wci_cfwr = + biasWorker_wci_wslv_respF_c_r != 2'd2 && + biasWorker_wci_wslv_reqF$EMPTY_N && + biasWorker_wci_wslv_wci_cfwr_pw$whas && + !WILL_FIRE_RL_biasWorker_wci_wslv_ctl_op_start && + !WILL_FIRE_RL_biasWorker_wci_wslv_ctl_op_complete ; + + // rule RL_biasWorker_wci_wslv_ctl_op_complete + assign WILL_FIRE_RL_biasWorker_wci_wslv_ctl_op_complete = + biasWorker_wci_wslv_respF_c_r != 2'd2 && + biasWorker_wci_wslv_ctlOpActive && + biasWorker_wci_wslv_ctlAckReg ; + + // rule RL_biasWorker_wci_cfrd + assign WILL_FIRE_RL_biasWorker_wci_cfrd = + biasWorker_wci_wslv_respF_c_r != 2'd2 && + biasWorker_wci_wslv_reqF$EMPTY_N && + biasWorker_wci_wslv_wci_cfrd_pw$whas && + !WILL_FIRE_RL_biasWorker_wci_wslv_ctl_op_start && + !WILL_FIRE_RL_biasWorker_wci_wslv_ctl_op_complete ; + + // rule RL_biasWorker_wci_wslv_respF_incCtr + assign WILL_FIRE_RL_biasWorker_wci_wslv_respF_incCtr = + ((biasWorker_wci_wslv_respF_c_r == 2'd0) ? + biasWorker_wci_wslv_respF_x_wire$whas : + biasWorker_wci_wslv_respF_c_r != 2'd1 || + biasWorker_wci_wslv_respF_x_wire$whas) && + biasWorker_wci_wslv_respF_enqueueing$whas && + !(biasWorker_wci_wslv_respF_c_r != 2'd0) ; + + // rule RL_biasWorker_wci_wslv_respF_decCtr + assign WILL_FIRE_RL_biasWorker_wci_wslv_respF_decCtr = + biasWorker_wci_wslv_respF_c_r != 2'd0 && + !biasWorker_wci_wslv_respF_enqueueing$whas ; + + // rule RL_biasWorker_wci_wslv_respF_both + assign WILL_FIRE_RL_biasWorker_wci_wslv_respF_both = + ((biasWorker_wci_wslv_respF_c_r == 2'd1) ? + biasWorker_wci_wslv_respF_x_wire$whas : + biasWorker_wci_wslv_respF_c_r != 2'd2 || + biasWorker_wci_wslv_respF_x_wire$whas) && + biasWorker_wci_wslv_respF_c_r != 2'd0 && + biasWorker_wci_wslv_respF_enqueueing$whas ; + + // rule RL_biasWorker_wsiM_reqFifo_deq + assign WILL_FIRE_RL_biasWorker_wsiM_reqFifo_deq = + biasWorker_wsiM_reqFifo_c_r != 2'd0 && + !biasWorker_wsiM_sThreadBusy_d ; + + // rule RL_biasWorker_wsiM_reqFifo_incCtr + assign WILL_FIRE_RL_biasWorker_wsiM_reqFifo_incCtr = + ((biasWorker_wsiM_reqFifo_c_r == 2'd0) ? + MUX_biasWorker_wsiS_reqFifo_levelsValid$write_1__SEL_3 : + biasWorker_wsiM_reqFifo_c_r != 2'd1 || + MUX_biasWorker_wsiS_reqFifo_levelsValid$write_1__SEL_3) && + MUX_biasWorker_wsiS_reqFifo_levelsValid$write_1__SEL_3 && + !WILL_FIRE_RL_biasWorker_wsiM_reqFifo_deq ; + + // rule RL_biasWorker_wsiM_reqFifo_decCtr + assign WILL_FIRE_RL_biasWorker_wsiM_reqFifo_decCtr = + WILL_FIRE_RL_biasWorker_wsiM_reqFifo_deq && + !MUX_biasWorker_wsiS_reqFifo_levelsValid$write_1__SEL_3 ; + + // rule RL_biasWorker_wsiM_reqFifo_both + assign WILL_FIRE_RL_biasWorker_wsiM_reqFifo_both = + ((biasWorker_wsiM_reqFifo_c_r == 2'd1) ? + MUX_biasWorker_wsiS_reqFifo_levelsValid$write_1__SEL_3 : + biasWorker_wsiM_reqFifo_c_r != 2'd2 || + MUX_biasWorker_wsiS_reqFifo_levelsValid$write_1__SEL_3) && + WILL_FIRE_RL_biasWorker_wsiM_reqFifo_deq && + MUX_biasWorker_wsiS_reqFifo_levelsValid$write_1__SEL_3 ; + + // rule RL_biasWorker_wsiS_reqFifo_enq + assign WILL_FIRE_RL_biasWorker_wsiS_reqFifo_enq = + biasWorker_wsiS_reqFifo$FULL_N && biasWorker_wsiS_operateD && + biasWorker_wsiS_peerIsReady && + biasWorker_wsiS_wsiReq$wget[60:58] == 3'd1 ; + + // rule RL_biasWorker_wsiS_reqFifo_reset + assign WILL_FIRE_RL_biasWorker_wsiS_reqFifo_reset = + WILL_FIRE_RL_biasWorker_wsiS_reqFifo_enq || + MUX_biasWorker_wsiS_reqFifo_levelsValid$write_1__SEL_3 ; + + // rule RL_wsiS_reqFifo_enq + assign WILL_FIRE_RL_wsiS_reqFifo_enq = + wsiS_reqFifo$FULL_N && wsiS_operateD && wsiS_peerIsReady && + wsiS_wsiReq$wget[60:58] == 3'd1 ; + + // rule RL_wsiS_reqFifo_reset + assign WILL_FIRE_RL_wsiS_reqFifo_reset = + WILL_FIRE_RL_wsiS_reqFifo_enq || + MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 ; + + // rule RL_wciSeqFsm_action_l51c10 + assign WILL_FIRE_RL_wciSeqFsm_action_l51c10 = + wci_slvPresent && wciSeqFsm_state_mkFSMstate == 5'd1 ; + + // rule RL_wciSeqFsm_action_l54c8 + assign WILL_FIRE_RL_wciSeqFsm_action_l54c8 = + !wci_busy && wci_respF$FULL_N && + wciSeqFsm_state_mkFSMstate == 5'd3 ; + + // rule RL_wciSeqFsm_action_l55c5 + assign WILL_FIRE_RL_wciSeqFsm_action_l55c5 = + wci_respF$EMPTY_N && wciSeqFsm_state_mkFSMstate == 5'd4 ; + + // rule RL_wciSeqFsm_action_l58c8 + assign WILL_FIRE_RL_wciSeqFsm_action_l58c8 = + NOT_wci_busy_5_04_AND_IF_wci_wReset_n_5_THEN_N_ETC___d817 && + wciSeqFsm_state_mkFSMstate == 5'd6 ; + + // rule RL_wciSeqFsm_action_l59c5 + assign WILL_FIRE_RL_wciSeqFsm_action_l59c5 = + wci_respF$EMPTY_N && wciSeqFsm_state_mkFSMstate == 5'd7 ; + + // rule RL_wciSeqFsm_action_l62c8 + assign WILL_FIRE_RL_wciSeqFsm_action_l62c8 = + NOT_wci_busy_5_04_AND_IF_wci_wReset_n_5_THEN_N_ETC___d817 && + wciSeqFsm_state_mkFSMstate == 5'd9 ; + + // rule RL_wciSeqFsm_action_l63c5 + assign WILL_FIRE_RL_wciSeqFsm_action_l63c5 = + wci_respF$EMPTY_N && wciSeqFsm_state_mkFSMstate == 5'd10 ; + + // rule RL_wciSeqFsm_action_l66c8 + assign WILL_FIRE_RL_wciSeqFsm_action_l66c8 = + NOT_wci_busy_5_04_AND_IF_wci_wReset_n_5_THEN_N_ETC___d817 && + wciSeqFsm_state_mkFSMstate == 5'd12 ; + + // rule RL_wciSeqFsm_action_l67c5 + assign WILL_FIRE_RL_wciSeqFsm_action_l67c5 = + wci_respF$EMPTY_N && wciSeqFsm_state_mkFSMstate == 5'd13 ; + + // rule RL_wciSeqFsm_action_l70c8 + assign WILL_FIRE_RL_wciSeqFsm_action_l70c8 = + NOT_wci_busy_5_04_AND_IF_wci_wReset_n_5_THEN_N_ETC___d817 && + wciSeqFsm_state_mkFSMstate == 5'd15 ; + + // rule RL_wci_reqF_incCtr + assign WILL_FIRE_RL_wci_reqF_incCtr = + (wci_reqF_c_r || wci_reqF_x_wire$whas) && + wci_reqF_enqueueing$whas && + !wci_reqF_dequeueing$whas ; + + // rule RL_wci_reqF_decCtr + assign WILL_FIRE_RL_wci_reqF_decCtr = + wci_reqF_dequeueing$whas && !wci_reqF_enqueueing$whas ; + + // rule RL_wci_reqF_both + assign WILL_FIRE_RL_wci_reqF_both = + (!wci_reqF_c_r || wci_reqF_x_wire$whas) && + wci_reqF_dequeueing$whas && + wci_reqF_enqueueing$whas ; + + // rule RL_wciSeqFsm_action_l71c5 + assign WILL_FIRE_RL_wciSeqFsm_action_l71c5 = + wci_respF$EMPTY_N && wciSeqFsm_state_mkFSMstate == 5'd16 ; + + // rule RL_wciSeqFsm_fsm_start + assign WILL_FIRE_RL_wciSeqFsm_fsm_start = + wciSeqFsm_abort_whas__63_AND_wciSeqFsm_abort_w_ETC___d875 && + wciSeqFsm_start_reg ; + + // rule RL_wciSeqFsm_action_l50c5 + assign WILL_FIRE_RL_wciSeqFsm_action_l50c5 = + wciSeqFsm_start_wire$whas && + (wciSeqFsm_state_mkFSMstate == 5'd0 || + wciSeqFsm_state_mkFSMstate == 5'd22) ; + + // rule RL_wciSeqFsm_idle_l49c3 + assign WILL_FIRE_RL_wciSeqFsm_idle_l49c3 = + !wciSeqFsm_start_wire$whas && + wciSeqFsm_state_mkFSMstate == 5'd22 ; + + // inputs to muxes for submodule ports + assign MUX_biasWorker_biasValue$write_1__SEL_1 = + WILL_FIRE_RL_biasWorker_wci_cfwr && + biasWorker_wci_wslv_reqF$D_OUT[39:32] == 8'h0 ; + assign MUX_biasWorker_controlReg$write_1__SEL_1 = + WILL_FIRE_RL_biasWorker_wci_cfwr && + biasWorker_wci_wslv_reqF$D_OUT[39:32] == 8'h04 ; + assign MUX_biasWorker_wci_wslv_illegalEdge$write_1__SEL_1 = + WILL_FIRE_RL_biasWorker_wci_wslv_ctl_op_complete && + biasWorker_wci_wslv_illegalEdge ; + assign MUX_biasWorker_wci_wslv_illegalEdge$write_1__SEL_2 = + WILL_FIRE_RL_biasWorker_wci_wslv_ctl_op_start && + (biasWorker_wci_wslv_reqF$D_OUT[36:34] == 3'd0 && + biasWorker_wci_wslv_cState != 3'd0 || + biasWorker_wci_wslv_reqF$D_OUT[36:34] == 3'd1 && + biasWorker_wci_wslv_cState != 3'd1 && + biasWorker_wci_wslv_cState != 3'd3 || + biasWorker_wci_wslv_reqF$D_OUT[36:34] == 3'd2 && + biasWorker_wci_wslv_cState != 3'd2 || + biasWorker_wci_wslv_reqF$D_OUT[36:34] == 3'd3 && + biasWorker_wci_wslv_cState != 3'd3 && + biasWorker_wci_wslv_cState != 3'd2 && + biasWorker_wci_wslv_cState != 3'd1 || + biasWorker_wci_wslv_reqF$D_OUT[36:34] == 3'd4 || + biasWorker_wci_wslv_reqF$D_OUT[36:34] == 3'd5 || + biasWorker_wci_wslv_reqF$D_OUT[36:34] == 3'd6 || + biasWorker_wci_wslv_reqF$D_OUT[36:34] == 3'd7) ; + assign MUX_biasWorker_wci_wslv_respF_q_0$write_1__SEL_1 = + WILL_FIRE_RL_biasWorker_wci_wslv_respF_incCtr && + biasWorker_wci_wslv_respF_c_r == 2'd0 ; + assign MUX_biasWorker_wci_wslv_respF_q_1$write_1__SEL_2 = + WILL_FIRE_RL_biasWorker_wci_wslv_respF_incCtr && + biasWorker_wci_wslv_respF_c_r == 2'd1 ; + assign MUX_biasWorker_wsiM_reqFifo_q_0$write_1__SEL_1 = + WILL_FIRE_RL_biasWorker_wsiM_reqFifo_incCtr && + biasWorker_wsiM_reqFifo_c_r == 2'd0 ; + assign MUX_biasWorker_wsiM_reqFifo_q_1$write_1__SEL_1 = + WILL_FIRE_RL_biasWorker_wsiM_reqFifo_incCtr && + biasWorker_wsiM_reqFifo_c_r == 2'd1 ; + assign MUX_biasWorker_wsiS_reqFifo_levelsValid$write_1__SEL_3 = + biasWorker_wsiM_reqFifo_c_r != 2'd2 && + biasWorker_wsiS_reqFifo$EMPTY_N && + biasWorker_wci_wslv_cState == 3'd2 ; + assign MUX_wciSeqFsm_start_reg$write_1__SEL_2 = + wciSeqOnce_onceReady && + wciSeqFsm_abort_whas__63_AND_wciSeqFsm_abort_w_ETC___d875 && + !wciSeqFsm_start_reg ; + assign MUX_wci_busy$write_1__PSEL_1 = + WILL_FIRE_RL_wciSeqFsm_action_l70c8 || + WILL_FIRE_RL_wciSeqFsm_action_l66c8 || + WILL_FIRE_RL_wciSeqFsm_action_l62c8 || + WILL_FIRE_RL_wciSeqFsm_action_l58c8 ; + assign MUX_wci_busy$write_1__SEL_1 = + MUX_wci_busy$write_1__PSEL_1 && wci_wReset_n ; + assign MUX_wci_busy$write_1__SEL_2 = + WILL_FIRE_RL_wci_wrkBusy && + (!wci_respTimr_7_ULT_1_SL_wci_wTimeout_8_9___d969 || + biasWorker_wci_wslv_respF_q_0[33:32] != 2'd0) ; + assign MUX_wci_lastConfigBE$write_1__SEL_1 = + WILL_FIRE_RL_wciSeqFsm_action_l66c8 && wci_wReset_n ; + assign MUX_wci_lastConfigBE$write_1__SEL_2 = + WILL_FIRE_RL_wciSeqFsm_action_l62c8 && wci_wReset_n ; + assign MUX_wci_lastControlOp$write_1__SEL_1 = + WILL_FIRE_RL_wciSeqFsm_action_l58c8 && wci_wReset_n ; + assign MUX_wci_lastControlOp$write_1__SEL_2 = + WILL_FIRE_RL_wciSeqFsm_action_l70c8 && wci_wReset_n ; + assign MUX_wci_reqF_q_0$write_1__SEL_2 = + WILL_FIRE_RL_wci_reqF_incCtr && !wci_reqF_c_r ; + assign MUX_wci_reqPend$write_1__PSEL_3 = + WILL_FIRE_RL_wciSeqFsm_action_l70c8 || + WILL_FIRE_RL_wciSeqFsm_action_l58c8 ; + assign MUX_wci_reqPend$write_1__SEL_3 = + MUX_wci_reqPend$write_1__PSEL_3 && wci_wReset_n ; + assign MUX_wci_reqPend$write_1__SEL_4 = + WILL_FIRE_RL_wci_wrkBusy && + biasWorker_wci_wslv_respF_q_0[33:32] != 2'd0 ; + assign MUX_wci_respF$enq_1__SEL_1 = + MUX_wci_busy$write_1__PSEL_1 && !wci_wReset_n ; + assign MUX_wsiM_reqFifo_q_0$write_1__SEL_2 = + WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_c_r == 2'd0 ; + assign MUX_wsiM_reqFifo_q_1$write_1__SEL_2 = + WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_c_r == 2'd1 ; + assign MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 = + wsiS_reqFifo$EMPTY_N && enWsiChecker ; + assign MUX_biasWorker_wci_wslv_illegalEdge$write_1__VAL_2 = + biasWorker_wci_wslv_reqF$D_OUT[36:34] != 3'd4 && + biasWorker_wci_wslv_reqF$D_OUT[36:34] != 3'd5 && + biasWorker_wci_wslv_reqF$D_OUT[36:34] != 3'd6 ; + assign MUX_biasWorker_wci_wslv_respF_c_r$write_1__VAL_1 = + biasWorker_wci_wslv_respF_c_r + 2'd1 ; + assign MUX_biasWorker_wci_wslv_respF_c_r$write_1__VAL_2 = + biasWorker_wci_wslv_respF_c_r - 2'd1 ; + always@(WILL_FIRE_RL_biasWorker_wci_wslv_ctl_op_complete or + MUX_biasWorker_wci_wslv_respF_x_wire$wset_1__VAL_1 or + WILL_FIRE_RL_biasWorker_wci_cfrd or + MUX_biasWorker_wci_wslv_respF_x_wire$wset_1__VAL_2 or + WILL_FIRE_RL_biasWorker_wci_cfwr) + begin + case (1'b1) // synopsys parallel_case + WILL_FIRE_RL_biasWorker_wci_wslv_ctl_op_complete: + MUX_biasWorker_wci_wslv_respF_q_0$write_1__VAL_1 = + MUX_biasWorker_wci_wslv_respF_x_wire$wset_1__VAL_1; + WILL_FIRE_RL_biasWorker_wci_cfrd: + MUX_biasWorker_wci_wslv_respF_q_0$write_1__VAL_1 = + MUX_biasWorker_wci_wslv_respF_x_wire$wset_1__VAL_2; + WILL_FIRE_RL_biasWorker_wci_cfwr: + MUX_biasWorker_wci_wslv_respF_q_0$write_1__VAL_1 = 34'h1C0DE4201; + default: MUX_biasWorker_wci_wslv_respF_q_0$write_1__VAL_1 = + 34'h2AAAAAAAA /* unspecified value */ ; + endcase + end + assign MUX_biasWorker_wci_wslv_respF_q_0$write_1__VAL_2 = + (biasWorker_wci_wslv_respF_c_r == 2'd1) ? + MUX_biasWorker_wci_wslv_respF_q_0$write_1__VAL_1 : + biasWorker_wci_wslv_respF_q_1 ; + assign MUX_biasWorker_wci_wslv_respF_q_1$write_1__VAL_1 = + (biasWorker_wci_wslv_respF_c_r == 2'd2) ? + MUX_biasWorker_wci_wslv_respF_q_0$write_1__VAL_1 : + 34'h0AAAAAAAA ; + assign MUX_biasWorker_wci_wslv_respF_x_wire$wset_1__VAL_1 = + biasWorker_wci_wslv_illegalEdge ? 34'h3C0DE4202 : 34'h1C0DE4201 ; + assign MUX_biasWorker_wci_wslv_respF_x_wire$wset_1__VAL_2 = + { 2'd1, _theResult____h21260 } ; + assign MUX_biasWorker_wsiM_reqFifo_c_r$write_1__VAL_1 = + biasWorker_wsiM_reqFifo_c_r + 2'd1 ; + assign MUX_biasWorker_wsiM_reqFifo_c_r$write_1__VAL_2 = + biasWorker_wsiM_reqFifo_c_r - 2'd1 ; + assign MUX_biasWorker_wsiM_reqFifo_q_0$write_1__VAL_1 = + { biasWorker_wsiS_reqFifo$D_OUT[60:44], + x_data__h20592, + biasWorker_wsiS_reqFifo$D_OUT[11:0] } ; + assign MUX_biasWorker_wsiM_reqFifo_q_0$write_1__VAL_2 = + (biasWorker_wsiM_reqFifo_c_r == 2'd1) ? + MUX_biasWorker_wsiM_reqFifo_q_0$write_1__VAL_1 : + biasWorker_wsiM_reqFifo_q_1 ; + assign MUX_biasWorker_wsiM_reqFifo_q_1$write_1__VAL_2 = + (biasWorker_wsiM_reqFifo_c_r == 2'd2) ? + MUX_biasWorker_wsiM_reqFifo_q_0$write_1__VAL_1 : + 61'h00000AAAAAAAAA00 ; + assign MUX_dstUnrollCnt$write_1__VAL_2 = + (dstUnrollCnt == 16'd1) ? wsiBurstLength__h66174 : x__h66543 ; + assign MUX_srcUnrollCnt$write_1__VAL_2 = + (srcUnrollCnt == 16'd1) ? 16'd16 : x__h66071 ; + assign MUX_wci_reqF_c_r$write_1__VAL_1 = wci_reqF_c_r + 1'd1 ; + assign MUX_wci_reqF_c_r$write_1__VAL_2 = wci_reqF_c_r - 1'd1 ; + assign MUX_wci_reqF_q_0$write_1__VAL_1 = + wci_reqF_c_r ? + MUX_wci_reqF_q_0$write_1__VAL_2 : + 72'h0000000000AAAAAAAA ; + always@(MUX_wci_lastControlOp$write_1__SEL_1 or + MUX_wci_lastConfigBE$write_1__SEL_2 or + MUX_wci_reqF_x_wire$wset_1__VAL_2 or + MUX_wci_lastConfigBE$write_1__SEL_1 or + MUX_wci_reqF_x_wire$wset_1__VAL_3 or + MUX_wci_lastControlOp$write_1__SEL_2) + begin + case (1'b1) // synopsys parallel_case + MUX_wci_lastControlOp$write_1__SEL_1: + MUX_wci_reqF_q_0$write_1__VAL_2 = 72'h4F00000000AAAAAAAA; + MUX_wci_lastConfigBE$write_1__SEL_2: + MUX_wci_reqF_q_0$write_1__VAL_2 = MUX_wci_reqF_x_wire$wset_1__VAL_2; + MUX_wci_lastConfigBE$write_1__SEL_1: + MUX_wci_reqF_q_0$write_1__VAL_2 = MUX_wci_reqF_x_wire$wset_1__VAL_3; + MUX_wci_lastControlOp$write_1__SEL_2: + MUX_wci_reqF_q_0$write_1__VAL_2 = 72'h4F00000004AAAAAAAA; + default: MUX_wci_reqF_q_0$write_1__VAL_2 = + 72'hAAAAAAAAAAAAAAAAAA /* unspecified value */ ; + endcase + end + assign MUX_wci_reqF_x_wire$wset_1__VAL_2 = + { 8'd63, wciAddr__h60695, 32'h00004242 } ; + assign MUX_wci_reqF_x_wire$wset_1__VAL_3 = + { 8'd90, wciAddr__h60695, 32'hAAAAAAAA } ; + assign MUX_wci_respF$enq_1__VAL_2 = + (biasWorker_wci_wslv_respF_q_0[33:32] == 2'd0) ? + 34'h1C0DE4203 : + biasWorker_wci_wslv_respF_q_0 ; + assign MUX_wci_respTimr$write_1__VAL_2 = + (biasWorker_wci_wslv_respF_q_0[33:32] == 2'd0) ? + (wci_respTimr_7_ULT_1_SL_wci_wTimeout_8_9___d969 ? + x__h2746 : + 32'd0) : + 32'd0 ; + assign MUX_wsiM_reqFifo_c_r$write_1__VAL_1 = wsiM_reqFifo_c_r + 2'd1 ; + assign MUX_wsiM_reqFifo_c_r$write_1__VAL_2 = wsiM_reqFifo_c_r - 2'd1 ; + assign MUX_wsiM_reqFifo_q_0$write_1__VAL_1 = + (wsiM_reqFifo_c_r == 2'd1) ? + MUX_wsiM_reqFifo_q_0$write_1__VAL_2 : + wsiM_reqFifo_q_1 ; + assign MUX_wsiM_reqFifo_q_0$write_1__VAL_2 = + { 3'd1, srcUnrollCnt == 16'd1, 13'd4112, srcDataOut, 12'd3840 } ; + assign MUX_wsiM_reqFifo_q_1$write_1__VAL_1 = + (wsiM_reqFifo_c_r == 2'd2) ? + MUX_wsiM_reqFifo_q_0$write_1__VAL_2 : + 61'h00000AAAAAAAAA00 ; + + // inlined wires + assign wci_reqF_x_wire$wget = MUX_wci_reqF_q_0$write_1__VAL_2 ; + assign wci_reqF_x_wire$whas = + WILL_FIRE_RL_wciSeqFsm_action_l58c8 && wci_wReset_n || + WILL_FIRE_RL_wciSeqFsm_action_l62c8 && wci_wReset_n || + WILL_FIRE_RL_wciSeqFsm_action_l66c8 && wci_wReset_n || + WILL_FIRE_RL_wciSeqFsm_action_l70c8 && wci_wReset_n ; + assign wci_wciResponse$wget = biasWorker_wci_wslv_respF_q_0 ; + assign wci_wciResponse$whas = 1'd1 ; + assign wci_sfCapSet_1$wget = biasWorker_wci_wslv_sFlagReg ; + assign wci_sfCapSet_1$whas = 1'd1 ; + assign wci_sfCapClear_1$wget = 1'b0 ; + assign wci_sfCapClear_1$whas = 1'b0 ; + assign wci_wci_Em_resp_w$wget = biasWorker_wci_wslv_respF_q_0[33:32] ; + assign wci_wci_Em_resp_w$whas = 1'd1 ; + assign wci_wci_Em_respData_w$wget = biasWorker_wci_wslv_respF_q_0[31:0] ; + assign wci_wci_Em_respData_w$whas = 1'd1 ; + assign wsiM_reqFifo_x_wire$wget = MUX_wsiM_reqFifo_q_0$write_1__VAL_2 ; + assign wsiM_reqFifo_x_wire$whas = wsiM_reqFifo_enqueueing$whas ; + assign wsiM_operateD_1$wget = 1'd1 ; + assign wsiM_operateD_1$whas = testOperating ; + assign wsiM_peerIsReady_1$wget = 1'd1 ; + assign wsiM_peerIsReady_1$whas = + !biasWorker_wsiS_isReset_isInReset && biasWorker_wsiS_operateD ; + assign wsiS_wsiReq$wget = + { wsi_Es_mCmd_w$wget, + wsi_Es_mReqLast_w$whas, + wsi_Es_mBurstPrecise_w$whas, + wsi_Es_mBurstLength_w$wget, + biasWorker_wsiM_reqFifo_q_0[43:8], + wsi_Es_mReqInfo_w$wget } ; + assign wsiS_wsiReq$whas = 1'd1 ; + assign wsiS_operateD_1$wget = 1'd1 ; + assign wsiS_operateD_1$whas = testOperating ; + assign wsiS_peerIsReady_1$wget = 1'd1 ; + assign wsiS_peerIsReady_1$whas = + !biasWorker_wsiM_isReset_isInReset && biasWorker_wsiM_operateD ; + assign wsiS_sThreadBusy_dw$wget = wsiS_reqFifo_countReg > 2'd1 ; + assign wsiS_sThreadBusy_dw$whas = + wsiS_reqFifo_levelsValid && wsiS_operateD && wsiS_peerIsReady ; + assign biasWorker_wci_wslv_wciReq$wget = + { biasWorker_wci_wci_Es_mCmd_w$wget, + biasWorker_wci_wci_Es_mAddrSpace_w$wget, + biasWorker_wci_wci_Es_mByteEn_w$wget, + biasWorker_wci_wci_Es_mAddr_w$wget, + wci_reqF_q_0[31:0] } ; + assign biasWorker_wci_wslv_wciReq$whas = 1'd1 ; + assign biasWorker_wci_wslv_respF_x_wire$wget = + MUX_biasWorker_wci_wslv_respF_q_0$write_1__VAL_1 ; + assign biasWorker_wci_wslv_respF_x_wire$whas = + WILL_FIRE_RL_biasWorker_wci_wslv_ctl_op_complete || + WILL_FIRE_RL_biasWorker_wci_cfrd || + WILL_FIRE_RL_biasWorker_wci_cfwr ; + assign biasWorker_wci_wslv_wEdge$wget = + biasWorker_wci_wslv_reqF$D_OUT[36:34] ; + assign biasWorker_wci_wslv_wEdge$whas = + WILL_FIRE_RL_biasWorker_wci_wslv_ctl_op_start ; + assign biasWorker_wci_wslv_sFlagReg_1$wget = 1'b0 ; + assign biasWorker_wci_wslv_sFlagReg_1$whas = 1'b0 ; + assign biasWorker_wci_wslv_ctlAckReg_1$wget = 1'd1 ; + assign biasWorker_wci_wslv_ctlAckReg_1$whas = + WILL_FIRE_RL_biasWorker_wci_ctrl_OrE || + WILL_FIRE_RL_biasWorker_wci_ctrl_IsO || + WILL_FIRE_RL_biasWorker_wci_ctrl_EiI ; + assign biasWorker_wci_wci_Es_mCmd_w$wget = + wci_sThreadBusy_d ? 3'd0 : wci_reqF_q_0[71:69] ; + assign biasWorker_wci_wci_Es_mCmd_w$whas = 1'd1 ; + assign biasWorker_wci_wci_Es_mAddrSpace_w$wget = + !wci_sThreadBusy_d && wci_reqF_q_0[68] ; + assign biasWorker_wci_wci_Es_mAddrSpace_w$whas = 1'd1 ; + assign biasWorker_wci_wci_Es_mByteEn_w$wget = + wci_sThreadBusy_d ? 4'd0 : wci_reqF_q_0[67:64] ; + assign biasWorker_wci_wci_Es_mByteEn_w$whas = 1'd1 ; + assign biasWorker_wci_wci_Es_mAddr_w$wget = + wci_sThreadBusy_d ? 32'd0 : wci_reqF_q_0[63:32] ; + assign biasWorker_wci_wci_Es_mAddr_w$whas = 1'd1 ; + assign biasWorker_wci_wci_Es_mData_w$wget = wci_reqF_q_0[31:0] ; + assign biasWorker_wci_wci_Es_mData_w$whas = 1'd1 ; + assign biasWorker_wsiS_wsiReq$wget = + { biasWorker_wsi_Es_mCmd_w$wget, + biasWorker_wsi_Es_mReqLast_w$whas, + biasWorker_wsi_Es_mBurstPrecise_w$whas, + biasWorker_wsi_Es_mBurstLength_w$wget, + wsiM_reqFifo_q_0[43:8], + biasWorker_wsi_Es_mReqInfo_w$wget } ; + assign biasWorker_wsiS_wsiReq$whas = 1'd1 ; + assign biasWorker_wsiS_operateD_1$wget = 1'd1 ; + assign biasWorker_wsiS_operateD_1$whas = + biasWorker_wci_wslv_cState == 3'd2 ; + assign biasWorker_wsiS_peerIsReady_1$wget = 1'd1 ; + assign biasWorker_wsiS_peerIsReady_1$whas = + !wsiM_isReset_isInReset && wsiM_operateD ; + assign biasWorker_wsiS_sThreadBusy_dw$wget = + biasWorker_wsiS_reqFifo_countReg > 2'd1 ; + assign biasWorker_wsiS_sThreadBusy_dw$whas = + biasWorker_wsiS_reqFifo_levelsValid && + biasWorker_wsiS_operateD && + biasWorker_wsiS_peerIsReady ; + assign biasWorker_wsiM_reqFifo_x_wire$wget = + MUX_biasWorker_wsiM_reqFifo_q_0$write_1__VAL_1 ; + assign biasWorker_wsiM_reqFifo_x_wire$whas = + MUX_biasWorker_wsiS_reqFifo_levelsValid$write_1__SEL_3 ; + assign biasWorker_wsiM_operateD_1$wget = 1'd1 ; + assign biasWorker_wsiM_operateD_1$whas = + biasWorker_wci_wslv_cState == 3'd2 ; + assign biasWorker_wsiM_peerIsReady_1$wget = 1'd1 ; + assign biasWorker_wsiM_peerIsReady_1$whas = + !wsiS_isReset_isInReset && wsiS_operateD ; + assign biasWorker_wsi_Es_mCmd_w$wget = + wsiM_sThreadBusy_d ? 3'd0 : wsiM_reqFifo_q_0[60:58] ; + assign biasWorker_wsi_Es_mCmd_w$whas = 1'd1 ; + assign biasWorker_wsi_Es_mBurstLength_w$wget = + wsiM_sThreadBusy_d ? 12'd0 : wsiM_reqFifo_q_0[55:44] ; + assign biasWorker_wsi_Es_mBurstLength_w$whas = 1'd1 ; + assign biasWorker_wsi_Es_mData_w$wget = wsiM_reqFifo_q_0[43:12] ; + assign biasWorker_wsi_Es_mData_w$whas = 1'd1 ; + assign biasWorker_wsi_Es_mByteEn_w$wget = wsiM_reqFifo_q_0[11:8] ; + assign biasWorker_wsi_Es_mByteEn_w$whas = 1'd1 ; + assign biasWorker_wsi_Es_mReqInfo_w$wget = + wsiM_sThreadBusy_d ? 8'd0 : wsiM_reqFifo_q_0[7:0] ; + assign biasWorker_wsi_Es_mReqInfo_w$whas = 1'd1 ; + assign wsi_Es_mCmd_w$wget = + biasWorker_wsiM_sThreadBusy_d ? + 3'd0 : + biasWorker_wsiM_reqFifo_q_0[60:58] ; + assign wsi_Es_mCmd_w$whas = 1'd1 ; + assign wsi_Es_mBurstLength_w$wget = + biasWorker_wsiM_sThreadBusy_d ? + 12'd0 : + biasWorker_wsiM_reqFifo_q_0[55:44] ; + assign wsi_Es_mBurstLength_w$whas = 1'd1 ; + assign wsi_Es_mData_w$wget = biasWorker_wsiM_reqFifo_q_0[43:12] ; + assign wsi_Es_mData_w$whas = 1'd1 ; + assign wsi_Es_mByteEn_w$wget = biasWorker_wsiM_reqFifo_q_0[11:8] ; + assign wsi_Es_mByteEn_w$whas = 1'd1 ; + assign wsi_Es_mReqInfo_w$wget = + biasWorker_wsiM_sThreadBusy_d ? + 8'd0 : + biasWorker_wsiM_reqFifo_q_0[7:0] ; + assign wsi_Es_mReqInfo_w$whas = 1'd1 ; + assign wciSeqFsm_start_wire$wget = 1'd1 ; + assign wciSeqFsm_start_wire$whas = + WILL_FIRE_RL_wciSeqFsm_fsm_start || + wciSeqFsm_start_reg_1 && !wciSeqFsm_state_fired ; + assign wciSeqFsm_start_reg_1_1$wget = 1'd1 ; + assign wciSeqFsm_start_reg_1_1$whas = wciSeqFsm_start_wire$whas ; + assign wciSeqFsm_abort$wget = 1'b0 ; + assign wciSeqFsm_abort$whas = 1'b0 ; + assign wciSeqFsm_state_fired_1$wget = 1'd1 ; + assign wciSeqFsm_state_fired_1$whas = wciSeqFsm_state_set_pw$whas ; + assign wci_reqF_enqueueing$whas = + MUX_wci_busy$write_1__PSEL_1 && wci_wReset_n ; + assign wci_reqF_dequeueing$whas = + !wci_sThreadBusy_d && + biasWorker_wci_wslv_respF_q_0[33:32] == 2'd0 && + wci_reqF_c_r ; + assign wci_sThreadBusy_pw$whas = + biasWorker_wci_wslv_reqF_countReg > 2'd1 || + biasWorker_wci_wslv_isReset_isInReset ; + assign wsiM_reqFifo_enqueueing$whas = + wsiM_reqFifo_c_r != 2'd2 && enWsiSource ; + assign wsiM_reqFifo_dequeueing$whas = WILL_FIRE_RL_wsiM_reqFifo_deq ; + assign wsiM_sThreadBusy_pw$whas = + !biasWorker_wsiS_sThreadBusy_dw$whas || + biasWorker_wsiS_sThreadBusy_dw$wget ; + assign wsiS_reqFifo_r_enq$whas = WILL_FIRE_RL_wsiS_reqFifo_enq ; + assign wsiS_reqFifo_r_deq$whas = + MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 ; + assign wsiS_reqFifo_r_clr$whas = 1'b0 ; + assign wsiS_reqFifo_doResetEnq$whas = WILL_FIRE_RL_wsiS_reqFifo_enq ; + assign wsiS_reqFifo_doResetDeq$whas = + MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 ; + assign wsiS_reqFifo_doResetClr$whas = 1'b0 ; + assign biasWorker_wci_wslv_reqF_r_enq$whas = + biasWorker_wci_wslv_wciReq$wget[71:69] != 3'd0 ; + assign biasWorker_wci_wslv_reqF_r_deq$whas = + WILL_FIRE_RL_biasWorker_wci_cfrd || + WILL_FIRE_RL_biasWorker_wci_cfwr || + WILL_FIRE_RL_biasWorker_wci_wslv_ctl_op_start ; + assign biasWorker_wci_wslv_reqF_r_clr$whas = 1'b0 ; + assign biasWorker_wci_wslv_respF_enqueueing$whas = + WILL_FIRE_RL_biasWorker_wci_cfrd || + WILL_FIRE_RL_biasWorker_wci_cfwr || + WILL_FIRE_RL_biasWorker_wci_wslv_ctl_op_complete ; + assign biasWorker_wci_wslv_respF_dequeueing$whas = + biasWorker_wci_wslv_respF_c_r != 2'd0 ; + assign biasWorker_wci_wslv_sThreadBusy_pw$whas = 1'b0 ; + assign biasWorker_wci_wslv_wci_cfwr_pw$whas = + biasWorker_wci_wslv_reqF$EMPTY_N && + biasWorker_wci_wslv_reqF$D_OUT[68] && + biasWorker_wci_wslv_reqF$D_OUT[71:69] == 3'd1 ; + assign biasWorker_wci_wslv_wci_cfrd_pw$whas = + biasWorker_wci_wslv_reqF$EMPTY_N && + biasWorker_wci_wslv_reqF$D_OUT[68] && + biasWorker_wci_wslv_reqF$D_OUT[71:69] == 3'd2 ; + assign biasWorker_wci_wslv_wci_ctrl_pw$whas = + biasWorker_wci_wslv_reqF$EMPTY_N && + !biasWorker_wci_wslv_reqF$D_OUT[68] && + biasWorker_wci_wslv_reqF$D_OUT[71:69] == 3'd2 ; + assign biasWorker_wsiS_reqFifo_r_enq$whas = + WILL_FIRE_RL_biasWorker_wsiS_reqFifo_enq ; + assign biasWorker_wsiS_reqFifo_r_deq$whas = + MUX_biasWorker_wsiS_reqFifo_levelsValid$write_1__SEL_3 ; + assign biasWorker_wsiS_reqFifo_r_clr$whas = 1'b0 ; + assign biasWorker_wsiS_reqFifo_doResetEnq$whas = + WILL_FIRE_RL_biasWorker_wsiS_reqFifo_enq ; + assign biasWorker_wsiS_reqFifo_doResetDeq$whas = + MUX_biasWorker_wsiS_reqFifo_levelsValid$write_1__SEL_3 ; + assign biasWorker_wsiS_reqFifo_doResetClr$whas = 1'b0 ; + assign biasWorker_wsiM_reqFifo_enqueueing$whas = + MUX_biasWorker_wsiS_reqFifo_levelsValid$write_1__SEL_3 ; + assign biasWorker_wsiM_reqFifo_dequeueing$whas = + WILL_FIRE_RL_biasWorker_wsiM_reqFifo_deq ; + assign biasWorker_wsiM_sThreadBusy_pw$whas = + !wsiS_sThreadBusy_dw$whas || wsiS_sThreadBusy_dw$wget ; + assign biasWorker_wsi_Es_mReqLast_w$whas = + !wsiM_sThreadBusy_d && wsiM_reqFifo_q_0[57] ; + assign biasWorker_wsi_Es_mBurstPrecise_w$whas = + !wsiM_sThreadBusy_d && wsiM_reqFifo_q_0[56] ; + assign biasWorker_wsi_Es_mDataInfo_w$whas = 1'd1 ; + assign wsi_Es_mReqLast_w$whas = + !biasWorker_wsiM_sThreadBusy_d && + biasWorker_wsiM_reqFifo_q_0[57] ; + assign wsi_Es_mBurstPrecise_w$whas = + !biasWorker_wsiM_sThreadBusy_d && + biasWorker_wsiM_reqFifo_q_0[56] ; + assign wsi_Es_mDataInfo_w$whas = 1'd1 ; + assign wciSeqFsm_state_set_pw$whas = + WILL_FIRE_RL_wciSeqFsm_idle_l49c3 || + wciSeqFsm_state_mkFSMstate == 5'd21 || + wciSeqFsm_state_mkFSMstate == 5'd20 || + wciSeqFsm_state_mkFSMstate == 5'd19 || + wciSeqFsm_state_mkFSMstate == 5'd18 || + wciSeqFsm_state_mkFSMstate == 5'd17 || + WILL_FIRE_RL_wciSeqFsm_action_l71c5 || + WILL_FIRE_RL_wciSeqFsm_action_l70c8 || + wciSeqFsm_state_mkFSMstate == 5'd14 || + WILL_FIRE_RL_wciSeqFsm_action_l67c5 || + WILL_FIRE_RL_wciSeqFsm_action_l66c8 || + wciSeqFsm_state_mkFSMstate == 5'd11 || + WILL_FIRE_RL_wciSeqFsm_action_l63c5 || + WILL_FIRE_RL_wciSeqFsm_action_l62c8 || + wciSeqFsm_state_mkFSMstate == 5'd8 || + WILL_FIRE_RL_wciSeqFsm_action_l59c5 || + WILL_FIRE_RL_wciSeqFsm_action_l58c8 || + wciSeqFsm_state_mkFSMstate == 5'd5 || + WILL_FIRE_RL_wciSeqFsm_action_l55c5 || + WILL_FIRE_RL_wciSeqFsm_action_l54c8 || + wciSeqFsm_state_mkFSMstate == 5'd2 || + WILL_FIRE_RL_wciSeqFsm_action_l51c10 || + WILL_FIRE_RL_wciSeqFsm_action_l50c5 ; + assign wciSeqFsm_state_overlap_pw$whas = 1'b0 ; + assign wsiM_extStatusW$wget = + { wsiM_pMesgCount, wsiM_iMesgCount, wsiM_tBusyCount } ; + assign wsiS_extStatusW$wget = + { wsiS_pMesgCount, wsiS_iMesgCount, wsiS_tBusyCount } ; + assign biasWorker_wsiS_extStatusW$wget = + { biasWorker_wsiS_pMesgCount, + biasWorker_wsiS_iMesgCount, + biasWorker_wsiS_tBusyCount } ; + assign biasWorker_wsiM_extStatusW$wget = + { biasWorker_wsiM_pMesgCount, + biasWorker_wsiM_iMesgCount, + biasWorker_wsiM_tBusyCount } ; + + // register badDataCnt + assign badDataCnt$D_IN = badDataCnt + 32'd1 ; + assign badDataCnt$EN = + MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 && + !wsiS_reqFifo_first__99_BITS_43_TO_12_00_EQ_dst_ETC___d943 ; + + // register badMesgCnt + assign badMesgCnt$D_IN = badMesgCnt + 32'd1 ; + assign badMesgCnt$EN = + MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 && + dstUnrollCnt == 16'd1 && + (!wsiS_reqFifo_first__99_BITS_43_TO_12_00_EQ_dst_ETC___d943 || + mesgHadError) ; + + // register biasWorker_biasValue + assign biasWorker_biasValue$D_IN = + MUX_biasWorker_biasValue$write_1__SEL_1 ? + biasWorker_wci_wslv_reqF$D_OUT[31:0] : + 32'd0 ; + assign biasWorker_biasValue$EN = + WILL_FIRE_RL_biasWorker_wci_cfwr && + biasWorker_wci_wslv_reqF$D_OUT[39:32] == 8'h0 || + WILL_FIRE_RL_biasWorker_wci_ctrl_EiI ; + + // register biasWorker_controlReg + assign biasWorker_controlReg$D_IN = + MUX_biasWorker_controlReg$write_1__SEL_1 ? + biasWorker_wci_wslv_reqF$D_OUT[31:0] : + 32'd0 ; + assign biasWorker_controlReg$EN = + WILL_FIRE_RL_biasWorker_wci_cfwr && + biasWorker_wci_wslv_reqF$D_OUT[39:32] == 8'h04 || + WILL_FIRE_RL_biasWorker_wci_ctrl_EiI ; + + // register biasWorker_wci_wslv_cEdge + assign biasWorker_wci_wslv_cEdge$D_IN = + biasWorker_wci_wslv_reqF$D_OUT[36:34] ; + assign biasWorker_wci_wslv_cEdge$EN = + WILL_FIRE_RL_biasWorker_wci_wslv_ctl_op_start ; + + // register biasWorker_wci_wslv_cState + assign biasWorker_wci_wslv_cState$D_IN = biasWorker_wci_wslv_nState ; + assign biasWorker_wci_wslv_cState$EN = + WILL_FIRE_RL_biasWorker_wci_wslv_ctl_op_complete && + !biasWorker_wci_wslv_illegalEdge ; + + // register biasWorker_wci_wslv_ctlAckReg + assign biasWorker_wci_wslv_ctlAckReg$D_IN = + biasWorker_wci_wslv_ctlAckReg_1$whas ; + assign biasWorker_wci_wslv_ctlAckReg$EN = 1'd1 ; + + // register biasWorker_wci_wslv_ctlOpActive + assign biasWorker_wci_wslv_ctlOpActive$D_IN = + !WILL_FIRE_RL_biasWorker_wci_wslv_ctl_op_complete ; + assign biasWorker_wci_wslv_ctlOpActive$EN = + WILL_FIRE_RL_biasWorker_wci_wslv_ctl_op_complete || + WILL_FIRE_RL_biasWorker_wci_wslv_ctl_op_start ; + + // register biasWorker_wci_wslv_illegalEdge + assign biasWorker_wci_wslv_illegalEdge$D_IN = + !MUX_biasWorker_wci_wslv_illegalEdge$write_1__SEL_1 && + MUX_biasWorker_wci_wslv_illegalEdge$write_1__VAL_2 ; + assign biasWorker_wci_wslv_illegalEdge$EN = + WILL_FIRE_RL_biasWorker_wci_wslv_ctl_op_complete && + biasWorker_wci_wslv_illegalEdge || + MUX_biasWorker_wci_wslv_illegalEdge$write_1__SEL_2 ; + + // register biasWorker_wci_wslv_isReset_isInReset + assign biasWorker_wci_wslv_isReset_isInReset$D_IN = 1'd0 ; + assign biasWorker_wci_wslv_isReset_isInReset$EN = + biasWorker_wci_wslv_isReset_isInReset ; + + // register biasWorker_wci_wslv_nState + always@(biasWorker_wci_wslv_reqF$D_OUT) + begin + case (biasWorker_wci_wslv_reqF$D_OUT[36:34]) + 3'd0: biasWorker_wci_wslv_nState$D_IN = 3'd1; + 3'd1: biasWorker_wci_wslv_nState$D_IN = 3'd2; + 3'd2: biasWorker_wci_wslv_nState$D_IN = 3'd3; + default: biasWorker_wci_wslv_nState$D_IN = 3'd0; + endcase + end + assign biasWorker_wci_wslv_nState$EN = + WILL_FIRE_RL_biasWorker_wci_wslv_ctl_op_start && + (biasWorker_wci_wslv_reqF$D_OUT[36:34] == 3'd0 && + biasWorker_wci_wslv_cState == 3'd0 || + biasWorker_wci_wslv_reqF$D_OUT[36:34] == 3'd1 && + (biasWorker_wci_wslv_cState == 3'd1 || + biasWorker_wci_wslv_cState == 3'd3) || + biasWorker_wci_wslv_reqF$D_OUT[36:34] == 3'd2 && + biasWorker_wci_wslv_cState == 3'd2 || + biasWorker_wci_wslv_reqF$D_OUT[36:34] == 3'd3 && + (biasWorker_wci_wslv_cState == 3'd3 || + biasWorker_wci_wslv_cState == 3'd2 || + biasWorker_wci_wslv_cState == 3'd1)) ; + + // register biasWorker_wci_wslv_reqF_countReg + assign biasWorker_wci_wslv_reqF_countReg$D_IN = + (biasWorker_wci_wslv_wciReq$wget[71:69] != 3'd0) ? + biasWorker_wci_wslv_reqF_countReg + 2'd1 : + biasWorker_wci_wslv_reqF_countReg - 2'd1 ; + assign biasWorker_wci_wslv_reqF_countReg$EN = + (biasWorker_wci_wslv_wciReq$wget[71:69] != 3'd0) != + biasWorker_wci_wslv_reqF_r_deq$whas ; + + // register biasWorker_wci_wslv_respF_c_r + assign biasWorker_wci_wslv_respF_c_r$D_IN = + WILL_FIRE_RL_biasWorker_wci_wslv_respF_incCtr ? + MUX_biasWorker_wci_wslv_respF_c_r$write_1__VAL_1 : + MUX_biasWorker_wci_wslv_respF_c_r$write_1__VAL_2 ; + assign biasWorker_wci_wslv_respF_c_r$EN = + WILL_FIRE_RL_biasWorker_wci_wslv_respF_incCtr || + WILL_FIRE_RL_biasWorker_wci_wslv_respF_decCtr ; + + // register biasWorker_wci_wslv_respF_q_0 + always@(MUX_biasWorker_wci_wslv_respF_q_0$write_1__SEL_1 or + MUX_biasWorker_wci_wslv_respF_q_0$write_1__VAL_1 or + WILL_FIRE_RL_biasWorker_wci_wslv_respF_both or + MUX_biasWorker_wci_wslv_respF_q_0$write_1__VAL_2 or + WILL_FIRE_RL_biasWorker_wci_wslv_respF_decCtr or + biasWorker_wci_wslv_respF_q_1) + begin + case (1'b1) // synopsys parallel_case + MUX_biasWorker_wci_wslv_respF_q_0$write_1__SEL_1: + biasWorker_wci_wslv_respF_q_0$D_IN = + MUX_biasWorker_wci_wslv_respF_q_0$write_1__VAL_1; + WILL_FIRE_RL_biasWorker_wci_wslv_respF_both: + biasWorker_wci_wslv_respF_q_0$D_IN = + MUX_biasWorker_wci_wslv_respF_q_0$write_1__VAL_2; + WILL_FIRE_RL_biasWorker_wci_wslv_respF_decCtr: + biasWorker_wci_wslv_respF_q_0$D_IN = biasWorker_wci_wslv_respF_q_1; + default: biasWorker_wci_wslv_respF_q_0$D_IN = + 34'h2AAAAAAAA /* unspecified value */ ; + endcase + end + assign biasWorker_wci_wslv_respF_q_0$EN = + WILL_FIRE_RL_biasWorker_wci_wslv_respF_incCtr && + biasWorker_wci_wslv_respF_c_r == 2'd0 || + WILL_FIRE_RL_biasWorker_wci_wslv_respF_both || + WILL_FIRE_RL_biasWorker_wci_wslv_respF_decCtr ; + + // register biasWorker_wci_wslv_respF_q_1 + always@(WILL_FIRE_RL_biasWorker_wci_wslv_respF_both or + MUX_biasWorker_wci_wslv_respF_q_1$write_1__VAL_1 or + MUX_biasWorker_wci_wslv_respF_q_1$write_1__SEL_2 or + MUX_biasWorker_wci_wslv_respF_q_0$write_1__VAL_1 or + WILL_FIRE_RL_biasWorker_wci_wslv_respF_decCtr) + begin + case (1'b1) // synopsys parallel_case + WILL_FIRE_RL_biasWorker_wci_wslv_respF_both: + biasWorker_wci_wslv_respF_q_1$D_IN = + MUX_biasWorker_wci_wslv_respF_q_1$write_1__VAL_1; + MUX_biasWorker_wci_wslv_respF_q_1$write_1__SEL_2: + biasWorker_wci_wslv_respF_q_1$D_IN = + MUX_biasWorker_wci_wslv_respF_q_0$write_1__VAL_1; + WILL_FIRE_RL_biasWorker_wci_wslv_respF_decCtr: + biasWorker_wci_wslv_respF_q_1$D_IN = 34'h0AAAAAAAA; + default: biasWorker_wci_wslv_respF_q_1$D_IN = + 34'h2AAAAAAAA /* unspecified value */ ; + endcase + end + assign biasWorker_wci_wslv_respF_q_1$EN = + WILL_FIRE_RL_biasWorker_wci_wslv_respF_both || + WILL_FIRE_RL_biasWorker_wci_wslv_respF_incCtr && + biasWorker_wci_wslv_respF_c_r == 2'd1 || + WILL_FIRE_RL_biasWorker_wci_wslv_respF_decCtr ; + + // register biasWorker_wci_wslv_sFlagReg + assign biasWorker_wci_wslv_sFlagReg$D_IN = 1'b0 ; + assign biasWorker_wci_wslv_sFlagReg$EN = 1'd1 ; + + // register biasWorker_wci_wslv_sThreadBusy_d + assign biasWorker_wci_wslv_sThreadBusy_d$D_IN = 1'b0 ; + assign biasWorker_wci_wslv_sThreadBusy_d$EN = 1'd1 ; + + // register biasWorker_wsiM_burstKind + assign biasWorker_wsiM_burstKind$D_IN = + (biasWorker_wsiM_burstKind == 2'd0) ? + (biasWorker_wsiM_reqFifo_q_0[56] ? 2'd1 : 2'd2) : + 2'd0 ; + assign biasWorker_wsiM_burstKind$EN = + WILL_FIRE_RL_biasWorker_wsiM_reqFifo_deq && + biasWorker_wsiM_reqFifo_q_0[60:58] == 3'd1 && + (biasWorker_wsiM_burstKind == 2'd0 || + (biasWorker_wsiM_burstKind == 2'd1 || + biasWorker_wsiM_burstKind == 2'd2) && + biasWorker_wsiM_reqFifo_q_0[57]) ; + + // register biasWorker_wsiM_errorSticky + assign biasWorker_wsiM_errorSticky$D_IN = 1'b0 ; + assign biasWorker_wsiM_errorSticky$EN = 1'b0 ; + + // register biasWorker_wsiM_iMesgCount + assign biasWorker_wsiM_iMesgCount$D_IN = + biasWorker_wsiM_iMesgCount + 32'd1 ; + assign biasWorker_wsiM_iMesgCount$EN = + WILL_FIRE_RL_biasWorker_wsiM_reqFifo_deq && + biasWorker_wsiM_reqFifo_q_0[60:58] == 3'd1 && + biasWorker_wsiM_burstKind == 2'd2 && + biasWorker_wsiM_reqFifo_q_0[57] ; + + // register biasWorker_wsiM_isReset_isInReset + assign biasWorker_wsiM_isReset_isInReset$D_IN = 1'd0 ; + assign biasWorker_wsiM_isReset_isInReset$EN = + biasWorker_wsiM_isReset_isInReset ; + + // register biasWorker_wsiM_operateD + assign biasWorker_wsiM_operateD$D_IN = biasWorker_wci_wslv_cState == 3'd2 ; + assign biasWorker_wsiM_operateD$EN = 1'd1 ; + + // register biasWorker_wsiM_pMesgCount + assign biasWorker_wsiM_pMesgCount$D_IN = + biasWorker_wsiM_pMesgCount + 32'd1 ; + assign biasWorker_wsiM_pMesgCount$EN = + WILL_FIRE_RL_biasWorker_wsiM_reqFifo_deq && + biasWorker_wsiM_reqFifo_q_0[60:58] == 3'd1 && + biasWorker_wsiM_burstKind == 2'd1 && + biasWorker_wsiM_reqFifo_q_0[57] ; + + // register biasWorker_wsiM_peerIsReady + assign biasWorker_wsiM_peerIsReady$D_IN = + biasWorker_wsiM_peerIsReady_1$whas ; + assign biasWorker_wsiM_peerIsReady$EN = 1'd1 ; + + // register biasWorker_wsiM_reqFifo_c_r + assign biasWorker_wsiM_reqFifo_c_r$D_IN = + WILL_FIRE_RL_biasWorker_wsiM_reqFifo_incCtr ? + MUX_biasWorker_wsiM_reqFifo_c_r$write_1__VAL_1 : + MUX_biasWorker_wsiM_reqFifo_c_r$write_1__VAL_2 ; + assign biasWorker_wsiM_reqFifo_c_r$EN = + WILL_FIRE_RL_biasWorker_wsiM_reqFifo_incCtr || + WILL_FIRE_RL_biasWorker_wsiM_reqFifo_decCtr ; + + // register biasWorker_wsiM_reqFifo_q_0 + always@(MUX_biasWorker_wsiM_reqFifo_q_0$write_1__SEL_1 or + MUX_biasWorker_wsiM_reqFifo_q_0$write_1__VAL_1 or + WILL_FIRE_RL_biasWorker_wsiM_reqFifo_both or + MUX_biasWorker_wsiM_reqFifo_q_0$write_1__VAL_2 or + WILL_FIRE_RL_biasWorker_wsiM_reqFifo_decCtr or + biasWorker_wsiM_reqFifo_q_1) + begin + case (1'b1) // synopsys parallel_case + MUX_biasWorker_wsiM_reqFifo_q_0$write_1__SEL_1: + biasWorker_wsiM_reqFifo_q_0$D_IN = + MUX_biasWorker_wsiM_reqFifo_q_0$write_1__VAL_1; + WILL_FIRE_RL_biasWorker_wsiM_reqFifo_both: + biasWorker_wsiM_reqFifo_q_0$D_IN = + MUX_biasWorker_wsiM_reqFifo_q_0$write_1__VAL_2; + WILL_FIRE_RL_biasWorker_wsiM_reqFifo_decCtr: + biasWorker_wsiM_reqFifo_q_0$D_IN = biasWorker_wsiM_reqFifo_q_1; + default: biasWorker_wsiM_reqFifo_q_0$D_IN = + 61'h0AAAAAAAAAAAAAAA /* unspecified value */ ; + endcase + end + assign biasWorker_wsiM_reqFifo_q_0$EN = + WILL_FIRE_RL_biasWorker_wsiM_reqFifo_incCtr && + biasWorker_wsiM_reqFifo_c_r == 2'd0 || + WILL_FIRE_RL_biasWorker_wsiM_reqFifo_both || + WILL_FIRE_RL_biasWorker_wsiM_reqFifo_decCtr ; + + // register biasWorker_wsiM_reqFifo_q_1 + always@(MUX_biasWorker_wsiM_reqFifo_q_1$write_1__SEL_1 or + MUX_biasWorker_wsiM_reqFifo_q_0$write_1__VAL_1 or + WILL_FIRE_RL_biasWorker_wsiM_reqFifo_both or + MUX_biasWorker_wsiM_reqFifo_q_1$write_1__VAL_2 or + WILL_FIRE_RL_biasWorker_wsiM_reqFifo_decCtr) + begin + case (1'b1) // synopsys parallel_case + MUX_biasWorker_wsiM_reqFifo_q_1$write_1__SEL_1: + biasWorker_wsiM_reqFifo_q_1$D_IN = + MUX_biasWorker_wsiM_reqFifo_q_0$write_1__VAL_1; + WILL_FIRE_RL_biasWorker_wsiM_reqFifo_both: + biasWorker_wsiM_reqFifo_q_1$D_IN = + MUX_biasWorker_wsiM_reqFifo_q_1$write_1__VAL_2; + WILL_FIRE_RL_biasWorker_wsiM_reqFifo_decCtr: + biasWorker_wsiM_reqFifo_q_1$D_IN = 61'h00000AAAAAAAAA00; + default: biasWorker_wsiM_reqFifo_q_1$D_IN = + 61'h0AAAAAAAAAAAAAAA /* unspecified value */ ; + endcase + end + assign biasWorker_wsiM_reqFifo_q_1$EN = + WILL_FIRE_RL_biasWorker_wsiM_reqFifo_incCtr && + biasWorker_wsiM_reqFifo_c_r == 2'd1 || + WILL_FIRE_RL_biasWorker_wsiM_reqFifo_both || + WILL_FIRE_RL_biasWorker_wsiM_reqFifo_decCtr ; + + // register biasWorker_wsiM_sThreadBusy_d + assign biasWorker_wsiM_sThreadBusy_d$D_IN = + biasWorker_wsiM_sThreadBusy_pw$whas ; + assign biasWorker_wsiM_sThreadBusy_d$EN = 1'd1 ; + + // register biasWorker_wsiM_statusR + assign biasWorker_wsiM_statusR$D_IN = + { biasWorker_wsiM_isReset_isInReset, + !biasWorker_wsiM_peerIsReady, + !biasWorker_wsiM_operateD, + biasWorker_wsiM_errorSticky, + biasWorker_wsiM_burstKind != 2'd0, + biasWorker_wsiM_sThreadBusy_d, + 1'd0, + biasWorker_wsiM_trafficSticky } ; + assign biasWorker_wsiM_statusR$EN = 1'd1 ; + + // register biasWorker_wsiM_tBusyCount + assign biasWorker_wsiM_tBusyCount$D_IN = + biasWorker_wsiM_tBusyCount + 32'd1 ; + assign biasWorker_wsiM_tBusyCount$EN = + biasWorker_wsiM_operateD && biasWorker_wsiM_peerIsReady && + biasWorker_wsiM_sThreadBusy_d ; + + // register biasWorker_wsiM_trafficSticky + assign biasWorker_wsiM_trafficSticky$D_IN = 1'd1 ; + assign biasWorker_wsiM_trafficSticky$EN = + WILL_FIRE_RL_biasWorker_wsiM_reqFifo_deq && + biasWorker_wsiM_reqFifo_q_0[60:58] == 3'd1 ; + + // register biasWorker_wsiS_burstKind + assign biasWorker_wsiS_burstKind$D_IN = + (biasWorker_wsiS_burstKind == 2'd0) ? + (biasWorker_wsiS_wsiReq$wget[56] ? 2'd1 : 2'd2) : + 2'd0 ; + assign biasWorker_wsiS_burstKind$EN = + WILL_FIRE_RL_biasWorker_wsiS_reqFifo_enq && + (biasWorker_wsiS_burstKind == 2'd0 || + (biasWorker_wsiS_burstKind == 2'd1 || + biasWorker_wsiS_burstKind == 2'd2) && + biasWorker_wsiS_wsiReq$wget[57]) ; + + // register biasWorker_wsiS_errorSticky + assign biasWorker_wsiS_errorSticky$D_IN = 1'b0 ; + assign biasWorker_wsiS_errorSticky$EN = 1'b0 ; + + // register biasWorker_wsiS_iMesgCount + assign biasWorker_wsiS_iMesgCount$D_IN = + biasWorker_wsiS_iMesgCount + 32'd1 ; + assign biasWorker_wsiS_iMesgCount$EN = + WILL_FIRE_RL_biasWorker_wsiS_reqFifo_enq && + biasWorker_wsiS_burstKind == 2'd2 && + biasWorker_wsiS_wsiReq$wget[57] ; + + // register biasWorker_wsiS_isReset_isInReset + assign biasWorker_wsiS_isReset_isInReset$D_IN = 1'd0 ; + assign biasWorker_wsiS_isReset_isInReset$EN = + biasWorker_wsiS_isReset_isInReset ; + + // register biasWorker_wsiS_mesgWordLength + assign biasWorker_wsiS_mesgWordLength$D_IN = biasWorker_wsiS_wordCount ; + assign biasWorker_wsiS_mesgWordLength$EN = + WILL_FIRE_RL_biasWorker_wsiS_reqFifo_enq && + biasWorker_wsiS_wsiReq$wget[57] ; + + // register biasWorker_wsiS_operateD + assign biasWorker_wsiS_operateD$D_IN = biasWorker_wci_wslv_cState == 3'd2 ; + assign biasWorker_wsiS_operateD$EN = 1'd1 ; + + // register biasWorker_wsiS_pMesgCount + assign biasWorker_wsiS_pMesgCount$D_IN = + biasWorker_wsiS_pMesgCount + 32'd1 ; + assign biasWorker_wsiS_pMesgCount$EN = + WILL_FIRE_RL_biasWorker_wsiS_reqFifo_enq && + biasWorker_wsiS_burstKind == 2'd1 && + biasWorker_wsiS_wsiReq$wget[57] ; + + // register biasWorker_wsiS_peerIsReady + assign biasWorker_wsiS_peerIsReady$D_IN = + biasWorker_wsiS_peerIsReady_1$whas ; + assign biasWorker_wsiS_peerIsReady$EN = 1'd1 ; + + // register biasWorker_wsiS_reqFifo_countReg + assign biasWorker_wsiS_reqFifo_countReg$D_IN = + WILL_FIRE_RL_biasWorker_wsiS_reqFifo_enq ? + biasWorker_wsiS_reqFifo_countReg + 2'd1 : + biasWorker_wsiS_reqFifo_countReg - 2'd1 ; + assign biasWorker_wsiS_reqFifo_countReg$EN = + WILL_FIRE_RL_biasWorker_wsiS_reqFifo_enq != + MUX_biasWorker_wsiS_reqFifo_levelsValid$write_1__SEL_3 ; + + // register biasWorker_wsiS_reqFifo_levelsValid + assign biasWorker_wsiS_reqFifo_levelsValid$D_IN = + WILL_FIRE_RL_biasWorker_wsiS_reqFifo_reset ; + assign biasWorker_wsiS_reqFifo_levelsValid$EN = + biasWorker_wsiM_reqFifo_c_r != 2'd2 && + biasWorker_wsiS_reqFifo$EMPTY_N && + biasWorker_wci_wslv_cState == 3'd2 || + WILL_FIRE_RL_biasWorker_wsiS_reqFifo_enq || + WILL_FIRE_RL_biasWorker_wsiS_reqFifo_reset ; + + // register biasWorker_wsiS_statusR + assign biasWorker_wsiS_statusR$D_IN = + { biasWorker_wsiS_isReset_isInReset, + !biasWorker_wsiS_peerIsReady, + !biasWorker_wsiS_operateD, + biasWorker_wsiS_errorSticky, + biasWorker_wsiS_burstKind != 2'd0, + !biasWorker_wsiS_sThreadBusy_dw$whas || + biasWorker_wsiS_sThreadBusy_dw$wget, + 1'd0, + biasWorker_wsiS_trafficSticky } ; + assign biasWorker_wsiS_statusR$EN = 1'd1 ; + + // register biasWorker_wsiS_tBusyCount + assign biasWorker_wsiS_tBusyCount$D_IN = + biasWorker_wsiS_tBusyCount + 32'd1 ; + assign biasWorker_wsiS_tBusyCount$EN = + biasWorker_wsiS_operateD && biasWorker_wsiS_peerIsReady && + (!biasWorker_wsiS_sThreadBusy_dw$whas || + biasWorker_wsiS_sThreadBusy_dw$wget) ; + + // register biasWorker_wsiS_trafficSticky + assign biasWorker_wsiS_trafficSticky$D_IN = 1'd1 ; + assign biasWorker_wsiS_trafficSticky$EN = + WILL_FIRE_RL_biasWorker_wsiS_reqFifo_enq ; + + // register biasWorker_wsiS_wordCount + assign biasWorker_wsiS_wordCount$D_IN = + biasWorker_wsiS_wsiReq$wget[57] ? + 12'd1 : + biasWorker_wsiS_wordCount + 12'd1 ; + assign biasWorker_wsiS_wordCount$EN = + WILL_FIRE_RL_biasWorker_wsiS_reqFifo_enq ; + + // register dstDataOut + assign dstDataOut$D_IN = dstDataOut + 32'd1 ; + assign dstDataOut$EN = MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 ; + + // register dstMesgCount + assign dstMesgCount$D_IN = dstMesgCount + 16'd1 ; + assign dstMesgCount$EN = + MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 && + dstUnrollCnt == 16'd1 ; + + // register dstUnrollCnt + assign dstUnrollCnt$D_IN = + (wciSeqFsm_state_mkFSMstate == 5'd18) ? + 16'd16 : + MUX_dstUnrollCnt$write_1__VAL_2 ; + assign dstUnrollCnt$EN = + MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 || + wciSeqFsm_state_mkFSMstate == 5'd18 ; + + // register enWsiChecker + assign enWsiChecker$D_IN = 1'd1 ; + assign enWsiChecker$EN = wciSeqFsm_state_mkFSMstate == 5'd19 ; + + // register enWsiSource + assign enWsiSource$D_IN = 1'd1 ; + assign enWsiSource$EN = wciSeqFsm_state_mkFSMstate == 5'd21 ; + + // register goodDataCnt + assign goodDataCnt$D_IN = goodDataCnt + 32'd1 ; + assign goodDataCnt$EN = + MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 && + wsiS_reqFifo_first__99_BITS_43_TO_12_00_EQ_dst_ETC___d943 ; + + // register goodMesgCnt + assign goodMesgCnt$D_IN = goodMesgCnt + 32'd1 ; + assign goodMesgCnt$EN = + MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 && + dstUnrollCnt == 16'd1 && + wsiS_reqFifo_first__99_BITS_43_TO_12_00_EQ_dst_ETC___d943 && + !mesgHadError ; + + // register mesgHadError + assign mesgHadError$D_IN = + dstUnrollCnt != 16'd1 && + !wsiS_reqFifo_first__99_BITS_43_TO_12_00_EQ_dst_ETC___d943 ; + assign mesgHadError$EN = MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 ; + + // register simCycle + assign simCycle$D_IN = simCycle + 16'd1 ; + assign simCycle$EN = 1'd1 ; + + // register srcDataOut + assign srcDataOut$D_IN = srcDataOut + 32'd1 ; + assign srcDataOut$EN = wsiM_reqFifo_enqueueing$whas ; + + // register srcMesgCount + assign srcMesgCount$D_IN = srcMesgCount + 16'd1 ; + assign srcMesgCount$EN = + wsiM_reqFifo_enqueueing$whas && srcUnrollCnt == 16'd1 ; + + // register srcUnrollCnt + assign srcUnrollCnt$D_IN = + (wciSeqFsm_state_mkFSMstate == 5'd20) ? + 16'd16 : + MUX_srcUnrollCnt$write_1__VAL_2 ; + assign srcUnrollCnt$EN = + wsiM_reqFifo_enqueueing$whas || + wciSeqFsm_state_mkFSMstate == 5'd20 ; + + // register testOperating + assign testOperating$D_IN = 1'd1 ; + assign testOperating$EN = wciSeqFsm_state_mkFSMstate == 5'd17 ; + + // register wciSeqFsm_start_reg + assign wciSeqFsm_start_reg$D_IN = !WILL_FIRE_RL_wciSeqFsm_fsm_start ; + assign wciSeqFsm_start_reg$EN = + WILL_FIRE_RL_wciSeqFsm_fsm_start || + wciSeqOnce_onceReady && + wciSeqFsm_abort_whas__63_AND_wciSeqFsm_abort_w_ETC___d875 && + !wciSeqFsm_start_reg ; + + // register wciSeqFsm_start_reg_1 + assign wciSeqFsm_start_reg_1$D_IN = wciSeqFsm_start_wire$whas ; + assign wciSeqFsm_start_reg_1$EN = 1'd1 ; + + // register wciSeqFsm_state_can_overlap + assign wciSeqFsm_state_can_overlap$D_IN = + wciSeqFsm_state_set_pw$whas || wciSeqFsm_state_can_overlap ; + assign wciSeqFsm_state_can_overlap$EN = 1'd1 ; + + // register wciSeqFsm_state_fired + assign wciSeqFsm_state_fired$D_IN = wciSeqFsm_state_set_pw$whas ; + assign wciSeqFsm_state_fired$EN = 1'd1 ; + + // register wciSeqFsm_state_mkFSMstate + always@(WILL_FIRE_RL_wciSeqFsm_idle_l49c3 or + WILL_FIRE_RL_wciSeqFsm_action_l50c5 or + WILL_FIRE_RL_wciSeqFsm_action_l51c10 or + wciSeqFsm_state_mkFSMstate or + WILL_FIRE_RL_wciSeqFsm_action_l54c8 or + WILL_FIRE_RL_wciSeqFsm_action_l55c5 or + WILL_FIRE_RL_wciSeqFsm_action_l58c8 or + WILL_FIRE_RL_wciSeqFsm_action_l59c5 or + WILL_FIRE_RL_wciSeqFsm_action_l62c8 or + WILL_FIRE_RL_wciSeqFsm_action_l63c5 or + WILL_FIRE_RL_wciSeqFsm_action_l66c8 or + WILL_FIRE_RL_wciSeqFsm_action_l67c5 or + WILL_FIRE_RL_wciSeqFsm_action_l70c8 or + WILL_FIRE_RL_wciSeqFsm_action_l71c5) + begin + case (1'b1) // synopsys parallel_case + WILL_FIRE_RL_wciSeqFsm_idle_l49c3: + wciSeqFsm_state_mkFSMstate$D_IN = 5'd0; + WILL_FIRE_RL_wciSeqFsm_action_l50c5: + wciSeqFsm_state_mkFSMstate$D_IN = 5'd1; + WILL_FIRE_RL_wciSeqFsm_action_l51c10: + wciSeqFsm_state_mkFSMstate$D_IN = 5'd2; + wciSeqFsm_state_mkFSMstate == 5'd2: + wciSeqFsm_state_mkFSMstate$D_IN = 5'd3; + WILL_FIRE_RL_wciSeqFsm_action_l54c8: + wciSeqFsm_state_mkFSMstate$D_IN = 5'd4; + WILL_FIRE_RL_wciSeqFsm_action_l55c5: + wciSeqFsm_state_mkFSMstate$D_IN = 5'd5; + wciSeqFsm_state_mkFSMstate == 5'd5: + wciSeqFsm_state_mkFSMstate$D_IN = 5'd6; + WILL_FIRE_RL_wciSeqFsm_action_l58c8: + wciSeqFsm_state_mkFSMstate$D_IN = 5'd7; + WILL_FIRE_RL_wciSeqFsm_action_l59c5: + wciSeqFsm_state_mkFSMstate$D_IN = 5'd8; + wciSeqFsm_state_mkFSMstate == 5'd8: + wciSeqFsm_state_mkFSMstate$D_IN = 5'd9; + WILL_FIRE_RL_wciSeqFsm_action_l62c8: + wciSeqFsm_state_mkFSMstate$D_IN = 5'd10; + WILL_FIRE_RL_wciSeqFsm_action_l63c5: + wciSeqFsm_state_mkFSMstate$D_IN = 5'd11; + wciSeqFsm_state_mkFSMstate == 5'd11: + wciSeqFsm_state_mkFSMstate$D_IN = 5'd12; + WILL_FIRE_RL_wciSeqFsm_action_l66c8: + wciSeqFsm_state_mkFSMstate$D_IN = 5'd13; + WILL_FIRE_RL_wciSeqFsm_action_l67c5: + wciSeqFsm_state_mkFSMstate$D_IN = 5'd14; + wciSeqFsm_state_mkFSMstate == 5'd14: + wciSeqFsm_state_mkFSMstate$D_IN = 5'd15; + WILL_FIRE_RL_wciSeqFsm_action_l70c8: + wciSeqFsm_state_mkFSMstate$D_IN = 5'd16; + WILL_FIRE_RL_wciSeqFsm_action_l71c5: + wciSeqFsm_state_mkFSMstate$D_IN = 5'd17; + wciSeqFsm_state_mkFSMstate == 5'd17: + wciSeqFsm_state_mkFSMstate$D_IN = 5'd18; + wciSeqFsm_state_mkFSMstate == 5'd18: + wciSeqFsm_state_mkFSMstate$D_IN = 5'd19; + wciSeqFsm_state_mkFSMstate == 5'd19: + wciSeqFsm_state_mkFSMstate$D_IN = 5'd20; + wciSeqFsm_state_mkFSMstate == 5'd20: + wciSeqFsm_state_mkFSMstate$D_IN = 5'd21; + wciSeqFsm_state_mkFSMstate == 5'd21: + wciSeqFsm_state_mkFSMstate$D_IN = 5'd22; + default: wciSeqFsm_state_mkFSMstate$D_IN = + 5'b01010 /* unspecified value */ ; + endcase + end + assign wciSeqFsm_state_mkFSMstate$EN = + WILL_FIRE_RL_wciSeqFsm_idle_l49c3 || + WILL_FIRE_RL_wciSeqFsm_action_l50c5 || + WILL_FIRE_RL_wciSeqFsm_action_l51c10 || + wciSeqFsm_state_mkFSMstate == 5'd2 || + WILL_FIRE_RL_wciSeqFsm_action_l54c8 || + WILL_FIRE_RL_wciSeqFsm_action_l55c5 || + wciSeqFsm_state_mkFSMstate == 5'd5 || + WILL_FIRE_RL_wciSeqFsm_action_l58c8 || + WILL_FIRE_RL_wciSeqFsm_action_l59c5 || + wciSeqFsm_state_mkFSMstate == 5'd8 || + WILL_FIRE_RL_wciSeqFsm_action_l62c8 || + WILL_FIRE_RL_wciSeqFsm_action_l63c5 || + wciSeqFsm_state_mkFSMstate == 5'd11 || + WILL_FIRE_RL_wciSeqFsm_action_l66c8 || + WILL_FIRE_RL_wciSeqFsm_action_l67c5 || + wciSeqFsm_state_mkFSMstate == 5'd14 || + WILL_FIRE_RL_wciSeqFsm_action_l70c8 || + WILL_FIRE_RL_wciSeqFsm_action_l71c5 || + wciSeqFsm_state_mkFSMstate == 5'd17 || + wciSeqFsm_state_mkFSMstate == 5'd18 || + wciSeqFsm_state_mkFSMstate == 5'd19 || + wciSeqFsm_state_mkFSMstate == 5'd20 || + wciSeqFsm_state_mkFSMstate == 5'd21 ; + + // register wciSeqOnce_onceReady + assign wciSeqOnce_onceReady$D_IN = 1'd0 ; + assign wciSeqOnce_onceReady$EN = MUX_wciSeqFsm_start_reg$write_1__SEL_2 ; + + // register wci_busy + assign wci_busy$D_IN = MUX_wci_busy$write_1__SEL_1 ; + assign wci_busy$EN = + _dand1wci_busy$EN_write || + WILL_FIRE_RL_wci_wrkBusy && + (!wci_respTimr_7_ULT_1_SL_wci_wTimeout_8_9___d969 || + biasWorker_wci_wslv_respF_q_0[33:32] != 2'd0) ; + + // register wci_lastConfigAddr + assign wci_lastConfigAddr$D_IN = 33'h100000004 ; + assign wci_lastConfigAddr$EN = + _dor1wci_lastConfigAddr$EN_write && wci_wReset_n ; + + // register wci_lastConfigBE + assign wci_lastConfigBE$D_IN = + MUX_wci_lastConfigBE$write_1__SEL_1 ? 5'd26 : 5'd31 ; + assign wci_lastConfigBE$EN = + WILL_FIRE_RL_wciSeqFsm_action_l66c8 && wci_wReset_n || + WILL_FIRE_RL_wciSeqFsm_action_l62c8 && wci_wReset_n ; + + // register wci_lastControlOp + assign wci_lastControlOp$D_IN = + MUX_wci_lastControlOp$write_1__SEL_1 ? 4'd8 : 4'd9 ; + assign wci_lastControlOp$EN = + WILL_FIRE_RL_wciSeqFsm_action_l58c8 && wci_wReset_n || + WILL_FIRE_RL_wciSeqFsm_action_l70c8 && wci_wReset_n ; + + // register wci_lastOpWrite + assign wci_lastOpWrite$D_IN = + MUX_wci_lastConfigBE$write_1__SEL_1 ? 2'd2 : 2'd3 ; + assign wci_lastOpWrite$EN = + WILL_FIRE_RL_wciSeqFsm_action_l66c8 && wci_wReset_n || + WILL_FIRE_RL_wciSeqFsm_action_l62c8 && wci_wReset_n ; + + // register wci_mFlagReg + assign wci_mFlagReg$D_IN = 2'h0 ; + assign wci_mFlagReg$EN = 1'b0 ; + + // register wci_pageWindow + assign wci_pageWindow$D_IN = 12'h0 ; + assign wci_pageWindow$EN = 1'b0 ; + + // register wci_reqERR + always@(wci_reqPend or wci_reqERR) + begin + case (wci_reqPend) + 2'd1: wci_reqERR$D_IN = { 1'd1, wci_reqERR[1:0] }; + 2'd2: wci_reqERR$D_IN = { wci_reqERR[2], 1'd1, wci_reqERR[0] }; + default: wci_reqERR$D_IN = { wci_reqERR[2:1], 1'd1 }; + endcase + end + assign wci_reqERR$EN = + WILL_FIRE_RL_wci_wrkBusy && + biasWorker_wci_wslv_respF_q_0[33:32] == 2'd3 && + (wci_reqPend == 2'd1 || wci_reqPend == 2'd2 || + wci_reqPend == 2'd3) ; + + // register wci_reqFAIL + always@(wci_reqPend or wci_reqFAIL) + begin + case (wci_reqPend) + 2'd1: wci_reqFAIL$D_IN = { 1'd1, wci_reqFAIL[1:0] }; + 2'd2: wci_reqFAIL$D_IN = { wci_reqFAIL[2], 1'd1, wci_reqFAIL[0] }; + default: wci_reqFAIL$D_IN = { wci_reqFAIL[2:1], 1'd1 }; + endcase + end + assign wci_reqFAIL$EN = + WILL_FIRE_RL_wci_wrkBusy && + biasWorker_wci_wslv_respF_q_0[33:32] == 2'd2 && + (wci_reqPend == 2'd1 || wci_reqPend == 2'd2 || + wci_reqPend == 2'd3) ; + + // register wci_reqF_c_r + assign wci_reqF_c_r$D_IN = + WILL_FIRE_RL_wci_reqF_incCtr ? + MUX_wci_reqF_c_r$write_1__VAL_1 : + MUX_wci_reqF_c_r$write_1__VAL_2 ; + assign wci_reqF_c_r$EN = + WILL_FIRE_RL_wci_reqF_incCtr || WILL_FIRE_RL_wci_reqF_decCtr ; + + // register wci_reqF_q_0 + always@(WILL_FIRE_RL_wci_reqF_both or + MUX_wci_reqF_q_0$write_1__VAL_1 or + MUX_wci_reqF_q_0$write_1__SEL_2 or + MUX_wci_reqF_q_0$write_1__VAL_2 or WILL_FIRE_RL_wci_reqF_decCtr) + begin + case (1'b1) // synopsys parallel_case + WILL_FIRE_RL_wci_reqF_both: + wci_reqF_q_0$D_IN = MUX_wci_reqF_q_0$write_1__VAL_1; + MUX_wci_reqF_q_0$write_1__SEL_2: + wci_reqF_q_0$D_IN = MUX_wci_reqF_q_0$write_1__VAL_2; + WILL_FIRE_RL_wci_reqF_decCtr: + wci_reqF_q_0$D_IN = 72'h0000000000AAAAAAAA; + default: wci_reqF_q_0$D_IN = + 72'hAAAAAAAAAAAAAAAAAA /* unspecified value */ ; + endcase + end + assign wci_reqF_q_0$EN = + WILL_FIRE_RL_wci_reqF_both || + WILL_FIRE_RL_wci_reqF_incCtr && !wci_reqF_c_r || + WILL_FIRE_RL_wci_reqF_decCtr ; + + // register wci_reqPend + always@(MUX_wci_lastConfigBE$write_1__SEL_2 or + MUX_wci_lastConfigBE$write_1__SEL_1 or + MUX_wci_reqPend$write_1__SEL_3 or MUX_wci_reqPend$write_1__SEL_4) + begin + case (1'b1) // synopsys parallel_case + MUX_wci_lastConfigBE$write_1__SEL_2: wci_reqPend$D_IN = 2'd1; + MUX_wci_lastConfigBE$write_1__SEL_1: wci_reqPend$D_IN = 2'd2; + MUX_wci_reqPend$write_1__SEL_3: wci_reqPend$D_IN = 2'd3; + MUX_wci_reqPend$write_1__SEL_4: wci_reqPend$D_IN = 2'd0; + default: wci_reqPend$D_IN = 2'b10 /* unspecified value */ ; + endcase + end + assign wci_reqPend$EN = + WILL_FIRE_RL_wciSeqFsm_action_l62c8 && wci_wReset_n || + WILL_FIRE_RL_wciSeqFsm_action_l66c8 && wci_wReset_n || + (WILL_FIRE_RL_wciSeqFsm_action_l70c8 || + WILL_FIRE_RL_wciSeqFsm_action_l58c8) && + wci_wReset_n || + WILL_FIRE_RL_wci_wrkBusy && + biasWorker_wci_wslv_respF_q_0[33:32] != 2'd0 ; + + // register wci_reqTO + always@(wci_reqPend or wci_reqTO) + begin + case (wci_reqPend) + 2'd1: wci_reqTO$D_IN = { 1'd1, wci_reqTO[1:0] }; + 2'd2: wci_reqTO$D_IN = { wci_reqTO[2], 1'd1, wci_reqTO[0] }; + default: wci_reqTO$D_IN = { wci_reqTO[2:1], 1'd1 }; + endcase + end + assign wci_reqTO$EN = + WILL_FIRE_RL_wci_wrkBusy && + biasWorker_wci_wslv_respF_q_0[33:32] == 2'd0 && + !wci_respTimr_7_ULT_1_SL_wci_wTimeout_8_9___d969 && + (wci_reqPend == 2'd1 || wci_reqPend == 2'd2 || + wci_reqPend == 2'd3) ; + + // register wci_respTimr + assign wci_respTimr$D_IN = + wci_reqF_c_r ? 32'd0 : MUX_wci_respTimr$write_1__VAL_2 ; + assign wci_respTimr$EN = WILL_FIRE_RL_wci_wrkBusy || wci_reqF_c_r ; + + // register wci_respTimrAct + assign wci_respTimrAct$D_IN = wci_reqF_c_r ; + assign wci_respTimrAct$EN = + WILL_FIRE_RL_wci_wrkBusy && + (!wci_respTimr_7_ULT_1_SL_wci_wTimeout_8_9___d969 || + biasWorker_wci_wslv_respF_q_0[33:32] != 2'd0) || + wci_reqF_c_r ; + + // register wci_sThreadBusy_d + assign wci_sThreadBusy_d$D_IN = wci_sThreadBusy_pw$whas ; + assign wci_sThreadBusy_d$EN = 1'd1 ; + + // register wci_sfCap + assign wci_sfCap$D_IN = wci_sfCapSet ; + assign wci_sfCap$EN = wci_sfCapSet || wci_sfCapClear ; + + // register wci_sfCapClear + assign wci_sfCapClear$D_IN = 1'b0 ; + assign wci_sfCapClear$EN = 1'd1 ; + + // register wci_sfCapSet + assign wci_sfCapSet$D_IN = biasWorker_wci_wslv_sFlagReg ; + assign wci_sfCapSet$EN = 1'd1 ; + + // register wci_slvPresent + assign wci_slvPresent$D_IN = 1'd1 ; + assign wci_slvPresent$EN = 1'd1 ; + + // register wci_wReset_n + assign wci_wReset_n$D_IN = 1'd1 ; + assign wci_wReset_n$EN = WILL_FIRE_RL_wciSeqFsm_action_l54c8 ; + + // register wci_wStatus + assign wci_wStatus$D_IN = + { 4'b0, + !wci_lastOpWrite[1] || wci_lastOpWrite[0], + IF_wci_lastControlOp_22_BIT_3_23_THEN_wci_last_ETC___d137 } ; + assign wci_wStatus$EN = 1'd1 ; + + // register wci_wTimeout + assign wci_wTimeout$D_IN = 5'd4 ; + assign wci_wTimeout$EN = WILL_FIRE_RL_wciSeqFsm_action_l54c8 ; + + // register wsiM_burstKind + assign wsiM_burstKind$D_IN = + (wsiM_burstKind == 2'd0) ? + (wsiM_reqFifo_q_0[56] ? 2'd1 : 2'd2) : + 2'd0 ; + assign wsiM_burstKind$EN = + WILL_FIRE_RL_wsiM_reqFifo_deq && + wsiM_reqFifo_q_0[60:58] == 3'd1 && + (wsiM_burstKind == 2'd0 || + (wsiM_burstKind == 2'd1 || wsiM_burstKind == 2'd2) && + wsiM_reqFifo_q_0[57]) ; + + // register wsiM_errorSticky + assign wsiM_errorSticky$D_IN = 1'b0 ; + assign wsiM_errorSticky$EN = 1'b0 ; + + // register wsiM_iMesgCount + assign wsiM_iMesgCount$D_IN = wsiM_iMesgCount + 32'd1 ; + assign wsiM_iMesgCount$EN = + WILL_FIRE_RL_wsiM_reqFifo_deq && + wsiM_reqFifo_q_0[60:58] == 3'd1 && + wsiM_burstKind == 2'd2 && + wsiM_reqFifo_q_0[57] ; + + // register wsiM_isReset_isInReset + assign wsiM_isReset_isInReset$D_IN = 1'd0 ; + assign wsiM_isReset_isInReset$EN = wsiM_isReset_isInReset ; + + // register wsiM_operateD + assign wsiM_operateD$D_IN = testOperating ; + assign wsiM_operateD$EN = 1'd1 ; + + // register wsiM_pMesgCount + assign wsiM_pMesgCount$D_IN = wsiM_pMesgCount + 32'd1 ; + assign wsiM_pMesgCount$EN = + WILL_FIRE_RL_wsiM_reqFifo_deq && + wsiM_reqFifo_q_0[60:58] == 3'd1 && + wsiM_burstKind == 2'd1 && + wsiM_reqFifo_q_0[57] ; + + // register wsiM_peerIsReady + assign wsiM_peerIsReady$D_IN = wsiM_peerIsReady_1$whas ; + assign wsiM_peerIsReady$EN = 1'd1 ; + + // register wsiM_reqFifo_c_r + assign wsiM_reqFifo_c_r$D_IN = + WILL_FIRE_RL_wsiM_reqFifo_incCtr ? + MUX_wsiM_reqFifo_c_r$write_1__VAL_1 : + MUX_wsiM_reqFifo_c_r$write_1__VAL_2 ; + assign wsiM_reqFifo_c_r$EN = + WILL_FIRE_RL_wsiM_reqFifo_incCtr || + WILL_FIRE_RL_wsiM_reqFifo_decCtr ; + + // register wsiM_reqFifo_q_0 + always@(WILL_FIRE_RL_wsiM_reqFifo_both or + MUX_wsiM_reqFifo_q_0$write_1__VAL_1 or + MUX_wsiM_reqFifo_q_0$write_1__SEL_2 or + MUX_wsiM_reqFifo_q_0$write_1__VAL_2 or + WILL_FIRE_RL_wsiM_reqFifo_decCtr or wsiM_reqFifo_q_1) + begin + case (1'b1) // synopsys parallel_case + WILL_FIRE_RL_wsiM_reqFifo_both: + wsiM_reqFifo_q_0$D_IN = MUX_wsiM_reqFifo_q_0$write_1__VAL_1; + MUX_wsiM_reqFifo_q_0$write_1__SEL_2: + wsiM_reqFifo_q_0$D_IN = MUX_wsiM_reqFifo_q_0$write_1__VAL_2; + WILL_FIRE_RL_wsiM_reqFifo_decCtr: + wsiM_reqFifo_q_0$D_IN = wsiM_reqFifo_q_1; + default: wsiM_reqFifo_q_0$D_IN = + 61'h0AAAAAAAAAAAAAAA /* unspecified value */ ; + endcase + end + assign wsiM_reqFifo_q_0$EN = + WILL_FIRE_RL_wsiM_reqFifo_both || + WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_c_r == 2'd0 || + WILL_FIRE_RL_wsiM_reqFifo_decCtr ; + + // register wsiM_reqFifo_q_1 + always@(WILL_FIRE_RL_wsiM_reqFifo_both or + MUX_wsiM_reqFifo_q_1$write_1__VAL_1 or + MUX_wsiM_reqFifo_q_1$write_1__SEL_2 or + MUX_wsiM_reqFifo_q_0$write_1__VAL_2 or + WILL_FIRE_RL_wsiM_reqFifo_decCtr) + begin + case (1'b1) // synopsys parallel_case + WILL_FIRE_RL_wsiM_reqFifo_both: + wsiM_reqFifo_q_1$D_IN = MUX_wsiM_reqFifo_q_1$write_1__VAL_1; + MUX_wsiM_reqFifo_q_1$write_1__SEL_2: + wsiM_reqFifo_q_1$D_IN = MUX_wsiM_reqFifo_q_0$write_1__VAL_2; + WILL_FIRE_RL_wsiM_reqFifo_decCtr: + wsiM_reqFifo_q_1$D_IN = 61'h00000AAAAAAAAA00; + default: wsiM_reqFifo_q_1$D_IN = + 61'h0AAAAAAAAAAAAAAA /* unspecified value */ ; + endcase + end + assign wsiM_reqFifo_q_1$EN = + WILL_FIRE_RL_wsiM_reqFifo_both || + WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_c_r == 2'd1 || + WILL_FIRE_RL_wsiM_reqFifo_decCtr ; + + // register wsiM_sThreadBusy_d + assign wsiM_sThreadBusy_d$D_IN = wsiM_sThreadBusy_pw$whas ; + assign wsiM_sThreadBusy_d$EN = 1'd1 ; + + // register wsiM_statusR + assign wsiM_statusR$D_IN = + { wsiM_isReset_isInReset, + !wsiM_peerIsReady, + !wsiM_operateD, + wsiM_errorSticky, + wsiM_burstKind != 2'd0, + wsiM_sThreadBusy_d, + 1'd0, + wsiM_trafficSticky } ; + assign wsiM_statusR$EN = 1'd1 ; + + // register wsiM_tBusyCount + assign wsiM_tBusyCount$D_IN = wsiM_tBusyCount + 32'd1 ; + assign wsiM_tBusyCount$EN = + wsiM_operateD && wsiM_peerIsReady && wsiM_sThreadBusy_d ; + + // register wsiM_trafficSticky + assign wsiM_trafficSticky$D_IN = 1'd1 ; + assign wsiM_trafficSticky$EN = + WILL_FIRE_RL_wsiM_reqFifo_deq && + wsiM_reqFifo_q_0[60:58] == 3'd1 ; + + // register wsiS_burstKind + assign wsiS_burstKind$D_IN = + (wsiS_burstKind == 2'd0) ? + (wsiS_wsiReq$wget[56] ? 2'd1 : 2'd2) : + 2'd0 ; + assign wsiS_burstKind$EN = + WILL_FIRE_RL_wsiS_reqFifo_enq && + (wsiS_burstKind == 2'd0 || + (wsiS_burstKind == 2'd1 || wsiS_burstKind == 2'd2) && + wsiS_wsiReq$wget[57]) ; + + // register wsiS_errorSticky + assign wsiS_errorSticky$D_IN = 1'b0 ; + assign wsiS_errorSticky$EN = 1'b0 ; + + // register wsiS_iMesgCount + assign wsiS_iMesgCount$D_IN = wsiS_iMesgCount + 32'd1 ; + assign wsiS_iMesgCount$EN = + WILL_FIRE_RL_wsiS_reqFifo_enq && wsiS_burstKind == 2'd2 && + wsiS_wsiReq$wget[57] ; + + // register wsiS_isReset_isInReset + assign wsiS_isReset_isInReset$D_IN = 1'd0 ; + assign wsiS_isReset_isInReset$EN = wsiS_isReset_isInReset ; + + // register wsiS_mesgWordLength + assign wsiS_mesgWordLength$D_IN = wsiS_wordCount ; + assign wsiS_mesgWordLength$EN = + WILL_FIRE_RL_wsiS_reqFifo_enq && wsiS_wsiReq$wget[57] ; + + // register wsiS_operateD + assign wsiS_operateD$D_IN = testOperating ; + assign wsiS_operateD$EN = 1'd1 ; + + // register wsiS_pMesgCount + assign wsiS_pMesgCount$D_IN = wsiS_pMesgCount + 32'd1 ; + assign wsiS_pMesgCount$EN = + WILL_FIRE_RL_wsiS_reqFifo_enq && wsiS_burstKind == 2'd1 && + wsiS_wsiReq$wget[57] ; + + // register wsiS_peerIsReady + assign wsiS_peerIsReady$D_IN = wsiS_peerIsReady_1$whas ; + assign wsiS_peerIsReady$EN = 1'd1 ; + + // register wsiS_reqFifo_countReg + assign wsiS_reqFifo_countReg$D_IN = + WILL_FIRE_RL_wsiS_reqFifo_enq ? + wsiS_reqFifo_countReg + 2'd1 : + wsiS_reqFifo_countReg - 2'd1 ; + assign wsiS_reqFifo_countReg$EN = + WILL_FIRE_RL_wsiS_reqFifo_enq != + MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 ; + + // register wsiS_reqFifo_levelsValid + assign wsiS_reqFifo_levelsValid$D_IN = WILL_FIRE_RL_wsiS_reqFifo_reset ; + assign wsiS_reqFifo_levelsValid$EN = + MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 || + WILL_FIRE_RL_wsiS_reqFifo_enq || + WILL_FIRE_RL_wsiS_reqFifo_reset ; + + // register wsiS_statusR + assign wsiS_statusR$D_IN = + { wsiS_isReset_isInReset, + !wsiS_peerIsReady, + !wsiS_operateD, + wsiS_errorSticky, + wsiS_burstKind != 2'd0, + !wsiS_sThreadBusy_dw$whas || wsiS_sThreadBusy_dw$wget, + 1'd0, + wsiS_trafficSticky } ; + assign wsiS_statusR$EN = 1'd1 ; + + // register wsiS_tBusyCount + assign wsiS_tBusyCount$D_IN = wsiS_tBusyCount + 32'd1 ; + assign wsiS_tBusyCount$EN = + wsiS_operateD && wsiS_peerIsReady && + (!wsiS_sThreadBusy_dw$whas || wsiS_sThreadBusy_dw$wget) ; + + // register wsiS_trafficSticky + assign wsiS_trafficSticky$D_IN = 1'd1 ; + assign wsiS_trafficSticky$EN = WILL_FIRE_RL_wsiS_reqFifo_enq ; + + // register wsiS_wordCount + assign wsiS_wordCount$D_IN = + wsiS_wsiReq$wget[57] ? 12'd1 : wsiS_wordCount + 12'd1 ; + assign wsiS_wordCount$EN = WILL_FIRE_RL_wsiS_reqFifo_enq ; + + // submodule biasWorker_wci_wslv_reqF + assign biasWorker_wci_wslv_reqF$D_IN = biasWorker_wci_wslv_wciReq$wget ; + assign biasWorker_wci_wslv_reqF$ENQ = + biasWorker_wci_wslv_wciReq$wget[71:69] != 3'd0 ; + assign biasWorker_wci_wslv_reqF$DEQ = biasWorker_wci_wslv_reqF_r_deq$whas ; + assign biasWorker_wci_wslv_reqF$CLR = 1'b0 ; + + // submodule biasWorker_wsiS_reqFifo + assign biasWorker_wsiS_reqFifo$D_IN = biasWorker_wsiS_wsiReq$wget ; + assign biasWorker_wsiS_reqFifo$ENQ = + WILL_FIRE_RL_biasWorker_wsiS_reqFifo_enq ; + assign biasWorker_wsiS_reqFifo$DEQ = + MUX_biasWorker_wsiS_reqFifo_levelsValid$write_1__SEL_3 ; + assign biasWorker_wsiS_reqFifo$CLR = 1'b0 ; + + // submodule wci_mReset + assign wci_mReset$ASSERT_IN = !wci_wReset_n ; + + // submodule wci_respF + always@(MUX_wci_respF$enq_1__SEL_1 or + MUX_wci_busy$write_1__SEL_2 or + MUX_wci_respF$enq_1__VAL_2 or WILL_FIRE_RL_wciSeqFsm_action_l54c8) + begin + case (1'b1) // synopsys parallel_case + MUX_wci_respF$enq_1__SEL_1: wci_respF$D_IN = 34'h1C0DE4204; + MUX_wci_busy$write_1__SEL_2: + wci_respF$D_IN = MUX_wci_respF$enq_1__VAL_2; + WILL_FIRE_RL_wciSeqFsm_action_l54c8: wci_respF$D_IN = 34'h100000000; + default: wci_respF$D_IN = 34'h2AAAAAAAA /* unspecified value */ ; + endcase + end + assign wci_respF$ENQ = + _dand1wci_respF$EN_enq || + WILL_FIRE_RL_wci_wrkBusy && + (!wci_respTimr_7_ULT_1_SL_wci_wTimeout_8_9___d969 || + biasWorker_wci_wslv_respF_q_0[33:32] != 2'd0) || + WILL_FIRE_RL_wciSeqFsm_action_l54c8 ; + assign wci_respF$DEQ = + WILL_FIRE_RL_wciSeqFsm_action_l71c5 || + WILL_FIRE_RL_wciSeqFsm_action_l67c5 || + WILL_FIRE_RL_wciSeqFsm_action_l63c5 || + WILL_FIRE_RL_wciSeqFsm_action_l59c5 || + WILL_FIRE_RL_wciSeqFsm_action_l55c5 ; + assign wci_respF$CLR = 1'b0 ; + + // submodule wsiS_reqFifo + assign wsiS_reqFifo$D_IN = wsiS_wsiReq$wget ; + assign wsiS_reqFifo$ENQ = WILL_FIRE_RL_wsiS_reqFifo_enq ; + assign wsiS_reqFifo$DEQ = MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 ; + assign wsiS_reqFifo$CLR = 1'b0 ; + + // remaining internal signals + assign IF_wci_lastControlOp_22_BIT_3_23_THEN_wci_last_ETC___d137 = + { wci_lastControlOp[3] ? wci_lastControlOp[2:0] : 3'b111, + wci_lastConfigBE[4] ? wci_lastConfigBE[3:0] : 4'hF, + wci_lastOpWrite[1], + wci_lastControlOp[3], + wci_lastConfigBE[4], + wci_lastConfigAddr[32], + 6'b0, + wci_sfCap, + wci_reqTO, + wci_reqFAIL, + wci_reqERR } ; + assign NOT_wci_busy_5_04_AND_IF_wci_wReset_n_5_THEN_N_ETC___d817 = + !wci_busy && (wci_wReset_n ? !wci_reqF_c_r : wci_respF$FULL_N) ; + assign _dand1wci_busy$EN_write = + (WILL_FIRE_RL_wciSeqFsm_action_l70c8 || + WILL_FIRE_RL_wciSeqFsm_action_l66c8 || + WILL_FIRE_RL_wciSeqFsm_action_l62c8 || + WILL_FIRE_RL_wciSeqFsm_action_l58c8) && + wci_wReset_n ; + assign _dand1wci_respF$EN_enq = + (WILL_FIRE_RL_wciSeqFsm_action_l70c8 || + WILL_FIRE_RL_wciSeqFsm_action_l66c8 || + WILL_FIRE_RL_wciSeqFsm_action_l62c8 || + WILL_FIRE_RL_wciSeqFsm_action_l58c8) && + !wci_wReset_n ; + assign _dor1wci_lastConfigAddr$EN_write = + WILL_FIRE_RL_wciSeqFsm_action_l66c8 || + WILL_FIRE_RL_wciSeqFsm_action_l62c8 ; + assign rdat__h21350 = { 16'd0, x__h21353 } ; + assign toCount__h2586 = 32'd1 << wci_wTimeout ; + assign wciAddr__h60695 = { wci_pageWindow, 20'h00004 } ; + assign wciSeqFsm_abort_whas__63_AND_wciSeqFsm_abort_w_ETC___d875 = + (wciSeqFsm_state_mkFSMstate == 5'd0 || + wciSeqFsm_state_mkFSMstate == 5'd22) && + (!wciSeqFsm_start_reg_1 || wciSeqFsm_state_fired) ; + assign wci_respTimr_7_ULT_1_SL_wci_wTimeout_8_9___d969 = + wci_respTimr < toCount__h2586 ; + assign wsiBurstLength__h66174 = { 4'd0, wsiS_reqFifo$D_OUT[55:44] } ; + assign wsiS_reqFifo_first__99_BITS_43_TO_12_00_EQ_dst_ETC___d943 = + wsiS_reqFifo$D_OUT[43:12] == dstDataOut ; + assign x__h21353 = { biasWorker_wsiS_statusR, biasWorker_wsiM_statusR } ; + assign x__h2746 = wci_respTimr + 32'd1 ; + assign x__h66071 = srcUnrollCnt - 16'd1 ; + assign x__h66543 = dstUnrollCnt - 16'd1 ; + assign x_data__h20592 = + biasWorker_wsiS_reqFifo$D_OUT[43:12] + biasWorker_biasValue ; + always@(biasWorker_wci_wslv_reqF$D_OUT or + biasWorker_biasValue or + biasWorker_controlReg or + rdat__h21350 or + biasWorker_wsiS_extStatusW$wget or biasWorker_wsiM_extStatusW$wget) + begin + case (biasWorker_wci_wslv_reqF$D_OUT[39:32]) + 8'h0: _theResult____h21260 = biasWorker_biasValue; + 8'h04: _theResult____h21260 = biasWorker_controlReg; + 8'h20: _theResult____h21260 = rdat__h21350; + 8'h24: _theResult____h21260 = biasWorker_wsiS_extStatusW$wget[95:64]; + 8'h28: _theResult____h21260 = biasWorker_wsiS_extStatusW$wget[63:32]; + 8'h2C: _theResult____h21260 = biasWorker_wsiS_extStatusW$wget[31:0]; + 8'h30: _theResult____h21260 = biasWorker_wsiM_extStatusW$wget[95:64]; + 8'h34: _theResult____h21260 = biasWorker_wsiM_extStatusW$wget[63:32]; + 8'h38: _theResult____h21260 = biasWorker_wsiM_extStatusW$wget[31:0]; + default: _theResult____h21260 = 32'd0; + endcase + end + + // handling of inlined registers + + always@(posedge CLK) + begin + if (RST_N == `BSV_RESET_VALUE) + begin + badDataCnt <= `BSV_ASSIGNMENT_DELAY 32'd0; + badMesgCnt <= `BSV_ASSIGNMENT_DELAY 32'd0; + dstDataOut <= `BSV_ASSIGNMENT_DELAY 32'd0; + dstMesgCount <= `BSV_ASSIGNMENT_DELAY 16'd0; + dstUnrollCnt <= `BSV_ASSIGNMENT_DELAY 16'd0; + enWsiChecker <= `BSV_ASSIGNMENT_DELAY 1'd0; + enWsiSource <= `BSV_ASSIGNMENT_DELAY 1'd0; + goodDataCnt <= `BSV_ASSIGNMENT_DELAY 32'd0; + goodMesgCnt <= `BSV_ASSIGNMENT_DELAY 32'd0; + mesgHadError <= `BSV_ASSIGNMENT_DELAY 1'd0; + simCycle <= `BSV_ASSIGNMENT_DELAY 16'd0; + srcDataOut <= `BSV_ASSIGNMENT_DELAY 32'd0; + srcMesgCount <= `BSV_ASSIGNMENT_DELAY 16'd0; + srcUnrollCnt <= `BSV_ASSIGNMENT_DELAY 16'd0; + testOperating <= `BSV_ASSIGNMENT_DELAY 1'd0; + wciSeqFsm_start_reg <= `BSV_ASSIGNMENT_DELAY 1'd0; + wciSeqFsm_start_reg_1 <= `BSV_ASSIGNMENT_DELAY 1'd0; + wciSeqFsm_state_can_overlap <= `BSV_ASSIGNMENT_DELAY 1'd1; + wciSeqFsm_state_fired <= `BSV_ASSIGNMENT_DELAY 1'd0; + wciSeqFsm_state_mkFSMstate <= `BSV_ASSIGNMENT_DELAY 5'd0; + wciSeqOnce_onceReady <= `BSV_ASSIGNMENT_DELAY 1'd1; + wci_busy <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_lastConfigAddr <= `BSV_ASSIGNMENT_DELAY 33'h0AAAAAAAA; + wci_lastConfigBE <= `BSV_ASSIGNMENT_DELAY 5'd10; + wci_lastControlOp <= `BSV_ASSIGNMENT_DELAY 4'd2; + wci_lastOpWrite <= `BSV_ASSIGNMENT_DELAY 2'd0; + wci_mFlagReg <= `BSV_ASSIGNMENT_DELAY 2'b10; + wci_pageWindow <= `BSV_ASSIGNMENT_DELAY 12'd0; + wci_reqERR <= `BSV_ASSIGNMENT_DELAY 3'd0; + wci_reqFAIL <= `BSV_ASSIGNMENT_DELAY 3'd0; + wci_reqF_c_r <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_reqF_q_0 <= `BSV_ASSIGNMENT_DELAY 72'h0000000000AAAAAAAA; + wci_reqPend <= `BSV_ASSIGNMENT_DELAY 2'd0; + wci_reqTO <= `BSV_ASSIGNMENT_DELAY 3'd0; + wci_respTimr <= `BSV_ASSIGNMENT_DELAY 32'd0; + wci_respTimrAct <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY 1'd1; + wci_sfCap <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_sfCapClear <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_sfCapSet <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_slvPresent <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_wReset_n <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_wTimeout <= `BSV_ASSIGNMENT_DELAY 5'h04; + wsiM_burstKind <= `BSV_ASSIGNMENT_DELAY 2'd0; + wsiM_errorSticky <= `BSV_ASSIGNMENT_DELAY 1'd0; + wsiM_iMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0; + wsiM_operateD <= `BSV_ASSIGNMENT_DELAY 1'd0; + wsiM_pMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0; + wsiM_peerIsReady <= `BSV_ASSIGNMENT_DELAY 1'd0; + wsiM_reqFifo_c_r <= `BSV_ASSIGNMENT_DELAY 2'd0; + wsiM_reqFifo_q_0 <= `BSV_ASSIGNMENT_DELAY 61'h00000AAAAAAAAA00; + wsiM_reqFifo_q_1 <= `BSV_ASSIGNMENT_DELAY 61'h00000AAAAAAAAA00; + wsiM_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY 1'd1; + wsiM_tBusyCount <= `BSV_ASSIGNMENT_DELAY 32'd0; + wsiM_trafficSticky <= `BSV_ASSIGNMENT_DELAY 1'd0; + wsiS_burstKind <= `BSV_ASSIGNMENT_DELAY 2'd0; + wsiS_errorSticky <= `BSV_ASSIGNMENT_DELAY 1'd0; + wsiS_iMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0; + wsiS_operateD <= `BSV_ASSIGNMENT_DELAY 1'd0; + wsiS_pMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0; + wsiS_peerIsReady <= `BSV_ASSIGNMENT_DELAY 1'd0; + wsiS_reqFifo_countReg <= `BSV_ASSIGNMENT_DELAY 2'd0; + wsiS_reqFifo_levelsValid <= `BSV_ASSIGNMENT_DELAY 1'd1; + wsiS_tBusyCount <= `BSV_ASSIGNMENT_DELAY 32'd0; + wsiS_trafficSticky <= `BSV_ASSIGNMENT_DELAY 1'd0; + wsiS_wordCount <= `BSV_ASSIGNMENT_DELAY 12'd1; + end + else + begin + if (badDataCnt$EN) + badDataCnt <= `BSV_ASSIGNMENT_DELAY badDataCnt$D_IN; + if (badMesgCnt$EN) + badMesgCnt <= `BSV_ASSIGNMENT_DELAY badMesgCnt$D_IN; + if (dstDataOut$EN) + dstDataOut <= `BSV_ASSIGNMENT_DELAY dstDataOut$D_IN; + if (dstMesgCount$EN) + dstMesgCount <= `BSV_ASSIGNMENT_DELAY dstMesgCount$D_IN; + if (dstUnrollCnt$EN) + dstUnrollCnt <= `BSV_ASSIGNMENT_DELAY dstUnrollCnt$D_IN; + if (enWsiChecker$EN) + enWsiChecker <= `BSV_ASSIGNMENT_DELAY enWsiChecker$D_IN; + if (enWsiSource$EN) + enWsiSource <= `BSV_ASSIGNMENT_DELAY enWsiSource$D_IN; + if (goodDataCnt$EN) + goodDataCnt <= `BSV_ASSIGNMENT_DELAY goodDataCnt$D_IN; + if (goodMesgCnt$EN) + goodMesgCnt <= `BSV_ASSIGNMENT_DELAY goodMesgCnt$D_IN; + if (mesgHadError$EN) + mesgHadError <= `BSV_ASSIGNMENT_DELAY mesgHadError$D_IN; + if (simCycle$EN) simCycle <= `BSV_ASSIGNMENT_DELAY simCycle$D_IN; + if (srcDataOut$EN) + srcDataOut <= `BSV_ASSIGNMENT_DELAY srcDataOut$D_IN; + if (srcMesgCount$EN) + srcMesgCount <= `BSV_ASSIGNMENT_DELAY srcMesgCount$D_IN; + if (srcUnrollCnt$EN) + srcUnrollCnt <= `BSV_ASSIGNMENT_DELAY srcUnrollCnt$D_IN; + if (testOperating$EN) + testOperating <= `BSV_ASSIGNMENT_DELAY testOperating$D_IN; + if (wciSeqFsm_start_reg$EN) + wciSeqFsm_start_reg <= `BSV_ASSIGNMENT_DELAY + wciSeqFsm_start_reg$D_IN; + if (wciSeqFsm_start_reg_1$EN) + wciSeqFsm_start_reg_1 <= `BSV_ASSIGNMENT_DELAY + wciSeqFsm_start_reg_1$D_IN; + if (wciSeqFsm_state_can_overlap$EN) + wciSeqFsm_state_can_overlap <= `BSV_ASSIGNMENT_DELAY + wciSeqFsm_state_can_overlap$D_IN; + if (wciSeqFsm_state_fired$EN) + wciSeqFsm_state_fired <= `BSV_ASSIGNMENT_DELAY + wciSeqFsm_state_fired$D_IN; + if (wciSeqFsm_state_mkFSMstate$EN) + wciSeqFsm_state_mkFSMstate <= `BSV_ASSIGNMENT_DELAY + wciSeqFsm_state_mkFSMstate$D_IN; + if (wciSeqOnce_onceReady$EN) + wciSeqOnce_onceReady <= `BSV_ASSIGNMENT_DELAY + wciSeqOnce_onceReady$D_IN; + if (wci_busy$EN) wci_busy <= `BSV_ASSIGNMENT_DELAY wci_busy$D_IN; + if (wci_lastConfigAddr$EN) + wci_lastConfigAddr <= `BSV_ASSIGNMENT_DELAY wci_lastConfigAddr$D_IN; + if (wci_lastConfigBE$EN) + wci_lastConfigBE <= `BSV_ASSIGNMENT_DELAY wci_lastConfigBE$D_IN; + if (wci_lastControlOp$EN) + wci_lastControlOp <= `BSV_ASSIGNMENT_DELAY wci_lastControlOp$D_IN; + if (wci_lastOpWrite$EN) + wci_lastOpWrite <= `BSV_ASSIGNMENT_DELAY wci_lastOpWrite$D_IN; + if (wci_mFlagReg$EN) + wci_mFlagReg <= `BSV_ASSIGNMENT_DELAY wci_mFlagReg$D_IN; + if (wci_pageWindow$EN) + wci_pageWindow <= `BSV_ASSIGNMENT_DELAY wci_pageWindow$D_IN; + if (wci_reqERR$EN) + wci_reqERR <= `BSV_ASSIGNMENT_DELAY wci_reqERR$D_IN; + if (wci_reqFAIL$EN) + wci_reqFAIL <= `BSV_ASSIGNMENT_DELAY wci_reqFAIL$D_IN; + if (wci_reqF_c_r$EN) + wci_reqF_c_r <= `BSV_ASSIGNMENT_DELAY wci_reqF_c_r$D_IN; + if (wci_reqF_q_0$EN) + wci_reqF_q_0 <= `BSV_ASSIGNMENT_DELAY wci_reqF_q_0$D_IN; + if (wci_reqPend$EN) + wci_reqPend <= `BSV_ASSIGNMENT_DELAY wci_reqPend$D_IN; + if (wci_reqTO$EN) wci_reqTO <= `BSV_ASSIGNMENT_DELAY wci_reqTO$D_IN; + if (wci_respTimr$EN) + wci_respTimr <= `BSV_ASSIGNMENT_DELAY wci_respTimr$D_IN; + if (wci_respTimrAct$EN) + wci_respTimrAct <= `BSV_ASSIGNMENT_DELAY wci_respTimrAct$D_IN; + if (wci_sThreadBusy_d$EN) + wci_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY wci_sThreadBusy_d$D_IN; + if (wci_sfCap$EN) wci_sfCap <= `BSV_ASSIGNMENT_DELAY wci_sfCap$D_IN; + if (wci_sfCapClear$EN) + wci_sfCapClear <= `BSV_ASSIGNMENT_DELAY wci_sfCapClear$D_IN; + if (wci_sfCapSet$EN) + wci_sfCapSet <= `BSV_ASSIGNMENT_DELAY wci_sfCapSet$D_IN; + if (wci_slvPresent$EN) + wci_slvPresent <= `BSV_ASSIGNMENT_DELAY wci_slvPresent$D_IN; + if (wci_wReset_n$EN) + wci_wReset_n <= `BSV_ASSIGNMENT_DELAY wci_wReset_n$D_IN; + if (wci_wTimeout$EN) + wci_wTimeout <= `BSV_ASSIGNMENT_DELAY wci_wTimeout$D_IN; + if (wsiM_burstKind$EN) + wsiM_burstKind <= `BSV_ASSIGNMENT_DELAY wsiM_burstKind$D_IN; + if (wsiM_errorSticky$EN) + wsiM_errorSticky <= `BSV_ASSIGNMENT_DELAY wsiM_errorSticky$D_IN; + if (wsiM_iMesgCount$EN) + wsiM_iMesgCount <= `BSV_ASSIGNMENT_DELAY wsiM_iMesgCount$D_IN; + if (wsiM_operateD$EN) + wsiM_operateD <= `BSV_ASSIGNMENT_DELAY wsiM_operateD$D_IN; + if (wsiM_pMesgCount$EN) + wsiM_pMesgCount <= `BSV_ASSIGNMENT_DELAY wsiM_pMesgCount$D_IN; + if (wsiM_peerIsReady$EN) + wsiM_peerIsReady <= `BSV_ASSIGNMENT_DELAY wsiM_peerIsReady$D_IN; + if (wsiM_reqFifo_c_r$EN) + wsiM_reqFifo_c_r <= `BSV_ASSIGNMENT_DELAY wsiM_reqFifo_c_r$D_IN; + if (wsiM_reqFifo_q_0$EN) + wsiM_reqFifo_q_0 <= `BSV_ASSIGNMENT_DELAY wsiM_reqFifo_q_0$D_IN; + if (wsiM_reqFifo_q_1$EN) + wsiM_reqFifo_q_1 <= `BSV_ASSIGNMENT_DELAY wsiM_reqFifo_q_1$D_IN; + if (wsiM_sThreadBusy_d$EN) + wsiM_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY wsiM_sThreadBusy_d$D_IN; + if (wsiM_tBusyCount$EN) + wsiM_tBusyCount <= `BSV_ASSIGNMENT_DELAY wsiM_tBusyCount$D_IN; + if (wsiM_trafficSticky$EN) + wsiM_trafficSticky <= `BSV_ASSIGNMENT_DELAY wsiM_trafficSticky$D_IN; + if (wsiS_burstKind$EN) + wsiS_burstKind <= `BSV_ASSIGNMENT_DELAY wsiS_burstKind$D_IN; + if (wsiS_errorSticky$EN) + wsiS_errorSticky <= `BSV_ASSIGNMENT_DELAY wsiS_errorSticky$D_IN; + if (wsiS_iMesgCount$EN) + wsiS_iMesgCount <= `BSV_ASSIGNMENT_DELAY wsiS_iMesgCount$D_IN; + if (wsiS_operateD$EN) + wsiS_operateD <= `BSV_ASSIGNMENT_DELAY wsiS_operateD$D_IN; + if (wsiS_pMesgCount$EN) + wsiS_pMesgCount <= `BSV_ASSIGNMENT_DELAY wsiS_pMesgCount$D_IN; + if (wsiS_peerIsReady$EN) + wsiS_peerIsReady <= `BSV_ASSIGNMENT_DELAY wsiS_peerIsReady$D_IN; + if (wsiS_reqFifo_countReg$EN) + wsiS_reqFifo_countReg <= `BSV_ASSIGNMENT_DELAY + wsiS_reqFifo_countReg$D_IN; + if (wsiS_reqFifo_levelsValid$EN) + wsiS_reqFifo_levelsValid <= `BSV_ASSIGNMENT_DELAY + wsiS_reqFifo_levelsValid$D_IN; + if (wsiS_tBusyCount$EN) + wsiS_tBusyCount <= `BSV_ASSIGNMENT_DELAY wsiS_tBusyCount$D_IN; + if (wsiS_trafficSticky$EN) + wsiS_trafficSticky <= `BSV_ASSIGNMENT_DELAY wsiS_trafficSticky$D_IN; + if (wsiS_wordCount$EN) + wsiS_wordCount <= `BSV_ASSIGNMENT_DELAY wsiS_wordCount$D_IN; + end + if (wci_mReset$OUT_RST == `BSV_RESET_VALUE) + begin + biasWorker_wci_wslv_cEdge <= `BSV_ASSIGNMENT_DELAY 3'h2; + biasWorker_wci_wslv_cState <= `BSV_ASSIGNMENT_DELAY 3'd0; + biasWorker_wci_wslv_ctlAckReg <= `BSV_ASSIGNMENT_DELAY 1'd0; + biasWorker_wci_wslv_ctlOpActive <= `BSV_ASSIGNMENT_DELAY 1'd0; + biasWorker_wci_wslv_illegalEdge <= `BSV_ASSIGNMENT_DELAY 1'd0; + biasWorker_wci_wslv_nState <= `BSV_ASSIGNMENT_DELAY 3'd0; + biasWorker_wci_wslv_reqF_countReg <= `BSV_ASSIGNMENT_DELAY 2'd0; + biasWorker_wci_wslv_respF_c_r <= `BSV_ASSIGNMENT_DELAY 2'd0; + biasWorker_wci_wslv_respF_q_0 <= `BSV_ASSIGNMENT_DELAY 34'h0AAAAAAAA; + biasWorker_wci_wslv_respF_q_1 <= `BSV_ASSIGNMENT_DELAY 34'h0AAAAAAAA; + biasWorker_wci_wslv_sFlagReg <= `BSV_ASSIGNMENT_DELAY 1'd0; + biasWorker_wci_wslv_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY 1'd1; + biasWorker_wsiM_burstKind <= `BSV_ASSIGNMENT_DELAY 2'd0; + biasWorker_wsiM_errorSticky <= `BSV_ASSIGNMENT_DELAY 1'd0; + biasWorker_wsiM_iMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0; + biasWorker_wsiM_operateD <= `BSV_ASSIGNMENT_DELAY 1'd0; + biasWorker_wsiM_pMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0; + biasWorker_wsiM_peerIsReady <= `BSV_ASSIGNMENT_DELAY 1'd0; + biasWorker_wsiM_reqFifo_c_r <= `BSV_ASSIGNMENT_DELAY 2'd0; + biasWorker_wsiM_reqFifo_q_0 <= `BSV_ASSIGNMENT_DELAY + 61'h00000AAAAAAAAA00; + biasWorker_wsiM_reqFifo_q_1 <= `BSV_ASSIGNMENT_DELAY + 61'h00000AAAAAAAAA00; + biasWorker_wsiM_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY 1'd1; + biasWorker_wsiM_tBusyCount <= `BSV_ASSIGNMENT_DELAY 32'd0; + biasWorker_wsiM_trafficSticky <= `BSV_ASSIGNMENT_DELAY 1'd0; + biasWorker_wsiS_burstKind <= `BSV_ASSIGNMENT_DELAY 2'd0; + biasWorker_wsiS_errorSticky <= `BSV_ASSIGNMENT_DELAY 1'd0; + biasWorker_wsiS_iMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0; + biasWorker_wsiS_operateD <= `BSV_ASSIGNMENT_DELAY 1'd0; + biasWorker_wsiS_pMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0; + biasWorker_wsiS_peerIsReady <= `BSV_ASSIGNMENT_DELAY 1'd0; + biasWorker_wsiS_reqFifo_countReg <= `BSV_ASSIGNMENT_DELAY 2'd0; + biasWorker_wsiS_reqFifo_levelsValid <= `BSV_ASSIGNMENT_DELAY 1'd1; + biasWorker_wsiS_tBusyCount <= `BSV_ASSIGNMENT_DELAY 32'd0; + biasWorker_wsiS_trafficSticky <= `BSV_ASSIGNMENT_DELAY 1'd0; + biasWorker_wsiS_wordCount <= `BSV_ASSIGNMENT_DELAY 12'd1; + end + else + begin + if (biasWorker_wci_wslv_cEdge$EN) + biasWorker_wci_wslv_cEdge <= `BSV_ASSIGNMENT_DELAY + biasWorker_wci_wslv_cEdge$D_IN; + if (biasWorker_wci_wslv_cState$EN) + biasWorker_wci_wslv_cState <= `BSV_ASSIGNMENT_DELAY + biasWorker_wci_wslv_cState$D_IN; + if (biasWorker_wci_wslv_ctlAckReg$EN) + biasWorker_wci_wslv_ctlAckReg <= `BSV_ASSIGNMENT_DELAY + biasWorker_wci_wslv_ctlAckReg$D_IN; + if (biasWorker_wci_wslv_ctlOpActive$EN) + biasWorker_wci_wslv_ctlOpActive <= `BSV_ASSIGNMENT_DELAY + biasWorker_wci_wslv_ctlOpActive$D_IN; + if (biasWorker_wci_wslv_illegalEdge$EN) + biasWorker_wci_wslv_illegalEdge <= `BSV_ASSIGNMENT_DELAY + biasWorker_wci_wslv_illegalEdge$D_IN; + if (biasWorker_wci_wslv_nState$EN) + biasWorker_wci_wslv_nState <= `BSV_ASSIGNMENT_DELAY + biasWorker_wci_wslv_nState$D_IN; + if (biasWorker_wci_wslv_reqF_countReg$EN) + biasWorker_wci_wslv_reqF_countReg <= `BSV_ASSIGNMENT_DELAY + biasWorker_wci_wslv_reqF_countReg$D_IN; + if (biasWorker_wci_wslv_respF_c_r$EN) + biasWorker_wci_wslv_respF_c_r <= `BSV_ASSIGNMENT_DELAY + biasWorker_wci_wslv_respF_c_r$D_IN; + if (biasWorker_wci_wslv_respF_q_0$EN) + biasWorker_wci_wslv_respF_q_0 <= `BSV_ASSIGNMENT_DELAY + biasWorker_wci_wslv_respF_q_0$D_IN; + if (biasWorker_wci_wslv_respF_q_1$EN) + biasWorker_wci_wslv_respF_q_1 <= `BSV_ASSIGNMENT_DELAY + biasWorker_wci_wslv_respF_q_1$D_IN; + if (biasWorker_wci_wslv_sFlagReg$EN) + biasWorker_wci_wslv_sFlagReg <= `BSV_ASSIGNMENT_DELAY + biasWorker_wci_wslv_sFlagReg$D_IN; + if (biasWorker_wci_wslv_sThreadBusy_d$EN) + biasWorker_wci_wslv_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY + biasWorker_wci_wslv_sThreadBusy_d$D_IN; + if (biasWorker_wsiM_burstKind$EN) + biasWorker_wsiM_burstKind <= `BSV_ASSIGNMENT_DELAY + biasWorker_wsiM_burstKind$D_IN; + if (biasWorker_wsiM_errorSticky$EN) + biasWorker_wsiM_errorSticky <= `BSV_ASSIGNMENT_DELAY + biasWorker_wsiM_errorSticky$D_IN; + if (biasWorker_wsiM_iMesgCount$EN) + biasWorker_wsiM_iMesgCount <= `BSV_ASSIGNMENT_DELAY + biasWorker_wsiM_iMesgCount$D_IN; + if (biasWorker_wsiM_operateD$EN) + biasWorker_wsiM_operateD <= `BSV_ASSIGNMENT_DELAY + biasWorker_wsiM_operateD$D_IN; + if (biasWorker_wsiM_pMesgCount$EN) + biasWorker_wsiM_pMesgCount <= `BSV_ASSIGNMENT_DELAY + biasWorker_wsiM_pMesgCount$D_IN; + if (biasWorker_wsiM_peerIsReady$EN) + biasWorker_wsiM_peerIsReady <= `BSV_ASSIGNMENT_DELAY + biasWorker_wsiM_peerIsReady$D_IN; + if (biasWorker_wsiM_reqFifo_c_r$EN) + biasWorker_wsiM_reqFifo_c_r <= `BSV_ASSIGNMENT_DELAY + biasWorker_wsiM_reqFifo_c_r$D_IN; + if (biasWorker_wsiM_reqFifo_q_0$EN) + biasWorker_wsiM_reqFifo_q_0 <= `BSV_ASSIGNMENT_DELAY + biasWorker_wsiM_reqFifo_q_0$D_IN; + if (biasWorker_wsiM_reqFifo_q_1$EN) + biasWorker_wsiM_reqFifo_q_1 <= `BSV_ASSIGNMENT_DELAY + biasWorker_wsiM_reqFifo_q_1$D_IN; + if (biasWorker_wsiM_sThreadBusy_d$EN) + biasWorker_wsiM_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY + biasWorker_wsiM_sThreadBusy_d$D_IN; + if (biasWorker_wsiM_tBusyCount$EN) + biasWorker_wsiM_tBusyCount <= `BSV_ASSIGNMENT_DELAY + biasWorker_wsiM_tBusyCount$D_IN; + if (biasWorker_wsiM_trafficSticky$EN) + biasWorker_wsiM_trafficSticky <= `BSV_ASSIGNMENT_DELAY + biasWorker_wsiM_trafficSticky$D_IN; + if (biasWorker_wsiS_burstKind$EN) + biasWorker_wsiS_burstKind <= `BSV_ASSIGNMENT_DELAY + biasWorker_wsiS_burstKind$D_IN; + if (biasWorker_wsiS_errorSticky$EN) + biasWorker_wsiS_errorSticky <= `BSV_ASSIGNMENT_DELAY + biasWorker_wsiS_errorSticky$D_IN; + if (biasWorker_wsiS_iMesgCount$EN) + biasWorker_wsiS_iMesgCount <= `BSV_ASSIGNMENT_DELAY + biasWorker_wsiS_iMesgCount$D_IN; + if (biasWorker_wsiS_operateD$EN) + biasWorker_wsiS_operateD <= `BSV_ASSIGNMENT_DELAY + biasWorker_wsiS_operateD$D_IN; + if (biasWorker_wsiS_pMesgCount$EN) + biasWorker_wsiS_pMesgCount <= `BSV_ASSIGNMENT_DELAY + biasWorker_wsiS_pMesgCount$D_IN; + if (biasWorker_wsiS_peerIsReady$EN) + biasWorker_wsiS_peerIsReady <= `BSV_ASSIGNMENT_DELAY + biasWorker_wsiS_peerIsReady$D_IN; + if (biasWorker_wsiS_reqFifo_countReg$EN) + biasWorker_wsiS_reqFifo_countReg <= `BSV_ASSIGNMENT_DELAY + biasWorker_wsiS_reqFifo_countReg$D_IN; + if (biasWorker_wsiS_reqFifo_levelsValid$EN) + biasWorker_wsiS_reqFifo_levelsValid <= `BSV_ASSIGNMENT_DELAY + biasWorker_wsiS_reqFifo_levelsValid$D_IN; + if (biasWorker_wsiS_tBusyCount$EN) + biasWorker_wsiS_tBusyCount <= `BSV_ASSIGNMENT_DELAY + biasWorker_wsiS_tBusyCount$D_IN; + if (biasWorker_wsiS_trafficSticky$EN) + biasWorker_wsiS_trafficSticky <= `BSV_ASSIGNMENT_DELAY + biasWorker_wsiS_trafficSticky$D_IN; + if (biasWorker_wsiS_wordCount$EN) + biasWorker_wsiS_wordCount <= `BSV_ASSIGNMENT_DELAY + biasWorker_wsiS_wordCount$D_IN; + end + if (biasWorker_biasValue$EN) + biasWorker_biasValue <= `BSV_ASSIGNMENT_DELAY biasWorker_biasValue$D_IN; + if (biasWorker_controlReg$EN) + biasWorker_controlReg <= `BSV_ASSIGNMENT_DELAY + biasWorker_controlReg$D_IN; + if (biasWorker_wsiM_statusR$EN) + biasWorker_wsiM_statusR <= `BSV_ASSIGNMENT_DELAY + biasWorker_wsiM_statusR$D_IN; + if (biasWorker_wsiS_mesgWordLength$EN) + biasWorker_wsiS_mesgWordLength <= `BSV_ASSIGNMENT_DELAY + biasWorker_wsiS_mesgWordLength$D_IN; + if (biasWorker_wsiS_statusR$EN) + biasWorker_wsiS_statusR <= `BSV_ASSIGNMENT_DELAY + biasWorker_wsiS_statusR$D_IN; + if (wci_wStatus$EN) wci_wStatus <= `BSV_ASSIGNMENT_DELAY wci_wStatus$D_IN; + if (wsiM_statusR$EN) + wsiM_statusR <= `BSV_ASSIGNMENT_DELAY wsiM_statusR$D_IN; + if (wsiS_mesgWordLength$EN) + wsiS_mesgWordLength <= `BSV_ASSIGNMENT_DELAY wsiS_mesgWordLength$D_IN; + if (wsiS_statusR$EN) + wsiS_statusR <= `BSV_ASSIGNMENT_DELAY wsiS_statusR$D_IN; + end + + always@(posedge CLK or `BSV_RESET_EDGE RST_N) + if (RST_N == `BSV_RESET_VALUE) + begin + wsiM_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY 1'd1; + wsiS_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY 1'd1; + end + else + begin + if (wsiM_isReset_isInReset$EN) + wsiM_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY + wsiM_isReset_isInReset$D_IN; + if (wsiS_isReset_isInReset$EN) + wsiS_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY + wsiS_isReset_isInReset$D_IN; + end + + always@(posedge CLK or `BSV_RESET_EDGE wci_mReset$OUT_RST) + if (wci_mReset$OUT_RST == `BSV_RESET_VALUE) + begin + biasWorker_wci_wslv_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY 1'd1; + biasWorker_wsiM_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY 1'd1; + biasWorker_wsiS_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY 1'd1; + end + else + begin + if (biasWorker_wci_wslv_isReset_isInReset$EN) + biasWorker_wci_wslv_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY + biasWorker_wci_wslv_isReset_isInReset$D_IN; + if (biasWorker_wsiM_isReset_isInReset$EN) + biasWorker_wsiM_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY + biasWorker_wsiM_isReset_isInReset$D_IN; + if (biasWorker_wsiS_isReset_isInReset$EN) + biasWorker_wsiS_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY + biasWorker_wsiS_isReset_isInReset$D_IN; + end + + // synopsys translate_off + `ifdef BSV_NO_INITIAL_BLOCKS + `else // not BSV_NO_INITIAL_BLOCKS + initial + begin + badDataCnt = 32'hAAAAAAAA; + badMesgCnt = 32'hAAAAAAAA; + biasWorker_biasValue = 32'hAAAAAAAA; + biasWorker_controlReg = 32'hAAAAAAAA; + biasWorker_wci_wslv_cEdge = 3'h2; + biasWorker_wci_wslv_cState = 3'h2; + biasWorker_wci_wslv_ctlAckReg = 1'h0; + biasWorker_wci_wslv_ctlOpActive = 1'h0; + biasWorker_wci_wslv_illegalEdge = 1'h0; + biasWorker_wci_wslv_isReset_isInReset = 1'h0; + biasWorker_wci_wslv_nState = 3'h2; + biasWorker_wci_wslv_reqF_countReg = 2'h2; + biasWorker_wci_wslv_respF_c_r = 2'h2; + biasWorker_wci_wslv_respF_q_0 = 34'h2AAAAAAAA; + biasWorker_wci_wslv_respF_q_1 = 34'h2AAAAAAAA; + biasWorker_wci_wslv_sFlagReg = 1'h0; + biasWorker_wci_wslv_sThreadBusy_d = 1'h0; + biasWorker_wsiM_burstKind = 2'h2; + biasWorker_wsiM_errorSticky = 1'h0; + biasWorker_wsiM_iMesgCount = 32'hAAAAAAAA; + biasWorker_wsiM_isReset_isInReset = 1'h0; + biasWorker_wsiM_operateD = 1'h0; + biasWorker_wsiM_pMesgCount = 32'hAAAAAAAA; + biasWorker_wsiM_peerIsReady = 1'h0; + biasWorker_wsiM_reqFifo_c_r = 2'h2; + biasWorker_wsiM_reqFifo_q_0 = 61'h0AAAAAAAAAAAAAAA; + biasWorker_wsiM_reqFifo_q_1 = 61'h0AAAAAAAAAAAAAAA; + biasWorker_wsiM_sThreadBusy_d = 1'h0; + biasWorker_wsiM_statusR = 8'hAA; + biasWorker_wsiM_tBusyCount = 32'hAAAAAAAA; + biasWorker_wsiM_trafficSticky = 1'h0; + biasWorker_wsiS_burstKind = 2'h2; + biasWorker_wsiS_errorSticky = 1'h0; + biasWorker_wsiS_iMesgCount = 32'hAAAAAAAA; + biasWorker_wsiS_isReset_isInReset = 1'h0; + biasWorker_wsiS_mesgWordLength = 12'hAAA; + biasWorker_wsiS_operateD = 1'h0; + biasWorker_wsiS_pMesgCount = 32'hAAAAAAAA; + biasWorker_wsiS_peerIsReady = 1'h0; + biasWorker_wsiS_reqFifo_countReg = 2'h2; + biasWorker_wsiS_reqFifo_levelsValid = 1'h0; + biasWorker_wsiS_statusR = 8'hAA; + biasWorker_wsiS_tBusyCount = 32'hAAAAAAAA; + biasWorker_wsiS_trafficSticky = 1'h0; + biasWorker_wsiS_wordCount = 12'hAAA; + dstDataOut = 32'hAAAAAAAA; + dstMesgCount = 16'hAAAA; + dstUnrollCnt = 16'hAAAA; + enWsiChecker = 1'h0; + enWsiSource = 1'h0; + goodDataCnt = 32'hAAAAAAAA; + goodMesgCnt = 32'hAAAAAAAA; + mesgHadError = 1'h0; + simCycle = 16'hAAAA; + srcDataOut = 32'hAAAAAAAA; + srcMesgCount = 16'hAAAA; + srcUnrollCnt = 16'hAAAA; + testOperating = 1'h0; + wciSeqFsm_start_reg = 1'h0; + wciSeqFsm_start_reg_1 = 1'h0; + wciSeqFsm_state_can_overlap = 1'h0; + wciSeqFsm_state_fired = 1'h0; + wciSeqFsm_state_mkFSMstate = 5'h0A; + wciSeqOnce_onceReady = 1'h0; + wci_busy = 1'h0; + wci_lastConfigAddr = 33'h0AAAAAAAA; + wci_lastConfigBE = 5'h0A; + wci_lastControlOp = 4'hA; + wci_lastOpWrite = 2'h2; + wci_mFlagReg = 2'h2; + wci_pageWindow = 12'hAAA; + wci_reqERR = 3'h2; + wci_reqFAIL = 3'h2; + wci_reqF_c_r = 1'h0; + wci_reqF_q_0 = 72'hAAAAAAAAAAAAAAAAAA; + wci_reqPend = 2'h2; + wci_reqTO = 3'h2; + wci_respTimr = 32'hAAAAAAAA; + wci_respTimrAct = 1'h0; + wci_sThreadBusy_d = 1'h0; + wci_sfCap = 1'h0; + wci_sfCapClear = 1'h0; + wci_sfCapSet = 1'h0; + wci_slvPresent = 1'h0; + wci_wReset_n = 1'h0; + wci_wStatus = 32'hAAAAAAAA; + wci_wTimeout = 5'h0A; + wsiM_burstKind = 2'h2; + wsiM_errorSticky = 1'h0; + wsiM_iMesgCount = 32'hAAAAAAAA; + wsiM_isReset_isInReset = 1'h0; + wsiM_operateD = 1'h0; + wsiM_pMesgCount = 32'hAAAAAAAA; + wsiM_peerIsReady = 1'h0; + wsiM_reqFifo_c_r = 2'h2; + wsiM_reqFifo_q_0 = 61'h0AAAAAAAAAAAAAAA; + wsiM_reqFifo_q_1 = 61'h0AAAAAAAAAAAAAAA; + wsiM_sThreadBusy_d = 1'h0; + wsiM_statusR = 8'hAA; + wsiM_tBusyCount = 32'hAAAAAAAA; + wsiM_trafficSticky = 1'h0; + wsiS_burstKind = 2'h2; + wsiS_errorSticky = 1'h0; + wsiS_iMesgCount = 32'hAAAAAAAA; + wsiS_isReset_isInReset = 1'h0; + wsiS_mesgWordLength = 12'hAAA; + wsiS_operateD = 1'h0; + wsiS_pMesgCount = 32'hAAAAAAAA; + wsiS_peerIsReady = 1'h0; + wsiS_reqFifo_countReg = 2'h2; + wsiS_reqFifo_levelsValid = 1'h0; + wsiS_statusR = 8'hAA; + wsiS_tBusyCount = 32'hAAAAAAAA; + wsiS_trafficSticky = 1'h0; + wsiS_wordCount = 12'hAAA; + end + `endif // BSV_NO_INITIAL_BLOCKS + // synopsys translate_on + + // handling of system tasks + + // synopsys translate_off + always@(negedge CLK) + begin + #0; + if (RST_N != `BSV_RESET_VALUE) + if (wsiM_reqFifo_enqueueing$whas && srcUnrollCnt == 16'd1) + begin + v__h66131 = $time; + #0; + end + if (RST_N != `BSV_RESET_VALUE) + if (wsiM_reqFifo_enqueueing$whas && srcUnrollCnt == 16'd1) + $display("[%0d]: %m: wsi_source: End of WSI Producer Egress: srcMesgCount:%0x opcode:%0x", + v__h66131, + srcMesgCount, + 8'd0); + if (RST_N != `BSV_RESET_VALUE) + if (simCycle == 16'd1000) + begin + v__h66773 = $time; + #0; + end + if (RST_N != `BSV_RESET_VALUE) + if (simCycle == 16'd1000) + $display("[%0d]: %m: mkTB1 termination", v__h66773); + if (RST_N != `BSV_RESET_VALUE) + if (simCycle == 16'd1000) $display("goodDataCnt:%08x", goodDataCnt); + if (RST_N != `BSV_RESET_VALUE) + if (simCycle == 16'd1000) $display("goodMesgCnt:%08x", goodMesgCnt); + if (RST_N != `BSV_RESET_VALUE) + if (simCycle == 16'd1000) $display("badDataCnt :%08x", badDataCnt); + if (RST_N != `BSV_RESET_VALUE) + if (simCycle == 16'd1000) $display("badMesgCnt :%08x", badMesgCnt); + if (RST_N != `BSV_RESET_VALUE) + if (simCycle == 16'd1000 && badDataCnt == 32'd0) + $display("mkTB1 PASSED OK"); + if (RST_N != `BSV_RESET_VALUE) + if (simCycle == 16'd1000 && badDataCnt != 32'd0) + $display("mkTB1 had %d ERRORS and FAILED", badDataCnt); + if (RST_N != `BSV_RESET_VALUE) if (simCycle == 16'd1000) $finish(32'd1); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_wrkBusy && + biasWorker_wci_wslv_respF_q_0[33:32] == 2'd0 && + !wci_respTimr_7_ULT_1_SL_wci_wTimeout_8_9___d969 && + wci_reqPend == 2'd1) + begin + v__h2879 = $time; + #0; + end + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_wrkBusy && + biasWorker_wci_wslv_respF_q_0[33:32] == 2'd0 && + !wci_respTimr_7_ULT_1_SL_wci_wTimeout_8_9___d969 && + wci_reqPend == 2'd1) + $display("[%0d]: %m: WORKER CONFIG-WRITE TIMEOUT", v__h2879); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_wrkBusy && + biasWorker_wci_wslv_respF_q_0[33:32] == 2'd0 && + !wci_respTimr_7_ULT_1_SL_wci_wTimeout_8_9___d969 && + wci_reqPend == 2'd2) + begin + v__h2969 = $time; + #0; + end + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_wrkBusy && + biasWorker_wci_wslv_respF_q_0[33:32] == 2'd0 && + !wci_respTimr_7_ULT_1_SL_wci_wTimeout_8_9___d969 && + wci_reqPend == 2'd2) + $display("[%0d]: %m: WORKER CONFIG-READ TIMEOUT", v__h2969); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_wrkBusy && + biasWorker_wci_wslv_respF_q_0[33:32] == 2'd0 && + !wci_respTimr_7_ULT_1_SL_wci_wTimeout_8_9___d969 && + wci_reqPend == 2'd3) + begin + v__h3058 = $time; + #0; + end + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_wrkBusy && + biasWorker_wci_wslv_respF_q_0[33:32] == 2'd0 && + !wci_respTimr_7_ULT_1_SL_wci_wTimeout_8_9___d969 && + wci_reqPend == 2'd3) + $display("[%0d]: %m: WORKER CONTROL-OP TIMEOUT", v__h3058); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_wrkBusy && + biasWorker_wci_wslv_respF_q_0[33:32] == 2'd2 && + wci_reqPend == 2'd1) + begin + v__h3282 = $time; + #0; + end + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_wrkBusy && + biasWorker_wci_wslv_respF_q_0[33:32] == 2'd2 && + wci_reqPend == 2'd1) + $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-FAIL", v__h3282); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_wrkBusy && + biasWorker_wci_wslv_respF_q_0[33:32] == 2'd2 && + wci_reqPend == 2'd2) + begin + v__h3372 = $time; + #0; + end + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_wrkBusy && + biasWorker_wci_wslv_respF_q_0[33:32] == 2'd2 && + wci_reqPend == 2'd2) + $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-FAIL", v__h3372); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_wrkBusy && + biasWorker_wci_wslv_respF_q_0[33:32] == 2'd2 && + wci_reqPend == 2'd3) + begin + v__h3461 = $time; + #0; + end + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_wrkBusy && + biasWorker_wci_wslv_respF_q_0[33:32] == 2'd2 && + wci_reqPend == 2'd3) + $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-FAIL", v__h3461); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_wrkBusy && + biasWorker_wci_wslv_respF_q_0[33:32] == 2'd3 && + wci_reqPend == 2'd1) + begin + v__h3690 = $time; + #0; + end + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_wrkBusy && + biasWorker_wci_wslv_respF_q_0[33:32] == 2'd3 && + wci_reqPend == 2'd1) + $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-ERR", v__h3690); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_wrkBusy && + biasWorker_wci_wslv_respF_q_0[33:32] == 2'd3 && + wci_reqPend == 2'd2) + begin + v__h3780 = $time; + #0; + end + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_wrkBusy && + biasWorker_wci_wslv_respF_q_0[33:32] == 2'd3 && + wci_reqPend == 2'd2) + $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-ERR", v__h3780); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_wrkBusy && + biasWorker_wci_wslv_respF_q_0[33:32] == 2'd3 && + wci_reqPend == 2'd3) + begin + v__h3869 = $time; + #0; + end + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_wrkBusy && + biasWorker_wci_wslv_respF_q_0[33:32] == 2'd3 && + wci_reqPend == 2'd3) + $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-ERR", v__h3869); + if (RST_N != `BSV_RESET_VALUE) + if (MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 && + !wsiS_reqFifo_first__99_BITS_43_TO_12_00_EQ_dst_ETC___d943) + begin + v__h66381 = $time; + #0; + end + if (RST_N != `BSV_RESET_VALUE) + if (MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 && + !wsiS_reqFifo_first__99_BITS_43_TO_12_00_EQ_dst_ETC___d943) + $display("[%0d]: %m: wsi_checker MISMATCH: exp:%0x got:%0x srcMesgCount:%0x", + v__h66381, + dstDataOut, + wsiS_reqFifo$D_OUT[43:12], + dstMesgCount); + if (RST_N != `BSV_RESET_VALUE) + if (MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 && + dstUnrollCnt == 16'd1) + begin + v__h66575 = $time; + #0; + end + if (RST_N != `BSV_RESET_VALUE) + if (MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 && + dstUnrollCnt == 16'd1) + $display("[%0d]: %m: wsi_source: End of WSI Consumer Ingress: dstMesgCount:%0x opcode:%0x", + v__h66575, + dstMesgCount, + wsiS_reqFifo$D_OUT[7:0]); + if (wci_mReset$OUT_RST != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_biasWorker_wci_wslv_ctl_op_start) + begin + v__h13915 = $time; + #0; + end + if (wci_mReset$OUT_RST != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_biasWorker_wci_wslv_ctl_op_start) + $display("[%0d]: %m: WCI ControlOp: Starting-transition edge:%x from:%x", + v__h13915, + biasWorker_wci_wslv_reqF$D_OUT[36:34], + biasWorker_wci_wslv_cState); + if (wci_mReset$OUT_RST != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_biasWorker_wci_ctrl_EiI && + WILL_FIRE_RL_biasWorker_wci_ctrl_OrE) + $display("Error: \"bsv/wrk/BiasWorker.bsv\", line 67, column 48: (R0001)\n Mutually exclusive rules (from the ME sets [RL_biasWorker_wci_ctrl_EiI] and\n [RL_biasWorker_wci_ctrl_OrE] ) fired in the same clock cycle.\n"); + if (wci_mReset$OUT_RST != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_biasWorker_wci_ctrl_EiI && + WILL_FIRE_RL_biasWorker_wci_ctrl_IsO) + $display("Error: \"bsv/wrk/BiasWorker.bsv\", line 67, column 48: (R0001)\n Mutually exclusive rules (from the ME sets [RL_biasWorker_wci_ctrl_EiI] and\n [RL_biasWorker_wci_ctrl_IsO] ) fired in the same clock cycle.\n"); + if (wci_mReset$OUT_RST != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_biasWorker_wci_ctrl_IsO && + WILL_FIRE_RL_biasWorker_wci_ctrl_OrE) + $display("Error: \"bsv/wrk/BiasWorker.bsv\", line 67, column 62: (R0001)\n Mutually exclusive rules (from the ME sets [RL_biasWorker_wci_ctrl_IsO] and\n [RL_biasWorker_wci_ctrl_OrE] ) fired in the same clock cycle.\n"); + if (wci_mReset$OUT_RST != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_biasWorker_wci_cfwr) + begin + v__h21121 = $time; + #0; + end + if (wci_mReset$OUT_RST != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_biasWorker_wci_cfwr) + $display("[%0d]: %m: WCI CONFIG WRITE Addr:%0x BE:%0x Data:%0x", + v__h21121, + biasWorker_wci_wslv_reqF$D_OUT[63:32], + biasWorker_wci_wslv_reqF$D_OUT[67:64], + biasWorker_wci_wslv_reqF$D_OUT[31:0]); + if (wci_mReset$OUT_RST != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_biasWorker_wci_wslv_ctl_op_complete && + biasWorker_wci_wslv_illegalEdge) + begin + v__h14234 = $time; + #0; + end + if (wci_mReset$OUT_RST != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_biasWorker_wci_wslv_ctl_op_complete && + biasWorker_wci_wslv_illegalEdge) + $display("[%0d]: %m: WCI ControlOp: ILLEGAL-EDGE Completed-transition edge:%x from:%x", + v__h14234, + biasWorker_wci_wslv_cEdge, + biasWorker_wci_wslv_cState); + if (wci_mReset$OUT_RST != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_biasWorker_wci_wslv_ctl_op_complete && + !biasWorker_wci_wslv_illegalEdge) + begin + v__h14090 = $time; + #0; + end + if (wci_mReset$OUT_RST != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_biasWorker_wci_wslv_ctl_op_complete && + !biasWorker_wci_wslv_illegalEdge) + $display("[%0d]: %m: WCI ControlOp: Completed-transition edge:%x from:%x to:%x", + v__h14090, + biasWorker_wci_wslv_cEdge, + biasWorker_wci_wslv_cState, + biasWorker_wci_wslv_nState); + if (wci_mReset$OUT_RST != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_biasWorker_wci_cfrd) + begin + v__h21276 = $time; + #0; + end + if (wci_mReset$OUT_RST != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_biasWorker_wci_cfrd) + $display("[%0d]: %m: WCI CONFIG READ Addr:%0x BE:%0x Data:%0x", + v__h21276, + biasWorker_wci_wslv_reqF$D_OUT[63:32], + biasWorker_wci_wslv_reqF$D_OUT[67:64], + _theResult____h21260); + if (wci_mReset$OUT_RST != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_biasWorker_wci_cfwr && + WILL_FIRE_RL_biasWorker_wci_ctrl_OrE) + $display("Error: \"bsv/wrk/BiasWorker.bsv\", line 67, column 28: (R0001)\n Mutually exclusive rules (from the ME sets [RL_biasWorker_wci_cfwr] and\n [RL_biasWorker_wci_ctrl_OrE] ) fired in the same clock cycle.\n"); + if (wci_mReset$OUT_RST != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_biasWorker_wci_cfwr && + WILL_FIRE_RL_biasWorker_wci_ctrl_IsO) + $display("Error: \"bsv/wrk/BiasWorker.bsv\", line 67, column 28: (R0001)\n Mutually exclusive rules (from the ME sets [RL_biasWorker_wci_cfwr] and\n [RL_biasWorker_wci_ctrl_IsO] ) fired in the same clock cycle.\n"); + if (wci_mReset$OUT_RST != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_biasWorker_wci_cfwr && + WILL_FIRE_RL_biasWorker_wci_ctrl_EiI) + $display("Error: \"bsv/wrk/BiasWorker.bsv\", line 67, column 28: (R0001)\n Mutually exclusive rules (from the ME sets [RL_biasWorker_wci_cfwr] and\n [RL_biasWorker_wci_ctrl_EiI] ) fired in the same clock cycle.\n"); + if (wci_mReset$OUT_RST != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_biasWorker_wci_cfwr && + WILL_FIRE_RL_biasWorker_wci_cfrd) + $display("Error: \"bsv/wrk/BiasWorker.bsv\", line 67, column 28: (R0001)\n Mutually exclusive rules (from the ME sets [RL_biasWorker_wci_cfwr] and\n [RL_biasWorker_wci_cfrd] ) fired in the same clock cycle.\n"); + if (wci_mReset$OUT_RST != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_biasWorker_wci_cfrd && + WILL_FIRE_RL_biasWorker_wci_ctrl_OrE) + $display("Error: \"bsv/wrk/BiasWorker.bsv\", line 67, column 38: (R0001)\n Mutually exclusive rules (from the ME sets [RL_biasWorker_wci_cfrd] and\n [RL_biasWorker_wci_ctrl_OrE] ) fired in the same clock cycle.\n"); + if (wci_mReset$OUT_RST != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_biasWorker_wci_cfrd && + WILL_FIRE_RL_biasWorker_wci_ctrl_IsO) + $display("Error: \"bsv/wrk/BiasWorker.bsv\", line 67, column 38: (R0001)\n Mutually exclusive rules (from the ME sets [RL_biasWorker_wci_cfrd] and\n [RL_biasWorker_wci_ctrl_IsO] ) fired in the same clock cycle.\n"); + if (wci_mReset$OUT_RST != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_biasWorker_wci_cfrd && + WILL_FIRE_RL_biasWorker_wci_ctrl_EiI) + $display("Error: \"bsv/wrk/BiasWorker.bsv\", line 67, column 38: (R0001)\n Mutually exclusive rules (from the ME sets [RL_biasWorker_wci_cfrd] and\n [RL_biasWorker_wci_ctrl_EiI] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (wciSeqFsm_state_mkFSMstate == 5'd2) + begin + v__h58288 = $time; + #0; + end + if (RST_N != `BSV_RESET_VALUE) + if (wciSeqFsm_state_mkFSMstate == 5'd2) + $display("[%0d]: %m: Taking DUT out of Reset...", v__h58288); + if (RST_N != `BSV_RESET_VALUE) + if (wciSeqFsm_state_mkFSMstate == 5'd5) + begin + v__h59334 = $time; + #0; + end + if (RST_N != `BSV_RESET_VALUE) + if (wciSeqFsm_state_mkFSMstate == 5'd5) + $display("[%0d]: %m: CONTROL-OP: -INITIALIZE- DUT...", v__h59334); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wciSeqFsm_action_l58c8) + begin + v__h59639 = $time; + #0; + end + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wciSeqFsm_action_l58c8) + $display("[%0d]: %m: WORKER CONTROL ARM...", v__h59639); + if (RST_N != `BSV_RESET_VALUE) + if (wciSeqFsm_state_mkFSMstate == 5'd8) + begin + v__h60412 = $time; + #0; + end + if (RST_N != `BSV_RESET_VALUE) + if (wciSeqFsm_state_mkFSMstate == 5'd8) + $display("[%0d]: %m: Write Dataplane Config Properties...", + v__h60412); + if (RST_N != `BSV_RESET_VALUE) + if (wciSeqFsm_state_mkFSMstate == 5'd11) + begin + v__h61491 = $time; + #0; + end + if (RST_N != `BSV_RESET_VALUE) + if (wciSeqFsm_state_mkFSMstate == 5'd11) + $display("[%0d]: %m: Read Dataplane Config Properties...", v__h61491); + if (RST_N != `BSV_RESET_VALUE) + if (wciSeqFsm_state_mkFSMstate == 5'd14) + begin + v__h62651 = $time; + #0; + end + if (RST_N != `BSV_RESET_VALUE) + if (wciSeqFsm_state_mkFSMstate == 5'd14) + $display("[%0d]: %m: CONTROL-OP: -START- DUT...", v__h62651); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wciSeqFsm_action_l70c8) + begin + v__h63028 = $time; + #0; + end + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wciSeqFsm_action_l70c8) + $display("[%0d]: %m: WORKER CONTROL ARM...", v__h63028); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wciSeqFsm_action_l51c10 && + (wciSeqFsm_state_mkFSMstate == 5'd2 || + WILL_FIRE_RL_wciSeqFsm_action_l54c8 || + WILL_FIRE_RL_wciSeqFsm_action_l55c5 || + wciSeqFsm_state_mkFSMstate == 5'd5 || + WILL_FIRE_RL_wciSeqFsm_action_l58c8 || + WILL_FIRE_RL_wciSeqFsm_action_l59c5 || + wciSeqFsm_state_mkFSMstate == 5'd8 || + WILL_FIRE_RL_wciSeqFsm_action_l62c8 || + WILL_FIRE_RL_wciSeqFsm_action_l63c5 || + wciSeqFsm_state_mkFSMstate == 5'd11 || + WILL_FIRE_RL_wciSeqFsm_action_l66c8 || + WILL_FIRE_RL_wciSeqFsm_action_l67c5 || + wciSeqFsm_state_mkFSMstate == 5'd14 || + WILL_FIRE_RL_wciSeqFsm_action_l70c8 || + WILL_FIRE_RL_wciSeqFsm_action_l71c5 || + wciSeqFsm_state_mkFSMstate == 5'd17 || + wciSeqFsm_state_mkFSMstate == 5'd18 || + wciSeqFsm_state_mkFSMstate == 5'd19 || + wciSeqFsm_state_mkFSMstate == 5'd20 || + wciSeqFsm_state_mkFSMstate == 5'd21)) + $display("Error: \"bsv/tst/TB1.bsv\", line 51, column 10: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wciSeqFsm_action_l51c10] and\n [RL_wciSeqFsm_action_l53c5, RL_wciSeqFsm_action_l54c8,\n RL_wciSeqFsm_action_l55c5, RL_wciSeqFsm_action_l57c5,\n RL_wciSeqFsm_action_l58c8, RL_wciSeqFsm_action_l59c5,\n RL_wciSeqFsm_action_l61c5, RL_wciSeqFsm_action_l62c8,\n RL_wciSeqFsm_action_l63c5, RL_wciSeqFsm_action_l65c5,\n RL_wciSeqFsm_action_l66c8, RL_wciSeqFsm_action_l67c5,\n RL_wciSeqFsm_action_l69c5, RL_wciSeqFsm_action_l70c8,\n RL_wciSeqFsm_action_l71c5, RL_wciSeqFsm_action_l73c19,\n RL_wciSeqFsm_action_l74c19, RL_wciSeqFsm_action_l75c19,\n RL_wciSeqFsm_action_l76c19, RL_wciSeqFsm_action_l77c19] ) fired in the same\n clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (wciSeqFsm_state_mkFSMstate == 5'd2 && + (WILL_FIRE_RL_wciSeqFsm_action_l54c8 || + WILL_FIRE_RL_wciSeqFsm_action_l55c5 || + wciSeqFsm_state_mkFSMstate == 5'd5 || + WILL_FIRE_RL_wciSeqFsm_action_l58c8 || + WILL_FIRE_RL_wciSeqFsm_action_l59c5 || + wciSeqFsm_state_mkFSMstate == 5'd8 || + WILL_FIRE_RL_wciSeqFsm_action_l62c8 || + WILL_FIRE_RL_wciSeqFsm_action_l63c5 || + wciSeqFsm_state_mkFSMstate == 5'd11 || + WILL_FIRE_RL_wciSeqFsm_action_l66c8 || + WILL_FIRE_RL_wciSeqFsm_action_l67c5 || + wciSeqFsm_state_mkFSMstate == 5'd14 || + WILL_FIRE_RL_wciSeqFsm_action_l70c8 || + WILL_FIRE_RL_wciSeqFsm_action_l71c5 || + wciSeqFsm_state_mkFSMstate == 5'd17 || + wciSeqFsm_state_mkFSMstate == 5'd18 || + wciSeqFsm_state_mkFSMstate == 5'd19 || + wciSeqFsm_state_mkFSMstate == 5'd20 || + wciSeqFsm_state_mkFSMstate == 5'd21)) + $display("Error: \"bsv/tst/TB1.bsv\", line 53, column 5: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wciSeqFsm_action_l53c5] and\n [RL_wciSeqFsm_action_l54c8, RL_wciSeqFsm_action_l55c5,\n RL_wciSeqFsm_action_l57c5, RL_wciSeqFsm_action_l58c8,\n RL_wciSeqFsm_action_l59c5, RL_wciSeqFsm_action_l61c5,\n RL_wciSeqFsm_action_l62c8, RL_wciSeqFsm_action_l63c5,\n RL_wciSeqFsm_action_l65c5, RL_wciSeqFsm_action_l66c8,\n RL_wciSeqFsm_action_l67c5, RL_wciSeqFsm_action_l69c5,\n RL_wciSeqFsm_action_l70c8, RL_wciSeqFsm_action_l71c5,\n RL_wciSeqFsm_action_l73c19, RL_wciSeqFsm_action_l74c19,\n RL_wciSeqFsm_action_l75c19, RL_wciSeqFsm_action_l76c19,\n RL_wciSeqFsm_action_l77c19] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wciSeqFsm_action_l54c8 && + (WILL_FIRE_RL_wciSeqFsm_action_l55c5 || + wciSeqFsm_state_mkFSMstate == 5'd5 || + WILL_FIRE_RL_wciSeqFsm_action_l58c8 || + WILL_FIRE_RL_wciSeqFsm_action_l59c5 || + wciSeqFsm_state_mkFSMstate == 5'd8 || + WILL_FIRE_RL_wciSeqFsm_action_l62c8 || + WILL_FIRE_RL_wciSeqFsm_action_l63c5 || + wciSeqFsm_state_mkFSMstate == 5'd11 || + WILL_FIRE_RL_wciSeqFsm_action_l66c8 || + WILL_FIRE_RL_wciSeqFsm_action_l67c5 || + wciSeqFsm_state_mkFSMstate == 5'd14 || + WILL_FIRE_RL_wciSeqFsm_action_l70c8 || + WILL_FIRE_RL_wciSeqFsm_action_l71c5 || + wciSeqFsm_state_mkFSMstate == 5'd17 || + wciSeqFsm_state_mkFSMstate == 5'd18 || + wciSeqFsm_state_mkFSMstate == 5'd19 || + wciSeqFsm_state_mkFSMstate == 5'd20 || + wciSeqFsm_state_mkFSMstate == 5'd21)) + $display("Error: \"bsv/tst/TB1.bsv\", line 54, column 8: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wciSeqFsm_action_l54c8] and\n [RL_wciSeqFsm_action_l55c5, RL_wciSeqFsm_action_l57c5,\n RL_wciSeqFsm_action_l58c8, RL_wciSeqFsm_action_l59c5,\n RL_wciSeqFsm_action_l61c5, RL_wciSeqFsm_action_l62c8,\n RL_wciSeqFsm_action_l63c5, RL_wciSeqFsm_action_l65c5,\n RL_wciSeqFsm_action_l66c8, RL_wciSeqFsm_action_l67c5,\n RL_wciSeqFsm_action_l69c5, RL_wciSeqFsm_action_l70c8,\n RL_wciSeqFsm_action_l71c5, RL_wciSeqFsm_action_l73c19,\n RL_wciSeqFsm_action_l74c19, RL_wciSeqFsm_action_l75c19,\n RL_wciSeqFsm_action_l76c19, RL_wciSeqFsm_action_l77c19] ) fired in the same\n clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (wciSeqFsm_state_mkFSMstate == 5'd5 && + (WILL_FIRE_RL_wciSeqFsm_action_l58c8 || + WILL_FIRE_RL_wciSeqFsm_action_l59c5 || + wciSeqFsm_state_mkFSMstate == 5'd8 || + WILL_FIRE_RL_wciSeqFsm_action_l62c8 || + WILL_FIRE_RL_wciSeqFsm_action_l63c5 || + wciSeqFsm_state_mkFSMstate == 5'd11 || + WILL_FIRE_RL_wciSeqFsm_action_l66c8 || + WILL_FIRE_RL_wciSeqFsm_action_l67c5 || + wciSeqFsm_state_mkFSMstate == 5'd14 || + WILL_FIRE_RL_wciSeqFsm_action_l70c8 || + WILL_FIRE_RL_wciSeqFsm_action_l71c5 || + wciSeqFsm_state_mkFSMstate == 5'd17 || + wciSeqFsm_state_mkFSMstate == 5'd18 || + wciSeqFsm_state_mkFSMstate == 5'd19 || + wciSeqFsm_state_mkFSMstate == 5'd20 || + wciSeqFsm_state_mkFSMstate == 5'd21)) + $display("Error: \"bsv/tst/TB1.bsv\", line 57, column 5: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wciSeqFsm_action_l57c5] and\n [RL_wciSeqFsm_action_l58c8, RL_wciSeqFsm_action_l59c5,\n RL_wciSeqFsm_action_l61c5, RL_wciSeqFsm_action_l62c8,\n RL_wciSeqFsm_action_l63c5, RL_wciSeqFsm_action_l65c5,\n RL_wciSeqFsm_action_l66c8, RL_wciSeqFsm_action_l67c5,\n RL_wciSeqFsm_action_l69c5, RL_wciSeqFsm_action_l70c8,\n RL_wciSeqFsm_action_l71c5, RL_wciSeqFsm_action_l73c19,\n RL_wciSeqFsm_action_l74c19, RL_wciSeqFsm_action_l75c19,\n RL_wciSeqFsm_action_l76c19, RL_wciSeqFsm_action_l77c19] ) fired in the same\n clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wciSeqFsm_action_l55c5 && + (wciSeqFsm_state_mkFSMstate == 5'd5 || + WILL_FIRE_RL_wciSeqFsm_action_l58c8 || + WILL_FIRE_RL_wciSeqFsm_action_l59c5 || + wciSeqFsm_state_mkFSMstate == 5'd8 || + WILL_FIRE_RL_wciSeqFsm_action_l62c8 || + WILL_FIRE_RL_wciSeqFsm_action_l63c5 || + wciSeqFsm_state_mkFSMstate == 5'd11 || + WILL_FIRE_RL_wciSeqFsm_action_l66c8 || + WILL_FIRE_RL_wciSeqFsm_action_l67c5 || + wciSeqFsm_state_mkFSMstate == 5'd14 || + WILL_FIRE_RL_wciSeqFsm_action_l70c8 || + WILL_FIRE_RL_wciSeqFsm_action_l71c5 || + wciSeqFsm_state_mkFSMstate == 5'd17 || + wciSeqFsm_state_mkFSMstate == 5'd18 || + wciSeqFsm_state_mkFSMstate == 5'd19 || + wciSeqFsm_state_mkFSMstate == 5'd20 || + wciSeqFsm_state_mkFSMstate == 5'd21)) + $display("Error: \"bsv/tst/TB1.bsv\", line 55, column 5: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wciSeqFsm_action_l55c5] and\n [RL_wciSeqFsm_action_l57c5, RL_wciSeqFsm_action_l58c8,\n RL_wciSeqFsm_action_l59c5, RL_wciSeqFsm_action_l61c5,\n RL_wciSeqFsm_action_l62c8, RL_wciSeqFsm_action_l63c5,\n RL_wciSeqFsm_action_l65c5, RL_wciSeqFsm_action_l66c8,\n RL_wciSeqFsm_action_l67c5, RL_wciSeqFsm_action_l69c5,\n RL_wciSeqFsm_action_l70c8, RL_wciSeqFsm_action_l71c5,\n RL_wciSeqFsm_action_l73c19, RL_wciSeqFsm_action_l74c19,\n RL_wciSeqFsm_action_l75c19, RL_wciSeqFsm_action_l76c19,\n RL_wciSeqFsm_action_l77c19] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wciSeqFsm_action_l58c8 && + (WILL_FIRE_RL_wciSeqFsm_action_l59c5 || + wciSeqFsm_state_mkFSMstate == 5'd8 || + WILL_FIRE_RL_wciSeqFsm_action_l62c8 || + WILL_FIRE_RL_wciSeqFsm_action_l63c5 || + wciSeqFsm_state_mkFSMstate == 5'd11 || + WILL_FIRE_RL_wciSeqFsm_action_l66c8 || + WILL_FIRE_RL_wciSeqFsm_action_l67c5 || + wciSeqFsm_state_mkFSMstate == 5'd14 || + WILL_FIRE_RL_wciSeqFsm_action_l70c8 || + WILL_FIRE_RL_wciSeqFsm_action_l71c5 || + wciSeqFsm_state_mkFSMstate == 5'd17 || + wciSeqFsm_state_mkFSMstate == 5'd18 || + wciSeqFsm_state_mkFSMstate == 5'd19 || + wciSeqFsm_state_mkFSMstate == 5'd20 || + wciSeqFsm_state_mkFSMstate == 5'd21)) + $display("Error: \"bsv/tst/TB1.bsv\", line 58, column 8: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wciSeqFsm_action_l58c8] and\n [RL_wciSeqFsm_action_l59c5, RL_wciSeqFsm_action_l61c5,\n RL_wciSeqFsm_action_l62c8, RL_wciSeqFsm_action_l63c5,\n RL_wciSeqFsm_action_l65c5, RL_wciSeqFsm_action_l66c8,\n RL_wciSeqFsm_action_l67c5, RL_wciSeqFsm_action_l69c5,\n RL_wciSeqFsm_action_l70c8, RL_wciSeqFsm_action_l71c5,\n RL_wciSeqFsm_action_l73c19, RL_wciSeqFsm_action_l74c19,\n RL_wciSeqFsm_action_l75c19, RL_wciSeqFsm_action_l76c19,\n RL_wciSeqFsm_action_l77c19] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wciSeqFsm_action_l59c5 && + (wciSeqFsm_state_mkFSMstate == 5'd8 || + WILL_FIRE_RL_wciSeqFsm_action_l62c8 || + WILL_FIRE_RL_wciSeqFsm_action_l63c5 || + wciSeqFsm_state_mkFSMstate == 5'd11 || + WILL_FIRE_RL_wciSeqFsm_action_l66c8 || + WILL_FIRE_RL_wciSeqFsm_action_l67c5 || + wciSeqFsm_state_mkFSMstate == 5'd14 || + WILL_FIRE_RL_wciSeqFsm_action_l70c8 || + WILL_FIRE_RL_wciSeqFsm_action_l71c5 || + wciSeqFsm_state_mkFSMstate == 5'd17 || + wciSeqFsm_state_mkFSMstate == 5'd18 || + wciSeqFsm_state_mkFSMstate == 5'd19 || + wciSeqFsm_state_mkFSMstate == 5'd20 || + wciSeqFsm_state_mkFSMstate == 5'd21)) + $display("Error: \"bsv/tst/TB1.bsv\", line 59, column 5: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wciSeqFsm_action_l59c5] and\n [RL_wciSeqFsm_action_l61c5, RL_wciSeqFsm_action_l62c8,\n RL_wciSeqFsm_action_l63c5, RL_wciSeqFsm_action_l65c5,\n RL_wciSeqFsm_action_l66c8, RL_wciSeqFsm_action_l67c5,\n RL_wciSeqFsm_action_l69c5, RL_wciSeqFsm_action_l70c8,\n RL_wciSeqFsm_action_l71c5, RL_wciSeqFsm_action_l73c19,\n RL_wciSeqFsm_action_l74c19, RL_wciSeqFsm_action_l75c19,\n RL_wciSeqFsm_action_l76c19, RL_wciSeqFsm_action_l77c19] ) fired in the same\n clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wciSeqFsm_action_l62c8 && + (WILL_FIRE_RL_wciSeqFsm_action_l63c5 || + wciSeqFsm_state_mkFSMstate == 5'd11 || + WILL_FIRE_RL_wciSeqFsm_action_l66c8 || + WILL_FIRE_RL_wciSeqFsm_action_l67c5 || + wciSeqFsm_state_mkFSMstate == 5'd14 || + WILL_FIRE_RL_wciSeqFsm_action_l70c8 || + WILL_FIRE_RL_wciSeqFsm_action_l71c5 || + wciSeqFsm_state_mkFSMstate == 5'd17 || + wciSeqFsm_state_mkFSMstate == 5'd18 || + wciSeqFsm_state_mkFSMstate == 5'd19 || + wciSeqFsm_state_mkFSMstate == 5'd20 || + wciSeqFsm_state_mkFSMstate == 5'd21)) + $display("Error: \"bsv/tst/TB1.bsv\", line 62, column 8: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wciSeqFsm_action_l62c8] and\n [RL_wciSeqFsm_action_l63c5, RL_wciSeqFsm_action_l65c5,\n RL_wciSeqFsm_action_l66c8, RL_wciSeqFsm_action_l67c5,\n RL_wciSeqFsm_action_l69c5, RL_wciSeqFsm_action_l70c8,\n RL_wciSeqFsm_action_l71c5, RL_wciSeqFsm_action_l73c19,\n RL_wciSeqFsm_action_l74c19, RL_wciSeqFsm_action_l75c19,\n RL_wciSeqFsm_action_l76c19, RL_wciSeqFsm_action_l77c19] ) fired in the same\n clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (wciSeqFsm_state_mkFSMstate == 5'd8 && + (WILL_FIRE_RL_wciSeqFsm_action_l62c8 || + WILL_FIRE_RL_wciSeqFsm_action_l63c5 || + wciSeqFsm_state_mkFSMstate == 5'd11 || + WILL_FIRE_RL_wciSeqFsm_action_l66c8 || + WILL_FIRE_RL_wciSeqFsm_action_l67c5 || + wciSeqFsm_state_mkFSMstate == 5'd14 || + WILL_FIRE_RL_wciSeqFsm_action_l70c8 || + WILL_FIRE_RL_wciSeqFsm_action_l71c5 || + wciSeqFsm_state_mkFSMstate == 5'd17 || + wciSeqFsm_state_mkFSMstate == 5'd18 || + wciSeqFsm_state_mkFSMstate == 5'd19 || + wciSeqFsm_state_mkFSMstate == 5'd20 || + wciSeqFsm_state_mkFSMstate == 5'd21)) + $display("Error: \"bsv/tst/TB1.bsv\", line 61, column 5: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wciSeqFsm_action_l61c5] and\n [RL_wciSeqFsm_action_l62c8, RL_wciSeqFsm_action_l63c5,\n RL_wciSeqFsm_action_l65c5, RL_wciSeqFsm_action_l66c8,\n RL_wciSeqFsm_action_l67c5, RL_wciSeqFsm_action_l69c5,\n RL_wciSeqFsm_action_l70c8, RL_wciSeqFsm_action_l71c5,\n RL_wciSeqFsm_action_l73c19, RL_wciSeqFsm_action_l74c19,\n RL_wciSeqFsm_action_l75c19, RL_wciSeqFsm_action_l76c19,\n RL_wciSeqFsm_action_l77c19] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wciSeqFsm_action_l63c5 && + (wciSeqFsm_state_mkFSMstate == 5'd11 || + WILL_FIRE_RL_wciSeqFsm_action_l66c8 || + WILL_FIRE_RL_wciSeqFsm_action_l67c5 || + wciSeqFsm_state_mkFSMstate == 5'd14 || + WILL_FIRE_RL_wciSeqFsm_action_l70c8 || + WILL_FIRE_RL_wciSeqFsm_action_l71c5 || + wciSeqFsm_state_mkFSMstate == 5'd17 || + wciSeqFsm_state_mkFSMstate == 5'd18 || + wciSeqFsm_state_mkFSMstate == 5'd19 || + wciSeqFsm_state_mkFSMstate == 5'd20 || + wciSeqFsm_state_mkFSMstate == 5'd21)) + $display("Error: \"bsv/tst/TB1.bsv\", line 63, column 5: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wciSeqFsm_action_l63c5] and\n [RL_wciSeqFsm_action_l65c5, RL_wciSeqFsm_action_l66c8,\n RL_wciSeqFsm_action_l67c5, RL_wciSeqFsm_action_l69c5,\n RL_wciSeqFsm_action_l70c8, RL_wciSeqFsm_action_l71c5,\n RL_wciSeqFsm_action_l73c19, RL_wciSeqFsm_action_l74c19,\n RL_wciSeqFsm_action_l75c19, RL_wciSeqFsm_action_l76c19,\n RL_wciSeqFsm_action_l77c19] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wciSeqFsm_action_l66c8 && + (WILL_FIRE_RL_wciSeqFsm_action_l67c5 || + wciSeqFsm_state_mkFSMstate == 5'd14 || + WILL_FIRE_RL_wciSeqFsm_action_l70c8 || + WILL_FIRE_RL_wciSeqFsm_action_l71c5 || + wciSeqFsm_state_mkFSMstate == 5'd17 || + wciSeqFsm_state_mkFSMstate == 5'd18 || + wciSeqFsm_state_mkFSMstate == 5'd19 || + wciSeqFsm_state_mkFSMstate == 5'd20 || + wciSeqFsm_state_mkFSMstate == 5'd21)) + $display("Error: \"bsv/tst/TB1.bsv\", line 66, column 8: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wciSeqFsm_action_l66c8] and\n [RL_wciSeqFsm_action_l67c5, RL_wciSeqFsm_action_l69c5,\n RL_wciSeqFsm_action_l70c8, RL_wciSeqFsm_action_l71c5,\n RL_wciSeqFsm_action_l73c19, RL_wciSeqFsm_action_l74c19,\n RL_wciSeqFsm_action_l75c19, RL_wciSeqFsm_action_l76c19,\n RL_wciSeqFsm_action_l77c19] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (wciSeqFsm_state_mkFSMstate == 5'd11 && + (WILL_FIRE_RL_wciSeqFsm_action_l66c8 || + WILL_FIRE_RL_wciSeqFsm_action_l67c5 || + wciSeqFsm_state_mkFSMstate == 5'd14 || + WILL_FIRE_RL_wciSeqFsm_action_l70c8 || + WILL_FIRE_RL_wciSeqFsm_action_l71c5 || + wciSeqFsm_state_mkFSMstate == 5'd17 || + wciSeqFsm_state_mkFSMstate == 5'd18 || + wciSeqFsm_state_mkFSMstate == 5'd19 || + wciSeqFsm_state_mkFSMstate == 5'd20 || + wciSeqFsm_state_mkFSMstate == 5'd21)) + $display("Error: \"bsv/tst/TB1.bsv\", line 65, column 5: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wciSeqFsm_action_l65c5] and\n [RL_wciSeqFsm_action_l66c8, RL_wciSeqFsm_action_l67c5,\n RL_wciSeqFsm_action_l69c5, RL_wciSeqFsm_action_l70c8,\n RL_wciSeqFsm_action_l71c5, RL_wciSeqFsm_action_l73c19,\n RL_wciSeqFsm_action_l74c19, RL_wciSeqFsm_action_l75c19,\n RL_wciSeqFsm_action_l76c19, RL_wciSeqFsm_action_l77c19] ) fired in the same\n clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wciSeqFsm_action_l67c5 && + (wciSeqFsm_state_mkFSMstate == 5'd14 || + WILL_FIRE_RL_wciSeqFsm_action_l70c8 || + WILL_FIRE_RL_wciSeqFsm_action_l71c5 || + wciSeqFsm_state_mkFSMstate == 5'd17 || + wciSeqFsm_state_mkFSMstate == 5'd18 || + wciSeqFsm_state_mkFSMstate == 5'd19 || + wciSeqFsm_state_mkFSMstate == 5'd20 || + wciSeqFsm_state_mkFSMstate == 5'd21)) + $display("Error: \"bsv/tst/TB1.bsv\", line 67, column 5: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wciSeqFsm_action_l67c5] and\n [RL_wciSeqFsm_action_l69c5, RL_wciSeqFsm_action_l70c8,\n RL_wciSeqFsm_action_l71c5, RL_wciSeqFsm_action_l73c19,\n RL_wciSeqFsm_action_l74c19, RL_wciSeqFsm_action_l75c19,\n RL_wciSeqFsm_action_l76c19, RL_wciSeqFsm_action_l77c19] ) fired in the same\n clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (wciSeqFsm_state_mkFSMstate == 5'd14 && + (WILL_FIRE_RL_wciSeqFsm_action_l70c8 || + WILL_FIRE_RL_wciSeqFsm_action_l71c5 || + wciSeqFsm_state_mkFSMstate == 5'd17 || + wciSeqFsm_state_mkFSMstate == 5'd18 || + wciSeqFsm_state_mkFSMstate == 5'd19 || + wciSeqFsm_state_mkFSMstate == 5'd20 || + wciSeqFsm_state_mkFSMstate == 5'd21)) + $display("Error: \"bsv/tst/TB1.bsv\", line 69, column 5: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wciSeqFsm_action_l69c5] and\n [RL_wciSeqFsm_action_l70c8, RL_wciSeqFsm_action_l71c5,\n RL_wciSeqFsm_action_l73c19, RL_wciSeqFsm_action_l74c19,\n RL_wciSeqFsm_action_l75c19, RL_wciSeqFsm_action_l76c19,\n RL_wciSeqFsm_action_l77c19] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wciSeqFsm_action_l71c5 && + (wciSeqFsm_state_mkFSMstate == 5'd17 || + wciSeqFsm_state_mkFSMstate == 5'd18 || + wciSeqFsm_state_mkFSMstate == 5'd19 || + wciSeqFsm_state_mkFSMstate == 5'd20 || + wciSeqFsm_state_mkFSMstate == 5'd21)) + $display("Error: \"bsv/tst/TB1.bsv\", line 71, column 5: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wciSeqFsm_action_l71c5] and\n [RL_wciSeqFsm_action_l73c19, RL_wciSeqFsm_action_l74c19,\n RL_wciSeqFsm_action_l75c19, RL_wciSeqFsm_action_l76c19,\n RL_wciSeqFsm_action_l77c19] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wciSeqFsm_action_l70c8 && + (WILL_FIRE_RL_wciSeqFsm_action_l71c5 || + wciSeqFsm_state_mkFSMstate == 5'd17 || + wciSeqFsm_state_mkFSMstate == 5'd18 || + wciSeqFsm_state_mkFSMstate == 5'd19 || + wciSeqFsm_state_mkFSMstate == 5'd20 || + wciSeqFsm_state_mkFSMstate == 5'd21)) + $display("Error: \"bsv/tst/TB1.bsv\", line 70, column 8: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wciSeqFsm_action_l70c8] and\n [RL_wciSeqFsm_action_l71c5, RL_wciSeqFsm_action_l73c19,\n RL_wciSeqFsm_action_l74c19, RL_wciSeqFsm_action_l75c19,\n RL_wciSeqFsm_action_l76c19, RL_wciSeqFsm_action_l77c19] ) fired in the same\n clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (wciSeqFsm_state_mkFSMstate == 5'd17 && + (wciSeqFsm_state_mkFSMstate == 5'd18 || + wciSeqFsm_state_mkFSMstate == 5'd19 || + wciSeqFsm_state_mkFSMstate == 5'd20 || + wciSeqFsm_state_mkFSMstate == 5'd21)) + $display("Error: \"bsv/tst/TB1.bsv\", line 73, column 19: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wciSeqFsm_action_l73c19] and\n [RL_wciSeqFsm_action_l74c19, RL_wciSeqFsm_action_l75c19,\n RL_wciSeqFsm_action_l76c19, RL_wciSeqFsm_action_l77c19] ) fired in the same\n clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (wciSeqFsm_state_mkFSMstate == 5'd18 && + (wciSeqFsm_state_mkFSMstate == 5'd19 || + wciSeqFsm_state_mkFSMstate == 5'd20 || + wciSeqFsm_state_mkFSMstate == 5'd21)) + $display("Error: \"bsv/tst/TB1.bsv\", line 74, column 19: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wciSeqFsm_action_l74c19] and\n [RL_wciSeqFsm_action_l75c19, RL_wciSeqFsm_action_l76c19,\n RL_wciSeqFsm_action_l77c19] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (wciSeqFsm_state_mkFSMstate == 5'd19 && + (wciSeqFsm_state_mkFSMstate == 5'd20 || + wciSeqFsm_state_mkFSMstate == 5'd21)) + $display("Error: \"bsv/tst/TB1.bsv\", line 75, column 19: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wciSeqFsm_action_l75c19] and\n [RL_wciSeqFsm_action_l76c19, RL_wciSeqFsm_action_l77c19] ) fired in the same\n clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (wciSeqFsm_state_mkFSMstate == 5'd20 && + wciSeqFsm_state_mkFSMstate == 5'd21) + $display("Error: \"bsv/tst/TB1.bsv\", line 76, column 19: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wciSeqFsm_action_l76c19] and\n [RL_wciSeqFsm_action_l77c19] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wciSeqFsm_action_l50c5) + begin + v__h57858 = $time; + #0; + end + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wciSeqFsm_action_l50c5) + $display("[%0d]: %m: Checking for DUT presence...", v__h57858); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wciSeqFsm_action_l50c5 && + (WILL_FIRE_RL_wciSeqFsm_action_l51c10 || + wciSeqFsm_state_mkFSMstate == 5'd2 || + WILL_FIRE_RL_wciSeqFsm_action_l54c8 || + WILL_FIRE_RL_wciSeqFsm_action_l55c5 || + wciSeqFsm_state_mkFSMstate == 5'd5 || + WILL_FIRE_RL_wciSeqFsm_action_l58c8 || + WILL_FIRE_RL_wciSeqFsm_action_l59c5 || + wciSeqFsm_state_mkFSMstate == 5'd8 || + WILL_FIRE_RL_wciSeqFsm_action_l62c8 || + WILL_FIRE_RL_wciSeqFsm_action_l63c5 || + wciSeqFsm_state_mkFSMstate == 5'd11 || + WILL_FIRE_RL_wciSeqFsm_action_l66c8 || + WILL_FIRE_RL_wciSeqFsm_action_l67c5 || + wciSeqFsm_state_mkFSMstate == 5'd14 || + WILL_FIRE_RL_wciSeqFsm_action_l70c8 || + WILL_FIRE_RL_wciSeqFsm_action_l71c5 || + wciSeqFsm_state_mkFSMstate == 5'd17 || + wciSeqFsm_state_mkFSMstate == 5'd18 || + wciSeqFsm_state_mkFSMstate == 5'd19 || + wciSeqFsm_state_mkFSMstate == 5'd20 || + wciSeqFsm_state_mkFSMstate == 5'd21)) + $display("Error: \"bsv/tst/TB1.bsv\", line 50, column 5: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wciSeqFsm_action_l50c5] and\n [RL_wciSeqFsm_action_l51c10, RL_wciSeqFsm_action_l53c5,\n RL_wciSeqFsm_action_l54c8, RL_wciSeqFsm_action_l55c5,\n RL_wciSeqFsm_action_l57c5, RL_wciSeqFsm_action_l58c8,\n RL_wciSeqFsm_action_l59c5, RL_wciSeqFsm_action_l61c5,\n RL_wciSeqFsm_action_l62c8, RL_wciSeqFsm_action_l63c5,\n RL_wciSeqFsm_action_l65c5, RL_wciSeqFsm_action_l66c8,\n RL_wciSeqFsm_action_l67c5, RL_wciSeqFsm_action_l69c5,\n RL_wciSeqFsm_action_l70c8, RL_wciSeqFsm_action_l71c5,\n RL_wciSeqFsm_action_l73c19, RL_wciSeqFsm_action_l74c19,\n RL_wciSeqFsm_action_l75c19, RL_wciSeqFsm_action_l76c19,\n RL_wciSeqFsm_action_l77c19] ) fired in the same clock cycle.\n"); + end + // synopsys translate_on +endmodule // mkTB1 + diff --git a/rtl/mkTLPCM.v b/rtl/mkTLPCM.v index 9d720396..111f0736 100644 --- a/rtl/mkTLPCM.v +++ b/rtl/mkTLPCM.v @@ -1,7 +1,7 @@ // -// Generated by Bluespec Compiler, version 2012.09.beta1 (build 29570, 2012-09.11) +// Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Tue Dec 11 16:19:42 EST 2012 +// On Fri Jun 21 16:58:23 EDT 2013 // // // Ports: @@ -134,7 +134,7 @@ module mkTLPCM(pfk, pktMerge$RDY_oport_get; // remaining internal signals - reg [1 : 0] CASE_pfk_BITS_13_TO_12_3_0_pfk_BITS_13_TO_12_1_ETC__q1; + reg [1 : 0] CASE_pfk_BITS_13_TO_12_0_pfk_BITS_13_TO_12_1_p_ETC__q1; wire [13 : 0] x__h110; // actionvalue method c_request_get @@ -200,14 +200,14 @@ module mkTLPCM(pfk, // remaining internal signals assign x__h110 = - { CASE_pfk_BITS_13_TO_12_3_0_pfk_BITS_13_TO_12_1_ETC__q1, + { CASE_pfk_BITS_13_TO_12_0_pfk_BITS_13_TO_12_1_p_ETC__q1, pfk[11:0] } ; always@(pfk) begin case (pfk[13:12]) 2'd0, 2'd1, 2'd2: - CASE_pfk_BITS_13_TO_12_3_0_pfk_BITS_13_TO_12_1_ETC__q1 = pfk[13:12]; - 2'd3: CASE_pfk_BITS_13_TO_12_3_0_pfk_BITS_13_TO_12_1_ETC__q1 = 2'd3; + CASE_pfk_BITS_13_TO_12_0_pfk_BITS_13_TO_12_1_p_ETC__q1 = pfk[13:12]; + 2'd3: CASE_pfk_BITS_13_TO_12_0_pfk_BITS_13_TO_12_1_p_ETC__q1 = 2'd3; endcase end endmodule // mkTLPCM diff --git a/rtl/mkTLPClientNode.v b/rtl/mkTLPClientNode.v index baf240e1..62adc91c 100644 --- a/rtl/mkTLPClientNode.v +++ b/rtl/mkTLPClientNode.v @@ -1,7 +1,7 @@ // -// Generated by Bluespec Compiler, version 2012.09.beta1 (build 29570, 2012-09.11) +// Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Tue Dec 11 16:19:42 EST 2012 +// On Fri Jun 21 16:58:23 EDT 2013 // // // Ports: @@ -105,7 +105,7 @@ module mkTLPClientNode(pfk, pktMerge$RDY_oport_get; // remaining internal signals - reg [1 : 0] CASE_pfk_BITS_13_TO_12_3_0_pfk_BITS_13_TO_12_1_ETC__q1; + reg [1 : 0] CASE_pfk_BITS_13_TO_12_0_pfk_BITS_13_TO_12_1_p_ETC__q1; wire [13 : 0] x__h110; // action method s_request_put @@ -166,14 +166,14 @@ module mkTLPClientNode(pfk, // remaining internal signals assign x__h110 = - { CASE_pfk_BITS_13_TO_12_3_0_pfk_BITS_13_TO_12_1_ETC__q1, + { CASE_pfk_BITS_13_TO_12_0_pfk_BITS_13_TO_12_1_p_ETC__q1, pfk[11:0] } ; always@(pfk) begin case (pfk[13:12]) 2'd0, 2'd1, 2'd2: - CASE_pfk_BITS_13_TO_12_3_0_pfk_BITS_13_TO_12_1_ETC__q1 = pfk[13:12]; - 2'd3: CASE_pfk_BITS_13_TO_12_3_0_pfk_BITS_13_TO_12_1_ETC__q1 = 2'd3; + CASE_pfk_BITS_13_TO_12_0_pfk_BITS_13_TO_12_1_p_ETC__q1 = pfk[13:12]; + 2'd3: CASE_pfk_BITS_13_TO_12_0_pfk_BITS_13_TO_12_1_p_ETC__q1 = 2'd3; endcase end endmodule // mkTLPClientNode diff --git a/rtl/mkTLPSM.v b/rtl/mkTLPSM.v index 1d05305c..47e8678f 100644 --- a/rtl/mkTLPSM.v +++ b/rtl/mkTLPSM.v @@ -1,7 +1,7 @@ // -// Generated by Bluespec Compiler, version 2012.09.beta1 (build 29570, 2012-09.11) +// Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Tue Dec 11 16:19:42 EST 2012 +// On Fri Jun 21 16:58:23 EDT 2013 // // // Ports: @@ -134,7 +134,7 @@ module mkTLPSM(pfk, pktMerge$RDY_oport_get; // remaining internal signals - reg [1 : 0] CASE_pfk_BITS_13_TO_12_3_0_pfk_BITS_13_TO_12_1_ETC__q1; + reg [1 : 0] CASE_pfk_BITS_13_TO_12_0_pfk_BITS_13_TO_12_1_p_ETC__q1; wire [13 : 0] x__h110; // action method s_request_put @@ -200,14 +200,14 @@ module mkTLPSM(pfk, // remaining internal signals assign x__h110 = - { CASE_pfk_BITS_13_TO_12_3_0_pfk_BITS_13_TO_12_1_ETC__q1, + { CASE_pfk_BITS_13_TO_12_0_pfk_BITS_13_TO_12_1_p_ETC__q1, pfk[11:0] } ; always@(pfk) begin case (pfk[13:12]) 2'd0, 2'd1, 2'd2: - CASE_pfk_BITS_13_TO_12_3_0_pfk_BITS_13_TO_12_1_ETC__q1 = pfk[13:12]; - 2'd3: CASE_pfk_BITS_13_TO_12_3_0_pfk_BITS_13_TO_12_1_ETC__q1 = 2'd3; + CASE_pfk_BITS_13_TO_12_0_pfk_BITS_13_TO_12_1_p_ETC__q1 = pfk[13:12]; + 2'd3: CASE_pfk_BITS_13_TO_12_0_pfk_BITS_13_TO_12_1_p_ETC__q1 = 2'd3; endcase end endmodule // mkTLPSM diff --git a/rtl/mkTLPSerializer.v b/rtl/mkTLPSerializer.v new file mode 100644 index 00000000..7eb3d7fc --- /dev/null +++ b/rtl/mkTLPSerializer.v @@ -0,0 +1,623 @@ +// +// Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) +// +// On Fri Jun 21 17:00:49 EDT 2013 +// +// +// Ports: +// Name I/O size props +// RDY_server_request_put O 1 reg +// server_response_get O 153 reg +// RDY_server_response_get O 1 reg +// client_request_get O 59 reg +// RDY_client_request_get O 1 reg +// RDY_client_response_put O 1 reg +// pciDevice I 16 +// CLK I 1 clock +// RST_N I 1 reset +// server_request_put I 153 reg +// client_response_put I 40 reg +// EN_server_request_put I 1 +// EN_client_response_put I 1 +// EN_server_response_get I 1 +// EN_client_request_get I 1 +// +// No combinational paths from inputs to outputs +// +// + +`ifdef BSV_ASSIGNMENT_DELAY +`else + `define BSV_ASSIGNMENT_DELAY +`endif + +`ifdef BSV_POSITIVE_RESET + `define BSV_RESET_VALUE 1'b1 + `define BSV_RESET_EDGE posedge +`else + `define BSV_RESET_VALUE 1'b0 + `define BSV_RESET_EDGE negedge +`endif + +module mkTLPSerializer(pciDevice, + CLK, + RST_N, + + server_request_put, + EN_server_request_put, + RDY_server_request_put, + + EN_server_response_get, + server_response_get, + RDY_server_response_get, + + EN_client_request_get, + client_request_get, + RDY_client_request_get, + + client_response_put, + EN_client_response_put, + RDY_client_response_put); + input [15 : 0] pciDevice; + input CLK; + input RST_N; + + // action method server_request_put + input [152 : 0] server_request_put; + input EN_server_request_put; + output RDY_server_request_put; + + // actionvalue method server_response_get + input EN_server_response_get; + output [152 : 0] server_response_get; + output RDY_server_response_get; + + // actionvalue method client_request_get + input EN_client_request_get; + output [58 : 0] client_request_get; + output RDY_client_request_get; + + // action method client_response_put + input [39 : 0] client_response_put; + input EN_client_response_put; + output RDY_client_response_put; + + // signals for module outputs + wire [152 : 0] server_response_get; + wire [58 : 0] client_request_get; + wire RDY_client_request_get, + RDY_client_response_put, + RDY_server_request_put, + RDY_server_response_get; + + // register cmpActive + reg cmpActive; + wire cmpActive$D_IN, cmpActive$EN; + + // register cmpDWRemain + reg [9 : 0] cmpDWRemain; + wire [9 : 0] cmpDWRemain$D_IN; + wire cmpDWRemain$EN; + + // register rdp + reg [1 : 0] rdp; + wire [1 : 0] rdp$D_IN; + wire rdp$EN; + + // register rdv + reg [127 : 0] rdv; + wire [127 : 0] rdv$D_IN; + wire rdv$EN; + + // register rss + reg [1 : 0] rss; + wire [1 : 0] rss$D_IN; + wire rss$EN; + + // register tlpActive + reg tlpActive; + wire tlpActive$D_IN, tlpActive$EN; + + // register tlpDW + reg [31 : 0] tlpDW; + wire [31 : 0] tlpDW$D_IN; + wire tlpDW$EN; + + // register tlpDWAddr + reg [29 : 0] tlpDWAddr; + wire [29 : 0] tlpDWAddr$D_IN; + wire tlpDWAddr$EN; + + // register tlpDWp + reg [1 : 0] tlpDWp; + wire [1 : 0] tlpDWp$D_IN; + wire tlpDWp$EN; + + // register tlpFirst + reg tlpFirst; + wire tlpFirst$D_IN, tlpFirst$EN; + + // register tlpReq + reg [63 : 0] tlpReq; + wire [63 : 0] tlpReq$D_IN; + wire tlpReq$EN; + + // register tlpUnroll + reg [9 : 0] tlpUnroll; + wire [9 : 0] tlpUnroll$D_IN; + wire tlpUnroll$EN; + + // ports of submodule cmpF + wire [55 : 0] cmpF$D_IN, cmpF$D_OUT; + wire cmpF$CLR, cmpF$DEQ, cmpF$EMPTY_N, cmpF$ENQ, cmpF$FULL_N; + + // ports of submodule cpReqF + wire [58 : 0] cpReqF$D_IN, cpReqF$D_OUT; + wire cpReqF$CLR, cpReqF$DEQ, cpReqF$EMPTY_N, cpReqF$ENQ, cpReqF$FULL_N; + + // ports of submodule cpRespF + wire [39 : 0] cpRespF$D_IN, cpRespF$D_OUT; + wire cpRespF$CLR, cpRespF$DEQ, cpRespF$EMPTY_N, cpRespF$ENQ, cpRespF$FULL_N; + + // ports of submodule inF + wire [152 : 0] inF$D_IN, inF$D_OUT; + wire inF$CLR, inF$DEQ, inF$EMPTY_N, inF$ENQ, inF$FULL_N; + + // ports of submodule outF + wire [152 : 0] outF$D_IN, outF$D_OUT; + wire outF$CLR, outF$DEQ, outF$EMPTY_N, outF$ENQ, outF$FULL_N; + + // rule scheduling signals + wire WILL_FIRE_RL_tlpFirstComplWord, + WILL_FIRE_RL_tlpFirstRcv, + WILL_FIRE_RL_tlpNextComplWord, + WILL_FIRE_RL_tlpReqGen, + WILL_FIRE_RL_tlpStageNextWord; + + // inputs to muxes for submodule ports + wire [152 : 0] MUX_outF$enq_1__VAL_1, MUX_outF$enq_1__VAL_2; + wire [29 : 0] MUX_tlpDWAddr$write_1__VAL_2; + wire [9 : 0] MUX_cmpDWRemain$write_1__VAL_1, + MUX_cmpDWRemain$write_1__VAL_2, + MUX_tlpUnroll$write_1__VAL_2; + wire [1 : 0] MUX_rdp$write_1__VAL_1, + MUX_rss$write_1__VAL_2, + MUX_tlpDWp$write_1__VAL_1; + wire MUX_cmpActive$write_1__SEL_1, + MUX_tlpActive$write_1__SEL_1, + MUX_tlpDWAddr$write_1__SEL_1, + MUX_tlpDWp$write_1__SEL_1; + + // remaining internal signals + reg [31 : 0] v__h2549; + reg [15 : 0] lastRema__h7245; + reg [1 : 0] lowAddr10__h2074, x__h2304, x__h2327; + wire [127 : 0] pkt__h4230, pw_data__h7278; + wire [57 : 0] IF_tlpReq_3_BIT_62_4_THEN_tlpDWAddr_8_BITS_21__ETC___d113; + wire [31 : 0] IF_tlpReq_3_BIT_62_4_AND_NOT_tlpFirst_6_4_5_TH_ETC___d102, + wreq_data__h3050; + wire [15 : 0] pw_be__h7277; + wire [11 : 0] byteCount__h2076, x__h2295, x__h2297, y__h2296, y__h2298; + wire [6 : 0] lowAddr__h2075; + wire [3 : 0] _theResult_____2__h2491; + wire [2 : 0] x__h7701; + wire cpReqF_i_notFull__2_AND_NOT_tlpReq_3_BIT_62_4__ETC___d82; + + // action method server_request_put + assign RDY_server_request_put = inF$FULL_N ; + + // actionvalue method server_response_get + assign server_response_get = outF$D_OUT ; + assign RDY_server_response_get = outF$EMPTY_N ; + + // actionvalue method client_request_get + assign client_request_get = cpReqF$D_OUT ; + assign RDY_client_request_get = cpReqF$EMPTY_N ; + + // action method client_response_put + assign RDY_client_response_put = cpRespF$FULL_N ; + + // submodule cmpF + FIFO2 #(.width(32'd56), .guarded(32'd1)) cmpF(.RST(RST_N), + .CLK(CLK), + .D_IN(cmpF$D_IN), + .ENQ(cmpF$ENQ), + .DEQ(cmpF$DEQ), + .CLR(cmpF$CLR), + .D_OUT(cmpF$D_OUT), + .FULL_N(cmpF$FULL_N), + .EMPTY_N(cmpF$EMPTY_N)); + + // submodule cpReqF + FIFO2 #(.width(32'd59), .guarded(32'd1)) cpReqF(.RST(RST_N), + .CLK(CLK), + .D_IN(cpReqF$D_IN), + .ENQ(cpReqF$ENQ), + .DEQ(cpReqF$DEQ), + .CLR(cpReqF$CLR), + .D_OUT(cpReqF$D_OUT), + .FULL_N(cpReqF$FULL_N), + .EMPTY_N(cpReqF$EMPTY_N)); + + // submodule cpRespF + FIFO2 #(.width(32'd40), .guarded(32'd1)) cpRespF(.RST(RST_N), + .CLK(CLK), + .D_IN(cpRespF$D_IN), + .ENQ(cpRespF$ENQ), + .DEQ(cpRespF$DEQ), + .CLR(cpRespF$CLR), + .D_OUT(cpRespF$D_OUT), + .FULL_N(cpRespF$FULL_N), + .EMPTY_N(cpRespF$EMPTY_N)); + + // submodule inF + FIFO2 #(.width(32'd153), .guarded(32'd1)) inF(.RST(RST_N), + .CLK(CLK), + .D_IN(inF$D_IN), + .ENQ(inF$ENQ), + .DEQ(inF$DEQ), + .CLR(inF$CLR), + .D_OUT(inF$D_OUT), + .FULL_N(inF$FULL_N), + .EMPTY_N(inF$EMPTY_N)); + + // submodule outF + FIFO2 #(.width(32'd153), .guarded(32'd1)) outF(.RST(RST_N), + .CLK(CLK), + .D_IN(outF$D_IN), + .ENQ(outF$ENQ), + .DEQ(outF$DEQ), + .CLR(outF$CLR), + .D_OUT(outF$D_OUT), + .FULL_N(outF$FULL_N), + .EMPTY_N(outF$EMPTY_N)); + + // rule RL_tlpFirstRcv + assign WILL_FIRE_RL_tlpFirstRcv = + inF$EMPTY_N && + (!inF$D_OUT[152] || inF$D_OUT[110] || inF$D_OUT[125] || + inF$D_OUT[124:120] != 5'b0 || + inF$D_OUT[126] || + cmpF$FULL_N) && + !tlpActive ; + + // rule RL_tlpReqGen + assign WILL_FIRE_RL_tlpReqGen = + cpReqF_i_notFull__2_AND_NOT_tlpReq_3_BIT_62_4__ETC___d82 && + tlpActive ; + + // rule RL_tlpFirstComplWord + assign WILL_FIRE_RL_tlpFirstComplWord = + cmpF$EMPTY_N && cpRespF$EMPTY_N && outF$FULL_N && !cmpActive ; + + // rule RL_tlpStageNextWord + assign WILL_FIRE_RL_tlpStageNextWord = + cpRespF$EMPTY_N && cmpActive && cmpDWRemain != 10'd0 && + !WILL_FIRE_RL_tlpNextComplWord ; + + // rule RL_tlpNextComplWord + assign WILL_FIRE_RL_tlpNextComplWord = + outF$FULL_N && cmpActive && rss != 2'd0 ; + + // inputs to muxes for submodule ports + assign MUX_cmpActive$write_1__SEL_1 = + WILL_FIRE_RL_tlpNextComplWord && rss == 2'd2 ; + assign MUX_tlpActive$write_1__SEL_1 = + WILL_FIRE_RL_tlpReqGen && tlpUnroll == 10'd1 ; + assign MUX_tlpDWAddr$write_1__SEL_1 = + WILL_FIRE_RL_tlpFirstRcv && inF$D_OUT[152] && !inF$D_OUT[110] && + !inF$D_OUT[125] && + inF$D_OUT[124:120] == 5'b0 ; + assign MUX_tlpDWp$write_1__SEL_1 = + WILL_FIRE_RL_tlpReqGen && tlpReq[62] && !tlpFirst ; + assign MUX_cmpDWRemain$write_1__VAL_1 = cmpF$D_OUT[21:12] - 10'd1 ; + assign MUX_cmpDWRemain$write_1__VAL_2 = cmpDWRemain - 10'd1 ; + assign MUX_outF$enq_1__VAL_1 = + { 1'd1, cmpF$D_OUT[21:12] == 10'd1, 23'h2AFFFF, pkt__h4230 } ; + assign MUX_outF$enq_1__VAL_2 = + { 1'd0, rss == 2'd2, 7'h2A, pw_be__h7277, pw_data__h7278 } ; + assign MUX_rdp$write_1__VAL_1 = rdp + 2'd1 ; + assign MUX_rss$write_1__VAL_2 = (cmpDWRemain == 10'd1) ? 2'd2 : 2'd1 ; + assign MUX_tlpDWAddr$write_1__VAL_2 = tlpDWAddr + 30'd1 ; + assign MUX_tlpDWp$write_1__VAL_1 = tlpDWp - 2'd1 ; + assign MUX_tlpUnroll$write_1__VAL_2 = tlpUnroll - 10'd1 ; + + // register cmpActive + assign cmpActive$D_IN = !MUX_cmpActive$write_1__SEL_1 ; + assign cmpActive$EN = + WILL_FIRE_RL_tlpNextComplWord && rss == 2'd2 || + WILL_FIRE_RL_tlpFirstComplWord && cmpF$D_OUT[21:12] != 10'd1 ; + + // register cmpDWRemain + assign cmpDWRemain$D_IN = + WILL_FIRE_RL_tlpFirstComplWord ? + MUX_cmpDWRemain$write_1__VAL_1 : + MUX_cmpDWRemain$write_1__VAL_2 ; + assign cmpDWRemain$EN = + WILL_FIRE_RL_tlpFirstComplWord || WILL_FIRE_RL_tlpStageNextWord ; + + // register rdp + assign rdp$D_IN = + WILL_FIRE_RL_tlpStageNextWord ? MUX_rdp$write_1__VAL_1 : 2'd0 ; + assign rdp$EN = + WILL_FIRE_RL_tlpStageNextWord || WILL_FIRE_RL_tlpNextComplWord ; + + // register rdv + assign rdv$D_IN = + { rdv[95:0], + cpRespF$D_OUT[7:0], + cpRespF$D_OUT[15:8], + cpRespF$D_OUT[23:16], + cpRespF$D_OUT[31:24] } ; + assign rdv$EN = WILL_FIRE_RL_tlpStageNextWord ; + + // register rss + assign rss$D_IN = + MUX_cmpActive$write_1__SEL_1 ? 2'd0 : MUX_rss$write_1__VAL_2 ; + assign rss$EN = + WILL_FIRE_RL_tlpNextComplWord && rss == 2'd2 || + WILL_FIRE_RL_tlpStageNextWord && + (cmpDWRemain == 10'd1 || rdp == 2'd3) ; + + // register tlpActive + assign tlpActive$D_IN = !MUX_tlpActive$write_1__SEL_1 ; + assign tlpActive$EN = + WILL_FIRE_RL_tlpReqGen && tlpUnroll == 10'd1 || + WILL_FIRE_RL_tlpFirstRcv ; + + // register tlpDW + assign tlpDW$D_IN = inF$D_OUT[31:0] ; + assign tlpDW$EN = MUX_tlpDWAddr$write_1__SEL_1 ; + + // register tlpDWAddr + assign tlpDWAddr$D_IN = + MUX_tlpDWAddr$write_1__SEL_1 ? + inF$D_OUT[63:34] : + MUX_tlpDWAddr$write_1__VAL_2 ; + assign tlpDWAddr$EN = + WILL_FIRE_RL_tlpFirstRcv && inF$D_OUT[152] && !inF$D_OUT[110] && + !inF$D_OUT[125] && + inF$D_OUT[124:120] == 5'b0 || + WILL_FIRE_RL_tlpReqGen ; + + // register tlpDWp + assign tlpDWp$D_IN = + MUX_tlpDWp$write_1__SEL_1 ? MUX_tlpDWp$write_1__VAL_1 : 2'd3 ; + assign tlpDWp$EN = + WILL_FIRE_RL_tlpReqGen && tlpReq[62] && !tlpFirst || + WILL_FIRE_RL_tlpFirstRcv && inF$D_OUT[152] && !inF$D_OUT[110] && + !inF$D_OUT[125] && + inF$D_OUT[124:120] == 5'b0 ; + + // register tlpFirst + assign tlpFirst$D_IN = MUX_tlpDWAddr$write_1__SEL_1 ; + assign tlpFirst$EN = + WILL_FIRE_RL_tlpFirstRcv && inF$D_OUT[152] && !inF$D_OUT[110] && + !inF$D_OUT[125] && + inF$D_OUT[124:120] == 5'b0 || + WILL_FIRE_RL_tlpReqGen ; + + // register tlpReq + assign tlpReq$D_IN = + { 1'b0, + inF$D_OUT[126:120], + 1'b0, + inF$D_OUT[118:116], + 4'b0, + inF$D_OUT[111:108], + 2'b0, + inF$D_OUT[105:64] } ; + assign tlpReq$EN = MUX_tlpDWAddr$write_1__SEL_1 ; + + // register tlpUnroll + assign tlpUnroll$D_IN = + MUX_tlpDWAddr$write_1__SEL_1 ? + inF$D_OUT[105:96] : + MUX_tlpUnroll$write_1__VAL_2 ; + assign tlpUnroll$EN = + WILL_FIRE_RL_tlpFirstRcv && inF$D_OUT[152] && !inF$D_OUT[110] && + !inF$D_OUT[125] && + inF$D_OUT[124:120] == 5'b0 || + WILL_FIRE_RL_tlpReqGen ; + + // submodule cmpF + assign cmpF$D_IN = + { inF$D_OUT[95:80], + inF$D_OUT[118:116], + inF$D_OUT[79:72], + lowAddr__h2075, + inF$D_OUT[105:96], + byteCount__h2076 } ; + assign cmpF$ENQ = + WILL_FIRE_RL_tlpFirstRcv && inF$D_OUT[152] && !inF$D_OUT[110] && + !inF$D_OUT[125] && + inF$D_OUT[124:120] == 5'b0 && + !inF$D_OUT[126] ; + assign cmpF$DEQ = WILL_FIRE_RL_tlpFirstComplWord ; + assign cmpF$CLR = 1'b0 ; + + // submodule cpReqF + assign cpReqF$D_IN = + { !tlpReq[62], + IF_tlpReq_3_BIT_62_4_THEN_tlpDWAddr_8_BITS_21__ETC___d113 } ; + assign cpReqF$ENQ = + cpReqF_i_notFull__2_AND_NOT_tlpReq_3_BIT_62_4__ETC___d82 && + tlpActive ; + assign cpReqF$DEQ = EN_client_request_get ; + assign cpReqF$CLR = 1'b0 ; + + // submodule cpRespF + assign cpRespF$D_IN = client_response_put ; + assign cpRespF$ENQ = EN_client_response_put ; + assign cpRespF$DEQ = + WILL_FIRE_RL_tlpFirstComplWord || WILL_FIRE_RL_tlpStageNextWord ; + assign cpRespF$CLR = 1'b0 ; + + // submodule inF + assign inF$D_IN = server_request_put ; + assign inF$ENQ = EN_server_request_put ; + assign inF$DEQ = + WILL_FIRE_RL_tlpReqGen && tlpReq[62] && !tlpFirst || + WILL_FIRE_RL_tlpFirstRcv ; + assign inF$CLR = 1'b0 ; + + // submodule outF + assign outF$D_IN = + WILL_FIRE_RL_tlpFirstComplWord ? + MUX_outF$enq_1__VAL_1 : + MUX_outF$enq_1__VAL_2 ; + assign outF$ENQ = + WILL_FIRE_RL_tlpFirstComplWord || WILL_FIRE_RL_tlpNextComplWord ; + assign outF$DEQ = EN_server_response_get ; + assign outF$CLR = 1'b0 ; + + // remaining internal signals + assign IF_tlpReq_3_BIT_62_4_AND_NOT_tlpFirst_6_4_5_TH_ETC___d102 = + (tlpReq[62] && !tlpFirst) ? v__h2549 : tlpDW ; + assign IF_tlpReq_3_BIT_62_4_THEN_tlpDWAddr_8_BITS_21__ETC___d113 = + tlpReq[62] ? + { tlpDWAddr[21:0], + _theResult_____2__h2491, + wreq_data__h3050 } : + { 24'hAAAAAA, + tlpReq[15:8], + tlpDWAddr[21:0], + _theResult_____2__h2491 } ; + assign _theResult_____2__h2491 = + tlpFirst ? + tlpReq[3:0] : + ((tlpUnroll == 10'd1) ? tlpReq[7:4] : 4'hF) ; + assign byteCount__h2076 = x__h2295 - y__h2296 ; + assign cpReqF_i_notFull__2_AND_NOT_tlpReq_3_BIT_62_4__ETC___d82 = + cpReqF$FULL_N && (!tlpReq[62] || tlpFirst || inF$EMPTY_N) ; + assign lowAddr__h2075 = { inF$D_OUT[38:34], lowAddr10__h2074 } ; + assign pkt__h4230 = + { 9'd148, + cmpF$D_OUT[39:37], + 10'd0, + cmpF$D_OUT[21:12], + pciDevice, + 4'd0, + cmpF$D_OUT[11:0], + cmpF$D_OUT[55:40], + cmpF$D_OUT[36:29], + 1'b0, + cmpF$D_OUT[28:22], + cpRespF$D_OUT[7:0], + cpRespF$D_OUT[15:8], + cpRespF$D_OUT[23:16], + cpRespF$D_OUT[31:24] } ; + assign pw_be__h7277 = (rss == 2'd2) ? lastRema__h7245 : 16'd65535 ; + assign pw_data__h7278 = + x__h7701[1] ? + (x__h7701[0] ? + { rdv[31:0], rdv[127:32] } : + { rdv[63:0], rdv[127:64] }) : + (x__h7701[0] ? { rdv[95:0], rdv[127:96] } : rdv) ; + assign wreq_data__h3050 = + { IF_tlpReq_3_BIT_62_4_AND_NOT_tlpFirst_6_4_5_TH_ETC___d102[7:0], + IF_tlpReq_3_BIT_62_4_AND_NOT_tlpFirst_6_4_5_TH_ETC___d102[15:8], + IF_tlpReq_3_BIT_62_4_AND_NOT_tlpFirst_6_4_5_TH_ETC___d102[23:16], + IF_tlpReq_3_BIT_62_4_AND_NOT_tlpFirst_6_4_5_TH_ETC___d102[31:24] } ; + assign x__h2295 = x__h2297 - y__h2298 ; + assign x__h2297 = { inF$D_OUT[105:96], 2'b0 } ; + assign x__h7701 = 3'h4 - { 1'd0, rdp } ; + assign y__h2296 = + (inF$D_OUT[105:96] == 10'd1) ? 12'd0 : { 10'd0, x__h2327 } ; + assign y__h2298 = { 10'd0, x__h2304 } ; + always@(inF$D_OUT) + begin + case (inF$D_OUT[67:64]) + 4'b1100: x__h2304 = 2'b10; + 4'b1110: x__h2304 = 2'b01; + 4'b1111: x__h2304 = 2'b0; + default: x__h2304 = 2'b11; + endcase + end + always@(inF$D_OUT) + begin + case (inF$D_OUT[71:68]) + 4'b1100: x__h2327 = 2'b10; + 4'b1110: x__h2327 = 2'b01; + 4'b1111: x__h2327 = 2'b0; + default: x__h2327 = 2'b11; + endcase + end + always@(tlpDWp or inF$D_OUT) + begin + case (tlpDWp) + 2'd0: v__h2549 = inF$D_OUT[31:0]; + 2'd1: v__h2549 = inF$D_OUT[63:32]; + 2'd2: v__h2549 = inF$D_OUT[95:64]; + 2'd3: v__h2549 = inF$D_OUT[127:96]; + endcase + end + always@(rdp) + begin + case (rdp) + 2'b0: lastRema__h7245 = 16'hFFFF; + 2'b01: lastRema__h7245 = 16'hF000; + 2'b10: lastRema__h7245 = 16'hFF00; + 2'd3: lastRema__h7245 = 16'hFFF0; + endcase + end + always@(inF$D_OUT) + begin + case (inF$D_OUT[67:64]) + 4'b1000: lowAddr10__h2074 = 2'b11; + 4'b1100: lowAddr10__h2074 = 2'b10; + 4'b1110: lowAddr10__h2074 = 2'b01; + default: lowAddr10__h2074 = 2'b0; + endcase + end + + // handling of inlined registers + + always@(posedge CLK) + begin + if (RST_N == `BSV_RESET_VALUE) + begin + cmpActive <= `BSV_ASSIGNMENT_DELAY 1'd0; + rdp <= `BSV_ASSIGNMENT_DELAY 2'd0; + rss <= `BSV_ASSIGNMENT_DELAY 2'd0; + tlpActive <= `BSV_ASSIGNMENT_DELAY 1'd0; + end + else + begin + if (cmpActive$EN) cmpActive <= `BSV_ASSIGNMENT_DELAY cmpActive$D_IN; + if (rdp$EN) rdp <= `BSV_ASSIGNMENT_DELAY rdp$D_IN; + if (rss$EN) rss <= `BSV_ASSIGNMENT_DELAY rss$D_IN; + if (tlpActive$EN) tlpActive <= `BSV_ASSIGNMENT_DELAY tlpActive$D_IN; + end + if (cmpDWRemain$EN) cmpDWRemain <= `BSV_ASSIGNMENT_DELAY cmpDWRemain$D_IN; + if (rdv$EN) rdv <= `BSV_ASSIGNMENT_DELAY rdv$D_IN; + if (tlpDW$EN) tlpDW <= `BSV_ASSIGNMENT_DELAY tlpDW$D_IN; + if (tlpDWAddr$EN) tlpDWAddr <= `BSV_ASSIGNMENT_DELAY tlpDWAddr$D_IN; + if (tlpDWp$EN) tlpDWp <= `BSV_ASSIGNMENT_DELAY tlpDWp$D_IN; + if (tlpFirst$EN) tlpFirst <= `BSV_ASSIGNMENT_DELAY tlpFirst$D_IN; + if (tlpReq$EN) tlpReq <= `BSV_ASSIGNMENT_DELAY tlpReq$D_IN; + if (tlpUnroll$EN) tlpUnroll <= `BSV_ASSIGNMENT_DELAY tlpUnroll$D_IN; + end + + // synopsys translate_off + `ifdef BSV_NO_INITIAL_BLOCKS + `else // not BSV_NO_INITIAL_BLOCKS + initial + begin + cmpActive = 1'h0; + cmpDWRemain = 10'h2AA; + rdp = 2'h2; + rdv = 128'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; + rss = 2'h2; + tlpActive = 1'h0; + tlpDW = 32'hAAAAAAAA; + tlpDWAddr = 30'h2AAAAAAA; + tlpDWp = 2'h2; + tlpFirst = 1'h0; + tlpReq = 64'hAAAAAAAAAAAAAAAA; + tlpUnroll = 10'h2AA; + end + `endif // BSV_NO_INITIAL_BLOCKS + // synopsys translate_on +endmodule // mkTLPSerializer + diff --git a/rtl/mkTLPServerNode.v b/rtl/mkTLPServerNode.v index af817d87..de08af68 100644 --- a/rtl/mkTLPServerNode.v +++ b/rtl/mkTLPServerNode.v @@ -1,7 +1,7 @@ // -// Generated by Bluespec Compiler, version 2012.09.beta1 (build 29570, 2012-09.11) +// Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Tue Dec 11 16:19:42 EST 2012 +// On Fri Jun 21 16:58:23 EDT 2013 // // // Ports: @@ -105,7 +105,7 @@ module mkTLPServerNode(pfk, pktMerge$RDY_oport_get; // remaining internal signals - reg [1 : 0] CASE_pfk_BITS_13_TO_12_3_0_pfk_BITS_13_TO_12_1_ETC__q1; + reg [1 : 0] CASE_pfk_BITS_13_TO_12_0_pfk_BITS_13_TO_12_1_p_ETC__q1; wire [13 : 0] x__h110; // actionvalue method c_request_get @@ -166,14 +166,14 @@ module mkTLPServerNode(pfk, // remaining internal signals assign x__h110 = - { CASE_pfk_BITS_13_TO_12_3_0_pfk_BITS_13_TO_12_1_ETC__q1, + { CASE_pfk_BITS_13_TO_12_0_pfk_BITS_13_TO_12_1_p_ETC__q1, pfk[11:0] } ; always@(pfk) begin case (pfk[13:12]) 2'd0, 2'd1, 2'd2: - CASE_pfk_BITS_13_TO_12_3_0_pfk_BITS_13_TO_12_1_ETC__q1 = pfk[13:12]; - 2'd3: CASE_pfk_BITS_13_TO_12_3_0_pfk_BITS_13_TO_12_1_ETC__q1 = 2'd3; + CASE_pfk_BITS_13_TO_12_0_pfk_BITS_13_TO_12_1_p_ETC__q1 = pfk[13:12]; + 2'd3: CASE_pfk_BITS_13_TO_12_0_pfk_BITS_13_TO_12_1_p_ETC__q1 = 2'd3; endcase end endmodule // mkTLPServerNode diff --git a/rtl/mkTimeClient.v b/rtl/mkTimeClient.v index 6077cc83..0230df43 100644 --- a/rtl/mkTimeClient.v +++ b/rtl/mkTimeClient.v @@ -1,7 +1,7 @@ // -// Generated by Bluespec Compiler, version 2012.09.beta1 (build 29570, 2012-09.11) +// Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Tue Dec 11 16:19:58 EST 2012 +// On Fri Jun 21 16:57:24 EDT 2013 // // // Ports: diff --git a/rtl/mkUUID.v b/rtl/mkUUID.v index 05633da3..1a58fcf9 100644 --- a/rtl/mkUUID.v +++ b/rtl/mkUUID.v @@ -1,7 +1,7 @@ // -// Generated by Bluespec Compiler, version 2012.09.beta1 (build 29570, 2012-09.11) +// Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Tue Dec 11 16:19:25 EST 2012 +// On Fri Jun 21 16:56:57 EDT 2013 // // // Ports: diff --git a/rtl/mkWSICaptureWorker4B.v b/rtl/mkWSICaptureWorker4B.v index 3ff21013..8d07cea4 100644 --- a/rtl/mkWSICaptureWorker4B.v +++ b/rtl/mkWSICaptureWorker4B.v @@ -1,7 +1,7 @@ // -// Generated by Bluespec Compiler, version 2012.09.beta1 (build 29570, 2012-09.11) +// Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Tue Dec 11 16:21:18 EST 2012 +// On Fri Jun 21 16:57:38 EDT 2013 // // // Ports: @@ -194,26 +194,26 @@ module mkWSICaptureWorker4B(wciS0_Clk, wire [63 : 0] nowW$wget, wti_Es_mData_w$wget; wire [60 : 0] wsiS_wsiReq$wget; wire [33 : 0] wci_wslv_respF_x_wire$wget; - wire [31 : 0] dataBram_serverAdapterA_outData_enqData$wget, - dataBram_serverAdapterA_outData_outData$wget, - dataBram_serverAdapterB_outData_enqData$wget, - dataBram_serverAdapterB_outData_outData$wget, - metaBram_serverAdapterA_1_outData_enqData$wget, - metaBram_serverAdapterA_1_outData_outData$wget, - metaBram_serverAdapterA_2_outData_enqData$wget, - metaBram_serverAdapterA_2_outData_outData$wget, - metaBram_serverAdapterA_3_outData_enqData$wget, - metaBram_serverAdapterA_3_outData_outData$wget, - metaBram_serverAdapterA_outData_enqData$wget, - metaBram_serverAdapterA_outData_outData$wget, - metaBram_serverAdapterB_1_outData_enqData$wget, - metaBram_serverAdapterB_1_outData_outData$wget, - metaBram_serverAdapterB_2_outData_enqData$wget, - metaBram_serverAdapterB_2_outData_outData$wget, - metaBram_serverAdapterB_3_outData_enqData$wget, - metaBram_serverAdapterB_3_outData_outData$wget, - metaBram_serverAdapterB_outData_enqData$wget, - metaBram_serverAdapterB_outData_outData$wget, + wire [31 : 0] dataBram_0_serverAdapterA_outData_enqData$wget, + dataBram_0_serverAdapterA_outData_outData$wget, + dataBram_0_serverAdapterB_outData_enqData$wget, + dataBram_0_serverAdapterB_outData_outData$wget, + metaBram_0_serverAdapterA_outData_enqData$wget, + metaBram_0_serverAdapterA_outData_outData$wget, + metaBram_0_serverAdapterB_outData_enqData$wget, + metaBram_0_serverAdapterB_outData_outData$wget, + metaBram_1_serverAdapterA_outData_enqData$wget, + metaBram_1_serverAdapterA_outData_outData$wget, + metaBram_1_serverAdapterB_outData_enqData$wget, + metaBram_1_serverAdapterB_outData_outData$wget, + metaBram_2_serverAdapterA_outData_enqData$wget, + metaBram_2_serverAdapterA_outData_outData$wget, + metaBram_2_serverAdapterB_outData_enqData$wget, + metaBram_2_serverAdapterB_outData_outData$wget, + metaBram_3_serverAdapterA_outData_enqData$wget, + metaBram_3_serverAdapterA_outData_outData$wget, + metaBram_3_serverAdapterB_outData_enqData$wget, + metaBram_3_serverAdapterB_outData_outData$wget, statusReg_w$wget, wci_wci_Es_mAddr_w$wget, wci_wci_Es_mData_w$wget, @@ -221,140 +221,140 @@ module mkWSICaptureWorker4B(wciS0_Clk, wire [11 : 0] wsi_Es_mBurstLength_w$wget; wire [7 : 0] wsi_Es_mReqInfo_w$wget; wire [3 : 0] wci_wci_Es_mByteEn_w$wget, wsi_Es_mByteEn_w$wget; - wire [2 : 0] dataBram_serverAdapterA_cnt_1$wget, - dataBram_serverAdapterA_cnt_2$wget, - dataBram_serverAdapterA_cnt_3$wget, - dataBram_serverAdapterB_cnt_1$wget, - dataBram_serverAdapterB_cnt_2$wget, - dataBram_serverAdapterB_cnt_3$wget, - metaBram_serverAdapterA_1_cnt_1$wget, - metaBram_serverAdapterA_1_cnt_2$wget, - metaBram_serverAdapterA_1_cnt_3$wget, - metaBram_serverAdapterA_2_cnt_1$wget, - metaBram_serverAdapterA_2_cnt_2$wget, - metaBram_serverAdapterA_2_cnt_3$wget, - metaBram_serverAdapterA_3_cnt_1$wget, - metaBram_serverAdapterA_3_cnt_2$wget, - metaBram_serverAdapterA_3_cnt_3$wget, - metaBram_serverAdapterA_cnt_1$wget, - metaBram_serverAdapterA_cnt_2$wget, - metaBram_serverAdapterA_cnt_3$wget, - metaBram_serverAdapterB_1_cnt_1$wget, - metaBram_serverAdapterB_1_cnt_2$wget, - metaBram_serverAdapterB_1_cnt_3$wget, - metaBram_serverAdapterB_2_cnt_1$wget, - metaBram_serverAdapterB_2_cnt_2$wget, - metaBram_serverAdapterB_2_cnt_3$wget, - metaBram_serverAdapterB_3_cnt_1$wget, - metaBram_serverAdapterB_3_cnt_2$wget, - metaBram_serverAdapterB_3_cnt_3$wget, - metaBram_serverAdapterB_cnt_1$wget, - metaBram_serverAdapterB_cnt_2$wget, - metaBram_serverAdapterB_cnt_3$wget, + wire [2 : 0] dataBram_0_serverAdapterA_cnt_1$wget, + dataBram_0_serverAdapterA_cnt_2$wget, + dataBram_0_serverAdapterA_cnt_3$wget, + dataBram_0_serverAdapterB_cnt_1$wget, + dataBram_0_serverAdapterB_cnt_2$wget, + dataBram_0_serverAdapterB_cnt_3$wget, + metaBram_0_serverAdapterA_cnt_1$wget, + metaBram_0_serverAdapterA_cnt_2$wget, + metaBram_0_serverAdapterA_cnt_3$wget, + metaBram_0_serverAdapterB_cnt_1$wget, + metaBram_0_serverAdapterB_cnt_2$wget, + metaBram_0_serverAdapterB_cnt_3$wget, + metaBram_1_serverAdapterA_cnt_1$wget, + metaBram_1_serverAdapterA_cnt_2$wget, + metaBram_1_serverAdapterA_cnt_3$wget, + metaBram_1_serverAdapterB_cnt_1$wget, + metaBram_1_serverAdapterB_cnt_2$wget, + metaBram_1_serverAdapterB_cnt_3$wget, + metaBram_2_serverAdapterA_cnt_1$wget, + metaBram_2_serverAdapterA_cnt_2$wget, + metaBram_2_serverAdapterA_cnt_3$wget, + metaBram_2_serverAdapterB_cnt_1$wget, + metaBram_2_serverAdapterB_cnt_2$wget, + metaBram_2_serverAdapterB_cnt_3$wget, + metaBram_3_serverAdapterA_cnt_1$wget, + metaBram_3_serverAdapterA_cnt_2$wget, + metaBram_3_serverAdapterA_cnt_3$wget, + metaBram_3_serverAdapterB_cnt_1$wget, + metaBram_3_serverAdapterB_cnt_2$wget, + metaBram_3_serverAdapterB_cnt_3$wget, wci_wci_Es_mCmd_w$wget, wci_wslv_wEdge$wget, wsi_Es_mCmd_w$wget, wti_Es_mCmd_w$wget; - wire [1 : 0] dataBram_serverAdapterA_s1_1$wget, - dataBram_serverAdapterA_writeWithResp$wget, - dataBram_serverAdapterB_s1_1$wget, - dataBram_serverAdapterB_writeWithResp$wget, - metaBram_serverAdapterA_1_s1_1$wget, - metaBram_serverAdapterA_1_writeWithResp$wget, - metaBram_serverAdapterA_2_s1_1$wget, - metaBram_serverAdapterA_2_writeWithResp$wget, - metaBram_serverAdapterA_3_s1_1$wget, - metaBram_serverAdapterA_3_writeWithResp$wget, - metaBram_serverAdapterA_s1_1$wget, - metaBram_serverAdapterA_writeWithResp$wget, - metaBram_serverAdapterB_1_s1_1$wget, - metaBram_serverAdapterB_1_writeWithResp$wget, - metaBram_serverAdapterB_2_s1_1$wget, - metaBram_serverAdapterB_2_writeWithResp$wget, - metaBram_serverAdapterB_3_s1_1$wget, - metaBram_serverAdapterB_3_writeWithResp$wget, - metaBram_serverAdapterB_s1_1$wget, - metaBram_serverAdapterB_writeWithResp$wget; - wire dataBram_serverAdapterA_cnt_1$whas, - dataBram_serverAdapterA_cnt_2$whas, - dataBram_serverAdapterA_cnt_3$whas, - dataBram_serverAdapterA_outData_deqCalled$whas, - dataBram_serverAdapterA_outData_enqData$whas, - dataBram_serverAdapterA_outData_outData$whas, - dataBram_serverAdapterA_s1_1$whas, - dataBram_serverAdapterA_writeWithResp$whas, - dataBram_serverAdapterB_cnt_1$whas, - dataBram_serverAdapterB_cnt_2$whas, - dataBram_serverAdapterB_cnt_3$whas, - dataBram_serverAdapterB_outData_deqCalled$whas, - dataBram_serverAdapterB_outData_enqData$whas, - dataBram_serverAdapterB_outData_outData$whas, - dataBram_serverAdapterB_s1_1$whas, - dataBram_serverAdapterB_writeWithResp$whas, - metaBram_serverAdapterA_1_cnt_1$whas, - metaBram_serverAdapterA_1_cnt_2$whas, - metaBram_serverAdapterA_1_cnt_3$whas, - metaBram_serverAdapterA_1_outData_deqCalled$whas, - metaBram_serverAdapterA_1_outData_enqData$whas, - metaBram_serverAdapterA_1_outData_outData$whas, - metaBram_serverAdapterA_1_s1_1$whas, - metaBram_serverAdapterA_1_writeWithResp$whas, - metaBram_serverAdapterA_2_cnt_1$whas, - metaBram_serverAdapterA_2_cnt_2$whas, - metaBram_serverAdapterA_2_cnt_3$whas, - metaBram_serverAdapterA_2_outData_deqCalled$whas, - metaBram_serverAdapterA_2_outData_enqData$whas, - metaBram_serverAdapterA_2_outData_outData$whas, - metaBram_serverAdapterA_2_s1_1$whas, - metaBram_serverAdapterA_2_writeWithResp$whas, - metaBram_serverAdapterA_3_cnt_1$whas, - metaBram_serverAdapterA_3_cnt_2$whas, - metaBram_serverAdapterA_3_cnt_3$whas, - metaBram_serverAdapterA_3_outData_deqCalled$whas, - metaBram_serverAdapterA_3_outData_enqData$whas, - metaBram_serverAdapterA_3_outData_outData$whas, - metaBram_serverAdapterA_3_s1_1$whas, - metaBram_serverAdapterA_3_writeWithResp$whas, - metaBram_serverAdapterA_cnt_1$whas, - metaBram_serverAdapterA_cnt_2$whas, - metaBram_serverAdapterA_cnt_3$whas, - metaBram_serverAdapterA_outData_deqCalled$whas, - metaBram_serverAdapterA_outData_enqData$whas, - metaBram_serverAdapterA_outData_outData$whas, - metaBram_serverAdapterA_s1_1$whas, - metaBram_serverAdapterA_writeWithResp$whas, - metaBram_serverAdapterB_1_cnt_1$whas, - metaBram_serverAdapterB_1_cnt_2$whas, - metaBram_serverAdapterB_1_cnt_3$whas, - metaBram_serverAdapterB_1_outData_deqCalled$whas, - metaBram_serverAdapterB_1_outData_enqData$whas, - metaBram_serverAdapterB_1_outData_outData$whas, - metaBram_serverAdapterB_1_s1_1$whas, - metaBram_serverAdapterB_1_writeWithResp$whas, - metaBram_serverAdapterB_2_cnt_1$whas, - metaBram_serverAdapterB_2_cnt_2$whas, - metaBram_serverAdapterB_2_cnt_3$whas, - metaBram_serverAdapterB_2_outData_deqCalled$whas, - metaBram_serverAdapterB_2_outData_enqData$whas, - metaBram_serverAdapterB_2_outData_outData$whas, - metaBram_serverAdapterB_2_s1_1$whas, - metaBram_serverAdapterB_2_writeWithResp$whas, - metaBram_serverAdapterB_3_cnt_1$whas, - metaBram_serverAdapterB_3_cnt_2$whas, - metaBram_serverAdapterB_3_cnt_3$whas, - metaBram_serverAdapterB_3_outData_deqCalled$whas, - metaBram_serverAdapterB_3_outData_enqData$whas, - metaBram_serverAdapterB_3_outData_outData$whas, - metaBram_serverAdapterB_3_s1_1$whas, - metaBram_serverAdapterB_3_writeWithResp$whas, - metaBram_serverAdapterB_cnt_1$whas, - metaBram_serverAdapterB_cnt_2$whas, - metaBram_serverAdapterB_cnt_3$whas, - metaBram_serverAdapterB_outData_deqCalled$whas, - metaBram_serverAdapterB_outData_enqData$whas, - metaBram_serverAdapterB_outData_outData$whas, - metaBram_serverAdapterB_s1_1$whas, - metaBram_serverAdapterB_writeWithResp$whas, + wire [1 : 0] dataBram_0_serverAdapterA_s1_1$wget, + dataBram_0_serverAdapterA_writeWithResp$wget, + dataBram_0_serverAdapterB_s1_1$wget, + dataBram_0_serverAdapterB_writeWithResp$wget, + metaBram_0_serverAdapterA_s1_1$wget, + metaBram_0_serverAdapterA_writeWithResp$wget, + metaBram_0_serverAdapterB_s1_1$wget, + metaBram_0_serverAdapterB_writeWithResp$wget, + metaBram_1_serverAdapterA_s1_1$wget, + metaBram_1_serverAdapterA_writeWithResp$wget, + metaBram_1_serverAdapterB_s1_1$wget, + metaBram_1_serverAdapterB_writeWithResp$wget, + metaBram_2_serverAdapterA_s1_1$wget, + metaBram_2_serverAdapterA_writeWithResp$wget, + metaBram_2_serverAdapterB_s1_1$wget, + metaBram_2_serverAdapterB_writeWithResp$wget, + metaBram_3_serverAdapterA_s1_1$wget, + metaBram_3_serverAdapterA_writeWithResp$wget, + metaBram_3_serverAdapterB_s1_1$wget, + metaBram_3_serverAdapterB_writeWithResp$wget; + wire dataBram_0_serverAdapterA_cnt_1$whas, + dataBram_0_serverAdapterA_cnt_2$whas, + dataBram_0_serverAdapterA_cnt_3$whas, + dataBram_0_serverAdapterA_outData_deqCalled$whas, + dataBram_0_serverAdapterA_outData_enqData$whas, + dataBram_0_serverAdapterA_outData_outData$whas, + dataBram_0_serverAdapterA_s1_1$whas, + dataBram_0_serverAdapterA_writeWithResp$whas, + dataBram_0_serverAdapterB_cnt_1$whas, + dataBram_0_serverAdapterB_cnt_2$whas, + dataBram_0_serverAdapterB_cnt_3$whas, + dataBram_0_serverAdapterB_outData_deqCalled$whas, + dataBram_0_serverAdapterB_outData_enqData$whas, + dataBram_0_serverAdapterB_outData_outData$whas, + dataBram_0_serverAdapterB_s1_1$whas, + dataBram_0_serverAdapterB_writeWithResp$whas, + metaBram_0_serverAdapterA_cnt_1$whas, + metaBram_0_serverAdapterA_cnt_2$whas, + metaBram_0_serverAdapterA_cnt_3$whas, + metaBram_0_serverAdapterA_outData_deqCalled$whas, + metaBram_0_serverAdapterA_outData_enqData$whas, + metaBram_0_serverAdapterA_outData_outData$whas, + metaBram_0_serverAdapterA_s1_1$whas, + metaBram_0_serverAdapterA_writeWithResp$whas, + metaBram_0_serverAdapterB_cnt_1$whas, + metaBram_0_serverAdapterB_cnt_2$whas, + metaBram_0_serverAdapterB_cnt_3$whas, + metaBram_0_serverAdapterB_outData_deqCalled$whas, + metaBram_0_serverAdapterB_outData_enqData$whas, + metaBram_0_serverAdapterB_outData_outData$whas, + metaBram_0_serverAdapterB_s1_1$whas, + metaBram_0_serverAdapterB_writeWithResp$whas, + metaBram_1_serverAdapterA_cnt_1$whas, + metaBram_1_serverAdapterA_cnt_2$whas, + metaBram_1_serverAdapterA_cnt_3$whas, + metaBram_1_serverAdapterA_outData_deqCalled$whas, + metaBram_1_serverAdapterA_outData_enqData$whas, + metaBram_1_serverAdapterA_outData_outData$whas, + metaBram_1_serverAdapterA_s1_1$whas, + metaBram_1_serverAdapterA_writeWithResp$whas, + metaBram_1_serverAdapterB_cnt_1$whas, + metaBram_1_serverAdapterB_cnt_2$whas, + metaBram_1_serverAdapterB_cnt_3$whas, + metaBram_1_serverAdapterB_outData_deqCalled$whas, + metaBram_1_serverAdapterB_outData_enqData$whas, + metaBram_1_serverAdapterB_outData_outData$whas, + metaBram_1_serverAdapterB_s1_1$whas, + metaBram_1_serverAdapterB_writeWithResp$whas, + metaBram_2_serverAdapterA_cnt_1$whas, + metaBram_2_serverAdapterA_cnt_2$whas, + metaBram_2_serverAdapterA_cnt_3$whas, + metaBram_2_serverAdapterA_outData_deqCalled$whas, + metaBram_2_serverAdapterA_outData_enqData$whas, + metaBram_2_serverAdapterA_outData_outData$whas, + metaBram_2_serverAdapterA_s1_1$whas, + metaBram_2_serverAdapterA_writeWithResp$whas, + metaBram_2_serverAdapterB_cnt_1$whas, + metaBram_2_serverAdapterB_cnt_2$whas, + metaBram_2_serverAdapterB_cnt_3$whas, + metaBram_2_serverAdapterB_outData_deqCalled$whas, + metaBram_2_serverAdapterB_outData_enqData$whas, + metaBram_2_serverAdapterB_outData_outData$whas, + metaBram_2_serverAdapterB_s1_1$whas, + metaBram_2_serverAdapterB_writeWithResp$whas, + metaBram_3_serverAdapterA_cnt_1$whas, + metaBram_3_serverAdapterA_cnt_2$whas, + metaBram_3_serverAdapterA_cnt_3$whas, + metaBram_3_serverAdapterA_outData_deqCalled$whas, + metaBram_3_serverAdapterA_outData_enqData$whas, + metaBram_3_serverAdapterA_outData_outData$whas, + metaBram_3_serverAdapterA_s1_1$whas, + metaBram_3_serverAdapterA_writeWithResp$whas, + metaBram_3_serverAdapterB_cnt_1$whas, + metaBram_3_serverAdapterB_cnt_2$whas, + metaBram_3_serverAdapterB_cnt_3$whas, + metaBram_3_serverAdapterB_outData_deqCalled$whas, + metaBram_3_serverAdapterB_outData_enqData$whas, + metaBram_3_serverAdapterB_outData_outData$whas, + metaBram_3_serverAdapterB_s1_1$whas, + metaBram_3_serverAdapterB_writeWithResp$whas, nowW$whas, statusReg_w$whas, wci_wci_Es_mAddrSpace_w$wget, @@ -411,25 +411,25 @@ module mkWSICaptureWorker4B(wciS0_Clk, wire [31 : 0] controlReg$D_IN; wire controlReg$EN; - // register dataBram_serverAdapterA_cnt - reg [2 : 0] dataBram_serverAdapterA_cnt; - wire [2 : 0] dataBram_serverAdapterA_cnt$D_IN; - wire dataBram_serverAdapterA_cnt$EN; + // register dataBram_0_serverAdapterA_cnt + reg [2 : 0] dataBram_0_serverAdapterA_cnt; + wire [2 : 0] dataBram_0_serverAdapterA_cnt$D_IN; + wire dataBram_0_serverAdapterA_cnt$EN; - // register dataBram_serverAdapterA_s1 - reg [1 : 0] dataBram_serverAdapterA_s1; - wire [1 : 0] dataBram_serverAdapterA_s1$D_IN; - wire dataBram_serverAdapterA_s1$EN; + // register dataBram_0_serverAdapterA_s1 + reg [1 : 0] dataBram_0_serverAdapterA_s1; + wire [1 : 0] dataBram_0_serverAdapterA_s1$D_IN; + wire dataBram_0_serverAdapterA_s1$EN; - // register dataBram_serverAdapterB_cnt - reg [2 : 0] dataBram_serverAdapterB_cnt; - wire [2 : 0] dataBram_serverAdapterB_cnt$D_IN; - wire dataBram_serverAdapterB_cnt$EN; + // register dataBram_0_serverAdapterB_cnt + reg [2 : 0] dataBram_0_serverAdapterB_cnt; + wire [2 : 0] dataBram_0_serverAdapterB_cnt$D_IN; + wire dataBram_0_serverAdapterB_cnt$EN; - // register dataBram_serverAdapterB_s1 - reg [1 : 0] dataBram_serverAdapterB_s1; - wire [1 : 0] dataBram_serverAdapterB_s1$D_IN; - wire dataBram_serverAdapterB_s1$EN; + // register dataBram_0_serverAdapterB_s1 + reg [1 : 0] dataBram_0_serverAdapterB_s1; + wire [1 : 0] dataBram_0_serverAdapterB_s1$D_IN; + wire dataBram_0_serverAdapterB_s1$EN; // register dataCount reg [31 : 0] dataCount; @@ -445,85 +445,85 @@ module mkWSICaptureWorker4B(wciS0_Clk, wire [13 : 0] mesgLengthSoFar$D_IN; wire mesgLengthSoFar$EN; - // register metaBram_serverAdapterA_1_cnt - reg [2 : 0] metaBram_serverAdapterA_1_cnt; - wire [2 : 0] metaBram_serverAdapterA_1_cnt$D_IN; - wire metaBram_serverAdapterA_1_cnt$EN; - - // register metaBram_serverAdapterA_1_s1 - reg [1 : 0] metaBram_serverAdapterA_1_s1; - wire [1 : 0] metaBram_serverAdapterA_1_s1$D_IN; - wire metaBram_serverAdapterA_1_s1$EN; - - // register metaBram_serverAdapterA_2_cnt - reg [2 : 0] metaBram_serverAdapterA_2_cnt; - wire [2 : 0] metaBram_serverAdapterA_2_cnt$D_IN; - wire metaBram_serverAdapterA_2_cnt$EN; - - // register metaBram_serverAdapterA_2_s1 - reg [1 : 0] metaBram_serverAdapterA_2_s1; - wire [1 : 0] metaBram_serverAdapterA_2_s1$D_IN; - wire metaBram_serverAdapterA_2_s1$EN; - - // register metaBram_serverAdapterA_3_cnt - reg [2 : 0] metaBram_serverAdapterA_3_cnt; - wire [2 : 0] metaBram_serverAdapterA_3_cnt$D_IN; - wire metaBram_serverAdapterA_3_cnt$EN; - - // register metaBram_serverAdapterA_3_s1 - reg [1 : 0] metaBram_serverAdapterA_3_s1; - wire [1 : 0] metaBram_serverAdapterA_3_s1$D_IN; - wire metaBram_serverAdapterA_3_s1$EN; - - // register metaBram_serverAdapterA_cnt - reg [2 : 0] metaBram_serverAdapterA_cnt; - wire [2 : 0] metaBram_serverAdapterA_cnt$D_IN; - wire metaBram_serverAdapterA_cnt$EN; - - // register metaBram_serverAdapterA_s1 - reg [1 : 0] metaBram_serverAdapterA_s1; - wire [1 : 0] metaBram_serverAdapterA_s1$D_IN; - wire metaBram_serverAdapterA_s1$EN; - - // register metaBram_serverAdapterB_1_cnt - reg [2 : 0] metaBram_serverAdapterB_1_cnt; - wire [2 : 0] metaBram_serverAdapterB_1_cnt$D_IN; - wire metaBram_serverAdapterB_1_cnt$EN; - - // register metaBram_serverAdapterB_1_s1 - reg [1 : 0] metaBram_serverAdapterB_1_s1; - wire [1 : 0] metaBram_serverAdapterB_1_s1$D_IN; - wire metaBram_serverAdapterB_1_s1$EN; - - // register metaBram_serverAdapterB_2_cnt - reg [2 : 0] metaBram_serverAdapterB_2_cnt; - wire [2 : 0] metaBram_serverAdapterB_2_cnt$D_IN; - wire metaBram_serverAdapterB_2_cnt$EN; - - // register metaBram_serverAdapterB_2_s1 - reg [1 : 0] metaBram_serverAdapterB_2_s1; - wire [1 : 0] metaBram_serverAdapterB_2_s1$D_IN; - wire metaBram_serverAdapterB_2_s1$EN; - - // register metaBram_serverAdapterB_3_cnt - reg [2 : 0] metaBram_serverAdapterB_3_cnt; - wire [2 : 0] metaBram_serverAdapterB_3_cnt$D_IN; - wire metaBram_serverAdapterB_3_cnt$EN; - - // register metaBram_serverAdapterB_3_s1 - reg [1 : 0] metaBram_serverAdapterB_3_s1; - wire [1 : 0] metaBram_serverAdapterB_3_s1$D_IN; - wire metaBram_serverAdapterB_3_s1$EN; - - // register metaBram_serverAdapterB_cnt - reg [2 : 0] metaBram_serverAdapterB_cnt; - wire [2 : 0] metaBram_serverAdapterB_cnt$D_IN; - wire metaBram_serverAdapterB_cnt$EN; - - // register metaBram_serverAdapterB_s1 - reg [1 : 0] metaBram_serverAdapterB_s1; - wire [1 : 0] metaBram_serverAdapterB_s1$D_IN; - wire metaBram_serverAdapterB_s1$EN; + // register metaBram_0_serverAdapterA_cnt + reg [2 : 0] metaBram_0_serverAdapterA_cnt; + wire [2 : 0] metaBram_0_serverAdapterA_cnt$D_IN; + wire metaBram_0_serverAdapterA_cnt$EN; + + // register metaBram_0_serverAdapterA_s1 + reg [1 : 0] metaBram_0_serverAdapterA_s1; + wire [1 : 0] metaBram_0_serverAdapterA_s1$D_IN; + wire metaBram_0_serverAdapterA_s1$EN; + + // register metaBram_0_serverAdapterB_cnt + reg [2 : 0] metaBram_0_serverAdapterB_cnt; + wire [2 : 0] metaBram_0_serverAdapterB_cnt$D_IN; + wire metaBram_0_serverAdapterB_cnt$EN; + + // register metaBram_0_serverAdapterB_s1 + reg [1 : 0] metaBram_0_serverAdapterB_s1; + wire [1 : 0] metaBram_0_serverAdapterB_s1$D_IN; + wire metaBram_0_serverAdapterB_s1$EN; + + // register metaBram_1_serverAdapterA_cnt + reg [2 : 0] metaBram_1_serverAdapterA_cnt; + wire [2 : 0] metaBram_1_serverAdapterA_cnt$D_IN; + wire metaBram_1_serverAdapterA_cnt$EN; + + // register metaBram_1_serverAdapterA_s1 + reg [1 : 0] metaBram_1_serverAdapterA_s1; + wire [1 : 0] metaBram_1_serverAdapterA_s1$D_IN; + wire metaBram_1_serverAdapterA_s1$EN; + + // register metaBram_1_serverAdapterB_cnt + reg [2 : 0] metaBram_1_serverAdapterB_cnt; + wire [2 : 0] metaBram_1_serverAdapterB_cnt$D_IN; + wire metaBram_1_serverAdapterB_cnt$EN; + + // register metaBram_1_serverAdapterB_s1 + reg [1 : 0] metaBram_1_serverAdapterB_s1; + wire [1 : 0] metaBram_1_serverAdapterB_s1$D_IN; + wire metaBram_1_serverAdapterB_s1$EN; + + // register metaBram_2_serverAdapterA_cnt + reg [2 : 0] metaBram_2_serverAdapterA_cnt; + wire [2 : 0] metaBram_2_serverAdapterA_cnt$D_IN; + wire metaBram_2_serverAdapterA_cnt$EN; + + // register metaBram_2_serverAdapterA_s1 + reg [1 : 0] metaBram_2_serverAdapterA_s1; + wire [1 : 0] metaBram_2_serverAdapterA_s1$D_IN; + wire metaBram_2_serverAdapterA_s1$EN; + + // register metaBram_2_serverAdapterB_cnt + reg [2 : 0] metaBram_2_serverAdapterB_cnt; + wire [2 : 0] metaBram_2_serverAdapterB_cnt$D_IN; + wire metaBram_2_serverAdapterB_cnt$EN; + + // register metaBram_2_serverAdapterB_s1 + reg [1 : 0] metaBram_2_serverAdapterB_s1; + wire [1 : 0] metaBram_2_serverAdapterB_s1$D_IN; + wire metaBram_2_serverAdapterB_s1$EN; + + // register metaBram_3_serverAdapterA_cnt + reg [2 : 0] metaBram_3_serverAdapterA_cnt; + wire [2 : 0] metaBram_3_serverAdapterA_cnt$D_IN; + wire metaBram_3_serverAdapterA_cnt$EN; + + // register metaBram_3_serverAdapterA_s1 + reg [1 : 0] metaBram_3_serverAdapterA_s1; + wire [1 : 0] metaBram_3_serverAdapterA_s1$D_IN; + wire metaBram_3_serverAdapterA_s1$EN; + + // register metaBram_3_serverAdapterB_cnt + reg [2 : 0] metaBram_3_serverAdapterB_cnt; + wire [2 : 0] metaBram_3_serverAdapterB_cnt$D_IN; + wire metaBram_3_serverAdapterB_cnt$EN; + + // register metaBram_3_serverAdapterB_s1 + reg [1 : 0] metaBram_3_serverAdapterB_s1; + wire [1 : 0] metaBram_3_serverAdapterB_s1$D_IN; + wire metaBram_3_serverAdapterB_s1$EN; // register metaCount reg [31 : 0] metaCount; @@ -570,10 +570,10 @@ module mkWSICaptureWorker4B(wciS0_Clk, wire [1 : 0] wci_wslv_reqF_countReg$D_IN; wire wci_wslv_reqF_countReg$EN; - // register wci_wslv_respF_c_r - reg [1 : 0] wci_wslv_respF_c_r; - wire [1 : 0] wci_wslv_respF_c_r$D_IN; - wire wci_wslv_respF_c_r$EN; + // register wci_wslv_respF_cntr_r + reg [1 : 0] wci_wslv_respF_cntr_r; + wire [1 : 0] wci_wslv_respF_cntr_r$D_IN; + wire wci_wslv_respF_cntr_r$EN; // register wci_wslv_respF_q_0 reg [33 : 0] wci_wslv_respF_q_0; @@ -670,150 +670,150 @@ module mkWSICaptureWorker4B(wciS0_Clk, reg wtiS_operateD; wire wtiS_operateD$D_IN, wtiS_operateD$EN; - // ports of submodule dataBram_memory - wire [31 : 0] dataBram_memory$DIA, - dataBram_memory$DIB, - dataBram_memory$DOA, - dataBram_memory$DOB; - wire [9 : 0] dataBram_memory$ADDRA, dataBram_memory$ADDRB; - wire dataBram_memory$ENA, - dataBram_memory$ENB, - dataBram_memory$WEA, - dataBram_memory$WEB; - - // ports of submodule dataBram_serverAdapterA_outDataCore - wire [31 : 0] dataBram_serverAdapterA_outDataCore$D_IN, - dataBram_serverAdapterA_outDataCore$D_OUT; - wire dataBram_serverAdapterA_outDataCore$CLR, - dataBram_serverAdapterA_outDataCore$DEQ, - dataBram_serverAdapterA_outDataCore$EMPTY_N, - dataBram_serverAdapterA_outDataCore$ENQ, - dataBram_serverAdapterA_outDataCore$FULL_N; - - // ports of submodule dataBram_serverAdapterB_outDataCore - wire [31 : 0] dataBram_serverAdapterB_outDataCore$D_IN, - dataBram_serverAdapterB_outDataCore$D_OUT; - wire dataBram_serverAdapterB_outDataCore$CLR, - dataBram_serverAdapterB_outDataCore$DEQ, - dataBram_serverAdapterB_outDataCore$EMPTY_N, - dataBram_serverAdapterB_outDataCore$ENQ, - dataBram_serverAdapterB_outDataCore$FULL_N; - - // ports of submodule metaBram_memory - wire [31 : 0] metaBram_memory$DIA, - metaBram_memory$DIB, - metaBram_memory$DOA, - metaBram_memory$DOB; - wire [9 : 0] metaBram_memory$ADDRA, metaBram_memory$ADDRB; - wire metaBram_memory$ENA, - metaBram_memory$ENB, - metaBram_memory$WEA, - metaBram_memory$WEB; - - // ports of submodule metaBram_memory_1 - wire [31 : 0] metaBram_memory_1$DIA, - metaBram_memory_1$DIB, - metaBram_memory_1$DOA, - metaBram_memory_1$DOB; - wire [9 : 0] metaBram_memory_1$ADDRA, metaBram_memory_1$ADDRB; - wire metaBram_memory_1$ENA, - metaBram_memory_1$ENB, - metaBram_memory_1$WEA, - metaBram_memory_1$WEB; - - // ports of submodule metaBram_memory_2 - wire [31 : 0] metaBram_memory_2$DIA, - metaBram_memory_2$DIB, - metaBram_memory_2$DOA, - metaBram_memory_2$DOB; - wire [9 : 0] metaBram_memory_2$ADDRA, metaBram_memory_2$ADDRB; - wire metaBram_memory_2$ENA, - metaBram_memory_2$ENB, - metaBram_memory_2$WEA, - metaBram_memory_2$WEB; - - // ports of submodule metaBram_memory_3 - wire [31 : 0] metaBram_memory_3$DIA, - metaBram_memory_3$DIB, - metaBram_memory_3$DOA, - metaBram_memory_3$DOB; - wire [9 : 0] metaBram_memory_3$ADDRA, metaBram_memory_3$ADDRB; - wire metaBram_memory_3$ENA, - metaBram_memory_3$ENB, - metaBram_memory_3$WEA, - metaBram_memory_3$WEB; - - // ports of submodule metaBram_serverAdapterA_1_outDataCore - wire [31 : 0] metaBram_serverAdapterA_1_outDataCore$D_IN, - metaBram_serverAdapterA_1_outDataCore$D_OUT; - wire metaBram_serverAdapterA_1_outDataCore$CLR, - metaBram_serverAdapterA_1_outDataCore$DEQ, - metaBram_serverAdapterA_1_outDataCore$EMPTY_N, - metaBram_serverAdapterA_1_outDataCore$ENQ, - metaBram_serverAdapterA_1_outDataCore$FULL_N; - - // ports of submodule metaBram_serverAdapterA_2_outDataCore - wire [31 : 0] metaBram_serverAdapterA_2_outDataCore$D_IN, - metaBram_serverAdapterA_2_outDataCore$D_OUT; - wire metaBram_serverAdapterA_2_outDataCore$CLR, - metaBram_serverAdapterA_2_outDataCore$DEQ, - metaBram_serverAdapterA_2_outDataCore$EMPTY_N, - metaBram_serverAdapterA_2_outDataCore$ENQ, - metaBram_serverAdapterA_2_outDataCore$FULL_N; - - // ports of submodule metaBram_serverAdapterA_3_outDataCore - wire [31 : 0] metaBram_serverAdapterA_3_outDataCore$D_IN, - metaBram_serverAdapterA_3_outDataCore$D_OUT; - wire metaBram_serverAdapterA_3_outDataCore$CLR, - metaBram_serverAdapterA_3_outDataCore$DEQ, - metaBram_serverAdapterA_3_outDataCore$EMPTY_N, - metaBram_serverAdapterA_3_outDataCore$ENQ, - metaBram_serverAdapterA_3_outDataCore$FULL_N; - - // ports of submodule metaBram_serverAdapterA_outDataCore - wire [31 : 0] metaBram_serverAdapterA_outDataCore$D_IN, - metaBram_serverAdapterA_outDataCore$D_OUT; - wire metaBram_serverAdapterA_outDataCore$CLR, - metaBram_serverAdapterA_outDataCore$DEQ, - metaBram_serverAdapterA_outDataCore$EMPTY_N, - metaBram_serverAdapterA_outDataCore$ENQ, - metaBram_serverAdapterA_outDataCore$FULL_N; - - // ports of submodule metaBram_serverAdapterB_1_outDataCore - wire [31 : 0] metaBram_serverAdapterB_1_outDataCore$D_IN, - metaBram_serverAdapterB_1_outDataCore$D_OUT; - wire metaBram_serverAdapterB_1_outDataCore$CLR, - metaBram_serverAdapterB_1_outDataCore$DEQ, - metaBram_serverAdapterB_1_outDataCore$EMPTY_N, - metaBram_serverAdapterB_1_outDataCore$ENQ, - metaBram_serverAdapterB_1_outDataCore$FULL_N; - - // ports of submodule metaBram_serverAdapterB_2_outDataCore - wire [31 : 0] metaBram_serverAdapterB_2_outDataCore$D_IN, - metaBram_serverAdapterB_2_outDataCore$D_OUT; - wire metaBram_serverAdapterB_2_outDataCore$CLR, - metaBram_serverAdapterB_2_outDataCore$DEQ, - metaBram_serverAdapterB_2_outDataCore$EMPTY_N, - metaBram_serverAdapterB_2_outDataCore$ENQ, - metaBram_serverAdapterB_2_outDataCore$FULL_N; - - // ports of submodule metaBram_serverAdapterB_3_outDataCore - wire [31 : 0] metaBram_serverAdapterB_3_outDataCore$D_IN, - metaBram_serverAdapterB_3_outDataCore$D_OUT; - wire metaBram_serverAdapterB_3_outDataCore$CLR, - metaBram_serverAdapterB_3_outDataCore$DEQ, - metaBram_serverAdapterB_3_outDataCore$EMPTY_N, - metaBram_serverAdapterB_3_outDataCore$ENQ, - metaBram_serverAdapterB_3_outDataCore$FULL_N; - - // ports of submodule metaBram_serverAdapterB_outDataCore - wire [31 : 0] metaBram_serverAdapterB_outDataCore$D_IN, - metaBram_serverAdapterB_outDataCore$D_OUT; - wire metaBram_serverAdapterB_outDataCore$CLR, - metaBram_serverAdapterB_outDataCore$DEQ, - metaBram_serverAdapterB_outDataCore$EMPTY_N, - metaBram_serverAdapterB_outDataCore$ENQ, - metaBram_serverAdapterB_outDataCore$FULL_N; + // ports of submodule dataBram_0_memory + wire [31 : 0] dataBram_0_memory$DIA, + dataBram_0_memory$DIB, + dataBram_0_memory$DOA, + dataBram_0_memory$DOB; + wire [9 : 0] dataBram_0_memory$ADDRA, dataBram_0_memory$ADDRB; + wire dataBram_0_memory$ENA, + dataBram_0_memory$ENB, + dataBram_0_memory$WEA, + dataBram_0_memory$WEB; + + // ports of submodule dataBram_0_serverAdapterA_outDataCore + wire [31 : 0] dataBram_0_serverAdapterA_outDataCore$D_IN, + dataBram_0_serverAdapterA_outDataCore$D_OUT; + wire dataBram_0_serverAdapterA_outDataCore$CLR, + dataBram_0_serverAdapterA_outDataCore$DEQ, + dataBram_0_serverAdapterA_outDataCore$EMPTY_N, + dataBram_0_serverAdapterA_outDataCore$ENQ, + dataBram_0_serverAdapterA_outDataCore$FULL_N; + + // ports of submodule dataBram_0_serverAdapterB_outDataCore + wire [31 : 0] dataBram_0_serverAdapterB_outDataCore$D_IN, + dataBram_0_serverAdapterB_outDataCore$D_OUT; + wire dataBram_0_serverAdapterB_outDataCore$CLR, + dataBram_0_serverAdapterB_outDataCore$DEQ, + dataBram_0_serverAdapterB_outDataCore$EMPTY_N, + dataBram_0_serverAdapterB_outDataCore$ENQ, + dataBram_0_serverAdapterB_outDataCore$FULL_N; + + // ports of submodule metaBram_0_memory + wire [31 : 0] metaBram_0_memory$DIA, + metaBram_0_memory$DIB, + metaBram_0_memory$DOA, + metaBram_0_memory$DOB; + wire [9 : 0] metaBram_0_memory$ADDRA, metaBram_0_memory$ADDRB; + wire metaBram_0_memory$ENA, + metaBram_0_memory$ENB, + metaBram_0_memory$WEA, + metaBram_0_memory$WEB; + + // ports of submodule metaBram_0_serverAdapterA_outDataCore + wire [31 : 0] metaBram_0_serverAdapterA_outDataCore$D_IN, + metaBram_0_serverAdapterA_outDataCore$D_OUT; + wire metaBram_0_serverAdapterA_outDataCore$CLR, + metaBram_0_serverAdapterA_outDataCore$DEQ, + metaBram_0_serverAdapterA_outDataCore$EMPTY_N, + metaBram_0_serverAdapterA_outDataCore$ENQ, + metaBram_0_serverAdapterA_outDataCore$FULL_N; + + // ports of submodule metaBram_0_serverAdapterB_outDataCore + wire [31 : 0] metaBram_0_serverAdapterB_outDataCore$D_IN, + metaBram_0_serverAdapterB_outDataCore$D_OUT; + wire metaBram_0_serverAdapterB_outDataCore$CLR, + metaBram_0_serverAdapterB_outDataCore$DEQ, + metaBram_0_serverAdapterB_outDataCore$EMPTY_N, + metaBram_0_serverAdapterB_outDataCore$ENQ, + metaBram_0_serverAdapterB_outDataCore$FULL_N; + + // ports of submodule metaBram_1_memory + wire [31 : 0] metaBram_1_memory$DIA, + metaBram_1_memory$DIB, + metaBram_1_memory$DOA, + metaBram_1_memory$DOB; + wire [9 : 0] metaBram_1_memory$ADDRA, metaBram_1_memory$ADDRB; + wire metaBram_1_memory$ENA, + metaBram_1_memory$ENB, + metaBram_1_memory$WEA, + metaBram_1_memory$WEB; + + // ports of submodule metaBram_1_serverAdapterA_outDataCore + wire [31 : 0] metaBram_1_serverAdapterA_outDataCore$D_IN, + metaBram_1_serverAdapterA_outDataCore$D_OUT; + wire metaBram_1_serverAdapterA_outDataCore$CLR, + metaBram_1_serverAdapterA_outDataCore$DEQ, + metaBram_1_serverAdapterA_outDataCore$EMPTY_N, + metaBram_1_serverAdapterA_outDataCore$ENQ, + metaBram_1_serverAdapterA_outDataCore$FULL_N; + + // ports of submodule metaBram_1_serverAdapterB_outDataCore + wire [31 : 0] metaBram_1_serverAdapterB_outDataCore$D_IN, + metaBram_1_serverAdapterB_outDataCore$D_OUT; + wire metaBram_1_serverAdapterB_outDataCore$CLR, + metaBram_1_serverAdapterB_outDataCore$DEQ, + metaBram_1_serverAdapterB_outDataCore$EMPTY_N, + metaBram_1_serverAdapterB_outDataCore$ENQ, + metaBram_1_serverAdapterB_outDataCore$FULL_N; + + // ports of submodule metaBram_2_memory + wire [31 : 0] metaBram_2_memory$DIA, + metaBram_2_memory$DIB, + metaBram_2_memory$DOA, + metaBram_2_memory$DOB; + wire [9 : 0] metaBram_2_memory$ADDRA, metaBram_2_memory$ADDRB; + wire metaBram_2_memory$ENA, + metaBram_2_memory$ENB, + metaBram_2_memory$WEA, + metaBram_2_memory$WEB; + + // ports of submodule metaBram_2_serverAdapterA_outDataCore + wire [31 : 0] metaBram_2_serverAdapterA_outDataCore$D_IN, + metaBram_2_serverAdapterA_outDataCore$D_OUT; + wire metaBram_2_serverAdapterA_outDataCore$CLR, + metaBram_2_serverAdapterA_outDataCore$DEQ, + metaBram_2_serverAdapterA_outDataCore$EMPTY_N, + metaBram_2_serverAdapterA_outDataCore$ENQ, + metaBram_2_serverAdapterA_outDataCore$FULL_N; + + // ports of submodule metaBram_2_serverAdapterB_outDataCore + wire [31 : 0] metaBram_2_serverAdapterB_outDataCore$D_IN, + metaBram_2_serverAdapterB_outDataCore$D_OUT; + wire metaBram_2_serverAdapterB_outDataCore$CLR, + metaBram_2_serverAdapterB_outDataCore$DEQ, + metaBram_2_serverAdapterB_outDataCore$EMPTY_N, + metaBram_2_serverAdapterB_outDataCore$ENQ, + metaBram_2_serverAdapterB_outDataCore$FULL_N; + + // ports of submodule metaBram_3_memory + wire [31 : 0] metaBram_3_memory$DIA, + metaBram_3_memory$DIB, + metaBram_3_memory$DOA, + metaBram_3_memory$DOB; + wire [9 : 0] metaBram_3_memory$ADDRA, metaBram_3_memory$ADDRB; + wire metaBram_3_memory$ENA, + metaBram_3_memory$ENB, + metaBram_3_memory$WEA, + metaBram_3_memory$WEB; + + // ports of submodule metaBram_3_serverAdapterA_outDataCore + wire [31 : 0] metaBram_3_serverAdapterA_outDataCore$D_IN, + metaBram_3_serverAdapterA_outDataCore$D_OUT; + wire metaBram_3_serverAdapterA_outDataCore$CLR, + metaBram_3_serverAdapterA_outDataCore$DEQ, + metaBram_3_serverAdapterA_outDataCore$EMPTY_N, + metaBram_3_serverAdapterA_outDataCore$ENQ, + metaBram_3_serverAdapterA_outDataCore$FULL_N; + + // ports of submodule metaBram_3_serverAdapterB_outDataCore + wire [31 : 0] metaBram_3_serverAdapterB_outDataCore$D_IN, + metaBram_3_serverAdapterB_outDataCore$D_OUT; + wire metaBram_3_serverAdapterB_outDataCore$CLR, + metaBram_3_serverAdapterB_outDataCore$DEQ, + metaBram_3_serverAdapterB_outDataCore$EMPTY_N, + metaBram_3_serverAdapterB_outDataCore$ENQ, + metaBram_3_serverAdapterB_outDataCore$FULL_N; // ports of submodule splaF wire [2 : 0] splaF$D_IN, splaF$D_OUT; @@ -835,17 +835,18 @@ module mkWSICaptureWorker4B(wciS0_Clk, wsiS_reqFifo$FULL_N; // rule scheduling signals - wire CAN_FIRE_RL_wci_cfrd, - WILL_FIRE_RL_dataBram_serverAdapterB_outData_enqAndDeq, - WILL_FIRE_RL_dataBram_serverAdapterB_stageReadResponseAlways, - WILL_FIRE_RL_metaBram_serverAdapterB_1_outData_enqAndDeq, - WILL_FIRE_RL_metaBram_serverAdapterB_1_stageReadResponseAlways, - WILL_FIRE_RL_metaBram_serverAdapterB_2_outData_enqAndDeq, - WILL_FIRE_RL_metaBram_serverAdapterB_2_stageReadResponseAlways, - WILL_FIRE_RL_metaBram_serverAdapterB_3_outData_enqAndDeq, - WILL_FIRE_RL_metaBram_serverAdapterB_3_stageReadResponseAlways, - WILL_FIRE_RL_metaBram_serverAdapterB_outData_enqAndDeq, - WILL_FIRE_RL_metaBram_serverAdapterB_stageReadResponseAlways, + wire CAN_FIRE_RL_advance_split_response, + CAN_FIRE_RL_wci_cfrd, + WILL_FIRE_RL_dataBram_0_serverAdapterB_outData_enqAndDeq, + WILL_FIRE_RL_dataBram_0_serverAdapterB_stageReadResponseAlways, + WILL_FIRE_RL_metaBram_0_serverAdapterB_outData_enqAndDeq, + WILL_FIRE_RL_metaBram_0_serverAdapterB_stageReadResponseAlways, + WILL_FIRE_RL_metaBram_1_serverAdapterB_outData_enqAndDeq, + WILL_FIRE_RL_metaBram_1_serverAdapterB_stageReadResponseAlways, + WILL_FIRE_RL_metaBram_2_serverAdapterB_outData_enqAndDeq, + WILL_FIRE_RL_metaBram_2_serverAdapterB_stageReadResponseAlways, + WILL_FIRE_RL_metaBram_3_serverAdapterB_outData_enqAndDeq, + WILL_FIRE_RL_metaBram_3_serverAdapterB_stageReadResponseAlways, WILL_FIRE_RL_wci_cfrd, WILL_FIRE_RL_wci_cfwr, WILL_FIRE_RL_wci_ctrl_IsO, @@ -866,8 +867,7 @@ module mkWSICaptureWorker4B(wciS0_Clk, MUX_wci_wslv_respF_x_wire$wset_1__VAL_2, MUX_wci_wslv_respF_x_wire$wset_1__VAL_3; wire [31 : 0] MUX_dataCount$write_1__VAL_2, MUX_metaCount$write_1__VAL_2; - wire [1 : 0] MUX_wci_wslv_respF_c_r$write_1__VAL_1, - MUX_wci_wslv_respF_c_r$write_1__VAL_2; + wire [1 : 0] MUX_wci_wslv_respF_cntr_r$write_1__VAL_2; wire MUX_controlReg$write_1__SEL_1, MUX_controlReg$write_1__SEL_2, MUX_dataCount$write_1__SEL_1, @@ -877,56 +877,60 @@ module mkWSICaptureWorker4B(wciS0_Clk, MUX_splitReadInFlight$write_1__SEL_1, MUX_wci_wslv_illegalEdge$write_1__SEL_1, MUX_wci_wslv_illegalEdge$write_1__VAL_1, + MUX_wci_wslv_respF_q_0$write_1__SEL_1, MUX_wci_wslv_respF_q_0$write_1__SEL_2, + MUX_wci_wslv_respF_q_1$write_1__SEL_1, MUX_wci_wslv_respF_q_1$write_1__SEL_2, MUX_wci_wslv_respF_x_wire$wset_1__SEL_1, MUX_wci_wslv_respF_x_wire$wset_1__SEL_3, MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3; // remaining internal signals - reg [63 : 0] v__h25452, - v__h26500, - v__h26795, - v__h27000, - v__h3718, - v__h3893, - v__h4037; - reg [31 : 0] IF_splaF_first__97_BITS_1_TO_0_99_EQ_0_00_THEN_ETC___d951, - v__h26981; - reg CASE_splaFD_OUT_BITS_1_TO_0_NOT_splaFD_OUT_B_ETC__q1, - IF_splaF_first__97_BITS_1_TO_0_99_EQ_0_00_THEN_ETC___d918, - IF_wci_wslv_reqF_first__5_BITS_35_TO_34_81_EQ__ETC___d994, - IF_wci_wslv_reqF_first__5_BITS_63_TO_52_65_EQ__ETC___d998; - wire [31 : 0] g_data__h28071, - rdat___1__h27078, - rdat___1__h27162, - rdat___1__h27217, - rdat___1__h27231, - rdat___1__h27239, - v__h25581, - y_avValue__h26208, - y_avValue__h26252, - y_avValue__h26292, - y_avValue__h26332, - y_avValue__h26372; - wire [13 : 0] mlB__h23348, mlInc__h23347; - wire [2 : 0] dataBram_serverAdapterB_cnt_21_PLUS_IF_dataBra_ETC___d327, - metaBram_serverAdapterB_1_cnt_57_PLUS_IF_metaB_ETC___d563, - metaBram_serverAdapterB_2_cnt_75_PLUS_IF_metaB_ETC___d681, - metaBram_serverAdapterB_3_cnt_93_PLUS_IF_metaB_ETC___d799, - metaBram_serverAdapterB_cnt_39_PLUS_IF_metaBra_ETC___d445, - x__h23396, - x__h23408, - x__h23420, - y__h23397, - y__h23409, - y__h23421; - wire IF_splaF_first__97_BITS_1_TO_0_99_EQ_0_00_THEN_ETC___d927, - NOT_controlReg_30_BIT_0_31_32_OR_controlReg_30_ETC___d856, - controlReg_30_BIT_0_31_AND_NOT_controlReg_30_B_ETC___d878, - dataCount_37_ULT_1024___d1205, - metaCount_34_ULT_1024___d1204, - splaF_i_notEmpty__96_AND_IF_splaF_first__97_BI_ETC___d929; + reg [63 : 0] v__h25329, + v__h26261, + v__h26550, + v__h26755, + v__h3586, + v__h3761, + v__h3905; + reg [31 : 0] SEL_ARR_metaBram_0_serverAdapterB_outData_outD_ETC___d940, + v__h26736; + reg CASE_splaF_first__95_BITS_1_TO_0_97_0_metaBram_ETC___d909, + CASE_splaF_first__95_BITS_1_TO_0_97_0_metaBram_ETC___d914, + CASE_wci_wslv_reqF_first__3_BITS_35_TO_34_70_0_ETC___d975, + IF_wci_wslv_reqF_first__3_BITS_63_TO_52_54_EQ__ETC___d979; + wire [31 : 0] g_data__h27820, + rdat___1__h26833, + rdat___1__h26917, + rdat___1__h26972, + rdat___1__h26986, + rdat___1__h26994, + v__h25458, + y_avValue__h25982, + y_avValue__h26025, + y_avValue__h26065, + y_avValue__h26105, + y_avValue__h26145; + wire [13 : 0] mlB__h23202, mlInc__h23201; + wire [2 : 0] dataBram_0_serverAdapterB_cnt_19_PLUS_IF_dataB_ETC___d325, + metaBram_0_serverAdapterB_cnt_37_PLUS_IF_metaB_ETC___d443, + metaBram_1_serverAdapterB_cnt_55_PLUS_IF_metaB_ETC___d561, + metaBram_2_serverAdapterB_cnt_73_PLUS_IF_metaB_ETC___d679, + metaBram_3_serverAdapterB_cnt_91_PLUS_IF_metaB_ETC___d797, + x__h23250, + x__h23262, + x__h23274, + y__h23251, + y__h23263, + y__h23275; + wire [1 : 0] wci_wslv_respF_cntr_r_8_MINUS_1___d27; + wire IF_splaF_first__95_BIT_2_96_THEN_NOT_splaF_fir_ETC___d916, + NOT_controlReg_28_BIT_0_29_30_OR_controlReg_28_ETC___d854, + _dfoo1, + _dfoo3, + controlReg_28_BIT_0_29_AND_NOT_controlReg_28_B_ETC___d876, + dataCount_35_ULT_1024___d836, + metaCount_32_ULT_1024___d833; // value method wciS0_sResp assign wciS0_SResp = wci_wslv_respF_q_0[33:32] ; @@ -954,230 +958,230 @@ module mkWSICaptureWorker4B(wciS0_Clk, // value method wtiS0_sReset_n assign wtiS0_SReset_n = !wtiS_isReset_isInReset && wtiS_operateD ; - // submodule dataBram_memory + // submodule dataBram_0_memory BRAM2 #(.PIPELINED(1'd0), .ADDR_WIDTH(32'd10), .DATA_WIDTH(32'd32), - .MEMSIZE(11'd1024)) dataBram_memory(.CLKA(wciS0_Clk), - .CLKB(wciS0_Clk), - .ADDRA(dataBram_memory$ADDRA), - .ADDRB(dataBram_memory$ADDRB), - .DIA(dataBram_memory$DIA), - .DIB(dataBram_memory$DIB), - .WEA(dataBram_memory$WEA), - .WEB(dataBram_memory$WEB), - .ENA(dataBram_memory$ENA), - .ENB(dataBram_memory$ENB), - .DOA(dataBram_memory$DOA), - .DOB(dataBram_memory$DOB)); - - // submodule dataBram_serverAdapterA_outDataCore + .MEMSIZE(11'd1024)) dataBram_0_memory(.CLKA(wciS0_Clk), + .CLKB(wciS0_Clk), + .ADDRA(dataBram_0_memory$ADDRA), + .ADDRB(dataBram_0_memory$ADDRB), + .DIA(dataBram_0_memory$DIA), + .DIB(dataBram_0_memory$DIB), + .WEA(dataBram_0_memory$WEA), + .WEB(dataBram_0_memory$WEB), + .ENA(dataBram_0_memory$ENA), + .ENB(dataBram_0_memory$ENB), + .DOA(dataBram_0_memory$DOA), + .DOB(dataBram_0_memory$DOB)); + + // submodule dataBram_0_serverAdapterA_outDataCore SizedFIFO #(.p1width(32'd32), .p2depth(32'd3), .p3cntr_width(32'd1), - .guarded(32'd1)) dataBram_serverAdapterA_outDataCore(.RST(wciS0_MReset_n), - .CLK(wciS0_Clk), - .D_IN(dataBram_serverAdapterA_outDataCore$D_IN), - .ENQ(dataBram_serverAdapterA_outDataCore$ENQ), - .DEQ(dataBram_serverAdapterA_outDataCore$DEQ), - .CLR(dataBram_serverAdapterA_outDataCore$CLR), - .D_OUT(dataBram_serverAdapterA_outDataCore$D_OUT), - .FULL_N(dataBram_serverAdapterA_outDataCore$FULL_N), - .EMPTY_N(dataBram_serverAdapterA_outDataCore$EMPTY_N)); - - // submodule dataBram_serverAdapterB_outDataCore + .guarded(32'd1)) dataBram_0_serverAdapterA_outDataCore(.RST(wciS0_MReset_n), + .CLK(wciS0_Clk), + .D_IN(dataBram_0_serverAdapterA_outDataCore$D_IN), + .ENQ(dataBram_0_serverAdapterA_outDataCore$ENQ), + .DEQ(dataBram_0_serverAdapterA_outDataCore$DEQ), + .CLR(dataBram_0_serverAdapterA_outDataCore$CLR), + .D_OUT(dataBram_0_serverAdapterA_outDataCore$D_OUT), + .FULL_N(dataBram_0_serverAdapterA_outDataCore$FULL_N), + .EMPTY_N(dataBram_0_serverAdapterA_outDataCore$EMPTY_N)); + + // submodule dataBram_0_serverAdapterB_outDataCore SizedFIFO #(.p1width(32'd32), .p2depth(32'd3), .p3cntr_width(32'd1), - .guarded(32'd1)) dataBram_serverAdapterB_outDataCore(.RST(wciS0_MReset_n), - .CLK(wciS0_Clk), - .D_IN(dataBram_serverAdapterB_outDataCore$D_IN), - .ENQ(dataBram_serverAdapterB_outDataCore$ENQ), - .DEQ(dataBram_serverAdapterB_outDataCore$DEQ), - .CLR(dataBram_serverAdapterB_outDataCore$CLR), - .D_OUT(dataBram_serverAdapterB_outDataCore$D_OUT), - .FULL_N(dataBram_serverAdapterB_outDataCore$FULL_N), - .EMPTY_N(dataBram_serverAdapterB_outDataCore$EMPTY_N)); - - // submodule metaBram_memory - BRAM2 #(.PIPELINED(1'd0), - .ADDR_WIDTH(32'd10), - .DATA_WIDTH(32'd32), - .MEMSIZE(11'd1024)) metaBram_memory(.CLKA(wciS0_Clk), - .CLKB(wciS0_Clk), - .ADDRA(metaBram_memory$ADDRA), - .ADDRB(metaBram_memory$ADDRB), - .DIA(metaBram_memory$DIA), - .DIB(metaBram_memory$DIB), - .WEA(metaBram_memory$WEA), - .WEB(metaBram_memory$WEB), - .ENA(metaBram_memory$ENA), - .ENB(metaBram_memory$ENB), - .DOA(metaBram_memory$DOA), - .DOB(metaBram_memory$DOB)); - - // submodule metaBram_memory_1 - BRAM2 #(.PIPELINED(1'd0), - .ADDR_WIDTH(32'd10), - .DATA_WIDTH(32'd32), - .MEMSIZE(11'd1024)) metaBram_memory_1(.CLKA(wciS0_Clk), - .CLKB(wciS0_Clk), - .ADDRA(metaBram_memory_1$ADDRA), - .ADDRB(metaBram_memory_1$ADDRB), - .DIA(metaBram_memory_1$DIA), - .DIB(metaBram_memory_1$DIB), - .WEA(metaBram_memory_1$WEA), - .WEB(metaBram_memory_1$WEB), - .ENA(metaBram_memory_1$ENA), - .ENB(metaBram_memory_1$ENB), - .DOA(metaBram_memory_1$DOA), - .DOB(metaBram_memory_1$DOB)); - - // submodule metaBram_memory_2 - BRAM2 #(.PIPELINED(1'd0), - .ADDR_WIDTH(32'd10), - .DATA_WIDTH(32'd32), - .MEMSIZE(11'd1024)) metaBram_memory_2(.CLKA(wciS0_Clk), - .CLKB(wciS0_Clk), - .ADDRA(metaBram_memory_2$ADDRA), - .ADDRB(metaBram_memory_2$ADDRB), - .DIA(metaBram_memory_2$DIA), - .DIB(metaBram_memory_2$DIB), - .WEA(metaBram_memory_2$WEA), - .WEB(metaBram_memory_2$WEB), - .ENA(metaBram_memory_2$ENA), - .ENB(metaBram_memory_2$ENB), - .DOA(metaBram_memory_2$DOA), - .DOB(metaBram_memory_2$DOB)); - - // submodule metaBram_memory_3 + .guarded(32'd1)) dataBram_0_serverAdapterB_outDataCore(.RST(wciS0_MReset_n), + .CLK(wciS0_Clk), + .D_IN(dataBram_0_serverAdapterB_outDataCore$D_IN), + .ENQ(dataBram_0_serverAdapterB_outDataCore$ENQ), + .DEQ(dataBram_0_serverAdapterB_outDataCore$DEQ), + .CLR(dataBram_0_serverAdapterB_outDataCore$CLR), + .D_OUT(dataBram_0_serverAdapterB_outDataCore$D_OUT), + .FULL_N(dataBram_0_serverAdapterB_outDataCore$FULL_N), + .EMPTY_N(dataBram_0_serverAdapterB_outDataCore$EMPTY_N)); + + // submodule metaBram_0_memory BRAM2 #(.PIPELINED(1'd0), .ADDR_WIDTH(32'd10), .DATA_WIDTH(32'd32), - .MEMSIZE(11'd1024)) metaBram_memory_3(.CLKA(wciS0_Clk), + .MEMSIZE(11'd1024)) metaBram_0_memory(.CLKA(wciS0_Clk), .CLKB(wciS0_Clk), - .ADDRA(metaBram_memory_3$ADDRA), - .ADDRB(metaBram_memory_3$ADDRB), - .DIA(metaBram_memory_3$DIA), - .DIB(metaBram_memory_3$DIB), - .WEA(metaBram_memory_3$WEA), - .WEB(metaBram_memory_3$WEB), - .ENA(metaBram_memory_3$ENA), - .ENB(metaBram_memory_3$ENB), - .DOA(metaBram_memory_3$DOA), - .DOB(metaBram_memory_3$DOB)); - - // submodule metaBram_serverAdapterA_1_outDataCore + .ADDRA(metaBram_0_memory$ADDRA), + .ADDRB(metaBram_0_memory$ADDRB), + .DIA(metaBram_0_memory$DIA), + .DIB(metaBram_0_memory$DIB), + .WEA(metaBram_0_memory$WEA), + .WEB(metaBram_0_memory$WEB), + .ENA(metaBram_0_memory$ENA), + .ENB(metaBram_0_memory$ENB), + .DOA(metaBram_0_memory$DOA), + .DOB(metaBram_0_memory$DOB)); + + // submodule metaBram_0_serverAdapterA_outDataCore SizedFIFO #(.p1width(32'd32), .p2depth(32'd3), .p3cntr_width(32'd1), - .guarded(32'd1)) metaBram_serverAdapterA_1_outDataCore(.RST(wciS0_MReset_n), + .guarded(32'd1)) metaBram_0_serverAdapterA_outDataCore(.RST(wciS0_MReset_n), .CLK(wciS0_Clk), - .D_IN(metaBram_serverAdapterA_1_outDataCore$D_IN), - .ENQ(metaBram_serverAdapterA_1_outDataCore$ENQ), - .DEQ(metaBram_serverAdapterA_1_outDataCore$DEQ), - .CLR(metaBram_serverAdapterA_1_outDataCore$CLR), - .D_OUT(metaBram_serverAdapterA_1_outDataCore$D_OUT), - .FULL_N(metaBram_serverAdapterA_1_outDataCore$FULL_N), - .EMPTY_N(metaBram_serverAdapterA_1_outDataCore$EMPTY_N)); - - // submodule metaBram_serverAdapterA_2_outDataCore + .D_IN(metaBram_0_serverAdapterA_outDataCore$D_IN), + .ENQ(metaBram_0_serverAdapterA_outDataCore$ENQ), + .DEQ(metaBram_0_serverAdapterA_outDataCore$DEQ), + .CLR(metaBram_0_serverAdapterA_outDataCore$CLR), + .D_OUT(metaBram_0_serverAdapterA_outDataCore$D_OUT), + .FULL_N(metaBram_0_serverAdapterA_outDataCore$FULL_N), + .EMPTY_N(metaBram_0_serverAdapterA_outDataCore$EMPTY_N)); + + // submodule metaBram_0_serverAdapterB_outDataCore SizedFIFO #(.p1width(32'd32), .p2depth(32'd3), .p3cntr_width(32'd1), - .guarded(32'd1)) metaBram_serverAdapterA_2_outDataCore(.RST(wciS0_MReset_n), + .guarded(32'd1)) metaBram_0_serverAdapterB_outDataCore(.RST(wciS0_MReset_n), .CLK(wciS0_Clk), - .D_IN(metaBram_serverAdapterA_2_outDataCore$D_IN), - .ENQ(metaBram_serverAdapterA_2_outDataCore$ENQ), - .DEQ(metaBram_serverAdapterA_2_outDataCore$DEQ), - .CLR(metaBram_serverAdapterA_2_outDataCore$CLR), - .D_OUT(metaBram_serverAdapterA_2_outDataCore$D_OUT), - .FULL_N(metaBram_serverAdapterA_2_outDataCore$FULL_N), - .EMPTY_N(metaBram_serverAdapterA_2_outDataCore$EMPTY_N)); - - // submodule metaBram_serverAdapterA_3_outDataCore + .D_IN(metaBram_0_serverAdapterB_outDataCore$D_IN), + .ENQ(metaBram_0_serverAdapterB_outDataCore$ENQ), + .DEQ(metaBram_0_serverAdapterB_outDataCore$DEQ), + .CLR(metaBram_0_serverAdapterB_outDataCore$CLR), + .D_OUT(metaBram_0_serverAdapterB_outDataCore$D_OUT), + .FULL_N(metaBram_0_serverAdapterB_outDataCore$FULL_N), + .EMPTY_N(metaBram_0_serverAdapterB_outDataCore$EMPTY_N)); + + // submodule metaBram_1_memory + BRAM2 #(.PIPELINED(1'd0), + .ADDR_WIDTH(32'd10), + .DATA_WIDTH(32'd32), + .MEMSIZE(11'd1024)) metaBram_1_memory(.CLKA(wciS0_Clk), + .CLKB(wciS0_Clk), + .ADDRA(metaBram_1_memory$ADDRA), + .ADDRB(metaBram_1_memory$ADDRB), + .DIA(metaBram_1_memory$DIA), + .DIB(metaBram_1_memory$DIB), + .WEA(metaBram_1_memory$WEA), + .WEB(metaBram_1_memory$WEB), + .ENA(metaBram_1_memory$ENA), + .ENB(metaBram_1_memory$ENB), + .DOA(metaBram_1_memory$DOA), + .DOB(metaBram_1_memory$DOB)); + + // submodule metaBram_1_serverAdapterA_outDataCore SizedFIFO #(.p1width(32'd32), .p2depth(32'd3), .p3cntr_width(32'd1), - .guarded(32'd1)) metaBram_serverAdapterA_3_outDataCore(.RST(wciS0_MReset_n), + .guarded(32'd1)) metaBram_1_serverAdapterA_outDataCore(.RST(wciS0_MReset_n), .CLK(wciS0_Clk), - .D_IN(metaBram_serverAdapterA_3_outDataCore$D_IN), - .ENQ(metaBram_serverAdapterA_3_outDataCore$ENQ), - .DEQ(metaBram_serverAdapterA_3_outDataCore$DEQ), - .CLR(metaBram_serverAdapterA_3_outDataCore$CLR), - .D_OUT(metaBram_serverAdapterA_3_outDataCore$D_OUT), - .FULL_N(metaBram_serverAdapterA_3_outDataCore$FULL_N), - .EMPTY_N(metaBram_serverAdapterA_3_outDataCore$EMPTY_N)); - - // submodule metaBram_serverAdapterA_outDataCore + .D_IN(metaBram_1_serverAdapterA_outDataCore$D_IN), + .ENQ(metaBram_1_serverAdapterA_outDataCore$ENQ), + .DEQ(metaBram_1_serverAdapterA_outDataCore$DEQ), + .CLR(metaBram_1_serverAdapterA_outDataCore$CLR), + .D_OUT(metaBram_1_serverAdapterA_outDataCore$D_OUT), + .FULL_N(metaBram_1_serverAdapterA_outDataCore$FULL_N), + .EMPTY_N(metaBram_1_serverAdapterA_outDataCore$EMPTY_N)); + + // submodule metaBram_1_serverAdapterB_outDataCore SizedFIFO #(.p1width(32'd32), .p2depth(32'd3), .p3cntr_width(32'd1), - .guarded(32'd1)) metaBram_serverAdapterA_outDataCore(.RST(wciS0_MReset_n), - .CLK(wciS0_Clk), - .D_IN(metaBram_serverAdapterA_outDataCore$D_IN), - .ENQ(metaBram_serverAdapterA_outDataCore$ENQ), - .DEQ(metaBram_serverAdapterA_outDataCore$DEQ), - .CLR(metaBram_serverAdapterA_outDataCore$CLR), - .D_OUT(metaBram_serverAdapterA_outDataCore$D_OUT), - .FULL_N(metaBram_serverAdapterA_outDataCore$FULL_N), - .EMPTY_N(metaBram_serverAdapterA_outDataCore$EMPTY_N)); - - // submodule metaBram_serverAdapterB_1_outDataCore + .guarded(32'd1)) metaBram_1_serverAdapterB_outDataCore(.RST(wciS0_MReset_n), + .CLK(wciS0_Clk), + .D_IN(metaBram_1_serverAdapterB_outDataCore$D_IN), + .ENQ(metaBram_1_serverAdapterB_outDataCore$ENQ), + .DEQ(metaBram_1_serverAdapterB_outDataCore$DEQ), + .CLR(metaBram_1_serverAdapterB_outDataCore$CLR), + .D_OUT(metaBram_1_serverAdapterB_outDataCore$D_OUT), + .FULL_N(metaBram_1_serverAdapterB_outDataCore$FULL_N), + .EMPTY_N(metaBram_1_serverAdapterB_outDataCore$EMPTY_N)); + + // submodule metaBram_2_memory + BRAM2 #(.PIPELINED(1'd0), + .ADDR_WIDTH(32'd10), + .DATA_WIDTH(32'd32), + .MEMSIZE(11'd1024)) metaBram_2_memory(.CLKA(wciS0_Clk), + .CLKB(wciS0_Clk), + .ADDRA(metaBram_2_memory$ADDRA), + .ADDRB(metaBram_2_memory$ADDRB), + .DIA(metaBram_2_memory$DIA), + .DIB(metaBram_2_memory$DIB), + .WEA(metaBram_2_memory$WEA), + .WEB(metaBram_2_memory$WEB), + .ENA(metaBram_2_memory$ENA), + .ENB(metaBram_2_memory$ENB), + .DOA(metaBram_2_memory$DOA), + .DOB(metaBram_2_memory$DOB)); + + // submodule metaBram_2_serverAdapterA_outDataCore SizedFIFO #(.p1width(32'd32), .p2depth(32'd3), .p3cntr_width(32'd1), - .guarded(32'd1)) metaBram_serverAdapterB_1_outDataCore(.RST(wciS0_MReset_n), + .guarded(32'd1)) metaBram_2_serverAdapterA_outDataCore(.RST(wciS0_MReset_n), .CLK(wciS0_Clk), - .D_IN(metaBram_serverAdapterB_1_outDataCore$D_IN), - .ENQ(metaBram_serverAdapterB_1_outDataCore$ENQ), - .DEQ(metaBram_serverAdapterB_1_outDataCore$DEQ), - .CLR(metaBram_serverAdapterB_1_outDataCore$CLR), - .D_OUT(metaBram_serverAdapterB_1_outDataCore$D_OUT), - .FULL_N(metaBram_serverAdapterB_1_outDataCore$FULL_N), - .EMPTY_N(metaBram_serverAdapterB_1_outDataCore$EMPTY_N)); - - // submodule metaBram_serverAdapterB_2_outDataCore + .D_IN(metaBram_2_serverAdapterA_outDataCore$D_IN), + .ENQ(metaBram_2_serverAdapterA_outDataCore$ENQ), + .DEQ(metaBram_2_serverAdapterA_outDataCore$DEQ), + .CLR(metaBram_2_serverAdapterA_outDataCore$CLR), + .D_OUT(metaBram_2_serverAdapterA_outDataCore$D_OUT), + .FULL_N(metaBram_2_serverAdapterA_outDataCore$FULL_N), + .EMPTY_N(metaBram_2_serverAdapterA_outDataCore$EMPTY_N)); + + // submodule metaBram_2_serverAdapterB_outDataCore SizedFIFO #(.p1width(32'd32), .p2depth(32'd3), .p3cntr_width(32'd1), - .guarded(32'd1)) metaBram_serverAdapterB_2_outDataCore(.RST(wciS0_MReset_n), + .guarded(32'd1)) metaBram_2_serverAdapterB_outDataCore(.RST(wciS0_MReset_n), .CLK(wciS0_Clk), - .D_IN(metaBram_serverAdapterB_2_outDataCore$D_IN), - .ENQ(metaBram_serverAdapterB_2_outDataCore$ENQ), - .DEQ(metaBram_serverAdapterB_2_outDataCore$DEQ), - .CLR(metaBram_serverAdapterB_2_outDataCore$CLR), - .D_OUT(metaBram_serverAdapterB_2_outDataCore$D_OUT), - .FULL_N(metaBram_serverAdapterB_2_outDataCore$FULL_N), - .EMPTY_N(metaBram_serverAdapterB_2_outDataCore$EMPTY_N)); - - // submodule metaBram_serverAdapterB_3_outDataCore + .D_IN(metaBram_2_serverAdapterB_outDataCore$D_IN), + .ENQ(metaBram_2_serverAdapterB_outDataCore$ENQ), + .DEQ(metaBram_2_serverAdapterB_outDataCore$DEQ), + .CLR(metaBram_2_serverAdapterB_outDataCore$CLR), + .D_OUT(metaBram_2_serverAdapterB_outDataCore$D_OUT), + .FULL_N(metaBram_2_serverAdapterB_outDataCore$FULL_N), + .EMPTY_N(metaBram_2_serverAdapterB_outDataCore$EMPTY_N)); + + // submodule metaBram_3_memory + BRAM2 #(.PIPELINED(1'd0), + .ADDR_WIDTH(32'd10), + .DATA_WIDTH(32'd32), + .MEMSIZE(11'd1024)) metaBram_3_memory(.CLKA(wciS0_Clk), + .CLKB(wciS0_Clk), + .ADDRA(metaBram_3_memory$ADDRA), + .ADDRB(metaBram_3_memory$ADDRB), + .DIA(metaBram_3_memory$DIA), + .DIB(metaBram_3_memory$DIB), + .WEA(metaBram_3_memory$WEA), + .WEB(metaBram_3_memory$WEB), + .ENA(metaBram_3_memory$ENA), + .ENB(metaBram_3_memory$ENB), + .DOA(metaBram_3_memory$DOA), + .DOB(metaBram_3_memory$DOB)); + + // submodule metaBram_3_serverAdapterA_outDataCore SizedFIFO #(.p1width(32'd32), .p2depth(32'd3), .p3cntr_width(32'd1), - .guarded(32'd1)) metaBram_serverAdapterB_3_outDataCore(.RST(wciS0_MReset_n), + .guarded(32'd1)) metaBram_3_serverAdapterA_outDataCore(.RST(wciS0_MReset_n), .CLK(wciS0_Clk), - .D_IN(metaBram_serverAdapterB_3_outDataCore$D_IN), - .ENQ(metaBram_serverAdapterB_3_outDataCore$ENQ), - .DEQ(metaBram_serverAdapterB_3_outDataCore$DEQ), - .CLR(metaBram_serverAdapterB_3_outDataCore$CLR), - .D_OUT(metaBram_serverAdapterB_3_outDataCore$D_OUT), - .FULL_N(metaBram_serverAdapterB_3_outDataCore$FULL_N), - .EMPTY_N(metaBram_serverAdapterB_3_outDataCore$EMPTY_N)); - - // submodule metaBram_serverAdapterB_outDataCore + .D_IN(metaBram_3_serverAdapterA_outDataCore$D_IN), + .ENQ(metaBram_3_serverAdapterA_outDataCore$ENQ), + .DEQ(metaBram_3_serverAdapterA_outDataCore$DEQ), + .CLR(metaBram_3_serverAdapterA_outDataCore$CLR), + .D_OUT(metaBram_3_serverAdapterA_outDataCore$D_OUT), + .FULL_N(metaBram_3_serverAdapterA_outDataCore$FULL_N), + .EMPTY_N(metaBram_3_serverAdapterA_outDataCore$EMPTY_N)); + + // submodule metaBram_3_serverAdapterB_outDataCore SizedFIFO #(.p1width(32'd32), .p2depth(32'd3), .p3cntr_width(32'd1), - .guarded(32'd1)) metaBram_serverAdapterB_outDataCore(.RST(wciS0_MReset_n), - .CLK(wciS0_Clk), - .D_IN(metaBram_serverAdapterB_outDataCore$D_IN), - .ENQ(metaBram_serverAdapterB_outDataCore$ENQ), - .DEQ(metaBram_serverAdapterB_outDataCore$DEQ), - .CLR(metaBram_serverAdapterB_outDataCore$CLR), - .D_OUT(metaBram_serverAdapterB_outDataCore$D_OUT), - .FULL_N(metaBram_serverAdapterB_outDataCore$FULL_N), - .EMPTY_N(metaBram_serverAdapterB_outDataCore$EMPTY_N)); + .guarded(32'd1)) metaBram_3_serverAdapterB_outDataCore(.RST(wciS0_MReset_n), + .CLK(wciS0_Clk), + .D_IN(metaBram_3_serverAdapterB_outDataCore$D_IN), + .ENQ(metaBram_3_serverAdapterB_outDataCore$ENQ), + .DEQ(metaBram_3_serverAdapterB_outDataCore$DEQ), + .CLR(metaBram_3_serverAdapterB_outDataCore$CLR), + .D_OUT(metaBram_3_serverAdapterB_outDataCore$D_OUT), + .FULL_N(metaBram_3_serverAdapterB_outDataCore$FULL_N), + .EMPTY_N(metaBram_3_serverAdapterB_outDataCore$EMPTY_N)); // submodule splaF FIFO2 #(.width(32'd3), .guarded(32'd1)) splaF(.RST(wciS0_MReset_n), @@ -1240,10 +1244,10 @@ module mkWSICaptureWorker4B(wciS0_Clk, // rule RL_wci_cfrd assign CAN_FIRE_RL_wci_cfrd = wci_wslv_reqF$EMPTY_N && - IF_wci_wslv_reqF_first__5_BITS_63_TO_52_65_EQ__ETC___d998 && + IF_wci_wslv_reqF_first__3_BITS_63_TO_52_54_EQ__ETC___d979 && (wci_wslv_reqF$D_OUT[63:52] == 12'h800 || wci_wslv_reqF$D_OUT[63:52] == 12'h400 || - wci_wslv_respF_c_r != 2'd2) && + wci_wslv_respF_cntr_r != 2'd2) && wci_wslv_wci_cfrd_pw$whas ; assign WILL_FIRE_RL_wci_cfrd = CAN_FIRE_RL_wci_cfrd && !WILL_FIRE_RL_wci_wslv_ctl_op_start && @@ -1251,94 +1255,96 @@ module mkWSICaptureWorker4B(wciS0_Clk, // rule RL_wci_cfwr assign WILL_FIRE_RL_wci_cfwr = - wci_wslv_respF_c_r != 2'd2 && wci_wslv_reqF$EMPTY_N && + wci_wslv_respF_cntr_r != 2'd2 && wci_wslv_reqF$EMPTY_N && wci_wslv_wci_cfwr_pw$whas && !WILL_FIRE_RL_wci_wslv_ctl_op_start && !WILL_FIRE_RL_wci_wslv_ctl_op_complete ; // rule RL_wci_wslv_ctl_op_complete assign WILL_FIRE_RL_wci_wslv_ctl_op_complete = - wci_wslv_respF_c_r != 2'd2 && wci_wslv_ctlOpActive && + wci_wslv_respF_cntr_r != 2'd2 && wci_wslv_ctlOpActive && wci_wslv_ctlAckReg ; - // rule RL_dataBram_serverAdapterB_stageReadResponseAlways - assign WILL_FIRE_RL_dataBram_serverAdapterB_stageReadResponseAlways = + // rule RL_dataBram_0_serverAdapterB_stageReadResponseAlways + assign WILL_FIRE_RL_dataBram_0_serverAdapterB_stageReadResponseAlways = WILL_FIRE_RL_wci_cfrd && wci_wslv_reqF$D_OUT[63:52] == 12'h800 ; - // rule RL_metaBram_serverAdapterB_stageReadResponseAlways - assign WILL_FIRE_RL_metaBram_serverAdapterB_stageReadResponseAlways = - WILL_FIRE_RL_wci_cfrd && wci_wslv_reqF$D_OUT[63:52] == 12'h400 && - wci_wslv_reqF$D_OUT[35:34] == 2'd0 ; - - // rule RL_metaBram_serverAdapterB_1_stageReadResponseAlways - assign WILL_FIRE_RL_metaBram_serverAdapterB_1_stageReadResponseAlways = - WILL_FIRE_RL_wci_cfrd && wci_wslv_reqF$D_OUT[63:52] == 12'h400 && - wci_wslv_reqF$D_OUT[35:34] == 2'd1 ; - - // rule RL_metaBram_serverAdapterB_2_stageReadResponseAlways - assign WILL_FIRE_RL_metaBram_serverAdapterB_2_stageReadResponseAlways = - WILL_FIRE_RL_wci_cfrd && wci_wslv_reqF$D_OUT[63:52] == 12'h400 && - wci_wslv_reqF$D_OUT[35:34] == 2'd2 ; - - // rule RL_metaBram_serverAdapterB_3_stageReadResponseAlways - assign WILL_FIRE_RL_metaBram_serverAdapterB_3_stageReadResponseAlways = - WILL_FIRE_RL_wci_cfrd && wci_wslv_reqF$D_OUT[63:52] == 12'h400 && - wci_wslv_reqF$D_OUT[35:34] == 2'd3 ; + // rule RL_metaBram_0_serverAdapterB_stageReadResponseAlways + assign WILL_FIRE_RL_metaBram_0_serverAdapterB_stageReadResponseAlways = + WILL_FIRE_RL_wci_cfrd && wci_wslv_reqF$D_OUT[35:34] == 2'd0 && + wci_wslv_reqF$D_OUT[63:52] == 12'h400 ; + + // rule RL_metaBram_1_serverAdapterB_stageReadResponseAlways + assign WILL_FIRE_RL_metaBram_1_serverAdapterB_stageReadResponseAlways = + WILL_FIRE_RL_wci_cfrd && wci_wslv_reqF$D_OUT[35:34] == 2'd1 && + wci_wslv_reqF$D_OUT[63:52] == 12'h400 ; + + // rule RL_metaBram_2_serverAdapterB_stageReadResponseAlways + assign WILL_FIRE_RL_metaBram_2_serverAdapterB_stageReadResponseAlways = + WILL_FIRE_RL_wci_cfrd && wci_wslv_reqF$D_OUT[35:34] == 2'd2 && + wci_wslv_reqF$D_OUT[63:52] == 12'h400 ; + + // rule RL_metaBram_3_serverAdapterB_stageReadResponseAlways + assign WILL_FIRE_RL_metaBram_3_serverAdapterB_stageReadResponseAlways = + WILL_FIRE_RL_wci_cfrd && wci_wslv_reqF$D_OUT[35:34] == 2'd3 && + wci_wslv_reqF$D_OUT[63:52] == 12'h400 ; + + // rule RL_advance_split_response + assign CAN_FIRE_RL_advance_split_response = + wci_wslv_respF_cntr_r != 2'd2 && splaF$EMPTY_N && + IF_splaF_first__95_BIT_2_96_THEN_NOT_splaF_fir_ETC___d916 && + !wci_wslv_wci_cfwr_pw$whas && + splitReadInFlight ; // rule RL_wci_wslv_respF_incCtr assign WILL_FIRE_RL_wci_wslv_respF_incCtr = - ((wci_wslv_respF_c_r == 2'd0) ? - wci_wslv_respF_x_wire$whas : - wci_wslv_respF_c_r != 2'd1 || wci_wslv_respF_x_wire$whas) && - wci_wslv_respF_enqueueing$whas && - !(wci_wslv_respF_c_r != 2'd0) ; + wci_wslv_respF_x_wire$whas && wci_wslv_respF_enqueueing$whas && + !(wci_wslv_respF_cntr_r != 2'd0) ; // rule RL_wci_wslv_respF_decCtr assign WILL_FIRE_RL_wci_wslv_respF_decCtr = - wci_wslv_respF_c_r != 2'd0 && !wci_wslv_respF_enqueueing$whas ; + wci_wslv_respF_cntr_r != 2'd0 && + !wci_wslv_respF_enqueueing$whas ; // rule RL_wci_wslv_respF_both assign WILL_FIRE_RL_wci_wslv_respF_both = - ((wci_wslv_respF_c_r == 2'd1) ? - wci_wslv_respF_x_wire$whas : - wci_wslv_respF_c_r != 2'd2 || wci_wslv_respF_x_wire$whas) && - wci_wslv_respF_c_r != 2'd0 && + wci_wslv_respF_x_wire$whas && wci_wslv_respF_cntr_r != 2'd0 && wci_wslv_respF_enqueueing$whas ; - // rule RL_dataBram_serverAdapterB_outData_enqAndDeq - assign WILL_FIRE_RL_dataBram_serverAdapterB_outData_enqAndDeq = - dataBram_serverAdapterB_outDataCore$EMPTY_N && - dataBram_serverAdapterB_outDataCore$FULL_N && - dataBram_serverAdapterB_outData_deqCalled$whas && - dataBram_serverAdapterB_outData_enqData$whas ; - - // rule RL_metaBram_serverAdapterB_outData_enqAndDeq - assign WILL_FIRE_RL_metaBram_serverAdapterB_outData_enqAndDeq = - metaBram_serverAdapterB_outDataCore$EMPTY_N && - metaBram_serverAdapterB_outDataCore$FULL_N && - metaBram_serverAdapterB_outData_deqCalled$whas && - metaBram_serverAdapterB_outData_enqData$whas ; - - // rule RL_metaBram_serverAdapterB_1_outData_enqAndDeq - assign WILL_FIRE_RL_metaBram_serverAdapterB_1_outData_enqAndDeq = - metaBram_serverAdapterB_1_outDataCore$EMPTY_N && - metaBram_serverAdapterB_1_outDataCore$FULL_N && - metaBram_serverAdapterB_1_outData_deqCalled$whas && - metaBram_serverAdapterB_1_outData_enqData$whas ; - - // rule RL_metaBram_serverAdapterB_2_outData_enqAndDeq - assign WILL_FIRE_RL_metaBram_serverAdapterB_2_outData_enqAndDeq = - metaBram_serverAdapterB_2_outDataCore$EMPTY_N && - metaBram_serverAdapterB_2_outDataCore$FULL_N && - metaBram_serverAdapterB_2_outData_deqCalled$whas && - metaBram_serverAdapterB_2_outData_enqData$whas ; - - // rule RL_metaBram_serverAdapterB_3_outData_enqAndDeq - assign WILL_FIRE_RL_metaBram_serverAdapterB_3_outData_enqAndDeq = - metaBram_serverAdapterB_3_outDataCore$EMPTY_N && - metaBram_serverAdapterB_3_outDataCore$FULL_N && - metaBram_serverAdapterB_3_outData_deqCalled$whas && - metaBram_serverAdapterB_3_outData_enqData$whas ; + // rule RL_dataBram_0_serverAdapterB_outData_enqAndDeq + assign WILL_FIRE_RL_dataBram_0_serverAdapterB_outData_enqAndDeq = + dataBram_0_serverAdapterB_outDataCore$EMPTY_N && + dataBram_0_serverAdapterB_outDataCore$FULL_N && + dataBram_0_serverAdapterB_outData_deqCalled$whas && + dataBram_0_serverAdapterB_outData_enqData$whas ; + + // rule RL_metaBram_0_serverAdapterB_outData_enqAndDeq + assign WILL_FIRE_RL_metaBram_0_serverAdapterB_outData_enqAndDeq = + metaBram_0_serverAdapterB_outDataCore$EMPTY_N && + metaBram_0_serverAdapterB_outDataCore$FULL_N && + metaBram_0_serverAdapterB_outData_deqCalled$whas && + metaBram_0_serverAdapterB_outData_enqData$whas ; + + // rule RL_metaBram_1_serverAdapterB_outData_enqAndDeq + assign WILL_FIRE_RL_metaBram_1_serverAdapterB_outData_enqAndDeq = + metaBram_1_serverAdapterB_outDataCore$EMPTY_N && + metaBram_1_serverAdapterB_outDataCore$FULL_N && + metaBram_1_serverAdapterB_cnt_2$whas && + metaBram_1_serverAdapterB_outData_enqData$whas ; + + // rule RL_metaBram_2_serverAdapterB_outData_enqAndDeq + assign WILL_FIRE_RL_metaBram_2_serverAdapterB_outData_enqAndDeq = + metaBram_2_serverAdapterB_outDataCore$EMPTY_N && + metaBram_2_serverAdapterB_outDataCore$FULL_N && + metaBram_2_serverAdapterB_outData_deqCalled$whas && + metaBram_2_serverAdapterB_outData_enqData$whas ; + + // rule RL_metaBram_3_serverAdapterB_outData_enqAndDeq + assign WILL_FIRE_RL_metaBram_3_serverAdapterB_outData_enqAndDeq = + metaBram_3_serverAdapterB_outDataCore$EMPTY_N && + metaBram_3_serverAdapterB_outDataCore$FULL_N && + metaBram_3_serverAdapterB_outData_deqCalled$whas && + metaBram_3_serverAdapterB_outData_enqData$whas ; // rule RL_wsiS_reqFifo_enq assign WILL_FIRE_RL_wsiS_reqFifo_enq = @@ -1362,12 +1368,12 @@ module mkWSICaptureWorker4B(wciS0_Clk, WILL_FIRE_RL_wci_cfwr && wci_wslv_reqF$D_OUT[39:32] == 8'h08 ; assign MUX_dataCount$write_1__SEL_2 = MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 && - controlReg_30_BIT_0_31_AND_NOT_controlReg_30_B_ETC___d878 ; + controlReg_28_BIT_0_29_AND_NOT_controlReg_28_B_ETC___d876 ; assign MUX_metaCount$write_1__SEL_1 = WILL_FIRE_RL_wci_cfwr && wci_wslv_reqF$D_OUT[39:32] == 8'h04 ; assign MUX_metaCount$write_1__SEL_2 = MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 && - controlReg_30_BIT_0_31_AND_NOT_controlReg_30_B_ETC___d878 && + controlReg_28_BIT_0_29_AND_NOT_controlReg_28_B_ETC___d876 && wsiS_reqFifo$D_OUT[57] ; assign MUX_splitReadInFlight$write_1__SEL_1 = WILL_FIRE_RL_wci_cfrd && @@ -1386,24 +1392,25 @@ module mkWSICaptureWorker4B(wciS0_Clk, wci_wslv_reqF$D_OUT[36:34] == 3'd5 || wci_wslv_reqF$D_OUT[36:34] == 3'd6 || wci_wslv_reqF$D_OUT[36:34] == 3'd7) ; + assign MUX_wci_wslv_respF_q_0$write_1__SEL_1 = + WILL_FIRE_RL_wci_wslv_respF_both && _dfoo3 ; assign MUX_wci_wslv_respF_q_0$write_1__SEL_2 = WILL_FIRE_RL_wci_wslv_respF_incCtr && - wci_wslv_respF_c_r == 2'd0 ; + wci_wslv_respF_cntr_r == 2'd0 ; + assign MUX_wci_wslv_respF_q_1$write_1__SEL_1 = + WILL_FIRE_RL_wci_wslv_respF_both && _dfoo1 ; assign MUX_wci_wslv_respF_q_1$write_1__SEL_2 = WILL_FIRE_RL_wci_wslv_respF_incCtr && - wci_wslv_respF_c_r == 2'd1 ; + wci_wslv_respF_cntr_r == 2'd1 ; assign MUX_wci_wslv_respF_x_wire$wset_1__SEL_1 = WILL_FIRE_RL_wci_cfrd && wci_wslv_reqF$D_OUT[63:52] != 12'h800 && wci_wslv_reqF$D_OUT[63:52] != 12'h400 ; assign MUX_wci_wslv_respF_x_wire$wset_1__SEL_3 = - wci_wslv_respF_c_r != 2'd2 && - splaF_i_notEmpty__96_AND_IF_splaF_first__97_BI_ETC___d929 && - !wci_wslv_wci_cfwr_pw$whas && - splitReadInFlight && + CAN_FIRE_RL_advance_split_response && !WILL_FIRE_RL_wci_wslv_ctl_op_complete ; assign MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 = wsiS_reqFifo$EMPTY_N && - NOT_controlReg_30_BIT_0_31_32_OR_controlReg_30_ETC___d856 && + NOT_controlReg_28_BIT_0_29_30_OR_controlReg_28_ETC___d854 && wci_wslv_cState == 3'd2 ; assign MUX_dataCount$write_1__VAL_2 = dataCount + 32'd1 ; assign MUX_metaCount$write_1__VAL_2 = metaCount + 32'd1 ; @@ -1411,10 +1418,10 @@ module mkWSICaptureWorker4B(wciS0_Clk, wci_wslv_reqF$D_OUT[36:34] != 3'd4 && wci_wslv_reqF$D_OUT[36:34] != 3'd5 && wci_wslv_reqF$D_OUT[36:34] != 3'd6 ; - assign MUX_wci_wslv_respF_c_r$write_1__VAL_1 = wci_wslv_respF_c_r + 2'd1 ; - assign MUX_wci_wslv_respF_c_r$write_1__VAL_2 = wci_wslv_respF_c_r - 2'd1 ; + assign MUX_wci_wslv_respF_cntr_r$write_1__VAL_2 = + wci_wslv_respF_cntr_r + 2'd1 ; assign MUX_wci_wslv_respF_q_0$write_1__VAL_1 = - (wci_wslv_respF_c_r == 2'd1) ? + (wci_wslv_respF_cntr_r == 2'd1) ? MUX_wci_wslv_respF_q_0$write_1__VAL_2 : wci_wslv_respF_q_1 ; always@(MUX_wci_wslv_respF_x_wire$wset_1__SEL_1 or @@ -1441,13 +1448,13 @@ module mkWSICaptureWorker4B(wciS0_Clk, endcase end assign MUX_wci_wslv_respF_q_1$write_1__VAL_1 = - (wci_wslv_respF_c_r == 2'd2) ? + (wci_wslv_respF_cntr_r == 2'd2) ? MUX_wci_wslv_respF_q_0$write_1__VAL_2 : 34'h0AAAAAAAA ; - assign MUX_wci_wslv_respF_x_wire$wset_1__VAL_1 = { 2'd1, g_data__h28071 } ; + assign MUX_wci_wslv_respF_x_wire$wset_1__VAL_1 = { 2'd1, g_data__h27820 } ; assign MUX_wci_wslv_respF_x_wire$wset_1__VAL_2 = wci_wslv_illegalEdge ? 34'h3C0DE4202 : 34'h1C0DE4201 ; - assign MUX_wci_wslv_respF_x_wire$wset_1__VAL_3 = { 2'd1, v__h25581 } ; + assign MUX_wci_wslv_respF_x_wire$wset_1__VAL_3 = { 2'd1, v__h25458 } ; // inlined wires assign wci_wslv_wciReq$wget = @@ -1504,264 +1511,270 @@ module mkWSICaptureWorker4B(wciS0_Clk, assign wtiS_operateD_1$whas = 1'b0 ; assign nowW$wget = wtiS_nowReq[63:0] ; assign nowW$whas = 1'd1 ; - assign statusReg_w$wget = rdat___1__h27078 ; + assign statusReg_w$wget = rdat___1__h26833 ; assign statusReg_w$whas = 1'd1 ; - assign dataBram_serverAdapterA_outData_enqData$wget = dataBram_memory$DOA ; - assign dataBram_serverAdapterA_outData_enqData$whas = - (!dataBram_serverAdapterA_s1[0] || - dataBram_serverAdapterA_outDataCore$FULL_N) && - dataBram_serverAdapterA_s1[1] && - dataBram_serverAdapterA_s1[0] ; - assign dataBram_serverAdapterA_outData_outData$wget = - dataBram_serverAdapterA_outDataCore$EMPTY_N ? - dataBram_serverAdapterA_outDataCore$D_OUT : - dataBram_memory$DOA ; - assign dataBram_serverAdapterA_outData_outData$whas = - dataBram_serverAdapterA_outDataCore$EMPTY_N || - !dataBram_serverAdapterA_outDataCore$EMPTY_N && - dataBram_serverAdapterA_outData_enqData$whas ; - assign dataBram_serverAdapterA_cnt_1$wget = 3'd1 ; - assign dataBram_serverAdapterA_cnt_1$whas = 1'b0 ; - assign dataBram_serverAdapterA_cnt_2$wget = 3'h0 ; - assign dataBram_serverAdapterA_cnt_2$whas = 1'b0 ; - assign dataBram_serverAdapterA_cnt_3$wget = 3'h0 ; - assign dataBram_serverAdapterA_cnt_3$whas = 1'b0 ; - assign dataBram_serverAdapterA_writeWithResp$wget = 2'd2 ; - assign dataBram_serverAdapterA_writeWithResp$whas = + assign dataBram_0_serverAdapterA_outData_enqData$wget = + dataBram_0_memory$DOA ; + assign dataBram_0_serverAdapterA_outData_enqData$whas = + (!dataBram_0_serverAdapterA_s1[0] || + dataBram_0_serverAdapterA_outDataCore$FULL_N) && + dataBram_0_serverAdapterA_s1[1] && + dataBram_0_serverAdapterA_s1[0] ; + assign dataBram_0_serverAdapterA_outData_outData$wget = + dataBram_0_serverAdapterA_outDataCore$EMPTY_N ? + dataBram_0_serverAdapterA_outDataCore$D_OUT : + dataBram_0_memory$DOA ; + assign dataBram_0_serverAdapterA_outData_outData$whas = + dataBram_0_serverAdapterA_outDataCore$EMPTY_N || + !dataBram_0_serverAdapterA_outDataCore$EMPTY_N && + dataBram_0_serverAdapterA_outData_enqData$whas ; + assign dataBram_0_serverAdapterA_cnt_1$wget = 3'd1 ; + assign dataBram_0_serverAdapterA_cnt_1$whas = 1'b0 ; + assign dataBram_0_serverAdapterA_cnt_2$wget = 3'h0 ; + assign dataBram_0_serverAdapterA_cnt_2$whas = 1'b0 ; + assign dataBram_0_serverAdapterA_cnt_3$wget = 3'h0 ; + assign dataBram_0_serverAdapterA_cnt_3$whas = 1'b0 ; + assign dataBram_0_serverAdapterA_writeWithResp$wget = 2'd2 ; + assign dataBram_0_serverAdapterA_writeWithResp$whas = MUX_dataCount$write_1__SEL_2 ; - assign dataBram_serverAdapterA_s1_1$wget = 2'd2 ; - assign dataBram_serverAdapterA_s1_1$whas = MUX_dataCount$write_1__SEL_2 ; - assign dataBram_serverAdapterB_outData_enqData$wget = dataBram_memory$DOB ; - assign dataBram_serverAdapterB_outData_enqData$whas = - (!dataBram_serverAdapterB_s1[0] || - dataBram_serverAdapterB_outDataCore$FULL_N) && - dataBram_serverAdapterB_s1[1] && - dataBram_serverAdapterB_s1[0] ; - assign dataBram_serverAdapterB_outData_outData$wget = y_avValue__h26208 ; - assign dataBram_serverAdapterB_outData_outData$whas = - dataBram_serverAdapterB_outDataCore$EMPTY_N || - !dataBram_serverAdapterB_outDataCore$EMPTY_N && - dataBram_serverAdapterB_outData_enqData$whas ; - assign dataBram_serverAdapterB_cnt_1$wget = 3'd1 ; - assign dataBram_serverAdapterB_cnt_1$whas = - WILL_FIRE_RL_dataBram_serverAdapterB_stageReadResponseAlways ; - assign dataBram_serverAdapterB_cnt_2$wget = 3'd7 ; - assign dataBram_serverAdapterB_cnt_2$whas = - dataBram_serverAdapterB_outData_deqCalled$whas ; - assign dataBram_serverAdapterB_cnt_3$wget = 3'h0 ; - assign dataBram_serverAdapterB_cnt_3$whas = 1'b0 ; - assign dataBram_serverAdapterB_writeWithResp$wget = 2'd0 ; - assign dataBram_serverAdapterB_writeWithResp$whas = - WILL_FIRE_RL_dataBram_serverAdapterB_stageReadResponseAlways ; - assign dataBram_serverAdapterB_s1_1$wget = 2'd3 ; - assign dataBram_serverAdapterB_s1_1$whas = - WILL_FIRE_RL_dataBram_serverAdapterB_stageReadResponseAlways ; - assign metaBram_serverAdapterA_outData_enqData$wget = metaBram_memory$DOA ; - assign metaBram_serverAdapterA_outData_enqData$whas = - (!metaBram_serverAdapterA_s1[0] || - metaBram_serverAdapterA_outDataCore$FULL_N) && - metaBram_serverAdapterA_s1[1] && - metaBram_serverAdapterA_s1[0] ; - assign metaBram_serverAdapterA_outData_outData$wget = - metaBram_serverAdapterA_outDataCore$EMPTY_N ? - metaBram_serverAdapterA_outDataCore$D_OUT : - metaBram_memory$DOA ; - assign metaBram_serverAdapterA_outData_outData$whas = - metaBram_serverAdapterA_outDataCore$EMPTY_N || - !metaBram_serverAdapterA_outDataCore$EMPTY_N && - metaBram_serverAdapterA_outData_enqData$whas ; - assign metaBram_serverAdapterA_cnt_1$wget = 3'd1 ; - assign metaBram_serverAdapterA_cnt_1$whas = 1'b0 ; - assign metaBram_serverAdapterA_cnt_2$wget = 3'h0 ; - assign metaBram_serverAdapterA_cnt_2$whas = 1'b0 ; - assign metaBram_serverAdapterA_cnt_3$wget = 3'h0 ; - assign metaBram_serverAdapterA_cnt_3$whas = 1'b0 ; - assign metaBram_serverAdapterA_writeWithResp$wget = 2'd2 ; - assign metaBram_serverAdapterA_writeWithResp$whas = + assign dataBram_0_serverAdapterA_s1_1$wget = 2'd2 ; + assign dataBram_0_serverAdapterA_s1_1$whas = MUX_dataCount$write_1__SEL_2 ; + assign dataBram_0_serverAdapterB_outData_enqData$wget = + dataBram_0_memory$DOB ; + assign dataBram_0_serverAdapterB_outData_enqData$whas = + (!dataBram_0_serverAdapterB_s1[0] || + dataBram_0_serverAdapterB_outDataCore$FULL_N) && + dataBram_0_serverAdapterB_s1[1] && + dataBram_0_serverAdapterB_s1[0] ; + assign dataBram_0_serverAdapterB_outData_outData$wget = y_avValue__h25982 ; + assign dataBram_0_serverAdapterB_outData_outData$whas = + dataBram_0_serverAdapterB_outDataCore$EMPTY_N || + !dataBram_0_serverAdapterB_outDataCore$EMPTY_N && + dataBram_0_serverAdapterB_outData_enqData$whas ; + assign dataBram_0_serverAdapterB_cnt_1$wget = 3'd1 ; + assign dataBram_0_serverAdapterB_cnt_1$whas = + WILL_FIRE_RL_dataBram_0_serverAdapterB_stageReadResponseAlways ; + assign dataBram_0_serverAdapterB_cnt_2$wget = 3'd7 ; + assign dataBram_0_serverAdapterB_cnt_2$whas = + dataBram_0_serverAdapterB_outData_deqCalled$whas ; + assign dataBram_0_serverAdapterB_cnt_3$wget = 3'h0 ; + assign dataBram_0_serverAdapterB_cnt_3$whas = 1'b0 ; + assign dataBram_0_serverAdapterB_writeWithResp$wget = 2'd0 ; + assign dataBram_0_serverAdapterB_writeWithResp$whas = + WILL_FIRE_RL_dataBram_0_serverAdapterB_stageReadResponseAlways ; + assign dataBram_0_serverAdapterB_s1_1$wget = 2'd3 ; + assign dataBram_0_serverAdapterB_s1_1$whas = + WILL_FIRE_RL_dataBram_0_serverAdapterB_stageReadResponseAlways ; + assign metaBram_0_serverAdapterA_outData_enqData$wget = + metaBram_0_memory$DOA ; + assign metaBram_0_serverAdapterA_outData_enqData$whas = + (!metaBram_0_serverAdapterA_s1[0] || + metaBram_0_serverAdapterA_outDataCore$FULL_N) && + metaBram_0_serverAdapterA_s1[1] && + metaBram_0_serverAdapterA_s1[0] ; + assign metaBram_0_serverAdapterA_outData_outData$wget = + metaBram_0_serverAdapterA_outDataCore$EMPTY_N ? + metaBram_0_serverAdapterA_outDataCore$D_OUT : + metaBram_0_memory$DOA ; + assign metaBram_0_serverAdapterA_outData_outData$whas = + metaBram_0_serverAdapterA_outDataCore$EMPTY_N || + !metaBram_0_serverAdapterA_outDataCore$EMPTY_N && + metaBram_0_serverAdapterA_outData_enqData$whas ; + assign metaBram_0_serverAdapterA_cnt_1$wget = 3'd1 ; + assign metaBram_0_serverAdapterA_cnt_1$whas = 1'b0 ; + assign metaBram_0_serverAdapterA_cnt_2$wget = 3'h0 ; + assign metaBram_0_serverAdapterA_cnt_2$whas = 1'b0 ; + assign metaBram_0_serverAdapterA_cnt_3$wget = 3'h0 ; + assign metaBram_0_serverAdapterA_cnt_3$whas = 1'b0 ; + assign metaBram_0_serverAdapterA_writeWithResp$wget = 2'd2 ; + assign metaBram_0_serverAdapterA_writeWithResp$whas = MUX_metaCount$write_1__SEL_2 ; - assign metaBram_serverAdapterA_s1_1$wget = 2'd2 ; - assign metaBram_serverAdapterA_s1_1$whas = MUX_metaCount$write_1__SEL_2 ; - assign metaBram_serverAdapterB_outData_enqData$wget = metaBram_memory$DOB ; - assign metaBram_serverAdapterB_outData_enqData$whas = - (!metaBram_serverAdapterB_s1[0] || - metaBram_serverAdapterB_outDataCore$FULL_N) && - metaBram_serverAdapterB_s1[1] && - metaBram_serverAdapterB_s1[0] ; - assign metaBram_serverAdapterB_outData_outData$wget = y_avValue__h26252 ; - assign metaBram_serverAdapterB_outData_outData$whas = - metaBram_serverAdapterB_outDataCore$EMPTY_N || - !metaBram_serverAdapterB_outDataCore$EMPTY_N && - metaBram_serverAdapterB_outData_enqData$whas ; - assign metaBram_serverAdapterB_cnt_1$wget = 3'd1 ; - assign metaBram_serverAdapterB_cnt_1$whas = - WILL_FIRE_RL_metaBram_serverAdapterB_stageReadResponseAlways ; - assign metaBram_serverAdapterB_cnt_2$wget = 3'd7 ; - assign metaBram_serverAdapterB_cnt_2$whas = - metaBram_serverAdapterB_outData_deqCalled$whas ; - assign metaBram_serverAdapterB_cnt_3$wget = 3'h0 ; - assign metaBram_serverAdapterB_cnt_3$whas = 1'b0 ; - assign metaBram_serverAdapterB_writeWithResp$wget = 2'd0 ; - assign metaBram_serverAdapterB_writeWithResp$whas = - WILL_FIRE_RL_metaBram_serverAdapterB_stageReadResponseAlways ; - assign metaBram_serverAdapterB_s1_1$wget = 2'd3 ; - assign metaBram_serverAdapterB_s1_1$whas = - WILL_FIRE_RL_metaBram_serverAdapterB_stageReadResponseAlways ; - assign metaBram_serverAdapterA_1_outData_enqData$wget = - metaBram_memory_1$DOA ; - assign metaBram_serverAdapterA_1_outData_enqData$whas = - (!metaBram_serverAdapterA_1_s1[0] || - metaBram_serverAdapterA_1_outDataCore$FULL_N) && - metaBram_serverAdapterA_1_s1[1] && - metaBram_serverAdapterA_1_s1[0] ; - assign metaBram_serverAdapterA_1_outData_outData$wget = - metaBram_serverAdapterA_1_outDataCore$EMPTY_N ? - metaBram_serverAdapterA_1_outDataCore$D_OUT : - metaBram_memory_1$DOA ; - assign metaBram_serverAdapterA_1_outData_outData$whas = - metaBram_serverAdapterA_1_outDataCore$EMPTY_N || - !metaBram_serverAdapterA_1_outDataCore$EMPTY_N && - metaBram_serverAdapterA_1_outData_enqData$whas ; - assign metaBram_serverAdapterA_1_cnt_1$wget = 3'd1 ; - assign metaBram_serverAdapterA_1_cnt_1$whas = 1'b0 ; - assign metaBram_serverAdapterA_1_cnt_2$wget = 3'h0 ; - assign metaBram_serverAdapterA_1_cnt_2$whas = 1'b0 ; - assign metaBram_serverAdapterA_1_cnt_3$wget = 3'h0 ; - assign metaBram_serverAdapterA_1_cnt_3$whas = 1'b0 ; - assign metaBram_serverAdapterA_1_writeWithResp$wget = 2'd2 ; - assign metaBram_serverAdapterA_1_writeWithResp$whas = + assign metaBram_0_serverAdapterA_s1_1$wget = 2'd2 ; + assign metaBram_0_serverAdapterA_s1_1$whas = MUX_metaCount$write_1__SEL_2 ; + assign metaBram_0_serverAdapterB_outData_enqData$wget = + metaBram_0_memory$DOB ; + assign metaBram_0_serverAdapterB_outData_enqData$whas = + (!metaBram_0_serverAdapterB_s1[0] || + metaBram_0_serverAdapterB_outDataCore$FULL_N) && + metaBram_0_serverAdapterB_s1[1] && + metaBram_0_serverAdapterB_s1[0] ; + assign metaBram_0_serverAdapterB_outData_outData$wget = y_avValue__h26025 ; + assign metaBram_0_serverAdapterB_outData_outData$whas = + metaBram_0_serverAdapterB_outDataCore$EMPTY_N || + !metaBram_0_serverAdapterB_outDataCore$EMPTY_N && + metaBram_0_serverAdapterB_outData_enqData$whas ; + assign metaBram_0_serverAdapterB_cnt_1$wget = 3'd1 ; + assign metaBram_0_serverAdapterB_cnt_1$whas = + WILL_FIRE_RL_metaBram_0_serverAdapterB_stageReadResponseAlways ; + assign metaBram_0_serverAdapterB_cnt_2$wget = 3'd7 ; + assign metaBram_0_serverAdapterB_cnt_2$whas = + metaBram_0_serverAdapterB_outData_deqCalled$whas ; + assign metaBram_0_serverAdapterB_cnt_3$wget = 3'h0 ; + assign metaBram_0_serverAdapterB_cnt_3$whas = 1'b0 ; + assign metaBram_0_serverAdapterB_writeWithResp$wget = 2'd0 ; + assign metaBram_0_serverAdapterB_writeWithResp$whas = + WILL_FIRE_RL_metaBram_0_serverAdapterB_stageReadResponseAlways ; + assign metaBram_0_serverAdapterB_s1_1$wget = 2'd3 ; + assign metaBram_0_serverAdapterB_s1_1$whas = + WILL_FIRE_RL_metaBram_0_serverAdapterB_stageReadResponseAlways ; + assign metaBram_1_serverAdapterA_outData_enqData$wget = + metaBram_1_memory$DOA ; + assign metaBram_1_serverAdapterA_outData_enqData$whas = + (!metaBram_1_serverAdapterA_s1[0] || + metaBram_1_serverAdapterA_outDataCore$FULL_N) && + metaBram_1_serverAdapterA_s1[1] && + metaBram_1_serverAdapterA_s1[0] ; + assign metaBram_1_serverAdapterA_outData_outData$wget = + metaBram_1_serverAdapterA_outDataCore$EMPTY_N ? + metaBram_1_serverAdapterA_outDataCore$D_OUT : + metaBram_1_memory$DOA ; + assign metaBram_1_serverAdapterA_outData_outData$whas = + metaBram_1_serverAdapterA_outDataCore$EMPTY_N || + !metaBram_1_serverAdapterA_outDataCore$EMPTY_N && + metaBram_1_serverAdapterA_outData_enqData$whas ; + assign metaBram_1_serverAdapterA_cnt_1$wget = 3'd1 ; + assign metaBram_1_serverAdapterA_cnt_1$whas = 1'b0 ; + assign metaBram_1_serverAdapterA_cnt_2$wget = 3'h0 ; + assign metaBram_1_serverAdapterA_cnt_2$whas = 1'b0 ; + assign metaBram_1_serverAdapterA_cnt_3$wget = 3'h0 ; + assign metaBram_1_serverAdapterA_cnt_3$whas = 1'b0 ; + assign metaBram_1_serverAdapterA_writeWithResp$wget = 2'd2 ; + assign metaBram_1_serverAdapterA_writeWithResp$whas = MUX_metaCount$write_1__SEL_2 ; - assign metaBram_serverAdapterA_1_s1_1$wget = 2'd2 ; - assign metaBram_serverAdapterA_1_s1_1$whas = MUX_metaCount$write_1__SEL_2 ; - assign metaBram_serverAdapterB_1_outData_enqData$wget = - metaBram_memory_1$DOB ; - assign metaBram_serverAdapterB_1_outData_enqData$whas = - (!metaBram_serverAdapterB_1_s1[0] || - metaBram_serverAdapterB_1_outDataCore$FULL_N) && - metaBram_serverAdapterB_1_s1[1] && - metaBram_serverAdapterB_1_s1[0] ; - assign metaBram_serverAdapterB_1_outData_outData$wget = y_avValue__h26292 ; - assign metaBram_serverAdapterB_1_outData_outData$whas = - metaBram_serverAdapterB_1_outDataCore$EMPTY_N || - !metaBram_serverAdapterB_1_outDataCore$EMPTY_N && - metaBram_serverAdapterB_1_outData_enqData$whas ; - assign metaBram_serverAdapterB_1_cnt_1$wget = 3'd1 ; - assign metaBram_serverAdapterB_1_cnt_1$whas = - WILL_FIRE_RL_metaBram_serverAdapterB_1_stageReadResponseAlways ; - assign metaBram_serverAdapterB_1_cnt_2$wget = 3'd7 ; - assign metaBram_serverAdapterB_1_cnt_2$whas = - metaBram_serverAdapterB_1_outData_deqCalled$whas ; - assign metaBram_serverAdapterB_1_cnt_3$wget = 3'h0 ; - assign metaBram_serverAdapterB_1_cnt_3$whas = 1'b0 ; - assign metaBram_serverAdapterB_1_writeWithResp$wget = 2'd0 ; - assign metaBram_serverAdapterB_1_writeWithResp$whas = - WILL_FIRE_RL_metaBram_serverAdapterB_1_stageReadResponseAlways ; - assign metaBram_serverAdapterB_1_s1_1$wget = 2'd3 ; - assign metaBram_serverAdapterB_1_s1_1$whas = - WILL_FIRE_RL_metaBram_serverAdapterB_1_stageReadResponseAlways ; - assign metaBram_serverAdapterA_2_outData_enqData$wget = - metaBram_memory_2$DOA ; - assign metaBram_serverAdapterA_2_outData_enqData$whas = - (!metaBram_serverAdapterA_2_s1[0] || - metaBram_serverAdapterA_2_outDataCore$FULL_N) && - metaBram_serverAdapterA_2_s1[1] && - metaBram_serverAdapterA_2_s1[0] ; - assign metaBram_serverAdapterA_2_outData_outData$wget = - metaBram_serverAdapterA_2_outDataCore$EMPTY_N ? - metaBram_serverAdapterA_2_outDataCore$D_OUT : - metaBram_memory_2$DOA ; - assign metaBram_serverAdapterA_2_outData_outData$whas = - metaBram_serverAdapterA_2_outDataCore$EMPTY_N || - !metaBram_serverAdapterA_2_outDataCore$EMPTY_N && - metaBram_serverAdapterA_2_outData_enqData$whas ; - assign metaBram_serverAdapterA_2_cnt_1$wget = 3'd1 ; - assign metaBram_serverAdapterA_2_cnt_1$whas = 1'b0 ; - assign metaBram_serverAdapterA_2_cnt_2$wget = 3'h0 ; - assign metaBram_serverAdapterA_2_cnt_2$whas = 1'b0 ; - assign metaBram_serverAdapterA_2_cnt_3$wget = 3'h0 ; - assign metaBram_serverAdapterA_2_cnt_3$whas = 1'b0 ; - assign metaBram_serverAdapterA_2_writeWithResp$wget = 2'd2 ; - assign metaBram_serverAdapterA_2_writeWithResp$whas = + assign metaBram_1_serverAdapterA_s1_1$wget = 2'd2 ; + assign metaBram_1_serverAdapterA_s1_1$whas = MUX_metaCount$write_1__SEL_2 ; + assign metaBram_1_serverAdapterB_outData_enqData$wget = + metaBram_1_memory$DOB ; + assign metaBram_1_serverAdapterB_outData_enqData$whas = + (!metaBram_1_serverAdapterB_s1[0] || + metaBram_1_serverAdapterB_outDataCore$FULL_N) && + metaBram_1_serverAdapterB_s1[1] && + metaBram_1_serverAdapterB_s1[0] ; + assign metaBram_1_serverAdapterB_outData_outData$wget = y_avValue__h26065 ; + assign metaBram_1_serverAdapterB_outData_outData$whas = + metaBram_1_serverAdapterB_outDataCore$EMPTY_N || + !metaBram_1_serverAdapterB_outDataCore$EMPTY_N && + metaBram_1_serverAdapterB_outData_enqData$whas ; + assign metaBram_1_serverAdapterB_cnt_1$wget = 3'd1 ; + assign metaBram_1_serverAdapterB_cnt_1$whas = + WILL_FIRE_RL_metaBram_1_serverAdapterB_stageReadResponseAlways ; + assign metaBram_1_serverAdapterB_cnt_2$wget = 3'd7 ; + assign metaBram_1_serverAdapterB_cnt_2$whas = + MUX_wci_wslv_respF_x_wire$wset_1__SEL_3 && + splaF$D_OUT[1:0] == 2'd1 && + !splaF$D_OUT[2] ; + assign metaBram_1_serverAdapterB_cnt_3$wget = 3'h0 ; + assign metaBram_1_serverAdapterB_cnt_3$whas = 1'b0 ; + assign metaBram_1_serverAdapterB_writeWithResp$wget = 2'd0 ; + assign metaBram_1_serverAdapterB_writeWithResp$whas = + WILL_FIRE_RL_metaBram_1_serverAdapterB_stageReadResponseAlways ; + assign metaBram_1_serverAdapterB_s1_1$wget = 2'd3 ; + assign metaBram_1_serverAdapterB_s1_1$whas = + WILL_FIRE_RL_metaBram_1_serverAdapterB_stageReadResponseAlways ; + assign metaBram_2_serverAdapterA_outData_enqData$wget = + metaBram_2_memory$DOA ; + assign metaBram_2_serverAdapterA_outData_enqData$whas = + (!metaBram_2_serverAdapterA_s1[0] || + metaBram_2_serverAdapterA_outDataCore$FULL_N) && + metaBram_2_serverAdapterA_s1[1] && + metaBram_2_serverAdapterA_s1[0] ; + assign metaBram_2_serverAdapterA_outData_outData$wget = + metaBram_2_serverAdapterA_outDataCore$EMPTY_N ? + metaBram_2_serverAdapterA_outDataCore$D_OUT : + metaBram_2_memory$DOA ; + assign metaBram_2_serverAdapterA_outData_outData$whas = + metaBram_2_serverAdapterA_outDataCore$EMPTY_N || + !metaBram_2_serverAdapterA_outDataCore$EMPTY_N && + metaBram_2_serverAdapterA_outData_enqData$whas ; + assign metaBram_2_serverAdapterA_cnt_1$wget = 3'd1 ; + assign metaBram_2_serverAdapterA_cnt_1$whas = 1'b0 ; + assign metaBram_2_serverAdapterA_cnt_2$wget = 3'h0 ; + assign metaBram_2_serverAdapterA_cnt_2$whas = 1'b0 ; + assign metaBram_2_serverAdapterA_cnt_3$wget = 3'h0 ; + assign metaBram_2_serverAdapterA_cnt_3$whas = 1'b0 ; + assign metaBram_2_serverAdapterA_writeWithResp$wget = 2'd2 ; + assign metaBram_2_serverAdapterA_writeWithResp$whas = MUX_metaCount$write_1__SEL_2 ; - assign metaBram_serverAdapterA_2_s1_1$wget = 2'd2 ; - assign metaBram_serverAdapterA_2_s1_1$whas = MUX_metaCount$write_1__SEL_2 ; - assign metaBram_serverAdapterB_2_outData_enqData$wget = - metaBram_memory_2$DOB ; - assign metaBram_serverAdapterB_2_outData_enqData$whas = - (!metaBram_serverAdapterB_2_s1[0] || - metaBram_serverAdapterB_2_outDataCore$FULL_N) && - metaBram_serverAdapterB_2_s1[1] && - metaBram_serverAdapterB_2_s1[0] ; - assign metaBram_serverAdapterB_2_outData_outData$wget = y_avValue__h26332 ; - assign metaBram_serverAdapterB_2_outData_outData$whas = - metaBram_serverAdapterB_2_outDataCore$EMPTY_N || - !metaBram_serverAdapterB_2_outDataCore$EMPTY_N && - metaBram_serverAdapterB_2_outData_enqData$whas ; - assign metaBram_serverAdapterB_2_cnt_1$wget = 3'd1 ; - assign metaBram_serverAdapterB_2_cnt_1$whas = - WILL_FIRE_RL_metaBram_serverAdapterB_2_stageReadResponseAlways ; - assign metaBram_serverAdapterB_2_cnt_2$wget = 3'd7 ; - assign metaBram_serverAdapterB_2_cnt_2$whas = - metaBram_serverAdapterB_2_outData_deqCalled$whas ; - assign metaBram_serverAdapterB_2_cnt_3$wget = 3'h0 ; - assign metaBram_serverAdapterB_2_cnt_3$whas = 1'b0 ; - assign metaBram_serverAdapterB_2_writeWithResp$wget = 2'd0 ; - assign metaBram_serverAdapterB_2_writeWithResp$whas = - WILL_FIRE_RL_metaBram_serverAdapterB_2_stageReadResponseAlways ; - assign metaBram_serverAdapterB_2_s1_1$wget = 2'd3 ; - assign metaBram_serverAdapterB_2_s1_1$whas = - WILL_FIRE_RL_metaBram_serverAdapterB_2_stageReadResponseAlways ; - assign metaBram_serverAdapterA_3_outData_enqData$wget = - metaBram_memory_3$DOA ; - assign metaBram_serverAdapterA_3_outData_enqData$whas = - (!metaBram_serverAdapterA_3_s1[0] || - metaBram_serverAdapterA_3_outDataCore$FULL_N) && - metaBram_serverAdapterA_3_s1[1] && - metaBram_serverAdapterA_3_s1[0] ; - assign metaBram_serverAdapterA_3_outData_outData$wget = - metaBram_serverAdapterA_3_outDataCore$EMPTY_N ? - metaBram_serverAdapterA_3_outDataCore$D_OUT : - metaBram_memory_3$DOA ; - assign metaBram_serverAdapterA_3_outData_outData$whas = - metaBram_serverAdapterA_3_outDataCore$EMPTY_N || - !metaBram_serverAdapterA_3_outDataCore$EMPTY_N && - metaBram_serverAdapterA_3_outData_enqData$whas ; - assign metaBram_serverAdapterA_3_cnt_1$wget = 3'd1 ; - assign metaBram_serverAdapterA_3_cnt_1$whas = 1'b0 ; - assign metaBram_serverAdapterA_3_cnt_2$wget = 3'h0 ; - assign metaBram_serverAdapterA_3_cnt_2$whas = 1'b0 ; - assign metaBram_serverAdapterA_3_cnt_3$wget = 3'h0 ; - assign metaBram_serverAdapterA_3_cnt_3$whas = 1'b0 ; - assign metaBram_serverAdapterA_3_writeWithResp$wget = 2'd2 ; - assign metaBram_serverAdapterA_3_writeWithResp$whas = + assign metaBram_2_serverAdapterA_s1_1$wget = 2'd2 ; + assign metaBram_2_serverAdapterA_s1_1$whas = MUX_metaCount$write_1__SEL_2 ; + assign metaBram_2_serverAdapterB_outData_enqData$wget = + metaBram_2_memory$DOB ; + assign metaBram_2_serverAdapterB_outData_enqData$whas = + (!metaBram_2_serverAdapterB_s1[0] || + metaBram_2_serverAdapterB_outDataCore$FULL_N) && + metaBram_2_serverAdapterB_s1[1] && + metaBram_2_serverAdapterB_s1[0] ; + assign metaBram_2_serverAdapterB_outData_outData$wget = y_avValue__h26105 ; + assign metaBram_2_serverAdapterB_outData_outData$whas = + metaBram_2_serverAdapterB_outDataCore$EMPTY_N || + !metaBram_2_serverAdapterB_outDataCore$EMPTY_N && + metaBram_2_serverAdapterB_outData_enqData$whas ; + assign metaBram_2_serverAdapterB_cnt_1$wget = 3'd1 ; + assign metaBram_2_serverAdapterB_cnt_1$whas = + WILL_FIRE_RL_metaBram_2_serverAdapterB_stageReadResponseAlways ; + assign metaBram_2_serverAdapterB_cnt_2$wget = 3'd7 ; + assign metaBram_2_serverAdapterB_cnt_2$whas = + metaBram_2_serverAdapterB_outData_deqCalled$whas ; + assign metaBram_2_serverAdapterB_cnt_3$wget = 3'h0 ; + assign metaBram_2_serverAdapterB_cnt_3$whas = 1'b0 ; + assign metaBram_2_serverAdapterB_writeWithResp$wget = 2'd0 ; + assign metaBram_2_serverAdapterB_writeWithResp$whas = + WILL_FIRE_RL_metaBram_2_serverAdapterB_stageReadResponseAlways ; + assign metaBram_2_serverAdapterB_s1_1$wget = 2'd3 ; + assign metaBram_2_serverAdapterB_s1_1$whas = + WILL_FIRE_RL_metaBram_2_serverAdapterB_stageReadResponseAlways ; + assign metaBram_3_serverAdapterA_outData_enqData$wget = + metaBram_3_memory$DOA ; + assign metaBram_3_serverAdapterA_outData_enqData$whas = + (!metaBram_3_serverAdapterA_s1[0] || + metaBram_3_serverAdapterA_outDataCore$FULL_N) && + metaBram_3_serverAdapterA_s1[1] && + metaBram_3_serverAdapterA_s1[0] ; + assign metaBram_3_serverAdapterA_outData_outData$wget = + metaBram_3_serverAdapterA_outDataCore$EMPTY_N ? + metaBram_3_serverAdapterA_outDataCore$D_OUT : + metaBram_3_memory$DOA ; + assign metaBram_3_serverAdapterA_outData_outData$whas = + metaBram_3_serverAdapterA_outDataCore$EMPTY_N || + !metaBram_3_serverAdapterA_outDataCore$EMPTY_N && + metaBram_3_serverAdapterA_outData_enqData$whas ; + assign metaBram_3_serverAdapterA_cnt_1$wget = 3'd1 ; + assign metaBram_3_serverAdapterA_cnt_1$whas = 1'b0 ; + assign metaBram_3_serverAdapterA_cnt_2$wget = 3'h0 ; + assign metaBram_3_serverAdapterA_cnt_2$whas = 1'b0 ; + assign metaBram_3_serverAdapterA_cnt_3$wget = 3'h0 ; + assign metaBram_3_serverAdapterA_cnt_3$whas = 1'b0 ; + assign metaBram_3_serverAdapterA_writeWithResp$wget = 2'd2 ; + assign metaBram_3_serverAdapterA_writeWithResp$whas = MUX_metaCount$write_1__SEL_2 ; - assign metaBram_serverAdapterA_3_s1_1$wget = 2'd2 ; - assign metaBram_serverAdapterA_3_s1_1$whas = MUX_metaCount$write_1__SEL_2 ; - assign metaBram_serverAdapterB_3_outData_enqData$wget = - metaBram_memory_3$DOB ; - assign metaBram_serverAdapterB_3_outData_enqData$whas = - (!metaBram_serverAdapterB_3_s1[0] || - metaBram_serverAdapterB_3_outDataCore$FULL_N) && - metaBram_serverAdapterB_3_s1[1] && - metaBram_serverAdapterB_3_s1[0] ; - assign metaBram_serverAdapterB_3_outData_outData$wget = y_avValue__h26372 ; - assign metaBram_serverAdapterB_3_outData_outData$whas = - metaBram_serverAdapterB_3_outDataCore$EMPTY_N || - !metaBram_serverAdapterB_3_outDataCore$EMPTY_N && - metaBram_serverAdapterB_3_outData_enqData$whas ; - assign metaBram_serverAdapterB_3_cnt_1$wget = 3'd1 ; - assign metaBram_serverAdapterB_3_cnt_1$whas = - WILL_FIRE_RL_metaBram_serverAdapterB_3_stageReadResponseAlways ; - assign metaBram_serverAdapterB_3_cnt_2$wget = 3'd7 ; - assign metaBram_serverAdapterB_3_cnt_2$whas = - metaBram_serverAdapterB_3_outData_deqCalled$whas ; - assign metaBram_serverAdapterB_3_cnt_3$wget = 3'h0 ; - assign metaBram_serverAdapterB_3_cnt_3$whas = 1'b0 ; - assign metaBram_serverAdapterB_3_writeWithResp$wget = 2'd0 ; - assign metaBram_serverAdapterB_3_writeWithResp$whas = - WILL_FIRE_RL_metaBram_serverAdapterB_3_stageReadResponseAlways ; - assign metaBram_serverAdapterB_3_s1_1$wget = 2'd3 ; - assign metaBram_serverAdapterB_3_s1_1$whas = - WILL_FIRE_RL_metaBram_serverAdapterB_3_stageReadResponseAlways ; + assign metaBram_3_serverAdapterA_s1_1$wget = 2'd2 ; + assign metaBram_3_serverAdapterA_s1_1$whas = MUX_metaCount$write_1__SEL_2 ; + assign metaBram_3_serverAdapterB_outData_enqData$wget = + metaBram_3_memory$DOB ; + assign metaBram_3_serverAdapterB_outData_enqData$whas = + (!metaBram_3_serverAdapterB_s1[0] || + metaBram_3_serverAdapterB_outDataCore$FULL_N) && + metaBram_3_serverAdapterB_s1[1] && + metaBram_3_serverAdapterB_s1[0] ; + assign metaBram_3_serverAdapterB_outData_outData$wget = y_avValue__h26145 ; + assign metaBram_3_serverAdapterB_outData_outData$whas = + metaBram_3_serverAdapterB_outDataCore$EMPTY_N || + !metaBram_3_serverAdapterB_outDataCore$EMPTY_N && + metaBram_3_serverAdapterB_outData_enqData$whas ; + assign metaBram_3_serverAdapterB_cnt_1$wget = 3'd1 ; + assign metaBram_3_serverAdapterB_cnt_1$whas = + WILL_FIRE_RL_metaBram_3_serverAdapterB_stageReadResponseAlways ; + assign metaBram_3_serverAdapterB_cnt_2$wget = 3'd7 ; + assign metaBram_3_serverAdapterB_cnt_2$whas = + metaBram_3_serverAdapterB_outData_deqCalled$whas ; + assign metaBram_3_serverAdapterB_cnt_3$wget = 3'h0 ; + assign metaBram_3_serverAdapterB_cnt_3$whas = 1'b0 ; + assign metaBram_3_serverAdapterB_writeWithResp$wget = 2'd0 ; + assign metaBram_3_serverAdapterB_writeWithResp$whas = + WILL_FIRE_RL_metaBram_3_serverAdapterB_stageReadResponseAlways ; + assign metaBram_3_serverAdapterB_s1_1$wget = 2'd3 ; + assign metaBram_3_serverAdapterB_s1_1$whas = + WILL_FIRE_RL_metaBram_3_serverAdapterB_stageReadResponseAlways ; assign wsi_Es_mCmd_w$wget = wsiS0_MCmd ; assign wsi_Es_mCmd_w$whas = 1'd1 ; assign wsi_Es_mBurstLength_w$wget = wsiS0_MBurstLength ; @@ -1787,7 +1800,7 @@ module mkWSICaptureWorker4B(wciS0_Clk, MUX_wci_wslv_respF_x_wire$wset_1__SEL_3 || WILL_FIRE_RL_wci_cfwr || WILL_FIRE_RL_wci_wslv_ctl_op_complete ; - assign wci_wslv_respF_dequeueing$whas = wci_wslv_respF_c_r != 2'd0 ; + assign wci_wslv_respF_dequeueing$whas = wci_wslv_respF_cntr_r != 2'd0 ; assign wci_wslv_sThreadBusy_pw$whas = 1'b0 ; assign wci_wslv_wci_cfwr_pw$whas = wci_wslv_reqF$EMPTY_N && wci_wslv_reqF$D_OUT[68] && @@ -1806,26 +1819,28 @@ module mkWSICaptureWorker4B(wciS0_Clk, assign wsiS_reqFifo_doResetDeq$whas = MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 ; assign wsiS_reqFifo_doResetClr$whas = 1'b0 ; - assign dataBram_serverAdapterA_outData_deqCalled$whas = 1'b0 ; - assign dataBram_serverAdapterB_outData_deqCalled$whas = + assign dataBram_0_serverAdapterA_outData_deqCalled$whas = 1'b0 ; + assign dataBram_0_serverAdapterB_outData_deqCalled$whas = MUX_wci_wslv_respF_x_wire$wset_1__SEL_3 && splaF$D_OUT[2] && splaF$D_OUT[1:0] == 2'd0 ; - assign metaBram_serverAdapterA_outData_deqCalled$whas = 1'b0 ; - assign metaBram_serverAdapterB_outData_deqCalled$whas = - MUX_wci_wslv_respF_x_wire$wset_1__SEL_3 && !splaF$D_OUT[2] && - splaF$D_OUT[1:0] == 2'd0 ; - assign metaBram_serverAdapterA_1_outData_deqCalled$whas = 1'b0 ; - assign metaBram_serverAdapterB_1_outData_deqCalled$whas = - MUX_wci_wslv_respF_x_wire$wset_1__SEL_3 && !splaF$D_OUT[2] && - splaF$D_OUT[1:0] == 2'd1 ; - assign metaBram_serverAdapterA_2_outData_deqCalled$whas = 1'b0 ; - assign metaBram_serverAdapterB_2_outData_deqCalled$whas = - MUX_wci_wslv_respF_x_wire$wset_1__SEL_3 && !splaF$D_OUT[2] && - splaF$D_OUT[1:0] == 2'd2 ; - assign metaBram_serverAdapterA_3_outData_deqCalled$whas = 1'b0 ; - assign metaBram_serverAdapterB_3_outData_deqCalled$whas = - MUX_wci_wslv_respF_x_wire$wset_1__SEL_3 && !splaF$D_OUT[2] && - splaF$D_OUT[1:0] == 2'd3 ; + assign metaBram_0_serverAdapterA_outData_deqCalled$whas = 1'b0 ; + assign metaBram_0_serverAdapterB_outData_deqCalled$whas = + MUX_wci_wslv_respF_x_wire$wset_1__SEL_3 && + splaF$D_OUT[1:0] == 2'd0 && + !splaF$D_OUT[2] ; + assign metaBram_1_serverAdapterA_outData_deqCalled$whas = 1'b0 ; + assign metaBram_1_serverAdapterB_outData_deqCalled$whas = + metaBram_1_serverAdapterB_cnt_2$whas ; + assign metaBram_2_serverAdapterA_outData_deqCalled$whas = 1'b0 ; + assign metaBram_2_serverAdapterB_outData_deqCalled$whas = + MUX_wci_wslv_respF_x_wire$wset_1__SEL_3 && + splaF$D_OUT[1:0] == 2'd2 && + !splaF$D_OUT[2] ; + assign metaBram_3_serverAdapterA_outData_deqCalled$whas = 1'b0 ; + assign metaBram_3_serverAdapterB_outData_deqCalled$whas = + MUX_wci_wslv_respF_x_wire$wset_1__SEL_3 && + splaF$D_OUT[1:0] == 2'd3 && + !splaF$D_OUT[2] ; assign wsi_Es_mReqLast_w$whas = wsiS0_MReqLast ; assign wsi_Es_mBurstPrecise_w$whas = wsiS0_MBurstPrecise ; assign wsi_Es_mDataInfo_w$whas = 1'd1 ; @@ -1841,28 +1856,28 @@ module mkWSICaptureWorker4B(wciS0_Clk, WILL_FIRE_RL_wci_cfwr && wci_wslv_reqF$D_OUT[39:32] == 8'h0 || MUX_controlReg$write_1__SEL_2 ; - // register dataBram_serverAdapterA_cnt - assign dataBram_serverAdapterA_cnt$D_IN = - dataBram_serverAdapterA_cnt + 3'd0 + 3'd0 ; - assign dataBram_serverAdapterA_cnt$EN = 1'b0 ; + // register dataBram_0_serverAdapterA_cnt + assign dataBram_0_serverAdapterA_cnt$D_IN = + dataBram_0_serverAdapterA_cnt + 3'd0 + 3'd0 ; + assign dataBram_0_serverAdapterA_cnt$EN = 1'b0 ; - // register dataBram_serverAdapterA_s1 - assign dataBram_serverAdapterA_s1$D_IN = + // register dataBram_0_serverAdapterA_s1 + assign dataBram_0_serverAdapterA_s1$D_IN = { MUX_dataCount$write_1__SEL_2, 1'b0 } ; - assign dataBram_serverAdapterA_s1$EN = 1'd1 ; - - // register dataBram_serverAdapterB_cnt - assign dataBram_serverAdapterB_cnt$D_IN = - dataBram_serverAdapterB_cnt_21_PLUS_IF_dataBra_ETC___d327 ; - assign dataBram_serverAdapterB_cnt$EN = - WILL_FIRE_RL_dataBram_serverAdapterB_stageReadResponseAlways || - dataBram_serverAdapterB_outData_deqCalled$whas ; - - // register dataBram_serverAdapterB_s1 - assign dataBram_serverAdapterB_s1$D_IN = - { WILL_FIRE_RL_dataBram_serverAdapterB_stageReadResponseAlways, + assign dataBram_0_serverAdapterA_s1$EN = 1'd1 ; + + // register dataBram_0_serverAdapterB_cnt + assign dataBram_0_serverAdapterB_cnt$D_IN = + dataBram_0_serverAdapterB_cnt_19_PLUS_IF_dataB_ETC___d325 ; + assign dataBram_0_serverAdapterB_cnt$EN = + WILL_FIRE_RL_dataBram_0_serverAdapterB_stageReadResponseAlways || + dataBram_0_serverAdapterB_outData_deqCalled$whas ; + + // register dataBram_0_serverAdapterB_s1 + assign dataBram_0_serverAdapterB_s1$D_IN = + { WILL_FIRE_RL_dataBram_0_serverAdapterB_stageReadResponseAlways, 1'b1 } ; - assign dataBram_serverAdapterB_s1$EN = 1'd1 ; + assign dataBram_0_serverAdapterB_s1$EN = 1'd1 ; // register dataCount always@(MUX_dataCount$write_1__SEL_1 or @@ -1878,7 +1893,7 @@ module mkWSICaptureWorker4B(wciS0_Clk, endcase assign dataCount$EN = MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 && - controlReg_30_BIT_0_31_AND_NOT_controlReg_30_B_ETC___d878 || + controlReg_28_BIT_0_29_AND_NOT_controlReg_28_B_ETC___d876 || WILL_FIRE_RL_wci_cfwr && wci_wslv_reqF$D_OUT[39:32] == 8'h08 || MUX_controlReg$write_1__SEL_2 ; @@ -1887,100 +1902,100 @@ module mkWSICaptureWorker4B(wciS0_Clk, assign isFirst$EN = 1'b0 ; // register mesgLengthSoFar - assign mesgLengthSoFar$D_IN = wsiS_reqFifo$D_OUT[57] ? 14'd0 : mlB__h23348 ; + assign mesgLengthSoFar$D_IN = wsiS_reqFifo$D_OUT[57] ? 14'd0 : mlB__h23202 ; assign mesgLengthSoFar$EN = MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 ; - // register metaBram_serverAdapterA_1_cnt - assign metaBram_serverAdapterA_1_cnt$D_IN = - metaBram_serverAdapterA_1_cnt + 3'd0 + 3'd0 ; - assign metaBram_serverAdapterA_1_cnt$EN = 1'b0 ; + // register metaBram_0_serverAdapterA_cnt + assign metaBram_0_serverAdapterA_cnt$D_IN = + metaBram_0_serverAdapterA_cnt + 3'd0 + 3'd0 ; + assign metaBram_0_serverAdapterA_cnt$EN = 1'b0 ; - // register metaBram_serverAdapterA_1_s1 - assign metaBram_serverAdapterA_1_s1$D_IN = + // register metaBram_0_serverAdapterA_s1 + assign metaBram_0_serverAdapterA_s1$D_IN = { MUX_metaCount$write_1__SEL_2, 1'b0 } ; - assign metaBram_serverAdapterA_1_s1$EN = 1'd1 ; + assign metaBram_0_serverAdapterA_s1$EN = 1'd1 ; + + // register metaBram_0_serverAdapterB_cnt + assign metaBram_0_serverAdapterB_cnt$D_IN = + metaBram_0_serverAdapterB_cnt_37_PLUS_IF_metaB_ETC___d443 ; + assign metaBram_0_serverAdapterB_cnt$EN = + WILL_FIRE_RL_metaBram_0_serverAdapterB_stageReadResponseAlways || + metaBram_0_serverAdapterB_outData_deqCalled$whas ; + + // register metaBram_0_serverAdapterB_s1 + assign metaBram_0_serverAdapterB_s1$D_IN = + { WILL_FIRE_RL_metaBram_0_serverAdapterB_stageReadResponseAlways, + 1'b1 } ; + assign metaBram_0_serverAdapterB_s1$EN = 1'd1 ; - // register metaBram_serverAdapterA_2_cnt - assign metaBram_serverAdapterA_2_cnt$D_IN = - metaBram_serverAdapterA_2_cnt + 3'd0 + 3'd0 ; - assign metaBram_serverAdapterA_2_cnt$EN = 1'b0 ; + // register metaBram_1_serverAdapterA_cnt + assign metaBram_1_serverAdapterA_cnt$D_IN = + metaBram_1_serverAdapterA_cnt + 3'd0 + 3'd0 ; + assign metaBram_1_serverAdapterA_cnt$EN = 1'b0 ; - // register metaBram_serverAdapterA_2_s1 - assign metaBram_serverAdapterA_2_s1$D_IN = + // register metaBram_1_serverAdapterA_s1 + assign metaBram_1_serverAdapterA_s1$D_IN = { MUX_metaCount$write_1__SEL_2, 1'b0 } ; - assign metaBram_serverAdapterA_2_s1$EN = 1'd1 ; + assign metaBram_1_serverAdapterA_s1$EN = 1'd1 ; + + // register metaBram_1_serverAdapterB_cnt + assign metaBram_1_serverAdapterB_cnt$D_IN = + metaBram_1_serverAdapterB_cnt_55_PLUS_IF_metaB_ETC___d561 ; + assign metaBram_1_serverAdapterB_cnt$EN = + WILL_FIRE_RL_metaBram_1_serverAdapterB_stageReadResponseAlways || + metaBram_1_serverAdapterB_cnt_2$whas ; + + // register metaBram_1_serverAdapterB_s1 + assign metaBram_1_serverAdapterB_s1$D_IN = + { WILL_FIRE_RL_metaBram_1_serverAdapterB_stageReadResponseAlways, + 1'b1 } ; + assign metaBram_1_serverAdapterB_s1$EN = 1'd1 ; - // register metaBram_serverAdapterA_3_cnt - assign metaBram_serverAdapterA_3_cnt$D_IN = - metaBram_serverAdapterA_3_cnt + 3'd0 + 3'd0 ; - assign metaBram_serverAdapterA_3_cnt$EN = 1'b0 ; + // register metaBram_2_serverAdapterA_cnt + assign metaBram_2_serverAdapterA_cnt$D_IN = + metaBram_2_serverAdapterA_cnt + 3'd0 + 3'd0 ; + assign metaBram_2_serverAdapterA_cnt$EN = 1'b0 ; - // register metaBram_serverAdapterA_3_s1 - assign metaBram_serverAdapterA_3_s1$D_IN = + // register metaBram_2_serverAdapterA_s1 + assign metaBram_2_serverAdapterA_s1$D_IN = { MUX_metaCount$write_1__SEL_2, 1'b0 } ; - assign metaBram_serverAdapterA_3_s1$EN = 1'd1 ; + assign metaBram_2_serverAdapterA_s1$EN = 1'd1 ; + + // register metaBram_2_serverAdapterB_cnt + assign metaBram_2_serverAdapterB_cnt$D_IN = + metaBram_2_serverAdapterB_cnt_73_PLUS_IF_metaB_ETC___d679 ; + assign metaBram_2_serverAdapterB_cnt$EN = + WILL_FIRE_RL_metaBram_2_serverAdapterB_stageReadResponseAlways || + metaBram_2_serverAdapterB_outData_deqCalled$whas ; + + // register metaBram_2_serverAdapterB_s1 + assign metaBram_2_serverAdapterB_s1$D_IN = + { WILL_FIRE_RL_metaBram_2_serverAdapterB_stageReadResponseAlways, + 1'b1 } ; + assign metaBram_2_serverAdapterB_s1$EN = 1'd1 ; - // register metaBram_serverAdapterA_cnt - assign metaBram_serverAdapterA_cnt$D_IN = - metaBram_serverAdapterA_cnt + 3'd0 + 3'd0 ; - assign metaBram_serverAdapterA_cnt$EN = 1'b0 ; + // register metaBram_3_serverAdapterA_cnt + assign metaBram_3_serverAdapterA_cnt$D_IN = + metaBram_3_serverAdapterA_cnt + 3'd0 + 3'd0 ; + assign metaBram_3_serverAdapterA_cnt$EN = 1'b0 ; - // register metaBram_serverAdapterA_s1 - assign metaBram_serverAdapterA_s1$D_IN = + // register metaBram_3_serverAdapterA_s1 + assign metaBram_3_serverAdapterA_s1$D_IN = { MUX_metaCount$write_1__SEL_2, 1'b0 } ; - assign metaBram_serverAdapterA_s1$EN = 1'd1 ; - - // register metaBram_serverAdapterB_1_cnt - assign metaBram_serverAdapterB_1_cnt$D_IN = - metaBram_serverAdapterB_1_cnt_57_PLUS_IF_metaB_ETC___d563 ; - assign metaBram_serverAdapterB_1_cnt$EN = - WILL_FIRE_RL_metaBram_serverAdapterB_1_stageReadResponseAlways || - metaBram_serverAdapterB_1_outData_deqCalled$whas ; - - // register metaBram_serverAdapterB_1_s1 - assign metaBram_serverAdapterB_1_s1$D_IN = - { WILL_FIRE_RL_metaBram_serverAdapterB_1_stageReadResponseAlways, - 1'b1 } ; - assign metaBram_serverAdapterB_1_s1$EN = 1'd1 ; - - // register metaBram_serverAdapterB_2_cnt - assign metaBram_serverAdapterB_2_cnt$D_IN = - metaBram_serverAdapterB_2_cnt_75_PLUS_IF_metaB_ETC___d681 ; - assign metaBram_serverAdapterB_2_cnt$EN = - WILL_FIRE_RL_metaBram_serverAdapterB_2_stageReadResponseAlways || - metaBram_serverAdapterB_2_outData_deqCalled$whas ; - - // register metaBram_serverAdapterB_2_s1 - assign metaBram_serverAdapterB_2_s1$D_IN = - { WILL_FIRE_RL_metaBram_serverAdapterB_2_stageReadResponseAlways, + assign metaBram_3_serverAdapterA_s1$EN = 1'd1 ; + + // register metaBram_3_serverAdapterB_cnt + assign metaBram_3_serverAdapterB_cnt$D_IN = + metaBram_3_serverAdapterB_cnt_91_PLUS_IF_metaB_ETC___d797 ; + assign metaBram_3_serverAdapterB_cnt$EN = + WILL_FIRE_RL_metaBram_3_serverAdapterB_stageReadResponseAlways || + metaBram_3_serverAdapterB_outData_deqCalled$whas ; + + // register metaBram_3_serverAdapterB_s1 + assign metaBram_3_serverAdapterB_s1$D_IN = + { WILL_FIRE_RL_metaBram_3_serverAdapterB_stageReadResponseAlways, 1'b1 } ; - assign metaBram_serverAdapterB_2_s1$EN = 1'd1 ; - - // register metaBram_serverAdapterB_3_cnt - assign metaBram_serverAdapterB_3_cnt$D_IN = - metaBram_serverAdapterB_3_cnt_93_PLUS_IF_metaB_ETC___d799 ; - assign metaBram_serverAdapterB_3_cnt$EN = - WILL_FIRE_RL_metaBram_serverAdapterB_3_stageReadResponseAlways || - metaBram_serverAdapterB_3_outData_deqCalled$whas ; - - // register metaBram_serverAdapterB_3_s1 - assign metaBram_serverAdapterB_3_s1$D_IN = - { WILL_FIRE_RL_metaBram_serverAdapterB_3_stageReadResponseAlways, - 1'b1 } ; - assign metaBram_serverAdapterB_3_s1$EN = 1'd1 ; - - // register metaBram_serverAdapterB_cnt - assign metaBram_serverAdapterB_cnt$D_IN = - metaBram_serverAdapterB_cnt_39_PLUS_IF_metaBra_ETC___d445 ; - assign metaBram_serverAdapterB_cnt$EN = - WILL_FIRE_RL_metaBram_serverAdapterB_stageReadResponseAlways || - metaBram_serverAdapterB_outData_deqCalled$whas ; - - // register metaBram_serverAdapterB_s1 - assign metaBram_serverAdapterB_s1$D_IN = - { WILL_FIRE_RL_metaBram_serverAdapterB_stageReadResponseAlways, - 1'b1 } ; - assign metaBram_serverAdapterB_s1$EN = 1'd1 ; + assign metaBram_3_serverAdapterB_s1$EN = 1'd1 ; // register metaCount always@(MUX_metaCount$write_1__SEL_1 or @@ -1995,10 +2010,10 @@ module mkWSICaptureWorker4B(wciS0_Clk, default: metaCount$D_IN = 32'hAAAAAAAA /* unspecified value */ ; endcase assign metaCount$EN = + WILL_FIRE_RL_wci_cfwr && wci_wslv_reqF$D_OUT[39:32] == 8'h04 || MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 && - controlReg_30_BIT_0_31_AND_NOT_controlReg_30_B_ETC___d878 && + controlReg_28_BIT_0_29_AND_NOT_controlReg_28_B_ETC___d876 && wsiS_reqFifo$D_OUT[57] || - WILL_FIRE_RL_wci_cfwr && wci_wslv_reqF$D_OUT[39:32] == 8'h04 || MUX_controlReg$write_1__SEL_2 ; // register splitReadInFlight @@ -2069,24 +2084,24 @@ module mkWSICaptureWorker4B(wciS0_Clk, (wci_wslv_wciReq$wget[71:69] != 3'd0) != wci_wslv_reqF_r_deq$whas ; - // register wci_wslv_respF_c_r - assign wci_wslv_respF_c_r$D_IN = - WILL_FIRE_RL_wci_wslv_respF_incCtr ? - MUX_wci_wslv_respF_c_r$write_1__VAL_1 : - MUX_wci_wslv_respF_c_r$write_1__VAL_2 ; - assign wci_wslv_respF_c_r$EN = - WILL_FIRE_RL_wci_wslv_respF_incCtr || - WILL_FIRE_RL_wci_wslv_respF_decCtr ; + // register wci_wslv_respF_cntr_r + assign wci_wslv_respF_cntr_r$D_IN = + WILL_FIRE_RL_wci_wslv_respF_decCtr ? + wci_wslv_respF_cntr_r_8_MINUS_1___d27 : + MUX_wci_wslv_respF_cntr_r$write_1__VAL_2 ; + assign wci_wslv_respF_cntr_r$EN = + WILL_FIRE_RL_wci_wslv_respF_decCtr || + WILL_FIRE_RL_wci_wslv_respF_incCtr ; // register wci_wslv_respF_q_0 - always@(WILL_FIRE_RL_wci_wslv_respF_both or + always@(MUX_wci_wslv_respF_q_0$write_1__SEL_1 or MUX_wci_wslv_respF_q_0$write_1__VAL_1 or MUX_wci_wslv_respF_q_0$write_1__SEL_2 or MUX_wci_wslv_respF_q_0$write_1__VAL_2 or WILL_FIRE_RL_wci_wslv_respF_decCtr or wci_wslv_respF_q_1) begin case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_wci_wslv_respF_both: + MUX_wci_wslv_respF_q_0$write_1__SEL_1: wci_wslv_respF_q_0$D_IN = MUX_wci_wslv_respF_q_0$write_1__VAL_1; MUX_wci_wslv_respF_q_0$write_1__SEL_2: wci_wslv_respF_q_0$D_IN = MUX_wci_wslv_respF_q_0$write_1__VAL_2; @@ -2097,20 +2112,20 @@ module mkWSICaptureWorker4B(wciS0_Clk, endcase end assign wci_wslv_respF_q_0$EN = - WILL_FIRE_RL_wci_wslv_respF_both || + WILL_FIRE_RL_wci_wslv_respF_both && _dfoo3 || WILL_FIRE_RL_wci_wslv_respF_incCtr && - wci_wslv_respF_c_r == 2'd0 || + wci_wslv_respF_cntr_r == 2'd0 || WILL_FIRE_RL_wci_wslv_respF_decCtr ; // register wci_wslv_respF_q_1 - always@(WILL_FIRE_RL_wci_wslv_respF_both or + always@(MUX_wci_wslv_respF_q_1$write_1__SEL_1 or MUX_wci_wslv_respF_q_1$write_1__VAL_1 or MUX_wci_wslv_respF_q_1$write_1__SEL_2 or MUX_wci_wslv_respF_q_0$write_1__VAL_2 or WILL_FIRE_RL_wci_wslv_respF_decCtr) begin case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_wci_wslv_respF_both: + MUX_wci_wslv_respF_q_1$write_1__SEL_1: wci_wslv_respF_q_1$D_IN = MUX_wci_wslv_respF_q_1$write_1__VAL_1; MUX_wci_wslv_respF_q_1$write_1__SEL_2: wci_wslv_respF_q_1$D_IN = MUX_wci_wslv_respF_q_0$write_1__VAL_2; @@ -2121,9 +2136,9 @@ module mkWSICaptureWorker4B(wciS0_Clk, endcase end assign wci_wslv_respF_q_1$EN = - WILL_FIRE_RL_wci_wslv_respF_both || + WILL_FIRE_RL_wci_wslv_respF_both && _dfoo1 || WILL_FIRE_RL_wci_wslv_respF_incCtr && - wci_wslv_respF_c_r == 2'd1 || + wci_wslv_respF_cntr_r == 2'd1 || WILL_FIRE_RL_wci_wslv_respF_decCtr ; // register wci_wslv_sFlagReg @@ -2233,170 +2248,170 @@ module mkWSICaptureWorker4B(wciS0_Clk, assign wtiS_operateD$D_IN = 1'b1 ; assign wtiS_operateD$EN = 1'd1 ; - // submodule dataBram_memory - assign dataBram_memory$ADDRA = dataCount[9:0] ; - assign dataBram_memory$ADDRB = wci_wslv_reqF$D_OUT[43:34] ; - assign dataBram_memory$DIA = wsiS_reqFifo$D_OUT[43:12] ; - assign dataBram_memory$DIB = 32'd0 ; - assign dataBram_memory$WEA = 1'd1 ; - assign dataBram_memory$WEB = 1'd0 ; - assign dataBram_memory$ENA = MUX_dataCount$write_1__SEL_2 ; - assign dataBram_memory$ENB = - WILL_FIRE_RL_dataBram_serverAdapterB_stageReadResponseAlways ; - - // submodule dataBram_serverAdapterA_outDataCore - assign dataBram_serverAdapterA_outDataCore$D_IN = dataBram_memory$DOA ; - assign dataBram_serverAdapterA_outDataCore$ENQ = - dataBram_serverAdapterA_outDataCore$FULL_N && - dataBram_serverAdapterA_outData_enqData$whas ; - assign dataBram_serverAdapterA_outDataCore$DEQ = 1'b0 ; - assign dataBram_serverAdapterA_outDataCore$CLR = 1'b0 ; - - // submodule dataBram_serverAdapterB_outDataCore - assign dataBram_serverAdapterB_outDataCore$D_IN = dataBram_memory$DOB ; - assign dataBram_serverAdapterB_outDataCore$ENQ = - WILL_FIRE_RL_dataBram_serverAdapterB_outData_enqAndDeq || - dataBram_serverAdapterB_outDataCore$FULL_N && - !dataBram_serverAdapterB_outData_deqCalled$whas && - dataBram_serverAdapterB_outData_enqData$whas ; - assign dataBram_serverAdapterB_outDataCore$DEQ = - WILL_FIRE_RL_dataBram_serverAdapterB_outData_enqAndDeq || - dataBram_serverAdapterB_outDataCore$EMPTY_N && - dataBram_serverAdapterB_outData_deqCalled$whas && - !dataBram_serverAdapterB_outData_enqData$whas ; - assign dataBram_serverAdapterB_outDataCore$CLR = 1'b0 ; - - // submodule metaBram_memory - assign metaBram_memory$ADDRA = metaCount[9:0] ; - assign metaBram_memory$ADDRB = wci_wslv_reqF$D_OUT[45:36] ; - assign metaBram_memory$DIA = { 18'd0, mlB__h23348 } ; - assign metaBram_memory$DIB = 32'd0 ; - assign metaBram_memory$WEA = 1'd1 ; - assign metaBram_memory$WEB = 1'd0 ; - assign metaBram_memory$ENA = MUX_metaCount$write_1__SEL_2 ; - assign metaBram_memory$ENB = - WILL_FIRE_RL_metaBram_serverAdapterB_stageReadResponseAlways ; - - // submodule metaBram_memory_1 - assign metaBram_memory_1$ADDRA = metaCount[9:0] ; - assign metaBram_memory_1$ADDRB = wci_wslv_reqF$D_OUT[45:36] ; - assign metaBram_memory_1$DIA = { 24'd0, wsiS_reqFifo$D_OUT[7:0] } ; - assign metaBram_memory_1$DIB = 32'd0 ; - assign metaBram_memory_1$WEA = 1'd1 ; - assign metaBram_memory_1$WEB = 1'd0 ; - assign metaBram_memory_1$ENA = MUX_metaCount$write_1__SEL_2 ; - assign metaBram_memory_1$ENB = - WILL_FIRE_RL_metaBram_serverAdapterB_1_stageReadResponseAlways ; - - // submodule metaBram_memory_2 - assign metaBram_memory_2$ADDRA = metaCount[9:0] ; - assign metaBram_memory_2$ADDRB = wci_wslv_reqF$D_OUT[45:36] ; - assign metaBram_memory_2$DIA = nowW$wget[63:32] ; - assign metaBram_memory_2$DIB = 32'd0 ; - assign metaBram_memory_2$WEA = 1'd1 ; - assign metaBram_memory_2$WEB = 1'd0 ; - assign metaBram_memory_2$ENA = MUX_metaCount$write_1__SEL_2 ; - assign metaBram_memory_2$ENB = - WILL_FIRE_RL_metaBram_serverAdapterB_2_stageReadResponseAlways ; - - // submodule metaBram_memory_3 - assign metaBram_memory_3$ADDRA = metaCount[9:0] ; - assign metaBram_memory_3$ADDRB = wci_wslv_reqF$D_OUT[45:36] ; - assign metaBram_memory_3$DIA = nowW$wget[31:0] ; - assign metaBram_memory_3$DIB = 32'd0 ; - assign metaBram_memory_3$WEA = 1'd1 ; - assign metaBram_memory_3$WEB = 1'd0 ; - assign metaBram_memory_3$ENA = MUX_metaCount$write_1__SEL_2 ; - assign metaBram_memory_3$ENB = - WILL_FIRE_RL_metaBram_serverAdapterB_3_stageReadResponseAlways ; - - // submodule metaBram_serverAdapterA_1_outDataCore - assign metaBram_serverAdapterA_1_outDataCore$D_IN = metaBram_memory_1$DOA ; - assign metaBram_serverAdapterA_1_outDataCore$ENQ = - metaBram_serverAdapterA_1_outDataCore$FULL_N && - metaBram_serverAdapterA_1_outData_enqData$whas ; - assign metaBram_serverAdapterA_1_outDataCore$DEQ = 1'b0 ; - assign metaBram_serverAdapterA_1_outDataCore$CLR = 1'b0 ; - - // submodule metaBram_serverAdapterA_2_outDataCore - assign metaBram_serverAdapterA_2_outDataCore$D_IN = metaBram_memory_2$DOA ; - assign metaBram_serverAdapterA_2_outDataCore$ENQ = - metaBram_serverAdapterA_2_outDataCore$FULL_N && - metaBram_serverAdapterA_2_outData_enqData$whas ; - assign metaBram_serverAdapterA_2_outDataCore$DEQ = 1'b0 ; - assign metaBram_serverAdapterA_2_outDataCore$CLR = 1'b0 ; - - // submodule metaBram_serverAdapterA_3_outDataCore - assign metaBram_serverAdapterA_3_outDataCore$D_IN = metaBram_memory_3$DOA ; - assign metaBram_serverAdapterA_3_outDataCore$ENQ = - metaBram_serverAdapterA_3_outDataCore$FULL_N && - metaBram_serverAdapterA_3_outData_enqData$whas ; - assign metaBram_serverAdapterA_3_outDataCore$DEQ = 1'b0 ; - assign metaBram_serverAdapterA_3_outDataCore$CLR = 1'b0 ; - - // submodule metaBram_serverAdapterA_outDataCore - assign metaBram_serverAdapterA_outDataCore$D_IN = metaBram_memory$DOA ; - assign metaBram_serverAdapterA_outDataCore$ENQ = - metaBram_serverAdapterA_outDataCore$FULL_N && - metaBram_serverAdapterA_outData_enqData$whas ; - assign metaBram_serverAdapterA_outDataCore$DEQ = 1'b0 ; - assign metaBram_serverAdapterA_outDataCore$CLR = 1'b0 ; - - // submodule metaBram_serverAdapterB_1_outDataCore - assign metaBram_serverAdapterB_1_outDataCore$D_IN = metaBram_memory_1$DOB ; - assign metaBram_serverAdapterB_1_outDataCore$ENQ = - WILL_FIRE_RL_metaBram_serverAdapterB_1_outData_enqAndDeq || - metaBram_serverAdapterB_1_outDataCore$FULL_N && - !metaBram_serverAdapterB_1_outData_deqCalled$whas && - metaBram_serverAdapterB_1_outData_enqData$whas ; - assign metaBram_serverAdapterB_1_outDataCore$DEQ = - WILL_FIRE_RL_metaBram_serverAdapterB_1_outData_enqAndDeq || - metaBram_serverAdapterB_1_outDataCore$EMPTY_N && - metaBram_serverAdapterB_1_outData_deqCalled$whas && - !metaBram_serverAdapterB_1_outData_enqData$whas ; - assign metaBram_serverAdapterB_1_outDataCore$CLR = 1'b0 ; - - // submodule metaBram_serverAdapterB_2_outDataCore - assign metaBram_serverAdapterB_2_outDataCore$D_IN = metaBram_memory_2$DOB ; - assign metaBram_serverAdapterB_2_outDataCore$ENQ = - WILL_FIRE_RL_metaBram_serverAdapterB_2_outData_enqAndDeq || - metaBram_serverAdapterB_2_outDataCore$FULL_N && - !metaBram_serverAdapterB_2_outData_deqCalled$whas && - metaBram_serverAdapterB_2_outData_enqData$whas ; - assign metaBram_serverAdapterB_2_outDataCore$DEQ = - WILL_FIRE_RL_metaBram_serverAdapterB_2_outData_enqAndDeq || - metaBram_serverAdapterB_2_outDataCore$EMPTY_N && - metaBram_serverAdapterB_2_outData_deqCalled$whas && - !metaBram_serverAdapterB_2_outData_enqData$whas ; - assign metaBram_serverAdapterB_2_outDataCore$CLR = 1'b0 ; - - // submodule metaBram_serverAdapterB_3_outDataCore - assign metaBram_serverAdapterB_3_outDataCore$D_IN = metaBram_memory_3$DOB ; - assign metaBram_serverAdapterB_3_outDataCore$ENQ = - WILL_FIRE_RL_metaBram_serverAdapterB_3_outData_enqAndDeq || - metaBram_serverAdapterB_3_outDataCore$FULL_N && - !metaBram_serverAdapterB_3_outData_deqCalled$whas && - metaBram_serverAdapterB_3_outData_enqData$whas ; - assign metaBram_serverAdapterB_3_outDataCore$DEQ = - WILL_FIRE_RL_metaBram_serverAdapterB_3_outData_enqAndDeq || - metaBram_serverAdapterB_3_outDataCore$EMPTY_N && - metaBram_serverAdapterB_3_outData_deqCalled$whas && - !metaBram_serverAdapterB_3_outData_enqData$whas ; - assign metaBram_serverAdapterB_3_outDataCore$CLR = 1'b0 ; - - // submodule metaBram_serverAdapterB_outDataCore - assign metaBram_serverAdapterB_outDataCore$D_IN = metaBram_memory$DOB ; - assign metaBram_serverAdapterB_outDataCore$ENQ = - WILL_FIRE_RL_metaBram_serverAdapterB_outData_enqAndDeq || - metaBram_serverAdapterB_outDataCore$FULL_N && - !metaBram_serverAdapterB_outData_deqCalled$whas && - metaBram_serverAdapterB_outData_enqData$whas ; - assign metaBram_serverAdapterB_outDataCore$DEQ = - WILL_FIRE_RL_metaBram_serverAdapterB_outData_enqAndDeq || - metaBram_serverAdapterB_outDataCore$EMPTY_N && - metaBram_serverAdapterB_outData_deqCalled$whas && - !metaBram_serverAdapterB_outData_enqData$whas ; - assign metaBram_serverAdapterB_outDataCore$CLR = 1'b0 ; + // submodule dataBram_0_memory + assign dataBram_0_memory$ADDRA = dataCount[9:0] ; + assign dataBram_0_memory$ADDRB = wci_wslv_reqF$D_OUT[43:34] ; + assign dataBram_0_memory$DIA = wsiS_reqFifo$D_OUT[43:12] ; + assign dataBram_0_memory$DIB = 32'd0 ; + assign dataBram_0_memory$WEA = 1'd1 ; + assign dataBram_0_memory$WEB = 1'd0 ; + assign dataBram_0_memory$ENA = MUX_dataCount$write_1__SEL_2 ; + assign dataBram_0_memory$ENB = + WILL_FIRE_RL_dataBram_0_serverAdapterB_stageReadResponseAlways ; + + // submodule dataBram_0_serverAdapterA_outDataCore + assign dataBram_0_serverAdapterA_outDataCore$D_IN = dataBram_0_memory$DOA ; + assign dataBram_0_serverAdapterA_outDataCore$ENQ = + dataBram_0_serverAdapterA_outDataCore$FULL_N && + dataBram_0_serverAdapterA_outData_enqData$whas ; + assign dataBram_0_serverAdapterA_outDataCore$DEQ = 1'b0 ; + assign dataBram_0_serverAdapterA_outDataCore$CLR = 1'b0 ; + + // submodule dataBram_0_serverAdapterB_outDataCore + assign dataBram_0_serverAdapterB_outDataCore$D_IN = dataBram_0_memory$DOB ; + assign dataBram_0_serverAdapterB_outDataCore$ENQ = + WILL_FIRE_RL_dataBram_0_serverAdapterB_outData_enqAndDeq || + dataBram_0_serverAdapterB_outDataCore$FULL_N && + !dataBram_0_serverAdapterB_outData_deqCalled$whas && + dataBram_0_serverAdapterB_outData_enqData$whas ; + assign dataBram_0_serverAdapterB_outDataCore$DEQ = + WILL_FIRE_RL_dataBram_0_serverAdapterB_outData_enqAndDeq || + dataBram_0_serverAdapterB_outDataCore$EMPTY_N && + dataBram_0_serverAdapterB_outData_deqCalled$whas && + !dataBram_0_serverAdapterB_outData_enqData$whas ; + assign dataBram_0_serverAdapterB_outDataCore$CLR = 1'b0 ; + + // submodule metaBram_0_memory + assign metaBram_0_memory$ADDRA = metaCount[9:0] ; + assign metaBram_0_memory$ADDRB = wci_wslv_reqF$D_OUT[45:36] ; + assign metaBram_0_memory$DIA = { 18'd0, mlB__h23202 } ; + assign metaBram_0_memory$DIB = 32'd0 ; + assign metaBram_0_memory$WEA = 1'd1 ; + assign metaBram_0_memory$WEB = 1'd0 ; + assign metaBram_0_memory$ENA = MUX_metaCount$write_1__SEL_2 ; + assign metaBram_0_memory$ENB = + WILL_FIRE_RL_metaBram_0_serverAdapterB_stageReadResponseAlways ; + + // submodule metaBram_0_serverAdapterA_outDataCore + assign metaBram_0_serverAdapterA_outDataCore$D_IN = metaBram_0_memory$DOA ; + assign metaBram_0_serverAdapterA_outDataCore$ENQ = + metaBram_0_serverAdapterA_outDataCore$FULL_N && + metaBram_0_serverAdapterA_outData_enqData$whas ; + assign metaBram_0_serverAdapterA_outDataCore$DEQ = 1'b0 ; + assign metaBram_0_serverAdapterA_outDataCore$CLR = 1'b0 ; + + // submodule metaBram_0_serverAdapterB_outDataCore + assign metaBram_0_serverAdapterB_outDataCore$D_IN = metaBram_0_memory$DOB ; + assign metaBram_0_serverAdapterB_outDataCore$ENQ = + WILL_FIRE_RL_metaBram_0_serverAdapterB_outData_enqAndDeq || + metaBram_0_serverAdapterB_outDataCore$FULL_N && + !metaBram_0_serverAdapterB_outData_deqCalled$whas && + metaBram_0_serverAdapterB_outData_enqData$whas ; + assign metaBram_0_serverAdapterB_outDataCore$DEQ = + WILL_FIRE_RL_metaBram_0_serverAdapterB_outData_enqAndDeq || + metaBram_0_serverAdapterB_outDataCore$EMPTY_N && + metaBram_0_serverAdapterB_outData_deqCalled$whas && + !metaBram_0_serverAdapterB_outData_enqData$whas ; + assign metaBram_0_serverAdapterB_outDataCore$CLR = 1'b0 ; + + // submodule metaBram_1_memory + assign metaBram_1_memory$ADDRA = metaCount[9:0] ; + assign metaBram_1_memory$ADDRB = wci_wslv_reqF$D_OUT[45:36] ; + assign metaBram_1_memory$DIA = { 24'd0, wsiS_reqFifo$D_OUT[7:0] } ; + assign metaBram_1_memory$DIB = 32'd0 ; + assign metaBram_1_memory$WEA = 1'd1 ; + assign metaBram_1_memory$WEB = 1'd0 ; + assign metaBram_1_memory$ENA = MUX_metaCount$write_1__SEL_2 ; + assign metaBram_1_memory$ENB = + WILL_FIRE_RL_metaBram_1_serverAdapterB_stageReadResponseAlways ; + + // submodule metaBram_1_serverAdapterA_outDataCore + assign metaBram_1_serverAdapterA_outDataCore$D_IN = metaBram_1_memory$DOA ; + assign metaBram_1_serverAdapterA_outDataCore$ENQ = + metaBram_1_serverAdapterA_outDataCore$FULL_N && + metaBram_1_serverAdapterA_outData_enqData$whas ; + assign metaBram_1_serverAdapterA_outDataCore$DEQ = 1'b0 ; + assign metaBram_1_serverAdapterA_outDataCore$CLR = 1'b0 ; + + // submodule metaBram_1_serverAdapterB_outDataCore + assign metaBram_1_serverAdapterB_outDataCore$D_IN = metaBram_1_memory$DOB ; + assign metaBram_1_serverAdapterB_outDataCore$ENQ = + WILL_FIRE_RL_metaBram_1_serverAdapterB_outData_enqAndDeq || + metaBram_1_serverAdapterB_outDataCore$FULL_N && + !metaBram_1_serverAdapterB_cnt_2$whas && + metaBram_1_serverAdapterB_outData_enqData$whas ; + assign metaBram_1_serverAdapterB_outDataCore$DEQ = + WILL_FIRE_RL_metaBram_1_serverAdapterB_outData_enqAndDeq || + metaBram_1_serverAdapterB_outDataCore$EMPTY_N && + metaBram_1_serverAdapterB_cnt_2$whas && + !metaBram_1_serverAdapterB_outData_enqData$whas ; + assign metaBram_1_serverAdapterB_outDataCore$CLR = 1'b0 ; + + // submodule metaBram_2_memory + assign metaBram_2_memory$ADDRA = metaCount[9:0] ; + assign metaBram_2_memory$ADDRB = wci_wslv_reqF$D_OUT[45:36] ; + assign metaBram_2_memory$DIA = nowW$wget[63:32] ; + assign metaBram_2_memory$DIB = 32'd0 ; + assign metaBram_2_memory$WEA = 1'd1 ; + assign metaBram_2_memory$WEB = 1'd0 ; + assign metaBram_2_memory$ENA = MUX_metaCount$write_1__SEL_2 ; + assign metaBram_2_memory$ENB = + WILL_FIRE_RL_metaBram_2_serverAdapterB_stageReadResponseAlways ; + + // submodule metaBram_2_serverAdapterA_outDataCore + assign metaBram_2_serverAdapterA_outDataCore$D_IN = metaBram_2_memory$DOA ; + assign metaBram_2_serverAdapterA_outDataCore$ENQ = + metaBram_2_serverAdapterA_outDataCore$FULL_N && + metaBram_2_serverAdapterA_outData_enqData$whas ; + assign metaBram_2_serverAdapterA_outDataCore$DEQ = 1'b0 ; + assign metaBram_2_serverAdapterA_outDataCore$CLR = 1'b0 ; + + // submodule metaBram_2_serverAdapterB_outDataCore + assign metaBram_2_serverAdapterB_outDataCore$D_IN = metaBram_2_memory$DOB ; + assign metaBram_2_serverAdapterB_outDataCore$ENQ = + WILL_FIRE_RL_metaBram_2_serverAdapterB_outData_enqAndDeq || + metaBram_2_serverAdapterB_outDataCore$FULL_N && + !metaBram_2_serverAdapterB_outData_deqCalled$whas && + metaBram_2_serverAdapterB_outData_enqData$whas ; + assign metaBram_2_serverAdapterB_outDataCore$DEQ = + WILL_FIRE_RL_metaBram_2_serverAdapterB_outData_enqAndDeq || + metaBram_2_serverAdapterB_outDataCore$EMPTY_N && + metaBram_2_serverAdapterB_outData_deqCalled$whas && + !metaBram_2_serverAdapterB_outData_enqData$whas ; + assign metaBram_2_serverAdapterB_outDataCore$CLR = 1'b0 ; + + // submodule metaBram_3_memory + assign metaBram_3_memory$ADDRA = metaCount[9:0] ; + assign metaBram_3_memory$ADDRB = wci_wslv_reqF$D_OUT[45:36] ; + assign metaBram_3_memory$DIA = nowW$wget[31:0] ; + assign metaBram_3_memory$DIB = 32'd0 ; + assign metaBram_3_memory$WEA = 1'd1 ; + assign metaBram_3_memory$WEB = 1'd0 ; + assign metaBram_3_memory$ENA = MUX_metaCount$write_1__SEL_2 ; + assign metaBram_3_memory$ENB = + WILL_FIRE_RL_metaBram_3_serverAdapterB_stageReadResponseAlways ; + + // submodule metaBram_3_serverAdapterA_outDataCore + assign metaBram_3_serverAdapterA_outDataCore$D_IN = metaBram_3_memory$DOA ; + assign metaBram_3_serverAdapterA_outDataCore$ENQ = + metaBram_3_serverAdapterA_outDataCore$FULL_N && + metaBram_3_serverAdapterA_outData_enqData$whas ; + assign metaBram_3_serverAdapterA_outDataCore$DEQ = 1'b0 ; + assign metaBram_3_serverAdapterA_outDataCore$CLR = 1'b0 ; + + // submodule metaBram_3_serverAdapterB_outDataCore + assign metaBram_3_serverAdapterB_outDataCore$D_IN = metaBram_3_memory$DOB ; + assign metaBram_3_serverAdapterB_outDataCore$ENQ = + WILL_FIRE_RL_metaBram_3_serverAdapterB_outData_enqAndDeq || + metaBram_3_serverAdapterB_outDataCore$FULL_N && + !metaBram_3_serverAdapterB_outData_deqCalled$whas && + metaBram_3_serverAdapterB_outData_enqData$whas ; + assign metaBram_3_serverAdapterB_outDataCore$DEQ = + WILL_FIRE_RL_metaBram_3_serverAdapterB_outData_enqAndDeq || + metaBram_3_serverAdapterB_outDataCore$EMPTY_N && + metaBram_3_serverAdapterB_outData_deqCalled$whas && + !metaBram_3_serverAdapterB_outData_enqData$whas ; + assign metaBram_3_serverAdapterB_outDataCore$CLR = 1'b0 ; // submodule splaF assign splaF$D_IN = @@ -2420,247 +2435,250 @@ module mkWSICaptureWorker4B(wciS0_Clk, assign wsiS_reqFifo$CLR = 1'b0 ; // remaining internal signals - assign IF_splaF_first__97_BITS_1_TO_0_99_EQ_0_00_THEN_ETC___d927 = - IF_splaF_first__97_BITS_1_TO_0_99_EQ_0_00_THEN_ETC___d918 && - CASE_splaFD_OUT_BITS_1_TO_0_NOT_splaFD_OUT_B_ETC__q1 ; - assign NOT_controlReg_30_BIT_0_31_32_OR_controlReg_30_ETC___d856 = + assign IF_splaF_first__95_BIT_2_96_THEN_NOT_splaF_fir_ETC___d916 = + splaF$D_OUT[2] ? + (splaF$D_OUT[1:0] != 2'd0 || + dataBram_0_serverAdapterB_outDataCore$EMPTY_N || + dataBram_0_serverAdapterB_outData_enqData$whas) && + (splaF$D_OUT[1:0] != 2'd0 || + dataBram_0_serverAdapterB_outData_outData$whas) : + CASE_splaF_first__95_BITS_1_TO_0_97_0_metaBram_ETC___d909 && + CASE_splaF_first__95_BITS_1_TO_0_97_0_metaBram_ETC___d914 ; + assign NOT_controlReg_28_BIT_0_29_30_OR_controlReg_28_ETC___d854 = !controlReg[0] || controlReg[1] && - (!metaCount_34_ULT_1024___d1204 || - !dataCount_37_ULT_1024___d1205) || - (dataBram_serverAdapterA_cnt ^ 3'h4) < 3'd7 && + (!metaCount_32_ULT_1024___d833 || + !dataCount_35_ULT_1024___d836) || + (dataBram_0_serverAdapterA_cnt ^ 3'h4) < 3'd7 && (!wsiS_reqFifo$D_OUT[57] || - (metaBram_serverAdapterA_cnt ^ 3'h4) < 3'd7 && - (metaBram_serverAdapterA_1_cnt ^ 3'h4) < 3'd7 && - (metaBram_serverAdapterA_2_cnt ^ 3'h4) < 3'd7 && - (metaBram_serverAdapterA_3_cnt ^ 3'h4) < 3'd7) ; - assign controlReg_30_BIT_0_31_AND_NOT_controlReg_30_B_ETC___d878 = + (metaBram_0_serverAdapterA_cnt ^ 3'h4) < 3'd7 && + (metaBram_1_serverAdapterA_cnt ^ 3'h4) < 3'd7 && + (metaBram_2_serverAdapterA_cnt ^ 3'h4) < 3'd7 && + (metaBram_3_serverAdapterA_cnt ^ 3'h4) < 3'd7) ; + assign _dfoo1 = + wci_wslv_respF_cntr_r != 2'd2 || + wci_wslv_respF_cntr_r_8_MINUS_1___d27 == 2'd1 ; + assign _dfoo3 = + wci_wslv_respF_cntr_r != 2'd1 || + wci_wslv_respF_cntr_r_8_MINUS_1___d27 == 2'd0 ; + assign controlReg_28_BIT_0_29_AND_NOT_controlReg_28_B_ETC___d876 = controlReg[0] && (!controlReg[1] || - metaCount_34_ULT_1024___d1204 && - dataCount_37_ULT_1024___d1205) ; - assign dataBram_serverAdapterB_cnt_21_PLUS_IF_dataBra_ETC___d327 = - dataBram_serverAdapterB_cnt + - (WILL_FIRE_RL_dataBram_serverAdapterB_stageReadResponseAlways ? - 3'd1 : - 3'd0) + - (dataBram_serverAdapterB_outData_deqCalled$whas ? 3'd7 : 3'd0) ; - assign dataCount_37_ULT_1024___d1205 = dataCount < 32'd1024 ; - assign g_data__h28071 = - (wci_wslv_reqF$D_OUT[63:52] == 12'h0) ? v__h26981 : 32'd0 ; - assign metaBram_serverAdapterB_1_cnt_57_PLUS_IF_metaB_ETC___d563 = - metaBram_serverAdapterB_1_cnt + - (WILL_FIRE_RL_metaBram_serverAdapterB_1_stageReadResponseAlways ? + metaCount_32_ULT_1024___d833 && dataCount_35_ULT_1024___d836) ; + assign dataBram_0_serverAdapterB_cnt_19_PLUS_IF_dataB_ETC___d325 = + dataBram_0_serverAdapterB_cnt + + (WILL_FIRE_RL_dataBram_0_serverAdapterB_stageReadResponseAlways ? 3'd1 : 3'd0) + - (metaBram_serverAdapterB_1_outData_deqCalled$whas ? + (dataBram_0_serverAdapterB_outData_deqCalled$whas ? 3'd7 : 3'd0) ; - assign metaBram_serverAdapterB_2_cnt_75_PLUS_IF_metaB_ETC___d681 = - metaBram_serverAdapterB_2_cnt + - (WILL_FIRE_RL_metaBram_serverAdapterB_2_stageReadResponseAlways ? + assign dataCount_35_ULT_1024___d836 = dataCount < 32'd1024 ; + assign g_data__h27820 = + (wci_wslv_reqF$D_OUT[63:52] == 12'h0) ? v__h26736 : 32'd0 ; + assign metaBram_0_serverAdapterB_cnt_37_PLUS_IF_metaB_ETC___d443 = + metaBram_0_serverAdapterB_cnt + + (WILL_FIRE_RL_metaBram_0_serverAdapterB_stageReadResponseAlways ? 3'd1 : 3'd0) + - (metaBram_serverAdapterB_2_outData_deqCalled$whas ? + (metaBram_0_serverAdapterB_outData_deqCalled$whas ? 3'd7 : 3'd0) ; - assign metaBram_serverAdapterB_3_cnt_93_PLUS_IF_metaB_ETC___d799 = - metaBram_serverAdapterB_3_cnt + - (WILL_FIRE_RL_metaBram_serverAdapterB_3_stageReadResponseAlways ? + assign metaBram_1_serverAdapterB_cnt_55_PLUS_IF_metaB_ETC___d561 = + metaBram_1_serverAdapterB_cnt + + (WILL_FIRE_RL_metaBram_1_serverAdapterB_stageReadResponseAlways ? 3'd1 : 3'd0) + - (metaBram_serverAdapterB_3_outData_deqCalled$whas ? + (metaBram_1_serverAdapterB_cnt_2$whas ? 3'd7 : 3'd0) ; + assign metaBram_2_serverAdapterB_cnt_73_PLUS_IF_metaB_ETC___d679 = + metaBram_2_serverAdapterB_cnt + + (WILL_FIRE_RL_metaBram_2_serverAdapterB_stageReadResponseAlways ? + 3'd1 : + 3'd0) + + (metaBram_2_serverAdapterB_outData_deqCalled$whas ? 3'd7 : 3'd0) ; - assign metaBram_serverAdapterB_cnt_39_PLUS_IF_metaBra_ETC___d445 = - metaBram_serverAdapterB_cnt + - (WILL_FIRE_RL_metaBram_serverAdapterB_stageReadResponseAlways ? + assign metaBram_3_serverAdapterB_cnt_91_PLUS_IF_metaB_ETC___d797 = + metaBram_3_serverAdapterB_cnt + + (WILL_FIRE_RL_metaBram_3_serverAdapterB_stageReadResponseAlways ? 3'd1 : 3'd0) + - (metaBram_serverAdapterB_outData_deqCalled$whas ? 3'd7 : 3'd0) ; - assign metaCount_34_ULT_1024___d1204 = metaCount < 32'd1024 ; - assign mlB__h23348 = mesgLengthSoFar + mlInc__h23347 ; - assign mlInc__h23347 = + (metaBram_3_serverAdapterB_outData_deqCalled$whas ? + 3'd7 : + 3'd0) ; + assign metaCount_32_ULT_1024___d833 = metaCount < 32'd1024 ; + assign mlB__h23202 = mesgLengthSoFar + mlInc__h23201 ; + assign mlInc__h23201 = wsiS_reqFifo$D_OUT[57] ? - { 11'd0, x__h23396 + y__h23397 } : + { 11'd0, x__h23250 + y__h23251 } : 14'd4 ; - assign rdat___1__h27078 = + assign rdat___1__h26833 = { 6'd40, - !metaCount_34_ULT_1024___d1204, - !dataCount_37_ULT_1024___d1205, + !metaCount_32_ULT_1024___d833, + !dataCount_35_ULT_1024___d836, 24'd2361866 } ; - assign rdat___1__h27162 = hasDebugLogic ? { 24'd0, wsiS_statusR } : 32'd0 ; - assign rdat___1__h27217 = + assign rdat___1__h26917 = hasDebugLogic ? { 24'd0, wsiS_statusR } : 32'd0 ; + assign rdat___1__h26972 = hasDebugLogic ? wsiS_extStatusW$wget[95:64] : 32'd0 ; - assign rdat___1__h27231 = + assign rdat___1__h26986 = hasDebugLogic ? wsiS_extStatusW$wget[63:32] : 32'd0 ; - assign rdat___1__h27239 = + assign rdat___1__h26994 = hasDebugLogic ? wsiS_extStatusW$wget[31:0] : 32'd0 ; - assign splaF_i_notEmpty__96_AND_IF_splaF_first__97_BI_ETC___d929 = - splaF$EMPTY_N && - (splaF$D_OUT[2] ? - (splaF$D_OUT[1:0] != 2'd0 || - dataBram_serverAdapterB_outDataCore$EMPTY_N || - dataBram_serverAdapterB_outData_enqData$whas) && - (splaF$D_OUT[1:0] != 2'd0 || - dataBram_serverAdapterB_outData_outData$whas) : - IF_splaF_first__97_BITS_1_TO_0_99_EQ_0_00_THEN_ETC___d927) ; - assign v__h25581 = + assign v__h25458 = splaF$D_OUT[2] ? - y_avValue__h26208 : - IF_splaF_first__97_BITS_1_TO_0_99_EQ_0_00_THEN_ETC___d951 ; - assign x__h23396 = x__h23408 + y__h23409 ; - assign x__h23408 = x__h23420 + y__h23421 ; - assign x__h23420 = { 2'd0, wsiS_reqFifo$D_OUT[11] } ; - assign y__h23397 = { 2'd0, wsiS_reqFifo$D_OUT[8] } ; - assign y__h23409 = { 2'd0, wsiS_reqFifo$D_OUT[9] } ; - assign y__h23421 = { 2'd0, wsiS_reqFifo$D_OUT[10] } ; - assign y_avValue__h26208 = - dataBram_serverAdapterB_outDataCore$EMPTY_N ? - dataBram_serverAdapterB_outDataCore$D_OUT : - dataBram_memory$DOB ; - assign y_avValue__h26252 = - metaBram_serverAdapterB_outDataCore$EMPTY_N ? - metaBram_serverAdapterB_outDataCore$D_OUT : - metaBram_memory$DOB ; - assign y_avValue__h26292 = - metaBram_serverAdapterB_1_outDataCore$EMPTY_N ? - metaBram_serverAdapterB_1_outDataCore$D_OUT : - metaBram_memory_1$DOB ; - assign y_avValue__h26332 = - metaBram_serverAdapterB_2_outDataCore$EMPTY_N ? - metaBram_serverAdapterB_2_outDataCore$D_OUT : - metaBram_memory_2$DOB ; - assign y_avValue__h26372 = - metaBram_serverAdapterB_3_outDataCore$EMPTY_N ? - metaBram_serverAdapterB_3_outDataCore$D_OUT : - metaBram_memory_3$DOB ; + y_avValue__h25982 : + SEL_ARR_metaBram_0_serverAdapterB_outData_outD_ETC___d940 ; + assign wci_wslv_respF_cntr_r_8_MINUS_1___d27 = + wci_wslv_respF_cntr_r - 2'd1 ; + assign x__h23250 = x__h23262 + y__h23263 ; + assign x__h23262 = x__h23274 + y__h23275 ; + assign x__h23274 = { 2'd0, wsiS_reqFifo$D_OUT[11] } ; + assign y__h23251 = { 2'd0, wsiS_reqFifo$D_OUT[8] } ; + assign y__h23263 = { 2'd0, wsiS_reqFifo$D_OUT[9] } ; + assign y__h23275 = { 2'd0, wsiS_reqFifo$D_OUT[10] } ; + assign y_avValue__h25982 = + dataBram_0_serverAdapterB_outDataCore$EMPTY_N ? + dataBram_0_serverAdapterB_outDataCore$D_OUT : + dataBram_0_memory$DOB ; + assign y_avValue__h26025 = + metaBram_0_serverAdapterB_outDataCore$EMPTY_N ? + metaBram_0_serverAdapterB_outDataCore$D_OUT : + metaBram_0_memory$DOB ; + assign y_avValue__h26065 = + metaBram_1_serverAdapterB_outDataCore$EMPTY_N ? + metaBram_1_serverAdapterB_outDataCore$D_OUT : + metaBram_1_memory$DOB ; + assign y_avValue__h26105 = + metaBram_2_serverAdapterB_outDataCore$EMPTY_N ? + metaBram_2_serverAdapterB_outDataCore$D_OUT : + metaBram_2_memory$DOB ; + assign y_avValue__h26145 = + metaBram_3_serverAdapterB_outDataCore$EMPTY_N ? + metaBram_3_serverAdapterB_outDataCore$D_OUT : + metaBram_3_memory$DOB ; always@(wci_wslv_reqF$D_OUT or - metaBram_serverAdapterB_3_cnt or - metaBram_serverAdapterB_cnt or - metaBram_serverAdapterB_1_cnt or metaBram_serverAdapterB_2_cnt) + controlReg or + metaCount or + dataCount or + rdat___1__h26833 or + rdat___1__h26917 or + rdat___1__h26972 or rdat___1__h26986 or rdat___1__h26994) + begin + case (wci_wslv_reqF$D_OUT[39:32]) + 8'h0: v__h26736 = controlReg; + 8'h04: v__h26736 = metaCount; + 8'h08: v__h26736 = dataCount; + 8'h0C: v__h26736 = rdat___1__h26833; + 8'h10: v__h26736 = rdat___1__h26917; + 8'h14: v__h26736 = rdat___1__h26972; + 8'h18: v__h26736 = rdat___1__h26986; + 8'h1C: v__h26736 = rdat___1__h26994; + default: v__h26736 = 32'd0; + endcase + end + always@(wci_wslv_reqF$D_OUT or + metaBram_0_serverAdapterB_cnt or + metaBram_1_serverAdapterB_cnt or + metaBram_2_serverAdapterB_cnt or metaBram_3_serverAdapterB_cnt) begin case (wci_wslv_reqF$D_OUT[35:34]) 2'd0: - IF_wci_wslv_reqF_first__5_BITS_35_TO_34_81_EQ__ETC___d994 = - (metaBram_serverAdapterB_cnt ^ 3'h4) < 3'd7; + CASE_wci_wslv_reqF_first__3_BITS_35_TO_34_70_0_ETC___d975 = + (metaBram_0_serverAdapterB_cnt ^ 3'h4) < 3'd7; 2'd1: - IF_wci_wslv_reqF_first__5_BITS_35_TO_34_81_EQ__ETC___d994 = - (metaBram_serverAdapterB_1_cnt ^ 3'h4) < 3'd7; + CASE_wci_wslv_reqF_first__3_BITS_35_TO_34_70_0_ETC___d975 = + (metaBram_1_serverAdapterB_cnt ^ 3'h4) < 3'd7; 2'd2: - IF_wci_wslv_reqF_first__5_BITS_35_TO_34_81_EQ__ETC___d994 = - (metaBram_serverAdapterB_2_cnt ^ 3'h4) < 3'd7; + CASE_wci_wslv_reqF_first__3_BITS_35_TO_34_70_0_ETC___d975 = + (metaBram_2_serverAdapterB_cnt ^ 3'h4) < 3'd7; 2'd3: - IF_wci_wslv_reqF_first__5_BITS_35_TO_34_81_EQ__ETC___d994 = - wci_wslv_reqF$D_OUT[35:34] != 2'd3 || - (metaBram_serverAdapterB_3_cnt ^ 3'h4) < 3'd7; + CASE_wci_wslv_reqF_first__3_BITS_35_TO_34_70_0_ETC___d975 = + (metaBram_3_serverAdapterB_cnt ^ 3'h4) < 3'd7; endcase end always@(wci_wslv_reqF$D_OUT or splaF$FULL_N or - IF_wci_wslv_reqF_first__5_BITS_35_TO_34_81_EQ__ETC___d994 or - dataBram_serverAdapterB_cnt) + CASE_wci_wslv_reqF_first__3_BITS_35_TO_34_70_0_ETC___d975 or + dataBram_0_serverAdapterB_cnt) begin case (wci_wslv_reqF$D_OUT[63:52]) - 12'h0: IF_wci_wslv_reqF_first__5_BITS_63_TO_52_65_EQ__ETC___d998 = 1'b1; + 12'h0: IF_wci_wslv_reqF_first__3_BITS_63_TO_52_54_EQ__ETC___d979 = 1'b1; 12'h800: - IF_wci_wslv_reqF_first__5_BITS_63_TO_52_65_EQ__ETC___d998 = - (dataBram_serverAdapterB_cnt ^ 3'h4) < 3'd7 && splaF$FULL_N; - default: IF_wci_wslv_reqF_first__5_BITS_63_TO_52_65_EQ__ETC___d998 = + IF_wci_wslv_reqF_first__3_BITS_63_TO_52_54_EQ__ETC___d979 = + (dataBram_0_serverAdapterB_cnt ^ 3'h4) < 3'd7 && splaF$FULL_N; + default: IF_wci_wslv_reqF_first__3_BITS_63_TO_52_54_EQ__ETC___d979 = wci_wslv_reqF$D_OUT[63:52] != 12'h400 || splaF$FULL_N && - IF_wci_wslv_reqF_first__5_BITS_35_TO_34_81_EQ__ETC___d994; + CASE_wci_wslv_reqF_first__3_BITS_35_TO_34_70_0_ETC___d975; endcase end always@(splaF$D_OUT or - y_avValue__h26372 or - y_avValue__h26252 or y_avValue__h26292 or y_avValue__h26332) + y_avValue__h26025 or + y_avValue__h26065 or y_avValue__h26105 or y_avValue__h26145) begin case (splaF$D_OUT[1:0]) 2'd0: - IF_splaF_first__97_BITS_1_TO_0_99_EQ_0_00_THEN_ETC___d951 = - y_avValue__h26252; + SEL_ARR_metaBram_0_serverAdapterB_outData_outD_ETC___d940 = + y_avValue__h26025; 2'd1: - IF_splaF_first__97_BITS_1_TO_0_99_EQ_0_00_THEN_ETC___d951 = - y_avValue__h26292; + SEL_ARR_metaBram_0_serverAdapterB_outData_outD_ETC___d940 = + y_avValue__h26065; 2'd2: - IF_splaF_first__97_BITS_1_TO_0_99_EQ_0_00_THEN_ETC___d951 = - y_avValue__h26332; + SEL_ARR_metaBram_0_serverAdapterB_outData_outD_ETC___d940 = + y_avValue__h26105; 2'd3: - IF_splaF_first__97_BITS_1_TO_0_99_EQ_0_00_THEN_ETC___d951 = - y_avValue__h26372; - endcase - end - always@(wci_wslv_reqF$D_OUT or - controlReg or - metaCount or - dataCount or - rdat___1__h27078 or - rdat___1__h27162 or - rdat___1__h27217 or rdat___1__h27231 or rdat___1__h27239) - begin - case (wci_wslv_reqF$D_OUT[39:32]) - 8'h0: v__h26981 = controlReg; - 8'h04: v__h26981 = metaCount; - 8'h08: v__h26981 = dataCount; - 8'h0C: v__h26981 = rdat___1__h27078; - 8'h10: v__h26981 = rdat___1__h27162; - 8'h14: v__h26981 = rdat___1__h27217; - 8'h18: v__h26981 = rdat___1__h27231; - 8'h1C: v__h26981 = rdat___1__h27239; - default: v__h26981 = 32'd0; + SEL_ARR_metaBram_0_serverAdapterB_outData_outD_ETC___d940 = + y_avValue__h26145; endcase end always@(splaF$D_OUT or - metaBram_serverAdapterB_3_outDataCore$EMPTY_N or - metaBram_serverAdapterB_3_outData_enqData$whas or - metaBram_serverAdapterB_outDataCore$EMPTY_N or - metaBram_serverAdapterB_outData_enqData$whas or - metaBram_serverAdapterB_1_outDataCore$EMPTY_N or - metaBram_serverAdapterB_1_outData_enqData$whas or - metaBram_serverAdapterB_2_outDataCore$EMPTY_N or - metaBram_serverAdapterB_2_outData_enqData$whas) + metaBram_0_serverAdapterB_outDataCore$EMPTY_N or + metaBram_0_serverAdapterB_outData_enqData$whas or + metaBram_1_serverAdapterB_outDataCore$EMPTY_N or + metaBram_1_serverAdapterB_outData_enqData$whas or + metaBram_2_serverAdapterB_outDataCore$EMPTY_N or + metaBram_2_serverAdapterB_outData_enqData$whas or + metaBram_3_serverAdapterB_outDataCore$EMPTY_N or + metaBram_3_serverAdapterB_outData_enqData$whas) begin case (splaF$D_OUT[1:0]) 2'd0: - IF_splaF_first__97_BITS_1_TO_0_99_EQ_0_00_THEN_ETC___d918 = - metaBram_serverAdapterB_outDataCore$EMPTY_N || - metaBram_serverAdapterB_outData_enqData$whas; + CASE_splaF_first__95_BITS_1_TO_0_97_0_metaBram_ETC___d909 = + metaBram_0_serverAdapterB_outDataCore$EMPTY_N || + metaBram_0_serverAdapterB_outData_enqData$whas; 2'd1: - IF_splaF_first__97_BITS_1_TO_0_99_EQ_0_00_THEN_ETC___d918 = - metaBram_serverAdapterB_1_outDataCore$EMPTY_N || - metaBram_serverAdapterB_1_outData_enqData$whas; + CASE_splaF_first__95_BITS_1_TO_0_97_0_metaBram_ETC___d909 = + metaBram_1_serverAdapterB_outDataCore$EMPTY_N || + metaBram_1_serverAdapterB_outData_enqData$whas; 2'd2: - IF_splaF_first__97_BITS_1_TO_0_99_EQ_0_00_THEN_ETC___d918 = - metaBram_serverAdapterB_2_outDataCore$EMPTY_N || - metaBram_serverAdapterB_2_outData_enqData$whas; + CASE_splaF_first__95_BITS_1_TO_0_97_0_metaBram_ETC___d909 = + metaBram_2_serverAdapterB_outDataCore$EMPTY_N || + metaBram_2_serverAdapterB_outData_enqData$whas; 2'd3: - IF_splaF_first__97_BITS_1_TO_0_99_EQ_0_00_THEN_ETC___d918 = - splaF$D_OUT[1:0] != 2'd3 || - metaBram_serverAdapterB_3_outDataCore$EMPTY_N || - metaBram_serverAdapterB_3_outData_enqData$whas; + CASE_splaF_first__95_BITS_1_TO_0_97_0_metaBram_ETC___d909 = + metaBram_3_serverAdapterB_outDataCore$EMPTY_N || + metaBram_3_serverAdapterB_outData_enqData$whas; endcase end always@(splaF$D_OUT or - metaBram_serverAdapterB_3_outData_outData$whas or - metaBram_serverAdapterB_outData_outData$whas or - metaBram_serverAdapterB_1_outData_outData$whas or - metaBram_serverAdapterB_2_outData_outData$whas) + metaBram_0_serverAdapterB_outData_outData$whas or + metaBram_1_serverAdapterB_outData_outData$whas or + metaBram_2_serverAdapterB_outData_outData$whas or + metaBram_3_serverAdapterB_outData_outData$whas) begin case (splaF$D_OUT[1:0]) 2'd0: - CASE_splaFD_OUT_BITS_1_TO_0_NOT_splaFD_OUT_B_ETC__q1 = - metaBram_serverAdapterB_outData_outData$whas; + CASE_splaF_first__95_BITS_1_TO_0_97_0_metaBram_ETC___d914 = + metaBram_0_serverAdapterB_outData_outData$whas; 2'd1: - CASE_splaFD_OUT_BITS_1_TO_0_NOT_splaFD_OUT_B_ETC__q1 = - metaBram_serverAdapterB_1_outData_outData$whas; + CASE_splaF_first__95_BITS_1_TO_0_97_0_metaBram_ETC___d914 = + metaBram_1_serverAdapterB_outData_outData$whas; 2'd2: - CASE_splaFD_OUT_BITS_1_TO_0_NOT_splaFD_OUT_B_ETC__q1 = - metaBram_serverAdapterB_2_outData_outData$whas; + CASE_splaF_first__95_BITS_1_TO_0_97_0_metaBram_ETC___d914 = + metaBram_2_serverAdapterB_outData_outData$whas; 2'd3: - CASE_splaFD_OUT_BITS_1_TO_0_NOT_splaFD_OUT_B_ETC__q1 = - splaF$D_OUT[1:0] != 2'd3 || - metaBram_serverAdapterB_3_outData_outData$whas; + CASE_splaF_first__95_BITS_1_TO_0_97_0_metaBram_ETC___d914 = + metaBram_3_serverAdapterB_outData_outData$whas; endcase end @@ -2670,28 +2688,28 @@ module mkWSICaptureWorker4B(wciS0_Clk, begin if (wciS0_MReset_n == `BSV_RESET_VALUE) begin - dataBram_serverAdapterA_cnt <= `BSV_ASSIGNMENT_DELAY 3'd0; - dataBram_serverAdapterA_s1 <= `BSV_ASSIGNMENT_DELAY 2'd0; - dataBram_serverAdapterB_cnt <= `BSV_ASSIGNMENT_DELAY 3'd0; - dataBram_serverAdapterB_s1 <= `BSV_ASSIGNMENT_DELAY 2'd0; + dataBram_0_serverAdapterA_cnt <= `BSV_ASSIGNMENT_DELAY 3'd0; + dataBram_0_serverAdapterA_s1 <= `BSV_ASSIGNMENT_DELAY 2'd0; + dataBram_0_serverAdapterB_cnt <= `BSV_ASSIGNMENT_DELAY 3'd0; + dataBram_0_serverAdapterB_s1 <= `BSV_ASSIGNMENT_DELAY 2'd0; isFirst <= `BSV_ASSIGNMENT_DELAY 1'd1; mesgLengthSoFar <= `BSV_ASSIGNMENT_DELAY 14'd0; - metaBram_serverAdapterA_1_cnt <= `BSV_ASSIGNMENT_DELAY 3'd0; - metaBram_serverAdapterA_1_s1 <= `BSV_ASSIGNMENT_DELAY 2'd0; - metaBram_serverAdapterA_2_cnt <= `BSV_ASSIGNMENT_DELAY 3'd0; - metaBram_serverAdapterA_2_s1 <= `BSV_ASSIGNMENT_DELAY 2'd0; - metaBram_serverAdapterA_3_cnt <= `BSV_ASSIGNMENT_DELAY 3'd0; - metaBram_serverAdapterA_3_s1 <= `BSV_ASSIGNMENT_DELAY 2'd0; - metaBram_serverAdapterA_cnt <= `BSV_ASSIGNMENT_DELAY 3'd0; - metaBram_serverAdapterA_s1 <= `BSV_ASSIGNMENT_DELAY 2'd0; - metaBram_serverAdapterB_1_cnt <= `BSV_ASSIGNMENT_DELAY 3'd0; - metaBram_serverAdapterB_1_s1 <= `BSV_ASSIGNMENT_DELAY 2'd0; - metaBram_serverAdapterB_2_cnt <= `BSV_ASSIGNMENT_DELAY 3'd0; - metaBram_serverAdapterB_2_s1 <= `BSV_ASSIGNMENT_DELAY 2'd0; - metaBram_serverAdapterB_3_cnt <= `BSV_ASSIGNMENT_DELAY 3'd0; - metaBram_serverAdapterB_3_s1 <= `BSV_ASSIGNMENT_DELAY 2'd0; - metaBram_serverAdapterB_cnt <= `BSV_ASSIGNMENT_DELAY 3'd0; - metaBram_serverAdapterB_s1 <= `BSV_ASSIGNMENT_DELAY 2'd0; + metaBram_0_serverAdapterA_cnt <= `BSV_ASSIGNMENT_DELAY 3'd0; + metaBram_0_serverAdapterA_s1 <= `BSV_ASSIGNMENT_DELAY 2'd0; + metaBram_0_serverAdapterB_cnt <= `BSV_ASSIGNMENT_DELAY 3'd0; + metaBram_0_serverAdapterB_s1 <= `BSV_ASSIGNMENT_DELAY 2'd0; + metaBram_1_serverAdapterA_cnt <= `BSV_ASSIGNMENT_DELAY 3'd0; + metaBram_1_serverAdapterA_s1 <= `BSV_ASSIGNMENT_DELAY 2'd0; + metaBram_1_serverAdapterB_cnt <= `BSV_ASSIGNMENT_DELAY 3'd0; + metaBram_1_serverAdapterB_s1 <= `BSV_ASSIGNMENT_DELAY 2'd0; + metaBram_2_serverAdapterA_cnt <= `BSV_ASSIGNMENT_DELAY 3'd0; + metaBram_2_serverAdapterA_s1 <= `BSV_ASSIGNMENT_DELAY 2'd0; + metaBram_2_serverAdapterB_cnt <= `BSV_ASSIGNMENT_DELAY 3'd0; + metaBram_2_serverAdapterB_s1 <= `BSV_ASSIGNMENT_DELAY 2'd0; + metaBram_3_serverAdapterA_cnt <= `BSV_ASSIGNMENT_DELAY 3'd0; + metaBram_3_serverAdapterA_s1 <= `BSV_ASSIGNMENT_DELAY 2'd0; + metaBram_3_serverAdapterB_cnt <= `BSV_ASSIGNMENT_DELAY 3'd0; + metaBram_3_serverAdapterB_s1 <= `BSV_ASSIGNMENT_DELAY 2'd0; splitReadInFlight <= `BSV_ASSIGNMENT_DELAY 1'd0; wci_wslv_cEdge <= `BSV_ASSIGNMENT_DELAY 3'h2; wci_wslv_cState <= `BSV_ASSIGNMENT_DELAY 3'd0; @@ -2700,7 +2718,7 @@ module mkWSICaptureWorker4B(wciS0_Clk, wci_wslv_illegalEdge <= `BSV_ASSIGNMENT_DELAY 1'd0; wci_wslv_nState <= `BSV_ASSIGNMENT_DELAY 3'd0; wci_wslv_reqF_countReg <= `BSV_ASSIGNMENT_DELAY 2'd0; - wci_wslv_respF_c_r <= `BSV_ASSIGNMENT_DELAY 2'd0; + wci_wslv_respF_cntr_r <= `BSV_ASSIGNMENT_DELAY 2'd0; wci_wslv_respF_q_0 <= `BSV_ASSIGNMENT_DELAY 34'h0AAAAAAAA; wci_wslv_respF_q_1 <= `BSV_ASSIGNMENT_DELAY 34'h0AAAAAAAA; wci_wslv_sFlagReg <= `BSV_ASSIGNMENT_DELAY 1'd0; @@ -2721,69 +2739,69 @@ module mkWSICaptureWorker4B(wciS0_Clk, end else begin - if (dataBram_serverAdapterA_cnt$EN) - dataBram_serverAdapterA_cnt <= `BSV_ASSIGNMENT_DELAY - dataBram_serverAdapterA_cnt$D_IN; - if (dataBram_serverAdapterA_s1$EN) - dataBram_serverAdapterA_s1 <= `BSV_ASSIGNMENT_DELAY - dataBram_serverAdapterA_s1$D_IN; - if (dataBram_serverAdapterB_cnt$EN) - dataBram_serverAdapterB_cnt <= `BSV_ASSIGNMENT_DELAY - dataBram_serverAdapterB_cnt$D_IN; - if (dataBram_serverAdapterB_s1$EN) - dataBram_serverAdapterB_s1 <= `BSV_ASSIGNMENT_DELAY - dataBram_serverAdapterB_s1$D_IN; + if (dataBram_0_serverAdapterA_cnt$EN) + dataBram_0_serverAdapterA_cnt <= `BSV_ASSIGNMENT_DELAY + dataBram_0_serverAdapterA_cnt$D_IN; + if (dataBram_0_serverAdapterA_s1$EN) + dataBram_0_serverAdapterA_s1 <= `BSV_ASSIGNMENT_DELAY + dataBram_0_serverAdapterA_s1$D_IN; + if (dataBram_0_serverAdapterB_cnt$EN) + dataBram_0_serverAdapterB_cnt <= `BSV_ASSIGNMENT_DELAY + dataBram_0_serverAdapterB_cnt$D_IN; + if (dataBram_0_serverAdapterB_s1$EN) + dataBram_0_serverAdapterB_s1 <= `BSV_ASSIGNMENT_DELAY + dataBram_0_serverAdapterB_s1$D_IN; if (isFirst$EN) isFirst <= `BSV_ASSIGNMENT_DELAY isFirst$D_IN; if (mesgLengthSoFar$EN) mesgLengthSoFar <= `BSV_ASSIGNMENT_DELAY mesgLengthSoFar$D_IN; - if (metaBram_serverAdapterA_1_cnt$EN) - metaBram_serverAdapterA_1_cnt <= `BSV_ASSIGNMENT_DELAY - metaBram_serverAdapterA_1_cnt$D_IN; - if (metaBram_serverAdapterA_1_s1$EN) - metaBram_serverAdapterA_1_s1 <= `BSV_ASSIGNMENT_DELAY - metaBram_serverAdapterA_1_s1$D_IN; - if (metaBram_serverAdapterA_2_cnt$EN) - metaBram_serverAdapterA_2_cnt <= `BSV_ASSIGNMENT_DELAY - metaBram_serverAdapterA_2_cnt$D_IN; - if (metaBram_serverAdapterA_2_s1$EN) - metaBram_serverAdapterA_2_s1 <= `BSV_ASSIGNMENT_DELAY - metaBram_serverAdapterA_2_s1$D_IN; - if (metaBram_serverAdapterA_3_cnt$EN) - metaBram_serverAdapterA_3_cnt <= `BSV_ASSIGNMENT_DELAY - metaBram_serverAdapterA_3_cnt$D_IN; - if (metaBram_serverAdapterA_3_s1$EN) - metaBram_serverAdapterA_3_s1 <= `BSV_ASSIGNMENT_DELAY - metaBram_serverAdapterA_3_s1$D_IN; - if (metaBram_serverAdapterA_cnt$EN) - metaBram_serverAdapterA_cnt <= `BSV_ASSIGNMENT_DELAY - metaBram_serverAdapterA_cnt$D_IN; - if (metaBram_serverAdapterA_s1$EN) - metaBram_serverAdapterA_s1 <= `BSV_ASSIGNMENT_DELAY - metaBram_serverAdapterA_s1$D_IN; - if (metaBram_serverAdapterB_1_cnt$EN) - metaBram_serverAdapterB_1_cnt <= `BSV_ASSIGNMENT_DELAY - metaBram_serverAdapterB_1_cnt$D_IN; - if (metaBram_serverAdapterB_1_s1$EN) - metaBram_serverAdapterB_1_s1 <= `BSV_ASSIGNMENT_DELAY - metaBram_serverAdapterB_1_s1$D_IN; - if (metaBram_serverAdapterB_2_cnt$EN) - metaBram_serverAdapterB_2_cnt <= `BSV_ASSIGNMENT_DELAY - metaBram_serverAdapterB_2_cnt$D_IN; - if (metaBram_serverAdapterB_2_s1$EN) - metaBram_serverAdapterB_2_s1 <= `BSV_ASSIGNMENT_DELAY - metaBram_serverAdapterB_2_s1$D_IN; - if (metaBram_serverAdapterB_3_cnt$EN) - metaBram_serverAdapterB_3_cnt <= `BSV_ASSIGNMENT_DELAY - metaBram_serverAdapterB_3_cnt$D_IN; - if (metaBram_serverAdapterB_3_s1$EN) - metaBram_serverAdapterB_3_s1 <= `BSV_ASSIGNMENT_DELAY - metaBram_serverAdapterB_3_s1$D_IN; - if (metaBram_serverAdapterB_cnt$EN) - metaBram_serverAdapterB_cnt <= `BSV_ASSIGNMENT_DELAY - metaBram_serverAdapterB_cnt$D_IN; - if (metaBram_serverAdapterB_s1$EN) - metaBram_serverAdapterB_s1 <= `BSV_ASSIGNMENT_DELAY - metaBram_serverAdapterB_s1$D_IN; + if (metaBram_0_serverAdapterA_cnt$EN) + metaBram_0_serverAdapterA_cnt <= `BSV_ASSIGNMENT_DELAY + metaBram_0_serverAdapterA_cnt$D_IN; + if (metaBram_0_serverAdapterA_s1$EN) + metaBram_0_serverAdapterA_s1 <= `BSV_ASSIGNMENT_DELAY + metaBram_0_serverAdapterA_s1$D_IN; + if (metaBram_0_serverAdapterB_cnt$EN) + metaBram_0_serverAdapterB_cnt <= `BSV_ASSIGNMENT_DELAY + metaBram_0_serverAdapterB_cnt$D_IN; + if (metaBram_0_serverAdapterB_s1$EN) + metaBram_0_serverAdapterB_s1 <= `BSV_ASSIGNMENT_DELAY + metaBram_0_serverAdapterB_s1$D_IN; + if (metaBram_1_serverAdapterA_cnt$EN) + metaBram_1_serverAdapterA_cnt <= `BSV_ASSIGNMENT_DELAY + metaBram_1_serverAdapterA_cnt$D_IN; + if (metaBram_1_serverAdapterA_s1$EN) + metaBram_1_serverAdapterA_s1 <= `BSV_ASSIGNMENT_DELAY + metaBram_1_serverAdapterA_s1$D_IN; + if (metaBram_1_serverAdapterB_cnt$EN) + metaBram_1_serverAdapterB_cnt <= `BSV_ASSIGNMENT_DELAY + metaBram_1_serverAdapterB_cnt$D_IN; + if (metaBram_1_serverAdapterB_s1$EN) + metaBram_1_serverAdapterB_s1 <= `BSV_ASSIGNMENT_DELAY + metaBram_1_serverAdapterB_s1$D_IN; + if (metaBram_2_serverAdapterA_cnt$EN) + metaBram_2_serverAdapterA_cnt <= `BSV_ASSIGNMENT_DELAY + metaBram_2_serverAdapterA_cnt$D_IN; + if (metaBram_2_serverAdapterA_s1$EN) + metaBram_2_serverAdapterA_s1 <= `BSV_ASSIGNMENT_DELAY + metaBram_2_serverAdapterA_s1$D_IN; + if (metaBram_2_serverAdapterB_cnt$EN) + metaBram_2_serverAdapterB_cnt <= `BSV_ASSIGNMENT_DELAY + metaBram_2_serverAdapterB_cnt$D_IN; + if (metaBram_2_serverAdapterB_s1$EN) + metaBram_2_serverAdapterB_s1 <= `BSV_ASSIGNMENT_DELAY + metaBram_2_serverAdapterB_s1$D_IN; + if (metaBram_3_serverAdapterA_cnt$EN) + metaBram_3_serverAdapterA_cnt <= `BSV_ASSIGNMENT_DELAY + metaBram_3_serverAdapterA_cnt$D_IN; + if (metaBram_3_serverAdapterA_s1$EN) + metaBram_3_serverAdapterA_s1 <= `BSV_ASSIGNMENT_DELAY + metaBram_3_serverAdapterA_s1$D_IN; + if (metaBram_3_serverAdapterB_cnt$EN) + metaBram_3_serverAdapterB_cnt <= `BSV_ASSIGNMENT_DELAY + metaBram_3_serverAdapterB_cnt$D_IN; + if (metaBram_3_serverAdapterB_s1$EN) + metaBram_3_serverAdapterB_s1 <= `BSV_ASSIGNMENT_DELAY + metaBram_3_serverAdapterB_s1$D_IN; if (splitReadInFlight$EN) splitReadInFlight <= `BSV_ASSIGNMENT_DELAY splitReadInFlight$D_IN; if (wci_wslv_cEdge$EN) @@ -2803,8 +2821,9 @@ module mkWSICaptureWorker4B(wciS0_Clk, if (wci_wslv_reqF_countReg$EN) wci_wslv_reqF_countReg <= `BSV_ASSIGNMENT_DELAY wci_wslv_reqF_countReg$D_IN; - if (wci_wslv_respF_c_r$EN) - wci_wslv_respF_c_r <= `BSV_ASSIGNMENT_DELAY wci_wslv_respF_c_r$D_IN; + if (wci_wslv_respF_cntr_r$EN) + wci_wslv_respF_cntr_r <= `BSV_ASSIGNMENT_DELAY + wci_wslv_respF_cntr_r$D_IN; if (wci_wslv_respF_q_0$EN) wci_wslv_respF_q_0 <= `BSV_ASSIGNMENT_DELAY wci_wslv_respF_q_0$D_IN; if (wci_wslv_respF_q_1$EN) @@ -2878,29 +2897,29 @@ module mkWSICaptureWorker4B(wciS0_Clk, initial begin controlReg = 32'hAAAAAAAA; - dataBram_serverAdapterA_cnt = 3'h2; - dataBram_serverAdapterA_s1 = 2'h2; - dataBram_serverAdapterB_cnt = 3'h2; - dataBram_serverAdapterB_s1 = 2'h2; + dataBram_0_serverAdapterA_cnt = 3'h2; + dataBram_0_serverAdapterA_s1 = 2'h2; + dataBram_0_serverAdapterB_cnt = 3'h2; + dataBram_0_serverAdapterB_s1 = 2'h2; dataCount = 32'hAAAAAAAA; isFirst = 1'h0; mesgLengthSoFar = 14'h2AAA; - metaBram_serverAdapterA_1_cnt = 3'h2; - metaBram_serverAdapterA_1_s1 = 2'h2; - metaBram_serverAdapterA_2_cnt = 3'h2; - metaBram_serverAdapterA_2_s1 = 2'h2; - metaBram_serverAdapterA_3_cnt = 3'h2; - metaBram_serverAdapterA_3_s1 = 2'h2; - metaBram_serverAdapterA_cnt = 3'h2; - metaBram_serverAdapterA_s1 = 2'h2; - metaBram_serverAdapterB_1_cnt = 3'h2; - metaBram_serverAdapterB_1_s1 = 2'h2; - metaBram_serverAdapterB_2_cnt = 3'h2; - metaBram_serverAdapterB_2_s1 = 2'h2; - metaBram_serverAdapterB_3_cnt = 3'h2; - metaBram_serverAdapterB_3_s1 = 2'h2; - metaBram_serverAdapterB_cnt = 3'h2; - metaBram_serverAdapterB_s1 = 2'h2; + metaBram_0_serverAdapterA_cnt = 3'h2; + metaBram_0_serverAdapterA_s1 = 2'h2; + metaBram_0_serverAdapterB_cnt = 3'h2; + metaBram_0_serverAdapterB_s1 = 2'h2; + metaBram_1_serverAdapterA_cnt = 3'h2; + metaBram_1_serverAdapterA_s1 = 2'h2; + metaBram_1_serverAdapterB_cnt = 3'h2; + metaBram_1_serverAdapterB_s1 = 2'h2; + metaBram_2_serverAdapterA_cnt = 3'h2; + metaBram_2_serverAdapterA_s1 = 2'h2; + metaBram_2_serverAdapterB_cnt = 3'h2; + metaBram_2_serverAdapterB_s1 = 2'h2; + metaBram_3_serverAdapterA_cnt = 3'h2; + metaBram_3_serverAdapterA_s1 = 2'h2; + metaBram_3_serverAdapterB_cnt = 3'h2; + metaBram_3_serverAdapterB_s1 = 2'h2; metaCount = 32'hAAAAAAAA; splitReadInFlight = 1'h0; wci_wslv_cEdge = 3'h2; @@ -2911,7 +2930,7 @@ module mkWSICaptureWorker4B(wciS0_Clk, wci_wslv_isReset_isInReset = 1'h0; wci_wslv_nState = 3'h2; wci_wslv_reqF_countReg = 2'h2; - wci_wslv_respF_c_r = 2'h2; + wci_wslv_respF_cntr_r = 2'h2; wci_wslv_respF_q_0 = 34'h2AAAAAAAA; wci_wslv_respF_q_1 = 34'h2AAAAAAAA; wci_wslv_sFlagReg = 1'h0; @@ -2946,132 +2965,132 @@ module mkWSICaptureWorker4B(wciS0_Clk, if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_start) begin - v__h3718 = $time; + v__h3586 = $time; #0; end if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_start) $display("[%0d]: %m: WCI ControlOp: Starting-transition edge:%x from:%x", - v__h3718, + v__h3586, wci_wslv_reqF$D_OUT[36:34], wci_wslv_cState); if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfrd && wci_wslv_reqF$D_OUT[63:52] == 12'h0) begin - v__h27000 = $time; + v__h26755 = $time; #0; end if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfrd && wci_wslv_reqF$D_OUT[63:52] == 12'h0) $display("[%0d]: %m: WCI CONFIG READ Addr:%0x BE:%0x Data:%0x", - v__h27000, + v__h26755, wci_wslv_reqF$D_OUT[63:32], wci_wslv_reqF$D_OUT[67:64], - v__h26981); + v__h26736); if (wciS0_MReset_n != `BSV_RESET_VALUE) if (MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 && - controlReg_30_BIT_0_31_AND_NOT_controlReg_30_B_ETC___d878 && + controlReg_28_BIT_0_29_AND_NOT_controlReg_28_B_ETC___d876 && wsiS_reqFifo$D_OUT[57]) begin - v__h25452 = $time; + v__h25329 = $time; #0; end if (wciS0_MReset_n != `BSV_RESET_VALUE) if (MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 && - controlReg_30_BIT_0_31_AND_NOT_controlReg_30_B_ETC___d878 && + controlReg_28_BIT_0_29_AND_NOT_controlReg_28_B_ETC___d876 && wsiS_reqFifo$D_OUT[57]) $display("[%0d]: %m: doMessageAccept DWM metaCount:%0x WSI opcode:%0x length:%0x", - v__h25452, + v__h25329, metaCount, wsiS_reqFifo$D_OUT[7:0], - mlB__h23348); + mlB__h23202); if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfwr) begin - v__h26795 = $time; + v__h26550 = $time; #0; end if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfwr) $display("[%0d]: %m: WCI CONFIG WRITE Addr:%0x BE:%0x Data:%0x", - v__h26795, + v__h26550, wci_wslv_reqF$D_OUT[63:32], wci_wslv_reqF$D_OUT[67:64], wci_wslv_reqF$D_OUT[31:0]); if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge) begin - v__h4037 = $time; + v__h3905 = $time; #0; end if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge) $display("[%0d]: %m: WCI ControlOp: ILLEGAL-EDGE Completed-transition edge:%x from:%x", - v__h4037, + v__h3905, wci_wslv_cEdge, wci_wslv_cState); if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && !wci_wslv_illegalEdge) begin - v__h3893 = $time; + v__h3761 = $time; #0; end if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && !wci_wslv_illegalEdge) $display("[%0d]: %m: WCI ControlOp: Completed-transition edge:%x from:%x to:%x", - v__h3893, + v__h3761, wci_wslv_cEdge, wci_wslv_cState, wci_wslv_nState); if (wciS0_MReset_n != `BSV_RESET_VALUE) - if (dataBram_serverAdapterA_s1[1] && - !dataBram_serverAdapterA_outDataCore$FULL_N) + if (dataBram_0_serverAdapterA_s1[1] && + !dataBram_0_serverAdapterA_outDataCore$FULL_N) $display("ERROR: %m: mkBRAMSeverAdapter overrun"); if (wciS0_MReset_n != `BSV_RESET_VALUE) - if (dataBram_serverAdapterB_s1[1] && - !dataBram_serverAdapterB_outDataCore$FULL_N) + if (dataBram_0_serverAdapterB_s1[1] && + !dataBram_0_serverAdapterB_outDataCore$FULL_N) $display("ERROR: %m: mkBRAMSeverAdapter overrun"); if (wciS0_MReset_n != `BSV_RESET_VALUE) - if (metaBram_serverAdapterA_s1[1] && - !metaBram_serverAdapterA_outDataCore$FULL_N) + if (metaBram_0_serverAdapterA_s1[1] && + !metaBram_0_serverAdapterA_outDataCore$FULL_N) $display("ERROR: %m: mkBRAMSeverAdapter overrun"); if (wciS0_MReset_n != `BSV_RESET_VALUE) - if (metaBram_serverAdapterB_s1[1] && - !metaBram_serverAdapterB_outDataCore$FULL_N) + if (metaBram_0_serverAdapterB_s1[1] && + !metaBram_0_serverAdapterB_outDataCore$FULL_N) $display("ERROR: %m: mkBRAMSeverAdapter overrun"); if (wciS0_MReset_n != `BSV_RESET_VALUE) - if (metaBram_serverAdapterA_1_s1[1] && - !metaBram_serverAdapterA_1_outDataCore$FULL_N) + if (metaBram_1_serverAdapterA_s1[1] && + !metaBram_1_serverAdapterA_outDataCore$FULL_N) $display("ERROR: %m: mkBRAMSeverAdapter overrun"); if (wciS0_MReset_n != `BSV_RESET_VALUE) - if (metaBram_serverAdapterB_1_s1[1] && - !metaBram_serverAdapterB_1_outDataCore$FULL_N) + if (metaBram_1_serverAdapterB_s1[1] && + !metaBram_1_serverAdapterB_outDataCore$FULL_N) $display("ERROR: %m: mkBRAMSeverAdapter overrun"); if (wciS0_MReset_n != `BSV_RESET_VALUE) - if (metaBram_serverAdapterA_2_s1[1] && - !metaBram_serverAdapterA_2_outDataCore$FULL_N) + if (metaBram_2_serverAdapterA_s1[1] && + !metaBram_2_serverAdapterA_outDataCore$FULL_N) $display("ERROR: %m: mkBRAMSeverAdapter overrun"); if (wciS0_MReset_n != `BSV_RESET_VALUE) - if (metaBram_serverAdapterB_2_s1[1] && - !metaBram_serverAdapterB_2_outDataCore$FULL_N) + if (metaBram_2_serverAdapterB_s1[1] && + !metaBram_2_serverAdapterB_outDataCore$FULL_N) $display("ERROR: %m: mkBRAMSeverAdapter overrun"); if (wciS0_MReset_n != `BSV_RESET_VALUE) - if (metaBram_serverAdapterA_3_s1[1] && - !metaBram_serverAdapterA_3_outDataCore$FULL_N) + if (metaBram_3_serverAdapterA_s1[1] && + !metaBram_3_serverAdapterA_outDataCore$FULL_N) $display("ERROR: %m: mkBRAMSeverAdapter overrun"); if (wciS0_MReset_n != `BSV_RESET_VALUE) - if (metaBram_serverAdapterB_3_s1[1] && - !metaBram_serverAdapterB_3_outDataCore$FULL_N) + if (metaBram_3_serverAdapterB_s1[1] && + !metaBram_3_serverAdapterB_outDataCore$FULL_N) $display("ERROR: %m: mkBRAMSeverAdapter overrun"); if (wciS0_MReset_n != `BSV_RESET_VALUE) if (MUX_wci_wslv_respF_x_wire$wset_1__SEL_3) begin - v__h26500 = $time; + v__h26261 = $time; #0; end if (wciS0_MReset_n != `BSV_RESET_VALUE) if (MUX_wci_wslv_respF_x_wire$wset_1__SEL_3) - $display("[%0d]: %m: WCI SPLIT READ Data:%0x", v__h26500, v__h25581); + $display("[%0d]: %m: WCI SPLIT READ Data:%0x", v__h26261, v__h25458); if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_wci_cfwr && MUX_wci_wslv_respF_x_wire$wset_1__SEL_3) $display("Error: \"bsv/wrk/WSICaptureWorker.bsv\", line 157, column 28: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_advance_split_response] ) fired in the same clock cycle.\n"); diff --git a/rtl/mkWciInitiator.v b/rtl/mkWciInitiator.v index 4d238d28..996b38d0 100644 --- a/rtl/mkWciInitiator.v +++ b/rtl/mkWciInitiator.v @@ -1,7 +1,7 @@ // -// Generated by Bluespec Compiler, version 2012.09.beta1 (build 29570, 2012-09.11) +// Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Tue Dec 11 16:19:51 EST 2012 +// On Fri Jun 21 16:57:04 EDT 2013 // // // Ports: @@ -111,8 +111,8 @@ module mkWciInitiator(CLK, wire [1 : 0] wci_Em_resp_w$wget; wire initFsm_abort$wget, initFsm_abort$whas, - initFsm_start_reg_1_1$wget, - initFsm_start_reg_1_1$whas, + initFsm_start_reg_2$wget, + initFsm_start_reg_2$whas, initFsm_start_wire$wget, initFsm_start_wire$whas, initFsm_state_fired_1$wget, @@ -196,9 +196,9 @@ module mkWciInitiator(CLK, reg [2 : 0] initiator_reqFAIL$D_IN; wire initiator_reqFAIL$EN; - // register initiator_reqF_c_r - reg initiator_reqF_c_r; - wire initiator_reqF_c_r$D_IN, initiator_reqF_c_r$EN; + // register initiator_reqF_cntr_r + reg initiator_reqF_cntr_r; + wire initiator_reqF_cntr_r$D_IN, initiator_reqF_cntr_r$EN; // register initiator_reqF_q_0 reg [71 : 0] initiator_reqF_q_0; @@ -275,19 +275,19 @@ module mkWciInitiator(CLK, initiator_respF$FULL_N; // rule scheduling signals - wire WILL_FIRE_RL_initFsm_action_l1105c5, - WILL_FIRE_RL_initFsm_action_l1106c14, - WILL_FIRE_RL_initFsm_action_l1107c5, - WILL_FIRE_RL_initFsm_action_l1108c14, - WILL_FIRE_RL_initFsm_action_l1109c5, + wire WILL_FIRE_RL_initFsm_action_l1109c5, WILL_FIRE_RL_initFsm_action_l1110c14, WILL_FIRE_RL_initFsm_action_l1111c5, WILL_FIRE_RL_initFsm_action_l1112c14, WILL_FIRE_RL_initFsm_action_l1113c5, WILL_FIRE_RL_initFsm_action_l1114c14, WILL_FIRE_RL_initFsm_action_l1115c5, + WILL_FIRE_RL_initFsm_action_l1116c14, + WILL_FIRE_RL_initFsm_action_l1117c5, + WILL_FIRE_RL_initFsm_action_l1118c14, + WILL_FIRE_RL_initFsm_action_l1119c5, WILL_FIRE_RL_initFsm_fsm_start, - WILL_FIRE_RL_initFsm_idle_l1104c3, + WILL_FIRE_RL_initFsm_idle_l1108c3, WILL_FIRE_RL_initiator_reqF_both, WILL_FIRE_RL_initiator_reqF_decCtr, WILL_FIRE_RL_initiator_reqF_incCtr, @@ -308,8 +308,8 @@ module mkWciInitiator(CLK, MUX_initiator_lastControlOp$write_1__SEL_2, MUX_initiator_lastOpWrite$write_1__SEL_1, MUX_initiator_lastOpWrite$write_1__SEL_2, - MUX_initiator_reqF_c_r$write_1__VAL_1, - MUX_initiator_reqF_c_r$write_1__VAL_2, + MUX_initiator_reqF_cntr_r$write_1__VAL_1, + MUX_initiator_reqF_cntr_r$write_1__VAL_2, MUX_initiator_reqF_q_0$write_1__SEL_1, MUX_initiator_reqPend$write_1__PSEL_3, MUX_initiator_reqPend$write_1__SEL_3, @@ -317,24 +317,24 @@ module mkWciInitiator(CLK, MUX_initiator_respF$enq_1__SEL_1; // remaining internal signals - reg [63 : 0] v__h22397, - v__h23185, - v__h23475, - v__h23971, - v__h24273, - v__h24777, - v__h25559, - v__h26363, - v__h2868, - v__h2958, - v__h3047, - v__h3280, - v__h3370, - v__h3459, - v__h3697, - v__h3787, - v__h3876; - wire [31 : 0] toCount__h2563, x__h25252, x__h2726; + reg [63 : 0] v__h22302, + v__h23090, + v__h23380, + v__h23876, + v__h24178, + v__h24682, + v__h25464, + v__h26268, + v__h2800, + v__h2890, + v__h2979, + v__h3212, + v__h3302, + v__h3391, + v__h3629, + v__h3719, + v__h3808; + wire [31 : 0] toCount__h2495, x__h25157, x__h2658; wire [26 : 0] IF_initiator_lastControlOp_22_BIT_3_23_THEN_in_ETC___d137; wire NOT_initiator_busy_5_79_AND_IF_initiator_wRese_ETC___d192, _dand1initiator_busy$EN_write, @@ -342,7 +342,7 @@ module mkWciInitiator(CLK, _dor1initiator_lastConfigAddr$EN_write, _dor1initiator_lastConfigBE$EN_write, initFsm_abort_whas__45_AND_initFsm_abort_wget__ETC___d231, - initiator_respTimr_7_ULT_1_SL_initiator_wTimeo_ETC___d283; + initiator_respTimr_7_ULT_1_SL_initiator_wTimeo_ETC___d40; // output resets assign RST_N_wciM0 = initiator_mReset$OUT_RST ; @@ -388,49 +388,49 @@ module mkWciInitiator(CLK, .FULL_N(initiator_respF$FULL_N), .EMPTY_N(initiator_respF$EMPTY_N)); - // rule RL_initFsm_action_l1106c14 - assign WILL_FIRE_RL_initFsm_action_l1106c14 = + // rule RL_initFsm_action_l1110c14 + assign WILL_FIRE_RL_initFsm_action_l1110c14 = !initiator_busy && initiator_respF$FULL_N && initFsm_state_mkFSMstate == 4'd1 ; - // rule RL_initFsm_action_l1107c5 - assign WILL_FIRE_RL_initFsm_action_l1107c5 = + // rule RL_initFsm_action_l1111c5 + assign WILL_FIRE_RL_initFsm_action_l1111c5 = initiator_respF$EMPTY_N && initFsm_state_mkFSMstate == 4'd2 ; - // rule RL_initFsm_action_l1108c14 - assign WILL_FIRE_RL_initFsm_action_l1108c14 = + // rule RL_initFsm_action_l1112c14 + assign WILL_FIRE_RL_initFsm_action_l1112c14 = NOT_initiator_busy_5_79_AND_IF_initiator_wRese_ETC___d192 && initFsm_state_mkFSMstate == 4'd3 ; - // rule RL_initFsm_action_l1109c5 - assign WILL_FIRE_RL_initFsm_action_l1109c5 = + // rule RL_initFsm_action_l1113c5 + assign WILL_FIRE_RL_initFsm_action_l1113c5 = initiator_respF$EMPTY_N && initFsm_state_mkFSMstate == 4'd4 ; - // rule RL_initFsm_action_l1110c14 - assign WILL_FIRE_RL_initFsm_action_l1110c14 = + // rule RL_initFsm_action_l1114c14 + assign WILL_FIRE_RL_initFsm_action_l1114c14 = NOT_initiator_busy_5_79_AND_IF_initiator_wRese_ETC___d192 && initFsm_state_mkFSMstate == 4'd5 ; - // rule RL_initFsm_action_l1111c5 - assign WILL_FIRE_RL_initFsm_action_l1111c5 = + // rule RL_initFsm_action_l1115c5 + assign WILL_FIRE_RL_initFsm_action_l1115c5 = initiator_respF$EMPTY_N && initFsm_state_mkFSMstate == 4'd6 ; - // rule RL_initFsm_action_l1112c14 - assign WILL_FIRE_RL_initFsm_action_l1112c14 = + // rule RL_initFsm_action_l1116c14 + assign WILL_FIRE_RL_initFsm_action_l1116c14 = NOT_initiator_busy_5_79_AND_IF_initiator_wRese_ETC___d192 && initFsm_state_mkFSMstate == 4'd7 ; - // rule RL_initFsm_action_l1113c5 - assign WILL_FIRE_RL_initFsm_action_l1113c5 = + // rule RL_initFsm_action_l1117c5 + assign WILL_FIRE_RL_initFsm_action_l1117c5 = initiator_respF$EMPTY_N && initFsm_state_mkFSMstate == 4'd8 ; - // rule RL_initFsm_action_l1114c14 - assign WILL_FIRE_RL_initFsm_action_l1114c14 = + // rule RL_initFsm_action_l1118c14 + assign WILL_FIRE_RL_initFsm_action_l1118c14 = NOT_initiator_busy_5_79_AND_IF_initiator_wRese_ETC___d192 && initFsm_state_mkFSMstate == 4'd9 ; - // rule RL_initFsm_action_l1115c5 - assign WILL_FIRE_RL_initFsm_action_l1115c5 = + // rule RL_initFsm_action_l1119c5 + assign WILL_FIRE_RL_initFsm_action_l1119c5 = initiator_respF$EMPTY_N && initFsm_state_mkFSMstate == 4'd10 ; // rule RL_initFsm_fsm_start @@ -438,27 +438,27 @@ module mkWciInitiator(CLK, initFsm_abort_whas__45_AND_initFsm_abort_wget__ETC___d231 && initFsm_start_reg ; - // rule RL_initFsm_action_l1105c5 - assign WILL_FIRE_RL_initFsm_action_l1105c5 = + // rule RL_initFsm_action_l1109c5 + assign WILL_FIRE_RL_initFsm_action_l1109c5 = initFsm_start_wire$whas && (initFsm_state_mkFSMstate == 4'd0 || initFsm_state_mkFSMstate == 4'd11) ; - // rule RL_initFsm_idle_l1104c3 - assign WILL_FIRE_RL_initFsm_idle_l1104c3 = + // rule RL_initFsm_idle_l1108c3 + assign WILL_FIRE_RL_initFsm_idle_l1108c3 = !initFsm_start_wire$whas && initFsm_state_mkFSMstate == 4'd11 ; // rule RL_initiator_wrkBusy assign WILL_FIRE_RL_initiator_wrkBusy = ((initiator_wciResponse$wget[33:32] == 2'd0) ? - initiator_respTimr_7_ULT_1_SL_initiator_wTimeo_ETC___d283 || + initiator_respTimr_7_ULT_1_SL_initiator_wTimeo_ETC___d40 || initiator_respF$FULL_N : initiator_respF$FULL_N) && initiator_busy ; // rule RL_initiator_reqF_incCtr assign WILL_FIRE_RL_initiator_reqF_incCtr = - (initiator_reqF_c_r || initiator_reqF_x_wire$whas) && + (initiator_reqF_cntr_r || initiator_reqF_x_wire$whas) && initiator_reqF_enqueueing$whas && !initiator_reqF_dequeueing$whas ; @@ -469,7 +469,7 @@ module mkWciInitiator(CLK, // rule RL_initiator_reqF_both assign WILL_FIRE_RL_initiator_reqF_both = - (!initiator_reqF_c_r || initiator_reqF_x_wire$whas) && + (!initiator_reqF_cntr_r || initiator_reqF_x_wire$whas) && initiator_reqF_dequeueing$whas && initiator_reqF_enqueueing$whas ; @@ -479,29 +479,29 @@ module mkWciInitiator(CLK, !initFsm_start_reg && !started ; assign MUX_initiator_busy$write_1__PSEL_1 = + WILL_FIRE_RL_initFsm_action_l1118c14 || + WILL_FIRE_RL_initFsm_action_l1116c14 || WILL_FIRE_RL_initFsm_action_l1114c14 || - WILL_FIRE_RL_initFsm_action_l1112c14 || - WILL_FIRE_RL_initFsm_action_l1110c14 || - WILL_FIRE_RL_initFsm_action_l1108c14 ; + WILL_FIRE_RL_initFsm_action_l1112c14 ; assign MUX_initiator_busy$write_1__SEL_1 = MUX_initiator_busy$write_1__PSEL_1 && initiator_wReset_n ; assign MUX_initiator_busy$write_1__SEL_2 = WILL_FIRE_RL_initiator_wrkBusy && - (!initiator_respTimr_7_ULT_1_SL_initiator_wTimeo_ETC___d283 || + (!initiator_respTimr_7_ULT_1_SL_initiator_wTimeo_ETC___d40 || initiator_wciResponse$wget[33:32] != 2'd0) ; assign MUX_initiator_lastControlOp$write_1__SEL_1 = - WILL_FIRE_RL_initFsm_action_l1108c14 && initiator_wReset_n ; + WILL_FIRE_RL_initFsm_action_l1112c14 && initiator_wReset_n ; assign MUX_initiator_lastControlOp$write_1__SEL_2 = - WILL_FIRE_RL_initFsm_action_l1110c14 && initiator_wReset_n ; - assign MUX_initiator_lastOpWrite$write_1__SEL_1 = WILL_FIRE_RL_initFsm_action_l1114c14 && initiator_wReset_n ; + assign MUX_initiator_lastOpWrite$write_1__SEL_1 = + WILL_FIRE_RL_initFsm_action_l1118c14 && initiator_wReset_n ; assign MUX_initiator_lastOpWrite$write_1__SEL_2 = - WILL_FIRE_RL_initFsm_action_l1112c14 && initiator_wReset_n ; + WILL_FIRE_RL_initFsm_action_l1116c14 && initiator_wReset_n ; assign MUX_initiator_reqF_q_0$write_1__SEL_1 = - WILL_FIRE_RL_initiator_reqF_incCtr && !initiator_reqF_c_r ; + WILL_FIRE_RL_initiator_reqF_incCtr && !initiator_reqF_cntr_r ; assign MUX_initiator_reqPend$write_1__PSEL_3 = - WILL_FIRE_RL_initFsm_action_l1110c14 || - WILL_FIRE_RL_initFsm_action_l1108c14 ; + WILL_FIRE_RL_initFsm_action_l1114c14 || + WILL_FIRE_RL_initFsm_action_l1112c14 ; assign MUX_initiator_reqPend$write_1__SEL_3 = MUX_initiator_reqPend$write_1__PSEL_3 && initiator_wReset_n ; assign MUX_initiator_reqPend$write_1__SEL_4 = @@ -509,8 +509,10 @@ module mkWciInitiator(CLK, initiator_wciResponse$wget[33:32] != 2'd0 ; assign MUX_initiator_respF$enq_1__SEL_1 = MUX_initiator_busy$write_1__PSEL_1 && !initiator_wReset_n ; - assign MUX_initiator_reqF_c_r$write_1__VAL_1 = initiator_reqF_c_r + 1'd1 ; - assign MUX_initiator_reqF_c_r$write_1__VAL_2 = initiator_reqF_c_r - 1'd1 ; + assign MUX_initiator_reqF_cntr_r$write_1__VAL_1 = + initiator_reqF_cntr_r + 1'd1 ; + assign MUX_initiator_reqF_cntr_r$write_1__VAL_2 = + initiator_reqF_cntr_r - 1'd1 ; always@(MUX_initiator_lastOpWrite$write_1__SEL_2 or MUX_initiator_reqF_x_wire$wset_1__VAL_1 or MUX_initiator_lastOpWrite$write_1__SEL_1 or @@ -534,31 +536,31 @@ module mkWciInitiator(CLK, endcase end assign MUX_initiator_reqF_q_0$write_1__VAL_2 = - initiator_reqF_c_r ? + initiator_reqF_cntr_r ? MUX_initiator_reqF_q_0$write_1__VAL_1 : 72'h0000000000AAAAAAAA ; assign MUX_initiator_reqF_x_wire$wset_1__VAL_1 = - { 8'd63, x__h25252, 32'h80000042 } ; + { 8'd63, x__h25157, 32'h80000042 } ; assign MUX_initiator_reqF_x_wire$wset_1__VAL_2 = - { 8'd95, x__h25252, 32'h80000000 } ; + { 8'd95, x__h25157, 32'h80000000 } ; assign MUX_initiator_respF$enq_1__VAL_2 = (initiator_wciResponse$wget[33:32] == 2'd0) ? 34'h1C0DE4203 : initiator_wciResponse$wget ; assign MUX_initiator_respTimr$write_1__VAL_2 = (initiator_wciResponse$wget[33:32] == 2'd0) ? - (initiator_respTimr_7_ULT_1_SL_initiator_wTimeo_ETC___d283 ? - x__h2726 : + (initiator_respTimr_7_ULT_1_SL_initiator_wTimeo_ETC___d40 ? + x__h2658 : 32'd0) : 32'd0 ; // inlined wires assign initiator_reqF_x_wire$wget = MUX_initiator_reqF_q_0$write_1__VAL_1 ; assign initiator_reqF_x_wire$whas = + WILL_FIRE_RL_initFsm_action_l1116c14 && initiator_wReset_n || + WILL_FIRE_RL_initFsm_action_l1118c14 && initiator_wReset_n || WILL_FIRE_RL_initFsm_action_l1112c14 && initiator_wReset_n || - WILL_FIRE_RL_initFsm_action_l1114c14 && initiator_wReset_n || - WILL_FIRE_RL_initFsm_action_l1108c14 && initiator_wReset_n || - WILL_FIRE_RL_initFsm_action_l1110c14 && initiator_wReset_n ; + WILL_FIRE_RL_initFsm_action_l1114c14 && initiator_wReset_n ; assign initiator_wciResponse$wget = { wciM0_SResp, wciM0_SData } ; assign initiator_wciResponse$whas = 1'd1 ; assign initiator_sfCapSet_1$wget = wciM0_SFlag[0] ; @@ -569,8 +571,8 @@ module mkWciInitiator(CLK, assign initFsm_start_wire$whas = WILL_FIRE_RL_initFsm_fsm_start || initFsm_start_reg_1 && !initFsm_state_fired ; - assign initFsm_start_reg_1_1$wget = 1'd1 ; - assign initFsm_start_reg_1_1$whas = initFsm_start_wire$whas ; + assign initFsm_start_reg_2$wget = 1'd1 ; + assign initFsm_start_reg_2$whas = initFsm_start_wire$whas ; assign initFsm_abort$wget = 1'b0 ; assign initFsm_abort$whas = 1'b0 ; assign initFsm_state_fired_1$wget = 1'd1 ; @@ -584,21 +586,21 @@ module mkWciInitiator(CLK, assign initiator_reqF_dequeueing$whas = !initiator_sThreadBusy_d && initiator_wciResponse$wget[33:32] == 2'd0 && - initiator_reqF_c_r ; + initiator_reqF_cntr_r ; assign initiator_sThreadBusy_pw$whas = wciM0_SThreadBusy ; assign initFsm_state_set_pw$whas = - WILL_FIRE_RL_initFsm_idle_l1104c3 || + WILL_FIRE_RL_initFsm_idle_l1108c3 || + WILL_FIRE_RL_initFsm_action_l1119c5 || + WILL_FIRE_RL_initFsm_action_l1118c14 || + WILL_FIRE_RL_initFsm_action_l1117c5 || + WILL_FIRE_RL_initFsm_action_l1116c14 || WILL_FIRE_RL_initFsm_action_l1115c5 || WILL_FIRE_RL_initFsm_action_l1114c14 || WILL_FIRE_RL_initFsm_action_l1113c5 || WILL_FIRE_RL_initFsm_action_l1112c14 || WILL_FIRE_RL_initFsm_action_l1111c5 || WILL_FIRE_RL_initFsm_action_l1110c14 || - WILL_FIRE_RL_initFsm_action_l1109c5 || - WILL_FIRE_RL_initFsm_action_l1108c14 || - WILL_FIRE_RL_initFsm_action_l1107c5 || - WILL_FIRE_RL_initFsm_action_l1106c14 || - WILL_FIRE_RL_initFsm_action_l1105c5 ; + WILL_FIRE_RL_initFsm_action_l1109c5 ; assign initFsm_state_overlap_pw$whas = 1'b0 ; // register initFsm_start_reg @@ -623,67 +625,67 @@ module mkWciInitiator(CLK, assign initFsm_state_fired$EN = 1'd1 ; // register initFsm_state_mkFSMstate - always@(WILL_FIRE_RL_initFsm_idle_l1104c3 or - WILL_FIRE_RL_initFsm_action_l1105c5 or - WILL_FIRE_RL_initFsm_action_l1106c14 or - WILL_FIRE_RL_initFsm_action_l1107c5 or - WILL_FIRE_RL_initFsm_action_l1108c14 or + always@(WILL_FIRE_RL_initFsm_idle_l1108c3 or WILL_FIRE_RL_initFsm_action_l1109c5 or WILL_FIRE_RL_initFsm_action_l1110c14 or WILL_FIRE_RL_initFsm_action_l1111c5 or WILL_FIRE_RL_initFsm_action_l1112c14 or WILL_FIRE_RL_initFsm_action_l1113c5 or WILL_FIRE_RL_initFsm_action_l1114c14 or - WILL_FIRE_RL_initFsm_action_l1115c5) + WILL_FIRE_RL_initFsm_action_l1115c5 or + WILL_FIRE_RL_initFsm_action_l1116c14 or + WILL_FIRE_RL_initFsm_action_l1117c5 or + WILL_FIRE_RL_initFsm_action_l1118c14 or + WILL_FIRE_RL_initFsm_action_l1119c5) begin case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_initFsm_idle_l1104c3: initFsm_state_mkFSMstate$D_IN = 4'd0; - WILL_FIRE_RL_initFsm_action_l1105c5: + WILL_FIRE_RL_initFsm_idle_l1108c3: initFsm_state_mkFSMstate$D_IN = 4'd0; + WILL_FIRE_RL_initFsm_action_l1109c5: initFsm_state_mkFSMstate$D_IN = 4'd1; - WILL_FIRE_RL_initFsm_action_l1106c14: + WILL_FIRE_RL_initFsm_action_l1110c14: initFsm_state_mkFSMstate$D_IN = 4'd2; - WILL_FIRE_RL_initFsm_action_l1107c5: + WILL_FIRE_RL_initFsm_action_l1111c5: initFsm_state_mkFSMstate$D_IN = 4'd3; - WILL_FIRE_RL_initFsm_action_l1108c14: + WILL_FIRE_RL_initFsm_action_l1112c14: initFsm_state_mkFSMstate$D_IN = 4'd4; - WILL_FIRE_RL_initFsm_action_l1109c5: + WILL_FIRE_RL_initFsm_action_l1113c5: initFsm_state_mkFSMstate$D_IN = 4'd5; - WILL_FIRE_RL_initFsm_action_l1110c14: + WILL_FIRE_RL_initFsm_action_l1114c14: initFsm_state_mkFSMstate$D_IN = 4'd6; - WILL_FIRE_RL_initFsm_action_l1111c5: + WILL_FIRE_RL_initFsm_action_l1115c5: initFsm_state_mkFSMstate$D_IN = 4'd7; - WILL_FIRE_RL_initFsm_action_l1112c14: + WILL_FIRE_RL_initFsm_action_l1116c14: initFsm_state_mkFSMstate$D_IN = 4'd8; - WILL_FIRE_RL_initFsm_action_l1113c5: + WILL_FIRE_RL_initFsm_action_l1117c5: initFsm_state_mkFSMstate$D_IN = 4'd9; - WILL_FIRE_RL_initFsm_action_l1114c14: + WILL_FIRE_RL_initFsm_action_l1118c14: initFsm_state_mkFSMstate$D_IN = 4'd10; - WILL_FIRE_RL_initFsm_action_l1115c5: + WILL_FIRE_RL_initFsm_action_l1119c5: initFsm_state_mkFSMstate$D_IN = 4'd11; default: initFsm_state_mkFSMstate$D_IN = 4'b1010 /* unspecified value */ ; endcase end assign initFsm_state_mkFSMstate$EN = - WILL_FIRE_RL_initFsm_idle_l1104c3 || - WILL_FIRE_RL_initFsm_action_l1105c5 || - WILL_FIRE_RL_initFsm_action_l1106c14 || - WILL_FIRE_RL_initFsm_action_l1107c5 || - WILL_FIRE_RL_initFsm_action_l1108c14 || + WILL_FIRE_RL_initFsm_idle_l1108c3 || WILL_FIRE_RL_initFsm_action_l1109c5 || WILL_FIRE_RL_initFsm_action_l1110c14 || WILL_FIRE_RL_initFsm_action_l1111c5 || WILL_FIRE_RL_initFsm_action_l1112c14 || WILL_FIRE_RL_initFsm_action_l1113c5 || WILL_FIRE_RL_initFsm_action_l1114c14 || - WILL_FIRE_RL_initFsm_action_l1115c5 ; + WILL_FIRE_RL_initFsm_action_l1115c5 || + WILL_FIRE_RL_initFsm_action_l1116c14 || + WILL_FIRE_RL_initFsm_action_l1117c5 || + WILL_FIRE_RL_initFsm_action_l1118c14 || + WILL_FIRE_RL_initFsm_action_l1119c5 ; // register initiator_busy assign initiator_busy$D_IN = MUX_initiator_busy$write_1__SEL_1 ; assign initiator_busy$EN = _dand1initiator_busy$EN_write || WILL_FIRE_RL_initiator_wrkBusy && - (!initiator_respTimr_7_ULT_1_SL_initiator_wTimeo_ETC___d283 || + (!initiator_respTimr_7_ULT_1_SL_initiator_wTimeo_ETC___d40 || initiator_wciResponse$wget[33:32] != 2'd0) ; // register initiator_lastConfigAddr @@ -700,15 +702,15 @@ module mkWciInitiator(CLK, assign initiator_lastControlOp$D_IN = MUX_initiator_lastControlOp$write_1__SEL_1 ? 4'd8 : 4'd9 ; assign initiator_lastControlOp$EN = - WILL_FIRE_RL_initFsm_action_l1108c14 && initiator_wReset_n || - WILL_FIRE_RL_initFsm_action_l1110c14 && initiator_wReset_n ; + WILL_FIRE_RL_initFsm_action_l1112c14 && initiator_wReset_n || + WILL_FIRE_RL_initFsm_action_l1114c14 && initiator_wReset_n ; // register initiator_lastOpWrite assign initiator_lastOpWrite$D_IN = MUX_initiator_lastOpWrite$write_1__SEL_1 ? 2'd2 : 2'd3 ; assign initiator_lastOpWrite$EN = - WILL_FIRE_RL_initFsm_action_l1114c14 && initiator_wReset_n || - WILL_FIRE_RL_initFsm_action_l1112c14 && initiator_wReset_n ; + WILL_FIRE_RL_initFsm_action_l1118c14 && initiator_wReset_n || + WILL_FIRE_RL_initFsm_action_l1116c14 && initiator_wReset_n ; // register initiator_mFlagReg assign initiator_mFlagReg$D_IN = 2'h0 ; @@ -752,12 +754,12 @@ module mkWciInitiator(CLK, (initiator_reqPend == 2'd1 || initiator_reqPend == 2'd2 || initiator_reqPend == 2'd3) ; - // register initiator_reqF_c_r - assign initiator_reqF_c_r$D_IN = + // register initiator_reqF_cntr_r + assign initiator_reqF_cntr_r$D_IN = WILL_FIRE_RL_initiator_reqF_incCtr ? - MUX_initiator_reqF_c_r$write_1__VAL_1 : - MUX_initiator_reqF_c_r$write_1__VAL_2 ; - assign initiator_reqF_c_r$EN = + MUX_initiator_reqF_cntr_r$write_1__VAL_1 : + MUX_initiator_reqF_cntr_r$write_1__VAL_2 ; + assign initiator_reqF_cntr_r$EN = WILL_FIRE_RL_initiator_reqF_incCtr || WILL_FIRE_RL_initiator_reqF_decCtr ; @@ -780,7 +782,7 @@ module mkWciInitiator(CLK, endcase end assign initiator_reqF_q_0$EN = - WILL_FIRE_RL_initiator_reqF_incCtr && !initiator_reqF_c_r || + WILL_FIRE_RL_initiator_reqF_incCtr && !initiator_reqF_cntr_r || WILL_FIRE_RL_initiator_reqF_both || WILL_FIRE_RL_initiator_reqF_decCtr ; @@ -799,10 +801,10 @@ module mkWciInitiator(CLK, endcase end assign initiator_reqPend$EN = - WILL_FIRE_RL_initFsm_action_l1112c14 && initiator_wReset_n || - WILL_FIRE_RL_initFsm_action_l1114c14 && initiator_wReset_n || - (WILL_FIRE_RL_initFsm_action_l1110c14 || - WILL_FIRE_RL_initFsm_action_l1108c14) && + WILL_FIRE_RL_initFsm_action_l1116c14 && initiator_wReset_n || + WILL_FIRE_RL_initFsm_action_l1118c14 && initiator_wReset_n || + (WILL_FIRE_RL_initFsm_action_l1114c14 || + WILL_FIRE_RL_initFsm_action_l1112c14) && initiator_wReset_n || WILL_FIRE_RL_initiator_wrkBusy && initiator_wciResponse$wget[33:32] != 2'd0 ; @@ -821,25 +823,25 @@ module mkWciInitiator(CLK, assign initiator_reqTO$EN = WILL_FIRE_RL_initiator_wrkBusy && initiator_wciResponse$wget[33:32] == 2'd0 && - !initiator_respTimr_7_ULT_1_SL_initiator_wTimeo_ETC___d283 && + !initiator_respTimr_7_ULT_1_SL_initiator_wTimeo_ETC___d40 && (initiator_reqPend == 2'd1 || initiator_reqPend == 2'd2 || initiator_reqPend == 2'd3) ; // register initiator_respTimr assign initiator_respTimr$D_IN = - initiator_reqF_c_r ? + initiator_reqF_cntr_r ? 32'd0 : MUX_initiator_respTimr$write_1__VAL_2 ; assign initiator_respTimr$EN = - WILL_FIRE_RL_initiator_wrkBusy || initiator_reqF_c_r ; + WILL_FIRE_RL_initiator_wrkBusy || initiator_reqF_cntr_r ; // register initiator_respTimrAct - assign initiator_respTimrAct$D_IN = initiator_reqF_c_r ; + assign initiator_respTimrAct$D_IN = initiator_reqF_cntr_r ; assign initiator_respTimrAct$EN = WILL_FIRE_RL_initiator_wrkBusy && - (!initiator_respTimr_7_ULT_1_SL_initiator_wTimeo_ETC___d283 || + (!initiator_respTimr_7_ULT_1_SL_initiator_wTimeo_ETC___d40 || initiator_wciResponse$wget[33:32] != 2'd0) || - initiator_reqF_c_r ; + initiator_reqF_cntr_r ; // register initiator_sThreadBusy_d assign initiator_sThreadBusy_d$D_IN = wciM0_SThreadBusy ; @@ -863,7 +865,7 @@ module mkWciInitiator(CLK, // register initiator_wReset_n assign initiator_wReset_n$D_IN = 1'd1 ; - assign initiator_wReset_n$EN = WILL_FIRE_RL_initFsm_action_l1106c14 ; + assign initiator_wReset_n$EN = WILL_FIRE_RL_initFsm_action_l1110c14 ; // register initiator_wStatus assign initiator_wStatus$D_IN = @@ -874,7 +876,7 @@ module mkWciInitiator(CLK, // register initiator_wTimeout assign initiator_wTimeout$D_IN = 5'd4 ; - assign initiator_wTimeout$EN = WILL_FIRE_RL_initFsm_action_l1106c14 ; + assign initiator_wTimeout$EN = WILL_FIRE_RL_initFsm_action_l1110c14 ; // register started assign started$D_IN = 1'd1 ; @@ -887,13 +889,13 @@ module mkWciInitiator(CLK, always@(MUX_initiator_respF$enq_1__SEL_1 or MUX_initiator_busy$write_1__SEL_2 or MUX_initiator_respF$enq_1__VAL_2 or - WILL_FIRE_RL_initFsm_action_l1106c14) + WILL_FIRE_RL_initFsm_action_l1110c14) begin case (1'b1) // synopsys parallel_case MUX_initiator_respF$enq_1__SEL_1: initiator_respF$D_IN = 34'h1C0DE4204; MUX_initiator_busy$write_1__SEL_2: initiator_respF$D_IN = MUX_initiator_respF$enq_1__VAL_2; - WILL_FIRE_RL_initFsm_action_l1106c14: + WILL_FIRE_RL_initFsm_action_l1110c14: initiator_respF$D_IN = 34'h100000000; default: initiator_respF$D_IN = 34'h2AAAAAAAA /* unspecified value */ ; endcase @@ -901,15 +903,15 @@ module mkWciInitiator(CLK, assign initiator_respF$ENQ = _dand1initiator_respF$EN_enq || WILL_FIRE_RL_initiator_wrkBusy && - (!initiator_respTimr_7_ULT_1_SL_initiator_wTimeo_ETC___d283 || + (!initiator_respTimr_7_ULT_1_SL_initiator_wTimeo_ETC___d40 || initiator_wciResponse$wget[33:32] != 2'd0) || - WILL_FIRE_RL_initFsm_action_l1106c14 ; + WILL_FIRE_RL_initFsm_action_l1110c14 ; assign initiator_respF$DEQ = + WILL_FIRE_RL_initFsm_action_l1119c5 || + WILL_FIRE_RL_initFsm_action_l1117c5 || WILL_FIRE_RL_initFsm_action_l1115c5 || WILL_FIRE_RL_initFsm_action_l1113c5 || - WILL_FIRE_RL_initFsm_action_l1111c5 || - WILL_FIRE_RL_initFsm_action_l1109c5 || - WILL_FIRE_RL_initFsm_action_l1107c5 ; + WILL_FIRE_RL_initFsm_action_l1111c5 ; assign initiator_respF$CLR = 1'b0 ; // remaining internal signals @@ -930,35 +932,35 @@ module mkWciInitiator(CLK, assign NOT_initiator_busy_5_79_AND_IF_initiator_wRese_ETC___d192 = !initiator_busy && (initiator_wReset_n ? - !initiator_reqF_c_r : + !initiator_reqF_cntr_r : initiator_respF$FULL_N) ; assign _dand1initiator_busy$EN_write = - (WILL_FIRE_RL_initFsm_action_l1114c14 || - WILL_FIRE_RL_initFsm_action_l1112c14 || - WILL_FIRE_RL_initFsm_action_l1110c14 || - WILL_FIRE_RL_initFsm_action_l1108c14) && + (WILL_FIRE_RL_initFsm_action_l1118c14 || + WILL_FIRE_RL_initFsm_action_l1116c14 || + WILL_FIRE_RL_initFsm_action_l1114c14 || + WILL_FIRE_RL_initFsm_action_l1112c14) && initiator_wReset_n ; assign _dand1initiator_respF$EN_enq = - (WILL_FIRE_RL_initFsm_action_l1114c14 || - WILL_FIRE_RL_initFsm_action_l1112c14 || - WILL_FIRE_RL_initFsm_action_l1110c14 || - WILL_FIRE_RL_initFsm_action_l1108c14) && + (WILL_FIRE_RL_initFsm_action_l1118c14 || + WILL_FIRE_RL_initFsm_action_l1116c14 || + WILL_FIRE_RL_initFsm_action_l1114c14 || + WILL_FIRE_RL_initFsm_action_l1112c14) && !initiator_wReset_n ; assign _dor1initiator_lastConfigAddr$EN_write = - WILL_FIRE_RL_initFsm_action_l1114c14 || - WILL_FIRE_RL_initFsm_action_l1112c14 ; + WILL_FIRE_RL_initFsm_action_l1118c14 || + WILL_FIRE_RL_initFsm_action_l1116c14 ; assign _dor1initiator_lastConfigBE$EN_write = - WILL_FIRE_RL_initFsm_action_l1114c14 || - WILL_FIRE_RL_initFsm_action_l1112c14 ; + WILL_FIRE_RL_initFsm_action_l1118c14 || + WILL_FIRE_RL_initFsm_action_l1116c14 ; assign initFsm_abort_whas__45_AND_initFsm_abort_wget__ETC___d231 = (initFsm_state_mkFSMstate == 4'd0 || initFsm_state_mkFSMstate == 4'd11) && (!initFsm_start_reg_1 || initFsm_state_fired) ; - assign initiator_respTimr_7_ULT_1_SL_initiator_wTimeo_ETC___d283 = - initiator_respTimr < toCount__h2563 ; - assign toCount__h2563 = 32'd1 << initiator_wTimeout ; - assign x__h25252 = { initiator_pageWindow, 20'h0 } ; - assign x__h2726 = initiator_respTimr + 32'd1 ; + assign initiator_respTimr_7_ULT_1_SL_initiator_wTimeo_ETC___d40 = + initiator_respTimr < toCount__h2495 ; + assign toCount__h2495 = 32'd1 << initiator_wTimeout ; + assign x__h25157 = { initiator_pageWindow, 20'h0 } ; + assign x__h2658 = initiator_respTimr + 32'd1 ; // handling of inlined registers @@ -980,7 +982,7 @@ module mkWciInitiator(CLK, initiator_pageWindow <= `BSV_ASSIGNMENT_DELAY 12'd0; initiator_reqERR <= `BSV_ASSIGNMENT_DELAY 3'd0; initiator_reqFAIL <= `BSV_ASSIGNMENT_DELAY 3'd0; - initiator_reqF_c_r <= `BSV_ASSIGNMENT_DELAY 1'd0; + initiator_reqF_cntr_r <= `BSV_ASSIGNMENT_DELAY 1'd0; initiator_reqF_q_0 <= `BSV_ASSIGNMENT_DELAY 72'h0000000000AAAAAAAA; initiator_reqPend <= `BSV_ASSIGNMENT_DELAY 2'd0; initiator_reqTO <= `BSV_ASSIGNMENT_DELAY 3'd0; @@ -1034,8 +1036,9 @@ module mkWciInitiator(CLK, initiator_reqERR <= `BSV_ASSIGNMENT_DELAY initiator_reqERR$D_IN; if (initiator_reqFAIL$EN) initiator_reqFAIL <= `BSV_ASSIGNMENT_DELAY initiator_reqFAIL$D_IN; - if (initiator_reqF_c_r$EN) - initiator_reqF_c_r <= `BSV_ASSIGNMENT_DELAY initiator_reqF_c_r$D_IN; + if (initiator_reqF_cntr_r$EN) + initiator_reqF_cntr_r <= `BSV_ASSIGNMENT_DELAY + initiator_reqF_cntr_r$D_IN; if (initiator_reqF_q_0$EN) initiator_reqF_q_0 <= `BSV_ASSIGNMENT_DELAY initiator_reqF_q_0$D_IN; if (initiator_reqPend$EN) @@ -1089,7 +1092,7 @@ module mkWciInitiator(CLK, initiator_pageWindow = 12'hAAA; initiator_reqERR = 3'h2; initiator_reqFAIL = 3'h2; - initiator_reqF_c_r = 1'h0; + initiator_reqF_cntr_r = 1'h0; initiator_reqF_q_0 = 72'hAAAAAAAAAAAAAAAAAA; initiator_reqPend = 2'h2; initiator_reqTO = 3'h2; @@ -1115,296 +1118,296 @@ module mkWciInitiator(CLK, begin #0; if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_initFsm_action_l1107c5) + if (WILL_FIRE_RL_initFsm_action_l1111c5) begin - v__h23185 = $time; + v__h23090 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_initFsm_action_l1107c5) + if (WILL_FIRE_RL_initFsm_action_l1111c5) $display("[%0d]: %m: WCI Initiator received response %0x", - v__h23185, + v__h23090, initiator_respF$D_OUT[31:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_initFsm_action_l1108c14) + if (WILL_FIRE_RL_initFsm_action_l1112c14) begin - v__h23475 = $time; + v__h23380 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_initFsm_action_l1108c14) - $display("[%0d]: %m: WORKER CONTROL ARM...", v__h23475); + if (WILL_FIRE_RL_initFsm_action_l1112c14) + $display("[%0d]: %m: WORKER CONTROL ARM...", v__h23380); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_initFsm_action_l1109c5) + if (WILL_FIRE_RL_initFsm_action_l1113c5) begin - v__h23971 = $time; + v__h23876 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_initFsm_action_l1109c5) + if (WILL_FIRE_RL_initFsm_action_l1113c5) $display("[%0d]: %m: WCI Initiator received response %0x", - v__h23971, + v__h23876, initiator_respF$D_OUT[31:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_initFsm_action_l1110c14) + if (WILL_FIRE_RL_initFsm_action_l1114c14) begin - v__h24273 = $time; + v__h24178 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_initFsm_action_l1110c14) - $display("[%0d]: %m: WORKER CONTROL ARM...", v__h24273); + if (WILL_FIRE_RL_initFsm_action_l1114c14) + $display("[%0d]: %m: WORKER CONTROL ARM...", v__h24178); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_initFsm_action_l1111c5) + if (WILL_FIRE_RL_initFsm_action_l1115c5) begin - v__h24777 = $time; + v__h24682 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_initFsm_action_l1111c5) + if (WILL_FIRE_RL_initFsm_action_l1115c5) $display("[%0d]: %m: WCI Initiator received response %0x", - v__h24777, + v__h24682, initiator_respF$D_OUT[31:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_initFsm_action_l1113c5) + if (WILL_FIRE_RL_initFsm_action_l1117c5) begin - v__h25559 = $time; + v__h25464 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_initFsm_action_l1113c5) + if (WILL_FIRE_RL_initFsm_action_l1117c5) $display("[%0d]: %m: WCI Initiator received response %0x", - v__h25559, + v__h25464, initiator_respF$D_OUT[31:0]); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_initFsm_action_l1115c5) + if (WILL_FIRE_RL_initFsm_action_l1119c5) begin - v__h26363 = $time; + v__h26268 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_initFsm_action_l1115c5) + if (WILL_FIRE_RL_initFsm_action_l1119c5) $display("[%0d]: %m: WCI Initiator received response %0x", - v__h26363, + v__h26268, initiator_respF$D_OUT[31:0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_initFsm_action_l1106c14 && - (WILL_FIRE_RL_initFsm_action_l1107c5 || - WILL_FIRE_RL_initFsm_action_l1108c14 || - WILL_FIRE_RL_initFsm_action_l1109c5 || - WILL_FIRE_RL_initFsm_action_l1110c14 || - WILL_FIRE_RL_initFsm_action_l1111c5 || - WILL_FIRE_RL_initFsm_action_l1112c14 || - WILL_FIRE_RL_initFsm_action_l1113c5 || - WILL_FIRE_RL_initFsm_action_l1114c14 || - WILL_FIRE_RL_initFsm_action_l1115c5)) - $display("Error: \"bsv/wip/OCWci.bsv\", line 1106, column 14: (R0001)\n Mutually exclusive rules (from the ME sets [RL_initFsm_action_l1106c14] and\n [RL_initFsm_action_l1107c5, RL_initFsm_action_l1108c14,\n RL_initFsm_action_l1109c5, RL_initFsm_action_l1110c14,\n RL_initFsm_action_l1111c5, RL_initFsm_action_l1112c14,\n RL_initFsm_action_l1113c5, RL_initFsm_action_l1114c14,\n RL_initFsm_action_l1115c5] ) fired in the same clock cycle.\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_initFsm_action_l1107c5 && - (WILL_FIRE_RL_initFsm_action_l1108c14 || - WILL_FIRE_RL_initFsm_action_l1109c5 || - WILL_FIRE_RL_initFsm_action_l1110c14 || - WILL_FIRE_RL_initFsm_action_l1111c5 || - WILL_FIRE_RL_initFsm_action_l1112c14 || - WILL_FIRE_RL_initFsm_action_l1113c5 || - WILL_FIRE_RL_initFsm_action_l1114c14 || - WILL_FIRE_RL_initFsm_action_l1115c5)) - $display("Error: \"bsv/wip/OCWci.bsv\", line 1107, column 5: (R0001)\n Mutually exclusive rules (from the ME sets [RL_initFsm_action_l1107c5] and\n [RL_initFsm_action_l1108c14, RL_initFsm_action_l1109c5,\n RL_initFsm_action_l1110c14, RL_initFsm_action_l1111c5,\n RL_initFsm_action_l1112c14, RL_initFsm_action_l1113c5,\n RL_initFsm_action_l1114c14, RL_initFsm_action_l1115c5] ) fired in the same\n clock cycle.\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_initFsm_action_l1108c14 && - (WILL_FIRE_RL_initFsm_action_l1109c5 || - WILL_FIRE_RL_initFsm_action_l1110c14 || - WILL_FIRE_RL_initFsm_action_l1111c5 || - WILL_FIRE_RL_initFsm_action_l1112c14 || - WILL_FIRE_RL_initFsm_action_l1113c5 || - WILL_FIRE_RL_initFsm_action_l1114c14 || - WILL_FIRE_RL_initFsm_action_l1115c5)) - $display("Error: \"bsv/wip/OCWci.bsv\", line 1108, column 14: (R0001)\n Mutually exclusive rules (from the ME sets [RL_initFsm_action_l1108c14] and\n [RL_initFsm_action_l1109c5, RL_initFsm_action_l1110c14,\n RL_initFsm_action_l1111c5, RL_initFsm_action_l1112c14,\n RL_initFsm_action_l1113c5, RL_initFsm_action_l1114c14,\n RL_initFsm_action_l1115c5] ) fired in the same clock cycle.\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_initFsm_action_l1109c5 && - (WILL_FIRE_RL_initFsm_action_l1110c14 || - WILL_FIRE_RL_initFsm_action_l1111c5 || - WILL_FIRE_RL_initFsm_action_l1112c14 || - WILL_FIRE_RL_initFsm_action_l1113c5 || - WILL_FIRE_RL_initFsm_action_l1114c14 || - WILL_FIRE_RL_initFsm_action_l1115c5)) - $display("Error: \"bsv/wip/OCWci.bsv\", line 1109, column 5: (R0001)\n Mutually exclusive rules (from the ME sets [RL_initFsm_action_l1109c5] and\n [RL_initFsm_action_l1110c14, RL_initFsm_action_l1111c5,\n RL_initFsm_action_l1112c14, RL_initFsm_action_l1113c5,\n RL_initFsm_action_l1114c14, RL_initFsm_action_l1115c5] ) fired in the same\n clock cycle.\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_initFsm_action_l1110c14 && (WILL_FIRE_RL_initFsm_action_l1111c5 || WILL_FIRE_RL_initFsm_action_l1112c14 || WILL_FIRE_RL_initFsm_action_l1113c5 || WILL_FIRE_RL_initFsm_action_l1114c14 || - WILL_FIRE_RL_initFsm_action_l1115c5)) - $display("Error: \"bsv/wip/OCWci.bsv\", line 1110, column 14: (R0001)\n Mutually exclusive rules (from the ME sets [RL_initFsm_action_l1110c14] and\n [RL_initFsm_action_l1111c5, RL_initFsm_action_l1112c14,\n RL_initFsm_action_l1113c5, RL_initFsm_action_l1114c14,\n RL_initFsm_action_l1115c5] ) fired in the same clock cycle.\n"); + WILL_FIRE_RL_initFsm_action_l1115c5 || + WILL_FIRE_RL_initFsm_action_l1116c14 || + WILL_FIRE_RL_initFsm_action_l1117c5 || + WILL_FIRE_RL_initFsm_action_l1118c14 || + WILL_FIRE_RL_initFsm_action_l1119c5)) + $display("Error: \"bsv/wip/OCWci.bsv\", line 1110, column 14: (R0001)\n Mutually exclusive rules (from the ME sets [RL_initFsm_action_l1110c14] and\n [RL_initFsm_action_l1111c5, RL_initFsm_action_l1112c14,\n RL_initFsm_action_l1113c5, RL_initFsm_action_l1114c14,\n RL_initFsm_action_l1115c5, RL_initFsm_action_l1116c14,\n RL_initFsm_action_l1117c5, RL_initFsm_action_l1118c14,\n RL_initFsm_action_l1119c5] ) fired in the same clock cycle.\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_initFsm_action_l1111c5 && (WILL_FIRE_RL_initFsm_action_l1112c14 || WILL_FIRE_RL_initFsm_action_l1113c5 || WILL_FIRE_RL_initFsm_action_l1114c14 || - WILL_FIRE_RL_initFsm_action_l1115c5)) - $display("Error: \"bsv/wip/OCWci.bsv\", line 1111, column 5: (R0001)\n Mutually exclusive rules (from the ME sets [RL_initFsm_action_l1111c5] and\n [RL_initFsm_action_l1112c14, RL_initFsm_action_l1113c5,\n RL_initFsm_action_l1114c14, RL_initFsm_action_l1115c5] ) fired in the same\n clock cycle.\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_initFsm_action_l1113c5 && - (WILL_FIRE_RL_initFsm_action_l1114c14 || - WILL_FIRE_RL_initFsm_action_l1115c5)) - $display("Error: \"bsv/wip/OCWci.bsv\", line 1113, column 5: (R0001)\n Mutually exclusive rules (from the ME sets [RL_initFsm_action_l1113c5] and\n [RL_initFsm_action_l1114c14, RL_initFsm_action_l1115c5] ) fired in the same\n clock cycle.\n"); + WILL_FIRE_RL_initFsm_action_l1115c5 || + WILL_FIRE_RL_initFsm_action_l1116c14 || + WILL_FIRE_RL_initFsm_action_l1117c5 || + WILL_FIRE_RL_initFsm_action_l1118c14 || + WILL_FIRE_RL_initFsm_action_l1119c5)) + $display("Error: \"bsv/wip/OCWci.bsv\", line 1111, column 5: (R0001)\n Mutually exclusive rules (from the ME sets [RL_initFsm_action_l1111c5] and\n [RL_initFsm_action_l1112c14, RL_initFsm_action_l1113c5,\n RL_initFsm_action_l1114c14, RL_initFsm_action_l1115c5,\n RL_initFsm_action_l1116c14, RL_initFsm_action_l1117c5,\n RL_initFsm_action_l1118c14, RL_initFsm_action_l1119c5] ) fired in the same\n clock cycle.\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_initFsm_action_l1112c14 && (WILL_FIRE_RL_initFsm_action_l1113c5 || WILL_FIRE_RL_initFsm_action_l1114c14 || - WILL_FIRE_RL_initFsm_action_l1115c5)) - $display("Error: \"bsv/wip/OCWci.bsv\", line 1112, column 14: (R0001)\n Mutually exclusive rules (from the ME sets [RL_initFsm_action_l1112c14] and\n [RL_initFsm_action_l1113c5, RL_initFsm_action_l1114c14,\n RL_initFsm_action_l1115c5] ) fired in the same clock cycle.\n"); + WILL_FIRE_RL_initFsm_action_l1115c5 || + WILL_FIRE_RL_initFsm_action_l1116c14 || + WILL_FIRE_RL_initFsm_action_l1117c5 || + WILL_FIRE_RL_initFsm_action_l1118c14 || + WILL_FIRE_RL_initFsm_action_l1119c5)) + $display("Error: \"bsv/wip/OCWci.bsv\", line 1112, column 14: (R0001)\n Mutually exclusive rules (from the ME sets [RL_initFsm_action_l1112c14] and\n [RL_initFsm_action_l1113c5, RL_initFsm_action_l1114c14,\n RL_initFsm_action_l1115c5, RL_initFsm_action_l1116c14,\n RL_initFsm_action_l1117c5, RL_initFsm_action_l1118c14,\n RL_initFsm_action_l1119c5] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_initFsm_action_l1113c5 && + (WILL_FIRE_RL_initFsm_action_l1114c14 || + WILL_FIRE_RL_initFsm_action_l1115c5 || + WILL_FIRE_RL_initFsm_action_l1116c14 || + WILL_FIRE_RL_initFsm_action_l1117c5 || + WILL_FIRE_RL_initFsm_action_l1118c14 || + WILL_FIRE_RL_initFsm_action_l1119c5)) + $display("Error: \"bsv/wip/OCWci.bsv\", line 1113, column 5: (R0001)\n Mutually exclusive rules (from the ME sets [RL_initFsm_action_l1113c5] and\n [RL_initFsm_action_l1114c14, RL_initFsm_action_l1115c5,\n RL_initFsm_action_l1116c14, RL_initFsm_action_l1117c5,\n RL_initFsm_action_l1118c14, RL_initFsm_action_l1119c5] ) fired in the same\n clock cycle.\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_initFsm_action_l1114c14 && - WILL_FIRE_RL_initFsm_action_l1115c5) - $display("Error: \"bsv/wip/OCWci.bsv\", line 1114, column 14: (R0001)\n Mutually exclusive rules (from the ME sets [RL_initFsm_action_l1114c14] and\n [RL_initFsm_action_l1115c5] ) fired in the same clock cycle.\n"); + (WILL_FIRE_RL_initFsm_action_l1115c5 || + WILL_FIRE_RL_initFsm_action_l1116c14 || + WILL_FIRE_RL_initFsm_action_l1117c5 || + WILL_FIRE_RL_initFsm_action_l1118c14 || + WILL_FIRE_RL_initFsm_action_l1119c5)) + $display("Error: \"bsv/wip/OCWci.bsv\", line 1114, column 14: (R0001)\n Mutually exclusive rules (from the ME sets [RL_initFsm_action_l1114c14] and\n [RL_initFsm_action_l1115c5, RL_initFsm_action_l1116c14,\n RL_initFsm_action_l1117c5, RL_initFsm_action_l1118c14,\n RL_initFsm_action_l1119c5] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_initFsm_action_l1115c5 && + (WILL_FIRE_RL_initFsm_action_l1116c14 || + WILL_FIRE_RL_initFsm_action_l1117c5 || + WILL_FIRE_RL_initFsm_action_l1118c14 || + WILL_FIRE_RL_initFsm_action_l1119c5)) + $display("Error: \"bsv/wip/OCWci.bsv\", line 1115, column 5: (R0001)\n Mutually exclusive rules (from the ME sets [RL_initFsm_action_l1115c5] and\n [RL_initFsm_action_l1116c14, RL_initFsm_action_l1117c5,\n RL_initFsm_action_l1118c14, RL_initFsm_action_l1119c5] ) fired in the same\n clock cycle.\n"); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_initFsm_action_l1105c5) + if (WILL_FIRE_RL_initFsm_action_l1117c5 && + (WILL_FIRE_RL_initFsm_action_l1118c14 || + WILL_FIRE_RL_initFsm_action_l1119c5)) + $display("Error: \"bsv/wip/OCWci.bsv\", line 1117, column 5: (R0001)\n Mutually exclusive rules (from the ME sets [RL_initFsm_action_l1117c5] and\n [RL_initFsm_action_l1118c14, RL_initFsm_action_l1119c5] ) fired in the same\n clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_initFsm_action_l1116c14 && + (WILL_FIRE_RL_initFsm_action_l1117c5 || + WILL_FIRE_RL_initFsm_action_l1118c14 || + WILL_FIRE_RL_initFsm_action_l1119c5)) + $display("Error: \"bsv/wip/OCWci.bsv\", line 1116, column 14: (R0001)\n Mutually exclusive rules (from the ME sets [RL_initFsm_action_l1116c14] and\n [RL_initFsm_action_l1117c5, RL_initFsm_action_l1118c14,\n RL_initFsm_action_l1119c5] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_initFsm_action_l1118c14 && + WILL_FIRE_RL_initFsm_action_l1119c5) + $display("Error: \"bsv/wip/OCWci.bsv\", line 1118, column 14: (R0001)\n Mutually exclusive rules (from the ME sets [RL_initFsm_action_l1118c14] and\n [RL_initFsm_action_l1119c5] ) fired in the same clock cycle.\n"); + if (RST_N != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_initFsm_action_l1109c5) begin - v__h22397 = $time; + v__h22302 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_initFsm_action_l1105c5) + if (WILL_FIRE_RL_initFsm_action_l1109c5) $display("[%0d]: %m: WCI Initiator Taking Worker out of Reset...", - v__h22397); + v__h22302); if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_initFsm_action_l1105c5 && - (WILL_FIRE_RL_initFsm_action_l1106c14 || - WILL_FIRE_RL_initFsm_action_l1107c5 || - WILL_FIRE_RL_initFsm_action_l1108c14 || - WILL_FIRE_RL_initFsm_action_l1109c5 || - WILL_FIRE_RL_initFsm_action_l1110c14 || + if (WILL_FIRE_RL_initFsm_action_l1109c5 && + (WILL_FIRE_RL_initFsm_action_l1110c14 || WILL_FIRE_RL_initFsm_action_l1111c5 || WILL_FIRE_RL_initFsm_action_l1112c14 || WILL_FIRE_RL_initFsm_action_l1113c5 || WILL_FIRE_RL_initFsm_action_l1114c14 || - WILL_FIRE_RL_initFsm_action_l1115c5)) - $display("Error: \"bsv/wip/OCWci.bsv\", line 1105, column 5: (R0001)\n Mutually exclusive rules (from the ME sets [RL_initFsm_action_l1105c5] and\n [RL_initFsm_action_l1106c14, RL_initFsm_action_l1107c5,\n RL_initFsm_action_l1108c14, RL_initFsm_action_l1109c5,\n RL_initFsm_action_l1110c14, RL_initFsm_action_l1111c5,\n RL_initFsm_action_l1112c14, RL_initFsm_action_l1113c5,\n RL_initFsm_action_l1114c14, RL_initFsm_action_l1115c5] ) fired in the same\n clock cycle.\n"); + WILL_FIRE_RL_initFsm_action_l1115c5 || + WILL_FIRE_RL_initFsm_action_l1116c14 || + WILL_FIRE_RL_initFsm_action_l1117c5 || + WILL_FIRE_RL_initFsm_action_l1118c14 || + WILL_FIRE_RL_initFsm_action_l1119c5)) + $display("Error: \"bsv/wip/OCWci.bsv\", line 1109, column 5: (R0001)\n Mutually exclusive rules (from the ME sets [RL_initFsm_action_l1109c5] and\n [RL_initFsm_action_l1110c14, RL_initFsm_action_l1111c5,\n RL_initFsm_action_l1112c14, RL_initFsm_action_l1113c5,\n RL_initFsm_action_l1114c14, RL_initFsm_action_l1115c5,\n RL_initFsm_action_l1116c14, RL_initFsm_action_l1117c5,\n RL_initFsm_action_l1118c14, RL_initFsm_action_l1119c5] ) fired in the same\n clock cycle.\n"); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_initiator_wrkBusy && initiator_wciResponse$wget[33:32] == 2'd0 && - !initiator_respTimr_7_ULT_1_SL_initiator_wTimeo_ETC___d283 && + !initiator_respTimr_7_ULT_1_SL_initiator_wTimeo_ETC___d40 && initiator_reqPend == 2'd1) begin - v__h2868 = $time; + v__h2800 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_initiator_wrkBusy && initiator_wciResponse$wget[33:32] == 2'd0 && - !initiator_respTimr_7_ULT_1_SL_initiator_wTimeo_ETC___d283 && + !initiator_respTimr_7_ULT_1_SL_initiator_wTimeo_ETC___d40 && initiator_reqPend == 2'd1) - $display("[%0d]: %m: WORKER CONFIG-WRITE TIMEOUT", v__h2868); + $display("[%0d]: %m: WORKER CONFIG-WRITE TIMEOUT", v__h2800); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_initiator_wrkBusy && initiator_wciResponse$wget[33:32] == 2'd0 && - !initiator_respTimr_7_ULT_1_SL_initiator_wTimeo_ETC___d283 && + !initiator_respTimr_7_ULT_1_SL_initiator_wTimeo_ETC___d40 && initiator_reqPend == 2'd2) begin - v__h2958 = $time; + v__h2890 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_initiator_wrkBusy && initiator_wciResponse$wget[33:32] == 2'd0 && - !initiator_respTimr_7_ULT_1_SL_initiator_wTimeo_ETC___d283 && + !initiator_respTimr_7_ULT_1_SL_initiator_wTimeo_ETC___d40 && initiator_reqPend == 2'd2) - $display("[%0d]: %m: WORKER CONFIG-READ TIMEOUT", v__h2958); + $display("[%0d]: %m: WORKER CONFIG-READ TIMEOUT", v__h2890); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_initiator_wrkBusy && initiator_wciResponse$wget[33:32] == 2'd0 && - !initiator_respTimr_7_ULT_1_SL_initiator_wTimeo_ETC___d283 && + !initiator_respTimr_7_ULT_1_SL_initiator_wTimeo_ETC___d40 && initiator_reqPend == 2'd3) begin - v__h3047 = $time; + v__h2979 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_initiator_wrkBusy && initiator_wciResponse$wget[33:32] == 2'd0 && - !initiator_respTimr_7_ULT_1_SL_initiator_wTimeo_ETC___d283 && + !initiator_respTimr_7_ULT_1_SL_initiator_wTimeo_ETC___d40 && initiator_reqPend == 2'd3) - $display("[%0d]: %m: WORKER CONTROL-OP TIMEOUT", v__h3047); + $display("[%0d]: %m: WORKER CONTROL-OP TIMEOUT", v__h2979); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_initiator_wrkBusy && initiator_wciResponse$wget[33:32] == 2'd2 && initiator_reqPend == 2'd1) begin - v__h3280 = $time; + v__h3212 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_initiator_wrkBusy && initiator_wciResponse$wget[33:32] == 2'd2 && initiator_reqPend == 2'd1) - $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-FAIL", v__h3280); + $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-FAIL", v__h3212); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_initiator_wrkBusy && initiator_wciResponse$wget[33:32] == 2'd2 && initiator_reqPend == 2'd2) begin - v__h3370 = $time; + v__h3302 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_initiator_wrkBusy && initiator_wciResponse$wget[33:32] == 2'd2 && initiator_reqPend == 2'd2) - $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-FAIL", v__h3370); + $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-FAIL", v__h3302); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_initiator_wrkBusy && initiator_wciResponse$wget[33:32] == 2'd2 && initiator_reqPend == 2'd3) begin - v__h3459 = $time; + v__h3391 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_initiator_wrkBusy && initiator_wciResponse$wget[33:32] == 2'd2 && initiator_reqPend == 2'd3) - $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-FAIL", v__h3459); + $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-FAIL", v__h3391); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_initiator_wrkBusy && initiator_wciResponse$wget[33:32] == 2'd3 && initiator_reqPend == 2'd1) begin - v__h3697 = $time; + v__h3629 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_initiator_wrkBusy && initiator_wciResponse$wget[33:32] == 2'd3 && initiator_reqPend == 2'd1) - $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-ERR", v__h3697); + $display("[%0d]: %m: WORKER CONFIG-WRITE RESPONSE-ERR", v__h3629); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_initiator_wrkBusy && initiator_wciResponse$wget[33:32] == 2'd3 && initiator_reqPend == 2'd2) begin - v__h3787 = $time; + v__h3719 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_initiator_wrkBusy && initiator_wciResponse$wget[33:32] == 2'd3 && initiator_reqPend == 2'd2) - $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-ERR", v__h3787); + $display("[%0d]: %m: WORKER CONFIG-READ RESPONSE-ERR", v__h3719); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_initiator_wrkBusy && initiator_wciResponse$wget[33:32] == 2'd3 && initiator_reqPend == 2'd3) begin - v__h3876 = $time; + v__h3808 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_initiator_wrkBusy && initiator_wciResponse$wget[33:32] == 2'd3 && initiator_reqPend == 2'd3) - $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-ERR", v__h3876); + $display("[%0d]: %m: WORKER CONTROL-OP RESPONSE-ERR", v__h3808); end // synopsys translate_on endmodule // mkWciInitiator diff --git a/rtl/mkWciMonitor.v b/rtl/mkWciMonitor.v index 73f52dfc..adc9a87a 100644 --- a/rtl/mkWciMonitor.v +++ b/rtl/mkWciMonitor.v @@ -1,7 +1,7 @@ // -// Generated by Bluespec Compiler, version 2012.09.beta1 (build 29570, 2012-09.11) +// Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Tue Dec 11 16:19:54 EST 2012 +// On Fri Jun 21 16:57:06 EDT 2013 // // // Ports: @@ -298,10 +298,10 @@ module mkWciMonitor(CLK, reg pmsender_wsiM_peerIsReady; wire pmsender_wsiM_peerIsReady$D_IN, pmsender_wsiM_peerIsReady$EN; - // register pmsender_wsiM_reqFifo_c_r - reg [1 : 0] pmsender_wsiM_reqFifo_c_r; - wire [1 : 0] pmsender_wsiM_reqFifo_c_r$D_IN; - wire pmsender_wsiM_reqFifo_c_r$EN; + // register pmsender_wsiM_reqFifo_cntr_r + reg [1 : 0] pmsender_wsiM_reqFifo_cntr_r; + wire [1 : 0] pmsender_wsiM_reqFifo_cntr_r$D_IN; + wire pmsender_wsiM_reqFifo_cntr_r$EN; // register pmsender_wsiM_reqFifo_q_0 reg [60 : 0] pmsender_wsiM_reqFifo_q_0; @@ -363,33 +363,37 @@ module mkWciMonitor(CLK, MUX_observer_evF$enq_1__VAL_2, MUX_observer_evF$enq_1__VAL_3; wire [60 : 0] MUX_pmsender_wsiM_reqFifo_q_0$write_1__VAL_1, - MUX_pmsender_wsiM_reqFifo_q_0$write_1__VAL_2, - MUX_pmsender_wsiM_reqFifo_q_1$write_1__VAL_1; - wire [1 : 0] MUX_pmsender_wsiM_reqFifo_c_r$write_1__VAL_1, - MUX_pmsender_wsiM_reqFifo_c_r$write_1__VAL_2; + MUX_pmsender_wsiM_reqFifo_q_1$write_1__VAL_1, + MUX_pmsender_wsiM_reqFifo_q_1$write_1__VAL_2; + wire [1 : 0] MUX_pmsender_wsiM_reqFifo_cntr_r$write_1__VAL_2; wire MUX_observer_evF$enq_1__SEL_1, MUX_observer_evF$enq_1__SEL_2, + MUX_pmsender_wsiM_reqFifo_q_0$write_1__SEL_1, MUX_pmsender_wsiM_reqFifo_q_0$write_1__SEL_2, + MUX_pmsender_wsiM_reqFifo_q_1$write_1__SEL_1, MUX_pmsender_wsiM_reqFifo_q_1$write_1__SEL_2; // remaining internal signals - reg [95 : 0] CASE_observer_evFD_OUT_BITS_98_TO_96_observer_ETC__q10; - reg [63 : 0] v__h1591, v__h1614; - reg [31 : 0] x_data__h4919; - reg [7 : 0] CASE_CASE_pmsender_evFD_OUT_BITS_98_TO_96_CASE_ETC__q5, - CASE_observer_evFD_OUT_BITS_39_TO_32_255_0_ob_ETC__q8, - CASE_observer_evFD_OUT_BITS_71_TO_64_255_0_ob_ETC__q9, - CASE_observer_evFD_OUT_BITS_7_TO_0_255_0_obse_ETC__q7, - x__h5933; - reg [4 : 0] CASE_pmsender_evFD_OUT_BITS_39_TO_32_28_0_0_1_ETC__q3, - CASE_pmsender_evFD_OUT_BITS_71_TO_64_28_0_0_1_ETC__q1, - CASE_pmsender_evFD_OUT_BITS_7_TO_0_28_0_0_1_1_ETC__q2, - CASE_pmsender_evFD_OUT_BITS_98_TO_96_CASE_pms_ETC__q4; - reg [2 : 0] CASE_observer_evFD_OUT_BITS_98_TO_96_5_0_obse_ETC__q6, - len__h4848; - wire [31 : 0] monId_CONCAT_IF_IF_pmsender_evF_first__30_BITS_ETC___d381; - wire [11 : 0] x_burstLength__h4918; - wire pmsender_idx_29_EQ_IF_pmsender_evF_first__30_B_ETC___d603; + reg [95 : 0] CASE_observer_evFD_OUT_BITS_98_TO_96_0_0xAAAA_ETC__q10; + reg [63 : 0] v__h1590, v__h1613; + reg [31 : 0] x_data__h4786; + reg [7 : 0] CASE_CASE_pmsender_evFD_OUT_BITS_98_TO_96_0_CA_ETC__q5, + CASE_observer_evFD_OUT_BITS_39_TO_32_0_observ_ETC__q9, + CASE_observer_evFD_OUT_BITS_71_TO_64_0_observ_ETC__q6, + CASE_observer_evFD_OUT_BITS_7_TO_0_0_observer_ETC__q8, + x__h5780; + reg [4 : 0] CASE_pmsender_evFD_OUT_BITS_39_TO_32_0_0_1_1__ETC__q3, + CASE_pmsender_evFD_OUT_BITS_71_TO_64_0_0_1_1__ETC__q1, + CASE_pmsender_evFD_OUT_BITS_7_TO_0_0_0_1_1_2__ETC__q2, + CASE_pmsender_evFD_OUT_BITS_98_TO_96_0_CASE_p_ETC__q4; + reg [2 : 0] CASE_observer_evFD_OUT_BITS_98_TO_96_0_observ_ETC__q7, + len__h4717; + wire [95 : 0] DONTCARE_CONCAT_IF_observer_evF_first__00_BITS_ETC___d588; + wire [11 : 0] x_burstLength__h4785; + wire [1 : 0] pmsender_wsiM_reqFifo_cntr_r_7_MINUS_1___d67; + wire _dfoo1, + _dfoo3, + pmsender_idx_27_EQ_IF_pmsender_evF_first__28_B_ETC___d136; // value method pmem_mCmd assign pmem_MCmd = @@ -473,19 +477,16 @@ module mkWciMonitor(CLK, // rule RL_pmsender_serialize_message assign WILL_FIRE_RL_pmsender_serialize_message = - pmsender_wsiM_reqFifo_c_r != 2'd2 && pmsender_evF$EMPTY_N ; + pmsender_wsiM_reqFifo_cntr_r != 2'd2 && pmsender_evF$EMPTY_N ; // rule RL_pmsender_wsiM_reqFifo_deq assign WILL_FIRE_RL_pmsender_wsiM_reqFifo_deq = - pmsender_wsiM_reqFifo_c_r != 2'd0 && + pmsender_wsiM_reqFifo_cntr_r != 2'd0 && !pmsender_wsiM_sThreadBusy_d ; // rule RL_pmsender_wsiM_reqFifo_incCtr assign WILL_FIRE_RL_pmsender_wsiM_reqFifo_incCtr = - ((pmsender_wsiM_reqFifo_c_r == 2'd0) ? - WILL_FIRE_RL_pmsender_serialize_message : - pmsender_wsiM_reqFifo_c_r != 2'd1 || - WILL_FIRE_RL_pmsender_serialize_message) && + WILL_FIRE_RL_pmsender_serialize_message && WILL_FIRE_RL_pmsender_serialize_message && !WILL_FIRE_RL_pmsender_wsiM_reqFifo_deq ; @@ -496,10 +497,7 @@ module mkWciMonitor(CLK, // rule RL_pmsender_wsiM_reqFifo_both assign WILL_FIRE_RL_pmsender_wsiM_reqFifo_both = - ((pmsender_wsiM_reqFifo_c_r == 2'd1) ? - WILL_FIRE_RL_pmsender_serialize_message : - pmsender_wsiM_reqFifo_c_r != 2'd2 || - WILL_FIRE_RL_pmsender_serialize_message) && + WILL_FIRE_RL_pmsender_serialize_message && WILL_FIRE_RL_pmsender_wsiM_reqFifo_deq && WILL_FIRE_RL_pmsender_serialize_message ; @@ -510,12 +508,16 @@ module mkWciMonitor(CLK, assign MUX_observer_evF$enq_1__SEL_2 = WILL_FIRE_RL_observer_request_detected && (observer_r_mCmd == 3'd1 || observer_r_mCmd == 3'd2) ; + assign MUX_pmsender_wsiM_reqFifo_q_0$write_1__SEL_1 = + WILL_FIRE_RL_pmsender_wsiM_reqFifo_both && _dfoo3 ; assign MUX_pmsender_wsiM_reqFifo_q_0$write_1__SEL_2 = WILL_FIRE_RL_pmsender_wsiM_reqFifo_incCtr && - pmsender_wsiM_reqFifo_c_r == 2'd0 ; + pmsender_wsiM_reqFifo_cntr_r == 2'd0 ; + assign MUX_pmsender_wsiM_reqFifo_q_1$write_1__SEL_1 = + WILL_FIRE_RL_pmsender_wsiM_reqFifo_both && _dfoo1 ; assign MUX_pmsender_wsiM_reqFifo_q_1$write_1__SEL_2 = WILL_FIRE_RL_pmsender_wsiM_reqFifo_incCtr && - pmsender_wsiM_reqFifo_c_r == 2'd1 ; + pmsender_wsiM_reqFifo_cntr_r == 2'd1 ; assign MUX_observer_evF$enq_1__VAL_1 = { 59'h1AAAAAAAAAAAAAA, observer_readInFlight ? 8'd64 : 8'd48, @@ -527,31 +529,29 @@ module mkWciMonitor(CLK, assign MUX_observer_evF$enq_1__VAL_3 = { 91'h0AAAAAAAAAAAAAAAAAAAAAA, observer_r_mResetn ? 8'd1 : 8'd2 } ; - assign MUX_pmsender_wsiM_reqFifo_c_r$write_1__VAL_1 = - pmsender_wsiM_reqFifo_c_r + 2'd1 ; - assign MUX_pmsender_wsiM_reqFifo_c_r$write_1__VAL_2 = - pmsender_wsiM_reqFifo_c_r - 2'd1 ; + assign MUX_pmsender_wsiM_reqFifo_cntr_r$write_1__VAL_2 = + pmsender_wsiM_reqFifo_cntr_r + 2'd1 ; assign MUX_pmsender_wsiM_reqFifo_q_0$write_1__VAL_1 = - (pmsender_wsiM_reqFifo_c_r == 2'd1) ? - MUX_pmsender_wsiM_reqFifo_q_0$write_1__VAL_2 : + (pmsender_wsiM_reqFifo_cntr_r == 2'd1) ? + MUX_pmsender_wsiM_reqFifo_q_1$write_1__VAL_2 : pmsender_wsiM_reqFifo_q_1 ; - assign MUX_pmsender_wsiM_reqFifo_q_0$write_1__VAL_2 = + assign MUX_pmsender_wsiM_reqFifo_q_1$write_1__VAL_1 = + (pmsender_wsiM_reqFifo_cntr_r == 2'd2) ? + MUX_pmsender_wsiM_reqFifo_q_1$write_1__VAL_2 : + 61'h00000AAAAAAAAA00 ; + assign MUX_pmsender_wsiM_reqFifo_q_1$write_1__VAL_2 = { 3'd1, - pmsender_idx_29_EQ_IF_pmsender_evF_first__30_B_ETC___d603, + pmsender_idx_27_EQ_IF_pmsender_evF_first__28_B_ETC___d136, 1'd0, - x_burstLength__h4918, - x_data__h4919, + x_burstLength__h4785, + x_data__h4786, 12'd3840 } ; - assign MUX_pmsender_wsiM_reqFifo_q_1$write_1__VAL_1 = - (pmsender_wsiM_reqFifo_c_r == 2'd2) ? - MUX_pmsender_wsiM_reqFifo_q_0$write_1__VAL_2 : - 61'h00000AAAAAAAAA00 ; // inlined wires assign observer_r_sThreadBusy_1$wget = 1'b1 ; assign observer_r_sThreadBusy_1$whas = observe_SThreadBusy ; assign pmsender_wsiM_reqFifo_x_wire$wget = - MUX_pmsender_wsiM_reqFifo_q_0$write_1__VAL_2 ; + MUX_pmsender_wsiM_reqFifo_q_1$write_1__VAL_2 ; assign pmsender_wsiM_reqFifo_x_wire$whas = WILL_FIRE_RL_pmsender_serialize_message ; assign pmsender_wsiM_operateD_1$wget = 1'd1 ; @@ -634,7 +634,7 @@ module mkWciMonitor(CLK, // register pmsender_idx assign pmsender_idx$D_IN = - pmsender_idx_29_EQ_IF_pmsender_evF_first__30_B_ETC___d603 ? + pmsender_idx_27_EQ_IF_pmsender_evF_first__28_B_ETC___d136 ? 3'd1 : pmsender_idx + 3'd1 ; assign pmsender_idx$EN = WILL_FIRE_RL_pmsender_serialize_message ; @@ -647,7 +647,7 @@ module mkWciMonitor(CLK, assign pmsender_srcTag$D_IN = pmsender_srcTag + 8'd1 ; assign pmsender_srcTag$EN = WILL_FIRE_RL_pmsender_serialize_message && - pmsender_idx_29_EQ_IF_pmsender_evF_first__30_B_ETC___d603 ; + pmsender_idx_27_EQ_IF_pmsender_evF_first__28_B_ETC___d136 ; // register pmsender_wsiM_burstKind assign pmsender_wsiM_burstKind$D_IN = @@ -695,30 +695,30 @@ module mkWciMonitor(CLK, assign pmsender_wsiM_peerIsReady$D_IN = pmem_SReset_n ; assign pmsender_wsiM_peerIsReady$EN = 1'd1 ; - // register pmsender_wsiM_reqFifo_c_r - assign pmsender_wsiM_reqFifo_c_r$D_IN = - WILL_FIRE_RL_pmsender_wsiM_reqFifo_incCtr ? - MUX_pmsender_wsiM_reqFifo_c_r$write_1__VAL_1 : - MUX_pmsender_wsiM_reqFifo_c_r$write_1__VAL_2 ; - assign pmsender_wsiM_reqFifo_c_r$EN = - WILL_FIRE_RL_pmsender_wsiM_reqFifo_incCtr || - WILL_FIRE_RL_pmsender_wsiM_reqFifo_decCtr ; + // register pmsender_wsiM_reqFifo_cntr_r + assign pmsender_wsiM_reqFifo_cntr_r$D_IN = + WILL_FIRE_RL_pmsender_wsiM_reqFifo_decCtr ? + pmsender_wsiM_reqFifo_cntr_r_7_MINUS_1___d67 : + MUX_pmsender_wsiM_reqFifo_cntr_r$write_1__VAL_2 ; + assign pmsender_wsiM_reqFifo_cntr_r$EN = + WILL_FIRE_RL_pmsender_wsiM_reqFifo_decCtr || + WILL_FIRE_RL_pmsender_wsiM_reqFifo_incCtr ; // register pmsender_wsiM_reqFifo_q_0 - always@(WILL_FIRE_RL_pmsender_wsiM_reqFifo_both or + always@(MUX_pmsender_wsiM_reqFifo_q_0$write_1__SEL_1 or MUX_pmsender_wsiM_reqFifo_q_0$write_1__VAL_1 or MUX_pmsender_wsiM_reqFifo_q_0$write_1__SEL_2 or - MUX_pmsender_wsiM_reqFifo_q_0$write_1__VAL_2 or + MUX_pmsender_wsiM_reqFifo_q_1$write_1__VAL_2 or WILL_FIRE_RL_pmsender_wsiM_reqFifo_decCtr or pmsender_wsiM_reqFifo_q_1) begin case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_pmsender_wsiM_reqFifo_both: + MUX_pmsender_wsiM_reqFifo_q_0$write_1__SEL_1: pmsender_wsiM_reqFifo_q_0$D_IN = MUX_pmsender_wsiM_reqFifo_q_0$write_1__VAL_1; MUX_pmsender_wsiM_reqFifo_q_0$write_1__SEL_2: pmsender_wsiM_reqFifo_q_0$D_IN = - MUX_pmsender_wsiM_reqFifo_q_0$write_1__VAL_2; + MUX_pmsender_wsiM_reqFifo_q_1$write_1__VAL_2; WILL_FIRE_RL_pmsender_wsiM_reqFifo_decCtr: pmsender_wsiM_reqFifo_q_0$D_IN = pmsender_wsiM_reqFifo_q_1; default: pmsender_wsiM_reqFifo_q_0$D_IN = @@ -726,25 +726,25 @@ module mkWciMonitor(CLK, endcase end assign pmsender_wsiM_reqFifo_q_0$EN = - WILL_FIRE_RL_pmsender_wsiM_reqFifo_both || + WILL_FIRE_RL_pmsender_wsiM_reqFifo_both && _dfoo3 || WILL_FIRE_RL_pmsender_wsiM_reqFifo_incCtr && - pmsender_wsiM_reqFifo_c_r == 2'd0 || + pmsender_wsiM_reqFifo_cntr_r == 2'd0 || WILL_FIRE_RL_pmsender_wsiM_reqFifo_decCtr ; // register pmsender_wsiM_reqFifo_q_1 - always@(WILL_FIRE_RL_pmsender_wsiM_reqFifo_both or + always@(MUX_pmsender_wsiM_reqFifo_q_1$write_1__SEL_1 or MUX_pmsender_wsiM_reqFifo_q_1$write_1__VAL_1 or MUX_pmsender_wsiM_reqFifo_q_1$write_1__SEL_2 or - MUX_pmsender_wsiM_reqFifo_q_0$write_1__VAL_2 or + MUX_pmsender_wsiM_reqFifo_q_1$write_1__VAL_2 or WILL_FIRE_RL_pmsender_wsiM_reqFifo_decCtr) begin case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_pmsender_wsiM_reqFifo_both: + MUX_pmsender_wsiM_reqFifo_q_1$write_1__SEL_1: pmsender_wsiM_reqFifo_q_1$D_IN = MUX_pmsender_wsiM_reqFifo_q_1$write_1__VAL_1; MUX_pmsender_wsiM_reqFifo_q_1$write_1__SEL_2: pmsender_wsiM_reqFifo_q_1$D_IN = - MUX_pmsender_wsiM_reqFifo_q_0$write_1__VAL_2; + MUX_pmsender_wsiM_reqFifo_q_1$write_1__VAL_2; WILL_FIRE_RL_pmsender_wsiM_reqFifo_decCtr: pmsender_wsiM_reqFifo_q_1$D_IN = 61'h00000AAAAAAAAA00; default: pmsender_wsiM_reqFifo_q_1$D_IN = @@ -752,9 +752,9 @@ module mkWciMonitor(CLK, endcase end assign pmsender_wsiM_reqFifo_q_1$EN = - WILL_FIRE_RL_pmsender_wsiM_reqFifo_both || + WILL_FIRE_RL_pmsender_wsiM_reqFifo_both && _dfoo1 || WILL_FIRE_RL_pmsender_wsiM_reqFifo_incCtr && - pmsender_wsiM_reqFifo_c_r == 2'd1 || + pmsender_wsiM_reqFifo_cntr_r == 2'd1 || WILL_FIRE_RL_pmsender_wsiM_reqFifo_decCtr ; // register pmsender_wsiM_sThreadBusy_d @@ -815,224 +815,227 @@ module mkWciMonitor(CLK, // submodule pmsender_evF assign pmsender_evF$D_IN = - { CASE_observer_evFD_OUT_BITS_98_TO_96_5_0_obse_ETC__q6, - CASE_observer_evFD_OUT_BITS_98_TO_96_observer_ETC__q10 } ; + { CASE_observer_evFD_OUT_BITS_98_TO_96_0_observ_ETC__q7, + CASE_observer_evFD_OUT_BITS_98_TO_96_0_0xAAAA_ETC__q10 } ; assign pmsender_evF$ENQ = observer_evF$EMPTY_N && pmsender_evF$FULL_N ; assign pmsender_evF$DEQ = WILL_FIRE_RL_pmsender_serialize_message && - pmsender_idx_29_EQ_IF_pmsender_evF_first__30_B_ETC___d603 ; + pmsender_idx_27_EQ_IF_pmsender_evF_first__28_B_ETC___d136 ; assign pmsender_evF$CLR = 1'b0 ; // remaining internal signals - assign monId_CONCAT_IF_IF_pmsender_evF_first__30_BITS_ETC___d381 = - { monId, - CASE_CASE_pmsender_evFD_OUT_BITS_98_TO_96_CASE_ETC__q5, - pmsender_srcTag, - x__h5933 } ; - assign pmsender_idx_29_EQ_IF_pmsender_evF_first__30_B_ETC___d603 = - pmsender_idx == len__h4848 ; - assign x_burstLength__h4918 = { 9'd0, len__h4848 } ; + assign DONTCARE_CONCAT_IF_observer_evF_first__00_BITS_ETC___d588 = + { 24'hAAAAAA, + CASE_observer_evFD_OUT_BITS_71_TO_64_0_observ_ETC__q6, + observer_evF$D_OUT[63:0] } ; + assign _dfoo1 = + pmsender_wsiM_reqFifo_cntr_r != 2'd2 || + pmsender_wsiM_reqFifo_cntr_r_7_MINUS_1___d67 == 2'd1 ; + assign _dfoo3 = + pmsender_wsiM_reqFifo_cntr_r != 2'd1 || + pmsender_wsiM_reqFifo_cntr_r_7_MINUS_1___d67 == 2'd0 ; + assign pmsender_idx_27_EQ_IF_pmsender_evF_first__28_B_ETC___d136 = + pmsender_idx == len__h4717 ; + assign pmsender_wsiM_reqFifo_cntr_r_7_MINUS_1___d67 = + pmsender_wsiM_reqFifo_cntr_r - 2'd1 ; + assign x_burstLength__h4785 = { 9'd0, len__h4717 } ; always@(pmsender_evF$D_OUT) begin case (pmsender_evF$D_OUT[98:96]) - 3'd0: len__h4848 = 3'd1; - 3'd1: len__h4848 = 3'd2; - 3'd2: len__h4848 = 3'd3; - default: len__h4848 = 3'd7; + 3'd0: len__h4717 = 3'd1; + 3'd1: len__h4717 = 3'd2; + 3'd2: len__h4717 = 3'd3; + default: len__h4717 = 3'd7; endcase end always@(pmsender_evF$D_OUT) begin case (pmsender_evF$D_OUT[98:96]) - 3'd0: x__h5933 = 8'd1; - 3'd1: x__h5933 = 8'd2; - 3'd2: x__h5933 = 8'd3; - 3'd3: x__h5933 = 8'd4; - 3'd4: x__h5933 = 8'd5; - default: x__h5933 = 8'd6; + 3'd0: x__h5780 = 8'd1; + 3'd1: x__h5780 = 8'd2; + 3'd2: x__h5780 = 8'd3; + 3'd3: x__h5780 = 8'd4; + 3'd4: x__h5780 = 8'd5; + default: x__h5780 = 8'd6; endcase end always@(pmsender_evF$D_OUT) begin case (pmsender_evF$D_OUT[71:64]) - 8'd0: CASE_pmsender_evFD_OUT_BITS_71_TO_64_28_0_0_1_ETC__q1 = 5'd0; - 8'd1: CASE_pmsender_evFD_OUT_BITS_71_TO_64_28_0_0_1_ETC__q1 = 5'd1; - 8'd2: CASE_pmsender_evFD_OUT_BITS_71_TO_64_28_0_0_1_ETC__q1 = 5'd2; - 8'd3: CASE_pmsender_evFD_OUT_BITS_71_TO_64_28_0_0_1_ETC__q1 = 5'd3; - 8'd4: CASE_pmsender_evFD_OUT_BITS_71_TO_64_28_0_0_1_ETC__q1 = 5'd4; - 8'd5: CASE_pmsender_evFD_OUT_BITS_71_TO_64_28_0_0_1_ETC__q1 = 5'd5; - 8'd6: CASE_pmsender_evFD_OUT_BITS_71_TO_64_28_0_0_1_ETC__q1 = 5'd6; - 8'd7: CASE_pmsender_evFD_OUT_BITS_71_TO_64_28_0_0_1_ETC__q1 = 5'd7; - 8'd8: CASE_pmsender_evFD_OUT_BITS_71_TO_64_28_0_0_1_ETC__q1 = 5'd8; - 8'd9: CASE_pmsender_evFD_OUT_BITS_71_TO_64_28_0_0_1_ETC__q1 = 5'd9; - 8'd10: CASE_pmsender_evFD_OUT_BITS_71_TO_64_28_0_0_1_ETC__q1 = 5'd10; - 8'd11: CASE_pmsender_evFD_OUT_BITS_71_TO_64_28_0_0_1_ETC__q1 = 5'd11; - 8'd12: CASE_pmsender_evFD_OUT_BITS_71_TO_64_28_0_0_1_ETC__q1 = 5'd12; - 8'd13: CASE_pmsender_evFD_OUT_BITS_71_TO_64_28_0_0_1_ETC__q1 = 5'd13; - 8'd14: CASE_pmsender_evFD_OUT_BITS_71_TO_64_28_0_0_1_ETC__q1 = 5'd14; - 8'd16: CASE_pmsender_evFD_OUT_BITS_71_TO_64_28_0_0_1_ETC__q1 = 5'd15; - 8'd32: CASE_pmsender_evFD_OUT_BITS_71_TO_64_28_0_0_1_ETC__q1 = 5'd16; - 8'd48: CASE_pmsender_evFD_OUT_BITS_71_TO_64_28_0_0_1_ETC__q1 = 5'd17; - 8'd64: CASE_pmsender_evFD_OUT_BITS_71_TO_64_28_0_0_1_ETC__q1 = 5'd18; - 8'd80: CASE_pmsender_evFD_OUT_BITS_71_TO_64_28_0_0_1_ETC__q1 = 5'd19; - 8'd96: CASE_pmsender_evFD_OUT_BITS_71_TO_64_28_0_0_1_ETC__q1 = 5'd20; - 8'd97: CASE_pmsender_evFD_OUT_BITS_71_TO_64_28_0_0_1_ETC__q1 = 5'd21; - 8'd128: CASE_pmsender_evFD_OUT_BITS_71_TO_64_28_0_0_1_ETC__q1 = 5'd22; - 8'd144: CASE_pmsender_evFD_OUT_BITS_71_TO_64_28_0_0_1_ETC__q1 = 5'd23; - 8'd160: CASE_pmsender_evFD_OUT_BITS_71_TO_64_28_0_0_1_ETC__q1 = 5'd24; - 8'd176: CASE_pmsender_evFD_OUT_BITS_71_TO_64_28_0_0_1_ETC__q1 = 5'd25; - 8'd192: CASE_pmsender_evFD_OUT_BITS_71_TO_64_28_0_0_1_ETC__q1 = 5'd26; - 8'd208: CASE_pmsender_evFD_OUT_BITS_71_TO_64_28_0_0_1_ETC__q1 = 5'd27; - default: CASE_pmsender_evFD_OUT_BITS_71_TO_64_28_0_0_1_ETC__q1 = 5'd28; + 8'd0: CASE_pmsender_evFD_OUT_BITS_71_TO_64_0_0_1_1__ETC__q1 = 5'd0; + 8'd1: CASE_pmsender_evFD_OUT_BITS_71_TO_64_0_0_1_1__ETC__q1 = 5'd1; + 8'd2: CASE_pmsender_evFD_OUT_BITS_71_TO_64_0_0_1_1__ETC__q1 = 5'd2; + 8'd3: CASE_pmsender_evFD_OUT_BITS_71_TO_64_0_0_1_1__ETC__q1 = 5'd3; + 8'd4: CASE_pmsender_evFD_OUT_BITS_71_TO_64_0_0_1_1__ETC__q1 = 5'd4; + 8'd5: CASE_pmsender_evFD_OUT_BITS_71_TO_64_0_0_1_1__ETC__q1 = 5'd5; + 8'd6: CASE_pmsender_evFD_OUT_BITS_71_TO_64_0_0_1_1__ETC__q1 = 5'd6; + 8'd7: CASE_pmsender_evFD_OUT_BITS_71_TO_64_0_0_1_1__ETC__q1 = 5'd7; + 8'd8: CASE_pmsender_evFD_OUT_BITS_71_TO_64_0_0_1_1__ETC__q1 = 5'd8; + 8'd9: CASE_pmsender_evFD_OUT_BITS_71_TO_64_0_0_1_1__ETC__q1 = 5'd9; + 8'd10: CASE_pmsender_evFD_OUT_BITS_71_TO_64_0_0_1_1__ETC__q1 = 5'd10; + 8'd11: CASE_pmsender_evFD_OUT_BITS_71_TO_64_0_0_1_1__ETC__q1 = 5'd11; + 8'd12: CASE_pmsender_evFD_OUT_BITS_71_TO_64_0_0_1_1__ETC__q1 = 5'd12; + 8'd13: CASE_pmsender_evFD_OUT_BITS_71_TO_64_0_0_1_1__ETC__q1 = 5'd13; + 8'd14: CASE_pmsender_evFD_OUT_BITS_71_TO_64_0_0_1_1__ETC__q1 = 5'd14; + 8'd16: CASE_pmsender_evFD_OUT_BITS_71_TO_64_0_0_1_1__ETC__q1 = 5'd15; + 8'd32: CASE_pmsender_evFD_OUT_BITS_71_TO_64_0_0_1_1__ETC__q1 = 5'd16; + 8'd48: CASE_pmsender_evFD_OUT_BITS_71_TO_64_0_0_1_1__ETC__q1 = 5'd17; + 8'd64: CASE_pmsender_evFD_OUT_BITS_71_TO_64_0_0_1_1__ETC__q1 = 5'd18; + 8'd80: CASE_pmsender_evFD_OUT_BITS_71_TO_64_0_0_1_1__ETC__q1 = 5'd19; + 8'd96: CASE_pmsender_evFD_OUT_BITS_71_TO_64_0_0_1_1__ETC__q1 = 5'd20; + 8'd97: CASE_pmsender_evFD_OUT_BITS_71_TO_64_0_0_1_1__ETC__q1 = 5'd21; + 8'd128: CASE_pmsender_evFD_OUT_BITS_71_TO_64_0_0_1_1__ETC__q1 = 5'd22; + 8'd144: CASE_pmsender_evFD_OUT_BITS_71_TO_64_0_0_1_1__ETC__q1 = 5'd23; + 8'd160: CASE_pmsender_evFD_OUT_BITS_71_TO_64_0_0_1_1__ETC__q1 = 5'd24; + 8'd176: CASE_pmsender_evFD_OUT_BITS_71_TO_64_0_0_1_1__ETC__q1 = 5'd25; + 8'd192: CASE_pmsender_evFD_OUT_BITS_71_TO_64_0_0_1_1__ETC__q1 = 5'd26; + 8'd208: CASE_pmsender_evFD_OUT_BITS_71_TO_64_0_0_1_1__ETC__q1 = 5'd27; + default: CASE_pmsender_evFD_OUT_BITS_71_TO_64_0_0_1_1__ETC__q1 = 5'd28; endcase end always@(pmsender_evF$D_OUT) begin case (pmsender_evF$D_OUT[7:0]) - 8'd0: CASE_pmsender_evFD_OUT_BITS_7_TO_0_28_0_0_1_1_ETC__q2 = 5'd0; - 8'd1: CASE_pmsender_evFD_OUT_BITS_7_TO_0_28_0_0_1_1_ETC__q2 = 5'd1; - 8'd2: CASE_pmsender_evFD_OUT_BITS_7_TO_0_28_0_0_1_1_ETC__q2 = 5'd2; - 8'd3: CASE_pmsender_evFD_OUT_BITS_7_TO_0_28_0_0_1_1_ETC__q2 = 5'd3; - 8'd4: CASE_pmsender_evFD_OUT_BITS_7_TO_0_28_0_0_1_1_ETC__q2 = 5'd4; - 8'd5: CASE_pmsender_evFD_OUT_BITS_7_TO_0_28_0_0_1_1_ETC__q2 = 5'd5; - 8'd6: CASE_pmsender_evFD_OUT_BITS_7_TO_0_28_0_0_1_1_ETC__q2 = 5'd6; - 8'd7: CASE_pmsender_evFD_OUT_BITS_7_TO_0_28_0_0_1_1_ETC__q2 = 5'd7; - 8'd8: CASE_pmsender_evFD_OUT_BITS_7_TO_0_28_0_0_1_1_ETC__q2 = 5'd8; - 8'd9: CASE_pmsender_evFD_OUT_BITS_7_TO_0_28_0_0_1_1_ETC__q2 = 5'd9; - 8'd10: CASE_pmsender_evFD_OUT_BITS_7_TO_0_28_0_0_1_1_ETC__q2 = 5'd10; - 8'd11: CASE_pmsender_evFD_OUT_BITS_7_TO_0_28_0_0_1_1_ETC__q2 = 5'd11; - 8'd12: CASE_pmsender_evFD_OUT_BITS_7_TO_0_28_0_0_1_1_ETC__q2 = 5'd12; - 8'd13: CASE_pmsender_evFD_OUT_BITS_7_TO_0_28_0_0_1_1_ETC__q2 = 5'd13; - 8'd14: CASE_pmsender_evFD_OUT_BITS_7_TO_0_28_0_0_1_1_ETC__q2 = 5'd14; - 8'd16: CASE_pmsender_evFD_OUT_BITS_7_TO_0_28_0_0_1_1_ETC__q2 = 5'd15; - 8'd32: CASE_pmsender_evFD_OUT_BITS_7_TO_0_28_0_0_1_1_ETC__q2 = 5'd16; - 8'd48: CASE_pmsender_evFD_OUT_BITS_7_TO_0_28_0_0_1_1_ETC__q2 = 5'd17; - 8'd64: CASE_pmsender_evFD_OUT_BITS_7_TO_0_28_0_0_1_1_ETC__q2 = 5'd18; - 8'd80: CASE_pmsender_evFD_OUT_BITS_7_TO_0_28_0_0_1_1_ETC__q2 = 5'd19; - 8'd96: CASE_pmsender_evFD_OUT_BITS_7_TO_0_28_0_0_1_1_ETC__q2 = 5'd20; - 8'd97: CASE_pmsender_evFD_OUT_BITS_7_TO_0_28_0_0_1_1_ETC__q2 = 5'd21; - 8'd128: CASE_pmsender_evFD_OUT_BITS_7_TO_0_28_0_0_1_1_ETC__q2 = 5'd22; - 8'd144: CASE_pmsender_evFD_OUT_BITS_7_TO_0_28_0_0_1_1_ETC__q2 = 5'd23; - 8'd160: CASE_pmsender_evFD_OUT_BITS_7_TO_0_28_0_0_1_1_ETC__q2 = 5'd24; - 8'd176: CASE_pmsender_evFD_OUT_BITS_7_TO_0_28_0_0_1_1_ETC__q2 = 5'd25; - 8'd192: CASE_pmsender_evFD_OUT_BITS_7_TO_0_28_0_0_1_1_ETC__q2 = 5'd26; - 8'd208: CASE_pmsender_evFD_OUT_BITS_7_TO_0_28_0_0_1_1_ETC__q2 = 5'd27; - default: CASE_pmsender_evFD_OUT_BITS_7_TO_0_28_0_0_1_1_ETC__q2 = 5'd28; + 8'd0: CASE_pmsender_evFD_OUT_BITS_7_TO_0_0_0_1_1_2__ETC__q2 = 5'd0; + 8'd1: CASE_pmsender_evFD_OUT_BITS_7_TO_0_0_0_1_1_2__ETC__q2 = 5'd1; + 8'd2: CASE_pmsender_evFD_OUT_BITS_7_TO_0_0_0_1_1_2__ETC__q2 = 5'd2; + 8'd3: CASE_pmsender_evFD_OUT_BITS_7_TO_0_0_0_1_1_2__ETC__q2 = 5'd3; + 8'd4: CASE_pmsender_evFD_OUT_BITS_7_TO_0_0_0_1_1_2__ETC__q2 = 5'd4; + 8'd5: CASE_pmsender_evFD_OUT_BITS_7_TO_0_0_0_1_1_2__ETC__q2 = 5'd5; + 8'd6: CASE_pmsender_evFD_OUT_BITS_7_TO_0_0_0_1_1_2__ETC__q2 = 5'd6; + 8'd7: CASE_pmsender_evFD_OUT_BITS_7_TO_0_0_0_1_1_2__ETC__q2 = 5'd7; + 8'd8: CASE_pmsender_evFD_OUT_BITS_7_TO_0_0_0_1_1_2__ETC__q2 = 5'd8; + 8'd9: CASE_pmsender_evFD_OUT_BITS_7_TO_0_0_0_1_1_2__ETC__q2 = 5'd9; + 8'd10: CASE_pmsender_evFD_OUT_BITS_7_TO_0_0_0_1_1_2__ETC__q2 = 5'd10; + 8'd11: CASE_pmsender_evFD_OUT_BITS_7_TO_0_0_0_1_1_2__ETC__q2 = 5'd11; + 8'd12: CASE_pmsender_evFD_OUT_BITS_7_TO_0_0_0_1_1_2__ETC__q2 = 5'd12; + 8'd13: CASE_pmsender_evFD_OUT_BITS_7_TO_0_0_0_1_1_2__ETC__q2 = 5'd13; + 8'd14: CASE_pmsender_evFD_OUT_BITS_7_TO_0_0_0_1_1_2__ETC__q2 = 5'd14; + 8'd16: CASE_pmsender_evFD_OUT_BITS_7_TO_0_0_0_1_1_2__ETC__q2 = 5'd15; + 8'd32: CASE_pmsender_evFD_OUT_BITS_7_TO_0_0_0_1_1_2__ETC__q2 = 5'd16; + 8'd48: CASE_pmsender_evFD_OUT_BITS_7_TO_0_0_0_1_1_2__ETC__q2 = 5'd17; + 8'd64: CASE_pmsender_evFD_OUT_BITS_7_TO_0_0_0_1_1_2__ETC__q2 = 5'd18; + 8'd80: CASE_pmsender_evFD_OUT_BITS_7_TO_0_0_0_1_1_2__ETC__q2 = 5'd19; + 8'd96: CASE_pmsender_evFD_OUT_BITS_7_TO_0_0_0_1_1_2__ETC__q2 = 5'd20; + 8'd97: CASE_pmsender_evFD_OUT_BITS_7_TO_0_0_0_1_1_2__ETC__q2 = 5'd21; + 8'd128: CASE_pmsender_evFD_OUT_BITS_7_TO_0_0_0_1_1_2__ETC__q2 = 5'd22; + 8'd144: CASE_pmsender_evFD_OUT_BITS_7_TO_0_0_0_1_1_2__ETC__q2 = 5'd23; + 8'd160: CASE_pmsender_evFD_OUT_BITS_7_TO_0_0_0_1_1_2__ETC__q2 = 5'd24; + 8'd176: CASE_pmsender_evFD_OUT_BITS_7_TO_0_0_0_1_1_2__ETC__q2 = 5'd25; + 8'd192: CASE_pmsender_evFD_OUT_BITS_7_TO_0_0_0_1_1_2__ETC__q2 = 5'd26; + 8'd208: CASE_pmsender_evFD_OUT_BITS_7_TO_0_0_0_1_1_2__ETC__q2 = 5'd27; + default: CASE_pmsender_evFD_OUT_BITS_7_TO_0_0_0_1_1_2__ETC__q2 = 5'd28; endcase end always@(pmsender_evF$D_OUT) begin case (pmsender_evF$D_OUT[39:32]) - 8'd0: CASE_pmsender_evFD_OUT_BITS_39_TO_32_28_0_0_1_ETC__q3 = 5'd0; - 8'd1: CASE_pmsender_evFD_OUT_BITS_39_TO_32_28_0_0_1_ETC__q3 = 5'd1; - 8'd2: CASE_pmsender_evFD_OUT_BITS_39_TO_32_28_0_0_1_ETC__q3 = 5'd2; - 8'd3: CASE_pmsender_evFD_OUT_BITS_39_TO_32_28_0_0_1_ETC__q3 = 5'd3; - 8'd4: CASE_pmsender_evFD_OUT_BITS_39_TO_32_28_0_0_1_ETC__q3 = 5'd4; - 8'd5: CASE_pmsender_evFD_OUT_BITS_39_TO_32_28_0_0_1_ETC__q3 = 5'd5; - 8'd6: CASE_pmsender_evFD_OUT_BITS_39_TO_32_28_0_0_1_ETC__q3 = 5'd6; - 8'd7: CASE_pmsender_evFD_OUT_BITS_39_TO_32_28_0_0_1_ETC__q3 = 5'd7; - 8'd8: CASE_pmsender_evFD_OUT_BITS_39_TO_32_28_0_0_1_ETC__q3 = 5'd8; - 8'd9: CASE_pmsender_evFD_OUT_BITS_39_TO_32_28_0_0_1_ETC__q3 = 5'd9; - 8'd10: CASE_pmsender_evFD_OUT_BITS_39_TO_32_28_0_0_1_ETC__q3 = 5'd10; - 8'd11: CASE_pmsender_evFD_OUT_BITS_39_TO_32_28_0_0_1_ETC__q3 = 5'd11; - 8'd12: CASE_pmsender_evFD_OUT_BITS_39_TO_32_28_0_0_1_ETC__q3 = 5'd12; - 8'd13: CASE_pmsender_evFD_OUT_BITS_39_TO_32_28_0_0_1_ETC__q3 = 5'd13; - 8'd14: CASE_pmsender_evFD_OUT_BITS_39_TO_32_28_0_0_1_ETC__q3 = 5'd14; - 8'd16: CASE_pmsender_evFD_OUT_BITS_39_TO_32_28_0_0_1_ETC__q3 = 5'd15; - 8'd32: CASE_pmsender_evFD_OUT_BITS_39_TO_32_28_0_0_1_ETC__q3 = 5'd16; - 8'd48: CASE_pmsender_evFD_OUT_BITS_39_TO_32_28_0_0_1_ETC__q3 = 5'd17; - 8'd64: CASE_pmsender_evFD_OUT_BITS_39_TO_32_28_0_0_1_ETC__q3 = 5'd18; - 8'd80: CASE_pmsender_evFD_OUT_BITS_39_TO_32_28_0_0_1_ETC__q3 = 5'd19; - 8'd96: CASE_pmsender_evFD_OUT_BITS_39_TO_32_28_0_0_1_ETC__q3 = 5'd20; - 8'd97: CASE_pmsender_evFD_OUT_BITS_39_TO_32_28_0_0_1_ETC__q3 = 5'd21; - 8'd128: CASE_pmsender_evFD_OUT_BITS_39_TO_32_28_0_0_1_ETC__q3 = 5'd22; - 8'd144: CASE_pmsender_evFD_OUT_BITS_39_TO_32_28_0_0_1_ETC__q3 = 5'd23; - 8'd160: CASE_pmsender_evFD_OUT_BITS_39_TO_32_28_0_0_1_ETC__q3 = 5'd24; - 8'd176: CASE_pmsender_evFD_OUT_BITS_39_TO_32_28_0_0_1_ETC__q3 = 5'd25; - 8'd192: CASE_pmsender_evFD_OUT_BITS_39_TO_32_28_0_0_1_ETC__q3 = 5'd26; - 8'd208: CASE_pmsender_evFD_OUT_BITS_39_TO_32_28_0_0_1_ETC__q3 = 5'd27; - default: CASE_pmsender_evFD_OUT_BITS_39_TO_32_28_0_0_1_ETC__q3 = 5'd28; + 8'd0: CASE_pmsender_evFD_OUT_BITS_39_TO_32_0_0_1_1__ETC__q3 = 5'd0; + 8'd1: CASE_pmsender_evFD_OUT_BITS_39_TO_32_0_0_1_1__ETC__q3 = 5'd1; + 8'd2: CASE_pmsender_evFD_OUT_BITS_39_TO_32_0_0_1_1__ETC__q3 = 5'd2; + 8'd3: CASE_pmsender_evFD_OUT_BITS_39_TO_32_0_0_1_1__ETC__q3 = 5'd3; + 8'd4: CASE_pmsender_evFD_OUT_BITS_39_TO_32_0_0_1_1__ETC__q3 = 5'd4; + 8'd5: CASE_pmsender_evFD_OUT_BITS_39_TO_32_0_0_1_1__ETC__q3 = 5'd5; + 8'd6: CASE_pmsender_evFD_OUT_BITS_39_TO_32_0_0_1_1__ETC__q3 = 5'd6; + 8'd7: CASE_pmsender_evFD_OUT_BITS_39_TO_32_0_0_1_1__ETC__q3 = 5'd7; + 8'd8: CASE_pmsender_evFD_OUT_BITS_39_TO_32_0_0_1_1__ETC__q3 = 5'd8; + 8'd9: CASE_pmsender_evFD_OUT_BITS_39_TO_32_0_0_1_1__ETC__q3 = 5'd9; + 8'd10: CASE_pmsender_evFD_OUT_BITS_39_TO_32_0_0_1_1__ETC__q3 = 5'd10; + 8'd11: CASE_pmsender_evFD_OUT_BITS_39_TO_32_0_0_1_1__ETC__q3 = 5'd11; + 8'd12: CASE_pmsender_evFD_OUT_BITS_39_TO_32_0_0_1_1__ETC__q3 = 5'd12; + 8'd13: CASE_pmsender_evFD_OUT_BITS_39_TO_32_0_0_1_1__ETC__q3 = 5'd13; + 8'd14: CASE_pmsender_evFD_OUT_BITS_39_TO_32_0_0_1_1__ETC__q3 = 5'd14; + 8'd16: CASE_pmsender_evFD_OUT_BITS_39_TO_32_0_0_1_1__ETC__q3 = 5'd15; + 8'd32: CASE_pmsender_evFD_OUT_BITS_39_TO_32_0_0_1_1__ETC__q3 = 5'd16; + 8'd48: CASE_pmsender_evFD_OUT_BITS_39_TO_32_0_0_1_1__ETC__q3 = 5'd17; + 8'd64: CASE_pmsender_evFD_OUT_BITS_39_TO_32_0_0_1_1__ETC__q3 = 5'd18; + 8'd80: CASE_pmsender_evFD_OUT_BITS_39_TO_32_0_0_1_1__ETC__q3 = 5'd19; + 8'd96: CASE_pmsender_evFD_OUT_BITS_39_TO_32_0_0_1_1__ETC__q3 = 5'd20; + 8'd97: CASE_pmsender_evFD_OUT_BITS_39_TO_32_0_0_1_1__ETC__q3 = 5'd21; + 8'd128: CASE_pmsender_evFD_OUT_BITS_39_TO_32_0_0_1_1__ETC__q3 = 5'd22; + 8'd144: CASE_pmsender_evFD_OUT_BITS_39_TO_32_0_0_1_1__ETC__q3 = 5'd23; + 8'd160: CASE_pmsender_evFD_OUT_BITS_39_TO_32_0_0_1_1__ETC__q3 = 5'd24; + 8'd176: CASE_pmsender_evFD_OUT_BITS_39_TO_32_0_0_1_1__ETC__q3 = 5'd25; + 8'd192: CASE_pmsender_evFD_OUT_BITS_39_TO_32_0_0_1_1__ETC__q3 = 5'd26; + 8'd208: CASE_pmsender_evFD_OUT_BITS_39_TO_32_0_0_1_1__ETC__q3 = 5'd27; + default: CASE_pmsender_evFD_OUT_BITS_39_TO_32_0_0_1_1__ETC__q3 = 5'd28; endcase end always@(pmsender_evF$D_OUT or - CASE_pmsender_evFD_OUT_BITS_71_TO_64_28_0_0_1_ETC__q1 or - CASE_pmsender_evFD_OUT_BITS_7_TO_0_28_0_0_1_1_ETC__q2 or - CASE_pmsender_evFD_OUT_BITS_39_TO_32_28_0_0_1_ETC__q3) + CASE_pmsender_evFD_OUT_BITS_71_TO_64_0_0_1_1__ETC__q1 or + CASE_pmsender_evFD_OUT_BITS_7_TO_0_0_0_1_1_2__ETC__q2 or + CASE_pmsender_evFD_OUT_BITS_39_TO_32_0_0_1_1__ETC__q3) begin case (pmsender_evF$D_OUT[98:96]) 3'd0: - CASE_pmsender_evFD_OUT_BITS_98_TO_96_CASE_pms_ETC__q4 = - CASE_pmsender_evFD_OUT_BITS_7_TO_0_28_0_0_1_1_ETC__q2; + CASE_pmsender_evFD_OUT_BITS_98_TO_96_0_CASE_p_ETC__q4 = + CASE_pmsender_evFD_OUT_BITS_7_TO_0_0_0_1_1_2__ETC__q2; 3'd1: - CASE_pmsender_evFD_OUT_BITS_98_TO_96_CASE_pms_ETC__q4 = - CASE_pmsender_evFD_OUT_BITS_39_TO_32_28_0_0_1_ETC__q3; - default: CASE_pmsender_evFD_OUT_BITS_98_TO_96_CASE_pms_ETC__q4 = - CASE_pmsender_evFD_OUT_BITS_71_TO_64_28_0_0_1_ETC__q1; + CASE_pmsender_evFD_OUT_BITS_98_TO_96_0_CASE_p_ETC__q4 = + CASE_pmsender_evFD_OUT_BITS_39_TO_32_0_0_1_1__ETC__q3; + default: CASE_pmsender_evFD_OUT_BITS_98_TO_96_0_CASE_p_ETC__q4 = + CASE_pmsender_evFD_OUT_BITS_71_TO_64_0_0_1_1__ETC__q1; endcase end - always@(CASE_pmsender_evFD_OUT_BITS_98_TO_96_CASE_pms_ETC__q4) + always@(CASE_pmsender_evFD_OUT_BITS_98_TO_96_0_CASE_p_ETC__q4) begin - case (CASE_pmsender_evFD_OUT_BITS_98_TO_96_CASE_pms_ETC__q4) - 5'd0: CASE_CASE_pmsender_evFD_OUT_BITS_98_TO_96_CASE_ETC__q5 = 8'd0; - 5'd1: CASE_CASE_pmsender_evFD_OUT_BITS_98_TO_96_CASE_ETC__q5 = 8'd1; - 5'd2: CASE_CASE_pmsender_evFD_OUT_BITS_98_TO_96_CASE_ETC__q5 = 8'd2; - 5'd3: CASE_CASE_pmsender_evFD_OUT_BITS_98_TO_96_CASE_ETC__q5 = 8'd3; - 5'd4: CASE_CASE_pmsender_evFD_OUT_BITS_98_TO_96_CASE_ETC__q5 = 8'd4; - 5'd5: CASE_CASE_pmsender_evFD_OUT_BITS_98_TO_96_CASE_ETC__q5 = 8'd5; - 5'd6: CASE_CASE_pmsender_evFD_OUT_BITS_98_TO_96_CASE_ETC__q5 = 8'd6; - 5'd7: CASE_CASE_pmsender_evFD_OUT_BITS_98_TO_96_CASE_ETC__q5 = 8'd7; - 5'd8: CASE_CASE_pmsender_evFD_OUT_BITS_98_TO_96_CASE_ETC__q5 = 8'd8; - 5'd9: CASE_CASE_pmsender_evFD_OUT_BITS_98_TO_96_CASE_ETC__q5 = 8'd9; - 5'd10: CASE_CASE_pmsender_evFD_OUT_BITS_98_TO_96_CASE_ETC__q5 = 8'd10; - 5'd11: CASE_CASE_pmsender_evFD_OUT_BITS_98_TO_96_CASE_ETC__q5 = 8'd11; - 5'd12: CASE_CASE_pmsender_evFD_OUT_BITS_98_TO_96_CASE_ETC__q5 = 8'd12; - 5'd13: CASE_CASE_pmsender_evFD_OUT_BITS_98_TO_96_CASE_ETC__q5 = 8'd13; - 5'd14: CASE_CASE_pmsender_evFD_OUT_BITS_98_TO_96_CASE_ETC__q5 = 8'd14; - 5'd15: CASE_CASE_pmsender_evFD_OUT_BITS_98_TO_96_CASE_ETC__q5 = 8'd16; - 5'd16: CASE_CASE_pmsender_evFD_OUT_BITS_98_TO_96_CASE_ETC__q5 = 8'd32; - 5'd17: CASE_CASE_pmsender_evFD_OUT_BITS_98_TO_96_CASE_ETC__q5 = 8'd48; - 5'd18: CASE_CASE_pmsender_evFD_OUT_BITS_98_TO_96_CASE_ETC__q5 = 8'd64; - 5'd19: CASE_CASE_pmsender_evFD_OUT_BITS_98_TO_96_CASE_ETC__q5 = 8'd80; - 5'd20: CASE_CASE_pmsender_evFD_OUT_BITS_98_TO_96_CASE_ETC__q5 = 8'd96; - 5'd21: CASE_CASE_pmsender_evFD_OUT_BITS_98_TO_96_CASE_ETC__q5 = 8'd97; - 5'd22: CASE_CASE_pmsender_evFD_OUT_BITS_98_TO_96_CASE_ETC__q5 = 8'd128; - 5'd23: CASE_CASE_pmsender_evFD_OUT_BITS_98_TO_96_CASE_ETC__q5 = 8'd144; - 5'd24: CASE_CASE_pmsender_evFD_OUT_BITS_98_TO_96_CASE_ETC__q5 = 8'd160; - 5'd25: CASE_CASE_pmsender_evFD_OUT_BITS_98_TO_96_CASE_ETC__q5 = 8'd176; - 5'd26: CASE_CASE_pmsender_evFD_OUT_BITS_98_TO_96_CASE_ETC__q5 = 8'd192; - 5'd27: CASE_CASE_pmsender_evFD_OUT_BITS_98_TO_96_CASE_ETC__q5 = 8'd208; - default: CASE_CASE_pmsender_evFD_OUT_BITS_98_TO_96_CASE_ETC__q5 = + case (CASE_pmsender_evFD_OUT_BITS_98_TO_96_0_CASE_p_ETC__q4) + 5'd0: CASE_CASE_pmsender_evFD_OUT_BITS_98_TO_96_0_CA_ETC__q5 = 8'd0; + 5'd1: CASE_CASE_pmsender_evFD_OUT_BITS_98_TO_96_0_CA_ETC__q5 = 8'd1; + 5'd2: CASE_CASE_pmsender_evFD_OUT_BITS_98_TO_96_0_CA_ETC__q5 = 8'd2; + 5'd3: CASE_CASE_pmsender_evFD_OUT_BITS_98_TO_96_0_CA_ETC__q5 = 8'd3; + 5'd4: CASE_CASE_pmsender_evFD_OUT_BITS_98_TO_96_0_CA_ETC__q5 = 8'd4; + 5'd5: CASE_CASE_pmsender_evFD_OUT_BITS_98_TO_96_0_CA_ETC__q5 = 8'd5; + 5'd6: CASE_CASE_pmsender_evFD_OUT_BITS_98_TO_96_0_CA_ETC__q5 = 8'd6; + 5'd7: CASE_CASE_pmsender_evFD_OUT_BITS_98_TO_96_0_CA_ETC__q5 = 8'd7; + 5'd8: CASE_CASE_pmsender_evFD_OUT_BITS_98_TO_96_0_CA_ETC__q5 = 8'd8; + 5'd9: CASE_CASE_pmsender_evFD_OUT_BITS_98_TO_96_0_CA_ETC__q5 = 8'd9; + 5'd10: CASE_CASE_pmsender_evFD_OUT_BITS_98_TO_96_0_CA_ETC__q5 = 8'd10; + 5'd11: CASE_CASE_pmsender_evFD_OUT_BITS_98_TO_96_0_CA_ETC__q5 = 8'd11; + 5'd12: CASE_CASE_pmsender_evFD_OUT_BITS_98_TO_96_0_CA_ETC__q5 = 8'd12; + 5'd13: CASE_CASE_pmsender_evFD_OUT_BITS_98_TO_96_0_CA_ETC__q5 = 8'd13; + 5'd14: CASE_CASE_pmsender_evFD_OUT_BITS_98_TO_96_0_CA_ETC__q5 = 8'd14; + 5'd15: CASE_CASE_pmsender_evFD_OUT_BITS_98_TO_96_0_CA_ETC__q5 = 8'd16; + 5'd16: CASE_CASE_pmsender_evFD_OUT_BITS_98_TO_96_0_CA_ETC__q5 = 8'd32; + 5'd17: CASE_CASE_pmsender_evFD_OUT_BITS_98_TO_96_0_CA_ETC__q5 = 8'd48; + 5'd18: CASE_CASE_pmsender_evFD_OUT_BITS_98_TO_96_0_CA_ETC__q5 = 8'd64; + 5'd19: CASE_CASE_pmsender_evFD_OUT_BITS_98_TO_96_0_CA_ETC__q5 = 8'd80; + 5'd20: CASE_CASE_pmsender_evFD_OUT_BITS_98_TO_96_0_CA_ETC__q5 = 8'd96; + 5'd21: CASE_CASE_pmsender_evFD_OUT_BITS_98_TO_96_0_CA_ETC__q5 = 8'd97; + 5'd22: CASE_CASE_pmsender_evFD_OUT_BITS_98_TO_96_0_CA_ETC__q5 = 8'd128; + 5'd23: CASE_CASE_pmsender_evFD_OUT_BITS_98_TO_96_0_CA_ETC__q5 = 8'd144; + 5'd24: CASE_CASE_pmsender_evFD_OUT_BITS_98_TO_96_0_CA_ETC__q5 = 8'd160; + 5'd25: CASE_CASE_pmsender_evFD_OUT_BITS_98_TO_96_0_CA_ETC__q5 = 8'd176; + 5'd26: CASE_CASE_pmsender_evFD_OUT_BITS_98_TO_96_0_CA_ETC__q5 = 8'd192; + 5'd27: CASE_CASE_pmsender_evFD_OUT_BITS_98_TO_96_0_CA_ETC__q5 = 8'd208; + default: CASE_CASE_pmsender_evFD_OUT_BITS_98_TO_96_0_CA_ETC__q5 = 8'd255; endcase end always@(pmsender_idx or pmsender_evF$D_OUT or - monId_CONCAT_IF_IF_pmsender_evF_first__30_BITS_ETC___d381) + monId or + CASE_CASE_pmsender_evFD_OUT_BITS_98_TO_96_0_CA_ETC__q5 or + pmsender_srcTag or x__h5780) begin case (pmsender_idx) 3'd1: - x_data__h4919 = - monId_CONCAT_IF_IF_pmsender_evF_first__30_BITS_ETC___d381; + x_data__h4786 = + { monId, + CASE_CASE_pmsender_evFD_OUT_BITS_98_TO_96_0_CA_ETC__q5, + pmsender_srcTag, + x__h5780 }; 3'd2: - x_data__h4919 = + x_data__h4786 = (pmsender_evF$D_OUT[98:96] == 3'd1) ? pmsender_evF$D_OUT[31:0] : pmsender_evF$D_OUT[63:32]; - default: x_data__h4919 = pmsender_evF$D_OUT[31:0]; + default: x_data__h4786 = pmsender_evF$D_OUT[31:0]; endcase end always@(observer_evF$D_OUT) begin - case (observer_evF$D_OUT[98:96]) - 3'd0, 3'd1, 3'd2, 3'd3, 3'd4: - CASE_observer_evFD_OUT_BITS_98_TO_96_5_0_obse_ETC__q6 = - observer_evF$D_OUT[98:96]; - default: CASE_observer_evFD_OUT_BITS_98_TO_96_5_0_obse_ETC__q6 = 3'd5; - endcase - end - always@(observer_evF$D_OUT) - begin - case (observer_evF$D_OUT[7:0]) + case (observer_evF$D_OUT[71:64]) 8'd0, 8'd1, 8'd2, @@ -1061,14 +1064,23 @@ module mkWciMonitor(CLK, 8'd176, 8'd192, 8'd208: - CASE_observer_evFD_OUT_BITS_7_TO_0_255_0_obse_ETC__q7 = - observer_evF$D_OUT[7:0]; - default: CASE_observer_evFD_OUT_BITS_7_TO_0_255_0_obse_ETC__q7 = 8'd255; + CASE_observer_evFD_OUT_BITS_71_TO_64_0_observ_ETC__q6 = + observer_evF$D_OUT[71:64]; + default: CASE_observer_evFD_OUT_BITS_71_TO_64_0_observ_ETC__q6 = 8'd255; endcase end always@(observer_evF$D_OUT) begin - case (observer_evF$D_OUT[39:32]) + case (observer_evF$D_OUT[98:96]) + 3'd0, 3'd1, 3'd2, 3'd3, 3'd4: + CASE_observer_evFD_OUT_BITS_98_TO_96_0_observ_ETC__q7 = + observer_evF$D_OUT[98:96]; + default: CASE_observer_evFD_OUT_BITS_98_TO_96_0_observ_ETC__q7 = 3'd5; + endcase + end + always@(observer_evF$D_OUT) + begin + case (observer_evF$D_OUT[7:0]) 8'd0, 8'd1, 8'd2, @@ -1097,14 +1109,14 @@ module mkWciMonitor(CLK, 8'd176, 8'd192, 8'd208: - CASE_observer_evFD_OUT_BITS_39_TO_32_255_0_ob_ETC__q8 = - observer_evF$D_OUT[39:32]; - default: CASE_observer_evFD_OUT_BITS_39_TO_32_255_0_ob_ETC__q8 = 8'd255; + CASE_observer_evFD_OUT_BITS_7_TO_0_0_observer_ETC__q8 = + observer_evF$D_OUT[7:0]; + default: CASE_observer_evFD_OUT_BITS_7_TO_0_0_observer_ETC__q8 = 8'd255; endcase end always@(observer_evF$D_OUT) begin - case (observer_evF$D_OUT[71:64]) + case (observer_evF$D_OUT[39:32]) 8'd0, 8'd1, 8'd2, @@ -1133,32 +1145,30 @@ module mkWciMonitor(CLK, 8'd176, 8'd192, 8'd208: - CASE_observer_evFD_OUT_BITS_71_TO_64_255_0_ob_ETC__q9 = - observer_evF$D_OUT[71:64]; - default: CASE_observer_evFD_OUT_BITS_71_TO_64_255_0_ob_ETC__q9 = 8'd255; + CASE_observer_evFD_OUT_BITS_39_TO_32_0_observ_ETC__q9 = + observer_evF$D_OUT[39:32]; + default: CASE_observer_evFD_OUT_BITS_39_TO_32_0_observ_ETC__q9 = 8'd255; endcase end always@(observer_evF$D_OUT or - CASE_observer_evFD_OUT_BITS_7_TO_0_255_0_obse_ETC__q7 or - CASE_observer_evFD_OUT_BITS_39_TO_32_255_0_ob_ETC__q8 or - CASE_observer_evFD_OUT_BITS_71_TO_64_255_0_ob_ETC__q9) + CASE_observer_evFD_OUT_BITS_7_TO_0_0_observer_ETC__q8 or + CASE_observer_evFD_OUT_BITS_39_TO_32_0_observ_ETC__q9 or + DONTCARE_CONCAT_IF_observer_evF_first__00_BITS_ETC___d588) begin case (observer_evF$D_OUT[98:96]) 3'd0: - CASE_observer_evFD_OUT_BITS_98_TO_96_observer_ETC__q10 = + CASE_observer_evFD_OUT_BITS_98_TO_96_0_0xAAAA_ETC__q10 = { 88'hAAAAAAAAAAAAAAAAAAAAAA, - CASE_observer_evFD_OUT_BITS_7_TO_0_255_0_obse_ETC__q7 }; + CASE_observer_evFD_OUT_BITS_7_TO_0_0_observer_ETC__q8 }; 3'd1: - CASE_observer_evFD_OUT_BITS_98_TO_96_observer_ETC__q10 = + CASE_observer_evFD_OUT_BITS_98_TO_96_0_0xAAAA_ETC__q10 = { 56'hAAAAAAAAAAAAAA, - CASE_observer_evFD_OUT_BITS_39_TO_32_255_0_ob_ETC__q8, + CASE_observer_evFD_OUT_BITS_39_TO_32_0_observ_ETC__q9, observer_evF$D_OUT[31:0] }; 3'd2, 3'd3: - CASE_observer_evFD_OUT_BITS_98_TO_96_observer_ETC__q10 = - { 24'hAAAAAA, - CASE_observer_evFD_OUT_BITS_71_TO_64_255_0_ob_ETC__q9, - observer_evF$D_OUT[63:0] }; - default: CASE_observer_evFD_OUT_BITS_98_TO_96_observer_ETC__q10 = + CASE_observer_evFD_OUT_BITS_98_TO_96_0_0xAAAA_ETC__q10 = + DONTCARE_CONCAT_IF_observer_evF_first__00_BITS_ETC___d588; + default: CASE_observer_evFD_OUT_BITS_98_TO_96_0_0xAAAA_ETC__q10 = observer_evF$D_OUT[95:0]; endcase end @@ -1193,7 +1203,7 @@ module mkWciMonitor(CLK, pmsender_wsiM_operateD <= `BSV_ASSIGNMENT_DELAY 1'd0; pmsender_wsiM_pMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0; pmsender_wsiM_peerIsReady <= `BSV_ASSIGNMENT_DELAY 1'd0; - pmsender_wsiM_reqFifo_c_r <= `BSV_ASSIGNMENT_DELAY 2'd0; + pmsender_wsiM_reqFifo_cntr_r <= `BSV_ASSIGNMENT_DELAY 2'd0; pmsender_wsiM_reqFifo_q_0 <= `BSV_ASSIGNMENT_DELAY 61'h00000AAAAAAAAA00; pmsender_wsiM_reqFifo_q_1 <= `BSV_ASSIGNMENT_DELAY @@ -1262,9 +1272,9 @@ module mkWciMonitor(CLK, if (pmsender_wsiM_peerIsReady$EN) pmsender_wsiM_peerIsReady <= `BSV_ASSIGNMENT_DELAY pmsender_wsiM_peerIsReady$D_IN; - if (pmsender_wsiM_reqFifo_c_r$EN) - pmsender_wsiM_reqFifo_c_r <= `BSV_ASSIGNMENT_DELAY - pmsender_wsiM_reqFifo_c_r$D_IN; + if (pmsender_wsiM_reqFifo_cntr_r$EN) + pmsender_wsiM_reqFifo_cntr_r <= `BSV_ASSIGNMENT_DELAY + pmsender_wsiM_reqFifo_cntr_r$D_IN; if (pmsender_wsiM_reqFifo_q_0$EN) pmsender_wsiM_reqFifo_q_0 <= `BSV_ASSIGNMENT_DELAY pmsender_wsiM_reqFifo_q_0$D_IN; @@ -1328,7 +1338,7 @@ module mkWciMonitor(CLK, pmsender_wsiM_operateD = 1'h0; pmsender_wsiM_pMesgCount = 32'hAAAAAAAA; pmsender_wsiM_peerIsReady = 1'h0; - pmsender_wsiM_reqFifo_c_r = 2'h2; + pmsender_wsiM_reqFifo_cntr_r = 2'h2; pmsender_wsiM_reqFifo_q_0 = 61'h0AAAAAAAAAAAAAAA; pmsender_wsiM_reqFifo_q_1 = 61'h0AAAAAAAAAAAAAAA; pmsender_wsiM_sThreadBusy_d = 1'h0; @@ -1348,21 +1358,21 @@ module mkWciMonitor(CLK, if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_observer_reset_changed && observer_r_mResetn) begin - v__h1591 = $time; + v__h1590 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_observer_reset_changed && observer_r_mResetn) - $display("[%0d]: %m: WCI reset DE-ASSERTED", v__h1591); + $display("[%0d]: %m: WCI reset DE-ASSERTED", v__h1590); if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_observer_reset_changed && !observer_r_mResetn) begin - v__h1614 = $time; + v__h1613 = $time; #0; end if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_observer_reset_changed && !observer_r_mResetn) - $display("[%0d]: %m: WCI reset IS-ASSERTED", v__h1614); + $display("[%0d]: %m: WCI reset IS-ASSERTED", v__h1613); end // synopsys translate_on endmodule // mkWciMonitor diff --git a/rtl/mkWciTarget.v b/rtl/mkWciTarget.v index a9ffb83c..21710cc4 100644 --- a/rtl/mkWciTarget.v +++ b/rtl/mkWciTarget.v @@ -1,7 +1,7 @@ // -// Generated by Bluespec Compiler, version 2012.09.beta1 (build 29570, 2012-09.11) +// Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Tue Dec 11 16:19:52 EST 2012 +// On Fri Jun 21 16:57:04 EDT 2013 // // // Ports: @@ -175,10 +175,10 @@ module mkWciTarget(wciS0_Clk, wire [1 : 0] target_reqF_countReg$D_IN; wire target_reqF_countReg$EN; - // register target_respF_c_r - reg [1 : 0] target_respF_c_r; - wire [1 : 0] target_respF_c_r$D_IN; - wire target_respF_c_r$EN; + // register target_respF_cntr_r + reg [1 : 0] target_respF_cntr_r; + wire [1 : 0] target_respF_cntr_r$D_IN; + wire target_respF_cntr_r$EN; // register target_respF_q_0 reg [33 : 0] target_respF_q_0; @@ -219,17 +219,20 @@ module mkWciTarget(wciS0_Clk, MUX_target_respF_q_1$write_1__VAL_1, MUX_target_respF_x_wire$wset_1__VAL_1, MUX_target_respF_x_wire$wset_1__VAL_2; - wire [1 : 0] MUX_target_respF_c_r$write_1__VAL_1, - MUX_target_respF_c_r$write_1__VAL_2; + wire [1 : 0] MUX_target_respF_cntr_r$write_1__VAL_2; wire MUX_target_illegalEdge$write_1__SEL_1, MUX_target_illegalEdge$write_1__SEL_2, MUX_target_illegalEdge$write_1__VAL_2, MUX_target_respF_q_0$write_1__SEL_1, + MUX_target_respF_q_0$write_1__SEL_2, + MUX_target_respF_q_1$write_1__SEL_1, MUX_target_respF_q_1$write_1__SEL_2; // remaining internal signals - reg [63 : 0] v__h3690, v__h3865, v__h4009, v__h4302, v__h4560, v__h4715; - reg [31 : 0] _theResult____h4699; + reg [63 : 0] v__h3558, v__h3733, v__h3877, v__h4170, v__h4428, v__h4583; + reg [31 : 0] _theResult____h4567; + wire [1 : 0] target_respF_cntr_r_8_MINUS_1___d27; + wire _dfoo1, _dfoo3; // value method wciS0_sResp assign wciS0_SResp = target_respF_q_0[33:32] ; @@ -263,12 +266,12 @@ module mkWciTarget(wciS0_Clk, // rule RL_target_cfwr assign WILL_FIRE_RL_target_cfwr = - target_respF_c_r != 2'd2 && target_reqF$EMPTY_N && + target_respF_cntr_r != 2'd2 && target_reqF$EMPTY_N && target_wci_cfwr_pw$whas ; // rule RL_target_cfrd assign WILL_FIRE_RL_target_cfrd = - target_respF_c_r != 2'd2 && target_reqF$EMPTY_N && + target_respF_cntr_r != 2'd2 && target_reqF$EMPTY_N && target_wci_cfrd_pw$whas && !WILL_FIRE_RL_target_cfwr ; @@ -287,29 +290,23 @@ module mkWciTarget(wciS0_Clk, // rule RL_target_ctl_op_complete assign WILL_FIRE_RL_target_ctl_op_complete = - target_respF_c_r != 2'd2 && target_ctlOpActive && + target_respF_cntr_r != 2'd2 && target_ctlOpActive && target_ctlAckReg && !WILL_FIRE_RL_target_cfrd && !WILL_FIRE_RL_target_cfwr ; // rule RL_target_respF_incCtr assign WILL_FIRE_RL_target_respF_incCtr = - ((target_respF_c_r == 2'd0) ? - target_respF_x_wire$whas : - target_respF_c_r != 2'd1 || target_respF_x_wire$whas) && - target_respF_enqueueing$whas && - !(target_respF_c_r != 2'd0) ; + target_respF_x_wire$whas && target_respF_enqueueing$whas && + !(target_respF_cntr_r != 2'd0) ; // rule RL_target_respF_decCtr assign WILL_FIRE_RL_target_respF_decCtr = - target_respF_c_r != 2'd0 && !target_respF_enqueueing$whas ; + target_respF_cntr_r != 2'd0 && !target_respF_enqueueing$whas ; // rule RL_target_respF_both assign WILL_FIRE_RL_target_respF_both = - ((target_respF_c_r == 2'd1) ? - target_respF_x_wire$whas : - target_respF_c_r != 2'd2 || target_respF_x_wire$whas) && - target_respF_c_r != 2'd0 && + target_respF_x_wire$whas && target_respF_cntr_r != 2'd0 && target_respF_enqueueing$whas ; // inputs to muxes for submodule ports @@ -329,15 +326,18 @@ module mkWciTarget(wciS0_Clk, target_reqF$D_OUT[36:34] == 3'd6 || target_reqF$D_OUT[36:34] == 3'd7) ; assign MUX_target_respF_q_0$write_1__SEL_1 = - WILL_FIRE_RL_target_respF_incCtr && target_respF_c_r == 2'd0 ; + WILL_FIRE_RL_target_respF_incCtr && target_respF_cntr_r == 2'd0 ; + assign MUX_target_respF_q_0$write_1__SEL_2 = + WILL_FIRE_RL_target_respF_both && _dfoo3 ; + assign MUX_target_respF_q_1$write_1__SEL_1 = + WILL_FIRE_RL_target_respF_both && _dfoo1 ; assign MUX_target_respF_q_1$write_1__SEL_2 = - WILL_FIRE_RL_target_respF_incCtr && target_respF_c_r == 2'd1 ; + WILL_FIRE_RL_target_respF_incCtr && target_respF_cntr_r == 2'd1 ; assign MUX_target_illegalEdge$write_1__VAL_2 = target_reqF$D_OUT[36:34] != 3'd4 && target_reqF$D_OUT[36:34] != 3'd5 && target_reqF$D_OUT[36:34] != 3'd6 ; - assign MUX_target_respF_c_r$write_1__VAL_1 = target_respF_c_r + 2'd1 ; - assign MUX_target_respF_c_r$write_1__VAL_2 = target_respF_c_r - 2'd1 ; + assign MUX_target_respF_cntr_r$write_1__VAL_2 = target_respF_cntr_r + 2'd1 ; always@(WILL_FIRE_RL_target_ctl_op_complete or MUX_target_respF_x_wire$wset_1__VAL_1 or WILL_FIRE_RL_target_cfrd or @@ -357,17 +357,17 @@ module mkWciTarget(wciS0_Clk, endcase end assign MUX_target_respF_q_0$write_1__VAL_2 = - (target_respF_c_r == 2'd1) ? + (target_respF_cntr_r == 2'd1) ? MUX_target_respF_q_0$write_1__VAL_1 : target_respF_q_1 ; assign MUX_target_respF_q_1$write_1__VAL_1 = - (target_respF_c_r == 2'd2) ? + (target_respF_cntr_r == 2'd2) ? MUX_target_respF_q_0$write_1__VAL_1 : 34'h0AAAAAAAA ; assign MUX_target_respF_x_wire$wset_1__VAL_1 = target_illegalEdge ? 34'h3C0DE4202 : 34'h1C0DE4201 ; assign MUX_target_respF_x_wire$wset_1__VAL_2 = - { 2'd1, _theResult____h4699 } ; + { 2'd1, _theResult____h4567 } ; // inlined wires assign target_wciReq$wget = @@ -413,7 +413,7 @@ module mkWciTarget(wciS0_Clk, assign target_respF_enqueueing$whas = WILL_FIRE_RL_target_cfrd || WILL_FIRE_RL_target_cfwr || WILL_FIRE_RL_target_ctl_op_complete ; - assign target_respF_dequeueing$whas = target_respF_c_r != 2'd0 ; + assign target_respF_dequeueing$whas = target_respF_cntr_r != 2'd0 ; assign target_sThreadBusy_pw$whas = 1'b0 ; assign target_wci_cfwr_pw$whas = target_reqF$EMPTY_N && target_reqF$D_OUT[68] && @@ -502,26 +502,26 @@ module mkWciTarget(wciS0_Clk, assign target_reqF_countReg$EN = (target_wciReq$wget[71:69] != 3'd0) != target_reqF_r_deq$whas ; - // register target_respF_c_r - assign target_respF_c_r$D_IN = - WILL_FIRE_RL_target_respF_incCtr ? - MUX_target_respF_c_r$write_1__VAL_1 : - MUX_target_respF_c_r$write_1__VAL_2 ; - assign target_respF_c_r$EN = - WILL_FIRE_RL_target_respF_incCtr || - WILL_FIRE_RL_target_respF_decCtr ; + // register target_respF_cntr_r + assign target_respF_cntr_r$D_IN = + WILL_FIRE_RL_target_respF_decCtr ? + target_respF_cntr_r_8_MINUS_1___d27 : + MUX_target_respF_cntr_r$write_1__VAL_2 ; + assign target_respF_cntr_r$EN = + WILL_FIRE_RL_target_respF_decCtr || + WILL_FIRE_RL_target_respF_incCtr ; // register target_respF_q_0 always@(MUX_target_respF_q_0$write_1__SEL_1 or MUX_target_respF_q_0$write_1__VAL_1 or - WILL_FIRE_RL_target_respF_both or + MUX_target_respF_q_0$write_1__SEL_2 or MUX_target_respF_q_0$write_1__VAL_2 or WILL_FIRE_RL_target_respF_decCtr or target_respF_q_1) begin case (1'b1) // synopsys parallel_case MUX_target_respF_q_0$write_1__SEL_1: target_respF_q_0$D_IN = MUX_target_respF_q_0$write_1__VAL_1; - WILL_FIRE_RL_target_respF_both: + MUX_target_respF_q_0$write_1__SEL_2: target_respF_q_0$D_IN = MUX_target_respF_q_0$write_1__VAL_2; WILL_FIRE_RL_target_respF_decCtr: target_respF_q_0$D_IN = target_respF_q_1; @@ -529,19 +529,20 @@ module mkWciTarget(wciS0_Clk, endcase end assign target_respF_q_0$EN = - WILL_FIRE_RL_target_respF_incCtr && target_respF_c_r == 2'd0 || - WILL_FIRE_RL_target_respF_both || + WILL_FIRE_RL_target_respF_incCtr && + target_respF_cntr_r == 2'd0 || + WILL_FIRE_RL_target_respF_both && _dfoo3 || WILL_FIRE_RL_target_respF_decCtr ; // register target_respF_q_1 - always@(WILL_FIRE_RL_target_respF_both or + always@(MUX_target_respF_q_1$write_1__SEL_1 or MUX_target_respF_q_1$write_1__VAL_1 or MUX_target_respF_q_1$write_1__SEL_2 or MUX_target_respF_q_0$write_1__VAL_1 or WILL_FIRE_RL_target_respF_decCtr) begin case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_target_respF_both: + MUX_target_respF_q_1$write_1__SEL_1: target_respF_q_1$D_IN = MUX_target_respF_q_1$write_1__VAL_1; MUX_target_respF_q_1$write_1__SEL_2: target_respF_q_1$D_IN = MUX_target_respF_q_0$write_1__VAL_1; @@ -550,8 +551,9 @@ module mkWciTarget(wciS0_Clk, endcase end assign target_respF_q_1$EN = - WILL_FIRE_RL_target_respF_both || - WILL_FIRE_RL_target_respF_incCtr && target_respF_c_r == 2'd1 || + WILL_FIRE_RL_target_respF_both && _dfoo1 || + WILL_FIRE_RL_target_respF_incCtr && + target_respF_cntr_r == 2'd1 || WILL_FIRE_RL_target_respF_decCtr ; // register target_sFlagReg @@ -569,12 +571,19 @@ module mkWciTarget(wciS0_Clk, assign target_reqF$CLR = 1'b0 ; // remaining internal signals + assign _dfoo1 = + target_respF_cntr_r != 2'd2 || + target_respF_cntr_r_8_MINUS_1___d27 == 2'd1 ; + assign _dfoo3 = + target_respF_cntr_r != 2'd1 || + target_respF_cntr_r_8_MINUS_1___d27 == 2'd0 ; + assign target_respF_cntr_r_8_MINUS_1___d27 = target_respF_cntr_r - 2'd1 ; always@(target_reqF$D_OUT or biasValue or controlReg) begin case (target_reqF$D_OUT[39:32]) - 8'h0: _theResult____h4699 = biasValue; - 8'h04: _theResult____h4699 = controlReg; - default: _theResult____h4699 = 32'd0; + 8'h0: _theResult____h4567 = biasValue; + 8'h04: _theResult____h4567 = controlReg; + default: _theResult____h4567 = 32'd0; endcase end @@ -592,7 +601,7 @@ module mkWciTarget(wciS0_Clk, target_illegalEdge <= `BSV_ASSIGNMENT_DELAY 1'd0; target_nState <= `BSV_ASSIGNMENT_DELAY 3'd0; target_reqF_countReg <= `BSV_ASSIGNMENT_DELAY 2'd0; - target_respF_c_r <= `BSV_ASSIGNMENT_DELAY 2'd0; + target_respF_cntr_r <= `BSV_ASSIGNMENT_DELAY 2'd0; target_respF_q_0 <= `BSV_ASSIGNMENT_DELAY 34'h0AAAAAAAA; target_respF_q_1 <= `BSV_ASSIGNMENT_DELAY 34'h0AAAAAAAA; target_sFlagReg <= `BSV_ASSIGNMENT_DELAY 1'd0; @@ -616,8 +625,9 @@ module mkWciTarget(wciS0_Clk, if (target_reqF_countReg$EN) target_reqF_countReg <= `BSV_ASSIGNMENT_DELAY target_reqF_countReg$D_IN; - if (target_respF_c_r$EN) - target_respF_c_r <= `BSV_ASSIGNMENT_DELAY target_respF_c_r$D_IN; + if (target_respF_cntr_r$EN) + target_respF_cntr_r <= `BSV_ASSIGNMENT_DELAY + target_respF_cntr_r$D_IN; if (target_respF_q_0$EN) target_respF_q_0 <= `BSV_ASSIGNMENT_DELAY target_respF_q_0$D_IN; if (target_respF_q_1$EN) @@ -660,7 +670,7 @@ module mkWciTarget(wciS0_Clk, target_isReset_isInReset = 1'h0; target_nState = 3'h2; target_reqF_countReg = 2'h2; - target_respF_c_r = 2'h2; + target_respF_cntr_r = 2'h2; target_respF_q_0 = 34'h2AAAAAAAA; target_respF_q_1 = 34'h2AAAAAAAA; target_sFlagReg = 1'h0; @@ -678,72 +688,72 @@ module mkWciTarget(wciS0_Clk, if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_report_operating) begin - v__h4302 = $time; + v__h4170 = $time; #0; end if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_report_operating) - $display("[%0d]: %m: WCI Target is Operating", v__h4302); + $display("[%0d]: %m: WCI Target is Operating", v__h4170); if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_target_cfwr) begin - v__h4560 = $time; + v__h4428 = $time; #0; end if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_target_cfwr) $display("[%0d]: %m: WCI TARGET CONFIG WRITE Addr:%0x BE:%0x Data:%0x", - v__h4560, + v__h4428, target_reqF$D_OUT[63:32], target_reqF$D_OUT[67:64], target_reqF$D_OUT[31:0]); if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_target_cfrd) begin - v__h4715 = $time; + v__h4583 = $time; #0; end if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_target_cfrd) $display("[%0d]: %m: WCI TARGET CONFIG READ Addr:%0x BE:%0x Data:%0x", - v__h4715, + v__h4583, target_reqF$D_OUT[63:32], target_reqF$D_OUT[67:64], - _theResult____h4699); + _theResult____h4567); if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_target_ctl_op_start) begin - v__h3690 = $time; + v__h3558 = $time; #0; end if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_target_ctl_op_start) $display("[%0d]: %m: WCI ControlOp: Starting-transition edge:%x from:%x", - v__h3690, + v__h3558, target_reqF$D_OUT[36:34], target_cState); if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_target_ctl_op_complete && target_illegalEdge) begin - v__h4009 = $time; + v__h3877 = $time; #0; end if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_target_ctl_op_complete && target_illegalEdge) $display("[%0d]: %m: WCI ControlOp: ILLEGAL-EDGE Completed-transition edge:%x from:%x", - v__h4009, + v__h3877, target_cEdge, target_cState); if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_target_ctl_op_complete && !target_illegalEdge) begin - v__h3865 = $time; + v__h3733 = $time; #0; end if (wciS0_MReset_n != `BSV_RESET_VALUE) if (WILL_FIRE_RL_target_ctl_op_complete && !target_illegalEdge) $display("[%0d]: %m: WCI ControlOp: Completed-transition edge:%x from:%x to:%x", - v__h3865, + v__h3733, target_cEdge, target_cState, target_nState); diff --git a/rtl/mkWsiAdapter16B4B.v b/rtl/mkWsiAdapter16B4B.v index 80e9b8b7..8f7417d4 100644 --- a/rtl/mkWsiAdapter16B4B.v +++ b/rtl/mkWsiAdapter16B4B.v @@ -1,7 +1,7 @@ // -// Generated by Bluespec Compiler, version 2012.09.beta1 (build 29570, 2012-09.11) +// Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Wed Nov 28 10:32:20 EST 2012 +// On Fri Jun 21 16:57:41 EDT 2013 // // // Ports: @@ -255,10 +255,10 @@ module mkWsiAdapter16B4B(CLK, reg wsiM_peerIsReady; wire wsiM_peerIsReady$D_IN, wsiM_peerIsReady$EN; - // register wsiM_reqFifo_c_r - reg [1 : 0] wsiM_reqFifo_c_r; - wire [1 : 0] wsiM_reqFifo_c_r$D_IN; - wire wsiM_reqFifo_c_r$EN; + // register wsiM_reqFifo_cntr_r + reg [1 : 0] wsiM_reqFifo_cntr_r; + wire [1 : 0] wsiM_reqFifo_cntr_r$D_IN; + wire wsiM_reqFifo_cntr_r$EN; // register wsiM_reqFifo_q_0 reg [60 : 0] wsiM_reqFifo_q_0; @@ -372,16 +372,19 @@ module mkWsiAdapter16B4B(CLK, wire [60 : 0] MUX_wsiM_reqFifo_q_0$write_1__VAL_1, MUX_wsiM_reqFifo_q_0$write_1__VAL_2, MUX_wsiM_reqFifo_q_1$write_1__VAL_1; - wire [1 : 0] MUX_wsiM_reqFifo_c_r$write_1__VAL_1, - MUX_wsiM_reqFifo_c_r$write_1__VAL_2; - wire MUX_wsiM_reqFifo_q_0$write_1__SEL_2, + wire [1 : 0] MUX_wsiM_reqFifo_cntr_r$write_1__VAL_1, + MUX_wsiM_reqFifo_cntr_r$write_1__VAL_2; + wire MUX_wsiM_reqFifo_q_0$write_1__SEL_1, + MUX_wsiM_reqFifo_q_0$write_1__SEL_2, + MUX_wsiM_reqFifo_q_1$write_1__SEL_1, MUX_wsiM_reqFifo_q_1$write_1__SEL_2, MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3; // remaining internal signals - reg [31 : 0] x_data__h6106; - reg [3 : 0] x_byteEn__h6107; - wire [11 : 0] x_burstLength__h6105; + reg [31 : 0] x_data__h5956; + reg [3 : 0] x_byteEn__h5957; + wire [11 : 0] x_burstLength__h5955; + wire _dfoo1, _dfoo3; // value method wsiS0_sThreadBusy assign wsiS0_SThreadBusy = @@ -431,14 +434,11 @@ module mkWsiAdapter16B4B(CLK, // rule RL_wsiM_reqFifo_deq assign WILL_FIRE_RL_wsiM_reqFifo_deq = - wsiM_reqFifo_c_r != 2'd0 && !wsiM_sThreadBusy_d ; + wsiM_reqFifo_cntr_r != 2'd0 && !wsiM_sThreadBusy_d ; // rule RL_wsiM_reqFifo_incCtr assign WILL_FIRE_RL_wsiM_reqFifo_incCtr = - ((wsiM_reqFifo_c_r == 2'd0) ? - wsiM_reqFifo_enqueueing$whas : - wsiM_reqFifo_c_r != 2'd1 || wsiM_reqFifo_enqueueing$whas) && - wsiM_reqFifo_enqueueing$whas && + wsiM_reqFifo_enqueueing$whas && wsiM_reqFifo_enqueueing$whas && !WILL_FIRE_RL_wsiM_reqFifo_deq ; // rule RL_wsiM_reqFifo_decCtr @@ -447,10 +447,7 @@ module mkWsiAdapter16B4B(CLK, // rule RL_wsiM_reqFifo_both assign WILL_FIRE_RL_wsiM_reqFifo_both = - ((wsiM_reqFifo_c_r == 2'd1) ? - wsiM_reqFifo_enqueueing$whas : - wsiM_reqFifo_c_r != 2'd2 || wsiM_reqFifo_enqueueing$whas) && - WILL_FIRE_RL_wsiM_reqFifo_deq && + wsiM_reqFifo_enqueueing$whas && WILL_FIRE_RL_wsiM_reqFifo_deq && wsiM_reqFifo_enqueueing$whas ; // rule RL_wsiS_reqFifo_enq @@ -464,28 +461,32 @@ module mkWsiAdapter16B4B(CLK, MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 ; // inputs to muxes for submodule ports + assign MUX_wsiM_reqFifo_q_0$write_1__SEL_1 = + WILL_FIRE_RL_wsiM_reqFifo_both && _dfoo3 ; assign MUX_wsiM_reqFifo_q_0$write_1__SEL_2 = - WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_c_r == 2'd0 ; + WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_cntr_r == 2'd0 ; + assign MUX_wsiM_reqFifo_q_1$write_1__SEL_1 = + WILL_FIRE_RL_wsiM_reqFifo_both && _dfoo1 ; assign MUX_wsiM_reqFifo_q_1$write_1__SEL_2 = - WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_c_r == 2'd1 ; + WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_cntr_r == 2'd1 ; assign MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 = wsiS_reqFifo$EMPTY_N && isEmpty ; - assign MUX_wsiM_reqFifo_c_r$write_1__VAL_1 = wsiM_reqFifo_c_r + 2'd1 ; - assign MUX_wsiM_reqFifo_c_r$write_1__VAL_2 = wsiM_reqFifo_c_r - 2'd1 ; + assign MUX_wsiM_reqFifo_cntr_r$write_1__VAL_1 = wsiM_reqFifo_cntr_r - 2'd1 ; + assign MUX_wsiM_reqFifo_cntr_r$write_1__VAL_2 = wsiM_reqFifo_cntr_r + 2'd1 ; assign MUX_wsiM_reqFifo_q_0$write_1__VAL_1 = - (wsiM_reqFifo_c_r == 2'd1) ? + (wsiM_reqFifo_cntr_r == 2'd1) ? MUX_wsiM_reqFifo_q_0$write_1__VAL_2 : wsiM_reqFifo_q_1 ; assign MUX_wsiM_reqFifo_q_0$write_1__VAL_2 = { 3'd1, isLast && pos == 2'd3, req16[164], - x_burstLength__h6105, - x_data__h6106, - x_byteEn__h6107, + x_burstLength__h5955, + x_data__h5956, + x_byteEn__h5957, req16[7:0] } ; assign MUX_wsiM_reqFifo_q_1$write_1__VAL_1 = - (wsiM_reqFifo_c_r == 2'd2) ? + (wsiM_reqFifo_cntr_r == 2'd2) ? MUX_wsiM_reqFifo_q_0$write_1__VAL_2 : 61'h00000AAAAAAAAA00 ; @@ -530,7 +531,8 @@ module mkWsiAdapter16B4B(CLK, assign wsiS_reqFifo_doResetDeq$whas = MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 ; assign wsiS_reqFifo_doResetClr$whas = 1'b0 ; - assign wsiM_reqFifo_enqueueing$whas = wsiM_reqFifo_c_r != 2'd2 && !isEmpty ; + assign wsiM_reqFifo_enqueueing$whas = + wsiM_reqFifo_cntr_r != 2'd2 && !isEmpty ; assign wsiM_reqFifo_dequeueing$whas = WILL_FIRE_RL_wsiM_reqFifo_deq ; assign wsiM_sThreadBusy_pw$whas = wsiM0_SThreadBusy ; assign wsi_Es_mReqLast_w$whas = wsiS0_MReqLast ; @@ -603,24 +605,24 @@ module mkWsiAdapter16B4B(CLK, assign wsiM_peerIsReady$D_IN = wsiM0_SReset_n ; assign wsiM_peerIsReady$EN = 1'd1 ; - // register wsiM_reqFifo_c_r - assign wsiM_reqFifo_c_r$D_IN = - WILL_FIRE_RL_wsiM_reqFifo_incCtr ? - MUX_wsiM_reqFifo_c_r$write_1__VAL_1 : - MUX_wsiM_reqFifo_c_r$write_1__VAL_2 ; - assign wsiM_reqFifo_c_r$EN = - WILL_FIRE_RL_wsiM_reqFifo_incCtr || - WILL_FIRE_RL_wsiM_reqFifo_decCtr ; + // register wsiM_reqFifo_cntr_r + assign wsiM_reqFifo_cntr_r$D_IN = + WILL_FIRE_RL_wsiM_reqFifo_decCtr ? + MUX_wsiM_reqFifo_cntr_r$write_1__VAL_1 : + MUX_wsiM_reqFifo_cntr_r$write_1__VAL_2 ; + assign wsiM_reqFifo_cntr_r$EN = + WILL_FIRE_RL_wsiM_reqFifo_decCtr || + WILL_FIRE_RL_wsiM_reqFifo_incCtr ; // register wsiM_reqFifo_q_0 - always@(WILL_FIRE_RL_wsiM_reqFifo_both or + always@(MUX_wsiM_reqFifo_q_0$write_1__SEL_1 or MUX_wsiM_reqFifo_q_0$write_1__VAL_1 or MUX_wsiM_reqFifo_q_0$write_1__SEL_2 or MUX_wsiM_reqFifo_q_0$write_1__VAL_2 or WILL_FIRE_RL_wsiM_reqFifo_decCtr or wsiM_reqFifo_q_1) begin case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_wsiM_reqFifo_both: + MUX_wsiM_reqFifo_q_0$write_1__SEL_1: wsiM_reqFifo_q_0$D_IN = MUX_wsiM_reqFifo_q_0$write_1__VAL_1; MUX_wsiM_reqFifo_q_0$write_1__SEL_2: wsiM_reqFifo_q_0$D_IN = MUX_wsiM_reqFifo_q_0$write_1__VAL_2; @@ -631,19 +633,20 @@ module mkWsiAdapter16B4B(CLK, endcase end assign wsiM_reqFifo_q_0$EN = - WILL_FIRE_RL_wsiM_reqFifo_both || - WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_c_r == 2'd0 || + WILL_FIRE_RL_wsiM_reqFifo_both && _dfoo3 || + WILL_FIRE_RL_wsiM_reqFifo_incCtr && + wsiM_reqFifo_cntr_r == 2'd0 || WILL_FIRE_RL_wsiM_reqFifo_decCtr ; // register wsiM_reqFifo_q_1 - always@(WILL_FIRE_RL_wsiM_reqFifo_both or + always@(MUX_wsiM_reqFifo_q_1$write_1__SEL_1 or MUX_wsiM_reqFifo_q_1$write_1__VAL_1 or MUX_wsiM_reqFifo_q_1$write_1__SEL_2 or MUX_wsiM_reqFifo_q_0$write_1__VAL_2 or WILL_FIRE_RL_wsiM_reqFifo_decCtr) begin case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_wsiM_reqFifo_both: + MUX_wsiM_reqFifo_q_1$write_1__SEL_1: wsiM_reqFifo_q_1$D_IN = MUX_wsiM_reqFifo_q_1$write_1__VAL_1; MUX_wsiM_reqFifo_q_1$write_1__SEL_2: wsiM_reqFifo_q_1$D_IN = MUX_wsiM_reqFifo_q_0$write_1__VAL_2; @@ -654,8 +657,9 @@ module mkWsiAdapter16B4B(CLK, endcase end assign wsiM_reqFifo_q_1$EN = - WILL_FIRE_RL_wsiM_reqFifo_both || - WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_c_r == 2'd1 || + WILL_FIRE_RL_wsiM_reqFifo_both && _dfoo1 || + WILL_FIRE_RL_wsiM_reqFifo_incCtr && + wsiM_reqFifo_cntr_r == 2'd1 || WILL_FIRE_RL_wsiM_reqFifo_decCtr ; // register wsiM_sThreadBusy_d @@ -779,23 +783,29 @@ module mkWsiAdapter16B4B(CLK, assign wsiS_reqFifo$CLR = 1'b0 ; // remaining internal signals - assign x_burstLength__h6105 = { req16[161:152], 2'd0 } ; + assign _dfoo1 = + wsiM_reqFifo_cntr_r != 2'd2 || + MUX_wsiM_reqFifo_cntr_r$write_1__VAL_1 == 2'd1 ; + assign _dfoo3 = + wsiM_reqFifo_cntr_r != 2'd1 || + MUX_wsiM_reqFifo_cntr_r$write_1__VAL_1 == 2'd0 ; + assign x_burstLength__h5955 = { req16[161:152], 2'd0 } ; always@(pos or req16) begin case (pos) - 2'd0: x_data__h6106 = req16[55:24]; - 2'd1: x_data__h6106 = req16[87:56]; - 2'd2: x_data__h6106 = req16[119:88]; - 2'd3: x_data__h6106 = req16[151:120]; + 2'd0: x_data__h5956 = req16[55:24]; + 2'd1: x_data__h5956 = req16[87:56]; + 2'd2: x_data__h5956 = req16[119:88]; + 2'd3: x_data__h5956 = req16[151:120]; endcase end always@(pos or req16) begin case (pos) - 2'd0: x_byteEn__h6107 = req16[11:8]; - 2'd1: x_byteEn__h6107 = req16[15:12]; - 2'd2: x_byteEn__h6107 = req16[19:16]; - 2'd3: x_byteEn__h6107 = req16[23:20]; + 2'd0: x_byteEn__h5957 = req16[11:8]; + 2'd1: x_byteEn__h5957 = req16[15:12]; + 2'd2: x_byteEn__h5957 = req16[19:16]; + 2'd3: x_byteEn__h5957 = req16[23:20]; endcase end @@ -814,7 +824,7 @@ module mkWsiAdapter16B4B(CLK, wsiM_operateD <= `BSV_ASSIGNMENT_DELAY 1'd0; wsiM_pMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0; wsiM_peerIsReady <= `BSV_ASSIGNMENT_DELAY 1'd0; - wsiM_reqFifo_c_r <= `BSV_ASSIGNMENT_DELAY 2'd0; + wsiM_reqFifo_cntr_r <= `BSV_ASSIGNMENT_DELAY 2'd0; wsiM_reqFifo_q_0 <= `BSV_ASSIGNMENT_DELAY 61'h00000AAAAAAAAA00; wsiM_reqFifo_q_1 <= `BSV_ASSIGNMENT_DELAY 61'h00000AAAAAAAAA00; wsiM_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY 1'd1; @@ -849,8 +859,9 @@ module mkWsiAdapter16B4B(CLK, wsiM_pMesgCount <= `BSV_ASSIGNMENT_DELAY wsiM_pMesgCount$D_IN; if (wsiM_peerIsReady$EN) wsiM_peerIsReady <= `BSV_ASSIGNMENT_DELAY wsiM_peerIsReady$D_IN; - if (wsiM_reqFifo_c_r$EN) - wsiM_reqFifo_c_r <= `BSV_ASSIGNMENT_DELAY wsiM_reqFifo_c_r$D_IN; + if (wsiM_reqFifo_cntr_r$EN) + wsiM_reqFifo_cntr_r <= `BSV_ASSIGNMENT_DELAY + wsiM_reqFifo_cntr_r$D_IN; if (wsiM_reqFifo_q_0$EN) wsiM_reqFifo_q_0 <= `BSV_ASSIGNMENT_DELAY wsiM_reqFifo_q_0$D_IN; if (wsiM_reqFifo_q_1$EN) @@ -927,7 +938,7 @@ module mkWsiAdapter16B4B(CLK, wsiM_operateD = 1'h0; wsiM_pMesgCount = 32'hAAAAAAAA; wsiM_peerIsReady = 1'h0; - wsiM_reqFifo_c_r = 2'h2; + wsiM_reqFifo_cntr_r = 2'h2; wsiM_reqFifo_q_0 = 61'h0AAAAAAAAAAAAAAA; wsiM_reqFifo_q_1 = 61'h0AAAAAAAAAAAAAAA; wsiM_sThreadBusy_d = 1'h0; diff --git a/rtl/mkWsiAdapter32B4B.v b/rtl/mkWsiAdapter32B4B.v index 8254899f..225486bc 100644 --- a/rtl/mkWsiAdapter32B4B.v +++ b/rtl/mkWsiAdapter32B4B.v @@ -1,7 +1,7 @@ // -// Generated by Bluespec Compiler, version 2012.09.beta1 (build 29570, 2012-09.11) +// Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Wed Nov 28 10:32:21 EST 2012 +// On Fri Jun 21 16:57:42 EDT 2013 // // // Ports: @@ -255,10 +255,10 @@ module mkWsiAdapter32B4B(CLK, reg wsiM_peerIsReady; wire wsiM_peerIsReady$D_IN, wsiM_peerIsReady$EN; - // register wsiM_reqFifo_c_r - reg [1 : 0] wsiM_reqFifo_c_r; - wire [1 : 0] wsiM_reqFifo_c_r$D_IN; - wire wsiM_reqFifo_c_r$EN; + // register wsiM_reqFifo_cntr_r + reg [1 : 0] wsiM_reqFifo_cntr_r; + wire [1 : 0] wsiM_reqFifo_cntr_r$D_IN; + wire wsiM_reqFifo_cntr_r$EN; // register wsiM_reqFifo_q_0 reg [60 : 0] wsiM_reqFifo_q_0; @@ -372,16 +372,19 @@ module mkWsiAdapter32B4B(CLK, wire [60 : 0] MUX_wsiM_reqFifo_q_0$write_1__VAL_1, MUX_wsiM_reqFifo_q_0$write_1__VAL_2, MUX_wsiM_reqFifo_q_1$write_1__VAL_1; - wire [1 : 0] MUX_wsiM_reqFifo_c_r$write_1__VAL_1, - MUX_wsiM_reqFifo_c_r$write_1__VAL_2; - wire MUX_wsiM_reqFifo_q_0$write_1__SEL_2, + wire [1 : 0] MUX_wsiM_reqFifo_cntr_r$write_1__VAL_1, + MUX_wsiM_reqFifo_cntr_r$write_1__VAL_2; + wire MUX_wsiM_reqFifo_q_0$write_1__SEL_1, + MUX_wsiM_reqFifo_q_0$write_1__SEL_2, + MUX_wsiM_reqFifo_q_1$write_1__SEL_1, MUX_wsiM_reqFifo_q_1$write_1__SEL_2, MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3; // remaining internal signals - reg [31 : 0] x_data__h6106; - reg [3 : 0] x_byteEn__h6107; - wire [11 : 0] x_burstLength__h6105; + reg [31 : 0] x_data__h5956; + reg [3 : 0] x_byteEn__h5957; + wire [11 : 0] x_burstLength__h5955; + wire _dfoo1, _dfoo3; // value method wsiS0_sThreadBusy assign wsiS0_SThreadBusy = @@ -431,14 +434,11 @@ module mkWsiAdapter32B4B(CLK, // rule RL_wsiM_reqFifo_deq assign WILL_FIRE_RL_wsiM_reqFifo_deq = - wsiM_reqFifo_c_r != 2'd0 && !wsiM_sThreadBusy_d ; + wsiM_reqFifo_cntr_r != 2'd0 && !wsiM_sThreadBusy_d ; // rule RL_wsiM_reqFifo_incCtr assign WILL_FIRE_RL_wsiM_reqFifo_incCtr = - ((wsiM_reqFifo_c_r == 2'd0) ? - wsiM_reqFifo_enqueueing$whas : - wsiM_reqFifo_c_r != 2'd1 || wsiM_reqFifo_enqueueing$whas) && - wsiM_reqFifo_enqueueing$whas && + wsiM_reqFifo_enqueueing$whas && wsiM_reqFifo_enqueueing$whas && !WILL_FIRE_RL_wsiM_reqFifo_deq ; // rule RL_wsiM_reqFifo_decCtr @@ -447,10 +447,7 @@ module mkWsiAdapter32B4B(CLK, // rule RL_wsiM_reqFifo_both assign WILL_FIRE_RL_wsiM_reqFifo_both = - ((wsiM_reqFifo_c_r == 2'd1) ? - wsiM_reqFifo_enqueueing$whas : - wsiM_reqFifo_c_r != 2'd2 || wsiM_reqFifo_enqueueing$whas) && - WILL_FIRE_RL_wsiM_reqFifo_deq && + wsiM_reqFifo_enqueueing$whas && WILL_FIRE_RL_wsiM_reqFifo_deq && wsiM_reqFifo_enqueueing$whas ; // rule RL_wsiS_reqFifo_enq @@ -464,28 +461,32 @@ module mkWsiAdapter32B4B(CLK, MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 ; // inputs to muxes for submodule ports + assign MUX_wsiM_reqFifo_q_0$write_1__SEL_1 = + WILL_FIRE_RL_wsiM_reqFifo_both && _dfoo3 ; assign MUX_wsiM_reqFifo_q_0$write_1__SEL_2 = - WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_c_r == 2'd0 ; + WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_cntr_r == 2'd0 ; + assign MUX_wsiM_reqFifo_q_1$write_1__SEL_1 = + WILL_FIRE_RL_wsiM_reqFifo_both && _dfoo1 ; assign MUX_wsiM_reqFifo_q_1$write_1__SEL_2 = - WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_c_r == 2'd1 ; + WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_cntr_r == 2'd1 ; assign MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 = wsiS_reqFifo$EMPTY_N && isEmpty ; - assign MUX_wsiM_reqFifo_c_r$write_1__VAL_1 = wsiM_reqFifo_c_r + 2'd1 ; - assign MUX_wsiM_reqFifo_c_r$write_1__VAL_2 = wsiM_reqFifo_c_r - 2'd1 ; + assign MUX_wsiM_reqFifo_cntr_r$write_1__VAL_1 = wsiM_reqFifo_cntr_r - 2'd1 ; + assign MUX_wsiM_reqFifo_cntr_r$write_1__VAL_2 = wsiM_reqFifo_cntr_r + 2'd1 ; assign MUX_wsiM_reqFifo_q_0$write_1__VAL_1 = - (wsiM_reqFifo_c_r == 2'd1) ? + (wsiM_reqFifo_cntr_r == 2'd1) ? MUX_wsiM_reqFifo_q_0$write_1__VAL_2 : wsiM_reqFifo_q_1 ; assign MUX_wsiM_reqFifo_q_0$write_1__VAL_2 = { 3'd1, isLast && pos == 3'd7, req32[308], - x_burstLength__h6105, - x_data__h6106, - x_byteEn__h6107, + x_burstLength__h5955, + x_data__h5956, + x_byteEn__h5957, req32[7:0] } ; assign MUX_wsiM_reqFifo_q_1$write_1__VAL_1 = - (wsiM_reqFifo_c_r == 2'd2) ? + (wsiM_reqFifo_cntr_r == 2'd2) ? MUX_wsiM_reqFifo_q_0$write_1__VAL_2 : 61'h00000AAAAAAAAA00 ; @@ -530,7 +531,8 @@ module mkWsiAdapter32B4B(CLK, assign wsiS_reqFifo_doResetDeq$whas = MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 ; assign wsiS_reqFifo_doResetClr$whas = 1'b0 ; - assign wsiM_reqFifo_enqueueing$whas = wsiM_reqFifo_c_r != 2'd2 && !isEmpty ; + assign wsiM_reqFifo_enqueueing$whas = + wsiM_reqFifo_cntr_r != 2'd2 && !isEmpty ; assign wsiM_reqFifo_dequeueing$whas = WILL_FIRE_RL_wsiM_reqFifo_deq ; assign wsiM_sThreadBusy_pw$whas = wsiM0_SThreadBusy ; assign wsi_Es_mReqLast_w$whas = wsiS0_MReqLast ; @@ -603,24 +605,24 @@ module mkWsiAdapter32B4B(CLK, assign wsiM_peerIsReady$D_IN = wsiM0_SReset_n ; assign wsiM_peerIsReady$EN = 1'd1 ; - // register wsiM_reqFifo_c_r - assign wsiM_reqFifo_c_r$D_IN = - WILL_FIRE_RL_wsiM_reqFifo_incCtr ? - MUX_wsiM_reqFifo_c_r$write_1__VAL_1 : - MUX_wsiM_reqFifo_c_r$write_1__VAL_2 ; - assign wsiM_reqFifo_c_r$EN = - WILL_FIRE_RL_wsiM_reqFifo_incCtr || - WILL_FIRE_RL_wsiM_reqFifo_decCtr ; + // register wsiM_reqFifo_cntr_r + assign wsiM_reqFifo_cntr_r$D_IN = + WILL_FIRE_RL_wsiM_reqFifo_decCtr ? + MUX_wsiM_reqFifo_cntr_r$write_1__VAL_1 : + MUX_wsiM_reqFifo_cntr_r$write_1__VAL_2 ; + assign wsiM_reqFifo_cntr_r$EN = + WILL_FIRE_RL_wsiM_reqFifo_decCtr || + WILL_FIRE_RL_wsiM_reqFifo_incCtr ; // register wsiM_reqFifo_q_0 - always@(WILL_FIRE_RL_wsiM_reqFifo_both or + always@(MUX_wsiM_reqFifo_q_0$write_1__SEL_1 or MUX_wsiM_reqFifo_q_0$write_1__VAL_1 or MUX_wsiM_reqFifo_q_0$write_1__SEL_2 or MUX_wsiM_reqFifo_q_0$write_1__VAL_2 or WILL_FIRE_RL_wsiM_reqFifo_decCtr or wsiM_reqFifo_q_1) begin case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_wsiM_reqFifo_both: + MUX_wsiM_reqFifo_q_0$write_1__SEL_1: wsiM_reqFifo_q_0$D_IN = MUX_wsiM_reqFifo_q_0$write_1__VAL_1; MUX_wsiM_reqFifo_q_0$write_1__SEL_2: wsiM_reqFifo_q_0$D_IN = MUX_wsiM_reqFifo_q_0$write_1__VAL_2; @@ -631,19 +633,20 @@ module mkWsiAdapter32B4B(CLK, endcase end assign wsiM_reqFifo_q_0$EN = - WILL_FIRE_RL_wsiM_reqFifo_both || - WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_c_r == 2'd0 || + WILL_FIRE_RL_wsiM_reqFifo_both && _dfoo3 || + WILL_FIRE_RL_wsiM_reqFifo_incCtr && + wsiM_reqFifo_cntr_r == 2'd0 || WILL_FIRE_RL_wsiM_reqFifo_decCtr ; // register wsiM_reqFifo_q_1 - always@(WILL_FIRE_RL_wsiM_reqFifo_both or + always@(MUX_wsiM_reqFifo_q_1$write_1__SEL_1 or MUX_wsiM_reqFifo_q_1$write_1__VAL_1 or MUX_wsiM_reqFifo_q_1$write_1__SEL_2 or MUX_wsiM_reqFifo_q_0$write_1__VAL_2 or WILL_FIRE_RL_wsiM_reqFifo_decCtr) begin case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_wsiM_reqFifo_both: + MUX_wsiM_reqFifo_q_1$write_1__SEL_1: wsiM_reqFifo_q_1$D_IN = MUX_wsiM_reqFifo_q_1$write_1__VAL_1; MUX_wsiM_reqFifo_q_1$write_1__SEL_2: wsiM_reqFifo_q_1$D_IN = MUX_wsiM_reqFifo_q_0$write_1__VAL_2; @@ -654,8 +657,9 @@ module mkWsiAdapter32B4B(CLK, endcase end assign wsiM_reqFifo_q_1$EN = - WILL_FIRE_RL_wsiM_reqFifo_both || - WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_c_r == 2'd1 || + WILL_FIRE_RL_wsiM_reqFifo_both && _dfoo1 || + WILL_FIRE_RL_wsiM_reqFifo_incCtr && + wsiM_reqFifo_cntr_r == 2'd1 || WILL_FIRE_RL_wsiM_reqFifo_decCtr ; // register wsiM_sThreadBusy_d @@ -779,31 +783,37 @@ module mkWsiAdapter32B4B(CLK, assign wsiS_reqFifo$CLR = 1'b0 ; // remaining internal signals - assign x_burstLength__h6105 = { req32[304:296], 3'd0 } ; + assign _dfoo1 = + wsiM_reqFifo_cntr_r != 2'd2 || + MUX_wsiM_reqFifo_cntr_r$write_1__VAL_1 == 2'd1 ; + assign _dfoo3 = + wsiM_reqFifo_cntr_r != 2'd1 || + MUX_wsiM_reqFifo_cntr_r$write_1__VAL_1 == 2'd0 ; + assign x_burstLength__h5955 = { req32[304:296], 3'd0 } ; always@(pos or req32) begin case (pos) - 3'd0: x_data__h6106 = req32[71:40]; - 3'd1: x_data__h6106 = req32[103:72]; - 3'd2: x_data__h6106 = req32[135:104]; - 3'd3: x_data__h6106 = req32[167:136]; - 3'd4: x_data__h6106 = req32[199:168]; - 3'd5: x_data__h6106 = req32[231:200]; - 3'd6: x_data__h6106 = req32[263:232]; - 3'd7: x_data__h6106 = req32[295:264]; + 3'd0: x_data__h5956 = req32[71:40]; + 3'd1: x_data__h5956 = req32[103:72]; + 3'd2: x_data__h5956 = req32[135:104]; + 3'd3: x_data__h5956 = req32[167:136]; + 3'd4: x_data__h5956 = req32[199:168]; + 3'd5: x_data__h5956 = req32[231:200]; + 3'd6: x_data__h5956 = req32[263:232]; + 3'd7: x_data__h5956 = req32[295:264]; endcase end always@(pos or req32) begin case (pos) - 3'd0: x_byteEn__h6107 = req32[11:8]; - 3'd1: x_byteEn__h6107 = req32[15:12]; - 3'd2: x_byteEn__h6107 = req32[19:16]; - 3'd3: x_byteEn__h6107 = req32[23:20]; - 3'd4: x_byteEn__h6107 = req32[27:24]; - 3'd5: x_byteEn__h6107 = req32[31:28]; - 3'd6: x_byteEn__h6107 = req32[35:32]; - 3'd7: x_byteEn__h6107 = req32[39:36]; + 3'd0: x_byteEn__h5957 = req32[11:8]; + 3'd1: x_byteEn__h5957 = req32[15:12]; + 3'd2: x_byteEn__h5957 = req32[19:16]; + 3'd3: x_byteEn__h5957 = req32[23:20]; + 3'd4: x_byteEn__h5957 = req32[27:24]; + 3'd5: x_byteEn__h5957 = req32[31:28]; + 3'd6: x_byteEn__h5957 = req32[35:32]; + 3'd7: x_byteEn__h5957 = req32[39:36]; endcase end @@ -822,7 +832,7 @@ module mkWsiAdapter32B4B(CLK, wsiM_operateD <= `BSV_ASSIGNMENT_DELAY 1'd0; wsiM_pMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0; wsiM_peerIsReady <= `BSV_ASSIGNMENT_DELAY 1'd0; - wsiM_reqFifo_c_r <= `BSV_ASSIGNMENT_DELAY 2'd0; + wsiM_reqFifo_cntr_r <= `BSV_ASSIGNMENT_DELAY 2'd0; wsiM_reqFifo_q_0 <= `BSV_ASSIGNMENT_DELAY 61'h00000AAAAAAAAA00; wsiM_reqFifo_q_1 <= `BSV_ASSIGNMENT_DELAY 61'h00000AAAAAAAAA00; wsiM_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY 1'd1; @@ -857,8 +867,9 @@ module mkWsiAdapter32B4B(CLK, wsiM_pMesgCount <= `BSV_ASSIGNMENT_DELAY wsiM_pMesgCount$D_IN; if (wsiM_peerIsReady$EN) wsiM_peerIsReady <= `BSV_ASSIGNMENT_DELAY wsiM_peerIsReady$D_IN; - if (wsiM_reqFifo_c_r$EN) - wsiM_reqFifo_c_r <= `BSV_ASSIGNMENT_DELAY wsiM_reqFifo_c_r$D_IN; + if (wsiM_reqFifo_cntr_r$EN) + wsiM_reqFifo_cntr_r <= `BSV_ASSIGNMENT_DELAY + wsiM_reqFifo_cntr_r$D_IN; if (wsiM_reqFifo_q_0$EN) wsiM_reqFifo_q_0 <= `BSV_ASSIGNMENT_DELAY wsiM_reqFifo_q_0$D_IN; if (wsiM_reqFifo_q_1$EN) @@ -936,7 +947,7 @@ module mkWsiAdapter32B4B(CLK, wsiM_operateD = 1'h0; wsiM_pMesgCount = 32'hAAAAAAAA; wsiM_peerIsReady = 1'h0; - wsiM_reqFifo_c_r = 2'h2; + wsiM_reqFifo_cntr_r = 2'h2; wsiM_reqFifo_q_0 = 61'h0AAAAAAAAAAAAAAA; wsiM_reqFifo_q_1 = 61'h0AAAAAAAAAAAAAAA; wsiM_sThreadBusy_d = 1'h0; diff --git a/rtl/mkWsiAdapter4B16B.v b/rtl/mkWsiAdapter4B16B.v index 5e03ea00..0cba6cd9 100644 --- a/rtl/mkWsiAdapter4B16B.v +++ b/rtl/mkWsiAdapter4B16B.v @@ -1,7 +1,7 @@ // -// Generated by Bluespec Compiler, version 2012.09.beta1 (build 29570, 2012-09.11) +// Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Wed Nov 28 10:32:19 EST 2012 +// On Fri Jun 21 16:57:41 EDT 2013 // // // Ports: @@ -219,10 +219,10 @@ module mkWsiAdapter4B16B(CLK, wire [1 : 0] pos$D_IN; wire pos$EN; - // register stage - reg [60 : 0] stage; - wire [60 : 0] stage$D_IN; - wire stage$EN; + // register stage_0 + reg [60 : 0] stage_0; + wire [60 : 0] stage_0$D_IN; + wire stage_0$EN; // register stage_1 reg [60 : 0] stage_1; @@ -270,10 +270,10 @@ module mkWsiAdapter4B16B(CLK, reg wsiM_peerIsReady; wire wsiM_peerIsReady$D_IN, wsiM_peerIsReady$EN; - // register wsiM_reqFifo_c_r - reg [1 : 0] wsiM_reqFifo_c_r; - wire [1 : 0] wsiM_reqFifo_c_r$D_IN; - wire wsiM_reqFifo_c_r$EN; + // register wsiM_reqFifo_cntr_r + reg [1 : 0] wsiM_reqFifo_cntr_r; + wire [1 : 0] wsiM_reqFifo_cntr_r$D_IN; + wire wsiM_reqFifo_cntr_r$EN; // register wsiM_reqFifo_q_0 reg [168 : 0] wsiM_reqFifo_q_0; @@ -388,19 +388,22 @@ module mkWsiAdapter4B16B(CLK, MUX_wsiM_reqFifo_q_0$write_1__VAL_2, MUX_wsiM_reqFifo_q_1$write_1__VAL_1; wire [1 : 0] MUX_pos$write_1__VAL_1, - MUX_wsiM_reqFifo_c_r$write_1__VAL_1, - MUX_wsiM_reqFifo_c_r$write_1__VAL_2; + MUX_wsiM_reqFifo_cntr_r$write_1__VAL_1, + MUX_wsiM_reqFifo_cntr_r$write_1__VAL_2; wire MUX_isFull$write_1__VAL_1, + MUX_wsiM_reqFifo_q_0$write_1__SEL_1, MUX_wsiM_reqFifo_q_0$write_1__SEL_2, + MUX_wsiM_reqFifo_q_1$write_1__SEL_1, MUX_wsiM_reqFifo_q_1$write_1__SEL_2, MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3; // remaining internal signals - reg [15 : 0] x_byteEn__h6727; - wire [127 : 0] x_data__h6726; - wire [15 : 0] be__h7516, be__h7535, be__h7576, be__h7632; - wire [11 : 0] x__h7580, x_burstLength__h6725; - wire [7 : 0] x__h7539; + reg [15 : 0] x_byteEn__h6493; + wire [127 : 0] x_data__h6492; + wire [15 : 0] be__h7294, be__h7313, be__h7354, be__h7410; + wire [11 : 0] x__h7358, x_burstLength__h6491; + wire [7 : 0] x__h7317; + wire _dfoo1, _dfoo3; // value method wsiS0_sThreadBusy assign wsiS0_SThreadBusy = @@ -450,14 +453,11 @@ module mkWsiAdapter4B16B(CLK, // rule RL_wsiM_reqFifo_deq assign WILL_FIRE_RL_wsiM_reqFifo_deq = - wsiM_reqFifo_c_r != 2'd0 && !wsiM_sThreadBusy_d ; + wsiM_reqFifo_cntr_r != 2'd0 && !wsiM_sThreadBusy_d ; // rule RL_wsiM_reqFifo_incCtr assign WILL_FIRE_RL_wsiM_reqFifo_incCtr = - ((wsiM_reqFifo_c_r == 2'd0) ? - wsiM_reqFifo_enqueueing$whas : - wsiM_reqFifo_c_r != 2'd1 || wsiM_reqFifo_enqueueing$whas) && - wsiM_reqFifo_enqueueing$whas && + wsiM_reqFifo_enqueueing$whas && wsiM_reqFifo_enqueueing$whas && !WILL_FIRE_RL_wsiM_reqFifo_deq ; // rule RL_wsiM_reqFifo_decCtr @@ -466,10 +466,7 @@ module mkWsiAdapter4B16B(CLK, // rule RL_wsiM_reqFifo_both assign WILL_FIRE_RL_wsiM_reqFifo_both = - ((wsiM_reqFifo_c_r == 2'd1) ? - wsiM_reqFifo_enqueueing$whas : - wsiM_reqFifo_c_r != 2'd2 || wsiM_reqFifo_enqueueing$whas) && - WILL_FIRE_RL_wsiM_reqFifo_deq && + wsiM_reqFifo_enqueueing$whas && WILL_FIRE_RL_wsiM_reqFifo_deq && wsiM_reqFifo_enqueueing$whas ; // rule RL_wsiS_reqFifo_enq @@ -483,30 +480,34 @@ module mkWsiAdapter4B16B(CLK, MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 ; // inputs to muxes for submodule ports + assign MUX_wsiM_reqFifo_q_0$write_1__SEL_1 = + WILL_FIRE_RL_wsiM_reqFifo_both && _dfoo3 ; assign MUX_wsiM_reqFifo_q_0$write_1__SEL_2 = - WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_c_r == 2'd0 ; + WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_cntr_r == 2'd0 ; + assign MUX_wsiM_reqFifo_q_1$write_1__SEL_1 = + WILL_FIRE_RL_wsiM_reqFifo_both && _dfoo1 ; assign MUX_wsiM_reqFifo_q_1$write_1__SEL_2 = - WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_c_r == 2'd1 ; + WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_cntr_r == 2'd1 ; assign MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 = wsiS_reqFifo$EMPTY_N && !isFull ; assign MUX_isFull$write_1__VAL_1 = pos == 2'd3 || wsiS_reqFifo$D_OUT[57] ; assign MUX_pos$write_1__VAL_1 = pos + 2'd1 ; - assign MUX_wsiM_reqFifo_c_r$write_1__VAL_1 = wsiM_reqFifo_c_r + 2'd1 ; - assign MUX_wsiM_reqFifo_c_r$write_1__VAL_2 = wsiM_reqFifo_c_r - 2'd1 ; + assign MUX_wsiM_reqFifo_cntr_r$write_1__VAL_1 = wsiM_reqFifo_cntr_r - 2'd1 ; + assign MUX_wsiM_reqFifo_cntr_r$write_1__VAL_2 = wsiM_reqFifo_cntr_r + 2'd1 ; assign MUX_wsiM_reqFifo_q_0$write_1__VAL_1 = - (wsiM_reqFifo_c_r == 2'd1) ? + (wsiM_reqFifo_cntr_r == 2'd1) ? MUX_wsiM_reqFifo_q_0$write_1__VAL_2 : wsiM_reqFifo_q_1 ; assign MUX_wsiM_reqFifo_q_0$write_1__VAL_2 = { 3'd1, isLast, - stage[56], - x_burstLength__h6725, - x_data__h6726, - x_byteEn__h6727, - stage[7:0] } ; + stage_0[56], + x_burstLength__h6491, + x_data__h6492, + x_byteEn__h6493, + stage_0[7:0] } ; assign MUX_wsiM_reqFifo_q_1$write_1__VAL_1 = - (wsiM_reqFifo_c_r == 2'd2) ? + (wsiM_reqFifo_cntr_r == 2'd2) ? MUX_wsiM_reqFifo_q_0$write_1__VAL_2 : 169'h00000AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA00 ; @@ -551,7 +552,8 @@ module mkWsiAdapter4B16B(CLK, assign wsiS_reqFifo_doResetDeq$whas = MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 ; assign wsiS_reqFifo_doResetClr$whas = 1'b0 ; - assign wsiM_reqFifo_enqueueing$whas = wsiM_reqFifo_c_r != 2'd2 && isFull ; + assign wsiM_reqFifo_enqueueing$whas = + wsiM_reqFifo_cntr_r != 2'd2 && isFull ; assign wsiM_reqFifo_dequeueing$whas = WILL_FIRE_RL_wsiM_reqFifo_deq ; assign wsiM_sThreadBusy_pw$whas = wsiM0_SThreadBusy ; assign wsi_Es_mReqLast_w$whas = wsiS0_MReqLast ; @@ -587,9 +589,9 @@ module mkWsiAdapter4B16B(CLK, MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 || wsiM_reqFifo_enqueueing$whas ; - // register stage - assign stage$D_IN = wsiS_reqFifo$D_OUT ; - assign stage$EN = + // register stage_0 + assign stage_0$D_IN = wsiS_reqFifo$D_OUT ; + assign stage_0$EN = MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 && pos == 2'd0 ; // register stage_1 @@ -651,24 +653,24 @@ module mkWsiAdapter4B16B(CLK, assign wsiM_peerIsReady$D_IN = wsiM0_SReset_n ; assign wsiM_peerIsReady$EN = 1'd1 ; - // register wsiM_reqFifo_c_r - assign wsiM_reqFifo_c_r$D_IN = - WILL_FIRE_RL_wsiM_reqFifo_incCtr ? - MUX_wsiM_reqFifo_c_r$write_1__VAL_1 : - MUX_wsiM_reqFifo_c_r$write_1__VAL_2 ; - assign wsiM_reqFifo_c_r$EN = - WILL_FIRE_RL_wsiM_reqFifo_incCtr || - WILL_FIRE_RL_wsiM_reqFifo_decCtr ; + // register wsiM_reqFifo_cntr_r + assign wsiM_reqFifo_cntr_r$D_IN = + WILL_FIRE_RL_wsiM_reqFifo_decCtr ? + MUX_wsiM_reqFifo_cntr_r$write_1__VAL_1 : + MUX_wsiM_reqFifo_cntr_r$write_1__VAL_2 ; + assign wsiM_reqFifo_cntr_r$EN = + WILL_FIRE_RL_wsiM_reqFifo_decCtr || + WILL_FIRE_RL_wsiM_reqFifo_incCtr ; // register wsiM_reqFifo_q_0 - always@(WILL_FIRE_RL_wsiM_reqFifo_both or + always@(MUX_wsiM_reqFifo_q_0$write_1__SEL_1 or MUX_wsiM_reqFifo_q_0$write_1__VAL_1 or MUX_wsiM_reqFifo_q_0$write_1__SEL_2 or MUX_wsiM_reqFifo_q_0$write_1__VAL_2 or WILL_FIRE_RL_wsiM_reqFifo_decCtr or wsiM_reqFifo_q_1) begin case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_wsiM_reqFifo_both: + MUX_wsiM_reqFifo_q_0$write_1__SEL_1: wsiM_reqFifo_q_0$D_IN = MUX_wsiM_reqFifo_q_0$write_1__VAL_1; MUX_wsiM_reqFifo_q_0$write_1__SEL_2: wsiM_reqFifo_q_0$D_IN = MUX_wsiM_reqFifo_q_0$write_1__VAL_2; @@ -679,19 +681,20 @@ module mkWsiAdapter4B16B(CLK, endcase end assign wsiM_reqFifo_q_0$EN = - WILL_FIRE_RL_wsiM_reqFifo_both || - WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_c_r == 2'd0 || + WILL_FIRE_RL_wsiM_reqFifo_both && _dfoo3 || + WILL_FIRE_RL_wsiM_reqFifo_incCtr && + wsiM_reqFifo_cntr_r == 2'd0 || WILL_FIRE_RL_wsiM_reqFifo_decCtr ; // register wsiM_reqFifo_q_1 - always@(WILL_FIRE_RL_wsiM_reqFifo_both or + always@(MUX_wsiM_reqFifo_q_1$write_1__SEL_1 or MUX_wsiM_reqFifo_q_1$write_1__VAL_1 or MUX_wsiM_reqFifo_q_1$write_1__SEL_2 or MUX_wsiM_reqFifo_q_0$write_1__VAL_2 or WILL_FIRE_RL_wsiM_reqFifo_decCtr) begin case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_wsiM_reqFifo_both: + MUX_wsiM_reqFifo_q_1$write_1__SEL_1: wsiM_reqFifo_q_1$D_IN = MUX_wsiM_reqFifo_q_1$write_1__VAL_1; MUX_wsiM_reqFifo_q_1$write_1__SEL_2: wsiM_reqFifo_q_1$D_IN = MUX_wsiM_reqFifo_q_0$write_1__VAL_2; @@ -703,8 +706,9 @@ module mkWsiAdapter4B16B(CLK, endcase end assign wsiM_reqFifo_q_1$EN = - WILL_FIRE_RL_wsiM_reqFifo_both || - WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_c_r == 2'd1 || + WILL_FIRE_RL_wsiM_reqFifo_both && _dfoo1 || + WILL_FIRE_RL_wsiM_reqFifo_incCtr && + wsiM_reqFifo_cntr_r == 2'd1 || WILL_FIRE_RL_wsiM_reqFifo_decCtr ; // register wsiM_sThreadBusy_d @@ -828,29 +832,35 @@ module mkWsiAdapter4B16B(CLK, assign wsiS_reqFifo$CLR = 1'b0 ; // remaining internal signals - assign be__h7516 = { 12'd0, stage[11:8] } ; - assign be__h7535 = { 8'd0, x__h7539 } ; - assign be__h7576 = { 4'd0, x__h7580 } ; - assign be__h7632 = { stage_3[11:8], x__h7580 } ; - assign x__h7539 = { stage_1[11:8], stage[11:8] } ; - assign x__h7580 = { stage_2[11:8], x__h7539 } ; - assign x_burstLength__h6725 = stage[55:44] >> 2 ; - assign x_data__h6726 = + assign _dfoo1 = + wsiM_reqFifo_cntr_r != 2'd2 || + MUX_wsiM_reqFifo_cntr_r$write_1__VAL_1 == 2'd1 ; + assign _dfoo3 = + wsiM_reqFifo_cntr_r != 2'd1 || + MUX_wsiM_reqFifo_cntr_r$write_1__VAL_1 == 2'd0 ; + assign be__h7294 = { 12'd0, stage_0[11:8] } ; + assign be__h7313 = { 8'd0, x__h7317 } ; + assign be__h7354 = { 4'd0, x__h7358 } ; + assign be__h7410 = { stage_3[11:8], x__h7358 } ; + assign x__h7317 = { stage_1[11:8], stage_0[11:8] } ; + assign x__h7358 = { stage_2[11:8], x__h7317 } ; + assign x_burstLength__h6491 = stage_0[55:44] >> 2 ; + assign x_data__h6492 = { stage_3[43:12], stage_2[43:12], stage_1[43:12], - stage[43:12] } ; + stage_0[43:12] } ; always@(pos or stage_3 or stage_2 or stage_1 or - stage or be__h7516 or be__h7535 or be__h7576 or be__h7632) + stage_0 or be__h7294 or be__h7313 or be__h7354 or be__h7410) begin case (pos) - 2'd0: x_byteEn__h6727 = be__h7516; - 2'd1: x_byteEn__h6727 = be__h7535; - 2'd2: x_byteEn__h6727 = be__h7576; - 2'd3: x_byteEn__h6727 = be__h7632; + 2'd0: x_byteEn__h6493 = be__h7294; + 2'd1: x_byteEn__h6493 = be__h7313; + 2'd2: x_byteEn__h6493 = be__h7354; + 2'd3: x_byteEn__h6493 = be__h7410; endcase end @@ -869,7 +879,7 @@ module mkWsiAdapter4B16B(CLK, wsiM_operateD <= `BSV_ASSIGNMENT_DELAY 1'd0; wsiM_pMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0; wsiM_peerIsReady <= `BSV_ASSIGNMENT_DELAY 1'd0; - wsiM_reqFifo_c_r <= `BSV_ASSIGNMENT_DELAY 2'd0; + wsiM_reqFifo_cntr_r <= `BSV_ASSIGNMENT_DELAY 2'd0; wsiM_reqFifo_q_0 <= `BSV_ASSIGNMENT_DELAY 169'h00000AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA00; wsiM_reqFifo_q_1 <= `BSV_ASSIGNMENT_DELAY @@ -906,8 +916,9 @@ module mkWsiAdapter4B16B(CLK, wsiM_pMesgCount <= `BSV_ASSIGNMENT_DELAY wsiM_pMesgCount$D_IN; if (wsiM_peerIsReady$EN) wsiM_peerIsReady <= `BSV_ASSIGNMENT_DELAY wsiM_peerIsReady$D_IN; - if (wsiM_reqFifo_c_r$EN) - wsiM_reqFifo_c_r <= `BSV_ASSIGNMENT_DELAY wsiM_reqFifo_c_r$D_IN; + if (wsiM_reqFifo_cntr_r$EN) + wsiM_reqFifo_cntr_r <= `BSV_ASSIGNMENT_DELAY + wsiM_reqFifo_cntr_r$D_IN; if (wsiM_reqFifo_q_0$EN) wsiM_reqFifo_q_0 <= `BSV_ASSIGNMENT_DELAY wsiM_reqFifo_q_0$D_IN; if (wsiM_reqFifo_q_1$EN) @@ -943,7 +954,7 @@ module mkWsiAdapter4B16B(CLK, if (wsiS_wordCount$EN) wsiS_wordCount <= `BSV_ASSIGNMENT_DELAY wsiS_wordCount$D_IN; end - if (stage$EN) stage <= `BSV_ASSIGNMENT_DELAY stage$D_IN; + if (stage_0$EN) stage_0 <= `BSV_ASSIGNMENT_DELAY stage_0$D_IN; if (stage_1$EN) stage_1 <= `BSV_ASSIGNMENT_DELAY stage_1$D_IN; if (stage_2$EN) stage_2 <= `BSV_ASSIGNMENT_DELAY stage_2$D_IN; if (stage_3$EN) stage_3 <= `BSV_ASSIGNMENT_DELAY stage_3$D_IN; @@ -979,7 +990,7 @@ module mkWsiAdapter4B16B(CLK, isFull = 1'h0; isLast = 1'h0; pos = 2'h2; - stage = 61'h0AAAAAAAAAAAAAAA; + stage_0 = 61'h0AAAAAAAAAAAAAAA; stage_1 = 61'h0AAAAAAAAAAAAAAA; stage_2 = 61'h0AAAAAAAAAAAAAAA; stage_3 = 61'h0AAAAAAAAAAAAAAA; @@ -990,7 +1001,7 @@ module mkWsiAdapter4B16B(CLK, wsiM_operateD = 1'h0; wsiM_pMesgCount = 32'hAAAAAAAA; wsiM_peerIsReady = 1'h0; - wsiM_reqFifo_c_r = 2'h2; + wsiM_reqFifo_cntr_r = 2'h2; wsiM_reqFifo_q_0 = 169'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; wsiM_reqFifo_q_1 = 169'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; wsiM_sThreadBusy_d = 1'h0; diff --git a/rtl/mkWsiAdapter4B32B.v b/rtl/mkWsiAdapter4B32B.v index 27c0e2a9..72d430d4 100644 --- a/rtl/mkWsiAdapter4B32B.v +++ b/rtl/mkWsiAdapter4B32B.v @@ -1,7 +1,7 @@ // -// Generated by Bluespec Compiler, version 2012.09.beta1 (build 29570, 2012-09.11) +// Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23) // -// On Wed Nov 28 10:32:20 EST 2012 +// On Fri Jun 21 16:57:42 EDT 2013 // // // Ports: @@ -219,10 +219,10 @@ module mkWsiAdapter4B32B(CLK, wire [2 : 0] pos$D_IN; wire pos$EN; - // register stage - reg [60 : 0] stage; - wire [60 : 0] stage$D_IN; - wire stage$EN; + // register stage_0 + reg [60 : 0] stage_0; + wire [60 : 0] stage_0$D_IN; + wire stage_0$EN; // register stage_1 reg [60 : 0] stage_1; @@ -290,10 +290,10 @@ module mkWsiAdapter4B32B(CLK, reg wsiM_peerIsReady; wire wsiM_peerIsReady$D_IN, wsiM_peerIsReady$EN; - // register wsiM_reqFifo_c_r - reg [1 : 0] wsiM_reqFifo_c_r; - wire [1 : 0] wsiM_reqFifo_c_r$D_IN; - wire wsiM_reqFifo_c_r$EN; + // register wsiM_reqFifo_cntr_r + reg [1 : 0] wsiM_reqFifo_cntr_r; + wire [1 : 0] wsiM_reqFifo_cntr_r$D_IN; + wire wsiM_reqFifo_cntr_r$EN; // register wsiM_reqFifo_q_0 reg [312 : 0] wsiM_reqFifo_q_0; @@ -408,30 +408,33 @@ module mkWsiAdapter4B32B(CLK, MUX_wsiM_reqFifo_q_0$write_1__VAL_2, MUX_wsiM_reqFifo_q_1$write_1__VAL_1; wire [2 : 0] MUX_pos$write_1__VAL_1; - wire [1 : 0] MUX_wsiM_reqFifo_c_r$write_1__VAL_1, - MUX_wsiM_reqFifo_c_r$write_1__VAL_2; + wire [1 : 0] MUX_wsiM_reqFifo_cntr_r$write_1__VAL_1, + MUX_wsiM_reqFifo_cntr_r$write_1__VAL_2; wire MUX_isFull$write_1__VAL_1, + MUX_wsiM_reqFifo_q_0$write_1__SEL_1, MUX_wsiM_reqFifo_q_0$write_1__SEL_2, + MUX_wsiM_reqFifo_q_1$write_1__SEL_1, MUX_wsiM_reqFifo_q_1$write_1__SEL_2, MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3; // remaining internal signals - reg [31 : 0] x_byteEn__h7271; - wire [255 : 0] x_data__h7270; - wire [31 : 0] be__h8760, - be__h8779, - be__h8820, + reg [31 : 0] x_byteEn__h6989; + wire [255 : 0] x_data__h6988; + wire [31 : 0] be__h8502, + be__h8521, + be__h8562, + be__h8618, + be__h8689, + be__h8775, be__h8876, - be__h8947, - be__h9033, - be__h9134, - be__h9250; - wire [27 : 0] x__h9138; - wire [23 : 0] x__h9037; - wire [19 : 0] x__h8951; - wire [15 : 0] x__h8880; - wire [11 : 0] x__h8824, x_burstLength__h7269; - wire [7 : 0] x__h8783; + be__h8992; + wire [27 : 0] x__h8880; + wire [23 : 0] x__h8779; + wire [19 : 0] x__h8693; + wire [15 : 0] x__h8622; + wire [11 : 0] x__h8566, x_burstLength__h6987; + wire [7 : 0] x__h8525; + wire _dfoo1, _dfoo3; // value method wsiS0_sThreadBusy assign wsiS0_SThreadBusy = @@ -481,14 +484,11 @@ module mkWsiAdapter4B32B(CLK, // rule RL_wsiM_reqFifo_deq assign WILL_FIRE_RL_wsiM_reqFifo_deq = - wsiM_reqFifo_c_r != 2'd0 && !wsiM_sThreadBusy_d ; + wsiM_reqFifo_cntr_r != 2'd0 && !wsiM_sThreadBusy_d ; // rule RL_wsiM_reqFifo_incCtr assign WILL_FIRE_RL_wsiM_reqFifo_incCtr = - ((wsiM_reqFifo_c_r == 2'd0) ? - wsiM_reqFifo_enqueueing$whas : - wsiM_reqFifo_c_r != 2'd1 || wsiM_reqFifo_enqueueing$whas) && - wsiM_reqFifo_enqueueing$whas && + wsiM_reqFifo_enqueueing$whas && wsiM_reqFifo_enqueueing$whas && !WILL_FIRE_RL_wsiM_reqFifo_deq ; // rule RL_wsiM_reqFifo_decCtr @@ -497,10 +497,7 @@ module mkWsiAdapter4B32B(CLK, // rule RL_wsiM_reqFifo_both assign WILL_FIRE_RL_wsiM_reqFifo_both = - ((wsiM_reqFifo_c_r == 2'd1) ? - wsiM_reqFifo_enqueueing$whas : - wsiM_reqFifo_c_r != 2'd2 || wsiM_reqFifo_enqueueing$whas) && - WILL_FIRE_RL_wsiM_reqFifo_deq && + wsiM_reqFifo_enqueueing$whas && WILL_FIRE_RL_wsiM_reqFifo_deq && wsiM_reqFifo_enqueueing$whas ; // rule RL_wsiS_reqFifo_enq @@ -514,30 +511,34 @@ module mkWsiAdapter4B32B(CLK, MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 ; // inputs to muxes for submodule ports + assign MUX_wsiM_reqFifo_q_0$write_1__SEL_1 = + WILL_FIRE_RL_wsiM_reqFifo_both && _dfoo3 ; assign MUX_wsiM_reqFifo_q_0$write_1__SEL_2 = - WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_c_r == 2'd0 ; + WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_cntr_r == 2'd0 ; + assign MUX_wsiM_reqFifo_q_1$write_1__SEL_1 = + WILL_FIRE_RL_wsiM_reqFifo_both && _dfoo1 ; assign MUX_wsiM_reqFifo_q_1$write_1__SEL_2 = - WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_c_r == 2'd1 ; + WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_cntr_r == 2'd1 ; assign MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 = wsiS_reqFifo$EMPTY_N && !isFull ; assign MUX_isFull$write_1__VAL_1 = pos == 3'd7 || wsiS_reqFifo$D_OUT[57] ; assign MUX_pos$write_1__VAL_1 = pos + 3'd1 ; - assign MUX_wsiM_reqFifo_c_r$write_1__VAL_1 = wsiM_reqFifo_c_r + 2'd1 ; - assign MUX_wsiM_reqFifo_c_r$write_1__VAL_2 = wsiM_reqFifo_c_r - 2'd1 ; + assign MUX_wsiM_reqFifo_cntr_r$write_1__VAL_1 = wsiM_reqFifo_cntr_r - 2'd1 ; + assign MUX_wsiM_reqFifo_cntr_r$write_1__VAL_2 = wsiM_reqFifo_cntr_r + 2'd1 ; assign MUX_wsiM_reqFifo_q_0$write_1__VAL_1 = - (wsiM_reqFifo_c_r == 2'd1) ? + (wsiM_reqFifo_cntr_r == 2'd1) ? MUX_wsiM_reqFifo_q_0$write_1__VAL_2 : wsiM_reqFifo_q_1 ; assign MUX_wsiM_reqFifo_q_0$write_1__VAL_2 = { 3'd1, isLast, - stage[56], - x_burstLength__h7269, - x_data__h7270, - x_byteEn__h7271, - stage[7:0] } ; + stage_0[56], + x_burstLength__h6987, + x_data__h6988, + x_byteEn__h6989, + stage_0[7:0] } ; assign MUX_wsiM_reqFifo_q_1$write_1__VAL_1 = - (wsiM_reqFifo_c_r == 2'd2) ? + (wsiM_reqFifo_cntr_r == 2'd2) ? MUX_wsiM_reqFifo_q_0$write_1__VAL_2 : 313'h00000AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA00 ; @@ -582,7 +583,8 @@ module mkWsiAdapter4B32B(CLK, assign wsiS_reqFifo_doResetDeq$whas = MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 ; assign wsiS_reqFifo_doResetClr$whas = 1'b0 ; - assign wsiM_reqFifo_enqueueing$whas = wsiM_reqFifo_c_r != 2'd2 && isFull ; + assign wsiM_reqFifo_enqueueing$whas = + wsiM_reqFifo_cntr_r != 2'd2 && isFull ; assign wsiM_reqFifo_dequeueing$whas = WILL_FIRE_RL_wsiM_reqFifo_deq ; assign wsiM_sThreadBusy_pw$whas = wsiM0_SThreadBusy ; assign wsi_Es_mReqLast_w$whas = wsiS0_MReqLast ; @@ -618,9 +620,9 @@ module mkWsiAdapter4B32B(CLK, MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 || wsiM_reqFifo_enqueueing$whas ; - // register stage - assign stage$D_IN = wsiS_reqFifo$D_OUT ; - assign stage$EN = + // register stage_0 + assign stage_0$D_IN = wsiS_reqFifo$D_OUT ; + assign stage_0$EN = MUX_wsiS_reqFifo_levelsValid$write_1__SEL_3 && pos == 3'd0 ; // register stage_1 @@ -702,24 +704,24 @@ module mkWsiAdapter4B32B(CLK, assign wsiM_peerIsReady$D_IN = wsiM0_SReset_n ; assign wsiM_peerIsReady$EN = 1'd1 ; - // register wsiM_reqFifo_c_r - assign wsiM_reqFifo_c_r$D_IN = - WILL_FIRE_RL_wsiM_reqFifo_incCtr ? - MUX_wsiM_reqFifo_c_r$write_1__VAL_1 : - MUX_wsiM_reqFifo_c_r$write_1__VAL_2 ; - assign wsiM_reqFifo_c_r$EN = - WILL_FIRE_RL_wsiM_reqFifo_incCtr || - WILL_FIRE_RL_wsiM_reqFifo_decCtr ; + // register wsiM_reqFifo_cntr_r + assign wsiM_reqFifo_cntr_r$D_IN = + WILL_FIRE_RL_wsiM_reqFifo_decCtr ? + MUX_wsiM_reqFifo_cntr_r$write_1__VAL_1 : + MUX_wsiM_reqFifo_cntr_r$write_1__VAL_2 ; + assign wsiM_reqFifo_cntr_r$EN = + WILL_FIRE_RL_wsiM_reqFifo_decCtr || + WILL_FIRE_RL_wsiM_reqFifo_incCtr ; // register wsiM_reqFifo_q_0 - always@(WILL_FIRE_RL_wsiM_reqFifo_both or + always@(MUX_wsiM_reqFifo_q_0$write_1__SEL_1 or MUX_wsiM_reqFifo_q_0$write_1__VAL_1 or MUX_wsiM_reqFifo_q_0$write_1__SEL_2 or MUX_wsiM_reqFifo_q_0$write_1__VAL_2 or WILL_FIRE_RL_wsiM_reqFifo_decCtr or wsiM_reqFifo_q_1) begin case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_wsiM_reqFifo_both: + MUX_wsiM_reqFifo_q_0$write_1__SEL_1: wsiM_reqFifo_q_0$D_IN = MUX_wsiM_reqFifo_q_0$write_1__VAL_1; MUX_wsiM_reqFifo_q_0$write_1__SEL_2: wsiM_reqFifo_q_0$D_IN = MUX_wsiM_reqFifo_q_0$write_1__VAL_2; @@ -730,19 +732,20 @@ module mkWsiAdapter4B32B(CLK, endcase end assign wsiM_reqFifo_q_0$EN = - WILL_FIRE_RL_wsiM_reqFifo_both || - WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_c_r == 2'd0 || + WILL_FIRE_RL_wsiM_reqFifo_both && _dfoo3 || + WILL_FIRE_RL_wsiM_reqFifo_incCtr && + wsiM_reqFifo_cntr_r == 2'd0 || WILL_FIRE_RL_wsiM_reqFifo_decCtr ; // register wsiM_reqFifo_q_1 - always@(WILL_FIRE_RL_wsiM_reqFifo_both or + always@(MUX_wsiM_reqFifo_q_1$write_1__SEL_1 or MUX_wsiM_reqFifo_q_1$write_1__VAL_1 or MUX_wsiM_reqFifo_q_1$write_1__SEL_2 or MUX_wsiM_reqFifo_q_0$write_1__VAL_2 or WILL_FIRE_RL_wsiM_reqFifo_decCtr) begin case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_wsiM_reqFifo_both: + MUX_wsiM_reqFifo_q_1$write_1__SEL_1: wsiM_reqFifo_q_1$D_IN = MUX_wsiM_reqFifo_q_1$write_1__VAL_1; MUX_wsiM_reqFifo_q_1$write_1__SEL_2: wsiM_reqFifo_q_1$D_IN = MUX_wsiM_reqFifo_q_0$write_1__VAL_2; @@ -754,8 +757,9 @@ module mkWsiAdapter4B32B(CLK, endcase end assign wsiM_reqFifo_q_1$EN = - WILL_FIRE_RL_wsiM_reqFifo_both || - WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_c_r == 2'd1 || + WILL_FIRE_RL_wsiM_reqFifo_both && _dfoo1 || + WILL_FIRE_RL_wsiM_reqFifo_incCtr && + wsiM_reqFifo_cntr_r == 2'd1 || WILL_FIRE_RL_wsiM_reqFifo_decCtr ; // register wsiM_sThreadBusy_d @@ -879,22 +883,28 @@ module mkWsiAdapter4B32B(CLK, assign wsiS_reqFifo$CLR = 1'b0 ; // remaining internal signals - assign be__h8760 = { 28'd0, stage[11:8] } ; - assign be__h8779 = { 24'd0, x__h8783 } ; - assign be__h8820 = { 20'd0, x__h8824 } ; - assign be__h8876 = { 16'd0, x__h8880 } ; - assign be__h8947 = { 12'd0, x__h8951 } ; - assign be__h9033 = { 8'd0, x__h9037 } ; - assign be__h9134 = { 4'd0, x__h9138 } ; - assign be__h9250 = { stage_7[11:8], x__h9138 } ; - assign x__h8783 = { stage_1[11:8], stage[11:8] } ; - assign x__h8824 = { stage_2[11:8], x__h8783 } ; - assign x__h8880 = { stage_3[11:8], x__h8824 } ; - assign x__h8951 = { stage_4[11:8], x__h8880 } ; - assign x__h9037 = { stage_5[11:8], x__h8951 } ; - assign x__h9138 = { stage_6[11:8], x__h9037 } ; - assign x_burstLength__h7269 = stage[55:44] >> 3 ; - assign x_data__h7270 = + assign _dfoo1 = + wsiM_reqFifo_cntr_r != 2'd2 || + MUX_wsiM_reqFifo_cntr_r$write_1__VAL_1 == 2'd1 ; + assign _dfoo3 = + wsiM_reqFifo_cntr_r != 2'd1 || + MUX_wsiM_reqFifo_cntr_r$write_1__VAL_1 == 2'd0 ; + assign be__h8502 = { 28'd0, stage_0[11:8] } ; + assign be__h8521 = { 24'd0, x__h8525 } ; + assign be__h8562 = { 20'd0, x__h8566 } ; + assign be__h8618 = { 16'd0, x__h8622 } ; + assign be__h8689 = { 12'd0, x__h8693 } ; + assign be__h8775 = { 8'd0, x__h8779 } ; + assign be__h8876 = { 4'd0, x__h8880 } ; + assign be__h8992 = { stage_7[11:8], x__h8880 } ; + assign x__h8525 = { stage_1[11:8], stage_0[11:8] } ; + assign x__h8566 = { stage_2[11:8], x__h8525 } ; + assign x__h8622 = { stage_3[11:8], x__h8566 } ; + assign x__h8693 = { stage_4[11:8], x__h8622 } ; + assign x__h8779 = { stage_5[11:8], x__h8693 } ; + assign x__h8880 = { stage_6[11:8], x__h8779 } ; + assign x_burstLength__h6987 = stage_0[55:44] >> 3 ; + assign x_data__h6988 = { stage_7[43:12], stage_6[43:12], stage_5[43:12], @@ -902,7 +912,7 @@ module mkWsiAdapter4B32B(CLK, stage_3[43:12], stage_2[43:12], stage_1[43:12], - stage[43:12] } ; + stage_0[43:12] } ; always@(pos or stage_7 or stage_6 or @@ -911,21 +921,21 @@ module mkWsiAdapter4B32B(CLK, stage_3 or stage_2 or stage_1 or - stage or - be__h8760 or - be__h8779 or - be__h8820 or - be__h8876 or be__h8947 or be__h9033 or be__h9134 or be__h9250) + stage_0 or + be__h8502 or + be__h8521 or + be__h8562 or + be__h8618 or be__h8689 or be__h8775 or be__h8876 or be__h8992) begin case (pos) - 3'd0: x_byteEn__h7271 = be__h8760; - 3'd1: x_byteEn__h7271 = be__h8779; - 3'd2: x_byteEn__h7271 = be__h8820; - 3'd3: x_byteEn__h7271 = be__h8876; - 3'd4: x_byteEn__h7271 = be__h8947; - 3'd5: x_byteEn__h7271 = be__h9033; - 3'd6: x_byteEn__h7271 = be__h9134; - 3'd7: x_byteEn__h7271 = be__h9250; + 3'd0: x_byteEn__h6989 = be__h8502; + 3'd1: x_byteEn__h6989 = be__h8521; + 3'd2: x_byteEn__h6989 = be__h8562; + 3'd3: x_byteEn__h6989 = be__h8618; + 3'd4: x_byteEn__h6989 = be__h8689; + 3'd5: x_byteEn__h6989 = be__h8775; + 3'd6: x_byteEn__h6989 = be__h8876; + 3'd7: x_byteEn__h6989 = be__h8992; endcase end @@ -944,7 +954,7 @@ module mkWsiAdapter4B32B(CLK, wsiM_operateD <= `BSV_ASSIGNMENT_DELAY 1'd0; wsiM_pMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0; wsiM_peerIsReady <= `BSV_ASSIGNMENT_DELAY 1'd0; - wsiM_reqFifo_c_r <= `BSV_ASSIGNMENT_DELAY 2'd0; + wsiM_reqFifo_cntr_r <= `BSV_ASSIGNMENT_DELAY 2'd0; wsiM_reqFifo_q_0 <= `BSV_ASSIGNMENT_DELAY 313'h00000AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA00; wsiM_reqFifo_q_1 <= `BSV_ASSIGNMENT_DELAY @@ -981,8 +991,9 @@ module mkWsiAdapter4B32B(CLK, wsiM_pMesgCount <= `BSV_ASSIGNMENT_DELAY wsiM_pMesgCount$D_IN; if (wsiM_peerIsReady$EN) wsiM_peerIsReady <= `BSV_ASSIGNMENT_DELAY wsiM_peerIsReady$D_IN; - if (wsiM_reqFifo_c_r$EN) - wsiM_reqFifo_c_r <= `BSV_ASSIGNMENT_DELAY wsiM_reqFifo_c_r$D_IN; + if (wsiM_reqFifo_cntr_r$EN) + wsiM_reqFifo_cntr_r <= `BSV_ASSIGNMENT_DELAY + wsiM_reqFifo_cntr_r$D_IN; if (wsiM_reqFifo_q_0$EN) wsiM_reqFifo_q_0 <= `BSV_ASSIGNMENT_DELAY wsiM_reqFifo_q_0$D_IN; if (wsiM_reqFifo_q_1$EN) @@ -1018,7 +1029,7 @@ module mkWsiAdapter4B32B(CLK, if (wsiS_wordCount$EN) wsiS_wordCount <= `BSV_ASSIGNMENT_DELAY wsiS_wordCount$D_IN; end - if (stage$EN) stage <= `BSV_ASSIGNMENT_DELAY stage$D_IN; + if (stage_0$EN) stage_0 <= `BSV_ASSIGNMENT_DELAY stage_0$D_IN; if (stage_1$EN) stage_1 <= `BSV_ASSIGNMENT_DELAY stage_1$D_IN; if (stage_2$EN) stage_2 <= `BSV_ASSIGNMENT_DELAY stage_2$D_IN; if (stage_3$EN) stage_3 <= `BSV_ASSIGNMENT_DELAY stage_3$D_IN; @@ -1058,7 +1069,7 @@ module mkWsiAdapter4B32B(CLK, isFull = 1'h0; isLast = 1'h0; pos = 3'h2; - stage = 61'h0AAAAAAAAAAAAAAA; + stage_0 = 61'h0AAAAAAAAAAAAAAA; stage_1 = 61'h0AAAAAAAAAAAAAAA; stage_2 = 61'h0AAAAAAAAAAAAAAA; stage_3 = 61'h0AAAAAAAAAAAAAAA; @@ -1073,7 +1084,7 @@ module mkWsiAdapter4B32B(CLK, wsiM_operateD = 1'h0; wsiM_pMesgCount = 32'hAAAAAAAA; wsiM_peerIsReady = 1'h0; - wsiM_reqFifo_c_r = 2'h2; + wsiM_reqFifo_cntr_r = 2'h2; wsiM_reqFifo_q_0 = 313'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; wsiM_reqFifo_q_1 = diff --git a/rtl/mkWsiSplitter2x216B.v b/rtl/mkWsiSplitter2x216B.v new file mode 100644 index 00000000..176dc378 --- /dev/null +++ b/rtl/mkWsiSplitter2x216B.v @@ -0,0 +1,2447 @@ +// +// Generated by Bluespec Compiler, version 2012.09.beta1 (build 29570, 2012-09.11) +// +// On Tue Jan 22 07:33:06 EST 2013 +// +// +// Ports: +// Name I/O size props +// wciS0_SResp O 2 reg +// wciS0_SData O 32 reg +// wciS0_SThreadBusy O 1 +// wciS0_SFlag O 2 +// wsiS0_SThreadBusy O 1 +// wsiS0_SReset_n O 1 +// wsiS1_SThreadBusy O 1 +// wsiS1_SReset_n O 1 +// wsiM0_MCmd O 3 +// wsiM0_MReqLast O 1 +// wsiM0_MBurstPrecise O 1 +// wsiM0_MBurstLength O 12 +// wsiM0_MData O 128 reg +// wsiM0_MByteEn O 16 reg +// wsiM0_MReqInfo O 8 +// wsiM0_MReset_n O 1 +// wsiM1_MCmd O 3 +// wsiM1_MReqLast O 1 +// wsiM1_MBurstPrecise O 1 +// wsiM1_MBurstLength O 12 +// wsiM1_MData O 128 reg +// wsiM1_MByteEn O 16 reg +// wsiM1_MReqInfo O 8 +// wsiM1_MReset_n O 1 +// wciS0_Clk I 1 clock +// wciS0_MReset_n I 1 reset +// wciS0_MCmd I 3 +// wciS0_MAddrSpace I 1 +// wciS0_MByteEn I 4 +// wciS0_MAddr I 32 +// wciS0_MData I 32 +// wciS0_MFlag I 2 unused +// wsiS0_MCmd I 3 +// wsiS0_MBurstLength I 12 +// wsiS0_MData I 128 +// wsiS0_MByteEn I 16 +// wsiS0_MReqInfo I 8 +// wsiS1_MCmd I 3 +// wsiS1_MBurstLength I 12 +// wsiS1_MData I 128 +// wsiS1_MByteEn I 16 +// wsiS1_MReqInfo I 8 +// wsiS0_MReqLast I 1 +// wsiS0_MBurstPrecise I 1 +// wsiS0_MReset_n I 1 reg +// wsiS1_MReqLast I 1 +// wsiS1_MBurstPrecise I 1 +// wsiS1_MReset_n I 1 reg +// wsiM0_SThreadBusy I 1 reg +// wsiM0_SReset_n I 1 reg +// wsiM1_SThreadBusy I 1 reg +// wsiM1_SReset_n I 1 reg +// +// No combinational paths from inputs to outputs +// +// + +`ifdef BSV_ASSIGNMENT_DELAY +`else + `define BSV_ASSIGNMENT_DELAY +`endif + +`ifdef BSV_POSITIVE_RESET + `define BSV_RESET_VALUE 1'b1 + `define BSV_RESET_EDGE posedge +`else + `define BSV_RESET_VALUE 1'b0 + `define BSV_RESET_EDGE negedge +`endif + +module mkWsiSplitter2x216B(wciS0_Clk, + wciS0_MReset_n, + + wciS0_MCmd, + + wciS0_MAddrSpace, + + wciS0_MByteEn, + + wciS0_MAddr, + + wciS0_MData, + + wciS0_SResp, + + wciS0_SData, + + wciS0_SThreadBusy, + + wciS0_SFlag, + + wciS0_MFlag, + + wsiS0_MCmd, + + wsiS0_MReqLast, + + wsiS0_MBurstPrecise, + + wsiS0_MBurstLength, + + wsiS0_MData, + + wsiS0_MByteEn, + + wsiS0_MReqInfo, + + wsiS0_SThreadBusy, + + wsiS0_SReset_n, + + wsiS0_MReset_n, + + wsiS1_MCmd, + + wsiS1_MReqLast, + + wsiS1_MBurstPrecise, + + wsiS1_MBurstLength, + + wsiS1_MData, + + wsiS1_MByteEn, + + wsiS1_MReqInfo, + + wsiS1_SThreadBusy, + + wsiS1_SReset_n, + + wsiS1_MReset_n, + + wsiM0_MCmd, + + wsiM0_MReqLast, + + wsiM0_MBurstPrecise, + + wsiM0_MBurstLength, + + wsiM0_MData, + + wsiM0_MByteEn, + + wsiM0_MReqInfo, + + wsiM0_SThreadBusy, + + wsiM0_MReset_n, + + wsiM0_SReset_n, + + wsiM1_MCmd, + + wsiM1_MReqLast, + + wsiM1_MBurstPrecise, + + wsiM1_MBurstLength, + + wsiM1_MData, + + wsiM1_MByteEn, + + wsiM1_MReqInfo, + + wsiM1_SThreadBusy, + + wsiM1_MReset_n, + + wsiM1_SReset_n); + parameter [31 : 0] ctrlInit = 32'b0; + parameter [0 : 0] hasDebugLogic = 1'b0; + input wciS0_Clk; + input wciS0_MReset_n; + + // action method wciS0_mCmd + input [2 : 0] wciS0_MCmd; + + // action method wciS0_mAddrSpace + input wciS0_MAddrSpace; + + // action method wciS0_mByteEn + input [3 : 0] wciS0_MByteEn; + + // action method wciS0_mAddr + input [31 : 0] wciS0_MAddr; + + // action method wciS0_mData + input [31 : 0] wciS0_MData; + + // value method wciS0_sResp + output [1 : 0] wciS0_SResp; + + // value method wciS0_sData + output [31 : 0] wciS0_SData; + + // value method wciS0_sThreadBusy + output wciS0_SThreadBusy; + + // value method wciS0_sFlag + output [1 : 0] wciS0_SFlag; + + // action method wciS0_mFlag + input [1 : 0] wciS0_MFlag; + + // action method wsiS0_mCmd + input [2 : 0] wsiS0_MCmd; + + // action method wsiS0_mReqLast + input wsiS0_MReqLast; + + // action method wsiS0_mBurstPrecise + input wsiS0_MBurstPrecise; + + // action method wsiS0_mBurstLength + input [11 : 0] wsiS0_MBurstLength; + + // action method wsiS0_mData + input [127 : 0] wsiS0_MData; + + // action method wsiS0_mByteEn + input [15 : 0] wsiS0_MByteEn; + + // action method wsiS0_mReqInfo + input [7 : 0] wsiS0_MReqInfo; + + // action method wsiS0_mDataInfo + + // value method wsiS0_sThreadBusy + output wsiS0_SThreadBusy; + + // value method wsiS0_sReset_n + output wsiS0_SReset_n; + + // action method wsiS0_mReset_n + input wsiS0_MReset_n; + + // action method wsiS1_mCmd + input [2 : 0] wsiS1_MCmd; + + // action method wsiS1_mReqLast + input wsiS1_MReqLast; + + // action method wsiS1_mBurstPrecise + input wsiS1_MBurstPrecise; + + // action method wsiS1_mBurstLength + input [11 : 0] wsiS1_MBurstLength; + + // action method wsiS1_mData + input [127 : 0] wsiS1_MData; + + // action method wsiS1_mByteEn + input [15 : 0] wsiS1_MByteEn; + + // action method wsiS1_mReqInfo + input [7 : 0] wsiS1_MReqInfo; + + // action method wsiS1_mDataInfo + + // value method wsiS1_sThreadBusy + output wsiS1_SThreadBusy; + + // value method wsiS1_sReset_n + output wsiS1_SReset_n; + + // action method wsiS1_mReset_n + input wsiS1_MReset_n; + + // value method wsiM0_mCmd + output [2 : 0] wsiM0_MCmd; + + // value method wsiM0_mReqLast + output wsiM0_MReqLast; + + // value method wsiM0_mBurstPrecise + output wsiM0_MBurstPrecise; + + // value method wsiM0_mBurstLength + output [11 : 0] wsiM0_MBurstLength; + + // value method wsiM0_mData + output [127 : 0] wsiM0_MData; + + // value method wsiM0_mByteEn + output [15 : 0] wsiM0_MByteEn; + + // value method wsiM0_mReqInfo + output [7 : 0] wsiM0_MReqInfo; + + // value method wsiM0_mDataInfo + + // action method wsiM0_sThreadBusy + input wsiM0_SThreadBusy; + + // value method wsiM0_mReset_n + output wsiM0_MReset_n; + + // action method wsiM0_sReset_n + input wsiM0_SReset_n; + + // value method wsiM1_mCmd + output [2 : 0] wsiM1_MCmd; + + // value method wsiM1_mReqLast + output wsiM1_MReqLast; + + // value method wsiM1_mBurstPrecise + output wsiM1_MBurstPrecise; + + // value method wsiM1_mBurstLength + output [11 : 0] wsiM1_MBurstLength; + + // value method wsiM1_mData + output [127 : 0] wsiM1_MData; + + // value method wsiM1_mByteEn + output [15 : 0] wsiM1_MByteEn; + + // value method wsiM1_mReqInfo + output [7 : 0] wsiM1_MReqInfo; + + // value method wsiM1_mDataInfo + + // action method wsiM1_sThreadBusy + input wsiM1_SThreadBusy; + + // value method wsiM1_mReset_n + output wsiM1_MReset_n; + + // action method wsiM1_sReset_n + input wsiM1_SReset_n; + + // signals for module outputs + wire [127 : 0] wsiM0_MData, wsiM1_MData; + wire [31 : 0] wciS0_SData; + wire [15 : 0] wsiM0_MByteEn, wsiM1_MByteEn; + wire [11 : 0] wsiM0_MBurstLength, wsiM1_MBurstLength; + wire [7 : 0] wsiM0_MReqInfo, wsiM1_MReqInfo; + wire [2 : 0] wsiM0_MCmd, wsiM1_MCmd; + wire [1 : 0] wciS0_SFlag, wciS0_SResp; + wire wciS0_SThreadBusy, + wsiM0_MBurstPrecise, + wsiM0_MReqLast, + wsiM0_MReset_n, + wsiM1_MBurstPrecise, + wsiM1_MReqLast, + wsiM1_MReset_n, + wsiS0_SReset_n, + wsiS0_SThreadBusy, + wsiS1_SReset_n, + wsiS1_SThreadBusy; + + // inlined wires + wire [168 : 0] wsi_M0_reqFifo_x_wire$wget, + wsi_M1_reqFifo_x_wire$wget, + wsi_S0_wsiReq$wget, + wsi_S1_wsiReq$wget; + wire [127 : 0] wsi_Es0_mData_w$wget, wsi_Es1_mData_w$wget; + wire [95 : 0] wsi_M0_extStatusW$wget, + wsi_M1_extStatusW$wget, + wsi_S0_extStatusW$wget, + wsi_S1_extStatusW$wget; + wire [71 : 0] wci_wciReq$wget; + wire [33 : 0] wci_respF_x_wire$wget; + wire [31 : 0] wci_Es_mAddr_w$wget, wci_Es_mData_w$wget; + wire [15 : 0] wsi_Es0_mByteEn_w$wget, wsi_Es1_mByteEn_w$wget; + wire [11 : 0] wsi_Es0_mBurstLength_w$wget, wsi_Es1_mBurstLength_w$wget; + wire [7 : 0] wsi_Es0_mReqInfo_w$wget, wsi_Es1_mReqInfo_w$wget; + wire [3 : 0] wci_Es_mByteEn_w$wget; + wire [2 : 0] wci_Es_mCmd_w$wget, + wci_wEdge$wget, + wsi_Es0_mCmd_w$wget, + wsi_Es1_mCmd_w$wget; + wire wci_Es_mAddrSpace_w$wget, + wci_Es_mAddrSpace_w$whas, + wci_Es_mAddr_w$whas, + wci_Es_mByteEn_w$whas, + wci_Es_mCmd_w$whas, + wci_Es_mData_w$whas, + wci_ctlAckReg_1$wget, + wci_ctlAckReg_1$whas, + wci_reqF_r_clr$whas, + wci_reqF_r_deq$whas, + wci_reqF_r_enq$whas, + wci_respF_dequeueing$whas, + wci_respF_enqueueing$whas, + wci_respF_x_wire$whas, + wci_sFlagReg_1$wget, + wci_sFlagReg_1$whas, + wci_sThreadBusy_pw$whas, + wci_wEdge$whas, + wci_wciReq$whas, + wci_wci_cfrd_pw$whas, + wci_wci_cfwr_pw$whas, + wci_wci_ctrl_pw$whas, + wsi_Es0_mBurstLength_w$whas, + wsi_Es0_mBurstPrecise_w$whas, + wsi_Es0_mByteEn_w$whas, + wsi_Es0_mCmd_w$whas, + wsi_Es0_mDataInfo_w$whas, + wsi_Es0_mData_w$whas, + wsi_Es0_mReqInfo_w$whas, + wsi_Es0_mReqLast_w$whas, + wsi_Es1_mBurstLength_w$whas, + wsi_Es1_mBurstPrecise_w$whas, + wsi_Es1_mByteEn_w$whas, + wsi_Es1_mCmd_w$whas, + wsi_Es1_mDataInfo_w$whas, + wsi_Es1_mData_w$whas, + wsi_Es1_mReqInfo_w$whas, + wsi_Es1_mReqLast_w$whas, + wsi_M0_operateD_1$wget, + wsi_M0_operateD_1$whas, + wsi_M0_peerIsReady_1$wget, + wsi_M0_peerIsReady_1$whas, + wsi_M0_reqFifo_dequeueing$whas, + wsi_M0_reqFifo_enqueueing$whas, + wsi_M0_reqFifo_x_wire$whas, + wsi_M0_sThreadBusy_pw$whas, + wsi_M1_operateD_1$wget, + wsi_M1_operateD_1$whas, + wsi_M1_peerIsReady_1$wget, + wsi_M1_peerIsReady_1$whas, + wsi_M1_reqFifo_dequeueing$whas, + wsi_M1_reqFifo_enqueueing$whas, + wsi_M1_reqFifo_x_wire$whas, + wsi_M1_sThreadBusy_pw$whas, + wsi_S0_operateD_1$wget, + wsi_S0_operateD_1$whas, + wsi_S0_peerIsReady_1$wget, + wsi_S0_peerIsReady_1$whas, + wsi_S0_reqFifo_doResetClr$whas, + wsi_S0_reqFifo_doResetDeq$whas, + wsi_S0_reqFifo_doResetEnq$whas, + wsi_S0_reqFifo_r_clr$whas, + wsi_S0_reqFifo_r_deq$whas, + wsi_S0_reqFifo_r_enq$whas, + wsi_S0_sThreadBusy_dw$wget, + wsi_S0_sThreadBusy_dw$whas, + wsi_S0_wsiReq$whas, + wsi_S1_operateD_1$wget, + wsi_S1_operateD_1$whas, + wsi_S1_peerIsReady_1$wget, + wsi_S1_peerIsReady_1$whas, + wsi_S1_reqFifo_doResetClr$whas, + wsi_S1_reqFifo_doResetDeq$whas, + wsi_S1_reqFifo_doResetEnq$whas, + wsi_S1_reqFifo_r_clr$whas, + wsi_S1_reqFifo_r_deq$whas, + wsi_S1_reqFifo_r_enq$whas, + wsi_S1_sThreadBusy_dw$wget, + wsi_S1_sThreadBusy_dw$whas, + wsi_S1_wsiReq$whas; + + // register splitCtrl + reg [31 : 0] splitCtrl; + wire [31 : 0] splitCtrl$D_IN; + wire splitCtrl$EN; + + // register wci_cEdge + reg [2 : 0] wci_cEdge; + wire [2 : 0] wci_cEdge$D_IN; + wire wci_cEdge$EN; + + // register wci_cState + reg [2 : 0] wci_cState; + wire [2 : 0] wci_cState$D_IN; + wire wci_cState$EN; + + // register wci_ctlAckReg + reg wci_ctlAckReg; + wire wci_ctlAckReg$D_IN, wci_ctlAckReg$EN; + + // register wci_ctlOpActive + reg wci_ctlOpActive; + wire wci_ctlOpActive$D_IN, wci_ctlOpActive$EN; + + // register wci_illegalEdge + reg wci_illegalEdge; + wire wci_illegalEdge$D_IN, wci_illegalEdge$EN; + + // register wci_isReset_isInReset + reg wci_isReset_isInReset; + wire wci_isReset_isInReset$D_IN, wci_isReset_isInReset$EN; + + // register wci_nState + reg [2 : 0] wci_nState; + reg [2 : 0] wci_nState$D_IN; + wire wci_nState$EN; + + // register wci_reqF_countReg + reg [1 : 0] wci_reqF_countReg; + wire [1 : 0] wci_reqF_countReg$D_IN; + wire wci_reqF_countReg$EN; + + // register wci_respF_c_r + reg [1 : 0] wci_respF_c_r; + wire [1 : 0] wci_respF_c_r$D_IN; + wire wci_respF_c_r$EN; + + // register wci_respF_q_0 + reg [33 : 0] wci_respF_q_0; + reg [33 : 0] wci_respF_q_0$D_IN; + wire wci_respF_q_0$EN; + + // register wci_respF_q_1 + reg [33 : 0] wci_respF_q_1; + reg [33 : 0] wci_respF_q_1$D_IN; + wire wci_respF_q_1$EN; + + // register wci_sFlagReg + reg wci_sFlagReg; + wire wci_sFlagReg$D_IN, wci_sFlagReg$EN; + + // register wci_sThreadBusy_d + reg wci_sThreadBusy_d; + wire wci_sThreadBusy_d$D_IN, wci_sThreadBusy_d$EN; + + // register wsi_M0_burstKind + reg [1 : 0] wsi_M0_burstKind; + wire [1 : 0] wsi_M0_burstKind$D_IN; + wire wsi_M0_burstKind$EN; + + // register wsi_M0_errorSticky + reg wsi_M0_errorSticky; + wire wsi_M0_errorSticky$D_IN, wsi_M0_errorSticky$EN; + + // register wsi_M0_iMesgCount + reg [31 : 0] wsi_M0_iMesgCount; + wire [31 : 0] wsi_M0_iMesgCount$D_IN; + wire wsi_M0_iMesgCount$EN; + + // register wsi_M0_isReset_isInReset + reg wsi_M0_isReset_isInReset; + wire wsi_M0_isReset_isInReset$D_IN, wsi_M0_isReset_isInReset$EN; + + // register wsi_M0_operateD + reg wsi_M0_operateD; + wire wsi_M0_operateD$D_IN, wsi_M0_operateD$EN; + + // register wsi_M0_pMesgCount + reg [31 : 0] wsi_M0_pMesgCount; + wire [31 : 0] wsi_M0_pMesgCount$D_IN; + wire wsi_M0_pMesgCount$EN; + + // register wsi_M0_peerIsReady + reg wsi_M0_peerIsReady; + wire wsi_M0_peerIsReady$D_IN, wsi_M0_peerIsReady$EN; + + // register wsi_M0_reqFifo_c_r + reg [1 : 0] wsi_M0_reqFifo_c_r; + wire [1 : 0] wsi_M0_reqFifo_c_r$D_IN; + wire wsi_M0_reqFifo_c_r$EN; + + // register wsi_M0_reqFifo_q_0 + reg [168 : 0] wsi_M0_reqFifo_q_0; + reg [168 : 0] wsi_M0_reqFifo_q_0$D_IN; + wire wsi_M0_reqFifo_q_0$EN; + + // register wsi_M0_reqFifo_q_1 + reg [168 : 0] wsi_M0_reqFifo_q_1; + reg [168 : 0] wsi_M0_reqFifo_q_1$D_IN; + wire wsi_M0_reqFifo_q_1$EN; + + // register wsi_M0_sThreadBusy_d + reg wsi_M0_sThreadBusy_d; + wire wsi_M0_sThreadBusy_d$D_IN, wsi_M0_sThreadBusy_d$EN; + + // register wsi_M0_statusR + reg [7 : 0] wsi_M0_statusR; + wire [7 : 0] wsi_M0_statusR$D_IN; + wire wsi_M0_statusR$EN; + + // register wsi_M0_tBusyCount + reg [31 : 0] wsi_M0_tBusyCount; + wire [31 : 0] wsi_M0_tBusyCount$D_IN; + wire wsi_M0_tBusyCount$EN; + + // register wsi_M0_trafficSticky + reg wsi_M0_trafficSticky; + wire wsi_M0_trafficSticky$D_IN, wsi_M0_trafficSticky$EN; + + // register wsi_M1_burstKind + reg [1 : 0] wsi_M1_burstKind; + wire [1 : 0] wsi_M1_burstKind$D_IN; + wire wsi_M1_burstKind$EN; + + // register wsi_M1_errorSticky + reg wsi_M1_errorSticky; + wire wsi_M1_errorSticky$D_IN, wsi_M1_errorSticky$EN; + + // register wsi_M1_iMesgCount + reg [31 : 0] wsi_M1_iMesgCount; + wire [31 : 0] wsi_M1_iMesgCount$D_IN; + wire wsi_M1_iMesgCount$EN; + + // register wsi_M1_isReset_isInReset + reg wsi_M1_isReset_isInReset; + wire wsi_M1_isReset_isInReset$D_IN, wsi_M1_isReset_isInReset$EN; + + // register wsi_M1_operateD + reg wsi_M1_operateD; + wire wsi_M1_operateD$D_IN, wsi_M1_operateD$EN; + + // register wsi_M1_pMesgCount + reg [31 : 0] wsi_M1_pMesgCount; + wire [31 : 0] wsi_M1_pMesgCount$D_IN; + wire wsi_M1_pMesgCount$EN; + + // register wsi_M1_peerIsReady + reg wsi_M1_peerIsReady; + wire wsi_M1_peerIsReady$D_IN, wsi_M1_peerIsReady$EN; + + // register wsi_M1_reqFifo_c_r + reg [1 : 0] wsi_M1_reqFifo_c_r; + wire [1 : 0] wsi_M1_reqFifo_c_r$D_IN; + wire wsi_M1_reqFifo_c_r$EN; + + // register wsi_M1_reqFifo_q_0 + reg [168 : 0] wsi_M1_reqFifo_q_0; + reg [168 : 0] wsi_M1_reqFifo_q_0$D_IN; + wire wsi_M1_reqFifo_q_0$EN; + + // register wsi_M1_reqFifo_q_1 + reg [168 : 0] wsi_M1_reqFifo_q_1; + reg [168 : 0] wsi_M1_reqFifo_q_1$D_IN; + wire wsi_M1_reqFifo_q_1$EN; + + // register wsi_M1_sThreadBusy_d + reg wsi_M1_sThreadBusy_d; + wire wsi_M1_sThreadBusy_d$D_IN, wsi_M1_sThreadBusy_d$EN; + + // register wsi_M1_statusR + reg [7 : 0] wsi_M1_statusR; + wire [7 : 0] wsi_M1_statusR$D_IN; + wire wsi_M1_statusR$EN; + + // register wsi_M1_tBusyCount + reg [31 : 0] wsi_M1_tBusyCount; + wire [31 : 0] wsi_M1_tBusyCount$D_IN; + wire wsi_M1_tBusyCount$EN; + + // register wsi_M1_trafficSticky + reg wsi_M1_trafficSticky; + wire wsi_M1_trafficSticky$D_IN, wsi_M1_trafficSticky$EN; + + // register wsi_S0_burstKind + reg [1 : 0] wsi_S0_burstKind; + wire [1 : 0] wsi_S0_burstKind$D_IN; + wire wsi_S0_burstKind$EN; + + // register wsi_S0_errorSticky + reg wsi_S0_errorSticky; + wire wsi_S0_errorSticky$D_IN, wsi_S0_errorSticky$EN; + + // register wsi_S0_iMesgCount + reg [31 : 0] wsi_S0_iMesgCount; + wire [31 : 0] wsi_S0_iMesgCount$D_IN; + wire wsi_S0_iMesgCount$EN; + + // register wsi_S0_isReset_isInReset + reg wsi_S0_isReset_isInReset; + wire wsi_S0_isReset_isInReset$D_IN, wsi_S0_isReset_isInReset$EN; + + // register wsi_S0_mesgWordLength + reg [11 : 0] wsi_S0_mesgWordLength; + wire [11 : 0] wsi_S0_mesgWordLength$D_IN; + wire wsi_S0_mesgWordLength$EN; + + // register wsi_S0_operateD + reg wsi_S0_operateD; + wire wsi_S0_operateD$D_IN, wsi_S0_operateD$EN; + + // register wsi_S0_pMesgCount + reg [31 : 0] wsi_S0_pMesgCount; + wire [31 : 0] wsi_S0_pMesgCount$D_IN; + wire wsi_S0_pMesgCount$EN; + + // register wsi_S0_peerIsReady + reg wsi_S0_peerIsReady; + wire wsi_S0_peerIsReady$D_IN, wsi_S0_peerIsReady$EN; + + // register wsi_S0_reqFifo_countReg + reg [1 : 0] wsi_S0_reqFifo_countReg; + wire [1 : 0] wsi_S0_reqFifo_countReg$D_IN; + wire wsi_S0_reqFifo_countReg$EN; + + // register wsi_S0_reqFifo_levelsValid + reg wsi_S0_reqFifo_levelsValid; + wire wsi_S0_reqFifo_levelsValid$D_IN, wsi_S0_reqFifo_levelsValid$EN; + + // register wsi_S0_statusR + reg [7 : 0] wsi_S0_statusR; + wire [7 : 0] wsi_S0_statusR$D_IN; + wire wsi_S0_statusR$EN; + + // register wsi_S0_tBusyCount + reg [31 : 0] wsi_S0_tBusyCount; + wire [31 : 0] wsi_S0_tBusyCount$D_IN; + wire wsi_S0_tBusyCount$EN; + + // register wsi_S0_trafficSticky + reg wsi_S0_trafficSticky; + wire wsi_S0_trafficSticky$D_IN, wsi_S0_trafficSticky$EN; + + // register wsi_S0_wordCount + reg [11 : 0] wsi_S0_wordCount; + wire [11 : 0] wsi_S0_wordCount$D_IN; + wire wsi_S0_wordCount$EN; + + // register wsi_S1_burstKind + reg [1 : 0] wsi_S1_burstKind; + wire [1 : 0] wsi_S1_burstKind$D_IN; + wire wsi_S1_burstKind$EN; + + // register wsi_S1_errorSticky + reg wsi_S1_errorSticky; + wire wsi_S1_errorSticky$D_IN, wsi_S1_errorSticky$EN; + + // register wsi_S1_iMesgCount + reg [31 : 0] wsi_S1_iMesgCount; + wire [31 : 0] wsi_S1_iMesgCount$D_IN; + wire wsi_S1_iMesgCount$EN; + + // register wsi_S1_isReset_isInReset + reg wsi_S1_isReset_isInReset; + wire wsi_S1_isReset_isInReset$D_IN, wsi_S1_isReset_isInReset$EN; + + // register wsi_S1_mesgWordLength + reg [11 : 0] wsi_S1_mesgWordLength; + wire [11 : 0] wsi_S1_mesgWordLength$D_IN; + wire wsi_S1_mesgWordLength$EN; + + // register wsi_S1_operateD + reg wsi_S1_operateD; + wire wsi_S1_operateD$D_IN, wsi_S1_operateD$EN; + + // register wsi_S1_pMesgCount + reg [31 : 0] wsi_S1_pMesgCount; + wire [31 : 0] wsi_S1_pMesgCount$D_IN; + wire wsi_S1_pMesgCount$EN; + + // register wsi_S1_peerIsReady + reg wsi_S1_peerIsReady; + wire wsi_S1_peerIsReady$D_IN, wsi_S1_peerIsReady$EN; + + // register wsi_S1_reqFifo_countReg + reg [1 : 0] wsi_S1_reqFifo_countReg; + wire [1 : 0] wsi_S1_reqFifo_countReg$D_IN; + wire wsi_S1_reqFifo_countReg$EN; + + // register wsi_S1_reqFifo_levelsValid + reg wsi_S1_reqFifo_levelsValid; + wire wsi_S1_reqFifo_levelsValid$D_IN, wsi_S1_reqFifo_levelsValid$EN; + + // register wsi_S1_statusR + reg [7 : 0] wsi_S1_statusR; + wire [7 : 0] wsi_S1_statusR$D_IN; + wire wsi_S1_statusR$EN; + + // register wsi_S1_tBusyCount + reg [31 : 0] wsi_S1_tBusyCount; + wire [31 : 0] wsi_S1_tBusyCount$D_IN; + wire wsi_S1_tBusyCount$EN; + + // register wsi_S1_trafficSticky + reg wsi_S1_trafficSticky; + wire wsi_S1_trafficSticky$D_IN, wsi_S1_trafficSticky$EN; + + // register wsi_S1_wordCount + reg [11 : 0] wsi_S1_wordCount; + wire [11 : 0] wsi_S1_wordCount$D_IN; + wire wsi_S1_wordCount$EN; + + // ports of submodule wci_reqF + wire [71 : 0] wci_reqF$D_IN, wci_reqF$D_OUT; + wire wci_reqF$CLR, wci_reqF$DEQ, wci_reqF$EMPTY_N, wci_reqF$ENQ; + + // ports of submodule wsi_S0_reqFifo + wire [168 : 0] wsi_S0_reqFifo$D_IN, wsi_S0_reqFifo$D_OUT; + wire wsi_S0_reqFifo$CLR, + wsi_S0_reqFifo$DEQ, + wsi_S0_reqFifo$EMPTY_N, + wsi_S0_reqFifo$ENQ, + wsi_S0_reqFifo$FULL_N; + + // ports of submodule wsi_S1_reqFifo + wire [168 : 0] wsi_S1_reqFifo$D_IN, wsi_S1_reqFifo$D_OUT; + wire wsi_S1_reqFifo$CLR, + wsi_S1_reqFifo$DEQ, + wsi_S1_reqFifo$EMPTY_N, + wsi_S1_reqFifo$ENQ, + wsi_S1_reqFifo$FULL_N; + + // rule scheduling signals + wire CAN_FIRE_RL_doMessageConsume_S1, + WILL_FIRE_RL_doMessageConsume_S0, + WILL_FIRE_RL_doMessageConsume_S1, + WILL_FIRE_RL_wci_cfrd, + WILL_FIRE_RL_wci_cfwr, + WILL_FIRE_RL_wci_ctl_op_complete, + WILL_FIRE_RL_wci_ctl_op_start, + WILL_FIRE_RL_wci_ctrl_EiI, + WILL_FIRE_RL_wci_ctrl_IsO, + WILL_FIRE_RL_wci_ctrl_OrE, + WILL_FIRE_RL_wci_respF_both, + WILL_FIRE_RL_wci_respF_decCtr, + WILL_FIRE_RL_wci_respF_incCtr, + WILL_FIRE_RL_wsi_M0_reqFifo_both, + WILL_FIRE_RL_wsi_M0_reqFifo_decCtr, + WILL_FIRE_RL_wsi_M0_reqFifo_deq, + WILL_FIRE_RL_wsi_M0_reqFifo_incCtr, + WILL_FIRE_RL_wsi_M1_reqFifo_both, + WILL_FIRE_RL_wsi_M1_reqFifo_decCtr, + WILL_FIRE_RL_wsi_M1_reqFifo_deq, + WILL_FIRE_RL_wsi_M1_reqFifo_incCtr, + WILL_FIRE_RL_wsi_S0_reqFifo_enq, + WILL_FIRE_RL_wsi_S0_reqFifo_reset, + WILL_FIRE_RL_wsi_S1_reqFifo_enq, + WILL_FIRE_RL_wsi_S1_reqFifo_reset; + + // inputs to muxes for submodule ports + reg [33 : 0] MUX_wci_respF_q_0$write_1__VAL_2; + wire [168 : 0] MUX_wsi_M0_reqFifo_q_0$write_1__VAL_1, + MUX_wsi_M0_reqFifo_q_0$write_1__VAL_2, + MUX_wsi_M0_reqFifo_q_1$write_1__VAL_1, + MUX_wsi_M1_reqFifo_q_0$write_1__VAL_1, + MUX_wsi_M1_reqFifo_q_0$write_1__VAL_2, + MUX_wsi_M1_reqFifo_q_1$write_1__VAL_1; + wire [33 : 0] MUX_wci_respF_q_0$write_1__VAL_1, + MUX_wci_respF_q_1$write_1__VAL_1, + MUX_wci_respF_x_wire$wset_1__VAL_1, + MUX_wci_respF_x_wire$wset_1__VAL_2; + wire [1 : 0] MUX_wci_respF_c_r$write_1__VAL_1, + MUX_wci_respF_c_r$write_1__VAL_2, + MUX_wsi_M0_reqFifo_c_r$write_1__VAL_1, + MUX_wsi_M0_reqFifo_c_r$write_1__VAL_2, + MUX_wsi_M1_reqFifo_c_r$write_1__VAL_1, + MUX_wsi_M1_reqFifo_c_r$write_1__VAL_2; + wire MUX_wci_illegalEdge$write_1__SEL_1, + MUX_wci_illegalEdge$write_1__VAL_1, + MUX_wci_respF_q_0$write_1__SEL_2, + MUX_wci_respF_q_1$write_1__SEL_2, + MUX_wsi_M0_reqFifo_q_0$write_1__SEL_2, + MUX_wsi_M0_reqFifo_q_1$write_1__SEL_2, + MUX_wsi_M0_reqFifo_x_wire$wset_1__SEL_1, + MUX_wsi_M1_reqFifo_q_0$write_1__SEL_2, + MUX_wsi_M1_reqFifo_q_1$write_1__SEL_2, + MUX_wsi_M1_reqFifo_x_wire$wset_1__SEL_1; + + // remaining internal signals + reg [63 : 0] v__h16289, v__h16444, v__h3698, v__h3873, v__h4017; + reg [31 : 0] _theResult____h16428; + wire [31 : 0] rdat__h16512, + rdat__h16701, + rdat__h16715, + rdat__h16723, + rdat__h16737, + rdat__h16745, + rdat__h16759, + rdat__h16767, + rdat__h16781; + + // value method wciS0_sResp + assign wciS0_SResp = wci_respF_q_0[33:32] ; + + // value method wciS0_sData + assign wciS0_SData = wci_respF_q_0[31:0] ; + + // value method wciS0_sThreadBusy + assign wciS0_SThreadBusy = + wci_reqF_countReg > 2'd1 || wci_isReset_isInReset ; + + // value method wciS0_sFlag + assign wciS0_SFlag = { 1'd1, wci_sFlagReg } ; + + // value method wsiS0_sThreadBusy + assign wsiS0_SThreadBusy = + !wsi_S0_sThreadBusy_dw$whas || wsi_S0_sThreadBusy_dw$wget ; + + // value method wsiS0_sReset_n + assign wsiS0_SReset_n = !wsi_S0_isReset_isInReset && wsi_S0_operateD ; + + // value method wsiS1_sThreadBusy + assign wsiS1_SThreadBusy = + !wsi_S1_sThreadBusy_dw$whas || wsi_S1_sThreadBusy_dw$wget ; + + // value method wsiS1_sReset_n + assign wsiS1_SReset_n = !wsi_S1_isReset_isInReset && wsi_S1_operateD ; + + // value method wsiM0_mCmd + assign wsiM0_MCmd = + wsi_M0_sThreadBusy_d ? 3'd0 : wsi_M0_reqFifo_q_0[168:166] ; + + // value method wsiM0_mReqLast + assign wsiM0_MReqLast = !wsi_M0_sThreadBusy_d && wsi_M0_reqFifo_q_0[165] ; + + // value method wsiM0_mBurstPrecise + assign wsiM0_MBurstPrecise = + !wsi_M0_sThreadBusy_d && wsi_M0_reqFifo_q_0[164] ; + + // value method wsiM0_mBurstLength + assign wsiM0_MBurstLength = + wsi_M0_sThreadBusy_d ? 12'd0 : wsi_M0_reqFifo_q_0[163:152] ; + + // value method wsiM0_mData + assign wsiM0_MData = wsi_M0_reqFifo_q_0[151:24] ; + + // value method wsiM0_mByteEn + assign wsiM0_MByteEn = wsi_M0_reqFifo_q_0[23:8] ; + + // value method wsiM0_mReqInfo + assign wsiM0_MReqInfo = + wsi_M0_sThreadBusy_d ? 8'd0 : wsi_M0_reqFifo_q_0[7:0] ; + + // value method wsiM0_mReset_n + assign wsiM0_MReset_n = !wsi_M0_isReset_isInReset && wsi_M0_operateD ; + + // value method wsiM1_mCmd + assign wsiM1_MCmd = + wsi_M1_sThreadBusy_d ? 3'd0 : wsi_M1_reqFifo_q_0[168:166] ; + + // value method wsiM1_mReqLast + assign wsiM1_MReqLast = !wsi_M1_sThreadBusy_d && wsi_M1_reqFifo_q_0[165] ; + + // value method wsiM1_mBurstPrecise + assign wsiM1_MBurstPrecise = + !wsi_M1_sThreadBusy_d && wsi_M1_reqFifo_q_0[164] ; + + // value method wsiM1_mBurstLength + assign wsiM1_MBurstLength = + wsi_M1_sThreadBusy_d ? 12'd0 : wsi_M1_reqFifo_q_0[163:152] ; + + // value method wsiM1_mData + assign wsiM1_MData = wsi_M1_reqFifo_q_0[151:24] ; + + // value method wsiM1_mByteEn + assign wsiM1_MByteEn = wsi_M1_reqFifo_q_0[23:8] ; + + // value method wsiM1_mReqInfo + assign wsiM1_MReqInfo = + wsi_M1_sThreadBusy_d ? 8'd0 : wsi_M1_reqFifo_q_0[7:0] ; + + // value method wsiM1_mReset_n + assign wsiM1_MReset_n = !wsi_M1_isReset_isInReset && wsi_M1_operateD ; + + // submodule wci_reqF + SizedFIFO #(.p1width(32'd72), + .p2depth(32'd3), + .p3cntr_width(32'd1), + .guarded(32'd1)) wci_reqF(.RST(wciS0_MReset_n), + .CLK(wciS0_Clk), + .D_IN(wci_reqF$D_IN), + .ENQ(wci_reqF$ENQ), + .DEQ(wci_reqF$DEQ), + .CLR(wci_reqF$CLR), + .D_OUT(wci_reqF$D_OUT), + .FULL_N(), + .EMPTY_N(wci_reqF$EMPTY_N)); + + // submodule wsi_S0_reqFifo + SizedFIFO #(.p1width(32'd169), + .p2depth(32'd3), + .p3cntr_width(32'd1), + .guarded(32'd1)) wsi_S0_reqFifo(.RST(wciS0_MReset_n), + .CLK(wciS0_Clk), + .D_IN(wsi_S0_reqFifo$D_IN), + .ENQ(wsi_S0_reqFifo$ENQ), + .DEQ(wsi_S0_reqFifo$DEQ), + .CLR(wsi_S0_reqFifo$CLR), + .D_OUT(wsi_S0_reqFifo$D_OUT), + .FULL_N(wsi_S0_reqFifo$FULL_N), + .EMPTY_N(wsi_S0_reqFifo$EMPTY_N)); + + // submodule wsi_S1_reqFifo + SizedFIFO #(.p1width(32'd169), + .p2depth(32'd3), + .p3cntr_width(32'd1), + .guarded(32'd1)) wsi_S1_reqFifo(.RST(wciS0_MReset_n), + .CLK(wciS0_Clk), + .D_IN(wsi_S1_reqFifo$D_IN), + .ENQ(wsi_S1_reqFifo$ENQ), + .DEQ(wsi_S1_reqFifo$DEQ), + .CLR(wsi_S1_reqFifo$CLR), + .D_OUT(wsi_S1_reqFifo$D_OUT), + .FULL_N(wsi_S1_reqFifo$FULL_N), + .EMPTY_N(wsi_S1_reqFifo$EMPTY_N)); + + // rule RL_wci_ctl_op_start + assign WILL_FIRE_RL_wci_ctl_op_start = + wci_reqF$EMPTY_N && wci_wci_ctrl_pw$whas && + !WILL_FIRE_RL_wci_ctl_op_complete ; + + // rule RL_wci_ctrl_EiI + assign WILL_FIRE_RL_wci_ctrl_EiI = + wci_wci_ctrl_pw$whas && WILL_FIRE_RL_wci_ctl_op_start && + wci_cState == 3'd0 && + wci_reqF$D_OUT[36:34] == 3'd0 ; + + // rule RL_wci_ctrl_IsO + assign WILL_FIRE_RL_wci_ctrl_IsO = + wci_wci_ctrl_pw$whas && WILL_FIRE_RL_wci_ctl_op_start && + wci_cState == 3'd1 && + wci_reqF$D_OUT[36:34] == 3'd1 ; + + // rule RL_wci_ctrl_OrE + assign WILL_FIRE_RL_wci_ctrl_OrE = + wci_wci_ctrl_pw$whas && WILL_FIRE_RL_wci_ctl_op_start && + wci_cState == 3'd2 && + wci_reqF$D_OUT[36:34] == 3'd3 ; + + // rule RL_doMessageConsume_S0 + assign WILL_FIRE_RL_doMessageConsume_S0 = + wsi_S0_reqFifo$EMPTY_N && + (splitCtrl[0] || splitCtrl[7] || wsi_M0_reqFifo_c_r != 2'd2) && + (splitCtrl[8] || splitCtrl[15] || wsi_M1_reqFifo_c_r != 2'd2) && + wci_cState == 3'd2 ; + + // rule RL_doMessageConsume_S1 + assign CAN_FIRE_RL_doMessageConsume_S1 = + wsi_S1_reqFifo$EMPTY_N && + (!splitCtrl[0] || splitCtrl[7] || wsi_M0_reqFifo_c_r != 2'd2) && + (!splitCtrl[8] || splitCtrl[15] || wsi_M1_reqFifo_c_r != 2'd2) && + wci_cState == 3'd2 ; + assign WILL_FIRE_RL_doMessageConsume_S1 = + CAN_FIRE_RL_doMessageConsume_S1 && + !WILL_FIRE_RL_doMessageConsume_S0 ; + + // rule RL_wci_cfwr + assign WILL_FIRE_RL_wci_cfwr = + wci_respF_c_r != 2'd2 && wci_reqF$EMPTY_N && + wci_wci_cfwr_pw$whas && + !WILL_FIRE_RL_wci_ctl_op_start && + !WILL_FIRE_RL_wci_ctl_op_complete ; + + // rule RL_wci_ctl_op_complete + assign WILL_FIRE_RL_wci_ctl_op_complete = + wci_respF_c_r != 2'd2 && wci_ctlOpActive && wci_ctlAckReg ; + + // rule RL_wsi_M0_reqFifo_deq + assign WILL_FIRE_RL_wsi_M0_reqFifo_deq = + wsi_M0_reqFifo_c_r != 2'd0 && !wsi_M0_sThreadBusy_d ; + + // rule RL_wsi_M0_reqFifo_incCtr + assign WILL_FIRE_RL_wsi_M0_reqFifo_incCtr = + ((wsi_M0_reqFifo_c_r == 2'd0) ? + wsi_M0_reqFifo_enqueueing$whas : + wsi_M0_reqFifo_c_r != 2'd1 || + wsi_M0_reqFifo_enqueueing$whas) && + wsi_M0_reqFifo_enqueueing$whas && + !WILL_FIRE_RL_wsi_M0_reqFifo_deq ; + + // rule RL_wsi_M0_reqFifo_decCtr + assign WILL_FIRE_RL_wsi_M0_reqFifo_decCtr = + WILL_FIRE_RL_wsi_M0_reqFifo_deq && + !wsi_M0_reqFifo_enqueueing$whas ; + + // rule RL_wsi_M0_reqFifo_both + assign WILL_FIRE_RL_wsi_M0_reqFifo_both = + ((wsi_M0_reqFifo_c_r == 2'd1) ? + wsi_M0_reqFifo_enqueueing$whas : + wsi_M0_reqFifo_c_r != 2'd2 || + wsi_M0_reqFifo_enqueueing$whas) && + WILL_FIRE_RL_wsi_M0_reqFifo_deq && + wsi_M0_reqFifo_enqueueing$whas ; + + // rule RL_wci_cfrd + assign WILL_FIRE_RL_wci_cfrd = + wci_respF_c_r != 2'd2 && wci_reqF$EMPTY_N && + wci_wci_cfrd_pw$whas && + !WILL_FIRE_RL_wci_ctl_op_start && + !WILL_FIRE_RL_wci_ctl_op_complete ; + + // rule RL_wci_respF_incCtr + assign WILL_FIRE_RL_wci_respF_incCtr = + ((wci_respF_c_r == 2'd0) ? + wci_respF_enqueueing$whas : + wci_respF_c_r != 2'd1 || wci_respF_enqueueing$whas) && + wci_respF_enqueueing$whas && + !(wci_respF_c_r != 2'd0) ; + + // rule RL_wci_respF_decCtr + assign WILL_FIRE_RL_wci_respF_decCtr = + wci_respF_c_r != 2'd0 && !wci_respF_enqueueing$whas ; + + // rule RL_wci_respF_both + assign WILL_FIRE_RL_wci_respF_both = + ((wci_respF_c_r == 2'd1) ? + wci_respF_enqueueing$whas : + wci_respF_c_r != 2'd2 || wci_respF_enqueueing$whas) && + wci_respF_c_r != 2'd0 && + wci_respF_enqueueing$whas ; + + // rule RL_wsi_M1_reqFifo_deq + assign WILL_FIRE_RL_wsi_M1_reqFifo_deq = + wsi_M1_reqFifo_c_r != 2'd0 && !wsi_M1_sThreadBusy_d ; + + // rule RL_wsi_M1_reqFifo_incCtr + assign WILL_FIRE_RL_wsi_M1_reqFifo_incCtr = + ((wsi_M1_reqFifo_c_r == 2'd0) ? + wsi_M1_reqFifo_enqueueing$whas : + wsi_M1_reqFifo_c_r != 2'd1 || + wsi_M1_reqFifo_enqueueing$whas) && + wsi_M1_reqFifo_enqueueing$whas && + !WILL_FIRE_RL_wsi_M1_reqFifo_deq ; + + // rule RL_wsi_M1_reqFifo_decCtr + assign WILL_FIRE_RL_wsi_M1_reqFifo_decCtr = + WILL_FIRE_RL_wsi_M1_reqFifo_deq && + !wsi_M1_reqFifo_enqueueing$whas ; + + // rule RL_wsi_M1_reqFifo_both + assign WILL_FIRE_RL_wsi_M1_reqFifo_both = + ((wsi_M1_reqFifo_c_r == 2'd1) ? + wsi_M1_reqFifo_enqueueing$whas : + wsi_M1_reqFifo_c_r != 2'd2 || + wsi_M1_reqFifo_enqueueing$whas) && + WILL_FIRE_RL_wsi_M1_reqFifo_deq && + wsi_M1_reqFifo_enqueueing$whas ; + + // rule RL_wsi_S0_reqFifo_enq + assign WILL_FIRE_RL_wsi_S0_reqFifo_enq = + wsi_S0_reqFifo$FULL_N && wsi_S0_operateD && wsi_S0_peerIsReady && + wsi_S0_wsiReq$wget[168:166] == 3'd1 ; + + // rule RL_wsi_S0_reqFifo_reset + assign WILL_FIRE_RL_wsi_S0_reqFifo_reset = + WILL_FIRE_RL_wsi_S0_reqFifo_enq || + WILL_FIRE_RL_doMessageConsume_S0 ; + + // rule RL_wsi_S1_reqFifo_enq + assign WILL_FIRE_RL_wsi_S1_reqFifo_enq = + wsi_S1_reqFifo$FULL_N && wsi_S1_operateD && wsi_S1_peerIsReady && + wsi_S1_wsiReq$wget[168:166] == 3'd1 ; + + // rule RL_wsi_S1_reqFifo_reset + assign WILL_FIRE_RL_wsi_S1_reqFifo_reset = + WILL_FIRE_RL_wsi_S1_reqFifo_enq || + WILL_FIRE_RL_doMessageConsume_S1 ; + + // inputs to muxes for submodule ports + assign MUX_wci_illegalEdge$write_1__SEL_1 = + WILL_FIRE_RL_wci_ctl_op_start && + (wci_reqF$D_OUT[36:34] == 3'd0 && wci_cState != 3'd0 || + wci_reqF$D_OUT[36:34] == 3'd1 && wci_cState != 3'd1 && + wci_cState != 3'd3 || + wci_reqF$D_OUT[36:34] == 3'd2 && wci_cState != 3'd2 || + wci_reqF$D_OUT[36:34] == 3'd3 && wci_cState != 3'd3 && + wci_cState != 3'd2 && + wci_cState != 3'd1 || + wci_reqF$D_OUT[36:34] == 3'd4 || + wci_reqF$D_OUT[36:34] == 3'd5 || + wci_reqF$D_OUT[36:34] == 3'd6 || + wci_reqF$D_OUT[36:34] == 3'd7) ; + assign MUX_wci_respF_q_0$write_1__SEL_2 = + WILL_FIRE_RL_wci_respF_incCtr && wci_respF_c_r == 2'd0 ; + assign MUX_wci_respF_q_1$write_1__SEL_2 = + WILL_FIRE_RL_wci_respF_incCtr && wci_respF_c_r == 2'd1 ; + assign MUX_wsi_M0_reqFifo_q_0$write_1__SEL_2 = + WILL_FIRE_RL_wsi_M0_reqFifo_incCtr && + wsi_M0_reqFifo_c_r == 2'd0 ; + assign MUX_wsi_M0_reqFifo_q_1$write_1__SEL_2 = + WILL_FIRE_RL_wsi_M0_reqFifo_incCtr && + wsi_M0_reqFifo_c_r == 2'd1 ; + assign MUX_wsi_M0_reqFifo_x_wire$wset_1__SEL_1 = + WILL_FIRE_RL_doMessageConsume_S0 && !splitCtrl[0] && + !splitCtrl[7] ; + assign MUX_wsi_M1_reqFifo_q_0$write_1__SEL_2 = + WILL_FIRE_RL_wsi_M1_reqFifo_incCtr && + wsi_M1_reqFifo_c_r == 2'd0 ; + assign MUX_wsi_M1_reqFifo_q_1$write_1__SEL_2 = + WILL_FIRE_RL_wsi_M1_reqFifo_incCtr && + wsi_M1_reqFifo_c_r == 2'd1 ; + assign MUX_wsi_M1_reqFifo_x_wire$wset_1__SEL_1 = + WILL_FIRE_RL_doMessageConsume_S0 && !splitCtrl[8] && + !splitCtrl[15] ; + assign MUX_wci_illegalEdge$write_1__VAL_1 = + wci_reqF$D_OUT[36:34] != 3'd4 && wci_reqF$D_OUT[36:34] != 3'd5 && + wci_reqF$D_OUT[36:34] != 3'd6 ; + assign MUX_wci_respF_c_r$write_1__VAL_1 = wci_respF_c_r + 2'd1 ; + assign MUX_wci_respF_c_r$write_1__VAL_2 = wci_respF_c_r - 2'd1 ; + assign MUX_wci_respF_q_0$write_1__VAL_1 = + (wci_respF_c_r == 2'd1) ? + MUX_wci_respF_q_0$write_1__VAL_2 : + wci_respF_q_1 ; + always@(WILL_FIRE_RL_wci_ctl_op_complete or + MUX_wci_respF_x_wire$wset_1__VAL_1 or + WILL_FIRE_RL_wci_cfrd or + MUX_wci_respF_x_wire$wset_1__VAL_2 or WILL_FIRE_RL_wci_cfwr) + begin + case (1'b1) // synopsys parallel_case + WILL_FIRE_RL_wci_ctl_op_complete: + MUX_wci_respF_q_0$write_1__VAL_2 = + MUX_wci_respF_x_wire$wset_1__VAL_1; + WILL_FIRE_RL_wci_cfrd: + MUX_wci_respF_q_0$write_1__VAL_2 = + MUX_wci_respF_x_wire$wset_1__VAL_2; + WILL_FIRE_RL_wci_cfwr: MUX_wci_respF_q_0$write_1__VAL_2 = 34'h1C0DE4201; + default: MUX_wci_respF_q_0$write_1__VAL_2 = + 34'h2AAAAAAAA /* unspecified value */ ; + endcase + end + assign MUX_wci_respF_q_1$write_1__VAL_1 = + (wci_respF_c_r == 2'd2) ? + MUX_wci_respF_q_0$write_1__VAL_2 : + 34'h0AAAAAAAA ; + assign MUX_wci_respF_x_wire$wset_1__VAL_1 = + wci_illegalEdge ? 34'h3C0DE4202 : 34'h1C0DE4201 ; + assign MUX_wci_respF_x_wire$wset_1__VAL_2 = { 2'd1, _theResult____h16428 } ; + assign MUX_wsi_M0_reqFifo_c_r$write_1__VAL_1 = wsi_M0_reqFifo_c_r + 2'd1 ; + assign MUX_wsi_M0_reqFifo_c_r$write_1__VAL_2 = wsi_M0_reqFifo_c_r - 2'd1 ; + assign MUX_wsi_M0_reqFifo_q_0$write_1__VAL_1 = + (wsi_M0_reqFifo_c_r == 2'd1) ? + MUX_wsi_M0_reqFifo_q_0$write_1__VAL_2 : + wsi_M0_reqFifo_q_1 ; + assign MUX_wsi_M0_reqFifo_q_0$write_1__VAL_2 = + MUX_wsi_M0_reqFifo_x_wire$wset_1__SEL_1 ? + wsi_S0_reqFifo$D_OUT : + wsi_S1_reqFifo$D_OUT ; + assign MUX_wsi_M0_reqFifo_q_1$write_1__VAL_1 = + (wsi_M0_reqFifo_c_r == 2'd2) ? + MUX_wsi_M0_reqFifo_q_0$write_1__VAL_2 : + 169'h00000AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA00 ; + assign MUX_wsi_M1_reqFifo_c_r$write_1__VAL_1 = wsi_M1_reqFifo_c_r + 2'd1 ; + assign MUX_wsi_M1_reqFifo_c_r$write_1__VAL_2 = wsi_M1_reqFifo_c_r - 2'd1 ; + assign MUX_wsi_M1_reqFifo_q_0$write_1__VAL_1 = + (wsi_M1_reqFifo_c_r == 2'd1) ? + MUX_wsi_M1_reqFifo_q_0$write_1__VAL_2 : + wsi_M1_reqFifo_q_1 ; + assign MUX_wsi_M1_reqFifo_q_0$write_1__VAL_2 = + MUX_wsi_M1_reqFifo_x_wire$wset_1__SEL_1 ? + wsi_S0_reqFifo$D_OUT : + wsi_S1_reqFifo$D_OUT ; + assign MUX_wsi_M1_reqFifo_q_1$write_1__VAL_1 = + (wsi_M1_reqFifo_c_r == 2'd2) ? + MUX_wsi_M1_reqFifo_q_0$write_1__VAL_2 : + 169'h00000AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA00 ; + + // inlined wires + assign wci_wciReq$wget = + { wciS0_MCmd, + wciS0_MAddrSpace, + wciS0_MByteEn, + wciS0_MAddr, + wciS0_MData } ; + assign wci_wciReq$whas = 1'd1 ; + assign wci_respF_x_wire$wget = MUX_wci_respF_q_0$write_1__VAL_2 ; + assign wci_respF_x_wire$whas = wci_respF_enqueueing$whas ; + assign wci_wEdge$wget = wci_reqF$D_OUT[36:34] ; + assign wci_wEdge$whas = WILL_FIRE_RL_wci_ctl_op_start ; + assign wci_sFlagReg_1$wget = 1'b0 ; + assign wci_sFlagReg_1$whas = 1'b0 ; + assign wci_ctlAckReg_1$wget = 1'd1 ; + assign wci_ctlAckReg_1$whas = + WILL_FIRE_RL_wci_ctrl_OrE || WILL_FIRE_RL_wci_ctrl_IsO || + WILL_FIRE_RL_wci_ctrl_EiI ; + assign wsi_S0_wsiReq$wget = + { wsiS0_MCmd, + wsiS0_MReqLast, + wsiS0_MBurstPrecise, + wsiS0_MBurstLength, + wsiS0_MData, + wsiS0_MByteEn, + wsiS0_MReqInfo } ; + assign wsi_S0_wsiReq$whas = 1'd1 ; + assign wsi_S0_operateD_1$wget = 1'd1 ; + assign wsi_S0_operateD_1$whas = wci_cState == 3'd2 ; + assign wsi_S0_peerIsReady_1$wget = 1'd1 ; + assign wsi_S0_peerIsReady_1$whas = wsiS0_MReset_n ; + assign wsi_S0_sThreadBusy_dw$wget = wsi_S0_reqFifo_countReg > 2'd1 ; + assign wsi_S0_sThreadBusy_dw$whas = + wsi_S0_reqFifo_levelsValid && wsi_S0_operateD && + wsi_S0_peerIsReady ; + assign wsi_S1_wsiReq$wget = + { wsiS1_MCmd, + wsiS1_MReqLast, + wsiS1_MBurstPrecise, + wsiS1_MBurstLength, + wsiS1_MData, + wsiS1_MByteEn, + wsiS1_MReqInfo } ; + assign wsi_S1_wsiReq$whas = 1'd1 ; + assign wsi_S1_operateD_1$wget = 1'd1 ; + assign wsi_S1_operateD_1$whas = wci_cState == 3'd2 ; + assign wsi_S1_peerIsReady_1$wget = 1'd1 ; + assign wsi_S1_peerIsReady_1$whas = wsiS1_MReset_n ; + assign wsi_S1_sThreadBusy_dw$wget = wsi_S1_reqFifo_countReg > 2'd1 ; + assign wsi_S1_sThreadBusy_dw$whas = + wsi_S1_reqFifo_levelsValid && wsi_S1_operateD && + wsi_S1_peerIsReady ; + assign wsi_M0_reqFifo_x_wire$wget = MUX_wsi_M0_reqFifo_q_0$write_1__VAL_2 ; + assign wsi_M0_reqFifo_x_wire$whas = wsi_M0_reqFifo_enqueueing$whas ; + assign wsi_M0_operateD_1$wget = 1'd1 ; + assign wsi_M0_operateD_1$whas = wci_cState == 3'd2 ; + assign wsi_M0_peerIsReady_1$wget = 1'd1 ; + assign wsi_M0_peerIsReady_1$whas = wsiM0_SReset_n ; + assign wsi_M1_reqFifo_x_wire$wget = MUX_wsi_M1_reqFifo_q_0$write_1__VAL_2 ; + assign wsi_M1_reqFifo_x_wire$whas = wsi_M1_reqFifo_enqueueing$whas ; + assign wsi_M1_operateD_1$wget = 1'd1 ; + assign wsi_M1_operateD_1$whas = wci_cState == 3'd2 ; + assign wsi_M1_peerIsReady_1$wget = 1'd1 ; + assign wsi_M1_peerIsReady_1$whas = wsiM1_SReset_n ; + assign wci_Es_mCmd_w$wget = wciS0_MCmd ; + assign wci_Es_mCmd_w$whas = 1'd1 ; + assign wci_Es_mAddrSpace_w$wget = wciS0_MAddrSpace ; + assign wci_Es_mAddrSpace_w$whas = 1'd1 ; + assign wci_Es_mByteEn_w$wget = wciS0_MByteEn ; + assign wci_Es_mByteEn_w$whas = 1'd1 ; + assign wci_Es_mAddr_w$wget = wciS0_MAddr ; + assign wci_Es_mAddr_w$whas = 1'd1 ; + assign wci_Es_mData_w$wget = wciS0_MData ; + assign wci_Es_mData_w$whas = 1'd1 ; + assign wsi_Es0_mCmd_w$wget = wsiS0_MCmd ; + assign wsi_Es0_mCmd_w$whas = 1'd1 ; + assign wsi_Es0_mBurstLength_w$wget = wsiS0_MBurstLength ; + assign wsi_Es0_mBurstLength_w$whas = 1'd1 ; + assign wsi_Es0_mData_w$wget = wsiS0_MData ; + assign wsi_Es0_mData_w$whas = 1'd1 ; + assign wsi_Es0_mByteEn_w$wget = wsiS0_MByteEn ; + assign wsi_Es0_mByteEn_w$whas = 1'd1 ; + assign wsi_Es0_mReqInfo_w$wget = wsiS0_MReqInfo ; + assign wsi_Es0_mReqInfo_w$whas = 1'd1 ; + assign wsi_Es1_mCmd_w$wget = wsiS1_MCmd ; + assign wsi_Es1_mCmd_w$whas = 1'd1 ; + assign wsi_Es1_mBurstLength_w$wget = wsiS1_MBurstLength ; + assign wsi_Es1_mBurstLength_w$whas = 1'd1 ; + assign wsi_Es1_mData_w$wget = wsiS1_MData ; + assign wsi_Es1_mData_w$whas = 1'd1 ; + assign wsi_Es1_mByteEn_w$wget = wsiS1_MByteEn ; + assign wsi_Es1_mByteEn_w$whas = 1'd1 ; + assign wsi_Es1_mReqInfo_w$wget = wsiS1_MReqInfo ; + assign wsi_Es1_mReqInfo_w$whas = 1'd1 ; + assign wci_reqF_r_enq$whas = wci_wciReq$wget[71:69] != 3'd0 ; + assign wci_reqF_r_deq$whas = + WILL_FIRE_RL_wci_ctl_op_start || WILL_FIRE_RL_wci_cfrd || + WILL_FIRE_RL_wci_cfwr ; + assign wci_reqF_r_clr$whas = 1'b0 ; + assign wci_respF_enqueueing$whas = + WILL_FIRE_RL_wci_ctl_op_complete || WILL_FIRE_RL_wci_cfrd || + WILL_FIRE_RL_wci_cfwr ; + assign wci_respF_dequeueing$whas = wci_respF_c_r != 2'd0 ; + assign wci_sThreadBusy_pw$whas = 1'b0 ; + assign wci_wci_cfwr_pw$whas = + wci_reqF$EMPTY_N && wci_reqF$D_OUT[68] && + wci_reqF$D_OUT[71:69] == 3'd1 ; + assign wci_wci_cfrd_pw$whas = + wci_reqF$EMPTY_N && wci_reqF$D_OUT[68] && + wci_reqF$D_OUT[71:69] == 3'd2 ; + assign wci_wci_ctrl_pw$whas = + wci_reqF$EMPTY_N && !wci_reqF$D_OUT[68] && + wci_reqF$D_OUT[71:69] == 3'd2 ; + assign wsi_S0_reqFifo_r_enq$whas = WILL_FIRE_RL_wsi_S0_reqFifo_enq ; + assign wsi_S0_reqFifo_r_deq$whas = WILL_FIRE_RL_doMessageConsume_S0 ; + assign wsi_S0_reqFifo_r_clr$whas = 1'b0 ; + assign wsi_S0_reqFifo_doResetEnq$whas = WILL_FIRE_RL_wsi_S0_reqFifo_enq ; + assign wsi_S0_reqFifo_doResetDeq$whas = WILL_FIRE_RL_doMessageConsume_S0 ; + assign wsi_S0_reqFifo_doResetClr$whas = 1'b0 ; + assign wsi_S1_reqFifo_r_enq$whas = WILL_FIRE_RL_wsi_S1_reqFifo_enq ; + assign wsi_S1_reqFifo_r_deq$whas = WILL_FIRE_RL_doMessageConsume_S1 ; + assign wsi_S1_reqFifo_r_clr$whas = 1'b0 ; + assign wsi_S1_reqFifo_doResetEnq$whas = WILL_FIRE_RL_wsi_S1_reqFifo_enq ; + assign wsi_S1_reqFifo_doResetDeq$whas = WILL_FIRE_RL_doMessageConsume_S1 ; + assign wsi_S1_reqFifo_doResetClr$whas = 1'b0 ; + assign wsi_M0_reqFifo_enqueueing$whas = + WILL_FIRE_RL_doMessageConsume_S0 && !splitCtrl[0] && + !splitCtrl[7] || + WILL_FIRE_RL_doMessageConsume_S1 && splitCtrl[0] && + !splitCtrl[7] ; + assign wsi_M0_reqFifo_dequeueing$whas = WILL_FIRE_RL_wsi_M0_reqFifo_deq ; + assign wsi_M0_sThreadBusy_pw$whas = wsiM0_SThreadBusy ; + assign wsi_M1_reqFifo_enqueueing$whas = + WILL_FIRE_RL_doMessageConsume_S0 && !splitCtrl[8] && + !splitCtrl[15] || + WILL_FIRE_RL_doMessageConsume_S1 && splitCtrl[8] && + !splitCtrl[15] ; + assign wsi_M1_reqFifo_dequeueing$whas = WILL_FIRE_RL_wsi_M1_reqFifo_deq ; + assign wsi_M1_sThreadBusy_pw$whas = wsiM1_SThreadBusy ; + assign wsi_Es0_mReqLast_w$whas = wsiS0_MReqLast ; + assign wsi_Es0_mBurstPrecise_w$whas = wsiS0_MBurstPrecise ; + assign wsi_Es0_mDataInfo_w$whas = 1'd1 ; + assign wsi_Es1_mReqLast_w$whas = wsiS1_MReqLast ; + assign wsi_Es1_mBurstPrecise_w$whas = wsiS1_MBurstPrecise ; + assign wsi_Es1_mDataInfo_w$whas = 1'd1 ; + assign wsi_S0_extStatusW$wget = + { wsi_S0_pMesgCount, wsi_S0_iMesgCount, wsi_S0_tBusyCount } ; + assign wsi_S1_extStatusW$wget = + { wsi_S1_pMesgCount, wsi_S1_iMesgCount, wsi_S1_tBusyCount } ; + assign wsi_M0_extStatusW$wget = + { wsi_M0_pMesgCount, wsi_M0_iMesgCount, wsi_M0_tBusyCount } ; + assign wsi_M1_extStatusW$wget = + { wsi_M1_pMesgCount, wsi_M1_iMesgCount, wsi_M1_tBusyCount } ; + + // register splitCtrl + assign splitCtrl$D_IN = wci_reqF$D_OUT[31:0] ; + assign splitCtrl$EN = + WILL_FIRE_RL_wci_cfwr && wci_reqF$D_OUT[39:32] == 8'h04 ; + + // register wci_cEdge + assign wci_cEdge$D_IN = wci_reqF$D_OUT[36:34] ; + assign wci_cEdge$EN = WILL_FIRE_RL_wci_ctl_op_start ; + + // register wci_cState + assign wci_cState$D_IN = wci_nState ; + assign wci_cState$EN = + WILL_FIRE_RL_wci_ctl_op_complete && !wci_illegalEdge ; + + // register wci_ctlAckReg + assign wci_ctlAckReg$D_IN = wci_ctlAckReg_1$whas ; + assign wci_ctlAckReg$EN = 1'd1 ; + + // register wci_ctlOpActive + assign wci_ctlOpActive$D_IN = !WILL_FIRE_RL_wci_ctl_op_complete ; + assign wci_ctlOpActive$EN = + WILL_FIRE_RL_wci_ctl_op_complete || + WILL_FIRE_RL_wci_ctl_op_start ; + + // register wci_illegalEdge + assign wci_illegalEdge$D_IN = + MUX_wci_illegalEdge$write_1__SEL_1 && + MUX_wci_illegalEdge$write_1__VAL_1 ; + assign wci_illegalEdge$EN = + MUX_wci_illegalEdge$write_1__SEL_1 || + WILL_FIRE_RL_wci_ctl_op_complete && wci_illegalEdge ; + + // register wci_isReset_isInReset + assign wci_isReset_isInReset$D_IN = 1'd0 ; + assign wci_isReset_isInReset$EN = wci_isReset_isInReset ; + + // register wci_nState + always@(wci_reqF$D_OUT) + begin + case (wci_reqF$D_OUT[36:34]) + 3'd0: wci_nState$D_IN = 3'd1; + 3'd1: wci_nState$D_IN = 3'd2; + 3'd2: wci_nState$D_IN = 3'd3; + default: wci_nState$D_IN = 3'd0; + endcase + end + assign wci_nState$EN = + WILL_FIRE_RL_wci_ctl_op_start && + (wci_reqF$D_OUT[36:34] == 3'd0 && wci_cState == 3'd0 || + wci_reqF$D_OUT[36:34] == 3'd1 && + (wci_cState == 3'd1 || wci_cState == 3'd3) || + wci_reqF$D_OUT[36:34] == 3'd2 && wci_cState == 3'd2 || + wci_reqF$D_OUT[36:34] == 3'd3 && + (wci_cState == 3'd3 || wci_cState == 3'd2 || + wci_cState == 3'd1)) ; + + // register wci_reqF_countReg + assign wci_reqF_countReg$D_IN = + (wci_wciReq$wget[71:69] != 3'd0) ? + wci_reqF_countReg + 2'd1 : + wci_reqF_countReg - 2'd1 ; + assign wci_reqF_countReg$EN = + (wci_wciReq$wget[71:69] != 3'd0) != wci_reqF_r_deq$whas ; + + // register wci_respF_c_r + assign wci_respF_c_r$D_IN = + WILL_FIRE_RL_wci_respF_incCtr ? + MUX_wci_respF_c_r$write_1__VAL_1 : + MUX_wci_respF_c_r$write_1__VAL_2 ; + assign wci_respF_c_r$EN = + WILL_FIRE_RL_wci_respF_incCtr || WILL_FIRE_RL_wci_respF_decCtr ; + + // register wci_respF_q_0 + always@(WILL_FIRE_RL_wci_respF_both or + MUX_wci_respF_q_0$write_1__VAL_1 or + MUX_wci_respF_q_0$write_1__SEL_2 or + MUX_wci_respF_q_0$write_1__VAL_2 or + WILL_FIRE_RL_wci_respF_decCtr or wci_respF_q_1) + begin + case (1'b1) // synopsys parallel_case + WILL_FIRE_RL_wci_respF_both: + wci_respF_q_0$D_IN = MUX_wci_respF_q_0$write_1__VAL_1; + MUX_wci_respF_q_0$write_1__SEL_2: + wci_respF_q_0$D_IN = MUX_wci_respF_q_0$write_1__VAL_2; + WILL_FIRE_RL_wci_respF_decCtr: wci_respF_q_0$D_IN = wci_respF_q_1; + default: wci_respF_q_0$D_IN = 34'h2AAAAAAAA /* unspecified value */ ; + endcase + end + assign wci_respF_q_0$EN = + WILL_FIRE_RL_wci_respF_both || + WILL_FIRE_RL_wci_respF_incCtr && wci_respF_c_r == 2'd0 || + WILL_FIRE_RL_wci_respF_decCtr ; + + // register wci_respF_q_1 + always@(WILL_FIRE_RL_wci_respF_both or + MUX_wci_respF_q_1$write_1__VAL_1 or + MUX_wci_respF_q_1$write_1__SEL_2 or + MUX_wci_respF_q_0$write_1__VAL_2 or WILL_FIRE_RL_wci_respF_decCtr) + begin + case (1'b1) // synopsys parallel_case + WILL_FIRE_RL_wci_respF_both: + wci_respF_q_1$D_IN = MUX_wci_respF_q_1$write_1__VAL_1; + MUX_wci_respF_q_1$write_1__SEL_2: + wci_respF_q_1$D_IN = MUX_wci_respF_q_0$write_1__VAL_2; + WILL_FIRE_RL_wci_respF_decCtr: wci_respF_q_1$D_IN = 34'h0AAAAAAAA; + default: wci_respF_q_1$D_IN = 34'h2AAAAAAAA /* unspecified value */ ; + endcase + end + assign wci_respF_q_1$EN = + WILL_FIRE_RL_wci_respF_both || + WILL_FIRE_RL_wci_respF_incCtr && wci_respF_c_r == 2'd1 || + WILL_FIRE_RL_wci_respF_decCtr ; + + // register wci_sFlagReg + assign wci_sFlagReg$D_IN = 1'b0 ; + assign wci_sFlagReg$EN = 1'd1 ; + + // register wci_sThreadBusy_d + assign wci_sThreadBusy_d$D_IN = 1'b0 ; + assign wci_sThreadBusy_d$EN = 1'd1 ; + + // register wsi_M0_burstKind + assign wsi_M0_burstKind$D_IN = + (wsi_M0_burstKind == 2'd0) ? + (wsi_M0_reqFifo_q_0[164] ? 2'd1 : 2'd2) : + 2'd0 ; + assign wsi_M0_burstKind$EN = + WILL_FIRE_RL_wsi_M0_reqFifo_deq && + wsi_M0_reqFifo_q_0[168:166] == 3'd1 && + (wsi_M0_burstKind == 2'd0 || + (wsi_M0_burstKind == 2'd1 || wsi_M0_burstKind == 2'd2) && + wsi_M0_reqFifo_q_0[165]) ; + + // register wsi_M0_errorSticky + assign wsi_M0_errorSticky$D_IN = 1'b0 ; + assign wsi_M0_errorSticky$EN = 1'b0 ; + + // register wsi_M0_iMesgCount + assign wsi_M0_iMesgCount$D_IN = wsi_M0_iMesgCount + 32'd1 ; + assign wsi_M0_iMesgCount$EN = + WILL_FIRE_RL_wsi_M0_reqFifo_deq && + wsi_M0_reqFifo_q_0[168:166] == 3'd1 && + wsi_M0_burstKind == 2'd2 && + wsi_M0_reqFifo_q_0[165] ; + + // register wsi_M0_isReset_isInReset + assign wsi_M0_isReset_isInReset$D_IN = 1'd0 ; + assign wsi_M0_isReset_isInReset$EN = wsi_M0_isReset_isInReset ; + + // register wsi_M0_operateD + assign wsi_M0_operateD$D_IN = wci_cState == 3'd2 ; + assign wsi_M0_operateD$EN = 1'd1 ; + + // register wsi_M0_pMesgCount + assign wsi_M0_pMesgCount$D_IN = wsi_M0_pMesgCount + 32'd1 ; + assign wsi_M0_pMesgCount$EN = + WILL_FIRE_RL_wsi_M0_reqFifo_deq && + wsi_M0_reqFifo_q_0[168:166] == 3'd1 && + wsi_M0_burstKind == 2'd1 && + wsi_M0_reqFifo_q_0[165] ; + + // register wsi_M0_peerIsReady + assign wsi_M0_peerIsReady$D_IN = wsiM0_SReset_n ; + assign wsi_M0_peerIsReady$EN = 1'd1 ; + + // register wsi_M0_reqFifo_c_r + assign wsi_M0_reqFifo_c_r$D_IN = + WILL_FIRE_RL_wsi_M0_reqFifo_incCtr ? + MUX_wsi_M0_reqFifo_c_r$write_1__VAL_1 : + MUX_wsi_M0_reqFifo_c_r$write_1__VAL_2 ; + assign wsi_M0_reqFifo_c_r$EN = + WILL_FIRE_RL_wsi_M0_reqFifo_incCtr || + WILL_FIRE_RL_wsi_M0_reqFifo_decCtr ; + + // register wsi_M0_reqFifo_q_0 + always@(WILL_FIRE_RL_wsi_M0_reqFifo_both or + MUX_wsi_M0_reqFifo_q_0$write_1__VAL_1 or + MUX_wsi_M0_reqFifo_q_0$write_1__SEL_2 or + MUX_wsi_M0_reqFifo_q_0$write_1__VAL_2 or + WILL_FIRE_RL_wsi_M0_reqFifo_decCtr or wsi_M0_reqFifo_q_1) + begin + case (1'b1) // synopsys parallel_case + WILL_FIRE_RL_wsi_M0_reqFifo_both: + wsi_M0_reqFifo_q_0$D_IN = MUX_wsi_M0_reqFifo_q_0$write_1__VAL_1; + MUX_wsi_M0_reqFifo_q_0$write_1__SEL_2: + wsi_M0_reqFifo_q_0$D_IN = MUX_wsi_M0_reqFifo_q_0$write_1__VAL_2; + WILL_FIRE_RL_wsi_M0_reqFifo_decCtr: + wsi_M0_reqFifo_q_0$D_IN = wsi_M0_reqFifo_q_1; + default: wsi_M0_reqFifo_q_0$D_IN = + 169'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ; + endcase + end + assign wsi_M0_reqFifo_q_0$EN = + WILL_FIRE_RL_wsi_M0_reqFifo_both || + WILL_FIRE_RL_wsi_M0_reqFifo_incCtr && + wsi_M0_reqFifo_c_r == 2'd0 || + WILL_FIRE_RL_wsi_M0_reqFifo_decCtr ; + + // register wsi_M0_reqFifo_q_1 + always@(WILL_FIRE_RL_wsi_M0_reqFifo_both or + MUX_wsi_M0_reqFifo_q_1$write_1__VAL_1 or + MUX_wsi_M0_reqFifo_q_1$write_1__SEL_2 or + MUX_wsi_M0_reqFifo_q_0$write_1__VAL_2 or + WILL_FIRE_RL_wsi_M0_reqFifo_decCtr) + begin + case (1'b1) // synopsys parallel_case + WILL_FIRE_RL_wsi_M0_reqFifo_both: + wsi_M0_reqFifo_q_1$D_IN = MUX_wsi_M0_reqFifo_q_1$write_1__VAL_1; + MUX_wsi_M0_reqFifo_q_1$write_1__SEL_2: + wsi_M0_reqFifo_q_1$D_IN = MUX_wsi_M0_reqFifo_q_0$write_1__VAL_2; + WILL_FIRE_RL_wsi_M0_reqFifo_decCtr: + wsi_M0_reqFifo_q_1$D_IN = + 169'h00000AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA00; + default: wsi_M0_reqFifo_q_1$D_IN = + 169'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ; + endcase + end + assign wsi_M0_reqFifo_q_1$EN = + WILL_FIRE_RL_wsi_M0_reqFifo_both || + WILL_FIRE_RL_wsi_M0_reqFifo_incCtr && + wsi_M0_reqFifo_c_r == 2'd1 || + WILL_FIRE_RL_wsi_M0_reqFifo_decCtr ; + + // register wsi_M0_sThreadBusy_d + assign wsi_M0_sThreadBusy_d$D_IN = wsiM0_SThreadBusy ; + assign wsi_M0_sThreadBusy_d$EN = 1'd1 ; + + // register wsi_M0_statusR + assign wsi_M0_statusR$D_IN = + { wsi_M0_isReset_isInReset, + !wsi_M0_peerIsReady, + !wsi_M0_operateD, + wsi_M0_errorSticky, + wsi_M0_burstKind != 2'd0, + wsi_M0_sThreadBusy_d, + 1'd0, + wsi_M0_trafficSticky } ; + assign wsi_M0_statusR$EN = 1'd1 ; + + // register wsi_M0_tBusyCount + assign wsi_M0_tBusyCount$D_IN = wsi_M0_tBusyCount + 32'd1 ; + assign wsi_M0_tBusyCount$EN = + wsi_M0_operateD && wsi_M0_peerIsReady && wsi_M0_sThreadBusy_d ; + + // register wsi_M0_trafficSticky + assign wsi_M0_trafficSticky$D_IN = 1'd1 ; + assign wsi_M0_trafficSticky$EN = + WILL_FIRE_RL_wsi_M0_reqFifo_deq && + wsi_M0_reqFifo_q_0[168:166] == 3'd1 ; + + // register wsi_M1_burstKind + assign wsi_M1_burstKind$D_IN = + (wsi_M1_burstKind == 2'd0) ? + (wsi_M1_reqFifo_q_0[164] ? 2'd1 : 2'd2) : + 2'd0 ; + assign wsi_M1_burstKind$EN = + WILL_FIRE_RL_wsi_M1_reqFifo_deq && + wsi_M1_reqFifo_q_0[168:166] == 3'd1 && + (wsi_M1_burstKind == 2'd0 || + (wsi_M1_burstKind == 2'd1 || wsi_M1_burstKind == 2'd2) && + wsi_M1_reqFifo_q_0[165]) ; + + // register wsi_M1_errorSticky + assign wsi_M1_errorSticky$D_IN = 1'b0 ; + assign wsi_M1_errorSticky$EN = 1'b0 ; + + // register wsi_M1_iMesgCount + assign wsi_M1_iMesgCount$D_IN = wsi_M1_iMesgCount + 32'd1 ; + assign wsi_M1_iMesgCount$EN = + WILL_FIRE_RL_wsi_M1_reqFifo_deq && + wsi_M1_reqFifo_q_0[168:166] == 3'd1 && + wsi_M1_burstKind == 2'd2 && + wsi_M1_reqFifo_q_0[165] ; + + // register wsi_M1_isReset_isInReset + assign wsi_M1_isReset_isInReset$D_IN = 1'd0 ; + assign wsi_M1_isReset_isInReset$EN = wsi_M1_isReset_isInReset ; + + // register wsi_M1_operateD + assign wsi_M1_operateD$D_IN = wci_cState == 3'd2 ; + assign wsi_M1_operateD$EN = 1'd1 ; + + // register wsi_M1_pMesgCount + assign wsi_M1_pMesgCount$D_IN = wsi_M1_pMesgCount + 32'd1 ; + assign wsi_M1_pMesgCount$EN = + WILL_FIRE_RL_wsi_M1_reqFifo_deq && + wsi_M1_reqFifo_q_0[168:166] == 3'd1 && + wsi_M1_burstKind == 2'd1 && + wsi_M1_reqFifo_q_0[165] ; + + // register wsi_M1_peerIsReady + assign wsi_M1_peerIsReady$D_IN = wsiM1_SReset_n ; + assign wsi_M1_peerIsReady$EN = 1'd1 ; + + // register wsi_M1_reqFifo_c_r + assign wsi_M1_reqFifo_c_r$D_IN = + WILL_FIRE_RL_wsi_M1_reqFifo_incCtr ? + MUX_wsi_M1_reqFifo_c_r$write_1__VAL_1 : + MUX_wsi_M1_reqFifo_c_r$write_1__VAL_2 ; + assign wsi_M1_reqFifo_c_r$EN = + WILL_FIRE_RL_wsi_M1_reqFifo_incCtr || + WILL_FIRE_RL_wsi_M1_reqFifo_decCtr ; + + // register wsi_M1_reqFifo_q_0 + always@(WILL_FIRE_RL_wsi_M1_reqFifo_both or + MUX_wsi_M1_reqFifo_q_0$write_1__VAL_1 or + MUX_wsi_M1_reqFifo_q_0$write_1__SEL_2 or + MUX_wsi_M1_reqFifo_q_0$write_1__VAL_2 or + WILL_FIRE_RL_wsi_M1_reqFifo_decCtr or wsi_M1_reqFifo_q_1) + begin + case (1'b1) // synopsys parallel_case + WILL_FIRE_RL_wsi_M1_reqFifo_both: + wsi_M1_reqFifo_q_0$D_IN = MUX_wsi_M1_reqFifo_q_0$write_1__VAL_1; + MUX_wsi_M1_reqFifo_q_0$write_1__SEL_2: + wsi_M1_reqFifo_q_0$D_IN = MUX_wsi_M1_reqFifo_q_0$write_1__VAL_2; + WILL_FIRE_RL_wsi_M1_reqFifo_decCtr: + wsi_M1_reqFifo_q_0$D_IN = wsi_M1_reqFifo_q_1; + default: wsi_M1_reqFifo_q_0$D_IN = + 169'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ; + endcase + end + assign wsi_M1_reqFifo_q_0$EN = + WILL_FIRE_RL_wsi_M1_reqFifo_both || + WILL_FIRE_RL_wsi_M1_reqFifo_incCtr && + wsi_M1_reqFifo_c_r == 2'd0 || + WILL_FIRE_RL_wsi_M1_reqFifo_decCtr ; + + // register wsi_M1_reqFifo_q_1 + always@(WILL_FIRE_RL_wsi_M1_reqFifo_both or + MUX_wsi_M1_reqFifo_q_1$write_1__VAL_1 or + MUX_wsi_M1_reqFifo_q_1$write_1__SEL_2 or + MUX_wsi_M1_reqFifo_q_0$write_1__VAL_2 or + WILL_FIRE_RL_wsi_M1_reqFifo_decCtr) + begin + case (1'b1) // synopsys parallel_case + WILL_FIRE_RL_wsi_M1_reqFifo_both: + wsi_M1_reqFifo_q_1$D_IN = MUX_wsi_M1_reqFifo_q_1$write_1__VAL_1; + MUX_wsi_M1_reqFifo_q_1$write_1__SEL_2: + wsi_M1_reqFifo_q_1$D_IN = MUX_wsi_M1_reqFifo_q_0$write_1__VAL_2; + WILL_FIRE_RL_wsi_M1_reqFifo_decCtr: + wsi_M1_reqFifo_q_1$D_IN = + 169'h00000AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA00; + default: wsi_M1_reqFifo_q_1$D_IN = + 169'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ; + endcase + end + assign wsi_M1_reqFifo_q_1$EN = + WILL_FIRE_RL_wsi_M1_reqFifo_both || + WILL_FIRE_RL_wsi_M1_reqFifo_incCtr && + wsi_M1_reqFifo_c_r == 2'd1 || + WILL_FIRE_RL_wsi_M1_reqFifo_decCtr ; + + // register wsi_M1_sThreadBusy_d + assign wsi_M1_sThreadBusy_d$D_IN = wsiM1_SThreadBusy ; + assign wsi_M1_sThreadBusy_d$EN = 1'd1 ; + + // register wsi_M1_statusR + assign wsi_M1_statusR$D_IN = + { wsi_M1_isReset_isInReset, + !wsi_M1_peerIsReady, + !wsi_M1_operateD, + wsi_M1_errorSticky, + wsi_M1_burstKind != 2'd0, + wsi_M1_sThreadBusy_d, + 1'd0, + wsi_M1_trafficSticky } ; + assign wsi_M1_statusR$EN = 1'd1 ; + + // register wsi_M1_tBusyCount + assign wsi_M1_tBusyCount$D_IN = wsi_M1_tBusyCount + 32'd1 ; + assign wsi_M1_tBusyCount$EN = + wsi_M1_operateD && wsi_M1_peerIsReady && wsi_M1_sThreadBusy_d ; + + // register wsi_M1_trafficSticky + assign wsi_M1_trafficSticky$D_IN = 1'd1 ; + assign wsi_M1_trafficSticky$EN = + WILL_FIRE_RL_wsi_M1_reqFifo_deq && + wsi_M1_reqFifo_q_0[168:166] == 3'd1 ; + + // register wsi_S0_burstKind + assign wsi_S0_burstKind$D_IN = + (wsi_S0_burstKind == 2'd0) ? + (wsi_S0_wsiReq$wget[164] ? 2'd1 : 2'd2) : + 2'd0 ; + assign wsi_S0_burstKind$EN = + WILL_FIRE_RL_wsi_S0_reqFifo_enq && + (wsi_S0_burstKind == 2'd0 || + (wsi_S0_burstKind == 2'd1 || wsi_S0_burstKind == 2'd2) && + wsi_S0_wsiReq$wget[165]) ; + + // register wsi_S0_errorSticky + assign wsi_S0_errorSticky$D_IN = 1'b0 ; + assign wsi_S0_errorSticky$EN = 1'b0 ; + + // register wsi_S0_iMesgCount + assign wsi_S0_iMesgCount$D_IN = wsi_S0_iMesgCount + 32'd1 ; + assign wsi_S0_iMesgCount$EN = + WILL_FIRE_RL_wsi_S0_reqFifo_enq && wsi_S0_burstKind == 2'd2 && + wsi_S0_wsiReq$wget[165] ; + + // register wsi_S0_isReset_isInReset + assign wsi_S0_isReset_isInReset$D_IN = 1'd0 ; + assign wsi_S0_isReset_isInReset$EN = wsi_S0_isReset_isInReset ; + + // register wsi_S0_mesgWordLength + assign wsi_S0_mesgWordLength$D_IN = wsi_S0_wordCount ; + assign wsi_S0_mesgWordLength$EN = + WILL_FIRE_RL_wsi_S0_reqFifo_enq && wsi_S0_wsiReq$wget[165] ; + + // register wsi_S0_operateD + assign wsi_S0_operateD$D_IN = wci_cState == 3'd2 ; + assign wsi_S0_operateD$EN = 1'd1 ; + + // register wsi_S0_pMesgCount + assign wsi_S0_pMesgCount$D_IN = wsi_S0_pMesgCount + 32'd1 ; + assign wsi_S0_pMesgCount$EN = + WILL_FIRE_RL_wsi_S0_reqFifo_enq && wsi_S0_burstKind == 2'd1 && + wsi_S0_wsiReq$wget[165] ; + + // register wsi_S0_peerIsReady + assign wsi_S0_peerIsReady$D_IN = wsiS0_MReset_n ; + assign wsi_S0_peerIsReady$EN = 1'd1 ; + + // register wsi_S0_reqFifo_countReg + assign wsi_S0_reqFifo_countReg$D_IN = + WILL_FIRE_RL_wsi_S0_reqFifo_enq ? + wsi_S0_reqFifo_countReg + 2'd1 : + wsi_S0_reqFifo_countReg - 2'd1 ; + assign wsi_S0_reqFifo_countReg$EN = + WILL_FIRE_RL_wsi_S0_reqFifo_enq != + WILL_FIRE_RL_doMessageConsume_S0 ; + + // register wsi_S0_reqFifo_levelsValid + assign wsi_S0_reqFifo_levelsValid$D_IN = WILL_FIRE_RL_wsi_S0_reqFifo_reset ; + assign wsi_S0_reqFifo_levelsValid$EN = + WILL_FIRE_RL_doMessageConsume_S0 || + WILL_FIRE_RL_wsi_S0_reqFifo_enq || + WILL_FIRE_RL_wsi_S0_reqFifo_reset ; + + // register wsi_S0_statusR + assign wsi_S0_statusR$D_IN = + { wsi_S0_isReset_isInReset, + !wsi_S0_peerIsReady, + !wsi_S0_operateD, + wsi_S0_errorSticky, + wsi_S0_burstKind != 2'd0, + !wsi_S0_sThreadBusy_dw$whas || wsi_S0_sThreadBusy_dw$wget, + 1'd0, + wsi_S0_trafficSticky } ; + assign wsi_S0_statusR$EN = 1'd1 ; + + // register wsi_S0_tBusyCount + assign wsi_S0_tBusyCount$D_IN = wsi_S0_tBusyCount + 32'd1 ; + assign wsi_S0_tBusyCount$EN = + wsi_S0_operateD && wsi_S0_peerIsReady && + (!wsi_S0_sThreadBusy_dw$whas || wsi_S0_sThreadBusy_dw$wget) ; + + // register wsi_S0_trafficSticky + assign wsi_S0_trafficSticky$D_IN = 1'd1 ; + assign wsi_S0_trafficSticky$EN = WILL_FIRE_RL_wsi_S0_reqFifo_enq ; + + // register wsi_S0_wordCount + assign wsi_S0_wordCount$D_IN = + wsi_S0_wsiReq$wget[165] ? 12'd1 : wsi_S0_wordCount + 12'd1 ; + assign wsi_S0_wordCount$EN = WILL_FIRE_RL_wsi_S0_reqFifo_enq ; + + // register wsi_S1_burstKind + assign wsi_S1_burstKind$D_IN = + (wsi_S1_burstKind == 2'd0) ? + (wsi_S1_wsiReq$wget[164] ? 2'd1 : 2'd2) : + 2'd0 ; + assign wsi_S1_burstKind$EN = + WILL_FIRE_RL_wsi_S1_reqFifo_enq && + (wsi_S1_burstKind == 2'd0 || + (wsi_S1_burstKind == 2'd1 || wsi_S1_burstKind == 2'd2) && + wsi_S1_wsiReq$wget[165]) ; + + // register wsi_S1_errorSticky + assign wsi_S1_errorSticky$D_IN = 1'b0 ; + assign wsi_S1_errorSticky$EN = 1'b0 ; + + // register wsi_S1_iMesgCount + assign wsi_S1_iMesgCount$D_IN = wsi_S1_iMesgCount + 32'd1 ; + assign wsi_S1_iMesgCount$EN = + WILL_FIRE_RL_wsi_S1_reqFifo_enq && wsi_S1_burstKind == 2'd2 && + wsi_S1_wsiReq$wget[165] ; + + // register wsi_S1_isReset_isInReset + assign wsi_S1_isReset_isInReset$D_IN = 1'd0 ; + assign wsi_S1_isReset_isInReset$EN = wsi_S1_isReset_isInReset ; + + // register wsi_S1_mesgWordLength + assign wsi_S1_mesgWordLength$D_IN = wsi_S1_wordCount ; + assign wsi_S1_mesgWordLength$EN = + WILL_FIRE_RL_wsi_S1_reqFifo_enq && wsi_S1_wsiReq$wget[165] ; + + // register wsi_S1_operateD + assign wsi_S1_operateD$D_IN = wci_cState == 3'd2 ; + assign wsi_S1_operateD$EN = 1'd1 ; + + // register wsi_S1_pMesgCount + assign wsi_S1_pMesgCount$D_IN = wsi_S1_pMesgCount + 32'd1 ; + assign wsi_S1_pMesgCount$EN = + WILL_FIRE_RL_wsi_S1_reqFifo_enq && wsi_S1_burstKind == 2'd1 && + wsi_S1_wsiReq$wget[165] ; + + // register wsi_S1_peerIsReady + assign wsi_S1_peerIsReady$D_IN = wsiS1_MReset_n ; + assign wsi_S1_peerIsReady$EN = 1'd1 ; + + // register wsi_S1_reqFifo_countReg + assign wsi_S1_reqFifo_countReg$D_IN = + WILL_FIRE_RL_wsi_S1_reqFifo_enq ? + wsi_S1_reqFifo_countReg + 2'd1 : + wsi_S1_reqFifo_countReg - 2'd1 ; + assign wsi_S1_reqFifo_countReg$EN = + WILL_FIRE_RL_wsi_S1_reqFifo_enq != + WILL_FIRE_RL_doMessageConsume_S1 ; + + // register wsi_S1_reqFifo_levelsValid + assign wsi_S1_reqFifo_levelsValid$D_IN = WILL_FIRE_RL_wsi_S1_reqFifo_reset ; + assign wsi_S1_reqFifo_levelsValid$EN = + WILL_FIRE_RL_doMessageConsume_S1 || + WILL_FIRE_RL_wsi_S1_reqFifo_enq || + WILL_FIRE_RL_wsi_S1_reqFifo_reset ; + + // register wsi_S1_statusR + assign wsi_S1_statusR$D_IN = + { wsi_S1_isReset_isInReset, + !wsi_S1_peerIsReady, + !wsi_S1_operateD, + wsi_S1_errorSticky, + wsi_S1_burstKind != 2'd0, + !wsi_S1_sThreadBusy_dw$whas || wsi_S1_sThreadBusy_dw$wget, + 1'd0, + wsi_S1_trafficSticky } ; + assign wsi_S1_statusR$EN = 1'd1 ; + + // register wsi_S1_tBusyCount + assign wsi_S1_tBusyCount$D_IN = wsi_S1_tBusyCount + 32'd1 ; + assign wsi_S1_tBusyCount$EN = + wsi_S1_operateD && wsi_S1_peerIsReady && + (!wsi_S1_sThreadBusy_dw$whas || wsi_S1_sThreadBusy_dw$wget) ; + + // register wsi_S1_trafficSticky + assign wsi_S1_trafficSticky$D_IN = 1'd1 ; + assign wsi_S1_trafficSticky$EN = WILL_FIRE_RL_wsi_S1_reqFifo_enq ; + + // register wsi_S1_wordCount + assign wsi_S1_wordCount$D_IN = + wsi_S1_wsiReq$wget[165] ? 12'd1 : wsi_S1_wordCount + 12'd1 ; + assign wsi_S1_wordCount$EN = WILL_FIRE_RL_wsi_S1_reqFifo_enq ; + + // submodule wci_reqF + assign wci_reqF$D_IN = wci_wciReq$wget ; + assign wci_reqF$ENQ = wci_wciReq$wget[71:69] != 3'd0 ; + assign wci_reqF$DEQ = wci_reqF_r_deq$whas ; + assign wci_reqF$CLR = 1'b0 ; + + // submodule wsi_S0_reqFifo + assign wsi_S0_reqFifo$D_IN = wsi_S0_wsiReq$wget ; + assign wsi_S0_reqFifo$ENQ = WILL_FIRE_RL_wsi_S0_reqFifo_enq ; + assign wsi_S0_reqFifo$DEQ = WILL_FIRE_RL_doMessageConsume_S0 ; + assign wsi_S0_reqFifo$CLR = 1'b0 ; + + // submodule wsi_S1_reqFifo + assign wsi_S1_reqFifo$D_IN = wsi_S1_wsiReq$wget ; + assign wsi_S1_reqFifo$ENQ = WILL_FIRE_RL_wsi_S1_reqFifo_enq ; + assign wsi_S1_reqFifo$DEQ = WILL_FIRE_RL_doMessageConsume_S1 ; + assign wsi_S1_reqFifo$CLR = 1'b0 ; + + // remaining internal signals + assign rdat__h16512 = + hasDebugLogic ? + { wsi_S0_statusR, + wsi_S1_statusR, + wsi_M0_statusR, + wsi_M1_statusR } : + 32'd0 ; + assign rdat__h16701 = + hasDebugLogic ? wsi_S0_extStatusW$wget[95:64] : 32'd0 ; + assign rdat__h16715 = + hasDebugLogic ? wsi_S0_extStatusW$wget[63:32] : 32'd0 ; + assign rdat__h16723 = + hasDebugLogic ? wsi_S1_extStatusW$wget[95:64] : 32'd0 ; + assign rdat__h16737 = + hasDebugLogic ? wsi_S1_extStatusW$wget[63:32] : 32'd0 ; + assign rdat__h16745 = + hasDebugLogic ? wsi_M0_extStatusW$wget[95:64] : 32'd0 ; + assign rdat__h16759 = + hasDebugLogic ? wsi_M0_extStatusW$wget[63:32] : 32'd0 ; + assign rdat__h16767 = + hasDebugLogic ? wsi_M1_extStatusW$wget[95:64] : 32'd0 ; + assign rdat__h16781 = + hasDebugLogic ? wsi_M1_extStatusW$wget[63:32] : 32'd0 ; + always@(wci_reqF$D_OUT or + splitCtrl or + rdat__h16512 or + rdat__h16701 or + rdat__h16715 or + rdat__h16723 or + rdat__h16737 or + rdat__h16745 or rdat__h16759 or rdat__h16767 or rdat__h16781) + begin + case (wci_reqF$D_OUT[39:32]) + 8'h04: _theResult____h16428 = splitCtrl; + 8'h1C: _theResult____h16428 = rdat__h16512; + 8'h20: _theResult____h16428 = rdat__h16701; + 8'h24: _theResult____h16428 = rdat__h16715; + 8'h28: _theResult____h16428 = rdat__h16723; + 8'h2C: _theResult____h16428 = rdat__h16737; + 8'h30: _theResult____h16428 = rdat__h16745; + 8'h34: _theResult____h16428 = rdat__h16759; + 8'h38: _theResult____h16428 = rdat__h16767; + 8'h3C: _theResult____h16428 = rdat__h16781; + default: _theResult____h16428 = 32'd0; + endcase + end + + // handling of inlined registers + + always@(posedge wciS0_Clk) + begin + if (wciS0_MReset_n == `BSV_RESET_VALUE) + begin + splitCtrl <= `BSV_ASSIGNMENT_DELAY ctrlInit; + wci_cEdge <= `BSV_ASSIGNMENT_DELAY 3'h2; + wci_cState <= `BSV_ASSIGNMENT_DELAY 3'd0; + wci_ctlAckReg <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_ctlOpActive <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_illegalEdge <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_nState <= `BSV_ASSIGNMENT_DELAY 3'd0; + wci_reqF_countReg <= `BSV_ASSIGNMENT_DELAY 2'd0; + wci_respF_c_r <= `BSV_ASSIGNMENT_DELAY 2'd0; + wci_respF_q_0 <= `BSV_ASSIGNMENT_DELAY 34'h0AAAAAAAA; + wci_respF_q_1 <= `BSV_ASSIGNMENT_DELAY 34'h0AAAAAAAA; + wci_sFlagReg <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY 1'd1; + wsi_M0_burstKind <= `BSV_ASSIGNMENT_DELAY 2'd0; + wsi_M0_errorSticky <= `BSV_ASSIGNMENT_DELAY 1'd0; + wsi_M0_iMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0; + wsi_M0_operateD <= `BSV_ASSIGNMENT_DELAY 1'd0; + wsi_M0_pMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0; + wsi_M0_peerIsReady <= `BSV_ASSIGNMENT_DELAY 1'd0; + wsi_M0_reqFifo_c_r <= `BSV_ASSIGNMENT_DELAY 2'd0; + wsi_M0_reqFifo_q_0 <= `BSV_ASSIGNMENT_DELAY + 169'h00000AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA00; + wsi_M0_reqFifo_q_1 <= `BSV_ASSIGNMENT_DELAY + 169'h00000AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA00; + wsi_M0_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY 1'd1; + wsi_M0_tBusyCount <= `BSV_ASSIGNMENT_DELAY 32'd0; + wsi_M0_trafficSticky <= `BSV_ASSIGNMENT_DELAY 1'd0; + wsi_M1_burstKind <= `BSV_ASSIGNMENT_DELAY 2'd0; + wsi_M1_errorSticky <= `BSV_ASSIGNMENT_DELAY 1'd0; + wsi_M1_iMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0; + wsi_M1_operateD <= `BSV_ASSIGNMENT_DELAY 1'd0; + wsi_M1_pMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0; + wsi_M1_peerIsReady <= `BSV_ASSIGNMENT_DELAY 1'd0; + wsi_M1_reqFifo_c_r <= `BSV_ASSIGNMENT_DELAY 2'd0; + wsi_M1_reqFifo_q_0 <= `BSV_ASSIGNMENT_DELAY + 169'h00000AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA00; + wsi_M1_reqFifo_q_1 <= `BSV_ASSIGNMENT_DELAY + 169'h00000AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA00; + wsi_M1_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY 1'd1; + wsi_M1_tBusyCount <= `BSV_ASSIGNMENT_DELAY 32'd0; + wsi_M1_trafficSticky <= `BSV_ASSIGNMENT_DELAY 1'd0; + wsi_S0_burstKind <= `BSV_ASSIGNMENT_DELAY 2'd0; + wsi_S0_errorSticky <= `BSV_ASSIGNMENT_DELAY 1'd0; + wsi_S0_iMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0; + wsi_S0_operateD <= `BSV_ASSIGNMENT_DELAY 1'd0; + wsi_S0_pMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0; + wsi_S0_peerIsReady <= `BSV_ASSIGNMENT_DELAY 1'd0; + wsi_S0_reqFifo_countReg <= `BSV_ASSIGNMENT_DELAY 2'd0; + wsi_S0_reqFifo_levelsValid <= `BSV_ASSIGNMENT_DELAY 1'd1; + wsi_S0_tBusyCount <= `BSV_ASSIGNMENT_DELAY 32'd0; + wsi_S0_trafficSticky <= `BSV_ASSIGNMENT_DELAY 1'd0; + wsi_S0_wordCount <= `BSV_ASSIGNMENT_DELAY 12'd1; + wsi_S1_burstKind <= `BSV_ASSIGNMENT_DELAY 2'd0; + wsi_S1_errorSticky <= `BSV_ASSIGNMENT_DELAY 1'd0; + wsi_S1_iMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0; + wsi_S1_operateD <= `BSV_ASSIGNMENT_DELAY 1'd0; + wsi_S1_pMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0; + wsi_S1_peerIsReady <= `BSV_ASSIGNMENT_DELAY 1'd0; + wsi_S1_reqFifo_countReg <= `BSV_ASSIGNMENT_DELAY 2'd0; + wsi_S1_reqFifo_levelsValid <= `BSV_ASSIGNMENT_DELAY 1'd1; + wsi_S1_tBusyCount <= `BSV_ASSIGNMENT_DELAY 32'd0; + wsi_S1_trafficSticky <= `BSV_ASSIGNMENT_DELAY 1'd0; + wsi_S1_wordCount <= `BSV_ASSIGNMENT_DELAY 12'd1; + end + else + begin + if (splitCtrl$EN) splitCtrl <= `BSV_ASSIGNMENT_DELAY splitCtrl$D_IN; + if (wci_cEdge$EN) wci_cEdge <= `BSV_ASSIGNMENT_DELAY wci_cEdge$D_IN; + if (wci_cState$EN) + wci_cState <= `BSV_ASSIGNMENT_DELAY wci_cState$D_IN; + if (wci_ctlAckReg$EN) + wci_ctlAckReg <= `BSV_ASSIGNMENT_DELAY wci_ctlAckReg$D_IN; + if (wci_ctlOpActive$EN) + wci_ctlOpActive <= `BSV_ASSIGNMENT_DELAY wci_ctlOpActive$D_IN; + if (wci_illegalEdge$EN) + wci_illegalEdge <= `BSV_ASSIGNMENT_DELAY wci_illegalEdge$D_IN; + if (wci_nState$EN) + wci_nState <= `BSV_ASSIGNMENT_DELAY wci_nState$D_IN; + if (wci_reqF_countReg$EN) + wci_reqF_countReg <= `BSV_ASSIGNMENT_DELAY wci_reqF_countReg$D_IN; + if (wci_respF_c_r$EN) + wci_respF_c_r <= `BSV_ASSIGNMENT_DELAY wci_respF_c_r$D_IN; + if (wci_respF_q_0$EN) + wci_respF_q_0 <= `BSV_ASSIGNMENT_DELAY wci_respF_q_0$D_IN; + if (wci_respF_q_1$EN) + wci_respF_q_1 <= `BSV_ASSIGNMENT_DELAY wci_respF_q_1$D_IN; + if (wci_sFlagReg$EN) + wci_sFlagReg <= `BSV_ASSIGNMENT_DELAY wci_sFlagReg$D_IN; + if (wci_sThreadBusy_d$EN) + wci_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY wci_sThreadBusy_d$D_IN; + if (wsi_M0_burstKind$EN) + wsi_M0_burstKind <= `BSV_ASSIGNMENT_DELAY wsi_M0_burstKind$D_IN; + if (wsi_M0_errorSticky$EN) + wsi_M0_errorSticky <= `BSV_ASSIGNMENT_DELAY wsi_M0_errorSticky$D_IN; + if (wsi_M0_iMesgCount$EN) + wsi_M0_iMesgCount <= `BSV_ASSIGNMENT_DELAY wsi_M0_iMesgCount$D_IN; + if (wsi_M0_operateD$EN) + wsi_M0_operateD <= `BSV_ASSIGNMENT_DELAY wsi_M0_operateD$D_IN; + if (wsi_M0_pMesgCount$EN) + wsi_M0_pMesgCount <= `BSV_ASSIGNMENT_DELAY wsi_M0_pMesgCount$D_IN; + if (wsi_M0_peerIsReady$EN) + wsi_M0_peerIsReady <= `BSV_ASSIGNMENT_DELAY wsi_M0_peerIsReady$D_IN; + if (wsi_M0_reqFifo_c_r$EN) + wsi_M0_reqFifo_c_r <= `BSV_ASSIGNMENT_DELAY wsi_M0_reqFifo_c_r$D_IN; + if (wsi_M0_reqFifo_q_0$EN) + wsi_M0_reqFifo_q_0 <= `BSV_ASSIGNMENT_DELAY wsi_M0_reqFifo_q_0$D_IN; + if (wsi_M0_reqFifo_q_1$EN) + wsi_M0_reqFifo_q_1 <= `BSV_ASSIGNMENT_DELAY wsi_M0_reqFifo_q_1$D_IN; + if (wsi_M0_sThreadBusy_d$EN) + wsi_M0_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY + wsi_M0_sThreadBusy_d$D_IN; + if (wsi_M0_tBusyCount$EN) + wsi_M0_tBusyCount <= `BSV_ASSIGNMENT_DELAY wsi_M0_tBusyCount$D_IN; + if (wsi_M0_trafficSticky$EN) + wsi_M0_trafficSticky <= `BSV_ASSIGNMENT_DELAY + wsi_M0_trafficSticky$D_IN; + if (wsi_M1_burstKind$EN) + wsi_M1_burstKind <= `BSV_ASSIGNMENT_DELAY wsi_M1_burstKind$D_IN; + if (wsi_M1_errorSticky$EN) + wsi_M1_errorSticky <= `BSV_ASSIGNMENT_DELAY wsi_M1_errorSticky$D_IN; + if (wsi_M1_iMesgCount$EN) + wsi_M1_iMesgCount <= `BSV_ASSIGNMENT_DELAY wsi_M1_iMesgCount$D_IN; + if (wsi_M1_operateD$EN) + wsi_M1_operateD <= `BSV_ASSIGNMENT_DELAY wsi_M1_operateD$D_IN; + if (wsi_M1_pMesgCount$EN) + wsi_M1_pMesgCount <= `BSV_ASSIGNMENT_DELAY wsi_M1_pMesgCount$D_IN; + if (wsi_M1_peerIsReady$EN) + wsi_M1_peerIsReady <= `BSV_ASSIGNMENT_DELAY wsi_M1_peerIsReady$D_IN; + if (wsi_M1_reqFifo_c_r$EN) + wsi_M1_reqFifo_c_r <= `BSV_ASSIGNMENT_DELAY wsi_M1_reqFifo_c_r$D_IN; + if (wsi_M1_reqFifo_q_0$EN) + wsi_M1_reqFifo_q_0 <= `BSV_ASSIGNMENT_DELAY wsi_M1_reqFifo_q_0$D_IN; + if (wsi_M1_reqFifo_q_1$EN) + wsi_M1_reqFifo_q_1 <= `BSV_ASSIGNMENT_DELAY wsi_M1_reqFifo_q_1$D_IN; + if (wsi_M1_sThreadBusy_d$EN) + wsi_M1_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY + wsi_M1_sThreadBusy_d$D_IN; + if (wsi_M1_tBusyCount$EN) + wsi_M1_tBusyCount <= `BSV_ASSIGNMENT_DELAY wsi_M1_tBusyCount$D_IN; + if (wsi_M1_trafficSticky$EN) + wsi_M1_trafficSticky <= `BSV_ASSIGNMENT_DELAY + wsi_M1_trafficSticky$D_IN; + if (wsi_S0_burstKind$EN) + wsi_S0_burstKind <= `BSV_ASSIGNMENT_DELAY wsi_S0_burstKind$D_IN; + if (wsi_S0_errorSticky$EN) + wsi_S0_errorSticky <= `BSV_ASSIGNMENT_DELAY wsi_S0_errorSticky$D_IN; + if (wsi_S0_iMesgCount$EN) + wsi_S0_iMesgCount <= `BSV_ASSIGNMENT_DELAY wsi_S0_iMesgCount$D_IN; + if (wsi_S0_operateD$EN) + wsi_S0_operateD <= `BSV_ASSIGNMENT_DELAY wsi_S0_operateD$D_IN; + if (wsi_S0_pMesgCount$EN) + wsi_S0_pMesgCount <= `BSV_ASSIGNMENT_DELAY wsi_S0_pMesgCount$D_IN; + if (wsi_S0_peerIsReady$EN) + wsi_S0_peerIsReady <= `BSV_ASSIGNMENT_DELAY wsi_S0_peerIsReady$D_IN; + if (wsi_S0_reqFifo_countReg$EN) + wsi_S0_reqFifo_countReg <= `BSV_ASSIGNMENT_DELAY + wsi_S0_reqFifo_countReg$D_IN; + if (wsi_S0_reqFifo_levelsValid$EN) + wsi_S0_reqFifo_levelsValid <= `BSV_ASSIGNMENT_DELAY + wsi_S0_reqFifo_levelsValid$D_IN; + if (wsi_S0_tBusyCount$EN) + wsi_S0_tBusyCount <= `BSV_ASSIGNMENT_DELAY wsi_S0_tBusyCount$D_IN; + if (wsi_S0_trafficSticky$EN) + wsi_S0_trafficSticky <= `BSV_ASSIGNMENT_DELAY + wsi_S0_trafficSticky$D_IN; + if (wsi_S0_wordCount$EN) + wsi_S0_wordCount <= `BSV_ASSIGNMENT_DELAY wsi_S0_wordCount$D_IN; + if (wsi_S1_burstKind$EN) + wsi_S1_burstKind <= `BSV_ASSIGNMENT_DELAY wsi_S1_burstKind$D_IN; + if (wsi_S1_errorSticky$EN) + wsi_S1_errorSticky <= `BSV_ASSIGNMENT_DELAY wsi_S1_errorSticky$D_IN; + if (wsi_S1_iMesgCount$EN) + wsi_S1_iMesgCount <= `BSV_ASSIGNMENT_DELAY wsi_S1_iMesgCount$D_IN; + if (wsi_S1_operateD$EN) + wsi_S1_operateD <= `BSV_ASSIGNMENT_DELAY wsi_S1_operateD$D_IN; + if (wsi_S1_pMesgCount$EN) + wsi_S1_pMesgCount <= `BSV_ASSIGNMENT_DELAY wsi_S1_pMesgCount$D_IN; + if (wsi_S1_peerIsReady$EN) + wsi_S1_peerIsReady <= `BSV_ASSIGNMENT_DELAY wsi_S1_peerIsReady$D_IN; + if (wsi_S1_reqFifo_countReg$EN) + wsi_S1_reqFifo_countReg <= `BSV_ASSIGNMENT_DELAY + wsi_S1_reqFifo_countReg$D_IN; + if (wsi_S1_reqFifo_levelsValid$EN) + wsi_S1_reqFifo_levelsValid <= `BSV_ASSIGNMENT_DELAY + wsi_S1_reqFifo_levelsValid$D_IN; + if (wsi_S1_tBusyCount$EN) + wsi_S1_tBusyCount <= `BSV_ASSIGNMENT_DELAY wsi_S1_tBusyCount$D_IN; + if (wsi_S1_trafficSticky$EN) + wsi_S1_trafficSticky <= `BSV_ASSIGNMENT_DELAY + wsi_S1_trafficSticky$D_IN; + if (wsi_S1_wordCount$EN) + wsi_S1_wordCount <= `BSV_ASSIGNMENT_DELAY wsi_S1_wordCount$D_IN; + end + if (wsi_M0_statusR$EN) + wsi_M0_statusR <= `BSV_ASSIGNMENT_DELAY wsi_M0_statusR$D_IN; + if (wsi_M1_statusR$EN) + wsi_M1_statusR <= `BSV_ASSIGNMENT_DELAY wsi_M1_statusR$D_IN; + if (wsi_S0_mesgWordLength$EN) + wsi_S0_mesgWordLength <= `BSV_ASSIGNMENT_DELAY + wsi_S0_mesgWordLength$D_IN; + if (wsi_S0_statusR$EN) + wsi_S0_statusR <= `BSV_ASSIGNMENT_DELAY wsi_S0_statusR$D_IN; + if (wsi_S1_mesgWordLength$EN) + wsi_S1_mesgWordLength <= `BSV_ASSIGNMENT_DELAY + wsi_S1_mesgWordLength$D_IN; + if (wsi_S1_statusR$EN) + wsi_S1_statusR <= `BSV_ASSIGNMENT_DELAY wsi_S1_statusR$D_IN; + end + + always@(posedge wciS0_Clk or `BSV_RESET_EDGE wciS0_MReset_n) + if (wciS0_MReset_n == `BSV_RESET_VALUE) + begin + wci_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY 1'd1; + wsi_M0_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY 1'd1; + wsi_M1_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY 1'd1; + wsi_S0_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY 1'd1; + wsi_S1_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY 1'd1; + end + else + begin + if (wci_isReset_isInReset$EN) + wci_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY + wci_isReset_isInReset$D_IN; + if (wsi_M0_isReset_isInReset$EN) + wsi_M0_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY + wsi_M0_isReset_isInReset$D_IN; + if (wsi_M1_isReset_isInReset$EN) + wsi_M1_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY + wsi_M1_isReset_isInReset$D_IN; + if (wsi_S0_isReset_isInReset$EN) + wsi_S0_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY + wsi_S0_isReset_isInReset$D_IN; + if (wsi_S1_isReset_isInReset$EN) + wsi_S1_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY + wsi_S1_isReset_isInReset$D_IN; + end + + // synopsys translate_off + `ifdef BSV_NO_INITIAL_BLOCKS + `else // not BSV_NO_INITIAL_BLOCKS + initial + begin + splitCtrl = 32'hAAAAAAAA; + wci_cEdge = 3'h2; + wci_cState = 3'h2; + wci_ctlAckReg = 1'h0; + wci_ctlOpActive = 1'h0; + wci_illegalEdge = 1'h0; + wci_isReset_isInReset = 1'h0; + wci_nState = 3'h2; + wci_reqF_countReg = 2'h2; + wci_respF_c_r = 2'h2; + wci_respF_q_0 = 34'h2AAAAAAAA; + wci_respF_q_1 = 34'h2AAAAAAAA; + wci_sFlagReg = 1'h0; + wci_sThreadBusy_d = 1'h0; + wsi_M0_burstKind = 2'h2; + wsi_M0_errorSticky = 1'h0; + wsi_M0_iMesgCount = 32'hAAAAAAAA; + wsi_M0_isReset_isInReset = 1'h0; + wsi_M0_operateD = 1'h0; + wsi_M0_pMesgCount = 32'hAAAAAAAA; + wsi_M0_peerIsReady = 1'h0; + wsi_M0_reqFifo_c_r = 2'h2; + wsi_M0_reqFifo_q_0 = 169'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; + wsi_M0_reqFifo_q_1 = 169'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; + wsi_M0_sThreadBusy_d = 1'h0; + wsi_M0_statusR = 8'hAA; + wsi_M0_tBusyCount = 32'hAAAAAAAA; + wsi_M0_trafficSticky = 1'h0; + wsi_M1_burstKind = 2'h2; + wsi_M1_errorSticky = 1'h0; + wsi_M1_iMesgCount = 32'hAAAAAAAA; + wsi_M1_isReset_isInReset = 1'h0; + wsi_M1_operateD = 1'h0; + wsi_M1_pMesgCount = 32'hAAAAAAAA; + wsi_M1_peerIsReady = 1'h0; + wsi_M1_reqFifo_c_r = 2'h2; + wsi_M1_reqFifo_q_0 = 169'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; + wsi_M1_reqFifo_q_1 = 169'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; + wsi_M1_sThreadBusy_d = 1'h0; + wsi_M1_statusR = 8'hAA; + wsi_M1_tBusyCount = 32'hAAAAAAAA; + wsi_M1_trafficSticky = 1'h0; + wsi_S0_burstKind = 2'h2; + wsi_S0_errorSticky = 1'h0; + wsi_S0_iMesgCount = 32'hAAAAAAAA; + wsi_S0_isReset_isInReset = 1'h0; + wsi_S0_mesgWordLength = 12'hAAA; + wsi_S0_operateD = 1'h0; + wsi_S0_pMesgCount = 32'hAAAAAAAA; + wsi_S0_peerIsReady = 1'h0; + wsi_S0_reqFifo_countReg = 2'h2; + wsi_S0_reqFifo_levelsValid = 1'h0; + wsi_S0_statusR = 8'hAA; + wsi_S0_tBusyCount = 32'hAAAAAAAA; + wsi_S0_trafficSticky = 1'h0; + wsi_S0_wordCount = 12'hAAA; + wsi_S1_burstKind = 2'h2; + wsi_S1_errorSticky = 1'h0; + wsi_S1_iMesgCount = 32'hAAAAAAAA; + wsi_S1_isReset_isInReset = 1'h0; + wsi_S1_mesgWordLength = 12'hAAA; + wsi_S1_operateD = 1'h0; + wsi_S1_pMesgCount = 32'hAAAAAAAA; + wsi_S1_peerIsReady = 1'h0; + wsi_S1_reqFifo_countReg = 2'h2; + wsi_S1_reqFifo_levelsValid = 1'h0; + wsi_S1_statusR = 8'hAA; + wsi_S1_tBusyCount = 32'hAAAAAAAA; + wsi_S1_trafficSticky = 1'h0; + wsi_S1_wordCount = 12'hAAA; + end + `endif // BSV_NO_INITIAL_BLOCKS + // synopsys translate_on + + // handling of system tasks + + // synopsys translate_off + always@(negedge wciS0_Clk) + begin + #0; + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_ctl_op_start) + begin + v__h3698 = $time; + #0; + end + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_ctl_op_start) + $display("[%0d]: %m: WCI ControlOp: Starting-transition edge:%x from:%x", + v__h3698, + wci_reqF$D_OUT[36:34], + wci_cState); + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_ctrl_EiI && WILL_FIRE_RL_wci_ctrl_OrE) + $display("Error: \"bsv/inf/WsiSplitter2x2.bsv\", line 48, column 46: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_EiI] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n"); + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_ctrl_EiI && WILL_FIRE_RL_wci_ctrl_IsO) + $display("Error: \"bsv/inf/WsiSplitter2x2.bsv\", line 48, column 46: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_EiI] and\n [RL_wci_ctrl_IsO] ) fired in the same clock cycle.\n"); + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_ctrl_IsO && WILL_FIRE_RL_wci_ctrl_OrE) + $display("Error: \"bsv/inf/WsiSplitter2x2.bsv\", line 48, column 60: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_IsO] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n"); + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_cfwr) + begin + v__h16289 = $time; + #0; + end + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_cfwr) + $display("[%0d]: %m: WCI CONFIG WRITE Addr:%0x BE:%0x Data:%0x", + v__h16289, + wci_reqF$D_OUT[63:32], + wci_reqF$D_OUT[67:64], + wci_reqF$D_OUT[31:0]); + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_ctl_op_complete && wci_illegalEdge) + begin + v__h4017 = $time; + #0; + end + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_ctl_op_complete && wci_illegalEdge) + $display("[%0d]: %m: WCI ControlOp: ILLEGAL-EDGE Completed-transition edge:%x from:%x", + v__h4017, + wci_cEdge, + wci_cState); + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_ctl_op_complete && !wci_illegalEdge) + begin + v__h3873 = $time; + #0; + end + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_ctl_op_complete && !wci_illegalEdge) + $display("[%0d]: %m: WCI ControlOp: Completed-transition edge:%x from:%x to:%x", + v__h3873, + wci_cEdge, + wci_cState, + wci_nState); + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_cfrd) + begin + v__h16444 = $time; + #0; + end + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_cfrd) + $display("[%0d]: %m: WCI CONFIG READ Addr:%0x BE:%0x Data:%0x", + v__h16444, + wci_reqF$D_OUT[63:32], + wci_reqF$D_OUT[67:64], + _theResult____h16428); + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_OrE) + $display("Error: \"bsv/inf/WsiSplitter2x2.bsv\", line 48, column 26: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n"); + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_IsO) + $display("Error: \"bsv/inf/WsiSplitter2x2.bsv\", line 48, column 26: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_wci_ctrl_IsO] ) fired in the same clock cycle.\n"); + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_EiI) + $display("Error: \"bsv/inf/WsiSplitter2x2.bsv\", line 48, column 26: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_wci_ctrl_EiI] ) fired in the same clock cycle.\n"); + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_cfrd) + $display("Error: \"bsv/inf/WsiSplitter2x2.bsv\", line 48, column 26: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and [RL_wci_cfrd] )\n fired in the same clock cycle.\n"); + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_cfrd && WILL_FIRE_RL_wci_ctrl_OrE) + $display("Error: \"bsv/inf/WsiSplitter2x2.bsv\", line 48, column 36: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n"); + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_cfrd && WILL_FIRE_RL_wci_ctrl_IsO) + $display("Error: \"bsv/inf/WsiSplitter2x2.bsv\", line 48, column 36: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n [RL_wci_ctrl_IsO] ) fired in the same clock cycle.\n"); + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_cfrd && WILL_FIRE_RL_wci_ctrl_EiI) + $display("Error: \"bsv/inf/WsiSplitter2x2.bsv\", line 48, column 36: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n [RL_wci_ctrl_EiI] ) fired in the same clock cycle.\n"); + end + // synopsys translate_on +endmodule // mkWsiSplitter2x216B + diff --git a/rtl/mkWsiSplitter2x232B.v b/rtl/mkWsiSplitter2x232B.v new file mode 100644 index 00000000..d95b1590 --- /dev/null +++ b/rtl/mkWsiSplitter2x232B.v @@ -0,0 +1,2452 @@ +// +// Generated by Bluespec Compiler, version 2012.09.beta1 (build 29570, 2012-09.11) +// +// On Tue Jan 22 07:33:07 EST 2013 +// +// +// Ports: +// Name I/O size props +// wciS0_SResp O 2 reg +// wciS0_SData O 32 reg +// wciS0_SThreadBusy O 1 +// wciS0_SFlag O 2 +// wsiS0_SThreadBusy O 1 +// wsiS0_SReset_n O 1 +// wsiS1_SThreadBusy O 1 +// wsiS1_SReset_n O 1 +// wsiM0_MCmd O 3 +// wsiM0_MReqLast O 1 +// wsiM0_MBurstPrecise O 1 +// wsiM0_MBurstLength O 12 +// wsiM0_MData O 256 reg +// wsiM0_MByteEn O 32 reg +// wsiM0_MReqInfo O 8 +// wsiM0_MReset_n O 1 +// wsiM1_MCmd O 3 +// wsiM1_MReqLast O 1 +// wsiM1_MBurstPrecise O 1 +// wsiM1_MBurstLength O 12 +// wsiM1_MData O 256 reg +// wsiM1_MByteEn O 32 reg +// wsiM1_MReqInfo O 8 +// wsiM1_MReset_n O 1 +// wciS0_Clk I 1 clock +// wciS0_MReset_n I 1 reset +// wciS0_MCmd I 3 +// wciS0_MAddrSpace I 1 +// wciS0_MByteEn I 4 +// wciS0_MAddr I 32 +// wciS0_MData I 32 +// wciS0_MFlag I 2 unused +// wsiS0_MCmd I 3 +// wsiS0_MBurstLength I 12 +// wsiS0_MData I 256 +// wsiS0_MByteEn I 32 +// wsiS0_MReqInfo I 8 +// wsiS1_MCmd I 3 +// wsiS1_MBurstLength I 12 +// wsiS1_MData I 256 +// wsiS1_MByteEn I 32 +// wsiS1_MReqInfo I 8 +// wsiS0_MReqLast I 1 +// wsiS0_MBurstPrecise I 1 +// wsiS0_MReset_n I 1 reg +// wsiS1_MReqLast I 1 +// wsiS1_MBurstPrecise I 1 +// wsiS1_MReset_n I 1 reg +// wsiM0_SThreadBusy I 1 reg +// wsiM0_SReset_n I 1 reg +// wsiM1_SThreadBusy I 1 reg +// wsiM1_SReset_n I 1 reg +// +// No combinational paths from inputs to outputs +// +// + +`ifdef BSV_ASSIGNMENT_DELAY +`else + `define BSV_ASSIGNMENT_DELAY +`endif + +`ifdef BSV_POSITIVE_RESET + `define BSV_RESET_VALUE 1'b1 + `define BSV_RESET_EDGE posedge +`else + `define BSV_RESET_VALUE 1'b0 + `define BSV_RESET_EDGE negedge +`endif + +module mkWsiSplitter2x232B(wciS0_Clk, + wciS0_MReset_n, + + wciS0_MCmd, + + wciS0_MAddrSpace, + + wciS0_MByteEn, + + wciS0_MAddr, + + wciS0_MData, + + wciS0_SResp, + + wciS0_SData, + + wciS0_SThreadBusy, + + wciS0_SFlag, + + wciS0_MFlag, + + wsiS0_MCmd, + + wsiS0_MReqLast, + + wsiS0_MBurstPrecise, + + wsiS0_MBurstLength, + + wsiS0_MData, + + wsiS0_MByteEn, + + wsiS0_MReqInfo, + + wsiS0_SThreadBusy, + + wsiS0_SReset_n, + + wsiS0_MReset_n, + + wsiS1_MCmd, + + wsiS1_MReqLast, + + wsiS1_MBurstPrecise, + + wsiS1_MBurstLength, + + wsiS1_MData, + + wsiS1_MByteEn, + + wsiS1_MReqInfo, + + wsiS1_SThreadBusy, + + wsiS1_SReset_n, + + wsiS1_MReset_n, + + wsiM0_MCmd, + + wsiM0_MReqLast, + + wsiM0_MBurstPrecise, + + wsiM0_MBurstLength, + + wsiM0_MData, + + wsiM0_MByteEn, + + wsiM0_MReqInfo, + + wsiM0_SThreadBusy, + + wsiM0_MReset_n, + + wsiM0_SReset_n, + + wsiM1_MCmd, + + wsiM1_MReqLast, + + wsiM1_MBurstPrecise, + + wsiM1_MBurstLength, + + wsiM1_MData, + + wsiM1_MByteEn, + + wsiM1_MReqInfo, + + wsiM1_SThreadBusy, + + wsiM1_MReset_n, + + wsiM1_SReset_n); + parameter [31 : 0] ctrlInit = 32'b0; + parameter [0 : 0] hasDebugLogic = 1'b0; + input wciS0_Clk; + input wciS0_MReset_n; + + // action method wciS0_mCmd + input [2 : 0] wciS0_MCmd; + + // action method wciS0_mAddrSpace + input wciS0_MAddrSpace; + + // action method wciS0_mByteEn + input [3 : 0] wciS0_MByteEn; + + // action method wciS0_mAddr + input [31 : 0] wciS0_MAddr; + + // action method wciS0_mData + input [31 : 0] wciS0_MData; + + // value method wciS0_sResp + output [1 : 0] wciS0_SResp; + + // value method wciS0_sData + output [31 : 0] wciS0_SData; + + // value method wciS0_sThreadBusy + output wciS0_SThreadBusy; + + // value method wciS0_sFlag + output [1 : 0] wciS0_SFlag; + + // action method wciS0_mFlag + input [1 : 0] wciS0_MFlag; + + // action method wsiS0_mCmd + input [2 : 0] wsiS0_MCmd; + + // action method wsiS0_mReqLast + input wsiS0_MReqLast; + + // action method wsiS0_mBurstPrecise + input wsiS0_MBurstPrecise; + + // action method wsiS0_mBurstLength + input [11 : 0] wsiS0_MBurstLength; + + // action method wsiS0_mData + input [255 : 0] wsiS0_MData; + + // action method wsiS0_mByteEn + input [31 : 0] wsiS0_MByteEn; + + // action method wsiS0_mReqInfo + input [7 : 0] wsiS0_MReqInfo; + + // action method wsiS0_mDataInfo + + // value method wsiS0_sThreadBusy + output wsiS0_SThreadBusy; + + // value method wsiS0_sReset_n + output wsiS0_SReset_n; + + // action method wsiS0_mReset_n + input wsiS0_MReset_n; + + // action method wsiS1_mCmd + input [2 : 0] wsiS1_MCmd; + + // action method wsiS1_mReqLast + input wsiS1_MReqLast; + + // action method wsiS1_mBurstPrecise + input wsiS1_MBurstPrecise; + + // action method wsiS1_mBurstLength + input [11 : 0] wsiS1_MBurstLength; + + // action method wsiS1_mData + input [255 : 0] wsiS1_MData; + + // action method wsiS1_mByteEn + input [31 : 0] wsiS1_MByteEn; + + // action method wsiS1_mReqInfo + input [7 : 0] wsiS1_MReqInfo; + + // action method wsiS1_mDataInfo + + // value method wsiS1_sThreadBusy + output wsiS1_SThreadBusy; + + // value method wsiS1_sReset_n + output wsiS1_SReset_n; + + // action method wsiS1_mReset_n + input wsiS1_MReset_n; + + // value method wsiM0_mCmd + output [2 : 0] wsiM0_MCmd; + + // value method wsiM0_mReqLast + output wsiM0_MReqLast; + + // value method wsiM0_mBurstPrecise + output wsiM0_MBurstPrecise; + + // value method wsiM0_mBurstLength + output [11 : 0] wsiM0_MBurstLength; + + // value method wsiM0_mData + output [255 : 0] wsiM0_MData; + + // value method wsiM0_mByteEn + output [31 : 0] wsiM0_MByteEn; + + // value method wsiM0_mReqInfo + output [7 : 0] wsiM0_MReqInfo; + + // value method wsiM0_mDataInfo + + // action method wsiM0_sThreadBusy + input wsiM0_SThreadBusy; + + // value method wsiM0_mReset_n + output wsiM0_MReset_n; + + // action method wsiM0_sReset_n + input wsiM0_SReset_n; + + // value method wsiM1_mCmd + output [2 : 0] wsiM1_MCmd; + + // value method wsiM1_mReqLast + output wsiM1_MReqLast; + + // value method wsiM1_mBurstPrecise + output wsiM1_MBurstPrecise; + + // value method wsiM1_mBurstLength + output [11 : 0] wsiM1_MBurstLength; + + // value method wsiM1_mData + output [255 : 0] wsiM1_MData; + + // value method wsiM1_mByteEn + output [31 : 0] wsiM1_MByteEn; + + // value method wsiM1_mReqInfo + output [7 : 0] wsiM1_MReqInfo; + + // value method wsiM1_mDataInfo + + // action method wsiM1_sThreadBusy + input wsiM1_SThreadBusy; + + // value method wsiM1_mReset_n + output wsiM1_MReset_n; + + // action method wsiM1_sReset_n + input wsiM1_SReset_n; + + // signals for module outputs + wire [255 : 0] wsiM0_MData, wsiM1_MData; + wire [31 : 0] wciS0_SData, wsiM0_MByteEn, wsiM1_MByteEn; + wire [11 : 0] wsiM0_MBurstLength, wsiM1_MBurstLength; + wire [7 : 0] wsiM0_MReqInfo, wsiM1_MReqInfo; + wire [2 : 0] wsiM0_MCmd, wsiM1_MCmd; + wire [1 : 0] wciS0_SFlag, wciS0_SResp; + wire wciS0_SThreadBusy, + wsiM0_MBurstPrecise, + wsiM0_MReqLast, + wsiM0_MReset_n, + wsiM1_MBurstPrecise, + wsiM1_MReqLast, + wsiM1_MReset_n, + wsiS0_SReset_n, + wsiS0_SThreadBusy, + wsiS1_SReset_n, + wsiS1_SThreadBusy; + + // inlined wires + wire [312 : 0] wsi_M0_reqFifo_x_wire$wget, + wsi_M1_reqFifo_x_wire$wget, + wsi_S0_wsiReq$wget, + wsi_S1_wsiReq$wget; + wire [255 : 0] wsi_Es0_mData_w$wget, wsi_Es1_mData_w$wget; + wire [95 : 0] wsi_M0_extStatusW$wget, + wsi_M1_extStatusW$wget, + wsi_S0_extStatusW$wget, + wsi_S1_extStatusW$wget; + wire [71 : 0] wci_wciReq$wget; + wire [33 : 0] wci_respF_x_wire$wget; + wire [31 : 0] wci_Es_mAddr_w$wget, + wci_Es_mData_w$wget, + wsi_Es0_mByteEn_w$wget, + wsi_Es1_mByteEn_w$wget; + wire [11 : 0] wsi_Es0_mBurstLength_w$wget, wsi_Es1_mBurstLength_w$wget; + wire [7 : 0] wsi_Es0_mReqInfo_w$wget, wsi_Es1_mReqInfo_w$wget; + wire [3 : 0] wci_Es_mByteEn_w$wget; + wire [2 : 0] wci_Es_mCmd_w$wget, + wci_wEdge$wget, + wsi_Es0_mCmd_w$wget, + wsi_Es1_mCmd_w$wget; + wire wci_Es_mAddrSpace_w$wget, + wci_Es_mAddrSpace_w$whas, + wci_Es_mAddr_w$whas, + wci_Es_mByteEn_w$whas, + wci_Es_mCmd_w$whas, + wci_Es_mData_w$whas, + wci_ctlAckReg_1$wget, + wci_ctlAckReg_1$whas, + wci_reqF_r_clr$whas, + wci_reqF_r_deq$whas, + wci_reqF_r_enq$whas, + wci_respF_dequeueing$whas, + wci_respF_enqueueing$whas, + wci_respF_x_wire$whas, + wci_sFlagReg_1$wget, + wci_sFlagReg_1$whas, + wci_sThreadBusy_pw$whas, + wci_wEdge$whas, + wci_wciReq$whas, + wci_wci_cfrd_pw$whas, + wci_wci_cfwr_pw$whas, + wci_wci_ctrl_pw$whas, + wsi_Es0_mBurstLength_w$whas, + wsi_Es0_mBurstPrecise_w$whas, + wsi_Es0_mByteEn_w$whas, + wsi_Es0_mCmd_w$whas, + wsi_Es0_mDataInfo_w$whas, + wsi_Es0_mData_w$whas, + wsi_Es0_mReqInfo_w$whas, + wsi_Es0_mReqLast_w$whas, + wsi_Es1_mBurstLength_w$whas, + wsi_Es1_mBurstPrecise_w$whas, + wsi_Es1_mByteEn_w$whas, + wsi_Es1_mCmd_w$whas, + wsi_Es1_mDataInfo_w$whas, + wsi_Es1_mData_w$whas, + wsi_Es1_mReqInfo_w$whas, + wsi_Es1_mReqLast_w$whas, + wsi_M0_operateD_1$wget, + wsi_M0_operateD_1$whas, + wsi_M0_peerIsReady_1$wget, + wsi_M0_peerIsReady_1$whas, + wsi_M0_reqFifo_dequeueing$whas, + wsi_M0_reqFifo_enqueueing$whas, + wsi_M0_reqFifo_x_wire$whas, + wsi_M0_sThreadBusy_pw$whas, + wsi_M1_operateD_1$wget, + wsi_M1_operateD_1$whas, + wsi_M1_peerIsReady_1$wget, + wsi_M1_peerIsReady_1$whas, + wsi_M1_reqFifo_dequeueing$whas, + wsi_M1_reqFifo_enqueueing$whas, + wsi_M1_reqFifo_x_wire$whas, + wsi_M1_sThreadBusy_pw$whas, + wsi_S0_operateD_1$wget, + wsi_S0_operateD_1$whas, + wsi_S0_peerIsReady_1$wget, + wsi_S0_peerIsReady_1$whas, + wsi_S0_reqFifo_doResetClr$whas, + wsi_S0_reqFifo_doResetDeq$whas, + wsi_S0_reqFifo_doResetEnq$whas, + wsi_S0_reqFifo_r_clr$whas, + wsi_S0_reqFifo_r_deq$whas, + wsi_S0_reqFifo_r_enq$whas, + wsi_S0_sThreadBusy_dw$wget, + wsi_S0_sThreadBusy_dw$whas, + wsi_S0_wsiReq$whas, + wsi_S1_operateD_1$wget, + wsi_S1_operateD_1$whas, + wsi_S1_peerIsReady_1$wget, + wsi_S1_peerIsReady_1$whas, + wsi_S1_reqFifo_doResetClr$whas, + wsi_S1_reqFifo_doResetDeq$whas, + wsi_S1_reqFifo_doResetEnq$whas, + wsi_S1_reqFifo_r_clr$whas, + wsi_S1_reqFifo_r_deq$whas, + wsi_S1_reqFifo_r_enq$whas, + wsi_S1_sThreadBusy_dw$wget, + wsi_S1_sThreadBusy_dw$whas, + wsi_S1_wsiReq$whas; + + // register splitCtrl + reg [31 : 0] splitCtrl; + wire [31 : 0] splitCtrl$D_IN; + wire splitCtrl$EN; + + // register wci_cEdge + reg [2 : 0] wci_cEdge; + wire [2 : 0] wci_cEdge$D_IN; + wire wci_cEdge$EN; + + // register wci_cState + reg [2 : 0] wci_cState; + wire [2 : 0] wci_cState$D_IN; + wire wci_cState$EN; + + // register wci_ctlAckReg + reg wci_ctlAckReg; + wire wci_ctlAckReg$D_IN, wci_ctlAckReg$EN; + + // register wci_ctlOpActive + reg wci_ctlOpActive; + wire wci_ctlOpActive$D_IN, wci_ctlOpActive$EN; + + // register wci_illegalEdge + reg wci_illegalEdge; + wire wci_illegalEdge$D_IN, wci_illegalEdge$EN; + + // register wci_isReset_isInReset + reg wci_isReset_isInReset; + wire wci_isReset_isInReset$D_IN, wci_isReset_isInReset$EN; + + // register wci_nState + reg [2 : 0] wci_nState; + reg [2 : 0] wci_nState$D_IN; + wire wci_nState$EN; + + // register wci_reqF_countReg + reg [1 : 0] wci_reqF_countReg; + wire [1 : 0] wci_reqF_countReg$D_IN; + wire wci_reqF_countReg$EN; + + // register wci_respF_c_r + reg [1 : 0] wci_respF_c_r; + wire [1 : 0] wci_respF_c_r$D_IN; + wire wci_respF_c_r$EN; + + // register wci_respF_q_0 + reg [33 : 0] wci_respF_q_0; + reg [33 : 0] wci_respF_q_0$D_IN; + wire wci_respF_q_0$EN; + + // register wci_respF_q_1 + reg [33 : 0] wci_respF_q_1; + reg [33 : 0] wci_respF_q_1$D_IN; + wire wci_respF_q_1$EN; + + // register wci_sFlagReg + reg wci_sFlagReg; + wire wci_sFlagReg$D_IN, wci_sFlagReg$EN; + + // register wci_sThreadBusy_d + reg wci_sThreadBusy_d; + wire wci_sThreadBusy_d$D_IN, wci_sThreadBusy_d$EN; + + // register wsi_M0_burstKind + reg [1 : 0] wsi_M0_burstKind; + wire [1 : 0] wsi_M0_burstKind$D_IN; + wire wsi_M0_burstKind$EN; + + // register wsi_M0_errorSticky + reg wsi_M0_errorSticky; + wire wsi_M0_errorSticky$D_IN, wsi_M0_errorSticky$EN; + + // register wsi_M0_iMesgCount + reg [31 : 0] wsi_M0_iMesgCount; + wire [31 : 0] wsi_M0_iMesgCount$D_IN; + wire wsi_M0_iMesgCount$EN; + + // register wsi_M0_isReset_isInReset + reg wsi_M0_isReset_isInReset; + wire wsi_M0_isReset_isInReset$D_IN, wsi_M0_isReset_isInReset$EN; + + // register wsi_M0_operateD + reg wsi_M0_operateD; + wire wsi_M0_operateD$D_IN, wsi_M0_operateD$EN; + + // register wsi_M0_pMesgCount + reg [31 : 0] wsi_M0_pMesgCount; + wire [31 : 0] wsi_M0_pMesgCount$D_IN; + wire wsi_M0_pMesgCount$EN; + + // register wsi_M0_peerIsReady + reg wsi_M0_peerIsReady; + wire wsi_M0_peerIsReady$D_IN, wsi_M0_peerIsReady$EN; + + // register wsi_M0_reqFifo_c_r + reg [1 : 0] wsi_M0_reqFifo_c_r; + wire [1 : 0] wsi_M0_reqFifo_c_r$D_IN; + wire wsi_M0_reqFifo_c_r$EN; + + // register wsi_M0_reqFifo_q_0 + reg [312 : 0] wsi_M0_reqFifo_q_0; + reg [312 : 0] wsi_M0_reqFifo_q_0$D_IN; + wire wsi_M0_reqFifo_q_0$EN; + + // register wsi_M0_reqFifo_q_1 + reg [312 : 0] wsi_M0_reqFifo_q_1; + reg [312 : 0] wsi_M0_reqFifo_q_1$D_IN; + wire wsi_M0_reqFifo_q_1$EN; + + // register wsi_M0_sThreadBusy_d + reg wsi_M0_sThreadBusy_d; + wire wsi_M0_sThreadBusy_d$D_IN, wsi_M0_sThreadBusy_d$EN; + + // register wsi_M0_statusR + reg [7 : 0] wsi_M0_statusR; + wire [7 : 0] wsi_M0_statusR$D_IN; + wire wsi_M0_statusR$EN; + + // register wsi_M0_tBusyCount + reg [31 : 0] wsi_M0_tBusyCount; + wire [31 : 0] wsi_M0_tBusyCount$D_IN; + wire wsi_M0_tBusyCount$EN; + + // register wsi_M0_trafficSticky + reg wsi_M0_trafficSticky; + wire wsi_M0_trafficSticky$D_IN, wsi_M0_trafficSticky$EN; + + // register wsi_M1_burstKind + reg [1 : 0] wsi_M1_burstKind; + wire [1 : 0] wsi_M1_burstKind$D_IN; + wire wsi_M1_burstKind$EN; + + // register wsi_M1_errorSticky + reg wsi_M1_errorSticky; + wire wsi_M1_errorSticky$D_IN, wsi_M1_errorSticky$EN; + + // register wsi_M1_iMesgCount + reg [31 : 0] wsi_M1_iMesgCount; + wire [31 : 0] wsi_M1_iMesgCount$D_IN; + wire wsi_M1_iMesgCount$EN; + + // register wsi_M1_isReset_isInReset + reg wsi_M1_isReset_isInReset; + wire wsi_M1_isReset_isInReset$D_IN, wsi_M1_isReset_isInReset$EN; + + // register wsi_M1_operateD + reg wsi_M1_operateD; + wire wsi_M1_operateD$D_IN, wsi_M1_operateD$EN; + + // register wsi_M1_pMesgCount + reg [31 : 0] wsi_M1_pMesgCount; + wire [31 : 0] wsi_M1_pMesgCount$D_IN; + wire wsi_M1_pMesgCount$EN; + + // register wsi_M1_peerIsReady + reg wsi_M1_peerIsReady; + wire wsi_M1_peerIsReady$D_IN, wsi_M1_peerIsReady$EN; + + // register wsi_M1_reqFifo_c_r + reg [1 : 0] wsi_M1_reqFifo_c_r; + wire [1 : 0] wsi_M1_reqFifo_c_r$D_IN; + wire wsi_M1_reqFifo_c_r$EN; + + // register wsi_M1_reqFifo_q_0 + reg [312 : 0] wsi_M1_reqFifo_q_0; + reg [312 : 0] wsi_M1_reqFifo_q_0$D_IN; + wire wsi_M1_reqFifo_q_0$EN; + + // register wsi_M1_reqFifo_q_1 + reg [312 : 0] wsi_M1_reqFifo_q_1; + reg [312 : 0] wsi_M1_reqFifo_q_1$D_IN; + wire wsi_M1_reqFifo_q_1$EN; + + // register wsi_M1_sThreadBusy_d + reg wsi_M1_sThreadBusy_d; + wire wsi_M1_sThreadBusy_d$D_IN, wsi_M1_sThreadBusy_d$EN; + + // register wsi_M1_statusR + reg [7 : 0] wsi_M1_statusR; + wire [7 : 0] wsi_M1_statusR$D_IN; + wire wsi_M1_statusR$EN; + + // register wsi_M1_tBusyCount + reg [31 : 0] wsi_M1_tBusyCount; + wire [31 : 0] wsi_M1_tBusyCount$D_IN; + wire wsi_M1_tBusyCount$EN; + + // register wsi_M1_trafficSticky + reg wsi_M1_trafficSticky; + wire wsi_M1_trafficSticky$D_IN, wsi_M1_trafficSticky$EN; + + // register wsi_S0_burstKind + reg [1 : 0] wsi_S0_burstKind; + wire [1 : 0] wsi_S0_burstKind$D_IN; + wire wsi_S0_burstKind$EN; + + // register wsi_S0_errorSticky + reg wsi_S0_errorSticky; + wire wsi_S0_errorSticky$D_IN, wsi_S0_errorSticky$EN; + + // register wsi_S0_iMesgCount + reg [31 : 0] wsi_S0_iMesgCount; + wire [31 : 0] wsi_S0_iMesgCount$D_IN; + wire wsi_S0_iMesgCount$EN; + + // register wsi_S0_isReset_isInReset + reg wsi_S0_isReset_isInReset; + wire wsi_S0_isReset_isInReset$D_IN, wsi_S0_isReset_isInReset$EN; + + // register wsi_S0_mesgWordLength + reg [11 : 0] wsi_S0_mesgWordLength; + wire [11 : 0] wsi_S0_mesgWordLength$D_IN; + wire wsi_S0_mesgWordLength$EN; + + // register wsi_S0_operateD + reg wsi_S0_operateD; + wire wsi_S0_operateD$D_IN, wsi_S0_operateD$EN; + + // register wsi_S0_pMesgCount + reg [31 : 0] wsi_S0_pMesgCount; + wire [31 : 0] wsi_S0_pMesgCount$D_IN; + wire wsi_S0_pMesgCount$EN; + + // register wsi_S0_peerIsReady + reg wsi_S0_peerIsReady; + wire wsi_S0_peerIsReady$D_IN, wsi_S0_peerIsReady$EN; + + // register wsi_S0_reqFifo_countReg + reg [1 : 0] wsi_S0_reqFifo_countReg; + wire [1 : 0] wsi_S0_reqFifo_countReg$D_IN; + wire wsi_S0_reqFifo_countReg$EN; + + // register wsi_S0_reqFifo_levelsValid + reg wsi_S0_reqFifo_levelsValid; + wire wsi_S0_reqFifo_levelsValid$D_IN, wsi_S0_reqFifo_levelsValid$EN; + + // register wsi_S0_statusR + reg [7 : 0] wsi_S0_statusR; + wire [7 : 0] wsi_S0_statusR$D_IN; + wire wsi_S0_statusR$EN; + + // register wsi_S0_tBusyCount + reg [31 : 0] wsi_S0_tBusyCount; + wire [31 : 0] wsi_S0_tBusyCount$D_IN; + wire wsi_S0_tBusyCount$EN; + + // register wsi_S0_trafficSticky + reg wsi_S0_trafficSticky; + wire wsi_S0_trafficSticky$D_IN, wsi_S0_trafficSticky$EN; + + // register wsi_S0_wordCount + reg [11 : 0] wsi_S0_wordCount; + wire [11 : 0] wsi_S0_wordCount$D_IN; + wire wsi_S0_wordCount$EN; + + // register wsi_S1_burstKind + reg [1 : 0] wsi_S1_burstKind; + wire [1 : 0] wsi_S1_burstKind$D_IN; + wire wsi_S1_burstKind$EN; + + // register wsi_S1_errorSticky + reg wsi_S1_errorSticky; + wire wsi_S1_errorSticky$D_IN, wsi_S1_errorSticky$EN; + + // register wsi_S1_iMesgCount + reg [31 : 0] wsi_S1_iMesgCount; + wire [31 : 0] wsi_S1_iMesgCount$D_IN; + wire wsi_S1_iMesgCount$EN; + + // register wsi_S1_isReset_isInReset + reg wsi_S1_isReset_isInReset; + wire wsi_S1_isReset_isInReset$D_IN, wsi_S1_isReset_isInReset$EN; + + // register wsi_S1_mesgWordLength + reg [11 : 0] wsi_S1_mesgWordLength; + wire [11 : 0] wsi_S1_mesgWordLength$D_IN; + wire wsi_S1_mesgWordLength$EN; + + // register wsi_S1_operateD + reg wsi_S1_operateD; + wire wsi_S1_operateD$D_IN, wsi_S1_operateD$EN; + + // register wsi_S1_pMesgCount + reg [31 : 0] wsi_S1_pMesgCount; + wire [31 : 0] wsi_S1_pMesgCount$D_IN; + wire wsi_S1_pMesgCount$EN; + + // register wsi_S1_peerIsReady + reg wsi_S1_peerIsReady; + wire wsi_S1_peerIsReady$D_IN, wsi_S1_peerIsReady$EN; + + // register wsi_S1_reqFifo_countReg + reg [1 : 0] wsi_S1_reqFifo_countReg; + wire [1 : 0] wsi_S1_reqFifo_countReg$D_IN; + wire wsi_S1_reqFifo_countReg$EN; + + // register wsi_S1_reqFifo_levelsValid + reg wsi_S1_reqFifo_levelsValid; + wire wsi_S1_reqFifo_levelsValid$D_IN, wsi_S1_reqFifo_levelsValid$EN; + + // register wsi_S1_statusR + reg [7 : 0] wsi_S1_statusR; + wire [7 : 0] wsi_S1_statusR$D_IN; + wire wsi_S1_statusR$EN; + + // register wsi_S1_tBusyCount + reg [31 : 0] wsi_S1_tBusyCount; + wire [31 : 0] wsi_S1_tBusyCount$D_IN; + wire wsi_S1_tBusyCount$EN; + + // register wsi_S1_trafficSticky + reg wsi_S1_trafficSticky; + wire wsi_S1_trafficSticky$D_IN, wsi_S1_trafficSticky$EN; + + // register wsi_S1_wordCount + reg [11 : 0] wsi_S1_wordCount; + wire [11 : 0] wsi_S1_wordCount$D_IN; + wire wsi_S1_wordCount$EN; + + // ports of submodule wci_reqF + wire [71 : 0] wci_reqF$D_IN, wci_reqF$D_OUT; + wire wci_reqF$CLR, wci_reqF$DEQ, wci_reqF$EMPTY_N, wci_reqF$ENQ; + + // ports of submodule wsi_S0_reqFifo + wire [312 : 0] wsi_S0_reqFifo$D_IN, wsi_S0_reqFifo$D_OUT; + wire wsi_S0_reqFifo$CLR, + wsi_S0_reqFifo$DEQ, + wsi_S0_reqFifo$EMPTY_N, + wsi_S0_reqFifo$ENQ, + wsi_S0_reqFifo$FULL_N; + + // ports of submodule wsi_S1_reqFifo + wire [312 : 0] wsi_S1_reqFifo$D_IN, wsi_S1_reqFifo$D_OUT; + wire wsi_S1_reqFifo$CLR, + wsi_S1_reqFifo$DEQ, + wsi_S1_reqFifo$EMPTY_N, + wsi_S1_reqFifo$ENQ, + wsi_S1_reqFifo$FULL_N; + + // rule scheduling signals + wire CAN_FIRE_RL_doMessageConsume_S1, + WILL_FIRE_RL_doMessageConsume_S0, + WILL_FIRE_RL_doMessageConsume_S1, + WILL_FIRE_RL_wci_cfrd, + WILL_FIRE_RL_wci_cfwr, + WILL_FIRE_RL_wci_ctl_op_complete, + WILL_FIRE_RL_wci_ctl_op_start, + WILL_FIRE_RL_wci_ctrl_EiI, + WILL_FIRE_RL_wci_ctrl_IsO, + WILL_FIRE_RL_wci_ctrl_OrE, + WILL_FIRE_RL_wci_respF_both, + WILL_FIRE_RL_wci_respF_decCtr, + WILL_FIRE_RL_wci_respF_incCtr, + WILL_FIRE_RL_wsi_M0_reqFifo_both, + WILL_FIRE_RL_wsi_M0_reqFifo_decCtr, + WILL_FIRE_RL_wsi_M0_reqFifo_deq, + WILL_FIRE_RL_wsi_M0_reqFifo_incCtr, + WILL_FIRE_RL_wsi_M1_reqFifo_both, + WILL_FIRE_RL_wsi_M1_reqFifo_decCtr, + WILL_FIRE_RL_wsi_M1_reqFifo_deq, + WILL_FIRE_RL_wsi_M1_reqFifo_incCtr, + WILL_FIRE_RL_wsi_S0_reqFifo_enq, + WILL_FIRE_RL_wsi_S0_reqFifo_reset, + WILL_FIRE_RL_wsi_S1_reqFifo_enq, + WILL_FIRE_RL_wsi_S1_reqFifo_reset; + + // inputs to muxes for submodule ports + reg [33 : 0] MUX_wci_respF_q_0$write_1__VAL_2; + wire [312 : 0] MUX_wsi_M0_reqFifo_q_0$write_1__VAL_1, + MUX_wsi_M0_reqFifo_q_0$write_1__VAL_2, + MUX_wsi_M0_reqFifo_q_1$write_1__VAL_1, + MUX_wsi_M1_reqFifo_q_0$write_1__VAL_1, + MUX_wsi_M1_reqFifo_q_0$write_1__VAL_2, + MUX_wsi_M1_reqFifo_q_1$write_1__VAL_1; + wire [33 : 0] MUX_wci_respF_q_0$write_1__VAL_1, + MUX_wci_respF_q_1$write_1__VAL_1, + MUX_wci_respF_x_wire$wset_1__VAL_1, + MUX_wci_respF_x_wire$wset_1__VAL_2; + wire [1 : 0] MUX_wci_respF_c_r$write_1__VAL_1, + MUX_wci_respF_c_r$write_1__VAL_2, + MUX_wsi_M0_reqFifo_c_r$write_1__VAL_1, + MUX_wsi_M0_reqFifo_c_r$write_1__VAL_2, + MUX_wsi_M1_reqFifo_c_r$write_1__VAL_1, + MUX_wsi_M1_reqFifo_c_r$write_1__VAL_2; + wire MUX_wci_illegalEdge$write_1__SEL_1, + MUX_wci_illegalEdge$write_1__VAL_1, + MUX_wci_respF_q_0$write_1__SEL_2, + MUX_wci_respF_q_1$write_1__SEL_2, + MUX_wsi_M0_reqFifo_q_0$write_1__SEL_2, + MUX_wsi_M0_reqFifo_q_1$write_1__SEL_2, + MUX_wsi_M0_reqFifo_x_wire$wset_1__SEL_1, + MUX_wsi_M1_reqFifo_q_0$write_1__SEL_2, + MUX_wsi_M1_reqFifo_q_1$write_1__SEL_2, + MUX_wsi_M1_reqFifo_x_wire$wset_1__SEL_1; + + // remaining internal signals + reg [63 : 0] v__h16289, v__h16444, v__h3698, v__h3873, v__h4017; + reg [31 : 0] _theResult____h16428; + wire [31 : 0] rdat__h16512, + rdat__h16701, + rdat__h16715, + rdat__h16723, + rdat__h16737, + rdat__h16745, + rdat__h16759, + rdat__h16767, + rdat__h16781; + + // value method wciS0_sResp + assign wciS0_SResp = wci_respF_q_0[33:32] ; + + // value method wciS0_sData + assign wciS0_SData = wci_respF_q_0[31:0] ; + + // value method wciS0_sThreadBusy + assign wciS0_SThreadBusy = + wci_reqF_countReg > 2'd1 || wci_isReset_isInReset ; + + // value method wciS0_sFlag + assign wciS0_SFlag = { 1'd1, wci_sFlagReg } ; + + // value method wsiS0_sThreadBusy + assign wsiS0_SThreadBusy = + !wsi_S0_sThreadBusy_dw$whas || wsi_S0_sThreadBusy_dw$wget ; + + // value method wsiS0_sReset_n + assign wsiS0_SReset_n = !wsi_S0_isReset_isInReset && wsi_S0_operateD ; + + // value method wsiS1_sThreadBusy + assign wsiS1_SThreadBusy = + !wsi_S1_sThreadBusy_dw$whas || wsi_S1_sThreadBusy_dw$wget ; + + // value method wsiS1_sReset_n + assign wsiS1_SReset_n = !wsi_S1_isReset_isInReset && wsi_S1_operateD ; + + // value method wsiM0_mCmd + assign wsiM0_MCmd = + wsi_M0_sThreadBusy_d ? 3'd0 : wsi_M0_reqFifo_q_0[312:310] ; + + // value method wsiM0_mReqLast + assign wsiM0_MReqLast = !wsi_M0_sThreadBusy_d && wsi_M0_reqFifo_q_0[309] ; + + // value method wsiM0_mBurstPrecise + assign wsiM0_MBurstPrecise = + !wsi_M0_sThreadBusy_d && wsi_M0_reqFifo_q_0[308] ; + + // value method wsiM0_mBurstLength + assign wsiM0_MBurstLength = + wsi_M0_sThreadBusy_d ? 12'd0 : wsi_M0_reqFifo_q_0[307:296] ; + + // value method wsiM0_mData + assign wsiM0_MData = wsi_M0_reqFifo_q_0[295:40] ; + + // value method wsiM0_mByteEn + assign wsiM0_MByteEn = wsi_M0_reqFifo_q_0[39:8] ; + + // value method wsiM0_mReqInfo + assign wsiM0_MReqInfo = + wsi_M0_sThreadBusy_d ? 8'd0 : wsi_M0_reqFifo_q_0[7:0] ; + + // value method wsiM0_mReset_n + assign wsiM0_MReset_n = !wsi_M0_isReset_isInReset && wsi_M0_operateD ; + + // value method wsiM1_mCmd + assign wsiM1_MCmd = + wsi_M1_sThreadBusy_d ? 3'd0 : wsi_M1_reqFifo_q_0[312:310] ; + + // value method wsiM1_mReqLast + assign wsiM1_MReqLast = !wsi_M1_sThreadBusy_d && wsi_M1_reqFifo_q_0[309] ; + + // value method wsiM1_mBurstPrecise + assign wsiM1_MBurstPrecise = + !wsi_M1_sThreadBusy_d && wsi_M1_reqFifo_q_0[308] ; + + // value method wsiM1_mBurstLength + assign wsiM1_MBurstLength = + wsi_M1_sThreadBusy_d ? 12'd0 : wsi_M1_reqFifo_q_0[307:296] ; + + // value method wsiM1_mData + assign wsiM1_MData = wsi_M1_reqFifo_q_0[295:40] ; + + // value method wsiM1_mByteEn + assign wsiM1_MByteEn = wsi_M1_reqFifo_q_0[39:8] ; + + // value method wsiM1_mReqInfo + assign wsiM1_MReqInfo = + wsi_M1_sThreadBusy_d ? 8'd0 : wsi_M1_reqFifo_q_0[7:0] ; + + // value method wsiM1_mReset_n + assign wsiM1_MReset_n = !wsi_M1_isReset_isInReset && wsi_M1_operateD ; + + // submodule wci_reqF + SizedFIFO #(.p1width(32'd72), + .p2depth(32'd3), + .p3cntr_width(32'd1), + .guarded(32'd1)) wci_reqF(.RST(wciS0_MReset_n), + .CLK(wciS0_Clk), + .D_IN(wci_reqF$D_IN), + .ENQ(wci_reqF$ENQ), + .DEQ(wci_reqF$DEQ), + .CLR(wci_reqF$CLR), + .D_OUT(wci_reqF$D_OUT), + .FULL_N(), + .EMPTY_N(wci_reqF$EMPTY_N)); + + // submodule wsi_S0_reqFifo + SizedFIFO #(.p1width(32'd313), + .p2depth(32'd3), + .p3cntr_width(32'd1), + .guarded(32'd1)) wsi_S0_reqFifo(.RST(wciS0_MReset_n), + .CLK(wciS0_Clk), + .D_IN(wsi_S0_reqFifo$D_IN), + .ENQ(wsi_S0_reqFifo$ENQ), + .DEQ(wsi_S0_reqFifo$DEQ), + .CLR(wsi_S0_reqFifo$CLR), + .D_OUT(wsi_S0_reqFifo$D_OUT), + .FULL_N(wsi_S0_reqFifo$FULL_N), + .EMPTY_N(wsi_S0_reqFifo$EMPTY_N)); + + // submodule wsi_S1_reqFifo + SizedFIFO #(.p1width(32'd313), + .p2depth(32'd3), + .p3cntr_width(32'd1), + .guarded(32'd1)) wsi_S1_reqFifo(.RST(wciS0_MReset_n), + .CLK(wciS0_Clk), + .D_IN(wsi_S1_reqFifo$D_IN), + .ENQ(wsi_S1_reqFifo$ENQ), + .DEQ(wsi_S1_reqFifo$DEQ), + .CLR(wsi_S1_reqFifo$CLR), + .D_OUT(wsi_S1_reqFifo$D_OUT), + .FULL_N(wsi_S1_reqFifo$FULL_N), + .EMPTY_N(wsi_S1_reqFifo$EMPTY_N)); + + // rule RL_wci_ctl_op_start + assign WILL_FIRE_RL_wci_ctl_op_start = + wci_reqF$EMPTY_N && wci_wci_ctrl_pw$whas && + !WILL_FIRE_RL_wci_ctl_op_complete ; + + // rule RL_wci_ctrl_EiI + assign WILL_FIRE_RL_wci_ctrl_EiI = + wci_wci_ctrl_pw$whas && WILL_FIRE_RL_wci_ctl_op_start && + wci_cState == 3'd0 && + wci_reqF$D_OUT[36:34] == 3'd0 ; + + // rule RL_wci_ctrl_IsO + assign WILL_FIRE_RL_wci_ctrl_IsO = + wci_wci_ctrl_pw$whas && WILL_FIRE_RL_wci_ctl_op_start && + wci_cState == 3'd1 && + wci_reqF$D_OUT[36:34] == 3'd1 ; + + // rule RL_wci_ctrl_OrE + assign WILL_FIRE_RL_wci_ctrl_OrE = + wci_wci_ctrl_pw$whas && WILL_FIRE_RL_wci_ctl_op_start && + wci_cState == 3'd2 && + wci_reqF$D_OUT[36:34] == 3'd3 ; + + // rule RL_doMessageConsume_S0 + assign WILL_FIRE_RL_doMessageConsume_S0 = + wsi_S0_reqFifo$EMPTY_N && + (splitCtrl[0] || splitCtrl[7] || wsi_M0_reqFifo_c_r != 2'd2) && + (splitCtrl[8] || splitCtrl[15] || wsi_M1_reqFifo_c_r != 2'd2) && + wci_cState == 3'd2 ; + + // rule RL_doMessageConsume_S1 + assign CAN_FIRE_RL_doMessageConsume_S1 = + wsi_S1_reqFifo$EMPTY_N && + (!splitCtrl[0] || splitCtrl[7] || wsi_M0_reqFifo_c_r != 2'd2) && + (!splitCtrl[8] || splitCtrl[15] || wsi_M1_reqFifo_c_r != 2'd2) && + wci_cState == 3'd2 ; + assign WILL_FIRE_RL_doMessageConsume_S1 = + CAN_FIRE_RL_doMessageConsume_S1 && + !WILL_FIRE_RL_doMessageConsume_S0 ; + + // rule RL_wci_cfwr + assign WILL_FIRE_RL_wci_cfwr = + wci_respF_c_r != 2'd2 && wci_reqF$EMPTY_N && + wci_wci_cfwr_pw$whas && + !WILL_FIRE_RL_wci_ctl_op_start && + !WILL_FIRE_RL_wci_ctl_op_complete ; + + // rule RL_wci_ctl_op_complete + assign WILL_FIRE_RL_wci_ctl_op_complete = + wci_respF_c_r != 2'd2 && wci_ctlOpActive && wci_ctlAckReg ; + + // rule RL_wsi_M0_reqFifo_deq + assign WILL_FIRE_RL_wsi_M0_reqFifo_deq = + wsi_M0_reqFifo_c_r != 2'd0 && !wsi_M0_sThreadBusy_d ; + + // rule RL_wsi_M0_reqFifo_incCtr + assign WILL_FIRE_RL_wsi_M0_reqFifo_incCtr = + ((wsi_M0_reqFifo_c_r == 2'd0) ? + wsi_M0_reqFifo_enqueueing$whas : + wsi_M0_reqFifo_c_r != 2'd1 || + wsi_M0_reqFifo_enqueueing$whas) && + wsi_M0_reqFifo_enqueueing$whas && + !WILL_FIRE_RL_wsi_M0_reqFifo_deq ; + + // rule RL_wsi_M0_reqFifo_decCtr + assign WILL_FIRE_RL_wsi_M0_reqFifo_decCtr = + WILL_FIRE_RL_wsi_M0_reqFifo_deq && + !wsi_M0_reqFifo_enqueueing$whas ; + + // rule RL_wsi_M0_reqFifo_both + assign WILL_FIRE_RL_wsi_M0_reqFifo_both = + ((wsi_M0_reqFifo_c_r == 2'd1) ? + wsi_M0_reqFifo_enqueueing$whas : + wsi_M0_reqFifo_c_r != 2'd2 || + wsi_M0_reqFifo_enqueueing$whas) && + WILL_FIRE_RL_wsi_M0_reqFifo_deq && + wsi_M0_reqFifo_enqueueing$whas ; + + // rule RL_wci_cfrd + assign WILL_FIRE_RL_wci_cfrd = + wci_respF_c_r != 2'd2 && wci_reqF$EMPTY_N && + wci_wci_cfrd_pw$whas && + !WILL_FIRE_RL_wci_ctl_op_start && + !WILL_FIRE_RL_wci_ctl_op_complete ; + + // rule RL_wci_respF_incCtr + assign WILL_FIRE_RL_wci_respF_incCtr = + ((wci_respF_c_r == 2'd0) ? + wci_respF_enqueueing$whas : + wci_respF_c_r != 2'd1 || wci_respF_enqueueing$whas) && + wci_respF_enqueueing$whas && + !(wci_respF_c_r != 2'd0) ; + + // rule RL_wci_respF_decCtr + assign WILL_FIRE_RL_wci_respF_decCtr = + wci_respF_c_r != 2'd0 && !wci_respF_enqueueing$whas ; + + // rule RL_wci_respF_both + assign WILL_FIRE_RL_wci_respF_both = + ((wci_respF_c_r == 2'd1) ? + wci_respF_enqueueing$whas : + wci_respF_c_r != 2'd2 || wci_respF_enqueueing$whas) && + wci_respF_c_r != 2'd0 && + wci_respF_enqueueing$whas ; + + // rule RL_wsi_M1_reqFifo_deq + assign WILL_FIRE_RL_wsi_M1_reqFifo_deq = + wsi_M1_reqFifo_c_r != 2'd0 && !wsi_M1_sThreadBusy_d ; + + // rule RL_wsi_M1_reqFifo_incCtr + assign WILL_FIRE_RL_wsi_M1_reqFifo_incCtr = + ((wsi_M1_reqFifo_c_r == 2'd0) ? + wsi_M1_reqFifo_enqueueing$whas : + wsi_M1_reqFifo_c_r != 2'd1 || + wsi_M1_reqFifo_enqueueing$whas) && + wsi_M1_reqFifo_enqueueing$whas && + !WILL_FIRE_RL_wsi_M1_reqFifo_deq ; + + // rule RL_wsi_M1_reqFifo_decCtr + assign WILL_FIRE_RL_wsi_M1_reqFifo_decCtr = + WILL_FIRE_RL_wsi_M1_reqFifo_deq && + !wsi_M1_reqFifo_enqueueing$whas ; + + // rule RL_wsi_M1_reqFifo_both + assign WILL_FIRE_RL_wsi_M1_reqFifo_both = + ((wsi_M1_reqFifo_c_r == 2'd1) ? + wsi_M1_reqFifo_enqueueing$whas : + wsi_M1_reqFifo_c_r != 2'd2 || + wsi_M1_reqFifo_enqueueing$whas) && + WILL_FIRE_RL_wsi_M1_reqFifo_deq && + wsi_M1_reqFifo_enqueueing$whas ; + + // rule RL_wsi_S0_reqFifo_enq + assign WILL_FIRE_RL_wsi_S0_reqFifo_enq = + wsi_S0_reqFifo$FULL_N && wsi_S0_operateD && wsi_S0_peerIsReady && + wsi_S0_wsiReq$wget[312:310] == 3'd1 ; + + // rule RL_wsi_S0_reqFifo_reset + assign WILL_FIRE_RL_wsi_S0_reqFifo_reset = + WILL_FIRE_RL_wsi_S0_reqFifo_enq || + WILL_FIRE_RL_doMessageConsume_S0 ; + + // rule RL_wsi_S1_reqFifo_enq + assign WILL_FIRE_RL_wsi_S1_reqFifo_enq = + wsi_S1_reqFifo$FULL_N && wsi_S1_operateD && wsi_S1_peerIsReady && + wsi_S1_wsiReq$wget[312:310] == 3'd1 ; + + // rule RL_wsi_S1_reqFifo_reset + assign WILL_FIRE_RL_wsi_S1_reqFifo_reset = + WILL_FIRE_RL_wsi_S1_reqFifo_enq || + WILL_FIRE_RL_doMessageConsume_S1 ; + + // inputs to muxes for submodule ports + assign MUX_wci_illegalEdge$write_1__SEL_1 = + WILL_FIRE_RL_wci_ctl_op_start && + (wci_reqF$D_OUT[36:34] == 3'd0 && wci_cState != 3'd0 || + wci_reqF$D_OUT[36:34] == 3'd1 && wci_cState != 3'd1 && + wci_cState != 3'd3 || + wci_reqF$D_OUT[36:34] == 3'd2 && wci_cState != 3'd2 || + wci_reqF$D_OUT[36:34] == 3'd3 && wci_cState != 3'd3 && + wci_cState != 3'd2 && + wci_cState != 3'd1 || + wci_reqF$D_OUT[36:34] == 3'd4 || + wci_reqF$D_OUT[36:34] == 3'd5 || + wci_reqF$D_OUT[36:34] == 3'd6 || + wci_reqF$D_OUT[36:34] == 3'd7) ; + assign MUX_wci_respF_q_0$write_1__SEL_2 = + WILL_FIRE_RL_wci_respF_incCtr && wci_respF_c_r == 2'd0 ; + assign MUX_wci_respF_q_1$write_1__SEL_2 = + WILL_FIRE_RL_wci_respF_incCtr && wci_respF_c_r == 2'd1 ; + assign MUX_wsi_M0_reqFifo_q_0$write_1__SEL_2 = + WILL_FIRE_RL_wsi_M0_reqFifo_incCtr && + wsi_M0_reqFifo_c_r == 2'd0 ; + assign MUX_wsi_M0_reqFifo_q_1$write_1__SEL_2 = + WILL_FIRE_RL_wsi_M0_reqFifo_incCtr && + wsi_M0_reqFifo_c_r == 2'd1 ; + assign MUX_wsi_M0_reqFifo_x_wire$wset_1__SEL_1 = + WILL_FIRE_RL_doMessageConsume_S0 && !splitCtrl[0] && + !splitCtrl[7] ; + assign MUX_wsi_M1_reqFifo_q_0$write_1__SEL_2 = + WILL_FIRE_RL_wsi_M1_reqFifo_incCtr && + wsi_M1_reqFifo_c_r == 2'd0 ; + assign MUX_wsi_M1_reqFifo_q_1$write_1__SEL_2 = + WILL_FIRE_RL_wsi_M1_reqFifo_incCtr && + wsi_M1_reqFifo_c_r == 2'd1 ; + assign MUX_wsi_M1_reqFifo_x_wire$wset_1__SEL_1 = + WILL_FIRE_RL_doMessageConsume_S0 && !splitCtrl[8] && + !splitCtrl[15] ; + assign MUX_wci_illegalEdge$write_1__VAL_1 = + wci_reqF$D_OUT[36:34] != 3'd4 && wci_reqF$D_OUT[36:34] != 3'd5 && + wci_reqF$D_OUT[36:34] != 3'd6 ; + assign MUX_wci_respF_c_r$write_1__VAL_1 = wci_respF_c_r + 2'd1 ; + assign MUX_wci_respF_c_r$write_1__VAL_2 = wci_respF_c_r - 2'd1 ; + assign MUX_wci_respF_q_0$write_1__VAL_1 = + (wci_respF_c_r == 2'd1) ? + MUX_wci_respF_q_0$write_1__VAL_2 : + wci_respF_q_1 ; + always@(WILL_FIRE_RL_wci_ctl_op_complete or + MUX_wci_respF_x_wire$wset_1__VAL_1 or + WILL_FIRE_RL_wci_cfrd or + MUX_wci_respF_x_wire$wset_1__VAL_2 or WILL_FIRE_RL_wci_cfwr) + begin + case (1'b1) // synopsys parallel_case + WILL_FIRE_RL_wci_ctl_op_complete: + MUX_wci_respF_q_0$write_1__VAL_2 = + MUX_wci_respF_x_wire$wset_1__VAL_1; + WILL_FIRE_RL_wci_cfrd: + MUX_wci_respF_q_0$write_1__VAL_2 = + MUX_wci_respF_x_wire$wset_1__VAL_2; + WILL_FIRE_RL_wci_cfwr: MUX_wci_respF_q_0$write_1__VAL_2 = 34'h1C0DE4201; + default: MUX_wci_respF_q_0$write_1__VAL_2 = + 34'h2AAAAAAAA /* unspecified value */ ; + endcase + end + assign MUX_wci_respF_q_1$write_1__VAL_1 = + (wci_respF_c_r == 2'd2) ? + MUX_wci_respF_q_0$write_1__VAL_2 : + 34'h0AAAAAAAA ; + assign MUX_wci_respF_x_wire$wset_1__VAL_1 = + wci_illegalEdge ? 34'h3C0DE4202 : 34'h1C0DE4201 ; + assign MUX_wci_respF_x_wire$wset_1__VAL_2 = { 2'd1, _theResult____h16428 } ; + assign MUX_wsi_M0_reqFifo_c_r$write_1__VAL_1 = wsi_M0_reqFifo_c_r + 2'd1 ; + assign MUX_wsi_M0_reqFifo_c_r$write_1__VAL_2 = wsi_M0_reqFifo_c_r - 2'd1 ; + assign MUX_wsi_M0_reqFifo_q_0$write_1__VAL_1 = + (wsi_M0_reqFifo_c_r == 2'd1) ? + MUX_wsi_M0_reqFifo_q_0$write_1__VAL_2 : + wsi_M0_reqFifo_q_1 ; + assign MUX_wsi_M0_reqFifo_q_0$write_1__VAL_2 = + MUX_wsi_M0_reqFifo_x_wire$wset_1__SEL_1 ? + wsi_S0_reqFifo$D_OUT : + wsi_S1_reqFifo$D_OUT ; + assign MUX_wsi_M0_reqFifo_q_1$write_1__VAL_1 = + (wsi_M0_reqFifo_c_r == 2'd2) ? + MUX_wsi_M0_reqFifo_q_0$write_1__VAL_2 : + 313'h00000AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA00 ; + assign MUX_wsi_M1_reqFifo_c_r$write_1__VAL_1 = wsi_M1_reqFifo_c_r + 2'd1 ; + assign MUX_wsi_M1_reqFifo_c_r$write_1__VAL_2 = wsi_M1_reqFifo_c_r - 2'd1 ; + assign MUX_wsi_M1_reqFifo_q_0$write_1__VAL_1 = + (wsi_M1_reqFifo_c_r == 2'd1) ? + MUX_wsi_M1_reqFifo_q_0$write_1__VAL_2 : + wsi_M1_reqFifo_q_1 ; + assign MUX_wsi_M1_reqFifo_q_0$write_1__VAL_2 = + MUX_wsi_M1_reqFifo_x_wire$wset_1__SEL_1 ? + wsi_S0_reqFifo$D_OUT : + wsi_S1_reqFifo$D_OUT ; + assign MUX_wsi_M1_reqFifo_q_1$write_1__VAL_1 = + (wsi_M1_reqFifo_c_r == 2'd2) ? + MUX_wsi_M1_reqFifo_q_0$write_1__VAL_2 : + 313'h00000AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA00 ; + + // inlined wires + assign wci_wciReq$wget = + { wciS0_MCmd, + wciS0_MAddrSpace, + wciS0_MByteEn, + wciS0_MAddr, + wciS0_MData } ; + assign wci_wciReq$whas = 1'd1 ; + assign wci_respF_x_wire$wget = MUX_wci_respF_q_0$write_1__VAL_2 ; + assign wci_respF_x_wire$whas = wci_respF_enqueueing$whas ; + assign wci_wEdge$wget = wci_reqF$D_OUT[36:34] ; + assign wci_wEdge$whas = WILL_FIRE_RL_wci_ctl_op_start ; + assign wci_sFlagReg_1$wget = 1'b0 ; + assign wci_sFlagReg_1$whas = 1'b0 ; + assign wci_ctlAckReg_1$wget = 1'd1 ; + assign wci_ctlAckReg_1$whas = + WILL_FIRE_RL_wci_ctrl_OrE || WILL_FIRE_RL_wci_ctrl_IsO || + WILL_FIRE_RL_wci_ctrl_EiI ; + assign wsi_S0_wsiReq$wget = + { wsiS0_MCmd, + wsiS0_MReqLast, + wsiS0_MBurstPrecise, + wsiS0_MBurstLength, + wsiS0_MData, + wsiS0_MByteEn, + wsiS0_MReqInfo } ; + assign wsi_S0_wsiReq$whas = 1'd1 ; + assign wsi_S0_operateD_1$wget = 1'd1 ; + assign wsi_S0_operateD_1$whas = wci_cState == 3'd2 ; + assign wsi_S0_peerIsReady_1$wget = 1'd1 ; + assign wsi_S0_peerIsReady_1$whas = wsiS0_MReset_n ; + assign wsi_S0_sThreadBusy_dw$wget = wsi_S0_reqFifo_countReg > 2'd1 ; + assign wsi_S0_sThreadBusy_dw$whas = + wsi_S0_reqFifo_levelsValid && wsi_S0_operateD && + wsi_S0_peerIsReady ; + assign wsi_S1_wsiReq$wget = + { wsiS1_MCmd, + wsiS1_MReqLast, + wsiS1_MBurstPrecise, + wsiS1_MBurstLength, + wsiS1_MData, + wsiS1_MByteEn, + wsiS1_MReqInfo } ; + assign wsi_S1_wsiReq$whas = 1'd1 ; + assign wsi_S1_operateD_1$wget = 1'd1 ; + assign wsi_S1_operateD_1$whas = wci_cState == 3'd2 ; + assign wsi_S1_peerIsReady_1$wget = 1'd1 ; + assign wsi_S1_peerIsReady_1$whas = wsiS1_MReset_n ; + assign wsi_S1_sThreadBusy_dw$wget = wsi_S1_reqFifo_countReg > 2'd1 ; + assign wsi_S1_sThreadBusy_dw$whas = + wsi_S1_reqFifo_levelsValid && wsi_S1_operateD && + wsi_S1_peerIsReady ; + assign wsi_M0_reqFifo_x_wire$wget = MUX_wsi_M0_reqFifo_q_0$write_1__VAL_2 ; + assign wsi_M0_reqFifo_x_wire$whas = wsi_M0_reqFifo_enqueueing$whas ; + assign wsi_M0_operateD_1$wget = 1'd1 ; + assign wsi_M0_operateD_1$whas = wci_cState == 3'd2 ; + assign wsi_M0_peerIsReady_1$wget = 1'd1 ; + assign wsi_M0_peerIsReady_1$whas = wsiM0_SReset_n ; + assign wsi_M1_reqFifo_x_wire$wget = MUX_wsi_M1_reqFifo_q_0$write_1__VAL_2 ; + assign wsi_M1_reqFifo_x_wire$whas = wsi_M1_reqFifo_enqueueing$whas ; + assign wsi_M1_operateD_1$wget = 1'd1 ; + assign wsi_M1_operateD_1$whas = wci_cState == 3'd2 ; + assign wsi_M1_peerIsReady_1$wget = 1'd1 ; + assign wsi_M1_peerIsReady_1$whas = wsiM1_SReset_n ; + assign wci_Es_mCmd_w$wget = wciS0_MCmd ; + assign wci_Es_mCmd_w$whas = 1'd1 ; + assign wci_Es_mAddrSpace_w$wget = wciS0_MAddrSpace ; + assign wci_Es_mAddrSpace_w$whas = 1'd1 ; + assign wci_Es_mByteEn_w$wget = wciS0_MByteEn ; + assign wci_Es_mByteEn_w$whas = 1'd1 ; + assign wci_Es_mAddr_w$wget = wciS0_MAddr ; + assign wci_Es_mAddr_w$whas = 1'd1 ; + assign wci_Es_mData_w$wget = wciS0_MData ; + assign wci_Es_mData_w$whas = 1'd1 ; + assign wsi_Es0_mCmd_w$wget = wsiS0_MCmd ; + assign wsi_Es0_mCmd_w$whas = 1'd1 ; + assign wsi_Es0_mBurstLength_w$wget = wsiS0_MBurstLength ; + assign wsi_Es0_mBurstLength_w$whas = 1'd1 ; + assign wsi_Es0_mData_w$wget = wsiS0_MData ; + assign wsi_Es0_mData_w$whas = 1'd1 ; + assign wsi_Es0_mByteEn_w$wget = wsiS0_MByteEn ; + assign wsi_Es0_mByteEn_w$whas = 1'd1 ; + assign wsi_Es0_mReqInfo_w$wget = wsiS0_MReqInfo ; + assign wsi_Es0_mReqInfo_w$whas = 1'd1 ; + assign wsi_Es1_mCmd_w$wget = wsiS1_MCmd ; + assign wsi_Es1_mCmd_w$whas = 1'd1 ; + assign wsi_Es1_mBurstLength_w$wget = wsiS1_MBurstLength ; + assign wsi_Es1_mBurstLength_w$whas = 1'd1 ; + assign wsi_Es1_mData_w$wget = wsiS1_MData ; + assign wsi_Es1_mData_w$whas = 1'd1 ; + assign wsi_Es1_mByteEn_w$wget = wsiS1_MByteEn ; + assign wsi_Es1_mByteEn_w$whas = 1'd1 ; + assign wsi_Es1_mReqInfo_w$wget = wsiS1_MReqInfo ; + assign wsi_Es1_mReqInfo_w$whas = 1'd1 ; + assign wci_reqF_r_enq$whas = wci_wciReq$wget[71:69] != 3'd0 ; + assign wci_reqF_r_deq$whas = + WILL_FIRE_RL_wci_ctl_op_start || WILL_FIRE_RL_wci_cfrd || + WILL_FIRE_RL_wci_cfwr ; + assign wci_reqF_r_clr$whas = 1'b0 ; + assign wci_respF_enqueueing$whas = + WILL_FIRE_RL_wci_ctl_op_complete || WILL_FIRE_RL_wci_cfrd || + WILL_FIRE_RL_wci_cfwr ; + assign wci_respF_dequeueing$whas = wci_respF_c_r != 2'd0 ; + assign wci_sThreadBusy_pw$whas = 1'b0 ; + assign wci_wci_cfwr_pw$whas = + wci_reqF$EMPTY_N && wci_reqF$D_OUT[68] && + wci_reqF$D_OUT[71:69] == 3'd1 ; + assign wci_wci_cfrd_pw$whas = + wci_reqF$EMPTY_N && wci_reqF$D_OUT[68] && + wci_reqF$D_OUT[71:69] == 3'd2 ; + assign wci_wci_ctrl_pw$whas = + wci_reqF$EMPTY_N && !wci_reqF$D_OUT[68] && + wci_reqF$D_OUT[71:69] == 3'd2 ; + assign wsi_S0_reqFifo_r_enq$whas = WILL_FIRE_RL_wsi_S0_reqFifo_enq ; + assign wsi_S0_reqFifo_r_deq$whas = WILL_FIRE_RL_doMessageConsume_S0 ; + assign wsi_S0_reqFifo_r_clr$whas = 1'b0 ; + assign wsi_S0_reqFifo_doResetEnq$whas = WILL_FIRE_RL_wsi_S0_reqFifo_enq ; + assign wsi_S0_reqFifo_doResetDeq$whas = WILL_FIRE_RL_doMessageConsume_S0 ; + assign wsi_S0_reqFifo_doResetClr$whas = 1'b0 ; + assign wsi_S1_reqFifo_r_enq$whas = WILL_FIRE_RL_wsi_S1_reqFifo_enq ; + assign wsi_S1_reqFifo_r_deq$whas = WILL_FIRE_RL_doMessageConsume_S1 ; + assign wsi_S1_reqFifo_r_clr$whas = 1'b0 ; + assign wsi_S1_reqFifo_doResetEnq$whas = WILL_FIRE_RL_wsi_S1_reqFifo_enq ; + assign wsi_S1_reqFifo_doResetDeq$whas = WILL_FIRE_RL_doMessageConsume_S1 ; + assign wsi_S1_reqFifo_doResetClr$whas = 1'b0 ; + assign wsi_M0_reqFifo_enqueueing$whas = + WILL_FIRE_RL_doMessageConsume_S0 && !splitCtrl[0] && + !splitCtrl[7] || + WILL_FIRE_RL_doMessageConsume_S1 && splitCtrl[0] && + !splitCtrl[7] ; + assign wsi_M0_reqFifo_dequeueing$whas = WILL_FIRE_RL_wsi_M0_reqFifo_deq ; + assign wsi_M0_sThreadBusy_pw$whas = wsiM0_SThreadBusy ; + assign wsi_M1_reqFifo_enqueueing$whas = + WILL_FIRE_RL_doMessageConsume_S0 && !splitCtrl[8] && + !splitCtrl[15] || + WILL_FIRE_RL_doMessageConsume_S1 && splitCtrl[8] && + !splitCtrl[15] ; + assign wsi_M1_reqFifo_dequeueing$whas = WILL_FIRE_RL_wsi_M1_reqFifo_deq ; + assign wsi_M1_sThreadBusy_pw$whas = wsiM1_SThreadBusy ; + assign wsi_Es0_mReqLast_w$whas = wsiS0_MReqLast ; + assign wsi_Es0_mBurstPrecise_w$whas = wsiS0_MBurstPrecise ; + assign wsi_Es0_mDataInfo_w$whas = 1'd1 ; + assign wsi_Es1_mReqLast_w$whas = wsiS1_MReqLast ; + assign wsi_Es1_mBurstPrecise_w$whas = wsiS1_MBurstPrecise ; + assign wsi_Es1_mDataInfo_w$whas = 1'd1 ; + assign wsi_S0_extStatusW$wget = + { wsi_S0_pMesgCount, wsi_S0_iMesgCount, wsi_S0_tBusyCount } ; + assign wsi_S1_extStatusW$wget = + { wsi_S1_pMesgCount, wsi_S1_iMesgCount, wsi_S1_tBusyCount } ; + assign wsi_M0_extStatusW$wget = + { wsi_M0_pMesgCount, wsi_M0_iMesgCount, wsi_M0_tBusyCount } ; + assign wsi_M1_extStatusW$wget = + { wsi_M1_pMesgCount, wsi_M1_iMesgCount, wsi_M1_tBusyCount } ; + + // register splitCtrl + assign splitCtrl$D_IN = wci_reqF$D_OUT[31:0] ; + assign splitCtrl$EN = + WILL_FIRE_RL_wci_cfwr && wci_reqF$D_OUT[39:32] == 8'h04 ; + + // register wci_cEdge + assign wci_cEdge$D_IN = wci_reqF$D_OUT[36:34] ; + assign wci_cEdge$EN = WILL_FIRE_RL_wci_ctl_op_start ; + + // register wci_cState + assign wci_cState$D_IN = wci_nState ; + assign wci_cState$EN = + WILL_FIRE_RL_wci_ctl_op_complete && !wci_illegalEdge ; + + // register wci_ctlAckReg + assign wci_ctlAckReg$D_IN = wci_ctlAckReg_1$whas ; + assign wci_ctlAckReg$EN = 1'd1 ; + + // register wci_ctlOpActive + assign wci_ctlOpActive$D_IN = !WILL_FIRE_RL_wci_ctl_op_complete ; + assign wci_ctlOpActive$EN = + WILL_FIRE_RL_wci_ctl_op_complete || + WILL_FIRE_RL_wci_ctl_op_start ; + + // register wci_illegalEdge + assign wci_illegalEdge$D_IN = + MUX_wci_illegalEdge$write_1__SEL_1 && + MUX_wci_illegalEdge$write_1__VAL_1 ; + assign wci_illegalEdge$EN = + MUX_wci_illegalEdge$write_1__SEL_1 || + WILL_FIRE_RL_wci_ctl_op_complete && wci_illegalEdge ; + + // register wci_isReset_isInReset + assign wci_isReset_isInReset$D_IN = 1'd0 ; + assign wci_isReset_isInReset$EN = wci_isReset_isInReset ; + + // register wci_nState + always@(wci_reqF$D_OUT) + begin + case (wci_reqF$D_OUT[36:34]) + 3'd0: wci_nState$D_IN = 3'd1; + 3'd1: wci_nState$D_IN = 3'd2; + 3'd2: wci_nState$D_IN = 3'd3; + default: wci_nState$D_IN = 3'd0; + endcase + end + assign wci_nState$EN = + WILL_FIRE_RL_wci_ctl_op_start && + (wci_reqF$D_OUT[36:34] == 3'd0 && wci_cState == 3'd0 || + wci_reqF$D_OUT[36:34] == 3'd1 && + (wci_cState == 3'd1 || wci_cState == 3'd3) || + wci_reqF$D_OUT[36:34] == 3'd2 && wci_cState == 3'd2 || + wci_reqF$D_OUT[36:34] == 3'd3 && + (wci_cState == 3'd3 || wci_cState == 3'd2 || + wci_cState == 3'd1)) ; + + // register wci_reqF_countReg + assign wci_reqF_countReg$D_IN = + (wci_wciReq$wget[71:69] != 3'd0) ? + wci_reqF_countReg + 2'd1 : + wci_reqF_countReg - 2'd1 ; + assign wci_reqF_countReg$EN = + (wci_wciReq$wget[71:69] != 3'd0) != wci_reqF_r_deq$whas ; + + // register wci_respF_c_r + assign wci_respF_c_r$D_IN = + WILL_FIRE_RL_wci_respF_incCtr ? + MUX_wci_respF_c_r$write_1__VAL_1 : + MUX_wci_respF_c_r$write_1__VAL_2 ; + assign wci_respF_c_r$EN = + WILL_FIRE_RL_wci_respF_incCtr || WILL_FIRE_RL_wci_respF_decCtr ; + + // register wci_respF_q_0 + always@(WILL_FIRE_RL_wci_respF_both or + MUX_wci_respF_q_0$write_1__VAL_1 or + MUX_wci_respF_q_0$write_1__SEL_2 or + MUX_wci_respF_q_0$write_1__VAL_2 or + WILL_FIRE_RL_wci_respF_decCtr or wci_respF_q_1) + begin + case (1'b1) // synopsys parallel_case + WILL_FIRE_RL_wci_respF_both: + wci_respF_q_0$D_IN = MUX_wci_respF_q_0$write_1__VAL_1; + MUX_wci_respF_q_0$write_1__SEL_2: + wci_respF_q_0$D_IN = MUX_wci_respF_q_0$write_1__VAL_2; + WILL_FIRE_RL_wci_respF_decCtr: wci_respF_q_0$D_IN = wci_respF_q_1; + default: wci_respF_q_0$D_IN = 34'h2AAAAAAAA /* unspecified value */ ; + endcase + end + assign wci_respF_q_0$EN = + WILL_FIRE_RL_wci_respF_both || + WILL_FIRE_RL_wci_respF_incCtr && wci_respF_c_r == 2'd0 || + WILL_FIRE_RL_wci_respF_decCtr ; + + // register wci_respF_q_1 + always@(WILL_FIRE_RL_wci_respF_both or + MUX_wci_respF_q_1$write_1__VAL_1 or + MUX_wci_respF_q_1$write_1__SEL_2 or + MUX_wci_respF_q_0$write_1__VAL_2 or WILL_FIRE_RL_wci_respF_decCtr) + begin + case (1'b1) // synopsys parallel_case + WILL_FIRE_RL_wci_respF_both: + wci_respF_q_1$D_IN = MUX_wci_respF_q_1$write_1__VAL_1; + MUX_wci_respF_q_1$write_1__SEL_2: + wci_respF_q_1$D_IN = MUX_wci_respF_q_0$write_1__VAL_2; + WILL_FIRE_RL_wci_respF_decCtr: wci_respF_q_1$D_IN = 34'h0AAAAAAAA; + default: wci_respF_q_1$D_IN = 34'h2AAAAAAAA /* unspecified value */ ; + endcase + end + assign wci_respF_q_1$EN = + WILL_FIRE_RL_wci_respF_both || + WILL_FIRE_RL_wci_respF_incCtr && wci_respF_c_r == 2'd1 || + WILL_FIRE_RL_wci_respF_decCtr ; + + // register wci_sFlagReg + assign wci_sFlagReg$D_IN = 1'b0 ; + assign wci_sFlagReg$EN = 1'd1 ; + + // register wci_sThreadBusy_d + assign wci_sThreadBusy_d$D_IN = 1'b0 ; + assign wci_sThreadBusy_d$EN = 1'd1 ; + + // register wsi_M0_burstKind + assign wsi_M0_burstKind$D_IN = + (wsi_M0_burstKind == 2'd0) ? + (wsi_M0_reqFifo_q_0[308] ? 2'd1 : 2'd2) : + 2'd0 ; + assign wsi_M0_burstKind$EN = + WILL_FIRE_RL_wsi_M0_reqFifo_deq && + wsi_M0_reqFifo_q_0[312:310] == 3'd1 && + (wsi_M0_burstKind == 2'd0 || + (wsi_M0_burstKind == 2'd1 || wsi_M0_burstKind == 2'd2) && + wsi_M0_reqFifo_q_0[309]) ; + + // register wsi_M0_errorSticky + assign wsi_M0_errorSticky$D_IN = 1'b0 ; + assign wsi_M0_errorSticky$EN = 1'b0 ; + + // register wsi_M0_iMesgCount + assign wsi_M0_iMesgCount$D_IN = wsi_M0_iMesgCount + 32'd1 ; + assign wsi_M0_iMesgCount$EN = + WILL_FIRE_RL_wsi_M0_reqFifo_deq && + wsi_M0_reqFifo_q_0[312:310] == 3'd1 && + wsi_M0_burstKind == 2'd2 && + wsi_M0_reqFifo_q_0[309] ; + + // register wsi_M0_isReset_isInReset + assign wsi_M0_isReset_isInReset$D_IN = 1'd0 ; + assign wsi_M0_isReset_isInReset$EN = wsi_M0_isReset_isInReset ; + + // register wsi_M0_operateD + assign wsi_M0_operateD$D_IN = wci_cState == 3'd2 ; + assign wsi_M0_operateD$EN = 1'd1 ; + + // register wsi_M0_pMesgCount + assign wsi_M0_pMesgCount$D_IN = wsi_M0_pMesgCount + 32'd1 ; + assign wsi_M0_pMesgCount$EN = + WILL_FIRE_RL_wsi_M0_reqFifo_deq && + wsi_M0_reqFifo_q_0[312:310] == 3'd1 && + wsi_M0_burstKind == 2'd1 && + wsi_M0_reqFifo_q_0[309] ; + + // register wsi_M0_peerIsReady + assign wsi_M0_peerIsReady$D_IN = wsiM0_SReset_n ; + assign wsi_M0_peerIsReady$EN = 1'd1 ; + + // register wsi_M0_reqFifo_c_r + assign wsi_M0_reqFifo_c_r$D_IN = + WILL_FIRE_RL_wsi_M0_reqFifo_incCtr ? + MUX_wsi_M0_reqFifo_c_r$write_1__VAL_1 : + MUX_wsi_M0_reqFifo_c_r$write_1__VAL_2 ; + assign wsi_M0_reqFifo_c_r$EN = + WILL_FIRE_RL_wsi_M0_reqFifo_incCtr || + WILL_FIRE_RL_wsi_M0_reqFifo_decCtr ; + + // register wsi_M0_reqFifo_q_0 + always@(WILL_FIRE_RL_wsi_M0_reqFifo_both or + MUX_wsi_M0_reqFifo_q_0$write_1__VAL_1 or + MUX_wsi_M0_reqFifo_q_0$write_1__SEL_2 or + MUX_wsi_M0_reqFifo_q_0$write_1__VAL_2 or + WILL_FIRE_RL_wsi_M0_reqFifo_decCtr or wsi_M0_reqFifo_q_1) + begin + case (1'b1) // synopsys parallel_case + WILL_FIRE_RL_wsi_M0_reqFifo_both: + wsi_M0_reqFifo_q_0$D_IN = MUX_wsi_M0_reqFifo_q_0$write_1__VAL_1; + MUX_wsi_M0_reqFifo_q_0$write_1__SEL_2: + wsi_M0_reqFifo_q_0$D_IN = MUX_wsi_M0_reqFifo_q_0$write_1__VAL_2; + WILL_FIRE_RL_wsi_M0_reqFifo_decCtr: + wsi_M0_reqFifo_q_0$D_IN = wsi_M0_reqFifo_q_1; + default: wsi_M0_reqFifo_q_0$D_IN = + 313'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ; + endcase + end + assign wsi_M0_reqFifo_q_0$EN = + WILL_FIRE_RL_wsi_M0_reqFifo_both || + WILL_FIRE_RL_wsi_M0_reqFifo_incCtr && + wsi_M0_reqFifo_c_r == 2'd0 || + WILL_FIRE_RL_wsi_M0_reqFifo_decCtr ; + + // register wsi_M0_reqFifo_q_1 + always@(WILL_FIRE_RL_wsi_M0_reqFifo_both or + MUX_wsi_M0_reqFifo_q_1$write_1__VAL_1 or + MUX_wsi_M0_reqFifo_q_1$write_1__SEL_2 or + MUX_wsi_M0_reqFifo_q_0$write_1__VAL_2 or + WILL_FIRE_RL_wsi_M0_reqFifo_decCtr) + begin + case (1'b1) // synopsys parallel_case + WILL_FIRE_RL_wsi_M0_reqFifo_both: + wsi_M0_reqFifo_q_1$D_IN = MUX_wsi_M0_reqFifo_q_1$write_1__VAL_1; + MUX_wsi_M0_reqFifo_q_1$write_1__SEL_2: + wsi_M0_reqFifo_q_1$D_IN = MUX_wsi_M0_reqFifo_q_0$write_1__VAL_2; + WILL_FIRE_RL_wsi_M0_reqFifo_decCtr: + wsi_M0_reqFifo_q_1$D_IN = + 313'h00000AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA00; + default: wsi_M0_reqFifo_q_1$D_IN = + 313'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ; + endcase + end + assign wsi_M0_reqFifo_q_1$EN = + WILL_FIRE_RL_wsi_M0_reqFifo_both || + WILL_FIRE_RL_wsi_M0_reqFifo_incCtr && + wsi_M0_reqFifo_c_r == 2'd1 || + WILL_FIRE_RL_wsi_M0_reqFifo_decCtr ; + + // register wsi_M0_sThreadBusy_d + assign wsi_M0_sThreadBusy_d$D_IN = wsiM0_SThreadBusy ; + assign wsi_M0_sThreadBusy_d$EN = 1'd1 ; + + // register wsi_M0_statusR + assign wsi_M0_statusR$D_IN = + { wsi_M0_isReset_isInReset, + !wsi_M0_peerIsReady, + !wsi_M0_operateD, + wsi_M0_errorSticky, + wsi_M0_burstKind != 2'd0, + wsi_M0_sThreadBusy_d, + 1'd0, + wsi_M0_trafficSticky } ; + assign wsi_M0_statusR$EN = 1'd1 ; + + // register wsi_M0_tBusyCount + assign wsi_M0_tBusyCount$D_IN = wsi_M0_tBusyCount + 32'd1 ; + assign wsi_M0_tBusyCount$EN = + wsi_M0_operateD && wsi_M0_peerIsReady && wsi_M0_sThreadBusy_d ; + + // register wsi_M0_trafficSticky + assign wsi_M0_trafficSticky$D_IN = 1'd1 ; + assign wsi_M0_trafficSticky$EN = + WILL_FIRE_RL_wsi_M0_reqFifo_deq && + wsi_M0_reqFifo_q_0[312:310] == 3'd1 ; + + // register wsi_M1_burstKind + assign wsi_M1_burstKind$D_IN = + (wsi_M1_burstKind == 2'd0) ? + (wsi_M1_reqFifo_q_0[308] ? 2'd1 : 2'd2) : + 2'd0 ; + assign wsi_M1_burstKind$EN = + WILL_FIRE_RL_wsi_M1_reqFifo_deq && + wsi_M1_reqFifo_q_0[312:310] == 3'd1 && + (wsi_M1_burstKind == 2'd0 || + (wsi_M1_burstKind == 2'd1 || wsi_M1_burstKind == 2'd2) && + wsi_M1_reqFifo_q_0[309]) ; + + // register wsi_M1_errorSticky + assign wsi_M1_errorSticky$D_IN = 1'b0 ; + assign wsi_M1_errorSticky$EN = 1'b0 ; + + // register wsi_M1_iMesgCount + assign wsi_M1_iMesgCount$D_IN = wsi_M1_iMesgCount + 32'd1 ; + assign wsi_M1_iMesgCount$EN = + WILL_FIRE_RL_wsi_M1_reqFifo_deq && + wsi_M1_reqFifo_q_0[312:310] == 3'd1 && + wsi_M1_burstKind == 2'd2 && + wsi_M1_reqFifo_q_0[309] ; + + // register wsi_M1_isReset_isInReset + assign wsi_M1_isReset_isInReset$D_IN = 1'd0 ; + assign wsi_M1_isReset_isInReset$EN = wsi_M1_isReset_isInReset ; + + // register wsi_M1_operateD + assign wsi_M1_operateD$D_IN = wci_cState == 3'd2 ; + assign wsi_M1_operateD$EN = 1'd1 ; + + // register wsi_M1_pMesgCount + assign wsi_M1_pMesgCount$D_IN = wsi_M1_pMesgCount + 32'd1 ; + assign wsi_M1_pMesgCount$EN = + WILL_FIRE_RL_wsi_M1_reqFifo_deq && + wsi_M1_reqFifo_q_0[312:310] == 3'd1 && + wsi_M1_burstKind == 2'd1 && + wsi_M1_reqFifo_q_0[309] ; + + // register wsi_M1_peerIsReady + assign wsi_M1_peerIsReady$D_IN = wsiM1_SReset_n ; + assign wsi_M1_peerIsReady$EN = 1'd1 ; + + // register wsi_M1_reqFifo_c_r + assign wsi_M1_reqFifo_c_r$D_IN = + WILL_FIRE_RL_wsi_M1_reqFifo_incCtr ? + MUX_wsi_M1_reqFifo_c_r$write_1__VAL_1 : + MUX_wsi_M1_reqFifo_c_r$write_1__VAL_2 ; + assign wsi_M1_reqFifo_c_r$EN = + WILL_FIRE_RL_wsi_M1_reqFifo_incCtr || + WILL_FIRE_RL_wsi_M1_reqFifo_decCtr ; + + // register wsi_M1_reqFifo_q_0 + always@(WILL_FIRE_RL_wsi_M1_reqFifo_both or + MUX_wsi_M1_reqFifo_q_0$write_1__VAL_1 or + MUX_wsi_M1_reqFifo_q_0$write_1__SEL_2 or + MUX_wsi_M1_reqFifo_q_0$write_1__VAL_2 or + WILL_FIRE_RL_wsi_M1_reqFifo_decCtr or wsi_M1_reqFifo_q_1) + begin + case (1'b1) // synopsys parallel_case + WILL_FIRE_RL_wsi_M1_reqFifo_both: + wsi_M1_reqFifo_q_0$D_IN = MUX_wsi_M1_reqFifo_q_0$write_1__VAL_1; + MUX_wsi_M1_reqFifo_q_0$write_1__SEL_2: + wsi_M1_reqFifo_q_0$D_IN = MUX_wsi_M1_reqFifo_q_0$write_1__VAL_2; + WILL_FIRE_RL_wsi_M1_reqFifo_decCtr: + wsi_M1_reqFifo_q_0$D_IN = wsi_M1_reqFifo_q_1; + default: wsi_M1_reqFifo_q_0$D_IN = + 313'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ; + endcase + end + assign wsi_M1_reqFifo_q_0$EN = + WILL_FIRE_RL_wsi_M1_reqFifo_both || + WILL_FIRE_RL_wsi_M1_reqFifo_incCtr && + wsi_M1_reqFifo_c_r == 2'd0 || + WILL_FIRE_RL_wsi_M1_reqFifo_decCtr ; + + // register wsi_M1_reqFifo_q_1 + always@(WILL_FIRE_RL_wsi_M1_reqFifo_both or + MUX_wsi_M1_reqFifo_q_1$write_1__VAL_1 or + MUX_wsi_M1_reqFifo_q_1$write_1__SEL_2 or + MUX_wsi_M1_reqFifo_q_0$write_1__VAL_2 or + WILL_FIRE_RL_wsi_M1_reqFifo_decCtr) + begin + case (1'b1) // synopsys parallel_case + WILL_FIRE_RL_wsi_M1_reqFifo_both: + wsi_M1_reqFifo_q_1$D_IN = MUX_wsi_M1_reqFifo_q_1$write_1__VAL_1; + MUX_wsi_M1_reqFifo_q_1$write_1__SEL_2: + wsi_M1_reqFifo_q_1$D_IN = MUX_wsi_M1_reqFifo_q_0$write_1__VAL_2; + WILL_FIRE_RL_wsi_M1_reqFifo_decCtr: + wsi_M1_reqFifo_q_1$D_IN = + 313'h00000AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA00; + default: wsi_M1_reqFifo_q_1$D_IN = + 313'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ; + endcase + end + assign wsi_M1_reqFifo_q_1$EN = + WILL_FIRE_RL_wsi_M1_reqFifo_both || + WILL_FIRE_RL_wsi_M1_reqFifo_incCtr && + wsi_M1_reqFifo_c_r == 2'd1 || + WILL_FIRE_RL_wsi_M1_reqFifo_decCtr ; + + // register wsi_M1_sThreadBusy_d + assign wsi_M1_sThreadBusy_d$D_IN = wsiM1_SThreadBusy ; + assign wsi_M1_sThreadBusy_d$EN = 1'd1 ; + + // register wsi_M1_statusR + assign wsi_M1_statusR$D_IN = + { wsi_M1_isReset_isInReset, + !wsi_M1_peerIsReady, + !wsi_M1_operateD, + wsi_M1_errorSticky, + wsi_M1_burstKind != 2'd0, + wsi_M1_sThreadBusy_d, + 1'd0, + wsi_M1_trafficSticky } ; + assign wsi_M1_statusR$EN = 1'd1 ; + + // register wsi_M1_tBusyCount + assign wsi_M1_tBusyCount$D_IN = wsi_M1_tBusyCount + 32'd1 ; + assign wsi_M1_tBusyCount$EN = + wsi_M1_operateD && wsi_M1_peerIsReady && wsi_M1_sThreadBusy_d ; + + // register wsi_M1_trafficSticky + assign wsi_M1_trafficSticky$D_IN = 1'd1 ; + assign wsi_M1_trafficSticky$EN = + WILL_FIRE_RL_wsi_M1_reqFifo_deq && + wsi_M1_reqFifo_q_0[312:310] == 3'd1 ; + + // register wsi_S0_burstKind + assign wsi_S0_burstKind$D_IN = + (wsi_S0_burstKind == 2'd0) ? + (wsi_S0_wsiReq$wget[308] ? 2'd1 : 2'd2) : + 2'd0 ; + assign wsi_S0_burstKind$EN = + WILL_FIRE_RL_wsi_S0_reqFifo_enq && + (wsi_S0_burstKind == 2'd0 || + (wsi_S0_burstKind == 2'd1 || wsi_S0_burstKind == 2'd2) && + wsi_S0_wsiReq$wget[309]) ; + + // register wsi_S0_errorSticky + assign wsi_S0_errorSticky$D_IN = 1'b0 ; + assign wsi_S0_errorSticky$EN = 1'b0 ; + + // register wsi_S0_iMesgCount + assign wsi_S0_iMesgCount$D_IN = wsi_S0_iMesgCount + 32'd1 ; + assign wsi_S0_iMesgCount$EN = + WILL_FIRE_RL_wsi_S0_reqFifo_enq && wsi_S0_burstKind == 2'd2 && + wsi_S0_wsiReq$wget[309] ; + + // register wsi_S0_isReset_isInReset + assign wsi_S0_isReset_isInReset$D_IN = 1'd0 ; + assign wsi_S0_isReset_isInReset$EN = wsi_S0_isReset_isInReset ; + + // register wsi_S0_mesgWordLength + assign wsi_S0_mesgWordLength$D_IN = wsi_S0_wordCount ; + assign wsi_S0_mesgWordLength$EN = + WILL_FIRE_RL_wsi_S0_reqFifo_enq && wsi_S0_wsiReq$wget[309] ; + + // register wsi_S0_operateD + assign wsi_S0_operateD$D_IN = wci_cState == 3'd2 ; + assign wsi_S0_operateD$EN = 1'd1 ; + + // register wsi_S0_pMesgCount + assign wsi_S0_pMesgCount$D_IN = wsi_S0_pMesgCount + 32'd1 ; + assign wsi_S0_pMesgCount$EN = + WILL_FIRE_RL_wsi_S0_reqFifo_enq && wsi_S0_burstKind == 2'd1 && + wsi_S0_wsiReq$wget[309] ; + + // register wsi_S0_peerIsReady + assign wsi_S0_peerIsReady$D_IN = wsiS0_MReset_n ; + assign wsi_S0_peerIsReady$EN = 1'd1 ; + + // register wsi_S0_reqFifo_countReg + assign wsi_S0_reqFifo_countReg$D_IN = + WILL_FIRE_RL_wsi_S0_reqFifo_enq ? + wsi_S0_reqFifo_countReg + 2'd1 : + wsi_S0_reqFifo_countReg - 2'd1 ; + assign wsi_S0_reqFifo_countReg$EN = + WILL_FIRE_RL_wsi_S0_reqFifo_enq != + WILL_FIRE_RL_doMessageConsume_S0 ; + + // register wsi_S0_reqFifo_levelsValid + assign wsi_S0_reqFifo_levelsValid$D_IN = WILL_FIRE_RL_wsi_S0_reqFifo_reset ; + assign wsi_S0_reqFifo_levelsValid$EN = + WILL_FIRE_RL_doMessageConsume_S0 || + WILL_FIRE_RL_wsi_S0_reqFifo_enq || + WILL_FIRE_RL_wsi_S0_reqFifo_reset ; + + // register wsi_S0_statusR + assign wsi_S0_statusR$D_IN = + { wsi_S0_isReset_isInReset, + !wsi_S0_peerIsReady, + !wsi_S0_operateD, + wsi_S0_errorSticky, + wsi_S0_burstKind != 2'd0, + !wsi_S0_sThreadBusy_dw$whas || wsi_S0_sThreadBusy_dw$wget, + 1'd0, + wsi_S0_trafficSticky } ; + assign wsi_S0_statusR$EN = 1'd1 ; + + // register wsi_S0_tBusyCount + assign wsi_S0_tBusyCount$D_IN = wsi_S0_tBusyCount + 32'd1 ; + assign wsi_S0_tBusyCount$EN = + wsi_S0_operateD && wsi_S0_peerIsReady && + (!wsi_S0_sThreadBusy_dw$whas || wsi_S0_sThreadBusy_dw$wget) ; + + // register wsi_S0_trafficSticky + assign wsi_S0_trafficSticky$D_IN = 1'd1 ; + assign wsi_S0_trafficSticky$EN = WILL_FIRE_RL_wsi_S0_reqFifo_enq ; + + // register wsi_S0_wordCount + assign wsi_S0_wordCount$D_IN = + wsi_S0_wsiReq$wget[309] ? 12'd1 : wsi_S0_wordCount + 12'd1 ; + assign wsi_S0_wordCount$EN = WILL_FIRE_RL_wsi_S0_reqFifo_enq ; + + // register wsi_S1_burstKind + assign wsi_S1_burstKind$D_IN = + (wsi_S1_burstKind == 2'd0) ? + (wsi_S1_wsiReq$wget[308] ? 2'd1 : 2'd2) : + 2'd0 ; + assign wsi_S1_burstKind$EN = + WILL_FIRE_RL_wsi_S1_reqFifo_enq && + (wsi_S1_burstKind == 2'd0 || + (wsi_S1_burstKind == 2'd1 || wsi_S1_burstKind == 2'd2) && + wsi_S1_wsiReq$wget[309]) ; + + // register wsi_S1_errorSticky + assign wsi_S1_errorSticky$D_IN = 1'b0 ; + assign wsi_S1_errorSticky$EN = 1'b0 ; + + // register wsi_S1_iMesgCount + assign wsi_S1_iMesgCount$D_IN = wsi_S1_iMesgCount + 32'd1 ; + assign wsi_S1_iMesgCount$EN = + WILL_FIRE_RL_wsi_S1_reqFifo_enq && wsi_S1_burstKind == 2'd2 && + wsi_S1_wsiReq$wget[309] ; + + // register wsi_S1_isReset_isInReset + assign wsi_S1_isReset_isInReset$D_IN = 1'd0 ; + assign wsi_S1_isReset_isInReset$EN = wsi_S1_isReset_isInReset ; + + // register wsi_S1_mesgWordLength + assign wsi_S1_mesgWordLength$D_IN = wsi_S1_wordCount ; + assign wsi_S1_mesgWordLength$EN = + WILL_FIRE_RL_wsi_S1_reqFifo_enq && wsi_S1_wsiReq$wget[309] ; + + // register wsi_S1_operateD + assign wsi_S1_operateD$D_IN = wci_cState == 3'd2 ; + assign wsi_S1_operateD$EN = 1'd1 ; + + // register wsi_S1_pMesgCount + assign wsi_S1_pMesgCount$D_IN = wsi_S1_pMesgCount + 32'd1 ; + assign wsi_S1_pMesgCount$EN = + WILL_FIRE_RL_wsi_S1_reqFifo_enq && wsi_S1_burstKind == 2'd1 && + wsi_S1_wsiReq$wget[309] ; + + // register wsi_S1_peerIsReady + assign wsi_S1_peerIsReady$D_IN = wsiS1_MReset_n ; + assign wsi_S1_peerIsReady$EN = 1'd1 ; + + // register wsi_S1_reqFifo_countReg + assign wsi_S1_reqFifo_countReg$D_IN = + WILL_FIRE_RL_wsi_S1_reqFifo_enq ? + wsi_S1_reqFifo_countReg + 2'd1 : + wsi_S1_reqFifo_countReg - 2'd1 ; + assign wsi_S1_reqFifo_countReg$EN = + WILL_FIRE_RL_wsi_S1_reqFifo_enq != + WILL_FIRE_RL_doMessageConsume_S1 ; + + // register wsi_S1_reqFifo_levelsValid + assign wsi_S1_reqFifo_levelsValid$D_IN = WILL_FIRE_RL_wsi_S1_reqFifo_reset ; + assign wsi_S1_reqFifo_levelsValid$EN = + WILL_FIRE_RL_doMessageConsume_S1 || + WILL_FIRE_RL_wsi_S1_reqFifo_enq || + WILL_FIRE_RL_wsi_S1_reqFifo_reset ; + + // register wsi_S1_statusR + assign wsi_S1_statusR$D_IN = + { wsi_S1_isReset_isInReset, + !wsi_S1_peerIsReady, + !wsi_S1_operateD, + wsi_S1_errorSticky, + wsi_S1_burstKind != 2'd0, + !wsi_S1_sThreadBusy_dw$whas || wsi_S1_sThreadBusy_dw$wget, + 1'd0, + wsi_S1_trafficSticky } ; + assign wsi_S1_statusR$EN = 1'd1 ; + + // register wsi_S1_tBusyCount + assign wsi_S1_tBusyCount$D_IN = wsi_S1_tBusyCount + 32'd1 ; + assign wsi_S1_tBusyCount$EN = + wsi_S1_operateD && wsi_S1_peerIsReady && + (!wsi_S1_sThreadBusy_dw$whas || wsi_S1_sThreadBusy_dw$wget) ; + + // register wsi_S1_trafficSticky + assign wsi_S1_trafficSticky$D_IN = 1'd1 ; + assign wsi_S1_trafficSticky$EN = WILL_FIRE_RL_wsi_S1_reqFifo_enq ; + + // register wsi_S1_wordCount + assign wsi_S1_wordCount$D_IN = + wsi_S1_wsiReq$wget[309] ? 12'd1 : wsi_S1_wordCount + 12'd1 ; + assign wsi_S1_wordCount$EN = WILL_FIRE_RL_wsi_S1_reqFifo_enq ; + + // submodule wci_reqF + assign wci_reqF$D_IN = wci_wciReq$wget ; + assign wci_reqF$ENQ = wci_wciReq$wget[71:69] != 3'd0 ; + assign wci_reqF$DEQ = wci_reqF_r_deq$whas ; + assign wci_reqF$CLR = 1'b0 ; + + // submodule wsi_S0_reqFifo + assign wsi_S0_reqFifo$D_IN = wsi_S0_wsiReq$wget ; + assign wsi_S0_reqFifo$ENQ = WILL_FIRE_RL_wsi_S0_reqFifo_enq ; + assign wsi_S0_reqFifo$DEQ = WILL_FIRE_RL_doMessageConsume_S0 ; + assign wsi_S0_reqFifo$CLR = 1'b0 ; + + // submodule wsi_S1_reqFifo + assign wsi_S1_reqFifo$D_IN = wsi_S1_wsiReq$wget ; + assign wsi_S1_reqFifo$ENQ = WILL_FIRE_RL_wsi_S1_reqFifo_enq ; + assign wsi_S1_reqFifo$DEQ = WILL_FIRE_RL_doMessageConsume_S1 ; + assign wsi_S1_reqFifo$CLR = 1'b0 ; + + // remaining internal signals + assign rdat__h16512 = + hasDebugLogic ? + { wsi_S0_statusR, + wsi_S1_statusR, + wsi_M0_statusR, + wsi_M1_statusR } : + 32'd0 ; + assign rdat__h16701 = + hasDebugLogic ? wsi_S0_extStatusW$wget[95:64] : 32'd0 ; + assign rdat__h16715 = + hasDebugLogic ? wsi_S0_extStatusW$wget[63:32] : 32'd0 ; + assign rdat__h16723 = + hasDebugLogic ? wsi_S1_extStatusW$wget[95:64] : 32'd0 ; + assign rdat__h16737 = + hasDebugLogic ? wsi_S1_extStatusW$wget[63:32] : 32'd0 ; + assign rdat__h16745 = + hasDebugLogic ? wsi_M0_extStatusW$wget[95:64] : 32'd0 ; + assign rdat__h16759 = + hasDebugLogic ? wsi_M0_extStatusW$wget[63:32] : 32'd0 ; + assign rdat__h16767 = + hasDebugLogic ? wsi_M1_extStatusW$wget[95:64] : 32'd0 ; + assign rdat__h16781 = + hasDebugLogic ? wsi_M1_extStatusW$wget[63:32] : 32'd0 ; + always@(wci_reqF$D_OUT or + splitCtrl or + rdat__h16512 or + rdat__h16701 or + rdat__h16715 or + rdat__h16723 or + rdat__h16737 or + rdat__h16745 or rdat__h16759 or rdat__h16767 or rdat__h16781) + begin + case (wci_reqF$D_OUT[39:32]) + 8'h04: _theResult____h16428 = splitCtrl; + 8'h1C: _theResult____h16428 = rdat__h16512; + 8'h20: _theResult____h16428 = rdat__h16701; + 8'h24: _theResult____h16428 = rdat__h16715; + 8'h28: _theResult____h16428 = rdat__h16723; + 8'h2C: _theResult____h16428 = rdat__h16737; + 8'h30: _theResult____h16428 = rdat__h16745; + 8'h34: _theResult____h16428 = rdat__h16759; + 8'h38: _theResult____h16428 = rdat__h16767; + 8'h3C: _theResult____h16428 = rdat__h16781; + default: _theResult____h16428 = 32'd0; + endcase + end + + // handling of inlined registers + + always@(posedge wciS0_Clk) + begin + if (wciS0_MReset_n == `BSV_RESET_VALUE) + begin + splitCtrl <= `BSV_ASSIGNMENT_DELAY ctrlInit; + wci_cEdge <= `BSV_ASSIGNMENT_DELAY 3'h2; + wci_cState <= `BSV_ASSIGNMENT_DELAY 3'd0; + wci_ctlAckReg <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_ctlOpActive <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_illegalEdge <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_nState <= `BSV_ASSIGNMENT_DELAY 3'd0; + wci_reqF_countReg <= `BSV_ASSIGNMENT_DELAY 2'd0; + wci_respF_c_r <= `BSV_ASSIGNMENT_DELAY 2'd0; + wci_respF_q_0 <= `BSV_ASSIGNMENT_DELAY 34'h0AAAAAAAA; + wci_respF_q_1 <= `BSV_ASSIGNMENT_DELAY 34'h0AAAAAAAA; + wci_sFlagReg <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY 1'd1; + wsi_M0_burstKind <= `BSV_ASSIGNMENT_DELAY 2'd0; + wsi_M0_errorSticky <= `BSV_ASSIGNMENT_DELAY 1'd0; + wsi_M0_iMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0; + wsi_M0_operateD <= `BSV_ASSIGNMENT_DELAY 1'd0; + wsi_M0_pMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0; + wsi_M0_peerIsReady <= `BSV_ASSIGNMENT_DELAY 1'd0; + wsi_M0_reqFifo_c_r <= `BSV_ASSIGNMENT_DELAY 2'd0; + wsi_M0_reqFifo_q_0 <= `BSV_ASSIGNMENT_DELAY + 313'h00000AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA00; + wsi_M0_reqFifo_q_1 <= `BSV_ASSIGNMENT_DELAY + 313'h00000AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA00; + wsi_M0_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY 1'd1; + wsi_M0_tBusyCount <= `BSV_ASSIGNMENT_DELAY 32'd0; + wsi_M0_trafficSticky <= `BSV_ASSIGNMENT_DELAY 1'd0; + wsi_M1_burstKind <= `BSV_ASSIGNMENT_DELAY 2'd0; + wsi_M1_errorSticky <= `BSV_ASSIGNMENT_DELAY 1'd0; + wsi_M1_iMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0; + wsi_M1_operateD <= `BSV_ASSIGNMENT_DELAY 1'd0; + wsi_M1_pMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0; + wsi_M1_peerIsReady <= `BSV_ASSIGNMENT_DELAY 1'd0; + wsi_M1_reqFifo_c_r <= `BSV_ASSIGNMENT_DELAY 2'd0; + wsi_M1_reqFifo_q_0 <= `BSV_ASSIGNMENT_DELAY + 313'h00000AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA00; + wsi_M1_reqFifo_q_1 <= `BSV_ASSIGNMENT_DELAY + 313'h00000AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA00; + wsi_M1_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY 1'd1; + wsi_M1_tBusyCount <= `BSV_ASSIGNMENT_DELAY 32'd0; + wsi_M1_trafficSticky <= `BSV_ASSIGNMENT_DELAY 1'd0; + wsi_S0_burstKind <= `BSV_ASSIGNMENT_DELAY 2'd0; + wsi_S0_errorSticky <= `BSV_ASSIGNMENT_DELAY 1'd0; + wsi_S0_iMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0; + wsi_S0_operateD <= `BSV_ASSIGNMENT_DELAY 1'd0; + wsi_S0_pMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0; + wsi_S0_peerIsReady <= `BSV_ASSIGNMENT_DELAY 1'd0; + wsi_S0_reqFifo_countReg <= `BSV_ASSIGNMENT_DELAY 2'd0; + wsi_S0_reqFifo_levelsValid <= `BSV_ASSIGNMENT_DELAY 1'd1; + wsi_S0_tBusyCount <= `BSV_ASSIGNMENT_DELAY 32'd0; + wsi_S0_trafficSticky <= `BSV_ASSIGNMENT_DELAY 1'd0; + wsi_S0_wordCount <= `BSV_ASSIGNMENT_DELAY 12'd1; + wsi_S1_burstKind <= `BSV_ASSIGNMENT_DELAY 2'd0; + wsi_S1_errorSticky <= `BSV_ASSIGNMENT_DELAY 1'd0; + wsi_S1_iMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0; + wsi_S1_operateD <= `BSV_ASSIGNMENT_DELAY 1'd0; + wsi_S1_pMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0; + wsi_S1_peerIsReady <= `BSV_ASSIGNMENT_DELAY 1'd0; + wsi_S1_reqFifo_countReg <= `BSV_ASSIGNMENT_DELAY 2'd0; + wsi_S1_reqFifo_levelsValid <= `BSV_ASSIGNMENT_DELAY 1'd1; + wsi_S1_tBusyCount <= `BSV_ASSIGNMENT_DELAY 32'd0; + wsi_S1_trafficSticky <= `BSV_ASSIGNMENT_DELAY 1'd0; + wsi_S1_wordCount <= `BSV_ASSIGNMENT_DELAY 12'd1; + end + else + begin + if (splitCtrl$EN) splitCtrl <= `BSV_ASSIGNMENT_DELAY splitCtrl$D_IN; + if (wci_cEdge$EN) wci_cEdge <= `BSV_ASSIGNMENT_DELAY wci_cEdge$D_IN; + if (wci_cState$EN) + wci_cState <= `BSV_ASSIGNMENT_DELAY wci_cState$D_IN; + if (wci_ctlAckReg$EN) + wci_ctlAckReg <= `BSV_ASSIGNMENT_DELAY wci_ctlAckReg$D_IN; + if (wci_ctlOpActive$EN) + wci_ctlOpActive <= `BSV_ASSIGNMENT_DELAY wci_ctlOpActive$D_IN; + if (wci_illegalEdge$EN) + wci_illegalEdge <= `BSV_ASSIGNMENT_DELAY wci_illegalEdge$D_IN; + if (wci_nState$EN) + wci_nState <= `BSV_ASSIGNMENT_DELAY wci_nState$D_IN; + if (wci_reqF_countReg$EN) + wci_reqF_countReg <= `BSV_ASSIGNMENT_DELAY wci_reqF_countReg$D_IN; + if (wci_respF_c_r$EN) + wci_respF_c_r <= `BSV_ASSIGNMENT_DELAY wci_respF_c_r$D_IN; + if (wci_respF_q_0$EN) + wci_respF_q_0 <= `BSV_ASSIGNMENT_DELAY wci_respF_q_0$D_IN; + if (wci_respF_q_1$EN) + wci_respF_q_1 <= `BSV_ASSIGNMENT_DELAY wci_respF_q_1$D_IN; + if (wci_sFlagReg$EN) + wci_sFlagReg <= `BSV_ASSIGNMENT_DELAY wci_sFlagReg$D_IN; + if (wci_sThreadBusy_d$EN) + wci_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY wci_sThreadBusy_d$D_IN; + if (wsi_M0_burstKind$EN) + wsi_M0_burstKind <= `BSV_ASSIGNMENT_DELAY wsi_M0_burstKind$D_IN; + if (wsi_M0_errorSticky$EN) + wsi_M0_errorSticky <= `BSV_ASSIGNMENT_DELAY wsi_M0_errorSticky$D_IN; + if (wsi_M0_iMesgCount$EN) + wsi_M0_iMesgCount <= `BSV_ASSIGNMENT_DELAY wsi_M0_iMesgCount$D_IN; + if (wsi_M0_operateD$EN) + wsi_M0_operateD <= `BSV_ASSIGNMENT_DELAY wsi_M0_operateD$D_IN; + if (wsi_M0_pMesgCount$EN) + wsi_M0_pMesgCount <= `BSV_ASSIGNMENT_DELAY wsi_M0_pMesgCount$D_IN; + if (wsi_M0_peerIsReady$EN) + wsi_M0_peerIsReady <= `BSV_ASSIGNMENT_DELAY wsi_M0_peerIsReady$D_IN; + if (wsi_M0_reqFifo_c_r$EN) + wsi_M0_reqFifo_c_r <= `BSV_ASSIGNMENT_DELAY wsi_M0_reqFifo_c_r$D_IN; + if (wsi_M0_reqFifo_q_0$EN) + wsi_M0_reqFifo_q_0 <= `BSV_ASSIGNMENT_DELAY wsi_M0_reqFifo_q_0$D_IN; + if (wsi_M0_reqFifo_q_1$EN) + wsi_M0_reqFifo_q_1 <= `BSV_ASSIGNMENT_DELAY wsi_M0_reqFifo_q_1$D_IN; + if (wsi_M0_sThreadBusy_d$EN) + wsi_M0_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY + wsi_M0_sThreadBusy_d$D_IN; + if (wsi_M0_tBusyCount$EN) + wsi_M0_tBusyCount <= `BSV_ASSIGNMENT_DELAY wsi_M0_tBusyCount$D_IN; + if (wsi_M0_trafficSticky$EN) + wsi_M0_trafficSticky <= `BSV_ASSIGNMENT_DELAY + wsi_M0_trafficSticky$D_IN; + if (wsi_M1_burstKind$EN) + wsi_M1_burstKind <= `BSV_ASSIGNMENT_DELAY wsi_M1_burstKind$D_IN; + if (wsi_M1_errorSticky$EN) + wsi_M1_errorSticky <= `BSV_ASSIGNMENT_DELAY wsi_M1_errorSticky$D_IN; + if (wsi_M1_iMesgCount$EN) + wsi_M1_iMesgCount <= `BSV_ASSIGNMENT_DELAY wsi_M1_iMesgCount$D_IN; + if (wsi_M1_operateD$EN) + wsi_M1_operateD <= `BSV_ASSIGNMENT_DELAY wsi_M1_operateD$D_IN; + if (wsi_M1_pMesgCount$EN) + wsi_M1_pMesgCount <= `BSV_ASSIGNMENT_DELAY wsi_M1_pMesgCount$D_IN; + if (wsi_M1_peerIsReady$EN) + wsi_M1_peerIsReady <= `BSV_ASSIGNMENT_DELAY wsi_M1_peerIsReady$D_IN; + if (wsi_M1_reqFifo_c_r$EN) + wsi_M1_reqFifo_c_r <= `BSV_ASSIGNMENT_DELAY wsi_M1_reqFifo_c_r$D_IN; + if (wsi_M1_reqFifo_q_0$EN) + wsi_M1_reqFifo_q_0 <= `BSV_ASSIGNMENT_DELAY wsi_M1_reqFifo_q_0$D_IN; + if (wsi_M1_reqFifo_q_1$EN) + wsi_M1_reqFifo_q_1 <= `BSV_ASSIGNMENT_DELAY wsi_M1_reqFifo_q_1$D_IN; + if (wsi_M1_sThreadBusy_d$EN) + wsi_M1_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY + wsi_M1_sThreadBusy_d$D_IN; + if (wsi_M1_tBusyCount$EN) + wsi_M1_tBusyCount <= `BSV_ASSIGNMENT_DELAY wsi_M1_tBusyCount$D_IN; + if (wsi_M1_trafficSticky$EN) + wsi_M1_trafficSticky <= `BSV_ASSIGNMENT_DELAY + wsi_M1_trafficSticky$D_IN; + if (wsi_S0_burstKind$EN) + wsi_S0_burstKind <= `BSV_ASSIGNMENT_DELAY wsi_S0_burstKind$D_IN; + if (wsi_S0_errorSticky$EN) + wsi_S0_errorSticky <= `BSV_ASSIGNMENT_DELAY wsi_S0_errorSticky$D_IN; + if (wsi_S0_iMesgCount$EN) + wsi_S0_iMesgCount <= `BSV_ASSIGNMENT_DELAY wsi_S0_iMesgCount$D_IN; + if (wsi_S0_operateD$EN) + wsi_S0_operateD <= `BSV_ASSIGNMENT_DELAY wsi_S0_operateD$D_IN; + if (wsi_S0_pMesgCount$EN) + wsi_S0_pMesgCount <= `BSV_ASSIGNMENT_DELAY wsi_S0_pMesgCount$D_IN; + if (wsi_S0_peerIsReady$EN) + wsi_S0_peerIsReady <= `BSV_ASSIGNMENT_DELAY wsi_S0_peerIsReady$D_IN; + if (wsi_S0_reqFifo_countReg$EN) + wsi_S0_reqFifo_countReg <= `BSV_ASSIGNMENT_DELAY + wsi_S0_reqFifo_countReg$D_IN; + if (wsi_S0_reqFifo_levelsValid$EN) + wsi_S0_reqFifo_levelsValid <= `BSV_ASSIGNMENT_DELAY + wsi_S0_reqFifo_levelsValid$D_IN; + if (wsi_S0_tBusyCount$EN) + wsi_S0_tBusyCount <= `BSV_ASSIGNMENT_DELAY wsi_S0_tBusyCount$D_IN; + if (wsi_S0_trafficSticky$EN) + wsi_S0_trafficSticky <= `BSV_ASSIGNMENT_DELAY + wsi_S0_trafficSticky$D_IN; + if (wsi_S0_wordCount$EN) + wsi_S0_wordCount <= `BSV_ASSIGNMENT_DELAY wsi_S0_wordCount$D_IN; + if (wsi_S1_burstKind$EN) + wsi_S1_burstKind <= `BSV_ASSIGNMENT_DELAY wsi_S1_burstKind$D_IN; + if (wsi_S1_errorSticky$EN) + wsi_S1_errorSticky <= `BSV_ASSIGNMENT_DELAY wsi_S1_errorSticky$D_IN; + if (wsi_S1_iMesgCount$EN) + wsi_S1_iMesgCount <= `BSV_ASSIGNMENT_DELAY wsi_S1_iMesgCount$D_IN; + if (wsi_S1_operateD$EN) + wsi_S1_operateD <= `BSV_ASSIGNMENT_DELAY wsi_S1_operateD$D_IN; + if (wsi_S1_pMesgCount$EN) + wsi_S1_pMesgCount <= `BSV_ASSIGNMENT_DELAY wsi_S1_pMesgCount$D_IN; + if (wsi_S1_peerIsReady$EN) + wsi_S1_peerIsReady <= `BSV_ASSIGNMENT_DELAY wsi_S1_peerIsReady$D_IN; + if (wsi_S1_reqFifo_countReg$EN) + wsi_S1_reqFifo_countReg <= `BSV_ASSIGNMENT_DELAY + wsi_S1_reqFifo_countReg$D_IN; + if (wsi_S1_reqFifo_levelsValid$EN) + wsi_S1_reqFifo_levelsValid <= `BSV_ASSIGNMENT_DELAY + wsi_S1_reqFifo_levelsValid$D_IN; + if (wsi_S1_tBusyCount$EN) + wsi_S1_tBusyCount <= `BSV_ASSIGNMENT_DELAY wsi_S1_tBusyCount$D_IN; + if (wsi_S1_trafficSticky$EN) + wsi_S1_trafficSticky <= `BSV_ASSIGNMENT_DELAY + wsi_S1_trafficSticky$D_IN; + if (wsi_S1_wordCount$EN) + wsi_S1_wordCount <= `BSV_ASSIGNMENT_DELAY wsi_S1_wordCount$D_IN; + end + if (wsi_M0_statusR$EN) + wsi_M0_statusR <= `BSV_ASSIGNMENT_DELAY wsi_M0_statusR$D_IN; + if (wsi_M1_statusR$EN) + wsi_M1_statusR <= `BSV_ASSIGNMENT_DELAY wsi_M1_statusR$D_IN; + if (wsi_S0_mesgWordLength$EN) + wsi_S0_mesgWordLength <= `BSV_ASSIGNMENT_DELAY + wsi_S0_mesgWordLength$D_IN; + if (wsi_S0_statusR$EN) + wsi_S0_statusR <= `BSV_ASSIGNMENT_DELAY wsi_S0_statusR$D_IN; + if (wsi_S1_mesgWordLength$EN) + wsi_S1_mesgWordLength <= `BSV_ASSIGNMENT_DELAY + wsi_S1_mesgWordLength$D_IN; + if (wsi_S1_statusR$EN) + wsi_S1_statusR <= `BSV_ASSIGNMENT_DELAY wsi_S1_statusR$D_IN; + end + + always@(posedge wciS0_Clk or `BSV_RESET_EDGE wciS0_MReset_n) + if (wciS0_MReset_n == `BSV_RESET_VALUE) + begin + wci_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY 1'd1; + wsi_M0_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY 1'd1; + wsi_M1_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY 1'd1; + wsi_S0_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY 1'd1; + wsi_S1_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY 1'd1; + end + else + begin + if (wci_isReset_isInReset$EN) + wci_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY + wci_isReset_isInReset$D_IN; + if (wsi_M0_isReset_isInReset$EN) + wsi_M0_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY + wsi_M0_isReset_isInReset$D_IN; + if (wsi_M1_isReset_isInReset$EN) + wsi_M1_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY + wsi_M1_isReset_isInReset$D_IN; + if (wsi_S0_isReset_isInReset$EN) + wsi_S0_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY + wsi_S0_isReset_isInReset$D_IN; + if (wsi_S1_isReset_isInReset$EN) + wsi_S1_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY + wsi_S1_isReset_isInReset$D_IN; + end + + // synopsys translate_off + `ifdef BSV_NO_INITIAL_BLOCKS + `else // not BSV_NO_INITIAL_BLOCKS + initial + begin + splitCtrl = 32'hAAAAAAAA; + wci_cEdge = 3'h2; + wci_cState = 3'h2; + wci_ctlAckReg = 1'h0; + wci_ctlOpActive = 1'h0; + wci_illegalEdge = 1'h0; + wci_isReset_isInReset = 1'h0; + wci_nState = 3'h2; + wci_reqF_countReg = 2'h2; + wci_respF_c_r = 2'h2; + wci_respF_q_0 = 34'h2AAAAAAAA; + wci_respF_q_1 = 34'h2AAAAAAAA; + wci_sFlagReg = 1'h0; + wci_sThreadBusy_d = 1'h0; + wsi_M0_burstKind = 2'h2; + wsi_M0_errorSticky = 1'h0; + wsi_M0_iMesgCount = 32'hAAAAAAAA; + wsi_M0_isReset_isInReset = 1'h0; + wsi_M0_operateD = 1'h0; + wsi_M0_pMesgCount = 32'hAAAAAAAA; + wsi_M0_peerIsReady = 1'h0; + wsi_M0_reqFifo_c_r = 2'h2; + wsi_M0_reqFifo_q_0 = + 313'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; + wsi_M0_reqFifo_q_1 = + 313'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; + wsi_M0_sThreadBusy_d = 1'h0; + wsi_M0_statusR = 8'hAA; + wsi_M0_tBusyCount = 32'hAAAAAAAA; + wsi_M0_trafficSticky = 1'h0; + wsi_M1_burstKind = 2'h2; + wsi_M1_errorSticky = 1'h0; + wsi_M1_iMesgCount = 32'hAAAAAAAA; + wsi_M1_isReset_isInReset = 1'h0; + wsi_M1_operateD = 1'h0; + wsi_M1_pMesgCount = 32'hAAAAAAAA; + wsi_M1_peerIsReady = 1'h0; + wsi_M1_reqFifo_c_r = 2'h2; + wsi_M1_reqFifo_q_0 = + 313'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; + wsi_M1_reqFifo_q_1 = + 313'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; + wsi_M1_sThreadBusy_d = 1'h0; + wsi_M1_statusR = 8'hAA; + wsi_M1_tBusyCount = 32'hAAAAAAAA; + wsi_M1_trafficSticky = 1'h0; + wsi_S0_burstKind = 2'h2; + wsi_S0_errorSticky = 1'h0; + wsi_S0_iMesgCount = 32'hAAAAAAAA; + wsi_S0_isReset_isInReset = 1'h0; + wsi_S0_mesgWordLength = 12'hAAA; + wsi_S0_operateD = 1'h0; + wsi_S0_pMesgCount = 32'hAAAAAAAA; + wsi_S0_peerIsReady = 1'h0; + wsi_S0_reqFifo_countReg = 2'h2; + wsi_S0_reqFifo_levelsValid = 1'h0; + wsi_S0_statusR = 8'hAA; + wsi_S0_tBusyCount = 32'hAAAAAAAA; + wsi_S0_trafficSticky = 1'h0; + wsi_S0_wordCount = 12'hAAA; + wsi_S1_burstKind = 2'h2; + wsi_S1_errorSticky = 1'h0; + wsi_S1_iMesgCount = 32'hAAAAAAAA; + wsi_S1_isReset_isInReset = 1'h0; + wsi_S1_mesgWordLength = 12'hAAA; + wsi_S1_operateD = 1'h0; + wsi_S1_pMesgCount = 32'hAAAAAAAA; + wsi_S1_peerIsReady = 1'h0; + wsi_S1_reqFifo_countReg = 2'h2; + wsi_S1_reqFifo_levelsValid = 1'h0; + wsi_S1_statusR = 8'hAA; + wsi_S1_tBusyCount = 32'hAAAAAAAA; + wsi_S1_trafficSticky = 1'h0; + wsi_S1_wordCount = 12'hAAA; + end + `endif // BSV_NO_INITIAL_BLOCKS + // synopsys translate_on + + // handling of system tasks + + // synopsys translate_off + always@(negedge wciS0_Clk) + begin + #0; + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_ctl_op_start) + begin + v__h3698 = $time; + #0; + end + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_ctl_op_start) + $display("[%0d]: %m: WCI ControlOp: Starting-transition edge:%x from:%x", + v__h3698, + wci_reqF$D_OUT[36:34], + wci_cState); + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_ctrl_EiI && WILL_FIRE_RL_wci_ctrl_OrE) + $display("Error: \"bsv/inf/WsiSplitter2x2.bsv\", line 48, column 46: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_EiI] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n"); + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_ctrl_EiI && WILL_FIRE_RL_wci_ctrl_IsO) + $display("Error: \"bsv/inf/WsiSplitter2x2.bsv\", line 48, column 46: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_EiI] and\n [RL_wci_ctrl_IsO] ) fired in the same clock cycle.\n"); + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_ctrl_IsO && WILL_FIRE_RL_wci_ctrl_OrE) + $display("Error: \"bsv/inf/WsiSplitter2x2.bsv\", line 48, column 60: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_IsO] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n"); + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_cfwr) + begin + v__h16289 = $time; + #0; + end + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_cfwr) + $display("[%0d]: %m: WCI CONFIG WRITE Addr:%0x BE:%0x Data:%0x", + v__h16289, + wci_reqF$D_OUT[63:32], + wci_reqF$D_OUT[67:64], + wci_reqF$D_OUT[31:0]); + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_ctl_op_complete && wci_illegalEdge) + begin + v__h4017 = $time; + #0; + end + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_ctl_op_complete && wci_illegalEdge) + $display("[%0d]: %m: WCI ControlOp: ILLEGAL-EDGE Completed-transition edge:%x from:%x", + v__h4017, + wci_cEdge, + wci_cState); + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_ctl_op_complete && !wci_illegalEdge) + begin + v__h3873 = $time; + #0; + end + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_ctl_op_complete && !wci_illegalEdge) + $display("[%0d]: %m: WCI ControlOp: Completed-transition edge:%x from:%x to:%x", + v__h3873, + wci_cEdge, + wci_cState, + wci_nState); + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_cfrd) + begin + v__h16444 = $time; + #0; + end + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_cfrd) + $display("[%0d]: %m: WCI CONFIG READ Addr:%0x BE:%0x Data:%0x", + v__h16444, + wci_reqF$D_OUT[63:32], + wci_reqF$D_OUT[67:64], + _theResult____h16428); + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_OrE) + $display("Error: \"bsv/inf/WsiSplitter2x2.bsv\", line 48, column 26: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n"); + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_IsO) + $display("Error: \"bsv/inf/WsiSplitter2x2.bsv\", line 48, column 26: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_wci_ctrl_IsO] ) fired in the same clock cycle.\n"); + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_EiI) + $display("Error: \"bsv/inf/WsiSplitter2x2.bsv\", line 48, column 26: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_wci_ctrl_EiI] ) fired in the same clock cycle.\n"); + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_cfrd) + $display("Error: \"bsv/inf/WsiSplitter2x2.bsv\", line 48, column 26: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and [RL_wci_cfrd] )\n fired in the same clock cycle.\n"); + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_cfrd && WILL_FIRE_RL_wci_ctrl_OrE) + $display("Error: \"bsv/inf/WsiSplitter2x2.bsv\", line 48, column 36: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n"); + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_cfrd && WILL_FIRE_RL_wci_ctrl_IsO) + $display("Error: \"bsv/inf/WsiSplitter2x2.bsv\", line 48, column 36: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n [RL_wci_ctrl_IsO] ) fired in the same clock cycle.\n"); + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_cfrd && WILL_FIRE_RL_wci_ctrl_EiI) + $display("Error: \"bsv/inf/WsiSplitter2x2.bsv\", line 48, column 36: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n [RL_wci_ctrl_EiI] ) fired in the same clock cycle.\n"); + end + // synopsys translate_on +endmodule // mkWsiSplitter2x232B + diff --git a/rtl/mkWsiSplitter2x24B.v b/rtl/mkWsiSplitter2x24B.v new file mode 100644 index 00000000..3b57ba24 --- /dev/null +++ b/rtl/mkWsiSplitter2x24B.v @@ -0,0 +1,2443 @@ +// +// Generated by Bluespec Compiler, version 2012.09.beta1 (build 29570, 2012-09.11) +// +// On Tue Jan 22 07:33:03 EST 2013 +// +// +// Ports: +// Name I/O size props +// wciS0_SResp O 2 reg +// wciS0_SData O 32 reg +// wciS0_SThreadBusy O 1 +// wciS0_SFlag O 2 +// wsiS0_SThreadBusy O 1 +// wsiS0_SReset_n O 1 +// wsiS1_SThreadBusy O 1 +// wsiS1_SReset_n O 1 +// wsiM0_MCmd O 3 +// wsiM0_MReqLast O 1 +// wsiM0_MBurstPrecise O 1 +// wsiM0_MBurstLength O 12 +// wsiM0_MData O 32 reg +// wsiM0_MByteEn O 4 reg +// wsiM0_MReqInfo O 8 +// wsiM0_MReset_n O 1 +// wsiM1_MCmd O 3 +// wsiM1_MReqLast O 1 +// wsiM1_MBurstPrecise O 1 +// wsiM1_MBurstLength O 12 +// wsiM1_MData O 32 reg +// wsiM1_MByteEn O 4 reg +// wsiM1_MReqInfo O 8 +// wsiM1_MReset_n O 1 +// wciS0_Clk I 1 clock +// wciS0_MReset_n I 1 reset +// wciS0_MCmd I 3 +// wciS0_MAddrSpace I 1 +// wciS0_MByteEn I 4 +// wciS0_MAddr I 32 +// wciS0_MData I 32 +// wciS0_MFlag I 2 unused +// wsiS0_MCmd I 3 +// wsiS0_MBurstLength I 12 +// wsiS0_MData I 32 +// wsiS0_MByteEn I 4 +// wsiS0_MReqInfo I 8 +// wsiS1_MCmd I 3 +// wsiS1_MBurstLength I 12 +// wsiS1_MData I 32 +// wsiS1_MByteEn I 4 +// wsiS1_MReqInfo I 8 +// wsiS0_MReqLast I 1 +// wsiS0_MBurstPrecise I 1 +// wsiS0_MReset_n I 1 reg +// wsiS1_MReqLast I 1 +// wsiS1_MBurstPrecise I 1 +// wsiS1_MReset_n I 1 reg +// wsiM0_SThreadBusy I 1 reg +// wsiM0_SReset_n I 1 reg +// wsiM1_SThreadBusy I 1 reg +// wsiM1_SReset_n I 1 reg +// +// No combinational paths from inputs to outputs +// +// + +`ifdef BSV_ASSIGNMENT_DELAY +`else + `define BSV_ASSIGNMENT_DELAY +`endif + +`ifdef BSV_POSITIVE_RESET + `define BSV_RESET_VALUE 1'b1 + `define BSV_RESET_EDGE posedge +`else + `define BSV_RESET_VALUE 1'b0 + `define BSV_RESET_EDGE negedge +`endif + +module mkWsiSplitter2x24B(wciS0_Clk, + wciS0_MReset_n, + + wciS0_MCmd, + + wciS0_MAddrSpace, + + wciS0_MByteEn, + + wciS0_MAddr, + + wciS0_MData, + + wciS0_SResp, + + wciS0_SData, + + wciS0_SThreadBusy, + + wciS0_SFlag, + + wciS0_MFlag, + + wsiS0_MCmd, + + wsiS0_MReqLast, + + wsiS0_MBurstPrecise, + + wsiS0_MBurstLength, + + wsiS0_MData, + + wsiS0_MByteEn, + + wsiS0_MReqInfo, + + wsiS0_SThreadBusy, + + wsiS0_SReset_n, + + wsiS0_MReset_n, + + wsiS1_MCmd, + + wsiS1_MReqLast, + + wsiS1_MBurstPrecise, + + wsiS1_MBurstLength, + + wsiS1_MData, + + wsiS1_MByteEn, + + wsiS1_MReqInfo, + + wsiS1_SThreadBusy, + + wsiS1_SReset_n, + + wsiS1_MReset_n, + + wsiM0_MCmd, + + wsiM0_MReqLast, + + wsiM0_MBurstPrecise, + + wsiM0_MBurstLength, + + wsiM0_MData, + + wsiM0_MByteEn, + + wsiM0_MReqInfo, + + wsiM0_SThreadBusy, + + wsiM0_MReset_n, + + wsiM0_SReset_n, + + wsiM1_MCmd, + + wsiM1_MReqLast, + + wsiM1_MBurstPrecise, + + wsiM1_MBurstLength, + + wsiM1_MData, + + wsiM1_MByteEn, + + wsiM1_MReqInfo, + + wsiM1_SThreadBusy, + + wsiM1_MReset_n, + + wsiM1_SReset_n); + parameter [31 : 0] ctrlInit = 32'b0; + parameter [0 : 0] hasDebugLogic = 1'b0; + input wciS0_Clk; + input wciS0_MReset_n; + + // action method wciS0_mCmd + input [2 : 0] wciS0_MCmd; + + // action method wciS0_mAddrSpace + input wciS0_MAddrSpace; + + // action method wciS0_mByteEn + input [3 : 0] wciS0_MByteEn; + + // action method wciS0_mAddr + input [31 : 0] wciS0_MAddr; + + // action method wciS0_mData + input [31 : 0] wciS0_MData; + + // value method wciS0_sResp + output [1 : 0] wciS0_SResp; + + // value method wciS0_sData + output [31 : 0] wciS0_SData; + + // value method wciS0_sThreadBusy + output wciS0_SThreadBusy; + + // value method wciS0_sFlag + output [1 : 0] wciS0_SFlag; + + // action method wciS0_mFlag + input [1 : 0] wciS0_MFlag; + + // action method wsiS0_mCmd + input [2 : 0] wsiS0_MCmd; + + // action method wsiS0_mReqLast + input wsiS0_MReqLast; + + // action method wsiS0_mBurstPrecise + input wsiS0_MBurstPrecise; + + // action method wsiS0_mBurstLength + input [11 : 0] wsiS0_MBurstLength; + + // action method wsiS0_mData + input [31 : 0] wsiS0_MData; + + // action method wsiS0_mByteEn + input [3 : 0] wsiS0_MByteEn; + + // action method wsiS0_mReqInfo + input [7 : 0] wsiS0_MReqInfo; + + // action method wsiS0_mDataInfo + + // value method wsiS0_sThreadBusy + output wsiS0_SThreadBusy; + + // value method wsiS0_sReset_n + output wsiS0_SReset_n; + + // action method wsiS0_mReset_n + input wsiS0_MReset_n; + + // action method wsiS1_mCmd + input [2 : 0] wsiS1_MCmd; + + // action method wsiS1_mReqLast + input wsiS1_MReqLast; + + // action method wsiS1_mBurstPrecise + input wsiS1_MBurstPrecise; + + // action method wsiS1_mBurstLength + input [11 : 0] wsiS1_MBurstLength; + + // action method wsiS1_mData + input [31 : 0] wsiS1_MData; + + // action method wsiS1_mByteEn + input [3 : 0] wsiS1_MByteEn; + + // action method wsiS1_mReqInfo + input [7 : 0] wsiS1_MReqInfo; + + // action method wsiS1_mDataInfo + + // value method wsiS1_sThreadBusy + output wsiS1_SThreadBusy; + + // value method wsiS1_sReset_n + output wsiS1_SReset_n; + + // action method wsiS1_mReset_n + input wsiS1_MReset_n; + + // value method wsiM0_mCmd + output [2 : 0] wsiM0_MCmd; + + // value method wsiM0_mReqLast + output wsiM0_MReqLast; + + // value method wsiM0_mBurstPrecise + output wsiM0_MBurstPrecise; + + // value method wsiM0_mBurstLength + output [11 : 0] wsiM0_MBurstLength; + + // value method wsiM0_mData + output [31 : 0] wsiM0_MData; + + // value method wsiM0_mByteEn + output [3 : 0] wsiM0_MByteEn; + + // value method wsiM0_mReqInfo + output [7 : 0] wsiM0_MReqInfo; + + // value method wsiM0_mDataInfo + + // action method wsiM0_sThreadBusy + input wsiM0_SThreadBusy; + + // value method wsiM0_mReset_n + output wsiM0_MReset_n; + + // action method wsiM0_sReset_n + input wsiM0_SReset_n; + + // value method wsiM1_mCmd + output [2 : 0] wsiM1_MCmd; + + // value method wsiM1_mReqLast + output wsiM1_MReqLast; + + // value method wsiM1_mBurstPrecise + output wsiM1_MBurstPrecise; + + // value method wsiM1_mBurstLength + output [11 : 0] wsiM1_MBurstLength; + + // value method wsiM1_mData + output [31 : 0] wsiM1_MData; + + // value method wsiM1_mByteEn + output [3 : 0] wsiM1_MByteEn; + + // value method wsiM1_mReqInfo + output [7 : 0] wsiM1_MReqInfo; + + // value method wsiM1_mDataInfo + + // action method wsiM1_sThreadBusy + input wsiM1_SThreadBusy; + + // value method wsiM1_mReset_n + output wsiM1_MReset_n; + + // action method wsiM1_sReset_n + input wsiM1_SReset_n; + + // signals for module outputs + wire [31 : 0] wciS0_SData, wsiM0_MData, wsiM1_MData; + wire [11 : 0] wsiM0_MBurstLength, wsiM1_MBurstLength; + wire [7 : 0] wsiM0_MReqInfo, wsiM1_MReqInfo; + wire [3 : 0] wsiM0_MByteEn, wsiM1_MByteEn; + wire [2 : 0] wsiM0_MCmd, wsiM1_MCmd; + wire [1 : 0] wciS0_SFlag, wciS0_SResp; + wire wciS0_SThreadBusy, + wsiM0_MBurstPrecise, + wsiM0_MReqLast, + wsiM0_MReset_n, + wsiM1_MBurstPrecise, + wsiM1_MReqLast, + wsiM1_MReset_n, + wsiS0_SReset_n, + wsiS0_SThreadBusy, + wsiS1_SReset_n, + wsiS1_SThreadBusy; + + // inlined wires + wire [95 : 0] wsi_M0_extStatusW$wget, + wsi_M1_extStatusW$wget, + wsi_S0_extStatusW$wget, + wsi_S1_extStatusW$wget; + wire [71 : 0] wci_wciReq$wget; + wire [60 : 0] wsi_M0_reqFifo_x_wire$wget, + wsi_M1_reqFifo_x_wire$wget, + wsi_S0_wsiReq$wget, + wsi_S1_wsiReq$wget; + wire [33 : 0] wci_respF_x_wire$wget; + wire [31 : 0] wci_Es_mAddr_w$wget, + wci_Es_mData_w$wget, + wsi_Es0_mData_w$wget, + wsi_Es1_mData_w$wget; + wire [11 : 0] wsi_Es0_mBurstLength_w$wget, wsi_Es1_mBurstLength_w$wget; + wire [7 : 0] wsi_Es0_mReqInfo_w$wget, wsi_Es1_mReqInfo_w$wget; + wire [3 : 0] wci_Es_mByteEn_w$wget, + wsi_Es0_mByteEn_w$wget, + wsi_Es1_mByteEn_w$wget; + wire [2 : 0] wci_Es_mCmd_w$wget, + wci_wEdge$wget, + wsi_Es0_mCmd_w$wget, + wsi_Es1_mCmd_w$wget; + wire wci_Es_mAddrSpace_w$wget, + wci_Es_mAddrSpace_w$whas, + wci_Es_mAddr_w$whas, + wci_Es_mByteEn_w$whas, + wci_Es_mCmd_w$whas, + wci_Es_mData_w$whas, + wci_ctlAckReg_1$wget, + wci_ctlAckReg_1$whas, + wci_reqF_r_clr$whas, + wci_reqF_r_deq$whas, + wci_reqF_r_enq$whas, + wci_respF_dequeueing$whas, + wci_respF_enqueueing$whas, + wci_respF_x_wire$whas, + wci_sFlagReg_1$wget, + wci_sFlagReg_1$whas, + wci_sThreadBusy_pw$whas, + wci_wEdge$whas, + wci_wciReq$whas, + wci_wci_cfrd_pw$whas, + wci_wci_cfwr_pw$whas, + wci_wci_ctrl_pw$whas, + wsi_Es0_mBurstLength_w$whas, + wsi_Es0_mBurstPrecise_w$whas, + wsi_Es0_mByteEn_w$whas, + wsi_Es0_mCmd_w$whas, + wsi_Es0_mDataInfo_w$whas, + wsi_Es0_mData_w$whas, + wsi_Es0_mReqInfo_w$whas, + wsi_Es0_mReqLast_w$whas, + wsi_Es1_mBurstLength_w$whas, + wsi_Es1_mBurstPrecise_w$whas, + wsi_Es1_mByteEn_w$whas, + wsi_Es1_mCmd_w$whas, + wsi_Es1_mDataInfo_w$whas, + wsi_Es1_mData_w$whas, + wsi_Es1_mReqInfo_w$whas, + wsi_Es1_mReqLast_w$whas, + wsi_M0_operateD_1$wget, + wsi_M0_operateD_1$whas, + wsi_M0_peerIsReady_1$wget, + wsi_M0_peerIsReady_1$whas, + wsi_M0_reqFifo_dequeueing$whas, + wsi_M0_reqFifo_enqueueing$whas, + wsi_M0_reqFifo_x_wire$whas, + wsi_M0_sThreadBusy_pw$whas, + wsi_M1_operateD_1$wget, + wsi_M1_operateD_1$whas, + wsi_M1_peerIsReady_1$wget, + wsi_M1_peerIsReady_1$whas, + wsi_M1_reqFifo_dequeueing$whas, + wsi_M1_reqFifo_enqueueing$whas, + wsi_M1_reqFifo_x_wire$whas, + wsi_M1_sThreadBusy_pw$whas, + wsi_S0_operateD_1$wget, + wsi_S0_operateD_1$whas, + wsi_S0_peerIsReady_1$wget, + wsi_S0_peerIsReady_1$whas, + wsi_S0_reqFifo_doResetClr$whas, + wsi_S0_reqFifo_doResetDeq$whas, + wsi_S0_reqFifo_doResetEnq$whas, + wsi_S0_reqFifo_r_clr$whas, + wsi_S0_reqFifo_r_deq$whas, + wsi_S0_reqFifo_r_enq$whas, + wsi_S0_sThreadBusy_dw$wget, + wsi_S0_sThreadBusy_dw$whas, + wsi_S0_wsiReq$whas, + wsi_S1_operateD_1$wget, + wsi_S1_operateD_1$whas, + wsi_S1_peerIsReady_1$wget, + wsi_S1_peerIsReady_1$whas, + wsi_S1_reqFifo_doResetClr$whas, + wsi_S1_reqFifo_doResetDeq$whas, + wsi_S1_reqFifo_doResetEnq$whas, + wsi_S1_reqFifo_r_clr$whas, + wsi_S1_reqFifo_r_deq$whas, + wsi_S1_reqFifo_r_enq$whas, + wsi_S1_sThreadBusy_dw$wget, + wsi_S1_sThreadBusy_dw$whas, + wsi_S1_wsiReq$whas; + + // register splitCtrl + reg [31 : 0] splitCtrl; + wire [31 : 0] splitCtrl$D_IN; + wire splitCtrl$EN; + + // register wci_cEdge + reg [2 : 0] wci_cEdge; + wire [2 : 0] wci_cEdge$D_IN; + wire wci_cEdge$EN; + + // register wci_cState + reg [2 : 0] wci_cState; + wire [2 : 0] wci_cState$D_IN; + wire wci_cState$EN; + + // register wci_ctlAckReg + reg wci_ctlAckReg; + wire wci_ctlAckReg$D_IN, wci_ctlAckReg$EN; + + // register wci_ctlOpActive + reg wci_ctlOpActive; + wire wci_ctlOpActive$D_IN, wci_ctlOpActive$EN; + + // register wci_illegalEdge + reg wci_illegalEdge; + wire wci_illegalEdge$D_IN, wci_illegalEdge$EN; + + // register wci_isReset_isInReset + reg wci_isReset_isInReset; + wire wci_isReset_isInReset$D_IN, wci_isReset_isInReset$EN; + + // register wci_nState + reg [2 : 0] wci_nState; + reg [2 : 0] wci_nState$D_IN; + wire wci_nState$EN; + + // register wci_reqF_countReg + reg [1 : 0] wci_reqF_countReg; + wire [1 : 0] wci_reqF_countReg$D_IN; + wire wci_reqF_countReg$EN; + + // register wci_respF_c_r + reg [1 : 0] wci_respF_c_r; + wire [1 : 0] wci_respF_c_r$D_IN; + wire wci_respF_c_r$EN; + + // register wci_respF_q_0 + reg [33 : 0] wci_respF_q_0; + reg [33 : 0] wci_respF_q_0$D_IN; + wire wci_respF_q_0$EN; + + // register wci_respF_q_1 + reg [33 : 0] wci_respF_q_1; + reg [33 : 0] wci_respF_q_1$D_IN; + wire wci_respF_q_1$EN; + + // register wci_sFlagReg + reg wci_sFlagReg; + wire wci_sFlagReg$D_IN, wci_sFlagReg$EN; + + // register wci_sThreadBusy_d + reg wci_sThreadBusy_d; + wire wci_sThreadBusy_d$D_IN, wci_sThreadBusy_d$EN; + + // register wsi_M0_burstKind + reg [1 : 0] wsi_M0_burstKind; + wire [1 : 0] wsi_M0_burstKind$D_IN; + wire wsi_M0_burstKind$EN; + + // register wsi_M0_errorSticky + reg wsi_M0_errorSticky; + wire wsi_M0_errorSticky$D_IN, wsi_M0_errorSticky$EN; + + // register wsi_M0_iMesgCount + reg [31 : 0] wsi_M0_iMesgCount; + wire [31 : 0] wsi_M0_iMesgCount$D_IN; + wire wsi_M0_iMesgCount$EN; + + // register wsi_M0_isReset_isInReset + reg wsi_M0_isReset_isInReset; + wire wsi_M0_isReset_isInReset$D_IN, wsi_M0_isReset_isInReset$EN; + + // register wsi_M0_operateD + reg wsi_M0_operateD; + wire wsi_M0_operateD$D_IN, wsi_M0_operateD$EN; + + // register wsi_M0_pMesgCount + reg [31 : 0] wsi_M0_pMesgCount; + wire [31 : 0] wsi_M0_pMesgCount$D_IN; + wire wsi_M0_pMesgCount$EN; + + // register wsi_M0_peerIsReady + reg wsi_M0_peerIsReady; + wire wsi_M0_peerIsReady$D_IN, wsi_M0_peerIsReady$EN; + + // register wsi_M0_reqFifo_c_r + reg [1 : 0] wsi_M0_reqFifo_c_r; + wire [1 : 0] wsi_M0_reqFifo_c_r$D_IN; + wire wsi_M0_reqFifo_c_r$EN; + + // register wsi_M0_reqFifo_q_0 + reg [60 : 0] wsi_M0_reqFifo_q_0; + reg [60 : 0] wsi_M0_reqFifo_q_0$D_IN; + wire wsi_M0_reqFifo_q_0$EN; + + // register wsi_M0_reqFifo_q_1 + reg [60 : 0] wsi_M0_reqFifo_q_1; + reg [60 : 0] wsi_M0_reqFifo_q_1$D_IN; + wire wsi_M0_reqFifo_q_1$EN; + + // register wsi_M0_sThreadBusy_d + reg wsi_M0_sThreadBusy_d; + wire wsi_M0_sThreadBusy_d$D_IN, wsi_M0_sThreadBusy_d$EN; + + // register wsi_M0_statusR + reg [7 : 0] wsi_M0_statusR; + wire [7 : 0] wsi_M0_statusR$D_IN; + wire wsi_M0_statusR$EN; + + // register wsi_M0_tBusyCount + reg [31 : 0] wsi_M0_tBusyCount; + wire [31 : 0] wsi_M0_tBusyCount$D_IN; + wire wsi_M0_tBusyCount$EN; + + // register wsi_M0_trafficSticky + reg wsi_M0_trafficSticky; + wire wsi_M0_trafficSticky$D_IN, wsi_M0_trafficSticky$EN; + + // register wsi_M1_burstKind + reg [1 : 0] wsi_M1_burstKind; + wire [1 : 0] wsi_M1_burstKind$D_IN; + wire wsi_M1_burstKind$EN; + + // register wsi_M1_errorSticky + reg wsi_M1_errorSticky; + wire wsi_M1_errorSticky$D_IN, wsi_M1_errorSticky$EN; + + // register wsi_M1_iMesgCount + reg [31 : 0] wsi_M1_iMesgCount; + wire [31 : 0] wsi_M1_iMesgCount$D_IN; + wire wsi_M1_iMesgCount$EN; + + // register wsi_M1_isReset_isInReset + reg wsi_M1_isReset_isInReset; + wire wsi_M1_isReset_isInReset$D_IN, wsi_M1_isReset_isInReset$EN; + + // register wsi_M1_operateD + reg wsi_M1_operateD; + wire wsi_M1_operateD$D_IN, wsi_M1_operateD$EN; + + // register wsi_M1_pMesgCount + reg [31 : 0] wsi_M1_pMesgCount; + wire [31 : 0] wsi_M1_pMesgCount$D_IN; + wire wsi_M1_pMesgCount$EN; + + // register wsi_M1_peerIsReady + reg wsi_M1_peerIsReady; + wire wsi_M1_peerIsReady$D_IN, wsi_M1_peerIsReady$EN; + + // register wsi_M1_reqFifo_c_r + reg [1 : 0] wsi_M1_reqFifo_c_r; + wire [1 : 0] wsi_M1_reqFifo_c_r$D_IN; + wire wsi_M1_reqFifo_c_r$EN; + + // register wsi_M1_reqFifo_q_0 + reg [60 : 0] wsi_M1_reqFifo_q_0; + reg [60 : 0] wsi_M1_reqFifo_q_0$D_IN; + wire wsi_M1_reqFifo_q_0$EN; + + // register wsi_M1_reqFifo_q_1 + reg [60 : 0] wsi_M1_reqFifo_q_1; + reg [60 : 0] wsi_M1_reqFifo_q_1$D_IN; + wire wsi_M1_reqFifo_q_1$EN; + + // register wsi_M1_sThreadBusy_d + reg wsi_M1_sThreadBusy_d; + wire wsi_M1_sThreadBusy_d$D_IN, wsi_M1_sThreadBusy_d$EN; + + // register wsi_M1_statusR + reg [7 : 0] wsi_M1_statusR; + wire [7 : 0] wsi_M1_statusR$D_IN; + wire wsi_M1_statusR$EN; + + // register wsi_M1_tBusyCount + reg [31 : 0] wsi_M1_tBusyCount; + wire [31 : 0] wsi_M1_tBusyCount$D_IN; + wire wsi_M1_tBusyCount$EN; + + // register wsi_M1_trafficSticky + reg wsi_M1_trafficSticky; + wire wsi_M1_trafficSticky$D_IN, wsi_M1_trafficSticky$EN; + + // register wsi_S0_burstKind + reg [1 : 0] wsi_S0_burstKind; + wire [1 : 0] wsi_S0_burstKind$D_IN; + wire wsi_S0_burstKind$EN; + + // register wsi_S0_errorSticky + reg wsi_S0_errorSticky; + wire wsi_S0_errorSticky$D_IN, wsi_S0_errorSticky$EN; + + // register wsi_S0_iMesgCount + reg [31 : 0] wsi_S0_iMesgCount; + wire [31 : 0] wsi_S0_iMesgCount$D_IN; + wire wsi_S0_iMesgCount$EN; + + // register wsi_S0_isReset_isInReset + reg wsi_S0_isReset_isInReset; + wire wsi_S0_isReset_isInReset$D_IN, wsi_S0_isReset_isInReset$EN; + + // register wsi_S0_mesgWordLength + reg [11 : 0] wsi_S0_mesgWordLength; + wire [11 : 0] wsi_S0_mesgWordLength$D_IN; + wire wsi_S0_mesgWordLength$EN; + + // register wsi_S0_operateD + reg wsi_S0_operateD; + wire wsi_S0_operateD$D_IN, wsi_S0_operateD$EN; + + // register wsi_S0_pMesgCount + reg [31 : 0] wsi_S0_pMesgCount; + wire [31 : 0] wsi_S0_pMesgCount$D_IN; + wire wsi_S0_pMesgCount$EN; + + // register wsi_S0_peerIsReady + reg wsi_S0_peerIsReady; + wire wsi_S0_peerIsReady$D_IN, wsi_S0_peerIsReady$EN; + + // register wsi_S0_reqFifo_countReg + reg [1 : 0] wsi_S0_reqFifo_countReg; + wire [1 : 0] wsi_S0_reqFifo_countReg$D_IN; + wire wsi_S0_reqFifo_countReg$EN; + + // register wsi_S0_reqFifo_levelsValid + reg wsi_S0_reqFifo_levelsValid; + wire wsi_S0_reqFifo_levelsValid$D_IN, wsi_S0_reqFifo_levelsValid$EN; + + // register wsi_S0_statusR + reg [7 : 0] wsi_S0_statusR; + wire [7 : 0] wsi_S0_statusR$D_IN; + wire wsi_S0_statusR$EN; + + // register wsi_S0_tBusyCount + reg [31 : 0] wsi_S0_tBusyCount; + wire [31 : 0] wsi_S0_tBusyCount$D_IN; + wire wsi_S0_tBusyCount$EN; + + // register wsi_S0_trafficSticky + reg wsi_S0_trafficSticky; + wire wsi_S0_trafficSticky$D_IN, wsi_S0_trafficSticky$EN; + + // register wsi_S0_wordCount + reg [11 : 0] wsi_S0_wordCount; + wire [11 : 0] wsi_S0_wordCount$D_IN; + wire wsi_S0_wordCount$EN; + + // register wsi_S1_burstKind + reg [1 : 0] wsi_S1_burstKind; + wire [1 : 0] wsi_S1_burstKind$D_IN; + wire wsi_S1_burstKind$EN; + + // register wsi_S1_errorSticky + reg wsi_S1_errorSticky; + wire wsi_S1_errorSticky$D_IN, wsi_S1_errorSticky$EN; + + // register wsi_S1_iMesgCount + reg [31 : 0] wsi_S1_iMesgCount; + wire [31 : 0] wsi_S1_iMesgCount$D_IN; + wire wsi_S1_iMesgCount$EN; + + // register wsi_S1_isReset_isInReset + reg wsi_S1_isReset_isInReset; + wire wsi_S1_isReset_isInReset$D_IN, wsi_S1_isReset_isInReset$EN; + + // register wsi_S1_mesgWordLength + reg [11 : 0] wsi_S1_mesgWordLength; + wire [11 : 0] wsi_S1_mesgWordLength$D_IN; + wire wsi_S1_mesgWordLength$EN; + + // register wsi_S1_operateD + reg wsi_S1_operateD; + wire wsi_S1_operateD$D_IN, wsi_S1_operateD$EN; + + // register wsi_S1_pMesgCount + reg [31 : 0] wsi_S1_pMesgCount; + wire [31 : 0] wsi_S1_pMesgCount$D_IN; + wire wsi_S1_pMesgCount$EN; + + // register wsi_S1_peerIsReady + reg wsi_S1_peerIsReady; + wire wsi_S1_peerIsReady$D_IN, wsi_S1_peerIsReady$EN; + + // register wsi_S1_reqFifo_countReg + reg [1 : 0] wsi_S1_reqFifo_countReg; + wire [1 : 0] wsi_S1_reqFifo_countReg$D_IN; + wire wsi_S1_reqFifo_countReg$EN; + + // register wsi_S1_reqFifo_levelsValid + reg wsi_S1_reqFifo_levelsValid; + wire wsi_S1_reqFifo_levelsValid$D_IN, wsi_S1_reqFifo_levelsValid$EN; + + // register wsi_S1_statusR + reg [7 : 0] wsi_S1_statusR; + wire [7 : 0] wsi_S1_statusR$D_IN; + wire wsi_S1_statusR$EN; + + // register wsi_S1_tBusyCount + reg [31 : 0] wsi_S1_tBusyCount; + wire [31 : 0] wsi_S1_tBusyCount$D_IN; + wire wsi_S1_tBusyCount$EN; + + // register wsi_S1_trafficSticky + reg wsi_S1_trafficSticky; + wire wsi_S1_trafficSticky$D_IN, wsi_S1_trafficSticky$EN; + + // register wsi_S1_wordCount + reg [11 : 0] wsi_S1_wordCount; + wire [11 : 0] wsi_S1_wordCount$D_IN; + wire wsi_S1_wordCount$EN; + + // ports of submodule wci_reqF + wire [71 : 0] wci_reqF$D_IN, wci_reqF$D_OUT; + wire wci_reqF$CLR, wci_reqF$DEQ, wci_reqF$EMPTY_N, wci_reqF$ENQ; + + // ports of submodule wsi_S0_reqFifo + wire [60 : 0] wsi_S0_reqFifo$D_IN, wsi_S0_reqFifo$D_OUT; + wire wsi_S0_reqFifo$CLR, + wsi_S0_reqFifo$DEQ, + wsi_S0_reqFifo$EMPTY_N, + wsi_S0_reqFifo$ENQ, + wsi_S0_reqFifo$FULL_N; + + // ports of submodule wsi_S1_reqFifo + wire [60 : 0] wsi_S1_reqFifo$D_IN, wsi_S1_reqFifo$D_OUT; + wire wsi_S1_reqFifo$CLR, + wsi_S1_reqFifo$DEQ, + wsi_S1_reqFifo$EMPTY_N, + wsi_S1_reqFifo$ENQ, + wsi_S1_reqFifo$FULL_N; + + // rule scheduling signals + wire CAN_FIRE_RL_doMessageConsume_S1, + WILL_FIRE_RL_doMessageConsume_S0, + WILL_FIRE_RL_doMessageConsume_S1, + WILL_FIRE_RL_wci_cfrd, + WILL_FIRE_RL_wci_cfwr, + WILL_FIRE_RL_wci_ctl_op_complete, + WILL_FIRE_RL_wci_ctl_op_start, + WILL_FIRE_RL_wci_ctrl_EiI, + WILL_FIRE_RL_wci_ctrl_IsO, + WILL_FIRE_RL_wci_ctrl_OrE, + WILL_FIRE_RL_wci_respF_both, + WILL_FIRE_RL_wci_respF_decCtr, + WILL_FIRE_RL_wci_respF_incCtr, + WILL_FIRE_RL_wsi_M0_reqFifo_both, + WILL_FIRE_RL_wsi_M0_reqFifo_decCtr, + WILL_FIRE_RL_wsi_M0_reqFifo_deq, + WILL_FIRE_RL_wsi_M0_reqFifo_incCtr, + WILL_FIRE_RL_wsi_M1_reqFifo_both, + WILL_FIRE_RL_wsi_M1_reqFifo_decCtr, + WILL_FIRE_RL_wsi_M1_reqFifo_deq, + WILL_FIRE_RL_wsi_M1_reqFifo_incCtr, + WILL_FIRE_RL_wsi_S0_reqFifo_enq, + WILL_FIRE_RL_wsi_S0_reqFifo_reset, + WILL_FIRE_RL_wsi_S1_reqFifo_enq, + WILL_FIRE_RL_wsi_S1_reqFifo_reset; + + // inputs to muxes for submodule ports + reg [33 : 0] MUX_wci_respF_q_0$write_1__VAL_2; + wire [60 : 0] MUX_wsi_M0_reqFifo_q_0$write_1__VAL_1, + MUX_wsi_M0_reqFifo_q_0$write_1__VAL_2, + MUX_wsi_M0_reqFifo_q_1$write_1__VAL_1, + MUX_wsi_M1_reqFifo_q_0$write_1__VAL_1, + MUX_wsi_M1_reqFifo_q_0$write_1__VAL_2, + MUX_wsi_M1_reqFifo_q_1$write_1__VAL_1; + wire [33 : 0] MUX_wci_respF_q_0$write_1__VAL_1, + MUX_wci_respF_q_1$write_1__VAL_1, + MUX_wci_respF_x_wire$wset_1__VAL_1, + MUX_wci_respF_x_wire$wset_1__VAL_2; + wire [1 : 0] MUX_wci_respF_c_r$write_1__VAL_1, + MUX_wci_respF_c_r$write_1__VAL_2, + MUX_wsi_M0_reqFifo_c_r$write_1__VAL_1, + MUX_wsi_M0_reqFifo_c_r$write_1__VAL_2, + MUX_wsi_M1_reqFifo_c_r$write_1__VAL_1, + MUX_wsi_M1_reqFifo_c_r$write_1__VAL_2; + wire MUX_wci_illegalEdge$write_1__SEL_1, + MUX_wci_illegalEdge$write_1__VAL_1, + MUX_wci_respF_q_0$write_1__SEL_2, + MUX_wci_respF_q_1$write_1__SEL_2, + MUX_wsi_M0_reqFifo_q_0$write_1__SEL_2, + MUX_wsi_M0_reqFifo_q_1$write_1__SEL_2, + MUX_wsi_M0_reqFifo_x_wire$wset_1__SEL_1, + MUX_wsi_M1_reqFifo_q_0$write_1__SEL_2, + MUX_wsi_M1_reqFifo_q_1$write_1__SEL_2, + MUX_wsi_M1_reqFifo_x_wire$wset_1__SEL_1; + + // remaining internal signals + reg [63 : 0] v__h16289, v__h16444, v__h3698, v__h3873, v__h4017; + reg [31 : 0] _theResult____h16428; + wire [31 : 0] rdat__h16512, + rdat__h16701, + rdat__h16715, + rdat__h16723, + rdat__h16737, + rdat__h16745, + rdat__h16759, + rdat__h16767, + rdat__h16781; + + // value method wciS0_sResp + assign wciS0_SResp = wci_respF_q_0[33:32] ; + + // value method wciS0_sData + assign wciS0_SData = wci_respF_q_0[31:0] ; + + // value method wciS0_sThreadBusy + assign wciS0_SThreadBusy = + wci_reqF_countReg > 2'd1 || wci_isReset_isInReset ; + + // value method wciS0_sFlag + assign wciS0_SFlag = { 1'd1, wci_sFlagReg } ; + + // value method wsiS0_sThreadBusy + assign wsiS0_SThreadBusy = + !wsi_S0_sThreadBusy_dw$whas || wsi_S0_sThreadBusy_dw$wget ; + + // value method wsiS0_sReset_n + assign wsiS0_SReset_n = !wsi_S0_isReset_isInReset && wsi_S0_operateD ; + + // value method wsiS1_sThreadBusy + assign wsiS1_SThreadBusy = + !wsi_S1_sThreadBusy_dw$whas || wsi_S1_sThreadBusy_dw$wget ; + + // value method wsiS1_sReset_n + assign wsiS1_SReset_n = !wsi_S1_isReset_isInReset && wsi_S1_operateD ; + + // value method wsiM0_mCmd + assign wsiM0_MCmd = + wsi_M0_sThreadBusy_d ? 3'd0 : wsi_M0_reqFifo_q_0[60:58] ; + + // value method wsiM0_mReqLast + assign wsiM0_MReqLast = !wsi_M0_sThreadBusy_d && wsi_M0_reqFifo_q_0[57] ; + + // value method wsiM0_mBurstPrecise + assign wsiM0_MBurstPrecise = + !wsi_M0_sThreadBusy_d && wsi_M0_reqFifo_q_0[56] ; + + // value method wsiM0_mBurstLength + assign wsiM0_MBurstLength = + wsi_M0_sThreadBusy_d ? 12'd0 : wsi_M0_reqFifo_q_0[55:44] ; + + // value method wsiM0_mData + assign wsiM0_MData = wsi_M0_reqFifo_q_0[43:12] ; + + // value method wsiM0_mByteEn + assign wsiM0_MByteEn = wsi_M0_reqFifo_q_0[11:8] ; + + // value method wsiM0_mReqInfo + assign wsiM0_MReqInfo = + wsi_M0_sThreadBusy_d ? 8'd0 : wsi_M0_reqFifo_q_0[7:0] ; + + // value method wsiM0_mReset_n + assign wsiM0_MReset_n = !wsi_M0_isReset_isInReset && wsi_M0_operateD ; + + // value method wsiM1_mCmd + assign wsiM1_MCmd = + wsi_M1_sThreadBusy_d ? 3'd0 : wsi_M1_reqFifo_q_0[60:58] ; + + // value method wsiM1_mReqLast + assign wsiM1_MReqLast = !wsi_M1_sThreadBusy_d && wsi_M1_reqFifo_q_0[57] ; + + // value method wsiM1_mBurstPrecise + assign wsiM1_MBurstPrecise = + !wsi_M1_sThreadBusy_d && wsi_M1_reqFifo_q_0[56] ; + + // value method wsiM1_mBurstLength + assign wsiM1_MBurstLength = + wsi_M1_sThreadBusy_d ? 12'd0 : wsi_M1_reqFifo_q_0[55:44] ; + + // value method wsiM1_mData + assign wsiM1_MData = wsi_M1_reqFifo_q_0[43:12] ; + + // value method wsiM1_mByteEn + assign wsiM1_MByteEn = wsi_M1_reqFifo_q_0[11:8] ; + + // value method wsiM1_mReqInfo + assign wsiM1_MReqInfo = + wsi_M1_sThreadBusy_d ? 8'd0 : wsi_M1_reqFifo_q_0[7:0] ; + + // value method wsiM1_mReset_n + assign wsiM1_MReset_n = !wsi_M1_isReset_isInReset && wsi_M1_operateD ; + + // submodule wci_reqF + SizedFIFO #(.p1width(32'd72), + .p2depth(32'd3), + .p3cntr_width(32'd1), + .guarded(32'd1)) wci_reqF(.RST(wciS0_MReset_n), + .CLK(wciS0_Clk), + .D_IN(wci_reqF$D_IN), + .ENQ(wci_reqF$ENQ), + .DEQ(wci_reqF$DEQ), + .CLR(wci_reqF$CLR), + .D_OUT(wci_reqF$D_OUT), + .FULL_N(), + .EMPTY_N(wci_reqF$EMPTY_N)); + + // submodule wsi_S0_reqFifo + SizedFIFO #(.p1width(32'd61), + .p2depth(32'd3), + .p3cntr_width(32'd1), + .guarded(32'd1)) wsi_S0_reqFifo(.RST(wciS0_MReset_n), + .CLK(wciS0_Clk), + .D_IN(wsi_S0_reqFifo$D_IN), + .ENQ(wsi_S0_reqFifo$ENQ), + .DEQ(wsi_S0_reqFifo$DEQ), + .CLR(wsi_S0_reqFifo$CLR), + .D_OUT(wsi_S0_reqFifo$D_OUT), + .FULL_N(wsi_S0_reqFifo$FULL_N), + .EMPTY_N(wsi_S0_reqFifo$EMPTY_N)); + + // submodule wsi_S1_reqFifo + SizedFIFO #(.p1width(32'd61), + .p2depth(32'd3), + .p3cntr_width(32'd1), + .guarded(32'd1)) wsi_S1_reqFifo(.RST(wciS0_MReset_n), + .CLK(wciS0_Clk), + .D_IN(wsi_S1_reqFifo$D_IN), + .ENQ(wsi_S1_reqFifo$ENQ), + .DEQ(wsi_S1_reqFifo$DEQ), + .CLR(wsi_S1_reqFifo$CLR), + .D_OUT(wsi_S1_reqFifo$D_OUT), + .FULL_N(wsi_S1_reqFifo$FULL_N), + .EMPTY_N(wsi_S1_reqFifo$EMPTY_N)); + + // rule RL_wci_ctl_op_start + assign WILL_FIRE_RL_wci_ctl_op_start = + wci_reqF$EMPTY_N && wci_wci_ctrl_pw$whas && + !WILL_FIRE_RL_wci_ctl_op_complete ; + + // rule RL_wci_ctrl_EiI + assign WILL_FIRE_RL_wci_ctrl_EiI = + wci_wci_ctrl_pw$whas && WILL_FIRE_RL_wci_ctl_op_start && + wci_cState == 3'd0 && + wci_reqF$D_OUT[36:34] == 3'd0 ; + + // rule RL_wci_ctrl_IsO + assign WILL_FIRE_RL_wci_ctrl_IsO = + wci_wci_ctrl_pw$whas && WILL_FIRE_RL_wci_ctl_op_start && + wci_cState == 3'd1 && + wci_reqF$D_OUT[36:34] == 3'd1 ; + + // rule RL_wci_ctrl_OrE + assign WILL_FIRE_RL_wci_ctrl_OrE = + wci_wci_ctrl_pw$whas && WILL_FIRE_RL_wci_ctl_op_start && + wci_cState == 3'd2 && + wci_reqF$D_OUT[36:34] == 3'd3 ; + + // rule RL_doMessageConsume_S0 + assign WILL_FIRE_RL_doMessageConsume_S0 = + wsi_S0_reqFifo$EMPTY_N && + (splitCtrl[0] || splitCtrl[7] || wsi_M0_reqFifo_c_r != 2'd2) && + (splitCtrl[8] || splitCtrl[15] || wsi_M1_reqFifo_c_r != 2'd2) && + wci_cState == 3'd2 ; + + // rule RL_doMessageConsume_S1 + assign CAN_FIRE_RL_doMessageConsume_S1 = + wsi_S1_reqFifo$EMPTY_N && + (!splitCtrl[0] || splitCtrl[7] || wsi_M0_reqFifo_c_r != 2'd2) && + (!splitCtrl[8] || splitCtrl[15] || wsi_M1_reqFifo_c_r != 2'd2) && + wci_cState == 3'd2 ; + assign WILL_FIRE_RL_doMessageConsume_S1 = + CAN_FIRE_RL_doMessageConsume_S1 && + !WILL_FIRE_RL_doMessageConsume_S0 ; + + // rule RL_wci_cfwr + assign WILL_FIRE_RL_wci_cfwr = + wci_respF_c_r != 2'd2 && wci_reqF$EMPTY_N && + wci_wci_cfwr_pw$whas && + !WILL_FIRE_RL_wci_ctl_op_start && + !WILL_FIRE_RL_wci_ctl_op_complete ; + + // rule RL_wci_ctl_op_complete + assign WILL_FIRE_RL_wci_ctl_op_complete = + wci_respF_c_r != 2'd2 && wci_ctlOpActive && wci_ctlAckReg ; + + // rule RL_wsi_M0_reqFifo_deq + assign WILL_FIRE_RL_wsi_M0_reqFifo_deq = + wsi_M0_reqFifo_c_r != 2'd0 && !wsi_M0_sThreadBusy_d ; + + // rule RL_wsi_M0_reqFifo_incCtr + assign WILL_FIRE_RL_wsi_M0_reqFifo_incCtr = + ((wsi_M0_reqFifo_c_r == 2'd0) ? + wsi_M0_reqFifo_enqueueing$whas : + wsi_M0_reqFifo_c_r != 2'd1 || + wsi_M0_reqFifo_enqueueing$whas) && + wsi_M0_reqFifo_enqueueing$whas && + !WILL_FIRE_RL_wsi_M0_reqFifo_deq ; + + // rule RL_wsi_M0_reqFifo_decCtr + assign WILL_FIRE_RL_wsi_M0_reqFifo_decCtr = + WILL_FIRE_RL_wsi_M0_reqFifo_deq && + !wsi_M0_reqFifo_enqueueing$whas ; + + // rule RL_wsi_M0_reqFifo_both + assign WILL_FIRE_RL_wsi_M0_reqFifo_both = + ((wsi_M0_reqFifo_c_r == 2'd1) ? + wsi_M0_reqFifo_enqueueing$whas : + wsi_M0_reqFifo_c_r != 2'd2 || + wsi_M0_reqFifo_enqueueing$whas) && + WILL_FIRE_RL_wsi_M0_reqFifo_deq && + wsi_M0_reqFifo_enqueueing$whas ; + + // rule RL_wci_cfrd + assign WILL_FIRE_RL_wci_cfrd = + wci_respF_c_r != 2'd2 && wci_reqF$EMPTY_N && + wci_wci_cfrd_pw$whas && + !WILL_FIRE_RL_wci_ctl_op_start && + !WILL_FIRE_RL_wci_ctl_op_complete ; + + // rule RL_wci_respF_incCtr + assign WILL_FIRE_RL_wci_respF_incCtr = + ((wci_respF_c_r == 2'd0) ? + wci_respF_enqueueing$whas : + wci_respF_c_r != 2'd1 || wci_respF_enqueueing$whas) && + wci_respF_enqueueing$whas && + !(wci_respF_c_r != 2'd0) ; + + // rule RL_wci_respF_decCtr + assign WILL_FIRE_RL_wci_respF_decCtr = + wci_respF_c_r != 2'd0 && !wci_respF_enqueueing$whas ; + + // rule RL_wci_respF_both + assign WILL_FIRE_RL_wci_respF_both = + ((wci_respF_c_r == 2'd1) ? + wci_respF_enqueueing$whas : + wci_respF_c_r != 2'd2 || wci_respF_enqueueing$whas) && + wci_respF_c_r != 2'd0 && + wci_respF_enqueueing$whas ; + + // rule RL_wsi_M1_reqFifo_deq + assign WILL_FIRE_RL_wsi_M1_reqFifo_deq = + wsi_M1_reqFifo_c_r != 2'd0 && !wsi_M1_sThreadBusy_d ; + + // rule RL_wsi_M1_reqFifo_incCtr + assign WILL_FIRE_RL_wsi_M1_reqFifo_incCtr = + ((wsi_M1_reqFifo_c_r == 2'd0) ? + wsi_M1_reqFifo_enqueueing$whas : + wsi_M1_reqFifo_c_r != 2'd1 || + wsi_M1_reqFifo_enqueueing$whas) && + wsi_M1_reqFifo_enqueueing$whas && + !WILL_FIRE_RL_wsi_M1_reqFifo_deq ; + + // rule RL_wsi_M1_reqFifo_decCtr + assign WILL_FIRE_RL_wsi_M1_reqFifo_decCtr = + WILL_FIRE_RL_wsi_M1_reqFifo_deq && + !wsi_M1_reqFifo_enqueueing$whas ; + + // rule RL_wsi_M1_reqFifo_both + assign WILL_FIRE_RL_wsi_M1_reqFifo_both = + ((wsi_M1_reqFifo_c_r == 2'd1) ? + wsi_M1_reqFifo_enqueueing$whas : + wsi_M1_reqFifo_c_r != 2'd2 || + wsi_M1_reqFifo_enqueueing$whas) && + WILL_FIRE_RL_wsi_M1_reqFifo_deq && + wsi_M1_reqFifo_enqueueing$whas ; + + // rule RL_wsi_S0_reqFifo_enq + assign WILL_FIRE_RL_wsi_S0_reqFifo_enq = + wsi_S0_reqFifo$FULL_N && wsi_S0_operateD && wsi_S0_peerIsReady && + wsi_S0_wsiReq$wget[60:58] == 3'd1 ; + + // rule RL_wsi_S0_reqFifo_reset + assign WILL_FIRE_RL_wsi_S0_reqFifo_reset = + WILL_FIRE_RL_wsi_S0_reqFifo_enq || + WILL_FIRE_RL_doMessageConsume_S0 ; + + // rule RL_wsi_S1_reqFifo_enq + assign WILL_FIRE_RL_wsi_S1_reqFifo_enq = + wsi_S1_reqFifo$FULL_N && wsi_S1_operateD && wsi_S1_peerIsReady && + wsi_S1_wsiReq$wget[60:58] == 3'd1 ; + + // rule RL_wsi_S1_reqFifo_reset + assign WILL_FIRE_RL_wsi_S1_reqFifo_reset = + WILL_FIRE_RL_wsi_S1_reqFifo_enq || + WILL_FIRE_RL_doMessageConsume_S1 ; + + // inputs to muxes for submodule ports + assign MUX_wci_illegalEdge$write_1__SEL_1 = + WILL_FIRE_RL_wci_ctl_op_start && + (wci_reqF$D_OUT[36:34] == 3'd0 && wci_cState != 3'd0 || + wci_reqF$D_OUT[36:34] == 3'd1 && wci_cState != 3'd1 && + wci_cState != 3'd3 || + wci_reqF$D_OUT[36:34] == 3'd2 && wci_cState != 3'd2 || + wci_reqF$D_OUT[36:34] == 3'd3 && wci_cState != 3'd3 && + wci_cState != 3'd2 && + wci_cState != 3'd1 || + wci_reqF$D_OUT[36:34] == 3'd4 || + wci_reqF$D_OUT[36:34] == 3'd5 || + wci_reqF$D_OUT[36:34] == 3'd6 || + wci_reqF$D_OUT[36:34] == 3'd7) ; + assign MUX_wci_respF_q_0$write_1__SEL_2 = + WILL_FIRE_RL_wci_respF_incCtr && wci_respF_c_r == 2'd0 ; + assign MUX_wci_respF_q_1$write_1__SEL_2 = + WILL_FIRE_RL_wci_respF_incCtr && wci_respF_c_r == 2'd1 ; + assign MUX_wsi_M0_reqFifo_q_0$write_1__SEL_2 = + WILL_FIRE_RL_wsi_M0_reqFifo_incCtr && + wsi_M0_reqFifo_c_r == 2'd0 ; + assign MUX_wsi_M0_reqFifo_q_1$write_1__SEL_2 = + WILL_FIRE_RL_wsi_M0_reqFifo_incCtr && + wsi_M0_reqFifo_c_r == 2'd1 ; + assign MUX_wsi_M0_reqFifo_x_wire$wset_1__SEL_1 = + WILL_FIRE_RL_doMessageConsume_S0 && !splitCtrl[0] && + !splitCtrl[7] ; + assign MUX_wsi_M1_reqFifo_q_0$write_1__SEL_2 = + WILL_FIRE_RL_wsi_M1_reqFifo_incCtr && + wsi_M1_reqFifo_c_r == 2'd0 ; + assign MUX_wsi_M1_reqFifo_q_1$write_1__SEL_2 = + WILL_FIRE_RL_wsi_M1_reqFifo_incCtr && + wsi_M1_reqFifo_c_r == 2'd1 ; + assign MUX_wsi_M1_reqFifo_x_wire$wset_1__SEL_1 = + WILL_FIRE_RL_doMessageConsume_S0 && !splitCtrl[8] && + !splitCtrl[15] ; + assign MUX_wci_illegalEdge$write_1__VAL_1 = + wci_reqF$D_OUT[36:34] != 3'd4 && wci_reqF$D_OUT[36:34] != 3'd5 && + wci_reqF$D_OUT[36:34] != 3'd6 ; + assign MUX_wci_respF_c_r$write_1__VAL_1 = wci_respF_c_r + 2'd1 ; + assign MUX_wci_respF_c_r$write_1__VAL_2 = wci_respF_c_r - 2'd1 ; + assign MUX_wci_respF_q_0$write_1__VAL_1 = + (wci_respF_c_r == 2'd1) ? + MUX_wci_respF_q_0$write_1__VAL_2 : + wci_respF_q_1 ; + always@(WILL_FIRE_RL_wci_ctl_op_complete or + MUX_wci_respF_x_wire$wset_1__VAL_1 or + WILL_FIRE_RL_wci_cfrd or + MUX_wci_respF_x_wire$wset_1__VAL_2 or WILL_FIRE_RL_wci_cfwr) + begin + case (1'b1) // synopsys parallel_case + WILL_FIRE_RL_wci_ctl_op_complete: + MUX_wci_respF_q_0$write_1__VAL_2 = + MUX_wci_respF_x_wire$wset_1__VAL_1; + WILL_FIRE_RL_wci_cfrd: + MUX_wci_respF_q_0$write_1__VAL_2 = + MUX_wci_respF_x_wire$wset_1__VAL_2; + WILL_FIRE_RL_wci_cfwr: MUX_wci_respF_q_0$write_1__VAL_2 = 34'h1C0DE4201; + default: MUX_wci_respF_q_0$write_1__VAL_2 = + 34'h2AAAAAAAA /* unspecified value */ ; + endcase + end + assign MUX_wci_respF_q_1$write_1__VAL_1 = + (wci_respF_c_r == 2'd2) ? + MUX_wci_respF_q_0$write_1__VAL_2 : + 34'h0AAAAAAAA ; + assign MUX_wci_respF_x_wire$wset_1__VAL_1 = + wci_illegalEdge ? 34'h3C0DE4202 : 34'h1C0DE4201 ; + assign MUX_wci_respF_x_wire$wset_1__VAL_2 = { 2'd1, _theResult____h16428 } ; + assign MUX_wsi_M0_reqFifo_c_r$write_1__VAL_1 = wsi_M0_reqFifo_c_r + 2'd1 ; + assign MUX_wsi_M0_reqFifo_c_r$write_1__VAL_2 = wsi_M0_reqFifo_c_r - 2'd1 ; + assign MUX_wsi_M0_reqFifo_q_0$write_1__VAL_1 = + (wsi_M0_reqFifo_c_r == 2'd1) ? + MUX_wsi_M0_reqFifo_q_0$write_1__VAL_2 : + wsi_M0_reqFifo_q_1 ; + assign MUX_wsi_M0_reqFifo_q_0$write_1__VAL_2 = + MUX_wsi_M0_reqFifo_x_wire$wset_1__SEL_1 ? + wsi_S0_reqFifo$D_OUT : + wsi_S1_reqFifo$D_OUT ; + assign MUX_wsi_M0_reqFifo_q_1$write_1__VAL_1 = + (wsi_M0_reqFifo_c_r == 2'd2) ? + MUX_wsi_M0_reqFifo_q_0$write_1__VAL_2 : + 61'h00000AAAAAAAAA00 ; + assign MUX_wsi_M1_reqFifo_c_r$write_1__VAL_1 = wsi_M1_reqFifo_c_r + 2'd1 ; + assign MUX_wsi_M1_reqFifo_c_r$write_1__VAL_2 = wsi_M1_reqFifo_c_r - 2'd1 ; + assign MUX_wsi_M1_reqFifo_q_0$write_1__VAL_1 = + (wsi_M1_reqFifo_c_r == 2'd1) ? + MUX_wsi_M1_reqFifo_q_0$write_1__VAL_2 : + wsi_M1_reqFifo_q_1 ; + assign MUX_wsi_M1_reqFifo_q_0$write_1__VAL_2 = + MUX_wsi_M1_reqFifo_x_wire$wset_1__SEL_1 ? + wsi_S0_reqFifo$D_OUT : + wsi_S1_reqFifo$D_OUT ; + assign MUX_wsi_M1_reqFifo_q_1$write_1__VAL_1 = + (wsi_M1_reqFifo_c_r == 2'd2) ? + MUX_wsi_M1_reqFifo_q_0$write_1__VAL_2 : + 61'h00000AAAAAAAAA00 ; + + // inlined wires + assign wci_wciReq$wget = + { wciS0_MCmd, + wciS0_MAddrSpace, + wciS0_MByteEn, + wciS0_MAddr, + wciS0_MData } ; + assign wci_wciReq$whas = 1'd1 ; + assign wci_respF_x_wire$wget = MUX_wci_respF_q_0$write_1__VAL_2 ; + assign wci_respF_x_wire$whas = wci_respF_enqueueing$whas ; + assign wci_wEdge$wget = wci_reqF$D_OUT[36:34] ; + assign wci_wEdge$whas = WILL_FIRE_RL_wci_ctl_op_start ; + assign wci_sFlagReg_1$wget = 1'b0 ; + assign wci_sFlagReg_1$whas = 1'b0 ; + assign wci_ctlAckReg_1$wget = 1'd1 ; + assign wci_ctlAckReg_1$whas = + WILL_FIRE_RL_wci_ctrl_OrE || WILL_FIRE_RL_wci_ctrl_IsO || + WILL_FIRE_RL_wci_ctrl_EiI ; + assign wsi_S0_wsiReq$wget = + { wsiS0_MCmd, + wsiS0_MReqLast, + wsiS0_MBurstPrecise, + wsiS0_MBurstLength, + wsiS0_MData, + wsiS0_MByteEn, + wsiS0_MReqInfo } ; + assign wsi_S0_wsiReq$whas = 1'd1 ; + assign wsi_S0_operateD_1$wget = 1'd1 ; + assign wsi_S0_operateD_1$whas = wci_cState == 3'd2 ; + assign wsi_S0_peerIsReady_1$wget = 1'd1 ; + assign wsi_S0_peerIsReady_1$whas = wsiS0_MReset_n ; + assign wsi_S0_sThreadBusy_dw$wget = wsi_S0_reqFifo_countReg > 2'd1 ; + assign wsi_S0_sThreadBusy_dw$whas = + wsi_S0_reqFifo_levelsValid && wsi_S0_operateD && + wsi_S0_peerIsReady ; + assign wsi_S1_wsiReq$wget = + { wsiS1_MCmd, + wsiS1_MReqLast, + wsiS1_MBurstPrecise, + wsiS1_MBurstLength, + wsiS1_MData, + wsiS1_MByteEn, + wsiS1_MReqInfo } ; + assign wsi_S1_wsiReq$whas = 1'd1 ; + assign wsi_S1_operateD_1$wget = 1'd1 ; + assign wsi_S1_operateD_1$whas = wci_cState == 3'd2 ; + assign wsi_S1_peerIsReady_1$wget = 1'd1 ; + assign wsi_S1_peerIsReady_1$whas = wsiS1_MReset_n ; + assign wsi_S1_sThreadBusy_dw$wget = wsi_S1_reqFifo_countReg > 2'd1 ; + assign wsi_S1_sThreadBusy_dw$whas = + wsi_S1_reqFifo_levelsValid && wsi_S1_operateD && + wsi_S1_peerIsReady ; + assign wsi_M0_reqFifo_x_wire$wget = MUX_wsi_M0_reqFifo_q_0$write_1__VAL_2 ; + assign wsi_M0_reqFifo_x_wire$whas = wsi_M0_reqFifo_enqueueing$whas ; + assign wsi_M0_operateD_1$wget = 1'd1 ; + assign wsi_M0_operateD_1$whas = wci_cState == 3'd2 ; + assign wsi_M0_peerIsReady_1$wget = 1'd1 ; + assign wsi_M0_peerIsReady_1$whas = wsiM0_SReset_n ; + assign wsi_M1_reqFifo_x_wire$wget = MUX_wsi_M1_reqFifo_q_0$write_1__VAL_2 ; + assign wsi_M1_reqFifo_x_wire$whas = wsi_M1_reqFifo_enqueueing$whas ; + assign wsi_M1_operateD_1$wget = 1'd1 ; + assign wsi_M1_operateD_1$whas = wci_cState == 3'd2 ; + assign wsi_M1_peerIsReady_1$wget = 1'd1 ; + assign wsi_M1_peerIsReady_1$whas = wsiM1_SReset_n ; + assign wci_Es_mCmd_w$wget = wciS0_MCmd ; + assign wci_Es_mCmd_w$whas = 1'd1 ; + assign wci_Es_mAddrSpace_w$wget = wciS0_MAddrSpace ; + assign wci_Es_mAddrSpace_w$whas = 1'd1 ; + assign wci_Es_mByteEn_w$wget = wciS0_MByteEn ; + assign wci_Es_mByteEn_w$whas = 1'd1 ; + assign wci_Es_mAddr_w$wget = wciS0_MAddr ; + assign wci_Es_mAddr_w$whas = 1'd1 ; + assign wci_Es_mData_w$wget = wciS0_MData ; + assign wci_Es_mData_w$whas = 1'd1 ; + assign wsi_Es0_mCmd_w$wget = wsiS0_MCmd ; + assign wsi_Es0_mCmd_w$whas = 1'd1 ; + assign wsi_Es0_mBurstLength_w$wget = wsiS0_MBurstLength ; + assign wsi_Es0_mBurstLength_w$whas = 1'd1 ; + assign wsi_Es0_mData_w$wget = wsiS0_MData ; + assign wsi_Es0_mData_w$whas = 1'd1 ; + assign wsi_Es0_mByteEn_w$wget = wsiS0_MByteEn ; + assign wsi_Es0_mByteEn_w$whas = 1'd1 ; + assign wsi_Es0_mReqInfo_w$wget = wsiS0_MReqInfo ; + assign wsi_Es0_mReqInfo_w$whas = 1'd1 ; + assign wsi_Es1_mCmd_w$wget = wsiS1_MCmd ; + assign wsi_Es1_mCmd_w$whas = 1'd1 ; + assign wsi_Es1_mBurstLength_w$wget = wsiS1_MBurstLength ; + assign wsi_Es1_mBurstLength_w$whas = 1'd1 ; + assign wsi_Es1_mData_w$wget = wsiS1_MData ; + assign wsi_Es1_mData_w$whas = 1'd1 ; + assign wsi_Es1_mByteEn_w$wget = wsiS1_MByteEn ; + assign wsi_Es1_mByteEn_w$whas = 1'd1 ; + assign wsi_Es1_mReqInfo_w$wget = wsiS1_MReqInfo ; + assign wsi_Es1_mReqInfo_w$whas = 1'd1 ; + assign wci_reqF_r_enq$whas = wci_wciReq$wget[71:69] != 3'd0 ; + assign wci_reqF_r_deq$whas = + WILL_FIRE_RL_wci_ctl_op_start || WILL_FIRE_RL_wci_cfrd || + WILL_FIRE_RL_wci_cfwr ; + assign wci_reqF_r_clr$whas = 1'b0 ; + assign wci_respF_enqueueing$whas = + WILL_FIRE_RL_wci_ctl_op_complete || WILL_FIRE_RL_wci_cfrd || + WILL_FIRE_RL_wci_cfwr ; + assign wci_respF_dequeueing$whas = wci_respF_c_r != 2'd0 ; + assign wci_sThreadBusy_pw$whas = 1'b0 ; + assign wci_wci_cfwr_pw$whas = + wci_reqF$EMPTY_N && wci_reqF$D_OUT[68] && + wci_reqF$D_OUT[71:69] == 3'd1 ; + assign wci_wci_cfrd_pw$whas = + wci_reqF$EMPTY_N && wci_reqF$D_OUT[68] && + wci_reqF$D_OUT[71:69] == 3'd2 ; + assign wci_wci_ctrl_pw$whas = + wci_reqF$EMPTY_N && !wci_reqF$D_OUT[68] && + wci_reqF$D_OUT[71:69] == 3'd2 ; + assign wsi_S0_reqFifo_r_enq$whas = WILL_FIRE_RL_wsi_S0_reqFifo_enq ; + assign wsi_S0_reqFifo_r_deq$whas = WILL_FIRE_RL_doMessageConsume_S0 ; + assign wsi_S0_reqFifo_r_clr$whas = 1'b0 ; + assign wsi_S0_reqFifo_doResetEnq$whas = WILL_FIRE_RL_wsi_S0_reqFifo_enq ; + assign wsi_S0_reqFifo_doResetDeq$whas = WILL_FIRE_RL_doMessageConsume_S0 ; + assign wsi_S0_reqFifo_doResetClr$whas = 1'b0 ; + assign wsi_S1_reqFifo_r_enq$whas = WILL_FIRE_RL_wsi_S1_reqFifo_enq ; + assign wsi_S1_reqFifo_r_deq$whas = WILL_FIRE_RL_doMessageConsume_S1 ; + assign wsi_S1_reqFifo_r_clr$whas = 1'b0 ; + assign wsi_S1_reqFifo_doResetEnq$whas = WILL_FIRE_RL_wsi_S1_reqFifo_enq ; + assign wsi_S1_reqFifo_doResetDeq$whas = WILL_FIRE_RL_doMessageConsume_S1 ; + assign wsi_S1_reqFifo_doResetClr$whas = 1'b0 ; + assign wsi_M0_reqFifo_enqueueing$whas = + WILL_FIRE_RL_doMessageConsume_S0 && !splitCtrl[0] && + !splitCtrl[7] || + WILL_FIRE_RL_doMessageConsume_S1 && splitCtrl[0] && + !splitCtrl[7] ; + assign wsi_M0_reqFifo_dequeueing$whas = WILL_FIRE_RL_wsi_M0_reqFifo_deq ; + assign wsi_M0_sThreadBusy_pw$whas = wsiM0_SThreadBusy ; + assign wsi_M1_reqFifo_enqueueing$whas = + WILL_FIRE_RL_doMessageConsume_S0 && !splitCtrl[8] && + !splitCtrl[15] || + WILL_FIRE_RL_doMessageConsume_S1 && splitCtrl[8] && + !splitCtrl[15] ; + assign wsi_M1_reqFifo_dequeueing$whas = WILL_FIRE_RL_wsi_M1_reqFifo_deq ; + assign wsi_M1_sThreadBusy_pw$whas = wsiM1_SThreadBusy ; + assign wsi_Es0_mReqLast_w$whas = wsiS0_MReqLast ; + assign wsi_Es0_mBurstPrecise_w$whas = wsiS0_MBurstPrecise ; + assign wsi_Es0_mDataInfo_w$whas = 1'd1 ; + assign wsi_Es1_mReqLast_w$whas = wsiS1_MReqLast ; + assign wsi_Es1_mBurstPrecise_w$whas = wsiS1_MBurstPrecise ; + assign wsi_Es1_mDataInfo_w$whas = 1'd1 ; + assign wsi_S0_extStatusW$wget = + { wsi_S0_pMesgCount, wsi_S0_iMesgCount, wsi_S0_tBusyCount } ; + assign wsi_S1_extStatusW$wget = + { wsi_S1_pMesgCount, wsi_S1_iMesgCount, wsi_S1_tBusyCount } ; + assign wsi_M0_extStatusW$wget = + { wsi_M0_pMesgCount, wsi_M0_iMesgCount, wsi_M0_tBusyCount } ; + assign wsi_M1_extStatusW$wget = + { wsi_M1_pMesgCount, wsi_M1_iMesgCount, wsi_M1_tBusyCount } ; + + // register splitCtrl + assign splitCtrl$D_IN = wci_reqF$D_OUT[31:0] ; + assign splitCtrl$EN = + WILL_FIRE_RL_wci_cfwr && wci_reqF$D_OUT[39:32] == 8'h04 ; + + // register wci_cEdge + assign wci_cEdge$D_IN = wci_reqF$D_OUT[36:34] ; + assign wci_cEdge$EN = WILL_FIRE_RL_wci_ctl_op_start ; + + // register wci_cState + assign wci_cState$D_IN = wci_nState ; + assign wci_cState$EN = + WILL_FIRE_RL_wci_ctl_op_complete && !wci_illegalEdge ; + + // register wci_ctlAckReg + assign wci_ctlAckReg$D_IN = wci_ctlAckReg_1$whas ; + assign wci_ctlAckReg$EN = 1'd1 ; + + // register wci_ctlOpActive + assign wci_ctlOpActive$D_IN = !WILL_FIRE_RL_wci_ctl_op_complete ; + assign wci_ctlOpActive$EN = + WILL_FIRE_RL_wci_ctl_op_complete || + WILL_FIRE_RL_wci_ctl_op_start ; + + // register wci_illegalEdge + assign wci_illegalEdge$D_IN = + MUX_wci_illegalEdge$write_1__SEL_1 && + MUX_wci_illegalEdge$write_1__VAL_1 ; + assign wci_illegalEdge$EN = + MUX_wci_illegalEdge$write_1__SEL_1 || + WILL_FIRE_RL_wci_ctl_op_complete && wci_illegalEdge ; + + // register wci_isReset_isInReset + assign wci_isReset_isInReset$D_IN = 1'd0 ; + assign wci_isReset_isInReset$EN = wci_isReset_isInReset ; + + // register wci_nState + always@(wci_reqF$D_OUT) + begin + case (wci_reqF$D_OUT[36:34]) + 3'd0: wci_nState$D_IN = 3'd1; + 3'd1: wci_nState$D_IN = 3'd2; + 3'd2: wci_nState$D_IN = 3'd3; + default: wci_nState$D_IN = 3'd0; + endcase + end + assign wci_nState$EN = + WILL_FIRE_RL_wci_ctl_op_start && + (wci_reqF$D_OUT[36:34] == 3'd0 && wci_cState == 3'd0 || + wci_reqF$D_OUT[36:34] == 3'd1 && + (wci_cState == 3'd1 || wci_cState == 3'd3) || + wci_reqF$D_OUT[36:34] == 3'd2 && wci_cState == 3'd2 || + wci_reqF$D_OUT[36:34] == 3'd3 && + (wci_cState == 3'd3 || wci_cState == 3'd2 || + wci_cState == 3'd1)) ; + + // register wci_reqF_countReg + assign wci_reqF_countReg$D_IN = + (wci_wciReq$wget[71:69] != 3'd0) ? + wci_reqF_countReg + 2'd1 : + wci_reqF_countReg - 2'd1 ; + assign wci_reqF_countReg$EN = + (wci_wciReq$wget[71:69] != 3'd0) != wci_reqF_r_deq$whas ; + + // register wci_respF_c_r + assign wci_respF_c_r$D_IN = + WILL_FIRE_RL_wci_respF_incCtr ? + MUX_wci_respF_c_r$write_1__VAL_1 : + MUX_wci_respF_c_r$write_1__VAL_2 ; + assign wci_respF_c_r$EN = + WILL_FIRE_RL_wci_respF_incCtr || WILL_FIRE_RL_wci_respF_decCtr ; + + // register wci_respF_q_0 + always@(WILL_FIRE_RL_wci_respF_both or + MUX_wci_respF_q_0$write_1__VAL_1 or + MUX_wci_respF_q_0$write_1__SEL_2 or + MUX_wci_respF_q_0$write_1__VAL_2 or + WILL_FIRE_RL_wci_respF_decCtr or wci_respF_q_1) + begin + case (1'b1) // synopsys parallel_case + WILL_FIRE_RL_wci_respF_both: + wci_respF_q_0$D_IN = MUX_wci_respF_q_0$write_1__VAL_1; + MUX_wci_respF_q_0$write_1__SEL_2: + wci_respF_q_0$D_IN = MUX_wci_respF_q_0$write_1__VAL_2; + WILL_FIRE_RL_wci_respF_decCtr: wci_respF_q_0$D_IN = wci_respF_q_1; + default: wci_respF_q_0$D_IN = 34'h2AAAAAAAA /* unspecified value */ ; + endcase + end + assign wci_respF_q_0$EN = + WILL_FIRE_RL_wci_respF_both || + WILL_FIRE_RL_wci_respF_incCtr && wci_respF_c_r == 2'd0 || + WILL_FIRE_RL_wci_respF_decCtr ; + + // register wci_respF_q_1 + always@(WILL_FIRE_RL_wci_respF_both or + MUX_wci_respF_q_1$write_1__VAL_1 or + MUX_wci_respF_q_1$write_1__SEL_2 or + MUX_wci_respF_q_0$write_1__VAL_2 or WILL_FIRE_RL_wci_respF_decCtr) + begin + case (1'b1) // synopsys parallel_case + WILL_FIRE_RL_wci_respF_both: + wci_respF_q_1$D_IN = MUX_wci_respF_q_1$write_1__VAL_1; + MUX_wci_respF_q_1$write_1__SEL_2: + wci_respF_q_1$D_IN = MUX_wci_respF_q_0$write_1__VAL_2; + WILL_FIRE_RL_wci_respF_decCtr: wci_respF_q_1$D_IN = 34'h0AAAAAAAA; + default: wci_respF_q_1$D_IN = 34'h2AAAAAAAA /* unspecified value */ ; + endcase + end + assign wci_respF_q_1$EN = + WILL_FIRE_RL_wci_respF_both || + WILL_FIRE_RL_wci_respF_incCtr && wci_respF_c_r == 2'd1 || + WILL_FIRE_RL_wci_respF_decCtr ; + + // register wci_sFlagReg + assign wci_sFlagReg$D_IN = 1'b0 ; + assign wci_sFlagReg$EN = 1'd1 ; + + // register wci_sThreadBusy_d + assign wci_sThreadBusy_d$D_IN = 1'b0 ; + assign wci_sThreadBusy_d$EN = 1'd1 ; + + // register wsi_M0_burstKind + assign wsi_M0_burstKind$D_IN = + (wsi_M0_burstKind == 2'd0) ? + (wsi_M0_reqFifo_q_0[56] ? 2'd1 : 2'd2) : + 2'd0 ; + assign wsi_M0_burstKind$EN = + WILL_FIRE_RL_wsi_M0_reqFifo_deq && + wsi_M0_reqFifo_q_0[60:58] == 3'd1 && + (wsi_M0_burstKind == 2'd0 || + (wsi_M0_burstKind == 2'd1 || wsi_M0_burstKind == 2'd2) && + wsi_M0_reqFifo_q_0[57]) ; + + // register wsi_M0_errorSticky + assign wsi_M0_errorSticky$D_IN = 1'b0 ; + assign wsi_M0_errorSticky$EN = 1'b0 ; + + // register wsi_M0_iMesgCount + assign wsi_M0_iMesgCount$D_IN = wsi_M0_iMesgCount + 32'd1 ; + assign wsi_M0_iMesgCount$EN = + WILL_FIRE_RL_wsi_M0_reqFifo_deq && + wsi_M0_reqFifo_q_0[60:58] == 3'd1 && + wsi_M0_burstKind == 2'd2 && + wsi_M0_reqFifo_q_0[57] ; + + // register wsi_M0_isReset_isInReset + assign wsi_M0_isReset_isInReset$D_IN = 1'd0 ; + assign wsi_M0_isReset_isInReset$EN = wsi_M0_isReset_isInReset ; + + // register wsi_M0_operateD + assign wsi_M0_operateD$D_IN = wci_cState == 3'd2 ; + assign wsi_M0_operateD$EN = 1'd1 ; + + // register wsi_M0_pMesgCount + assign wsi_M0_pMesgCount$D_IN = wsi_M0_pMesgCount + 32'd1 ; + assign wsi_M0_pMesgCount$EN = + WILL_FIRE_RL_wsi_M0_reqFifo_deq && + wsi_M0_reqFifo_q_0[60:58] == 3'd1 && + wsi_M0_burstKind == 2'd1 && + wsi_M0_reqFifo_q_0[57] ; + + // register wsi_M0_peerIsReady + assign wsi_M0_peerIsReady$D_IN = wsiM0_SReset_n ; + assign wsi_M0_peerIsReady$EN = 1'd1 ; + + // register wsi_M0_reqFifo_c_r + assign wsi_M0_reqFifo_c_r$D_IN = + WILL_FIRE_RL_wsi_M0_reqFifo_incCtr ? + MUX_wsi_M0_reqFifo_c_r$write_1__VAL_1 : + MUX_wsi_M0_reqFifo_c_r$write_1__VAL_2 ; + assign wsi_M0_reqFifo_c_r$EN = + WILL_FIRE_RL_wsi_M0_reqFifo_incCtr || + WILL_FIRE_RL_wsi_M0_reqFifo_decCtr ; + + // register wsi_M0_reqFifo_q_0 + always@(WILL_FIRE_RL_wsi_M0_reqFifo_both or + MUX_wsi_M0_reqFifo_q_0$write_1__VAL_1 or + MUX_wsi_M0_reqFifo_q_0$write_1__SEL_2 or + MUX_wsi_M0_reqFifo_q_0$write_1__VAL_2 or + WILL_FIRE_RL_wsi_M0_reqFifo_decCtr or wsi_M0_reqFifo_q_1) + begin + case (1'b1) // synopsys parallel_case + WILL_FIRE_RL_wsi_M0_reqFifo_both: + wsi_M0_reqFifo_q_0$D_IN = MUX_wsi_M0_reqFifo_q_0$write_1__VAL_1; + MUX_wsi_M0_reqFifo_q_0$write_1__SEL_2: + wsi_M0_reqFifo_q_0$D_IN = MUX_wsi_M0_reqFifo_q_0$write_1__VAL_2; + WILL_FIRE_RL_wsi_M0_reqFifo_decCtr: + wsi_M0_reqFifo_q_0$D_IN = wsi_M0_reqFifo_q_1; + default: wsi_M0_reqFifo_q_0$D_IN = + 61'h0AAAAAAAAAAAAAAA /* unspecified value */ ; + endcase + end + assign wsi_M0_reqFifo_q_0$EN = + WILL_FIRE_RL_wsi_M0_reqFifo_both || + WILL_FIRE_RL_wsi_M0_reqFifo_incCtr && + wsi_M0_reqFifo_c_r == 2'd0 || + WILL_FIRE_RL_wsi_M0_reqFifo_decCtr ; + + // register wsi_M0_reqFifo_q_1 + always@(WILL_FIRE_RL_wsi_M0_reqFifo_both or + MUX_wsi_M0_reqFifo_q_1$write_1__VAL_1 or + MUX_wsi_M0_reqFifo_q_1$write_1__SEL_2 or + MUX_wsi_M0_reqFifo_q_0$write_1__VAL_2 or + WILL_FIRE_RL_wsi_M0_reqFifo_decCtr) + begin + case (1'b1) // synopsys parallel_case + WILL_FIRE_RL_wsi_M0_reqFifo_both: + wsi_M0_reqFifo_q_1$D_IN = MUX_wsi_M0_reqFifo_q_1$write_1__VAL_1; + MUX_wsi_M0_reqFifo_q_1$write_1__SEL_2: + wsi_M0_reqFifo_q_1$D_IN = MUX_wsi_M0_reqFifo_q_0$write_1__VAL_2; + WILL_FIRE_RL_wsi_M0_reqFifo_decCtr: + wsi_M0_reqFifo_q_1$D_IN = 61'h00000AAAAAAAAA00; + default: wsi_M0_reqFifo_q_1$D_IN = + 61'h0AAAAAAAAAAAAAAA /* unspecified value */ ; + endcase + end + assign wsi_M0_reqFifo_q_1$EN = + WILL_FIRE_RL_wsi_M0_reqFifo_both || + WILL_FIRE_RL_wsi_M0_reqFifo_incCtr && + wsi_M0_reqFifo_c_r == 2'd1 || + WILL_FIRE_RL_wsi_M0_reqFifo_decCtr ; + + // register wsi_M0_sThreadBusy_d + assign wsi_M0_sThreadBusy_d$D_IN = wsiM0_SThreadBusy ; + assign wsi_M0_sThreadBusy_d$EN = 1'd1 ; + + // register wsi_M0_statusR + assign wsi_M0_statusR$D_IN = + { wsi_M0_isReset_isInReset, + !wsi_M0_peerIsReady, + !wsi_M0_operateD, + wsi_M0_errorSticky, + wsi_M0_burstKind != 2'd0, + wsi_M0_sThreadBusy_d, + 1'd0, + wsi_M0_trafficSticky } ; + assign wsi_M0_statusR$EN = 1'd1 ; + + // register wsi_M0_tBusyCount + assign wsi_M0_tBusyCount$D_IN = wsi_M0_tBusyCount + 32'd1 ; + assign wsi_M0_tBusyCount$EN = + wsi_M0_operateD && wsi_M0_peerIsReady && wsi_M0_sThreadBusy_d ; + + // register wsi_M0_trafficSticky + assign wsi_M0_trafficSticky$D_IN = 1'd1 ; + assign wsi_M0_trafficSticky$EN = + WILL_FIRE_RL_wsi_M0_reqFifo_deq && + wsi_M0_reqFifo_q_0[60:58] == 3'd1 ; + + // register wsi_M1_burstKind + assign wsi_M1_burstKind$D_IN = + (wsi_M1_burstKind == 2'd0) ? + (wsi_M1_reqFifo_q_0[56] ? 2'd1 : 2'd2) : + 2'd0 ; + assign wsi_M1_burstKind$EN = + WILL_FIRE_RL_wsi_M1_reqFifo_deq && + wsi_M1_reqFifo_q_0[60:58] == 3'd1 && + (wsi_M1_burstKind == 2'd0 || + (wsi_M1_burstKind == 2'd1 || wsi_M1_burstKind == 2'd2) && + wsi_M1_reqFifo_q_0[57]) ; + + // register wsi_M1_errorSticky + assign wsi_M1_errorSticky$D_IN = 1'b0 ; + assign wsi_M1_errorSticky$EN = 1'b0 ; + + // register wsi_M1_iMesgCount + assign wsi_M1_iMesgCount$D_IN = wsi_M1_iMesgCount + 32'd1 ; + assign wsi_M1_iMesgCount$EN = + WILL_FIRE_RL_wsi_M1_reqFifo_deq && + wsi_M1_reqFifo_q_0[60:58] == 3'd1 && + wsi_M1_burstKind == 2'd2 && + wsi_M1_reqFifo_q_0[57] ; + + // register wsi_M1_isReset_isInReset + assign wsi_M1_isReset_isInReset$D_IN = 1'd0 ; + assign wsi_M1_isReset_isInReset$EN = wsi_M1_isReset_isInReset ; + + // register wsi_M1_operateD + assign wsi_M1_operateD$D_IN = wci_cState == 3'd2 ; + assign wsi_M1_operateD$EN = 1'd1 ; + + // register wsi_M1_pMesgCount + assign wsi_M1_pMesgCount$D_IN = wsi_M1_pMesgCount + 32'd1 ; + assign wsi_M1_pMesgCount$EN = + WILL_FIRE_RL_wsi_M1_reqFifo_deq && + wsi_M1_reqFifo_q_0[60:58] == 3'd1 && + wsi_M1_burstKind == 2'd1 && + wsi_M1_reqFifo_q_0[57] ; + + // register wsi_M1_peerIsReady + assign wsi_M1_peerIsReady$D_IN = wsiM1_SReset_n ; + assign wsi_M1_peerIsReady$EN = 1'd1 ; + + // register wsi_M1_reqFifo_c_r + assign wsi_M1_reqFifo_c_r$D_IN = + WILL_FIRE_RL_wsi_M1_reqFifo_incCtr ? + MUX_wsi_M1_reqFifo_c_r$write_1__VAL_1 : + MUX_wsi_M1_reqFifo_c_r$write_1__VAL_2 ; + assign wsi_M1_reqFifo_c_r$EN = + WILL_FIRE_RL_wsi_M1_reqFifo_incCtr || + WILL_FIRE_RL_wsi_M1_reqFifo_decCtr ; + + // register wsi_M1_reqFifo_q_0 + always@(WILL_FIRE_RL_wsi_M1_reqFifo_both or + MUX_wsi_M1_reqFifo_q_0$write_1__VAL_1 or + MUX_wsi_M1_reqFifo_q_0$write_1__SEL_2 or + MUX_wsi_M1_reqFifo_q_0$write_1__VAL_2 or + WILL_FIRE_RL_wsi_M1_reqFifo_decCtr or wsi_M1_reqFifo_q_1) + begin + case (1'b1) // synopsys parallel_case + WILL_FIRE_RL_wsi_M1_reqFifo_both: + wsi_M1_reqFifo_q_0$D_IN = MUX_wsi_M1_reqFifo_q_0$write_1__VAL_1; + MUX_wsi_M1_reqFifo_q_0$write_1__SEL_2: + wsi_M1_reqFifo_q_0$D_IN = MUX_wsi_M1_reqFifo_q_0$write_1__VAL_2; + WILL_FIRE_RL_wsi_M1_reqFifo_decCtr: + wsi_M1_reqFifo_q_0$D_IN = wsi_M1_reqFifo_q_1; + default: wsi_M1_reqFifo_q_0$D_IN = + 61'h0AAAAAAAAAAAAAAA /* unspecified value */ ; + endcase + end + assign wsi_M1_reqFifo_q_0$EN = + WILL_FIRE_RL_wsi_M1_reqFifo_both || + WILL_FIRE_RL_wsi_M1_reqFifo_incCtr && + wsi_M1_reqFifo_c_r == 2'd0 || + WILL_FIRE_RL_wsi_M1_reqFifo_decCtr ; + + // register wsi_M1_reqFifo_q_1 + always@(WILL_FIRE_RL_wsi_M1_reqFifo_both or + MUX_wsi_M1_reqFifo_q_1$write_1__VAL_1 or + MUX_wsi_M1_reqFifo_q_1$write_1__SEL_2 or + MUX_wsi_M1_reqFifo_q_0$write_1__VAL_2 or + WILL_FIRE_RL_wsi_M1_reqFifo_decCtr) + begin + case (1'b1) // synopsys parallel_case + WILL_FIRE_RL_wsi_M1_reqFifo_both: + wsi_M1_reqFifo_q_1$D_IN = MUX_wsi_M1_reqFifo_q_1$write_1__VAL_1; + MUX_wsi_M1_reqFifo_q_1$write_1__SEL_2: + wsi_M1_reqFifo_q_1$D_IN = MUX_wsi_M1_reqFifo_q_0$write_1__VAL_2; + WILL_FIRE_RL_wsi_M1_reqFifo_decCtr: + wsi_M1_reqFifo_q_1$D_IN = 61'h00000AAAAAAAAA00; + default: wsi_M1_reqFifo_q_1$D_IN = + 61'h0AAAAAAAAAAAAAAA /* unspecified value */ ; + endcase + end + assign wsi_M1_reqFifo_q_1$EN = + WILL_FIRE_RL_wsi_M1_reqFifo_both || + WILL_FIRE_RL_wsi_M1_reqFifo_incCtr && + wsi_M1_reqFifo_c_r == 2'd1 || + WILL_FIRE_RL_wsi_M1_reqFifo_decCtr ; + + // register wsi_M1_sThreadBusy_d + assign wsi_M1_sThreadBusy_d$D_IN = wsiM1_SThreadBusy ; + assign wsi_M1_sThreadBusy_d$EN = 1'd1 ; + + // register wsi_M1_statusR + assign wsi_M1_statusR$D_IN = + { wsi_M1_isReset_isInReset, + !wsi_M1_peerIsReady, + !wsi_M1_operateD, + wsi_M1_errorSticky, + wsi_M1_burstKind != 2'd0, + wsi_M1_sThreadBusy_d, + 1'd0, + wsi_M1_trafficSticky } ; + assign wsi_M1_statusR$EN = 1'd1 ; + + // register wsi_M1_tBusyCount + assign wsi_M1_tBusyCount$D_IN = wsi_M1_tBusyCount + 32'd1 ; + assign wsi_M1_tBusyCount$EN = + wsi_M1_operateD && wsi_M1_peerIsReady && wsi_M1_sThreadBusy_d ; + + // register wsi_M1_trafficSticky + assign wsi_M1_trafficSticky$D_IN = 1'd1 ; + assign wsi_M1_trafficSticky$EN = + WILL_FIRE_RL_wsi_M1_reqFifo_deq && + wsi_M1_reqFifo_q_0[60:58] == 3'd1 ; + + // register wsi_S0_burstKind + assign wsi_S0_burstKind$D_IN = + (wsi_S0_burstKind == 2'd0) ? + (wsi_S0_wsiReq$wget[56] ? 2'd1 : 2'd2) : + 2'd0 ; + assign wsi_S0_burstKind$EN = + WILL_FIRE_RL_wsi_S0_reqFifo_enq && + (wsi_S0_burstKind == 2'd0 || + (wsi_S0_burstKind == 2'd1 || wsi_S0_burstKind == 2'd2) && + wsi_S0_wsiReq$wget[57]) ; + + // register wsi_S0_errorSticky + assign wsi_S0_errorSticky$D_IN = 1'b0 ; + assign wsi_S0_errorSticky$EN = 1'b0 ; + + // register wsi_S0_iMesgCount + assign wsi_S0_iMesgCount$D_IN = wsi_S0_iMesgCount + 32'd1 ; + assign wsi_S0_iMesgCount$EN = + WILL_FIRE_RL_wsi_S0_reqFifo_enq && wsi_S0_burstKind == 2'd2 && + wsi_S0_wsiReq$wget[57] ; + + // register wsi_S0_isReset_isInReset + assign wsi_S0_isReset_isInReset$D_IN = 1'd0 ; + assign wsi_S0_isReset_isInReset$EN = wsi_S0_isReset_isInReset ; + + // register wsi_S0_mesgWordLength + assign wsi_S0_mesgWordLength$D_IN = wsi_S0_wordCount ; + assign wsi_S0_mesgWordLength$EN = + WILL_FIRE_RL_wsi_S0_reqFifo_enq && wsi_S0_wsiReq$wget[57] ; + + // register wsi_S0_operateD + assign wsi_S0_operateD$D_IN = wci_cState == 3'd2 ; + assign wsi_S0_operateD$EN = 1'd1 ; + + // register wsi_S0_pMesgCount + assign wsi_S0_pMesgCount$D_IN = wsi_S0_pMesgCount + 32'd1 ; + assign wsi_S0_pMesgCount$EN = + WILL_FIRE_RL_wsi_S0_reqFifo_enq && wsi_S0_burstKind == 2'd1 && + wsi_S0_wsiReq$wget[57] ; + + // register wsi_S0_peerIsReady + assign wsi_S0_peerIsReady$D_IN = wsiS0_MReset_n ; + assign wsi_S0_peerIsReady$EN = 1'd1 ; + + // register wsi_S0_reqFifo_countReg + assign wsi_S0_reqFifo_countReg$D_IN = + WILL_FIRE_RL_wsi_S0_reqFifo_enq ? + wsi_S0_reqFifo_countReg + 2'd1 : + wsi_S0_reqFifo_countReg - 2'd1 ; + assign wsi_S0_reqFifo_countReg$EN = + WILL_FIRE_RL_wsi_S0_reqFifo_enq != + WILL_FIRE_RL_doMessageConsume_S0 ; + + // register wsi_S0_reqFifo_levelsValid + assign wsi_S0_reqFifo_levelsValid$D_IN = WILL_FIRE_RL_wsi_S0_reqFifo_reset ; + assign wsi_S0_reqFifo_levelsValid$EN = + WILL_FIRE_RL_doMessageConsume_S0 || + WILL_FIRE_RL_wsi_S0_reqFifo_enq || + WILL_FIRE_RL_wsi_S0_reqFifo_reset ; + + // register wsi_S0_statusR + assign wsi_S0_statusR$D_IN = + { wsi_S0_isReset_isInReset, + !wsi_S0_peerIsReady, + !wsi_S0_operateD, + wsi_S0_errorSticky, + wsi_S0_burstKind != 2'd0, + !wsi_S0_sThreadBusy_dw$whas || wsi_S0_sThreadBusy_dw$wget, + 1'd0, + wsi_S0_trafficSticky } ; + assign wsi_S0_statusR$EN = 1'd1 ; + + // register wsi_S0_tBusyCount + assign wsi_S0_tBusyCount$D_IN = wsi_S0_tBusyCount + 32'd1 ; + assign wsi_S0_tBusyCount$EN = + wsi_S0_operateD && wsi_S0_peerIsReady && + (!wsi_S0_sThreadBusy_dw$whas || wsi_S0_sThreadBusy_dw$wget) ; + + // register wsi_S0_trafficSticky + assign wsi_S0_trafficSticky$D_IN = 1'd1 ; + assign wsi_S0_trafficSticky$EN = WILL_FIRE_RL_wsi_S0_reqFifo_enq ; + + // register wsi_S0_wordCount + assign wsi_S0_wordCount$D_IN = + wsi_S0_wsiReq$wget[57] ? 12'd1 : wsi_S0_wordCount + 12'd1 ; + assign wsi_S0_wordCount$EN = WILL_FIRE_RL_wsi_S0_reqFifo_enq ; + + // register wsi_S1_burstKind + assign wsi_S1_burstKind$D_IN = + (wsi_S1_burstKind == 2'd0) ? + (wsi_S1_wsiReq$wget[56] ? 2'd1 : 2'd2) : + 2'd0 ; + assign wsi_S1_burstKind$EN = + WILL_FIRE_RL_wsi_S1_reqFifo_enq && + (wsi_S1_burstKind == 2'd0 || + (wsi_S1_burstKind == 2'd1 || wsi_S1_burstKind == 2'd2) && + wsi_S1_wsiReq$wget[57]) ; + + // register wsi_S1_errorSticky + assign wsi_S1_errorSticky$D_IN = 1'b0 ; + assign wsi_S1_errorSticky$EN = 1'b0 ; + + // register wsi_S1_iMesgCount + assign wsi_S1_iMesgCount$D_IN = wsi_S1_iMesgCount + 32'd1 ; + assign wsi_S1_iMesgCount$EN = + WILL_FIRE_RL_wsi_S1_reqFifo_enq && wsi_S1_burstKind == 2'd2 && + wsi_S1_wsiReq$wget[57] ; + + // register wsi_S1_isReset_isInReset + assign wsi_S1_isReset_isInReset$D_IN = 1'd0 ; + assign wsi_S1_isReset_isInReset$EN = wsi_S1_isReset_isInReset ; + + // register wsi_S1_mesgWordLength + assign wsi_S1_mesgWordLength$D_IN = wsi_S1_wordCount ; + assign wsi_S1_mesgWordLength$EN = + WILL_FIRE_RL_wsi_S1_reqFifo_enq && wsi_S1_wsiReq$wget[57] ; + + // register wsi_S1_operateD + assign wsi_S1_operateD$D_IN = wci_cState == 3'd2 ; + assign wsi_S1_operateD$EN = 1'd1 ; + + // register wsi_S1_pMesgCount + assign wsi_S1_pMesgCount$D_IN = wsi_S1_pMesgCount + 32'd1 ; + assign wsi_S1_pMesgCount$EN = + WILL_FIRE_RL_wsi_S1_reqFifo_enq && wsi_S1_burstKind == 2'd1 && + wsi_S1_wsiReq$wget[57] ; + + // register wsi_S1_peerIsReady + assign wsi_S1_peerIsReady$D_IN = wsiS1_MReset_n ; + assign wsi_S1_peerIsReady$EN = 1'd1 ; + + // register wsi_S1_reqFifo_countReg + assign wsi_S1_reqFifo_countReg$D_IN = + WILL_FIRE_RL_wsi_S1_reqFifo_enq ? + wsi_S1_reqFifo_countReg + 2'd1 : + wsi_S1_reqFifo_countReg - 2'd1 ; + assign wsi_S1_reqFifo_countReg$EN = + WILL_FIRE_RL_wsi_S1_reqFifo_enq != + WILL_FIRE_RL_doMessageConsume_S1 ; + + // register wsi_S1_reqFifo_levelsValid + assign wsi_S1_reqFifo_levelsValid$D_IN = WILL_FIRE_RL_wsi_S1_reqFifo_reset ; + assign wsi_S1_reqFifo_levelsValid$EN = + WILL_FIRE_RL_doMessageConsume_S1 || + WILL_FIRE_RL_wsi_S1_reqFifo_enq || + WILL_FIRE_RL_wsi_S1_reqFifo_reset ; + + // register wsi_S1_statusR + assign wsi_S1_statusR$D_IN = + { wsi_S1_isReset_isInReset, + !wsi_S1_peerIsReady, + !wsi_S1_operateD, + wsi_S1_errorSticky, + wsi_S1_burstKind != 2'd0, + !wsi_S1_sThreadBusy_dw$whas || wsi_S1_sThreadBusy_dw$wget, + 1'd0, + wsi_S1_trafficSticky } ; + assign wsi_S1_statusR$EN = 1'd1 ; + + // register wsi_S1_tBusyCount + assign wsi_S1_tBusyCount$D_IN = wsi_S1_tBusyCount + 32'd1 ; + assign wsi_S1_tBusyCount$EN = + wsi_S1_operateD && wsi_S1_peerIsReady && + (!wsi_S1_sThreadBusy_dw$whas || wsi_S1_sThreadBusy_dw$wget) ; + + // register wsi_S1_trafficSticky + assign wsi_S1_trafficSticky$D_IN = 1'd1 ; + assign wsi_S1_trafficSticky$EN = WILL_FIRE_RL_wsi_S1_reqFifo_enq ; + + // register wsi_S1_wordCount + assign wsi_S1_wordCount$D_IN = + wsi_S1_wsiReq$wget[57] ? 12'd1 : wsi_S1_wordCount + 12'd1 ; + assign wsi_S1_wordCount$EN = WILL_FIRE_RL_wsi_S1_reqFifo_enq ; + + // submodule wci_reqF + assign wci_reqF$D_IN = wci_wciReq$wget ; + assign wci_reqF$ENQ = wci_wciReq$wget[71:69] != 3'd0 ; + assign wci_reqF$DEQ = wci_reqF_r_deq$whas ; + assign wci_reqF$CLR = 1'b0 ; + + // submodule wsi_S0_reqFifo + assign wsi_S0_reqFifo$D_IN = wsi_S0_wsiReq$wget ; + assign wsi_S0_reqFifo$ENQ = WILL_FIRE_RL_wsi_S0_reqFifo_enq ; + assign wsi_S0_reqFifo$DEQ = WILL_FIRE_RL_doMessageConsume_S0 ; + assign wsi_S0_reqFifo$CLR = 1'b0 ; + + // submodule wsi_S1_reqFifo + assign wsi_S1_reqFifo$D_IN = wsi_S1_wsiReq$wget ; + assign wsi_S1_reqFifo$ENQ = WILL_FIRE_RL_wsi_S1_reqFifo_enq ; + assign wsi_S1_reqFifo$DEQ = WILL_FIRE_RL_doMessageConsume_S1 ; + assign wsi_S1_reqFifo$CLR = 1'b0 ; + + // remaining internal signals + assign rdat__h16512 = + hasDebugLogic ? + { wsi_S0_statusR, + wsi_S1_statusR, + wsi_M0_statusR, + wsi_M1_statusR } : + 32'd0 ; + assign rdat__h16701 = + hasDebugLogic ? wsi_S0_extStatusW$wget[95:64] : 32'd0 ; + assign rdat__h16715 = + hasDebugLogic ? wsi_S0_extStatusW$wget[63:32] : 32'd0 ; + assign rdat__h16723 = + hasDebugLogic ? wsi_S1_extStatusW$wget[95:64] : 32'd0 ; + assign rdat__h16737 = + hasDebugLogic ? wsi_S1_extStatusW$wget[63:32] : 32'd0 ; + assign rdat__h16745 = + hasDebugLogic ? wsi_M0_extStatusW$wget[95:64] : 32'd0 ; + assign rdat__h16759 = + hasDebugLogic ? wsi_M0_extStatusW$wget[63:32] : 32'd0 ; + assign rdat__h16767 = + hasDebugLogic ? wsi_M1_extStatusW$wget[95:64] : 32'd0 ; + assign rdat__h16781 = + hasDebugLogic ? wsi_M1_extStatusW$wget[63:32] : 32'd0 ; + always@(wci_reqF$D_OUT or + splitCtrl or + rdat__h16512 or + rdat__h16701 or + rdat__h16715 or + rdat__h16723 or + rdat__h16737 or + rdat__h16745 or rdat__h16759 or rdat__h16767 or rdat__h16781) + begin + case (wci_reqF$D_OUT[39:32]) + 8'h04: _theResult____h16428 = splitCtrl; + 8'h1C: _theResult____h16428 = rdat__h16512; + 8'h20: _theResult____h16428 = rdat__h16701; + 8'h24: _theResult____h16428 = rdat__h16715; + 8'h28: _theResult____h16428 = rdat__h16723; + 8'h2C: _theResult____h16428 = rdat__h16737; + 8'h30: _theResult____h16428 = rdat__h16745; + 8'h34: _theResult____h16428 = rdat__h16759; + 8'h38: _theResult____h16428 = rdat__h16767; + 8'h3C: _theResult____h16428 = rdat__h16781; + default: _theResult____h16428 = 32'd0; + endcase + end + + // handling of inlined registers + + always@(posedge wciS0_Clk) + begin + if (wciS0_MReset_n == `BSV_RESET_VALUE) + begin + splitCtrl <= `BSV_ASSIGNMENT_DELAY ctrlInit; + wci_cEdge <= `BSV_ASSIGNMENT_DELAY 3'h2; + wci_cState <= `BSV_ASSIGNMENT_DELAY 3'd0; + wci_ctlAckReg <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_ctlOpActive <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_illegalEdge <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_nState <= `BSV_ASSIGNMENT_DELAY 3'd0; + wci_reqF_countReg <= `BSV_ASSIGNMENT_DELAY 2'd0; + wci_respF_c_r <= `BSV_ASSIGNMENT_DELAY 2'd0; + wci_respF_q_0 <= `BSV_ASSIGNMENT_DELAY 34'h0AAAAAAAA; + wci_respF_q_1 <= `BSV_ASSIGNMENT_DELAY 34'h0AAAAAAAA; + wci_sFlagReg <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY 1'd1; + wsi_M0_burstKind <= `BSV_ASSIGNMENT_DELAY 2'd0; + wsi_M0_errorSticky <= `BSV_ASSIGNMENT_DELAY 1'd0; + wsi_M0_iMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0; + wsi_M0_operateD <= `BSV_ASSIGNMENT_DELAY 1'd0; + wsi_M0_pMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0; + wsi_M0_peerIsReady <= `BSV_ASSIGNMENT_DELAY 1'd0; + wsi_M0_reqFifo_c_r <= `BSV_ASSIGNMENT_DELAY 2'd0; + wsi_M0_reqFifo_q_0 <= `BSV_ASSIGNMENT_DELAY 61'h00000AAAAAAAAA00; + wsi_M0_reqFifo_q_1 <= `BSV_ASSIGNMENT_DELAY 61'h00000AAAAAAAAA00; + wsi_M0_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY 1'd1; + wsi_M0_tBusyCount <= `BSV_ASSIGNMENT_DELAY 32'd0; + wsi_M0_trafficSticky <= `BSV_ASSIGNMENT_DELAY 1'd0; + wsi_M1_burstKind <= `BSV_ASSIGNMENT_DELAY 2'd0; + wsi_M1_errorSticky <= `BSV_ASSIGNMENT_DELAY 1'd0; + wsi_M1_iMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0; + wsi_M1_operateD <= `BSV_ASSIGNMENT_DELAY 1'd0; + wsi_M1_pMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0; + wsi_M1_peerIsReady <= `BSV_ASSIGNMENT_DELAY 1'd0; + wsi_M1_reqFifo_c_r <= `BSV_ASSIGNMENT_DELAY 2'd0; + wsi_M1_reqFifo_q_0 <= `BSV_ASSIGNMENT_DELAY 61'h00000AAAAAAAAA00; + wsi_M1_reqFifo_q_1 <= `BSV_ASSIGNMENT_DELAY 61'h00000AAAAAAAAA00; + wsi_M1_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY 1'd1; + wsi_M1_tBusyCount <= `BSV_ASSIGNMENT_DELAY 32'd0; + wsi_M1_trafficSticky <= `BSV_ASSIGNMENT_DELAY 1'd0; + wsi_S0_burstKind <= `BSV_ASSIGNMENT_DELAY 2'd0; + wsi_S0_errorSticky <= `BSV_ASSIGNMENT_DELAY 1'd0; + wsi_S0_iMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0; + wsi_S0_operateD <= `BSV_ASSIGNMENT_DELAY 1'd0; + wsi_S0_pMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0; + wsi_S0_peerIsReady <= `BSV_ASSIGNMENT_DELAY 1'd0; + wsi_S0_reqFifo_countReg <= `BSV_ASSIGNMENT_DELAY 2'd0; + wsi_S0_reqFifo_levelsValid <= `BSV_ASSIGNMENT_DELAY 1'd1; + wsi_S0_tBusyCount <= `BSV_ASSIGNMENT_DELAY 32'd0; + wsi_S0_trafficSticky <= `BSV_ASSIGNMENT_DELAY 1'd0; + wsi_S0_wordCount <= `BSV_ASSIGNMENT_DELAY 12'd1; + wsi_S1_burstKind <= `BSV_ASSIGNMENT_DELAY 2'd0; + wsi_S1_errorSticky <= `BSV_ASSIGNMENT_DELAY 1'd0; + wsi_S1_iMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0; + wsi_S1_operateD <= `BSV_ASSIGNMENT_DELAY 1'd0; + wsi_S1_pMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0; + wsi_S1_peerIsReady <= `BSV_ASSIGNMENT_DELAY 1'd0; + wsi_S1_reqFifo_countReg <= `BSV_ASSIGNMENT_DELAY 2'd0; + wsi_S1_reqFifo_levelsValid <= `BSV_ASSIGNMENT_DELAY 1'd1; + wsi_S1_tBusyCount <= `BSV_ASSIGNMENT_DELAY 32'd0; + wsi_S1_trafficSticky <= `BSV_ASSIGNMENT_DELAY 1'd0; + wsi_S1_wordCount <= `BSV_ASSIGNMENT_DELAY 12'd1; + end + else + begin + if (splitCtrl$EN) splitCtrl <= `BSV_ASSIGNMENT_DELAY splitCtrl$D_IN; + if (wci_cEdge$EN) wci_cEdge <= `BSV_ASSIGNMENT_DELAY wci_cEdge$D_IN; + if (wci_cState$EN) + wci_cState <= `BSV_ASSIGNMENT_DELAY wci_cState$D_IN; + if (wci_ctlAckReg$EN) + wci_ctlAckReg <= `BSV_ASSIGNMENT_DELAY wci_ctlAckReg$D_IN; + if (wci_ctlOpActive$EN) + wci_ctlOpActive <= `BSV_ASSIGNMENT_DELAY wci_ctlOpActive$D_IN; + if (wci_illegalEdge$EN) + wci_illegalEdge <= `BSV_ASSIGNMENT_DELAY wci_illegalEdge$D_IN; + if (wci_nState$EN) + wci_nState <= `BSV_ASSIGNMENT_DELAY wci_nState$D_IN; + if (wci_reqF_countReg$EN) + wci_reqF_countReg <= `BSV_ASSIGNMENT_DELAY wci_reqF_countReg$D_IN; + if (wci_respF_c_r$EN) + wci_respF_c_r <= `BSV_ASSIGNMENT_DELAY wci_respF_c_r$D_IN; + if (wci_respF_q_0$EN) + wci_respF_q_0 <= `BSV_ASSIGNMENT_DELAY wci_respF_q_0$D_IN; + if (wci_respF_q_1$EN) + wci_respF_q_1 <= `BSV_ASSIGNMENT_DELAY wci_respF_q_1$D_IN; + if (wci_sFlagReg$EN) + wci_sFlagReg <= `BSV_ASSIGNMENT_DELAY wci_sFlagReg$D_IN; + if (wci_sThreadBusy_d$EN) + wci_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY wci_sThreadBusy_d$D_IN; + if (wsi_M0_burstKind$EN) + wsi_M0_burstKind <= `BSV_ASSIGNMENT_DELAY wsi_M0_burstKind$D_IN; + if (wsi_M0_errorSticky$EN) + wsi_M0_errorSticky <= `BSV_ASSIGNMENT_DELAY wsi_M0_errorSticky$D_IN; + if (wsi_M0_iMesgCount$EN) + wsi_M0_iMesgCount <= `BSV_ASSIGNMENT_DELAY wsi_M0_iMesgCount$D_IN; + if (wsi_M0_operateD$EN) + wsi_M0_operateD <= `BSV_ASSIGNMENT_DELAY wsi_M0_operateD$D_IN; + if (wsi_M0_pMesgCount$EN) + wsi_M0_pMesgCount <= `BSV_ASSIGNMENT_DELAY wsi_M0_pMesgCount$D_IN; + if (wsi_M0_peerIsReady$EN) + wsi_M0_peerIsReady <= `BSV_ASSIGNMENT_DELAY wsi_M0_peerIsReady$D_IN; + if (wsi_M0_reqFifo_c_r$EN) + wsi_M0_reqFifo_c_r <= `BSV_ASSIGNMENT_DELAY wsi_M0_reqFifo_c_r$D_IN; + if (wsi_M0_reqFifo_q_0$EN) + wsi_M0_reqFifo_q_0 <= `BSV_ASSIGNMENT_DELAY wsi_M0_reqFifo_q_0$D_IN; + if (wsi_M0_reqFifo_q_1$EN) + wsi_M0_reqFifo_q_1 <= `BSV_ASSIGNMENT_DELAY wsi_M0_reqFifo_q_1$D_IN; + if (wsi_M0_sThreadBusy_d$EN) + wsi_M0_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY + wsi_M0_sThreadBusy_d$D_IN; + if (wsi_M0_tBusyCount$EN) + wsi_M0_tBusyCount <= `BSV_ASSIGNMENT_DELAY wsi_M0_tBusyCount$D_IN; + if (wsi_M0_trafficSticky$EN) + wsi_M0_trafficSticky <= `BSV_ASSIGNMENT_DELAY + wsi_M0_trafficSticky$D_IN; + if (wsi_M1_burstKind$EN) + wsi_M1_burstKind <= `BSV_ASSIGNMENT_DELAY wsi_M1_burstKind$D_IN; + if (wsi_M1_errorSticky$EN) + wsi_M1_errorSticky <= `BSV_ASSIGNMENT_DELAY wsi_M1_errorSticky$D_IN; + if (wsi_M1_iMesgCount$EN) + wsi_M1_iMesgCount <= `BSV_ASSIGNMENT_DELAY wsi_M1_iMesgCount$D_IN; + if (wsi_M1_operateD$EN) + wsi_M1_operateD <= `BSV_ASSIGNMENT_DELAY wsi_M1_operateD$D_IN; + if (wsi_M1_pMesgCount$EN) + wsi_M1_pMesgCount <= `BSV_ASSIGNMENT_DELAY wsi_M1_pMesgCount$D_IN; + if (wsi_M1_peerIsReady$EN) + wsi_M1_peerIsReady <= `BSV_ASSIGNMENT_DELAY wsi_M1_peerIsReady$D_IN; + if (wsi_M1_reqFifo_c_r$EN) + wsi_M1_reqFifo_c_r <= `BSV_ASSIGNMENT_DELAY wsi_M1_reqFifo_c_r$D_IN; + if (wsi_M1_reqFifo_q_0$EN) + wsi_M1_reqFifo_q_0 <= `BSV_ASSIGNMENT_DELAY wsi_M1_reqFifo_q_0$D_IN; + if (wsi_M1_reqFifo_q_1$EN) + wsi_M1_reqFifo_q_1 <= `BSV_ASSIGNMENT_DELAY wsi_M1_reqFifo_q_1$D_IN; + if (wsi_M1_sThreadBusy_d$EN) + wsi_M1_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY + wsi_M1_sThreadBusy_d$D_IN; + if (wsi_M1_tBusyCount$EN) + wsi_M1_tBusyCount <= `BSV_ASSIGNMENT_DELAY wsi_M1_tBusyCount$D_IN; + if (wsi_M1_trafficSticky$EN) + wsi_M1_trafficSticky <= `BSV_ASSIGNMENT_DELAY + wsi_M1_trafficSticky$D_IN; + if (wsi_S0_burstKind$EN) + wsi_S0_burstKind <= `BSV_ASSIGNMENT_DELAY wsi_S0_burstKind$D_IN; + if (wsi_S0_errorSticky$EN) + wsi_S0_errorSticky <= `BSV_ASSIGNMENT_DELAY wsi_S0_errorSticky$D_IN; + if (wsi_S0_iMesgCount$EN) + wsi_S0_iMesgCount <= `BSV_ASSIGNMENT_DELAY wsi_S0_iMesgCount$D_IN; + if (wsi_S0_operateD$EN) + wsi_S0_operateD <= `BSV_ASSIGNMENT_DELAY wsi_S0_operateD$D_IN; + if (wsi_S0_pMesgCount$EN) + wsi_S0_pMesgCount <= `BSV_ASSIGNMENT_DELAY wsi_S0_pMesgCount$D_IN; + if (wsi_S0_peerIsReady$EN) + wsi_S0_peerIsReady <= `BSV_ASSIGNMENT_DELAY wsi_S0_peerIsReady$D_IN; + if (wsi_S0_reqFifo_countReg$EN) + wsi_S0_reqFifo_countReg <= `BSV_ASSIGNMENT_DELAY + wsi_S0_reqFifo_countReg$D_IN; + if (wsi_S0_reqFifo_levelsValid$EN) + wsi_S0_reqFifo_levelsValid <= `BSV_ASSIGNMENT_DELAY + wsi_S0_reqFifo_levelsValid$D_IN; + if (wsi_S0_tBusyCount$EN) + wsi_S0_tBusyCount <= `BSV_ASSIGNMENT_DELAY wsi_S0_tBusyCount$D_IN; + if (wsi_S0_trafficSticky$EN) + wsi_S0_trafficSticky <= `BSV_ASSIGNMENT_DELAY + wsi_S0_trafficSticky$D_IN; + if (wsi_S0_wordCount$EN) + wsi_S0_wordCount <= `BSV_ASSIGNMENT_DELAY wsi_S0_wordCount$D_IN; + if (wsi_S1_burstKind$EN) + wsi_S1_burstKind <= `BSV_ASSIGNMENT_DELAY wsi_S1_burstKind$D_IN; + if (wsi_S1_errorSticky$EN) + wsi_S1_errorSticky <= `BSV_ASSIGNMENT_DELAY wsi_S1_errorSticky$D_IN; + if (wsi_S1_iMesgCount$EN) + wsi_S1_iMesgCount <= `BSV_ASSIGNMENT_DELAY wsi_S1_iMesgCount$D_IN; + if (wsi_S1_operateD$EN) + wsi_S1_operateD <= `BSV_ASSIGNMENT_DELAY wsi_S1_operateD$D_IN; + if (wsi_S1_pMesgCount$EN) + wsi_S1_pMesgCount <= `BSV_ASSIGNMENT_DELAY wsi_S1_pMesgCount$D_IN; + if (wsi_S1_peerIsReady$EN) + wsi_S1_peerIsReady <= `BSV_ASSIGNMENT_DELAY wsi_S1_peerIsReady$D_IN; + if (wsi_S1_reqFifo_countReg$EN) + wsi_S1_reqFifo_countReg <= `BSV_ASSIGNMENT_DELAY + wsi_S1_reqFifo_countReg$D_IN; + if (wsi_S1_reqFifo_levelsValid$EN) + wsi_S1_reqFifo_levelsValid <= `BSV_ASSIGNMENT_DELAY + wsi_S1_reqFifo_levelsValid$D_IN; + if (wsi_S1_tBusyCount$EN) + wsi_S1_tBusyCount <= `BSV_ASSIGNMENT_DELAY wsi_S1_tBusyCount$D_IN; + if (wsi_S1_trafficSticky$EN) + wsi_S1_trafficSticky <= `BSV_ASSIGNMENT_DELAY + wsi_S1_trafficSticky$D_IN; + if (wsi_S1_wordCount$EN) + wsi_S1_wordCount <= `BSV_ASSIGNMENT_DELAY wsi_S1_wordCount$D_IN; + end + if (wsi_M0_statusR$EN) + wsi_M0_statusR <= `BSV_ASSIGNMENT_DELAY wsi_M0_statusR$D_IN; + if (wsi_M1_statusR$EN) + wsi_M1_statusR <= `BSV_ASSIGNMENT_DELAY wsi_M1_statusR$D_IN; + if (wsi_S0_mesgWordLength$EN) + wsi_S0_mesgWordLength <= `BSV_ASSIGNMENT_DELAY + wsi_S0_mesgWordLength$D_IN; + if (wsi_S0_statusR$EN) + wsi_S0_statusR <= `BSV_ASSIGNMENT_DELAY wsi_S0_statusR$D_IN; + if (wsi_S1_mesgWordLength$EN) + wsi_S1_mesgWordLength <= `BSV_ASSIGNMENT_DELAY + wsi_S1_mesgWordLength$D_IN; + if (wsi_S1_statusR$EN) + wsi_S1_statusR <= `BSV_ASSIGNMENT_DELAY wsi_S1_statusR$D_IN; + end + + always@(posedge wciS0_Clk or `BSV_RESET_EDGE wciS0_MReset_n) + if (wciS0_MReset_n == `BSV_RESET_VALUE) + begin + wci_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY 1'd1; + wsi_M0_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY 1'd1; + wsi_M1_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY 1'd1; + wsi_S0_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY 1'd1; + wsi_S1_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY 1'd1; + end + else + begin + if (wci_isReset_isInReset$EN) + wci_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY + wci_isReset_isInReset$D_IN; + if (wsi_M0_isReset_isInReset$EN) + wsi_M0_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY + wsi_M0_isReset_isInReset$D_IN; + if (wsi_M1_isReset_isInReset$EN) + wsi_M1_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY + wsi_M1_isReset_isInReset$D_IN; + if (wsi_S0_isReset_isInReset$EN) + wsi_S0_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY + wsi_S0_isReset_isInReset$D_IN; + if (wsi_S1_isReset_isInReset$EN) + wsi_S1_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY + wsi_S1_isReset_isInReset$D_IN; + end + + // synopsys translate_off + `ifdef BSV_NO_INITIAL_BLOCKS + `else // not BSV_NO_INITIAL_BLOCKS + initial + begin + splitCtrl = 32'hAAAAAAAA; + wci_cEdge = 3'h2; + wci_cState = 3'h2; + wci_ctlAckReg = 1'h0; + wci_ctlOpActive = 1'h0; + wci_illegalEdge = 1'h0; + wci_isReset_isInReset = 1'h0; + wci_nState = 3'h2; + wci_reqF_countReg = 2'h2; + wci_respF_c_r = 2'h2; + wci_respF_q_0 = 34'h2AAAAAAAA; + wci_respF_q_1 = 34'h2AAAAAAAA; + wci_sFlagReg = 1'h0; + wci_sThreadBusy_d = 1'h0; + wsi_M0_burstKind = 2'h2; + wsi_M0_errorSticky = 1'h0; + wsi_M0_iMesgCount = 32'hAAAAAAAA; + wsi_M0_isReset_isInReset = 1'h0; + wsi_M0_operateD = 1'h0; + wsi_M0_pMesgCount = 32'hAAAAAAAA; + wsi_M0_peerIsReady = 1'h0; + wsi_M0_reqFifo_c_r = 2'h2; + wsi_M0_reqFifo_q_0 = 61'h0AAAAAAAAAAAAAAA; + wsi_M0_reqFifo_q_1 = 61'h0AAAAAAAAAAAAAAA; + wsi_M0_sThreadBusy_d = 1'h0; + wsi_M0_statusR = 8'hAA; + wsi_M0_tBusyCount = 32'hAAAAAAAA; + wsi_M0_trafficSticky = 1'h0; + wsi_M1_burstKind = 2'h2; + wsi_M1_errorSticky = 1'h0; + wsi_M1_iMesgCount = 32'hAAAAAAAA; + wsi_M1_isReset_isInReset = 1'h0; + wsi_M1_operateD = 1'h0; + wsi_M1_pMesgCount = 32'hAAAAAAAA; + wsi_M1_peerIsReady = 1'h0; + wsi_M1_reqFifo_c_r = 2'h2; + wsi_M1_reqFifo_q_0 = 61'h0AAAAAAAAAAAAAAA; + wsi_M1_reqFifo_q_1 = 61'h0AAAAAAAAAAAAAAA; + wsi_M1_sThreadBusy_d = 1'h0; + wsi_M1_statusR = 8'hAA; + wsi_M1_tBusyCount = 32'hAAAAAAAA; + wsi_M1_trafficSticky = 1'h0; + wsi_S0_burstKind = 2'h2; + wsi_S0_errorSticky = 1'h0; + wsi_S0_iMesgCount = 32'hAAAAAAAA; + wsi_S0_isReset_isInReset = 1'h0; + wsi_S0_mesgWordLength = 12'hAAA; + wsi_S0_operateD = 1'h0; + wsi_S0_pMesgCount = 32'hAAAAAAAA; + wsi_S0_peerIsReady = 1'h0; + wsi_S0_reqFifo_countReg = 2'h2; + wsi_S0_reqFifo_levelsValid = 1'h0; + wsi_S0_statusR = 8'hAA; + wsi_S0_tBusyCount = 32'hAAAAAAAA; + wsi_S0_trafficSticky = 1'h0; + wsi_S0_wordCount = 12'hAAA; + wsi_S1_burstKind = 2'h2; + wsi_S1_errorSticky = 1'h0; + wsi_S1_iMesgCount = 32'hAAAAAAAA; + wsi_S1_isReset_isInReset = 1'h0; + wsi_S1_mesgWordLength = 12'hAAA; + wsi_S1_operateD = 1'h0; + wsi_S1_pMesgCount = 32'hAAAAAAAA; + wsi_S1_peerIsReady = 1'h0; + wsi_S1_reqFifo_countReg = 2'h2; + wsi_S1_reqFifo_levelsValid = 1'h0; + wsi_S1_statusR = 8'hAA; + wsi_S1_tBusyCount = 32'hAAAAAAAA; + wsi_S1_trafficSticky = 1'h0; + wsi_S1_wordCount = 12'hAAA; + end + `endif // BSV_NO_INITIAL_BLOCKS + // synopsys translate_on + + // handling of system tasks + + // synopsys translate_off + always@(negedge wciS0_Clk) + begin + #0; + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_ctl_op_start) + begin + v__h3698 = $time; + #0; + end + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_ctl_op_start) + $display("[%0d]: %m: WCI ControlOp: Starting-transition edge:%x from:%x", + v__h3698, + wci_reqF$D_OUT[36:34], + wci_cState); + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_ctrl_EiI && WILL_FIRE_RL_wci_ctrl_OrE) + $display("Error: \"bsv/inf/WsiSplitter2x2.bsv\", line 48, column 46: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_EiI] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n"); + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_ctrl_EiI && WILL_FIRE_RL_wci_ctrl_IsO) + $display("Error: \"bsv/inf/WsiSplitter2x2.bsv\", line 48, column 46: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_EiI] and\n [RL_wci_ctrl_IsO] ) fired in the same clock cycle.\n"); + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_ctrl_IsO && WILL_FIRE_RL_wci_ctrl_OrE) + $display("Error: \"bsv/inf/WsiSplitter2x2.bsv\", line 48, column 60: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_IsO] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n"); + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_cfwr) + begin + v__h16289 = $time; + #0; + end + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_cfwr) + $display("[%0d]: %m: WCI CONFIG WRITE Addr:%0x BE:%0x Data:%0x", + v__h16289, + wci_reqF$D_OUT[63:32], + wci_reqF$D_OUT[67:64], + wci_reqF$D_OUT[31:0]); + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_ctl_op_complete && wci_illegalEdge) + begin + v__h4017 = $time; + #0; + end + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_ctl_op_complete && wci_illegalEdge) + $display("[%0d]: %m: WCI ControlOp: ILLEGAL-EDGE Completed-transition edge:%x from:%x", + v__h4017, + wci_cEdge, + wci_cState); + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_ctl_op_complete && !wci_illegalEdge) + begin + v__h3873 = $time; + #0; + end + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_ctl_op_complete && !wci_illegalEdge) + $display("[%0d]: %m: WCI ControlOp: Completed-transition edge:%x from:%x to:%x", + v__h3873, + wci_cEdge, + wci_cState, + wci_nState); + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_cfrd) + begin + v__h16444 = $time; + #0; + end + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_cfrd) + $display("[%0d]: %m: WCI CONFIG READ Addr:%0x BE:%0x Data:%0x", + v__h16444, + wci_reqF$D_OUT[63:32], + wci_reqF$D_OUT[67:64], + _theResult____h16428); + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_OrE) + $display("Error: \"bsv/inf/WsiSplitter2x2.bsv\", line 48, column 26: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n"); + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_IsO) + $display("Error: \"bsv/inf/WsiSplitter2x2.bsv\", line 48, column 26: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_wci_ctrl_IsO] ) fired in the same clock cycle.\n"); + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_EiI) + $display("Error: \"bsv/inf/WsiSplitter2x2.bsv\", line 48, column 26: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_wci_ctrl_EiI] ) fired in the same clock cycle.\n"); + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_cfrd) + $display("Error: \"bsv/inf/WsiSplitter2x2.bsv\", line 48, column 26: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and [RL_wci_cfrd] )\n fired in the same clock cycle.\n"); + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_cfrd && WILL_FIRE_RL_wci_ctrl_OrE) + $display("Error: \"bsv/inf/WsiSplitter2x2.bsv\", line 48, column 36: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n"); + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_cfrd && WILL_FIRE_RL_wci_ctrl_IsO) + $display("Error: \"bsv/inf/WsiSplitter2x2.bsv\", line 48, column 36: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n [RL_wci_ctrl_IsO] ) fired in the same clock cycle.\n"); + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_cfrd && WILL_FIRE_RL_wci_ctrl_EiI) + $display("Error: \"bsv/inf/WsiSplitter2x2.bsv\", line 48, column 36: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n [RL_wci_ctrl_EiI] ) fired in the same clock cycle.\n"); + end + // synopsys translate_on +endmodule // mkWsiSplitter2x24B + diff --git a/rtl/mkWsiSplitter2x28B.v b/rtl/mkWsiSplitter2x28B.v new file mode 100644 index 00000000..7255474a --- /dev/null +++ b/rtl/mkWsiSplitter2x28B.v @@ -0,0 +1,2446 @@ +// +// Generated by Bluespec Compiler, version 2012.09.beta1 (build 29570, 2012-09.11) +// +// On Tue Jan 22 07:33:04 EST 2013 +// +// +// Ports: +// Name I/O size props +// wciS0_SResp O 2 reg +// wciS0_SData O 32 reg +// wciS0_SThreadBusy O 1 +// wciS0_SFlag O 2 +// wsiS0_SThreadBusy O 1 +// wsiS0_SReset_n O 1 +// wsiS1_SThreadBusy O 1 +// wsiS1_SReset_n O 1 +// wsiM0_MCmd O 3 +// wsiM0_MReqLast O 1 +// wsiM0_MBurstPrecise O 1 +// wsiM0_MBurstLength O 12 +// wsiM0_MData O 64 reg +// wsiM0_MByteEn O 8 reg +// wsiM0_MReqInfo O 8 +// wsiM0_MReset_n O 1 +// wsiM1_MCmd O 3 +// wsiM1_MReqLast O 1 +// wsiM1_MBurstPrecise O 1 +// wsiM1_MBurstLength O 12 +// wsiM1_MData O 64 reg +// wsiM1_MByteEn O 8 reg +// wsiM1_MReqInfo O 8 +// wsiM1_MReset_n O 1 +// wciS0_Clk I 1 clock +// wciS0_MReset_n I 1 reset +// wciS0_MCmd I 3 +// wciS0_MAddrSpace I 1 +// wciS0_MByteEn I 4 +// wciS0_MAddr I 32 +// wciS0_MData I 32 +// wciS0_MFlag I 2 unused +// wsiS0_MCmd I 3 +// wsiS0_MBurstLength I 12 +// wsiS0_MData I 64 +// wsiS0_MByteEn I 8 +// wsiS0_MReqInfo I 8 +// wsiS1_MCmd I 3 +// wsiS1_MBurstLength I 12 +// wsiS1_MData I 64 +// wsiS1_MByteEn I 8 +// wsiS1_MReqInfo I 8 +// wsiS0_MReqLast I 1 +// wsiS0_MBurstPrecise I 1 +// wsiS0_MReset_n I 1 reg +// wsiS1_MReqLast I 1 +// wsiS1_MBurstPrecise I 1 +// wsiS1_MReset_n I 1 reg +// wsiM0_SThreadBusy I 1 reg +// wsiM0_SReset_n I 1 reg +// wsiM1_SThreadBusy I 1 reg +// wsiM1_SReset_n I 1 reg +// +// No combinational paths from inputs to outputs +// +// + +`ifdef BSV_ASSIGNMENT_DELAY +`else + `define BSV_ASSIGNMENT_DELAY +`endif + +`ifdef BSV_POSITIVE_RESET + `define BSV_RESET_VALUE 1'b1 + `define BSV_RESET_EDGE posedge +`else + `define BSV_RESET_VALUE 1'b0 + `define BSV_RESET_EDGE negedge +`endif + +module mkWsiSplitter2x28B(wciS0_Clk, + wciS0_MReset_n, + + wciS0_MCmd, + + wciS0_MAddrSpace, + + wciS0_MByteEn, + + wciS0_MAddr, + + wciS0_MData, + + wciS0_SResp, + + wciS0_SData, + + wciS0_SThreadBusy, + + wciS0_SFlag, + + wciS0_MFlag, + + wsiS0_MCmd, + + wsiS0_MReqLast, + + wsiS0_MBurstPrecise, + + wsiS0_MBurstLength, + + wsiS0_MData, + + wsiS0_MByteEn, + + wsiS0_MReqInfo, + + wsiS0_SThreadBusy, + + wsiS0_SReset_n, + + wsiS0_MReset_n, + + wsiS1_MCmd, + + wsiS1_MReqLast, + + wsiS1_MBurstPrecise, + + wsiS1_MBurstLength, + + wsiS1_MData, + + wsiS1_MByteEn, + + wsiS1_MReqInfo, + + wsiS1_SThreadBusy, + + wsiS1_SReset_n, + + wsiS1_MReset_n, + + wsiM0_MCmd, + + wsiM0_MReqLast, + + wsiM0_MBurstPrecise, + + wsiM0_MBurstLength, + + wsiM0_MData, + + wsiM0_MByteEn, + + wsiM0_MReqInfo, + + wsiM0_SThreadBusy, + + wsiM0_MReset_n, + + wsiM0_SReset_n, + + wsiM1_MCmd, + + wsiM1_MReqLast, + + wsiM1_MBurstPrecise, + + wsiM1_MBurstLength, + + wsiM1_MData, + + wsiM1_MByteEn, + + wsiM1_MReqInfo, + + wsiM1_SThreadBusy, + + wsiM1_MReset_n, + + wsiM1_SReset_n); + parameter [31 : 0] ctrlInit = 32'b0; + parameter [0 : 0] hasDebugLogic = 1'b0; + input wciS0_Clk; + input wciS0_MReset_n; + + // action method wciS0_mCmd + input [2 : 0] wciS0_MCmd; + + // action method wciS0_mAddrSpace + input wciS0_MAddrSpace; + + // action method wciS0_mByteEn + input [3 : 0] wciS0_MByteEn; + + // action method wciS0_mAddr + input [31 : 0] wciS0_MAddr; + + // action method wciS0_mData + input [31 : 0] wciS0_MData; + + // value method wciS0_sResp + output [1 : 0] wciS0_SResp; + + // value method wciS0_sData + output [31 : 0] wciS0_SData; + + // value method wciS0_sThreadBusy + output wciS0_SThreadBusy; + + // value method wciS0_sFlag + output [1 : 0] wciS0_SFlag; + + // action method wciS0_mFlag + input [1 : 0] wciS0_MFlag; + + // action method wsiS0_mCmd + input [2 : 0] wsiS0_MCmd; + + // action method wsiS0_mReqLast + input wsiS0_MReqLast; + + // action method wsiS0_mBurstPrecise + input wsiS0_MBurstPrecise; + + // action method wsiS0_mBurstLength + input [11 : 0] wsiS0_MBurstLength; + + // action method wsiS0_mData + input [63 : 0] wsiS0_MData; + + // action method wsiS0_mByteEn + input [7 : 0] wsiS0_MByteEn; + + // action method wsiS0_mReqInfo + input [7 : 0] wsiS0_MReqInfo; + + // action method wsiS0_mDataInfo + + // value method wsiS0_sThreadBusy + output wsiS0_SThreadBusy; + + // value method wsiS0_sReset_n + output wsiS0_SReset_n; + + // action method wsiS0_mReset_n + input wsiS0_MReset_n; + + // action method wsiS1_mCmd + input [2 : 0] wsiS1_MCmd; + + // action method wsiS1_mReqLast + input wsiS1_MReqLast; + + // action method wsiS1_mBurstPrecise + input wsiS1_MBurstPrecise; + + // action method wsiS1_mBurstLength + input [11 : 0] wsiS1_MBurstLength; + + // action method wsiS1_mData + input [63 : 0] wsiS1_MData; + + // action method wsiS1_mByteEn + input [7 : 0] wsiS1_MByteEn; + + // action method wsiS1_mReqInfo + input [7 : 0] wsiS1_MReqInfo; + + // action method wsiS1_mDataInfo + + // value method wsiS1_sThreadBusy + output wsiS1_SThreadBusy; + + // value method wsiS1_sReset_n + output wsiS1_SReset_n; + + // action method wsiS1_mReset_n + input wsiS1_MReset_n; + + // value method wsiM0_mCmd + output [2 : 0] wsiM0_MCmd; + + // value method wsiM0_mReqLast + output wsiM0_MReqLast; + + // value method wsiM0_mBurstPrecise + output wsiM0_MBurstPrecise; + + // value method wsiM0_mBurstLength + output [11 : 0] wsiM0_MBurstLength; + + // value method wsiM0_mData + output [63 : 0] wsiM0_MData; + + // value method wsiM0_mByteEn + output [7 : 0] wsiM0_MByteEn; + + // value method wsiM0_mReqInfo + output [7 : 0] wsiM0_MReqInfo; + + // value method wsiM0_mDataInfo + + // action method wsiM0_sThreadBusy + input wsiM0_SThreadBusy; + + // value method wsiM0_mReset_n + output wsiM0_MReset_n; + + // action method wsiM0_sReset_n + input wsiM0_SReset_n; + + // value method wsiM1_mCmd + output [2 : 0] wsiM1_MCmd; + + // value method wsiM1_mReqLast + output wsiM1_MReqLast; + + // value method wsiM1_mBurstPrecise + output wsiM1_MBurstPrecise; + + // value method wsiM1_mBurstLength + output [11 : 0] wsiM1_MBurstLength; + + // value method wsiM1_mData + output [63 : 0] wsiM1_MData; + + // value method wsiM1_mByteEn + output [7 : 0] wsiM1_MByteEn; + + // value method wsiM1_mReqInfo + output [7 : 0] wsiM1_MReqInfo; + + // value method wsiM1_mDataInfo + + // action method wsiM1_sThreadBusy + input wsiM1_SThreadBusy; + + // value method wsiM1_mReset_n + output wsiM1_MReset_n; + + // action method wsiM1_sReset_n + input wsiM1_SReset_n; + + // signals for module outputs + wire [63 : 0] wsiM0_MData, wsiM1_MData; + wire [31 : 0] wciS0_SData; + wire [11 : 0] wsiM0_MBurstLength, wsiM1_MBurstLength; + wire [7 : 0] wsiM0_MByteEn, wsiM0_MReqInfo, wsiM1_MByteEn, wsiM1_MReqInfo; + wire [2 : 0] wsiM0_MCmd, wsiM1_MCmd; + wire [1 : 0] wciS0_SFlag, wciS0_SResp; + wire wciS0_SThreadBusy, + wsiM0_MBurstPrecise, + wsiM0_MReqLast, + wsiM0_MReset_n, + wsiM1_MBurstPrecise, + wsiM1_MReqLast, + wsiM1_MReset_n, + wsiS0_SReset_n, + wsiS0_SThreadBusy, + wsiS1_SReset_n, + wsiS1_SThreadBusy; + + // inlined wires + wire [96 : 0] wsi_M0_reqFifo_x_wire$wget, + wsi_M1_reqFifo_x_wire$wget, + wsi_S0_wsiReq$wget, + wsi_S1_wsiReq$wget; + wire [95 : 0] wsi_M0_extStatusW$wget, + wsi_M1_extStatusW$wget, + wsi_S0_extStatusW$wget, + wsi_S1_extStatusW$wget; + wire [71 : 0] wci_wciReq$wget; + wire [63 : 0] wsi_Es0_mData_w$wget, wsi_Es1_mData_w$wget; + wire [33 : 0] wci_respF_x_wire$wget; + wire [31 : 0] wci_Es_mAddr_w$wget, wci_Es_mData_w$wget; + wire [11 : 0] wsi_Es0_mBurstLength_w$wget, wsi_Es1_mBurstLength_w$wget; + wire [7 : 0] wsi_Es0_mByteEn_w$wget, + wsi_Es0_mReqInfo_w$wget, + wsi_Es1_mByteEn_w$wget, + wsi_Es1_mReqInfo_w$wget; + wire [3 : 0] wci_Es_mByteEn_w$wget; + wire [2 : 0] wci_Es_mCmd_w$wget, + wci_wEdge$wget, + wsi_Es0_mCmd_w$wget, + wsi_Es1_mCmd_w$wget; + wire wci_Es_mAddrSpace_w$wget, + wci_Es_mAddrSpace_w$whas, + wci_Es_mAddr_w$whas, + wci_Es_mByteEn_w$whas, + wci_Es_mCmd_w$whas, + wci_Es_mData_w$whas, + wci_ctlAckReg_1$wget, + wci_ctlAckReg_1$whas, + wci_reqF_r_clr$whas, + wci_reqF_r_deq$whas, + wci_reqF_r_enq$whas, + wci_respF_dequeueing$whas, + wci_respF_enqueueing$whas, + wci_respF_x_wire$whas, + wci_sFlagReg_1$wget, + wci_sFlagReg_1$whas, + wci_sThreadBusy_pw$whas, + wci_wEdge$whas, + wci_wciReq$whas, + wci_wci_cfrd_pw$whas, + wci_wci_cfwr_pw$whas, + wci_wci_ctrl_pw$whas, + wsi_Es0_mBurstLength_w$whas, + wsi_Es0_mBurstPrecise_w$whas, + wsi_Es0_mByteEn_w$whas, + wsi_Es0_mCmd_w$whas, + wsi_Es0_mDataInfo_w$whas, + wsi_Es0_mData_w$whas, + wsi_Es0_mReqInfo_w$whas, + wsi_Es0_mReqLast_w$whas, + wsi_Es1_mBurstLength_w$whas, + wsi_Es1_mBurstPrecise_w$whas, + wsi_Es1_mByteEn_w$whas, + wsi_Es1_mCmd_w$whas, + wsi_Es1_mDataInfo_w$whas, + wsi_Es1_mData_w$whas, + wsi_Es1_mReqInfo_w$whas, + wsi_Es1_mReqLast_w$whas, + wsi_M0_operateD_1$wget, + wsi_M0_operateD_1$whas, + wsi_M0_peerIsReady_1$wget, + wsi_M0_peerIsReady_1$whas, + wsi_M0_reqFifo_dequeueing$whas, + wsi_M0_reqFifo_enqueueing$whas, + wsi_M0_reqFifo_x_wire$whas, + wsi_M0_sThreadBusy_pw$whas, + wsi_M1_operateD_1$wget, + wsi_M1_operateD_1$whas, + wsi_M1_peerIsReady_1$wget, + wsi_M1_peerIsReady_1$whas, + wsi_M1_reqFifo_dequeueing$whas, + wsi_M1_reqFifo_enqueueing$whas, + wsi_M1_reqFifo_x_wire$whas, + wsi_M1_sThreadBusy_pw$whas, + wsi_S0_operateD_1$wget, + wsi_S0_operateD_1$whas, + wsi_S0_peerIsReady_1$wget, + wsi_S0_peerIsReady_1$whas, + wsi_S0_reqFifo_doResetClr$whas, + wsi_S0_reqFifo_doResetDeq$whas, + wsi_S0_reqFifo_doResetEnq$whas, + wsi_S0_reqFifo_r_clr$whas, + wsi_S0_reqFifo_r_deq$whas, + wsi_S0_reqFifo_r_enq$whas, + wsi_S0_sThreadBusy_dw$wget, + wsi_S0_sThreadBusy_dw$whas, + wsi_S0_wsiReq$whas, + wsi_S1_operateD_1$wget, + wsi_S1_operateD_1$whas, + wsi_S1_peerIsReady_1$wget, + wsi_S1_peerIsReady_1$whas, + wsi_S1_reqFifo_doResetClr$whas, + wsi_S1_reqFifo_doResetDeq$whas, + wsi_S1_reqFifo_doResetEnq$whas, + wsi_S1_reqFifo_r_clr$whas, + wsi_S1_reqFifo_r_deq$whas, + wsi_S1_reqFifo_r_enq$whas, + wsi_S1_sThreadBusy_dw$wget, + wsi_S1_sThreadBusy_dw$whas, + wsi_S1_wsiReq$whas; + + // register splitCtrl + reg [31 : 0] splitCtrl; + wire [31 : 0] splitCtrl$D_IN; + wire splitCtrl$EN; + + // register wci_cEdge + reg [2 : 0] wci_cEdge; + wire [2 : 0] wci_cEdge$D_IN; + wire wci_cEdge$EN; + + // register wci_cState + reg [2 : 0] wci_cState; + wire [2 : 0] wci_cState$D_IN; + wire wci_cState$EN; + + // register wci_ctlAckReg + reg wci_ctlAckReg; + wire wci_ctlAckReg$D_IN, wci_ctlAckReg$EN; + + // register wci_ctlOpActive + reg wci_ctlOpActive; + wire wci_ctlOpActive$D_IN, wci_ctlOpActive$EN; + + // register wci_illegalEdge + reg wci_illegalEdge; + wire wci_illegalEdge$D_IN, wci_illegalEdge$EN; + + // register wci_isReset_isInReset + reg wci_isReset_isInReset; + wire wci_isReset_isInReset$D_IN, wci_isReset_isInReset$EN; + + // register wci_nState + reg [2 : 0] wci_nState; + reg [2 : 0] wci_nState$D_IN; + wire wci_nState$EN; + + // register wci_reqF_countReg + reg [1 : 0] wci_reqF_countReg; + wire [1 : 0] wci_reqF_countReg$D_IN; + wire wci_reqF_countReg$EN; + + // register wci_respF_c_r + reg [1 : 0] wci_respF_c_r; + wire [1 : 0] wci_respF_c_r$D_IN; + wire wci_respF_c_r$EN; + + // register wci_respF_q_0 + reg [33 : 0] wci_respF_q_0; + reg [33 : 0] wci_respF_q_0$D_IN; + wire wci_respF_q_0$EN; + + // register wci_respF_q_1 + reg [33 : 0] wci_respF_q_1; + reg [33 : 0] wci_respF_q_1$D_IN; + wire wci_respF_q_1$EN; + + // register wci_sFlagReg + reg wci_sFlagReg; + wire wci_sFlagReg$D_IN, wci_sFlagReg$EN; + + // register wci_sThreadBusy_d + reg wci_sThreadBusy_d; + wire wci_sThreadBusy_d$D_IN, wci_sThreadBusy_d$EN; + + // register wsi_M0_burstKind + reg [1 : 0] wsi_M0_burstKind; + wire [1 : 0] wsi_M0_burstKind$D_IN; + wire wsi_M0_burstKind$EN; + + // register wsi_M0_errorSticky + reg wsi_M0_errorSticky; + wire wsi_M0_errorSticky$D_IN, wsi_M0_errorSticky$EN; + + // register wsi_M0_iMesgCount + reg [31 : 0] wsi_M0_iMesgCount; + wire [31 : 0] wsi_M0_iMesgCount$D_IN; + wire wsi_M0_iMesgCount$EN; + + // register wsi_M0_isReset_isInReset + reg wsi_M0_isReset_isInReset; + wire wsi_M0_isReset_isInReset$D_IN, wsi_M0_isReset_isInReset$EN; + + // register wsi_M0_operateD + reg wsi_M0_operateD; + wire wsi_M0_operateD$D_IN, wsi_M0_operateD$EN; + + // register wsi_M0_pMesgCount + reg [31 : 0] wsi_M0_pMesgCount; + wire [31 : 0] wsi_M0_pMesgCount$D_IN; + wire wsi_M0_pMesgCount$EN; + + // register wsi_M0_peerIsReady + reg wsi_M0_peerIsReady; + wire wsi_M0_peerIsReady$D_IN, wsi_M0_peerIsReady$EN; + + // register wsi_M0_reqFifo_c_r + reg [1 : 0] wsi_M0_reqFifo_c_r; + wire [1 : 0] wsi_M0_reqFifo_c_r$D_IN; + wire wsi_M0_reqFifo_c_r$EN; + + // register wsi_M0_reqFifo_q_0 + reg [96 : 0] wsi_M0_reqFifo_q_0; + reg [96 : 0] wsi_M0_reqFifo_q_0$D_IN; + wire wsi_M0_reqFifo_q_0$EN; + + // register wsi_M0_reqFifo_q_1 + reg [96 : 0] wsi_M0_reqFifo_q_1; + reg [96 : 0] wsi_M0_reqFifo_q_1$D_IN; + wire wsi_M0_reqFifo_q_1$EN; + + // register wsi_M0_sThreadBusy_d + reg wsi_M0_sThreadBusy_d; + wire wsi_M0_sThreadBusy_d$D_IN, wsi_M0_sThreadBusy_d$EN; + + // register wsi_M0_statusR + reg [7 : 0] wsi_M0_statusR; + wire [7 : 0] wsi_M0_statusR$D_IN; + wire wsi_M0_statusR$EN; + + // register wsi_M0_tBusyCount + reg [31 : 0] wsi_M0_tBusyCount; + wire [31 : 0] wsi_M0_tBusyCount$D_IN; + wire wsi_M0_tBusyCount$EN; + + // register wsi_M0_trafficSticky + reg wsi_M0_trafficSticky; + wire wsi_M0_trafficSticky$D_IN, wsi_M0_trafficSticky$EN; + + // register wsi_M1_burstKind + reg [1 : 0] wsi_M1_burstKind; + wire [1 : 0] wsi_M1_burstKind$D_IN; + wire wsi_M1_burstKind$EN; + + // register wsi_M1_errorSticky + reg wsi_M1_errorSticky; + wire wsi_M1_errorSticky$D_IN, wsi_M1_errorSticky$EN; + + // register wsi_M1_iMesgCount + reg [31 : 0] wsi_M1_iMesgCount; + wire [31 : 0] wsi_M1_iMesgCount$D_IN; + wire wsi_M1_iMesgCount$EN; + + // register wsi_M1_isReset_isInReset + reg wsi_M1_isReset_isInReset; + wire wsi_M1_isReset_isInReset$D_IN, wsi_M1_isReset_isInReset$EN; + + // register wsi_M1_operateD + reg wsi_M1_operateD; + wire wsi_M1_operateD$D_IN, wsi_M1_operateD$EN; + + // register wsi_M1_pMesgCount + reg [31 : 0] wsi_M1_pMesgCount; + wire [31 : 0] wsi_M1_pMesgCount$D_IN; + wire wsi_M1_pMesgCount$EN; + + // register wsi_M1_peerIsReady + reg wsi_M1_peerIsReady; + wire wsi_M1_peerIsReady$D_IN, wsi_M1_peerIsReady$EN; + + // register wsi_M1_reqFifo_c_r + reg [1 : 0] wsi_M1_reqFifo_c_r; + wire [1 : 0] wsi_M1_reqFifo_c_r$D_IN; + wire wsi_M1_reqFifo_c_r$EN; + + // register wsi_M1_reqFifo_q_0 + reg [96 : 0] wsi_M1_reqFifo_q_0; + reg [96 : 0] wsi_M1_reqFifo_q_0$D_IN; + wire wsi_M1_reqFifo_q_0$EN; + + // register wsi_M1_reqFifo_q_1 + reg [96 : 0] wsi_M1_reqFifo_q_1; + reg [96 : 0] wsi_M1_reqFifo_q_1$D_IN; + wire wsi_M1_reqFifo_q_1$EN; + + // register wsi_M1_sThreadBusy_d + reg wsi_M1_sThreadBusy_d; + wire wsi_M1_sThreadBusy_d$D_IN, wsi_M1_sThreadBusy_d$EN; + + // register wsi_M1_statusR + reg [7 : 0] wsi_M1_statusR; + wire [7 : 0] wsi_M1_statusR$D_IN; + wire wsi_M1_statusR$EN; + + // register wsi_M1_tBusyCount + reg [31 : 0] wsi_M1_tBusyCount; + wire [31 : 0] wsi_M1_tBusyCount$D_IN; + wire wsi_M1_tBusyCount$EN; + + // register wsi_M1_trafficSticky + reg wsi_M1_trafficSticky; + wire wsi_M1_trafficSticky$D_IN, wsi_M1_trafficSticky$EN; + + // register wsi_S0_burstKind + reg [1 : 0] wsi_S0_burstKind; + wire [1 : 0] wsi_S0_burstKind$D_IN; + wire wsi_S0_burstKind$EN; + + // register wsi_S0_errorSticky + reg wsi_S0_errorSticky; + wire wsi_S0_errorSticky$D_IN, wsi_S0_errorSticky$EN; + + // register wsi_S0_iMesgCount + reg [31 : 0] wsi_S0_iMesgCount; + wire [31 : 0] wsi_S0_iMesgCount$D_IN; + wire wsi_S0_iMesgCount$EN; + + // register wsi_S0_isReset_isInReset + reg wsi_S0_isReset_isInReset; + wire wsi_S0_isReset_isInReset$D_IN, wsi_S0_isReset_isInReset$EN; + + // register wsi_S0_mesgWordLength + reg [11 : 0] wsi_S0_mesgWordLength; + wire [11 : 0] wsi_S0_mesgWordLength$D_IN; + wire wsi_S0_mesgWordLength$EN; + + // register wsi_S0_operateD + reg wsi_S0_operateD; + wire wsi_S0_operateD$D_IN, wsi_S0_operateD$EN; + + // register wsi_S0_pMesgCount + reg [31 : 0] wsi_S0_pMesgCount; + wire [31 : 0] wsi_S0_pMesgCount$D_IN; + wire wsi_S0_pMesgCount$EN; + + // register wsi_S0_peerIsReady + reg wsi_S0_peerIsReady; + wire wsi_S0_peerIsReady$D_IN, wsi_S0_peerIsReady$EN; + + // register wsi_S0_reqFifo_countReg + reg [1 : 0] wsi_S0_reqFifo_countReg; + wire [1 : 0] wsi_S0_reqFifo_countReg$D_IN; + wire wsi_S0_reqFifo_countReg$EN; + + // register wsi_S0_reqFifo_levelsValid + reg wsi_S0_reqFifo_levelsValid; + wire wsi_S0_reqFifo_levelsValid$D_IN, wsi_S0_reqFifo_levelsValid$EN; + + // register wsi_S0_statusR + reg [7 : 0] wsi_S0_statusR; + wire [7 : 0] wsi_S0_statusR$D_IN; + wire wsi_S0_statusR$EN; + + // register wsi_S0_tBusyCount + reg [31 : 0] wsi_S0_tBusyCount; + wire [31 : 0] wsi_S0_tBusyCount$D_IN; + wire wsi_S0_tBusyCount$EN; + + // register wsi_S0_trafficSticky + reg wsi_S0_trafficSticky; + wire wsi_S0_trafficSticky$D_IN, wsi_S0_trafficSticky$EN; + + // register wsi_S0_wordCount + reg [11 : 0] wsi_S0_wordCount; + wire [11 : 0] wsi_S0_wordCount$D_IN; + wire wsi_S0_wordCount$EN; + + // register wsi_S1_burstKind + reg [1 : 0] wsi_S1_burstKind; + wire [1 : 0] wsi_S1_burstKind$D_IN; + wire wsi_S1_burstKind$EN; + + // register wsi_S1_errorSticky + reg wsi_S1_errorSticky; + wire wsi_S1_errorSticky$D_IN, wsi_S1_errorSticky$EN; + + // register wsi_S1_iMesgCount + reg [31 : 0] wsi_S1_iMesgCount; + wire [31 : 0] wsi_S1_iMesgCount$D_IN; + wire wsi_S1_iMesgCount$EN; + + // register wsi_S1_isReset_isInReset + reg wsi_S1_isReset_isInReset; + wire wsi_S1_isReset_isInReset$D_IN, wsi_S1_isReset_isInReset$EN; + + // register wsi_S1_mesgWordLength + reg [11 : 0] wsi_S1_mesgWordLength; + wire [11 : 0] wsi_S1_mesgWordLength$D_IN; + wire wsi_S1_mesgWordLength$EN; + + // register wsi_S1_operateD + reg wsi_S1_operateD; + wire wsi_S1_operateD$D_IN, wsi_S1_operateD$EN; + + // register wsi_S1_pMesgCount + reg [31 : 0] wsi_S1_pMesgCount; + wire [31 : 0] wsi_S1_pMesgCount$D_IN; + wire wsi_S1_pMesgCount$EN; + + // register wsi_S1_peerIsReady + reg wsi_S1_peerIsReady; + wire wsi_S1_peerIsReady$D_IN, wsi_S1_peerIsReady$EN; + + // register wsi_S1_reqFifo_countReg + reg [1 : 0] wsi_S1_reqFifo_countReg; + wire [1 : 0] wsi_S1_reqFifo_countReg$D_IN; + wire wsi_S1_reqFifo_countReg$EN; + + // register wsi_S1_reqFifo_levelsValid + reg wsi_S1_reqFifo_levelsValid; + wire wsi_S1_reqFifo_levelsValid$D_IN, wsi_S1_reqFifo_levelsValid$EN; + + // register wsi_S1_statusR + reg [7 : 0] wsi_S1_statusR; + wire [7 : 0] wsi_S1_statusR$D_IN; + wire wsi_S1_statusR$EN; + + // register wsi_S1_tBusyCount + reg [31 : 0] wsi_S1_tBusyCount; + wire [31 : 0] wsi_S1_tBusyCount$D_IN; + wire wsi_S1_tBusyCount$EN; + + // register wsi_S1_trafficSticky + reg wsi_S1_trafficSticky; + wire wsi_S1_trafficSticky$D_IN, wsi_S1_trafficSticky$EN; + + // register wsi_S1_wordCount + reg [11 : 0] wsi_S1_wordCount; + wire [11 : 0] wsi_S1_wordCount$D_IN; + wire wsi_S1_wordCount$EN; + + // ports of submodule wci_reqF + wire [71 : 0] wci_reqF$D_IN, wci_reqF$D_OUT; + wire wci_reqF$CLR, wci_reqF$DEQ, wci_reqF$EMPTY_N, wci_reqF$ENQ; + + // ports of submodule wsi_S0_reqFifo + wire [96 : 0] wsi_S0_reqFifo$D_IN, wsi_S0_reqFifo$D_OUT; + wire wsi_S0_reqFifo$CLR, + wsi_S0_reqFifo$DEQ, + wsi_S0_reqFifo$EMPTY_N, + wsi_S0_reqFifo$ENQ, + wsi_S0_reqFifo$FULL_N; + + // ports of submodule wsi_S1_reqFifo + wire [96 : 0] wsi_S1_reqFifo$D_IN, wsi_S1_reqFifo$D_OUT; + wire wsi_S1_reqFifo$CLR, + wsi_S1_reqFifo$DEQ, + wsi_S1_reqFifo$EMPTY_N, + wsi_S1_reqFifo$ENQ, + wsi_S1_reqFifo$FULL_N; + + // rule scheduling signals + wire CAN_FIRE_RL_doMessageConsume_S1, + WILL_FIRE_RL_doMessageConsume_S0, + WILL_FIRE_RL_doMessageConsume_S1, + WILL_FIRE_RL_wci_cfrd, + WILL_FIRE_RL_wci_cfwr, + WILL_FIRE_RL_wci_ctl_op_complete, + WILL_FIRE_RL_wci_ctl_op_start, + WILL_FIRE_RL_wci_ctrl_EiI, + WILL_FIRE_RL_wci_ctrl_IsO, + WILL_FIRE_RL_wci_ctrl_OrE, + WILL_FIRE_RL_wci_respF_both, + WILL_FIRE_RL_wci_respF_decCtr, + WILL_FIRE_RL_wci_respF_incCtr, + WILL_FIRE_RL_wsi_M0_reqFifo_both, + WILL_FIRE_RL_wsi_M0_reqFifo_decCtr, + WILL_FIRE_RL_wsi_M0_reqFifo_deq, + WILL_FIRE_RL_wsi_M0_reqFifo_incCtr, + WILL_FIRE_RL_wsi_M1_reqFifo_both, + WILL_FIRE_RL_wsi_M1_reqFifo_decCtr, + WILL_FIRE_RL_wsi_M1_reqFifo_deq, + WILL_FIRE_RL_wsi_M1_reqFifo_incCtr, + WILL_FIRE_RL_wsi_S0_reqFifo_enq, + WILL_FIRE_RL_wsi_S0_reqFifo_reset, + WILL_FIRE_RL_wsi_S1_reqFifo_enq, + WILL_FIRE_RL_wsi_S1_reqFifo_reset; + + // inputs to muxes for submodule ports + reg [33 : 0] MUX_wci_respF_q_0$write_1__VAL_2; + wire [96 : 0] MUX_wsi_M0_reqFifo_q_0$write_1__VAL_1, + MUX_wsi_M0_reqFifo_q_0$write_1__VAL_2, + MUX_wsi_M0_reqFifo_q_1$write_1__VAL_1, + MUX_wsi_M1_reqFifo_q_0$write_1__VAL_1, + MUX_wsi_M1_reqFifo_q_0$write_1__VAL_2, + MUX_wsi_M1_reqFifo_q_1$write_1__VAL_1; + wire [33 : 0] MUX_wci_respF_q_0$write_1__VAL_1, + MUX_wci_respF_q_1$write_1__VAL_1, + MUX_wci_respF_x_wire$wset_1__VAL_1, + MUX_wci_respF_x_wire$wset_1__VAL_2; + wire [1 : 0] MUX_wci_respF_c_r$write_1__VAL_1, + MUX_wci_respF_c_r$write_1__VAL_2, + MUX_wsi_M0_reqFifo_c_r$write_1__VAL_1, + MUX_wsi_M0_reqFifo_c_r$write_1__VAL_2, + MUX_wsi_M1_reqFifo_c_r$write_1__VAL_1, + MUX_wsi_M1_reqFifo_c_r$write_1__VAL_2; + wire MUX_wci_illegalEdge$write_1__SEL_1, + MUX_wci_illegalEdge$write_1__VAL_1, + MUX_wci_respF_q_0$write_1__SEL_2, + MUX_wci_respF_q_1$write_1__SEL_2, + MUX_wsi_M0_reqFifo_q_0$write_1__SEL_2, + MUX_wsi_M0_reqFifo_q_1$write_1__SEL_2, + MUX_wsi_M0_reqFifo_x_wire$wset_1__SEL_1, + MUX_wsi_M1_reqFifo_q_0$write_1__SEL_2, + MUX_wsi_M1_reqFifo_q_1$write_1__SEL_2, + MUX_wsi_M1_reqFifo_x_wire$wset_1__SEL_1; + + // remaining internal signals + reg [63 : 0] v__h16289, v__h16444, v__h3698, v__h3873, v__h4017; + reg [31 : 0] _theResult____h16428; + wire [31 : 0] rdat__h16512, + rdat__h16701, + rdat__h16715, + rdat__h16723, + rdat__h16737, + rdat__h16745, + rdat__h16759, + rdat__h16767, + rdat__h16781; + + // value method wciS0_sResp + assign wciS0_SResp = wci_respF_q_0[33:32] ; + + // value method wciS0_sData + assign wciS0_SData = wci_respF_q_0[31:0] ; + + // value method wciS0_sThreadBusy + assign wciS0_SThreadBusy = + wci_reqF_countReg > 2'd1 || wci_isReset_isInReset ; + + // value method wciS0_sFlag + assign wciS0_SFlag = { 1'd1, wci_sFlagReg } ; + + // value method wsiS0_sThreadBusy + assign wsiS0_SThreadBusy = + !wsi_S0_sThreadBusy_dw$whas || wsi_S0_sThreadBusy_dw$wget ; + + // value method wsiS0_sReset_n + assign wsiS0_SReset_n = !wsi_S0_isReset_isInReset && wsi_S0_operateD ; + + // value method wsiS1_sThreadBusy + assign wsiS1_SThreadBusy = + !wsi_S1_sThreadBusy_dw$whas || wsi_S1_sThreadBusy_dw$wget ; + + // value method wsiS1_sReset_n + assign wsiS1_SReset_n = !wsi_S1_isReset_isInReset && wsi_S1_operateD ; + + // value method wsiM0_mCmd + assign wsiM0_MCmd = + wsi_M0_sThreadBusy_d ? 3'd0 : wsi_M0_reqFifo_q_0[96:94] ; + + // value method wsiM0_mReqLast + assign wsiM0_MReqLast = !wsi_M0_sThreadBusy_d && wsi_M0_reqFifo_q_0[93] ; + + // value method wsiM0_mBurstPrecise + assign wsiM0_MBurstPrecise = + !wsi_M0_sThreadBusy_d && wsi_M0_reqFifo_q_0[92] ; + + // value method wsiM0_mBurstLength + assign wsiM0_MBurstLength = + wsi_M0_sThreadBusy_d ? 12'd0 : wsi_M0_reqFifo_q_0[91:80] ; + + // value method wsiM0_mData + assign wsiM0_MData = wsi_M0_reqFifo_q_0[79:16] ; + + // value method wsiM0_mByteEn + assign wsiM0_MByteEn = wsi_M0_reqFifo_q_0[15:8] ; + + // value method wsiM0_mReqInfo + assign wsiM0_MReqInfo = + wsi_M0_sThreadBusy_d ? 8'd0 : wsi_M0_reqFifo_q_0[7:0] ; + + // value method wsiM0_mReset_n + assign wsiM0_MReset_n = !wsi_M0_isReset_isInReset && wsi_M0_operateD ; + + // value method wsiM1_mCmd + assign wsiM1_MCmd = + wsi_M1_sThreadBusy_d ? 3'd0 : wsi_M1_reqFifo_q_0[96:94] ; + + // value method wsiM1_mReqLast + assign wsiM1_MReqLast = !wsi_M1_sThreadBusy_d && wsi_M1_reqFifo_q_0[93] ; + + // value method wsiM1_mBurstPrecise + assign wsiM1_MBurstPrecise = + !wsi_M1_sThreadBusy_d && wsi_M1_reqFifo_q_0[92] ; + + // value method wsiM1_mBurstLength + assign wsiM1_MBurstLength = + wsi_M1_sThreadBusy_d ? 12'd0 : wsi_M1_reqFifo_q_0[91:80] ; + + // value method wsiM1_mData + assign wsiM1_MData = wsi_M1_reqFifo_q_0[79:16] ; + + // value method wsiM1_mByteEn + assign wsiM1_MByteEn = wsi_M1_reqFifo_q_0[15:8] ; + + // value method wsiM1_mReqInfo + assign wsiM1_MReqInfo = + wsi_M1_sThreadBusy_d ? 8'd0 : wsi_M1_reqFifo_q_0[7:0] ; + + // value method wsiM1_mReset_n + assign wsiM1_MReset_n = !wsi_M1_isReset_isInReset && wsi_M1_operateD ; + + // submodule wci_reqF + SizedFIFO #(.p1width(32'd72), + .p2depth(32'd3), + .p3cntr_width(32'd1), + .guarded(32'd1)) wci_reqF(.RST(wciS0_MReset_n), + .CLK(wciS0_Clk), + .D_IN(wci_reqF$D_IN), + .ENQ(wci_reqF$ENQ), + .DEQ(wci_reqF$DEQ), + .CLR(wci_reqF$CLR), + .D_OUT(wci_reqF$D_OUT), + .FULL_N(), + .EMPTY_N(wci_reqF$EMPTY_N)); + + // submodule wsi_S0_reqFifo + SizedFIFO #(.p1width(32'd97), + .p2depth(32'd3), + .p3cntr_width(32'd1), + .guarded(32'd1)) wsi_S0_reqFifo(.RST(wciS0_MReset_n), + .CLK(wciS0_Clk), + .D_IN(wsi_S0_reqFifo$D_IN), + .ENQ(wsi_S0_reqFifo$ENQ), + .DEQ(wsi_S0_reqFifo$DEQ), + .CLR(wsi_S0_reqFifo$CLR), + .D_OUT(wsi_S0_reqFifo$D_OUT), + .FULL_N(wsi_S0_reqFifo$FULL_N), + .EMPTY_N(wsi_S0_reqFifo$EMPTY_N)); + + // submodule wsi_S1_reqFifo + SizedFIFO #(.p1width(32'd97), + .p2depth(32'd3), + .p3cntr_width(32'd1), + .guarded(32'd1)) wsi_S1_reqFifo(.RST(wciS0_MReset_n), + .CLK(wciS0_Clk), + .D_IN(wsi_S1_reqFifo$D_IN), + .ENQ(wsi_S1_reqFifo$ENQ), + .DEQ(wsi_S1_reqFifo$DEQ), + .CLR(wsi_S1_reqFifo$CLR), + .D_OUT(wsi_S1_reqFifo$D_OUT), + .FULL_N(wsi_S1_reqFifo$FULL_N), + .EMPTY_N(wsi_S1_reqFifo$EMPTY_N)); + + // rule RL_wci_ctl_op_start + assign WILL_FIRE_RL_wci_ctl_op_start = + wci_reqF$EMPTY_N && wci_wci_ctrl_pw$whas && + !WILL_FIRE_RL_wci_ctl_op_complete ; + + // rule RL_wci_ctrl_EiI + assign WILL_FIRE_RL_wci_ctrl_EiI = + wci_wci_ctrl_pw$whas && WILL_FIRE_RL_wci_ctl_op_start && + wci_cState == 3'd0 && + wci_reqF$D_OUT[36:34] == 3'd0 ; + + // rule RL_wci_ctrl_IsO + assign WILL_FIRE_RL_wci_ctrl_IsO = + wci_wci_ctrl_pw$whas && WILL_FIRE_RL_wci_ctl_op_start && + wci_cState == 3'd1 && + wci_reqF$D_OUT[36:34] == 3'd1 ; + + // rule RL_wci_ctrl_OrE + assign WILL_FIRE_RL_wci_ctrl_OrE = + wci_wci_ctrl_pw$whas && WILL_FIRE_RL_wci_ctl_op_start && + wci_cState == 3'd2 && + wci_reqF$D_OUT[36:34] == 3'd3 ; + + // rule RL_doMessageConsume_S0 + assign WILL_FIRE_RL_doMessageConsume_S0 = + wsi_S0_reqFifo$EMPTY_N && + (splitCtrl[0] || splitCtrl[7] || wsi_M0_reqFifo_c_r != 2'd2) && + (splitCtrl[8] || splitCtrl[15] || wsi_M1_reqFifo_c_r != 2'd2) && + wci_cState == 3'd2 ; + + // rule RL_doMessageConsume_S1 + assign CAN_FIRE_RL_doMessageConsume_S1 = + wsi_S1_reqFifo$EMPTY_N && + (!splitCtrl[0] || splitCtrl[7] || wsi_M0_reqFifo_c_r != 2'd2) && + (!splitCtrl[8] || splitCtrl[15] || wsi_M1_reqFifo_c_r != 2'd2) && + wci_cState == 3'd2 ; + assign WILL_FIRE_RL_doMessageConsume_S1 = + CAN_FIRE_RL_doMessageConsume_S1 && + !WILL_FIRE_RL_doMessageConsume_S0 ; + + // rule RL_wci_cfwr + assign WILL_FIRE_RL_wci_cfwr = + wci_respF_c_r != 2'd2 && wci_reqF$EMPTY_N && + wci_wci_cfwr_pw$whas && + !WILL_FIRE_RL_wci_ctl_op_start && + !WILL_FIRE_RL_wci_ctl_op_complete ; + + // rule RL_wci_ctl_op_complete + assign WILL_FIRE_RL_wci_ctl_op_complete = + wci_respF_c_r != 2'd2 && wci_ctlOpActive && wci_ctlAckReg ; + + // rule RL_wsi_M0_reqFifo_deq + assign WILL_FIRE_RL_wsi_M0_reqFifo_deq = + wsi_M0_reqFifo_c_r != 2'd0 && !wsi_M0_sThreadBusy_d ; + + // rule RL_wsi_M0_reqFifo_incCtr + assign WILL_FIRE_RL_wsi_M0_reqFifo_incCtr = + ((wsi_M0_reqFifo_c_r == 2'd0) ? + wsi_M0_reqFifo_enqueueing$whas : + wsi_M0_reqFifo_c_r != 2'd1 || + wsi_M0_reqFifo_enqueueing$whas) && + wsi_M0_reqFifo_enqueueing$whas && + !WILL_FIRE_RL_wsi_M0_reqFifo_deq ; + + // rule RL_wsi_M0_reqFifo_decCtr + assign WILL_FIRE_RL_wsi_M0_reqFifo_decCtr = + WILL_FIRE_RL_wsi_M0_reqFifo_deq && + !wsi_M0_reqFifo_enqueueing$whas ; + + // rule RL_wsi_M0_reqFifo_both + assign WILL_FIRE_RL_wsi_M0_reqFifo_both = + ((wsi_M0_reqFifo_c_r == 2'd1) ? + wsi_M0_reqFifo_enqueueing$whas : + wsi_M0_reqFifo_c_r != 2'd2 || + wsi_M0_reqFifo_enqueueing$whas) && + WILL_FIRE_RL_wsi_M0_reqFifo_deq && + wsi_M0_reqFifo_enqueueing$whas ; + + // rule RL_wci_cfrd + assign WILL_FIRE_RL_wci_cfrd = + wci_respF_c_r != 2'd2 && wci_reqF$EMPTY_N && + wci_wci_cfrd_pw$whas && + !WILL_FIRE_RL_wci_ctl_op_start && + !WILL_FIRE_RL_wci_ctl_op_complete ; + + // rule RL_wci_respF_incCtr + assign WILL_FIRE_RL_wci_respF_incCtr = + ((wci_respF_c_r == 2'd0) ? + wci_respF_enqueueing$whas : + wci_respF_c_r != 2'd1 || wci_respF_enqueueing$whas) && + wci_respF_enqueueing$whas && + !(wci_respF_c_r != 2'd0) ; + + // rule RL_wci_respF_decCtr + assign WILL_FIRE_RL_wci_respF_decCtr = + wci_respF_c_r != 2'd0 && !wci_respF_enqueueing$whas ; + + // rule RL_wci_respF_both + assign WILL_FIRE_RL_wci_respF_both = + ((wci_respF_c_r == 2'd1) ? + wci_respF_enqueueing$whas : + wci_respF_c_r != 2'd2 || wci_respF_enqueueing$whas) && + wci_respF_c_r != 2'd0 && + wci_respF_enqueueing$whas ; + + // rule RL_wsi_M1_reqFifo_deq + assign WILL_FIRE_RL_wsi_M1_reqFifo_deq = + wsi_M1_reqFifo_c_r != 2'd0 && !wsi_M1_sThreadBusy_d ; + + // rule RL_wsi_M1_reqFifo_incCtr + assign WILL_FIRE_RL_wsi_M1_reqFifo_incCtr = + ((wsi_M1_reqFifo_c_r == 2'd0) ? + wsi_M1_reqFifo_enqueueing$whas : + wsi_M1_reqFifo_c_r != 2'd1 || + wsi_M1_reqFifo_enqueueing$whas) && + wsi_M1_reqFifo_enqueueing$whas && + !WILL_FIRE_RL_wsi_M1_reqFifo_deq ; + + // rule RL_wsi_M1_reqFifo_decCtr + assign WILL_FIRE_RL_wsi_M1_reqFifo_decCtr = + WILL_FIRE_RL_wsi_M1_reqFifo_deq && + !wsi_M1_reqFifo_enqueueing$whas ; + + // rule RL_wsi_M1_reqFifo_both + assign WILL_FIRE_RL_wsi_M1_reqFifo_both = + ((wsi_M1_reqFifo_c_r == 2'd1) ? + wsi_M1_reqFifo_enqueueing$whas : + wsi_M1_reqFifo_c_r != 2'd2 || + wsi_M1_reqFifo_enqueueing$whas) && + WILL_FIRE_RL_wsi_M1_reqFifo_deq && + wsi_M1_reqFifo_enqueueing$whas ; + + // rule RL_wsi_S0_reqFifo_enq + assign WILL_FIRE_RL_wsi_S0_reqFifo_enq = + wsi_S0_reqFifo$FULL_N && wsi_S0_operateD && wsi_S0_peerIsReady && + wsi_S0_wsiReq$wget[96:94] == 3'd1 ; + + // rule RL_wsi_S0_reqFifo_reset + assign WILL_FIRE_RL_wsi_S0_reqFifo_reset = + WILL_FIRE_RL_wsi_S0_reqFifo_enq || + WILL_FIRE_RL_doMessageConsume_S0 ; + + // rule RL_wsi_S1_reqFifo_enq + assign WILL_FIRE_RL_wsi_S1_reqFifo_enq = + wsi_S1_reqFifo$FULL_N && wsi_S1_operateD && wsi_S1_peerIsReady && + wsi_S1_wsiReq$wget[96:94] == 3'd1 ; + + // rule RL_wsi_S1_reqFifo_reset + assign WILL_FIRE_RL_wsi_S1_reqFifo_reset = + WILL_FIRE_RL_wsi_S1_reqFifo_enq || + WILL_FIRE_RL_doMessageConsume_S1 ; + + // inputs to muxes for submodule ports + assign MUX_wci_illegalEdge$write_1__SEL_1 = + WILL_FIRE_RL_wci_ctl_op_start && + (wci_reqF$D_OUT[36:34] == 3'd0 && wci_cState != 3'd0 || + wci_reqF$D_OUT[36:34] == 3'd1 && wci_cState != 3'd1 && + wci_cState != 3'd3 || + wci_reqF$D_OUT[36:34] == 3'd2 && wci_cState != 3'd2 || + wci_reqF$D_OUT[36:34] == 3'd3 && wci_cState != 3'd3 && + wci_cState != 3'd2 && + wci_cState != 3'd1 || + wci_reqF$D_OUT[36:34] == 3'd4 || + wci_reqF$D_OUT[36:34] == 3'd5 || + wci_reqF$D_OUT[36:34] == 3'd6 || + wci_reqF$D_OUT[36:34] == 3'd7) ; + assign MUX_wci_respF_q_0$write_1__SEL_2 = + WILL_FIRE_RL_wci_respF_incCtr && wci_respF_c_r == 2'd0 ; + assign MUX_wci_respF_q_1$write_1__SEL_2 = + WILL_FIRE_RL_wci_respF_incCtr && wci_respF_c_r == 2'd1 ; + assign MUX_wsi_M0_reqFifo_q_0$write_1__SEL_2 = + WILL_FIRE_RL_wsi_M0_reqFifo_incCtr && + wsi_M0_reqFifo_c_r == 2'd0 ; + assign MUX_wsi_M0_reqFifo_q_1$write_1__SEL_2 = + WILL_FIRE_RL_wsi_M0_reqFifo_incCtr && + wsi_M0_reqFifo_c_r == 2'd1 ; + assign MUX_wsi_M0_reqFifo_x_wire$wset_1__SEL_1 = + WILL_FIRE_RL_doMessageConsume_S0 && !splitCtrl[0] && + !splitCtrl[7] ; + assign MUX_wsi_M1_reqFifo_q_0$write_1__SEL_2 = + WILL_FIRE_RL_wsi_M1_reqFifo_incCtr && + wsi_M1_reqFifo_c_r == 2'd0 ; + assign MUX_wsi_M1_reqFifo_q_1$write_1__SEL_2 = + WILL_FIRE_RL_wsi_M1_reqFifo_incCtr && + wsi_M1_reqFifo_c_r == 2'd1 ; + assign MUX_wsi_M1_reqFifo_x_wire$wset_1__SEL_1 = + WILL_FIRE_RL_doMessageConsume_S0 && !splitCtrl[8] && + !splitCtrl[15] ; + assign MUX_wci_illegalEdge$write_1__VAL_1 = + wci_reqF$D_OUT[36:34] != 3'd4 && wci_reqF$D_OUT[36:34] != 3'd5 && + wci_reqF$D_OUT[36:34] != 3'd6 ; + assign MUX_wci_respF_c_r$write_1__VAL_1 = wci_respF_c_r + 2'd1 ; + assign MUX_wci_respF_c_r$write_1__VAL_2 = wci_respF_c_r - 2'd1 ; + assign MUX_wci_respF_q_0$write_1__VAL_1 = + (wci_respF_c_r == 2'd1) ? + MUX_wci_respF_q_0$write_1__VAL_2 : + wci_respF_q_1 ; + always@(WILL_FIRE_RL_wci_ctl_op_complete or + MUX_wci_respF_x_wire$wset_1__VAL_1 or + WILL_FIRE_RL_wci_cfrd or + MUX_wci_respF_x_wire$wset_1__VAL_2 or WILL_FIRE_RL_wci_cfwr) + begin + case (1'b1) // synopsys parallel_case + WILL_FIRE_RL_wci_ctl_op_complete: + MUX_wci_respF_q_0$write_1__VAL_2 = + MUX_wci_respF_x_wire$wset_1__VAL_1; + WILL_FIRE_RL_wci_cfrd: + MUX_wci_respF_q_0$write_1__VAL_2 = + MUX_wci_respF_x_wire$wset_1__VAL_2; + WILL_FIRE_RL_wci_cfwr: MUX_wci_respF_q_0$write_1__VAL_2 = 34'h1C0DE4201; + default: MUX_wci_respF_q_0$write_1__VAL_2 = + 34'h2AAAAAAAA /* unspecified value */ ; + endcase + end + assign MUX_wci_respF_q_1$write_1__VAL_1 = + (wci_respF_c_r == 2'd2) ? + MUX_wci_respF_q_0$write_1__VAL_2 : + 34'h0AAAAAAAA ; + assign MUX_wci_respF_x_wire$wset_1__VAL_1 = + wci_illegalEdge ? 34'h3C0DE4202 : 34'h1C0DE4201 ; + assign MUX_wci_respF_x_wire$wset_1__VAL_2 = { 2'd1, _theResult____h16428 } ; + assign MUX_wsi_M0_reqFifo_c_r$write_1__VAL_1 = wsi_M0_reqFifo_c_r + 2'd1 ; + assign MUX_wsi_M0_reqFifo_c_r$write_1__VAL_2 = wsi_M0_reqFifo_c_r - 2'd1 ; + assign MUX_wsi_M0_reqFifo_q_0$write_1__VAL_1 = + (wsi_M0_reqFifo_c_r == 2'd1) ? + MUX_wsi_M0_reqFifo_q_0$write_1__VAL_2 : + wsi_M0_reqFifo_q_1 ; + assign MUX_wsi_M0_reqFifo_q_0$write_1__VAL_2 = + MUX_wsi_M0_reqFifo_x_wire$wset_1__SEL_1 ? + wsi_S0_reqFifo$D_OUT : + wsi_S1_reqFifo$D_OUT ; + assign MUX_wsi_M0_reqFifo_q_1$write_1__VAL_1 = + (wsi_M0_reqFifo_c_r == 2'd2) ? + MUX_wsi_M0_reqFifo_q_0$write_1__VAL_2 : + 97'h00000AAAAAAAAAAAAAAAAAA00 ; + assign MUX_wsi_M1_reqFifo_c_r$write_1__VAL_1 = wsi_M1_reqFifo_c_r + 2'd1 ; + assign MUX_wsi_M1_reqFifo_c_r$write_1__VAL_2 = wsi_M1_reqFifo_c_r - 2'd1 ; + assign MUX_wsi_M1_reqFifo_q_0$write_1__VAL_1 = + (wsi_M1_reqFifo_c_r == 2'd1) ? + MUX_wsi_M1_reqFifo_q_0$write_1__VAL_2 : + wsi_M1_reqFifo_q_1 ; + assign MUX_wsi_M1_reqFifo_q_0$write_1__VAL_2 = + MUX_wsi_M1_reqFifo_x_wire$wset_1__SEL_1 ? + wsi_S0_reqFifo$D_OUT : + wsi_S1_reqFifo$D_OUT ; + assign MUX_wsi_M1_reqFifo_q_1$write_1__VAL_1 = + (wsi_M1_reqFifo_c_r == 2'd2) ? + MUX_wsi_M1_reqFifo_q_0$write_1__VAL_2 : + 97'h00000AAAAAAAAAAAAAAAAAA00 ; + + // inlined wires + assign wci_wciReq$wget = + { wciS0_MCmd, + wciS0_MAddrSpace, + wciS0_MByteEn, + wciS0_MAddr, + wciS0_MData } ; + assign wci_wciReq$whas = 1'd1 ; + assign wci_respF_x_wire$wget = MUX_wci_respF_q_0$write_1__VAL_2 ; + assign wci_respF_x_wire$whas = wci_respF_enqueueing$whas ; + assign wci_wEdge$wget = wci_reqF$D_OUT[36:34] ; + assign wci_wEdge$whas = WILL_FIRE_RL_wci_ctl_op_start ; + assign wci_sFlagReg_1$wget = 1'b0 ; + assign wci_sFlagReg_1$whas = 1'b0 ; + assign wci_ctlAckReg_1$wget = 1'd1 ; + assign wci_ctlAckReg_1$whas = + WILL_FIRE_RL_wci_ctrl_OrE || WILL_FIRE_RL_wci_ctrl_IsO || + WILL_FIRE_RL_wci_ctrl_EiI ; + assign wsi_S0_wsiReq$wget = + { wsiS0_MCmd, + wsiS0_MReqLast, + wsiS0_MBurstPrecise, + wsiS0_MBurstLength, + wsiS0_MData, + wsiS0_MByteEn, + wsiS0_MReqInfo } ; + assign wsi_S0_wsiReq$whas = 1'd1 ; + assign wsi_S0_operateD_1$wget = 1'd1 ; + assign wsi_S0_operateD_1$whas = wci_cState == 3'd2 ; + assign wsi_S0_peerIsReady_1$wget = 1'd1 ; + assign wsi_S0_peerIsReady_1$whas = wsiS0_MReset_n ; + assign wsi_S0_sThreadBusy_dw$wget = wsi_S0_reqFifo_countReg > 2'd1 ; + assign wsi_S0_sThreadBusy_dw$whas = + wsi_S0_reqFifo_levelsValid && wsi_S0_operateD && + wsi_S0_peerIsReady ; + assign wsi_S1_wsiReq$wget = + { wsiS1_MCmd, + wsiS1_MReqLast, + wsiS1_MBurstPrecise, + wsiS1_MBurstLength, + wsiS1_MData, + wsiS1_MByteEn, + wsiS1_MReqInfo } ; + assign wsi_S1_wsiReq$whas = 1'd1 ; + assign wsi_S1_operateD_1$wget = 1'd1 ; + assign wsi_S1_operateD_1$whas = wci_cState == 3'd2 ; + assign wsi_S1_peerIsReady_1$wget = 1'd1 ; + assign wsi_S1_peerIsReady_1$whas = wsiS1_MReset_n ; + assign wsi_S1_sThreadBusy_dw$wget = wsi_S1_reqFifo_countReg > 2'd1 ; + assign wsi_S1_sThreadBusy_dw$whas = + wsi_S1_reqFifo_levelsValid && wsi_S1_operateD && + wsi_S1_peerIsReady ; + assign wsi_M0_reqFifo_x_wire$wget = MUX_wsi_M0_reqFifo_q_0$write_1__VAL_2 ; + assign wsi_M0_reqFifo_x_wire$whas = wsi_M0_reqFifo_enqueueing$whas ; + assign wsi_M0_operateD_1$wget = 1'd1 ; + assign wsi_M0_operateD_1$whas = wci_cState == 3'd2 ; + assign wsi_M0_peerIsReady_1$wget = 1'd1 ; + assign wsi_M0_peerIsReady_1$whas = wsiM0_SReset_n ; + assign wsi_M1_reqFifo_x_wire$wget = MUX_wsi_M1_reqFifo_q_0$write_1__VAL_2 ; + assign wsi_M1_reqFifo_x_wire$whas = wsi_M1_reqFifo_enqueueing$whas ; + assign wsi_M1_operateD_1$wget = 1'd1 ; + assign wsi_M1_operateD_1$whas = wci_cState == 3'd2 ; + assign wsi_M1_peerIsReady_1$wget = 1'd1 ; + assign wsi_M1_peerIsReady_1$whas = wsiM1_SReset_n ; + assign wci_Es_mCmd_w$wget = wciS0_MCmd ; + assign wci_Es_mCmd_w$whas = 1'd1 ; + assign wci_Es_mAddrSpace_w$wget = wciS0_MAddrSpace ; + assign wci_Es_mAddrSpace_w$whas = 1'd1 ; + assign wci_Es_mByteEn_w$wget = wciS0_MByteEn ; + assign wci_Es_mByteEn_w$whas = 1'd1 ; + assign wci_Es_mAddr_w$wget = wciS0_MAddr ; + assign wci_Es_mAddr_w$whas = 1'd1 ; + assign wci_Es_mData_w$wget = wciS0_MData ; + assign wci_Es_mData_w$whas = 1'd1 ; + assign wsi_Es0_mCmd_w$wget = wsiS0_MCmd ; + assign wsi_Es0_mCmd_w$whas = 1'd1 ; + assign wsi_Es0_mBurstLength_w$wget = wsiS0_MBurstLength ; + assign wsi_Es0_mBurstLength_w$whas = 1'd1 ; + assign wsi_Es0_mData_w$wget = wsiS0_MData ; + assign wsi_Es0_mData_w$whas = 1'd1 ; + assign wsi_Es0_mByteEn_w$wget = wsiS0_MByteEn ; + assign wsi_Es0_mByteEn_w$whas = 1'd1 ; + assign wsi_Es0_mReqInfo_w$wget = wsiS0_MReqInfo ; + assign wsi_Es0_mReqInfo_w$whas = 1'd1 ; + assign wsi_Es1_mCmd_w$wget = wsiS1_MCmd ; + assign wsi_Es1_mCmd_w$whas = 1'd1 ; + assign wsi_Es1_mBurstLength_w$wget = wsiS1_MBurstLength ; + assign wsi_Es1_mBurstLength_w$whas = 1'd1 ; + assign wsi_Es1_mData_w$wget = wsiS1_MData ; + assign wsi_Es1_mData_w$whas = 1'd1 ; + assign wsi_Es1_mByteEn_w$wget = wsiS1_MByteEn ; + assign wsi_Es1_mByteEn_w$whas = 1'd1 ; + assign wsi_Es1_mReqInfo_w$wget = wsiS1_MReqInfo ; + assign wsi_Es1_mReqInfo_w$whas = 1'd1 ; + assign wci_reqF_r_enq$whas = wci_wciReq$wget[71:69] != 3'd0 ; + assign wci_reqF_r_deq$whas = + WILL_FIRE_RL_wci_ctl_op_start || WILL_FIRE_RL_wci_cfrd || + WILL_FIRE_RL_wci_cfwr ; + assign wci_reqF_r_clr$whas = 1'b0 ; + assign wci_respF_enqueueing$whas = + WILL_FIRE_RL_wci_ctl_op_complete || WILL_FIRE_RL_wci_cfrd || + WILL_FIRE_RL_wci_cfwr ; + assign wci_respF_dequeueing$whas = wci_respF_c_r != 2'd0 ; + assign wci_sThreadBusy_pw$whas = 1'b0 ; + assign wci_wci_cfwr_pw$whas = + wci_reqF$EMPTY_N && wci_reqF$D_OUT[68] && + wci_reqF$D_OUT[71:69] == 3'd1 ; + assign wci_wci_cfrd_pw$whas = + wci_reqF$EMPTY_N && wci_reqF$D_OUT[68] && + wci_reqF$D_OUT[71:69] == 3'd2 ; + assign wci_wci_ctrl_pw$whas = + wci_reqF$EMPTY_N && !wci_reqF$D_OUT[68] && + wci_reqF$D_OUT[71:69] == 3'd2 ; + assign wsi_S0_reqFifo_r_enq$whas = WILL_FIRE_RL_wsi_S0_reqFifo_enq ; + assign wsi_S0_reqFifo_r_deq$whas = WILL_FIRE_RL_doMessageConsume_S0 ; + assign wsi_S0_reqFifo_r_clr$whas = 1'b0 ; + assign wsi_S0_reqFifo_doResetEnq$whas = WILL_FIRE_RL_wsi_S0_reqFifo_enq ; + assign wsi_S0_reqFifo_doResetDeq$whas = WILL_FIRE_RL_doMessageConsume_S0 ; + assign wsi_S0_reqFifo_doResetClr$whas = 1'b0 ; + assign wsi_S1_reqFifo_r_enq$whas = WILL_FIRE_RL_wsi_S1_reqFifo_enq ; + assign wsi_S1_reqFifo_r_deq$whas = WILL_FIRE_RL_doMessageConsume_S1 ; + assign wsi_S1_reqFifo_r_clr$whas = 1'b0 ; + assign wsi_S1_reqFifo_doResetEnq$whas = WILL_FIRE_RL_wsi_S1_reqFifo_enq ; + assign wsi_S1_reqFifo_doResetDeq$whas = WILL_FIRE_RL_doMessageConsume_S1 ; + assign wsi_S1_reqFifo_doResetClr$whas = 1'b0 ; + assign wsi_M0_reqFifo_enqueueing$whas = + WILL_FIRE_RL_doMessageConsume_S0 && !splitCtrl[0] && + !splitCtrl[7] || + WILL_FIRE_RL_doMessageConsume_S1 && splitCtrl[0] && + !splitCtrl[7] ; + assign wsi_M0_reqFifo_dequeueing$whas = WILL_FIRE_RL_wsi_M0_reqFifo_deq ; + assign wsi_M0_sThreadBusy_pw$whas = wsiM0_SThreadBusy ; + assign wsi_M1_reqFifo_enqueueing$whas = + WILL_FIRE_RL_doMessageConsume_S0 && !splitCtrl[8] && + !splitCtrl[15] || + WILL_FIRE_RL_doMessageConsume_S1 && splitCtrl[8] && + !splitCtrl[15] ; + assign wsi_M1_reqFifo_dequeueing$whas = WILL_FIRE_RL_wsi_M1_reqFifo_deq ; + assign wsi_M1_sThreadBusy_pw$whas = wsiM1_SThreadBusy ; + assign wsi_Es0_mReqLast_w$whas = wsiS0_MReqLast ; + assign wsi_Es0_mBurstPrecise_w$whas = wsiS0_MBurstPrecise ; + assign wsi_Es0_mDataInfo_w$whas = 1'd1 ; + assign wsi_Es1_mReqLast_w$whas = wsiS1_MReqLast ; + assign wsi_Es1_mBurstPrecise_w$whas = wsiS1_MBurstPrecise ; + assign wsi_Es1_mDataInfo_w$whas = 1'd1 ; + assign wsi_S0_extStatusW$wget = + { wsi_S0_pMesgCount, wsi_S0_iMesgCount, wsi_S0_tBusyCount } ; + assign wsi_S1_extStatusW$wget = + { wsi_S1_pMesgCount, wsi_S1_iMesgCount, wsi_S1_tBusyCount } ; + assign wsi_M0_extStatusW$wget = + { wsi_M0_pMesgCount, wsi_M0_iMesgCount, wsi_M0_tBusyCount } ; + assign wsi_M1_extStatusW$wget = + { wsi_M1_pMesgCount, wsi_M1_iMesgCount, wsi_M1_tBusyCount } ; + + // register splitCtrl + assign splitCtrl$D_IN = wci_reqF$D_OUT[31:0] ; + assign splitCtrl$EN = + WILL_FIRE_RL_wci_cfwr && wci_reqF$D_OUT[39:32] == 8'h04 ; + + // register wci_cEdge + assign wci_cEdge$D_IN = wci_reqF$D_OUT[36:34] ; + assign wci_cEdge$EN = WILL_FIRE_RL_wci_ctl_op_start ; + + // register wci_cState + assign wci_cState$D_IN = wci_nState ; + assign wci_cState$EN = + WILL_FIRE_RL_wci_ctl_op_complete && !wci_illegalEdge ; + + // register wci_ctlAckReg + assign wci_ctlAckReg$D_IN = wci_ctlAckReg_1$whas ; + assign wci_ctlAckReg$EN = 1'd1 ; + + // register wci_ctlOpActive + assign wci_ctlOpActive$D_IN = !WILL_FIRE_RL_wci_ctl_op_complete ; + assign wci_ctlOpActive$EN = + WILL_FIRE_RL_wci_ctl_op_complete || + WILL_FIRE_RL_wci_ctl_op_start ; + + // register wci_illegalEdge + assign wci_illegalEdge$D_IN = + MUX_wci_illegalEdge$write_1__SEL_1 && + MUX_wci_illegalEdge$write_1__VAL_1 ; + assign wci_illegalEdge$EN = + MUX_wci_illegalEdge$write_1__SEL_1 || + WILL_FIRE_RL_wci_ctl_op_complete && wci_illegalEdge ; + + // register wci_isReset_isInReset + assign wci_isReset_isInReset$D_IN = 1'd0 ; + assign wci_isReset_isInReset$EN = wci_isReset_isInReset ; + + // register wci_nState + always@(wci_reqF$D_OUT) + begin + case (wci_reqF$D_OUT[36:34]) + 3'd0: wci_nState$D_IN = 3'd1; + 3'd1: wci_nState$D_IN = 3'd2; + 3'd2: wci_nState$D_IN = 3'd3; + default: wci_nState$D_IN = 3'd0; + endcase + end + assign wci_nState$EN = + WILL_FIRE_RL_wci_ctl_op_start && + (wci_reqF$D_OUT[36:34] == 3'd0 && wci_cState == 3'd0 || + wci_reqF$D_OUT[36:34] == 3'd1 && + (wci_cState == 3'd1 || wci_cState == 3'd3) || + wci_reqF$D_OUT[36:34] == 3'd2 && wci_cState == 3'd2 || + wci_reqF$D_OUT[36:34] == 3'd3 && + (wci_cState == 3'd3 || wci_cState == 3'd2 || + wci_cState == 3'd1)) ; + + // register wci_reqF_countReg + assign wci_reqF_countReg$D_IN = + (wci_wciReq$wget[71:69] != 3'd0) ? + wci_reqF_countReg + 2'd1 : + wci_reqF_countReg - 2'd1 ; + assign wci_reqF_countReg$EN = + (wci_wciReq$wget[71:69] != 3'd0) != wci_reqF_r_deq$whas ; + + // register wci_respF_c_r + assign wci_respF_c_r$D_IN = + WILL_FIRE_RL_wci_respF_incCtr ? + MUX_wci_respF_c_r$write_1__VAL_1 : + MUX_wci_respF_c_r$write_1__VAL_2 ; + assign wci_respF_c_r$EN = + WILL_FIRE_RL_wci_respF_incCtr || WILL_FIRE_RL_wci_respF_decCtr ; + + // register wci_respF_q_0 + always@(WILL_FIRE_RL_wci_respF_both or + MUX_wci_respF_q_0$write_1__VAL_1 or + MUX_wci_respF_q_0$write_1__SEL_2 or + MUX_wci_respF_q_0$write_1__VAL_2 or + WILL_FIRE_RL_wci_respF_decCtr or wci_respF_q_1) + begin + case (1'b1) // synopsys parallel_case + WILL_FIRE_RL_wci_respF_both: + wci_respF_q_0$D_IN = MUX_wci_respF_q_0$write_1__VAL_1; + MUX_wci_respF_q_0$write_1__SEL_2: + wci_respF_q_0$D_IN = MUX_wci_respF_q_0$write_1__VAL_2; + WILL_FIRE_RL_wci_respF_decCtr: wci_respF_q_0$D_IN = wci_respF_q_1; + default: wci_respF_q_0$D_IN = 34'h2AAAAAAAA /* unspecified value */ ; + endcase + end + assign wci_respF_q_0$EN = + WILL_FIRE_RL_wci_respF_both || + WILL_FIRE_RL_wci_respF_incCtr && wci_respF_c_r == 2'd0 || + WILL_FIRE_RL_wci_respF_decCtr ; + + // register wci_respF_q_1 + always@(WILL_FIRE_RL_wci_respF_both or + MUX_wci_respF_q_1$write_1__VAL_1 or + MUX_wci_respF_q_1$write_1__SEL_2 or + MUX_wci_respF_q_0$write_1__VAL_2 or WILL_FIRE_RL_wci_respF_decCtr) + begin + case (1'b1) // synopsys parallel_case + WILL_FIRE_RL_wci_respF_both: + wci_respF_q_1$D_IN = MUX_wci_respF_q_1$write_1__VAL_1; + MUX_wci_respF_q_1$write_1__SEL_2: + wci_respF_q_1$D_IN = MUX_wci_respF_q_0$write_1__VAL_2; + WILL_FIRE_RL_wci_respF_decCtr: wci_respF_q_1$D_IN = 34'h0AAAAAAAA; + default: wci_respF_q_1$D_IN = 34'h2AAAAAAAA /* unspecified value */ ; + endcase + end + assign wci_respF_q_1$EN = + WILL_FIRE_RL_wci_respF_both || + WILL_FIRE_RL_wci_respF_incCtr && wci_respF_c_r == 2'd1 || + WILL_FIRE_RL_wci_respF_decCtr ; + + // register wci_sFlagReg + assign wci_sFlagReg$D_IN = 1'b0 ; + assign wci_sFlagReg$EN = 1'd1 ; + + // register wci_sThreadBusy_d + assign wci_sThreadBusy_d$D_IN = 1'b0 ; + assign wci_sThreadBusy_d$EN = 1'd1 ; + + // register wsi_M0_burstKind + assign wsi_M0_burstKind$D_IN = + (wsi_M0_burstKind == 2'd0) ? + (wsi_M0_reqFifo_q_0[92] ? 2'd1 : 2'd2) : + 2'd0 ; + assign wsi_M0_burstKind$EN = + WILL_FIRE_RL_wsi_M0_reqFifo_deq && + wsi_M0_reqFifo_q_0[96:94] == 3'd1 && + (wsi_M0_burstKind == 2'd0 || + (wsi_M0_burstKind == 2'd1 || wsi_M0_burstKind == 2'd2) && + wsi_M0_reqFifo_q_0[93]) ; + + // register wsi_M0_errorSticky + assign wsi_M0_errorSticky$D_IN = 1'b0 ; + assign wsi_M0_errorSticky$EN = 1'b0 ; + + // register wsi_M0_iMesgCount + assign wsi_M0_iMesgCount$D_IN = wsi_M0_iMesgCount + 32'd1 ; + assign wsi_M0_iMesgCount$EN = + WILL_FIRE_RL_wsi_M0_reqFifo_deq && + wsi_M0_reqFifo_q_0[96:94] == 3'd1 && + wsi_M0_burstKind == 2'd2 && + wsi_M0_reqFifo_q_0[93] ; + + // register wsi_M0_isReset_isInReset + assign wsi_M0_isReset_isInReset$D_IN = 1'd0 ; + assign wsi_M0_isReset_isInReset$EN = wsi_M0_isReset_isInReset ; + + // register wsi_M0_operateD + assign wsi_M0_operateD$D_IN = wci_cState == 3'd2 ; + assign wsi_M0_operateD$EN = 1'd1 ; + + // register wsi_M0_pMesgCount + assign wsi_M0_pMesgCount$D_IN = wsi_M0_pMesgCount + 32'd1 ; + assign wsi_M0_pMesgCount$EN = + WILL_FIRE_RL_wsi_M0_reqFifo_deq && + wsi_M0_reqFifo_q_0[96:94] == 3'd1 && + wsi_M0_burstKind == 2'd1 && + wsi_M0_reqFifo_q_0[93] ; + + // register wsi_M0_peerIsReady + assign wsi_M0_peerIsReady$D_IN = wsiM0_SReset_n ; + assign wsi_M0_peerIsReady$EN = 1'd1 ; + + // register wsi_M0_reqFifo_c_r + assign wsi_M0_reqFifo_c_r$D_IN = + WILL_FIRE_RL_wsi_M0_reqFifo_incCtr ? + MUX_wsi_M0_reqFifo_c_r$write_1__VAL_1 : + MUX_wsi_M0_reqFifo_c_r$write_1__VAL_2 ; + assign wsi_M0_reqFifo_c_r$EN = + WILL_FIRE_RL_wsi_M0_reqFifo_incCtr || + WILL_FIRE_RL_wsi_M0_reqFifo_decCtr ; + + // register wsi_M0_reqFifo_q_0 + always@(WILL_FIRE_RL_wsi_M0_reqFifo_both or + MUX_wsi_M0_reqFifo_q_0$write_1__VAL_1 or + MUX_wsi_M0_reqFifo_q_0$write_1__SEL_2 or + MUX_wsi_M0_reqFifo_q_0$write_1__VAL_2 or + WILL_FIRE_RL_wsi_M0_reqFifo_decCtr or wsi_M0_reqFifo_q_1) + begin + case (1'b1) // synopsys parallel_case + WILL_FIRE_RL_wsi_M0_reqFifo_both: + wsi_M0_reqFifo_q_0$D_IN = MUX_wsi_M0_reqFifo_q_0$write_1__VAL_1; + MUX_wsi_M0_reqFifo_q_0$write_1__SEL_2: + wsi_M0_reqFifo_q_0$D_IN = MUX_wsi_M0_reqFifo_q_0$write_1__VAL_2; + WILL_FIRE_RL_wsi_M0_reqFifo_decCtr: + wsi_M0_reqFifo_q_0$D_IN = wsi_M0_reqFifo_q_1; + default: wsi_M0_reqFifo_q_0$D_IN = + 97'h0AAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ; + endcase + end + assign wsi_M0_reqFifo_q_0$EN = + WILL_FIRE_RL_wsi_M0_reqFifo_both || + WILL_FIRE_RL_wsi_M0_reqFifo_incCtr && + wsi_M0_reqFifo_c_r == 2'd0 || + WILL_FIRE_RL_wsi_M0_reqFifo_decCtr ; + + // register wsi_M0_reqFifo_q_1 + always@(WILL_FIRE_RL_wsi_M0_reqFifo_both or + MUX_wsi_M0_reqFifo_q_1$write_1__VAL_1 or + MUX_wsi_M0_reqFifo_q_1$write_1__SEL_2 or + MUX_wsi_M0_reqFifo_q_0$write_1__VAL_2 or + WILL_FIRE_RL_wsi_M0_reqFifo_decCtr) + begin + case (1'b1) // synopsys parallel_case + WILL_FIRE_RL_wsi_M0_reqFifo_both: + wsi_M0_reqFifo_q_1$D_IN = MUX_wsi_M0_reqFifo_q_1$write_1__VAL_1; + MUX_wsi_M0_reqFifo_q_1$write_1__SEL_2: + wsi_M0_reqFifo_q_1$D_IN = MUX_wsi_M0_reqFifo_q_0$write_1__VAL_2; + WILL_FIRE_RL_wsi_M0_reqFifo_decCtr: + wsi_M0_reqFifo_q_1$D_IN = 97'h00000AAAAAAAAAAAAAAAAAA00; + default: wsi_M0_reqFifo_q_1$D_IN = + 97'h0AAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ; + endcase + end + assign wsi_M0_reqFifo_q_1$EN = + WILL_FIRE_RL_wsi_M0_reqFifo_both || + WILL_FIRE_RL_wsi_M0_reqFifo_incCtr && + wsi_M0_reqFifo_c_r == 2'd1 || + WILL_FIRE_RL_wsi_M0_reqFifo_decCtr ; + + // register wsi_M0_sThreadBusy_d + assign wsi_M0_sThreadBusy_d$D_IN = wsiM0_SThreadBusy ; + assign wsi_M0_sThreadBusy_d$EN = 1'd1 ; + + // register wsi_M0_statusR + assign wsi_M0_statusR$D_IN = + { wsi_M0_isReset_isInReset, + !wsi_M0_peerIsReady, + !wsi_M0_operateD, + wsi_M0_errorSticky, + wsi_M0_burstKind != 2'd0, + wsi_M0_sThreadBusy_d, + 1'd0, + wsi_M0_trafficSticky } ; + assign wsi_M0_statusR$EN = 1'd1 ; + + // register wsi_M0_tBusyCount + assign wsi_M0_tBusyCount$D_IN = wsi_M0_tBusyCount + 32'd1 ; + assign wsi_M0_tBusyCount$EN = + wsi_M0_operateD && wsi_M0_peerIsReady && wsi_M0_sThreadBusy_d ; + + // register wsi_M0_trafficSticky + assign wsi_M0_trafficSticky$D_IN = 1'd1 ; + assign wsi_M0_trafficSticky$EN = + WILL_FIRE_RL_wsi_M0_reqFifo_deq && + wsi_M0_reqFifo_q_0[96:94] == 3'd1 ; + + // register wsi_M1_burstKind + assign wsi_M1_burstKind$D_IN = + (wsi_M1_burstKind == 2'd0) ? + (wsi_M1_reqFifo_q_0[92] ? 2'd1 : 2'd2) : + 2'd0 ; + assign wsi_M1_burstKind$EN = + WILL_FIRE_RL_wsi_M1_reqFifo_deq && + wsi_M1_reqFifo_q_0[96:94] == 3'd1 && + (wsi_M1_burstKind == 2'd0 || + (wsi_M1_burstKind == 2'd1 || wsi_M1_burstKind == 2'd2) && + wsi_M1_reqFifo_q_0[93]) ; + + // register wsi_M1_errorSticky + assign wsi_M1_errorSticky$D_IN = 1'b0 ; + assign wsi_M1_errorSticky$EN = 1'b0 ; + + // register wsi_M1_iMesgCount + assign wsi_M1_iMesgCount$D_IN = wsi_M1_iMesgCount + 32'd1 ; + assign wsi_M1_iMesgCount$EN = + WILL_FIRE_RL_wsi_M1_reqFifo_deq && + wsi_M1_reqFifo_q_0[96:94] == 3'd1 && + wsi_M1_burstKind == 2'd2 && + wsi_M1_reqFifo_q_0[93] ; + + // register wsi_M1_isReset_isInReset + assign wsi_M1_isReset_isInReset$D_IN = 1'd0 ; + assign wsi_M1_isReset_isInReset$EN = wsi_M1_isReset_isInReset ; + + // register wsi_M1_operateD + assign wsi_M1_operateD$D_IN = wci_cState == 3'd2 ; + assign wsi_M1_operateD$EN = 1'd1 ; + + // register wsi_M1_pMesgCount + assign wsi_M1_pMesgCount$D_IN = wsi_M1_pMesgCount + 32'd1 ; + assign wsi_M1_pMesgCount$EN = + WILL_FIRE_RL_wsi_M1_reqFifo_deq && + wsi_M1_reqFifo_q_0[96:94] == 3'd1 && + wsi_M1_burstKind == 2'd1 && + wsi_M1_reqFifo_q_0[93] ; + + // register wsi_M1_peerIsReady + assign wsi_M1_peerIsReady$D_IN = wsiM1_SReset_n ; + assign wsi_M1_peerIsReady$EN = 1'd1 ; + + // register wsi_M1_reqFifo_c_r + assign wsi_M1_reqFifo_c_r$D_IN = + WILL_FIRE_RL_wsi_M1_reqFifo_incCtr ? + MUX_wsi_M1_reqFifo_c_r$write_1__VAL_1 : + MUX_wsi_M1_reqFifo_c_r$write_1__VAL_2 ; + assign wsi_M1_reqFifo_c_r$EN = + WILL_FIRE_RL_wsi_M1_reqFifo_incCtr || + WILL_FIRE_RL_wsi_M1_reqFifo_decCtr ; + + // register wsi_M1_reqFifo_q_0 + always@(WILL_FIRE_RL_wsi_M1_reqFifo_both or + MUX_wsi_M1_reqFifo_q_0$write_1__VAL_1 or + MUX_wsi_M1_reqFifo_q_0$write_1__SEL_2 or + MUX_wsi_M1_reqFifo_q_0$write_1__VAL_2 or + WILL_FIRE_RL_wsi_M1_reqFifo_decCtr or wsi_M1_reqFifo_q_1) + begin + case (1'b1) // synopsys parallel_case + WILL_FIRE_RL_wsi_M1_reqFifo_both: + wsi_M1_reqFifo_q_0$D_IN = MUX_wsi_M1_reqFifo_q_0$write_1__VAL_1; + MUX_wsi_M1_reqFifo_q_0$write_1__SEL_2: + wsi_M1_reqFifo_q_0$D_IN = MUX_wsi_M1_reqFifo_q_0$write_1__VAL_2; + WILL_FIRE_RL_wsi_M1_reqFifo_decCtr: + wsi_M1_reqFifo_q_0$D_IN = wsi_M1_reqFifo_q_1; + default: wsi_M1_reqFifo_q_0$D_IN = + 97'h0AAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ; + endcase + end + assign wsi_M1_reqFifo_q_0$EN = + WILL_FIRE_RL_wsi_M1_reqFifo_both || + WILL_FIRE_RL_wsi_M1_reqFifo_incCtr && + wsi_M1_reqFifo_c_r == 2'd0 || + WILL_FIRE_RL_wsi_M1_reqFifo_decCtr ; + + // register wsi_M1_reqFifo_q_1 + always@(WILL_FIRE_RL_wsi_M1_reqFifo_both or + MUX_wsi_M1_reqFifo_q_1$write_1__VAL_1 or + MUX_wsi_M1_reqFifo_q_1$write_1__SEL_2 or + MUX_wsi_M1_reqFifo_q_0$write_1__VAL_2 or + WILL_FIRE_RL_wsi_M1_reqFifo_decCtr) + begin + case (1'b1) // synopsys parallel_case + WILL_FIRE_RL_wsi_M1_reqFifo_both: + wsi_M1_reqFifo_q_1$D_IN = MUX_wsi_M1_reqFifo_q_1$write_1__VAL_1; + MUX_wsi_M1_reqFifo_q_1$write_1__SEL_2: + wsi_M1_reqFifo_q_1$D_IN = MUX_wsi_M1_reqFifo_q_0$write_1__VAL_2; + WILL_FIRE_RL_wsi_M1_reqFifo_decCtr: + wsi_M1_reqFifo_q_1$D_IN = 97'h00000AAAAAAAAAAAAAAAAAA00; + default: wsi_M1_reqFifo_q_1$D_IN = + 97'h0AAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ; + endcase + end + assign wsi_M1_reqFifo_q_1$EN = + WILL_FIRE_RL_wsi_M1_reqFifo_both || + WILL_FIRE_RL_wsi_M1_reqFifo_incCtr && + wsi_M1_reqFifo_c_r == 2'd1 || + WILL_FIRE_RL_wsi_M1_reqFifo_decCtr ; + + // register wsi_M1_sThreadBusy_d + assign wsi_M1_sThreadBusy_d$D_IN = wsiM1_SThreadBusy ; + assign wsi_M1_sThreadBusy_d$EN = 1'd1 ; + + // register wsi_M1_statusR + assign wsi_M1_statusR$D_IN = + { wsi_M1_isReset_isInReset, + !wsi_M1_peerIsReady, + !wsi_M1_operateD, + wsi_M1_errorSticky, + wsi_M1_burstKind != 2'd0, + wsi_M1_sThreadBusy_d, + 1'd0, + wsi_M1_trafficSticky } ; + assign wsi_M1_statusR$EN = 1'd1 ; + + // register wsi_M1_tBusyCount + assign wsi_M1_tBusyCount$D_IN = wsi_M1_tBusyCount + 32'd1 ; + assign wsi_M1_tBusyCount$EN = + wsi_M1_operateD && wsi_M1_peerIsReady && wsi_M1_sThreadBusy_d ; + + // register wsi_M1_trafficSticky + assign wsi_M1_trafficSticky$D_IN = 1'd1 ; + assign wsi_M1_trafficSticky$EN = + WILL_FIRE_RL_wsi_M1_reqFifo_deq && + wsi_M1_reqFifo_q_0[96:94] == 3'd1 ; + + // register wsi_S0_burstKind + assign wsi_S0_burstKind$D_IN = + (wsi_S0_burstKind == 2'd0) ? + (wsi_S0_wsiReq$wget[92] ? 2'd1 : 2'd2) : + 2'd0 ; + assign wsi_S0_burstKind$EN = + WILL_FIRE_RL_wsi_S0_reqFifo_enq && + (wsi_S0_burstKind == 2'd0 || + (wsi_S0_burstKind == 2'd1 || wsi_S0_burstKind == 2'd2) && + wsi_S0_wsiReq$wget[93]) ; + + // register wsi_S0_errorSticky + assign wsi_S0_errorSticky$D_IN = 1'b0 ; + assign wsi_S0_errorSticky$EN = 1'b0 ; + + // register wsi_S0_iMesgCount + assign wsi_S0_iMesgCount$D_IN = wsi_S0_iMesgCount + 32'd1 ; + assign wsi_S0_iMesgCount$EN = + WILL_FIRE_RL_wsi_S0_reqFifo_enq && wsi_S0_burstKind == 2'd2 && + wsi_S0_wsiReq$wget[93] ; + + // register wsi_S0_isReset_isInReset + assign wsi_S0_isReset_isInReset$D_IN = 1'd0 ; + assign wsi_S0_isReset_isInReset$EN = wsi_S0_isReset_isInReset ; + + // register wsi_S0_mesgWordLength + assign wsi_S0_mesgWordLength$D_IN = wsi_S0_wordCount ; + assign wsi_S0_mesgWordLength$EN = + WILL_FIRE_RL_wsi_S0_reqFifo_enq && wsi_S0_wsiReq$wget[93] ; + + // register wsi_S0_operateD + assign wsi_S0_operateD$D_IN = wci_cState == 3'd2 ; + assign wsi_S0_operateD$EN = 1'd1 ; + + // register wsi_S0_pMesgCount + assign wsi_S0_pMesgCount$D_IN = wsi_S0_pMesgCount + 32'd1 ; + assign wsi_S0_pMesgCount$EN = + WILL_FIRE_RL_wsi_S0_reqFifo_enq && wsi_S0_burstKind == 2'd1 && + wsi_S0_wsiReq$wget[93] ; + + // register wsi_S0_peerIsReady + assign wsi_S0_peerIsReady$D_IN = wsiS0_MReset_n ; + assign wsi_S0_peerIsReady$EN = 1'd1 ; + + // register wsi_S0_reqFifo_countReg + assign wsi_S0_reqFifo_countReg$D_IN = + WILL_FIRE_RL_wsi_S0_reqFifo_enq ? + wsi_S0_reqFifo_countReg + 2'd1 : + wsi_S0_reqFifo_countReg - 2'd1 ; + assign wsi_S0_reqFifo_countReg$EN = + WILL_FIRE_RL_wsi_S0_reqFifo_enq != + WILL_FIRE_RL_doMessageConsume_S0 ; + + // register wsi_S0_reqFifo_levelsValid + assign wsi_S0_reqFifo_levelsValid$D_IN = WILL_FIRE_RL_wsi_S0_reqFifo_reset ; + assign wsi_S0_reqFifo_levelsValid$EN = + WILL_FIRE_RL_doMessageConsume_S0 || + WILL_FIRE_RL_wsi_S0_reqFifo_enq || + WILL_FIRE_RL_wsi_S0_reqFifo_reset ; + + // register wsi_S0_statusR + assign wsi_S0_statusR$D_IN = + { wsi_S0_isReset_isInReset, + !wsi_S0_peerIsReady, + !wsi_S0_operateD, + wsi_S0_errorSticky, + wsi_S0_burstKind != 2'd0, + !wsi_S0_sThreadBusy_dw$whas || wsi_S0_sThreadBusy_dw$wget, + 1'd0, + wsi_S0_trafficSticky } ; + assign wsi_S0_statusR$EN = 1'd1 ; + + // register wsi_S0_tBusyCount + assign wsi_S0_tBusyCount$D_IN = wsi_S0_tBusyCount + 32'd1 ; + assign wsi_S0_tBusyCount$EN = + wsi_S0_operateD && wsi_S0_peerIsReady && + (!wsi_S0_sThreadBusy_dw$whas || wsi_S0_sThreadBusy_dw$wget) ; + + // register wsi_S0_trafficSticky + assign wsi_S0_trafficSticky$D_IN = 1'd1 ; + assign wsi_S0_trafficSticky$EN = WILL_FIRE_RL_wsi_S0_reqFifo_enq ; + + // register wsi_S0_wordCount + assign wsi_S0_wordCount$D_IN = + wsi_S0_wsiReq$wget[93] ? 12'd1 : wsi_S0_wordCount + 12'd1 ; + assign wsi_S0_wordCount$EN = WILL_FIRE_RL_wsi_S0_reqFifo_enq ; + + // register wsi_S1_burstKind + assign wsi_S1_burstKind$D_IN = + (wsi_S1_burstKind == 2'd0) ? + (wsi_S1_wsiReq$wget[92] ? 2'd1 : 2'd2) : + 2'd0 ; + assign wsi_S1_burstKind$EN = + WILL_FIRE_RL_wsi_S1_reqFifo_enq && + (wsi_S1_burstKind == 2'd0 || + (wsi_S1_burstKind == 2'd1 || wsi_S1_burstKind == 2'd2) && + wsi_S1_wsiReq$wget[93]) ; + + // register wsi_S1_errorSticky + assign wsi_S1_errorSticky$D_IN = 1'b0 ; + assign wsi_S1_errorSticky$EN = 1'b0 ; + + // register wsi_S1_iMesgCount + assign wsi_S1_iMesgCount$D_IN = wsi_S1_iMesgCount + 32'd1 ; + assign wsi_S1_iMesgCount$EN = + WILL_FIRE_RL_wsi_S1_reqFifo_enq && wsi_S1_burstKind == 2'd2 && + wsi_S1_wsiReq$wget[93] ; + + // register wsi_S1_isReset_isInReset + assign wsi_S1_isReset_isInReset$D_IN = 1'd0 ; + assign wsi_S1_isReset_isInReset$EN = wsi_S1_isReset_isInReset ; + + // register wsi_S1_mesgWordLength + assign wsi_S1_mesgWordLength$D_IN = wsi_S1_wordCount ; + assign wsi_S1_mesgWordLength$EN = + WILL_FIRE_RL_wsi_S1_reqFifo_enq && wsi_S1_wsiReq$wget[93] ; + + // register wsi_S1_operateD + assign wsi_S1_operateD$D_IN = wci_cState == 3'd2 ; + assign wsi_S1_operateD$EN = 1'd1 ; + + // register wsi_S1_pMesgCount + assign wsi_S1_pMesgCount$D_IN = wsi_S1_pMesgCount + 32'd1 ; + assign wsi_S1_pMesgCount$EN = + WILL_FIRE_RL_wsi_S1_reqFifo_enq && wsi_S1_burstKind == 2'd1 && + wsi_S1_wsiReq$wget[93] ; + + // register wsi_S1_peerIsReady + assign wsi_S1_peerIsReady$D_IN = wsiS1_MReset_n ; + assign wsi_S1_peerIsReady$EN = 1'd1 ; + + // register wsi_S1_reqFifo_countReg + assign wsi_S1_reqFifo_countReg$D_IN = + WILL_FIRE_RL_wsi_S1_reqFifo_enq ? + wsi_S1_reqFifo_countReg + 2'd1 : + wsi_S1_reqFifo_countReg - 2'd1 ; + assign wsi_S1_reqFifo_countReg$EN = + WILL_FIRE_RL_wsi_S1_reqFifo_enq != + WILL_FIRE_RL_doMessageConsume_S1 ; + + // register wsi_S1_reqFifo_levelsValid + assign wsi_S1_reqFifo_levelsValid$D_IN = WILL_FIRE_RL_wsi_S1_reqFifo_reset ; + assign wsi_S1_reqFifo_levelsValid$EN = + WILL_FIRE_RL_doMessageConsume_S1 || + WILL_FIRE_RL_wsi_S1_reqFifo_enq || + WILL_FIRE_RL_wsi_S1_reqFifo_reset ; + + // register wsi_S1_statusR + assign wsi_S1_statusR$D_IN = + { wsi_S1_isReset_isInReset, + !wsi_S1_peerIsReady, + !wsi_S1_operateD, + wsi_S1_errorSticky, + wsi_S1_burstKind != 2'd0, + !wsi_S1_sThreadBusy_dw$whas || wsi_S1_sThreadBusy_dw$wget, + 1'd0, + wsi_S1_trafficSticky } ; + assign wsi_S1_statusR$EN = 1'd1 ; + + // register wsi_S1_tBusyCount + assign wsi_S1_tBusyCount$D_IN = wsi_S1_tBusyCount + 32'd1 ; + assign wsi_S1_tBusyCount$EN = + wsi_S1_operateD && wsi_S1_peerIsReady && + (!wsi_S1_sThreadBusy_dw$whas || wsi_S1_sThreadBusy_dw$wget) ; + + // register wsi_S1_trafficSticky + assign wsi_S1_trafficSticky$D_IN = 1'd1 ; + assign wsi_S1_trafficSticky$EN = WILL_FIRE_RL_wsi_S1_reqFifo_enq ; + + // register wsi_S1_wordCount + assign wsi_S1_wordCount$D_IN = + wsi_S1_wsiReq$wget[93] ? 12'd1 : wsi_S1_wordCount + 12'd1 ; + assign wsi_S1_wordCount$EN = WILL_FIRE_RL_wsi_S1_reqFifo_enq ; + + // submodule wci_reqF + assign wci_reqF$D_IN = wci_wciReq$wget ; + assign wci_reqF$ENQ = wci_wciReq$wget[71:69] != 3'd0 ; + assign wci_reqF$DEQ = wci_reqF_r_deq$whas ; + assign wci_reqF$CLR = 1'b0 ; + + // submodule wsi_S0_reqFifo + assign wsi_S0_reqFifo$D_IN = wsi_S0_wsiReq$wget ; + assign wsi_S0_reqFifo$ENQ = WILL_FIRE_RL_wsi_S0_reqFifo_enq ; + assign wsi_S0_reqFifo$DEQ = WILL_FIRE_RL_doMessageConsume_S0 ; + assign wsi_S0_reqFifo$CLR = 1'b0 ; + + // submodule wsi_S1_reqFifo + assign wsi_S1_reqFifo$D_IN = wsi_S1_wsiReq$wget ; + assign wsi_S1_reqFifo$ENQ = WILL_FIRE_RL_wsi_S1_reqFifo_enq ; + assign wsi_S1_reqFifo$DEQ = WILL_FIRE_RL_doMessageConsume_S1 ; + assign wsi_S1_reqFifo$CLR = 1'b0 ; + + // remaining internal signals + assign rdat__h16512 = + hasDebugLogic ? + { wsi_S0_statusR, + wsi_S1_statusR, + wsi_M0_statusR, + wsi_M1_statusR } : + 32'd0 ; + assign rdat__h16701 = + hasDebugLogic ? wsi_S0_extStatusW$wget[95:64] : 32'd0 ; + assign rdat__h16715 = + hasDebugLogic ? wsi_S0_extStatusW$wget[63:32] : 32'd0 ; + assign rdat__h16723 = + hasDebugLogic ? wsi_S1_extStatusW$wget[95:64] : 32'd0 ; + assign rdat__h16737 = + hasDebugLogic ? wsi_S1_extStatusW$wget[63:32] : 32'd0 ; + assign rdat__h16745 = + hasDebugLogic ? wsi_M0_extStatusW$wget[95:64] : 32'd0 ; + assign rdat__h16759 = + hasDebugLogic ? wsi_M0_extStatusW$wget[63:32] : 32'd0 ; + assign rdat__h16767 = + hasDebugLogic ? wsi_M1_extStatusW$wget[95:64] : 32'd0 ; + assign rdat__h16781 = + hasDebugLogic ? wsi_M1_extStatusW$wget[63:32] : 32'd0 ; + always@(wci_reqF$D_OUT or + splitCtrl or + rdat__h16512 or + rdat__h16701 or + rdat__h16715 or + rdat__h16723 or + rdat__h16737 or + rdat__h16745 or rdat__h16759 or rdat__h16767 or rdat__h16781) + begin + case (wci_reqF$D_OUT[39:32]) + 8'h04: _theResult____h16428 = splitCtrl; + 8'h1C: _theResult____h16428 = rdat__h16512; + 8'h20: _theResult____h16428 = rdat__h16701; + 8'h24: _theResult____h16428 = rdat__h16715; + 8'h28: _theResult____h16428 = rdat__h16723; + 8'h2C: _theResult____h16428 = rdat__h16737; + 8'h30: _theResult____h16428 = rdat__h16745; + 8'h34: _theResult____h16428 = rdat__h16759; + 8'h38: _theResult____h16428 = rdat__h16767; + 8'h3C: _theResult____h16428 = rdat__h16781; + default: _theResult____h16428 = 32'd0; + endcase + end + + // handling of inlined registers + + always@(posedge wciS0_Clk) + begin + if (wciS0_MReset_n == `BSV_RESET_VALUE) + begin + splitCtrl <= `BSV_ASSIGNMENT_DELAY ctrlInit; + wci_cEdge <= `BSV_ASSIGNMENT_DELAY 3'h2; + wci_cState <= `BSV_ASSIGNMENT_DELAY 3'd0; + wci_ctlAckReg <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_ctlOpActive <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_illegalEdge <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_nState <= `BSV_ASSIGNMENT_DELAY 3'd0; + wci_reqF_countReg <= `BSV_ASSIGNMENT_DELAY 2'd0; + wci_respF_c_r <= `BSV_ASSIGNMENT_DELAY 2'd0; + wci_respF_q_0 <= `BSV_ASSIGNMENT_DELAY 34'h0AAAAAAAA; + wci_respF_q_1 <= `BSV_ASSIGNMENT_DELAY 34'h0AAAAAAAA; + wci_sFlagReg <= `BSV_ASSIGNMENT_DELAY 1'd0; + wci_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY 1'd1; + wsi_M0_burstKind <= `BSV_ASSIGNMENT_DELAY 2'd0; + wsi_M0_errorSticky <= `BSV_ASSIGNMENT_DELAY 1'd0; + wsi_M0_iMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0; + wsi_M0_operateD <= `BSV_ASSIGNMENT_DELAY 1'd0; + wsi_M0_pMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0; + wsi_M0_peerIsReady <= `BSV_ASSIGNMENT_DELAY 1'd0; + wsi_M0_reqFifo_c_r <= `BSV_ASSIGNMENT_DELAY 2'd0; + wsi_M0_reqFifo_q_0 <= `BSV_ASSIGNMENT_DELAY + 97'h00000AAAAAAAAAAAAAAAAAA00; + wsi_M0_reqFifo_q_1 <= `BSV_ASSIGNMENT_DELAY + 97'h00000AAAAAAAAAAAAAAAAAA00; + wsi_M0_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY 1'd1; + wsi_M0_tBusyCount <= `BSV_ASSIGNMENT_DELAY 32'd0; + wsi_M0_trafficSticky <= `BSV_ASSIGNMENT_DELAY 1'd0; + wsi_M1_burstKind <= `BSV_ASSIGNMENT_DELAY 2'd0; + wsi_M1_errorSticky <= `BSV_ASSIGNMENT_DELAY 1'd0; + wsi_M1_iMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0; + wsi_M1_operateD <= `BSV_ASSIGNMENT_DELAY 1'd0; + wsi_M1_pMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0; + wsi_M1_peerIsReady <= `BSV_ASSIGNMENT_DELAY 1'd0; + wsi_M1_reqFifo_c_r <= `BSV_ASSIGNMENT_DELAY 2'd0; + wsi_M1_reqFifo_q_0 <= `BSV_ASSIGNMENT_DELAY + 97'h00000AAAAAAAAAAAAAAAAAA00; + wsi_M1_reqFifo_q_1 <= `BSV_ASSIGNMENT_DELAY + 97'h00000AAAAAAAAAAAAAAAAAA00; + wsi_M1_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY 1'd1; + wsi_M1_tBusyCount <= `BSV_ASSIGNMENT_DELAY 32'd0; + wsi_M1_trafficSticky <= `BSV_ASSIGNMENT_DELAY 1'd0; + wsi_S0_burstKind <= `BSV_ASSIGNMENT_DELAY 2'd0; + wsi_S0_errorSticky <= `BSV_ASSIGNMENT_DELAY 1'd0; + wsi_S0_iMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0; + wsi_S0_operateD <= `BSV_ASSIGNMENT_DELAY 1'd0; + wsi_S0_pMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0; + wsi_S0_peerIsReady <= `BSV_ASSIGNMENT_DELAY 1'd0; + wsi_S0_reqFifo_countReg <= `BSV_ASSIGNMENT_DELAY 2'd0; + wsi_S0_reqFifo_levelsValid <= `BSV_ASSIGNMENT_DELAY 1'd1; + wsi_S0_tBusyCount <= `BSV_ASSIGNMENT_DELAY 32'd0; + wsi_S0_trafficSticky <= `BSV_ASSIGNMENT_DELAY 1'd0; + wsi_S0_wordCount <= `BSV_ASSIGNMENT_DELAY 12'd1; + wsi_S1_burstKind <= `BSV_ASSIGNMENT_DELAY 2'd0; + wsi_S1_errorSticky <= `BSV_ASSIGNMENT_DELAY 1'd0; + wsi_S1_iMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0; + wsi_S1_operateD <= `BSV_ASSIGNMENT_DELAY 1'd0; + wsi_S1_pMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0; + wsi_S1_peerIsReady <= `BSV_ASSIGNMENT_DELAY 1'd0; + wsi_S1_reqFifo_countReg <= `BSV_ASSIGNMENT_DELAY 2'd0; + wsi_S1_reqFifo_levelsValid <= `BSV_ASSIGNMENT_DELAY 1'd1; + wsi_S1_tBusyCount <= `BSV_ASSIGNMENT_DELAY 32'd0; + wsi_S1_trafficSticky <= `BSV_ASSIGNMENT_DELAY 1'd0; + wsi_S1_wordCount <= `BSV_ASSIGNMENT_DELAY 12'd1; + end + else + begin + if (splitCtrl$EN) splitCtrl <= `BSV_ASSIGNMENT_DELAY splitCtrl$D_IN; + if (wci_cEdge$EN) wci_cEdge <= `BSV_ASSIGNMENT_DELAY wci_cEdge$D_IN; + if (wci_cState$EN) + wci_cState <= `BSV_ASSIGNMENT_DELAY wci_cState$D_IN; + if (wci_ctlAckReg$EN) + wci_ctlAckReg <= `BSV_ASSIGNMENT_DELAY wci_ctlAckReg$D_IN; + if (wci_ctlOpActive$EN) + wci_ctlOpActive <= `BSV_ASSIGNMENT_DELAY wci_ctlOpActive$D_IN; + if (wci_illegalEdge$EN) + wci_illegalEdge <= `BSV_ASSIGNMENT_DELAY wci_illegalEdge$D_IN; + if (wci_nState$EN) + wci_nState <= `BSV_ASSIGNMENT_DELAY wci_nState$D_IN; + if (wci_reqF_countReg$EN) + wci_reqF_countReg <= `BSV_ASSIGNMENT_DELAY wci_reqF_countReg$D_IN; + if (wci_respF_c_r$EN) + wci_respF_c_r <= `BSV_ASSIGNMENT_DELAY wci_respF_c_r$D_IN; + if (wci_respF_q_0$EN) + wci_respF_q_0 <= `BSV_ASSIGNMENT_DELAY wci_respF_q_0$D_IN; + if (wci_respF_q_1$EN) + wci_respF_q_1 <= `BSV_ASSIGNMENT_DELAY wci_respF_q_1$D_IN; + if (wci_sFlagReg$EN) + wci_sFlagReg <= `BSV_ASSIGNMENT_DELAY wci_sFlagReg$D_IN; + if (wci_sThreadBusy_d$EN) + wci_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY wci_sThreadBusy_d$D_IN; + if (wsi_M0_burstKind$EN) + wsi_M0_burstKind <= `BSV_ASSIGNMENT_DELAY wsi_M0_burstKind$D_IN; + if (wsi_M0_errorSticky$EN) + wsi_M0_errorSticky <= `BSV_ASSIGNMENT_DELAY wsi_M0_errorSticky$D_IN; + if (wsi_M0_iMesgCount$EN) + wsi_M0_iMesgCount <= `BSV_ASSIGNMENT_DELAY wsi_M0_iMesgCount$D_IN; + if (wsi_M0_operateD$EN) + wsi_M0_operateD <= `BSV_ASSIGNMENT_DELAY wsi_M0_operateD$D_IN; + if (wsi_M0_pMesgCount$EN) + wsi_M0_pMesgCount <= `BSV_ASSIGNMENT_DELAY wsi_M0_pMesgCount$D_IN; + if (wsi_M0_peerIsReady$EN) + wsi_M0_peerIsReady <= `BSV_ASSIGNMENT_DELAY wsi_M0_peerIsReady$D_IN; + if (wsi_M0_reqFifo_c_r$EN) + wsi_M0_reqFifo_c_r <= `BSV_ASSIGNMENT_DELAY wsi_M0_reqFifo_c_r$D_IN; + if (wsi_M0_reqFifo_q_0$EN) + wsi_M0_reqFifo_q_0 <= `BSV_ASSIGNMENT_DELAY wsi_M0_reqFifo_q_0$D_IN; + if (wsi_M0_reqFifo_q_1$EN) + wsi_M0_reqFifo_q_1 <= `BSV_ASSIGNMENT_DELAY wsi_M0_reqFifo_q_1$D_IN; + if (wsi_M0_sThreadBusy_d$EN) + wsi_M0_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY + wsi_M0_sThreadBusy_d$D_IN; + if (wsi_M0_tBusyCount$EN) + wsi_M0_tBusyCount <= `BSV_ASSIGNMENT_DELAY wsi_M0_tBusyCount$D_IN; + if (wsi_M0_trafficSticky$EN) + wsi_M0_trafficSticky <= `BSV_ASSIGNMENT_DELAY + wsi_M0_trafficSticky$D_IN; + if (wsi_M1_burstKind$EN) + wsi_M1_burstKind <= `BSV_ASSIGNMENT_DELAY wsi_M1_burstKind$D_IN; + if (wsi_M1_errorSticky$EN) + wsi_M1_errorSticky <= `BSV_ASSIGNMENT_DELAY wsi_M1_errorSticky$D_IN; + if (wsi_M1_iMesgCount$EN) + wsi_M1_iMesgCount <= `BSV_ASSIGNMENT_DELAY wsi_M1_iMesgCount$D_IN; + if (wsi_M1_operateD$EN) + wsi_M1_operateD <= `BSV_ASSIGNMENT_DELAY wsi_M1_operateD$D_IN; + if (wsi_M1_pMesgCount$EN) + wsi_M1_pMesgCount <= `BSV_ASSIGNMENT_DELAY wsi_M1_pMesgCount$D_IN; + if (wsi_M1_peerIsReady$EN) + wsi_M1_peerIsReady <= `BSV_ASSIGNMENT_DELAY wsi_M1_peerIsReady$D_IN; + if (wsi_M1_reqFifo_c_r$EN) + wsi_M1_reqFifo_c_r <= `BSV_ASSIGNMENT_DELAY wsi_M1_reqFifo_c_r$D_IN; + if (wsi_M1_reqFifo_q_0$EN) + wsi_M1_reqFifo_q_0 <= `BSV_ASSIGNMENT_DELAY wsi_M1_reqFifo_q_0$D_IN; + if (wsi_M1_reqFifo_q_1$EN) + wsi_M1_reqFifo_q_1 <= `BSV_ASSIGNMENT_DELAY wsi_M1_reqFifo_q_1$D_IN; + if (wsi_M1_sThreadBusy_d$EN) + wsi_M1_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY + wsi_M1_sThreadBusy_d$D_IN; + if (wsi_M1_tBusyCount$EN) + wsi_M1_tBusyCount <= `BSV_ASSIGNMENT_DELAY wsi_M1_tBusyCount$D_IN; + if (wsi_M1_trafficSticky$EN) + wsi_M1_trafficSticky <= `BSV_ASSIGNMENT_DELAY + wsi_M1_trafficSticky$D_IN; + if (wsi_S0_burstKind$EN) + wsi_S0_burstKind <= `BSV_ASSIGNMENT_DELAY wsi_S0_burstKind$D_IN; + if (wsi_S0_errorSticky$EN) + wsi_S0_errorSticky <= `BSV_ASSIGNMENT_DELAY wsi_S0_errorSticky$D_IN; + if (wsi_S0_iMesgCount$EN) + wsi_S0_iMesgCount <= `BSV_ASSIGNMENT_DELAY wsi_S0_iMesgCount$D_IN; + if (wsi_S0_operateD$EN) + wsi_S0_operateD <= `BSV_ASSIGNMENT_DELAY wsi_S0_operateD$D_IN; + if (wsi_S0_pMesgCount$EN) + wsi_S0_pMesgCount <= `BSV_ASSIGNMENT_DELAY wsi_S0_pMesgCount$D_IN; + if (wsi_S0_peerIsReady$EN) + wsi_S0_peerIsReady <= `BSV_ASSIGNMENT_DELAY wsi_S0_peerIsReady$D_IN; + if (wsi_S0_reqFifo_countReg$EN) + wsi_S0_reqFifo_countReg <= `BSV_ASSIGNMENT_DELAY + wsi_S0_reqFifo_countReg$D_IN; + if (wsi_S0_reqFifo_levelsValid$EN) + wsi_S0_reqFifo_levelsValid <= `BSV_ASSIGNMENT_DELAY + wsi_S0_reqFifo_levelsValid$D_IN; + if (wsi_S0_tBusyCount$EN) + wsi_S0_tBusyCount <= `BSV_ASSIGNMENT_DELAY wsi_S0_tBusyCount$D_IN; + if (wsi_S0_trafficSticky$EN) + wsi_S0_trafficSticky <= `BSV_ASSIGNMENT_DELAY + wsi_S0_trafficSticky$D_IN; + if (wsi_S0_wordCount$EN) + wsi_S0_wordCount <= `BSV_ASSIGNMENT_DELAY wsi_S0_wordCount$D_IN; + if (wsi_S1_burstKind$EN) + wsi_S1_burstKind <= `BSV_ASSIGNMENT_DELAY wsi_S1_burstKind$D_IN; + if (wsi_S1_errorSticky$EN) + wsi_S1_errorSticky <= `BSV_ASSIGNMENT_DELAY wsi_S1_errorSticky$D_IN; + if (wsi_S1_iMesgCount$EN) + wsi_S1_iMesgCount <= `BSV_ASSIGNMENT_DELAY wsi_S1_iMesgCount$D_IN; + if (wsi_S1_operateD$EN) + wsi_S1_operateD <= `BSV_ASSIGNMENT_DELAY wsi_S1_operateD$D_IN; + if (wsi_S1_pMesgCount$EN) + wsi_S1_pMesgCount <= `BSV_ASSIGNMENT_DELAY wsi_S1_pMesgCount$D_IN; + if (wsi_S1_peerIsReady$EN) + wsi_S1_peerIsReady <= `BSV_ASSIGNMENT_DELAY wsi_S1_peerIsReady$D_IN; + if (wsi_S1_reqFifo_countReg$EN) + wsi_S1_reqFifo_countReg <= `BSV_ASSIGNMENT_DELAY + wsi_S1_reqFifo_countReg$D_IN; + if (wsi_S1_reqFifo_levelsValid$EN) + wsi_S1_reqFifo_levelsValid <= `BSV_ASSIGNMENT_DELAY + wsi_S1_reqFifo_levelsValid$D_IN; + if (wsi_S1_tBusyCount$EN) + wsi_S1_tBusyCount <= `BSV_ASSIGNMENT_DELAY wsi_S1_tBusyCount$D_IN; + if (wsi_S1_trafficSticky$EN) + wsi_S1_trafficSticky <= `BSV_ASSIGNMENT_DELAY + wsi_S1_trafficSticky$D_IN; + if (wsi_S1_wordCount$EN) + wsi_S1_wordCount <= `BSV_ASSIGNMENT_DELAY wsi_S1_wordCount$D_IN; + end + if (wsi_M0_statusR$EN) + wsi_M0_statusR <= `BSV_ASSIGNMENT_DELAY wsi_M0_statusR$D_IN; + if (wsi_M1_statusR$EN) + wsi_M1_statusR <= `BSV_ASSIGNMENT_DELAY wsi_M1_statusR$D_IN; + if (wsi_S0_mesgWordLength$EN) + wsi_S0_mesgWordLength <= `BSV_ASSIGNMENT_DELAY + wsi_S0_mesgWordLength$D_IN; + if (wsi_S0_statusR$EN) + wsi_S0_statusR <= `BSV_ASSIGNMENT_DELAY wsi_S0_statusR$D_IN; + if (wsi_S1_mesgWordLength$EN) + wsi_S1_mesgWordLength <= `BSV_ASSIGNMENT_DELAY + wsi_S1_mesgWordLength$D_IN; + if (wsi_S1_statusR$EN) + wsi_S1_statusR <= `BSV_ASSIGNMENT_DELAY wsi_S1_statusR$D_IN; + end + + always@(posedge wciS0_Clk or `BSV_RESET_EDGE wciS0_MReset_n) + if (wciS0_MReset_n == `BSV_RESET_VALUE) + begin + wci_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY 1'd1; + wsi_M0_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY 1'd1; + wsi_M1_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY 1'd1; + wsi_S0_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY 1'd1; + wsi_S1_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY 1'd1; + end + else + begin + if (wci_isReset_isInReset$EN) + wci_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY + wci_isReset_isInReset$D_IN; + if (wsi_M0_isReset_isInReset$EN) + wsi_M0_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY + wsi_M0_isReset_isInReset$D_IN; + if (wsi_M1_isReset_isInReset$EN) + wsi_M1_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY + wsi_M1_isReset_isInReset$D_IN; + if (wsi_S0_isReset_isInReset$EN) + wsi_S0_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY + wsi_S0_isReset_isInReset$D_IN; + if (wsi_S1_isReset_isInReset$EN) + wsi_S1_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY + wsi_S1_isReset_isInReset$D_IN; + end + + // synopsys translate_off + `ifdef BSV_NO_INITIAL_BLOCKS + `else // not BSV_NO_INITIAL_BLOCKS + initial + begin + splitCtrl = 32'hAAAAAAAA; + wci_cEdge = 3'h2; + wci_cState = 3'h2; + wci_ctlAckReg = 1'h0; + wci_ctlOpActive = 1'h0; + wci_illegalEdge = 1'h0; + wci_isReset_isInReset = 1'h0; + wci_nState = 3'h2; + wci_reqF_countReg = 2'h2; + wci_respF_c_r = 2'h2; + wci_respF_q_0 = 34'h2AAAAAAAA; + wci_respF_q_1 = 34'h2AAAAAAAA; + wci_sFlagReg = 1'h0; + wci_sThreadBusy_d = 1'h0; + wsi_M0_burstKind = 2'h2; + wsi_M0_errorSticky = 1'h0; + wsi_M0_iMesgCount = 32'hAAAAAAAA; + wsi_M0_isReset_isInReset = 1'h0; + wsi_M0_operateD = 1'h0; + wsi_M0_pMesgCount = 32'hAAAAAAAA; + wsi_M0_peerIsReady = 1'h0; + wsi_M0_reqFifo_c_r = 2'h2; + wsi_M0_reqFifo_q_0 = 97'h0AAAAAAAAAAAAAAAAAAAAAAAA; + wsi_M0_reqFifo_q_1 = 97'h0AAAAAAAAAAAAAAAAAAAAAAAA; + wsi_M0_sThreadBusy_d = 1'h0; + wsi_M0_statusR = 8'hAA; + wsi_M0_tBusyCount = 32'hAAAAAAAA; + wsi_M0_trafficSticky = 1'h0; + wsi_M1_burstKind = 2'h2; + wsi_M1_errorSticky = 1'h0; + wsi_M1_iMesgCount = 32'hAAAAAAAA; + wsi_M1_isReset_isInReset = 1'h0; + wsi_M1_operateD = 1'h0; + wsi_M1_pMesgCount = 32'hAAAAAAAA; + wsi_M1_peerIsReady = 1'h0; + wsi_M1_reqFifo_c_r = 2'h2; + wsi_M1_reqFifo_q_0 = 97'h0AAAAAAAAAAAAAAAAAAAAAAAA; + wsi_M1_reqFifo_q_1 = 97'h0AAAAAAAAAAAAAAAAAAAAAAAA; + wsi_M1_sThreadBusy_d = 1'h0; + wsi_M1_statusR = 8'hAA; + wsi_M1_tBusyCount = 32'hAAAAAAAA; + wsi_M1_trafficSticky = 1'h0; + wsi_S0_burstKind = 2'h2; + wsi_S0_errorSticky = 1'h0; + wsi_S0_iMesgCount = 32'hAAAAAAAA; + wsi_S0_isReset_isInReset = 1'h0; + wsi_S0_mesgWordLength = 12'hAAA; + wsi_S0_operateD = 1'h0; + wsi_S0_pMesgCount = 32'hAAAAAAAA; + wsi_S0_peerIsReady = 1'h0; + wsi_S0_reqFifo_countReg = 2'h2; + wsi_S0_reqFifo_levelsValid = 1'h0; + wsi_S0_statusR = 8'hAA; + wsi_S0_tBusyCount = 32'hAAAAAAAA; + wsi_S0_trafficSticky = 1'h0; + wsi_S0_wordCount = 12'hAAA; + wsi_S1_burstKind = 2'h2; + wsi_S1_errorSticky = 1'h0; + wsi_S1_iMesgCount = 32'hAAAAAAAA; + wsi_S1_isReset_isInReset = 1'h0; + wsi_S1_mesgWordLength = 12'hAAA; + wsi_S1_operateD = 1'h0; + wsi_S1_pMesgCount = 32'hAAAAAAAA; + wsi_S1_peerIsReady = 1'h0; + wsi_S1_reqFifo_countReg = 2'h2; + wsi_S1_reqFifo_levelsValid = 1'h0; + wsi_S1_statusR = 8'hAA; + wsi_S1_tBusyCount = 32'hAAAAAAAA; + wsi_S1_trafficSticky = 1'h0; + wsi_S1_wordCount = 12'hAAA; + end + `endif // BSV_NO_INITIAL_BLOCKS + // synopsys translate_on + + // handling of system tasks + + // synopsys translate_off + always@(negedge wciS0_Clk) + begin + #0; + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_ctl_op_start) + begin + v__h3698 = $time; + #0; + end + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_ctl_op_start) + $display("[%0d]: %m: WCI ControlOp: Starting-transition edge:%x from:%x", + v__h3698, + wci_reqF$D_OUT[36:34], + wci_cState); + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_ctrl_EiI && WILL_FIRE_RL_wci_ctrl_OrE) + $display("Error: \"bsv/inf/WsiSplitter2x2.bsv\", line 48, column 46: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_EiI] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n"); + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_ctrl_EiI && WILL_FIRE_RL_wci_ctrl_IsO) + $display("Error: \"bsv/inf/WsiSplitter2x2.bsv\", line 48, column 46: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_EiI] and\n [RL_wci_ctrl_IsO] ) fired in the same clock cycle.\n"); + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_ctrl_IsO && WILL_FIRE_RL_wci_ctrl_OrE) + $display("Error: \"bsv/inf/WsiSplitter2x2.bsv\", line 48, column 60: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_IsO] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n"); + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_cfwr) + begin + v__h16289 = $time; + #0; + end + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_cfwr) + $display("[%0d]: %m: WCI CONFIG WRITE Addr:%0x BE:%0x Data:%0x", + v__h16289, + wci_reqF$D_OUT[63:32], + wci_reqF$D_OUT[67:64], + wci_reqF$D_OUT[31:0]); + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_ctl_op_complete && wci_illegalEdge) + begin + v__h4017 = $time; + #0; + end + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_ctl_op_complete && wci_illegalEdge) + $display("[%0d]: %m: WCI ControlOp: ILLEGAL-EDGE Completed-transition edge:%x from:%x", + v__h4017, + wci_cEdge, + wci_cState); + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_ctl_op_complete && !wci_illegalEdge) + begin + v__h3873 = $time; + #0; + end + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_ctl_op_complete && !wci_illegalEdge) + $display("[%0d]: %m: WCI ControlOp: Completed-transition edge:%x from:%x to:%x", + v__h3873, + wci_cEdge, + wci_cState, + wci_nState); + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_cfrd) + begin + v__h16444 = $time; + #0; + end + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_cfrd) + $display("[%0d]: %m: WCI CONFIG READ Addr:%0x BE:%0x Data:%0x", + v__h16444, + wci_reqF$D_OUT[63:32], + wci_reqF$D_OUT[67:64], + _theResult____h16428); + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_OrE) + $display("Error: \"bsv/inf/WsiSplitter2x2.bsv\", line 48, column 26: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n"); + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_IsO) + $display("Error: \"bsv/inf/WsiSplitter2x2.bsv\", line 48, column 26: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_wci_ctrl_IsO] ) fired in the same clock cycle.\n"); + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_EiI) + $display("Error: \"bsv/inf/WsiSplitter2x2.bsv\", line 48, column 26: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_wci_ctrl_EiI] ) fired in the same clock cycle.\n"); + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_cfrd) + $display("Error: \"bsv/inf/WsiSplitter2x2.bsv\", line 48, column 26: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and [RL_wci_cfrd] )\n fired in the same clock cycle.\n"); + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_cfrd && WILL_FIRE_RL_wci_ctrl_OrE) + $display("Error: \"bsv/inf/WsiSplitter2x2.bsv\", line 48, column 36: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n"); + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_cfrd && WILL_FIRE_RL_wci_ctrl_IsO) + $display("Error: \"bsv/inf/WsiSplitter2x2.bsv\", line 48, column 36: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n [RL_wci_ctrl_IsO] ) fired in the same clock cycle.\n"); + if (wciS0_MReset_n != `BSV_RESET_VALUE) + if (WILL_FIRE_RL_wci_cfrd && WILL_FIRE_RL_wci_ctrl_EiI) + $display("Error: \"bsv/inf/WsiSplitter2x2.bsv\", line 48, column 36: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n [RL_wci_ctrl_EiI] ) fired in the same clock cycle.\n"); + end + // synopsys translate_on +endmodule // mkWsiSplitter2x28B +